read_verilog -sv /eda/processor_ci/rtl/Cores-SweRV-EH2.sv
read_verilog /var/jenkins_home/workspace/Cores-SweRV-EH2/Cores-SweRV-EH2/design/dmi/dmi_jtag_to_core_sync.v
read_verilog /var/jenkins_home/workspace/Cores-SweRV-EH2/Cores-SweRV-EH2/design/dmi/dmi_wrapper.v
read_verilog /var/jenkins_home/workspace/Cores-SweRV-EH2/Cores-SweRV-EH2/design/dmi/rvjtag_tap.v
read_verilog -sv /var/jenkins_home/workspace/Cores-SweRV-EH2/Cores-SweRV-EH2/design/eh2_dma_ctrl.sv
read_verilog -sv /var/jenkins_home/workspace/Cores-SweRV-EH2/Cores-SweRV-EH2/design/eh2_mem.sv
read_verilog -sv /var/jenkins_home/workspace/Cores-SweRV-EH2/Cores-SweRV-EH2/design/eh2_pic_ctrl.sv
read_verilog -sv /var/jenkins_home/workspace/Cores-SweRV-EH2/Cores-SweRV-EH2/design/eh2_veer.sv
read_verilog -sv /var/jenkins_home/workspace/Cores-SweRV-EH2/Cores-SweRV-EH2/design/eh2_veer_wrapper.sv
read_verilog -sv /var/jenkins_home/workspace/Cores-SweRV-EH2/Cores-SweRV-EH2/design/dbg/eh2_dbg.sv
read_verilog -sv /var/jenkins_home/workspace/Cores-SweRV-EH2/Cores-SweRV-EH2/design/dec/eh2_dec.sv
read_verilog -sv /var/jenkins_home/workspace/Cores-SweRV-EH2/Cores-SweRV-EH2/design/dec/eh2_dec_csr.sv
read_verilog -sv /var/jenkins_home/workspace/Cores-SweRV-EH2/Cores-SweRV-EH2/design/dec/eh2_dec_decode_ctl.sv
read_verilog -sv /var/jenkins_home/workspace/Cores-SweRV-EH2/Cores-SweRV-EH2/design/dec/eh2_dec_gpr_ctl.sv
read_verilog -sv /var/jenkins_home/workspace/Cores-SweRV-EH2/Cores-SweRV-EH2/design/dec/eh2_dec_ib_ctl.sv
read_verilog -sv /var/jenkins_home/workspace/Cores-SweRV-EH2/Cores-SweRV-EH2/design/dec/eh2_dec_tlu_ctl.sv
read_verilog -sv /var/jenkins_home/workspace/Cores-SweRV-EH2/Cores-SweRV-EH2/design/dec/eh2_dec_tlu_top.sv
read_verilog -sv /var/jenkins_home/workspace/Cores-SweRV-EH2/Cores-SweRV-EH2/design/dec/eh2_dec_trigger.sv
read_verilog -sv /var/jenkins_home/workspace/Cores-SweRV-EH2/Cores-SweRV-EH2/design/exu/eh2_exu.sv
read_verilog -sv /var/jenkins_home/workspace/Cores-SweRV-EH2/Cores-SweRV-EH2/design/exu/eh2_exu_alu_ctl.sv
read_verilog -sv /var/jenkins_home/workspace/Cores-SweRV-EH2/Cores-SweRV-EH2/design/exu/eh2_exu_div_ctl.sv
read_verilog -sv /var/jenkins_home/workspace/Cores-SweRV-EH2/Cores-SweRV-EH2/design/exu/eh2_exu_mul_ctl.sv
read_verilog -sv /var/jenkins_home/workspace/Cores-SweRV-EH2/Cores-SweRV-EH2/design/ifu/eh2_ifu.sv
read_verilog -sv /var/jenkins_home/workspace/Cores-SweRV-EH2/Cores-SweRV-EH2/design/ifu/eh2_ifu_aln_ctl.sv
read_verilog -sv /var/jenkins_home/workspace/Cores-SweRV-EH2/Cores-SweRV-EH2/design/ifu/eh2_ifu_bp_ctl.sv
read_verilog -sv /var/jenkins_home/workspace/Cores-SweRV-EH2/Cores-SweRV-EH2/design/ifu/eh2_ifu_compress_ctl.sv
read_verilog -sv /var/jenkins_home/workspace/Cores-SweRV-EH2/Cores-SweRV-EH2/design/ifu/eh2_ifu_ic_mem.sv
read_verilog -sv /var/jenkins_home/workspace/Cores-SweRV-EH2/Cores-SweRV-EH2/design/ifu/eh2_ifu_iccm_mem.sv
read_verilog -sv /var/jenkins_home/workspace/Cores-SweRV-EH2/Cores-SweRV-EH2/design/ifu/eh2_ifu_ifc_ctl.sv
read_verilog -sv /var/jenkins_home/workspace/Cores-SweRV-EH2/Cores-SweRV-EH2/design/ifu/eh2_ifu_mem_ctl.sv
read_verilog -sv /var/jenkins_home/workspace/Cores-SweRV-EH2/Cores-SweRV-EH2/design/include/eh2_def.sv
read_verilog -sv /var/jenkins_home/workspace/Cores-SweRV-EH2/Cores-SweRV-EH2/design/lib/ahb_to_axi4.sv
read_verilog -sv /var/jenkins_home/workspace/Cores-SweRV-EH2/Cores-SweRV-EH2/design/lib/axi4_to_ahb.sv
read_verilog -sv /var/jenkins_home/workspace/Cores-SweRV-EH2/Cores-SweRV-EH2/design/lib/beh_lib.sv
read_verilog -sv /var/jenkins_home/workspace/Cores-SweRV-EH2/Cores-SweRV-EH2/design/lib/eh2_lib.sv
read_verilog -sv /var/jenkins_home/workspace/Cores-SweRV-EH2/Cores-SweRV-EH2/design/lib/mem_lib.sv
read_verilog -sv /var/jenkins_home/workspace/Cores-SweRV-EH2/Cores-SweRV-EH2/design/lsu/eh2_lsu.sv
read_verilog -sv /var/jenkins_home/workspace/Cores-SweRV-EH2/Cores-SweRV-EH2/design/lsu/eh2_lsu_addrcheck.sv
read_verilog -sv /var/jenkins_home/workspace/Cores-SweRV-EH2/Cores-SweRV-EH2/design/lsu/eh2_lsu_amo.sv
read_verilog -sv /var/jenkins_home/workspace/Cores-SweRV-EH2/Cores-SweRV-EH2/design/lsu/eh2_lsu_bus_buffer.sv
read_verilog -sv /var/jenkins_home/workspace/Cores-SweRV-EH2/Cores-SweRV-EH2/design/lsu/eh2_lsu_bus_intf.sv
read_verilog -sv /var/jenkins_home/workspace/Cores-SweRV-EH2/Cores-SweRV-EH2/design/lsu/eh2_lsu_clkdomain.sv
read_verilog -sv /var/jenkins_home/workspace/Cores-SweRV-EH2/Cores-SweRV-EH2/design/lsu/eh2_lsu_dccm_ctl.sv
read_verilog -sv /var/jenkins_home/workspace/Cores-SweRV-EH2/Cores-SweRV-EH2/design/lsu/eh2_lsu_dccm_mem.sv
read_verilog -sv /var/jenkins_home/workspace/Cores-SweRV-EH2/Cores-SweRV-EH2/design/lsu/eh2_lsu_ecc.sv
read_verilog -sv /var/jenkins_home/workspace/Cores-SweRV-EH2/Cores-SweRV-EH2/design/lsu/eh2_lsu_lsc_ctl.sv
read_verilog -sv /var/jenkins_home/workspace/Cores-SweRV-EH2/Cores-SweRV-EH2/design/lsu/eh2_lsu_trigger.sv
set_property include_dirs [list "/var/jenkins_home/workspace/Cores-SweRV-EH2/Cores-SweRV-EH2/design/include" "/var/jenkins_home/workspace/Cores-SweRV-EH2/Cores-SweRV-EH2/snapshots/default/" ] [get_filesets sources_1]
read_verilog -sv /eda/processor-ci-controller/modules/uart.sv
read_verilog /eda/processor-ci-controller/modules/UART/rtl/uart_rx.v
read_verilog /eda/processor-ci-controller/modules/UART/rtl/uart_tx.v

#read_verilog -sv /eda/processor-ci-controller/modules/spi.sv;
#read_verilog -sv /eda/processor-ci-controller/modules/SPI-Slave/rtl/spi_slave.sv;

read_verilog -sv /eda/processor_ci/internal/ahblite_to_wishbone.sv
read_verilog -sv /eda/processor_ci/internal/axi4_to_wishbone.sv
read_verilog -sv /eda/processor_ci/internal/axi4lite_to_wishbone.sv
read_verilog -sv /eda/processor-ci-controller/rtl/fifo.sv
read_verilog -sv /eda/processor-ci-controller/rtl/reset.sv
read_verilog -sv /eda/processor-ci-controller/rtl/clk_divider.sv
read_verilog -sv /eda/processor-ci-controller/rtl/memory.sv
read_verilog -sv /eda/processor-ci-controller/rtl/interpreter.sv
read_verilog -sv /eda/processor-ci-controller/rtl/controller.sv
read_verilog -sv /eda/processor-ci-controller/rtl/timer.sv
read_verilog -sv /eda/processor_ci/internal/fpga_top.sv

set_param general.maxThreads 16

read_xdc "/eda/processor_ci/constraints/digilent_arty_a7_100t.xdc"
set_property PROCESSING_ORDER EARLY [get_files /eda/processor_ci/constraints/digilent_arty_a7_100t.xdc]

# synth
synth_design -top "fpga_top" -part "xc7a100tcsg324-1"

# place and route
opt_design
place_design

report_utilization -hierarchical -file digilent_arty_a7_utilization_hierarchical_place.rpt
report_utilization               -file digilent_arty_a7_utilization_place.rpt
report_io                        -file digilent_arty_a7_io.rpt
report_control_sets -verbose     -file digilent_arty_a7_control_sets.rpt
report_clock_utilization         -file digilent_arty_a7_clock_utilization.rpt


route_design

report_timing_summary -no_header -no_detailed_paths
report_route_status                            -file digilent_arty_a7_route_status.rpt
report_drc                                     -file digilent_arty_a7_drc.rpt
report_timing_summary -datasheet -max_paths 10 -file digilent_arty_a7_timing.rpt
report_power                                   -file digilent_arty_a7_power.rpt


# write bitstream
write_bitstream -force "digilent_arty_a7_100t.bit"

exit