if { [info exists CHIPNAME] } {
   set  _CHIPNAME $CHIPNAME
} else {
   set  _CHIPNAME riscv
}

jtag newtap $_CHIPNAME tap -irlen 5
set _TARGETNAME $_CHIPNAME.tap
target create $_TARGETNAME.0 riscv -chain-position $_TARGETNAME -rtos hwthread

# Configure work area in on-chip SRAM
$_TARGETNAME.0 configure -work-area-phys 0x50001000 -work-area-size 0x1000 -work-area-backup 0

# Mem access mode
riscv set_mem_access sysbus

# The following commands disable target examination and set explicitly the
# core parameters read from CSRs. These required a modified version of
# OpenOCD from https://github.com/antmicro/openocd/tree/riscv-nohalt
riscv set_nohalt on
riscv set_xlen 32
riscv set_misa 0x40001104

# Be verbose about GDB errors
gdb_report_data_abort enable
gdb_report_register_access_error enable

# Always use hardware breakpoints.
gdb_breakpoint_override hard
