set _CHIPNAME riscv

jtag newtap $_CHIPNAME tap -irlen 5
set _TARGETNAME $_CHIPNAME.tap
target create $_TARGETNAME.0 riscv -chain-position $_TARGETNAME -rtos hwthread

# Mem access mode
riscv set_mem_access sysbus

# The following commands disable target examination and set explicitly the
# core parameters read from CSRs. These required a modified version of
# OpenOCD from https://github.com/antmicro/openocd/tree/riscv-nohalt
riscv set_nohalt on
riscv set_xlen 32
riscv set_misa 0x40001104
