- import: <riscv_dv_root>/target/rv32imc/testlist.yaml

- test: riscv_pmp_disable_all_regions_test_veer
  desc: >
    Disable all permissions from PMP regions, randomize the boot mode,
    and randomize mstatus.mprv.
    Expect that all appropriate faults are taken, and that the core
    finishes executing successfully.
  iterations: 50
  gen_test: riscv_rand_instr_test
  gen_opts: >
    +instr_cnt=6000
    +set_mstatus_mprv=1
    +pmp_max_offset=00024000
    +pmp_region_1=L:1,X:0,W:0,R:0
    +pmp_region_2=L:1,X:0,W:0,R:0
    +pmp_region_3=L:1,X:0,W:0,R:0
    +pmp_region_4=L:1,X:0,W:0,R:0
    +pmp_region_5=L:1,X:0,W:0,R:0
    +pmp_region_6=L:1,X:0,W:0,R:0
    +pmp_region_7=L:1,X:0,W:0,R:0
    +pmp_region_8=L:1,X:0,W:0,R:0
    +pmp_region_9=L:1,X:0,W:0,R:0
    +pmp_region_10=L:1,X:0,W:0,R:0
    +pmp_region_11=L:1,X:0,W:0,R:0
    +pmp_region_12=L:1,X:0,W:0,R:0
    +pmp_region_13=L:1,X:0,W:0,R:0
    +pmp_region_14=L:1,X:0,W:0,R:0
    +pmp_region_15=L:1,X:0,W:0,R:0
    +enable_write_pmp_csr=1
    +mseccfg=MML:0,MMWP:0,RLB:0
  rtl_test: core_base_test

- test: riscv_pmp_out_of_bounds_test_veer
  desc: >
    Default PMP settings - enable all regions with full permissions. Randomize
    mstatus.mprv and the boot mode. Insert streams of memory instructions that
    access addresses out of PMP boundaries.
  iterations: 50
  gen_test: riscv_rand_instr_test
  gen_opts: >
    +instr_cnt=6000
    +set_mstatus_mprv=1
    +pmp_max_offset=00024000
    +enable_write_pmp_csr=1
    +directed_instr_0=veer_load_store_rand_addr_instr_stream,50
    +mseccfg=MML:0,MMWP:0,RLB:0
  rtl_test: core_base_test
  sim_opts: >
    +is_double_fault_detected_fatal=0
    +enable_bad_intg_on_uninit_access=0

- test: riscv_pmp_full_random_test_veer
  desc: >
    Completely randomize the boot mode, mstatus.mprv, and all PMP
    configuration, and allow PMP regions to overlap.  A large number of
    iterations will be required since this introduces a huge state space of
    configurations.  Some configurations result in very slow execution as every
    instruction ends up generating a fault. As this is still a useful test a
    short timeout with pass on timeout is enabled.
  iterations: 600
  gen_test: riscv_rand_instr_test
  gen_opts: >
    +instr_cnt=6000
    +set_mstatus_mprv=1
    +pmp_randomize=1
    +pmp_max_offset=00040000
    +pmp_allow_illegal_tor=1
    +directed_instr_0=riscv_load_store_rand_instr_stream,40
    +directed_instr_1=riscv_load_store_hazard_instr_stream,40
    +directed_instr_2=veer_load_store_rand_addr_instr_stream,40
    +enable_unaligned_load_store=1
  sim_opts: >
    +is_double_fault_detected_fatal=0
    +is_timeout_s_fatal=0
    +enable_bad_intg_on_uninit_access=0
  rtl_test: core_base_test

- test: riscv_pmp_region_exec_test_veer
  desc: >
    A more specialised pmp_full_random_test that attempts to make regions
    executable whilst MML is set.
  iterations: 20
  gen_test: riscv_rand_instr_test
  gen_opts: >
    +instr_cnt=6000
    +set_mstatus_mprv=1
    +pmp_randomize=1
    +pmp_max_offset=00040000
    +pmp_allow_illegal_tor=1
    +directed_instr_0=riscv_load_store_rand_instr_stream,40
    +enable_unaligned_load_store=1
    +boot_mode=m
    +mseccfg=MML:1,MMWP:0,RLB:0
  sim_opts: >
    +is_double_fault_detected_fatal=0
    +is_timeout_s_fatal=0
    +enable_bad_intg_on_uninit_access=0
  rtl_test: core_base_test

- test: riscv_bitmanip_full_test_veer
  desc: >
    Random instruction test with supported B extension instructions in full
    configuration.
  iterations: 10
  gen_test: riscv_rand_instr_test
  gen_opts: >
    +enable_zba_extension=1
    +enable_zbb_extension=1
    +enable_zbc_extension=1
    +enable_zbs_extension=1
    +enable_b_extension=1
    +enable_bitmanip_groups=zbe,zbf,zbp,zbr,zbt
  rtl_test: core_base_test

- test: riscv_bitmanip_balanced_test_veer
  desc: >
    Random instruction test with supported B extension instructions in
    balanced configuration.
  iterations: 10
  gen_test: riscv_rand_instr_test
  gen_opts: >
    +enable_zba_extension=1
    +enable_zbb_extension=1
    +enable_zbs_extension=1
    +enable_b_extension=1
    +enable_bitmanip_groups=zbf,zbt

- test: riscv_user_mode_rand_test
  desc: >
    User mode random instruction test
  iterations: 100
  gen_test: riscv_instr_base_test
  gen_opts: >
    +instr_cnt=10000
    +boot_mode=u
  rtl_test: core_base_test
