Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
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| Tool Version : Vivado v.2023.2 (lin64) Build 4029153 Fri Oct 13 20:13:54 MDT 2023
| Date         : Thu Jul 23 22:07:02 2026
| Host         : 685a421e500f running 64-bit unknown
| Command      : report_control_sets -verbose -file digilent_arty_a7_control_sets.rpt
| Design       : fpga_top
| Device       : xc7a100t
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Control Set Information

Table of Contents
-----------------
1. Summary
2. Histogram
3. Flip-Flop Distribution
4. Detailed Control Set Information

1. Summary
----------

+----------------------------------------------------------+-------+
|                          Status                          | Count |
+----------------------------------------------------------+-------+
| Total control sets                                       |   192 |
|    Minimum number of control sets                        |   192 |
|    Addition due to synthesis replication                 |     0 |
|    Addition due to physical synthesis replication        |     0 |
| Unused register locations in slices containing registers |   288 |
+----------------------------------------------------------+-------+
* Control sets can be merged at opt_design using control_set_merge or merge_equivalent_drivers
** Run report_qor_suggestions for automated merging and remapping suggestions


2. Histogram
------------

+--------------------+-------+
|       Fanout       | Count |
+--------------------+-------+
| Total control sets |   192 |
| >= 0 to < 4        |    28 |
| >= 4 to < 6        |     5 |
| >= 6 to < 8        |     2 |
| >= 8 to < 10       |     7 |
| >= 10 to < 12      |     4 |
| >= 12 to < 14      |     3 |
| >= 14 to < 16      |     0 |
| >= 16              |   143 |
+--------------------+-------+
* Control sets can be remapped at either synth_design or opt_design


3. Flip-Flop Distribution
-------------------------

+--------------+-----------------------+------------------------+-----------------+--------------+
| Clock Enable | Synchronous Set/Reset | Asynchronous Set/Reset | Total Registers | Total Slices |
+--------------+-----------------------+------------------------+-----------------+--------------+
| No           | No                    | No                     |             277 |          121 |
| No           | No                    | Yes                    |             120 |           66 |
| No           | Yes                   | No                     |              97 |           42 |
| Yes          | No                    | No                     |             351 |          180 |
| Yes          | No                    | Yes                    |            4464 |         2422 |
| Yes          | Yes                   | No                     |             411 |          113 |
+--------------+-----------------------+------------------------+-----------------+--------------+


4. Detailed Control Set Information
-----------------------------------

+-----------------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------+------------------+----------------+--------------+
|                                                Clock Signal                                               |                                                 Enable Signal                                                 |                                Set/Reset Signal                                | Slice Load Count | Bel Load Count | Bels / Slice |
+-----------------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------+------------------+----------------+--------------+
|  clk_core                                                                                                 | ptop/u_klessydra_f0_3th_core/Pipe/TMR_CMP_csr_addr_i/MSTATUS_en7_out                                          | ptop/u_Controller/Interpreter/core_reset_reg_7                                 |                1 |              1 |         1.00 |
|  clk_o_BUFG                                                                                               | ptop/u_Controller/Uart/i_uart_tx/txd_reg_i_2_n_1                                                              | ptop/u_Controller/Uart/i_uart_tx/txd_reg_i_1_n_1                               |                1 |              1 |         1.00 |
|  rst_core                                                                                                 |                                                                                                               |                                                                                |                1 |              1 |         1.00 |
|  clk_core                                                                                                 |                                                                                                               |                                                                                |                1 |              1 |         1.00 |
|  clk_core                                                                                                 |                                                                                                               | ptop/u_Controller/Interpreter/core_reset_reg_4                                 |                1 |              1 |         1.00 |
|  clk_core                                                                                                 |                                                                                                               | ptop/u_Controller/Interpreter/core_reset_reg_6                                 |                1 |              1 |         1.00 |
|  clk_core                                                                                                 |                                                                                                               | ptop/u_Controller/Interpreter/core_reset_reg_8                                 |                1 |              1 |         1.00 |
|  clk_core                                                                                                 |                                                                                                               | ptop/u_Controller/Interpreter/core_reset_reg_10                                |                1 |              1 |         1.00 |
|  clk_core                                                                                                 |                                                                                                               | ptop/u_Controller/Interpreter/core_reset_reg_12                                |                1 |              1 |         1.00 |
|  clk_core                                                                                                 |                                                                                                               | ptop/u_Controller/Interpreter/core_reset_reg_14                                |                1 |              1 |         1.00 |
|  clk_core                                                                                                 | ptop/u_klessydra_f0_3th_core/Pipe/TMR_CMP_harc_to_csr/tmr_reg_i_en                                            | ptop/u_Controller/Interpreter/core_reset_reg_3                                 |                1 |              1 |         1.00 |
|  clk_core                                                                                                 | ptop/u_klessydra_f0_3th_core/Pipe/TMR_CMP_harc_to_csr/tmr_reg_i_en                                            | ptop/u_Controller/Interpreter/core_reset_reg_5                                 |                1 |              1 |         1.00 |
|  ptop/u_Controller/Interpreter/core_reset_reg_5                                                           |                                                                                                               | ptop/u_Controller/Interpreter/core_reset_reg_6                                 |                1 |              1 |         1.00 |
|  clk_core                                                                                                 | ptop/u_klessydra_f0_3th_core/Pipe/TMR_CMP_csr_addr_i/MSTATUS_en7_out                                          | ptop/u_Controller/Interpreter/core_reset_reg_9                                 |                1 |              1 |         1.00 |
|  clk_core                                                                                                 | ptop/u_klessydra_f0_3th_core/Pipe/TMR_CMP_instr_word_IE/MSTATUS_en5_out                                       | ptop/u_Controller/Interpreter/core_reset_reg_13                                |                1 |              1 |         1.00 |
|  clk_core                                                                                                 | ptop/u_klessydra_f0_3th_core/Pipe/TMR_CMP_instr_word_IE/MSTATUS_en5_out                                       | ptop/u_Controller/Interpreter/core_reset_reg_15                                |                1 |              1 |         1.00 |
|  ptop/u_klessydra_f0_3th_core/CSR/CSR_updating_logic[0].TMR_CMP_MIP/CSR_updating_logic[0].trap_hndlr_reg0 |                                                                                                               | ptop/u_klessydra_f0_3th_core/Pipe/TMR_CMP_pc_IE/tmr_reg_o_int_data_A_reg[7]_0  |                1 |              1 |         1.00 |
|  ptop/u_klessydra_f0_3th_core/CSR/CSR_updating_logic[2].TMR_CMP_MIP/CSR_updating_logic[2].trap_hndlr_reg0 |                                                                                                               | ptop/u_klessydra_f0_3th_core/Pipe/TMR_CMP_pc_IE/trap_hndlr                     |                1 |              1 |         1.00 |
|  ptop/u_klessydra_f0_3th_core/Pipe/TMR_CMP_harc_IE/core_reset_reg_1                                       |                                                                                                               |                                                                                |                1 |              1 |         1.00 |
|  ptop/u_klessydra_f0_3th_core/Pipe/TMR_CMP_harc_IE/core_reset_reg                                         |                                                                                                               |                                                                                |                1 |              1 |         1.00 |
|  ptop/u_klessydra_f0_3th_core/Pipe/TMR_CMP_harc_IE/core_reset_reg_0                                       |                                                                                                               |                                                                                |                1 |              1 |         1.00 |
|  ptop/u_klessydra_f0_3th_core/Pipe/TMR_CMP_csr_op_i/CSR_updating_logic[1].trap_hndlr_reg0                 |                                                                                                               | ptop/u_klessydra_f0_3th_core/Pipe/TMR_CMP_pc_IE/tmr_reg_o_int_data_A_reg[26]_0 |                1 |              1 |         1.00 |
|  clk_IBUF_BUFG                                                                                            |                                                                                                               |                                                                                |                1 |              1 |         1.00 |
|  ptop/u_Controller/Interpreter/core_reset_reg_3                                                           |                                                                                                               | ptop/u_Controller/Interpreter/core_reset_reg_4                                 |                1 |              1 |         1.00 |
|  ptop/u_Controller/Interpreter/core_reset_reg_15                                                          |                                                                                                               | ptop/u_Controller/Interpreter/core_reset_reg_14                                |                1 |              1 |         1.00 |
|  ptop/u_Controller/Interpreter/core_reset_reg_13                                                          |                                                                                                               | ptop/u_Controller/Interpreter/core_reset_reg_12                                |                1 |              1 |         1.00 |
|  ptop/u_Controller/Interpreter/core_reset_reg_9                                                           |                                                                                                               | ptop/u_Controller/Interpreter/core_reset_reg_10                                |                1 |              1 |         1.00 |
|  ptop/u_Controller/Interpreter/core_reset_reg_7                                                           |                                                                                                               | ptop/u_Controller/Interpreter/core_reset_reg_8                                 |                1 |              1 |         1.00 |
|  clk_o_BUFG                                                                                               | ptop/u_Controller/Uart/i_uart_tx/bit_counter[3]_i_2__0_n_1                                                    | ptop/u_Controller/Uart/i_uart_tx/bit_counter[3]_i_1__0_n_1                     |                1 |              4 |         4.00 |
|  clk_o_BUFG                                                                                               | ptop/u_Controller/Uart/i_uart_tx/E[0]                                                                         |                                                                                |                1 |              4 |         4.00 |
|  clk_o_BUFG                                                                                               | ptop/u_Controller/Uart/i_uart_rx/next_bit                                                                     | ptop/u_Controller/Uart/i_uart_rx/bit_counter[3]_i_1_n_1                        |                1 |              4 |         4.00 |
|  clk_o_BUFG                                                                                               | ResetBootSystem/counter                                                                                       | ResetBootSystem/counter[3]_i_1__0_n_1                                          |                2 |              4 |         2.00 |
|  clk_o_BUFG                                                                                               | ptop/u_Controller/Interpreter/return_state                                                                    | ResetBootSystem/rst_o_reg_0                                                    |                3 |              5 |         1.67 |
|  clk_o_BUFG                                                                                               |                                                                                                               |                                                                                |                3 |              6 |         2.00 |
|  clk_o_BUFG                                                                                               | ptop/u_Controller/Uart/i_uart_tx/data_to_send[6]_i_1_n_1                                                      | ResetBootSystem/rst_o_reg_0                                                    |                2 |              7 |         3.50 |
|  clk_o_BUFG                                                                                               | ptop/u_Controller/Interpreter/accumulator[7]_i_1_n_1                                                          | ResetBootSystem/rst_o_reg_0                                                    |                2 |              8 |         4.00 |
|  clk_o_BUFG                                                                                               | ptop/u_Controller/Uart/i_uart_rx/E[0]                                                                         | ResetBootSystem/rst_o_reg_0                                                    |                2 |              8 |         4.00 |
|  clk_o_BUFG                                                                                               | ptop/u_Controller/Uart/i_uart_rx/recieved_data0                                                               | ptop/u_Controller/Uart/i_uart_rx/recieved_data[7]_i_1_n_1                      |                2 |              8 |         4.00 |
|  clk_o_BUFG                                                                                               | ptop/u_Controller/Uart/uart_tx_en                                                                             | ResetBootSystem/rst_o_reg_0                                                    |                1 |              8 |         8.00 |
|  clk_o_BUFG                                                                                               | ptop/u_Controller/Uart/i_uart_rx/uart_rx_data[7]_i_1_n_1                                                      | ResetBootSystem/rst_o_reg_0                                                    |                1 |              8 |         8.00 |
|  clk_o_BUFG                                                                                               | ptop/u_Controller/Uart/tx_fifo/FSM_sequential_state_write_reg[2][0]                                           | ResetBootSystem/rst_o_reg_0                                                    |                2 |              8 |         4.00 |
|  clk_o_BUFG                                                                                               | ptop/u_Controller/Interpreter/counter                                                                         | ResetBootSystem/rst_o_reg_0                                                    |                3 |              8 |         2.67 |
|  clk_o_BUFG                                                                                               | ptop/u_Controller/Uart/i_uart_tx/txd_reg_i_2_n_1                                                              | ResetBootSystem/SR[0]                                                          |                3 |             10 |         3.33 |
|  clk_o_BUFG                                                                                               | ptop/u_Controller/Uart/i_uart_rx/cycle_counter0                                                               | ptop/u_Controller/Uart/i_uart_rx/cycle_counter[9]_i_1__0_n_1                   |                3 |             10 |         3.33 |
|  clk_o_BUFG                                                                                               | ptop/u_Controller/Uart/tx_fifo/read_ptr[2]_i_1_n_1                                                            | ResetBootSystem/rst_o_reg_0                                                    |                3 |             11 |         3.67 |
|  clk_o_BUFG                                                                                               | ptop/u_Controller/Uart/rx_fifo/read_ptr0                                                                      | ResetBootSystem/rst_o_reg_0                                                    |                3 |             11 |         3.67 |
|  clk_o_BUFG                                                                                               | ptop/u_Controller/Uart/tx_fifo/memory_reg_0_7_0_5_i_1_n_1                                                     |                                                                                |                2 |             12 |         6.00 |
|  clk_o_BUFG                                                                                               | ptop/u_Controller/Uart/rx_fifo/memory_reg_0_7_0_5_i_1__0_n_1                                                  |                                                                                |                2 |             12 |         6.00 |
|  clk_o_BUFG                                                                                               | ptop/u_Controller/Interpreter/address[31]_i_1_n_1                                                             |                                                                                |                6 |             12 |         2.00 |
|  clk_o_BUFG                                                                                               | ptop/u_Controller/Interpreter/accumulator0                                                                    | ResetBootSystem/rst_o_reg_0                                                    |                5 |             24 |         4.80 |
|  clk_o_BUFG                                                                                               | ptop/u_Controller/Interpreter/timeout                                                                         | ResetBootSystem/rst_o_reg_0                                                    |                8 |             24 |         3.00 |
|  clk_o_BUFG                                                                                               | ptop/u_Controller/Interpreter/num_of_pages                                                                    | ResetBootSystem/rst_o_reg_0                                                    |                5 |             24 |         4.80 |
|  clk_o_BUFG                                                                                               | ResetBootSystem/E[0]                                                                                          |                                                                                |                7 |             24 |         3.43 |
|  clk_o_BUFG                                                                                               | ptop/u_Controller/Interpreter/memory_page_number[23]_i_2_n_1                                                  | ptop/u_Controller/Interpreter/memory_page_number[23]_i_1_n_1                   |                7 |             24 |         3.43 |
|  clk_core                                                                                                 | ptop/u_klessydra_f0_3th_core/CSR/CSR_updating_logic[2].sTMR_CMP_csr_instr_done/tmr_sreg_o_int_data_A_reg_6    | rst_core                                                                       |               27 |             31 |         1.15 |
|  clk_core                                                                                                 | ptop/u_klessydra_f0_3th_core/Pipe/TMR_CMP_harc_to_csr/tmr_ireg_o_int_data_A_reg[0]_2                          | rst_core                                                                       |               20 |             31 |         1.55 |
|  clk_core                                                                                                 | ptop/u_klessydra_f0_3th_core/Pipe/TMR_CMP_harc_to_csr/tmr_sreg_o_int_data_A_reg_1                             | rst_core                                                                       |               21 |             31 |         1.48 |
|  ptop/u_klessydra_f0_3th_core/Pipe/TMR_CMP_harc_IE/E_BUFG[0]                                              |                                                                                                               |                                                                                |               18 |             31 |         1.72 |
|  ptop/u_klessydra_f0_3th_core/Pipe/TMR_CMP_harc_IE/tmr_sreg_o_int_data_A_reg_4_BUFG[0]                    |                                                                                                               |                                                                                |               17 |             31 |         1.82 |
|  ptop/u_klessydra_f0_3th_core/Pipe/TMR_CMP_harc_IE/tmr_sreg_o_int_data_A_reg_3_BUFG[0]                    |                                                                                                               |                                                                                |               18 |             31 |         1.72 |
|  clk_core                                                                                                 | ptop/u_klessydra_f0_3th_core/Pipe/TMR_CMP_csr_addr_i/tmr_reg_o_int_data_A_reg[1]_0[0]                         | rst_core                                                                       |               16 |             32 |         2.00 |
|  clk_core                                                                                                 | ptop/u_klessydra_f0_3th_core/Pipe/TMR_CMP_instr_word_WB/tmr_reg_o_int_data_A_reg[9]_3[0]                      | rst_core                                                                       |               22 |             32 |         1.45 |
|  clk_core                                                                                                 | ptop/u_klessydra_f0_3th_core/Pipe/TMR_CMP_instr_word_WB/tmr_reg_o_int_data_A_reg[11]_3[0]                     | rst_core                                                                       |               23 |             32 |         1.39 |
|  clk_core                                                                                                 | ptop/u_klessydra_f0_3th_core/Pipe/TMR_CMP_instr_word_WB/tmr_ireg_o_int_data_A_reg[0]_0[0]                     | rst_core                                                                       |               23 |             32 |         1.39 |
|  clk_core                                                                                                 | ptop/u_klessydra_f0_3th_core/Pipe/TMR_CMP_instr_word_WB/tmr_reg_o_int_data_A_reg[10]_1[0]                     | rst_core                                                                       |               21 |             32 |         1.52 |
|  clk_core                                                                                                 | ptop/u_klessydra_f0_3th_core/Pipe/TMR_CMP_harc_IE/tmr_sreg_o_int_data_A_reg_15[0]                             | rst_core                                                                       |               12 |             32 |         2.67 |
|  clk_core                                                                                                 | ptop/u_klessydra_f0_3th_core/Pipe/TMR_CMP_harc_IE/tmr_sreg_o_int_data_A_reg_14[0]                             |                                                                                |               19 |             32 |         1.68 |
|  clk_core                                                                                                 | ptop/u_klessydra_f0_3th_core/Pipe/TMR_CMP_harc_IE/tmr_reg_o_int_data_A_reg[3]_3[0]                            |                                                                                |               18 |             32 |         1.78 |
|  clk_core                                                                                                 | ptop/u_klessydra_f0_3th_core/Pipe/TMR_CMP_harc_WB/tmr_ireg_o_int_data_A_reg[0]_26[0]                          | rst_core                                                                       |               17 |             32 |         1.88 |
|  clk_core                                                                                                 | ptop/u_klessydra_f0_3th_core/Pipe/TMR_CMP_harc_WB/tmr_ireg_o_int_data_A_reg[0]_28[0]                          | rst_core                                                                       |               20 |             32 |         1.60 |
|  clk_core                                                                                                 | ptop/u_klessydra_f0_3th_core/Pipe/TMR_CMP_harc_WB/tmr_ireg_o_int_data_A_reg[0]_27[0]                          | rst_core                                                                       |               16 |             32 |         2.00 |
|  clk_core                                                                                                 | ptop/u_klessydra_f0_3th_core/Pipe/TMR_CMP_csr_addr_i/tmr_reg_o_int_data_A_reg[1]_2[0]                         | rst_core                                                                       |               18 |             32 |         1.78 |
|  clk_core                                                                                                 | ptop/u_klessydra_f0_3th_core/Pipe/TMR_CMP_csr_addr_i/tmr_reg_o_int_data_A_reg[2]_3[0]                         | rst_core                                                                       |               28 |             32 |         1.14 |
|  clk_core                                                                                                 | ptop/u_klessydra_f0_3th_core/Pipe/TMR_CMP_instr_word_WB/tmr_reg_o_int_data_A_reg[11]_11[0]                    | rst_core                                                                       |               22 |             32 |         1.45 |
|  clk_core                                                                                                 | ptop/u_klessydra_f0_3th_core/Pipe/TMR_CMP_csr_addr_i/tmr_reg_o_int_data_A_reg[7]_0[0]                         | rst_core                                                                       |               12 |             32 |         2.67 |
|  clk_core                                                                                                 | ptop/u_klessydra_f0_3th_core/Pipe/TMR_CMP_csr_addr_i/tmr_reg_o_int_data_A_reg[2]_8[0]                         | rst_core                                                                       |               29 |             32 |         1.10 |
|  clk_core                                                                                                 | ptop/u_klessydra_f0_3th_core/Pipe/TMR_CMP_harc_WB/tmr_ireg_o_int_data_A_reg[0]_29[0]                          | rst_core                                                                       |               18 |             32 |         1.78 |
|  clk_core                                                                                                 | ptop/u_klessydra_f0_3th_core/Pipe/TMR_CMP_harc_WB/tmr_ireg_o_int_data_A_reg[1]_8[0]                           | rst_core                                                                       |               19 |             32 |         1.68 |
|  clk_core                                                                                                 | ptop/u_klessydra_f0_3th_core/Pipe/TMR_CMP_harc_IE/tmr_sreg_o_int_data_A_reg[0]                                | rst_core                                                                       |               27 |             32 |         1.19 |
|  clk_core                                                                                                 | ptop/u_klessydra_f0_3th_core/Pipe/TMR_CMP_harc_IE/tmr_sreg_o_int_data_A_reg_1[0]                              |                                                                                |               22 |             32 |         1.45 |
|  clk_core                                                                                                 | ptop/u_klessydra_f0_3th_core/Pipe/TMR_CMP_instr_word_WB/tmr_reg_o_int_data_A_reg[11]_15[0]                    | rst_core                                                                       |               17 |             32 |         1.88 |
|  clk_core                                                                                                 | ptop/u_klessydra_f0_3th_core/Pipe/TMR_CMP_instr_word_WB/tmr_reg_o_int_data_A_reg[11]_5[0]                     | rst_core                                                                       |               22 |             32 |         1.45 |
|  clk_core                                                                                                 | ptop/u_klessydra_f0_3th_core/Pipe/TMR_CMP_instr_word_WB/tmr_reg_o_int_data_A_reg[7]_5[0]                      | rst_core                                                                       |               20 |             32 |         1.60 |
|  clk_core                                                                                                 | ptop/u_klessydra_f0_3th_core/Pipe/TMR_CMP_instr_word_WB/tmr_reg_o_int_data_A_reg[11]_2[0]                     | rst_core                                                                       |               17 |             32 |         1.88 |
|  clk_core                                                                                                 | ptop/u_klessydra_f0_3th_core/Pipe/TMR_CMP_instr_word_WB/E[0]                                                  | rst_core                                                                       |               20 |             32 |         1.60 |
|  clk_core                                                                                                 | ptop/u_klessydra_f0_3th_core/Pipe/TMR_CMP_instr_word_WB/tmr_reg_o_int_data_A_reg[7]_7[0]                      | rst_core                                                                       |               18 |             32 |         1.78 |
|  clk_core                                                                                                 | ptop/u_klessydra_f0_3th_core/Pipe/TMR_CMP_instr_word_WB/tmr_reg_o_int_data_A_reg[11]_6[0]                     | rst_core                                                                       |               19 |             32 |         1.68 |
|  clk_core                                                                                                 | ptop/u_klessydra_f0_3th_core/Pipe/TMR_CMP_instr_word_WB/tmr_reg_o_int_data_A_reg[11]_10[0]                    | rst_core                                                                       |               20 |             32 |         1.60 |
|  clk_core                                                                                                 | ptop/u_klessydra_f0_3th_core/Pipe/TMR_CMP_csr_addr_i/tmr_reg_o_int_data_A_reg[0]_4[0]                         | rst_core                                                                       |               19 |             32 |         1.68 |
|  u_klessydra_f0_3th_core/Prg_Ctr/taken_branch_pc_lat_internal[0]_0                                        |                                                                                                               |                                                                                |                8 |             32 |         4.00 |
|  u_klessydra_f0_3th_core/Prg_Ctr/taken_branch_pc_lat_internal[2]_2                                        |                                                                                                               |                                                                                |                8 |             32 |         4.00 |
|  u_klessydra_f0_3th_core/Prg_Ctr/taken_branch_pc_lat_internal[1]_1                                        |                                                                                                               |                                                                                |                8 |             32 |         4.00 |
|  clk_core                                                                                                 | ptop/u_klessydra_f0_3th_core/Pipe/TMR_CMP_harc_WB/tmr_ireg_o_int_data_A_reg[0]_11[0]                          | rst_core                                                                       |               21 |             32 |         1.52 |
|  clk_core                                                                                                 | ptop/u_klessydra_f0_3th_core/Pipe/TMR_CMP_harc_WB/tmr_ireg_o_int_data_A_reg[0]_6[0]                           | rst_core                                                                       |               17 |             32 |         1.88 |
|  clk_core                                                                                                 | ptop/u_klessydra_f0_3th_core/Pipe/TMR_CMP_harc_WB/tmr_ireg_o_int_data_A_reg[0]_5[0]                           | rst_core                                                                       |               19 |             32 |         1.68 |
|  clk_core                                                                                                 | ptop/u_klessydra_f0_3th_core/Pipe/TMR_CMP_harc_WB/tmr_ireg_o_int_data_A_reg[0]_2[0]                           | rst_core                                                                       |               17 |             32 |         1.88 |
|  clk_core                                                                                                 | ptop/u_klessydra_f0_3th_core/Pipe/TMR_CMP_harc_WB/tmr_ireg_o_int_data_A_reg[0]_8[0]                           | rst_core                                                                       |               19 |             32 |         1.68 |
|  clk_core                                                                                                 | ptop/u_klessydra_f0_3th_core/Pipe/TMR_CMP_harc_WB/tmr_ireg_o_int_data_A_reg[0]_1[0]                           | rst_core                                                                       |               15 |             32 |         2.13 |
|  clk_core                                                                                                 | ptop/u_klessydra_f0_3th_core/Pipe/TMR_CMP_harc_WB/tmr_ireg_o_int_data_A_reg[0]_4[0]                           | rst_core                                                                       |               19 |             32 |         1.68 |
|  clk_core                                                                                                 | ptop/u_klessydra_f0_3th_core/Pipe/TMR_CMP_harc_WB/tmr_ireg_o_int_data_A_reg[0]_3[0]                           | rst_core                                                                       |               20 |             32 |         1.60 |
|  clk_core                                                                                                 | ptop/u_klessydra_f0_3th_core/Pipe/TMR_CMP_harc_WB/tmr_ireg_o_int_data_A_reg[0]_7[0]                           | rst_core                                                                       |               17 |             32 |         1.88 |
|  clk_core                                                                                                 | ptop/u_klessydra_f0_3th_core/Pipe/TMR_CMP_harc_WB/tmr_ireg_o_int_data_A_reg[0]_9[0]                           | rst_core                                                                       |               19 |             32 |         1.68 |
|  clk_core                                                                                                 | ptop/u_klessydra_f0_3th_core/Pipe/TMR_CMP_csr_addr_i/tmr_reg_o_int_data_A_reg[0]_2[0]                         | rst_core                                                                       |               16 |             32 |         2.00 |
|  clk_core                                                                                                 | ptop/u_klessydra_f0_3th_core/Pipe/TMR_CMP_instr_word_WB/tmr_reg_o_int_data_A_reg[7]_3[0]                      | rst_core                                                                       |               24 |             32 |         1.33 |
|  clk_core                                                                                                 | ptop/u_klessydra_f0_3th_core/Pipe/TMR_CMP_csr_addr_i/core_reset_reg_3[0]                                      | rst_core                                                                       |               27 |             32 |         1.19 |
|  clk_core                                                                                                 | ptop/u_klessydra_f0_3th_core/Pipe/TMR_CMP_csr_addr_i/tmr_reg_o_int_data_A_reg[0]_3[0]                         | rst_core                                                                       |               17 |             32 |         1.88 |
|  clk_core                                                                                                 | ptop/u_klessydra_f0_3th_core/Pipe/TMR_CMP_decoded_instruction_IE/E[0]                                         | rst_core                                                                       |               23 |             32 |         1.39 |
|  clk_core                                                                                                 | ptop/u_klessydra_f0_3th_core/Pipe/TMR_CMP_csr_addr_i/MEPC_en[1]                                               | rst_core                                                                       |               17 |             32 |         1.88 |
|  clk_core                                                                                                 | ptop/u_klessydra_f0_3th_core/Pipe/TMR_CMP_csr_addr_i/core_reset_reg_0                                         |                                                                                |               19 |             32 |         1.68 |
|  clk_core                                                                                                 | ptop/u_klessydra_f0_3th_core/Pipe/TMR_CMP_csr_addr_i/MEPC_en[0]                                               | rst_core                                                                       |               18 |             32 |         1.78 |
|  clk_core                                                                                                 | ptop/u_klessydra_f0_3th_core/Pipe/TMR_CMP_csr_addr_i/MCAUSE_en__0[0]                                          | rst_core                                                                       |               26 |             32 |         1.23 |
|  clk_o_BUFG                                                                                               | ptop/u_Controller/ClkDivider/pulse_counter[0]_i_1_n_1                                                         | ResetBootSystem/rst_o_reg_0                                                    |                8 |             32 |         4.00 |
|  clk_core                                                                                                 | ptop/u_klessydra_f0_3th_core/Pipe/TMR_CMP_csr_addr_i/core_reset_reg_2                                         |                                                                                |               22 |             32 |         1.45 |
|  clk_core                                                                                                 | ptop/u_klessydra_f0_3th_core/Pipe/TMR_CMP_csr_addr_i/core_reset_reg_1                                         |                                                                                |               23 |             32 |         1.39 |
|  clk_core                                                                                                 | ptop/u_klessydra_f0_3th_core/Pipe/TMR_CMP_instr_word_WB/tmr_reg_o_int_data_A_reg[11]_0[0]                     | rst_core                                                                       |               21 |             32 |         1.52 |
|  clk_core                                                                                                 | ptop/u_klessydra_f0_3th_core/Pipe/TMR_CMP_instr_word_WB/tmr_reg_o_int_data_A_reg[11]_1[0]                     | rst_core                                                                       |               20 |             32 |         1.60 |
|  clk_core                                                                                                 | ptop/u_klessydra_f0_3th_core/Pipe/TMR_CMP_instr_word_WB/tmr_ireg_o_int_data_A_reg[0][0]                       | rst_core                                                                       |               21 |             32 |         1.52 |
|  clk_core                                                                                                 | ptop/u_klessydra_f0_3th_core/Pipe/TMR_CMP_harc_WB/tmr_ireg_o_int_data_A_reg[0]_12[0]                          | rst_core                                                                       |               20 |             32 |         1.60 |
|  clk_core                                                                                                 | ptop/u_klessydra_f0_3th_core/Pipe/TMR_CMP_harc_to_csr/CSR_updating_logic[0].PCER_reg[0][0][0]                 | rst_core                                                                       |               19 |             32 |         1.68 |
|  clk_core                                                                                                 | ptop/u_klessydra_f0_3th_core/Pipe/TMR_CMP_harc_to_csr/tmr_ireg_o_int_data_A_reg[0]_4[0]                       | rst_core                                                                       |               22 |             32 |         1.45 |
|  clk_core                                                                                                 | ptop/u_klessydra_f0_3th_core/Pipe/TMR_CMP_harc_IE/tmr_sreg_o_int_data_A_reg_13[0]                             | rst_core                                                                       |               14 |             32 |         2.29 |
|  clk_core                                                                                                 | ptop/u_klessydra_f0_3th_core/Pipe/TMR_CMP_harc_IE/tmr_sreg_o_int_data_A_reg_12[0]                             | rst_core                                                                       |               11 |             32 |         2.91 |
|  clk_core                                                                                                 | ptop/u_klessydra_f0_3th_core/Pipe/TMR_CMP_harc_WB/tmr_ireg_o_int_data_A_reg[0]_20[0]                          | rst_core                                                                       |               15 |             32 |         2.13 |
|  clk_core                                                                                                 | ptop/u_klessydra_f0_3th_core/Pipe/TMR_CMP_harc_WB/tmr_ireg_o_int_data_A_reg[0]_17[0]                          | rst_core                                                                       |               19 |             32 |         1.68 |
|  clk_core                                                                                                 | ptop/u_klessydra_f0_3th_core/Pipe/TMR_CMP_harc_WB/tmr_ireg_o_int_data_A_reg[0]_18[0]                          | rst_core                                                                       |               14 |             32 |         2.29 |
|  clk_core                                                                                                 | ptop/u_klessydra_f0_3th_core/Pipe/TMR_CMP_harc_WB/tmr_ireg_o_int_data_A_reg[0]_14[0]                          | rst_core                                                                       |               19 |             32 |         1.68 |
|  clk_core                                                                                                 | ptop/u_klessydra_f0_3th_core/Pipe/TMR_CMP_harc_WB/tmr_ireg_o_int_data_A_reg[0]_19[0]                          | rst_core                                                                       |               15 |             32 |         2.13 |
|  clk_core                                                                                                 | ptop/u_klessydra_f0_3th_core/Pipe/TMR_CMP_harc_WB/tmr_ireg_o_int_data_A_reg[0]_15[0]                          | rst_core                                                                       |               19 |             32 |         1.68 |
|  clk_core                                                                                                 | ptop/u_klessydra_f0_3th_core/Pipe/TMR_CMP_harc_WB/tmr_ireg_o_int_data_A_reg[0]_24[0]                          | rst_core                                                                       |               18 |             32 |         1.78 |
|  clk_core                                                                                                 | ptop/u_klessydra_f0_3th_core/Pipe/TMR_CMP_harc_WB/tmr_ireg_o_int_data_A_reg[0]_21[0]                          | rst_core                                                                       |               17 |             32 |         1.88 |
|  clk_core                                                                                                 | ptop/u_klessydra_f0_3th_core/Pipe/TMR_CMP_harc_WB/tmr_ireg_o_int_data_A_reg[0]_23[0]                          | rst_core                                                                       |               20 |             32 |         1.60 |
|  clk_core                                                                                                 | ptop/u_klessydra_f0_3th_core/Pipe/TMR_CMP_harc_WB/tmr_ireg_o_int_data_A_reg[0]_10[0]                          | rst_core                                                                       |               20 |             32 |         1.60 |
|  clk_core                                                                                                 | ptop/u_klessydra_f0_3th_core/Pipe/TMR_CMP_instr_word_WB/tmr_reg_o_int_data_A_reg[7]_6[0]                      | rst_core                                                                       |               21 |             32 |         1.52 |
|  clk_core                                                                                                 | ptop/u_klessydra_f0_3th_core/Pipe/TMR_CMP_harc_WB/tmr_ireg_o_int_data_A_reg[0]_22[0]                          | rst_core                                                                       |               18 |             32 |         1.78 |
|  clk_core                                                                                                 | ptop/u_klessydra_f0_3th_core/Pipe/TMR_CMP_harc_WB/tmr_ireg_o_int_data_A_reg[0]_25[0]                          | rst_core                                                                       |               19 |             32 |         1.68 |
|  clk_core                                                                                                 | ptop/u_klessydra_f0_3th_core/Pipe/TMR_CMP_harc_WB/tmr_ireg_o_int_data_A_reg[0]_16[0]                          | rst_core                                                                       |               15 |             32 |         2.13 |
|  clk_core                                                                                                 | ptop/u_klessydra_f0_3th_core/Pipe/TMR_CMP_harc_WB/tmr_ireg_o_int_data_A_reg[0]_13[0]                          | rst_core                                                                       |               19 |             32 |         1.68 |
|  clk_core                                                                                                 | ptop/u_klessydra_f0_3th_core/Pipe/TMR_CMP_harc_IE/tmr_sreg_o_int_data_A_reg_16[0]                             | rst_core                                                                       |               15 |             32 |         2.13 |
|  clk_core                                                                                                 | ptop/u_klessydra_f0_3th_core/Pipe/TMR_CMP_harc_IE/tmr_sreg_o_int_data_A_reg_17[0]                             | rst_core                                                                       |               14 |             32 |         2.29 |
|  clk_o_BUFG                                                                                               | ptop/u_Controller/Uart/rx_fifo/E[0]                                                                           | ResetBootSystem/rst_o_reg_0                                                    |                4 |             32 |         8.00 |
|  clk_o_BUFG                                                                                               | ptop/u_Controller/Interpreter/read_buffer[31]_i_1_n_1                                                         | ResetBootSystem/rst_o_reg_0                                                    |               20 |             32 |         1.60 |
|  clk_o_BUFG                                                                                               | ptop/u_Controller/Uart/tx_fifo/E[0]                                                                           | ResetBootSystem/rst_o_reg_0                                                    |                7 |             32 |         4.57 |
|  clk_o_BUFG                                                                                               | ResetBootSystem/rst_o_reg_1[0]                                                                                |                                                                                |               18 |             32 |         1.78 |
|  clk_o_BUFG                                                                                               | ptop/u_Controller/Interpreter/communication_write_data[31]_i_1_n_1                                            |                                                                                |               11 |             32 |         2.91 |
|  clk_o_BUFG                                                                                               | ptop/u_Controller/Interpreter/timeout_counter                                                                 | ResetBootSystem/rst_o_reg_0                                                    |                6 |             32 |         5.33 |
|  clk_o_BUFG                                                                                               | ptop/u_Controller/Interpreter/end_position[31]_i_1_n_1                                                        | ResetBootSystem/rst_o_reg_0                                                    |                7 |             32 |         4.57 |
|  clk_core                                                                                                 | ptop/u_klessydra_f0_3th_core/Pipe/TMR_CMP_instr_word_WB/tmr_reg_o_int_data_A_reg[7]_8[0]                      | rst_core                                                                       |               19 |             32 |         1.68 |
|  clk_core                                                                                                 | ptop/u_klessydra_f0_3th_core/Pipe/TMR_CMP_instr_word_WB/tmr_reg_o_int_data_A_reg[11]_17[0]                    | rst_core                                                                       |               19 |             32 |         1.68 |
|  clk_core                                                                                                 | ptop/u_klessydra_f0_3th_core/Pipe/TMR_CMP_instr_word_WB/tmr_reg_o_int_data_A_reg[10]_2[0]                     | rst_core                                                                       |               15 |             32 |         2.13 |
|  clk_core                                                                                                 | ptop/u_klessydra_f0_3th_core/Pipe/TMR_CMP_instr_word_WB/tmr_reg_o_int_data_A_reg[10]_4[0]                     | rst_core                                                                       |               14 |             32 |         2.29 |
|  clk_core                                                                                                 | ptop/u_klessydra_f0_3th_core/Pipe/TMR_CMP_instr_word_WB/tmr_reg_o_int_data_A_reg[9]_2[0]                      | rst_core                                                                       |               26 |             32 |         1.23 |
|  clk_core                                                                                                 | ptop/u_klessydra_f0_3th_core/Pipe/TMR_CMP_instr_word_WB/tmr_ireg_o_int_data_A_reg[0]_1[0]                     | rst_core                                                                       |               22 |             32 |         1.45 |
|  clk_core                                                                                                 | ptop/u_klessydra_f0_3th_core/Pipe/TMR_CMP_instr_word_WB/tmr_reg_o_int_data_A_reg[11]_4[0]                     | rst_core                                                                       |               23 |             32 |         1.39 |
|  clk_core                                                                                                 | ptop/u_klessydra_f0_3th_core/Pipe/TMR_CMP_instr_word_WB/tmr_reg_o_int_data_A_reg[11]_16[0]                    | rst_core                                                                       |               20 |             32 |         1.60 |
|  clk_core                                                                                                 | ptop/u_klessydra_f0_3th_core/Pipe/TMR_CMP_instr_word_WB/tmr_reg_o_int_data_A_reg[11]_8[0]                     | rst_core                                                                       |               22 |             32 |         1.45 |
|  clk_core                                                                                                 | ptop/u_klessydra_f0_3th_core/Pipe/TMR_CMP_harc_to_csr/MEPC_en[0]                                              | rst_core                                                                       |               19 |             32 |         1.68 |
|  clk_o_BUFG                                                                                               | ptop/u_Controller/Interpreter/communication_buffer[31]_i_1_n_1                                                | ResetBootSystem/rst_o_reg_0                                                    |                9 |             32 |         3.56 |
|  clk_core                                                                                                 | ptop/u_klessydra_f0_3th_core/Pipe/TMR_CMP_instr_word_WB/tmr_reg_o_int_data_A_reg[11]_12[0]                    | rst_core                                                                       |               19 |             32 |         1.68 |
|  clk_core                                                                                                 | ptop/u_klessydra_f0_3th_core/Pipe/TMR_CMP_instr_word_WB/tmr_reg_o_int_data_A_reg[11]_18[0]                    | rst_core                                                                       |               16 |             32 |         2.00 |
|  clk_core                                                                                                 | ptop/u_klessydra_f0_3th_core/Pipe/TMR_CMP_instr_word_WB/tmr_reg_o_int_data_A_reg[11]_9[0]                     | rst_core                                                                       |               23 |             32 |         1.39 |
|  clk_core                                                                                                 | ptop/u_klessydra_f0_3th_core/Pipe/TMR_CMP_instr_word_WB/tmr_reg_o_int_data_A_reg[11]_7[0]                     | rst_core                                                                       |               17 |             32 |         1.88 |
|  clk_core                                                                                                 | ptop/u_klessydra_f0_3th_core/Pipe/TMR_CMP_instr_word_WB/tmr_reg_o_int_data_A_reg[7]_4[0]                      | rst_core                                                                       |               23 |             32 |         1.39 |
|  clk_core                                                                                                 | ptop/u_klessydra_f0_3th_core/Pipe/TMR_CMP_instr_word_WB/tmr_reg_o_int_data_A_reg[11]_13[0]                    | rst_core                                                                       |               18 |             32 |         1.78 |
|  clk_core                                                                                                 | ptop/u_klessydra_f0_3th_core/Pipe/TMR_CMP_instr_word_WB/tmr_reg_o_int_data_A_reg[10]_3[0]                     | rst_core                                                                       |               17 |             32 |         1.88 |
|  clk_core                                                                                                 | ptop/u_klessydra_f0_3th_core/Pipe/TMR_CMP_harc_to_csr/tmr_ireg_o_int_data_A_reg[0]_10[0]                      | rst_core                                                                       |               11 |             32 |         2.91 |
|  clk_core                                                                                                 | ptop/u_klessydra_f0_3th_core/CSR/CSR_updating_logic[2].sTMR_CMP_csr_instr_done/E[0]                           | rst_core                                                                       |               17 |             32 |         1.88 |
|  clk_core                                                                                                 | ptop/u_klessydra_f0_3th_core/CSR/CSR_updating_logic[2].sTMR_CMP_csr_instr_done/tmr_sreg_o_int_data_A_reg_5[0] | rst_core                                                                       |               25 |             32 |         1.28 |
|  clk_core                                                                                                 | ptop/u_klessydra_f0_3th_core/Pipe/TMR_CMP_harc_to_csr/E[0]                                                    | rst_core                                                                       |               22 |             32 |         1.45 |
|  clk_core                                                                                                 | ptop/u_klessydra_f0_3th_core/Pipe/TMR_CMP_harc_to_csr/MCAUSE_en__0[0]                                         | rst_core                                                                       |               26 |             32 |         1.23 |
|  clk_core                                                                                                 | ptop/u_klessydra_f0_3th_core/CSR/CSR_updating_logic[2].sTMR_CMP_csr_instr_done/tmr_reg_o_int_data_A_reg[7][0] | rst_core                                                                       |               19 |             32 |         1.68 |
|  clk_core                                                                                                 | ptop/u_klessydra_f0_3th_core/Pipe/TMR_CMP_amo_load/E[0]                                                       | rst_core                                                                       |               18 |             33 |         1.83 |
|  u_klessydra_f0_3th_core/Pipe/harc_ID_lat__0                                                              |                                                                                                               |                                                                                |               17 |             34 |         2.00 |
|  clk_core                                                                                                 | ptop/u_klessydra_f0_3th_core/Pipe/TMR_CMP_harc_IE/tmr_reg_IE_en113_out                                        | rst_core                                                                       |               18 |             35 |         1.94 |
|  n_0_3092_BUFG                                                                                            |                                                                                                               |                                                                                |               18 |             42 |         2.33 |
|  clk_o_BUFG                                                                                               | ptop/u_Controller/Interpreter/num_of_positions[23]_i_1_n_1                                                    |                                                                                |               14 |             55 |         3.93 |
|  clk_o_BUFG                                                                                               |                                                                                                               | ResetBootSystem/rst_o_reg_0                                                    |               33 |             88 |         2.67 |
|  clk_core                                                                                                 |                                                                                                               | rst_core                                                                       |               60 |            114 |         1.90 |
|  clk_o_BUFG                                                                                               | ptop/u_Controller/Interpreter/memory_mux_selector_reg_7                                                       |                                                                                |               32 |            128 |         4.00 |
|  clk_o_BUFG                                                                                               | ptop/u_Controller/Interpreter/memory_mux_selector_reg_8                                                       |                                                                                |               32 |            128 |         4.00 |
|  clk_o_BUFG                                                                                               | ptop/u_Controller/Interpreter/memory_mux_selector_reg_9                                                       |                                                                                |               32 |            128 |         4.00 |
|  clk_o_BUFG                                                                                               | ptop/u_Controller/Interpreter/memory_mux_selector_reg_10                                                      |                                                                                |               32 |            128 |         4.00 |
|  clk_o_BUFG                                                                                               | ptop/u_Controller/Interpreter/memory_mux_selector_reg_11                                                      |                                                                                |               32 |            128 |         4.00 |
|  clk_o_BUFG                                                                                               | ptop/u_Controller/Interpreter/memory_mux_selector_reg_12                                                      |                                                                                |               32 |            128 |         4.00 |
|  clk_o_BUFG                                                                                               | ptop/u_Controller/Interpreter/memory_mux_selector_reg_6                                                       |                                                                                |               32 |            128 |         4.00 |
|  clk_o_BUFG                                                                                               | ptop/u_Controller/Interpreter/memory_mux_selector_reg_5                                                       |                                                                                |               32 |            128 |         4.00 |
|  clk_o_BUFG                                                                                               | ptop/u_Controller/Interpreter/memory_mux_selector_reg_rep_3                                                   |                                                                                |               32 |            128 |         4.00 |
|  clk_o_BUFG                                                                                               | ptop/u_Controller/Interpreter/address_reg[11]_0                                                               |                                                                                |               32 |            128 |         4.00 |
|  clk_o_BUFG                                                                                               | ptop/u_Controller/Interpreter/memory_mux_selector_reg_rep_2                                                   |                                                                                |               32 |            128 |         4.00 |
|  clk_o_BUFG                                                                                               | ptop/u_Controller/Interpreter/address_reg[10]_0                                                               |                                                                                |               32 |            128 |         4.00 |
|  clk_core                                                                                                 | ptop/u_klessydra_f0_3th_core/Pipe/TMR_CMP_harc_IE/core_reset_reg_9[0]                                         | rst_core                                                                       |               90 |            130 |         1.44 |
|  clk_core                                                                                                 | ptop/u_Controller/Interpreter/tmr_reg_ID_en                                                                   | rst_core                                                                       |               67 |            167 |         2.49 |
|  clk_core                                                                                                 | ptop/u_klessydra_f0_3th_core/Pipe/TMR_CMP_harc_WB/E[0]                                                        | rst_core                                                                       |              384 |           1024 |         2.67 |
+-----------------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------+------------------+----------------+--------------+


