Skip to content

Workspace

/ F03x /
.git
.Xil
klessydra-f0-3th
build_digilent_arty_a7_100t.tclSep 1, 2026, 2:04:11 AM3.07 KiB
clockInfo.txtSep 1, 2026, 2:06:47 AM375 B
digilent_arty_a7_100t.bitSep 1, 2026, 2:08:31 AM3.65 MiB
digilent_arty_a7_clock_utilization.rptSep 1, 2026, 2:07:08 AM58.83 KiB
digilent_arty_a7_control_sets.rptSep 1, 2026, 2:07:06 AM70.99 KiB
digilent_arty_a7_drc.rptSep 1, 2026, 2:08:03 AM8.55 KiB
digilent_arty_a7_io.rptSep 1, 2026, 2:07:06 AM96.81 KiB
digilent_arty_a7_power.rptSep 1, 2026, 2:08:08 AM8.84 KiB
digilent_arty_a7_route_status.rptSep 1, 2026, 2:08:01 AM651 B
digilent_arty_a7_timing.rptSep 1, 2026, 2:08:05 AM47.47 KiB
digilent_arty_a7_utilization_hierarchical_place.rptSep 1, 2026, 2:07:06 AM25.25 KiB
digilent_arty_a7_utilization_place.rptSep 1, 2026, 2:07:06 AM10.77 KiB
processor_ci_defines.vhSep 1, 2026, 2:04:11 AM300 B
README.mdSep 1, 2026, 2:04:04 AM421 B
src_files.ymlSep 1, 2026, 2:04:04 AM522 B