//
// Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24)
//
//
//
//
// Ports:
// Name                         I/O  size props
// RDY_set_verbosity              O     1 const
// RDY_server_reset_request_put   O     1 reg
// RDY_server_reset_response_get  O     1
// valid                          O     1
// addr                           O    64 reg
// cword                          O    64
// st_amo_val                     O    64
// exc                            O     1
// exc_code                       O     4 reg
// RDY_server_flush_request_put   O     1 reg
// RDY_server_flush_response_get  O     1
// RDY_tlb_flush                  O     1 const
// mem_master_awvalid             O     1 reg
// mem_master_awid                O     4 reg
// mem_master_awaddr              O    64 reg
// mem_master_awlen               O     8 reg
// mem_master_awsize              O     3 reg
// mem_master_awburst             O     2 reg
// mem_master_awlock              O     1 reg
// mem_master_awcache             O     4 reg
// mem_master_awprot              O     3 reg
// mem_master_awqos               O     4 reg
// mem_master_awregion            O     4 reg
// mem_master_wvalid              O     1 reg
// mem_master_wdata               O    64 reg
// mem_master_wstrb               O     8 reg
// mem_master_wlast               O     1 reg
// mem_master_bready              O     1 reg
// mem_master_arvalid             O     1 reg
// mem_master_arid                O     4 reg
// mem_master_araddr              O    64 reg
// mem_master_arlen               O     8 reg
// mem_master_arsize              O     3 reg
// mem_master_arburst             O     2 reg
// mem_master_arlock              O     1 reg
// mem_master_arcache             O     4 reg
// mem_master_arprot              O     3 reg
// mem_master_arqos               O     4 reg
// mem_master_arregion            O     4 reg
// mem_master_rready              O     1 reg
// RDY_ma_ddr4_ready              O     1 const
// mv_status                      O     8
// CLK                            I     1 clock
// RST_N                          I     1 reset
// set_verbosity_verbosity        I     4 reg
// req_op                         I     2
// req_f3                         I     3
// req_amo_funct7                 I     7 reg
// req_addr                       I    64
// req_st_value                   I    64
// req_priv                       I     2 reg
// req_sstatus_SUM                I     1 reg
// req_mstatus_MXR                I     1 reg
// req_satp                       I    64 reg
// mem_master_awready             I     1
// mem_master_wready              I     1
// mem_master_bvalid              I     1
// mem_master_bid                 I     4 reg
// mem_master_bresp               I     2 reg
// mem_master_arready             I     1
// mem_master_rvalid              I     1
// mem_master_rid                 I     4 reg
// mem_master_rdata               I    64 reg
// mem_master_rresp               I     2 reg
// mem_master_rlast               I     1 reg
// EN_set_verbosity               I     1
// EN_server_reset_request_put    I     1
// EN_server_reset_response_get   I     1
// EN_req                         I     1
// EN_server_flush_request_put    I     1
// EN_server_flush_response_get   I     1
// EN_tlb_flush                   I     1
// EN_ma_ddr4_ready               I     1
//
// No combinational paths from inputs to outputs
//
//

`ifdef BSV_ASSIGNMENT_DELAY
`else
  `define BSV_ASSIGNMENT_DELAY
`endif

`ifdef BSV_POSITIVE_RESET
  `define BSV_RESET_VALUE 1'b1
  `define BSV_RESET_EDGE posedge
`else
  `define BSV_RESET_VALUE 1'b0
  `define BSV_RESET_EDGE negedge
`endif

module mkMMU_Cache(CLK,
		   RST_N,

		   set_verbosity_verbosity,
		   EN_set_verbosity,
		   RDY_set_verbosity,

		   EN_server_reset_request_put,
		   RDY_server_reset_request_put,

		   EN_server_reset_response_get,
		   RDY_server_reset_response_get,

		   req_op,
		   req_f3,
		   req_amo_funct7,
		   req_addr,
		   req_st_value,
		   req_priv,
		   req_sstatus_SUM,
		   req_mstatus_MXR,
		   req_satp,
		   EN_req,

		   valid,

		   addr,

		   cword,

		   st_amo_val,

		   exc,

		   exc_code,

		   EN_server_flush_request_put,
		   RDY_server_flush_request_put,

		   EN_server_flush_response_get,
		   RDY_server_flush_response_get,

		   EN_tlb_flush,
		   RDY_tlb_flush,

		   mem_master_awvalid,

		   mem_master_awid,

		   mem_master_awaddr,

		   mem_master_awlen,

		   mem_master_awsize,

		   mem_master_awburst,

		   mem_master_awlock,

		   mem_master_awcache,

		   mem_master_awprot,

		   mem_master_awqos,

		   mem_master_awregion,

		   mem_master_awready,

		   mem_master_wvalid,

		   mem_master_wdata,

		   mem_master_wstrb,

		   mem_master_wlast,

		   mem_master_wready,

		   mem_master_bvalid,
		   mem_master_bid,
		   mem_master_bresp,

		   mem_master_bready,

		   mem_master_arvalid,

		   mem_master_arid,

		   mem_master_araddr,

		   mem_master_arlen,

		   mem_master_arsize,

		   mem_master_arburst,

		   mem_master_arlock,

		   mem_master_arcache,

		   mem_master_arprot,

		   mem_master_arqos,

		   mem_master_arregion,

		   mem_master_arready,

		   mem_master_rvalid,
		   mem_master_rid,
		   mem_master_rdata,
		   mem_master_rresp,
		   mem_master_rlast,

		   mem_master_rready,

		   EN_ma_ddr4_ready,
		   RDY_ma_ddr4_ready,

		   mv_status);
  parameter [0 : 0] dmem_not_imem = 1'b0;
  input  CLK;
  input  RST_N;

  // action method set_verbosity
  input  [3 : 0] set_verbosity_verbosity;
  input  EN_set_verbosity;
  output RDY_set_verbosity;

  // action method server_reset_request_put
  input  EN_server_reset_request_put;
  output RDY_server_reset_request_put;

  // action method server_reset_response_get
  input  EN_server_reset_response_get;
  output RDY_server_reset_response_get;

  // action method req
  input  [1 : 0] req_op;
  input  [2 : 0] req_f3;
  input  [6 : 0] req_amo_funct7;
  input  [63 : 0] req_addr;
  input  [63 : 0] req_st_value;
  input  [1 : 0] req_priv;
  input  req_sstatus_SUM;
  input  req_mstatus_MXR;
  input  [63 : 0] req_satp;
  input  EN_req;

  // value method valid
  output valid;

  // value method addr
  output [63 : 0] addr;

  // value method cword
  output [63 : 0] cword;

  // value method st_amo_val
  output [63 : 0] st_amo_val;

  // value method exc
  output exc;

  // value method exc_code
  output [3 : 0] exc_code;

  // action method server_flush_request_put
  input  EN_server_flush_request_put;
  output RDY_server_flush_request_put;

  // action method server_flush_response_get
  input  EN_server_flush_response_get;
  output RDY_server_flush_response_get;

  // action method tlb_flush
  input  EN_tlb_flush;
  output RDY_tlb_flush;

  // value method mem_master_m_awvalid
  output mem_master_awvalid;

  // value method mem_master_m_awid
  output [3 : 0] mem_master_awid;

  // value method mem_master_m_awaddr
  output [63 : 0] mem_master_awaddr;

  // value method mem_master_m_awlen
  output [7 : 0] mem_master_awlen;

  // value method mem_master_m_awsize
  output [2 : 0] mem_master_awsize;

  // value method mem_master_m_awburst
  output [1 : 0] mem_master_awburst;

  // value method mem_master_m_awlock
  output mem_master_awlock;

  // value method mem_master_m_awcache
  output [3 : 0] mem_master_awcache;

  // value method mem_master_m_awprot
  output [2 : 0] mem_master_awprot;

  // value method mem_master_m_awqos
  output [3 : 0] mem_master_awqos;

  // value method mem_master_m_awregion
  output [3 : 0] mem_master_awregion;

  // value method mem_master_m_awuser

  // action method mem_master_m_awready
  input  mem_master_awready;

  // value method mem_master_m_wvalid
  output mem_master_wvalid;

  // value method mem_master_m_wdata
  output [63 : 0] mem_master_wdata;

  // value method mem_master_m_wstrb
  output [7 : 0] mem_master_wstrb;

  // value method mem_master_m_wlast
  output mem_master_wlast;

  // value method mem_master_m_wuser

  // action method mem_master_m_wready
  input  mem_master_wready;

  // action method mem_master_m_bvalid
  input  mem_master_bvalid;
  input  [3 : 0] mem_master_bid;
  input  [1 : 0] mem_master_bresp;

  // value method mem_master_m_bready
  output mem_master_bready;

  // value method mem_master_m_arvalid
  output mem_master_arvalid;

  // value method mem_master_m_arid
  output [3 : 0] mem_master_arid;

  // value method mem_master_m_araddr
  output [63 : 0] mem_master_araddr;

  // value method mem_master_m_arlen
  output [7 : 0] mem_master_arlen;

  // value method mem_master_m_arsize
  output [2 : 0] mem_master_arsize;

  // value method mem_master_m_arburst
  output [1 : 0] mem_master_arburst;

  // value method mem_master_m_arlock
  output mem_master_arlock;

  // value method mem_master_m_arcache
  output [3 : 0] mem_master_arcache;

  // value method mem_master_m_arprot
  output [2 : 0] mem_master_arprot;

  // value method mem_master_m_arqos
  output [3 : 0] mem_master_arqos;

  // value method mem_master_m_arregion
  output [3 : 0] mem_master_arregion;

  // value method mem_master_m_aruser

  // action method mem_master_m_arready
  input  mem_master_arready;

  // action method mem_master_m_rvalid
  input  mem_master_rvalid;
  input  [3 : 0] mem_master_rid;
  input  [63 : 0] mem_master_rdata;
  input  [1 : 0] mem_master_rresp;
  input  mem_master_rlast;

  // value method mem_master_m_rready
  output mem_master_rready;

  // action method ma_ddr4_ready
  input  EN_ma_ddr4_ready;
  output RDY_ma_ddr4_ready;

  // value method mv_status
  output [7 : 0] mv_status;

  // signals for module outputs
  reg [63 : 0] cword;
  wire [63 : 0] addr,
		mem_master_araddr,
		mem_master_awaddr,
		mem_master_wdata,
		st_amo_val;
  wire [7 : 0] mem_master_arlen,
	       mem_master_awlen,
	       mem_master_wstrb,
	       mv_status;
  wire [3 : 0] exc_code,
	       mem_master_arcache,
	       mem_master_arid,
	       mem_master_arqos,
	       mem_master_arregion,
	       mem_master_awcache,
	       mem_master_awid,
	       mem_master_awqos,
	       mem_master_awregion;
  wire [2 : 0] mem_master_arprot,
	       mem_master_arsize,
	       mem_master_awprot,
	       mem_master_awsize;
  wire [1 : 0] mem_master_arburst, mem_master_awburst;
  wire RDY_ma_ddr4_ready,
       RDY_server_flush_request_put,
       RDY_server_flush_response_get,
       RDY_server_reset_request_put,
       RDY_server_reset_response_get,
       RDY_set_verbosity,
       RDY_tlb_flush,
       exc,
       mem_master_arlock,
       mem_master_arvalid,
       mem_master_awlock,
       mem_master_awvalid,
       mem_master_bready,
       mem_master_rready,
       mem_master_wlast,
       mem_master_wvalid,
       valid;

  // inlined wires
  wire [3 : 0] ctr_wr_rsps_pending_crg$port0__write_1,
	       ctr_wr_rsps_pending_crg$port1__write_1,
	       ctr_wr_rsps_pending_crg$port2__read,
	       ctr_wr_rsps_pending_crg$port3__read;
  wire ctr_wr_rsps_pending_crg$EN_port2__write, dw_valid$whas;

  // register cfg_verbosity
  reg [3 : 0] cfg_verbosity;
  wire [3 : 0] cfg_verbosity$D_IN;
  wire cfg_verbosity$EN;

  // register ctr_wr_rsps_pending_crg
  reg [3 : 0] ctr_wr_rsps_pending_crg;
  wire [3 : 0] ctr_wr_rsps_pending_crg$D_IN;
  wire ctr_wr_rsps_pending_crg$EN;

  // register rg_addr
  reg [63 : 0] rg_addr;
  wire [63 : 0] rg_addr$D_IN;
  wire rg_addr$EN;

  // register rg_amo_funct7
  reg [6 : 0] rg_amo_funct7;
  wire [6 : 0] rg_amo_funct7$D_IN;
  wire rg_amo_funct7$EN;

  // register rg_cset_cword_in_cache
  reg [8 : 0] rg_cset_cword_in_cache;
  wire [8 : 0] rg_cset_cword_in_cache$D_IN;
  wire rg_cset_cword_in_cache$EN;

  // register rg_cset_in_cache
  reg [5 : 0] rg_cset_in_cache;
  wire [5 : 0] rg_cset_in_cache$D_IN;
  wire rg_cset_in_cache$EN;

  // register rg_ddr4_ready
  reg rg_ddr4_ready;
  wire rg_ddr4_ready$D_IN, rg_ddr4_ready$EN;

  // register rg_error_during_refill
  reg rg_error_during_refill;
  wire rg_error_during_refill$D_IN, rg_error_during_refill$EN;

  // register rg_exc_code
  reg [3 : 0] rg_exc_code;
  reg [3 : 0] rg_exc_code$D_IN;
  wire rg_exc_code$EN;

  // register rg_f3
  reg [2 : 0] rg_f3;
  wire [2 : 0] rg_f3$D_IN;
  wire rg_f3$EN;

  // register rg_ld_val
  reg [63 : 0] rg_ld_val;
  reg [63 : 0] rg_ld_val$D_IN;
  wire rg_ld_val$EN;

  // register rg_lower_word32
  reg [31 : 0] rg_lower_word32;
  wire [31 : 0] rg_lower_word32$D_IN;
  wire rg_lower_word32$EN;

  // register rg_lower_word32_full
  reg rg_lower_word32_full;
  wire rg_lower_word32_full$D_IN, rg_lower_word32_full$EN;

  // register rg_lrsc_pa
  reg [63 : 0] rg_lrsc_pa;
  wire [63 : 0] rg_lrsc_pa$D_IN;
  wire rg_lrsc_pa$EN;

  // register rg_lrsc_valid
  reg rg_lrsc_valid;
  wire rg_lrsc_valid$D_IN, rg_lrsc_valid$EN;

  // register rg_mstatus_MXR
  reg rg_mstatus_MXR;
  wire rg_mstatus_MXR$D_IN, rg_mstatus_MXR$EN;

  // register rg_op
  reg [1 : 0] rg_op;
  wire [1 : 0] rg_op$D_IN;
  wire rg_op$EN;

  // register rg_pa
  reg [63 : 0] rg_pa;
  wire [63 : 0] rg_pa$D_IN;
  wire rg_pa$EN;

  // register rg_priv
  reg [1 : 0] rg_priv;
  wire [1 : 0] rg_priv$D_IN;
  wire rg_priv$EN;

  // register rg_pte_pa
  reg [63 : 0] rg_pte_pa;
  reg [63 : 0] rg_pte_pa$D_IN;
  wire rg_pte_pa$EN;

  // register rg_satp
  reg [63 : 0] rg_satp;
  wire [63 : 0] rg_satp$D_IN;
  wire rg_satp$EN;

  // register rg_sstatus_SUM
  reg rg_sstatus_SUM;
  wire rg_sstatus_SUM$D_IN, rg_sstatus_SUM$EN;

  // register rg_st_amo_val
  reg [63 : 0] rg_st_amo_val;
  wire [63 : 0] rg_st_amo_val$D_IN;
  wire rg_st_amo_val$EN;

  // register rg_state
  reg [4 : 0] rg_state;
  reg [4 : 0] rg_state$D_IN;
  wire rg_state$EN;

  // register rg_victim_way
  reg rg_victim_way;
  wire rg_victim_way$D_IN, rg_victim_way$EN;

  // register rg_wr_rsp_err
  reg rg_wr_rsp_err;
  wire rg_wr_rsp_err$D_IN, rg_wr_rsp_err$EN;

  // ports of submodule f_fabric_write_reqs
  reg [130 : 0] f_fabric_write_reqs$D_IN;
  wire [130 : 0] f_fabric_write_reqs$D_OUT;
  wire f_fabric_write_reqs$CLR,
       f_fabric_write_reqs$DEQ,
       f_fabric_write_reqs$EMPTY_N,
       f_fabric_write_reqs$ENQ,
       f_fabric_write_reqs$FULL_N;

  // ports of submodule f_pte_writebacks
  wire [127 : 0] f_pte_writebacks$D_IN, f_pte_writebacks$D_OUT;
  wire f_pte_writebacks$CLR,
       f_pte_writebacks$DEQ,
       f_pte_writebacks$EMPTY_N,
       f_pte_writebacks$ENQ,
       f_pte_writebacks$FULL_N;

  // ports of submodule f_reset_reqs
  wire f_reset_reqs$CLR,
       f_reset_reqs$DEQ,
       f_reset_reqs$D_IN,
       f_reset_reqs$D_OUT,
       f_reset_reqs$EMPTY_N,
       f_reset_reqs$ENQ,
       f_reset_reqs$FULL_N;

  // ports of submodule f_reset_rsps
  wire f_reset_rsps$CLR,
       f_reset_rsps$DEQ,
       f_reset_rsps$D_IN,
       f_reset_rsps$D_OUT,
       f_reset_rsps$EMPTY_N,
       f_reset_rsps$ENQ,
       f_reset_rsps$FULL_N;

  // ports of submodule master_xactor_f_rd_addr
  reg [96 : 0] master_xactor_f_rd_addr$D_IN;
  wire [96 : 0] master_xactor_f_rd_addr$D_OUT;
  wire master_xactor_f_rd_addr$CLR,
       master_xactor_f_rd_addr$DEQ,
       master_xactor_f_rd_addr$EMPTY_N,
       master_xactor_f_rd_addr$ENQ,
       master_xactor_f_rd_addr$FULL_N;

  // ports of submodule master_xactor_f_rd_data
  wire [70 : 0] master_xactor_f_rd_data$D_IN, master_xactor_f_rd_data$D_OUT;
  wire master_xactor_f_rd_data$CLR,
       master_xactor_f_rd_data$DEQ,
       master_xactor_f_rd_data$EMPTY_N,
       master_xactor_f_rd_data$ENQ,
       master_xactor_f_rd_data$FULL_N;

  // ports of submodule master_xactor_f_wr_addr
  wire [96 : 0] master_xactor_f_wr_addr$D_IN, master_xactor_f_wr_addr$D_OUT;
  wire master_xactor_f_wr_addr$CLR,
       master_xactor_f_wr_addr$DEQ,
       master_xactor_f_wr_addr$EMPTY_N,
       master_xactor_f_wr_addr$ENQ,
       master_xactor_f_wr_addr$FULL_N;

  // ports of submodule master_xactor_f_wr_data
  wire [72 : 0] master_xactor_f_wr_data$D_IN, master_xactor_f_wr_data$D_OUT;
  wire master_xactor_f_wr_data$CLR,
       master_xactor_f_wr_data$DEQ,
       master_xactor_f_wr_data$EMPTY_N,
       master_xactor_f_wr_data$ENQ,
       master_xactor_f_wr_data$FULL_N;

  // ports of submodule master_xactor_f_wr_resp
  wire [5 : 0] master_xactor_f_wr_resp$D_IN, master_xactor_f_wr_resp$D_OUT;
  wire master_xactor_f_wr_resp$CLR,
       master_xactor_f_wr_resp$DEQ,
       master_xactor_f_wr_resp$EMPTY_N,
       master_xactor_f_wr_resp$ENQ,
       master_xactor_f_wr_resp$FULL_N;

  // ports of submodule ram_cword_set
  reg [127 : 0] ram_cword_set$DIB;
  reg [8 : 0] ram_cword_set$ADDRB;
  wire [127 : 0] ram_cword_set$DIA, ram_cword_set$DOB;
  wire [8 : 0] ram_cword_set$ADDRA;
  wire ram_cword_set$ENA,
       ram_cword_set$ENB,
       ram_cword_set$WEA,
       ram_cword_set$WEB;

  // ports of submodule ram_state_and_ctag_cset
  wire [105 : 0] ram_state_and_ctag_cset$DIA,
		 ram_state_and_ctag_cset$DIB,
		 ram_state_and_ctag_cset$DOB;
  wire [5 : 0] ram_state_and_ctag_cset$ADDRA, ram_state_and_ctag_cset$ADDRB;
  wire ram_state_and_ctag_cset$ENA,
       ram_state_and_ctag_cset$ENB,
       ram_state_and_ctag_cset$WEA,
       ram_state_and_ctag_cset$WEB;

  // ports of submodule soc_map
  wire [63 : 0] soc_map$m_is_IO_addr_addr,
		soc_map$m_is_mem_addr_addr,
		soc_map$m_is_near_mem_IO_addr_addr;
  wire soc_map$m_is_mem_addr;

  // ports of submodule tlb
  reg [1 : 0] tlb$insert_level;
  wire [130 : 0] tlb$lookup;
  wire [63 : 0] tlb$insert_pte, tlb$insert_pte_pa;
  wire [26 : 0] tlb$insert_vpn, tlb$lookup_vpn;
  wire [15 : 0] tlb$insert_asid, tlb$lookup_asid;
  wire tlb$EN_flush, tlb$EN_insert, tlb$RDY_insert, tlb$RDY_lookup;

  // rule scheduling signals
  wire CAN_FIRE_RL_rl_ST_AMO_response,
       CAN_FIRE_RL_rl_cache_refill_rsps_loop,
       CAN_FIRE_RL_rl_discard_write_rsp,
       CAN_FIRE_RL_rl_drive_exception_rsp,
       CAN_FIRE_RL_rl_fabric_send_write_req,
       CAN_FIRE_RL_rl_io_AMO_SC_req,
       CAN_FIRE_RL_rl_io_AMO_op_req,
       CAN_FIRE_RL_rl_io_AMO_read_rsp,
       CAN_FIRE_RL_rl_io_read_req,
       CAN_FIRE_RL_rl_io_read_rsp,
       CAN_FIRE_RL_rl_io_write_req,
       CAN_FIRE_RL_rl_maintain_io_read_rsp,
       CAN_FIRE_RL_rl_probe_and_immed_rsp,
       CAN_FIRE_RL_rl_ptw_level_0,
       CAN_FIRE_RL_rl_ptw_level_1,
       CAN_FIRE_RL_rl_ptw_level_2,
       CAN_FIRE_RL_rl_rereq,
       CAN_FIRE_RL_rl_reset,
       CAN_FIRE_RL_rl_start_cache_refill,
       CAN_FIRE_RL_rl_start_reset,
       CAN_FIRE_RL_rl_start_tlb_refill,
       CAN_FIRE_RL_rl_writeback_updated_PTE,
       CAN_FIRE_ma_ddr4_ready,
       CAN_FIRE_mem_master_m_arready,
       CAN_FIRE_mem_master_m_awready,
       CAN_FIRE_mem_master_m_bvalid,
       CAN_FIRE_mem_master_m_rvalid,
       CAN_FIRE_mem_master_m_wready,
       CAN_FIRE_req,
       CAN_FIRE_server_flush_request_put,
       CAN_FIRE_server_flush_response_get,
       CAN_FIRE_server_reset_request_put,
       CAN_FIRE_server_reset_response_get,
       CAN_FIRE_set_verbosity,
       CAN_FIRE_tlb_flush,
       WILL_FIRE_RL_rl_ST_AMO_response,
       WILL_FIRE_RL_rl_cache_refill_rsps_loop,
       WILL_FIRE_RL_rl_discard_write_rsp,
       WILL_FIRE_RL_rl_drive_exception_rsp,
       WILL_FIRE_RL_rl_fabric_send_write_req,
       WILL_FIRE_RL_rl_io_AMO_SC_req,
       WILL_FIRE_RL_rl_io_AMO_op_req,
       WILL_FIRE_RL_rl_io_AMO_read_rsp,
       WILL_FIRE_RL_rl_io_read_req,
       WILL_FIRE_RL_rl_io_read_rsp,
       WILL_FIRE_RL_rl_io_write_req,
       WILL_FIRE_RL_rl_maintain_io_read_rsp,
       WILL_FIRE_RL_rl_probe_and_immed_rsp,
       WILL_FIRE_RL_rl_ptw_level_0,
       WILL_FIRE_RL_rl_ptw_level_1,
       WILL_FIRE_RL_rl_ptw_level_2,
       WILL_FIRE_RL_rl_rereq,
       WILL_FIRE_RL_rl_reset,
       WILL_FIRE_RL_rl_start_cache_refill,
       WILL_FIRE_RL_rl_start_reset,
       WILL_FIRE_RL_rl_start_tlb_refill,
       WILL_FIRE_RL_rl_writeback_updated_PTE,
       WILL_FIRE_ma_ddr4_ready,
       WILL_FIRE_mem_master_m_arready,
       WILL_FIRE_mem_master_m_awready,
       WILL_FIRE_mem_master_m_bvalid,
       WILL_FIRE_mem_master_m_rvalid,
       WILL_FIRE_mem_master_m_wready,
       WILL_FIRE_req,
       WILL_FIRE_server_flush_request_put,
       WILL_FIRE_server_flush_response_get,
       WILL_FIRE_server_reset_request_put,
       WILL_FIRE_server_reset_response_get,
       WILL_FIRE_set_verbosity,
       WILL_FIRE_tlb_flush;

  // inputs to muxes for submodule ports
  wire [130 : 0] MUX_f_fabric_write_reqs$enq_1__VAL_1,
		 MUX_f_fabric_write_reqs$enq_1__VAL_2,
		 MUX_f_fabric_write_reqs$enq_1__VAL_3,
		 MUX_f_fabric_write_reqs$enq_1__VAL_4;
  wire [127 : 0] MUX_ram_cword_set$a_put_3__VAL_1,
		 MUX_ram_cword_set$a_put_3__VAL_2;
  wire [105 : 0] MUX_ram_state_and_ctag_cset$a_put_3__VAL_1;
  wire [96 : 0] MUX_master_xactor_f_rd_addr$enq_1__VAL_1,
		MUX_master_xactor_f_rd_addr$enq_1__VAL_2,
		MUX_master_xactor_f_rd_addr$enq_1__VAL_3,
		MUX_master_xactor_f_rd_addr$enq_1__VAL_4,
		MUX_master_xactor_f_rd_addr$enq_1__VAL_5;
  wire [63 : 0] MUX_dw_output_ld_val$wset_1__VAL_3,
		MUX_rg_ld_val$write_1__VAL_2;
  wire [8 : 0] MUX_ram_cword_set$b_put_2__VAL_2,
	       MUX_ram_cword_set$b_put_2__VAL_4;
  wire [5 : 0] MUX_rg_cset_in_cache$write_1__VAL_1;
  wire [4 : 0] MUX_rg_state$write_1__VAL_11,
	       MUX_rg_state$write_1__VAL_13,
	       MUX_rg_state$write_1__VAL_14,
	       MUX_rg_state$write_1__VAL_15,
	       MUX_rg_state$write_1__VAL_17,
	       MUX_rg_state$write_1__VAL_2,
	       MUX_rg_state$write_1__VAL_4;
  wire [3 : 0] MUX_rg_exc_code$write_1__VAL_1, MUX_rg_exc_code$write_1__VAL_5;
  wire MUX_dw_output_ld_val$wset_1__SEL_1,
       MUX_dw_output_ld_val$wset_1__SEL_2,
       MUX_dw_output_ld_val$wset_1__SEL_4,
       MUX_dw_valid$wset_1__SEL_2,
       MUX_f_fabric_write_reqs$enq_1__SEL_2,
       MUX_master_xactor_f_rd_addr$enq_1__PSEL_1,
       MUX_master_xactor_f_rd_addr$enq_1__PSEL_2,
       MUX_master_xactor_f_rd_addr$enq_1__SEL_1,
       MUX_master_xactor_f_rd_addr$enq_1__SEL_2,
       MUX_master_xactor_f_rd_addr$enq_1__SEL_3,
       MUX_ram_cword_set$a_put_1__SEL_1,
       MUX_ram_cword_set$b_put_1__SEL_1,
       MUX_ram_cword_set$b_put_1__SEL_2,
       MUX_ram_state_and_ctag_cset$a_put_1__SEL_1,
       MUX_rg_error_during_refill$write_1__SEL_1,
       MUX_rg_exc_code$write_1__SEL_1,
       MUX_rg_exc_code$write_1__SEL_2,
       MUX_rg_exc_code$write_1__SEL_3,
       MUX_rg_exc_code$write_1__SEL_5,
       MUX_rg_exc_code$write_1__SEL_6,
       MUX_rg_exc_code$write_1__SEL_7,
       MUX_rg_exc_code$write_1__SEL_8,
       MUX_rg_ld_val$write_1__SEL_2,
       MUX_rg_lrsc_valid$write_1__SEL_2,
       MUX_rg_state$write_1__SEL_11,
       MUX_rg_state$write_1__SEL_17,
       MUX_rg_state$write_1__SEL_18,
       MUX_rg_state$write_1__SEL_3,
       MUX_tlb$insert_1__SEL_1,
       MUX_tlb$insert_1__SEL_2,
       MUX_tlb$insert_1__SEL_3,
       MUX_tlb$insert_2__SEL_4;

  // declarations used by system tasks
  // synopsys translate_off
  reg [31 : 0] v__h4724;
  reg [31 : 0] v__h4823;
  reg [31 : 0] v__h4973;
  reg [31 : 0] v__h21508;
  reg [31 : 0] v__h25224;
  reg [31 : 0] v__h42646;
  reg [31 : 0] v__h28736;
  reg [31 : 0] v__h29654;
  reg [31 : 0] v__h29411;
  reg [31 : 0] v__h29942;
  reg [31 : 0] v__h30054;
  reg [31 : 0] v__h29583;
  reg [31 : 0] v__h30687;
  reg [31 : 0] v__h30447;
  reg [31 : 0] v__h31087;
  reg [31 : 0] v__h30975;
  reg [31 : 0] v__h30616;
  reg [31 : 0] v__h31558;
  reg [31 : 0] v__h31629;
  reg [31 : 0] v__h31711;
  reg [31 : 0] v__h31487;
  reg [31 : 0] v__h31838;
  reg [31 : 0] v__h32529;
  reg [31 : 0] v__h32751;
  reg [31 : 0] v__h35142;
  reg [31 : 0] v__h35492;
  reg [31 : 0] v__h36592;
  reg [31 : 0] v__h36699;
  reg [31 : 0] v__h36804;
  reg [31 : 0] v__h36884;
  reg [31 : 0] v__h37094;
  reg [31 : 0] v__h37212;
  reg [31 : 0] v__h37506;
  reg [31 : 0] v__h37681;
  reg [31 : 0] v__h39940;
  reg [31 : 0] v__h37777;
  reg [31 : 0] v__h40518;
  reg [31 : 0] v__h40560;
  reg [31 : 0] v__h4250;
  reg [31 : 0] v__h40924;
  reg [31 : 0] v__h42299;
  reg [31 : 0] v__h4244;
  reg [31 : 0] v__h4718;
  reg [31 : 0] v__h4817;
  reg [31 : 0] v__h4967;
  reg [31 : 0] v__h21502;
  reg [31 : 0] v__h25218;
  reg [31 : 0] v__h28730;
  reg [31 : 0] v__h29405;
  reg [31 : 0] v__h29577;
  reg [31 : 0] v__h29648;
  reg [31 : 0] v__h29936;
  reg [31 : 0] v__h30048;
  reg [31 : 0] v__h30441;
  reg [31 : 0] v__h30610;
  reg [31 : 0] v__h30681;
  reg [31 : 0] v__h30969;
  reg [31 : 0] v__h31081;
  reg [31 : 0] v__h31481;
  reg [31 : 0] v__h31552;
  reg [31 : 0] v__h31623;
  reg [31 : 0] v__h31705;
  reg [31 : 0] v__h31832;
  reg [31 : 0] v__h32523;
  reg [31 : 0] v__h32745;
  reg [31 : 0] v__h35136;
  reg [31 : 0] v__h35486;
  reg [31 : 0] v__h36586;
  reg [31 : 0] v__h36693;
  reg [31 : 0] v__h36798;
  reg [31 : 0] v__h36878;
  reg [31 : 0] v__h37088;
  reg [31 : 0] v__h37206;
  reg [31 : 0] v__h37500;
  reg [31 : 0] v__h37675;
  reg [31 : 0] v__h37771;
  reg [31 : 0] v__h39934;
  reg [31 : 0] v__h40512;
  reg [31 : 0] v__h40554;
  reg [31 : 0] v__h40918;
  reg [31 : 0] v__h42293;
  reg [31 : 0] v__h42640;
  // synopsys translate_on

  // remaining internal signals
  reg [63 : 0] CASE_rg_addr_BITS_2_TO_0_0x0_result1328_0x4_re_ETC__q30,
	       CASE_rg_addr_BITS_2_TO_0_0x0_result6372_0x4_re_ETC__q35,
	       CASE_rg_addr_BITS_2_TO_0_0x0_result6437_0x4_re_ETC__q36,
	       CASE_rg_addr_BITS_2_TO_0_0x0_result9648_0x4_re_ETC__q51,
	       CASE_rg_f3_0b0_IF_rg_addr_7_BITS_2_TO_0_21_EQ__ETC__q53,
	       CASE_x1_avValue_pa240_BITS_2_TO_0_0x0_old_cwor_ETC__q31,
	       CASE_x1_avValue_pa240_BITS_2_TO_0_0x0_old_cwor_ETC__q34,
	       IF_IF_rg_priv_6_ULE_0b1_7_AND_rg_satp_9_BITS_6_ETC___d759,
	       IF_IF_rg_priv_6_ULE_0b1_7_AND_rg_satp_9_BITS_6_ETC___d768,
	       IF_IF_rg_priv_6_ULE_0b1_7_AND_rg_satp_9_BITS_6_ETC___d827,
	       IF_IF_rg_priv_6_ULE_0b1_7_AND_rg_satp_9_BITS_6_ETC___d836,
	       IF_rg_addr_7_BITS_2_TO_0_21_EQ_0x0_22_THEN_0_C_ETC___d1208,
	       IF_rg_addr_7_BITS_2_TO_0_21_EQ_0x0_22_THEN_0_C_ETC___d1228,
	       IF_rg_addr_7_BITS_2_TO_0_21_EQ_0x0_22_THEN_0_C_ETC___d1317,
	       IF_rg_addr_7_BITS_2_TO_0_21_EQ_0x0_22_THEN_0_C_ETC___d1337,
	       IF_rg_addr_7_BITS_2_TO_0_21_EQ_0x0_22_THEN_0_C_ETC___d1347,
	       IF_rg_addr_7_BITS_2_TO_0_21_EQ_0x0_22_THEN_0_C_ETC___d616,
	       IF_rg_addr_7_BITS_2_TO_0_21_EQ_0x0_22_THEN_0_C_ETC___d636,
	       IF_rg_addr_7_BITS_2_TO_0_21_EQ_0x0_22_THEN_0_C_ETC___d646,
	       IF_rg_addr_7_BITS_2_TO_0_21_EQ_0x0_22_THEN_SEX_ETC___d1192,
	       IF_rg_addr_7_BITS_2_TO_0_21_EQ_0x0_22_THEN_SEX_ETC___d1220,
	       IF_rg_addr_7_BITS_2_TO_0_21_EQ_0x0_22_THEN_SEX_ETC___d1301,
	       IF_rg_addr_7_BITS_2_TO_0_21_EQ_0x0_22_THEN_SEX_ETC___d1329,
	       IF_rg_addr_7_BITS_2_TO_0_21_EQ_0x0_22_THEN_SEX_ETC___d600,
	       IF_rg_addr_7_BITS_2_TO_0_21_EQ_0x0_22_THEN_SEX_ETC___d628,
	       IF_rg_f3_17_EQ_0b0_18_THEN_IF_rg_addr_7_BITS_2_ETC___d654,
	       IF_rg_f3_17_EQ_0b10_50_THEN_SEXT_IF_rg_f3_17_E_ETC___d715,
	       _theResult_____2__h25746,
	       _theResult_____2__h37853,
	       _theResult___fst__h6743,
	       ld_val__h35601,
	       mem_req_wr_data_wdata__h3221,
	       n__h22674,
	       n__h25608,
	       new_ld_val__h37807,
	       old_cword__h22663,
	       w1__h25738,
	       w1__h37841,
	       w1__h37845;
  reg [7 : 0] mem_req_wr_data_wstrb__h3222;
  reg [2 : 0] value__h37393, x__h3037;
  reg CASE_rg_amo_funct7_BITS_6_TO_2_0b0_IF_rg_f3_17_ETC__q29,
      IF_IF_rg_priv_6_ULE_0b1_7_AND_rg_satp_9_BITS_6_ETC___d324,
      IF_IF_rg_priv_6_ULE_0b1_7_AND_rg_satp_9_BITS_6_ETC___d330,
      IF_rg_addr_7_BITS_2_TO_0_21_EQ_0x0_22_OR_rg_ad_ETC___d241,
      IF_rg_addr_7_BITS_2_TO_0_21_EQ_0x0_22_OR_rg_ad_ETC___d249,
      IF_rg_f3_17_EQ_0b0_18_OR_rg_f3_17_EQ_0b100_19__ETC___d263,
      IF_rg_f3_17_EQ_0b0_18_OR_rg_f3_17_EQ_0b1_42_OR_ETC___d279,
      IF_rg_f3_17_EQ_0b0_18_THEN_NOT_rg_priv_6_ULE_0_ETC___d339;
  wire [63 : 0] IF_NOT_ram_state_and_ctag_cset_b_read__00_BIT__ETC___d779,
		IF_NOT_ram_state_and_ctag_cset_b_read__00_BIT__ETC___d847,
		IF_ram_state_and_ctag_cset_b_read__00_BIT_105__ETC___d778,
		IF_ram_state_and_ctag_cset_b_read__00_BIT_105__ETC___d846,
		IF_rg_addr_7_BITS_2_TO_0_21_EQ_0x0_22_THEN_1_E_ETC___d662,
		IF_rg_addr_7_BITS_2_TO_0_21_EQ_0x0_22_THEN_IF__ETC___d1348,
		IF_rg_addr_7_BITS_2_TO_0_21_EQ_0x0_22_THEN_ram_ETC___d647,
		IF_rg_f3_17_EQ_0b10_50_THEN_SEXT_rg_st_amo_val_ETC___d784,
		IF_rg_op_13_EQ_1_66_OR_rg_op_13_EQ_2_16_AND_rg_ETC___d856,
		_theResult___fst__h3157,
		_theResult___snd_fst__h6331,
		_theResult___snd_fst__h6402,
		_theResult___snd_fst__h6972,
		_theResult___snd_snd_fst__h6333,
		_theResult___snd_snd_fst__h6404,
		cline_fabric_addr__h31891,
		lev_0_pte_pa__h30719,
		lev_0_pte_pa_w64_fa__h30721,
		lev_1_PTN_pa__h29684,
		lev_1_pte_pa__h29686,
		lev_1_pte_pa_w64_fa__h29688,
		lev_2_pte_pa__h28789,
		lev_2_pte_pa_w64_fa__h28791,
		new_st_val__h25444,
		new_st_val__h25750,
		new_st_val__h25841,
		new_st_val__h26821,
		new_st_val__h26825,
		new_st_val__h26829,
		new_st_val__h26833,
		new_st_val__h26838,
		new_st_val__h26844,
		new_st_val__h26849,
		new_st_val__h37857,
		new_st_val__h37948,
		new_st_val__h39808,
		new_st_val__h39812,
		new_st_val__h39816,
		new_st_val__h39820,
		new_st_val__h39825,
		new_st_val__h39831,
		new_st_val__h39836,
		new_value__h24314,
		new_value__h7887,
		pa___1__h6749,
		pa___1__h6798,
		pa___1__h6867,
		pte___1__h7021,
		pte___1__h7049,
		pte___2__h6741,
		result__h20596,
		result__h20624,
		result__h20652,
		result__h20680,
		result__h20708,
		result__h20736,
		result__h20764,
		result__h20792,
		result__h20837,
		result__h20865,
		result__h20893,
		result__h20921,
		result__h20949,
		result__h20977,
		result__h21005,
		result__h21033,
		result__h21078,
		result__h21106,
		result__h21134,
		result__h21162,
		result__h21203,
		result__h21231,
		result__h21259,
		result__h21287,
		result__h21328,
		result__h21356,
		result__h21395,
		result__h21423,
		result__h35661,
		result__h35691,
		result__h35718,
		result__h35745,
		result__h35772,
		result__h35799,
		result__h35826,
		result__h35853,
		result__h35897,
		result__h35924,
		result__h35951,
		result__h35978,
		result__h36005,
		result__h36032,
		result__h36059,
		result__h36086,
		result__h36130,
		result__h36157,
		result__h36184,
		result__h36211,
		result__h36251,
		result__h36278,
		result__h36305,
		result__h36332,
		result__h36372,
		result__h36399,
		result__h36437,
		result__h36464,
		result__h38036,
		result__h38944,
		result__h38972,
		result__h39000,
		result__h39028,
		result__h39056,
		result__h39084,
		result__h39112,
		result__h39157,
		result__h39185,
		result__h39213,
		result__h39241,
		result__h39269,
		result__h39297,
		result__h39325,
		result__h39353,
		result__h39398,
		result__h39426,
		result__h39454,
		result__h39482,
		result__h39523,
		result__h39551,
		result__h39579,
		result__h39607,
		result__h39648,
		result__h39676,
		result__h39715,
		result__h39743,
		satp_pa__h2068,
		value__h7066,
		vpn_0_pa__h30718,
		vpn_1_pa__h29685,
		vpn_2_pa__h28788,
		w1___1__h25809,
		w1___1__h37916,
		w2___1__h37917,
		w2__h37847,
		word64__h7759,
		x1_avValue_pa__h6240,
		x__h21895,
		x__h37836,
		x__h7910,
		y__h14240,
		y__h7911,
		y__h7925;
  wire [55 : 0] x__h29765, x__h5093, x__h6752, x__h6801, x__h6870;
  wire [31 : 0] IF_rg_f3_17_EQ_0b0_18_THEN_IF_rg_addr_7_BITS_2_ETC__q32,
		ld_val5601_BITS_31_TO_0__q39,
		ld_val5601_BITS_63_TO_32__q46,
		master_xactor_f_rd_dataD_OUT_BITS_34_TO_3__q4,
		master_xactor_f_rd_dataD_OUT_BITS_66_TO_35__q10,
		rg_st_amo_val_BITS_31_TO_0__q33,
		w17841_BITS_31_TO_0__q52,
		word64759_BITS_31_TO_0__q17,
		word64759_BITS_63_TO_32__q25;
  wire [15 : 0] ld_val5601_BITS_15_TO_0__q38,
		ld_val5601_BITS_31_TO_16__q42,
		ld_val5601_BITS_47_TO_32__q45,
		ld_val5601_BITS_63_TO_48__q49,
		master_xactor_f_rd_dataD_OUT_BITS_18_TO_3__q3,
		master_xactor_f_rd_dataD_OUT_BITS_34_TO_19__q7,
		master_xactor_f_rd_dataD_OUT_BITS_50_TO_35__q9,
		master_xactor_f_rd_dataD_OUT_BITS_66_TO_51__q13,
		word64759_BITS_15_TO_0__q16,
		word64759_BITS_31_TO_16__q20,
		word64759_BITS_47_TO_32__q24,
		word64759_BITS_63_TO_48__q27;
  wire [7 : 0] ld_val5601_BITS_15_TO_8__q40,
	       ld_val5601_BITS_23_TO_16__q41,
	       ld_val5601_BITS_31_TO_24__q43,
	       ld_val5601_BITS_39_TO_32__q44,
	       ld_val5601_BITS_47_TO_40__q47,
	       ld_val5601_BITS_55_TO_48__q48,
	       ld_val5601_BITS_63_TO_56__q50,
	       ld_val5601_BITS_7_TO_0__q37,
	       master_xactor_f_rd_dataD_OUT_BITS_10_TO_3__q2,
	       master_xactor_f_rd_dataD_OUT_BITS_18_TO_11__q5,
	       master_xactor_f_rd_dataD_OUT_BITS_26_TO_19__q6,
	       master_xactor_f_rd_dataD_OUT_BITS_34_TO_27__q1,
	       master_xactor_f_rd_dataD_OUT_BITS_42_TO_35__q8,
	       master_xactor_f_rd_dataD_OUT_BITS_50_TO_43__q11,
	       master_xactor_f_rd_dataD_OUT_BITS_58_TO_51__q12,
	       master_xactor_f_rd_dataD_OUT_BITS_66_TO_59__q14,
	       strobe64__h3156,
	       strobe64__h3159,
	       strobe64__h3162,
	       word64759_BITS_15_TO_8__q18,
	       word64759_BITS_23_TO_16__q19,
	       word64759_BITS_31_TO_24__q21,
	       word64759_BITS_39_TO_32__q23,
	       word64759_BITS_47_TO_40__q22,
	       word64759_BITS_55_TO_48__q26,
	       word64759_BITS_63_TO_56__q28,
	       word64759_BITS_7_TO_0__q15;
  wire [5 : 0] shift_bits__h3004;
  wire [4 : 0] IF_NOT_ram_state_and_ctag_cset_b_read__00_BIT__ETC___d441,
	       IF_rg_op_13_EQ_0_14_OR_rg_op_13_EQ_2_16_AND_rg_ETC___d443,
	       IF_rg_op_13_EQ_1_66_OR_rg_op_13_EQ_2_16_AND_rg_ETC___d442,
	       IF_rg_priv_6_ULE_0b1_7_AND_rg_satp_9_BITS_63_T_ETC___d445;
  wire [3 : 0] access_exc_code__h2772,
	       b__h28690,
	       exc_code___1__h6641,
	       x1_avValue_exc_code__h6241;
  wire [1 : 0] tmp__h32030, tmp__h32031;
  wire IF_IF_rg_priv_6_ULE_0b1_7_AND_rg_satp_9_BITS_6_ETC___d334,
       IF_rg_addr_7_BITS_2_TO_0_21_EQ_0x0_22_THEN_NOT_ETC___d255,
       IF_rg_op_13_EQ_0_14_OR_rg_op_13_EQ_2_16_AND_rg_ETC___d348,
       IF_rg_op_13_EQ_1_66_OR_rg_op_13_EQ_2_16_AND_rg_ETC___d347,
       IF_rg_priv_6_ULE_0b1_7_AND_rg_satp_9_BITS_63_T_ETC___d485,
       NOT_IF_rg_priv_6_ULE_0b1_7_AND_rg_satp_9_BITS__ETC___d323,
       NOT_IF_rg_priv_6_ULE_0b1_7_AND_rg_satp_9_BITS__ETC___d329,
       NOT_IF_rg_priv_6_ULE_0b1_7_AND_rg_satp_9_BITS__ETC___d333,
       NOT_cfg_verbosity_read__1_ULE_2_106___d1107,
       NOT_cfg_verbosity_read__1_ULT_2_49___d450,
       NOT_ctr_wr_rsps_pending_crg_port0__read_EQ_15__ETC___d9,
       NOT_dmem_not_imem_28_AND_rg_op_13_EQ_0_14_OR_r_ETC___d385,
       NOT_dmem_not_imem_28_OR_NOT_rg_op_13_EQ_0_14_1_ETC___d135,
       NOT_dmem_not_imem_28_OR_soc_map_m_is_mem_addr__ETC___d479,
       NOT_dmem_not_imem_28_OR_soc_map_m_is_mem_addr__ETC___d675,
       NOT_dmem_not_imem_28_OR_soc_map_m_is_mem_addr__ETC___d687,
       NOT_dmem_not_imem_28_OR_soc_map_m_is_mem_addr__ETC___d692,
       NOT_dmem_not_imem_28_OR_soc_map_m_is_mem_addr__ETC___d700,
       NOT_dmem_not_imem_28_OR_soc_map_m_is_mem_addr__ETC___d709,
       NOT_dmem_not_imem_28_OR_soc_map_m_is_mem_addr__ETC___d722,
       NOT_dmem_not_imem_28_OR_soc_map_m_is_mem_addr__ETC___d859,
       NOT_dmem_not_imem_28_OR_soc_map_m_is_mem_addr__ETC___d877,
       NOT_dmem_not_imem_28_OR_soc_map_m_is_mem_addr__ETC___d923,
       NOT_master_xactor_f_rd_data_first__41_BITS_2_T_ETC___d1028,
       NOT_master_xactor_f_rd_data_first__41_BITS_2_T_ETC___d965,
       NOT_master_xactor_f_rd_data_first__41_BIT_3_45_ETC___d1034,
       NOT_master_xactor_f_rd_data_first__41_BIT_3_45_ETC___d972,
       NOT_ram_state_and_ctag_cset_b_read__00_BIT_105_ETC___d236,
       NOT_ram_state_and_ctag_cset_b_read__00_BIT_52__ETC___d235,
       NOT_ram_state_and_ctag_cset_b_read__00_BIT_52__ETC___d265,
       NOT_ram_state_and_ctag_cset_b_read__00_BIT_52__ETC___d285,
       NOT_ram_state_and_ctag_cset_b_read__00_BIT_52__ETC___d346,
       NOT_ram_state_and_ctag_cset_b_read__00_BIT_52__ETC___d487,
       NOT_ram_state_and_ctag_cset_b_read__00_BIT_52__ETC___d690,
       NOT_ram_state_and_ctag_cset_b_read__00_BIT_52__ETC___d697,
       NOT_req_f3_BITS_1_TO_0_433_EQ_0b0_434_435_AND__ETC___d1454,
       NOT_rg_op_13_EQ_0_14_15_AND_NOT_rg_op_13_EQ_2__ETC___d436,
       NOT_rg_op_13_EQ_1_66_93_AND_NOT_rg_op_13_EQ_2__ETC___d719,
       NOT_rg_op_13_EQ_1_66_93_AND_ram_state_and_ctag_ETC___d706,
       NOT_rg_op_13_EQ_2_16_17_OR_NOT_rg_amo_funct7_1_ETC___d717,
       NOT_rg_op_13_EQ_2_16_17_OR_NOT_rg_amo_funct7_1_ETC___d880,
       NOT_rg_op_13_EQ_2_16_17_OR_NOT_rg_amo_funct7_1_ETC___d886,
       NOT_rg_op_13_EQ_2_16_17_OR_NOT_rg_amo_funct7_1_ETC___d892,
       NOT_rg_priv_6_EQ_0b0_03_78_OR_tlb_lookup_rg_sa_ETC___d392,
       NOT_rg_priv_6_EQ_0b0_03_78_OR_tlb_lookup_rg_sa_ETC___d415,
       NOT_rg_priv_6_EQ_0b0_03_78_OR_tlb_lookup_rg_sa_ETC___d453,
       NOT_rg_priv_6_EQ_0b0_03_78_OR_tlb_lookup_rg_sa_ETC___d669,
       NOT_rg_priv_6_ULE_0b1_7_8_OR_NOT_rg_satp_9_BIT_ETC___d169,
       NOT_rg_priv_6_ULE_0b1_7_8_OR_NOT_rg_satp_9_BIT_ETC___d350,
       NOT_rg_priv_6_ULE_0b1_7_8_OR_NOT_rg_satp_9_BIT_ETC___d397,
       NOT_rg_priv_6_ULE_0b1_7_8_OR_NOT_rg_satp_9_BIT_ETC___d412,
       NOT_rg_priv_6_ULE_0b1_7_8_OR_NOT_rg_satp_9_BIT_ETC___d464,
       NOT_rg_priv_6_ULE_0b1_7_8_OR_NOT_rg_satp_9_BIT_ETC___d465,
       NOT_rg_priv_6_ULE_0b1_7_8_OR_NOT_rg_satp_9_BIT_ETC___d472,
       NOT_rg_priv_6_ULE_0b1_7_8_OR_NOT_rg_satp_9_BIT_ETC___d475,
       NOT_rg_priv_6_ULE_0b1_7_8_OR_NOT_rg_satp_9_BIT_ETC___d481,
       NOT_rg_priv_6_ULE_0b1_7_8_OR_NOT_rg_satp_9_BIT_ETC___d502,
       NOT_rg_priv_6_ULE_0b1_7_8_OR_NOT_rg_satp_9_BIT_ETC___d508,
       NOT_rg_priv_6_ULE_0b1_7_8_OR_NOT_rg_satp_9_BIT_ETC___d509,
       NOT_rg_priv_6_ULE_0b1_7_8_OR_NOT_rg_satp_9_BIT_ETC___d672,
       NOT_rg_priv_6_ULE_0b1_7_8_OR_NOT_rg_satp_9_BIT_ETC___d677,
       NOT_rg_priv_6_ULE_0b1_7_8_OR_NOT_rg_satp_9_BIT_ETC___d683,
       NOT_rg_priv_6_ULE_0b1_7_8_OR_NOT_rg_satp_9_BIT_ETC___d689,
       NOT_rg_priv_6_ULE_0b1_7_8_OR_NOT_rg_satp_9_BIT_ETC___d694,
       NOT_rg_priv_6_ULE_0b1_7_8_OR_NOT_rg_satp_9_BIT_ETC___d702,
       NOT_rg_priv_6_ULE_0b1_7_8_OR_NOT_rg_satp_9_BIT_ETC___d705,
       NOT_rg_priv_6_ULE_0b1_7_8_OR_NOT_rg_satp_9_BIT_ETC___d711,
       NOT_rg_priv_6_ULE_0b1_7_8_OR_NOT_rg_satp_9_BIT_ETC___d724,
       NOT_rg_priv_6_ULE_0b1_7_8_OR_NOT_rg_satp_9_BIT_ETC___d854,
       NOT_rg_priv_6_ULE_0b1_7_8_OR_NOT_rg_satp_9_BIT_ETC___d855,
       NOT_rg_priv_6_ULE_0b1_7_8_OR_NOT_rg_satp_9_BIT_ETC___d861,
       NOT_rg_priv_6_ULE_0b1_7_8_OR_NOT_rg_satp_9_BIT_ETC___d867,
       NOT_rg_priv_6_ULE_0b1_7_8_OR_NOT_rg_satp_9_BIT_ETC___d873,
       NOT_rg_priv_6_ULE_0b1_7_8_OR_NOT_rg_satp_9_BIT_ETC___d879,
       NOT_rg_priv_6_ULE_0b1_7_8_OR_NOT_rg_satp_9_BIT_ETC___d884,
       NOT_rg_priv_6_ULE_0b1_7_8_OR_NOT_rg_satp_9_BIT_ETC___d885,
       NOT_rg_priv_6_ULE_0b1_7_8_OR_NOT_rg_satp_9_BIT_ETC___d890,
       NOT_rg_priv_6_ULE_0b1_7_8_OR_NOT_rg_satp_9_BIT_ETC___d896,
       NOT_rg_priv_6_ULE_0b1_7_8_OR_NOT_rg_satp_9_BIT_ETC___d897,
       NOT_rg_priv_6_ULE_0b1_7_8_OR_NOT_rg_satp_9_BIT_ETC___d902,
       NOT_rg_priv_6_ULE_0b1_7_8_OR_NOT_rg_satp_9_BIT_ETC___d903,
       NOT_rg_priv_6_ULE_0b1_7_8_OR_NOT_rg_satp_9_BIT_ETC___d909,
       NOT_rg_priv_6_ULE_0b1_7_8_OR_NOT_rg_satp_9_BIT_ETC___d914,
       NOT_rg_priv_6_ULE_0b1_7_8_OR_NOT_rg_satp_9_BIT_ETC___d915,
       NOT_rg_priv_6_ULE_0b1_7_8_OR_NOT_rg_satp_9_BIT_ETC___d920,
       NOT_rg_priv_6_ULE_0b1_7_8_OR_NOT_rg_satp_9_BIT_ETC___d925,
       NOT_tlb_lookup_rg_satp_9_BITS_59_TO_44_6_rg_ad_ETC___d150,
       NOT_tlb_lookup_rg_satp_9_BITS_59_TO_44_6_rg_ad_ETC___d166,
       cfg_verbosity_read__1_ULE_1___d42,
       dmem_not_imem_AND_rg_op_13_EQ_0_14_OR_rg_op_13_ETC___d387,
       dmem_not_imem_OR_NOT_rg_op_13_EQ_0_14_15_AND_N_ETC___d127,
       lrsc_result__h21885,
       master_xactor_f_rd_data_first__41_BITS_2_TO_1__ETC___d1007,
       master_xactor_f_rd_data_first__41_BITS_2_TO_1__ETC___d1015,
       master_xactor_f_rd_data_first__41_BITS_2_TO_1__ETC___d1019,
       master_xactor_f_rd_data_first__41_BITS_2_TO_1__ETC___d1050,
       master_xactor_f_rd_data_first__41_BITS_2_TO_1__ETC___d1054,
       master_xactor_f_rd_data_first__41_BITS_2_TO_1__ETC___d1060,
       master_xactor_f_rd_data_first__41_BITS_2_TO_1__ETC___d1085,
       master_xactor_f_rd_data_first__41_BITS_2_TO_1__ETC___d981,
       master_xactor_f_rd_data_first__41_BITS_2_TO_1__ETC___d991,
       ram_state_and_ctag_cset_b_read__00_BITS_104_TO_ETC___d211,
       ram_state_and_ctag_cset_b_read__00_BITS_51_TO__ETC___d205,
       ram_state_and_ctag_cset_b_read__00_BIT_52_01_A_ETC___d484,
       ram_state_and_ctag_cset_b_read__00_BIT_52_01_A_ETC___d495,
       ram_state_and_ctag_cset_b_read__00_BIT_52_01_A_ETC___d673,
       ram_state_and_ctag_cset_b_read__00_BIT_52_01_A_ETC___d916,
       req_f3_BITS_1_TO_0_433_EQ_0b0_434_OR_req_f3_BI_ETC___d1463,
       rg_amo_funct7_18_BITS_6_TO_2_19_EQ_0b10_20_AND_ETC___d680,
       rg_amo_funct7_18_BITS_6_TO_2_19_EQ_0b1_88_OR_I_ETC___d344,
       rg_lrsc_pa_70_EQ_IF_rg_priv_6_ULE_0b1_7_AND_rg_ETC___d271,
       rg_op_13_EQ_0_14_OR_rg_op_13_EQ_2_16_AND_rg_am_ETC___d431,
       rg_op_13_EQ_0_14_OR_rg_op_13_EQ_2_16_AND_rg_am_ETC___d468,
       rg_op_13_EQ_0_14_OR_rg_op_13_EQ_2_16_AND_rg_am_ETC___d489,
       rg_op_13_EQ_0_14_OR_rg_op_13_EQ_2_16_AND_rg_am_ETC___d499,
       rg_op_13_EQ_0_14_OR_rg_op_13_EQ_2_16_AND_rg_am_ETC___d503,
       rg_op_13_EQ_1_66_OR_rg_op_13_EQ_2_16_AND_rg_am_ETC___d497,
       rg_op_13_EQ_1_66_OR_rg_op_13_EQ_2_16_AND_rg_am_ETC___d720,
       rg_op_13_EQ_1_66_OR_rg_op_13_EQ_2_16_AND_rg_am_ETC___d850,
       rg_op_13_EQ_2_16_AND_rg_amo_funct7_18_BITS_6_T_ETC___d287,
       rg_priv_6_EQ_0b0_03_AND_NOT_tlb_lookup_rg_satp_ETC___d144,
       rg_priv_6_EQ_0b0_03_AND_NOT_tlb_lookup_rg_satp_ETC___d157,
       rg_priv_6_ULE_0b1_7_AND_rg_satp_9_BITS_63_TO_6_ETC___d153,
       rg_priv_6_ULE_0b1_7_AND_rg_satp_9_BITS_63_TO_6_ETC___d352,
       rg_priv_6_ULE_0b1_7_AND_rg_satp_9_BITS_63_TO_6_ETC___d400,
       rg_priv_6_ULE_0b1_7_AND_rg_satp_9_BITS_63_TO_6_ETC___d422,
       rg_priv_6_ULE_0b1_7_AND_rg_satp_9_BITS_63_TO_6_ETC___d439,
       rg_priv_6_ULE_0b1_7_AND_rg_satp_9_BITS_63_TO_6_ETC___d440,
       rg_priv_6_ULE_0b1_7_AND_rg_satp_9_BITS_63_TO_6_ETC___d458,
       rg_priv_6_ULE_0b1_7_AND_rg_satp_9_BITS_63_TO_6_ETC___d461,
       rg_priv_6_ULE_0b1___d87,
       rg_state_1_EQ_13_148_AND_rg_op_13_EQ_0_14_OR_r_ETC___d1150,
       tlb_lookup_rg_satp_9_BITS_59_TO_44_6_rg_addr_7_ETC___d133,
       tlb_lookup_rg_satp_9_BITS_59_TO_44_6_rg_addr_7_ETC___d394,
       y__h6567;

  // action method set_verbosity
  assign RDY_set_verbosity = 1'd1 ;
  assign CAN_FIRE_set_verbosity = 1'd1 ;
  assign WILL_FIRE_set_verbosity = EN_set_verbosity ;

  // action method server_reset_request_put
  assign RDY_server_reset_request_put = f_reset_reqs$FULL_N ;
  assign CAN_FIRE_server_reset_request_put = f_reset_reqs$FULL_N ;
  assign WILL_FIRE_server_reset_request_put = EN_server_reset_request_put ;

  // action method server_reset_response_get
  assign RDY_server_reset_response_get =
	     !f_reset_rsps$D_OUT && f_reset_rsps$EMPTY_N ;
  assign CAN_FIRE_server_reset_response_get =
	     !f_reset_rsps$D_OUT && f_reset_rsps$EMPTY_N ;
  assign WILL_FIRE_server_reset_response_get = EN_server_reset_response_get ;

  // action method req
  assign CAN_FIRE_req = 1'd1 ;
  assign WILL_FIRE_req = EN_req ;

  // value method valid
  assign valid = dw_valid$whas ;

  // value method addr
  assign addr = rg_addr ;

  // value method cword
  always@(MUX_dw_output_ld_val$wset_1__SEL_1 or
	  ld_val__h35601 or
	  MUX_dw_output_ld_val$wset_1__SEL_2 or
	  new_ld_val__h37807 or
	  MUX_dw_valid$wset_1__SEL_2 or
	  MUX_dw_output_ld_val$wset_1__VAL_3 or
	  MUX_dw_output_ld_val$wset_1__SEL_4 or rg_ld_val)
  begin
    case (1'b1) // synopsys parallel_case
      MUX_dw_output_ld_val$wset_1__SEL_1: cword = ld_val__h35601;
      MUX_dw_output_ld_val$wset_1__SEL_2: cword = new_ld_val__h37807;
      MUX_dw_valid$wset_1__SEL_2: cword = MUX_dw_output_ld_val$wset_1__VAL_3;
      MUX_dw_output_ld_val$wset_1__SEL_4: cword = rg_ld_val;
      default: cword = 64'hAAAAAAAAAAAAAAAA /* unspecified value */ ;
    endcase
  end

  // value method st_amo_val
  assign st_amo_val = MUX_dw_valid$wset_1__SEL_2 ? 64'd0 : rg_st_amo_val ;

  // value method exc
  assign exc = rg_state == 5'd4 ;

  // value method exc_code
  assign exc_code = rg_exc_code ;

  // action method server_flush_request_put
  assign RDY_server_flush_request_put = f_reset_reqs$FULL_N ;
  assign CAN_FIRE_server_flush_request_put = f_reset_reqs$FULL_N ;
  assign WILL_FIRE_server_flush_request_put = EN_server_flush_request_put ;

  // action method server_flush_response_get
  assign RDY_server_flush_response_get =
	     f_reset_rsps$D_OUT && f_reset_rsps$EMPTY_N ;
  assign CAN_FIRE_server_flush_response_get =
	     f_reset_rsps$D_OUT && f_reset_rsps$EMPTY_N ;
  assign WILL_FIRE_server_flush_response_get = EN_server_flush_response_get ;

  // action method tlb_flush
  assign RDY_tlb_flush = 1'd1 ;
  assign CAN_FIRE_tlb_flush = 1'd1 ;
  assign WILL_FIRE_tlb_flush = EN_tlb_flush ;

  // value method mem_master_m_awvalid
  assign mem_master_awvalid = master_xactor_f_wr_addr$EMPTY_N ;

  // value method mem_master_m_awid
  assign mem_master_awid = master_xactor_f_wr_addr$D_OUT[96:93] ;

  // value method mem_master_m_awaddr
  assign mem_master_awaddr = master_xactor_f_wr_addr$D_OUT[92:29] ;

  // value method mem_master_m_awlen
  assign mem_master_awlen = master_xactor_f_wr_addr$D_OUT[28:21] ;

  // value method mem_master_m_awsize
  assign mem_master_awsize = master_xactor_f_wr_addr$D_OUT[20:18] ;

  // value method mem_master_m_awburst
  assign mem_master_awburst = master_xactor_f_wr_addr$D_OUT[17:16] ;

  // value method mem_master_m_awlock
  assign mem_master_awlock = master_xactor_f_wr_addr$D_OUT[15] ;

  // value method mem_master_m_awcache
  assign mem_master_awcache = master_xactor_f_wr_addr$D_OUT[14:11] ;

  // value method mem_master_m_awprot
  assign mem_master_awprot = master_xactor_f_wr_addr$D_OUT[10:8] ;

  // value method mem_master_m_awqos
  assign mem_master_awqos = master_xactor_f_wr_addr$D_OUT[7:4] ;

  // value method mem_master_m_awregion
  assign mem_master_awregion = master_xactor_f_wr_addr$D_OUT[3:0] ;

  // action method mem_master_m_awready
  assign CAN_FIRE_mem_master_m_awready = 1'd1 ;
  assign WILL_FIRE_mem_master_m_awready = 1'd1 ;

  // value method mem_master_m_wvalid
  assign mem_master_wvalid = master_xactor_f_wr_data$EMPTY_N ;

  // value method mem_master_m_wdata
  assign mem_master_wdata = master_xactor_f_wr_data$D_OUT[72:9] ;

  // value method mem_master_m_wstrb
  assign mem_master_wstrb = master_xactor_f_wr_data$D_OUT[8:1] ;

  // value method mem_master_m_wlast
  assign mem_master_wlast = master_xactor_f_wr_data$D_OUT[0] ;

  // action method mem_master_m_wready
  assign CAN_FIRE_mem_master_m_wready = 1'd1 ;
  assign WILL_FIRE_mem_master_m_wready = 1'd1 ;

  // action method mem_master_m_bvalid
  assign CAN_FIRE_mem_master_m_bvalid = 1'd1 ;
  assign WILL_FIRE_mem_master_m_bvalid = 1'd1 ;

  // value method mem_master_m_bready
  assign mem_master_bready = master_xactor_f_wr_resp$FULL_N ;

  // value method mem_master_m_arvalid
  assign mem_master_arvalid = master_xactor_f_rd_addr$EMPTY_N ;

  // value method mem_master_m_arid
  assign mem_master_arid = master_xactor_f_rd_addr$D_OUT[96:93] ;

  // value method mem_master_m_araddr
  assign mem_master_araddr = master_xactor_f_rd_addr$D_OUT[92:29] ;

  // value method mem_master_m_arlen
  assign mem_master_arlen = master_xactor_f_rd_addr$D_OUT[28:21] ;

  // value method mem_master_m_arsize
  assign mem_master_arsize = master_xactor_f_rd_addr$D_OUT[20:18] ;

  // value method mem_master_m_arburst
  assign mem_master_arburst = master_xactor_f_rd_addr$D_OUT[17:16] ;

  // value method mem_master_m_arlock
  assign mem_master_arlock = master_xactor_f_rd_addr$D_OUT[15] ;

  // value method mem_master_m_arcache
  assign mem_master_arcache = master_xactor_f_rd_addr$D_OUT[14:11] ;

  // value method mem_master_m_arprot
  assign mem_master_arprot = master_xactor_f_rd_addr$D_OUT[10:8] ;

  // value method mem_master_m_arqos
  assign mem_master_arqos = master_xactor_f_rd_addr$D_OUT[7:4] ;

  // value method mem_master_m_arregion
  assign mem_master_arregion = master_xactor_f_rd_addr$D_OUT[3:0] ;

  // action method mem_master_m_arready
  assign CAN_FIRE_mem_master_m_arready = 1'd1 ;
  assign WILL_FIRE_mem_master_m_arready = 1'd1 ;

  // action method mem_master_m_rvalid
  assign CAN_FIRE_mem_master_m_rvalid = 1'd1 ;
  assign WILL_FIRE_mem_master_m_rvalid = 1'd1 ;

  // value method mem_master_m_rready
  assign mem_master_rready = master_xactor_f_rd_data$FULL_N ;

  // action method ma_ddr4_ready
  assign RDY_ma_ddr4_ready = 1'd1 ;
  assign CAN_FIRE_ma_ddr4_ready = 1'd1 ;
  assign WILL_FIRE_ma_ddr4_ready = EN_ma_ddr4_ready ;

  // value method mv_status
  assign mv_status = rg_wr_rsp_err ? 8'd1 : 8'd0 ;

  // submodule f_fabric_write_reqs
  FIFO2 #(.width(32'd131), .guarded(32'd1)) f_fabric_write_reqs(.RST(RST_N),
								.CLK(CLK),
								.D_IN(f_fabric_write_reqs$D_IN),
								.ENQ(f_fabric_write_reqs$ENQ),
								.DEQ(f_fabric_write_reqs$DEQ),
								.CLR(f_fabric_write_reqs$CLR),
								.D_OUT(f_fabric_write_reqs$D_OUT),
								.FULL_N(f_fabric_write_reqs$FULL_N),
								.EMPTY_N(f_fabric_write_reqs$EMPTY_N));

  // submodule f_pte_writebacks
  FIFO2 #(.width(32'd128), .guarded(32'd1)) f_pte_writebacks(.RST(RST_N),
							     .CLK(CLK),
							     .D_IN(f_pte_writebacks$D_IN),
							     .ENQ(f_pte_writebacks$ENQ),
							     .DEQ(f_pte_writebacks$DEQ),
							     .CLR(f_pte_writebacks$CLR),
							     .D_OUT(f_pte_writebacks$D_OUT),
							     .FULL_N(f_pte_writebacks$FULL_N),
							     .EMPTY_N(f_pte_writebacks$EMPTY_N));

  // submodule f_reset_reqs
  FIFO2 #(.width(32'd1), .guarded(32'd1)) f_reset_reqs(.RST(RST_N),
						       .CLK(CLK),
						       .D_IN(f_reset_reqs$D_IN),
						       .ENQ(f_reset_reqs$ENQ),
						       .DEQ(f_reset_reqs$DEQ),
						       .CLR(f_reset_reqs$CLR),
						       .D_OUT(f_reset_reqs$D_OUT),
						       .FULL_N(f_reset_reqs$FULL_N),
						       .EMPTY_N(f_reset_reqs$EMPTY_N));

  // submodule f_reset_rsps
  FIFO2 #(.width(32'd1), .guarded(32'd1)) f_reset_rsps(.RST(RST_N),
						       .CLK(CLK),
						       .D_IN(f_reset_rsps$D_IN),
						       .ENQ(f_reset_rsps$ENQ),
						       .DEQ(f_reset_rsps$DEQ),
						       .CLR(f_reset_rsps$CLR),
						       .D_OUT(f_reset_rsps$D_OUT),
						       .FULL_N(f_reset_rsps$FULL_N),
						       .EMPTY_N(f_reset_rsps$EMPTY_N));

  // submodule master_xactor_f_rd_addr
  FIFO2 #(.width(32'd97),
	  .guarded(32'd1)) master_xactor_f_rd_addr(.RST(RST_N),
						   .CLK(CLK),
						   .D_IN(master_xactor_f_rd_addr$D_IN),
						   .ENQ(master_xactor_f_rd_addr$ENQ),
						   .DEQ(master_xactor_f_rd_addr$DEQ),
						   .CLR(master_xactor_f_rd_addr$CLR),
						   .D_OUT(master_xactor_f_rd_addr$D_OUT),
						   .FULL_N(master_xactor_f_rd_addr$FULL_N),
						   .EMPTY_N(master_xactor_f_rd_addr$EMPTY_N));

  // submodule master_xactor_f_rd_data
  FIFO2 #(.width(32'd71),
	  .guarded(32'd1)) master_xactor_f_rd_data(.RST(RST_N),
						   .CLK(CLK),
						   .D_IN(master_xactor_f_rd_data$D_IN),
						   .ENQ(master_xactor_f_rd_data$ENQ),
						   .DEQ(master_xactor_f_rd_data$DEQ),
						   .CLR(master_xactor_f_rd_data$CLR),
						   .D_OUT(master_xactor_f_rd_data$D_OUT),
						   .FULL_N(master_xactor_f_rd_data$FULL_N),
						   .EMPTY_N(master_xactor_f_rd_data$EMPTY_N));

  // submodule master_xactor_f_wr_addr
  FIFO2 #(.width(32'd97),
	  .guarded(32'd1)) master_xactor_f_wr_addr(.RST(RST_N),
						   .CLK(CLK),
						   .D_IN(master_xactor_f_wr_addr$D_IN),
						   .ENQ(master_xactor_f_wr_addr$ENQ),
						   .DEQ(master_xactor_f_wr_addr$DEQ),
						   .CLR(master_xactor_f_wr_addr$CLR),
						   .D_OUT(master_xactor_f_wr_addr$D_OUT),
						   .FULL_N(master_xactor_f_wr_addr$FULL_N),
						   .EMPTY_N(master_xactor_f_wr_addr$EMPTY_N));

  // submodule master_xactor_f_wr_data
  FIFO2 #(.width(32'd73),
	  .guarded(32'd1)) master_xactor_f_wr_data(.RST(RST_N),
						   .CLK(CLK),
						   .D_IN(master_xactor_f_wr_data$D_IN),
						   .ENQ(master_xactor_f_wr_data$ENQ),
						   .DEQ(master_xactor_f_wr_data$DEQ),
						   .CLR(master_xactor_f_wr_data$CLR),
						   .D_OUT(master_xactor_f_wr_data$D_OUT),
						   .FULL_N(master_xactor_f_wr_data$FULL_N),
						   .EMPTY_N(master_xactor_f_wr_data$EMPTY_N));

  // submodule master_xactor_f_wr_resp
  FIFO2 #(.width(32'd6), .guarded(32'd1)) master_xactor_f_wr_resp(.RST(RST_N),
								  .CLK(CLK),
								  .D_IN(master_xactor_f_wr_resp$D_IN),
								  .ENQ(master_xactor_f_wr_resp$ENQ),
								  .DEQ(master_xactor_f_wr_resp$DEQ),
								  .CLR(master_xactor_f_wr_resp$CLR),
								  .D_OUT(master_xactor_f_wr_resp$D_OUT),
								  .FULL_N(master_xactor_f_wr_resp$FULL_N),
								  .EMPTY_N(master_xactor_f_wr_resp$EMPTY_N));

  // submodule ram_cword_set
  BRAM2 #(.PIPELINED(1'd0),
	  .ADDR_WIDTH(32'd9),
	  .DATA_WIDTH(32'd128),
	  .MEMSIZE(10'd512)) ram_cword_set(.CLKA(CLK),
					   .CLKB(CLK),
					   .ADDRA(ram_cword_set$ADDRA),
					   .ADDRB(ram_cword_set$ADDRB),
					   .DIA(ram_cword_set$DIA),
					   .DIB(ram_cword_set$DIB),
					   .WEA(ram_cword_set$WEA),
					   .WEB(ram_cword_set$WEB),
					   .ENA(ram_cword_set$ENA),
					   .ENB(ram_cword_set$ENB),
					   .DOA(),
					   .DOB(ram_cword_set$DOB));

  // submodule ram_state_and_ctag_cset
  BRAM2 #(.PIPELINED(1'd0),
	  .ADDR_WIDTH(32'd6),
	  .DATA_WIDTH(32'd106),
	  .MEMSIZE(7'd64)) ram_state_and_ctag_cset(.CLKA(CLK),
						   .CLKB(CLK),
						   .ADDRA(ram_state_and_ctag_cset$ADDRA),
						   .ADDRB(ram_state_and_ctag_cset$ADDRB),
						   .DIA(ram_state_and_ctag_cset$DIA),
						   .DIB(ram_state_and_ctag_cset$DIB),
						   .WEA(ram_state_and_ctag_cset$WEA),
						   .WEB(ram_state_and_ctag_cset$WEB),
						   .ENA(ram_state_and_ctag_cset$ENA),
						   .ENB(ram_state_and_ctag_cset$ENB),
						   .DOA(),
						   .DOB(ram_state_and_ctag_cset$DOB));

  // submodule soc_map
  mkSoC_Map soc_map(.CLK(CLK),
		    .RST_N(RST_N),
		    .m_is_IO_addr_addr(soc_map$m_is_IO_addr_addr),
		    .m_is_mem_addr_addr(soc_map$m_is_mem_addr_addr),
		    .m_is_near_mem_IO_addr_addr(soc_map$m_is_near_mem_IO_addr_addr),
		    .m_plic_addr_base(),
		    .m_plic_addr_size(),
		    .m_plic_addr_lim(),
		    .m_near_mem_io_addr_base(),
		    .m_near_mem_io_addr_size(),
		    .m_near_mem_io_addr_lim(),
		    .m_flash_mem_addr_base(),
		    .m_flash_mem_addr_size(),
		    .m_flash_mem_addr_lim(),
		    .m_ethernet_0_addr_base(),
		    .m_ethernet_0_addr_size(),
		    .m_ethernet_0_addr_lim(),
		    .m_dma_0_addr_base(),
		    .m_dma_0_addr_size(),
		    .m_dma_0_addr_lim(),
		    .m_uart16550_0_addr_base(),
		    .m_uart16550_0_addr_size(),
		    .m_uart16550_0_addr_lim(),
		    .m_gpio_0_addr_base(),
		    .m_gpio_0_addr_size(),
		    .m_gpio_0_addr_lim(),
		    .m_boot_rom_addr_base(),
		    .m_boot_rom_addr_size(),
		    .m_boot_rom_addr_lim(),
		    .m_ddr4_0_uncached_addr_base(),
		    .m_ddr4_0_uncached_addr_size(),
		    .m_ddr4_0_uncached_addr_lim(),
		    .m_ddr4_0_cached_addr_base(),
		    .m_ddr4_0_cached_addr_size(),
		    .m_ddr4_0_cached_addr_lim(),
		    .m_is_mem_addr(soc_map$m_is_mem_addr),
		    .m_is_IO_addr(),
		    .m_is_near_mem_IO_addr(),
		    .m_pc_reset_value(),
		    .m_mtvec_reset_value(),
		    .m_nmivec_reset_value());

  // submodule tlb
  mkTLB #(.dmem_not_imem(dmem_not_imem)) tlb(.CLK(CLK),
					     .RST_N(RST_N),
					     .insert_asid(tlb$insert_asid),
					     .insert_level(tlb$insert_level),
					     .insert_pte(tlb$insert_pte),
					     .insert_pte_pa(tlb$insert_pte_pa),
					     .insert_vpn(tlb$insert_vpn),
					     .lookup_asid(tlb$lookup_asid),
					     .lookup_vpn(tlb$lookup_vpn),
					     .EN_flush(tlb$EN_flush),
					     .EN_insert(tlb$EN_insert),
					     .RDY_flush(),
					     .lookup(tlb$lookup),
					     .RDY_lookup(tlb$RDY_lookup),
					     .RDY_insert(tlb$RDY_insert));

  // rule RL_rl_fabric_send_write_req
  assign CAN_FIRE_RL_rl_fabric_send_write_req =
	     NOT_ctr_wr_rsps_pending_crg_port0__read_EQ_15__ETC___d9 &&
	     rg_ddr4_ready ;
  assign WILL_FIRE_RL_rl_fabric_send_write_req =
	     CAN_FIRE_RL_rl_fabric_send_write_req ;

  // rule RL_rl_reset
  assign CAN_FIRE_RL_rl_reset =
	     (rg_cset_in_cache != 6'd63 ||
	      f_reset_reqs$EMPTY_N && f_reset_rsps$FULL_N) &&
	     rg_state == 5'd1 ;
  assign WILL_FIRE_RL_rl_reset = CAN_FIRE_RL_rl_reset ;

  // rule RL_rl_probe_and_immed_rsp
  assign CAN_FIRE_RL_rl_probe_and_immed_rsp =
	     (cfg_verbosity_read__1_ULE_1___d42 || tlb$RDY_lookup) &&
	     (!rg_priv_6_ULE_0b1___d87 || rg_satp[63:60] != 4'd8 ||
	      tlb$RDY_lookup) &&
	     rg_priv_6_ULE_0b1_7_AND_rg_satp_9_BITS_63_TO_6_ETC___d352 &&
	     rg_ddr4_ready &&
	     rg_state == 5'd3 ;
  assign WILL_FIRE_RL_rl_probe_and_immed_rsp =
	     CAN_FIRE_RL_rl_probe_and_immed_rsp &&
	     !WILL_FIRE_RL_rl_start_reset ;

  // rule RL_rl_start_tlb_refill
  assign CAN_FIRE_RL_rl_start_tlb_refill =
	     master_xactor_f_rd_addr$FULL_N && rg_state == 5'd5 &&
	     b__h28690 == 4'd0 ;
  assign WILL_FIRE_RL_rl_start_tlb_refill =
	     CAN_FIRE_RL_rl_start_tlb_refill && !WILL_FIRE_RL_rl_start_reset ;

  // rule RL_rl_ptw_level_2
  assign CAN_FIRE_RL_rl_ptw_level_2 =
	     master_xactor_f_rd_data$EMPTY_N &&
	     NOT_master_xactor_f_rd_data_first__41_BITS_2_T_ETC___d965 &&
	     rg_state == 5'd6 ;
  assign WILL_FIRE_RL_rl_ptw_level_2 =
	     MUX_master_xactor_f_rd_addr$enq_1__PSEL_1 ;

  // rule RL_rl_ptw_level_1
  assign CAN_FIRE_RL_rl_ptw_level_1 =
	     master_xactor_f_rd_data$EMPTY_N &&
	     NOT_master_xactor_f_rd_data_first__41_BITS_2_T_ETC___d1028 &&
	     rg_state == 5'd7 ;
  assign WILL_FIRE_RL_rl_ptw_level_1 =
	     MUX_master_xactor_f_rd_addr$enq_1__PSEL_2 ;

  // rule RL_rl_ptw_level_0
  assign CAN_FIRE_RL_rl_ptw_level_0 =
	     master_xactor_f_rd_data$EMPTY_N &&
	     (master_xactor_f_rd_data$D_OUT[2:1] != 2'b0 ||
	      !master_xactor_f_rd_data$D_OUT[3] ||
	      !master_xactor_f_rd_data$D_OUT[4] &&
	      master_xactor_f_rd_data$D_OUT[5] ||
	      !master_xactor_f_rd_data$D_OUT[6] &&
	      !master_xactor_f_rd_data$D_OUT[4] ||
	      tlb$RDY_insert) &&
	     rg_state == 5'd8 ;
  assign WILL_FIRE_RL_rl_ptw_level_0 =
	     CAN_FIRE_RL_rl_ptw_level_0 && !WILL_FIRE_RL_rl_start_reset ;

  // rule RL_rl_start_cache_refill
  assign CAN_FIRE_RL_rl_start_cache_refill =
	     master_xactor_f_rd_addr$FULL_N && rg_state == 5'd9 &&
	     b__h28690 == 4'd0 ;
  assign WILL_FIRE_RL_rl_start_cache_refill =
	     CAN_FIRE_RL_rl_start_cache_refill &&
	     !WILL_FIRE_RL_rl_start_reset &&
	     !EN_req ;

  // rule RL_rl_cache_refill_rsps_loop
  assign CAN_FIRE_RL_rl_cache_refill_rsps_loop =
	     master_xactor_f_rd_data$EMPTY_N && rg_state == 5'd10 ;
  assign WILL_FIRE_RL_rl_cache_refill_rsps_loop =
	     CAN_FIRE_RL_rl_cache_refill_rsps_loop &&
	     !WILL_FIRE_RL_rl_start_reset &&
	     !EN_req ;

  // rule RL_rl_rereq
  assign CAN_FIRE_RL_rl_rereq = rg_state == 5'd11 ;
  assign WILL_FIRE_RL_rl_rereq =
	     CAN_FIRE_RL_rl_rereq && !WILL_FIRE_RL_rl_start_reset && !EN_req ;

  // rule RL_rl_ST_AMO_response
  assign CAN_FIRE_RL_rl_ST_AMO_response = rg_state == 5'd12 ;
  assign WILL_FIRE_RL_rl_ST_AMO_response = CAN_FIRE_RL_rl_ST_AMO_response ;

  // rule RL_rl_io_read_req
  assign CAN_FIRE_RL_rl_io_read_req =
	     master_xactor_f_rd_addr$FULL_N &&
	     rg_state_1_EQ_13_148_AND_rg_op_13_EQ_0_14_OR_r_ETC___d1150 ;
  assign WILL_FIRE_RL_rl_io_read_req =
	     CAN_FIRE_RL_rl_io_read_req && !WILL_FIRE_RL_rl_start_reset ;

  // rule RL_rl_io_read_rsp
  assign CAN_FIRE_RL_rl_io_read_rsp =
	     master_xactor_f_rd_data$EMPTY_N && rg_state == 5'd14 ;
  assign WILL_FIRE_RL_rl_io_read_rsp =
	     CAN_FIRE_RL_rl_io_read_rsp && !WILL_FIRE_RL_rl_start_reset ;

  // rule RL_rl_maintain_io_read_rsp
  assign CAN_FIRE_RL_rl_maintain_io_read_rsp = rg_state == 5'd15 ;
  assign WILL_FIRE_RL_rl_maintain_io_read_rsp =
	     CAN_FIRE_RL_rl_maintain_io_read_rsp ;

  // rule RL_rl_io_write_req
  assign CAN_FIRE_RL_rl_io_write_req =
	     f_fabric_write_reqs$FULL_N && rg_state == 5'd13 &&
	     rg_op == 2'd1 ;
  assign WILL_FIRE_RL_rl_io_write_req =
	     CAN_FIRE_RL_rl_io_write_req && !WILL_FIRE_RL_rl_start_reset ;

  // rule RL_rl_io_AMO_SC_req
  assign CAN_FIRE_RL_rl_io_AMO_SC_req =
	     rg_state == 5'd13 && rg_op == 2'd2 &&
	     rg_amo_funct7[6:2] == 5'b00011 ;
  assign WILL_FIRE_RL_rl_io_AMO_SC_req =
	     CAN_FIRE_RL_rl_io_AMO_SC_req && !WILL_FIRE_RL_rl_start_reset ;

  // rule RL_rl_io_AMO_op_req
  assign CAN_FIRE_RL_rl_io_AMO_op_req =
	     master_xactor_f_rd_addr$FULL_N && rg_state == 5'd13 &&
	     rg_op == 2'd2 &&
	     rg_amo_funct7[6:2] != 5'b00010 &&
	     rg_amo_funct7[6:2] != 5'b00011 ;
  assign WILL_FIRE_RL_rl_io_AMO_op_req =
	     CAN_FIRE_RL_rl_io_AMO_op_req && !WILL_FIRE_RL_rl_start_reset ;

  // rule RL_rl_writeback_updated_PTE
  assign CAN_FIRE_RL_rl_writeback_updated_PTE =
	     f_pte_writebacks$EMPTY_N && f_fabric_write_reqs$FULL_N ;
  assign WILL_FIRE_RL_rl_writeback_updated_PTE =
	     CAN_FIRE_RL_rl_writeback_updated_PTE &&
	     !WILL_FIRE_RL_rl_io_AMO_read_rsp &&
	     !WILL_FIRE_RL_rl_io_write_req &&
	     !WILL_FIRE_RL_rl_probe_and_immed_rsp ;

  // rule RL_rl_io_AMO_read_rsp
  assign CAN_FIRE_RL_rl_io_AMO_read_rsp =
	     master_xactor_f_rd_data$EMPTY_N &&
	     (master_xactor_f_rd_data$D_OUT[2:1] != 2'b0 ||
	      f_fabric_write_reqs$FULL_N) &&
	     rg_state == 5'd16 ;
  assign WILL_FIRE_RL_rl_io_AMO_read_rsp =
	     CAN_FIRE_RL_rl_io_AMO_read_rsp && !WILL_FIRE_RL_rl_start_reset ;

  // rule RL_rl_discard_write_rsp
  assign CAN_FIRE_RL_rl_discard_write_rsp =
	     b__h28690 != 4'd0 && master_xactor_f_wr_resp$EMPTY_N ;
  assign WILL_FIRE_RL_rl_discard_write_rsp =
	     CAN_FIRE_RL_rl_discard_write_rsp ;

  // rule RL_rl_drive_exception_rsp
  assign CAN_FIRE_RL_rl_drive_exception_rsp = rg_state == 5'd4 ;
  assign WILL_FIRE_RL_rl_drive_exception_rsp = rg_state == 5'd4 ;

  // rule RL_rl_start_reset
  assign CAN_FIRE_RL_rl_start_reset = MUX_rg_state$write_1__SEL_3 ;
  assign WILL_FIRE_RL_rl_start_reset = MUX_rg_state$write_1__SEL_3 ;

  // inputs to muxes for submodule ports
  assign MUX_dw_output_ld_val$wset_1__SEL_1 =
	     WILL_FIRE_RL_rl_io_read_rsp &&
	     master_xactor_f_rd_data$D_OUT[2:1] == 2'b0 ;
  assign MUX_dw_output_ld_val$wset_1__SEL_2 =
	     WILL_FIRE_RL_rl_io_AMO_read_rsp &&
	     master_xactor_f_rd_data$D_OUT[2:1] == 2'b0 ;
  assign MUX_dw_output_ld_val$wset_1__SEL_4 =
	     WILL_FIRE_RL_rl_maintain_io_read_rsp ||
	     WILL_FIRE_RL_rl_ST_AMO_response ;
  assign MUX_dw_valid$wset_1__SEL_2 =
	     WILL_FIRE_RL_rl_probe_and_immed_rsp &&
	     NOT_rg_priv_6_ULE_0b1_7_8_OR_NOT_rg_satp_9_BIT_ETC___d509 ;
  assign MUX_f_fabric_write_reqs$enq_1__SEL_2 =
	     WILL_FIRE_RL_rl_probe_and_immed_rsp &&
	     NOT_rg_priv_6_ULE_0b1_7_8_OR_NOT_rg_satp_9_BIT_ETC___d855 ;
  assign MUX_master_xactor_f_rd_addr$enq_1__PSEL_1 =
	     CAN_FIRE_RL_rl_ptw_level_2 && !WILL_FIRE_RL_rl_start_reset ;
  assign MUX_master_xactor_f_rd_addr$enq_1__SEL_1 =
	     WILL_FIRE_RL_rl_ptw_level_2 &&
	     master_xactor_f_rd_data$D_OUT[2:1] == 2'b0 &&
	     master_xactor_f_rd_data$D_OUT[3] &&
	     !master_xactor_f_rd_data$D_OUT[5] &&
	     !master_xactor_f_rd_data$D_OUT[6] &&
	     !master_xactor_f_rd_data$D_OUT[4] ;
  assign MUX_master_xactor_f_rd_addr$enq_1__PSEL_2 =
	     CAN_FIRE_RL_rl_ptw_level_1 && !WILL_FIRE_RL_rl_start_reset ;
  assign MUX_master_xactor_f_rd_addr$enq_1__SEL_2 =
	     WILL_FIRE_RL_rl_ptw_level_1 &&
	     master_xactor_f_rd_data$D_OUT[2:1] == 2'b0 &&
	     master_xactor_f_rd_data$D_OUT[3] &&
	     !master_xactor_f_rd_data$D_OUT[5] &&
	     !master_xactor_f_rd_data$D_OUT[6] &&
	     !master_xactor_f_rd_data$D_OUT[4] ;
  assign MUX_master_xactor_f_rd_addr$enq_1__SEL_3 =
	     WILL_FIRE_RL_rl_io_AMO_op_req || WILL_FIRE_RL_rl_io_read_req ;
  assign MUX_ram_cword_set$a_put_1__SEL_1 =
	     WILL_FIRE_RL_rl_cache_refill_rsps_loop &&
	     master_xactor_f_rd_data$D_OUT[2:1] == 2'b0 ;
  assign MUX_ram_cword_set$b_put_1__SEL_1 =
	     EN_req &&
	     req_f3_BITS_1_TO_0_433_EQ_0b0_434_OR_req_f3_BI_ETC___d1463 ;
  assign MUX_ram_cword_set$b_put_1__SEL_2 =
	     WILL_FIRE_RL_rl_cache_refill_rsps_loop &&
	     rg_cset_cword_in_cache[2:0] != 3'd7 ;
  assign MUX_ram_state_and_ctag_cset$a_put_1__SEL_1 =
	     WILL_FIRE_RL_rl_cache_refill_rsps_loop &&
	     rg_cset_cword_in_cache[2:0] == 3'd0 &&
	     master_xactor_f_rd_data$D_OUT[2:1] == 2'b0 ;
  assign MUX_rg_error_during_refill$write_1__SEL_1 =
	     WILL_FIRE_RL_rl_cache_refill_rsps_loop &&
	     master_xactor_f_rd_data$D_OUT[2:1] != 2'b0 ;
  assign MUX_rg_exc_code$write_1__SEL_1 =
	     EN_req &&
	     NOT_req_f3_BITS_1_TO_0_433_EQ_0b0_434_435_AND__ETC___d1454 ;
  assign MUX_rg_exc_code$write_1__SEL_2 =
	     WILL_FIRE_RL_rl_io_AMO_read_rsp &&
	     master_xactor_f_rd_data$D_OUT[2:1] != 2'b0 ;
  assign MUX_rg_exc_code$write_1__SEL_3 =
	     WILL_FIRE_RL_rl_io_read_rsp &&
	     master_xactor_f_rd_data$D_OUT[2:1] != 2'b0 ;
  assign MUX_rg_exc_code$write_1__SEL_5 =
	     WILL_FIRE_RL_rl_ptw_level_0 &&
	     (!master_xactor_f_rd_data$D_OUT[3] ||
	      !master_xactor_f_rd_data$D_OUT[4] &&
	      master_xactor_f_rd_data$D_OUT[5] ||
	      !master_xactor_f_rd_data$D_OUT[6] &&
	      !master_xactor_f_rd_data$D_OUT[4] ||
	      master_xactor_f_rd_data$D_OUT[2:1] != 2'b0) ;
  assign MUX_rg_exc_code$write_1__SEL_6 =
	     WILL_FIRE_RL_rl_ptw_level_1 &&
	     NOT_master_xactor_f_rd_data_first__41_BIT_3_45_ETC___d1034 ;
  assign MUX_rg_exc_code$write_1__SEL_7 =
	     WILL_FIRE_RL_rl_ptw_level_2 &&
	     NOT_master_xactor_f_rd_data_first__41_BIT_3_45_ETC___d972 ;
  assign MUX_rg_exc_code$write_1__SEL_8 =
	     WILL_FIRE_RL_rl_probe_and_immed_rsp &&
	     rg_priv_6_ULE_0b1_7_AND_rg_satp_9_BITS_63_TO_6_ETC___d153 ;
  assign MUX_rg_ld_val$write_1__SEL_2 =
	     WILL_FIRE_RL_rl_probe_and_immed_rsp &&
	     NOT_rg_priv_6_ULE_0b1_7_8_OR_NOT_rg_satp_9_BIT_ETC___d711 ;
  assign MUX_rg_lrsc_valid$write_1__SEL_2 =
	     WILL_FIRE_RL_rl_probe_and_immed_rsp &&
	     NOT_rg_priv_6_ULE_0b1_7_8_OR_NOT_rg_satp_9_BIT_ETC___d502 ;
  assign MUX_rg_state$write_1__SEL_3 =
	     f_reset_reqs$EMPTY_N && rg_state != 5'd1 ;
  assign MUX_rg_state$write_1__SEL_11 =
	     WILL_FIRE_RL_rl_cache_refill_rsps_loop &&
	     rg_cset_cword_in_cache[2:0] == 3'd7 ;
  assign MUX_rg_state$write_1__SEL_17 =
	     WILL_FIRE_RL_rl_probe_and_immed_rsp &&
	     rg_priv_6_ULE_0b1_7_AND_rg_satp_9_BITS_63_TO_6_ETC___d440 ;
  assign MUX_rg_state$write_1__SEL_18 =
	     WILL_FIRE_RL_rl_reset && rg_cset_in_cache == 6'd63 ;
  assign MUX_tlb$insert_1__SEL_1 =
	     WILL_FIRE_RL_rl_probe_and_immed_rsp &&
	     rg_priv_6_ULE_0b1_7_AND_rg_satp_9_BITS_63_TO_6_ETC___d422 ;
  assign MUX_tlb$insert_1__SEL_2 =
	     WILL_FIRE_RL_rl_ptw_level_2 &&
	     master_xactor_f_rd_data_first__41_BITS_2_TO_1__ETC___d1015 ;
  assign MUX_tlb$insert_1__SEL_3 =
	     WILL_FIRE_RL_rl_ptw_level_1 &&
	     master_xactor_f_rd_data_first__41_BITS_2_TO_1__ETC___d1050 ;
  assign MUX_tlb$insert_2__SEL_4 =
	     WILL_FIRE_RL_rl_ptw_level_0 &&
	     master_xactor_f_rd_data$D_OUT[2:1] == 2'b0 &&
	     master_xactor_f_rd_data$D_OUT[3] &&
	     (master_xactor_f_rd_data$D_OUT[4] ||
	      !master_xactor_f_rd_data$D_OUT[5]) &&
	     (master_xactor_f_rd_data$D_OUT[6] ||
	      master_xactor_f_rd_data$D_OUT[4]) ;
  assign MUX_dw_output_ld_val$wset_1__VAL_3 =
	     (rg_op == 2'd0 ||
	      rg_op == 2'd2 && rg_amo_funct7[6:2] == 5'b00010) ?
	       new_value__h7887 :
	       new_value__h24314 ;
  assign MUX_f_fabric_write_reqs$enq_1__VAL_1 = { rg_f3, rg_pa, x__h37836 } ;
  assign MUX_f_fabric_write_reqs$enq_1__VAL_2 =
	     { rg_f3,
	       x1_avValue_pa__h6240,
	       IF_rg_op_13_EQ_1_66_OR_rg_op_13_EQ_2_16_AND_rg_ETC___d856 } ;
  assign MUX_f_fabric_write_reqs$enq_1__VAL_3 =
	     { 3'b011, f_pte_writebacks$D_OUT } ;
  assign MUX_f_fabric_write_reqs$enq_1__VAL_4 =
	     { rg_f3, rg_pa, rg_st_amo_val } ;
  assign MUX_master_xactor_f_rd_addr$enq_1__VAL_1 =
	     { 4'd0, lev_1_pte_pa_w64_fa__h29688, 29'd851968 } ;
  assign MUX_master_xactor_f_rd_addr$enq_1__VAL_2 =
	     { 4'd0, lev_0_pte_pa_w64_fa__h30721, 29'd851968 } ;
  assign MUX_master_xactor_f_rd_addr$enq_1__VAL_3 =
	     { 4'd0, rg_pa, 8'd0, value__h37393, 18'd65536 } ;
  assign MUX_master_xactor_f_rd_addr$enq_1__VAL_4 =
	     { 4'd0, lev_2_pte_pa_w64_fa__h28791, 29'd851968 } ;
  assign MUX_master_xactor_f_rd_addr$enq_1__VAL_5 =
	     { 4'd0, cline_fabric_addr__h31891, 29'd15532032 } ;
  assign MUX_ram_cword_set$a_put_3__VAL_1 =
	     rg_victim_way ?
	       { master_xactor_f_rd_data$D_OUT[66:3],
		 ram_cword_set$DOB[63:0] } :
	       { ram_cword_set$DOB[127:64],
		 master_xactor_f_rd_data$D_OUT[66:3] } ;
  assign MUX_ram_cword_set$a_put_3__VAL_2 =
	     (rg_op == 2'd1 ||
	      rg_op == 2'd2 && rg_amo_funct7[6:2] == 5'b00011) ?
	       { IF_ram_state_and_ctag_cset_b_read__00_BIT_105__ETC___d778,
		 IF_NOT_ram_state_and_ctag_cset_b_read__00_BIT__ETC___d779 } :
	       { IF_ram_state_and_ctag_cset_b_read__00_BIT_105__ETC___d846,
		 IF_NOT_ram_state_and_ctag_cset_b_read__00_BIT__ETC___d847 } ;
  assign MUX_ram_cword_set$b_put_2__VAL_2 = rg_cset_cword_in_cache + 9'd1 ;
  assign MUX_ram_cword_set$b_put_2__VAL_4 = { rg_addr[11:6], 3'd0 } ;
  assign MUX_ram_state_and_ctag_cset$a_put_3__VAL_1 =
	     { rg_victim_way || ram_state_and_ctag_cset$DOB[105],
	       rg_victim_way ?
		 rg_pa[63:12] :
		 ram_state_and_ctag_cset$DOB[104:53],
	       !rg_victim_way || ram_state_and_ctag_cset$DOB[52],
	       rg_victim_way ?
		 ram_state_and_ctag_cset$DOB[51:0] :
		 rg_pa[63:12] } ;
  assign MUX_rg_cset_in_cache$write_1__VAL_1 = rg_cset_in_cache + 6'd1 ;
  assign MUX_rg_exc_code$write_1__VAL_1 = (req_op == 2'd0) ? 4'd4 : 4'd6 ;
  assign MUX_rg_exc_code$write_1__VAL_5 =
	     (master_xactor_f_rd_data$D_OUT[2:1] == 2'b0) ?
	       exc_code___1__h6641 :
	       access_exc_code__h2772 ;
  assign MUX_rg_ld_val$write_1__VAL_2 =
	     (rg_op == 2'd1 ||
	      rg_op == 2'd2 && rg_amo_funct7[6:2] == 5'b00011) ?
	       x__h21895 :
	       IF_rg_f3_17_EQ_0b10_50_THEN_SEXT_IF_rg_f3_17_E_ETC___d715 ;
  assign MUX_rg_state$write_1__VAL_2 =
	     NOT_req_f3_BITS_1_TO_0_433_EQ_0b0_434_435_AND__ETC___d1454 ?
	       5'd4 :
	       5'd3 ;
  assign MUX_rg_state$write_1__VAL_4 =
	     (master_xactor_f_rd_data$D_OUT[2:1] == 2'b0) ? 5'd15 : 5'd4 ;
  assign MUX_rg_state$write_1__VAL_11 =
	     (master_xactor_f_rd_data$D_OUT[2:1] != 2'b0 ||
	      rg_error_during_refill) ?
	       5'd4 :
	       5'd11 ;
  assign MUX_rg_state$write_1__VAL_13 =
	     (master_xactor_f_rd_data$D_OUT[2:1] == 2'b0) ?
	       ((!master_xactor_f_rd_data$D_OUT[3] ||
		 !master_xactor_f_rd_data$D_OUT[4] &&
		 master_xactor_f_rd_data$D_OUT[5] ||
		 !master_xactor_f_rd_data$D_OUT[6] &&
		 !master_xactor_f_rd_data$D_OUT[4]) ?
		  5'd4 :
		  5'd11) :
	       5'd4 ;
  assign MUX_rg_state$write_1__VAL_14 =
	     (master_xactor_f_rd_data$D_OUT[2:1] == 2'b0) ?
	       ((!master_xactor_f_rd_data$D_OUT[3] ||
		 !master_xactor_f_rd_data$D_OUT[4] &&
		 master_xactor_f_rd_data$D_OUT[5]) ?
		  5'd4 :
		  ((!master_xactor_f_rd_data$D_OUT[6] &&
		    !master_xactor_f_rd_data$D_OUT[4]) ?
		     5'd8 :
		     ((master_xactor_f_rd_data$D_OUT[21:13] == 9'd0) ?
			5'd11 :
			5'd4))) :
	       5'd4 ;
  assign MUX_rg_state$write_1__VAL_15 =
	     (master_xactor_f_rd_data$D_OUT[2:1] == 2'b0) ?
	       ((!master_xactor_f_rd_data$D_OUT[3] ||
		 !master_xactor_f_rd_data$D_OUT[4] &&
		 master_xactor_f_rd_data$D_OUT[5]) ?
		  5'd4 :
		  ((!master_xactor_f_rd_data$D_OUT[6] &&
		    !master_xactor_f_rd_data$D_OUT[4]) ?
		     5'd7 :
		     ((master_xactor_f_rd_data$D_OUT[30:22] != 9'd0 ||
		       master_xactor_f_rd_data$D_OUT[21:13] != 9'd0) ?
			5'd4 :
			5'd11))) :
	       5'd4 ;
  assign MUX_rg_state$write_1__VAL_17 =
	     (rg_priv_6_ULE_0b1___d87 && rg_satp[63:60] == 4'd8 &&
	      !tlb$lookup[130]) ?
	       5'd5 :
	       IF_rg_priv_6_ULE_0b1_7_AND_rg_satp_9_BITS_63_T_ETC___d445 ;

  // inlined wires
  assign dw_valid$whas =
	     (WILL_FIRE_RL_rl_io_read_rsp ||
	      WILL_FIRE_RL_rl_io_AMO_read_rsp) &&
	     master_xactor_f_rd_data$D_OUT[2:1] == 2'b0 ||
	     WILL_FIRE_RL_rl_probe_and_immed_rsp &&
	     NOT_rg_priv_6_ULE_0b1_7_8_OR_NOT_rg_satp_9_BIT_ETC___d509 ||
	     WILL_FIRE_RL_rl_drive_exception_rsp ||
	     WILL_FIRE_RL_rl_maintain_io_read_rsp ||
	     WILL_FIRE_RL_rl_ST_AMO_response ;
  assign ctr_wr_rsps_pending_crg$port0__write_1 =
	     ctr_wr_rsps_pending_crg + 4'd1 ;
  assign ctr_wr_rsps_pending_crg$port1__write_1 = b__h28690 - 4'd1 ;
  assign ctr_wr_rsps_pending_crg$port2__read =
	     CAN_FIRE_RL_rl_discard_write_rsp ?
	       ctr_wr_rsps_pending_crg$port1__write_1 :
	       b__h28690 ;
  assign ctr_wr_rsps_pending_crg$EN_port2__write =
	     WILL_FIRE_RL_rl_start_reset && !f_reset_reqs$D_OUT ;
  assign ctr_wr_rsps_pending_crg$port3__read =
	     ctr_wr_rsps_pending_crg$EN_port2__write ?
	       4'd0 :
	       ctr_wr_rsps_pending_crg$port2__read ;

  // register cfg_verbosity
  assign cfg_verbosity$D_IN = set_verbosity_verbosity ;
  assign cfg_verbosity$EN = EN_set_verbosity ;

  // register ctr_wr_rsps_pending_crg
  assign ctr_wr_rsps_pending_crg$D_IN = ctr_wr_rsps_pending_crg$port3__read ;
  assign ctr_wr_rsps_pending_crg$EN = 1'b1 ;

  // register rg_addr
  assign rg_addr$D_IN = req_addr ;
  assign rg_addr$EN = EN_req ;

  // register rg_amo_funct7
  assign rg_amo_funct7$D_IN = req_amo_funct7 ;
  assign rg_amo_funct7$EN = EN_req ;

  // register rg_cset_cword_in_cache
  assign rg_cset_cword_in_cache$D_IN =
	     MUX_ram_cword_set$b_put_1__SEL_2 ?
	       MUX_ram_cword_set$b_put_2__VAL_2 :
	       MUX_ram_cword_set$b_put_2__VAL_4 ;
  assign rg_cset_cword_in_cache$EN =
	     WILL_FIRE_RL_rl_cache_refill_rsps_loop &&
	     rg_cset_cword_in_cache[2:0] != 3'd7 ||
	     WILL_FIRE_RL_rl_start_cache_refill ;

  // register rg_cset_in_cache
  assign rg_cset_in_cache$D_IN =
	     WILL_FIRE_RL_rl_reset ?
	       MUX_rg_cset_in_cache$write_1__VAL_1 :
	       6'd0 ;
  assign rg_cset_in_cache$EN =
	     WILL_FIRE_RL_rl_reset || WILL_FIRE_RL_rl_start_reset ;

  // register rg_ddr4_ready
  assign rg_ddr4_ready$D_IN = 1'd1 ;
  assign rg_ddr4_ready$EN = EN_ma_ddr4_ready ;

  // register rg_error_during_refill
  assign rg_error_during_refill$D_IN =
	     MUX_rg_error_during_refill$write_1__SEL_1 ;
  assign rg_error_during_refill$EN =
	     WILL_FIRE_RL_rl_cache_refill_rsps_loop &&
	     master_xactor_f_rd_data$D_OUT[2:1] != 2'b0 ||
	     WILL_FIRE_RL_rl_start_cache_refill ;

  // register rg_exc_code
  always@(MUX_rg_exc_code$write_1__SEL_1 or
	  MUX_rg_exc_code$write_1__VAL_1 or
	  MUX_rg_exc_code$write_1__SEL_2 or
	  MUX_rg_exc_code$write_1__SEL_3 or
	  MUX_rg_error_during_refill$write_1__SEL_1 or
	  access_exc_code__h2772 or
	  MUX_rg_exc_code$write_1__SEL_5 or
	  MUX_rg_exc_code$write_1__VAL_5 or
	  MUX_rg_exc_code$write_1__SEL_6 or
	  MUX_rg_exc_code$write_1__SEL_7 or
	  MUX_rg_exc_code$write_1__SEL_8 or x1_avValue_exc_code__h6241)
  case (1'b1)
    MUX_rg_exc_code$write_1__SEL_1:
	rg_exc_code$D_IN = MUX_rg_exc_code$write_1__VAL_1;
    MUX_rg_exc_code$write_1__SEL_2: rg_exc_code$D_IN = 4'd7;
    MUX_rg_exc_code$write_1__SEL_3: rg_exc_code$D_IN = 4'd5;
    MUX_rg_error_during_refill$write_1__SEL_1:
	rg_exc_code$D_IN = access_exc_code__h2772;
    MUX_rg_exc_code$write_1__SEL_5:
	rg_exc_code$D_IN = MUX_rg_exc_code$write_1__VAL_5;
    MUX_rg_exc_code$write_1__SEL_6:
	rg_exc_code$D_IN = MUX_rg_exc_code$write_1__VAL_5;
    MUX_rg_exc_code$write_1__SEL_7:
	rg_exc_code$D_IN = MUX_rg_exc_code$write_1__VAL_5;
    MUX_rg_exc_code$write_1__SEL_8:
	rg_exc_code$D_IN = x1_avValue_exc_code__h6241;
    default: rg_exc_code$D_IN = 4'b1010 /* unspecified value */ ;
  endcase
  assign rg_exc_code$EN =
	     WILL_FIRE_RL_rl_probe_and_immed_rsp &&
	     rg_priv_6_ULE_0b1_7_AND_rg_satp_9_BITS_63_TO_6_ETC___d153 ||
	     WILL_FIRE_RL_rl_cache_refill_rsps_loop &&
	     master_xactor_f_rd_data$D_OUT[2:1] != 2'b0 ||
	     WILL_FIRE_RL_rl_io_read_rsp &&
	     master_xactor_f_rd_data$D_OUT[2:1] != 2'b0 ||
	     WILL_FIRE_RL_rl_io_AMO_read_rsp &&
	     master_xactor_f_rd_data$D_OUT[2:1] != 2'b0 ||
	     EN_req &&
	     NOT_req_f3_BITS_1_TO_0_433_EQ_0b0_434_435_AND__ETC___d1454 ||
	     WILL_FIRE_RL_rl_ptw_level_2 &&
	     NOT_master_xactor_f_rd_data_first__41_BIT_3_45_ETC___d972 ||
	     WILL_FIRE_RL_rl_ptw_level_1 &&
	     NOT_master_xactor_f_rd_data_first__41_BIT_3_45_ETC___d1034 ||
	     WILL_FIRE_RL_rl_ptw_level_0 &&
	     (!master_xactor_f_rd_data$D_OUT[3] ||
	      !master_xactor_f_rd_data$D_OUT[4] &&
	      master_xactor_f_rd_data$D_OUT[5] ||
	      !master_xactor_f_rd_data$D_OUT[6] &&
	      !master_xactor_f_rd_data$D_OUT[4] ||
	      master_xactor_f_rd_data$D_OUT[2:1] != 2'b0) ;

  // register rg_f3
  assign rg_f3$D_IN = req_f3 ;
  assign rg_f3$EN = EN_req ;

  // register rg_ld_val
  always@(MUX_dw_output_ld_val$wset_1__SEL_2 or
	  new_ld_val__h37807 or
	  MUX_rg_ld_val$write_1__SEL_2 or
	  MUX_rg_ld_val$write_1__VAL_2 or
	  WILL_FIRE_RL_rl_io_read_rsp or
	  ld_val__h35601 or WILL_FIRE_RL_rl_io_AMO_SC_req)
  begin
    case (1'b1) // synopsys parallel_case
      MUX_dw_output_ld_val$wset_1__SEL_2: rg_ld_val$D_IN = new_ld_val__h37807;
      MUX_rg_ld_val$write_1__SEL_2:
	  rg_ld_val$D_IN = MUX_rg_ld_val$write_1__VAL_2;
      WILL_FIRE_RL_rl_io_read_rsp: rg_ld_val$D_IN = ld_val__h35601;
      WILL_FIRE_RL_rl_io_AMO_SC_req: rg_ld_val$D_IN = 64'd1;
      default: rg_ld_val$D_IN = 64'hAAAAAAAAAAAAAAAA /* unspecified value */ ;
    endcase
  end
  assign rg_ld_val$EN =
	     WILL_FIRE_RL_rl_io_AMO_read_rsp &&
	     master_xactor_f_rd_data$D_OUT[2:1] == 2'b0 ||
	     WILL_FIRE_RL_rl_probe_and_immed_rsp &&
	     NOT_rg_priv_6_ULE_0b1_7_8_OR_NOT_rg_satp_9_BIT_ETC___d711 ||
	     WILL_FIRE_RL_rl_io_read_rsp ||
	     WILL_FIRE_RL_rl_io_AMO_SC_req ;

  // register rg_lower_word32
  assign rg_lower_word32$D_IN = 32'h0 ;
  assign rg_lower_word32$EN = 1'b0 ;

  // register rg_lower_word32_full
  assign rg_lower_word32_full$D_IN = 1'd0 ;
  assign rg_lower_word32_full$EN =
	     WILL_FIRE_RL_rl_start_cache_refill ||
	     WILL_FIRE_RL_rl_start_reset ;

  // register rg_lrsc_pa
  assign rg_lrsc_pa$D_IN = soc_map$m_is_mem_addr_addr ;
  assign rg_lrsc_pa$EN =
	     WILL_FIRE_RL_rl_probe_and_immed_rsp &&
	     (!rg_priv_6_ULE_0b1___d87 || rg_satp[63:60] != 4'd8 ||
	      tlb$lookup[130]) &&
	     NOT_rg_priv_6_ULE_0b1_7_8_OR_NOT_rg_satp_9_BIT_ETC___d683 ;

  // register rg_lrsc_valid
  assign rg_lrsc_valid$D_IN =
	     MUX_rg_lrsc_valid$write_1__SEL_2 &&
	     rg_op_13_EQ_0_14_OR_rg_op_13_EQ_2_16_AND_rg_am_ETC___d503 ;
  assign rg_lrsc_valid$EN =
	     WILL_FIRE_RL_rl_io_read_req && rg_op == 2'd2 &&
	     rg_amo_funct7[6:2] == 5'b00010 ||
	     WILL_FIRE_RL_rl_probe_and_immed_rsp &&
	     NOT_rg_priv_6_ULE_0b1_7_8_OR_NOT_rg_satp_9_BIT_ETC___d502 ||
	     WILL_FIRE_RL_rl_start_reset ;

  // register rg_mstatus_MXR
  assign rg_mstatus_MXR$D_IN = req_mstatus_MXR ;
  assign rg_mstatus_MXR$EN = EN_req ;

  // register rg_op
  assign rg_op$D_IN = req_op ;
  assign rg_op$EN = EN_req ;

  // register rg_pa
  assign rg_pa$D_IN = EN_req ? req_addr : soc_map$m_is_mem_addr_addr ;
  assign rg_pa$EN =
	     WILL_FIRE_RL_rl_probe_and_immed_rsp &&
	     NOT_rg_priv_6_ULE_0b1_7_8_OR_NOT_rg_satp_9_BIT_ETC___d465 ||
	     EN_req ;

  // register rg_priv
  assign rg_priv$D_IN = req_priv ;
  assign rg_priv$EN = EN_req ;

  // register rg_pte_pa
  always@(MUX_master_xactor_f_rd_addr$enq_1__SEL_1 or
	  lev_1_pte_pa__h29686 or
	  MUX_master_xactor_f_rd_addr$enq_1__SEL_2 or
	  lev_0_pte_pa__h30719 or
	  WILL_FIRE_RL_rl_start_tlb_refill or lev_2_pte_pa__h28789)
  begin
    case (1'b1) // synopsys parallel_case
      MUX_master_xactor_f_rd_addr$enq_1__SEL_1:
	  rg_pte_pa$D_IN = lev_1_pte_pa__h29686;
      MUX_master_xactor_f_rd_addr$enq_1__SEL_2:
	  rg_pte_pa$D_IN = lev_0_pte_pa__h30719;
      WILL_FIRE_RL_rl_start_tlb_refill: rg_pte_pa$D_IN = lev_2_pte_pa__h28789;
      default: rg_pte_pa$D_IN = 64'hAAAAAAAAAAAAAAAA /* unspecified value */ ;
    endcase
  end
  assign rg_pte_pa$EN =
	     WILL_FIRE_RL_rl_ptw_level_2 &&
	     master_xactor_f_rd_data$D_OUT[2:1] == 2'b0 &&
	     master_xactor_f_rd_data$D_OUT[3] &&
	     !master_xactor_f_rd_data$D_OUT[5] &&
	     !master_xactor_f_rd_data$D_OUT[6] &&
	     !master_xactor_f_rd_data$D_OUT[4] ||
	     WILL_FIRE_RL_rl_ptw_level_1 &&
	     master_xactor_f_rd_data$D_OUT[2:1] == 2'b0 &&
	     master_xactor_f_rd_data$D_OUT[3] &&
	     !master_xactor_f_rd_data$D_OUT[5] &&
	     !master_xactor_f_rd_data$D_OUT[6] &&
	     !master_xactor_f_rd_data$D_OUT[4] ||
	     WILL_FIRE_RL_rl_start_tlb_refill ;

  // register rg_satp
  assign rg_satp$D_IN = req_satp ;
  assign rg_satp$EN = EN_req ;

  // register rg_sstatus_SUM
  assign rg_sstatus_SUM$D_IN = req_sstatus_SUM ;
  assign rg_sstatus_SUM$EN = EN_req ;

  // register rg_st_amo_val
  assign rg_st_amo_val$D_IN = EN_req ? req_st_value : new_st_val__h25444 ;
  assign rg_st_amo_val$EN =
	     WILL_FIRE_RL_rl_probe_and_immed_rsp &&
	     NOT_rg_priv_6_ULE_0b1_7_8_OR_NOT_rg_satp_9_BIT_ETC___d925 ||
	     EN_req ;

  // register rg_state
  always@(EN_tlb_flush or
	  EN_req or
	  MUX_rg_state$write_1__VAL_2 or
	  WILL_FIRE_RL_rl_start_reset or
	  WILL_FIRE_RL_rl_io_AMO_read_rsp or
	  MUX_rg_state$write_1__VAL_4 or
	  WILL_FIRE_RL_rl_io_AMO_op_req or
	  WILL_FIRE_RL_rl_io_AMO_SC_req or
	  WILL_FIRE_RL_rl_io_write_req or
	  WILL_FIRE_RL_rl_io_read_rsp or
	  WILL_FIRE_RL_rl_io_read_req or
	  WILL_FIRE_RL_rl_rereq or
	  MUX_rg_state$write_1__SEL_11 or
	  MUX_rg_state$write_1__VAL_11 or
	  WILL_FIRE_RL_rl_start_cache_refill or
	  WILL_FIRE_RL_rl_ptw_level_0 or
	  MUX_rg_state$write_1__VAL_13 or
	  WILL_FIRE_RL_rl_ptw_level_1 or
	  MUX_rg_state$write_1__VAL_14 or
	  WILL_FIRE_RL_rl_ptw_level_2 or
	  MUX_rg_state$write_1__VAL_15 or
	  WILL_FIRE_RL_rl_start_tlb_refill or
	  MUX_rg_state$write_1__SEL_17 or
	  MUX_rg_state$write_1__VAL_17 or MUX_rg_state$write_1__SEL_18)
  case (1'b1)
    EN_tlb_flush: rg_state$D_IN = 5'd2;
    EN_req: rg_state$D_IN = MUX_rg_state$write_1__VAL_2;
    WILL_FIRE_RL_rl_start_reset: rg_state$D_IN = 5'd1;
    WILL_FIRE_RL_rl_io_AMO_read_rsp:
	rg_state$D_IN = MUX_rg_state$write_1__VAL_4;
    WILL_FIRE_RL_rl_io_AMO_op_req: rg_state$D_IN = 5'd16;
    WILL_FIRE_RL_rl_io_AMO_SC_req || WILL_FIRE_RL_rl_io_write_req:
	rg_state$D_IN = 5'd12;
    WILL_FIRE_RL_rl_io_read_rsp: rg_state$D_IN = MUX_rg_state$write_1__VAL_4;
    WILL_FIRE_RL_rl_io_read_req: rg_state$D_IN = 5'd14;
    WILL_FIRE_RL_rl_rereq: rg_state$D_IN = 5'd3;
    MUX_rg_state$write_1__SEL_11:
	rg_state$D_IN = MUX_rg_state$write_1__VAL_11;
    WILL_FIRE_RL_rl_start_cache_refill: rg_state$D_IN = 5'd10;
    WILL_FIRE_RL_rl_ptw_level_0: rg_state$D_IN = MUX_rg_state$write_1__VAL_13;
    WILL_FIRE_RL_rl_ptw_level_1: rg_state$D_IN = MUX_rg_state$write_1__VAL_14;
    WILL_FIRE_RL_rl_ptw_level_2: rg_state$D_IN = MUX_rg_state$write_1__VAL_15;
    WILL_FIRE_RL_rl_start_tlb_refill: rg_state$D_IN = 5'd6;
    MUX_rg_state$write_1__SEL_17:
	rg_state$D_IN = MUX_rg_state$write_1__VAL_17;
    MUX_rg_state$write_1__SEL_18: rg_state$D_IN = 5'd2;
    default: rg_state$D_IN = 5'b01010 /* unspecified value */ ;
  endcase
  assign rg_state$EN =
	     WILL_FIRE_RL_rl_reset && rg_cset_in_cache == 6'd63 ||
	     WILL_FIRE_RL_rl_cache_refill_rsps_loop &&
	     rg_cset_cword_in_cache[2:0] == 3'd7 ||
	     WILL_FIRE_RL_rl_probe_and_immed_rsp &&
	     rg_priv_6_ULE_0b1_7_AND_rg_satp_9_BITS_63_TO_6_ETC___d440 ||
	     WILL_FIRE_RL_rl_io_read_rsp ||
	     WILL_FIRE_RL_rl_io_AMO_read_rsp ||
	     WILL_FIRE_RL_rl_ptw_level_2 ||
	     WILL_FIRE_RL_rl_ptw_level_1 ||
	     WILL_FIRE_RL_rl_ptw_level_0 ||
	     EN_req ||
	     WILL_FIRE_RL_rl_start_reset ||
	     EN_tlb_flush ||
	     WILL_FIRE_RL_rl_rereq ||
	     WILL_FIRE_RL_rl_start_tlb_refill ||
	     WILL_FIRE_RL_rl_start_cache_refill ||
	     WILL_FIRE_RL_rl_io_AMO_SC_req ||
	     WILL_FIRE_RL_rl_io_write_req ||
	     WILL_FIRE_RL_rl_io_read_req ||
	     WILL_FIRE_RL_rl_io_AMO_op_req ;

  // register rg_victim_way
  assign rg_victim_way$D_IN = tmp__h32031[0] ;
  assign rg_victim_way$EN = WILL_FIRE_RL_rl_start_cache_refill ;

  // register rg_wr_rsp_err
  assign rg_wr_rsp_err$D_IN = 1'd1 ;
  assign rg_wr_rsp_err$EN =
	     WILL_FIRE_RL_rl_discard_write_rsp &&
	     master_xactor_f_wr_resp$D_OUT[1:0] != 2'b0 ;

  // submodule f_fabric_write_reqs
  always@(MUX_dw_output_ld_val$wset_1__SEL_2 or
	  MUX_f_fabric_write_reqs$enq_1__VAL_1 or
	  MUX_f_fabric_write_reqs$enq_1__SEL_2 or
	  MUX_f_fabric_write_reqs$enq_1__VAL_2 or
	  WILL_FIRE_RL_rl_writeback_updated_PTE or
	  MUX_f_fabric_write_reqs$enq_1__VAL_3 or
	  WILL_FIRE_RL_rl_io_write_req or
	  MUX_f_fabric_write_reqs$enq_1__VAL_4)
  begin
    case (1'b1) // synopsys parallel_case
      MUX_dw_output_ld_val$wset_1__SEL_2:
	  f_fabric_write_reqs$D_IN = MUX_f_fabric_write_reqs$enq_1__VAL_1;
      MUX_f_fabric_write_reqs$enq_1__SEL_2:
	  f_fabric_write_reqs$D_IN = MUX_f_fabric_write_reqs$enq_1__VAL_2;
      WILL_FIRE_RL_rl_writeback_updated_PTE:
	  f_fabric_write_reqs$D_IN = MUX_f_fabric_write_reqs$enq_1__VAL_3;
      WILL_FIRE_RL_rl_io_write_req:
	  f_fabric_write_reqs$D_IN = MUX_f_fabric_write_reqs$enq_1__VAL_4;
      default: f_fabric_write_reqs$D_IN =
		   131'h2AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA /* unspecified value */ ;
    endcase
  end
  assign f_fabric_write_reqs$ENQ =
	     WILL_FIRE_RL_rl_io_AMO_read_rsp &&
	     master_xactor_f_rd_data$D_OUT[2:1] == 2'b0 ||
	     WILL_FIRE_RL_rl_probe_and_immed_rsp &&
	     NOT_rg_priv_6_ULE_0b1_7_8_OR_NOT_rg_satp_9_BIT_ETC___d855 ||
	     WILL_FIRE_RL_rl_writeback_updated_PTE ||
	     WILL_FIRE_RL_rl_io_write_req ;
  assign f_fabric_write_reqs$DEQ = CAN_FIRE_RL_rl_fabric_send_write_req ;
  assign f_fabric_write_reqs$CLR = 1'b0 ;

  // submodule f_pte_writebacks
  assign f_pte_writebacks$D_IN = { tlb$lookup[63:0], value__h7066 } ;
  assign f_pte_writebacks$ENQ = MUX_tlb$insert_1__SEL_1 ;
  assign f_pte_writebacks$DEQ = WILL_FIRE_RL_rl_writeback_updated_PTE ;
  assign f_pte_writebacks$CLR = 1'b0 ;

  // submodule f_reset_reqs
  assign f_reset_reqs$D_IN = !EN_server_reset_request_put ;
  assign f_reset_reqs$ENQ =
	     EN_server_reset_request_put || EN_server_flush_request_put ;
  assign f_reset_reqs$DEQ =
	     WILL_FIRE_RL_rl_reset && rg_cset_in_cache == 6'd63 ;
  assign f_reset_reqs$CLR = 1'b0 ;

  // submodule f_reset_rsps
  assign f_reset_rsps$D_IN = f_reset_reqs$D_OUT ;
  assign f_reset_rsps$ENQ =
	     WILL_FIRE_RL_rl_reset && rg_cset_in_cache == 6'd63 ;
  assign f_reset_rsps$DEQ =
	     EN_server_flush_response_get || EN_server_reset_response_get ;
  assign f_reset_rsps$CLR = 1'b0 ;

  // submodule master_xactor_f_rd_addr
  always@(MUX_master_xactor_f_rd_addr$enq_1__SEL_1 or
	  MUX_master_xactor_f_rd_addr$enq_1__VAL_1 or
	  MUX_master_xactor_f_rd_addr$enq_1__SEL_2 or
	  MUX_master_xactor_f_rd_addr$enq_1__VAL_2 or
	  MUX_master_xactor_f_rd_addr$enq_1__SEL_3 or
	  MUX_master_xactor_f_rd_addr$enq_1__VAL_3 or
	  WILL_FIRE_RL_rl_start_tlb_refill or
	  MUX_master_xactor_f_rd_addr$enq_1__VAL_4 or
	  WILL_FIRE_RL_rl_start_cache_refill or
	  MUX_master_xactor_f_rd_addr$enq_1__VAL_5)
  begin
    case (1'b1) // synopsys parallel_case
      MUX_master_xactor_f_rd_addr$enq_1__SEL_1:
	  master_xactor_f_rd_addr$D_IN =
	      MUX_master_xactor_f_rd_addr$enq_1__VAL_1;
      MUX_master_xactor_f_rd_addr$enq_1__SEL_2:
	  master_xactor_f_rd_addr$D_IN =
	      MUX_master_xactor_f_rd_addr$enq_1__VAL_2;
      MUX_master_xactor_f_rd_addr$enq_1__SEL_3:
	  master_xactor_f_rd_addr$D_IN =
	      MUX_master_xactor_f_rd_addr$enq_1__VAL_3;
      WILL_FIRE_RL_rl_start_tlb_refill:
	  master_xactor_f_rd_addr$D_IN =
	      MUX_master_xactor_f_rd_addr$enq_1__VAL_4;
      WILL_FIRE_RL_rl_start_cache_refill:
	  master_xactor_f_rd_addr$D_IN =
	      MUX_master_xactor_f_rd_addr$enq_1__VAL_5;
      default: master_xactor_f_rd_addr$D_IN =
		   97'h0AAAAAAAAAAAAAAAAAAAAAAAA /* unspecified value */ ;
    endcase
  end
  assign master_xactor_f_rd_addr$ENQ =
	     WILL_FIRE_RL_rl_ptw_level_2 &&
	     master_xactor_f_rd_data$D_OUT[2:1] == 2'b0 &&
	     master_xactor_f_rd_data$D_OUT[3] &&
	     !master_xactor_f_rd_data$D_OUT[5] &&
	     !master_xactor_f_rd_data$D_OUT[6] &&
	     !master_xactor_f_rd_data$D_OUT[4] ||
	     WILL_FIRE_RL_rl_ptw_level_1 &&
	     master_xactor_f_rd_data$D_OUT[2:1] == 2'b0 &&
	     master_xactor_f_rd_data$D_OUT[3] &&
	     !master_xactor_f_rd_data$D_OUT[5] &&
	     !master_xactor_f_rd_data$D_OUT[6] &&
	     !master_xactor_f_rd_data$D_OUT[4] ||
	     WILL_FIRE_RL_rl_io_AMO_op_req ||
	     WILL_FIRE_RL_rl_io_read_req ||
	     WILL_FIRE_RL_rl_start_tlb_refill ||
	     WILL_FIRE_RL_rl_start_cache_refill ;
  assign master_xactor_f_rd_addr$DEQ =
	     master_xactor_f_rd_addr$EMPTY_N && mem_master_arready ;
  assign master_xactor_f_rd_addr$CLR =
	     WILL_FIRE_RL_rl_start_reset && !f_reset_reqs$D_OUT ;

  // submodule master_xactor_f_rd_data
  assign master_xactor_f_rd_data$D_IN =
	     { mem_master_rid,
	       mem_master_rdata,
	       mem_master_rresp,
	       mem_master_rlast } ;
  assign master_xactor_f_rd_data$ENQ =
	     mem_master_rvalid && master_xactor_f_rd_data$FULL_N ;
  assign master_xactor_f_rd_data$DEQ =
	     WILL_FIRE_RL_rl_io_read_rsp ||
	     WILL_FIRE_RL_rl_cache_refill_rsps_loop ||
	     WILL_FIRE_RL_rl_ptw_level_0 ||
	     WILL_FIRE_RL_rl_ptw_level_1 ||
	     WILL_FIRE_RL_rl_ptw_level_2 ||
	     WILL_FIRE_RL_rl_io_AMO_read_rsp ;
  assign master_xactor_f_rd_data$CLR =
	     WILL_FIRE_RL_rl_start_reset && !f_reset_reqs$D_OUT ;

  // submodule master_xactor_f_wr_addr
  assign master_xactor_f_wr_addr$D_IN =
	     { 4'd0,
	       f_fabric_write_reqs$D_OUT[127:64],
	       8'd0,
	       x__h3037,
	       18'd65536 } ;
  assign master_xactor_f_wr_addr$ENQ =
	     NOT_ctr_wr_rsps_pending_crg_port0__read_EQ_15__ETC___d9 &&
	     rg_ddr4_ready ;
  assign master_xactor_f_wr_addr$DEQ =
	     master_xactor_f_wr_addr$EMPTY_N && mem_master_awready ;
  assign master_xactor_f_wr_addr$CLR =
	     WILL_FIRE_RL_rl_start_reset && !f_reset_reqs$D_OUT ;

  // submodule master_xactor_f_wr_data
  assign master_xactor_f_wr_data$D_IN =
	     { mem_req_wr_data_wdata__h3221,
	       mem_req_wr_data_wstrb__h3222,
	       1'd1 } ;
  assign master_xactor_f_wr_data$ENQ =
	     NOT_ctr_wr_rsps_pending_crg_port0__read_EQ_15__ETC___d9 &&
	     rg_ddr4_ready ;
  assign master_xactor_f_wr_data$DEQ =
	     master_xactor_f_wr_data$EMPTY_N && mem_master_wready ;
  assign master_xactor_f_wr_data$CLR =
	     WILL_FIRE_RL_rl_start_reset && !f_reset_reqs$D_OUT ;

  // submodule master_xactor_f_wr_resp
  assign master_xactor_f_wr_resp$D_IN = { mem_master_bid, mem_master_bresp } ;
  assign master_xactor_f_wr_resp$ENQ =
	     mem_master_bvalid && master_xactor_f_wr_resp$FULL_N ;
  assign master_xactor_f_wr_resp$DEQ =
	     b__h28690 != 4'd0 && master_xactor_f_wr_resp$EMPTY_N ;
  assign master_xactor_f_wr_resp$CLR =
	     WILL_FIRE_RL_rl_start_reset && !f_reset_reqs$D_OUT ;

  // submodule ram_cword_set
  assign ram_cword_set$ADDRA =
	     MUX_ram_cword_set$a_put_1__SEL_1 ?
	       rg_cset_cword_in_cache :
	       rg_addr[11:3] ;
  always@(MUX_ram_cword_set$b_put_1__SEL_1 or
	  req_addr or
	  MUX_ram_cword_set$b_put_1__SEL_2 or
	  MUX_ram_cword_set$b_put_2__VAL_2 or
	  WILL_FIRE_RL_rl_rereq or
	  rg_addr or
	  WILL_FIRE_RL_rl_start_cache_refill or
	  MUX_ram_cword_set$b_put_2__VAL_4)
  begin
    case (1'b1) // synopsys parallel_case
      MUX_ram_cword_set$b_put_1__SEL_1: ram_cword_set$ADDRB = req_addr[11:3];
      MUX_ram_cword_set$b_put_1__SEL_2:
	  ram_cword_set$ADDRB = MUX_ram_cword_set$b_put_2__VAL_2;
      WILL_FIRE_RL_rl_rereq: ram_cword_set$ADDRB = rg_addr[11:3];
      WILL_FIRE_RL_rl_start_cache_refill:
	  ram_cword_set$ADDRB = MUX_ram_cword_set$b_put_2__VAL_4;
      default: ram_cword_set$ADDRB = 9'b010101010 /* unspecified value */ ;
    endcase
  end
  assign ram_cword_set$DIA =
	     MUX_ram_cword_set$a_put_1__SEL_1 ?
	       MUX_ram_cword_set$a_put_3__VAL_1 :
	       MUX_ram_cword_set$a_put_3__VAL_2 ;
  always@(MUX_ram_cword_set$b_put_1__SEL_1 or
	  MUX_ram_cword_set$b_put_1__SEL_2 or
	  WILL_FIRE_RL_rl_rereq or WILL_FIRE_RL_rl_start_cache_refill)
  begin
    case (1'b1) // synopsys parallel_case
      MUX_ram_cword_set$b_put_1__SEL_1:
	  ram_cword_set$DIB =
	      128'hAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA /* unspecified value */ ;
      MUX_ram_cword_set$b_put_1__SEL_2:
	  ram_cword_set$DIB =
	      128'hAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA /* unspecified value */ ;
      WILL_FIRE_RL_rl_rereq:
	  ram_cword_set$DIB =
	      128'hAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA /* unspecified value */ ;
      WILL_FIRE_RL_rl_start_cache_refill:
	  ram_cword_set$DIB =
	      128'hAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA /* unspecified value */ ;
      default: ram_cword_set$DIB =
		   128'hAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA /* unspecified value */ ;
    endcase
  end
  assign ram_cword_set$WEA = 1'd1 ;
  assign ram_cword_set$WEB = 1'd0 ;
  assign ram_cword_set$ENA =
	     WILL_FIRE_RL_rl_cache_refill_rsps_loop &&
	     master_xactor_f_rd_data$D_OUT[2:1] == 2'b0 ||
	     WILL_FIRE_RL_rl_probe_and_immed_rsp &&
	     NOT_rg_priv_6_ULE_0b1_7_8_OR_NOT_rg_satp_9_BIT_ETC___d724 ;
  assign ram_cword_set$ENB =
	     EN_req &&
	     req_f3_BITS_1_TO_0_433_EQ_0b0_434_OR_req_f3_BI_ETC___d1463 ||
	     WILL_FIRE_RL_rl_cache_refill_rsps_loop &&
	     rg_cset_cword_in_cache[2:0] != 3'd7 ||
	     WILL_FIRE_RL_rl_rereq ||
	     WILL_FIRE_RL_rl_start_cache_refill ;

  // submodule ram_state_and_ctag_cset
  assign ram_state_and_ctag_cset$ADDRA =
	     MUX_ram_state_and_ctag_cset$a_put_1__SEL_1 ?
	       rg_addr[11:6] :
	       rg_cset_in_cache ;
  assign ram_state_and_ctag_cset$ADDRB =
	     MUX_ram_cword_set$b_put_1__SEL_1 ?
	       req_addr[11:6] :
	       rg_addr[11:6] ;
  assign ram_state_and_ctag_cset$DIA =
	     MUX_ram_state_and_ctag_cset$a_put_1__SEL_1 ?
	       MUX_ram_state_and_ctag_cset$a_put_3__VAL_1 :
	       106'h15555555555554AAAAAAAAAAAAA ;
  assign ram_state_and_ctag_cset$DIB =
	     MUX_ram_cword_set$b_put_1__SEL_1 ?
	       106'h2AAAAAAAAAAAAAAAAAAAAAAAAAA /* unspecified value */  :
	       106'h2AAAAAAAAAAAAAAAAAAAAAAAAAA /* unspecified value */  ;
  assign ram_state_and_ctag_cset$WEA = 1'd1 ;
  assign ram_state_and_ctag_cset$WEB = 1'd0 ;
  assign ram_state_and_ctag_cset$ENA =
	     WILL_FIRE_RL_rl_cache_refill_rsps_loop &&
	     rg_cset_cword_in_cache[2:0] == 3'd0 &&
	     master_xactor_f_rd_data$D_OUT[2:1] == 2'b0 ||
	     WILL_FIRE_RL_rl_reset ;
  assign ram_state_and_ctag_cset$ENB =
	     EN_req &&
	     req_f3_BITS_1_TO_0_433_EQ_0b0_434_OR_req_f3_BI_ETC___d1463 ||
	     WILL_FIRE_RL_rl_rereq ;

  // submodule soc_map
  assign soc_map$m_is_IO_addr_addr = 64'h0 ;
  assign soc_map$m_is_mem_addr_addr =
	     (rg_priv_6_ULE_0b1___d87 && rg_satp[63:60] == 4'd8) ?
	       _theResult___snd_fst__h6331 :
	       rg_addr ;
  assign soc_map$m_is_near_mem_IO_addr_addr = 64'h0 ;

  // submodule tlb
  assign tlb$insert_asid = rg_satp[59:44] ;
  always@(MUX_tlb$insert_1__SEL_1 or
	  tlb$lookup or
	  MUX_tlb$insert_1__SEL_2 or
	  MUX_tlb$insert_1__SEL_3 or MUX_tlb$insert_2__SEL_4)
  begin
    case (1'b1) // synopsys parallel_case
      MUX_tlb$insert_1__SEL_1: tlb$insert_level = tlb$lookup[65:64];
      MUX_tlb$insert_1__SEL_2: tlb$insert_level = 2'd2;
      MUX_tlb$insert_1__SEL_3: tlb$insert_level = 2'd1;
      MUX_tlb$insert_2__SEL_4: tlb$insert_level = 2'd0;
      default: tlb$insert_level = 2'b10 /* unspecified value */ ;
    endcase
  end
  assign tlb$insert_pte =
	     (MUX_tlb$insert_1__SEL_2 || MUX_tlb$insert_1__SEL_3 ||
	      MUX_tlb$insert_2__SEL_4) ?
	       master_xactor_f_rd_data$D_OUT[66:3] :
	       value__h7066 ;
  assign tlb$insert_pte_pa =
	     MUX_tlb$insert_1__SEL_1 ? tlb$lookup[63:0] : rg_pte_pa ;
  assign tlb$insert_vpn = rg_addr[38:12] ;
  assign tlb$lookup_asid = rg_satp[59:44] ;
  assign tlb$lookup_vpn = rg_addr[38:12] ;
  assign tlb$EN_flush = WILL_FIRE_RL_rl_start_reset || EN_tlb_flush ;
  assign tlb$EN_insert =
	     WILL_FIRE_RL_rl_probe_and_immed_rsp &&
	     rg_priv_6_ULE_0b1_7_AND_rg_satp_9_BITS_63_TO_6_ETC___d422 ||
	     WILL_FIRE_RL_rl_ptw_level_2 &&
	     master_xactor_f_rd_data_first__41_BITS_2_TO_1__ETC___d1015 ||
	     WILL_FIRE_RL_rl_ptw_level_1 &&
	     master_xactor_f_rd_data_first__41_BITS_2_TO_1__ETC___d1050 ||
	     WILL_FIRE_RL_rl_ptw_level_0 &&
	     master_xactor_f_rd_data$D_OUT[2:1] == 2'b0 &&
	     master_xactor_f_rd_data$D_OUT[3] &&
	     (master_xactor_f_rd_data$D_OUT[4] ||
	      !master_xactor_f_rd_data$D_OUT[5]) &&
	     (master_xactor_f_rd_data$D_OUT[6] ||
	      master_xactor_f_rd_data$D_OUT[4]) ;

  // remaining internal signals
  assign IF_IF_rg_priv_6_ULE_0b1_7_AND_rg_satp_9_BITS_6_ETC___d334 =
	     (x1_avValue_pa__h6240[2:0] == 3'h0) ?
	       CASE_rg_amo_funct7_BITS_6_TO_2_0b0_IF_rg_f3_17_ETC__q29 :
	       NOT_IF_rg_priv_6_ULE_0b1_7_AND_rg_satp_9_BITS__ETC___d333 ;
  assign IF_NOT_ram_state_and_ctag_cset_b_read__00_BIT__ETC___d441 =
	     ((!ram_state_and_ctag_cset$DOB[52] ||
	       !ram_state_and_ctag_cset_b_read__00_BITS_51_TO__ETC___d205) &&
	      (!ram_state_and_ctag_cset$DOB[105] ||
	       !ram_state_and_ctag_cset_b_read__00_BITS_104_TO_ETC___d211)) ?
	       5'd9 :
	       5'd12 ;
  assign IF_NOT_ram_state_and_ctag_cset_b_read__00_BIT__ETC___d779 =
	     (!ram_state_and_ctag_cset$DOB[105] ||
	      !ram_state_and_ctag_cset_b_read__00_BITS_104_TO_ETC___d211) ?
	       n__h22674 :
	       ram_cword_set$DOB[63:0] ;
  assign IF_NOT_ram_state_and_ctag_cset_b_read__00_BIT__ETC___d847 =
	     (!ram_state_and_ctag_cset$DOB[105] ||
	      !ram_state_and_ctag_cset_b_read__00_BITS_104_TO_ETC___d211) ?
	       n__h25608 :
	       ram_cword_set$DOB[63:0] ;
  assign IF_ram_state_and_ctag_cset_b_read__00_BIT_105__ETC___d778 =
	     (ram_state_and_ctag_cset$DOB[105] &&
	      ram_state_and_ctag_cset_b_read__00_BITS_104_TO_ETC___d211) ?
	       n__h22674 :
	       ram_cword_set$DOB[127:64] ;
  assign IF_ram_state_and_ctag_cset_b_read__00_BIT_105__ETC___d846 =
	     (ram_state_and_ctag_cset$DOB[105] &&
	      ram_state_and_ctag_cset_b_read__00_BITS_104_TO_ETC___d211) ?
	       n__h25608 :
	       ram_cword_set$DOB[127:64] ;
  assign IF_rg_addr_7_BITS_2_TO_0_21_EQ_0x0_22_THEN_1_E_ETC___d662 =
	     (rg_addr[2:0] == 3'h0) ? 64'd1 : 64'd0 ;
  assign IF_rg_addr_7_BITS_2_TO_0_21_EQ_0x0_22_THEN_IF__ETC___d1348 =
	     (rg_addr[2:0] == 3'h0) ? ld_val__h35601 : 64'd0 ;
  assign IF_rg_addr_7_BITS_2_TO_0_21_EQ_0x0_22_THEN_NOT_ETC___d255 =
	     (rg_addr[2:0] == 3'h0) ?
	       NOT_ram_state_and_ctag_cset_b_read__00_BIT_52__ETC___d235 &&
	       NOT_ram_state_and_ctag_cset_b_read__00_BIT_105_ETC___d236 :
	       rg_addr[2:0] != 3'h4 ||
	       NOT_ram_state_and_ctag_cset_b_read__00_BIT_52__ETC___d235 &&
	       NOT_ram_state_and_ctag_cset_b_read__00_BIT_105_ETC___d236 ;
  assign IF_rg_addr_7_BITS_2_TO_0_21_EQ_0x0_22_THEN_ram_ETC___d647 =
	     (rg_addr[2:0] == 3'h0) ? word64__h7759 : 64'd0 ;
  assign IF_rg_f3_17_EQ_0b0_18_THEN_IF_rg_addr_7_BITS_2_ETC__q32 =
	     IF_rg_f3_17_EQ_0b0_18_THEN_IF_rg_addr_7_BITS_2_ETC___d654[31:0] ;
  assign IF_rg_f3_17_EQ_0b10_50_THEN_SEXT_rg_st_amo_val_ETC___d784 =
	     (rg_f3 == 3'b010) ?
	       { {32{rg_st_amo_val_BITS_31_TO_0__q33[31]}},
		 rg_st_amo_val_BITS_31_TO_0__q33 } :
	       rg_st_amo_val ;
  assign IF_rg_op_13_EQ_0_14_OR_rg_op_13_EQ_2_16_AND_rg_ETC___d348 =
	     (rg_op == 2'd0 ||
	      rg_op == 2'd2 && rg_amo_funct7[6:2] == 5'b00010) ?
	       NOT_ram_state_and_ctag_cset_b_read__00_BIT_52__ETC___d265 :
	       IF_rg_op_13_EQ_1_66_OR_rg_op_13_EQ_2_16_AND_rg_ETC___d347 ;
  assign IF_rg_op_13_EQ_0_14_OR_rg_op_13_EQ_2_16_AND_rg_ETC___d443 =
	     (rg_op == 2'd0 ||
	      rg_op == 2'd2 && rg_amo_funct7[6:2] == 5'b00010) ?
	       5'd9 :
	       IF_rg_op_13_EQ_1_66_OR_rg_op_13_EQ_2_16_AND_rg_ETC___d442 ;
  assign IF_rg_op_13_EQ_1_66_OR_rg_op_13_EQ_2_16_AND_rg_ETC___d347 =
	     (rg_op == 2'd1 ||
	      rg_op == 2'd2 && rg_amo_funct7[6:2] == 5'b00011) ?
	       rg_op_13_EQ_2_16_AND_rg_amo_funct7_18_BITS_6_T_ETC___d287 :
	       NOT_ram_state_and_ctag_cset_b_read__00_BIT_52__ETC___d346 ;
  assign IF_rg_op_13_EQ_1_66_OR_rg_op_13_EQ_2_16_AND_rg_ETC___d442 =
	     (rg_op == 2'd1 ||
	      rg_op == 2'd2 && rg_amo_funct7[6:2] == 5'b00011) ?
	       5'd12 :
	       IF_NOT_ram_state_and_ctag_cset_b_read__00_BIT__ETC___d441 ;
  assign IF_rg_op_13_EQ_1_66_OR_rg_op_13_EQ_2_16_AND_rg_ETC___d856 =
	     (rg_op == 2'd1 ||
	      rg_op == 2'd2 && rg_amo_funct7[6:2] == 5'b00011) ?
	       rg_st_amo_val :
	       new_st_val__h25444 ;
  assign IF_rg_priv_6_ULE_0b1_7_AND_rg_satp_9_BITS_63_T_ETC___d445 =
	     rg_priv_6_ULE_0b1_7_AND_rg_satp_9_BITS_63_TO_6_ETC___d153 ?
	       5'd4 :
	       ((dmem_not_imem && !soc_map$m_is_mem_addr) ?
		  5'd13 :
		  IF_rg_op_13_EQ_0_14_OR_rg_op_13_EQ_2_16_AND_rg_ETC___d443) ;
  assign IF_rg_priv_6_ULE_0b1_7_AND_rg_satp_9_BITS_63_T_ETC___d485 =
	     x1_avValue_pa__h6240 == rg_lrsc_pa ;
  assign NOT_IF_rg_priv_6_ULE_0b1_7_AND_rg_satp_9_BITS__ETC___d323 =
	     x1_avValue_pa__h6240[2:0] != 3'h7 ||
	     CASE_rg_amo_funct7_BITS_6_TO_2_0b0_IF_rg_f3_17_ETC__q29 ;
  assign NOT_IF_rg_priv_6_ULE_0b1_7_AND_rg_satp_9_BITS__ETC___d329 =
	     x1_avValue_pa__h6240[2:0] != 3'h6 ||
	     CASE_rg_amo_funct7_BITS_6_TO_2_0b0_IF_rg_f3_17_ETC__q29 ;
  assign NOT_IF_rg_priv_6_ULE_0b1_7_AND_rg_satp_9_BITS__ETC___d333 =
	     x1_avValue_pa__h6240[2:0] != 3'h4 ||
	     CASE_rg_amo_funct7_BITS_6_TO_2_0b0_IF_rg_f3_17_ETC__q29 ;
  assign NOT_cfg_verbosity_read__1_ULE_2_106___d1107 = cfg_verbosity > 4'd2 ;
  assign NOT_cfg_verbosity_read__1_ULT_2_49___d450 = cfg_verbosity >= 4'd2 ;
  assign NOT_ctr_wr_rsps_pending_crg_port0__read_EQ_15__ETC___d9 =
	     ctr_wr_rsps_pending_crg != 4'd15 &&
	     f_fabric_write_reqs$EMPTY_N &&
	     master_xactor_f_wr_addr$FULL_N &&
	     master_xactor_f_wr_data$FULL_N ;
  assign NOT_dmem_not_imem_28_AND_rg_op_13_EQ_0_14_OR_r_ETC___d385 =
	     !dmem_not_imem &&
	     (rg_op == 2'd0 ||
	      rg_op == 2'd2 && rg_amo_funct7[6:2] == 5'b00010) &&
	     tlb$lookup[69] ;
  assign NOT_dmem_not_imem_28_OR_NOT_rg_op_13_EQ_0_14_1_ETC___d135 =
	     !dmem_not_imem ||
	     rg_op != 2'd0 &&
	     (rg_op != 2'd2 || rg_amo_funct7[6:2] != 5'b00010) ||
	     !tlb_lookup_rg_satp_9_BITS_59_TO_44_6_rg_addr_7_ETC___d133 ;
  assign NOT_dmem_not_imem_28_OR_soc_map_m_is_mem_addr__ETC___d479 =
	     (!dmem_not_imem || soc_map$m_is_mem_addr) &&
	     ram_state_and_ctag_cset$DOB[52] &&
	     ram_state_and_ctag_cset_b_read__00_BITS_51_TO__ETC___d205 &&
	     ram_state_and_ctag_cset$DOB[105] &&
	     ram_state_and_ctag_cset_b_read__00_BITS_104_TO_ETC___d211 ;
  assign NOT_dmem_not_imem_28_OR_soc_map_m_is_mem_addr__ETC___d675 =
	     (!dmem_not_imem || soc_map$m_is_mem_addr) &&
	     (rg_op == 2'd0 ||
	      rg_op == 2'd2 && rg_amo_funct7[6:2] == 5'b00010) &&
	     ram_state_and_ctag_cset_b_read__00_BIT_52_01_A_ETC___d673 ;
  assign NOT_dmem_not_imem_28_OR_soc_map_m_is_mem_addr__ETC___d687 =
	     (!dmem_not_imem || soc_map$m_is_mem_addr) && rg_op == 2'd2 &&
	     rg_amo_funct7[6:2] == 5'b00010 &&
	     ram_state_and_ctag_cset_b_read__00_BIT_52_01_A_ETC___d673 ;
  assign NOT_dmem_not_imem_28_OR_soc_map_m_is_mem_addr__ETC___d692 =
	     (!dmem_not_imem || soc_map$m_is_mem_addr) &&
	     (rg_op == 2'd0 ||
	      rg_op == 2'd2 && rg_amo_funct7[6:2] == 5'b00010) &&
	     NOT_ram_state_and_ctag_cset_b_read__00_BIT_52__ETC___d690 ;
  assign NOT_dmem_not_imem_28_OR_soc_map_m_is_mem_addr__ETC___d700 =
	     (!dmem_not_imem || soc_map$m_is_mem_addr) && rg_op == 2'd2 &&
	     rg_amo_funct7[6:2] == 5'b00010 &&
	     NOT_ram_state_and_ctag_cset_b_read__00_BIT_52__ETC___d697 ;
  assign NOT_dmem_not_imem_28_OR_soc_map_m_is_mem_addr__ETC___d709 =
	     (!dmem_not_imem || soc_map$m_is_mem_addr) && rg_op != 2'd0 &&
	     (rg_op != 2'd2 || rg_amo_funct7[6:2] != 5'b00010) &&
	     (rg_op == 2'd2 && rg_amo_funct7[6:2] == 5'b00011 ||
	      NOT_rg_op_13_EQ_1_66_93_AND_ram_state_and_ctag_ETC___d706) ;
  assign NOT_dmem_not_imem_28_OR_soc_map_m_is_mem_addr__ETC___d722 =
	     (!dmem_not_imem || soc_map$m_is_mem_addr) && rg_op != 2'd0 &&
	     (rg_op != 2'd2 || rg_amo_funct7[6:2] != 5'b00010) &&
	     rg_op_13_EQ_1_66_OR_rg_op_13_EQ_2_16_AND_rg_am_ETC___d720 ;
  assign NOT_dmem_not_imem_28_OR_soc_map_m_is_mem_addr__ETC___d859 =
	     (!dmem_not_imem || soc_map$m_is_mem_addr) && rg_op == 2'd1 &&
	     IF_rg_priv_6_ULE_0b1_7_AND_rg_satp_9_BITS_63_T_ETC___d485 &&
	     !cfg_verbosity_read__1_ULE_1___d42 ;
  assign NOT_dmem_not_imem_28_OR_soc_map_m_is_mem_addr__ETC___d877 =
	     (!dmem_not_imem || soc_map$m_is_mem_addr) && rg_op == 2'd2 &&
	     rg_amo_funct7[6:2] == 5'b00011 &&
	     !cfg_verbosity_read__1_ULE_1___d42 ;
  assign NOT_dmem_not_imem_28_OR_soc_map_m_is_mem_addr__ETC___d923 =
	     (!dmem_not_imem || soc_map$m_is_mem_addr) && rg_op != 2'd0 &&
	     (rg_op != 2'd2 || rg_amo_funct7[6:2] != 5'b00010) &&
	     NOT_rg_op_13_EQ_1_66_93_AND_NOT_rg_op_13_EQ_2__ETC___d719 ;
  assign NOT_master_xactor_f_rd_data_first__41_BITS_2_T_ETC___d1028 =
	     master_xactor_f_rd_data$D_OUT[2:1] != 2'b0 ||
	     !master_xactor_f_rd_data$D_OUT[3] ||
	     !master_xactor_f_rd_data$D_OUT[4] &&
	     master_xactor_f_rd_data$D_OUT[5] ||
	     ((!master_xactor_f_rd_data$D_OUT[6] &&
	       !master_xactor_f_rd_data$D_OUT[4]) ?
		master_xactor_f_rd_addr$FULL_N :
		master_xactor_f_rd_data$D_OUT[21:13] != 9'd0 ||
		tlb$RDY_insert) ;
  assign NOT_master_xactor_f_rd_data_first__41_BITS_2_T_ETC___d965 =
	     master_xactor_f_rd_data$D_OUT[2:1] != 2'b0 ||
	     !master_xactor_f_rd_data$D_OUT[3] ||
	     !master_xactor_f_rd_data$D_OUT[4] &&
	     master_xactor_f_rd_data$D_OUT[5] ||
	     ((!master_xactor_f_rd_data$D_OUT[6] &&
	       !master_xactor_f_rd_data$D_OUT[4]) ?
		master_xactor_f_rd_addr$FULL_N :
		master_xactor_f_rd_data$D_OUT[30:22] != 9'd0 ||
		master_xactor_f_rd_data$D_OUT[21:13] != 9'd0 ||
		tlb$RDY_insert) ;
  assign NOT_master_xactor_f_rd_data_first__41_BIT_3_45_ETC___d1034 =
	     !master_xactor_f_rd_data$D_OUT[3] ||
	     !master_xactor_f_rd_data$D_OUT[4] &&
	     master_xactor_f_rd_data$D_OUT[5] ||
	     (master_xactor_f_rd_data$D_OUT[6] ||
	      master_xactor_f_rd_data$D_OUT[4]) &&
	     master_xactor_f_rd_data$D_OUT[21:13] != 9'd0 ||
	     master_xactor_f_rd_data$D_OUT[2:1] != 2'b0 ;
  assign NOT_master_xactor_f_rd_data_first__41_BIT_3_45_ETC___d972 =
	     !master_xactor_f_rd_data$D_OUT[3] ||
	     !master_xactor_f_rd_data$D_OUT[4] &&
	     master_xactor_f_rd_data$D_OUT[5] ||
	     (master_xactor_f_rd_data$D_OUT[6] ||
	      master_xactor_f_rd_data$D_OUT[4]) &&
	     (master_xactor_f_rd_data$D_OUT[30:22] != 9'd0 ||
	      master_xactor_f_rd_data$D_OUT[21:13] != 9'd0) ||
	     master_xactor_f_rd_data$D_OUT[2:1] != 2'b0 ;
  assign NOT_ram_state_and_ctag_cset_b_read__00_BIT_105_ETC___d236 =
	     !ram_state_and_ctag_cset$DOB[105] || !rg_priv_6_ULE_0b1___d87 ||
	     rg_satp[63:60] != 4'd8 ||
	     tlb$RDY_lookup ;
  assign NOT_ram_state_and_ctag_cset_b_read__00_BIT_52__ETC___d235 =
	     !ram_state_and_ctag_cset$DOB[52] || !rg_priv_6_ULE_0b1___d87 ||
	     rg_satp[63:60] != 4'd8 ||
	     tlb$RDY_lookup ;
  assign NOT_ram_state_and_ctag_cset_b_read__00_BIT_52__ETC___d265 =
	     (!ram_state_and_ctag_cset$DOB[52] ||
	      !ram_state_and_ctag_cset_b_read__00_BITS_51_TO__ETC___d205) &&
	     (!ram_state_and_ctag_cset$DOB[105] ||
	      !ram_state_and_ctag_cset_b_read__00_BITS_104_TO_ETC___d211) ||
	     rg_op == 2'd2 && rg_amo_funct7[6:2] == 5'b00011 ||
	     IF_rg_f3_17_EQ_0b0_18_OR_rg_f3_17_EQ_0b100_19__ETC___d263 ;
  assign NOT_ram_state_and_ctag_cset_b_read__00_BIT_52__ETC___d285 =
	     (!ram_state_and_ctag_cset$DOB[52] ||
	      !ram_state_and_ctag_cset_b_read__00_BITS_51_TO__ETC___d205) &&
	     (!ram_state_and_ctag_cset$DOB[105] ||
	      !ram_state_and_ctag_cset_b_read__00_BITS_104_TO_ETC___d211) ||
	     (!ram_state_and_ctag_cset$DOB[105] ||
	      !ram_state_and_ctag_cset_b_read__00_BITS_104_TO_ETC___d211 ||
	      IF_rg_f3_17_EQ_0b0_18_OR_rg_f3_17_EQ_0b1_42_OR_ETC___d279) &&
	     (ram_state_and_ctag_cset$DOB[105] &&
	      ram_state_and_ctag_cset_b_read__00_BITS_104_TO_ETC___d211 ||
	      IF_rg_f3_17_EQ_0b0_18_OR_rg_f3_17_EQ_0b1_42_OR_ETC___d279) ;
  assign NOT_ram_state_and_ctag_cset_b_read__00_BIT_52__ETC___d346 =
	     (!ram_state_and_ctag_cset$DOB[52] ||
	      !ram_state_and_ctag_cset_b_read__00_BITS_51_TO__ETC___d205) &&
	     (!ram_state_and_ctag_cset$DOB[105] ||
	      !ram_state_and_ctag_cset_b_read__00_BITS_104_TO_ETC___d211) ||
	     f_fabric_write_reqs$FULL_N &&
	     rg_amo_funct7_18_BITS_6_TO_2_19_EQ_0b1_88_OR_I_ETC___d344 ;
  assign NOT_ram_state_and_ctag_cset_b_read__00_BIT_52__ETC___d487 =
	     (!ram_state_and_ctag_cset$DOB[52] ||
	      !ram_state_and_ctag_cset_b_read__00_BITS_51_TO__ETC___d205) &&
	     (!ram_state_and_ctag_cset$DOB[105] ||
	      !ram_state_and_ctag_cset_b_read__00_BITS_104_TO_ETC___d211) &&
	     rg_op == 2'd2 &&
	     rg_amo_funct7[6:2] == 5'b00010 &&
	     IF_rg_priv_6_ULE_0b1_7_AND_rg_satp_9_BITS_63_T_ETC___d485 ;
  assign NOT_ram_state_and_ctag_cset_b_read__00_BIT_52__ETC___d690 =
	     (!ram_state_and_ctag_cset$DOB[52] ||
	      !ram_state_and_ctag_cset_b_read__00_BITS_51_TO__ETC___d205) &&
	     (!ram_state_and_ctag_cset$DOB[105] ||
	      !ram_state_and_ctag_cset_b_read__00_BITS_104_TO_ETC___d211) &&
	     !cfg_verbosity_read__1_ULE_1___d42 ;
  assign NOT_ram_state_and_ctag_cset_b_read__00_BIT_52__ETC___d697 =
	     (!ram_state_and_ctag_cset$DOB[52] ||
	      !ram_state_and_ctag_cset_b_read__00_BITS_51_TO__ETC___d205) &&
	     (!ram_state_and_ctag_cset$DOB[105] ||
	      !ram_state_and_ctag_cset_b_read__00_BITS_104_TO_ETC___d211) &&
	     IF_rg_priv_6_ULE_0b1_7_AND_rg_satp_9_BITS_63_T_ETC___d485 &&
	     !cfg_verbosity_read__1_ULE_1___d42 ;
  assign NOT_req_f3_BITS_1_TO_0_433_EQ_0b0_434_435_AND__ETC___d1454 =
	     req_f3[1:0] != 2'b0 && (req_f3[1:0] != 2'b01 || req_addr[0]) &&
	     (req_f3[1:0] != 2'b10 || req_addr[1:0] != 2'b0) &&
	     (req_f3[1:0] != 2'b11 || req_addr[2:0] != 3'b0) ;
  assign NOT_rg_op_13_EQ_0_14_15_AND_NOT_rg_op_13_EQ_2__ETC___d436 =
	     rg_op != 2'd0 &&
	     (rg_op != 2'd2 || rg_amo_funct7[6:2] != 5'b00010) &&
	     (rg_op != 2'd2 || rg_amo_funct7[6:2] != 5'b00011 ||
	      rg_lrsc_valid &&
	      rg_lrsc_pa_70_EQ_IF_rg_priv_6_ULE_0b1_7_AND_rg_ETC___d271) ;
  assign NOT_rg_op_13_EQ_1_66_93_AND_NOT_rg_op_13_EQ_2__ETC___d719 =
	     rg_op != 2'd1 &&
	     (rg_op != 2'd2 || rg_amo_funct7[6:2] != 5'b00011) &&
	     (ram_state_and_ctag_cset$DOB[52] &&
	      ram_state_and_ctag_cset_b_read__00_BITS_51_TO__ETC___d205 ||
	      ram_state_and_ctag_cset$DOB[105] &&
	      ram_state_and_ctag_cset_b_read__00_BITS_104_TO_ETC___d211) ;
  assign NOT_rg_op_13_EQ_1_66_93_AND_ram_state_and_ctag_ETC___d706 =
	     rg_op != 2'd1 &&
	     (ram_state_and_ctag_cset$DOB[52] &&
	      ram_state_and_ctag_cset_b_read__00_BITS_51_TO__ETC___d205 ||
	      ram_state_and_ctag_cset$DOB[105] &&
	      ram_state_and_ctag_cset_b_read__00_BITS_104_TO_ETC___d211) ;
  assign NOT_rg_op_13_EQ_2_16_17_OR_NOT_rg_amo_funct7_1_ETC___d717 =
	     (rg_op != 2'd2 || rg_amo_funct7[6:2] != 5'b00011 ||
	      rg_lrsc_valid &&
	      rg_lrsc_pa_70_EQ_IF_rg_priv_6_ULE_0b1_7_AND_rg_ETC___d271) &&
	     (ram_state_and_ctag_cset$DOB[52] &&
	      ram_state_and_ctag_cset_b_read__00_BITS_51_TO__ETC___d205 ||
	      ram_state_and_ctag_cset$DOB[105] &&
	      ram_state_and_ctag_cset_b_read__00_BITS_104_TO_ETC___d211) ;
  assign NOT_rg_op_13_EQ_2_16_17_OR_NOT_rg_amo_funct7_1_ETC___d880 =
	     (rg_op != 2'd2 || rg_amo_funct7[6:2] != 5'b00011 ||
	      rg_lrsc_valid &&
	      rg_lrsc_pa_70_EQ_IF_rg_priv_6_ULE_0b1_7_AND_rg_ETC___d271) &&
	     ram_state_and_ctag_cset_b_read__00_BIT_52_01_A_ETC___d673 ;
  assign NOT_rg_op_13_EQ_2_16_17_OR_NOT_rg_amo_funct7_1_ETC___d886 =
	     (rg_op != 2'd2 || rg_amo_funct7[6:2] != 5'b00011 ||
	      rg_lrsc_valid &&
	      rg_lrsc_pa_70_EQ_IF_rg_priv_6_ULE_0b1_7_AND_rg_ETC___d271) &&
	     NOT_ram_state_and_ctag_cset_b_read__00_BIT_52__ETC___d690 ;
  assign NOT_rg_op_13_EQ_2_16_17_OR_NOT_rg_amo_funct7_1_ETC___d892 =
	     (rg_op != 2'd2 || rg_amo_funct7[6:2] != 5'b00011 ||
	      rg_lrsc_valid &&
	      rg_lrsc_pa_70_EQ_IF_rg_priv_6_ULE_0b1_7_AND_rg_ETC___d271) &&
	     !cfg_verbosity_read__1_ULE_1___d42 ;
  assign NOT_rg_priv_6_EQ_0b0_03_78_OR_tlb_lookup_rg_sa_ETC___d392 =
	     (rg_priv != 2'b0 || tlb$lookup[70]) &&
	     (rg_priv != 2'b01 || !tlb$lookup[70] || rg_sstatus_SUM) &&
	     (NOT_dmem_not_imem_28_AND_rg_op_13_EQ_0_14_OR_r_ETC___d385 ||
	      dmem_not_imem_AND_rg_op_13_EQ_0_14_OR_rg_op_13_ETC___d387 ||
	      dmem_not_imem && rg_op != 2'd0 &&
	      (rg_op != 2'd2 || rg_amo_funct7[6:2] != 5'b00010) &&
	      tlb$lookup[68]) ;
  assign NOT_rg_priv_6_EQ_0b0_03_78_OR_tlb_lookup_rg_sa_ETC___d415 =
	     (rg_priv != 2'b0 || tlb$lookup[70]) &&
	     (rg_priv != 2'b01 || !tlb$lookup[70] || rg_sstatus_SUM) &&
	     dmem_not_imem &&
	     tlb$lookup[68] ;
  assign NOT_rg_priv_6_EQ_0b0_03_78_OR_tlb_lookup_rg_sa_ETC___d453 =
	     (rg_priv != 2'b0 || tlb$lookup[70]) &&
	     (rg_priv != 2'b01 || !tlb$lookup[70] || rg_sstatus_SUM) &&
	     tlb$lookup[72] &&
	     !pte___2__h6741[7] &&
	     rg_op != 2'd0 &&
	     (rg_op != 2'd2 || rg_amo_funct7[6:2] != 5'b00010) ;
  assign NOT_rg_priv_6_EQ_0b0_03_78_OR_tlb_lookup_rg_sa_ETC___d669 =
	     (rg_priv != 2'b0 || tlb$lookup[70]) &&
	     (rg_priv != 2'b01 || !tlb$lookup[70] || rg_sstatus_SUM) &&
	     (!dmem_not_imem && tlb$lookup[69] ||
	      dmem_not_imem &&
	      tlb_lookup_rg_satp_9_BITS_59_TO_44_6_rg_addr_7_ETC___d133) ;
  assign NOT_rg_priv_6_ULE_0b1_7_8_OR_NOT_rg_satp_9_BIT_ETC___d169 =
	     !rg_priv_6_ULE_0b1___d87 || rg_satp[63:60] != 4'd8 ||
	     !tlb$lookup[130] ||
	     rg_priv_6_EQ_0b0_03_AND_NOT_tlb_lookup_rg_satp_ETC___d157 ||
	     NOT_tlb_lookup_rg_satp_9_BITS_59_TO_44_6_rg_ad_ETC___d166 ;
  assign NOT_rg_priv_6_ULE_0b1_7_8_OR_NOT_rg_satp_9_BIT_ETC___d350 =
	     (NOT_rg_priv_6_ULE_0b1_7_8_OR_NOT_rg_satp_9_BIT_ETC___d169 ||
	      tlb$RDY_insert && tlb$RDY_lookup && f_pte_writebacks$FULL_N) &&
	     (dmem_not_imem && !soc_map$m_is_mem_addr ||
	      IF_rg_op_13_EQ_0_14_OR_rg_op_13_EQ_2_16_AND_rg_ETC___d348) ;
  assign NOT_rg_priv_6_ULE_0b1_7_8_OR_NOT_rg_satp_9_BIT_ETC___d397 =
	     !rg_priv_6_ULE_0b1___d87 || rg_satp[63:60] != 4'd8 ||
	     tlb$lookup[130] &&
	     NOT_rg_priv_6_EQ_0b0_03_78_OR_tlb_lookup_rg_sa_ETC___d392 &&
	     tlb_lookup_rg_satp_9_BITS_59_TO_44_6_rg_addr_7_ETC___d394 ;
  assign NOT_rg_priv_6_ULE_0b1_7_8_OR_NOT_rg_satp_9_BIT_ETC___d412 =
	     !rg_priv_6_ULE_0b1___d87 || rg_satp[63:60] != 4'd8 ||
	     !tlb$lookup[130] ||
	     rg_priv_6_EQ_0b0_03_AND_NOT_tlb_lookup_rg_satp_ETC___d157 ||
	     NOT_tlb_lookup_rg_satp_9_BITS_59_TO_44_6_rg_ad_ETC___d166 ;
  assign NOT_rg_priv_6_ULE_0b1_7_8_OR_NOT_rg_satp_9_BIT_ETC___d464 =
	     !rg_priv_6_ULE_0b1___d87 || rg_satp[63:60] != 4'd8 ||
	     !tlb$lookup[130] ||
	     NOT_rg_priv_6_EQ_0b0_03_78_OR_tlb_lookup_rg_sa_ETC___d392 &&
	     tlb_lookup_rg_satp_9_BITS_59_TO_44_6_rg_addr_7_ETC___d394 ;
  assign NOT_rg_priv_6_ULE_0b1_7_8_OR_NOT_rg_satp_9_BIT_ETC___d465 =
	     (!rg_priv_6_ULE_0b1___d87 || rg_satp[63:60] != 4'd8 ||
	      tlb$lookup[130]) &&
	     NOT_rg_priv_6_ULE_0b1_7_8_OR_NOT_rg_satp_9_BIT_ETC___d464 ;
  assign NOT_rg_priv_6_ULE_0b1_7_8_OR_NOT_rg_satp_9_BIT_ETC___d472 =
	     !rg_priv_6_ULE_0b1___d87 || rg_satp[63:60] != 4'd8 ||
	     !tlb$lookup[130] ||
	     (rg_priv != 2'b0 || tlb$lookup[70]) &&
	     (rg_priv != 2'b01 || !tlb$lookup[70] || rg_sstatus_SUM) &&
	     rg_op_13_EQ_0_14_OR_rg_op_13_EQ_2_16_AND_rg_am_ETC___d468 &&
	     tlb_lookup_rg_satp_9_BITS_59_TO_44_6_rg_addr_7_ETC___d394 ;
  assign NOT_rg_priv_6_ULE_0b1_7_8_OR_NOT_rg_satp_9_BIT_ETC___d475 =
	     (!rg_priv_6_ULE_0b1___d87 || rg_satp[63:60] != 4'd8 ||
	      tlb$lookup[130]) &&
	     NOT_rg_priv_6_ULE_0b1_7_8_OR_NOT_rg_satp_9_BIT_ETC___d472 &&
	     dmem_not_imem &&
	     !soc_map$m_is_mem_addr &&
	     !cfg_verbosity_read__1_ULE_1___d42 ;
  assign NOT_rg_priv_6_ULE_0b1_7_8_OR_NOT_rg_satp_9_BIT_ETC___d481 =
	     (!rg_priv_6_ULE_0b1___d87 || rg_satp[63:60] != 4'd8 ||
	      tlb$lookup[130]) &&
	     NOT_rg_priv_6_ULE_0b1_7_8_OR_NOT_rg_satp_9_BIT_ETC___d464 &&
	     NOT_dmem_not_imem_28_OR_soc_map_m_is_mem_addr__ETC___d479 ;
  assign NOT_rg_priv_6_ULE_0b1_7_8_OR_NOT_rg_satp_9_BIT_ETC___d502 =
	     (!rg_priv_6_ULE_0b1___d87 || rg_satp[63:60] != 4'd8 ||
	      tlb$lookup[130]) &&
	     NOT_rg_priv_6_ULE_0b1_7_8_OR_NOT_rg_satp_9_BIT_ETC___d464 &&
	     (!dmem_not_imem || soc_map$m_is_mem_addr) &&
	     rg_op_13_EQ_0_14_OR_rg_op_13_EQ_2_16_AND_rg_am_ETC___d499 ;
  assign NOT_rg_priv_6_ULE_0b1_7_8_OR_NOT_rg_satp_9_BIT_ETC___d508 =
	     NOT_rg_priv_6_ULE_0b1_7_8_OR_NOT_rg_satp_9_BIT_ETC___d464 &&
	     (!dmem_not_imem || soc_map$m_is_mem_addr) &&
	     (rg_op_13_EQ_0_14_OR_rg_op_13_EQ_2_16_AND_rg_am_ETC___d503 ||
	      rg_op == 2'd2 && rg_amo_funct7[6:2] == 5'b00011 &&
	      lrsc_result__h21885) ;
  assign NOT_rg_priv_6_ULE_0b1_7_8_OR_NOT_rg_satp_9_BIT_ETC___d509 =
	     (!rg_priv_6_ULE_0b1___d87 || rg_satp[63:60] != 4'd8 ||
	      tlb$lookup[130]) &&
	     NOT_rg_priv_6_ULE_0b1_7_8_OR_NOT_rg_satp_9_BIT_ETC___d508 ;
  assign NOT_rg_priv_6_ULE_0b1_7_8_OR_NOT_rg_satp_9_BIT_ETC___d672 =
	     !rg_priv_6_ULE_0b1___d87 || rg_satp[63:60] != 4'd8 ||
	     !tlb$lookup[130] ||
	     NOT_rg_priv_6_EQ_0b0_03_78_OR_tlb_lookup_rg_sa_ETC___d669 &&
	     tlb$lookup[72] ;
  assign NOT_rg_priv_6_ULE_0b1_7_8_OR_NOT_rg_satp_9_BIT_ETC___d677 =
	     (!rg_priv_6_ULE_0b1___d87 || rg_satp[63:60] != 4'd8 ||
	      tlb$lookup[130]) &&
	     NOT_rg_priv_6_ULE_0b1_7_8_OR_NOT_rg_satp_9_BIT_ETC___d672 &&
	     NOT_dmem_not_imem_28_OR_soc_map_m_is_mem_addr__ETC___d675 ;
  assign NOT_rg_priv_6_ULE_0b1_7_8_OR_NOT_rg_satp_9_BIT_ETC___d683 =
	     NOT_rg_priv_6_ULE_0b1_7_8_OR_NOT_rg_satp_9_BIT_ETC___d672 &&
	     (!dmem_not_imem || soc_map$m_is_mem_addr) &&
	     rg_op == 2'd2 &&
	     rg_amo_funct7_18_BITS_6_TO_2_19_EQ_0b10_20_AND_ETC___d680 ;
  assign NOT_rg_priv_6_ULE_0b1_7_8_OR_NOT_rg_satp_9_BIT_ETC___d689 =
	     (!rg_priv_6_ULE_0b1___d87 || rg_satp[63:60] != 4'd8 ||
	      tlb$lookup[130]) &&
	     NOT_rg_priv_6_ULE_0b1_7_8_OR_NOT_rg_satp_9_BIT_ETC___d672 &&
	     NOT_dmem_not_imem_28_OR_soc_map_m_is_mem_addr__ETC___d687 ;
  assign NOT_rg_priv_6_ULE_0b1_7_8_OR_NOT_rg_satp_9_BIT_ETC___d694 =
	     (!rg_priv_6_ULE_0b1___d87 || rg_satp[63:60] != 4'd8 ||
	      tlb$lookup[130]) &&
	     NOT_rg_priv_6_ULE_0b1_7_8_OR_NOT_rg_satp_9_BIT_ETC___d672 &&
	     NOT_dmem_not_imem_28_OR_soc_map_m_is_mem_addr__ETC___d692 ;
  assign NOT_rg_priv_6_ULE_0b1_7_8_OR_NOT_rg_satp_9_BIT_ETC___d702 =
	     (!rg_priv_6_ULE_0b1___d87 || rg_satp[63:60] != 4'd8 ||
	      tlb$lookup[130]) &&
	     NOT_rg_priv_6_ULE_0b1_7_8_OR_NOT_rg_satp_9_BIT_ETC___d672 &&
	     NOT_dmem_not_imem_28_OR_soc_map_m_is_mem_addr__ETC___d700 ;
  assign NOT_rg_priv_6_ULE_0b1_7_8_OR_NOT_rg_satp_9_BIT_ETC___d705 =
	     !rg_priv_6_ULE_0b1___d87 || rg_satp[63:60] != 4'd8 ||
	     !tlb$lookup[130] ||
	     NOT_rg_priv_6_EQ_0b0_03_78_OR_tlb_lookup_rg_sa_ETC___d415 &&
	     tlb$lookup[72] &&
	     tlb$lookup[73] ;
  assign NOT_rg_priv_6_ULE_0b1_7_8_OR_NOT_rg_satp_9_BIT_ETC___d711 =
	     (!rg_priv_6_ULE_0b1___d87 || rg_satp[63:60] != 4'd8 ||
	      tlb$lookup[130]) &&
	     NOT_rg_priv_6_ULE_0b1_7_8_OR_NOT_rg_satp_9_BIT_ETC___d705 &&
	     NOT_dmem_not_imem_28_OR_soc_map_m_is_mem_addr__ETC___d709 ;
  assign NOT_rg_priv_6_ULE_0b1_7_8_OR_NOT_rg_satp_9_BIT_ETC___d724 =
	     (!rg_priv_6_ULE_0b1___d87 || rg_satp[63:60] != 4'd8 ||
	      tlb$lookup[130]) &&
	     NOT_rg_priv_6_ULE_0b1_7_8_OR_NOT_rg_satp_9_BIT_ETC___d705 &&
	     NOT_dmem_not_imem_28_OR_soc_map_m_is_mem_addr__ETC___d722 ;
  assign NOT_rg_priv_6_ULE_0b1_7_8_OR_NOT_rg_satp_9_BIT_ETC___d854 =
	     NOT_rg_priv_6_ULE_0b1_7_8_OR_NOT_rg_satp_9_BIT_ETC___d705 &&
	     (!dmem_not_imem || soc_map$m_is_mem_addr) &&
	     rg_op != 2'd0 &&
	     (rg_op != 2'd2 || rg_amo_funct7[6:2] != 5'b00010) &&
	     (rg_op_13_EQ_1_66_OR_rg_op_13_EQ_2_16_AND_rg_am_ETC___d850 ||
	      NOT_rg_op_13_EQ_1_66_93_AND_NOT_rg_op_13_EQ_2__ETC___d719) ;
  assign NOT_rg_priv_6_ULE_0b1_7_8_OR_NOT_rg_satp_9_BIT_ETC___d855 =
	     (!rg_priv_6_ULE_0b1___d87 || rg_satp[63:60] != 4'd8 ||
	      tlb$lookup[130]) &&
	     NOT_rg_priv_6_ULE_0b1_7_8_OR_NOT_rg_satp_9_BIT_ETC___d854 ;
  assign NOT_rg_priv_6_ULE_0b1_7_8_OR_NOT_rg_satp_9_BIT_ETC___d861 =
	     (!rg_priv_6_ULE_0b1___d87 || rg_satp[63:60] != 4'd8 ||
	      tlb$lookup[130]) &&
	     NOT_rg_priv_6_ULE_0b1_7_8_OR_NOT_rg_satp_9_BIT_ETC___d705 &&
	     NOT_dmem_not_imem_28_OR_soc_map_m_is_mem_addr__ETC___d859 ;
  assign NOT_rg_priv_6_ULE_0b1_7_8_OR_NOT_rg_satp_9_BIT_ETC___d867 =
	     NOT_rg_priv_6_ULE_0b1_7_8_OR_NOT_rg_satp_9_BIT_ETC___d705 &&
	     (!dmem_not_imem || soc_map$m_is_mem_addr) &&
	     rg_op == 2'd2 &&
	     rg_amo_funct7[6:2] == 5'b00011 &&
	     rg_lrsc_valid &&
	     !rg_lrsc_pa_70_EQ_IF_rg_priv_6_ULE_0b1_7_AND_rg_ETC___d271 &&
	     !cfg_verbosity_read__1_ULE_1___d42 ;
  assign NOT_rg_priv_6_ULE_0b1_7_8_OR_NOT_rg_satp_9_BIT_ETC___d873 =
	     NOT_rg_priv_6_ULE_0b1_7_8_OR_NOT_rg_satp_9_BIT_ETC___d705 &&
	     (!dmem_not_imem || soc_map$m_is_mem_addr) &&
	     rg_op == 2'd2 &&
	     rg_amo_funct7[6:2] == 5'b00011 &&
	     !rg_lrsc_valid &&
	     !cfg_verbosity_read__1_ULE_1___d42 ;
  assign NOT_rg_priv_6_ULE_0b1_7_8_OR_NOT_rg_satp_9_BIT_ETC___d879 =
	     (!rg_priv_6_ULE_0b1___d87 || rg_satp[63:60] != 4'd8 ||
	      tlb$lookup[130]) &&
	     NOT_rg_priv_6_ULE_0b1_7_8_OR_NOT_rg_satp_9_BIT_ETC___d705 &&
	     NOT_dmem_not_imem_28_OR_soc_map_m_is_mem_addr__ETC___d877 ;
  assign NOT_rg_priv_6_ULE_0b1_7_8_OR_NOT_rg_satp_9_BIT_ETC___d884 =
	     NOT_rg_priv_6_ULE_0b1_7_8_OR_NOT_rg_satp_9_BIT_ETC___d705 &&
	     (!dmem_not_imem || soc_map$m_is_mem_addr) &&
	     (rg_op == 2'd1 ||
	      rg_op == 2'd2 && rg_amo_funct7[6:2] == 5'b00011) &&
	     NOT_rg_op_13_EQ_2_16_17_OR_NOT_rg_amo_funct7_1_ETC___d880 ;
  assign NOT_rg_priv_6_ULE_0b1_7_8_OR_NOT_rg_satp_9_BIT_ETC___d885 =
	     (!rg_priv_6_ULE_0b1___d87 || rg_satp[63:60] != 4'd8 ||
	      tlb$lookup[130]) &&
	     NOT_rg_priv_6_ULE_0b1_7_8_OR_NOT_rg_satp_9_BIT_ETC___d884 ;
  assign NOT_rg_priv_6_ULE_0b1_7_8_OR_NOT_rg_satp_9_BIT_ETC___d890 =
	     NOT_rg_priv_6_ULE_0b1_7_8_OR_NOT_rg_satp_9_BIT_ETC___d705 &&
	     (!dmem_not_imem || soc_map$m_is_mem_addr) &&
	     (rg_op == 2'd1 ||
	      rg_op == 2'd2 && rg_amo_funct7[6:2] == 5'b00011) &&
	     NOT_rg_op_13_EQ_2_16_17_OR_NOT_rg_amo_funct7_1_ETC___d886 ;
  assign NOT_rg_priv_6_ULE_0b1_7_8_OR_NOT_rg_satp_9_BIT_ETC___d896 =
	     NOT_rg_priv_6_ULE_0b1_7_8_OR_NOT_rg_satp_9_BIT_ETC___d705 &&
	     (!dmem_not_imem || soc_map$m_is_mem_addr) &&
	     (rg_op == 2'd1 ||
	      rg_op == 2'd2 && rg_amo_funct7[6:2] == 5'b00011) &&
	     NOT_rg_op_13_EQ_2_16_17_OR_NOT_rg_amo_funct7_1_ETC___d892 ;
  assign NOT_rg_priv_6_ULE_0b1_7_8_OR_NOT_rg_satp_9_BIT_ETC___d897 =
	     (!rg_priv_6_ULE_0b1___d87 || rg_satp[63:60] != 4'd8 ||
	      tlb$lookup[130]) &&
	     NOT_rg_priv_6_ULE_0b1_7_8_OR_NOT_rg_satp_9_BIT_ETC___d896 ;
  assign NOT_rg_priv_6_ULE_0b1_7_8_OR_NOT_rg_satp_9_BIT_ETC___d902 =
	     NOT_rg_priv_6_ULE_0b1_7_8_OR_NOT_rg_satp_9_BIT_ETC___d705 &&
	     (!dmem_not_imem || soc_map$m_is_mem_addr) &&
	     rg_op == 2'd2 &&
	     rg_amo_funct7[6:2] == 5'b00011 &&
	     lrsc_result__h21885 &&
	     !cfg_verbosity_read__1_ULE_1___d42 ;
  assign NOT_rg_priv_6_ULE_0b1_7_8_OR_NOT_rg_satp_9_BIT_ETC___d903 =
	     (!rg_priv_6_ULE_0b1___d87 || rg_satp[63:60] != 4'd8 ||
	      tlb$lookup[130]) &&
	     NOT_rg_priv_6_ULE_0b1_7_8_OR_NOT_rg_satp_9_BIT_ETC___d902 ;
  assign NOT_rg_priv_6_ULE_0b1_7_8_OR_NOT_rg_satp_9_BIT_ETC___d909 =
	     NOT_rg_priv_6_ULE_0b1_7_8_OR_NOT_rg_satp_9_BIT_ETC___d705 &&
	     (!dmem_not_imem || soc_map$m_is_mem_addr) &&
	     rg_op != 2'd0 &&
	     (rg_op != 2'd2 || rg_amo_funct7[6:2] != 5'b00010) &&
	     rg_op != 2'd1 &&
	     (rg_op != 2'd2 || rg_amo_funct7[6:2] != 5'b00011) &&
	     NOT_ram_state_and_ctag_cset_b_read__00_BIT_52__ETC___d690 ;
  assign NOT_rg_priv_6_ULE_0b1_7_8_OR_NOT_rg_satp_9_BIT_ETC___d914 =
	     NOT_rg_priv_6_ULE_0b1_7_8_OR_NOT_rg_satp_9_BIT_ETC___d705 &&
	     (!dmem_not_imem || soc_map$m_is_mem_addr) &&
	     rg_op != 2'd0 &&
	     (rg_op != 2'd2 || rg_amo_funct7[6:2] != 5'b00010) &&
	     rg_op != 2'd1 &&
	     (rg_op != 2'd2 || rg_amo_funct7[6:2] != 5'b00011) &&
	     ram_state_and_ctag_cset_b_read__00_BIT_52_01_A_ETC___d673 ;
  assign NOT_rg_priv_6_ULE_0b1_7_8_OR_NOT_rg_satp_9_BIT_ETC___d915 =
	     (!rg_priv_6_ULE_0b1___d87 || rg_satp[63:60] != 4'd8 ||
	      tlb$lookup[130]) &&
	     NOT_rg_priv_6_ULE_0b1_7_8_OR_NOT_rg_satp_9_BIT_ETC___d914 ;
  assign NOT_rg_priv_6_ULE_0b1_7_8_OR_NOT_rg_satp_9_BIT_ETC___d920 =
	     NOT_rg_priv_6_ULE_0b1_7_8_OR_NOT_rg_satp_9_BIT_ETC___d705 &&
	     (!dmem_not_imem || soc_map$m_is_mem_addr) &&
	     rg_op != 2'd0 &&
	     (rg_op != 2'd2 || rg_amo_funct7[6:2] != 5'b00010) &&
	     rg_op != 2'd1 &&
	     (rg_op != 2'd2 || rg_amo_funct7[6:2] != 5'b00011) &&
	     ram_state_and_ctag_cset_b_read__00_BIT_52_01_A_ETC___d916 ;
  assign NOT_rg_priv_6_ULE_0b1_7_8_OR_NOT_rg_satp_9_BIT_ETC___d925 =
	     (!rg_priv_6_ULE_0b1___d87 || rg_satp[63:60] != 4'd8 ||
	      tlb$lookup[130]) &&
	     NOT_rg_priv_6_ULE_0b1_7_8_OR_NOT_rg_satp_9_BIT_ETC___d705 &&
	     NOT_dmem_not_imem_28_OR_soc_map_m_is_mem_addr__ETC___d923 ;
  assign NOT_tlb_lookup_rg_satp_9_BITS_59_TO_44_6_rg_ad_ETC___d150 =
	     !tlb$lookup[72] ||
	     rg_op != 2'd0 &&
	     (rg_op != 2'd2 || rg_amo_funct7[6:2] != 5'b00010) &&
	     !tlb$lookup[73] ;
  assign NOT_tlb_lookup_rg_satp_9_BITS_59_TO_44_6_rg_ad_ETC___d166 =
	     !tlb$lookup[72] || !tlb$lookup[73] || pte___2__h6741[7] ||
	     rg_op == 2'd0 ||
	     rg_op == 2'd2 && rg_amo_funct7[6:2] == 5'b00010 ;
  assign _theResult___fst__h3157 =
	     f_fabric_write_reqs$D_OUT[63:0] << shift_bits__h3004 ;
  assign _theResult___snd_fst__h6331 =
	     tlb$lookup[130] ? _theResult___snd_fst__h6402 : rg_addr ;
  assign _theResult___snd_fst__h6402 =
	     (rg_priv_6_EQ_0b0_03_AND_NOT_tlb_lookup_rg_satp_ETC___d144 ||
	      NOT_tlb_lookup_rg_satp_9_BITS_59_TO_44_6_rg_ad_ETC___d150) ?
	       rg_addr :
	       _theResult___fst__h6743 ;
  assign _theResult___snd_fst__h6972 =
	     (!pte___2__h6741[7] && rg_op != 2'd0 &&
	      (rg_op != 2'd2 || rg_amo_funct7[6:2] != 5'b00010)) ?
	       pte___1__h7049 :
	       pte___2__h6741 ;
  assign _theResult___snd_snd_fst__h6333 =
	     tlb$lookup[130] ?
	       _theResult___snd_snd_fst__h6404 :
	       tlb$lookup[129:66] ;
  assign _theResult___snd_snd_fst__h6404 =
	     (rg_priv_6_EQ_0b0_03_AND_NOT_tlb_lookup_rg_satp_ETC___d144 ||
	      NOT_tlb_lookup_rg_satp_9_BITS_59_TO_44_6_rg_ad_ETC___d150) ?
	       tlb$lookup[129:66] :
	       _theResult___snd_fst__h6972 ;
  assign access_exc_code__h2772 =
	     dmem_not_imem ?
	       ((rg_op == 2'd0 ||
		 rg_op == 2'd2 && rg_amo_funct7[6:2] == 5'b00010) ?
		  4'd5 :
		  4'd7) :
	       4'd1 ;
  assign b__h28690 =
	     CAN_FIRE_RL_rl_fabric_send_write_req ?
	       ctr_wr_rsps_pending_crg$port0__write_1 :
	       ctr_wr_rsps_pending_crg ;
  assign cfg_verbosity_read__1_ULE_1___d42 = cfg_verbosity <= 4'd1 ;
  assign cline_fabric_addr__h31891 = { rg_pa[63:6], 6'd0 } ;
  assign dmem_not_imem_AND_rg_op_13_EQ_0_14_OR_rg_op_13_ETC___d387 =
	     dmem_not_imem &&
	     (rg_op == 2'd0 ||
	      rg_op == 2'd2 && rg_amo_funct7[6:2] == 5'b00010) &&
	     tlb_lookup_rg_satp_9_BITS_59_TO_44_6_rg_addr_7_ETC___d133 ;
  assign dmem_not_imem_OR_NOT_rg_op_13_EQ_0_14_15_AND_N_ETC___d127 =
	     dmem_not_imem ||
	     rg_op != 2'd0 &&
	     (rg_op != 2'd2 || rg_amo_funct7[6:2] != 5'b00010) ||
	     !tlb$lookup[69] ;
  assign exc_code___1__h6641 = x1_avValue_exc_code__h6241 ;
  assign ld_val5601_BITS_15_TO_0__q38 = ld_val__h35601[15:0] ;
  assign ld_val5601_BITS_15_TO_8__q40 = ld_val__h35601[15:8] ;
  assign ld_val5601_BITS_23_TO_16__q41 = ld_val__h35601[23:16] ;
  assign ld_val5601_BITS_31_TO_0__q39 = ld_val__h35601[31:0] ;
  assign ld_val5601_BITS_31_TO_16__q42 = ld_val__h35601[31:16] ;
  assign ld_val5601_BITS_31_TO_24__q43 = ld_val__h35601[31:24] ;
  assign ld_val5601_BITS_39_TO_32__q44 = ld_val__h35601[39:32] ;
  assign ld_val5601_BITS_47_TO_32__q45 = ld_val__h35601[47:32] ;
  assign ld_val5601_BITS_47_TO_40__q47 = ld_val__h35601[47:40] ;
  assign ld_val5601_BITS_55_TO_48__q48 = ld_val__h35601[55:48] ;
  assign ld_val5601_BITS_63_TO_32__q46 = ld_val__h35601[63:32] ;
  assign ld_val5601_BITS_63_TO_48__q49 = ld_val__h35601[63:48] ;
  assign ld_val5601_BITS_63_TO_56__q50 = ld_val__h35601[63:56] ;
  assign ld_val5601_BITS_7_TO_0__q37 = ld_val__h35601[7:0] ;
  assign lev_0_pte_pa__h30719 = lev_1_PTN_pa__h29684 + vpn_0_pa__h30718 ;
  assign lev_0_pte_pa_w64_fa__h30721 = { lev_0_pte_pa__h30719[63:3], 3'b0 } ;
  assign lev_1_PTN_pa__h29684 = { 8'd0, x__h29765 } ;
  assign lev_1_pte_pa__h29686 = lev_1_PTN_pa__h29684 + vpn_1_pa__h29685 ;
  assign lev_1_pte_pa_w64_fa__h29688 = { lev_1_pte_pa__h29686[63:3], 3'b0 } ;
  assign lev_2_pte_pa__h28789 = satp_pa__h2068 + vpn_2_pa__h28788 ;
  assign lev_2_pte_pa_w64_fa__h28791 = { lev_2_pte_pa__h28789[63:3], 3'b0 } ;
  assign lrsc_result__h21885 =
	     !rg_lrsc_valid ||
	     !rg_lrsc_pa_70_EQ_IF_rg_priv_6_ULE_0b1_7_AND_rg_ETC___d271 ;
  assign master_xactor_f_rd_dataD_OUT_BITS_10_TO_3__q2 =
	     master_xactor_f_rd_data$D_OUT[10:3] ;
  assign master_xactor_f_rd_dataD_OUT_BITS_18_TO_11__q5 =
	     master_xactor_f_rd_data$D_OUT[18:11] ;
  assign master_xactor_f_rd_dataD_OUT_BITS_18_TO_3__q3 =
	     master_xactor_f_rd_data$D_OUT[18:3] ;
  assign master_xactor_f_rd_dataD_OUT_BITS_26_TO_19__q6 =
	     master_xactor_f_rd_data$D_OUT[26:19] ;
  assign master_xactor_f_rd_dataD_OUT_BITS_34_TO_19__q7 =
	     master_xactor_f_rd_data$D_OUT[34:19] ;
  assign master_xactor_f_rd_dataD_OUT_BITS_34_TO_27__q1 =
	     master_xactor_f_rd_data$D_OUT[34:27] ;
  assign master_xactor_f_rd_dataD_OUT_BITS_34_TO_3__q4 =
	     master_xactor_f_rd_data$D_OUT[34:3] ;
  assign master_xactor_f_rd_dataD_OUT_BITS_42_TO_35__q8 =
	     master_xactor_f_rd_data$D_OUT[42:35] ;
  assign master_xactor_f_rd_dataD_OUT_BITS_50_TO_35__q9 =
	     master_xactor_f_rd_data$D_OUT[50:35] ;
  assign master_xactor_f_rd_dataD_OUT_BITS_50_TO_43__q11 =
	     master_xactor_f_rd_data$D_OUT[50:43] ;
  assign master_xactor_f_rd_dataD_OUT_BITS_58_TO_51__q12 =
	     master_xactor_f_rd_data$D_OUT[58:51] ;
  assign master_xactor_f_rd_dataD_OUT_BITS_66_TO_35__q10 =
	     master_xactor_f_rd_data$D_OUT[66:35] ;
  assign master_xactor_f_rd_dataD_OUT_BITS_66_TO_51__q13 =
	     master_xactor_f_rd_data$D_OUT[66:51] ;
  assign master_xactor_f_rd_dataD_OUT_BITS_66_TO_59__q14 =
	     master_xactor_f_rd_data$D_OUT[66:59] ;
  assign master_xactor_f_rd_data_first__41_BITS_2_TO_1__ETC___d1007 =
	     master_xactor_f_rd_data$D_OUT[2:1] == 2'b0 &&
	     master_xactor_f_rd_data$D_OUT[3] &&
	     (master_xactor_f_rd_data$D_OUT[4] ||
	      !master_xactor_f_rd_data$D_OUT[5]) &&
	     (master_xactor_f_rd_data$D_OUT[6] ||
	      master_xactor_f_rd_data$D_OUT[4]) &&
	     (master_xactor_f_rd_data$D_OUT[30:22] != 9'd0 ||
	      master_xactor_f_rd_data$D_OUT[21:13] != 9'd0) &&
	     !cfg_verbosity_read__1_ULE_1___d42 ;
  assign master_xactor_f_rd_data_first__41_BITS_2_TO_1__ETC___d1015 =
	     master_xactor_f_rd_data$D_OUT[2:1] == 2'b0 &&
	     master_xactor_f_rd_data$D_OUT[3] &&
	     (master_xactor_f_rd_data$D_OUT[4] ||
	      !master_xactor_f_rd_data$D_OUT[5]) &&
	     (master_xactor_f_rd_data$D_OUT[6] ||
	      master_xactor_f_rd_data$D_OUT[4]) &&
	     master_xactor_f_rd_data$D_OUT[30:22] == 9'd0 &&
	     master_xactor_f_rd_data$D_OUT[21:13] == 9'd0 ;
  assign master_xactor_f_rd_data_first__41_BITS_2_TO_1__ETC___d1019 =
	     master_xactor_f_rd_data$D_OUT[2:1] == 2'b0 &&
	     master_xactor_f_rd_data$D_OUT[3] &&
	     (master_xactor_f_rd_data$D_OUT[4] ||
	      !master_xactor_f_rd_data$D_OUT[5]) &&
	     (master_xactor_f_rd_data$D_OUT[6] ||
	      master_xactor_f_rd_data$D_OUT[4]) &&
	     master_xactor_f_rd_data$D_OUT[30:22] == 9'd0 &&
	     master_xactor_f_rd_data$D_OUT[21:13] == 9'd0 &&
	     !cfg_verbosity_read__1_ULE_1___d42 ;
  assign master_xactor_f_rd_data_first__41_BITS_2_TO_1__ETC___d1050 =
	     master_xactor_f_rd_data$D_OUT[2:1] == 2'b0 &&
	     master_xactor_f_rd_data$D_OUT[3] &&
	     (master_xactor_f_rd_data$D_OUT[4] ||
	      !master_xactor_f_rd_data$D_OUT[5]) &&
	     (master_xactor_f_rd_data$D_OUT[6] ||
	      master_xactor_f_rd_data$D_OUT[4]) &&
	     master_xactor_f_rd_data$D_OUT[21:13] == 9'd0 ;
  assign master_xactor_f_rd_data_first__41_BITS_2_TO_1__ETC___d1054 =
	     master_xactor_f_rd_data$D_OUT[2:1] == 2'b0 &&
	     master_xactor_f_rd_data$D_OUT[3] &&
	     (master_xactor_f_rd_data$D_OUT[4] ||
	      !master_xactor_f_rd_data$D_OUT[5]) &&
	     (master_xactor_f_rd_data$D_OUT[6] ||
	      master_xactor_f_rd_data$D_OUT[4]) &&
	     master_xactor_f_rd_data$D_OUT[21:13] == 9'd0 &&
	     !cfg_verbosity_read__1_ULE_1___d42 ;
  assign master_xactor_f_rd_data_first__41_BITS_2_TO_1__ETC___d1060 =
	     master_xactor_f_rd_data$D_OUT[2:1] == 2'b0 &&
	     master_xactor_f_rd_data$D_OUT[3] &&
	     (master_xactor_f_rd_data$D_OUT[4] ||
	      !master_xactor_f_rd_data$D_OUT[5]) &&
	     (master_xactor_f_rd_data$D_OUT[6] ||
	      master_xactor_f_rd_data$D_OUT[4]) &&
	     master_xactor_f_rd_data$D_OUT[21:13] != 9'd0 &&
	     !cfg_verbosity_read__1_ULE_1___d42 ;
  assign master_xactor_f_rd_data_first__41_BITS_2_TO_1__ETC___d1085 =
	     master_xactor_f_rd_data$D_OUT[2:1] == 2'b0 &&
	     master_xactor_f_rd_data$D_OUT[3] &&
	     (master_xactor_f_rd_data$D_OUT[4] ||
	      !master_xactor_f_rd_data$D_OUT[5]) &&
	     (master_xactor_f_rd_data$D_OUT[6] ||
	      master_xactor_f_rd_data$D_OUT[4]) &&
	     !cfg_verbosity_read__1_ULE_1___d42 ;
  assign master_xactor_f_rd_data_first__41_BITS_2_TO_1__ETC___d981 =
	     master_xactor_f_rd_data$D_OUT[2:1] == 2'b0 &&
	     (!master_xactor_f_rd_data$D_OUT[3] ||
	      !master_xactor_f_rd_data$D_OUT[4] &&
	      master_xactor_f_rd_data$D_OUT[5]) &&
	     !cfg_verbosity_read__1_ULE_1___d42 ;
  assign master_xactor_f_rd_data_first__41_BITS_2_TO_1__ETC___d991 =
	     master_xactor_f_rd_data$D_OUT[2:1] == 2'b0 &&
	     master_xactor_f_rd_data$D_OUT[3] &&
	     !master_xactor_f_rd_data$D_OUT[5] &&
	     !master_xactor_f_rd_data$D_OUT[6] &&
	     !master_xactor_f_rd_data$D_OUT[4] &&
	     !cfg_verbosity_read__1_ULE_1___d42 ;
  assign new_st_val__h25444 =
	     (rg_f3 == 3'b010) ?
	       new_st_val__h25750 :
	       _theResult_____2__h25746 ;
  assign new_st_val__h25750 = { 32'd0, _theResult_____2__h25746[31:0] } ;
  assign new_st_val__h25841 =
	     IF_rg_f3_17_EQ_0b10_50_THEN_SEXT_IF_rg_f3_17_E_ETC___d715 +
	     IF_rg_f3_17_EQ_0b10_50_THEN_SEXT_rg_st_amo_val_ETC___d784 ;
  assign new_st_val__h26821 = w1__h25738 ^ w2__h37847 ;
  assign new_st_val__h26825 = w1__h25738 & w2__h37847 ;
  assign new_st_val__h26829 = w1__h25738 | w2__h37847 ;
  assign new_st_val__h26833 =
	     (w1__h25738 < w2__h37847) ? w1__h25738 : w2__h37847 ;
  assign new_st_val__h26838 =
	     (w1__h25738 <= w2__h37847) ? w2__h37847 : w1__h25738 ;
  assign new_st_val__h26844 =
	     ((IF_rg_f3_17_EQ_0b10_50_THEN_SEXT_IF_rg_f3_17_E_ETC___d715 ^
	       64'h8000000000000000) <
	      (IF_rg_f3_17_EQ_0b10_50_THEN_SEXT_rg_st_amo_val_ETC___d784 ^
	       64'h8000000000000000)) ?
	       w1__h25738 :
	       w2__h37847 ;
  assign new_st_val__h26849 =
	     ((IF_rg_f3_17_EQ_0b10_50_THEN_SEXT_IF_rg_f3_17_E_ETC___d715 ^
	       64'h8000000000000000) <=
	      (IF_rg_f3_17_EQ_0b10_50_THEN_SEXT_rg_st_amo_val_ETC___d784 ^
	       64'h8000000000000000)) ?
	       w2__h37847 :
	       w1__h25738 ;
  assign new_st_val__h37857 = { 32'd0, _theResult_____2__h37853[31:0] } ;
  assign new_st_val__h37948 =
	     new_ld_val__h37807 +
	     IF_rg_f3_17_EQ_0b10_50_THEN_SEXT_rg_st_amo_val_ETC___d784 ;
  assign new_st_val__h39808 = w1__h37845 ^ w2__h37847 ;
  assign new_st_val__h39812 = w1__h37845 & w2__h37847 ;
  assign new_st_val__h39816 = w1__h37845 | w2__h37847 ;
  assign new_st_val__h39820 =
	     (w1__h37845 < w2__h37847) ? w1__h37845 : w2__h37847 ;
  assign new_st_val__h39825 =
	     (w1__h37845 <= w2__h37847) ? w2__h37847 : w1__h37845 ;
  assign new_st_val__h39831 =
	     ((new_ld_val__h37807 ^ 64'h8000000000000000) <
	      (IF_rg_f3_17_EQ_0b10_50_THEN_SEXT_rg_st_amo_val_ETC___d784 ^
	       64'h8000000000000000)) ?
	       w1__h37845 :
	       w2__h37847 ;
  assign new_st_val__h39836 =
	     ((new_ld_val__h37807 ^ 64'h8000000000000000) <=
	      (IF_rg_f3_17_EQ_0b10_50_THEN_SEXT_rg_st_amo_val_ETC___d784 ^
	       64'h8000000000000000)) ?
	       w2__h37847 :
	       w1__h37845 ;
  assign new_value__h24314 =
	     (rg_op == 2'd2 && rg_amo_funct7[6:2] == 5'b00011) ?
	       64'd1 :
	       CASE_rg_f3_0b0_IF_rg_addr_7_BITS_2_TO_0_21_EQ__ETC__q53 ;
  assign new_value__h7887 =
	     (rg_op == 2'd2 && rg_amo_funct7[6:2] == 5'b00011) ?
	       word64__h7759 :
	       IF_rg_f3_17_EQ_0b0_18_THEN_IF_rg_addr_7_BITS_2_ETC___d654 ;
  assign pa___1__h6749 = { 8'd0, x__h6752 } ;
  assign pa___1__h6798 = { 8'd0, x__h6801 } ;
  assign pa___1__h6867 = { 8'd0, x__h6870 } ;
  assign pte___1__h7021 = { tlb$lookup[129:73], 1'd1, tlb$lookup[71:66] } ;
  assign pte___1__h7049 =
	     { pte___2__h6741[63:8], 1'd1, pte___2__h6741[6:0] } ;
  assign pte___2__h6741 =
	     tlb$lookup[72] ? tlb$lookup[129:66] : pte___1__h7021 ;
  assign ram_state_and_ctag_cset_b_read__00_BITS_104_TO_ETC___d211 =
	     ram_state_and_ctag_cset$DOB[104:53] ==
	     x1_avValue_pa__h6240[63:12] ;
  assign ram_state_and_ctag_cset_b_read__00_BITS_51_TO__ETC___d205 =
	     ram_state_and_ctag_cset$DOB[51:0] ==
	     x1_avValue_pa__h6240[63:12] ;
  assign ram_state_and_ctag_cset_b_read__00_BIT_52_01_A_ETC___d484 =
	     (ram_state_and_ctag_cset$DOB[52] &&
	      ram_state_and_ctag_cset_b_read__00_BITS_51_TO__ETC___d205 ||
	      ram_state_and_ctag_cset$DOB[105] &&
	      ram_state_and_ctag_cset_b_read__00_BITS_104_TO_ETC___d211) &&
	     rg_op == 2'd2 &&
	     rg_amo_funct7[6:2] == 5'b00010 ;
  assign ram_state_and_ctag_cset_b_read__00_BIT_52_01_A_ETC___d495 =
	     (ram_state_and_ctag_cset$DOB[52] &&
	      ram_state_and_ctag_cset_b_read__00_BITS_51_TO__ETC___d205 ||
	      ram_state_and_ctag_cset$DOB[105] &&
	      ram_state_and_ctag_cset_b_read__00_BITS_104_TO_ETC___d211) &&
	     IF_rg_priv_6_ULE_0b1_7_AND_rg_satp_9_BITS_63_T_ETC___d485 ;
  assign ram_state_and_ctag_cset_b_read__00_BIT_52_01_A_ETC___d673 =
	     (ram_state_and_ctag_cset$DOB[52] &&
	      ram_state_and_ctag_cset_b_read__00_BITS_51_TO__ETC___d205 ||
	      ram_state_and_ctag_cset$DOB[105] &&
	      ram_state_and_ctag_cset_b_read__00_BITS_104_TO_ETC___d211) &&
	     !cfg_verbosity_read__1_ULE_1___d42 ;
  assign ram_state_and_ctag_cset_b_read__00_BIT_52_01_A_ETC___d916 =
	     (ram_state_and_ctag_cset$DOB[52] &&
	      ram_state_and_ctag_cset_b_read__00_BITS_51_TO__ETC___d205 ||
	      ram_state_and_ctag_cset$DOB[105] &&
	      ram_state_and_ctag_cset_b_read__00_BITS_104_TO_ETC___d211) &&
	     IF_rg_priv_6_ULE_0b1_7_AND_rg_satp_9_BITS_63_T_ETC___d485 &&
	     !cfg_verbosity_read__1_ULE_1___d42 ;
  assign req_f3_BITS_1_TO_0_433_EQ_0b0_434_OR_req_f3_BI_ETC___d1463 =
	     req_f3[1:0] == 2'b0 || req_f3[1:0] == 2'b01 && !req_addr[0] ||
	     req_f3[1:0] == 2'b10 && req_addr[1:0] == 2'b0 ||
	     req_f3[1:0] == 2'b11 && req_addr[2:0] == 3'b0 ;
  assign result__h20596 =
	     { {56{word64759_BITS_7_TO_0__q15[7]}},
	       word64759_BITS_7_TO_0__q15 } ;
  assign result__h20624 =
	     { {56{word64759_BITS_15_TO_8__q18[7]}},
	       word64759_BITS_15_TO_8__q18 } ;
  assign result__h20652 =
	     { {56{word64759_BITS_23_TO_16__q19[7]}},
	       word64759_BITS_23_TO_16__q19 } ;
  assign result__h20680 =
	     { {56{word64759_BITS_31_TO_24__q21[7]}},
	       word64759_BITS_31_TO_24__q21 } ;
  assign result__h20708 =
	     { {56{word64759_BITS_39_TO_32__q23[7]}},
	       word64759_BITS_39_TO_32__q23 } ;
  assign result__h20736 =
	     { {56{word64759_BITS_47_TO_40__q22[7]}},
	       word64759_BITS_47_TO_40__q22 } ;
  assign result__h20764 =
	     { {56{word64759_BITS_55_TO_48__q26[7]}},
	       word64759_BITS_55_TO_48__q26 } ;
  assign result__h20792 =
	     { {56{word64759_BITS_63_TO_56__q28[7]}},
	       word64759_BITS_63_TO_56__q28 } ;
  assign result__h20837 = { 56'd0, word64__h7759[7:0] } ;
  assign result__h20865 = { 56'd0, word64__h7759[15:8] } ;
  assign result__h20893 = { 56'd0, word64__h7759[23:16] } ;
  assign result__h20921 = { 56'd0, word64__h7759[31:24] } ;
  assign result__h20949 = { 56'd0, word64__h7759[39:32] } ;
  assign result__h20977 = { 56'd0, word64__h7759[47:40] } ;
  assign result__h21005 = { 56'd0, word64__h7759[55:48] } ;
  assign result__h21033 = { 56'd0, word64__h7759[63:56] } ;
  assign result__h21078 =
	     { {48{word64759_BITS_15_TO_0__q16[15]}},
	       word64759_BITS_15_TO_0__q16 } ;
  assign result__h21106 =
	     { {48{word64759_BITS_31_TO_16__q20[15]}},
	       word64759_BITS_31_TO_16__q20 } ;
  assign result__h21134 =
	     { {48{word64759_BITS_47_TO_32__q24[15]}},
	       word64759_BITS_47_TO_32__q24 } ;
  assign result__h21162 =
	     { {48{word64759_BITS_63_TO_48__q27[15]}},
	       word64759_BITS_63_TO_48__q27 } ;
  assign result__h21203 = { 48'd0, word64__h7759[15:0] } ;
  assign result__h21231 = { 48'd0, word64__h7759[31:16] } ;
  assign result__h21259 = { 48'd0, word64__h7759[47:32] } ;
  assign result__h21287 = { 48'd0, word64__h7759[63:48] } ;
  assign result__h21328 =
	     { {32{word64759_BITS_31_TO_0__q17[31]}},
	       word64759_BITS_31_TO_0__q17 } ;
  assign result__h21356 =
	     { {32{word64759_BITS_63_TO_32__q25[31]}},
	       word64759_BITS_63_TO_32__q25 } ;
  assign result__h21395 = { 32'd0, word64__h7759[31:0] } ;
  assign result__h21423 = { 32'd0, word64__h7759[63:32] } ;
  assign result__h35661 =
	     { {56{master_xactor_f_rd_dataD_OUT_BITS_10_TO_3__q2[7]}},
	       master_xactor_f_rd_dataD_OUT_BITS_10_TO_3__q2 } ;
  assign result__h35691 =
	     { {56{master_xactor_f_rd_dataD_OUT_BITS_18_TO_11__q5[7]}},
	       master_xactor_f_rd_dataD_OUT_BITS_18_TO_11__q5 } ;
  assign result__h35718 =
	     { {56{master_xactor_f_rd_dataD_OUT_BITS_26_TO_19__q6[7]}},
	       master_xactor_f_rd_dataD_OUT_BITS_26_TO_19__q6 } ;
  assign result__h35745 =
	     { {56{master_xactor_f_rd_dataD_OUT_BITS_34_TO_27__q1[7]}},
	       master_xactor_f_rd_dataD_OUT_BITS_34_TO_27__q1 } ;
  assign result__h35772 =
	     { {56{master_xactor_f_rd_dataD_OUT_BITS_42_TO_35__q8[7]}},
	       master_xactor_f_rd_dataD_OUT_BITS_42_TO_35__q8 } ;
  assign result__h35799 =
	     { {56{master_xactor_f_rd_dataD_OUT_BITS_50_TO_43__q11[7]}},
	       master_xactor_f_rd_dataD_OUT_BITS_50_TO_43__q11 } ;
  assign result__h35826 =
	     { {56{master_xactor_f_rd_dataD_OUT_BITS_58_TO_51__q12[7]}},
	       master_xactor_f_rd_dataD_OUT_BITS_58_TO_51__q12 } ;
  assign result__h35853 =
	     { {56{master_xactor_f_rd_dataD_OUT_BITS_66_TO_59__q14[7]}},
	       master_xactor_f_rd_dataD_OUT_BITS_66_TO_59__q14 } ;
  assign result__h35897 = { 56'd0, master_xactor_f_rd_data$D_OUT[10:3] } ;
  assign result__h35924 = { 56'd0, master_xactor_f_rd_data$D_OUT[18:11] } ;
  assign result__h35951 = { 56'd0, master_xactor_f_rd_data$D_OUT[26:19] } ;
  assign result__h35978 = { 56'd0, master_xactor_f_rd_data$D_OUT[34:27] } ;
  assign result__h36005 = { 56'd0, master_xactor_f_rd_data$D_OUT[42:35] } ;
  assign result__h36032 = { 56'd0, master_xactor_f_rd_data$D_OUT[50:43] } ;
  assign result__h36059 = { 56'd0, master_xactor_f_rd_data$D_OUT[58:51] } ;
  assign result__h36086 = { 56'd0, master_xactor_f_rd_data$D_OUT[66:59] } ;
  assign result__h36130 =
	     { {48{master_xactor_f_rd_dataD_OUT_BITS_18_TO_3__q3[15]}},
	       master_xactor_f_rd_dataD_OUT_BITS_18_TO_3__q3 } ;
  assign result__h36157 =
	     { {48{master_xactor_f_rd_dataD_OUT_BITS_34_TO_19__q7[15]}},
	       master_xactor_f_rd_dataD_OUT_BITS_34_TO_19__q7 } ;
  assign result__h36184 =
	     { {48{master_xactor_f_rd_dataD_OUT_BITS_50_TO_35__q9[15]}},
	       master_xactor_f_rd_dataD_OUT_BITS_50_TO_35__q9 } ;
  assign result__h36211 =
	     { {48{master_xactor_f_rd_dataD_OUT_BITS_66_TO_51__q13[15]}},
	       master_xactor_f_rd_dataD_OUT_BITS_66_TO_51__q13 } ;
  assign result__h36251 = { 48'd0, master_xactor_f_rd_data$D_OUT[18:3] } ;
  assign result__h36278 = { 48'd0, master_xactor_f_rd_data$D_OUT[34:19] } ;
  assign result__h36305 = { 48'd0, master_xactor_f_rd_data$D_OUT[50:35] } ;
  assign result__h36332 = { 48'd0, master_xactor_f_rd_data$D_OUT[66:51] } ;
  assign result__h36372 =
	     { {32{master_xactor_f_rd_dataD_OUT_BITS_34_TO_3__q4[31]}},
	       master_xactor_f_rd_dataD_OUT_BITS_34_TO_3__q4 } ;
  assign result__h36399 =
	     { {32{master_xactor_f_rd_dataD_OUT_BITS_66_TO_35__q10[31]}},
	       master_xactor_f_rd_dataD_OUT_BITS_66_TO_35__q10 } ;
  assign result__h36437 = { 32'd0, master_xactor_f_rd_data$D_OUT[34:3] } ;
  assign result__h36464 = { 32'd0, master_xactor_f_rd_data$D_OUT[66:35] } ;
  assign result__h38036 =
	     { {56{ld_val5601_BITS_7_TO_0__q37[7]}},
	       ld_val5601_BITS_7_TO_0__q37 } ;
  assign result__h38944 =
	     { {56{ld_val5601_BITS_15_TO_8__q40[7]}},
	       ld_val5601_BITS_15_TO_8__q40 } ;
  assign result__h38972 =
	     { {56{ld_val5601_BITS_23_TO_16__q41[7]}},
	       ld_val5601_BITS_23_TO_16__q41 } ;
  assign result__h39000 =
	     { {56{ld_val5601_BITS_31_TO_24__q43[7]}},
	       ld_val5601_BITS_31_TO_24__q43 } ;
  assign result__h39028 =
	     { {56{ld_val5601_BITS_39_TO_32__q44[7]}},
	       ld_val5601_BITS_39_TO_32__q44 } ;
  assign result__h39056 =
	     { {56{ld_val5601_BITS_47_TO_40__q47[7]}},
	       ld_val5601_BITS_47_TO_40__q47 } ;
  assign result__h39084 =
	     { {56{ld_val5601_BITS_55_TO_48__q48[7]}},
	       ld_val5601_BITS_55_TO_48__q48 } ;
  assign result__h39112 =
	     { {56{ld_val5601_BITS_63_TO_56__q50[7]}},
	       ld_val5601_BITS_63_TO_56__q50 } ;
  assign result__h39157 = { 56'd0, ld_val__h35601[7:0] } ;
  assign result__h39185 = { 56'd0, ld_val__h35601[15:8] } ;
  assign result__h39213 = { 56'd0, ld_val__h35601[23:16] } ;
  assign result__h39241 = { 56'd0, ld_val__h35601[31:24] } ;
  assign result__h39269 = { 56'd0, ld_val__h35601[39:32] } ;
  assign result__h39297 = { 56'd0, ld_val__h35601[47:40] } ;
  assign result__h39325 = { 56'd0, ld_val__h35601[55:48] } ;
  assign result__h39353 = { 56'd0, ld_val__h35601[63:56] } ;
  assign result__h39398 =
	     { {48{ld_val5601_BITS_15_TO_0__q38[15]}},
	       ld_val5601_BITS_15_TO_0__q38 } ;
  assign result__h39426 =
	     { {48{ld_val5601_BITS_31_TO_16__q42[15]}},
	       ld_val5601_BITS_31_TO_16__q42 } ;
  assign result__h39454 =
	     { {48{ld_val5601_BITS_47_TO_32__q45[15]}},
	       ld_val5601_BITS_47_TO_32__q45 } ;
  assign result__h39482 =
	     { {48{ld_val5601_BITS_63_TO_48__q49[15]}},
	       ld_val5601_BITS_63_TO_48__q49 } ;
  assign result__h39523 = { 48'd0, ld_val__h35601[15:0] } ;
  assign result__h39551 = { 48'd0, ld_val__h35601[31:16] } ;
  assign result__h39579 = { 48'd0, ld_val__h35601[47:32] } ;
  assign result__h39607 = { 48'd0, ld_val__h35601[63:48] } ;
  assign result__h39648 =
	     { {32{ld_val5601_BITS_31_TO_0__q39[31]}},
	       ld_val5601_BITS_31_TO_0__q39 } ;
  assign result__h39676 =
	     { {32{ld_val5601_BITS_63_TO_32__q46[31]}},
	       ld_val5601_BITS_63_TO_32__q46 } ;
  assign result__h39715 = { 32'd0, ld_val__h35601[31:0] } ;
  assign result__h39743 = { 32'd0, ld_val__h35601[63:32] } ;
  assign rg_amo_funct7_18_BITS_6_TO_2_19_EQ_0b10_20_AND_ETC___d680 =
	     rg_amo_funct7[6:2] == 5'b00010 &&
	     (ram_state_and_ctag_cset$DOB[52] &&
	      ram_state_and_ctag_cset_b_read__00_BITS_51_TO__ETC___d205 ||
	      ram_state_and_ctag_cset$DOB[105] &&
	      ram_state_and_ctag_cset_b_read__00_BITS_104_TO_ETC___d211) ;
  assign rg_amo_funct7_18_BITS_6_TO_2_19_EQ_0b1_88_OR_I_ETC___d344 =
	     IF_rg_f3_17_EQ_0b0_18_OR_rg_f3_17_EQ_0b100_19__ETC___d263 &&
	     (!ram_state_and_ctag_cset$DOB[105] ||
	      !ram_state_and_ctag_cset_b_read__00_BITS_104_TO_ETC___d211 ||
	      IF_rg_f3_17_EQ_0b0_18_THEN_NOT_rg_priv_6_ULE_0_ETC___d339) &&
	     (ram_state_and_ctag_cset$DOB[105] &&
	      ram_state_and_ctag_cset_b_read__00_BITS_104_TO_ETC___d211 ||
	      IF_rg_f3_17_EQ_0b0_18_THEN_NOT_rg_priv_6_ULE_0_ETC___d339) ;
  assign rg_lrsc_pa_70_EQ_IF_rg_priv_6_ULE_0b1_7_AND_rg_ETC___d271 =
	     rg_lrsc_pa == x1_avValue_pa__h6240 ;
  assign rg_op_13_EQ_0_14_OR_rg_op_13_EQ_2_16_AND_rg_am_ETC___d431 =
	     (rg_op == 2'd0 ||
	      rg_op == 2'd2 && rg_amo_funct7[6:2] == 5'b00010) &&
	     (!ram_state_and_ctag_cset$DOB[52] ||
	      !ram_state_and_ctag_cset_b_read__00_BITS_51_TO__ETC___d205) &&
	     (!ram_state_and_ctag_cset$DOB[105] ||
	      !ram_state_and_ctag_cset_b_read__00_BITS_104_TO_ETC___d211) ;
  assign rg_op_13_EQ_0_14_OR_rg_op_13_EQ_2_16_AND_rg_am_ETC___d468 =
	     (rg_op == 2'd0 ||
	      rg_op == 2'd2 && rg_amo_funct7[6:2] == 5'b00010) &&
	     tlb_lookup_rg_satp_9_BITS_59_TO_44_6_rg_addr_7_ETC___d133 ||
	     rg_op != 2'd0 &&
	     (rg_op != 2'd2 || rg_amo_funct7[6:2] != 5'b00010) &&
	     tlb$lookup[68] ;
  assign rg_op_13_EQ_0_14_OR_rg_op_13_EQ_2_16_AND_rg_am_ETC___d489 =
	     (rg_op == 2'd0 ||
	      rg_op == 2'd2 && rg_amo_funct7[6:2] == 5'b00010) &&
	     (ram_state_and_ctag_cset_b_read__00_BIT_52_01_A_ETC___d484 ||
	      NOT_ram_state_and_ctag_cset_b_read__00_BIT_52__ETC___d487) ;
  assign rg_op_13_EQ_0_14_OR_rg_op_13_EQ_2_16_AND_rg_am_ETC___d499 =
	     rg_op_13_EQ_0_14_OR_rg_op_13_EQ_2_16_AND_rg_am_ETC___d489 ||
	     rg_op != 2'd0 &&
	     (rg_op != 2'd2 || rg_amo_funct7[6:2] != 5'b00010) &&
	     rg_op_13_EQ_1_66_OR_rg_op_13_EQ_2_16_AND_rg_am_ETC___d497 ;
  assign rg_op_13_EQ_0_14_OR_rg_op_13_EQ_2_16_AND_rg_am_ETC___d503 =
	     (rg_op == 2'd0 ||
	      rg_op == 2'd2 && rg_amo_funct7[6:2] == 5'b00010) &&
	     (ram_state_and_ctag_cset$DOB[52] &&
	      ram_state_and_ctag_cset_b_read__00_BITS_51_TO__ETC___d205 ||
	      ram_state_and_ctag_cset$DOB[105] &&
	      ram_state_and_ctag_cset_b_read__00_BITS_104_TO_ETC___d211) ;
  assign rg_op_13_EQ_1_66_OR_rg_op_13_EQ_2_16_AND_rg_am_ETC___d497 =
	     rg_op == 2'd1 &&
	     IF_rg_priv_6_ULE_0b1_7_AND_rg_satp_9_BITS_63_T_ETC___d485 ||
	     rg_op == 2'd2 && rg_amo_funct7[6:2] == 5'b00011 ||
	     rg_op != 2'd1 &&
	     (rg_op != 2'd2 || rg_amo_funct7[6:2] != 5'b00011) &&
	     ram_state_and_ctag_cset_b_read__00_BIT_52_01_A_ETC___d495 ;
  assign rg_op_13_EQ_1_66_OR_rg_op_13_EQ_2_16_AND_rg_am_ETC___d720 =
	     (rg_op == 2'd1 ||
	      rg_op == 2'd2 && rg_amo_funct7[6:2] == 5'b00011) &&
	     NOT_rg_op_13_EQ_2_16_17_OR_NOT_rg_amo_funct7_1_ETC___d717 ||
	     NOT_rg_op_13_EQ_1_66_93_AND_NOT_rg_op_13_EQ_2__ETC___d719 ;
  assign rg_op_13_EQ_1_66_OR_rg_op_13_EQ_2_16_AND_rg_am_ETC___d850 =
	     (rg_op == 2'd1 ||
	      rg_op == 2'd2 && rg_amo_funct7[6:2] == 5'b00011) &&
	     (rg_op != 2'd2 || rg_amo_funct7[6:2] != 5'b00011 ||
	      rg_lrsc_valid &&
	      rg_lrsc_pa_70_EQ_IF_rg_priv_6_ULE_0b1_7_AND_rg_ETC___d271) ;
  assign rg_op_13_EQ_2_16_AND_rg_amo_funct7_18_BITS_6_T_ETC___d287 =
	     rg_op == 2'd2 && rg_amo_funct7[6:2] == 5'b00011 &&
	     lrsc_result__h21885 ||
	     f_fabric_write_reqs$FULL_N &&
	     NOT_ram_state_and_ctag_cset_b_read__00_BIT_52__ETC___d285 ;
  assign rg_priv_6_EQ_0b0_03_AND_NOT_tlb_lookup_rg_satp_ETC___d144 =
	     rg_priv == 2'b0 && !tlb$lookup[70] ||
	     rg_priv == 2'b01 && tlb$lookup[70] && !rg_sstatus_SUM ||
	     dmem_not_imem_OR_NOT_rg_op_13_EQ_0_14_15_AND_N_ETC___d127 &&
	     NOT_dmem_not_imem_28_OR_NOT_rg_op_13_EQ_0_14_1_ETC___d135 &&
	     (!dmem_not_imem || rg_op == 2'd0 ||
	      rg_op == 2'd2 && rg_amo_funct7[6:2] == 5'b00010 ||
	      !tlb$lookup[68]) ;
  assign rg_priv_6_EQ_0b0_03_AND_NOT_tlb_lookup_rg_satp_ETC___d157 =
	     rg_priv == 2'b0 && !tlb$lookup[70] ||
	     rg_priv == 2'b01 && tlb$lookup[70] && !rg_sstatus_SUM ||
	     !dmem_not_imem ||
	     !tlb$lookup[68] ;
  assign rg_priv_6_ULE_0b1_7_AND_rg_satp_9_BITS_63_TO_6_ETC___d153 =
	     rg_priv_6_ULE_0b1___d87 && rg_satp[63:60] == 4'd8 &&
	     tlb$lookup[130] &&
	     (rg_priv_6_EQ_0b0_03_AND_NOT_tlb_lookup_rg_satp_ETC___d144 ||
	      NOT_tlb_lookup_rg_satp_9_BITS_59_TO_44_6_rg_ad_ETC___d150) ;
  assign rg_priv_6_ULE_0b1_7_AND_rg_satp_9_BITS_63_TO_6_ETC___d352 =
	     rg_priv_6_ULE_0b1___d87 && rg_satp[63:60] == 4'd8 &&
	     !tlb$lookup[130] ||
	     (rg_priv_6_ULE_0b1_7_AND_rg_satp_9_BITS_63_TO_6_ETC___d153 ?
		tlb$RDY_lookup :
		NOT_rg_priv_6_ULE_0b1_7_8_OR_NOT_rg_satp_9_BIT_ETC___d350) ;
  assign rg_priv_6_ULE_0b1_7_AND_rg_satp_9_BITS_63_TO_6_ETC___d400 =
	     rg_priv_6_ULE_0b1___d87 && rg_satp[63:60] == 4'd8 &&
	     (rg_priv_6_EQ_0b0_03_AND_NOT_tlb_lookup_rg_satp_ETC___d144 ||
	      NOT_tlb_lookup_rg_satp_9_BITS_59_TO_44_6_rg_ad_ETC___d150) &&
	     tlb$lookup[130] ;
  assign rg_priv_6_ULE_0b1_7_AND_rg_satp_9_BITS_63_TO_6_ETC___d422 =
	     rg_priv_6_ULE_0b1___d87 && rg_satp[63:60] == 4'd8 &&
	     tlb$lookup[130] &&
	     NOT_rg_priv_6_EQ_0b0_03_78_OR_tlb_lookup_rg_sa_ETC___d415 &&
	     tlb$lookup[72] &&
	     tlb$lookup[73] &&
	     !pte___2__h6741[7] &&
	     rg_op != 2'd0 &&
	     (rg_op != 2'd2 || rg_amo_funct7[6:2] != 5'b00010) ;
  assign rg_priv_6_ULE_0b1_7_AND_rg_satp_9_BITS_63_TO_6_ETC___d439 =
	     rg_priv_6_ULE_0b1_7_AND_rg_satp_9_BITS_63_TO_6_ETC___d153 ||
	     dmem_not_imem && !soc_map$m_is_mem_addr ||
	     rg_op_13_EQ_0_14_OR_rg_op_13_EQ_2_16_AND_rg_am_ETC___d431 ||
	     NOT_rg_op_13_EQ_0_14_15_AND_NOT_rg_op_13_EQ_2__ETC___d436 ;
  assign rg_priv_6_ULE_0b1_7_AND_rg_satp_9_BITS_63_TO_6_ETC___d440 =
	     rg_priv_6_ULE_0b1___d87 && rg_satp[63:60] == 4'd8 &&
	     !tlb$lookup[130] ||
	     rg_priv_6_ULE_0b1_7_AND_rg_satp_9_BITS_63_TO_6_ETC___d439 ;
  assign rg_priv_6_ULE_0b1_7_AND_rg_satp_9_BITS_63_TO_6_ETC___d458 =
	     rg_priv_6_ULE_0b1___d87 && rg_satp[63:60] == 4'd8 &&
	     tlb$lookup[130] &&
	     NOT_rg_priv_6_EQ_0b0_03_78_OR_tlb_lookup_rg_sa_ETC___d453 &&
	     NOT_cfg_verbosity_read__1_ULT_2_49___d450 &&
	     dmem_not_imem &&
	     tlb$lookup[68] &&
	     tlb$lookup[73] ;
  assign rg_priv_6_ULE_0b1_7_AND_rg_satp_9_BITS_63_TO_6_ETC___d461 =
	     rg_priv_6_ULE_0b1_7_AND_rg_satp_9_BITS_63_TO_6_ETC___d422 &&
	     NOT_cfg_verbosity_read__1_ULT_2_49___d450 &&
	     (!dmem_not_imem || !tlb$lookup[68] || !tlb$lookup[73]) ;
  assign rg_priv_6_ULE_0b1___d87 = rg_priv <= 2'b01 ;
  assign rg_st_amo_val_BITS_31_TO_0__q33 = rg_st_amo_val[31:0] ;
  assign rg_state_1_EQ_13_148_AND_rg_op_13_EQ_0_14_OR_r_ETC___d1150 =
	     rg_state == 5'd13 &&
	     (rg_op == 2'd0 ||
	      rg_op == 2'd2 && rg_amo_funct7[6:2] == 5'b00010) &&
	     b__h28690 == 4'd0 ;
  assign satp_pa__h2068 = { 8'd0, x__h5093 } ;
  assign shift_bits__h3004 = { f_fabric_write_reqs$D_OUT[66:64], 3'b0 } ;
  assign strobe64__h3156 = 8'b00000001 << f_fabric_write_reqs$D_OUT[66:64] ;
  assign strobe64__h3159 = 8'b00000011 << f_fabric_write_reqs$D_OUT[66:64] ;
  assign strobe64__h3162 = 8'b00001111 << f_fabric_write_reqs$D_OUT[66:64] ;
  assign tlb_lookup_rg_satp_9_BITS_59_TO_44_6_rg_addr_7_ETC___d133 =
	     tlb$lookup[67] | y__h6567 ;
  assign tlb_lookup_rg_satp_9_BITS_59_TO_44_6_rg_addr_7_ETC___d394 =
	     tlb$lookup[72] &&
	     (rg_op == 2'd0 ||
	      rg_op == 2'd2 && rg_amo_funct7[6:2] == 5'b00010 ||
	      tlb$lookup[73]) ;
  assign tmp__h32030 = { 1'd0, rg_victim_way } ;
  assign tmp__h32031 = tmp__h32030 + 2'd1 ;
  assign value__h7066 =
	     (rg_priv_6_ULE_0b1___d87 && rg_satp[63:60] == 4'd8) ?
	       _theResult___snd_snd_fst__h6333 :
	       tlb$lookup[129:66] ;
  assign vpn_0_pa__h30718 = { 52'd0, rg_addr[20:12], 3'd0 } ;
  assign vpn_1_pa__h29685 = { 52'd0, rg_addr[29:21], 3'd0 } ;
  assign vpn_2_pa__h28788 = { 52'd0, rg_addr[38:30], 3'd0 } ;
  assign w17841_BITS_31_TO_0__q52 = w1__h37841[31:0] ;
  assign w1___1__h25809 =
	     { 32'd0,
	       IF_rg_f3_17_EQ_0b0_18_THEN_IF_rg_addr_7_BITS_2_ETC___d654[31:0] } ;
  assign w1___1__h37916 = { 32'd0, w1__h37841[31:0] } ;
  assign w2___1__h37917 = { 32'd0, rg_st_amo_val[31:0] } ;
  assign w2__h37847 = (rg_f3 == 3'b010) ? w2___1__h37917 : rg_st_amo_val ;
  assign word64759_BITS_15_TO_0__q16 = word64__h7759[15:0] ;
  assign word64759_BITS_15_TO_8__q18 = word64__h7759[15:8] ;
  assign word64759_BITS_23_TO_16__q19 = word64__h7759[23:16] ;
  assign word64759_BITS_31_TO_0__q17 = word64__h7759[31:0] ;
  assign word64759_BITS_31_TO_16__q20 = word64__h7759[31:16] ;
  assign word64759_BITS_31_TO_24__q21 = word64__h7759[31:24] ;
  assign word64759_BITS_39_TO_32__q23 = word64__h7759[39:32] ;
  assign word64759_BITS_47_TO_32__q24 = word64__h7759[47:32] ;
  assign word64759_BITS_47_TO_40__q22 = word64__h7759[47:40] ;
  assign word64759_BITS_55_TO_48__q26 = word64__h7759[55:48] ;
  assign word64759_BITS_63_TO_32__q25 = word64__h7759[63:32] ;
  assign word64759_BITS_63_TO_48__q27 = word64__h7759[63:48] ;
  assign word64759_BITS_63_TO_56__q28 = word64__h7759[63:56] ;
  assign word64759_BITS_7_TO_0__q15 = word64__h7759[7:0] ;
  assign word64__h7759 = x__h7910 | y__h7911 ;
  assign x1_avValue_exc_code__h6241 =
	     dmem_not_imem ?
	       ((rg_op == 2'd0 ||
		 rg_op == 2'd2 && rg_amo_funct7[6:2] == 5'b00010) ?
		  4'd13 :
		  4'd15) :
	       4'd12 ;
  assign x1_avValue_pa__h6240 = soc_map$m_is_mem_addr_addr ;
  assign x__h21895 = { 63'd0, lrsc_result__h21885 } ;
  assign x__h29765 = { master_xactor_f_rd_data$D_OUT[56:13], 12'b0 } ;
  assign x__h37836 =
	     (rg_f3 == 3'b010) ?
	       new_st_val__h37857 :
	       _theResult_____2__h37853 ;
  assign x__h5093 = { rg_satp[43:0], 12'b0 } ;
  assign x__h6752 = { tlb$lookup[119:76], rg_addr[11:0] } ;
  assign x__h6801 = { tlb$lookup[119:85], rg_addr[20:0] } ;
  assign x__h6870 = { tlb$lookup[119:94], rg_addr[29:0] } ;
  assign x__h7910 = ram_cword_set$DOB[63:0] & y__h7925 ;
  assign y__h14240 =
	     {64{ram_state_and_ctag_cset$DOB[105] &&
		 ram_state_and_ctag_cset_b_read__00_BITS_104_TO_ETC___d211}} ;
  assign y__h6567 = rg_mstatus_MXR & tlb$lookup[69] ;
  assign y__h7911 = ram_cword_set$DOB[127:64] & y__h14240 ;
  assign y__h7925 =
	     {64{ram_state_and_ctag_cset$DOB[52] &&
		 ram_state_and_ctag_cset_b_read__00_BITS_51_TO__ETC___d205}} ;
  always@(f_fabric_write_reqs$D_OUT)
  begin
    case (f_fabric_write_reqs$D_OUT[129:128])
      2'b0: x__h3037 = 3'b0;
      2'b01: x__h3037 = 3'b001;
      2'b10: x__h3037 = 3'b010;
      2'b11: x__h3037 = 3'b011;
    endcase
  end
  always@(rg_f3)
  begin
    case (rg_f3[1:0])
      2'b0: value__h37393 = 3'b0;
      2'b01: value__h37393 = 3'b001;
      2'b10: value__h37393 = 3'b010;
      2'd3: value__h37393 = 3'b011;
    endcase
  end
  always@(tlb$lookup or
	  rg_addr or pa___1__h6749 or pa___1__h6798 or pa___1__h6867)
  begin
    case (tlb$lookup[65:64])
      2'd0: _theResult___fst__h6743 = pa___1__h6749;
      2'd1: _theResult___fst__h6743 = pa___1__h6798;
      2'd2: _theResult___fst__h6743 = pa___1__h6867;
      2'd3: _theResult___fst__h6743 = rg_addr;
    endcase
  end
  always@(f_fabric_write_reqs$D_OUT or
	  strobe64__h3156 or strobe64__h3159 or strobe64__h3162)
  begin
    case (f_fabric_write_reqs$D_OUT[129:128])
      2'b0: mem_req_wr_data_wstrb__h3222 = strobe64__h3156;
      2'b01: mem_req_wr_data_wstrb__h3222 = strobe64__h3159;
      2'b10: mem_req_wr_data_wstrb__h3222 = strobe64__h3162;
      2'b11: mem_req_wr_data_wstrb__h3222 = 8'b11111111;
    endcase
  end
  always@(f_fabric_write_reqs$D_OUT or _theResult___fst__h3157)
  begin
    case (f_fabric_write_reqs$D_OUT[129:128])
      2'b0, 2'b01, 2'b10:
	  mem_req_wr_data_wdata__h3221 = _theResult___fst__h3157;
      2'd3: mem_req_wr_data_wdata__h3221 = f_fabric_write_reqs$D_OUT[63:0];
    endcase
  end
  always@(ram_state_and_ctag_cset$DOB or
	  ram_state_and_ctag_cset_b_read__00_BITS_104_TO_ETC___d211 or
	  ram_cword_set$DOB)
  begin
    case (ram_state_and_ctag_cset$DOB[105] &&
	  ram_state_and_ctag_cset_b_read__00_BITS_104_TO_ETC___d211)
      1'd0: old_cword__h22663 = ram_cword_set$DOB[63:0];
      1'd1: old_cword__h22663 = ram_cword_set$DOB[127:64];
    endcase
  end
  always@(rg_f3 or
	  NOT_ram_state_and_ctag_cset_b_read__00_BIT_105_ETC___d236 or
	  rg_priv_6_ULE_0b1___d87 or rg_satp or tlb$RDY_lookup)
  begin
    case (rg_f3)
      3'b0, 3'b001, 3'b010:
	  IF_rg_f3_17_EQ_0b0_18_OR_rg_f3_17_EQ_0b1_42_OR_ETC___d279 =
	      !rg_priv_6_ULE_0b1___d87 || rg_satp[63:60] != 4'd8 ||
	      tlb$RDY_lookup;
      default: IF_rg_f3_17_EQ_0b0_18_OR_rg_f3_17_EQ_0b1_42_OR_ETC___d279 =
		   rg_f3 == 3'b011 ||
		   NOT_ram_state_and_ctag_cset_b_read__00_BIT_105_ETC___d236;
    endcase
  end
  always@(rg_addr or
	  NOT_ram_state_and_ctag_cset_b_read__00_BIT_52__ETC___d235 or
	  NOT_ram_state_and_ctag_cset_b_read__00_BIT_105_ETC___d236)
  begin
    case (rg_addr[2:0])
      3'h0, 3'h1, 3'h2, 3'h3, 3'h4, 3'h5, 3'h6:
	  IF_rg_addr_7_BITS_2_TO_0_21_EQ_0x0_22_OR_rg_ad_ETC___d241 =
	      NOT_ram_state_and_ctag_cset_b_read__00_BIT_52__ETC___d235 &&
	      NOT_ram_state_and_ctag_cset_b_read__00_BIT_105_ETC___d236;
      3'd7:
	  IF_rg_addr_7_BITS_2_TO_0_21_EQ_0x0_22_OR_rg_ad_ETC___d241 =
	      rg_addr[2:0] != 3'h7 ||
	      NOT_ram_state_and_ctag_cset_b_read__00_BIT_52__ETC___d235 &&
	      NOT_ram_state_and_ctag_cset_b_read__00_BIT_105_ETC___d236;
    endcase
  end
  always@(rg_addr or
	  NOT_ram_state_and_ctag_cset_b_read__00_BIT_52__ETC___d235 or
	  NOT_ram_state_and_ctag_cset_b_read__00_BIT_105_ETC___d236)
  begin
    case (rg_addr[2:0])
      3'h0, 3'h2, 3'h4:
	  IF_rg_addr_7_BITS_2_TO_0_21_EQ_0x0_22_OR_rg_ad_ETC___d249 =
	      NOT_ram_state_and_ctag_cset_b_read__00_BIT_52__ETC___d235 &&
	      NOT_ram_state_and_ctag_cset_b_read__00_BIT_105_ETC___d236;
      default: IF_rg_addr_7_BITS_2_TO_0_21_EQ_0x0_22_OR_rg_ad_ETC___d249 =
		   rg_addr[2:0] != 3'h6 ||
		   NOT_ram_state_and_ctag_cset_b_read__00_BIT_52__ETC___d235 &&
		   NOT_ram_state_and_ctag_cset_b_read__00_BIT_105_ETC___d236;
    endcase
  end
  always@(rg_f3 or
	  rg_addr or
	  NOT_ram_state_and_ctag_cset_b_read__00_BIT_52__ETC___d235 or
	  NOT_ram_state_and_ctag_cset_b_read__00_BIT_105_ETC___d236 or
	  IF_rg_addr_7_BITS_2_TO_0_21_EQ_0x0_22_OR_rg_ad_ETC___d241 or
	  IF_rg_addr_7_BITS_2_TO_0_21_EQ_0x0_22_OR_rg_ad_ETC___d249 or
	  IF_rg_addr_7_BITS_2_TO_0_21_EQ_0x0_22_THEN_NOT_ETC___d255)
  begin
    case (rg_f3)
      3'b0, 3'b100:
	  IF_rg_f3_17_EQ_0b0_18_OR_rg_f3_17_EQ_0b100_19__ETC___d263 =
	      IF_rg_addr_7_BITS_2_TO_0_21_EQ_0x0_22_OR_rg_ad_ETC___d241;
      3'b001, 3'b101:
	  IF_rg_f3_17_EQ_0b0_18_OR_rg_f3_17_EQ_0b100_19__ETC___d263 =
	      IF_rg_addr_7_BITS_2_TO_0_21_EQ_0x0_22_OR_rg_ad_ETC___d249;
      3'b010, 3'b110:
	  IF_rg_f3_17_EQ_0b0_18_OR_rg_f3_17_EQ_0b100_19__ETC___d263 =
	      IF_rg_addr_7_BITS_2_TO_0_21_EQ_0x0_22_THEN_NOT_ETC___d255;
      default: IF_rg_f3_17_EQ_0b0_18_OR_rg_f3_17_EQ_0b100_19__ETC___d263 =
		   rg_f3 != 3'b011 || rg_addr[2:0] != 3'h0 ||
		   NOT_ram_state_and_ctag_cset_b_read__00_BIT_52__ETC___d235 &&
		   NOT_ram_state_and_ctag_cset_b_read__00_BIT_105_ETC___d236;
    endcase
  end
  always@(rg_amo_funct7 or
	  IF_rg_f3_17_EQ_0b0_18_OR_rg_f3_17_EQ_0b100_19__ETC___d263)
  begin
    case (rg_amo_funct7[6:2])
      5'b0, 5'b00100, 5'b01000, 5'b01100, 5'b10000, 5'b11000, 5'b11100:
	  CASE_rg_amo_funct7_BITS_6_TO_2_0b0_IF_rg_f3_17_ETC__q29 =
	      IF_rg_f3_17_EQ_0b0_18_OR_rg_f3_17_EQ_0b100_19__ETC___d263;
      default: CASE_rg_amo_funct7_BITS_6_TO_2_0b0_IF_rg_f3_17_ETC__q29 =
		   rg_amo_funct7[6:2] != 5'b10100 ||
		   IF_rg_f3_17_EQ_0b0_18_OR_rg_f3_17_EQ_0b100_19__ETC___d263;
    endcase
  end
  always@(x1_avValue_pa__h6240 or
	  NOT_IF_rg_priv_6_ULE_0b1_7_AND_rg_satp_9_BITS__ETC___d329 or
	  CASE_rg_amo_funct7_BITS_6_TO_2_0b0_IF_rg_f3_17_ETC__q29)
  begin
    case (x1_avValue_pa__h6240[2:0])
      3'h0, 3'h2, 3'h4:
	  IF_IF_rg_priv_6_ULE_0b1_7_AND_rg_satp_9_BITS_6_ETC___d330 =
	      CASE_rg_amo_funct7_BITS_6_TO_2_0b0_IF_rg_f3_17_ETC__q29;
      default: IF_IF_rg_priv_6_ULE_0b1_7_AND_rg_satp_9_BITS_6_ETC___d330 =
		   NOT_IF_rg_priv_6_ULE_0b1_7_AND_rg_satp_9_BITS__ETC___d329;
    endcase
  end
  always@(x1_avValue_pa__h6240 or
	  NOT_IF_rg_priv_6_ULE_0b1_7_AND_rg_satp_9_BITS__ETC___d323 or
	  CASE_rg_amo_funct7_BITS_6_TO_2_0b0_IF_rg_f3_17_ETC__q29)
  begin
    case (x1_avValue_pa__h6240[2:0])
      3'h0, 3'h1, 3'h2, 3'h3, 3'h4, 3'h5, 3'h6:
	  IF_IF_rg_priv_6_ULE_0b1_7_AND_rg_satp_9_BITS_6_ETC___d324 =
	      CASE_rg_amo_funct7_BITS_6_TO_2_0b0_IF_rg_f3_17_ETC__q29;
      3'd7:
	  IF_IF_rg_priv_6_ULE_0b1_7_AND_rg_satp_9_BITS_6_ETC___d324 =
	      NOT_IF_rg_priv_6_ULE_0b1_7_AND_rg_satp_9_BITS__ETC___d323;
    endcase
  end
  always@(rg_f3 or
	  NOT_ram_state_and_ctag_cset_b_read__00_BIT_105_ETC___d236 or
	  rg_priv_6_ULE_0b1___d87 or
	  rg_satp or
	  tlb$RDY_lookup or
	  IF_IF_rg_priv_6_ULE_0b1_7_AND_rg_satp_9_BITS_6_ETC___d324 or
	  IF_IF_rg_priv_6_ULE_0b1_7_AND_rg_satp_9_BITS_6_ETC___d330 or
	  IF_IF_rg_priv_6_ULE_0b1_7_AND_rg_satp_9_BITS_6_ETC___d334 or
	  CASE_rg_amo_funct7_BITS_6_TO_2_0b0_IF_rg_f3_17_ETC__q29)
  begin
    case (rg_f3)
      3'b0:
	  IF_rg_f3_17_EQ_0b0_18_THEN_NOT_rg_priv_6_ULE_0_ETC___d339 =
	      (!rg_priv_6_ULE_0b1___d87 || rg_satp[63:60] != 4'd8 ||
	       tlb$RDY_lookup) &&
	      IF_IF_rg_priv_6_ULE_0b1_7_AND_rg_satp_9_BITS_6_ETC___d324;
      3'b001:
	  IF_rg_f3_17_EQ_0b0_18_THEN_NOT_rg_priv_6_ULE_0_ETC___d339 =
	      (!rg_priv_6_ULE_0b1___d87 || rg_satp[63:60] != 4'd8 ||
	       tlb$RDY_lookup) &&
	      IF_IF_rg_priv_6_ULE_0b1_7_AND_rg_satp_9_BITS_6_ETC___d330;
      3'b010:
	  IF_rg_f3_17_EQ_0b0_18_THEN_NOT_rg_priv_6_ULE_0_ETC___d339 =
	      (!rg_priv_6_ULE_0b1___d87 || rg_satp[63:60] != 4'd8 ||
	       tlb$RDY_lookup) &&
	      IF_IF_rg_priv_6_ULE_0b1_7_AND_rg_satp_9_BITS_6_ETC___d334;
      3'b011:
	  IF_rg_f3_17_EQ_0b0_18_THEN_NOT_rg_priv_6_ULE_0_ETC___d339 =
	      CASE_rg_amo_funct7_BITS_6_TO_2_0b0_IF_rg_f3_17_ETC__q29;
      default: IF_rg_f3_17_EQ_0b0_18_THEN_NOT_rg_priv_6_ULE_0_ETC___d339 =
		   NOT_ram_state_and_ctag_cset_b_read__00_BIT_105_ETC___d236;
    endcase
  end
  always@(rg_addr or
	  result__h20596 or
	  result__h20624 or
	  result__h20652 or
	  result__h20680 or
	  result__h20708 or
	  result__h20736 or result__h20764 or result__h20792)
  begin
    case (rg_addr[2:0])
      3'h0:
	  IF_rg_addr_7_BITS_2_TO_0_21_EQ_0x0_22_THEN_SEX_ETC___d600 =
	      result__h20596;
      3'h1:
	  IF_rg_addr_7_BITS_2_TO_0_21_EQ_0x0_22_THEN_SEX_ETC___d600 =
	      result__h20624;
      3'h2:
	  IF_rg_addr_7_BITS_2_TO_0_21_EQ_0x0_22_THEN_SEX_ETC___d600 =
	      result__h20652;
      3'h3:
	  IF_rg_addr_7_BITS_2_TO_0_21_EQ_0x0_22_THEN_SEX_ETC___d600 =
	      result__h20680;
      3'h4:
	  IF_rg_addr_7_BITS_2_TO_0_21_EQ_0x0_22_THEN_SEX_ETC___d600 =
	      result__h20708;
      3'h5:
	  IF_rg_addr_7_BITS_2_TO_0_21_EQ_0x0_22_THEN_SEX_ETC___d600 =
	      result__h20736;
      3'h6:
	  IF_rg_addr_7_BITS_2_TO_0_21_EQ_0x0_22_THEN_SEX_ETC___d600 =
	      result__h20764;
      3'h7:
	  IF_rg_addr_7_BITS_2_TO_0_21_EQ_0x0_22_THEN_SEX_ETC___d600 =
	      result__h20792;
    endcase
  end
  always@(rg_addr or
	  result__h20837 or
	  result__h20865 or
	  result__h20893 or
	  result__h20921 or
	  result__h20949 or
	  result__h20977 or result__h21005 or result__h21033)
  begin
    case (rg_addr[2:0])
      3'h0:
	  IF_rg_addr_7_BITS_2_TO_0_21_EQ_0x0_22_THEN_0_C_ETC___d616 =
	      result__h20837;
      3'h1:
	  IF_rg_addr_7_BITS_2_TO_0_21_EQ_0x0_22_THEN_0_C_ETC___d616 =
	      result__h20865;
      3'h2:
	  IF_rg_addr_7_BITS_2_TO_0_21_EQ_0x0_22_THEN_0_C_ETC___d616 =
	      result__h20893;
      3'h3:
	  IF_rg_addr_7_BITS_2_TO_0_21_EQ_0x0_22_THEN_0_C_ETC___d616 =
	      result__h20921;
      3'h4:
	  IF_rg_addr_7_BITS_2_TO_0_21_EQ_0x0_22_THEN_0_C_ETC___d616 =
	      result__h20949;
      3'h5:
	  IF_rg_addr_7_BITS_2_TO_0_21_EQ_0x0_22_THEN_0_C_ETC___d616 =
	      result__h20977;
      3'h6:
	  IF_rg_addr_7_BITS_2_TO_0_21_EQ_0x0_22_THEN_0_C_ETC___d616 =
	      result__h21005;
      3'h7:
	  IF_rg_addr_7_BITS_2_TO_0_21_EQ_0x0_22_THEN_0_C_ETC___d616 =
	      result__h21033;
    endcase
  end
  always@(rg_addr or
	  result__h21078 or
	  result__h21106 or result__h21134 or result__h21162)
  begin
    case (rg_addr[2:0])
      3'h0:
	  IF_rg_addr_7_BITS_2_TO_0_21_EQ_0x0_22_THEN_SEX_ETC___d628 =
	      result__h21078;
      3'h2:
	  IF_rg_addr_7_BITS_2_TO_0_21_EQ_0x0_22_THEN_SEX_ETC___d628 =
	      result__h21106;
      3'h4:
	  IF_rg_addr_7_BITS_2_TO_0_21_EQ_0x0_22_THEN_SEX_ETC___d628 =
	      result__h21134;
      3'h6:
	  IF_rg_addr_7_BITS_2_TO_0_21_EQ_0x0_22_THEN_SEX_ETC___d628 =
	      result__h21162;
      default: IF_rg_addr_7_BITS_2_TO_0_21_EQ_0x0_22_THEN_SEX_ETC___d628 =
		   64'd0;
    endcase
  end
  always@(rg_addr or
	  result__h21203 or
	  result__h21231 or result__h21259 or result__h21287)
  begin
    case (rg_addr[2:0])
      3'h0:
	  IF_rg_addr_7_BITS_2_TO_0_21_EQ_0x0_22_THEN_0_C_ETC___d636 =
	      result__h21203;
      3'h2:
	  IF_rg_addr_7_BITS_2_TO_0_21_EQ_0x0_22_THEN_0_C_ETC___d636 =
	      result__h21231;
      3'h4:
	  IF_rg_addr_7_BITS_2_TO_0_21_EQ_0x0_22_THEN_0_C_ETC___d636 =
	      result__h21259;
      3'h6:
	  IF_rg_addr_7_BITS_2_TO_0_21_EQ_0x0_22_THEN_0_C_ETC___d636 =
	      result__h21287;
      default: IF_rg_addr_7_BITS_2_TO_0_21_EQ_0x0_22_THEN_0_C_ETC___d636 =
		   64'd0;
    endcase
  end
  always@(rg_addr or result__h21395 or result__h21423)
  begin
    case (rg_addr[2:0])
      3'h0:
	  IF_rg_addr_7_BITS_2_TO_0_21_EQ_0x0_22_THEN_0_C_ETC___d646 =
	      result__h21395;
      3'h4:
	  IF_rg_addr_7_BITS_2_TO_0_21_EQ_0x0_22_THEN_0_C_ETC___d646 =
	      result__h21423;
      default: IF_rg_addr_7_BITS_2_TO_0_21_EQ_0x0_22_THEN_0_C_ETC___d646 =
		   64'd0;
    endcase
  end
  always@(rg_addr or result__h21328 or result__h21356)
  begin
    case (rg_addr[2:0])
      3'h0:
	  CASE_rg_addr_BITS_2_TO_0_0x0_result1328_0x4_re_ETC__q30 =
	      result__h21328;
      3'h4:
	  CASE_rg_addr_BITS_2_TO_0_0x0_result1328_0x4_re_ETC__q30 =
	      result__h21356;
      default: CASE_rg_addr_BITS_2_TO_0_0x0_result1328_0x4_re_ETC__q30 =
		   64'd0;
    endcase
  end
  always@(rg_f3 or
	  IF_rg_addr_7_BITS_2_TO_0_21_EQ_0x0_22_THEN_SEX_ETC___d600 or
	  IF_rg_addr_7_BITS_2_TO_0_21_EQ_0x0_22_THEN_SEX_ETC___d628 or
	  CASE_rg_addr_BITS_2_TO_0_0x0_result1328_0x4_re_ETC__q30 or
	  IF_rg_addr_7_BITS_2_TO_0_21_EQ_0x0_22_THEN_ram_ETC___d647 or
	  IF_rg_addr_7_BITS_2_TO_0_21_EQ_0x0_22_THEN_0_C_ETC___d616 or
	  IF_rg_addr_7_BITS_2_TO_0_21_EQ_0x0_22_THEN_0_C_ETC___d636 or
	  IF_rg_addr_7_BITS_2_TO_0_21_EQ_0x0_22_THEN_0_C_ETC___d646)
  begin
    case (rg_f3)
      3'b0:
	  IF_rg_f3_17_EQ_0b0_18_THEN_IF_rg_addr_7_BITS_2_ETC___d654 =
	      IF_rg_addr_7_BITS_2_TO_0_21_EQ_0x0_22_THEN_SEX_ETC___d600;
      3'b001:
	  IF_rg_f3_17_EQ_0b0_18_THEN_IF_rg_addr_7_BITS_2_ETC___d654 =
	      IF_rg_addr_7_BITS_2_TO_0_21_EQ_0x0_22_THEN_SEX_ETC___d628;
      3'b010:
	  IF_rg_f3_17_EQ_0b0_18_THEN_IF_rg_addr_7_BITS_2_ETC___d654 =
	      CASE_rg_addr_BITS_2_TO_0_0x0_result1328_0x4_re_ETC__q30;
      3'b011:
	  IF_rg_f3_17_EQ_0b0_18_THEN_IF_rg_addr_7_BITS_2_ETC___d654 =
	      IF_rg_addr_7_BITS_2_TO_0_21_EQ_0x0_22_THEN_ram_ETC___d647;
      3'b100:
	  IF_rg_f3_17_EQ_0b0_18_THEN_IF_rg_addr_7_BITS_2_ETC___d654 =
	      IF_rg_addr_7_BITS_2_TO_0_21_EQ_0x0_22_THEN_0_C_ETC___d616;
      3'b101:
	  IF_rg_f3_17_EQ_0b0_18_THEN_IF_rg_addr_7_BITS_2_ETC___d654 =
	      IF_rg_addr_7_BITS_2_TO_0_21_EQ_0x0_22_THEN_0_C_ETC___d636;
      3'b110:
	  IF_rg_f3_17_EQ_0b0_18_THEN_IF_rg_addr_7_BITS_2_ETC___d654 =
	      IF_rg_addr_7_BITS_2_TO_0_21_EQ_0x0_22_THEN_0_C_ETC___d646;
      3'd7: IF_rg_f3_17_EQ_0b0_18_THEN_IF_rg_addr_7_BITS_2_ETC___d654 = 64'd0;
    endcase
  end
  always@(rg_f3 or
	  IF_rg_addr_7_BITS_2_TO_0_21_EQ_0x0_22_THEN_SEX_ETC___d600 or
	  IF_rg_addr_7_BITS_2_TO_0_21_EQ_0x0_22_THEN_SEX_ETC___d628 or
	  w1___1__h25809 or
	  IF_rg_addr_7_BITS_2_TO_0_21_EQ_0x0_22_THEN_ram_ETC___d647 or
	  IF_rg_addr_7_BITS_2_TO_0_21_EQ_0x0_22_THEN_0_C_ETC___d616 or
	  IF_rg_addr_7_BITS_2_TO_0_21_EQ_0x0_22_THEN_0_C_ETC___d636 or
	  IF_rg_addr_7_BITS_2_TO_0_21_EQ_0x0_22_THEN_0_C_ETC___d646)
  begin
    case (rg_f3)
      3'b0:
	  w1__h25738 =
	      IF_rg_addr_7_BITS_2_TO_0_21_EQ_0x0_22_THEN_SEX_ETC___d600;
      3'b001:
	  w1__h25738 =
	      IF_rg_addr_7_BITS_2_TO_0_21_EQ_0x0_22_THEN_SEX_ETC___d628;
      3'b010: w1__h25738 = w1___1__h25809;
      3'b011:
	  w1__h25738 =
	      IF_rg_addr_7_BITS_2_TO_0_21_EQ_0x0_22_THEN_ram_ETC___d647;
      3'b100:
	  w1__h25738 =
	      IF_rg_addr_7_BITS_2_TO_0_21_EQ_0x0_22_THEN_0_C_ETC___d616;
      3'b101:
	  w1__h25738 =
	      IF_rg_addr_7_BITS_2_TO_0_21_EQ_0x0_22_THEN_0_C_ETC___d636;
      3'b110:
	  w1__h25738 =
	      IF_rg_addr_7_BITS_2_TO_0_21_EQ_0x0_22_THEN_0_C_ETC___d646;
      3'd7: w1__h25738 = 64'd0;
    endcase
  end
  always@(x1_avValue_pa__h6240 or old_cword__h22663 or rg_st_amo_val)
  begin
    case (x1_avValue_pa__h6240[2:0])
      3'h0:
	  IF_IF_rg_priv_6_ULE_0b1_7_AND_rg_satp_9_BITS_6_ETC___d768 =
	      { old_cword__h22663[63:16], rg_st_amo_val[15:0] };
      3'h2:
	  IF_IF_rg_priv_6_ULE_0b1_7_AND_rg_satp_9_BITS_6_ETC___d768 =
	      { old_cword__h22663[63:32],
		rg_st_amo_val[15:0],
		old_cword__h22663[15:0] };
      3'h4:
	  IF_IF_rg_priv_6_ULE_0b1_7_AND_rg_satp_9_BITS_6_ETC___d768 =
	      { old_cword__h22663[63:48],
		rg_st_amo_val[15:0],
		old_cword__h22663[31:0] };
      3'h6:
	  IF_IF_rg_priv_6_ULE_0b1_7_AND_rg_satp_9_BITS_6_ETC___d768 =
	      { rg_st_amo_val[15:0], old_cword__h22663[47:0] };
      default: IF_IF_rg_priv_6_ULE_0b1_7_AND_rg_satp_9_BITS_6_ETC___d768 =
		   old_cword__h22663;
    endcase
  end
  always@(x1_avValue_pa__h6240 or old_cword__h22663 or rg_st_amo_val)
  begin
    case (x1_avValue_pa__h6240[2:0])
      3'h0:
	  IF_IF_rg_priv_6_ULE_0b1_7_AND_rg_satp_9_BITS_6_ETC___d759 =
	      { old_cword__h22663[63:8], rg_st_amo_val[7:0] };
      3'h1:
	  IF_IF_rg_priv_6_ULE_0b1_7_AND_rg_satp_9_BITS_6_ETC___d759 =
	      { old_cword__h22663[63:16],
		rg_st_amo_val[7:0],
		old_cword__h22663[7:0] };
      3'h2:
	  IF_IF_rg_priv_6_ULE_0b1_7_AND_rg_satp_9_BITS_6_ETC___d759 =
	      { old_cword__h22663[63:24],
		rg_st_amo_val[7:0],
		old_cword__h22663[15:0] };
      3'h3:
	  IF_IF_rg_priv_6_ULE_0b1_7_AND_rg_satp_9_BITS_6_ETC___d759 =
	      { old_cword__h22663[63:32],
		rg_st_amo_val[7:0],
		old_cword__h22663[23:0] };
      3'h4:
	  IF_IF_rg_priv_6_ULE_0b1_7_AND_rg_satp_9_BITS_6_ETC___d759 =
	      { old_cword__h22663[63:40],
		rg_st_amo_val[7:0],
		old_cword__h22663[31:0] };
      3'h5:
	  IF_IF_rg_priv_6_ULE_0b1_7_AND_rg_satp_9_BITS_6_ETC___d759 =
	      { old_cword__h22663[63:48],
		rg_st_amo_val[7:0],
		old_cword__h22663[39:0] };
      3'h6:
	  IF_IF_rg_priv_6_ULE_0b1_7_AND_rg_satp_9_BITS_6_ETC___d759 =
	      { old_cword__h22663[63:56],
		rg_st_amo_val[7:0],
		old_cword__h22663[47:0] };
      3'h7:
	  IF_IF_rg_priv_6_ULE_0b1_7_AND_rg_satp_9_BITS_6_ETC___d759 =
	      { rg_st_amo_val[7:0], old_cword__h22663[55:0] };
    endcase
  end
  always@(x1_avValue_pa__h6240 or old_cword__h22663 or rg_st_amo_val)
  begin
    case (x1_avValue_pa__h6240[2:0])
      3'h0:
	  CASE_x1_avValue_pa240_BITS_2_TO_0_0x0_old_cwor_ETC__q31 =
	      { old_cword__h22663[63:32], rg_st_amo_val[31:0] };
      3'h4:
	  CASE_x1_avValue_pa240_BITS_2_TO_0_0x0_old_cwor_ETC__q31 =
	      { rg_st_amo_val[31:0], old_cword__h22663[31:0] };
      default: CASE_x1_avValue_pa240_BITS_2_TO_0_0x0_old_cwor_ETC__q31 =
		   old_cword__h22663;
    endcase
  end
  always@(rg_f3 or
	  old_cword__h22663 or
	  IF_IF_rg_priv_6_ULE_0b1_7_AND_rg_satp_9_BITS_6_ETC___d759 or
	  IF_IF_rg_priv_6_ULE_0b1_7_AND_rg_satp_9_BITS_6_ETC___d768 or
	  CASE_x1_avValue_pa240_BITS_2_TO_0_0x0_old_cwor_ETC__q31 or
	  rg_st_amo_val)
  begin
    case (rg_f3)
      3'b0:
	  n__h22674 =
	      IF_IF_rg_priv_6_ULE_0b1_7_AND_rg_satp_9_BITS_6_ETC___d759;
      3'b001:
	  n__h22674 =
	      IF_IF_rg_priv_6_ULE_0b1_7_AND_rg_satp_9_BITS_6_ETC___d768;
      3'b010:
	  n__h22674 = CASE_x1_avValue_pa240_BITS_2_TO_0_0x0_old_cwor_ETC__q31;
      3'b011: n__h22674 = rg_st_amo_val;
      default: n__h22674 = old_cword__h22663;
    endcase
  end
  always@(rg_f3 or
	  IF_rg_addr_7_BITS_2_TO_0_21_EQ_0x0_22_THEN_SEX_ETC___d600 or
	  IF_rg_addr_7_BITS_2_TO_0_21_EQ_0x0_22_THEN_SEX_ETC___d628 or
	  IF_rg_f3_17_EQ_0b0_18_THEN_IF_rg_addr_7_BITS_2_ETC__q32 or
	  IF_rg_addr_7_BITS_2_TO_0_21_EQ_0x0_22_THEN_ram_ETC___d647 or
	  IF_rg_addr_7_BITS_2_TO_0_21_EQ_0x0_22_THEN_0_C_ETC___d616 or
	  IF_rg_addr_7_BITS_2_TO_0_21_EQ_0x0_22_THEN_0_C_ETC___d636 or
	  IF_rg_addr_7_BITS_2_TO_0_21_EQ_0x0_22_THEN_0_C_ETC___d646)
  begin
    case (rg_f3)
      3'b0:
	  IF_rg_f3_17_EQ_0b10_50_THEN_SEXT_IF_rg_f3_17_E_ETC___d715 =
	      IF_rg_addr_7_BITS_2_TO_0_21_EQ_0x0_22_THEN_SEX_ETC___d600;
      3'b001:
	  IF_rg_f3_17_EQ_0b10_50_THEN_SEXT_IF_rg_f3_17_E_ETC___d715 =
	      IF_rg_addr_7_BITS_2_TO_0_21_EQ_0x0_22_THEN_SEX_ETC___d628;
      3'b010:
	  IF_rg_f3_17_EQ_0b10_50_THEN_SEXT_IF_rg_f3_17_E_ETC___d715 =
	      { {32{IF_rg_f3_17_EQ_0b0_18_THEN_IF_rg_addr_7_BITS_2_ETC__q32[31]}},
		IF_rg_f3_17_EQ_0b0_18_THEN_IF_rg_addr_7_BITS_2_ETC__q32 };
      3'b011:
	  IF_rg_f3_17_EQ_0b10_50_THEN_SEXT_IF_rg_f3_17_E_ETC___d715 =
	      IF_rg_addr_7_BITS_2_TO_0_21_EQ_0x0_22_THEN_ram_ETC___d647;
      3'b100:
	  IF_rg_f3_17_EQ_0b10_50_THEN_SEXT_IF_rg_f3_17_E_ETC___d715 =
	      IF_rg_addr_7_BITS_2_TO_0_21_EQ_0x0_22_THEN_0_C_ETC___d616;
      3'b101:
	  IF_rg_f3_17_EQ_0b10_50_THEN_SEXT_IF_rg_f3_17_E_ETC___d715 =
	      IF_rg_addr_7_BITS_2_TO_0_21_EQ_0x0_22_THEN_0_C_ETC___d636;
      3'b110:
	  IF_rg_f3_17_EQ_0b10_50_THEN_SEXT_IF_rg_f3_17_E_ETC___d715 =
	      IF_rg_addr_7_BITS_2_TO_0_21_EQ_0x0_22_THEN_0_C_ETC___d646;
      3'd7: IF_rg_f3_17_EQ_0b10_50_THEN_SEXT_IF_rg_f3_17_E_ETC___d715 = 64'd0;
    endcase
  end
  always@(rg_amo_funct7 or
	  new_st_val__h26849 or
	  new_st_val__h25841 or
	  w2__h37847 or
	  new_st_val__h26821 or
	  new_st_val__h26829 or
	  new_st_val__h26825 or
	  new_st_val__h26844 or new_st_val__h26833 or new_st_val__h26838)
  begin
    case (rg_amo_funct7[6:2])
      5'b0: _theResult_____2__h25746 = new_st_val__h25841;
      5'b00001: _theResult_____2__h25746 = w2__h37847;
      5'b00100: _theResult_____2__h25746 = new_st_val__h26821;
      5'b01000: _theResult_____2__h25746 = new_st_val__h26829;
      5'b01100: _theResult_____2__h25746 = new_st_val__h26825;
      5'b10000: _theResult_____2__h25746 = new_st_val__h26844;
      5'b11000: _theResult_____2__h25746 = new_st_val__h26833;
      5'b11100: _theResult_____2__h25746 = new_st_val__h26838;
      default: _theResult_____2__h25746 = new_st_val__h26849;
    endcase
  end
  always@(x1_avValue_pa__h6240 or old_cword__h22663 or new_st_val__h25444)
  begin
    case (x1_avValue_pa__h6240[2:0])
      3'h0:
	  IF_IF_rg_priv_6_ULE_0b1_7_AND_rg_satp_9_BITS_6_ETC___d836 =
	      { old_cword__h22663[63:16], new_st_val__h25444[15:0] };
      3'h2:
	  IF_IF_rg_priv_6_ULE_0b1_7_AND_rg_satp_9_BITS_6_ETC___d836 =
	      { old_cword__h22663[63:32],
		new_st_val__h25444[15:0],
		old_cword__h22663[15:0] };
      3'h4:
	  IF_IF_rg_priv_6_ULE_0b1_7_AND_rg_satp_9_BITS_6_ETC___d836 =
	      { old_cword__h22663[63:48],
		new_st_val__h25444[15:0],
		old_cword__h22663[31:0] };
      3'h6:
	  IF_IF_rg_priv_6_ULE_0b1_7_AND_rg_satp_9_BITS_6_ETC___d836 =
	      { new_st_val__h25444[15:0], old_cword__h22663[47:0] };
      default: IF_IF_rg_priv_6_ULE_0b1_7_AND_rg_satp_9_BITS_6_ETC___d836 =
		   old_cword__h22663;
    endcase
  end
  always@(x1_avValue_pa__h6240 or old_cword__h22663 or new_st_val__h25444)
  begin
    case (x1_avValue_pa__h6240[2:0])
      3'h0:
	  IF_IF_rg_priv_6_ULE_0b1_7_AND_rg_satp_9_BITS_6_ETC___d827 =
	      { old_cword__h22663[63:8], new_st_val__h25444[7:0] };
      3'h1:
	  IF_IF_rg_priv_6_ULE_0b1_7_AND_rg_satp_9_BITS_6_ETC___d827 =
	      { old_cword__h22663[63:16],
		new_st_val__h25444[7:0],
		old_cword__h22663[7:0] };
      3'h2:
	  IF_IF_rg_priv_6_ULE_0b1_7_AND_rg_satp_9_BITS_6_ETC___d827 =
	      { old_cword__h22663[63:24],
		new_st_val__h25444[7:0],
		old_cword__h22663[15:0] };
      3'h3:
	  IF_IF_rg_priv_6_ULE_0b1_7_AND_rg_satp_9_BITS_6_ETC___d827 =
	      { old_cword__h22663[63:32],
		new_st_val__h25444[7:0],
		old_cword__h22663[23:0] };
      3'h4:
	  IF_IF_rg_priv_6_ULE_0b1_7_AND_rg_satp_9_BITS_6_ETC___d827 =
	      { old_cword__h22663[63:40],
		new_st_val__h25444[7:0],
		old_cword__h22663[31:0] };
      3'h5:
	  IF_IF_rg_priv_6_ULE_0b1_7_AND_rg_satp_9_BITS_6_ETC___d827 =
	      { old_cword__h22663[63:48],
		new_st_val__h25444[7:0],
		old_cword__h22663[39:0] };
      3'h6:
	  IF_IF_rg_priv_6_ULE_0b1_7_AND_rg_satp_9_BITS_6_ETC___d827 =
	      { old_cword__h22663[63:56],
		new_st_val__h25444[7:0],
		old_cword__h22663[47:0] };
      3'h7:
	  IF_IF_rg_priv_6_ULE_0b1_7_AND_rg_satp_9_BITS_6_ETC___d827 =
	      { new_st_val__h25444[7:0], old_cword__h22663[55:0] };
    endcase
  end
  always@(x1_avValue_pa__h6240 or old_cword__h22663 or new_st_val__h25444)
  begin
    case (x1_avValue_pa__h6240[2:0])
      3'h0:
	  CASE_x1_avValue_pa240_BITS_2_TO_0_0x0_old_cwor_ETC__q34 =
	      { old_cword__h22663[63:32], new_st_val__h25444[31:0] };
      3'h4:
	  CASE_x1_avValue_pa240_BITS_2_TO_0_0x0_old_cwor_ETC__q34 =
	      { new_st_val__h25444[31:0], old_cword__h22663[31:0] };
      default: CASE_x1_avValue_pa240_BITS_2_TO_0_0x0_old_cwor_ETC__q34 =
		   old_cword__h22663;
    endcase
  end
  always@(rg_f3 or
	  old_cword__h22663 or
	  IF_IF_rg_priv_6_ULE_0b1_7_AND_rg_satp_9_BITS_6_ETC___d827 or
	  IF_IF_rg_priv_6_ULE_0b1_7_AND_rg_satp_9_BITS_6_ETC___d836 or
	  CASE_x1_avValue_pa240_BITS_2_TO_0_0x0_old_cwor_ETC__q34 or
	  new_st_val__h25444)
  begin
    case (rg_f3)
      3'b0:
	  n__h25608 =
	      IF_IF_rg_priv_6_ULE_0b1_7_AND_rg_satp_9_BITS_6_ETC___d827;
      3'b001:
	  n__h25608 =
	      IF_IF_rg_priv_6_ULE_0b1_7_AND_rg_satp_9_BITS_6_ETC___d836;
      3'b010:
	  n__h25608 = CASE_x1_avValue_pa240_BITS_2_TO_0_0x0_old_cwor_ETC__q34;
      3'b011: n__h25608 = new_st_val__h25444;
      default: n__h25608 = old_cword__h22663;
    endcase
  end
  always@(rg_addr or
	  result__h36251 or
	  result__h36278 or result__h36305 or result__h36332)
  begin
    case (rg_addr[2:0])
      3'h0:
	  IF_rg_addr_7_BITS_2_TO_0_21_EQ_0x0_22_THEN_0_C_ETC___d1228 =
	      result__h36251;
      3'h2:
	  IF_rg_addr_7_BITS_2_TO_0_21_EQ_0x0_22_THEN_0_C_ETC___d1228 =
	      result__h36278;
      3'h4:
	  IF_rg_addr_7_BITS_2_TO_0_21_EQ_0x0_22_THEN_0_C_ETC___d1228 =
	      result__h36305;
      3'h6:
	  IF_rg_addr_7_BITS_2_TO_0_21_EQ_0x0_22_THEN_0_C_ETC___d1228 =
	      result__h36332;
      default: IF_rg_addr_7_BITS_2_TO_0_21_EQ_0x0_22_THEN_0_C_ETC___d1228 =
		   64'd0;
    endcase
  end
  always@(rg_addr or
	  result__h36130 or
	  result__h36157 or result__h36184 or result__h36211)
  begin
    case (rg_addr[2:0])
      3'h0:
	  IF_rg_addr_7_BITS_2_TO_0_21_EQ_0x0_22_THEN_SEX_ETC___d1220 =
	      result__h36130;
      3'h2:
	  IF_rg_addr_7_BITS_2_TO_0_21_EQ_0x0_22_THEN_SEX_ETC___d1220 =
	      result__h36157;
      3'h4:
	  IF_rg_addr_7_BITS_2_TO_0_21_EQ_0x0_22_THEN_SEX_ETC___d1220 =
	      result__h36184;
      3'h6:
	  IF_rg_addr_7_BITS_2_TO_0_21_EQ_0x0_22_THEN_SEX_ETC___d1220 =
	      result__h36211;
      default: IF_rg_addr_7_BITS_2_TO_0_21_EQ_0x0_22_THEN_SEX_ETC___d1220 =
		   64'd0;
    endcase
  end
  always@(rg_addr or
	  result__h35897 or
	  result__h35924 or
	  result__h35951 or
	  result__h35978 or
	  result__h36005 or
	  result__h36032 or result__h36059 or result__h36086)
  begin
    case (rg_addr[2:0])
      3'h0:
	  IF_rg_addr_7_BITS_2_TO_0_21_EQ_0x0_22_THEN_0_C_ETC___d1208 =
	      result__h35897;
      3'h1:
	  IF_rg_addr_7_BITS_2_TO_0_21_EQ_0x0_22_THEN_0_C_ETC___d1208 =
	      result__h35924;
      3'h2:
	  IF_rg_addr_7_BITS_2_TO_0_21_EQ_0x0_22_THEN_0_C_ETC___d1208 =
	      result__h35951;
      3'h3:
	  IF_rg_addr_7_BITS_2_TO_0_21_EQ_0x0_22_THEN_0_C_ETC___d1208 =
	      result__h35978;
      3'h4:
	  IF_rg_addr_7_BITS_2_TO_0_21_EQ_0x0_22_THEN_0_C_ETC___d1208 =
	      result__h36005;
      3'h5:
	  IF_rg_addr_7_BITS_2_TO_0_21_EQ_0x0_22_THEN_0_C_ETC___d1208 =
	      result__h36032;
      3'h6:
	  IF_rg_addr_7_BITS_2_TO_0_21_EQ_0x0_22_THEN_0_C_ETC___d1208 =
	      result__h36059;
      3'h7:
	  IF_rg_addr_7_BITS_2_TO_0_21_EQ_0x0_22_THEN_0_C_ETC___d1208 =
	      result__h36086;
    endcase
  end
  always@(rg_addr or
	  result__h35661 or
	  result__h35691 or
	  result__h35718 or
	  result__h35745 or
	  result__h35772 or
	  result__h35799 or result__h35826 or result__h35853)
  begin
    case (rg_addr[2:0])
      3'h0:
	  IF_rg_addr_7_BITS_2_TO_0_21_EQ_0x0_22_THEN_SEX_ETC___d1192 =
	      result__h35661;
      3'h1:
	  IF_rg_addr_7_BITS_2_TO_0_21_EQ_0x0_22_THEN_SEX_ETC___d1192 =
	      result__h35691;
      3'h2:
	  IF_rg_addr_7_BITS_2_TO_0_21_EQ_0x0_22_THEN_SEX_ETC___d1192 =
	      result__h35718;
      3'h3:
	  IF_rg_addr_7_BITS_2_TO_0_21_EQ_0x0_22_THEN_SEX_ETC___d1192 =
	      result__h35745;
      3'h4:
	  IF_rg_addr_7_BITS_2_TO_0_21_EQ_0x0_22_THEN_SEX_ETC___d1192 =
	      result__h35772;
      3'h5:
	  IF_rg_addr_7_BITS_2_TO_0_21_EQ_0x0_22_THEN_SEX_ETC___d1192 =
	      result__h35799;
      3'h6:
	  IF_rg_addr_7_BITS_2_TO_0_21_EQ_0x0_22_THEN_SEX_ETC___d1192 =
	      result__h35826;
      3'h7:
	  IF_rg_addr_7_BITS_2_TO_0_21_EQ_0x0_22_THEN_SEX_ETC___d1192 =
	      result__h35853;
    endcase
  end
  always@(rg_addr or result__h36372 or result__h36399)
  begin
    case (rg_addr[2:0])
      3'h0:
	  CASE_rg_addr_BITS_2_TO_0_0x0_result6372_0x4_re_ETC__q35 =
	      result__h36372;
      3'h4:
	  CASE_rg_addr_BITS_2_TO_0_0x0_result6372_0x4_re_ETC__q35 =
	      result__h36399;
      default: CASE_rg_addr_BITS_2_TO_0_0x0_result6372_0x4_re_ETC__q35 =
		   64'd0;
    endcase
  end
  always@(rg_addr or result__h36437 or result__h36464)
  begin
    case (rg_addr[2:0])
      3'h0:
	  CASE_rg_addr_BITS_2_TO_0_0x0_result6437_0x4_re_ETC__q36 =
	      result__h36437;
      3'h4:
	  CASE_rg_addr_BITS_2_TO_0_0x0_result6437_0x4_re_ETC__q36 =
	      result__h36464;
      default: CASE_rg_addr_BITS_2_TO_0_0x0_result6437_0x4_re_ETC__q36 =
		   64'd0;
    endcase
  end
  always@(rg_f3 or
	  IF_rg_addr_7_BITS_2_TO_0_21_EQ_0x0_22_THEN_SEX_ETC___d1192 or
	  IF_rg_addr_7_BITS_2_TO_0_21_EQ_0x0_22_THEN_SEX_ETC___d1220 or
	  CASE_rg_addr_BITS_2_TO_0_0x0_result6372_0x4_re_ETC__q35 or
	  rg_addr or
	  master_xactor_f_rd_data$D_OUT or
	  IF_rg_addr_7_BITS_2_TO_0_21_EQ_0x0_22_THEN_0_C_ETC___d1208 or
	  IF_rg_addr_7_BITS_2_TO_0_21_EQ_0x0_22_THEN_0_C_ETC___d1228 or
	  CASE_rg_addr_BITS_2_TO_0_0x0_result6437_0x4_re_ETC__q36)
  begin
    case (rg_f3)
      3'b0:
	  ld_val__h35601 =
	      IF_rg_addr_7_BITS_2_TO_0_21_EQ_0x0_22_THEN_SEX_ETC___d1192;
      3'b001:
	  ld_val__h35601 =
	      IF_rg_addr_7_BITS_2_TO_0_21_EQ_0x0_22_THEN_SEX_ETC___d1220;
      3'b010:
	  ld_val__h35601 =
	      CASE_rg_addr_BITS_2_TO_0_0x0_result6372_0x4_re_ETC__q35;
      3'b011:
	  ld_val__h35601 =
	      (rg_addr[2:0] == 3'h0) ?
		master_xactor_f_rd_data$D_OUT[66:3] :
		64'd0;
      3'b100:
	  ld_val__h35601 =
	      IF_rg_addr_7_BITS_2_TO_0_21_EQ_0x0_22_THEN_0_C_ETC___d1208;
      3'b101:
	  ld_val__h35601 =
	      IF_rg_addr_7_BITS_2_TO_0_21_EQ_0x0_22_THEN_0_C_ETC___d1228;
      3'b110:
	  ld_val__h35601 =
	      CASE_rg_addr_BITS_2_TO_0_0x0_result6437_0x4_re_ETC__q36;
      3'd7: ld_val__h35601 = 64'd0;
    endcase
  end
  always@(rg_addr or result__h39715 or result__h39743)
  begin
    case (rg_addr[2:0])
      3'h0:
	  IF_rg_addr_7_BITS_2_TO_0_21_EQ_0x0_22_THEN_0_C_ETC___d1347 =
	      result__h39715;
      3'h4:
	  IF_rg_addr_7_BITS_2_TO_0_21_EQ_0x0_22_THEN_0_C_ETC___d1347 =
	      result__h39743;
      default: IF_rg_addr_7_BITS_2_TO_0_21_EQ_0x0_22_THEN_0_C_ETC___d1347 =
		   64'd0;
    endcase
  end
  always@(rg_addr or
	  result__h39523 or
	  result__h39551 or result__h39579 or result__h39607)
  begin
    case (rg_addr[2:0])
      3'h0:
	  IF_rg_addr_7_BITS_2_TO_0_21_EQ_0x0_22_THEN_0_C_ETC___d1337 =
	      result__h39523;
      3'h2:
	  IF_rg_addr_7_BITS_2_TO_0_21_EQ_0x0_22_THEN_0_C_ETC___d1337 =
	      result__h39551;
      3'h4:
	  IF_rg_addr_7_BITS_2_TO_0_21_EQ_0x0_22_THEN_0_C_ETC___d1337 =
	      result__h39579;
      3'h6:
	  IF_rg_addr_7_BITS_2_TO_0_21_EQ_0x0_22_THEN_0_C_ETC___d1337 =
	      result__h39607;
      default: IF_rg_addr_7_BITS_2_TO_0_21_EQ_0x0_22_THEN_0_C_ETC___d1337 =
		   64'd0;
    endcase
  end
  always@(rg_addr or
	  result__h39157 or
	  result__h39185 or
	  result__h39213 or
	  result__h39241 or
	  result__h39269 or
	  result__h39297 or result__h39325 or result__h39353)
  begin
    case (rg_addr[2:0])
      3'h0:
	  IF_rg_addr_7_BITS_2_TO_0_21_EQ_0x0_22_THEN_0_C_ETC___d1317 =
	      result__h39157;
      3'h1:
	  IF_rg_addr_7_BITS_2_TO_0_21_EQ_0x0_22_THEN_0_C_ETC___d1317 =
	      result__h39185;
      3'h2:
	  IF_rg_addr_7_BITS_2_TO_0_21_EQ_0x0_22_THEN_0_C_ETC___d1317 =
	      result__h39213;
      3'h3:
	  IF_rg_addr_7_BITS_2_TO_0_21_EQ_0x0_22_THEN_0_C_ETC___d1317 =
	      result__h39241;
      3'h4:
	  IF_rg_addr_7_BITS_2_TO_0_21_EQ_0x0_22_THEN_0_C_ETC___d1317 =
	      result__h39269;
      3'h5:
	  IF_rg_addr_7_BITS_2_TO_0_21_EQ_0x0_22_THEN_0_C_ETC___d1317 =
	      result__h39297;
      3'h6:
	  IF_rg_addr_7_BITS_2_TO_0_21_EQ_0x0_22_THEN_0_C_ETC___d1317 =
	      result__h39325;
      3'h7:
	  IF_rg_addr_7_BITS_2_TO_0_21_EQ_0x0_22_THEN_0_C_ETC___d1317 =
	      result__h39353;
    endcase
  end
  always@(rg_addr or
	  result__h39398 or
	  result__h39426 or result__h39454 or result__h39482)
  begin
    case (rg_addr[2:0])
      3'h0:
	  IF_rg_addr_7_BITS_2_TO_0_21_EQ_0x0_22_THEN_SEX_ETC___d1329 =
	      result__h39398;
      3'h2:
	  IF_rg_addr_7_BITS_2_TO_0_21_EQ_0x0_22_THEN_SEX_ETC___d1329 =
	      result__h39426;
      3'h4:
	  IF_rg_addr_7_BITS_2_TO_0_21_EQ_0x0_22_THEN_SEX_ETC___d1329 =
	      result__h39454;
      3'h6:
	  IF_rg_addr_7_BITS_2_TO_0_21_EQ_0x0_22_THEN_SEX_ETC___d1329 =
	      result__h39482;
      default: IF_rg_addr_7_BITS_2_TO_0_21_EQ_0x0_22_THEN_SEX_ETC___d1329 =
		   64'd0;
    endcase
  end
  always@(rg_addr or
	  result__h38036 or
	  result__h38944 or
	  result__h38972 or
	  result__h39000 or
	  result__h39028 or
	  result__h39056 or result__h39084 or result__h39112)
  begin
    case (rg_addr[2:0])
      3'h0:
	  IF_rg_addr_7_BITS_2_TO_0_21_EQ_0x0_22_THEN_SEX_ETC___d1301 =
	      result__h38036;
      3'h1:
	  IF_rg_addr_7_BITS_2_TO_0_21_EQ_0x0_22_THEN_SEX_ETC___d1301 =
	      result__h38944;
      3'h2:
	  IF_rg_addr_7_BITS_2_TO_0_21_EQ_0x0_22_THEN_SEX_ETC___d1301 =
	      result__h38972;
      3'h3:
	  IF_rg_addr_7_BITS_2_TO_0_21_EQ_0x0_22_THEN_SEX_ETC___d1301 =
	      result__h39000;
      3'h4:
	  IF_rg_addr_7_BITS_2_TO_0_21_EQ_0x0_22_THEN_SEX_ETC___d1301 =
	      result__h39028;
      3'h5:
	  IF_rg_addr_7_BITS_2_TO_0_21_EQ_0x0_22_THEN_SEX_ETC___d1301 =
	      result__h39056;
      3'h6:
	  IF_rg_addr_7_BITS_2_TO_0_21_EQ_0x0_22_THEN_SEX_ETC___d1301 =
	      result__h39084;
      3'h7:
	  IF_rg_addr_7_BITS_2_TO_0_21_EQ_0x0_22_THEN_SEX_ETC___d1301 =
	      result__h39112;
    endcase
  end
  always@(rg_addr or result__h39648 or result__h39676)
  begin
    case (rg_addr[2:0])
      3'h0:
	  CASE_rg_addr_BITS_2_TO_0_0x0_result9648_0x4_re_ETC__q51 =
	      result__h39648;
      3'h4:
	  CASE_rg_addr_BITS_2_TO_0_0x0_result9648_0x4_re_ETC__q51 =
	      result__h39676;
      default: CASE_rg_addr_BITS_2_TO_0_0x0_result9648_0x4_re_ETC__q51 =
		   64'd0;
    endcase
  end
  always@(rg_f3 or
	  IF_rg_addr_7_BITS_2_TO_0_21_EQ_0x0_22_THEN_SEX_ETC___d1301 or
	  IF_rg_addr_7_BITS_2_TO_0_21_EQ_0x0_22_THEN_SEX_ETC___d1329 or
	  CASE_rg_addr_BITS_2_TO_0_0x0_result9648_0x4_re_ETC__q51 or
	  IF_rg_addr_7_BITS_2_TO_0_21_EQ_0x0_22_THEN_IF__ETC___d1348 or
	  IF_rg_addr_7_BITS_2_TO_0_21_EQ_0x0_22_THEN_0_C_ETC___d1317 or
	  IF_rg_addr_7_BITS_2_TO_0_21_EQ_0x0_22_THEN_0_C_ETC___d1337 or
	  IF_rg_addr_7_BITS_2_TO_0_21_EQ_0x0_22_THEN_0_C_ETC___d1347)
  begin
    case (rg_f3)
      3'b0:
	  w1__h37841 =
	      IF_rg_addr_7_BITS_2_TO_0_21_EQ_0x0_22_THEN_SEX_ETC___d1301;
      3'b001:
	  w1__h37841 =
	      IF_rg_addr_7_BITS_2_TO_0_21_EQ_0x0_22_THEN_SEX_ETC___d1329;
      3'b010:
	  w1__h37841 =
	      CASE_rg_addr_BITS_2_TO_0_0x0_result9648_0x4_re_ETC__q51;
      3'b011:
	  w1__h37841 =
	      IF_rg_addr_7_BITS_2_TO_0_21_EQ_0x0_22_THEN_IF__ETC___d1348;
      3'b100:
	  w1__h37841 =
	      IF_rg_addr_7_BITS_2_TO_0_21_EQ_0x0_22_THEN_0_C_ETC___d1317;
      3'b101:
	  w1__h37841 =
	      IF_rg_addr_7_BITS_2_TO_0_21_EQ_0x0_22_THEN_0_C_ETC___d1337;
      3'b110:
	  w1__h37841 =
	      IF_rg_addr_7_BITS_2_TO_0_21_EQ_0x0_22_THEN_0_C_ETC___d1347;
      3'd7: w1__h37841 = 64'd0;
    endcase
  end
  always@(rg_f3 or
	  IF_rg_addr_7_BITS_2_TO_0_21_EQ_0x0_22_THEN_SEX_ETC___d1301 or
	  IF_rg_addr_7_BITS_2_TO_0_21_EQ_0x0_22_THEN_SEX_ETC___d1329 or
	  w1___1__h37916 or
	  IF_rg_addr_7_BITS_2_TO_0_21_EQ_0x0_22_THEN_IF__ETC___d1348 or
	  IF_rg_addr_7_BITS_2_TO_0_21_EQ_0x0_22_THEN_0_C_ETC___d1317 or
	  IF_rg_addr_7_BITS_2_TO_0_21_EQ_0x0_22_THEN_0_C_ETC___d1337 or
	  IF_rg_addr_7_BITS_2_TO_0_21_EQ_0x0_22_THEN_0_C_ETC___d1347)
  begin
    case (rg_f3)
      3'b0:
	  w1__h37845 =
	      IF_rg_addr_7_BITS_2_TO_0_21_EQ_0x0_22_THEN_SEX_ETC___d1301;
      3'b001:
	  w1__h37845 =
	      IF_rg_addr_7_BITS_2_TO_0_21_EQ_0x0_22_THEN_SEX_ETC___d1329;
      3'b010: w1__h37845 = w1___1__h37916;
      3'b011:
	  w1__h37845 =
	      IF_rg_addr_7_BITS_2_TO_0_21_EQ_0x0_22_THEN_IF__ETC___d1348;
      3'b100:
	  w1__h37845 =
	      IF_rg_addr_7_BITS_2_TO_0_21_EQ_0x0_22_THEN_0_C_ETC___d1317;
      3'b101:
	  w1__h37845 =
	      IF_rg_addr_7_BITS_2_TO_0_21_EQ_0x0_22_THEN_0_C_ETC___d1337;
      3'b110:
	  w1__h37845 =
	      IF_rg_addr_7_BITS_2_TO_0_21_EQ_0x0_22_THEN_0_C_ETC___d1347;
      3'd7: w1__h37845 = 64'd0;
    endcase
  end
  always@(rg_f3 or
	  IF_rg_addr_7_BITS_2_TO_0_21_EQ_0x0_22_THEN_SEX_ETC___d1301 or
	  IF_rg_addr_7_BITS_2_TO_0_21_EQ_0x0_22_THEN_SEX_ETC___d1329 or
	  w17841_BITS_31_TO_0__q52 or
	  IF_rg_addr_7_BITS_2_TO_0_21_EQ_0x0_22_THEN_IF__ETC___d1348 or
	  IF_rg_addr_7_BITS_2_TO_0_21_EQ_0x0_22_THEN_0_C_ETC___d1317 or
	  IF_rg_addr_7_BITS_2_TO_0_21_EQ_0x0_22_THEN_0_C_ETC___d1337 or
	  IF_rg_addr_7_BITS_2_TO_0_21_EQ_0x0_22_THEN_0_C_ETC___d1347)
  begin
    case (rg_f3)
      3'b0:
	  new_ld_val__h37807 =
	      IF_rg_addr_7_BITS_2_TO_0_21_EQ_0x0_22_THEN_SEX_ETC___d1301;
      3'b001:
	  new_ld_val__h37807 =
	      IF_rg_addr_7_BITS_2_TO_0_21_EQ_0x0_22_THEN_SEX_ETC___d1329;
      3'b010:
	  new_ld_val__h37807 =
	      { {32{w17841_BITS_31_TO_0__q52[31]}},
		w17841_BITS_31_TO_0__q52 };
      3'b011:
	  new_ld_val__h37807 =
	      IF_rg_addr_7_BITS_2_TO_0_21_EQ_0x0_22_THEN_IF__ETC___d1348;
      3'b100:
	  new_ld_val__h37807 =
	      IF_rg_addr_7_BITS_2_TO_0_21_EQ_0x0_22_THEN_0_C_ETC___d1317;
      3'b101:
	  new_ld_val__h37807 =
	      IF_rg_addr_7_BITS_2_TO_0_21_EQ_0x0_22_THEN_0_C_ETC___d1337;
      3'b110:
	  new_ld_val__h37807 =
	      IF_rg_addr_7_BITS_2_TO_0_21_EQ_0x0_22_THEN_0_C_ETC___d1347;
      3'd7: new_ld_val__h37807 = 64'd0;
    endcase
  end
  always@(rg_amo_funct7 or
	  new_st_val__h39836 or
	  new_st_val__h37948 or
	  w2__h37847 or
	  new_st_val__h39808 or
	  new_st_val__h39816 or
	  new_st_val__h39812 or
	  new_st_val__h39831 or new_st_val__h39820 or new_st_val__h39825)
  begin
    case (rg_amo_funct7[6:2])
      5'b0: _theResult_____2__h37853 = new_st_val__h37948;
      5'b00001: _theResult_____2__h37853 = w2__h37847;
      5'b00100: _theResult_____2__h37853 = new_st_val__h39808;
      5'b01000: _theResult_____2__h37853 = new_st_val__h39816;
      5'b01100: _theResult_____2__h37853 = new_st_val__h39812;
      5'b10000: _theResult_____2__h37853 = new_st_val__h39831;
      5'b11000: _theResult_____2__h37853 = new_st_val__h39820;
      5'b11100: _theResult_____2__h37853 = new_st_val__h39825;
      default: _theResult_____2__h37853 = new_st_val__h39836;
    endcase
  end
  always@(rg_f3 or IF_rg_addr_7_BITS_2_TO_0_21_EQ_0x0_22_THEN_1_E_ETC___d662)
  begin
    case (rg_f3)
      3'b0, 3'b001, 3'b010, 3'b011, 3'b100, 3'b101, 3'b110:
	  CASE_rg_f3_0b0_IF_rg_addr_7_BITS_2_TO_0_21_EQ__ETC__q53 =
	      IF_rg_addr_7_BITS_2_TO_0_21_EQ_0x0_22_THEN_1_E_ETC___d662;
      3'd7: CASE_rg_f3_0b0_IF_rg_addr_7_BITS_2_TO_0_21_EQ__ETC__q53 = 64'd0;
    endcase
  end

  // handling of inlined registers

  always@(posedge CLK)
  begin
    if (RST_N == `BSV_RESET_VALUE)
      begin
        cfg_verbosity <= `BSV_ASSIGNMENT_DELAY 4'd0;
	ctr_wr_rsps_pending_crg <= `BSV_ASSIGNMENT_DELAY 4'd0;
	rg_cset_in_cache <= `BSV_ASSIGNMENT_DELAY 6'd0;
	rg_ddr4_ready <= `BSV_ASSIGNMENT_DELAY 1'd0;
	rg_lower_word32_full <= `BSV_ASSIGNMENT_DELAY 1'd0;
	rg_lrsc_valid <= `BSV_ASSIGNMENT_DELAY 1'd0;
	rg_state <= `BSV_ASSIGNMENT_DELAY 5'd0;
	rg_wr_rsp_err <= `BSV_ASSIGNMENT_DELAY 1'd0;
      end
    else
      begin
        if (cfg_verbosity$EN)
	  cfg_verbosity <= `BSV_ASSIGNMENT_DELAY cfg_verbosity$D_IN;
	if (ctr_wr_rsps_pending_crg$EN)
	  ctr_wr_rsps_pending_crg <= `BSV_ASSIGNMENT_DELAY
	      ctr_wr_rsps_pending_crg$D_IN;
	if (rg_cset_in_cache$EN)
	  rg_cset_in_cache <= `BSV_ASSIGNMENT_DELAY rg_cset_in_cache$D_IN;
	if (rg_ddr4_ready$EN)
	  rg_ddr4_ready <= `BSV_ASSIGNMENT_DELAY rg_ddr4_ready$D_IN;
	if (rg_lower_word32_full$EN)
	  rg_lower_word32_full <= `BSV_ASSIGNMENT_DELAY
	      rg_lower_word32_full$D_IN;
	if (rg_lrsc_valid$EN)
	  rg_lrsc_valid <= `BSV_ASSIGNMENT_DELAY rg_lrsc_valid$D_IN;
	if (rg_state$EN) rg_state <= `BSV_ASSIGNMENT_DELAY rg_state$D_IN;
	if (rg_wr_rsp_err$EN)
	  rg_wr_rsp_err <= `BSV_ASSIGNMENT_DELAY rg_wr_rsp_err$D_IN;
      end
    if (rg_addr$EN) rg_addr <= `BSV_ASSIGNMENT_DELAY rg_addr$D_IN;
    if (rg_amo_funct7$EN)
      rg_amo_funct7 <= `BSV_ASSIGNMENT_DELAY rg_amo_funct7$D_IN;
    if (rg_cset_cword_in_cache$EN)
      rg_cset_cword_in_cache <= `BSV_ASSIGNMENT_DELAY
	  rg_cset_cword_in_cache$D_IN;
    if (rg_error_during_refill$EN)
      rg_error_during_refill <= `BSV_ASSIGNMENT_DELAY
	  rg_error_during_refill$D_IN;
    if (rg_exc_code$EN) rg_exc_code <= `BSV_ASSIGNMENT_DELAY rg_exc_code$D_IN;
    if (rg_f3$EN) rg_f3 <= `BSV_ASSIGNMENT_DELAY rg_f3$D_IN;
    if (rg_ld_val$EN) rg_ld_val <= `BSV_ASSIGNMENT_DELAY rg_ld_val$D_IN;
    if (rg_lower_word32$EN)
      rg_lower_word32 <= `BSV_ASSIGNMENT_DELAY rg_lower_word32$D_IN;
    if (rg_lrsc_pa$EN) rg_lrsc_pa <= `BSV_ASSIGNMENT_DELAY rg_lrsc_pa$D_IN;
    if (rg_mstatus_MXR$EN)
      rg_mstatus_MXR <= `BSV_ASSIGNMENT_DELAY rg_mstatus_MXR$D_IN;
    if (rg_op$EN) rg_op <= `BSV_ASSIGNMENT_DELAY rg_op$D_IN;
    if (rg_pa$EN) rg_pa <= `BSV_ASSIGNMENT_DELAY rg_pa$D_IN;
    if (rg_priv$EN) rg_priv <= `BSV_ASSIGNMENT_DELAY rg_priv$D_IN;
    if (rg_pte_pa$EN) rg_pte_pa <= `BSV_ASSIGNMENT_DELAY rg_pte_pa$D_IN;
    if (rg_satp$EN) rg_satp <= `BSV_ASSIGNMENT_DELAY rg_satp$D_IN;
    if (rg_sstatus_SUM$EN)
      rg_sstatus_SUM <= `BSV_ASSIGNMENT_DELAY rg_sstatus_SUM$D_IN;
    if (rg_st_amo_val$EN)
      rg_st_amo_val <= `BSV_ASSIGNMENT_DELAY rg_st_amo_val$D_IN;
    if (rg_victim_way$EN)
      rg_victim_way <= `BSV_ASSIGNMENT_DELAY rg_victim_way$D_IN;
  end

  // synopsys translate_off
  `ifdef BSV_NO_INITIAL_BLOCKS
  `else // not BSV_NO_INITIAL_BLOCKS
  initial
  begin
    cfg_verbosity = 4'hA;
    ctr_wr_rsps_pending_crg = 4'hA;
    rg_addr = 64'hAAAAAAAAAAAAAAAA;
    rg_amo_funct7 = 7'h2A;
    rg_cset_cword_in_cache = 9'h0AA;
    rg_cset_in_cache = 6'h2A;
    rg_ddr4_ready = 1'h0;
    rg_error_during_refill = 1'h0;
    rg_exc_code = 4'hA;
    rg_f3 = 3'h2;
    rg_ld_val = 64'hAAAAAAAAAAAAAAAA;
    rg_lower_word32 = 32'hAAAAAAAA;
    rg_lower_word32_full = 1'h0;
    rg_lrsc_pa = 64'hAAAAAAAAAAAAAAAA;
    rg_lrsc_valid = 1'h0;
    rg_mstatus_MXR = 1'h0;
    rg_op = 2'h2;
    rg_pa = 64'hAAAAAAAAAAAAAAAA;
    rg_priv = 2'h2;
    rg_pte_pa = 64'hAAAAAAAAAAAAAAAA;
    rg_satp = 64'hAAAAAAAAAAAAAAAA;
    rg_sstatus_SUM = 1'h0;
    rg_st_amo_val = 64'hAAAAAAAAAAAAAAAA;
    rg_state = 5'h0A;
    rg_victim_way = 1'h0;
    rg_wr_rsp_err = 1'h0;
  end
  `endif // BSV_NO_INITIAL_BLOCKS
  // synopsys translate_on

  // handling of system tasks

  // synopsys translate_off
  always@(negedge CLK)
  begin
    #0;
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_fabric_send_write_req &&
	  !cfg_verbosity_read__1_ULE_1___d42)
	$write("            To fabric: ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_fabric_send_write_req &&
	  !cfg_verbosity_read__1_ULE_1___d42)
	$write("AXI4_Wr_Addr { ", "awid: ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_fabric_send_write_req &&
	  !cfg_verbosity_read__1_ULE_1___d42)
	$write("'h%h", 4'd0);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_fabric_send_write_req &&
	  !cfg_verbosity_read__1_ULE_1___d42)
	$write(", ", "awaddr: ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_fabric_send_write_req &&
	  !cfg_verbosity_read__1_ULE_1___d42)
	$write("'h%h", f_fabric_write_reqs$D_OUT[127:64]);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_fabric_send_write_req &&
	  !cfg_verbosity_read__1_ULE_1___d42)
	$write(", ", "awlen: ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_fabric_send_write_req &&
	  !cfg_verbosity_read__1_ULE_1___d42)
	$write("'h%h", 8'd0);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_fabric_send_write_req &&
	  !cfg_verbosity_read__1_ULE_1___d42)
	$write(", ", "awsize: ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_fabric_send_write_req &&
	  !cfg_verbosity_read__1_ULE_1___d42)
	$write("'h%h", x__h3037);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_fabric_send_write_req &&
	  !cfg_verbosity_read__1_ULE_1___d42)
	$write(", ", "awburst: ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_fabric_send_write_req &&
	  !cfg_verbosity_read__1_ULE_1___d42)
	$write("'h%h", 2'b01);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_fabric_send_write_req &&
	  !cfg_verbosity_read__1_ULE_1___d42)
	$write(", ", "awlock: ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_fabric_send_write_req &&
	  !cfg_verbosity_read__1_ULE_1___d42)
	$write("'h%h", 1'b0);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_fabric_send_write_req &&
	  !cfg_verbosity_read__1_ULE_1___d42)
	$write(", ", "awcache: ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_fabric_send_write_req &&
	  !cfg_verbosity_read__1_ULE_1___d42)
	$write("'h%h", 4'b0);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_fabric_send_write_req &&
	  !cfg_verbosity_read__1_ULE_1___d42)
	$write(", ", "awprot: ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_fabric_send_write_req &&
	  !cfg_verbosity_read__1_ULE_1___d42)
	$write("'h%h", 3'd0);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_fabric_send_write_req &&
	  !cfg_verbosity_read__1_ULE_1___d42)
	$write(", ", "awqos: ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_fabric_send_write_req &&
	  !cfg_verbosity_read__1_ULE_1___d42)
	$write("'h%h", 4'd0);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_fabric_send_write_req &&
	  !cfg_verbosity_read__1_ULE_1___d42)
	$write(", ", "awregion: ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_fabric_send_write_req &&
	  !cfg_verbosity_read__1_ULE_1___d42)
	$write("'h%h", 4'd0);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_fabric_send_write_req &&
	  !cfg_verbosity_read__1_ULE_1___d42)
	$write(", ", "awuser: ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_fabric_send_write_req &&
	  !cfg_verbosity_read__1_ULE_1___d42)
	$write("'h%h", 1'h0, " }");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_fabric_send_write_req &&
	  !cfg_verbosity_read__1_ULE_1___d42)
	$write("\n");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_fabric_send_write_req &&
	  !cfg_verbosity_read__1_ULE_1___d42)
	$write("                       ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_fabric_send_write_req &&
	  !cfg_verbosity_read__1_ULE_1___d42)
	$write("AXI4_Wr_Data { ", "wdata: ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_fabric_send_write_req &&
	  !cfg_verbosity_read__1_ULE_1___d42)
	$write("'h%h", mem_req_wr_data_wdata__h3221);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_fabric_send_write_req &&
	  !cfg_verbosity_read__1_ULE_1___d42)
	$write(", ", "wstrb: ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_fabric_send_write_req &&
	  !cfg_verbosity_read__1_ULE_1___d42)
	$write("'h%h", mem_req_wr_data_wstrb__h3222);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_fabric_send_write_req &&
	  !cfg_verbosity_read__1_ULE_1___d42)
	$write(", ", "wlast: ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_fabric_send_write_req &&
	  !cfg_verbosity_read__1_ULE_1___d42)
	$write("True");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_fabric_send_write_req &&
	  !cfg_verbosity_read__1_ULE_1___d42)
	$write(", ", "wuser: ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_fabric_send_write_req &&
	  !cfg_verbosity_read__1_ULE_1___d42)
	$write("'h%h", 1'h0, " }");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_fabric_send_write_req &&
	  !cfg_verbosity_read__1_ULE_1___d42)
	$write("\n");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_reset && rg_cset_in_cache == 6'd63 &&
	  cfg_verbosity != 4'd0 &&
	  !f_reset_reqs$D_OUT)
	begin
	  v__h4724 = $stime;
	  #0;
	end
    v__h4718 = v__h4724 / 32'd10;
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_reset && rg_cset_in_cache == 6'd63 &&
	  cfg_verbosity != 4'd0 &&
	  !f_reset_reqs$D_OUT)
	if (dmem_not_imem)
	  $display("%0d: %s.rl_reset: %0d sets x %0d ways: all tag states reset to CTAG_EMPTY",
		   v__h4718,
		   "D_MMU_Cache",
		   $signed(32'd64),
		   $signed(32'd2));
	else
	  $display("%0d: %s.rl_reset: %0d sets x %0d ways: all tag states reset to CTAG_EMPTY",
		   v__h4718,
		   "I_MMU_Cache",
		   $signed(32'd64),
		   $signed(32'd2));
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_reset && rg_cset_in_cache == 6'd63 &&
	  !cfg_verbosity_read__1_ULE_1___d42 &&
	  f_reset_reqs$D_OUT)
	begin
	  v__h4823 = $stime;
	  #0;
	end
    v__h4817 = v__h4823 / 32'd10;
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_reset && rg_cset_in_cache == 6'd63 &&
	  !cfg_verbosity_read__1_ULE_1___d42 &&
	  f_reset_reqs$D_OUT)
	if (dmem_not_imem)
	  $display("%0d: %s.rl_reset: Flushed", v__h4817, "D_MMU_Cache");
	else
	  $display("%0d: %s.rl_reset: Flushed", v__h4817, "I_MMU_Cache");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
	  !cfg_verbosity_read__1_ULE_1___d42)
	begin
	  v__h4973 = $stime;
	  #0;
	end
    v__h4967 = v__h4973 / 32'd10;
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
	  !cfg_verbosity_read__1_ULE_1___d42)
	if (dmem_not_imem)
	  $display("%0d: %s: rl_probe_and_immed_rsp; eaddr %0h",
		   v__h4967,
		   "D_MMU_Cache",
		   rg_addr);
	else
	  $display("%0d: %s: rl_probe_and_immed_rsp; eaddr %0h",
		   v__h4967,
		   "I_MMU_Cache",
		   rg_addr);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
	  !cfg_verbosity_read__1_ULE_1___d42 &&
	  rg_satp[63:60] != 4'd0)
	$display("        Priv:%0d  SATP:{mode %0d asid %0h pa %0h}  VA:%0h.%0h.%0h",
		 rg_priv,
		 rg_satp[63:60],
		 rg_satp[59:44],
		 satp_pa__h2068,
		 rg_addr[29:21],
		 rg_addr[20:12],
		 rg_addr[11:0]);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
	  !cfg_verbosity_read__1_ULE_1___d42)
	$display("        eaddr = {CTag 0x%0h  CSet 0x%0h  Word64 0x%0h  Byte 0x%0h}",
		 rg_addr[63:12],
		 rg_addr[11:6],
		 rg_addr[5:3],
		 rg_addr[2:0]);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
	  !cfg_verbosity_read__1_ULE_1___d42)
	$write("        CSet 0x%0x: (state, tag):", rg_addr[11:6]);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
	  !cfg_verbosity_read__1_ULE_1___d42)
	$write(" (");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
	  !cfg_verbosity_read__1_ULE_1___d42 &&
	  ram_state_and_ctag_cset$DOB[52])
	$write("CTAG_CLEAN");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
	  !cfg_verbosity_read__1_ULE_1___d42 &&
	  !ram_state_and_ctag_cset$DOB[52])
	$write("CTAG_EMPTY");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
	  !cfg_verbosity_read__1_ULE_1___d42 &&
	  ram_state_and_ctag_cset$DOB[52])
	$write(", 0x%0x", ram_state_and_ctag_cset$DOB[51:0]);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
	  !cfg_verbosity_read__1_ULE_1___d42 &&
	  !ram_state_and_ctag_cset$DOB[52])
	$write(", --");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
	  !cfg_verbosity_read__1_ULE_1___d42)
	$write(")");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
	  !cfg_verbosity_read__1_ULE_1___d42)
	$write(" (");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
	  !cfg_verbosity_read__1_ULE_1___d42 &&
	  ram_state_and_ctag_cset$DOB[105])
	$write("CTAG_CLEAN");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
	  !cfg_verbosity_read__1_ULE_1___d42 &&
	  !ram_state_and_ctag_cset$DOB[105])
	$write("CTAG_EMPTY");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
	  !cfg_verbosity_read__1_ULE_1___d42 &&
	  ram_state_and_ctag_cset$DOB[105])
	$write(", 0x%0x", ram_state_and_ctag_cset$DOB[104:53]);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
	  !cfg_verbosity_read__1_ULE_1___d42 &&
	  !ram_state_and_ctag_cset$DOB[105])
	$write(", --");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
	  !cfg_verbosity_read__1_ULE_1___d42)
	$write(")");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
	  !cfg_verbosity_read__1_ULE_1___d42)
	$write("\n");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
	  !cfg_verbosity_read__1_ULE_1___d42)
	$write("        CSet 0x%0x, CWord 0x%0x: ",
	       rg_addr[11:6],
	       rg_addr[5:3]);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
	  !cfg_verbosity_read__1_ULE_1___d42)
	$write(" 0x%0x", ram_cword_set$DOB[63:0]);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
	  !cfg_verbosity_read__1_ULE_1___d42)
	$write(" 0x%0x", ram_cword_set$DOB[127:64]);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
	  !cfg_verbosity_read__1_ULE_1___d42)
	$write("\n");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
	  !cfg_verbosity_read__1_ULE_1___d42)
	$write("    TLB result: ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
	  !cfg_verbosity_read__1_ULE_1___d42)
	$write("VM_Xlate_Result { ", "outcome: ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
	  !cfg_verbosity_read__1_ULE_1___d42 &&
	  NOT_rg_priv_6_ULE_0b1_7_8_OR_NOT_rg_satp_9_BIT_ETC___d397)
	$write("VM_XLATE_OK");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
	  !cfg_verbosity_read__1_ULE_1___d42 &&
	  rg_priv_6_ULE_0b1_7_AND_rg_satp_9_BITS_63_TO_6_ETC___d400)
	$write("VM_XLATE_EXCEPTION");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
	  !cfg_verbosity_read__1_ULE_1___d42 &&
	  rg_priv_6_ULE_0b1___d87 &&
	  rg_satp[63:60] == 4'd8 &&
	  !tlb$lookup[130])
	$write("VM_XLATE_TLB_MISS");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
	  !cfg_verbosity_read__1_ULE_1___d42)
	$write(", ", "pa: ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
	  !cfg_verbosity_read__1_ULE_1___d42)
	$write("'h%h", x1_avValue_pa__h6240);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
	  !cfg_verbosity_read__1_ULE_1___d42)
	$write(", ", "exc_code: ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
	  !cfg_verbosity_read__1_ULE_1___d42)
	$write("'h%h", x1_avValue_exc_code__h6241);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
	  !cfg_verbosity_read__1_ULE_1___d42)
	$write(", ", "pte_modified: ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
	  !cfg_verbosity_read__1_ULE_1___d42 &&
	  NOT_rg_priv_6_ULE_0b1_7_8_OR_NOT_rg_satp_9_BIT_ETC___d412)
	$write("False");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
	  !cfg_verbosity_read__1_ULE_1___d42 &&
	  rg_priv_6_ULE_0b1_7_AND_rg_satp_9_BITS_63_TO_6_ETC___d422)
	$write("True");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
	  !cfg_verbosity_read__1_ULE_1___d42)
	$write(", ", "pte: ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
	  !cfg_verbosity_read__1_ULE_1___d42)
	$write("'h%h", value__h7066, " }");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
	  !cfg_verbosity_read__1_ULE_1___d42)
	$write("\n");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
	  rg_priv_6_ULE_0b1_7_AND_rg_satp_9_BITS_63_TO_6_ETC___d422 &&
	  NOT_cfg_verbosity_read__1_ULT_2_49___d450)
	$display("    fa_record_pte_A_D_updates:");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
	  rg_priv_6_ULE_0b1_7_AND_rg_satp_9_BITS_63_TO_6_ETC___d422 &&
	  NOT_cfg_verbosity_read__1_ULT_2_49___d450)
	$write("      ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
	  rg_priv_6_ULE_0b1_7_AND_rg_satp_9_BITS_63_TO_6_ETC___d422 &&
	  NOT_cfg_verbosity_read__1_ULT_2_49___d450)
	$write("TLB_Lookup_Result { ", "hit: ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
	  rg_priv_6_ULE_0b1_7_AND_rg_satp_9_BITS_63_TO_6_ETC___d422 &&
	  NOT_cfg_verbosity_read__1_ULT_2_49___d450)
	$write("True");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
	  rg_priv_6_ULE_0b1_7_AND_rg_satp_9_BITS_63_TO_6_ETC___d422 &&
	  NOT_cfg_verbosity_read__1_ULT_2_49___d450)
	$write(", ", "pte: ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
	  rg_priv_6_ULE_0b1_7_AND_rg_satp_9_BITS_63_TO_6_ETC___d422 &&
	  NOT_cfg_verbosity_read__1_ULT_2_49___d450)
	$write("'h%h", tlb$lookup[129:66]);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
	  rg_priv_6_ULE_0b1_7_AND_rg_satp_9_BITS_63_TO_6_ETC___d422 &&
	  NOT_cfg_verbosity_read__1_ULT_2_49___d450)
	$write(", ", "pte_level: ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
	  rg_priv_6_ULE_0b1_7_AND_rg_satp_9_BITS_63_TO_6_ETC___d422 &&
	  NOT_cfg_verbosity_read__1_ULT_2_49___d450)
	$write("'h%h", tlb$lookup[65:64]);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
	  rg_priv_6_ULE_0b1_7_AND_rg_satp_9_BITS_63_TO_6_ETC___d422 &&
	  NOT_cfg_verbosity_read__1_ULT_2_49___d450)
	$write(", ", "pte_pa: ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
	  rg_priv_6_ULE_0b1_7_AND_rg_satp_9_BITS_63_TO_6_ETC___d422 &&
	  NOT_cfg_verbosity_read__1_ULT_2_49___d450)
	$write("'h%h", tlb$lookup[63:0], " }");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
	  rg_priv_6_ULE_0b1_7_AND_rg_satp_9_BITS_63_TO_6_ETC___d422 &&
	  NOT_cfg_verbosity_read__1_ULT_2_49___d450)
	$write("\n");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
	  rg_priv_6_ULE_0b1_7_AND_rg_satp_9_BITS_63_TO_6_ETC___d422 &&
	  NOT_cfg_verbosity_read__1_ULT_2_49___d450)
	$write("      ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
	  rg_priv_6_ULE_0b1_7_AND_rg_satp_9_BITS_63_TO_6_ETC___d422 &&
	  NOT_cfg_verbosity_read__1_ULT_2_49___d450)
	$write("VM_Xlate_Result { ", "outcome: ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
	  rg_priv_6_ULE_0b1_7_AND_rg_satp_9_BITS_63_TO_6_ETC___d458)
	$write("VM_XLATE_OK");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
	  rg_priv_6_ULE_0b1_7_AND_rg_satp_9_BITS_63_TO_6_ETC___d461)
	$write("VM_XLATE_EXCEPTION");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
	  rg_priv_6_ULE_0b1_7_AND_rg_satp_9_BITS_63_TO_6_ETC___d422 &&
	  NOT_cfg_verbosity_read__1_ULT_2_49___d450)
	$write(", ", "pa: ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
	  rg_priv_6_ULE_0b1_7_AND_rg_satp_9_BITS_63_TO_6_ETC___d422 &&
	  NOT_cfg_verbosity_read__1_ULT_2_49___d450)
	$write("'h%h", x1_avValue_pa__h6240);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
	  rg_priv_6_ULE_0b1_7_AND_rg_satp_9_BITS_63_TO_6_ETC___d422 &&
	  NOT_cfg_verbosity_read__1_ULT_2_49___d450)
	$write(", ", "exc_code: ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
	  rg_priv_6_ULE_0b1_7_AND_rg_satp_9_BITS_63_TO_6_ETC___d422 &&
	  NOT_cfg_verbosity_read__1_ULT_2_49___d450)
	$write("'h%h", x1_avValue_exc_code__h6241);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
	  rg_priv_6_ULE_0b1_7_AND_rg_satp_9_BITS_63_TO_6_ETC___d422 &&
	  NOT_cfg_verbosity_read__1_ULT_2_49___d450)
	$write(", ", "pte_modified: ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
	  rg_priv_6_ULE_0b1_7_AND_rg_satp_9_BITS_63_TO_6_ETC___d461)
	$write("False");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
	  rg_priv_6_ULE_0b1_7_AND_rg_satp_9_BITS_63_TO_6_ETC___d458)
	$write("True");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
	  rg_priv_6_ULE_0b1_7_AND_rg_satp_9_BITS_63_TO_6_ETC___d422 &&
	  NOT_cfg_verbosity_read__1_ULT_2_49___d450)
	$write(", ", "pte: ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
	  rg_priv_6_ULE_0b1_7_AND_rg_satp_9_BITS_63_TO_6_ETC___d422 &&
	  NOT_cfg_verbosity_read__1_ULT_2_49___d450)
	$write("'h%h", value__h7066, " }");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
	  rg_priv_6_ULE_0b1_7_AND_rg_satp_9_BITS_63_TO_6_ETC___d422 &&
	  NOT_cfg_verbosity_read__1_ULT_2_49___d450)
	$write("\n");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
	  NOT_rg_priv_6_ULE_0b1_7_8_OR_NOT_rg_satp_9_BIT_ETC___d475)
	$display("    => IO_REQ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
	  NOT_rg_priv_6_ULE_0b1_7_8_OR_NOT_rg_satp_9_BIT_ETC___d481)
	$display("        ASSERTION ERROR: fn_test_cache_hit_or_miss: multiple hits in set at [%0d] and [%0d]",
		 $signed(32'd1),
		 1'd0);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
	  NOT_rg_priv_6_ULE_0b1_7_8_OR_NOT_rg_satp_9_BIT_ETC___d677)
	begin
	  v__h21508 = $stime;
	  #0;
	end
    v__h21502 = v__h21508 / 32'd10;
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
	  NOT_rg_priv_6_ULE_0b1_7_8_OR_NOT_rg_satp_9_BIT_ETC___d677)
	if (dmem_not_imem)
	  $display("%0d: %s.drive_mem_rsp: addr 0x%0h ld_val 0x%0h st_amo_val 0x%0h",
		   v__h21502,
		   "D_MMU_Cache",
		   rg_addr,
		   word64__h7759,
		   64'd0);
	else
	  $display("%0d: %s.drive_mem_rsp: addr 0x%0h ld_val 0x%0h st_amo_val 0x%0h",
		   v__h21502,
		   "I_MMU_Cache",
		   rg_addr,
		   word64__h7759,
		   64'd0);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
	  NOT_rg_priv_6_ULE_0b1_7_8_OR_NOT_rg_satp_9_BIT_ETC___d689)
	$display("        AMO LR: reserving PA 0x%0h", x1_avValue_pa__h6240);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
	  NOT_rg_priv_6_ULE_0b1_7_8_OR_NOT_rg_satp_9_BIT_ETC___d677)
	$display("        Read-hit: addr 0x%0h word64 0x%0h",
		 rg_addr,
		 word64__h7759);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
	  NOT_rg_priv_6_ULE_0b1_7_8_OR_NOT_rg_satp_9_BIT_ETC___d694)
	$display("        Read Miss: -> CACHE_START_REFILL.");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
	  NOT_rg_priv_6_ULE_0b1_7_8_OR_NOT_rg_satp_9_BIT_ETC___d702)
	$display("        AMO LR: cache refill: cancelling LR/SC reservation for PA 0x%0h",
		 rg_lrsc_pa);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
	  NOT_rg_priv_6_ULE_0b1_7_8_OR_NOT_rg_satp_9_BIT_ETC___d861)
	$display("        ST: cancelling LR/SC reservation for PA",
		 x1_avValue_pa__h6240);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
	  (!rg_priv_6_ULE_0b1___d87 || rg_satp[63:60] != 4'd8 ||
	   tlb$lookup[130]) &&
	  NOT_rg_priv_6_ULE_0b1_7_8_OR_NOT_rg_satp_9_BIT_ETC___d867)
	$display("        AMO SC: fail: reserved addr 0x%0h, this address 0x%0h",
		 rg_lrsc_pa,
		 x1_avValue_pa__h6240);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
	  (!rg_priv_6_ULE_0b1___d87 || rg_satp[63:60] != 4'd8 ||
	   tlb$lookup[130]) &&
	  NOT_rg_priv_6_ULE_0b1_7_8_OR_NOT_rg_satp_9_BIT_ETC___d873)
	$display("        AMO SC: fail due to invalid LR/SC reservation");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
	  NOT_rg_priv_6_ULE_0b1_7_8_OR_NOT_rg_satp_9_BIT_ETC___d879)
	$display("        AMO SC result = %0d", lrsc_result__h21885);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
	  NOT_rg_priv_6_ULE_0b1_7_8_OR_NOT_rg_satp_9_BIT_ETC___d885)
	$display("        Write-Cache-Hit: pa 0x%0h word64 0x%0h",
		 x1_avValue_pa__h6240,
		 rg_st_amo_val);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
	  NOT_rg_priv_6_ULE_0b1_7_8_OR_NOT_rg_satp_9_BIT_ETC___d885)
	$write("        New Word64_Set:");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
	  NOT_rg_priv_6_ULE_0b1_7_8_OR_NOT_rg_satp_9_BIT_ETC___d885)
	$write("        CSet 0x%0x, CWord 0x%0x: ",
	       rg_addr[11:6],
	       rg_addr[5:3]);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
	  NOT_rg_priv_6_ULE_0b1_7_8_OR_NOT_rg_satp_9_BIT_ETC___d885)
	$write(" 0x%0x",
	       IF_NOT_ram_state_and_ctag_cset_b_read__00_BIT__ETC___d779);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
	  NOT_rg_priv_6_ULE_0b1_7_8_OR_NOT_rg_satp_9_BIT_ETC___d885)
	$write(" 0x%0x",
	       IF_ram_state_and_ctag_cset_b_read__00_BIT_105__ETC___d778);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
	  NOT_rg_priv_6_ULE_0b1_7_8_OR_NOT_rg_satp_9_BIT_ETC___d885)
	$write("\n");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
	  (!rg_priv_6_ULE_0b1___d87 || rg_satp[63:60] != 4'd8 ||
	   tlb$lookup[130]) &&
	  NOT_rg_priv_6_ULE_0b1_7_8_OR_NOT_rg_satp_9_BIT_ETC___d890)
	$display("        Write-Cache-Miss: pa 0x%0h word64 0x%0h",
		 x1_avValue_pa__h6240,
		 rg_st_amo_val);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
	  NOT_rg_priv_6_ULE_0b1_7_8_OR_NOT_rg_satp_9_BIT_ETC___d897)
	$display("        Write-Cache-Hit/Miss: eaddr 0x%0h word64 0x%0h",
		 rg_addr,
		 rg_st_amo_val);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
	  NOT_rg_priv_6_ULE_0b1_7_8_OR_NOT_rg_satp_9_BIT_ETC___d897)
	$display("        => rl_write_response");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
	  NOT_rg_priv_6_ULE_0b1_7_8_OR_NOT_rg_satp_9_BIT_ETC___d903)
	begin
	  v__h25224 = $stime;
	  #0;
	end
    v__h25218 = v__h25224 / 32'd10;
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
	  NOT_rg_priv_6_ULE_0b1_7_8_OR_NOT_rg_satp_9_BIT_ETC___d903)
	if (dmem_not_imem)
	  $display("%0d: %s.drive_mem_rsp: addr 0x%0h ld_val 0x%0h st_amo_val 0x%0h",
		   v__h25218,
		   "D_MMU_Cache",
		   rg_addr,
		   64'd1,
		   64'd0);
	else
	  $display("%0d: %s.drive_mem_rsp: addr 0x%0h ld_val 0x%0h st_amo_val 0x%0h",
		   v__h25218,
		   "I_MMU_Cache",
		   rg_addr,
		   64'd1,
		   64'd0);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
	  NOT_rg_priv_6_ULE_0b1_7_8_OR_NOT_rg_satp_9_BIT_ETC___d903)
	$display("        AMO SC: Fail response for addr 0x%0h", rg_addr);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
	  (!rg_priv_6_ULE_0b1___d87 || rg_satp[63:60] != 4'd8 ||
	   tlb$lookup[130]) &&
	  NOT_rg_priv_6_ULE_0b1_7_8_OR_NOT_rg_satp_9_BIT_ETC___d909)
	$display("        AMO Miss: -> CACHE_START_REFILL.");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
	  NOT_rg_priv_6_ULE_0b1_7_8_OR_NOT_rg_satp_9_BIT_ETC___d915)
	$display("        AMO: addr 0x%0h amo_f7 0x%0h f3 %0d rs2_val 0x%0h",
		 rg_addr,
		 rg_amo_funct7,
		 rg_f3,
		 rg_st_amo_val);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
	  NOT_rg_priv_6_ULE_0b1_7_8_OR_NOT_rg_satp_9_BIT_ETC___d915)
	$display("          PA 0x%0h ", x1_avValue_pa__h6240);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
	  NOT_rg_priv_6_ULE_0b1_7_8_OR_NOT_rg_satp_9_BIT_ETC___d915)
	$display("          Cache word64 0x%0h, load-result 0x%0h",
		 word64__h7759,
		 word64__h7759);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
	  NOT_rg_priv_6_ULE_0b1_7_8_OR_NOT_rg_satp_9_BIT_ETC___d915)
	$display("          0x%0h  op  0x%0h -> 0x%0h",
		 word64__h7759,
		 word64__h7759,
		 new_st_val__h25444);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
	  NOT_rg_priv_6_ULE_0b1_7_8_OR_NOT_rg_satp_9_BIT_ETC___d915)
	$write("          New Word64_Set:");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
	  NOT_rg_priv_6_ULE_0b1_7_8_OR_NOT_rg_satp_9_BIT_ETC___d915)
	$write("        CSet 0x%0x, CWord 0x%0x: ",
	       rg_addr[11:6],
	       rg_addr[5:3]);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
	  NOT_rg_priv_6_ULE_0b1_7_8_OR_NOT_rg_satp_9_BIT_ETC___d915)
	$write(" 0x%0x",
	       IF_NOT_ram_state_and_ctag_cset_b_read__00_BIT__ETC___d847);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
	  NOT_rg_priv_6_ULE_0b1_7_8_OR_NOT_rg_satp_9_BIT_ETC___d915)
	$write(" 0x%0x",
	       IF_ram_state_and_ctag_cset_b_read__00_BIT_105__ETC___d846);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
	  NOT_rg_priv_6_ULE_0b1_7_8_OR_NOT_rg_satp_9_BIT_ETC___d915)
	$write("\n");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
	  (!rg_priv_6_ULE_0b1___d87 || rg_satp[63:60] != 4'd8 ||
	   tlb$lookup[130]) &&
	  NOT_rg_priv_6_ULE_0b1_7_8_OR_NOT_rg_satp_9_BIT_ETC___d920)
	$display("        AMO_op: cancelling LR/SC reservation for PA",
		 x1_avValue_pa__h6240);
    if (RST_N != `BSV_RESET_VALUE)
      if (EN_ma_ddr4_ready)
	begin
	  v__h42646 = $stime;
	  #0;
	end
    v__h42640 = v__h42646 / 32'd10;
    if (RST_N != `BSV_RESET_VALUE)
      if (EN_ma_ddr4_ready)
	$display("%0d: %m.ma_ddr4_ready: Enabling MMU_Cache", v__h42640);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_start_tlb_refill &&
	  !cfg_verbosity_read__1_ULE_1___d42)
	begin
	  v__h28736 = $stime;
	  #0;
	end
    v__h28730 = v__h28736 / 32'd10;
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_start_tlb_refill &&
	  !cfg_verbosity_read__1_ULE_1___d42)
	if (dmem_not_imem)
	  $display("%0d: %s.rl_start_tlb_refill for eaddr 0x%0h; req for level 2 PTE",
		   v__h28730,
		   "D_MMU_Cache",
		   rg_addr);
	else
	  $display("%0d: %s.rl_start_tlb_refill for eaddr 0x%0h; req for level 2 PTE",
		   v__h28730,
		   "I_MMU_Cache",
		   rg_addr);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_start_tlb_refill &&
	  !cfg_verbosity_read__1_ULE_1___d42)
	$write("            To fabric: ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_start_tlb_refill &&
	  !cfg_verbosity_read__1_ULE_1___d42)
	$write("AXI4_Rd_Addr { ", "arid: ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_start_tlb_refill &&
	  !cfg_verbosity_read__1_ULE_1___d42)
	$write("'h%h", 4'd0);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_start_tlb_refill &&
	  !cfg_verbosity_read__1_ULE_1___d42)
	$write(", ", "araddr: ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_start_tlb_refill &&
	  !cfg_verbosity_read__1_ULE_1___d42)
	$write("'h%h", lev_2_pte_pa_w64_fa__h28791);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_start_tlb_refill &&
	  !cfg_verbosity_read__1_ULE_1___d42)
	$write(", ", "arlen: ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_start_tlb_refill &&
	  !cfg_verbosity_read__1_ULE_1___d42)
	$write("'h%h", 8'd0);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_start_tlb_refill &&
	  !cfg_verbosity_read__1_ULE_1___d42)
	$write(", ", "arsize: ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_start_tlb_refill &&
	  !cfg_verbosity_read__1_ULE_1___d42)
	$write("'h%h", 3'b011);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_start_tlb_refill &&
	  !cfg_verbosity_read__1_ULE_1___d42)
	$write(", ", "arburst: ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_start_tlb_refill &&
	  !cfg_verbosity_read__1_ULE_1___d42)
	$write("'h%h", 2'b01);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_start_tlb_refill &&
	  !cfg_verbosity_read__1_ULE_1___d42)
	$write(", ", "arlock: ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_start_tlb_refill &&
	  !cfg_verbosity_read__1_ULE_1___d42)
	$write("'h%h", 1'b0);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_start_tlb_refill &&
	  !cfg_verbosity_read__1_ULE_1___d42)
	$write(", ", "arcache: ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_start_tlb_refill &&
	  !cfg_verbosity_read__1_ULE_1___d42)
	$write("'h%h", 4'b0);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_start_tlb_refill &&
	  !cfg_verbosity_read__1_ULE_1___d42)
	$write(", ", "arprot: ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_start_tlb_refill &&
	  !cfg_verbosity_read__1_ULE_1___d42)
	$write("'h%h", 3'd0);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_start_tlb_refill &&
	  !cfg_verbosity_read__1_ULE_1___d42)
	$write(", ", "arqos: ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_start_tlb_refill &&
	  !cfg_verbosity_read__1_ULE_1___d42)
	$write("'h%h", 4'd0);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_start_tlb_refill &&
	  !cfg_verbosity_read__1_ULE_1___d42)
	$write(", ", "arregion: ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_start_tlb_refill &&
	  !cfg_verbosity_read__1_ULE_1___d42)
	$write("'h%h", 4'd0);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_start_tlb_refill &&
	  !cfg_verbosity_read__1_ULE_1___d42)
	$write(", ", "aruser: ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_start_tlb_refill &&
	  !cfg_verbosity_read__1_ULE_1___d42)
	$write("'h%h", 1'h0, " }");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_start_tlb_refill &&
	  !cfg_verbosity_read__1_ULE_1___d42)
	$write("\n");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_ptw_level_2 &&
	  master_xactor_f_rd_data_first__41_BITS_2_TO_1__ETC___d981)
	begin
	  v__h29654 = $stime;
	  #0;
	end
    v__h29648 = v__h29654 / 32'd10;
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_ptw_level_2 &&
	  master_xactor_f_rd_data_first__41_BITS_2_TO_1__ETC___d981)
	if (dmem_not_imem)
	  $display("%0d: %s.rl_ptw_level_2: for eaddr 0x%0h: pte 0x%0h @ 0x%0h: Invalid PTE; page fault %0d",
		   v__h29648,
		   "D_MMU_Cache",
		   rg_addr,
		   master_xactor_f_rd_data$D_OUT[66:3],
		   rg_pte_pa,
		   exc_code___1__h6641);
	else
	  $display("%0d: %s.rl_ptw_level_2: for eaddr 0x%0h: pte 0x%0h @ 0x%0h: Invalid PTE; page fault %0d",
		   v__h29648,
		   "I_MMU_Cache",
		   rg_addr,
		   master_xactor_f_rd_data$D_OUT[66:3],
		   rg_pte_pa,
		   exc_code___1__h6641);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_ptw_level_2 &&
	  master_xactor_f_rd_data_first__41_BITS_2_TO_1__ETC___d991)
	begin
	  v__h29411 = $stime;
	  #0;
	end
    v__h29405 = v__h29411 / 32'd10;
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_ptw_level_2 &&
	  master_xactor_f_rd_data_first__41_BITS_2_TO_1__ETC___d991)
	if (dmem_not_imem)
	  $display("%0d: %s.rl_rl_ptw_level_2: for eaddr 0x%0h: pte 0x%0h @ 0x%0h: continue to level 1",
		   v__h29405,
		   "D_MMU_Cache",
		   rg_addr,
		   master_xactor_f_rd_data$D_OUT[66:3],
		   rg_pte_pa);
	else
	  $display("%0d: %s.rl_rl_ptw_level_2: for eaddr 0x%0h: pte 0x%0h @ 0x%0h: continue to level 1",
		   v__h29405,
		   "I_MMU_Cache",
		   rg_addr,
		   master_xactor_f_rd_data$D_OUT[66:3],
		   rg_pte_pa);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_ptw_level_2 &&
	  master_xactor_f_rd_data_first__41_BITS_2_TO_1__ETC___d991)
	$display("    Req for level 1 PTE");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_ptw_level_2 &&
	  master_xactor_f_rd_data_first__41_BITS_2_TO_1__ETC___d991)
	$write("            To fabric: ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_ptw_level_2 &&
	  master_xactor_f_rd_data_first__41_BITS_2_TO_1__ETC___d991)
	$write("AXI4_Rd_Addr { ", "arid: ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_ptw_level_2 &&
	  master_xactor_f_rd_data_first__41_BITS_2_TO_1__ETC___d991)
	$write("'h%h", 4'd0);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_ptw_level_2 &&
	  master_xactor_f_rd_data_first__41_BITS_2_TO_1__ETC___d991)
	$write(", ", "araddr: ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_ptw_level_2 &&
	  master_xactor_f_rd_data_first__41_BITS_2_TO_1__ETC___d991)
	$write("'h%h", lev_1_pte_pa_w64_fa__h29688);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_ptw_level_2 &&
	  master_xactor_f_rd_data_first__41_BITS_2_TO_1__ETC___d991)
	$write(", ", "arlen: ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_ptw_level_2 &&
	  master_xactor_f_rd_data_first__41_BITS_2_TO_1__ETC___d991)
	$write("'h%h", 8'd0);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_ptw_level_2 &&
	  master_xactor_f_rd_data_first__41_BITS_2_TO_1__ETC___d991)
	$write(", ", "arsize: ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_ptw_level_2 &&
	  master_xactor_f_rd_data_first__41_BITS_2_TO_1__ETC___d991)
	$write("'h%h", 3'b011);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_ptw_level_2 &&
	  master_xactor_f_rd_data_first__41_BITS_2_TO_1__ETC___d991)
	$write(", ", "arburst: ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_ptw_level_2 &&
	  master_xactor_f_rd_data_first__41_BITS_2_TO_1__ETC___d991)
	$write("'h%h", 2'b01);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_ptw_level_2 &&
	  master_xactor_f_rd_data_first__41_BITS_2_TO_1__ETC___d991)
	$write(", ", "arlock: ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_ptw_level_2 &&
	  master_xactor_f_rd_data_first__41_BITS_2_TO_1__ETC___d991)
	$write("'h%h", 1'b0);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_ptw_level_2 &&
	  master_xactor_f_rd_data_first__41_BITS_2_TO_1__ETC___d991)
	$write(", ", "arcache: ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_ptw_level_2 &&
	  master_xactor_f_rd_data_first__41_BITS_2_TO_1__ETC___d991)
	$write("'h%h", 4'b0);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_ptw_level_2 &&
	  master_xactor_f_rd_data_first__41_BITS_2_TO_1__ETC___d991)
	$write(", ", "arprot: ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_ptw_level_2 &&
	  master_xactor_f_rd_data_first__41_BITS_2_TO_1__ETC___d991)
	$write("'h%h", 3'd0);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_ptw_level_2 &&
	  master_xactor_f_rd_data_first__41_BITS_2_TO_1__ETC___d991)
	$write(", ", "arqos: ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_ptw_level_2 &&
	  master_xactor_f_rd_data_first__41_BITS_2_TO_1__ETC___d991)
	$write("'h%h", 4'd0);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_ptw_level_2 &&
	  master_xactor_f_rd_data_first__41_BITS_2_TO_1__ETC___d991)
	$write(", ", "arregion: ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_ptw_level_2 &&
	  master_xactor_f_rd_data_first__41_BITS_2_TO_1__ETC___d991)
	$write("'h%h", 4'd0);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_ptw_level_2 &&
	  master_xactor_f_rd_data_first__41_BITS_2_TO_1__ETC___d991)
	$write(", ", "aruser: ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_ptw_level_2 &&
	  master_xactor_f_rd_data_first__41_BITS_2_TO_1__ETC___d991)
	$write("'h%h", 1'h0, " }");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_ptw_level_2 &&
	  master_xactor_f_rd_data_first__41_BITS_2_TO_1__ETC___d991)
	$write("\n");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_ptw_level_2 &&
	  master_xactor_f_rd_data_first__41_BITS_2_TO_1__ETC___d1007)
	begin
	  v__h29942 = $stime;
	  #0;
	end
    v__h29936 = v__h29942 / 32'd10;
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_ptw_level_2 &&
	  master_xactor_f_rd_data_first__41_BITS_2_TO_1__ETC___d1007)
	if (dmem_not_imem)
	  $display("%0d: %s.rl_ptw_level_2: for eaddr 0x%0h: gigapage pte 0x%0h @ 0x%0h",
		   v__h29936,
		   "D_MMU_Cache",
		   rg_addr,
		   master_xactor_f_rd_data$D_OUT[66:3],
		   rg_pte_pa);
	else
	  $display("%0d: %s.rl_ptw_level_2: for eaddr 0x%0h: gigapage pte 0x%0h @ 0x%0h",
		   v__h29936,
		   "I_MMU_Cache",
		   rg_addr,
		   master_xactor_f_rd_data$D_OUT[66:3],
		   rg_pte_pa);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_ptw_level_2 &&
	  master_xactor_f_rd_data$D_OUT[2:1] == 2'b0 &&
	  master_xactor_f_rd_data$D_OUT[3] &&
	  (master_xactor_f_rd_data$D_OUT[4] ||
	   !master_xactor_f_rd_data$D_OUT[5]) &&
	  (master_xactor_f_rd_data$D_OUT[6] ||
	   master_xactor_f_rd_data$D_OUT[4]) &&
	  (master_xactor_f_rd_data$D_OUT[30:22] != 9'd0 ||
	   master_xactor_f_rd_data$D_OUT[21:13] != 9'd0))
	$display("    Invalid PTE: PPN[1] or PPN[0] is not zero; page fault %0d",
		 exc_code___1__h6641);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_ptw_level_2 &&
	  master_xactor_f_rd_data_first__41_BITS_2_TO_1__ETC___d1019)
	begin
	  v__h30054 = $stime;
	  #0;
	end
    v__h30048 = v__h30054 / 32'd10;
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_ptw_level_2 &&
	  master_xactor_f_rd_data_first__41_BITS_2_TO_1__ETC___d1019)
	if (dmem_not_imem)
	  $display("%0d: %s.rl_ptw_level_2: for eaddr 0x%0h: pte 0x%0h @ 0x%0h: leaf PTE for gigapage",
		   v__h30048,
		   "D_MMU_Cache",
		   rg_addr,
		   master_xactor_f_rd_data$D_OUT[66:3],
		   rg_pte_pa);
	else
	  $display("%0d: %s.rl_ptw_level_2: for eaddr 0x%0h: pte 0x%0h @ 0x%0h: leaf PTE for gigapage",
		   v__h30048,
		   "I_MMU_Cache",
		   rg_addr,
		   master_xactor_f_rd_data$D_OUT[66:3],
		   rg_pte_pa);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_ptw_level_2 &&
	  master_xactor_f_rd_data_first__41_BITS_2_TO_1__ETC___d1019)
	$display("    Addr Space megapage pa: 0x%0h", lev_1_PTN_pa__h29684);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_ptw_level_2 &&
	  master_xactor_f_rd_data$D_OUT[2:1] != 2'b0 &&
	  !cfg_verbosity_read__1_ULE_1___d42)
	begin
	  v__h29583 = $stime;
	  #0;
	end
    v__h29577 = v__h29583 / 32'd10;
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_ptw_level_2 &&
	  master_xactor_f_rd_data$D_OUT[2:1] != 2'b0 &&
	  !cfg_verbosity_read__1_ULE_1___d42)
	if (dmem_not_imem)
	  $display("%0d: %s.rl_ptw_level_2: for eaddr 0x%0h: pte_pa 0x%0h: FABRIC_RSP_ERR: access exception %0d",
		   v__h29577,
		   "D_MMU_Cache",
		   rg_addr,
		   rg_pte_pa,
		   access_exc_code__h2772);
	else
	  $display("%0d: %s.rl_ptw_level_2: for eaddr 0x%0h: pte_pa 0x%0h: FABRIC_RSP_ERR: access exception %0d",
		   v__h29577,
		   "I_MMU_Cache",
		   rg_addr,
		   rg_pte_pa,
		   access_exc_code__h2772);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_ptw_level_1 &&
	  master_xactor_f_rd_data_first__41_BITS_2_TO_1__ETC___d981)
	begin
	  v__h30687 = $stime;
	  #0;
	end
    v__h30681 = v__h30687 / 32'd10;
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_ptw_level_1 &&
	  master_xactor_f_rd_data_first__41_BITS_2_TO_1__ETC___d981)
	if (dmem_not_imem)
	  $display("%0d: %s.rl_ptw_level_1: for eaddr 0x%0h: pte 0x%0h @ 0x%0h: Invalid PTE; page fault %0d",
		   v__h30681,
		   "D_MMU_Cache",
		   rg_addr,
		   master_xactor_f_rd_data$D_OUT[66:3],
		   rg_pte_pa,
		   exc_code___1__h6641);
	else
	  $display("%0d: %s.rl_ptw_level_1: for eaddr 0x%0h: pte 0x%0h @ 0x%0h: Invalid PTE; page fault %0d",
		   v__h30681,
		   "I_MMU_Cache",
		   rg_addr,
		   master_xactor_f_rd_data$D_OUT[66:3],
		   rg_pte_pa,
		   exc_code___1__h6641);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_ptw_level_1 &&
	  master_xactor_f_rd_data_first__41_BITS_2_TO_1__ETC___d991)
	begin
	  v__h30447 = $stime;
	  #0;
	end
    v__h30441 = v__h30447 / 32'd10;
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_ptw_level_1 &&
	  master_xactor_f_rd_data_first__41_BITS_2_TO_1__ETC___d991)
	if (dmem_not_imem)
	  $display("%0d: %s.rl_rl_ptw_level_1: for eaddr 0x%0h: pte 0x%0h @ 0x%0h: continue to level 0",
		   v__h30441,
		   "D_MMU_Cache",
		   rg_addr,
		   master_xactor_f_rd_data$D_OUT[66:3],
		   rg_pte_pa);
	else
	  $display("%0d: %s.rl_rl_ptw_level_1: for eaddr 0x%0h: pte 0x%0h @ 0x%0h: continue to level 0",
		   v__h30441,
		   "I_MMU_Cache",
		   rg_addr,
		   master_xactor_f_rd_data$D_OUT[66:3],
		   rg_pte_pa);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_ptw_level_1 &&
	  master_xactor_f_rd_data_first__41_BITS_2_TO_1__ETC___d991)
	$display("    Req for level 0 PTE");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_ptw_level_1 &&
	  master_xactor_f_rd_data_first__41_BITS_2_TO_1__ETC___d991)
	$write("            To fabric: ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_ptw_level_1 &&
	  master_xactor_f_rd_data_first__41_BITS_2_TO_1__ETC___d991)
	$write("AXI4_Rd_Addr { ", "arid: ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_ptw_level_1 &&
	  master_xactor_f_rd_data_first__41_BITS_2_TO_1__ETC___d991)
	$write("'h%h", 4'd0);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_ptw_level_1 &&
	  master_xactor_f_rd_data_first__41_BITS_2_TO_1__ETC___d991)
	$write(", ", "araddr: ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_ptw_level_1 &&
	  master_xactor_f_rd_data_first__41_BITS_2_TO_1__ETC___d991)
	$write("'h%h", lev_0_pte_pa_w64_fa__h30721);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_ptw_level_1 &&
	  master_xactor_f_rd_data_first__41_BITS_2_TO_1__ETC___d991)
	$write(", ", "arlen: ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_ptw_level_1 &&
	  master_xactor_f_rd_data_first__41_BITS_2_TO_1__ETC___d991)
	$write("'h%h", 8'd0);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_ptw_level_1 &&
	  master_xactor_f_rd_data_first__41_BITS_2_TO_1__ETC___d991)
	$write(", ", "arsize: ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_ptw_level_1 &&
	  master_xactor_f_rd_data_first__41_BITS_2_TO_1__ETC___d991)
	$write("'h%h", 3'b011);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_ptw_level_1 &&
	  master_xactor_f_rd_data_first__41_BITS_2_TO_1__ETC___d991)
	$write(", ", "arburst: ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_ptw_level_1 &&
	  master_xactor_f_rd_data_first__41_BITS_2_TO_1__ETC___d991)
	$write("'h%h", 2'b01);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_ptw_level_1 &&
	  master_xactor_f_rd_data_first__41_BITS_2_TO_1__ETC___d991)
	$write(", ", "arlock: ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_ptw_level_1 &&
	  master_xactor_f_rd_data_first__41_BITS_2_TO_1__ETC___d991)
	$write("'h%h", 1'b0);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_ptw_level_1 &&
	  master_xactor_f_rd_data_first__41_BITS_2_TO_1__ETC___d991)
	$write(", ", "arcache: ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_ptw_level_1 &&
	  master_xactor_f_rd_data_first__41_BITS_2_TO_1__ETC___d991)
	$write("'h%h", 4'b0);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_ptw_level_1 &&
	  master_xactor_f_rd_data_first__41_BITS_2_TO_1__ETC___d991)
	$write(", ", "arprot: ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_ptw_level_1 &&
	  master_xactor_f_rd_data_first__41_BITS_2_TO_1__ETC___d991)
	$write("'h%h", 3'd0);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_ptw_level_1 &&
	  master_xactor_f_rd_data_first__41_BITS_2_TO_1__ETC___d991)
	$write(", ", "arqos: ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_ptw_level_1 &&
	  master_xactor_f_rd_data_first__41_BITS_2_TO_1__ETC___d991)
	$write("'h%h", 4'd0);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_ptw_level_1 &&
	  master_xactor_f_rd_data_first__41_BITS_2_TO_1__ETC___d991)
	$write(", ", "arregion: ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_ptw_level_1 &&
	  master_xactor_f_rd_data_first__41_BITS_2_TO_1__ETC___d991)
	$write("'h%h", 4'd0);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_ptw_level_1 &&
	  master_xactor_f_rd_data_first__41_BITS_2_TO_1__ETC___d991)
	$write(", ", "aruser: ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_ptw_level_1 &&
	  master_xactor_f_rd_data_first__41_BITS_2_TO_1__ETC___d991)
	$write("'h%h", 1'h0, " }");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_ptw_level_1 &&
	  master_xactor_f_rd_data_first__41_BITS_2_TO_1__ETC___d991)
	$write("\n");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_ptw_level_1 &&
	  master_xactor_f_rd_data_first__41_BITS_2_TO_1__ETC___d1054)
	begin
	  v__h31087 = $stime;
	  #0;
	end
    v__h31081 = v__h31087 / 32'd10;
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_ptw_level_1 &&
	  master_xactor_f_rd_data_first__41_BITS_2_TO_1__ETC___d1054)
	if (dmem_not_imem)
	  $display("%0d: %s.rl_ptw_level_1: for eaddr 0x%0h: pte 0x%0h @ 0x%0h: leaf PTE for megapage",
		   v__h31081,
		   "D_MMU_Cache",
		   rg_addr,
		   master_xactor_f_rd_data$D_OUT[66:3],
		   rg_pte_pa);
	else
	  $display("%0d: %s.rl_ptw_level_1: for eaddr 0x%0h: pte 0x%0h @ 0x%0h: leaf PTE for megapage",
		   v__h31081,
		   "I_MMU_Cache",
		   rg_addr,
		   master_xactor_f_rd_data$D_OUT[66:3],
		   rg_pte_pa);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_ptw_level_1 &&
	  master_xactor_f_rd_data_first__41_BITS_2_TO_1__ETC___d1054)
	$display("    Addr Space megapage pa: 0x%0h", lev_1_PTN_pa__h29684);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_ptw_level_1 &&
	  master_xactor_f_rd_data_first__41_BITS_2_TO_1__ETC___d1060)
	begin
	  v__h30975 = $stime;
	  #0;
	end
    v__h30969 = v__h30975 / 32'd10;
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_ptw_level_1 &&
	  master_xactor_f_rd_data_first__41_BITS_2_TO_1__ETC___d1060)
	if (dmem_not_imem)
	  $display("%0d: %s.rl_ptw_level_1: for eaddr 0x%0h: megapage pte 0x%0h @ 0x%0h",
		   v__h30969,
		   "D_MMU_Cache",
		   rg_addr,
		   master_xactor_f_rd_data$D_OUT[66:3],
		   rg_pte_pa);
	else
	  $display("%0d: %s.rl_ptw_level_1: for eaddr 0x%0h: megapage pte 0x%0h @ 0x%0h",
		   v__h30969,
		   "I_MMU_Cache",
		   rg_addr,
		   master_xactor_f_rd_data$D_OUT[66:3],
		   rg_pte_pa);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_ptw_level_1 &&
	  master_xactor_f_rd_data$D_OUT[2:1] == 2'b0 &&
	  master_xactor_f_rd_data$D_OUT[3] &&
	  (master_xactor_f_rd_data$D_OUT[4] ||
	   !master_xactor_f_rd_data$D_OUT[5]) &&
	  (master_xactor_f_rd_data$D_OUT[6] ||
	   master_xactor_f_rd_data$D_OUT[4]) &&
	  master_xactor_f_rd_data$D_OUT[21:13] != 9'd0)
	$display("    Invalid PTE: PPN [0] is not zero; page fault %0d",
		 exc_code___1__h6641);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_ptw_level_1 &&
	  master_xactor_f_rd_data$D_OUT[2:1] != 2'b0 &&
	  !cfg_verbosity_read__1_ULE_1___d42)
	begin
	  v__h30616 = $stime;
	  #0;
	end
    v__h30610 = v__h30616 / 32'd10;
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_ptw_level_1 &&
	  master_xactor_f_rd_data$D_OUT[2:1] != 2'b0 &&
	  !cfg_verbosity_read__1_ULE_1___d42)
	if (dmem_not_imem)
	  $display("%0d: %s.rl_ptw_level_1: for eaddr 0x%0h: pte_pa 0x%0h: FABRIC_RSP_ERR: access exception %0d",
		   v__h30610,
		   "D_MMU_Cache",
		   rg_addr,
		   rg_pte_pa,
		   access_exc_code__h2772);
	else
	  $display("%0d: %s.rl_ptw_level_1: for eaddr 0x%0h: pte_pa 0x%0h: FABRIC_RSP_ERR: access exception %0d",
		   v__h30610,
		   "I_MMU_Cache",
		   rg_addr,
		   rg_pte_pa,
		   access_exc_code__h2772);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_ptw_level_0 &&
	  master_xactor_f_rd_data_first__41_BITS_2_TO_1__ETC___d981)
	begin
	  v__h31558 = $stime;
	  #0;
	end
    v__h31552 = v__h31558 / 32'd10;
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_ptw_level_0 &&
	  master_xactor_f_rd_data_first__41_BITS_2_TO_1__ETC___d981)
	if (dmem_not_imem)
	  $display("%0d: %s.rl_ptw_level_0: for eaddr 0x%0h: pte 0x%0h @ 0x%0h: Invalid PTE; page fault %0d",
		   v__h31552,
		   "D_MMU_Cache",
		   rg_addr,
		   master_xactor_f_rd_data$D_OUT[66:3],
		   rg_pte_pa,
		   exc_code___1__h6641);
	else
	  $display("%0d: %s.rl_ptw_level_0: for eaddr 0x%0h: pte 0x%0h @ 0x%0h: Invalid PTE; page fault %0d",
		   v__h31552,
		   "I_MMU_Cache",
		   rg_addr,
		   master_xactor_f_rd_data$D_OUT[66:3],
		   rg_pte_pa,
		   exc_code___1__h6641);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_ptw_level_0 &&
	  master_xactor_f_rd_data_first__41_BITS_2_TO_1__ETC___d991)
	begin
	  v__h31629 = $stime;
	  #0;
	end
    v__h31623 = v__h31629 / 32'd10;
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_ptw_level_0 &&
	  master_xactor_f_rd_data_first__41_BITS_2_TO_1__ETC___d991)
	if (dmem_not_imem)
	  $display("%0d: %s.rl_ptw_level_0: for eaddr 0x%0h: pte 0x%0h @ 0x50h: Not a leaf PTE; page fault %0d",
		   v__h31623,
		   "D_MMU_Cache",
		   rg_addr,
		   master_xactor_f_rd_data$D_OUT[66:3],
		   rg_pte_pa,
		   exc_code___1__h6641);
	else
	  $display("%0d: %s.rl_ptw_level_0: for eaddr 0x%0h: pte 0x%0h @ 0x50h: Not a leaf PTE; page fault %0d",
		   v__h31623,
		   "I_MMU_Cache",
		   rg_addr,
		   master_xactor_f_rd_data$D_OUT[66:3],
		   rg_pte_pa,
		   exc_code___1__h6641);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_ptw_level_0 &&
	  master_xactor_f_rd_data_first__41_BITS_2_TO_1__ETC___d1085)
	begin
	  v__h31711 = $stime;
	  #0;
	end
    v__h31705 = v__h31711 / 32'd10;
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_ptw_level_0 &&
	  master_xactor_f_rd_data_first__41_BITS_2_TO_1__ETC___d1085)
	if (dmem_not_imem)
	  $display("%0d: %s.rl_ptw_level_0: for eaddr 0x%0h: pte 0x%0h @ 0x%0h: leaf PTE",
		   v__h31705,
		   "D_MMU_Cache",
		   rg_addr,
		   master_xactor_f_rd_data$D_OUT[66:3],
		   rg_pte_pa);
	else
	  $display("%0d: %s.rl_ptw_level_0: for eaddr 0x%0h: pte 0x%0h @ 0x%0h: leaf PTE",
		   v__h31705,
		   "I_MMU_Cache",
		   rg_addr,
		   master_xactor_f_rd_data$D_OUT[66:3],
		   rg_pte_pa);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_ptw_level_0 &&
	  master_xactor_f_rd_data_first__41_BITS_2_TO_1__ETC___d1085)
	$display("    Addr Space page pa: 0x%0h", lev_1_PTN_pa__h29684);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_ptw_level_0 &&
	  master_xactor_f_rd_data$D_OUT[2:1] != 2'b0 &&
	  !cfg_verbosity_read__1_ULE_1___d42)
	begin
	  v__h31487 = $stime;
	  #0;
	end
    v__h31481 = v__h31487 / 32'd10;
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_ptw_level_0 &&
	  master_xactor_f_rd_data$D_OUT[2:1] != 2'b0 &&
	  !cfg_verbosity_read__1_ULE_1___d42)
	if (dmem_not_imem)
	  $display("%0d: %s.rl_ptw_level_0: for eaddr 0x%0h: pte_pa 0x%0h: FABRIC_RSP_ERR: access exception %0d",
		   v__h31481,
		   "D_MMU_Cache",
		   rg_addr,
		   rg_pte_pa,
		   access_exc_code__h2772);
	else
	  $display("%0d: %s.rl_ptw_level_0: for eaddr 0x%0h: pte_pa 0x%0h: FABRIC_RSP_ERR: access exception %0d",
		   v__h31481,
		   "I_MMU_Cache",
		   rg_addr,
		   rg_pte_pa,
		   access_exc_code__h2772);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_start_cache_refill &&
	  !cfg_verbosity_read__1_ULE_1___d42)
	begin
	  v__h31838 = $stime;
	  #0;
	end
    v__h31832 = v__h31838 / 32'd10;
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_start_cache_refill &&
	  !cfg_verbosity_read__1_ULE_1___d42)
	if (dmem_not_imem)
	  $display("%0d: %s.rl_start_cache_refill: ",
		   v__h31832,
		   "D_MMU_Cache");
	else
	  $display("%0d: %s.rl_start_cache_refill: ",
		   v__h31832,
		   "I_MMU_Cache");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_start_cache_refill &&
	  !cfg_verbosity_read__1_ULE_1___d42)
	$write("    To fabric: ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_start_cache_refill &&
	  !cfg_verbosity_read__1_ULE_1___d42)
	$write("AXI4_Rd_Addr { ", "arid: ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_start_cache_refill &&
	  !cfg_verbosity_read__1_ULE_1___d42)
	$write("'h%h", 4'd0);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_start_cache_refill &&
	  !cfg_verbosity_read__1_ULE_1___d42)
	$write(", ", "araddr: ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_start_cache_refill &&
	  !cfg_verbosity_read__1_ULE_1___d42)
	$write("'h%h", cline_fabric_addr__h31891);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_start_cache_refill &&
	  !cfg_verbosity_read__1_ULE_1___d42)
	$write(", ", "arlen: ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_start_cache_refill &&
	  !cfg_verbosity_read__1_ULE_1___d42)
	$write("'h%h", 8'd7);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_start_cache_refill &&
	  !cfg_verbosity_read__1_ULE_1___d42)
	$write(", ", "arsize: ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_start_cache_refill &&
	  !cfg_verbosity_read__1_ULE_1___d42)
	$write("'h%h", 3'b011);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_start_cache_refill &&
	  !cfg_verbosity_read__1_ULE_1___d42)
	$write(", ", "arburst: ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_start_cache_refill &&
	  !cfg_verbosity_read__1_ULE_1___d42)
	$write("'h%h", 2'b01);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_start_cache_refill &&
	  !cfg_verbosity_read__1_ULE_1___d42)
	$write(", ", "arlock: ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_start_cache_refill &&
	  !cfg_verbosity_read__1_ULE_1___d42)
	$write("'h%h", 1'b0);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_start_cache_refill &&
	  !cfg_verbosity_read__1_ULE_1___d42)
	$write(", ", "arcache: ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_start_cache_refill &&
	  !cfg_verbosity_read__1_ULE_1___d42)
	$write("'h%h", 4'b0);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_start_cache_refill &&
	  !cfg_verbosity_read__1_ULE_1___d42)
	$write(", ", "arprot: ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_start_cache_refill &&
	  !cfg_verbosity_read__1_ULE_1___d42)
	$write("'h%h", 3'd0);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_start_cache_refill &&
	  !cfg_verbosity_read__1_ULE_1___d42)
	$write(", ", "arqos: ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_start_cache_refill &&
	  !cfg_verbosity_read__1_ULE_1___d42)
	$write("'h%h", 4'd0);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_start_cache_refill &&
	  !cfg_verbosity_read__1_ULE_1___d42)
	$write(", ", "arregion: ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_start_cache_refill &&
	  !cfg_verbosity_read__1_ULE_1___d42)
	$write("'h%h", 4'd0);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_start_cache_refill &&
	  !cfg_verbosity_read__1_ULE_1___d42)
	$write(", ", "aruser: ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_start_cache_refill &&
	  !cfg_verbosity_read__1_ULE_1___d42)
	$write("'h%h", 1'h0, " }");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_start_cache_refill &&
	  !cfg_verbosity_read__1_ULE_1___d42)
	$write("\n");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_start_cache_refill &&
	  !cfg_verbosity_read__1_ULE_1___d42)
	$display("    Victim way %0d; => CACHE_REFILL", tmp__h32031[0]);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_cache_refill_rsps_loop &&
	  NOT_cfg_verbosity_read__1_ULE_2_106___d1107)
	begin
	  v__h32529 = $stime;
	  #0;
	end
    v__h32523 = v__h32529 / 32'd10;
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_cache_refill_rsps_loop &&
	  NOT_cfg_verbosity_read__1_ULE_2_106___d1107)
	if (dmem_not_imem)
	  $display("%0d: %s.rl_cache_refill_rsps_loop:",
		   v__h32523,
		   "D_MMU_Cache");
	else
	  $display("%0d: %s.rl_cache_refill_rsps_loop:",
		   v__h32523,
		   "I_MMU_Cache");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_cache_refill_rsps_loop &&
	  NOT_cfg_verbosity_read__1_ULE_2_106___d1107)
	$write("        ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_cache_refill_rsps_loop &&
	  NOT_cfg_verbosity_read__1_ULE_2_106___d1107)
	$write("AXI4_Rd_Data { ", "rid: ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_cache_refill_rsps_loop &&
	  NOT_cfg_verbosity_read__1_ULE_2_106___d1107)
	$write("'h%h", master_xactor_f_rd_data$D_OUT[70:67]);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_cache_refill_rsps_loop &&
	  NOT_cfg_verbosity_read__1_ULE_2_106___d1107)
	$write(", ", "rdata: ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_cache_refill_rsps_loop &&
	  NOT_cfg_verbosity_read__1_ULE_2_106___d1107)
	$write("'h%h", master_xactor_f_rd_data$D_OUT[66:3]);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_cache_refill_rsps_loop &&
	  NOT_cfg_verbosity_read__1_ULE_2_106___d1107)
	$write(", ", "rresp: ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_cache_refill_rsps_loop &&
	  NOT_cfg_verbosity_read__1_ULE_2_106___d1107)
	$write("'h%h", master_xactor_f_rd_data$D_OUT[2:1]);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_cache_refill_rsps_loop &&
	  NOT_cfg_verbosity_read__1_ULE_2_106___d1107)
	$write(", ", "rlast: ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_cache_refill_rsps_loop &&
	  NOT_cfg_verbosity_read__1_ULE_2_106___d1107 &&
	  master_xactor_f_rd_data$D_OUT[0])
	$write("True");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_cache_refill_rsps_loop &&
	  NOT_cfg_verbosity_read__1_ULE_2_106___d1107 &&
	  !master_xactor_f_rd_data$D_OUT[0])
	$write("False");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_cache_refill_rsps_loop &&
	  NOT_cfg_verbosity_read__1_ULE_2_106___d1107)
	$write(", ", "ruser: ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_cache_refill_rsps_loop &&
	  NOT_cfg_verbosity_read__1_ULE_2_106___d1107)
	$write("'h%h", 1'd0, " }");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_cache_refill_rsps_loop &&
	  NOT_cfg_verbosity_read__1_ULE_2_106___d1107)
	$write("\n");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_cache_refill_rsps_loop &&
	  master_xactor_f_rd_data$D_OUT[2:1] != 2'b0 &&
	  !cfg_verbosity_read__1_ULE_1___d42)
	begin
	  v__h32751 = $stime;
	  #0;
	end
    v__h32745 = v__h32751 / 32'd10;
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_cache_refill_rsps_loop &&
	  master_xactor_f_rd_data$D_OUT[2:1] != 2'b0 &&
	  !cfg_verbosity_read__1_ULE_1___d42)
	if (dmem_not_imem)
	  $display("%0d: %s.rl_cache_refill_rsps_loop: FABRIC_RSP_ERR: raising access exception %0d",
		   v__h32745,
		   "D_MMU_Cache",
		   access_exc_code__h2772);
	else
	  $display("%0d: %s.rl_cache_refill_rsps_loop: FABRIC_RSP_ERR: raising access exception %0d",
		   v__h32745,
		   "I_MMU_Cache",
		   access_exc_code__h2772);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_cache_refill_rsps_loop &&
	  rg_cset_cword_in_cache[2:0] == 3'd7 &&
	  (master_xactor_f_rd_data$D_OUT[2:1] != 2'b0 ||
	   rg_error_during_refill) &&
	  !cfg_verbosity_read__1_ULE_1___d42)
	$display("    => MODULE_EXCEPTION_RSP");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_cache_refill_rsps_loop &&
	  rg_cset_cword_in_cache[2:0] == 3'd7 &&
	  master_xactor_f_rd_data$D_OUT[2:1] == 2'b0 &&
	  !rg_error_during_refill &&
	  !cfg_verbosity_read__1_ULE_1___d42)
	$display("    => CACHE_REREQ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_cache_refill_rsps_loop &&
	  NOT_cfg_verbosity_read__1_ULE_2_106___d1107)
	$display("        Updating Cache cword_set 0x%0h, cword_in_cline %0d) old => new",
		 rg_cset_cword_in_cache,
		 rg_cset_cword_in_cache[2:0]);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_cache_refill_rsps_loop &&
	  NOT_cfg_verbosity_read__1_ULE_2_106___d1107)
	$write("        CSet 0x%0x, CWord 0x%0x: ",
	       rg_addr[11:6],
	       rg_cset_cword_in_cache[2:0]);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_cache_refill_rsps_loop &&
	  NOT_cfg_verbosity_read__1_ULE_2_106___d1107)
	$write(" 0x%0x", ram_cword_set$DOB[63:0]);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_cache_refill_rsps_loop &&
	  NOT_cfg_verbosity_read__1_ULE_2_106___d1107)
	$write(" 0x%0x", ram_cword_set$DOB[127:64]);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_cache_refill_rsps_loop &&
	  NOT_cfg_verbosity_read__1_ULE_2_106___d1107)
	$write("\n");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_cache_refill_rsps_loop &&
	  NOT_cfg_verbosity_read__1_ULE_2_106___d1107)
	$write("        CSet 0x%0x, CWord 0x%0x: ",
	       rg_addr[11:6],
	       rg_cset_cword_in_cache[2:0]);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_cache_refill_rsps_loop &&
	  NOT_cfg_verbosity_read__1_ULE_2_106___d1107)
	$write(" 0x%0x",
	       rg_victim_way ?
		 ram_cword_set$DOB[63:0] :
		 master_xactor_f_rd_data$D_OUT[66:3]);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_cache_refill_rsps_loop &&
	  NOT_cfg_verbosity_read__1_ULE_2_106___d1107)
	$write(" 0x%0x",
	       rg_victim_way ?
		 master_xactor_f_rd_data$D_OUT[66:3] :
		 ram_cword_set$DOB[127:64]);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_cache_refill_rsps_loop &&
	  NOT_cfg_verbosity_read__1_ULE_2_106___d1107)
	$write("\n");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_rereq && !cfg_verbosity_read__1_ULE_1___d42)
	$display("    fa_req_ram_B tagCSet [0x%0x] cword_set [0x%0d]",
		 rg_addr[11:6],
		 rg_addr[11:3]);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_io_read_req && !cfg_verbosity_read__1_ULE_1___d42)
	begin
	  v__h35142 = $stime;
	  #0;
	end
    v__h35136 = v__h35142 / 32'd10;
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_io_read_req && !cfg_verbosity_read__1_ULE_1___d42)
	if (dmem_not_imem)
	  $display("%0d: %s.rl_io_read_req; f3 0x%0h vaddr %0h  paddr %0h",
		   v__h35136,
		   "D_MMU_Cache",
		   rg_f3,
		   rg_addr,
		   rg_pa);
	else
	  $display("%0d: %s.rl_io_read_req; f3 0x%0h vaddr %0h  paddr %0h",
		   v__h35136,
		   "I_MMU_Cache",
		   rg_f3,
		   rg_addr,
		   rg_pa);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_io_read_req && !cfg_verbosity_read__1_ULE_1___d42)
	$write("            To fabric: ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_io_read_req && !cfg_verbosity_read__1_ULE_1___d42)
	$write("AXI4_Rd_Addr { ", "arid: ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_io_read_req && !cfg_verbosity_read__1_ULE_1___d42)
	$write("'h%h", 4'd0);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_io_read_req && !cfg_verbosity_read__1_ULE_1___d42)
	$write(", ", "araddr: ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_io_read_req && !cfg_verbosity_read__1_ULE_1___d42)
	$write("'h%h", rg_pa);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_io_read_req && !cfg_verbosity_read__1_ULE_1___d42)
	$write(", ", "arlen: ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_io_read_req && !cfg_verbosity_read__1_ULE_1___d42)
	$write("'h%h", 8'd0);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_io_read_req && !cfg_verbosity_read__1_ULE_1___d42)
	$write(", ", "arsize: ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_io_read_req && !cfg_verbosity_read__1_ULE_1___d42)
	$write("'h%h", value__h37393);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_io_read_req && !cfg_verbosity_read__1_ULE_1___d42)
	$write(", ", "arburst: ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_io_read_req && !cfg_verbosity_read__1_ULE_1___d42)
	$write("'h%h", 2'b01);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_io_read_req && !cfg_verbosity_read__1_ULE_1___d42)
	$write(", ", "arlock: ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_io_read_req && !cfg_verbosity_read__1_ULE_1___d42)
	$write("'h%h", 1'b0);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_io_read_req && !cfg_verbosity_read__1_ULE_1___d42)
	$write(", ", "arcache: ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_io_read_req && !cfg_verbosity_read__1_ULE_1___d42)
	$write("'h%h", 4'b0);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_io_read_req && !cfg_verbosity_read__1_ULE_1___d42)
	$write(", ", "arprot: ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_io_read_req && !cfg_verbosity_read__1_ULE_1___d42)
	$write("'h%h", 3'd0);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_io_read_req && !cfg_verbosity_read__1_ULE_1___d42)
	$write(", ", "arqos: ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_io_read_req && !cfg_verbosity_read__1_ULE_1___d42)
	$write("'h%h", 4'd0);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_io_read_req && !cfg_verbosity_read__1_ULE_1___d42)
	$write(", ", "arregion: ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_io_read_req && !cfg_verbosity_read__1_ULE_1___d42)
	$write("'h%h", 4'd0);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_io_read_req && !cfg_verbosity_read__1_ULE_1___d42)
	$write(", ", "aruser: ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_io_read_req && !cfg_verbosity_read__1_ULE_1___d42)
	$write("'h%h", 1'h0, " }");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_io_read_req && !cfg_verbosity_read__1_ULE_1___d42)
	$write("\n");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_io_read_rsp && !cfg_verbosity_read__1_ULE_1___d42)
	begin
	  v__h35492 = $stime;
	  #0;
	end
    v__h35486 = v__h35492 / 32'd10;
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_io_read_rsp && !cfg_verbosity_read__1_ULE_1___d42)
	if (dmem_not_imem)
	  $display("%0d: %s.rl_io_read_rsp: vaddr 0x%0h  paddr 0x%0h",
		   v__h35486,
		   "D_MMU_Cache",
		   rg_addr,
		   rg_pa);
	else
	  $display("%0d: %s.rl_io_read_rsp: vaddr 0x%0h  paddr 0x%0h",
		   v__h35486,
		   "I_MMU_Cache",
		   rg_addr,
		   rg_pa);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_io_read_rsp && !cfg_verbosity_read__1_ULE_1___d42)
	$write("    ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_io_read_rsp && !cfg_verbosity_read__1_ULE_1___d42)
	$write("AXI4_Rd_Data { ", "rid: ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_io_read_rsp && !cfg_verbosity_read__1_ULE_1___d42)
	$write("'h%h", master_xactor_f_rd_data$D_OUT[70:67]);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_io_read_rsp && !cfg_verbosity_read__1_ULE_1___d42)
	$write(", ", "rdata: ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_io_read_rsp && !cfg_verbosity_read__1_ULE_1___d42)
	$write("'h%h", master_xactor_f_rd_data$D_OUT[66:3]);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_io_read_rsp && !cfg_verbosity_read__1_ULE_1___d42)
	$write(", ", "rresp: ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_io_read_rsp && !cfg_verbosity_read__1_ULE_1___d42)
	$write("'h%h", master_xactor_f_rd_data$D_OUT[2:1]);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_io_read_rsp && !cfg_verbosity_read__1_ULE_1___d42)
	$write(", ", "rlast: ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_io_read_rsp && !cfg_verbosity_read__1_ULE_1___d42 &&
	  master_xactor_f_rd_data$D_OUT[0])
	$write("True");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_io_read_rsp && !cfg_verbosity_read__1_ULE_1___d42 &&
	  !master_xactor_f_rd_data$D_OUT[0])
	$write("False");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_io_read_rsp && !cfg_verbosity_read__1_ULE_1___d42)
	$write(", ", "ruser: ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_io_read_rsp && !cfg_verbosity_read__1_ULE_1___d42)
	$write("'h%h", 1'd0, " }");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_io_read_rsp && !cfg_verbosity_read__1_ULE_1___d42)
	$write("\n");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_io_read_rsp &&
	  master_xactor_f_rd_data$D_OUT[2:1] == 2'b0 &&
	  !cfg_verbosity_read__1_ULE_1___d42)
	begin
	  v__h36592 = $stime;
	  #0;
	end
    v__h36586 = v__h36592 / 32'd10;
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_io_read_rsp &&
	  master_xactor_f_rd_data$D_OUT[2:1] == 2'b0 &&
	  !cfg_verbosity_read__1_ULE_1___d42)
	if (dmem_not_imem)
	  $display("%0d: %s.drive_IO_read_rsp: addr 0x%0h ld_val 0x%0h",
		   v__h36586,
		   "D_MMU_Cache",
		   rg_addr,
		   ld_val__h35601);
	else
	  $display("%0d: %s.drive_IO_read_rsp: addr 0x%0h ld_val 0x%0h",
		   v__h36586,
		   "I_MMU_Cache",
		   rg_addr,
		   ld_val__h35601);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_io_read_rsp &&
	  master_xactor_f_rd_data$D_OUT[2:1] != 2'b0 &&
	  !cfg_verbosity_read__1_ULE_1___d42)
	begin
	  v__h36699 = $stime;
	  #0;
	end
    v__h36693 = v__h36699 / 32'd10;
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_io_read_rsp &&
	  master_xactor_f_rd_data$D_OUT[2:1] != 2'b0 &&
	  !cfg_verbosity_read__1_ULE_1___d42)
	if (dmem_not_imem)
	  $display("%0d: %s.rl_io_read_rsp: FABRIC_RSP_ERR: raising trap LOAD_ACCESS_FAULT",
		   v__h36693,
		   "D_MMU_Cache");
	else
	  $display("%0d: %s.rl_io_read_rsp: FABRIC_RSP_ERR: raising trap LOAD_ACCESS_FAULT",
		   v__h36693,
		   "I_MMU_Cache");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_maintain_io_read_rsp &&
	  !cfg_verbosity_read__1_ULE_1___d42)
	begin
	  v__h36804 = $stime;
	  #0;
	end
    v__h36798 = v__h36804 / 32'd10;
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_maintain_io_read_rsp &&
	  !cfg_verbosity_read__1_ULE_1___d42)
	if (dmem_not_imem)
	  $display("%0d: %s.drive_IO_read_rsp: addr 0x%0h ld_val 0x%0h",
		   v__h36798,
		   "D_MMU_Cache",
		   rg_addr,
		   rg_ld_val);
	else
	  $display("%0d: %s.drive_IO_read_rsp: addr 0x%0h ld_val 0x%0h",
		   v__h36798,
		   "I_MMU_Cache",
		   rg_addr,
		   rg_ld_val);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_io_write_req && !cfg_verbosity_read__1_ULE_1___d42)
	begin
	  v__h36884 = $stime;
	  #0;
	end
    v__h36878 = v__h36884 / 32'd10;
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_io_write_req && !cfg_verbosity_read__1_ULE_1___d42)
	if (dmem_not_imem)
	  $display("%0d: %s: rl_io_write_req; f3 0x%0h  vaddr %0h  paddr %0h  word64 0x%0h",
		   v__h36878,
		   "D_MMU_Cache",
		   rg_f3,
		   rg_addr,
		   rg_pa,
		   rg_st_amo_val);
	else
	  $display("%0d: %s: rl_io_write_req; f3 0x%0h  vaddr %0h  paddr %0h  word64 0x%0h",
		   v__h36878,
		   "I_MMU_Cache",
		   rg_f3,
		   rg_addr,
		   rg_pa,
		   rg_st_amo_val);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_io_write_req && !cfg_verbosity_read__1_ULE_1___d42)
	$display("    => rl_ST_AMO_response");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_io_AMO_SC_req && !cfg_verbosity_read__1_ULE_1___d42)
	begin
	  v__h37094 = $stime;
	  #0;
	end
    v__h37088 = v__h37094 / 32'd10;
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_io_AMO_SC_req && !cfg_verbosity_read__1_ULE_1___d42)
	if (dmem_not_imem)
	  $display("%0d: %s: rl_io_AMO_SC_req; f3 0x%0h  vaddr %0h  paddr %0h  word64 0x%0h",
		   v__h37088,
		   "D_MMU_Cache",
		   rg_f3,
		   rg_addr,
		   rg_pa,
		   rg_st_amo_val);
	else
	  $display("%0d: %s: rl_io_AMO_SC_req; f3 0x%0h  vaddr %0h  paddr %0h  word64 0x%0h",
		   v__h37088,
		   "I_MMU_Cache",
		   rg_f3,
		   rg_addr,
		   rg_pa,
		   rg_st_amo_val);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_io_AMO_SC_req && !cfg_verbosity_read__1_ULE_1___d42)
	$display("    FAIL due to I/O address.");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_io_AMO_SC_req && !cfg_verbosity_read__1_ULE_1___d42)
	$display("    => rl_ST_AMO_response");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_io_AMO_op_req && !cfg_verbosity_read__1_ULE_1___d42)
	begin
	  v__h37212 = $stime;
	  #0;
	end
    v__h37206 = v__h37212 / 32'd10;
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_io_AMO_op_req && !cfg_verbosity_read__1_ULE_1___d42)
	if (dmem_not_imem)
	  $display("%0d: %s.rl_io_AMO_op_req; f3 0x%0h vaddr %0h  paddr %0h",
		   v__h37206,
		   "D_MMU_Cache",
		   rg_f3,
		   rg_addr,
		   rg_pa);
	else
	  $display("%0d: %s.rl_io_AMO_op_req; f3 0x%0h vaddr %0h  paddr %0h",
		   v__h37206,
		   "I_MMU_Cache",
		   rg_f3,
		   rg_addr,
		   rg_pa);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_io_AMO_op_req && !cfg_verbosity_read__1_ULE_1___d42)
	$write("            To fabric: ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_io_AMO_op_req && !cfg_verbosity_read__1_ULE_1___d42)
	$write("AXI4_Rd_Addr { ", "arid: ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_io_AMO_op_req && !cfg_verbosity_read__1_ULE_1___d42)
	$write("'h%h", 4'd0);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_io_AMO_op_req && !cfg_verbosity_read__1_ULE_1___d42)
	$write(", ", "araddr: ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_io_AMO_op_req && !cfg_verbosity_read__1_ULE_1___d42)
	$write("'h%h", rg_pa);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_io_AMO_op_req && !cfg_verbosity_read__1_ULE_1___d42)
	$write(", ", "arlen: ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_io_AMO_op_req && !cfg_verbosity_read__1_ULE_1___d42)
	$write("'h%h", 8'd0);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_io_AMO_op_req && !cfg_verbosity_read__1_ULE_1___d42)
	$write(", ", "arsize: ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_io_AMO_op_req && !cfg_verbosity_read__1_ULE_1___d42)
	$write("'h%h", value__h37393);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_io_AMO_op_req && !cfg_verbosity_read__1_ULE_1___d42)
	$write(", ", "arburst: ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_io_AMO_op_req && !cfg_verbosity_read__1_ULE_1___d42)
	$write("'h%h", 2'b01);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_io_AMO_op_req && !cfg_verbosity_read__1_ULE_1___d42)
	$write(", ", "arlock: ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_io_AMO_op_req && !cfg_verbosity_read__1_ULE_1___d42)
	$write("'h%h", 1'b0);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_io_AMO_op_req && !cfg_verbosity_read__1_ULE_1___d42)
	$write(", ", "arcache: ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_io_AMO_op_req && !cfg_verbosity_read__1_ULE_1___d42)
	$write("'h%h", 4'b0);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_io_AMO_op_req && !cfg_verbosity_read__1_ULE_1___d42)
	$write(", ", "arprot: ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_io_AMO_op_req && !cfg_verbosity_read__1_ULE_1___d42)
	$write("'h%h", 3'd0);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_io_AMO_op_req && !cfg_verbosity_read__1_ULE_1___d42)
	$write(", ", "arqos: ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_io_AMO_op_req && !cfg_verbosity_read__1_ULE_1___d42)
	$write("'h%h", 4'd0);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_io_AMO_op_req && !cfg_verbosity_read__1_ULE_1___d42)
	$write(", ", "arregion: ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_io_AMO_op_req && !cfg_verbosity_read__1_ULE_1___d42)
	$write("'h%h", 4'd0);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_io_AMO_op_req && !cfg_verbosity_read__1_ULE_1___d42)
	$write(", ", "aruser: ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_io_AMO_op_req && !cfg_verbosity_read__1_ULE_1___d42)
	$write("'h%h", 1'h0, " }");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_io_AMO_op_req && !cfg_verbosity_read__1_ULE_1___d42)
	$write("\n");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_io_AMO_read_rsp &&
	  !cfg_verbosity_read__1_ULE_1___d42)
	begin
	  v__h37506 = $stime;
	  #0;
	end
    v__h37500 = v__h37506 / 32'd10;
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_io_AMO_read_rsp &&
	  !cfg_verbosity_read__1_ULE_1___d42)
	if (dmem_not_imem)
	  $display("%0d: %s.rl_io_AMO_read_rsp: vaddr 0x%0h  paddr 0x%0h",
		   v__h37500,
		   "D_MMU_Cache",
		   rg_addr,
		   rg_pa);
	else
	  $display("%0d: %s.rl_io_AMO_read_rsp: vaddr 0x%0h  paddr 0x%0h",
		   v__h37500,
		   "I_MMU_Cache",
		   rg_addr,
		   rg_pa);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_io_AMO_read_rsp &&
	  !cfg_verbosity_read__1_ULE_1___d42)
	$write("    ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_io_AMO_read_rsp &&
	  !cfg_verbosity_read__1_ULE_1___d42)
	$write("AXI4_Rd_Data { ", "rid: ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_io_AMO_read_rsp &&
	  !cfg_verbosity_read__1_ULE_1___d42)
	$write("'h%h", master_xactor_f_rd_data$D_OUT[70:67]);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_io_AMO_read_rsp &&
	  !cfg_verbosity_read__1_ULE_1___d42)
	$write(", ", "rdata: ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_io_AMO_read_rsp &&
	  !cfg_verbosity_read__1_ULE_1___d42)
	$write("'h%h", master_xactor_f_rd_data$D_OUT[66:3]);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_io_AMO_read_rsp &&
	  !cfg_verbosity_read__1_ULE_1___d42)
	$write(", ", "rresp: ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_io_AMO_read_rsp &&
	  !cfg_verbosity_read__1_ULE_1___d42)
	$write("'h%h", master_xactor_f_rd_data$D_OUT[2:1]);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_io_AMO_read_rsp &&
	  !cfg_verbosity_read__1_ULE_1___d42)
	$write(", ", "rlast: ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_io_AMO_read_rsp &&
	  !cfg_verbosity_read__1_ULE_1___d42 &&
	  master_xactor_f_rd_data$D_OUT[0])
	$write("True");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_io_AMO_read_rsp &&
	  !cfg_verbosity_read__1_ULE_1___d42 &&
	  !master_xactor_f_rd_data$D_OUT[0])
	$write("False");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_io_AMO_read_rsp &&
	  !cfg_verbosity_read__1_ULE_1___d42)
	$write(", ", "ruser: ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_io_AMO_read_rsp &&
	  !cfg_verbosity_read__1_ULE_1___d42)
	$write("'h%h", 1'd0, " }");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_io_AMO_read_rsp &&
	  !cfg_verbosity_read__1_ULE_1___d42)
	$write("\n");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_io_AMO_read_rsp &&
	  master_xactor_f_rd_data$D_OUT[2:1] == 2'b0 &&
	  !cfg_verbosity_read__1_ULE_1___d42)
	begin
	  v__h37681 = $stime;
	  #0;
	end
    v__h37675 = v__h37681 / 32'd10;
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_io_AMO_read_rsp &&
	  master_xactor_f_rd_data$D_OUT[2:1] == 2'b0 &&
	  !cfg_verbosity_read__1_ULE_1___d42)
	if (dmem_not_imem)
	  $display("%0d: %s: rl_io_AMO_read_rsp; f3 0x%0h  vaddr %0h  paddr %0h  word64 0x%0h",
		   v__h37675,
		   "D_MMU_Cache",
		   rg_f3,
		   rg_addr,
		   rg_pa,
		   rg_st_amo_val);
	else
	  $display("%0d: %s: rl_io_AMO_read_rsp; f3 0x%0h  vaddr %0h  paddr %0h  word64 0x%0h",
		   v__h37675,
		   "I_MMU_Cache",
		   rg_f3,
		   rg_addr,
		   rg_pa,
		   rg_st_amo_val);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_io_AMO_read_rsp &&
	  master_xactor_f_rd_data$D_OUT[2:1] == 2'b0 &&
	  !cfg_verbosity_read__1_ULE_1___d42)
	begin
	  v__h39940 = $stime;
	  #0;
	end
    v__h39934 = v__h39940 / 32'd10;
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_io_AMO_read_rsp &&
	  master_xactor_f_rd_data$D_OUT[2:1] == 2'b0 &&
	  !cfg_verbosity_read__1_ULE_1___d42)
	if (dmem_not_imem)
	  $display("%0d: %s.drive_IO_read_rsp: addr 0x%0h ld_val 0x%0h",
		   v__h39934,
		   "D_MMU_Cache",
		   rg_addr,
		   new_ld_val__h37807);
	else
	  $display("%0d: %s.drive_IO_read_rsp: addr 0x%0h ld_val 0x%0h",
		   v__h39934,
		   "I_MMU_Cache",
		   rg_addr,
		   new_ld_val__h37807);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_io_AMO_read_rsp &&
	  master_xactor_f_rd_data$D_OUT[2:1] == 2'b0 &&
	  !cfg_verbosity_read__1_ULE_1___d42)
	$display("    => rl_ST_AMO_response");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_io_AMO_read_rsp &&
	  master_xactor_f_rd_data$D_OUT[2:1] != 2'b0 &&
	  !cfg_verbosity_read__1_ULE_1___d42)
	begin
	  v__h37777 = $stime;
	  #0;
	end
    v__h37771 = v__h37777 / 32'd10;
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_io_AMO_read_rsp &&
	  master_xactor_f_rd_data$D_OUT[2:1] != 2'b0 &&
	  !cfg_verbosity_read__1_ULE_1___d42)
	if (dmem_not_imem)
	  $display("%0d: %s.rl_io_AMO_read_rsp: FABRIC_RSP_ERR: raising trap STORE_AMO_ACCESS_FAULT",
		   v__h37771,
		   "D_MMU_Cache");
	else
	  $display("%0d: %s.rl_io_AMO_read_rsp: FABRIC_RSP_ERR: raising trap STORE_AMO_ACCESS_FAULT",
		   v__h37771,
		   "I_MMU_Cache");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_discard_write_rsp &&
	  master_xactor_f_wr_resp$D_OUT[1:0] == 2'b0 &&
	  !cfg_verbosity_read__1_ULE_1___d42)
	begin
	  v__h40518 = $stime;
	  #0;
	end
    v__h40512 = v__h40518 / 32'd10;
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_discard_write_rsp &&
	  master_xactor_f_wr_resp$D_OUT[1:0] == 2'b0 &&
	  !cfg_verbosity_read__1_ULE_1___d42)
	if (dmem_not_imem)
	  $write("%0d: %s.rl_discard_write_rsp: pending %0d ",
		 v__h40512,
		 "D_MMU_Cache",
		 $unsigned(b__h28690));
	else
	  $write("%0d: %s.rl_discard_write_rsp: pending %0d ",
		 v__h40512,
		 "I_MMU_Cache",
		 $unsigned(b__h28690));
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_discard_write_rsp &&
	  master_xactor_f_wr_resp$D_OUT[1:0] == 2'b0 &&
	  !cfg_verbosity_read__1_ULE_1___d42)
	$write("AXI4_Wr_Resp { ", "bid: ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_discard_write_rsp &&
	  master_xactor_f_wr_resp$D_OUT[1:0] == 2'b0 &&
	  !cfg_verbosity_read__1_ULE_1___d42)
	$write("'h%h", master_xactor_f_wr_resp$D_OUT[5:2]);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_discard_write_rsp &&
	  master_xactor_f_wr_resp$D_OUT[1:0] == 2'b0 &&
	  !cfg_verbosity_read__1_ULE_1___d42)
	$write(", ", "bresp: ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_discard_write_rsp &&
	  master_xactor_f_wr_resp$D_OUT[1:0] == 2'b0 &&
	  !cfg_verbosity_read__1_ULE_1___d42)
	$write("'h%h", master_xactor_f_wr_resp$D_OUT[1:0]);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_discard_write_rsp &&
	  master_xactor_f_wr_resp$D_OUT[1:0] == 2'b0 &&
	  !cfg_verbosity_read__1_ULE_1___d42)
	$write(", ", "buser: ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_discard_write_rsp &&
	  master_xactor_f_wr_resp$D_OUT[1:0] == 2'b0 &&
	  !cfg_verbosity_read__1_ULE_1___d42)
	$write("'h%h", 1'd0, " }");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_discard_write_rsp &&
	  master_xactor_f_wr_resp$D_OUT[1:0] == 2'b0 &&
	  !cfg_verbosity_read__1_ULE_1___d42)
	$write("\n");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_discard_write_rsp &&
	  master_xactor_f_wr_resp$D_OUT[1:0] != 2'b0)
	begin
	  v__h40560 = $stime;
	  #0;
	end
    v__h40554 = v__h40560 / 32'd10;
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_discard_write_rsp &&
	  master_xactor_f_wr_resp$D_OUT[1:0] != 2'b0)
	if (dmem_not_imem)
	  $display("%0d: %s.rl_discard_write_rsp: fabric response error: exit",
		   v__h40554,
		   "D_MMU_Cache");
	else
	  $display("%0d: %s.rl_discard_write_rsp: fabric response error: exit",
		   v__h40554,
		   "I_MMU_Cache");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_discard_write_rsp &&
	  master_xactor_f_wr_resp$D_OUT[1:0] != 2'b0)
	$write("    ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_discard_write_rsp &&
	  master_xactor_f_wr_resp$D_OUT[1:0] != 2'b0)
	$write("AXI4_Wr_Resp { ", "bid: ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_discard_write_rsp &&
	  master_xactor_f_wr_resp$D_OUT[1:0] != 2'b0)
	$write("'h%h", master_xactor_f_wr_resp$D_OUT[5:2]);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_discard_write_rsp &&
	  master_xactor_f_wr_resp$D_OUT[1:0] != 2'b0)
	$write(", ", "bresp: ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_discard_write_rsp &&
	  master_xactor_f_wr_resp$D_OUT[1:0] != 2'b0)
	$write("'h%h", master_xactor_f_wr_resp$D_OUT[1:0]);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_discard_write_rsp &&
	  master_xactor_f_wr_resp$D_OUT[1:0] != 2'b0)
	$write(", ", "buser: ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_discard_write_rsp &&
	  master_xactor_f_wr_resp$D_OUT[1:0] != 2'b0)
	$write("'h%h", 1'd0, " }");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_discard_write_rsp &&
	  master_xactor_f_wr_resp$D_OUT[1:0] != 2'b0)
	$write("\n");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_start_reset)
	begin
	  v__h4250 = $stime;
	  #0;
	end
    v__h4244 = v__h4250 / 32'd10;
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_start_reset)
	if (dmem_not_imem)
	  $display("%0d: %s: cache size %0d KB, associativity %0d, line size %0d bytes (= %0d XLEN words)",
		   v__h4244,
		   "D_MMU_Cache",
		   $signed(32'd8),
		   $signed(32'd2),
		   $signed(32'd64),
		   $signed(32'd8));
	else
	  $display("%0d: %s: cache size %0d KB, associativity %0d, line size %0d bytes (= %0d XLEN words)",
		   v__h4244,
		   "I_MMU_Cache",
		   $signed(32'd8),
		   $signed(32'd2),
		   $signed(32'd64),
		   $signed(32'd8));
    if (RST_N != `BSV_RESET_VALUE)
      if (EN_req && !cfg_verbosity_read__1_ULE_1___d42)
	begin
	  v__h40924 = $stime;
	  #0;
	end
    v__h40918 = v__h40924 / 32'd10;
    if (RST_N != `BSV_RESET_VALUE)
      if (EN_req && !cfg_verbosity_read__1_ULE_1___d42)
	$write("%0d: %m.req: op:", v__h40918);
    if (RST_N != `BSV_RESET_VALUE)
      if (EN_req && !cfg_verbosity_read__1_ULE_1___d42 && req_op == 2'd0)
	$write("CACHE_LD");
    if (RST_N != `BSV_RESET_VALUE)
      if (EN_req && !cfg_verbosity_read__1_ULE_1___d42 && req_op == 2'd1)
	$write("CACHE_ST");
    if (RST_N != `BSV_RESET_VALUE)
      if (EN_req && !cfg_verbosity_read__1_ULE_1___d42 && req_op != 2'd0 &&
	  req_op != 2'd1)
	$write("CACHE_AMO");
    if (RST_N != `BSV_RESET_VALUE)
      if (EN_req && !cfg_verbosity_read__1_ULE_1___d42)
	$write(" f3:%0d addr:0x%0h st_value:0x%0h",
	       req_f3,
	       req_addr,
	       req_st_value,
	       "\n");
    if (RST_N != `BSV_RESET_VALUE)
      if (EN_req && !cfg_verbosity_read__1_ULE_1___d42) $write("    priv:");
    if (RST_N != `BSV_RESET_VALUE)
      if (EN_req && !cfg_verbosity_read__1_ULE_1___d42 && req_priv == 2'b0)
	$write("U");
    if (RST_N != `BSV_RESET_VALUE)
      if (EN_req && !cfg_verbosity_read__1_ULE_1___d42 && req_priv == 2'b01)
	$write("S");
    if (RST_N != `BSV_RESET_VALUE)
      if (EN_req && !cfg_verbosity_read__1_ULE_1___d42 && req_priv == 2'b11)
	$write("M");
    if (RST_N != `BSV_RESET_VALUE)
      if (EN_req && !cfg_verbosity_read__1_ULE_1___d42 && req_priv != 2'b0 &&
	  req_priv != 2'b01 &&
	  req_priv != 2'b11)
	$write("RESERVED");
    if (RST_N != `BSV_RESET_VALUE)
      if (EN_req && !cfg_verbosity_read__1_ULE_1___d42)
	$write(" sstatus_SUM:%0d mstatus_MXR:%0d satp:0x%0h",
	       req_sstatus_SUM,
	       req_mstatus_MXR,
	       req_satp,
	       "\n");
    if (RST_N != `BSV_RESET_VALUE)
      if (EN_req && !cfg_verbosity_read__1_ULE_1___d42)
	$display("    amo_funct7 = 0x%0h", req_amo_funct7);
    if (RST_N != `BSV_RESET_VALUE)
      if (EN_req &&
	  req_f3_BITS_1_TO_0_433_EQ_0b0_434_OR_req_f3_BI_ETC___d1463 &&
	  !cfg_verbosity_read__1_ULE_1___d42)
	$display("    fa_req_ram_B tagCSet [0x%0x] cword_set [0x%0d]",
		 req_addr[11:6],
		 req_addr[11:3]);
    if (RST_N != `BSV_RESET_VALUE)
      if (EN_tlb_flush && !cfg_verbosity_read__1_ULE_1___d42)
	begin
	  v__h42299 = $stime;
	  #0;
	end
    v__h42293 = v__h42299 / 32'd10;
    if (RST_N != `BSV_RESET_VALUE)
      if (EN_tlb_flush && !cfg_verbosity_read__1_ULE_1___d42)
	if (dmem_not_imem)
	  $display("%0d: %s.tlb_flush", v__h42293, "D_MMU_Cache");
	else
	  $display("%0d: %s.tlb_flush", v__h42293, "I_MMU_Cache");
  end
  // synopsys translate_on
endmodule  // mkMMU_Cache

