//
// Generated by Bluespec Compiler, version 2022.01 (build 066c7a8)
//
//
// Ports:
// Name                         I/O  size props
// RDY_imem_server_request_put    O     1 reg
// imem_server_response_get       O   132 reg
// RDY_imem_server_response_get   O     1 reg
// RDY_dmem_server_request_put    O     1 reg
// dmem_server_response_get       O   132 reg
// RDY_dmem_server_response_get   O     1 reg
// mem_client_request_get         O    64 reg
// RDY_mem_client_request_get     O     1 reg
// RDY_mem_client_response_put    O     1 reg
// CLK                            I     1 clock
// RST_N                          I     1 reset
// imem_server_request_put        I   128 reg
// dmem_server_request_put        I   128 reg
// mem_client_response_put        I    65 reg
// EN_imem_server_request_put     I     1
// EN_dmem_server_request_put     I     1
// EN_mem_client_response_put     I     1
// EN_imem_server_response_get    I     1
// EN_dmem_server_response_get    I     1
// EN_mem_client_request_get      I     1
//
// No combinational paths from inputs to outputs
//
//

`ifdef BSV_ASSIGNMENT_DELAY
`else
  `define BSV_ASSIGNMENT_DELAY
`endif

`ifdef BSV_POSITIVE_RESET
  `define BSV_RESET_VALUE 1'b1
  `define BSV_RESET_EDGE posedge
`else
  `define BSV_RESET_VALUE 1'b0
  `define BSV_RESET_EDGE negedge
`endif

module mkPTW(CLK,
	     RST_N,

	     imem_server_request_put,
	     EN_imem_server_request_put,
	     RDY_imem_server_request_put,

	     EN_imem_server_response_get,
	     imem_server_response_get,
	     RDY_imem_server_response_get,

	     dmem_server_request_put,
	     EN_dmem_server_request_put,
	     RDY_dmem_server_request_put,

	     EN_dmem_server_response_get,
	     dmem_server_response_get,
	     RDY_dmem_server_response_get,

	     EN_mem_client_request_get,
	     mem_client_request_get,
	     RDY_mem_client_request_get,

	     mem_client_response_put,
	     EN_mem_client_response_put,
	     RDY_mem_client_response_put);
  parameter [2 : 0] verbosity = 3'b0;
  input  CLK;
  input  RST_N;

  // action method imem_server_request_put
  input  [127 : 0] imem_server_request_put;
  input  EN_imem_server_request_put;
  output RDY_imem_server_request_put;

  // actionvalue method imem_server_response_get
  input  EN_imem_server_response_get;
  output [131 : 0] imem_server_response_get;
  output RDY_imem_server_response_get;

  // action method dmem_server_request_put
  input  [127 : 0] dmem_server_request_put;
  input  EN_dmem_server_request_put;
  output RDY_dmem_server_request_put;

  // actionvalue method dmem_server_response_get
  input  EN_dmem_server_response_get;
  output [131 : 0] dmem_server_response_get;
  output RDY_dmem_server_response_get;

  // actionvalue method mem_client_request_get
  input  EN_mem_client_request_get;
  output [63 : 0] mem_client_request_get;
  output RDY_mem_client_request_get;

  // action method mem_client_response_put
  input  [64 : 0] mem_client_response_put;
  input  EN_mem_client_response_put;
  output RDY_mem_client_response_put;

  // signals for module outputs
  wire [131 : 0] dmem_server_response_get, imem_server_response_get;
  wire [63 : 0] mem_client_request_get;
  wire RDY_dmem_server_request_put,
       RDY_dmem_server_response_get,
       RDY_imem_server_request_put,
       RDY_imem_server_response_get,
       RDY_mem_client_request_get,
       RDY_mem_client_response_put;

  // register rg_pte_pa
  reg [63 : 0] rg_pte_pa;
  reg [63 : 0] rg_pte_pa$D_IN;
  wire rg_pte_pa$EN;

  // register rg_state
  reg [1 : 0] rg_state;
  reg [1 : 0] rg_state$D_IN;
  wire rg_state$EN;

  // ports of submodule f_dmem_imem_reqs
  wire [128 : 0] f_dmem_imem_reqs$D_IN, f_dmem_imem_reqs$D_OUT;
  wire f_dmem_imem_reqs$CLR,
       f_dmem_imem_reqs$DEQ,
       f_dmem_imem_reqs$EMPTY_N,
       f_dmem_imem_reqs$ENQ,
       f_dmem_imem_reqs$FULL_N;

  // ports of submodule f_dmem_reqs
  wire [127 : 0] f_dmem_reqs$D_IN, f_dmem_reqs$D_OUT;
  wire f_dmem_reqs$CLR,
       f_dmem_reqs$DEQ,
       f_dmem_reqs$EMPTY_N,
       f_dmem_reqs$ENQ,
       f_dmem_reqs$FULL_N;

  // ports of submodule f_dmem_rsps
  reg [131 : 0] f_dmem_rsps$D_IN;
  wire [131 : 0] f_dmem_rsps$D_OUT;
  wire f_dmem_rsps$CLR,
       f_dmem_rsps$DEQ,
       f_dmem_rsps$EMPTY_N,
       f_dmem_rsps$ENQ,
       f_dmem_rsps$FULL_N;

  // ports of submodule f_imem_reqs
  wire [127 : 0] f_imem_reqs$D_IN, f_imem_reqs$D_OUT;
  wire f_imem_reqs$CLR,
       f_imem_reqs$DEQ,
       f_imem_reqs$EMPTY_N,
       f_imem_reqs$ENQ,
       f_imem_reqs$FULL_N;

  // ports of submodule f_imem_rsps
  reg [131 : 0] f_imem_rsps$D_IN;
  wire [131 : 0] f_imem_rsps$D_OUT;
  wire f_imem_rsps$CLR,
       f_imem_rsps$DEQ,
       f_imem_rsps$EMPTY_N,
       f_imem_rsps$ENQ,
       f_imem_rsps$FULL_N;

  // ports of submodule f_mem_reqs
  reg [63 : 0] f_mem_reqs$D_IN;
  wire [63 : 0] f_mem_reqs$D_OUT;
  wire f_mem_reqs$CLR,
       f_mem_reqs$DEQ,
       f_mem_reqs$EMPTY_N,
       f_mem_reqs$ENQ,
       f_mem_reqs$FULL_N;

  // ports of submodule f_mem_rsps
  wire [64 : 0] f_mem_rsps$D_IN, f_mem_rsps$D_OUT;
  wire f_mem_rsps$CLR,
       f_mem_rsps$DEQ,
       f_mem_rsps$EMPTY_N,
       f_mem_rsps$ENQ,
       f_mem_rsps$FULL_N;

  // rule scheduling signals
  wire CAN_FIRE_RL_rl_merge_dmem_reqs,
       CAN_FIRE_RL_rl_merge_imem_reqs,
       CAN_FIRE_RL_rl_ptw_level_0,
       CAN_FIRE_RL_rl_ptw_level_1,
       CAN_FIRE_RL_rl_ptw_level_2,
       CAN_FIRE_RL_rl_ptw_start,
       CAN_FIRE_dmem_server_request_put,
       CAN_FIRE_dmem_server_response_get,
       CAN_FIRE_imem_server_request_put,
       CAN_FIRE_imem_server_response_get,
       CAN_FIRE_mem_client_request_get,
       CAN_FIRE_mem_client_response_put,
       WILL_FIRE_RL_rl_merge_dmem_reqs,
       WILL_FIRE_RL_rl_merge_imem_reqs,
       WILL_FIRE_RL_rl_ptw_level_0,
       WILL_FIRE_RL_rl_ptw_level_1,
       WILL_FIRE_RL_rl_ptw_level_2,
       WILL_FIRE_RL_rl_ptw_start,
       WILL_FIRE_dmem_server_request_put,
       WILL_FIRE_dmem_server_response_get,
       WILL_FIRE_imem_server_request_put,
       WILL_FIRE_imem_server_response_get,
       WILL_FIRE_mem_client_request_get,
       WILL_FIRE_mem_client_response_put;

  // inputs to muxes for submodule ports
  wire [131 : 0] MUX_f_dmem_rsps$enq_1__VAL_1,
		 MUX_f_dmem_rsps$enq_1__VAL_2,
		 MUX_f_dmem_rsps$enq_1__VAL_3;
  wire [128 : 0] MUX_f_dmem_imem_reqs$enq_1__VAL_1,
		 MUX_f_dmem_imem_reqs$enq_1__VAL_2;
  wire [1 : 0] MUX_rg_state$write_1__VAL_1, MUX_rg_state$write_1__VAL_2;
  wire MUX_f_dmem_rsps$enq_1__SEL_1,
       MUX_f_dmem_rsps$enq_1__SEL_2,
       MUX_f_dmem_rsps$enq_1__SEL_3,
       MUX_f_imem_rsps$enq_1__SEL_1,
       MUX_f_imem_rsps$enq_1__SEL_2,
       MUX_f_imem_rsps$enq_1__SEL_3,
       MUX_f_mem_reqs$enq_1__SEL_1,
       MUX_f_mem_reqs$enq_1__SEL_2,
       MUX_rg_state$write_1__SEL_1,
       MUX_rg_state$write_1__SEL_2,
       MUX_rg_state$write_1__SEL_3;

  // declarations used by system tasks
  // synopsys translate_off
  reg [31 : 0] v__h856;
  reg [31 : 0] v__h977;
  reg [31 : 0] v__h1123;
  reg [31 : 0] v__h1530;
  reg [31 : 0] v__h2566;
  reg [31 : 0] v__h3536;
  reg [31 : 0] v__h850;
  reg [31 : 0] v__h971;
  reg [31 : 0] v__h1117;
  reg [31 : 0] v__h1524;
  reg [31 : 0] v__h2560;
  reg [31 : 0] v__h3530;
  // synopsys translate_on

  // remaining internal signals
  wire [63 : 0] lev_0_pte_pa__h2832,
		lev_1_PTN_pa__h1813,
		lev_1_pte_pa__h1815,
		lev_2_pte_pa__h1343,
		satp_pa__h1023,
		vpn_0_pa__h2831,
		vpn_1_pa__h1814,
		vpn_2_pa__h1342;
  wire [55 : 0] x__h1284, x__h2032;
  wire IF_NOT_f_mem_rsps_first__1_BIT_0_3_4_OR_NOT_f__ETC___d58,
       IF_f_dmem_imem_reqs_i_notEmpty__0_AND_f_dmem_i_ETC___d53,
       f_mem_rsps_i_notEmpty__0_AND_IF_f_mem_rsps_fir_ETC___d60;

  // action method imem_server_request_put
  assign RDY_imem_server_request_put = f_imem_reqs$FULL_N ;
  assign CAN_FIRE_imem_server_request_put = f_imem_reqs$FULL_N ;
  assign WILL_FIRE_imem_server_request_put = EN_imem_server_request_put ;

  // actionvalue method imem_server_response_get
  assign imem_server_response_get = f_imem_rsps$D_OUT ;
  assign RDY_imem_server_response_get = f_imem_rsps$EMPTY_N ;
  assign CAN_FIRE_imem_server_response_get = f_imem_rsps$EMPTY_N ;
  assign WILL_FIRE_imem_server_response_get = EN_imem_server_response_get ;

  // action method dmem_server_request_put
  assign RDY_dmem_server_request_put = f_dmem_reqs$FULL_N ;
  assign CAN_FIRE_dmem_server_request_put = f_dmem_reqs$FULL_N ;
  assign WILL_FIRE_dmem_server_request_put = EN_dmem_server_request_put ;

  // actionvalue method dmem_server_response_get
  assign dmem_server_response_get = f_dmem_rsps$D_OUT ;
  assign RDY_dmem_server_response_get = f_dmem_rsps$EMPTY_N ;
  assign CAN_FIRE_dmem_server_response_get = f_dmem_rsps$EMPTY_N ;
  assign WILL_FIRE_dmem_server_response_get = EN_dmem_server_response_get ;

  // actionvalue method mem_client_request_get
  assign mem_client_request_get = f_mem_reqs$D_OUT ;
  assign RDY_mem_client_request_get = f_mem_reqs$EMPTY_N ;
  assign CAN_FIRE_mem_client_request_get = f_mem_reqs$EMPTY_N ;
  assign WILL_FIRE_mem_client_request_get = EN_mem_client_request_get ;

  // action method mem_client_response_put
  assign RDY_mem_client_response_put = f_mem_rsps$FULL_N ;
  assign CAN_FIRE_mem_client_response_put = f_mem_rsps$FULL_N ;
  assign WILL_FIRE_mem_client_response_put = EN_mem_client_response_put ;

  // submodule f_dmem_imem_reqs
  FIFO2 #(.width(32'd129), .guarded(1'd1)) f_dmem_imem_reqs(.RST(RST_N),
							    .CLK(CLK),
							    .D_IN(f_dmem_imem_reqs$D_IN),
							    .ENQ(f_dmem_imem_reqs$ENQ),
							    .DEQ(f_dmem_imem_reqs$DEQ),
							    .CLR(f_dmem_imem_reqs$CLR),
							    .D_OUT(f_dmem_imem_reqs$D_OUT),
							    .FULL_N(f_dmem_imem_reqs$FULL_N),
							    .EMPTY_N(f_dmem_imem_reqs$EMPTY_N));

  // submodule f_dmem_reqs
  FIFO2 #(.width(32'd128), .guarded(1'd1)) f_dmem_reqs(.RST(RST_N),
						       .CLK(CLK),
						       .D_IN(f_dmem_reqs$D_IN),
						       .ENQ(f_dmem_reqs$ENQ),
						       .DEQ(f_dmem_reqs$DEQ),
						       .CLR(f_dmem_reqs$CLR),
						       .D_OUT(f_dmem_reqs$D_OUT),
						       .FULL_N(f_dmem_reqs$FULL_N),
						       .EMPTY_N(f_dmem_reqs$EMPTY_N));

  // submodule f_dmem_rsps
  FIFO2 #(.width(32'd132), .guarded(1'd1)) f_dmem_rsps(.RST(RST_N),
						       .CLK(CLK),
						       .D_IN(f_dmem_rsps$D_IN),
						       .ENQ(f_dmem_rsps$ENQ),
						       .DEQ(f_dmem_rsps$DEQ),
						       .CLR(f_dmem_rsps$CLR),
						       .D_OUT(f_dmem_rsps$D_OUT),
						       .FULL_N(f_dmem_rsps$FULL_N),
						       .EMPTY_N(f_dmem_rsps$EMPTY_N));

  // submodule f_imem_reqs
  FIFO2 #(.width(32'd128), .guarded(1'd1)) f_imem_reqs(.RST(RST_N),
						       .CLK(CLK),
						       .D_IN(f_imem_reqs$D_IN),
						       .ENQ(f_imem_reqs$ENQ),
						       .DEQ(f_imem_reqs$DEQ),
						       .CLR(f_imem_reqs$CLR),
						       .D_OUT(f_imem_reqs$D_OUT),
						       .FULL_N(f_imem_reqs$FULL_N),
						       .EMPTY_N(f_imem_reqs$EMPTY_N));

  // submodule f_imem_rsps
  FIFO2 #(.width(32'd132), .guarded(1'd1)) f_imem_rsps(.RST(RST_N),
						       .CLK(CLK),
						       .D_IN(f_imem_rsps$D_IN),
						       .ENQ(f_imem_rsps$ENQ),
						       .DEQ(f_imem_rsps$DEQ),
						       .CLR(f_imem_rsps$CLR),
						       .D_OUT(f_imem_rsps$D_OUT),
						       .FULL_N(f_imem_rsps$FULL_N),
						       .EMPTY_N(f_imem_rsps$EMPTY_N));

  // submodule f_mem_reqs
  FIFO2 #(.width(32'd64), .guarded(1'd1)) f_mem_reqs(.RST(RST_N),
						     .CLK(CLK),
						     .D_IN(f_mem_reqs$D_IN),
						     .ENQ(f_mem_reqs$ENQ),
						     .DEQ(f_mem_reqs$DEQ),
						     .CLR(f_mem_reqs$CLR),
						     .D_OUT(f_mem_reqs$D_OUT),
						     .FULL_N(f_mem_reqs$FULL_N),
						     .EMPTY_N(f_mem_reqs$EMPTY_N));

  // submodule f_mem_rsps
  FIFO2 #(.width(32'd65), .guarded(1'd1)) f_mem_rsps(.RST(RST_N),
						     .CLK(CLK),
						     .D_IN(f_mem_rsps$D_IN),
						     .ENQ(f_mem_rsps$ENQ),
						     .DEQ(f_mem_rsps$DEQ),
						     .CLR(f_mem_rsps$CLR),
						     .D_OUT(f_mem_rsps$D_OUT),
						     .FULL_N(f_mem_rsps$FULL_N),
						     .EMPTY_N(f_mem_rsps$EMPTY_N));

  // rule RL_rl_merge_dmem_reqs
  assign CAN_FIRE_RL_rl_merge_dmem_reqs =
	     f_dmem_reqs$EMPTY_N && f_dmem_imem_reqs$FULL_N ;
  assign WILL_FIRE_RL_rl_merge_dmem_reqs =
	     CAN_FIRE_RL_rl_merge_dmem_reqs &&
	     !WILL_FIRE_RL_rl_merge_imem_reqs ;

  // rule RL_rl_merge_imem_reqs
  assign CAN_FIRE_RL_rl_merge_imem_reqs =
	     f_dmem_imem_reqs$FULL_N && f_imem_reqs$EMPTY_N ;
  assign WILL_FIRE_RL_rl_merge_imem_reqs = CAN_FIRE_RL_rl_merge_imem_reqs ;

  // rule RL_rl_ptw_start
  assign CAN_FIRE_RL_rl_ptw_start =
	     f_dmem_imem_reqs$EMPTY_N && f_mem_reqs$FULL_N &&
	     rg_state == 2'd0 ;
  assign WILL_FIRE_RL_rl_ptw_start = CAN_FIRE_RL_rl_ptw_start ;

  // rule RL_rl_ptw_level_2
  assign CAN_FIRE_RL_rl_ptw_level_2 = MUX_rg_state$write_1__SEL_1 ;
  assign WILL_FIRE_RL_rl_ptw_level_2 = MUX_rg_state$write_1__SEL_1 ;

  // rule RL_rl_ptw_level_1
  assign CAN_FIRE_RL_rl_ptw_level_1 = MUX_rg_state$write_1__SEL_2 ;
  assign WILL_FIRE_RL_rl_ptw_level_1 = MUX_rg_state$write_1__SEL_2 ;

  // rule RL_rl_ptw_level_0
  assign CAN_FIRE_RL_rl_ptw_level_0 = MUX_rg_state$write_1__SEL_3 ;
  assign WILL_FIRE_RL_rl_ptw_level_0 = MUX_rg_state$write_1__SEL_3 ;

  // inputs to muxes for submodule ports
  assign MUX_f_dmem_rsps$enq_1__SEL_1 =
	     WILL_FIRE_RL_rl_ptw_level_2 &&
	     (f_mem_rsps$D_OUT[64] &&
	      ((!f_mem_rsps$D_OUT[0] ||
		!f_mem_rsps$D_OUT[1] && f_mem_rsps$D_OUT[2]) &&
	       f_dmem_imem_reqs$D_OUT[128] ||
	       f_mem_rsps$D_OUT[0] &&
	       (f_mem_rsps$D_OUT[1] || !f_mem_rsps$D_OUT[2]) &&
	       (f_mem_rsps$D_OUT[3] || f_mem_rsps$D_OUT[1]) &&
	       f_dmem_imem_reqs$D_OUT[128]) ||
	      !f_mem_rsps$D_OUT[64] && f_dmem_imem_reqs$D_OUT[128]) ;
  assign MUX_f_dmem_rsps$enq_1__SEL_2 =
	     WILL_FIRE_RL_rl_ptw_level_1 &&
	     (f_mem_rsps$D_OUT[64] &&
	      ((!f_mem_rsps$D_OUT[0] ||
		!f_mem_rsps$D_OUT[1] && f_mem_rsps$D_OUT[2]) &&
	       f_dmem_imem_reqs$D_OUT[128] ||
	       f_mem_rsps$D_OUT[0] &&
	       (f_mem_rsps$D_OUT[1] || !f_mem_rsps$D_OUT[2]) &&
	       (f_mem_rsps$D_OUT[3] || f_mem_rsps$D_OUT[1]) &&
	       f_dmem_imem_reqs$D_OUT[128]) ||
	      !f_mem_rsps$D_OUT[64] && f_dmem_imem_reqs$D_OUT[128]) ;
  assign MUX_f_dmem_rsps$enq_1__SEL_3 =
	     WILL_FIRE_RL_rl_ptw_level_0 && f_dmem_imem_reqs$D_OUT[128] ;
  assign MUX_f_imem_rsps$enq_1__SEL_1 =
	     WILL_FIRE_RL_rl_ptw_level_2 &&
	     (f_mem_rsps$D_OUT[64] &&
	      ((!f_mem_rsps$D_OUT[0] ||
		!f_mem_rsps$D_OUT[1] && f_mem_rsps$D_OUT[2]) &&
	       !f_dmem_imem_reqs$D_OUT[128] ||
	       f_mem_rsps$D_OUT[0] &&
	       (f_mem_rsps$D_OUT[1] || !f_mem_rsps$D_OUT[2]) &&
	       (f_mem_rsps$D_OUT[3] || f_mem_rsps$D_OUT[1]) &&
	       !f_dmem_imem_reqs$D_OUT[128]) ||
	      !f_mem_rsps$D_OUT[64] && !f_dmem_imem_reqs$D_OUT[128]) ;
  assign MUX_f_imem_rsps$enq_1__SEL_2 =
	     WILL_FIRE_RL_rl_ptw_level_1 &&
	     (f_mem_rsps$D_OUT[64] &&
	      ((!f_mem_rsps$D_OUT[0] ||
		!f_mem_rsps$D_OUT[1] && f_mem_rsps$D_OUT[2]) &&
	       !f_dmem_imem_reqs$D_OUT[128] ||
	       f_mem_rsps$D_OUT[0] &&
	       (f_mem_rsps$D_OUT[1] || !f_mem_rsps$D_OUT[2]) &&
	       (f_mem_rsps$D_OUT[3] || f_mem_rsps$D_OUT[1]) &&
	       !f_dmem_imem_reqs$D_OUT[128]) ||
	      !f_mem_rsps$D_OUT[64] && !f_dmem_imem_reqs$D_OUT[128]) ;
  assign MUX_f_imem_rsps$enq_1__SEL_3 =
	     WILL_FIRE_RL_rl_ptw_level_0 && !f_dmem_imem_reqs$D_OUT[128] ;
  assign MUX_f_mem_reqs$enq_1__SEL_1 =
	     WILL_FIRE_RL_rl_ptw_level_2 && f_mem_rsps$D_OUT[64] &&
	     f_mem_rsps$D_OUT[0] &&
	     !f_mem_rsps$D_OUT[2] &&
	     !f_mem_rsps$D_OUT[3] &&
	     !f_mem_rsps$D_OUT[1] ;
  assign MUX_f_mem_reqs$enq_1__SEL_2 =
	     WILL_FIRE_RL_rl_ptw_level_1 && f_mem_rsps$D_OUT[64] &&
	     f_mem_rsps$D_OUT[0] &&
	     !f_mem_rsps$D_OUT[2] &&
	     !f_mem_rsps$D_OUT[3] &&
	     !f_mem_rsps$D_OUT[1] ;
  assign MUX_rg_state$write_1__SEL_1 =
	     f_dmem_imem_reqs$EMPTY_N &&
	     f_mem_rsps_i_notEmpty__0_AND_IF_f_mem_rsps_fir_ETC___d60 &&
	     rg_state == 2'd1 ;
  assign MUX_rg_state$write_1__SEL_2 =
	     f_dmem_imem_reqs$EMPTY_N &&
	     f_mem_rsps_i_notEmpty__0_AND_IF_f_mem_rsps_fir_ETC___d60 &&
	     rg_state == 2'd2 ;
  assign MUX_rg_state$write_1__SEL_3 =
	     f_dmem_imem_reqs$EMPTY_N && f_mem_rsps$EMPTY_N &&
	     IF_f_dmem_imem_reqs_i_notEmpty__0_AND_f_dmem_i_ETC___d53 &&
	     rg_state == 2'd3 ;
  assign MUX_f_dmem_imem_reqs$enq_1__VAL_1 = { 1'd1, f_dmem_reqs$D_OUT } ;
  assign MUX_f_dmem_imem_reqs$enq_1__VAL_2 = { 1'd0, f_imem_reqs$D_OUT } ;
  assign MUX_f_dmem_rsps$enq_1__VAL_1 =
	     { f_mem_rsps$D_OUT[64] ?
		 ((!f_mem_rsps$D_OUT[0] ||
		   !f_mem_rsps$D_OUT[1] && f_mem_rsps$D_OUT[2] ||
		   f_mem_rsps$D_OUT[27:19] != 9'd0 ||
		   f_mem_rsps$D_OUT[18:10] != 9'd0) ?
		    2'd2 :
		    2'd0) :
		 2'd1,
	       f_mem_rsps$D_OUT[63:0],
	       2'd2,
	       rg_pte_pa } ;
  assign MUX_f_dmem_rsps$enq_1__VAL_2 =
	     { f_mem_rsps$D_OUT[64] ?
		 ((!f_mem_rsps$D_OUT[0] ||
		   !f_mem_rsps$D_OUT[1] && f_mem_rsps$D_OUT[2]) ?
		    2'd2 :
		    ((f_mem_rsps$D_OUT[18:10] == 9'd0) ? 2'd0 : 2'd2)) :
		 2'd1,
	       f_mem_rsps$D_OUT[63:0],
	       2'd1,
	       rg_pte_pa } ;
  assign MUX_f_dmem_rsps$enq_1__VAL_3 =
	     { f_mem_rsps$D_OUT[64] ?
		 ((!f_mem_rsps$D_OUT[0] ||
		   !f_mem_rsps$D_OUT[1] && f_mem_rsps$D_OUT[2] ||
		   !f_mem_rsps$D_OUT[3] && !f_mem_rsps$D_OUT[1]) ?
		    2'd2 :
		    2'd0) :
		 2'd1,
	       f_mem_rsps$D_OUT[63:0],
	       2'd0,
	       rg_pte_pa } ;
  assign MUX_rg_state$write_1__VAL_1 =
	     f_mem_rsps$D_OUT[64] ?
	       ((!f_mem_rsps$D_OUT[0] ||
		 !f_mem_rsps$D_OUT[1] && f_mem_rsps$D_OUT[2]) ?
		  2'd0 :
		  ((!f_mem_rsps$D_OUT[3] && !f_mem_rsps$D_OUT[1]) ?
		     2'd2 :
		     2'd0)) :
	       2'd0 ;
  assign MUX_rg_state$write_1__VAL_2 =
	     f_mem_rsps$D_OUT[64] ?
	       ((!f_mem_rsps$D_OUT[0] ||
		 !f_mem_rsps$D_OUT[1] && f_mem_rsps$D_OUT[2]) ?
		  2'd0 :
		  ((!f_mem_rsps$D_OUT[3] && !f_mem_rsps$D_OUT[1]) ?
		     2'd3 :
		     2'd0)) :
	       2'd0 ;

  // register rg_pte_pa
  always@(MUX_f_mem_reqs$enq_1__SEL_1 or
	  lev_1_pte_pa__h1815 or
	  MUX_f_mem_reqs$enq_1__SEL_2 or
	  lev_0_pte_pa__h2832 or
	  WILL_FIRE_RL_rl_ptw_start or lev_2_pte_pa__h1343)
  begin
    case (1'b1) // synopsys parallel_case
      MUX_f_mem_reqs$enq_1__SEL_1: rg_pte_pa$D_IN = lev_1_pte_pa__h1815;
      MUX_f_mem_reqs$enq_1__SEL_2: rg_pte_pa$D_IN = lev_0_pte_pa__h2832;
      WILL_FIRE_RL_rl_ptw_start: rg_pte_pa$D_IN = lev_2_pte_pa__h1343;
      default: rg_pte_pa$D_IN = 64'hAAAAAAAAAAAAAAAA /* unspecified value */ ;
    endcase
  end
  assign rg_pte_pa$EN =
	     WILL_FIRE_RL_rl_ptw_level_2 && f_mem_rsps$D_OUT[64] &&
	     f_mem_rsps$D_OUT[0] &&
	     !f_mem_rsps$D_OUT[2] &&
	     !f_mem_rsps$D_OUT[3] &&
	     !f_mem_rsps$D_OUT[1] ||
	     WILL_FIRE_RL_rl_ptw_level_1 && f_mem_rsps$D_OUT[64] &&
	     f_mem_rsps$D_OUT[0] &&
	     !f_mem_rsps$D_OUT[2] &&
	     !f_mem_rsps$D_OUT[3] &&
	     !f_mem_rsps$D_OUT[1] ||
	     WILL_FIRE_RL_rl_ptw_start ;

  // register rg_state
  always@(WILL_FIRE_RL_rl_ptw_level_2 or
	  MUX_rg_state$write_1__VAL_1 or
	  WILL_FIRE_RL_rl_ptw_level_1 or
	  MUX_rg_state$write_1__VAL_2 or
	  WILL_FIRE_RL_rl_ptw_level_0 or WILL_FIRE_RL_rl_ptw_start)
  begin
    case (1'b1) // synopsys parallel_case
      WILL_FIRE_RL_rl_ptw_level_2:
	  rg_state$D_IN = MUX_rg_state$write_1__VAL_1;
      WILL_FIRE_RL_rl_ptw_level_1:
	  rg_state$D_IN = MUX_rg_state$write_1__VAL_2;
      WILL_FIRE_RL_rl_ptw_level_0: rg_state$D_IN = 2'd0;
      WILL_FIRE_RL_rl_ptw_start: rg_state$D_IN = 2'd1;
      default: rg_state$D_IN = 2'b10 /* unspecified value */ ;
    endcase
  end
  assign rg_state$EN =
	     WILL_FIRE_RL_rl_ptw_level_2 || WILL_FIRE_RL_rl_ptw_level_1 ||
	     WILL_FIRE_RL_rl_ptw_level_0 ||
	     WILL_FIRE_RL_rl_ptw_start ;

  // submodule f_dmem_imem_reqs
  assign f_dmem_imem_reqs$D_IN =
	     WILL_FIRE_RL_rl_merge_dmem_reqs ?
	       MUX_f_dmem_imem_reqs$enq_1__VAL_1 :
	       MUX_f_dmem_imem_reqs$enq_1__VAL_2 ;
  assign f_dmem_imem_reqs$ENQ =
	     WILL_FIRE_RL_rl_merge_dmem_reqs ||
	     WILL_FIRE_RL_rl_merge_imem_reqs ;
  assign f_dmem_imem_reqs$DEQ =
	     (WILL_FIRE_RL_rl_ptw_level_1 || WILL_FIRE_RL_rl_ptw_level_2) &&
	     (!f_mem_rsps$D_OUT[0] || f_mem_rsps$D_OUT[2] ||
	      f_mem_rsps$D_OUT[3] ||
	      f_mem_rsps$D_OUT[1] ||
	      !f_mem_rsps$D_OUT[64]) ||
	     WILL_FIRE_RL_rl_ptw_level_0 ;
  assign f_dmem_imem_reqs$CLR = 1'b0 ;

  // submodule f_dmem_reqs
  assign f_dmem_reqs$D_IN = dmem_server_request_put ;
  assign f_dmem_reqs$ENQ = EN_dmem_server_request_put ;
  assign f_dmem_reqs$DEQ = WILL_FIRE_RL_rl_merge_dmem_reqs ;
  assign f_dmem_reqs$CLR = 1'b0 ;

  // submodule f_dmem_rsps
  always@(MUX_f_dmem_rsps$enq_1__SEL_1 or
	  MUX_f_dmem_rsps$enq_1__VAL_1 or
	  MUX_f_dmem_rsps$enq_1__SEL_2 or
	  MUX_f_dmem_rsps$enq_1__VAL_2 or
	  MUX_f_dmem_rsps$enq_1__SEL_3 or MUX_f_dmem_rsps$enq_1__VAL_3)
  begin
    case (1'b1) // synopsys parallel_case
      MUX_f_dmem_rsps$enq_1__SEL_1:
	  f_dmem_rsps$D_IN = MUX_f_dmem_rsps$enq_1__VAL_1;
      MUX_f_dmem_rsps$enq_1__SEL_2:
	  f_dmem_rsps$D_IN = MUX_f_dmem_rsps$enq_1__VAL_2;
      MUX_f_dmem_rsps$enq_1__SEL_3:
	  f_dmem_rsps$D_IN = MUX_f_dmem_rsps$enq_1__VAL_3;
      default: f_dmem_rsps$D_IN =
		   132'hAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA /* unspecified value */ ;
    endcase
  end
  assign f_dmem_rsps$ENQ =
	     MUX_f_dmem_rsps$enq_1__SEL_1 || MUX_f_dmem_rsps$enq_1__SEL_2 ||
	     WILL_FIRE_RL_rl_ptw_level_0 && f_dmem_imem_reqs$D_OUT[128] ;
  assign f_dmem_rsps$DEQ = EN_dmem_server_response_get ;
  assign f_dmem_rsps$CLR = 1'b0 ;

  // submodule f_imem_reqs
  assign f_imem_reqs$D_IN = imem_server_request_put ;
  assign f_imem_reqs$ENQ = EN_imem_server_request_put ;
  assign f_imem_reqs$DEQ = CAN_FIRE_RL_rl_merge_imem_reqs ;
  assign f_imem_reqs$CLR = 1'b0 ;

  // submodule f_imem_rsps
  always@(MUX_f_imem_rsps$enq_1__SEL_1 or
	  MUX_f_dmem_rsps$enq_1__VAL_1 or
	  MUX_f_imem_rsps$enq_1__SEL_2 or
	  MUX_f_dmem_rsps$enq_1__VAL_2 or
	  MUX_f_imem_rsps$enq_1__SEL_3 or MUX_f_dmem_rsps$enq_1__VAL_3)
  begin
    case (1'b1) // synopsys parallel_case
      MUX_f_imem_rsps$enq_1__SEL_1:
	  f_imem_rsps$D_IN = MUX_f_dmem_rsps$enq_1__VAL_1;
      MUX_f_imem_rsps$enq_1__SEL_2:
	  f_imem_rsps$D_IN = MUX_f_dmem_rsps$enq_1__VAL_2;
      MUX_f_imem_rsps$enq_1__SEL_3:
	  f_imem_rsps$D_IN = MUX_f_dmem_rsps$enq_1__VAL_3;
      default: f_imem_rsps$D_IN =
		   132'hAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA /* unspecified value */ ;
    endcase
  end
  assign f_imem_rsps$ENQ =
	     MUX_f_imem_rsps$enq_1__SEL_1 || MUX_f_imem_rsps$enq_1__SEL_2 ||
	     WILL_FIRE_RL_rl_ptw_level_0 && !f_dmem_imem_reqs$D_OUT[128] ;
  assign f_imem_rsps$DEQ = EN_imem_server_response_get ;
  assign f_imem_rsps$CLR = 1'b0 ;

  // submodule f_mem_reqs
  always@(MUX_f_mem_reqs$enq_1__SEL_1 or
	  lev_1_pte_pa__h1815 or
	  MUX_f_mem_reqs$enq_1__SEL_2 or
	  lev_0_pte_pa__h2832 or
	  WILL_FIRE_RL_rl_ptw_start or lev_2_pte_pa__h1343)
  begin
    case (1'b1) // synopsys parallel_case
      MUX_f_mem_reqs$enq_1__SEL_1: f_mem_reqs$D_IN = lev_1_pte_pa__h1815;
      MUX_f_mem_reqs$enq_1__SEL_2: f_mem_reqs$D_IN = lev_0_pte_pa__h2832;
      WILL_FIRE_RL_rl_ptw_start: f_mem_reqs$D_IN = lev_2_pte_pa__h1343;
      default: f_mem_reqs$D_IN =
		   64'hAAAAAAAAAAAAAAAA /* unspecified value */ ;
    endcase
  end
  assign f_mem_reqs$ENQ =
	     WILL_FIRE_RL_rl_ptw_level_2 && f_mem_rsps$D_OUT[64] &&
	     f_mem_rsps$D_OUT[0] &&
	     !f_mem_rsps$D_OUT[2] &&
	     !f_mem_rsps$D_OUT[3] &&
	     !f_mem_rsps$D_OUT[1] ||
	     WILL_FIRE_RL_rl_ptw_level_1 && f_mem_rsps$D_OUT[64] &&
	     f_mem_rsps$D_OUT[0] &&
	     !f_mem_rsps$D_OUT[2] &&
	     !f_mem_rsps$D_OUT[3] &&
	     !f_mem_rsps$D_OUT[1] ||
	     WILL_FIRE_RL_rl_ptw_start ;
  assign f_mem_reqs$DEQ = EN_mem_client_request_get ;
  assign f_mem_reqs$CLR = 1'b0 ;

  // submodule f_mem_rsps
  assign f_mem_rsps$D_IN = mem_client_response_put ;
  assign f_mem_rsps$ENQ = EN_mem_client_response_put ;
  assign f_mem_rsps$DEQ =
	     WILL_FIRE_RL_rl_ptw_level_0 || WILL_FIRE_RL_rl_ptw_level_1 ||
	     WILL_FIRE_RL_rl_ptw_level_2 ;
  assign f_mem_rsps$CLR = 1'b0 ;

  // remaining internal signals
  assign IF_NOT_f_mem_rsps_first__1_BIT_0_3_4_OR_NOT_f__ETC___d58 =
	     (!f_mem_rsps$D_OUT[0] ||
	      !f_mem_rsps$D_OUT[1] && f_mem_rsps$D_OUT[2]) ?
	       IF_f_dmem_imem_reqs_i_notEmpty__0_AND_f_dmem_i_ETC___d53 :
	       ((!f_mem_rsps$D_OUT[3] && !f_mem_rsps$D_OUT[1]) ?
		  f_mem_reqs$FULL_N :
		  IF_f_dmem_imem_reqs_i_notEmpty__0_AND_f_dmem_i_ETC___d53) ;
  assign IF_f_dmem_imem_reqs_i_notEmpty__0_AND_f_dmem_i_ETC___d53 =
	     (f_dmem_imem_reqs$EMPTY_N && f_dmem_imem_reqs$D_OUT[128]) ?
	       f_dmem_rsps$FULL_N :
	       f_imem_rsps$FULL_N ;
  assign f_mem_rsps_i_notEmpty__0_AND_IF_f_mem_rsps_fir_ETC___d60 =
	     f_mem_rsps$EMPTY_N &&
	     (f_mem_rsps$D_OUT[64] ?
		IF_NOT_f_mem_rsps_first__1_BIT_0_3_4_OR_NOT_f__ETC___d58 :
		IF_f_dmem_imem_reqs_i_notEmpty__0_AND_f_dmem_i_ETC___d53) ;
  assign lev_0_pte_pa__h2832 = lev_1_PTN_pa__h1813 + vpn_0_pa__h2831 ;
  assign lev_1_PTN_pa__h1813 = { 8'd0, x__h2032 } ;
  assign lev_1_pte_pa__h1815 = lev_1_PTN_pa__h1813 + vpn_1_pa__h1814 ;
  assign lev_2_pte_pa__h1343 = satp_pa__h1023 + vpn_2_pa__h1342 ;
  assign satp_pa__h1023 = { 8'd0, x__h1284 } ;
  assign vpn_0_pa__h2831 = { 52'd0, f_dmem_imem_reqs$D_OUT[84:76], 3'd0 } ;
  assign vpn_1_pa__h1814 = { 52'd0, f_dmem_imem_reqs$D_OUT[93:85], 3'd0 } ;
  assign vpn_2_pa__h1342 = { 52'd0, f_dmem_imem_reqs$D_OUT[102:94], 3'd0 } ;
  assign x__h1284 = { f_dmem_imem_reqs$D_OUT[43:0], 12'b0 } ;
  assign x__h2032 = { f_mem_rsps$D_OUT[53:10], 12'b0 } ;

  // handling of inlined registers

  always@(posedge CLK)
  begin
    if (RST_N == `BSV_RESET_VALUE)
      begin
        rg_state <= `BSV_ASSIGNMENT_DELAY 2'd0;
      end
    else
      begin
        if (rg_state$EN) rg_state <= `BSV_ASSIGNMENT_DELAY rg_state$D_IN;
      end
    if (rg_pte_pa$EN) rg_pte_pa <= `BSV_ASSIGNMENT_DELAY rg_pte_pa$D_IN;
  end

  // synopsys translate_off
  `ifdef BSV_NO_INITIAL_BLOCKS
  `else // not BSV_NO_INITIAL_BLOCKS
  initial
  begin
    rg_pte_pa = 64'hAAAAAAAAAAAAAAAA;
    rg_state = 2'h2;
  end
  `endif // BSV_NO_INITIAL_BLOCKS
  // synopsys translate_on

  // handling of system tasks

  // synopsys translate_off
  always@(negedge CLK)
  begin
    #0;
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_merge_dmem_reqs && verbosity != 3'd0)
	begin
	  v__h856 = $stime;
	  #0;
	end
    v__h850 = v__h856 / 32'd10;
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_merge_dmem_reqs && verbosity != 3'd0)
	$write("%0d: %m.rl_merge_dmem_reqs:\n    ", v__h850);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_merge_dmem_reqs && verbosity != 3'd0)
	$write("PTW_Req { ", "va: ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_merge_dmem_reqs && verbosity != 3'd0)
	$write("'h%h", f_dmem_reqs$D_OUT[127:64]);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_merge_dmem_reqs && verbosity != 3'd0)
	$write(", ", "satp: ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_merge_dmem_reqs && verbosity != 3'd0)
	$write("'h%h", f_dmem_reqs$D_OUT[63:0], " }");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_merge_dmem_reqs && verbosity != 3'd0) $write("\n");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_merge_imem_reqs && verbosity != 3'd0)
	begin
	  v__h977 = $stime;
	  #0;
	end
    v__h971 = v__h977 / 32'd10;
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_merge_imem_reqs && verbosity != 3'd0)
	$write("%0d: %m.rl_merge_imem_reqs:\n    ", v__h971);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_merge_imem_reqs && verbosity != 3'd0)
	$write("PTW_Req { ", "va: ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_merge_imem_reqs && verbosity != 3'd0)
	$write("'h%h", f_imem_reqs$D_OUT[127:64]);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_merge_imem_reqs && verbosity != 3'd0)
	$write(", ", "satp: ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_merge_imem_reqs && verbosity != 3'd0)
	$write("'h%h", f_imem_reqs$D_OUT[63:0], " }");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_merge_imem_reqs && verbosity != 3'd0) $write("\n");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_ptw_start && verbosity != 3'd0)
	begin
	  v__h1123 = $stime;
	  #0;
	end
    v__h1117 = v__h1123 / 32'd10;
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_ptw_start && verbosity != 3'd0)
	$display("%0d: %m.rl_ptw_start:", v__h1117);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_ptw_start && verbosity != 3'd0 &&
	  f_dmem_imem_reqs$D_OUT[128])
	$write("    for D_Mem:");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_ptw_start && verbosity != 3'd0 &&
	  !f_dmem_imem_reqs$D_OUT[128])
	$write("    for I_Mem:");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_ptw_start && verbosity != 3'd0)
	$display(" satp_pa %0h  va %0h",
		 satp_pa__h1023,
		 f_dmem_imem_reqs$D_OUT[102:64]);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_ptw_start && verbosity != 3'd0)
	$display("    Sv39/Sv48: mem_req level 2 PTE for PA %0h",
		 lev_2_pte_pa__h1343);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_ptw_level_2 && verbosity != 3'd0)
	begin
	  v__h1530 = $stime;
	  #0;
	end
    v__h1524 = v__h1530 / 32'd10;
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_ptw_level_2 && verbosity != 3'd0)
	$display("%0d: %m.rl_ptw_level_2:", v__h1524);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_ptw_level_2 && verbosity != 3'd0)
	$display("    satp_pa %0h  va %0h  pte_pa %0h",
		 satp_pa__h1023,
		 f_dmem_imem_reqs$D_OUT[102:64],
		 rg_pte_pa);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_ptw_level_2 && f_mem_rsps$D_OUT[64] &&
	  (!f_mem_rsps$D_OUT[0] ||
	   !f_mem_rsps$D_OUT[1] && f_mem_rsps$D_OUT[2]) &&
	  verbosity != 3'd0)
	$display("    pte %0h: PAGE FAULT: invalid PTE",
		 f_mem_rsps$D_OUT[63:0]);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_ptw_level_2 && f_mem_rsps$D_OUT[64] &&
	  f_mem_rsps$D_OUT[0] &&
	  !f_mem_rsps$D_OUT[2] &&
	  !f_mem_rsps$D_OUT[3] &&
	  !f_mem_rsps$D_OUT[1] &&
	  verbosity != 3'd0)
	$display("    pte %0h: continue to level 1: req addr %0h",
		 f_mem_rsps$D_OUT[63:0],
		 lev_1_pte_pa__h1815);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_ptw_level_2 && f_mem_rsps$D_OUT[64] &&
	  f_mem_rsps$D_OUT[0] &&
	  (f_mem_rsps$D_OUT[1] || !f_mem_rsps$D_OUT[2]) &&
	  (f_mem_rsps$D_OUT[3] || f_mem_rsps$D_OUT[1]) &&
	  (f_mem_rsps$D_OUT[27:19] != 9'd0 ||
	   f_mem_rsps$D_OUT[18:10] != 9'd0) &&
	  verbosity != 3'd0)
	$display("    pte %0h (leaf->gigapage): PAGE FAULT: PPN[1]/PPN[0] not 0",
		 f_mem_rsps$D_OUT[63:0]);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_ptw_level_2 && f_mem_rsps$D_OUT[64] &&
	  f_mem_rsps$D_OUT[0] &&
	  (f_mem_rsps$D_OUT[1] || !f_mem_rsps$D_OUT[2]) &&
	  (f_mem_rsps$D_OUT[3] || f_mem_rsps$D_OUT[1]) &&
	  f_mem_rsps$D_OUT[27:19] == 9'd0 &&
	  f_mem_rsps$D_OUT[18:10] == 9'd0 &&
	  verbosity != 3'd0)
	$display("    pte %0h (leaf->gigapage). pa %0h",
		 f_mem_rsps$D_OUT[63:0],
		 lev_1_PTN_pa__h1813);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_ptw_level_2 && !f_mem_rsps$D_OUT[64] &&
	  verbosity != 3'd0)
	$display("    ACCESS FAULT: fabric response error");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_ptw_level_1 && verbosity != 3'd0)
	begin
	  v__h2566 = $stime;
	  #0;
	end
    v__h2560 = v__h2566 / 32'd10;
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_ptw_level_1 && verbosity != 3'd0)
	$display("%0d: %m.rl_ptw_level_1:", v__h2560);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_ptw_level_1 && verbosity != 3'd0)
	$display("    satp_pa %0h  va %0h  pte_pa %0h",
		 satp_pa__h1023,
		 f_dmem_imem_reqs$D_OUT[102:64],
		 rg_pte_pa);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_ptw_level_1 && f_mem_rsps$D_OUT[64] &&
	  (!f_mem_rsps$D_OUT[0] ||
	   !f_mem_rsps$D_OUT[1] && f_mem_rsps$D_OUT[2]) &&
	  verbosity != 3'd0)
	$display("    pte %0h: PAGE FAULT: invalid PTE",
		 f_mem_rsps$D_OUT[63:0]);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_ptw_level_1 && f_mem_rsps$D_OUT[64] &&
	  f_mem_rsps$D_OUT[0] &&
	  !f_mem_rsps$D_OUT[2] &&
	  !f_mem_rsps$D_OUT[3] &&
	  !f_mem_rsps$D_OUT[1] &&
	  verbosity != 3'd0)
	$display("    pte %0h: continue to level 0: req addr %0h",
		 f_mem_rsps$D_OUT[63:0],
		 lev_0_pte_pa__h2832);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_ptw_level_1 && f_mem_rsps$D_OUT[64] &&
	  f_mem_rsps$D_OUT[0] &&
	  (f_mem_rsps$D_OUT[1] || !f_mem_rsps$D_OUT[2]) &&
	  (f_mem_rsps$D_OUT[3] || f_mem_rsps$D_OUT[1]) &&
	  f_mem_rsps$D_OUT[18:10] == 9'd0 &&
	  verbosity != 3'd0)
	$display("    pte %0h (leaf->megapage); pa %0h",
		 f_mem_rsps$D_OUT[63:0],
		 lev_1_PTN_pa__h1813);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_ptw_level_1 && f_mem_rsps$D_OUT[64] &&
	  f_mem_rsps$D_OUT[0] &&
	  (f_mem_rsps$D_OUT[1] || !f_mem_rsps$D_OUT[2]) &&
	  (f_mem_rsps$D_OUT[3] || f_mem_rsps$D_OUT[1]) &&
	  f_mem_rsps$D_OUT[18:10] != 9'd0 &&
	  verbosity != 3'd0)
	$display("    pte %0h (leaf->megapage): PAGE FAULT: PPN [0] is not zero",
		 f_mem_rsps$D_OUT[63:0]);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_ptw_level_1 && !f_mem_rsps$D_OUT[64] &&
	  verbosity != 3'd0)
	$display("    ACCESS FAULT: fabric response error");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_ptw_level_0 && verbosity != 3'd0)
	begin
	  v__h3536 = $stime;
	  #0;
	end
    v__h3530 = v__h3536 / 32'd10;
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_ptw_level_0 && verbosity != 3'd0)
	$display("%0d: %m.rl_ptw_level_0:", v__h3530);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_ptw_level_0 && verbosity != 3'd0)
	$display("    satp_pa %0h  va %0h  pte_pa %0h",
		 satp_pa__h1023,
		 f_dmem_imem_reqs$D_OUT[102:64],
		 rg_pte_pa);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_ptw_level_0 && f_mem_rsps$D_OUT[64] &&
	  (!f_mem_rsps$D_OUT[0] ||
	   !f_mem_rsps$D_OUT[1] && f_mem_rsps$D_OUT[2]) &&
	  verbosity != 3'd0)
	$display("    pte %0h: PAGE FAULT: invalid PTE",
		 f_mem_rsps$D_OUT[63:0]);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_ptw_level_0 && f_mem_rsps$D_OUT[64] &&
	  f_mem_rsps$D_OUT[0] &&
	  !f_mem_rsps$D_OUT[2] &&
	  !f_mem_rsps$D_OUT[3] &&
	  !f_mem_rsps$D_OUT[1] &&
	  verbosity != 3'd0)
	$display("    pte %0h: PAGE FAULT: not a leaf PTE",
		 f_mem_rsps$D_OUT[63:0]);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_ptw_level_0 && f_mem_rsps$D_OUT[64] &&
	  f_mem_rsps$D_OUT[0] &&
	  (f_mem_rsps$D_OUT[1] || !f_mem_rsps$D_OUT[2]) &&
	  (f_mem_rsps$D_OUT[3] || f_mem_rsps$D_OUT[1]) &&
	  verbosity != 3'd0)
	$display("    pte %0h: leaf PTE; pa %0h",
		 f_mem_rsps$D_OUT[63:0],
		 lev_1_PTN_pa__h1813);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_ptw_level_0 && !f_mem_rsps$D_OUT[64] &&
	  verbosity != 3'd0)
	$display("    ACCESS FAULT: fabric response error");
  end
  // synopsys translate_on
endmodule  // mkPTW

