//
// Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24)
//
//
//
//
// Ports:
// Name                         I/O  size props
// RDY_server_reset_request_put   O     1
// RDY_server_reset_response_get  O     1 reg
// imem_valid                     O     1
// imem_is_i32_not_i16            O     1 const
// imem_pc                        O    64
// imem_instr                     O    32
// imem_exc                       O     1
// imem_exc_code                  O     4
// imem_tval                      O    64
// imem_master_awvalid            O     1 reg
// imem_master_awid               O    16 reg
// imem_master_awaddr             O    64 reg
// imem_master_awlen              O     8 reg
// imem_master_awsize             O     3 reg
// imem_master_awburst            O     2 reg
// imem_master_awlock             O     1 reg
// imem_master_awcache            O     4 reg
// imem_master_awprot             O     3 reg
// imem_master_awqos              O     4 reg
// imem_master_awregion           O     4 reg
// imem_master_wvalid             O     1 reg
// imem_master_wdata              O    64 reg
// imem_master_wstrb              O     8 reg
// imem_master_wlast              O     1 reg
// imem_master_bready             O     1 reg
// imem_master_arvalid            O     1 reg
// imem_master_arid               O    16 reg
// imem_master_araddr             O    64 reg
// imem_master_arlen              O     8 reg
// imem_master_arsize             O     3 reg
// imem_master_arburst            O     2 reg
// imem_master_arlock             O     1 reg
// imem_master_arcache            O     4 reg
// imem_master_arprot             O     3 reg
// imem_master_arqos              O     4 reg
// imem_master_arregion           O     4 reg
// imem_master_rready             O     1 reg
// dmem_valid                     O     1
// dmem_word64                    O    64
// dmem_st_amo_val                O    64
// dmem_exc                       O     1
// dmem_exc_code                  O     4
// mem_master_awvalid             O     1
// mem_master_awid                O    16 reg
// mem_master_awaddr              O    64 reg
// mem_master_awlen               O     8 reg
// mem_master_awsize              O     3 reg
// mem_master_awburst             O     2 reg
// mem_master_awlock              O     1 reg
// mem_master_awcache             O     4 reg
// mem_master_awprot              O     3 reg
// mem_master_awqos               O     4 reg
// mem_master_awregion            O     4 reg
// mem_master_wvalid              O     1
// mem_master_wdata               O    64 reg
// mem_master_wstrb               O     8 reg
// mem_master_wlast               O     1 reg
// mem_master_bready              O     1
// mem_master_arvalid             O     1
// mem_master_arid                O    16 reg
// mem_master_araddr              O    64 reg
// mem_master_arlen               O     8 reg
// mem_master_arsize              O     3 reg
// mem_master_arburst             O     2 reg
// mem_master_arlock              O     1 reg
// mem_master_arcache             O     4 reg
// mem_master_arprot              O     3 reg
// mem_master_arqos               O     4 reg
// mem_master_arregion            O     4 reg
// mem_master_rready              O     1
// RDY_server_fence_i_request_put  O     1 const
// RDY_server_fence_i_response_get  O     1 const
// RDY_server_fence_request_put   O     1 const
// RDY_server_fence_response_get  O     1 const
// RDY_sfence_vma_server_request_put  O     1 const
// RDY_sfence_vma_server_response_get  O     1 const
// dma_server_awready             O     1 reg
// dma_server_wready              O     1 reg
// dma_server_bvalid              O     1 reg
// dma_server_bid                 O    16 reg
// dma_server_bresp               O     2 reg
// dma_server_arready             O     1 reg
// dma_server_rvalid              O     1 reg
// dma_server_rid                 O    16 reg
// dma_server_rdata               O   512 reg
// dma_server_rresp               O     2 reg
// dma_server_rlast               O     1 reg
// RDY_ma_ddr4_ready              O     1 const
// mv_status                      O     8
// CLK                            I     1 clock
// RST_N                          I     1 reset
// imem_req_f3                    I     3 unused
// imem_req_addr                  I    64
// imem_req_priv                  I     2
// imem_req_sstatus_SUM           I     1
// imem_req_mstatus_MXR           I     1
// imem_req_satp                  I    64
// imem_master_awready            I     1
// imem_master_wready             I     1
// imem_master_bvalid             I     1
// imem_master_bid                I    16 reg
// imem_master_bresp              I     2 reg
// imem_master_arready            I     1
// imem_master_rvalid             I     1
// imem_master_rid                I    16 reg
// imem_master_rdata              I    64 reg
// imem_master_rresp              I     2 reg
// imem_master_rlast              I     1 reg
// dmem_req_op                    I     2
// dmem_req_f3                    I     3
// dmem_req_amo_funct7            I     7
// dmem_req_addr                  I    64
// dmem_req_store_value           I    64
// dmem_req_priv                  I     2
// dmem_req_sstatus_SUM           I     1
// dmem_req_mstatus_MXR           I     1
// dmem_req_satp                  I    64
// mem_master_awready             I     1
// mem_master_wready              I     1
// mem_master_bvalid              I     1
// mem_master_bid                 I    16 reg
// mem_master_bresp               I     2 reg
// mem_master_arready             I     1
// mem_master_rvalid              I     1
// mem_master_rid                 I    16 reg
// mem_master_rdata               I    64 reg
// mem_master_rresp               I     2 reg
// mem_master_rlast               I     1 reg
// server_fence_request_put       I     8 unused
// dma_server_awvalid             I     1
// dma_server_awid                I    16 reg
// dma_server_awaddr              I    64 reg
// dma_server_awlen               I     8 reg
// dma_server_awsize              I     3 reg
// dma_server_awburst             I     2 reg
// dma_server_awlock              I     1 reg
// dma_server_awcache             I     4 reg
// dma_server_awprot              I     3 reg
// dma_server_awqos               I     4 reg
// dma_server_awregion            I     4 reg
// dma_server_wvalid              I     1
// dma_server_wdata               I   512 reg
// dma_server_wstrb               I    64 reg
// dma_server_wlast               I     1 reg
// dma_server_bready              I     1
// dma_server_arvalid             I     1
// dma_server_arid                I    16 reg
// dma_server_araddr              I    64 reg
// dma_server_arlen               I     8 reg
// dma_server_arsize              I     3 reg
// dma_server_arburst             I     2 reg
// dma_server_arlock              I     1 reg
// dma_server_arcache             I     4 reg
// dma_server_arprot              I     3 reg
// dma_server_arqos               I     4 reg
// dma_server_arregion            I     4 reg
// dma_server_rready              I     1
// EN_server_reset_request_put    I     1
// EN_server_reset_response_get   I     1
// EN_imem_req                    I     1
// EN_dmem_req                    I     1
// EN_server_fence_i_request_put  I     1 unused
// EN_server_fence_i_response_get  I     1 unused
// EN_server_fence_request_put    I     1 unused
// EN_server_fence_response_get   I     1 unused
// EN_sfence_vma_server_request_put  I     1
// EN_sfence_vma_server_response_get  I     1 unused
// EN_ma_ddr4_ready               I     1
//
// Combinational paths from inputs to outputs:
//   (mem_master_awready, mem_master_wready) -> mem_master_bready
//
//

`ifdef BSV_ASSIGNMENT_DELAY
`else
  `define BSV_ASSIGNMENT_DELAY
`endif

`ifdef BSV_POSITIVE_RESET
  `define BSV_RESET_VALUE 1'b1
  `define BSV_RESET_EDGE posedge
`else
  `define BSV_RESET_VALUE 1'b0
  `define BSV_RESET_EDGE negedge
`endif

module mkNear_Mem(CLK,
		  RST_N,

		  EN_server_reset_request_put,
		  RDY_server_reset_request_put,

		  EN_server_reset_response_get,
		  RDY_server_reset_response_get,

		  imem_req_f3,
		  imem_req_addr,
		  imem_req_priv,
		  imem_req_sstatus_SUM,
		  imem_req_mstatus_MXR,
		  imem_req_satp,
		  EN_imem_req,

		  imem_valid,

		  imem_is_i32_not_i16,

		  imem_pc,

		  imem_instr,

		  imem_exc,

		  imem_exc_code,

		  imem_tval,

		  imem_master_awvalid,

		  imem_master_awid,

		  imem_master_awaddr,

		  imem_master_awlen,

		  imem_master_awsize,

		  imem_master_awburst,

		  imem_master_awlock,

		  imem_master_awcache,

		  imem_master_awprot,

		  imem_master_awqos,

		  imem_master_awregion,

		  imem_master_awready,

		  imem_master_wvalid,

		  imem_master_wdata,

		  imem_master_wstrb,

		  imem_master_wlast,

		  imem_master_wready,

		  imem_master_bvalid,
		  imem_master_bid,
		  imem_master_bresp,

		  imem_master_bready,

		  imem_master_arvalid,

		  imem_master_arid,

		  imem_master_araddr,

		  imem_master_arlen,

		  imem_master_arsize,

		  imem_master_arburst,

		  imem_master_arlock,

		  imem_master_arcache,

		  imem_master_arprot,

		  imem_master_arqos,

		  imem_master_arregion,

		  imem_master_arready,

		  imem_master_rvalid,
		  imem_master_rid,
		  imem_master_rdata,
		  imem_master_rresp,
		  imem_master_rlast,

		  imem_master_rready,

		  dmem_req_op,
		  dmem_req_f3,
		  dmem_req_amo_funct7,
		  dmem_req_addr,
		  dmem_req_store_value,
		  dmem_req_priv,
		  dmem_req_sstatus_SUM,
		  dmem_req_mstatus_MXR,
		  dmem_req_satp,
		  EN_dmem_req,

		  dmem_valid,

		  dmem_word64,

		  dmem_st_amo_val,

		  dmem_exc,

		  dmem_exc_code,

		  mem_master_awvalid,

		  mem_master_awid,

		  mem_master_awaddr,

		  mem_master_awlen,

		  mem_master_awsize,

		  mem_master_awburst,

		  mem_master_awlock,

		  mem_master_awcache,

		  mem_master_awprot,

		  mem_master_awqos,

		  mem_master_awregion,

		  mem_master_awready,

		  mem_master_wvalid,

		  mem_master_wdata,

		  mem_master_wstrb,

		  mem_master_wlast,

		  mem_master_wready,

		  mem_master_bvalid,
		  mem_master_bid,
		  mem_master_bresp,

		  mem_master_bready,

		  mem_master_arvalid,

		  mem_master_arid,

		  mem_master_araddr,

		  mem_master_arlen,

		  mem_master_arsize,

		  mem_master_arburst,

		  mem_master_arlock,

		  mem_master_arcache,

		  mem_master_arprot,

		  mem_master_arqos,

		  mem_master_arregion,

		  mem_master_arready,

		  mem_master_rvalid,
		  mem_master_rid,
		  mem_master_rdata,
		  mem_master_rresp,
		  mem_master_rlast,

		  mem_master_rready,

		  EN_server_fence_i_request_put,
		  RDY_server_fence_i_request_put,

		  EN_server_fence_i_response_get,
		  RDY_server_fence_i_response_get,

		  server_fence_request_put,
		  EN_server_fence_request_put,
		  RDY_server_fence_request_put,

		  EN_server_fence_response_get,
		  RDY_server_fence_response_get,

		  EN_sfence_vma_server_request_put,
		  RDY_sfence_vma_server_request_put,

		  EN_sfence_vma_server_response_get,
		  RDY_sfence_vma_server_response_get,

		  dma_server_awvalid,
		  dma_server_awid,
		  dma_server_awaddr,
		  dma_server_awlen,
		  dma_server_awsize,
		  dma_server_awburst,
		  dma_server_awlock,
		  dma_server_awcache,
		  dma_server_awprot,
		  dma_server_awqos,
		  dma_server_awregion,

		  dma_server_awready,

		  dma_server_wvalid,
		  dma_server_wdata,
		  dma_server_wstrb,
		  dma_server_wlast,

		  dma_server_wready,

		  dma_server_bvalid,

		  dma_server_bid,

		  dma_server_bresp,

		  dma_server_bready,

		  dma_server_arvalid,
		  dma_server_arid,
		  dma_server_araddr,
		  dma_server_arlen,
		  dma_server_arsize,
		  dma_server_arburst,
		  dma_server_arlock,
		  dma_server_arcache,
		  dma_server_arprot,
		  dma_server_arqos,
		  dma_server_arregion,

		  dma_server_arready,

		  dma_server_rvalid,

		  dma_server_rid,

		  dma_server_rdata,

		  dma_server_rresp,

		  dma_server_rlast,

		  dma_server_rready,

		  EN_ma_ddr4_ready,
		  RDY_ma_ddr4_ready,

		  mv_status);
  input  CLK;
  input  RST_N;

  // action method server_reset_request_put
  input  EN_server_reset_request_put;
  output RDY_server_reset_request_put;

  // action method server_reset_response_get
  input  EN_server_reset_response_get;
  output RDY_server_reset_response_get;

  // action method imem_req
  input  [2 : 0] imem_req_f3;
  input  [63 : 0] imem_req_addr;
  input  [1 : 0] imem_req_priv;
  input  imem_req_sstatus_SUM;
  input  imem_req_mstatus_MXR;
  input  [63 : 0] imem_req_satp;
  input  EN_imem_req;

  // value method imem_valid
  output imem_valid;

  // value method imem_is_i32_not_i16
  output imem_is_i32_not_i16;

  // value method imem_pc
  output [63 : 0] imem_pc;

  // value method imem_instr
  output [31 : 0] imem_instr;

  // value method imem_exc
  output imem_exc;

  // value method imem_exc_code
  output [3 : 0] imem_exc_code;

  // value method imem_tval
  output [63 : 0] imem_tval;

  // value method imem_master_m_awvalid
  output imem_master_awvalid;

  // value method imem_master_m_awid
  output [15 : 0] imem_master_awid;

  // value method imem_master_m_awaddr
  output [63 : 0] imem_master_awaddr;

  // value method imem_master_m_awlen
  output [7 : 0] imem_master_awlen;

  // value method imem_master_m_awsize
  output [2 : 0] imem_master_awsize;

  // value method imem_master_m_awburst
  output [1 : 0] imem_master_awburst;

  // value method imem_master_m_awlock
  output imem_master_awlock;

  // value method imem_master_m_awcache
  output [3 : 0] imem_master_awcache;

  // value method imem_master_m_awprot
  output [2 : 0] imem_master_awprot;

  // value method imem_master_m_awqos
  output [3 : 0] imem_master_awqos;

  // value method imem_master_m_awregion
  output [3 : 0] imem_master_awregion;

  // value method imem_master_m_awuser

  // action method imem_master_m_awready
  input  imem_master_awready;

  // value method imem_master_m_wvalid
  output imem_master_wvalid;

  // value method imem_master_m_wdata
  output [63 : 0] imem_master_wdata;

  // value method imem_master_m_wstrb
  output [7 : 0] imem_master_wstrb;

  // value method imem_master_m_wlast
  output imem_master_wlast;

  // value method imem_master_m_wuser

  // action method imem_master_m_wready
  input  imem_master_wready;

  // action method imem_master_m_bvalid
  input  imem_master_bvalid;
  input  [15 : 0] imem_master_bid;
  input  [1 : 0] imem_master_bresp;

  // value method imem_master_m_bready
  output imem_master_bready;

  // value method imem_master_m_arvalid
  output imem_master_arvalid;

  // value method imem_master_m_arid
  output [15 : 0] imem_master_arid;

  // value method imem_master_m_araddr
  output [63 : 0] imem_master_araddr;

  // value method imem_master_m_arlen
  output [7 : 0] imem_master_arlen;

  // value method imem_master_m_arsize
  output [2 : 0] imem_master_arsize;

  // value method imem_master_m_arburst
  output [1 : 0] imem_master_arburst;

  // value method imem_master_m_arlock
  output imem_master_arlock;

  // value method imem_master_m_arcache
  output [3 : 0] imem_master_arcache;

  // value method imem_master_m_arprot
  output [2 : 0] imem_master_arprot;

  // value method imem_master_m_arqos
  output [3 : 0] imem_master_arqos;

  // value method imem_master_m_arregion
  output [3 : 0] imem_master_arregion;

  // value method imem_master_m_aruser

  // action method imem_master_m_arready
  input  imem_master_arready;

  // action method imem_master_m_rvalid
  input  imem_master_rvalid;
  input  [15 : 0] imem_master_rid;
  input  [63 : 0] imem_master_rdata;
  input  [1 : 0] imem_master_rresp;
  input  imem_master_rlast;

  // value method imem_master_m_rready
  output imem_master_rready;

  // action method dmem_req
  input  [1 : 0] dmem_req_op;
  input  [2 : 0] dmem_req_f3;
  input  [6 : 0] dmem_req_amo_funct7;
  input  [63 : 0] dmem_req_addr;
  input  [63 : 0] dmem_req_store_value;
  input  [1 : 0] dmem_req_priv;
  input  dmem_req_sstatus_SUM;
  input  dmem_req_mstatus_MXR;
  input  [63 : 0] dmem_req_satp;
  input  EN_dmem_req;

  // value method dmem_valid
  output dmem_valid;

  // value method dmem_word64
  output [63 : 0] dmem_word64;

  // value method dmem_st_amo_val
  output [63 : 0] dmem_st_amo_val;

  // value method dmem_exc
  output dmem_exc;

  // value method dmem_exc_code
  output [3 : 0] dmem_exc_code;

  // value method mem_master_m_awvalid
  output mem_master_awvalid;

  // value method mem_master_m_awid
  output [15 : 0] mem_master_awid;

  // value method mem_master_m_awaddr
  output [63 : 0] mem_master_awaddr;

  // value method mem_master_m_awlen
  output [7 : 0] mem_master_awlen;

  // value method mem_master_m_awsize
  output [2 : 0] mem_master_awsize;

  // value method mem_master_m_awburst
  output [1 : 0] mem_master_awburst;

  // value method mem_master_m_awlock
  output mem_master_awlock;

  // value method mem_master_m_awcache
  output [3 : 0] mem_master_awcache;

  // value method mem_master_m_awprot
  output [2 : 0] mem_master_awprot;

  // value method mem_master_m_awqos
  output [3 : 0] mem_master_awqos;

  // value method mem_master_m_awregion
  output [3 : 0] mem_master_awregion;

  // value method mem_master_m_awuser

  // action method mem_master_m_awready
  input  mem_master_awready;

  // value method mem_master_m_wvalid
  output mem_master_wvalid;

  // value method mem_master_m_wdata
  output [63 : 0] mem_master_wdata;

  // value method mem_master_m_wstrb
  output [7 : 0] mem_master_wstrb;

  // value method mem_master_m_wlast
  output mem_master_wlast;

  // value method mem_master_m_wuser

  // action method mem_master_m_wready
  input  mem_master_wready;

  // action method mem_master_m_bvalid
  input  mem_master_bvalid;
  input  [15 : 0] mem_master_bid;
  input  [1 : 0] mem_master_bresp;

  // value method mem_master_m_bready
  output mem_master_bready;

  // value method mem_master_m_arvalid
  output mem_master_arvalid;

  // value method mem_master_m_arid
  output [15 : 0] mem_master_arid;

  // value method mem_master_m_araddr
  output [63 : 0] mem_master_araddr;

  // value method mem_master_m_arlen
  output [7 : 0] mem_master_arlen;

  // value method mem_master_m_arsize
  output [2 : 0] mem_master_arsize;

  // value method mem_master_m_arburst
  output [1 : 0] mem_master_arburst;

  // value method mem_master_m_arlock
  output mem_master_arlock;

  // value method mem_master_m_arcache
  output [3 : 0] mem_master_arcache;

  // value method mem_master_m_arprot
  output [2 : 0] mem_master_arprot;

  // value method mem_master_m_arqos
  output [3 : 0] mem_master_arqos;

  // value method mem_master_m_arregion
  output [3 : 0] mem_master_arregion;

  // value method mem_master_m_aruser

  // action method mem_master_m_arready
  input  mem_master_arready;

  // action method mem_master_m_rvalid
  input  mem_master_rvalid;
  input  [15 : 0] mem_master_rid;
  input  [63 : 0] mem_master_rdata;
  input  [1 : 0] mem_master_rresp;
  input  mem_master_rlast;

  // value method mem_master_m_rready
  output mem_master_rready;

  // action method server_fence_i_request_put
  input  EN_server_fence_i_request_put;
  output RDY_server_fence_i_request_put;

  // action method server_fence_i_response_get
  input  EN_server_fence_i_response_get;
  output RDY_server_fence_i_response_get;

  // action method server_fence_request_put
  input  [7 : 0] server_fence_request_put;
  input  EN_server_fence_request_put;
  output RDY_server_fence_request_put;

  // action method server_fence_response_get
  input  EN_server_fence_response_get;
  output RDY_server_fence_response_get;

  // action method sfence_vma_server_request_put
  input  EN_sfence_vma_server_request_put;
  output RDY_sfence_vma_server_request_put;

  // action method sfence_vma_server_response_get
  input  EN_sfence_vma_server_response_get;
  output RDY_sfence_vma_server_response_get;

  // action method dma_server_m_awvalid
  input  dma_server_awvalid;
  input  [15 : 0] dma_server_awid;
  input  [63 : 0] dma_server_awaddr;
  input  [7 : 0] dma_server_awlen;
  input  [2 : 0] dma_server_awsize;
  input  [1 : 0] dma_server_awburst;
  input  dma_server_awlock;
  input  [3 : 0] dma_server_awcache;
  input  [2 : 0] dma_server_awprot;
  input  [3 : 0] dma_server_awqos;
  input  [3 : 0] dma_server_awregion;

  // value method dma_server_m_awready
  output dma_server_awready;

  // action method dma_server_m_wvalid
  input  dma_server_wvalid;
  input  [511 : 0] dma_server_wdata;
  input  [63 : 0] dma_server_wstrb;
  input  dma_server_wlast;

  // value method dma_server_m_wready
  output dma_server_wready;

  // value method dma_server_m_bvalid
  output dma_server_bvalid;

  // value method dma_server_m_bid
  output [15 : 0] dma_server_bid;

  // value method dma_server_m_bresp
  output [1 : 0] dma_server_bresp;

  // value method dma_server_m_buser

  // action method dma_server_m_bready
  input  dma_server_bready;

  // action method dma_server_m_arvalid
  input  dma_server_arvalid;
  input  [15 : 0] dma_server_arid;
  input  [63 : 0] dma_server_araddr;
  input  [7 : 0] dma_server_arlen;
  input  [2 : 0] dma_server_arsize;
  input  [1 : 0] dma_server_arburst;
  input  dma_server_arlock;
  input  [3 : 0] dma_server_arcache;
  input  [2 : 0] dma_server_arprot;
  input  [3 : 0] dma_server_arqos;
  input  [3 : 0] dma_server_arregion;

  // value method dma_server_m_arready
  output dma_server_arready;

  // value method dma_server_m_rvalid
  output dma_server_rvalid;

  // value method dma_server_m_rid
  output [15 : 0] dma_server_rid;

  // value method dma_server_m_rdata
  output [511 : 0] dma_server_rdata;

  // value method dma_server_m_rresp
  output [1 : 0] dma_server_rresp;

  // value method dma_server_m_rlast
  output dma_server_rlast;

  // value method dma_server_m_ruser

  // action method dma_server_m_rready
  input  dma_server_rready;

  // action method ma_ddr4_ready
  input  EN_ma_ddr4_ready;
  output RDY_ma_ddr4_ready;

  // value method mv_status
  output [7 : 0] mv_status;

  // signals for module outputs
  wire [511 : 0] dma_server_rdata;
  wire [63 : 0] dmem_st_amo_val,
		dmem_word64,
		imem_master_araddr,
		imem_master_awaddr,
		imem_master_wdata,
		imem_pc,
		imem_tval,
		mem_master_araddr,
		mem_master_awaddr,
		mem_master_wdata;
  wire [31 : 0] imem_instr;
  wire [15 : 0] dma_server_bid,
		dma_server_rid,
		imem_master_arid,
		imem_master_awid,
		mem_master_arid,
		mem_master_awid;
  wire [7 : 0] imem_master_arlen,
	       imem_master_awlen,
	       imem_master_wstrb,
	       mem_master_arlen,
	       mem_master_awlen,
	       mem_master_wstrb,
	       mv_status;
  wire [3 : 0] dmem_exc_code,
	       imem_exc_code,
	       imem_master_arcache,
	       imem_master_arqos,
	       imem_master_arregion,
	       imem_master_awcache,
	       imem_master_awqos,
	       imem_master_awregion,
	       mem_master_arcache,
	       mem_master_arqos,
	       mem_master_arregion,
	       mem_master_awcache,
	       mem_master_awqos,
	       mem_master_awregion;
  wire [2 : 0] imem_master_arprot,
	       imem_master_arsize,
	       imem_master_awprot,
	       imem_master_awsize,
	       mem_master_arprot,
	       mem_master_arsize,
	       mem_master_awprot,
	       mem_master_awsize;
  wire [1 : 0] dma_server_bresp,
	       dma_server_rresp,
	       imem_master_arburst,
	       imem_master_awburst,
	       mem_master_arburst,
	       mem_master_awburst;
  wire RDY_ma_ddr4_ready,
       RDY_server_fence_i_request_put,
       RDY_server_fence_i_response_get,
       RDY_server_fence_request_put,
       RDY_server_fence_response_get,
       RDY_server_reset_request_put,
       RDY_server_reset_response_get,
       RDY_sfence_vma_server_request_put,
       RDY_sfence_vma_server_response_get,
       dma_server_arready,
       dma_server_awready,
       dma_server_bvalid,
       dma_server_rlast,
       dma_server_rvalid,
       dma_server_wready,
       dmem_exc,
       dmem_valid,
       imem_exc,
       imem_is_i32_not_i16,
       imem_master_arlock,
       imem_master_arvalid,
       imem_master_awlock,
       imem_master_awvalid,
       imem_master_bready,
       imem_master_rready,
       imem_master_wlast,
       imem_master_wvalid,
       imem_valid,
       mem_master_arlock,
       mem_master_arvalid,
       mem_master_awlock,
       mem_master_awvalid,
       mem_master_bready,
       mem_master_rready,
       mem_master_wlast,
       mem_master_wvalid;

  // inlined wires
  wire [580 : 0] enqDst_1_0_lat_0$wget;
  wire [579 : 0] propDstData_1_0_lat_0$wget, propDstData_1_1_lat_0$wget;
  wire [73 : 0] enqDst_0_lat_0$wget;
  wire [72 : 0] propDstData_0_lat_0$wget, propDstData_1_lat_0$wget;
  wire [3 : 0] llc_axi4_adapter_ctr_wr_rsps_pending_crg$port0__write_1,
	       llc_axi4_adapter_ctr_wr_rsps_pending_crg$port1__write_1,
	       llc_axi4_adapter_ctr_wr_rsps_pending_crg$port2__read;
  wire llc_axi4_adapter_master_xactor_crg_rd_addr_full$EN_port1__write,
       llc_axi4_adapter_master_xactor_crg_rd_addr_full$port2__read,
       llc_axi4_adapter_master_xactor_crg_rd_addr_full$port3__read,
       llc_axi4_adapter_master_xactor_crg_rd_data_full$EN_port2__write,
       llc_axi4_adapter_master_xactor_crg_rd_data_full$port2__read,
       llc_axi4_adapter_master_xactor_crg_rd_data_full$port3__read,
       llc_axi4_adapter_master_xactor_crg_wr_addr_full$EN_port1__write,
       llc_axi4_adapter_master_xactor_crg_wr_addr_full$port2__read,
       llc_axi4_adapter_master_xactor_crg_wr_addr_full$port3__read,
       llc_axi4_adapter_master_xactor_crg_wr_data_full$EN_port1__write,
       llc_axi4_adapter_master_xactor_crg_wr_data_full$port2__read,
       llc_axi4_adapter_master_xactor_crg_wr_data_full$port3__read,
       llc_axi4_adapter_master_xactor_crg_wr_resp_full$EN_port2__write,
       llc_axi4_adapter_master_xactor_crg_wr_resp_full$port2__read,
       llc_axi4_adapter_master_xactor_crg_wr_resp_full$port3__read,
       propDstIdx_0_lat_1$whas,
       propDstIdx_1_0_lat_1$whas,
       propDstIdx_1_1_lat_1$whas,
       propDstIdx_1_lat_1$whas;

  // register cfg_verbosity
  reg [3 : 0] cfg_verbosity;
  wire [3 : 0] cfg_verbosity$D_IN;
  wire cfg_verbosity$EN;

  // register enqDst_0_rl
  reg [73 : 0] enqDst_0_rl;
  wire [73 : 0] enqDst_0_rl$D_IN;
  wire enqDst_0_rl$EN;

  // register enqDst_1_0_rl
  reg [580 : 0] enqDst_1_0_rl;
  wire [580 : 0] enqDst_1_0_rl$D_IN;
  wire enqDst_1_0_rl$EN;

  // register llc_axi4_adapter_ctr_wr_rsps_pending_crg
  reg [3 : 0] llc_axi4_adapter_ctr_wr_rsps_pending_crg;
  wire [3 : 0] llc_axi4_adapter_ctr_wr_rsps_pending_crg$D_IN;
  wire llc_axi4_adapter_ctr_wr_rsps_pending_crg$EN;

  // register llc_axi4_adapter_master_xactor_crg_rd_addr_full
  reg llc_axi4_adapter_master_xactor_crg_rd_addr_full;
  wire llc_axi4_adapter_master_xactor_crg_rd_addr_full$D_IN,
       llc_axi4_adapter_master_xactor_crg_rd_addr_full$EN;

  // register llc_axi4_adapter_master_xactor_crg_rd_data_full
  reg llc_axi4_adapter_master_xactor_crg_rd_data_full;
  wire llc_axi4_adapter_master_xactor_crg_rd_data_full$D_IN,
       llc_axi4_adapter_master_xactor_crg_rd_data_full$EN;

  // register llc_axi4_adapter_master_xactor_crg_wr_addr_full
  reg llc_axi4_adapter_master_xactor_crg_wr_addr_full;
  wire llc_axi4_adapter_master_xactor_crg_wr_addr_full$D_IN,
       llc_axi4_adapter_master_xactor_crg_wr_addr_full$EN;

  // register llc_axi4_adapter_master_xactor_crg_wr_data_full
  reg llc_axi4_adapter_master_xactor_crg_wr_data_full;
  wire llc_axi4_adapter_master_xactor_crg_wr_data_full$D_IN,
       llc_axi4_adapter_master_xactor_crg_wr_data_full$EN;

  // register llc_axi4_adapter_master_xactor_crg_wr_resp_full
  reg llc_axi4_adapter_master_xactor_crg_wr_resp_full;
  wire llc_axi4_adapter_master_xactor_crg_wr_resp_full$D_IN,
       llc_axi4_adapter_master_xactor_crg_wr_resp_full$EN;

  // register llc_axi4_adapter_master_xactor_rg_rd_addr
  reg [108 : 0] llc_axi4_adapter_master_xactor_rg_rd_addr;
  wire [108 : 0] llc_axi4_adapter_master_xactor_rg_rd_addr$D_IN;
  wire llc_axi4_adapter_master_xactor_rg_rd_addr$EN;

  // register llc_axi4_adapter_master_xactor_rg_rd_data
  reg [82 : 0] llc_axi4_adapter_master_xactor_rg_rd_data;
  wire [82 : 0] llc_axi4_adapter_master_xactor_rg_rd_data$D_IN;
  wire llc_axi4_adapter_master_xactor_rg_rd_data$EN;

  // register llc_axi4_adapter_master_xactor_rg_wr_addr
  reg [108 : 0] llc_axi4_adapter_master_xactor_rg_wr_addr;
  wire [108 : 0] llc_axi4_adapter_master_xactor_rg_wr_addr$D_IN;
  wire llc_axi4_adapter_master_xactor_rg_wr_addr$EN;

  // register llc_axi4_adapter_master_xactor_rg_wr_data
  reg [72 : 0] llc_axi4_adapter_master_xactor_rg_wr_data;
  wire [72 : 0] llc_axi4_adapter_master_xactor_rg_wr_data$D_IN;
  wire llc_axi4_adapter_master_xactor_rg_wr_data$EN;

  // register llc_axi4_adapter_master_xactor_rg_wr_resp
  reg [17 : 0] llc_axi4_adapter_master_xactor_rg_wr_resp;
  wire [17 : 0] llc_axi4_adapter_master_xactor_rg_wr_resp$D_IN;
  wire llc_axi4_adapter_master_xactor_rg_wr_resp$EN;

  // register llc_axi4_adapter_rg_AXI4_error
  reg llc_axi4_adapter_rg_AXI4_error;
  wire llc_axi4_adapter_rg_AXI4_error$D_IN, llc_axi4_adapter_rg_AXI4_error$EN;

  // register llc_axi4_adapter_rg_cline
  reg [511 : 0] llc_axi4_adapter_rg_cline;
  wire [511 : 0] llc_axi4_adapter_rg_cline$D_IN;
  wire llc_axi4_adapter_rg_cline$EN;

  // register llc_axi4_adapter_rg_ddr4_ready
  reg llc_axi4_adapter_rg_ddr4_ready;
  wire llc_axi4_adapter_rg_ddr4_ready$D_IN, llc_axi4_adapter_rg_ddr4_ready$EN;

  // register llc_axi4_adapter_rg_rd_req_beat
  reg [2 : 0] llc_axi4_adapter_rg_rd_req_beat;
  wire [2 : 0] llc_axi4_adapter_rg_rd_req_beat$D_IN;
  wire llc_axi4_adapter_rg_rd_req_beat$EN;

  // register llc_axi4_adapter_rg_rd_rsp_beat
  reg [2 : 0] llc_axi4_adapter_rg_rd_rsp_beat;
  wire [2 : 0] llc_axi4_adapter_rg_rd_rsp_beat$D_IN;
  wire llc_axi4_adapter_rg_rd_rsp_beat$EN;

  // register llc_axi4_adapter_rg_wr_req_beat
  reg [2 : 0] llc_axi4_adapter_rg_wr_req_beat;
  wire [2 : 0] llc_axi4_adapter_rg_wr_req_beat$D_IN;
  wire llc_axi4_adapter_rg_wr_req_beat$EN;

  // register llc_axi4_adapter_rg_wr_rsp_beat
  reg [2 : 0] llc_axi4_adapter_rg_wr_rsp_beat;
  wire [2 : 0] llc_axi4_adapter_rg_wr_rsp_beat$D_IN;
  wire llc_axi4_adapter_rg_wr_rsp_beat$EN;

  // register propDstData_0_rl
  reg [72 : 0] propDstData_0_rl;
  wire [72 : 0] propDstData_0_rl$D_IN;
  wire propDstData_0_rl$EN;

  // register propDstData_1_0_rl
  reg [579 : 0] propDstData_1_0_rl;
  wire [579 : 0] propDstData_1_0_rl$D_IN;
  wire propDstData_1_0_rl$EN;

  // register propDstData_1_1_rl
  reg [579 : 0] propDstData_1_1_rl;
  wire [579 : 0] propDstData_1_1_rl$D_IN;
  wire propDstData_1_1_rl$EN;

  // register propDstData_1_rl
  reg [72 : 0] propDstData_1_rl;
  wire [72 : 0] propDstData_1_rl$D_IN;
  wire propDstData_1_rl$EN;

  // register propDstIdx_0_rl
  reg propDstIdx_0_rl;
  wire propDstIdx_0_rl$D_IN, propDstIdx_0_rl$EN;

  // register propDstIdx_1_0_rl
  reg propDstIdx_1_0_rl;
  wire propDstIdx_1_0_rl$D_IN, propDstIdx_1_0_rl$EN;

  // register propDstIdx_1_1_rl
  reg propDstIdx_1_1_rl;
  wire propDstIdx_1_1_rl$D_IN, propDstIdx_1_1_rl$EN;

  // register propDstIdx_1_rl
  reg propDstIdx_1_rl;
  wire propDstIdx_1_rl$D_IN, propDstIdx_1_rl$EN;

  // register rg_state
  reg [1 : 0] rg_state;
  reg [1 : 0] rg_state$D_IN;
  wire rg_state$EN;

  // register srcRR_0
  reg srcRR_0;
  wire srcRR_0$D_IN, srcRR_0$EN;

  // register srcRR_1_0
  reg srcRR_1_0;
  wire srcRR_1_0$D_IN, srcRR_1_0$EN;

  // ports of submodule d_mmu_cache
  wire [578 : 0] d_mmu_cache$l1_to_l2_client_response_enq_x,
		 d_mmu_cache$l2_to_l1_server_response_first;
  wire [131 : 0] d_mmu_cache$imem_ptw_server_response_get;
  wire [130 : 0] d_mmu_cache$mmio_client_request_get;
  wire [127 : 0] d_mmu_cache$imem_pte_writeback_p_put,
		 d_mmu_cache$imem_ptw_server_request_put;
  wire [68 : 0] d_mmu_cache$l1_to_l2_client_request_first;
  wire [65 : 0] d_mmu_cache$l2_to_l1_server_request_enq_x;
  wire [64 : 0] d_mmu_cache$mmio_client_response_put;
  wire [63 : 0] d_mmu_cache$ma_req_satp,
		d_mmu_cache$ma_req_st_value,
		d_mmu_cache$ma_req_va,
		d_mmu_cache$st_amo_val,
		d_mmu_cache$word64;
  wire [6 : 0] d_mmu_cache$ma_req_amo_funct7;
  wire [3 : 0] d_mmu_cache$exc_code;
  wire [2 : 0] d_mmu_cache$ma_req_f3;
  wire [1 : 0] d_mmu_cache$ma_req_op, d_mmu_cache$ma_req_priv;
  wire d_mmu_cache$EN_flush_server_request_put,
       d_mmu_cache$EN_flush_server_response_get,
       d_mmu_cache$EN_imem_pte_writeback_p_put,
       d_mmu_cache$EN_imem_ptw_server_request_put,
       d_mmu_cache$EN_imem_ptw_server_response_get,
       d_mmu_cache$EN_l1_to_l2_client_request_deq,
       d_mmu_cache$EN_l1_to_l2_client_response_enq,
       d_mmu_cache$EN_l2_to_l1_server_request_enq,
       d_mmu_cache$EN_l2_to_l1_server_response_deq,
       d_mmu_cache$EN_ma_req,
       d_mmu_cache$EN_mmio_client_request_get,
       d_mmu_cache$EN_mmio_client_response_put,
       d_mmu_cache$EN_tlb_flush,
       d_mmu_cache$RDY_imem_pte_writeback_p_put,
       d_mmu_cache$RDY_imem_ptw_server_request_put,
       d_mmu_cache$RDY_imem_ptw_server_response_get,
       d_mmu_cache$RDY_l1_to_l2_client_request_deq,
       d_mmu_cache$RDY_l1_to_l2_client_request_first,
       d_mmu_cache$RDY_l1_to_l2_client_response_enq,
       d_mmu_cache$RDY_l2_to_l1_server_request_enq,
       d_mmu_cache$RDY_l2_to_l1_server_response_deq,
       d_mmu_cache$RDY_l2_to_l1_server_response_first,
       d_mmu_cache$RDY_mmio_client_request_get,
       d_mmu_cache$RDY_mmio_client_response_put,
       d_mmu_cache$exc,
       d_mmu_cache$flush_server_request_put,
       d_mmu_cache$ma_req_mstatus_MXR,
       d_mmu_cache$ma_req_sstatus_SUM,
       d_mmu_cache$valid;

  // ports of submodule enqDst_0_dummy2_0
  wire enqDst_0_dummy2_0$D_IN, enqDst_0_dummy2_0$EN, enqDst_0_dummy2_0$Q_OUT;

  // ports of submodule enqDst_0_dummy2_1
  wire enqDst_0_dummy2_1$D_IN, enqDst_0_dummy2_1$EN, enqDst_0_dummy2_1$Q_OUT;

  // ports of submodule enqDst_1_0_dummy2_0
  wire enqDst_1_0_dummy2_0$D_IN,
       enqDst_1_0_dummy2_0$EN,
       enqDst_1_0_dummy2_0$Q_OUT;

  // ports of submodule enqDst_1_0_dummy2_1
  wire enqDst_1_0_dummy2_1$D_IN,
       enqDst_1_0_dummy2_1$EN,
       enqDst_1_0_dummy2_1$Q_OUT;

  // ports of submodule f_reset_rsps
  wire f_reset_rsps$CLR,
       f_reset_rsps$DEQ,
       f_reset_rsps$EMPTY_N,
       f_reset_rsps$ENQ,
       f_reset_rsps$FULL_N;

  // ports of submodule i_mmu_cache
  wire [578 : 0] i_mmu_cache$l1_to_l2_client_response_enq_x,
		 i_mmu_cache$l2_to_l1_server_response_first;
  wire [131 : 0] i_mmu_cache$ptw_client_response_put;
  wire [130 : 0] i_mmu_cache$mmio_client_request_get;
  wire [127 : 0] i_mmu_cache$pte_writeback_g_get,
		 i_mmu_cache$ptw_client_request_get;
  wire [68 : 0] i_mmu_cache$l1_to_l2_client_request_first;
  wire [65 : 0] i_mmu_cache$l2_to_l1_server_request_enq_x;
  wire [64 : 0] i_mmu_cache$mmio_client_response_put;
  wire [63 : 0] i_mmu_cache$addr,
		i_mmu_cache$ma_req_satp,
		i_mmu_cache$ma_req_va,
		i_mmu_cache$word64;
  wire [3 : 0] i_mmu_cache$exc_code;
  wire [1 : 0] i_mmu_cache$ma_req_priv;
  wire i_mmu_cache$EN_flush_server_request_put,
       i_mmu_cache$EN_flush_server_response_get,
       i_mmu_cache$EN_l1_to_l2_client_request_deq,
       i_mmu_cache$EN_l1_to_l2_client_response_enq,
       i_mmu_cache$EN_l2_to_l1_server_request_enq,
       i_mmu_cache$EN_l2_to_l1_server_response_deq,
       i_mmu_cache$EN_ma_req,
       i_mmu_cache$EN_mmio_client_request_get,
       i_mmu_cache$EN_mmio_client_response_put,
       i_mmu_cache$EN_pte_writeback_g_get,
       i_mmu_cache$EN_ptw_client_request_get,
       i_mmu_cache$EN_ptw_client_response_put,
       i_mmu_cache$EN_tlb_flush,
       i_mmu_cache$RDY_l1_to_l2_client_request_deq,
       i_mmu_cache$RDY_l1_to_l2_client_request_first,
       i_mmu_cache$RDY_l1_to_l2_client_response_enq,
       i_mmu_cache$RDY_l2_to_l1_server_request_enq,
       i_mmu_cache$RDY_l2_to_l1_server_response_deq,
       i_mmu_cache$RDY_l2_to_l1_server_response_first,
       i_mmu_cache$RDY_mmio_client_request_get,
       i_mmu_cache$RDY_mmio_client_response_put,
       i_mmu_cache$RDY_pte_writeback_g_get,
       i_mmu_cache$RDY_ptw_client_request_get,
       i_mmu_cache$RDY_ptw_client_response_put,
       i_mmu_cache$exc,
       i_mmu_cache$flush_server_request_put,
       i_mmu_cache$ma_req_mstatus_MXR,
       i_mmu_cache$ma_req_sstatus_SUM,
       i_mmu_cache$valid;

  // ports of submodule llc
  wire [655 : 0] llc$dma_memReq_enq_x;
  wire [640 : 0] llc$to_mem_toM_first;
  wire [583 : 0] llc$to_child_toC_first;
  wire [579 : 0] llc$to_child_rsFromC_enq_x;
  wire [527 : 0] llc$dma_respLd_first;
  wire [516 : 0] llc$to_mem_rsFromM_enq_x;
  wire [72 : 0] llc$to_child_rqFromC_enq_x;
  wire [15 : 0] llc$dma_respSt_first;
  wire [3 : 0] llc$perf_req_r;
  wire llc$EN_cRqStuck_get,
       llc$EN_dma_memReq_enq,
       llc$EN_dma_respLd_deq,
       llc$EN_dma_respSt_deq,
       llc$EN_perf_req,
       llc$EN_perf_resp,
       llc$EN_perf_setStatus,
       llc$EN_to_child_rqFromC_enq,
       llc$EN_to_child_rsFromC_enq,
       llc$EN_to_child_toC_deq,
       llc$EN_to_mem_rsFromM_enq,
       llc$EN_to_mem_toM_deq,
       llc$RDY_dma_memReq_enq,
       llc$RDY_dma_respLd_deq,
       llc$RDY_dma_respLd_first,
       llc$RDY_dma_respSt_deq,
       llc$RDY_dma_respSt_first,
       llc$RDY_to_child_rqFromC_enq,
       llc$RDY_to_child_rsFromC_enq,
       llc$RDY_to_child_toC_deq,
       llc$RDY_to_child_toC_first,
       llc$RDY_to_mem_rsFromM_enq,
       llc$RDY_to_mem_toM_deq,
       llc$RDY_to_mem_toM_first,
       llc$perf_setStatus_doStats;

  // ports of submodule llc_axi4_adapter_f_pending_reads
  wire [68 : 0] llc_axi4_adapter_f_pending_reads$D_IN,
		llc_axi4_adapter_f_pending_reads$D_OUT;
  wire llc_axi4_adapter_f_pending_reads$CLR,
       llc_axi4_adapter_f_pending_reads$DEQ,
       llc_axi4_adapter_f_pending_reads$EMPTY_N,
       llc_axi4_adapter_f_pending_reads$ENQ,
       llc_axi4_adapter_f_pending_reads$FULL_N;

  // ports of submodule llc_axi4_adapter_f_pending_writes
  wire [639 : 0] llc_axi4_adapter_f_pending_writes$D_IN;
  wire llc_axi4_adapter_f_pending_writes$CLR,
       llc_axi4_adapter_f_pending_writes$DEQ,
       llc_axi4_adapter_f_pending_writes$EMPTY_N,
       llc_axi4_adapter_f_pending_writes$ENQ,
       llc_axi4_adapter_f_pending_writes$FULL_N;

  // ports of submodule llc_dma_axi4_adapter_axi4_slave_xactor_f_rd_addr
  wire [108 : 0] llc_dma_axi4_adapter_axi4_slave_xactor_f_rd_addr$D_IN,
		 llc_dma_axi4_adapter_axi4_slave_xactor_f_rd_addr$D_OUT;
  wire llc_dma_axi4_adapter_axi4_slave_xactor_f_rd_addr$CLR,
       llc_dma_axi4_adapter_axi4_slave_xactor_f_rd_addr$DEQ,
       llc_dma_axi4_adapter_axi4_slave_xactor_f_rd_addr$EMPTY_N,
       llc_dma_axi4_adapter_axi4_slave_xactor_f_rd_addr$ENQ,
       llc_dma_axi4_adapter_axi4_slave_xactor_f_rd_addr$FULL_N;

  // ports of submodule llc_dma_axi4_adapter_axi4_slave_xactor_f_rd_data
  wire [530 : 0] llc_dma_axi4_adapter_axi4_slave_xactor_f_rd_data$D_IN,
		 llc_dma_axi4_adapter_axi4_slave_xactor_f_rd_data$D_OUT;
  wire llc_dma_axi4_adapter_axi4_slave_xactor_f_rd_data$CLR,
       llc_dma_axi4_adapter_axi4_slave_xactor_f_rd_data$DEQ,
       llc_dma_axi4_adapter_axi4_slave_xactor_f_rd_data$EMPTY_N,
       llc_dma_axi4_adapter_axi4_slave_xactor_f_rd_data$ENQ,
       llc_dma_axi4_adapter_axi4_slave_xactor_f_rd_data$FULL_N;

  // ports of submodule llc_dma_axi4_adapter_axi4_slave_xactor_f_wr_addr
  wire [108 : 0] llc_dma_axi4_adapter_axi4_slave_xactor_f_wr_addr$D_IN,
		 llc_dma_axi4_adapter_axi4_slave_xactor_f_wr_addr$D_OUT;
  wire llc_dma_axi4_adapter_axi4_slave_xactor_f_wr_addr$CLR,
       llc_dma_axi4_adapter_axi4_slave_xactor_f_wr_addr$DEQ,
       llc_dma_axi4_adapter_axi4_slave_xactor_f_wr_addr$EMPTY_N,
       llc_dma_axi4_adapter_axi4_slave_xactor_f_wr_addr$ENQ,
       llc_dma_axi4_adapter_axi4_slave_xactor_f_wr_addr$FULL_N;

  // ports of submodule llc_dma_axi4_adapter_axi4_slave_xactor_f_wr_data
  wire [576 : 0] llc_dma_axi4_adapter_axi4_slave_xactor_f_wr_data$D_IN,
		 llc_dma_axi4_adapter_axi4_slave_xactor_f_wr_data$D_OUT;
  wire llc_dma_axi4_adapter_axi4_slave_xactor_f_wr_data$CLR,
       llc_dma_axi4_adapter_axi4_slave_xactor_f_wr_data$DEQ,
       llc_dma_axi4_adapter_axi4_slave_xactor_f_wr_data$EMPTY_N,
       llc_dma_axi4_adapter_axi4_slave_xactor_f_wr_data$ENQ,
       llc_dma_axi4_adapter_axi4_slave_xactor_f_wr_data$FULL_N;

  // ports of submodule llc_dma_axi4_adapter_axi4_slave_xactor_f_wr_resp
  wire [17 : 0] llc_dma_axi4_adapter_axi4_slave_xactor_f_wr_resp$D_IN,
		llc_dma_axi4_adapter_axi4_slave_xactor_f_wr_resp$D_OUT;
  wire llc_dma_axi4_adapter_axi4_slave_xactor_f_wr_resp$CLR,
       llc_dma_axi4_adapter_axi4_slave_xactor_f_wr_resp$DEQ,
       llc_dma_axi4_adapter_axi4_slave_xactor_f_wr_resp$EMPTY_N,
       llc_dma_axi4_adapter_axi4_slave_xactor_f_wr_resp$ENQ,
       llc_dma_axi4_adapter_axi4_slave_xactor_f_wr_resp$FULL_N;

  // ports of submodule mmio_axi4_adapter
  wire [130 : 0] mmio_axi4_adapter$v_mmio_server_0_request_put,
		 mmio_axi4_adapter$v_mmio_server_1_request_put;
  wire [64 : 0] mmio_axi4_adapter$v_mmio_server_0_response_get,
		mmio_axi4_adapter$v_mmio_server_1_response_get;
  wire [63 : 0] mmio_axi4_adapter$mem_master_araddr,
		mmio_axi4_adapter$mem_master_awaddr,
		mmio_axi4_adapter$mem_master_rdata,
		mmio_axi4_adapter$mem_master_wdata;
  wire [15 : 0] mmio_axi4_adapter$mem_master_arid,
		mmio_axi4_adapter$mem_master_awid,
		mmio_axi4_adapter$mem_master_bid,
		mmio_axi4_adapter$mem_master_rid;
  wire [7 : 0] mmio_axi4_adapter$mem_master_arlen,
	       mmio_axi4_adapter$mem_master_awlen,
	       mmio_axi4_adapter$mem_master_wstrb;
  wire [3 : 0] mmio_axi4_adapter$mem_master_arcache,
	       mmio_axi4_adapter$mem_master_arqos,
	       mmio_axi4_adapter$mem_master_arregion,
	       mmio_axi4_adapter$mem_master_awcache,
	       mmio_axi4_adapter$mem_master_awqos,
	       mmio_axi4_adapter$mem_master_awregion;
  wire [2 : 0] mmio_axi4_adapter$mem_master_arprot,
	       mmio_axi4_adapter$mem_master_arsize,
	       mmio_axi4_adapter$mem_master_awprot,
	       mmio_axi4_adapter$mem_master_awsize;
  wire [1 : 0] mmio_axi4_adapter$mem_master_arburst,
	       mmio_axi4_adapter$mem_master_awburst,
	       mmio_axi4_adapter$mem_master_bresp,
	       mmio_axi4_adapter$mem_master_rresp;
  wire mmio_axi4_adapter$EN_v_mmio_server_0_request_put,
       mmio_axi4_adapter$EN_v_mmio_server_0_response_get,
       mmio_axi4_adapter$EN_v_mmio_server_1_request_put,
       mmio_axi4_adapter$EN_v_mmio_server_1_response_get,
       mmio_axi4_adapter$RDY_v_mmio_server_0_request_put,
       mmio_axi4_adapter$RDY_v_mmio_server_0_response_get,
       mmio_axi4_adapter$RDY_v_mmio_server_1_request_put,
       mmio_axi4_adapter$RDY_v_mmio_server_1_response_get,
       mmio_axi4_adapter$mem_master_arlock,
       mmio_axi4_adapter$mem_master_arready,
       mmio_axi4_adapter$mem_master_arvalid,
       mmio_axi4_adapter$mem_master_awlock,
       mmio_axi4_adapter$mem_master_awready,
       mmio_axi4_adapter$mem_master_awvalid,
       mmio_axi4_adapter$mem_master_bready,
       mmio_axi4_adapter$mem_master_bvalid,
       mmio_axi4_adapter$mem_master_rlast,
       mmio_axi4_adapter$mem_master_rready,
       mmio_axi4_adapter$mem_master_rvalid,
       mmio_axi4_adapter$mem_master_wlast,
       mmio_axi4_adapter$mem_master_wready,
       mmio_axi4_adapter$mem_master_wvalid;

  // ports of submodule propDstData_0_dummy2_0
  wire propDstData_0_dummy2_0$D_IN, propDstData_0_dummy2_0$EN;

  // ports of submodule propDstData_0_dummy2_1
  wire propDstData_0_dummy2_1$D_IN,
       propDstData_0_dummy2_1$EN,
       propDstData_0_dummy2_1$Q_OUT;

  // ports of submodule propDstData_1_0_dummy2_0
  wire propDstData_1_0_dummy2_0$D_IN, propDstData_1_0_dummy2_0$EN;

  // ports of submodule propDstData_1_0_dummy2_1
  wire propDstData_1_0_dummy2_1$D_IN,
       propDstData_1_0_dummy2_1$EN,
       propDstData_1_0_dummy2_1$Q_OUT;

  // ports of submodule propDstData_1_1_dummy2_0
  wire propDstData_1_1_dummy2_0$D_IN, propDstData_1_1_dummy2_0$EN;

  // ports of submodule propDstData_1_1_dummy2_1
  wire propDstData_1_1_dummy2_1$D_IN,
       propDstData_1_1_dummy2_1$EN,
       propDstData_1_1_dummy2_1$Q_OUT;

  // ports of submodule propDstData_1_dummy2_0
  wire propDstData_1_dummy2_0$D_IN, propDstData_1_dummy2_0$EN;

  // ports of submodule propDstData_1_dummy2_1
  wire propDstData_1_dummy2_1$D_IN,
       propDstData_1_dummy2_1$EN,
       propDstData_1_dummy2_1$Q_OUT;

  // ports of submodule propDstIdx_0_dummy2_0
  wire propDstIdx_0_dummy2_0$D_IN,
       propDstIdx_0_dummy2_0$EN,
       propDstIdx_0_dummy2_0$Q_OUT;

  // ports of submodule propDstIdx_0_dummy2_1
  wire propDstIdx_0_dummy2_1$D_IN,
       propDstIdx_0_dummy2_1$EN,
       propDstIdx_0_dummy2_1$Q_OUT;

  // ports of submodule propDstIdx_1_0_dummy2_0
  wire propDstIdx_1_0_dummy2_0$D_IN,
       propDstIdx_1_0_dummy2_0$EN,
       propDstIdx_1_0_dummy2_0$Q_OUT;

  // ports of submodule propDstIdx_1_0_dummy2_1
  wire propDstIdx_1_0_dummy2_1$D_IN,
       propDstIdx_1_0_dummy2_1$EN,
       propDstIdx_1_0_dummy2_1$Q_OUT;

  // ports of submodule propDstIdx_1_1_dummy2_0
  wire propDstIdx_1_1_dummy2_0$D_IN,
       propDstIdx_1_1_dummy2_0$EN,
       propDstIdx_1_1_dummy2_0$Q_OUT;

  // ports of submodule propDstIdx_1_1_dummy2_1
  wire propDstIdx_1_1_dummy2_1$D_IN,
       propDstIdx_1_1_dummy2_1$EN,
       propDstIdx_1_1_dummy2_1$Q_OUT;

  // ports of submodule propDstIdx_1_dummy2_0
  wire propDstIdx_1_dummy2_0$D_IN,
       propDstIdx_1_dummy2_0$EN,
       propDstIdx_1_dummy2_0$Q_OUT;

  // ports of submodule propDstIdx_1_dummy2_1
  wire propDstIdx_1_dummy2_1$D_IN,
       propDstIdx_1_dummy2_1$EN,
       propDstIdx_1_dummy2_1$Q_OUT;

  // ports of submodule soc_map
  wire [63 : 0] soc_map$m_is_IO_addr_addr,
		soc_map$m_is_mem_addr_addr,
		soc_map$m_is_near_mem_IO_addr_addr;

  // rule scheduling signals
  wire CAN_FIRE_RL_ClientServerRequest,
       CAN_FIRE_RL_ClientServerRequest_1,
       CAN_FIRE_RL_ClientServerRequest_2,
       CAN_FIRE_RL_ClientServerResponse,
       CAN_FIRE_RL_ClientServerResponse_1,
       CAN_FIRE_RL_ClientServerResponse_2,
       CAN_FIRE_RL_doEnq,
       CAN_FIRE_RL_doEnq_1,
       CAN_FIRE_RL_dstSelectSrc,
       CAN_FIRE_RL_dstSelectSrc_1,
       CAN_FIRE_RL_enqDst_0_canon,
       CAN_FIRE_RL_enqDst_1_0_canon,
       CAN_FIRE_RL_llc_axi4_adapter_rl_discard_write_rsp,
       CAN_FIRE_RL_llc_axi4_adapter_rl_handle_read_req,
       CAN_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps,
       CAN_FIRE_RL_llc_axi4_adapter_rl_handle_write_req,
       CAN_FIRE_RL_llc_dma_axi4_adapter_rl_rd_req,
       CAN_FIRE_RL_llc_dma_axi4_adapter_rl_rd_rsp,
       CAN_FIRE_RL_llc_dma_axi4_adapter_rl_wr_req,
       CAN_FIRE_RL_llc_dma_axi4_adapter_rl_wr_rsp,
       CAN_FIRE_RL_mkConnectionGetPut,
       CAN_FIRE_RL_propDstData_0_canon,
       CAN_FIRE_RL_propDstData_1_0_canon,
       CAN_FIRE_RL_propDstData_1_1_canon,
       CAN_FIRE_RL_propDstData_1_canon,
       CAN_FIRE_RL_propDstIdx_0_canon,
       CAN_FIRE_RL_propDstIdx_1_0_canon,
       CAN_FIRE_RL_propDstIdx_1_1_canon,
       CAN_FIRE_RL_propDstIdx_1_canon,
       CAN_FIRE_RL_rl_reset,
       CAN_FIRE_RL_rl_reset_complete,
       CAN_FIRE_RL_sendPRq,
       CAN_FIRE_RL_sendPRq_1,
       CAN_FIRE_RL_sendPRs,
       CAN_FIRE_RL_sendPRs_1,
       CAN_FIRE_RL_srcPropose,
       CAN_FIRE_RL_srcPropose_1,
       CAN_FIRE_RL_srcPropose_2,
       CAN_FIRE_RL_srcPropose_3,
       CAN_FIRE_dma_server_m_arvalid,
       CAN_FIRE_dma_server_m_awvalid,
       CAN_FIRE_dma_server_m_bready,
       CAN_FIRE_dma_server_m_rready,
       CAN_FIRE_dma_server_m_wvalid,
       CAN_FIRE_dmem_req,
       CAN_FIRE_imem_master_m_arready,
       CAN_FIRE_imem_master_m_awready,
       CAN_FIRE_imem_master_m_bvalid,
       CAN_FIRE_imem_master_m_rvalid,
       CAN_FIRE_imem_master_m_wready,
       CAN_FIRE_imem_req,
       CAN_FIRE_ma_ddr4_ready,
       CAN_FIRE_mem_master_m_arready,
       CAN_FIRE_mem_master_m_awready,
       CAN_FIRE_mem_master_m_bvalid,
       CAN_FIRE_mem_master_m_rvalid,
       CAN_FIRE_mem_master_m_wready,
       CAN_FIRE_server_fence_i_request_put,
       CAN_FIRE_server_fence_i_response_get,
       CAN_FIRE_server_fence_request_put,
       CAN_FIRE_server_fence_response_get,
       CAN_FIRE_server_reset_request_put,
       CAN_FIRE_server_reset_response_get,
       CAN_FIRE_sfence_vma_server_request_put,
       CAN_FIRE_sfence_vma_server_response_get,
       WILL_FIRE_RL_ClientServerRequest,
       WILL_FIRE_RL_ClientServerRequest_1,
       WILL_FIRE_RL_ClientServerRequest_2,
       WILL_FIRE_RL_ClientServerResponse,
       WILL_FIRE_RL_ClientServerResponse_1,
       WILL_FIRE_RL_ClientServerResponse_2,
       WILL_FIRE_RL_doEnq,
       WILL_FIRE_RL_doEnq_1,
       WILL_FIRE_RL_dstSelectSrc,
       WILL_FIRE_RL_dstSelectSrc_1,
       WILL_FIRE_RL_enqDst_0_canon,
       WILL_FIRE_RL_enqDst_1_0_canon,
       WILL_FIRE_RL_llc_axi4_adapter_rl_discard_write_rsp,
       WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req,
       WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps,
       WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req,
       WILL_FIRE_RL_llc_dma_axi4_adapter_rl_rd_req,
       WILL_FIRE_RL_llc_dma_axi4_adapter_rl_rd_rsp,
       WILL_FIRE_RL_llc_dma_axi4_adapter_rl_wr_req,
       WILL_FIRE_RL_llc_dma_axi4_adapter_rl_wr_rsp,
       WILL_FIRE_RL_mkConnectionGetPut,
       WILL_FIRE_RL_propDstData_0_canon,
       WILL_FIRE_RL_propDstData_1_0_canon,
       WILL_FIRE_RL_propDstData_1_1_canon,
       WILL_FIRE_RL_propDstData_1_canon,
       WILL_FIRE_RL_propDstIdx_0_canon,
       WILL_FIRE_RL_propDstIdx_1_0_canon,
       WILL_FIRE_RL_propDstIdx_1_1_canon,
       WILL_FIRE_RL_propDstIdx_1_canon,
       WILL_FIRE_RL_rl_reset,
       WILL_FIRE_RL_rl_reset_complete,
       WILL_FIRE_RL_sendPRq,
       WILL_FIRE_RL_sendPRq_1,
       WILL_FIRE_RL_sendPRs,
       WILL_FIRE_RL_sendPRs_1,
       WILL_FIRE_RL_srcPropose,
       WILL_FIRE_RL_srcPropose_1,
       WILL_FIRE_RL_srcPropose_2,
       WILL_FIRE_RL_srcPropose_3,
       WILL_FIRE_dma_server_m_arvalid,
       WILL_FIRE_dma_server_m_awvalid,
       WILL_FIRE_dma_server_m_bready,
       WILL_FIRE_dma_server_m_rready,
       WILL_FIRE_dma_server_m_wvalid,
       WILL_FIRE_dmem_req,
       WILL_FIRE_imem_master_m_arready,
       WILL_FIRE_imem_master_m_awready,
       WILL_FIRE_imem_master_m_bvalid,
       WILL_FIRE_imem_master_m_rvalid,
       WILL_FIRE_imem_master_m_wready,
       WILL_FIRE_imem_req,
       WILL_FIRE_ma_ddr4_ready,
       WILL_FIRE_mem_master_m_arready,
       WILL_FIRE_mem_master_m_awready,
       WILL_FIRE_mem_master_m_bvalid,
       WILL_FIRE_mem_master_m_rvalid,
       WILL_FIRE_mem_master_m_wready,
       WILL_FIRE_server_fence_i_request_put,
       WILL_FIRE_server_fence_i_response_get,
       WILL_FIRE_server_fence_request_put,
       WILL_FIRE_server_fence_response_get,
       WILL_FIRE_server_reset_request_put,
       WILL_FIRE_server_reset_response_get,
       WILL_FIRE_sfence_vma_server_request_put,
       WILL_FIRE_sfence_vma_server_response_get;

  // inputs to muxes for submodule ports
  wire [655 : 0] MUX_llc$dma_memReq_enq_1__VAL_1,
		 MUX_llc$dma_memReq_enq_1__VAL_2;
  wire MUX_rg_state$write_1__SEL_3;

  // declarations used by system tasks
  // synopsys translate_off
  reg [31 : 0] v__h77688;
  reg [31 : 0] v__h77791;
  reg [31 : 0] v__h21259;
  reg [31 : 0] v__h79349;
  reg [31 : 0] v__h39273;
  reg [31 : 0] v__h21253;
  reg [31 : 0] v__h39267;
  reg [31 : 0] v__h77682;
  reg [31 : 0] v__h77785;
  reg [31 : 0] v__h79343;
  // synopsys translate_on

  // remaining internal signals
  reg [63 : 0] CASE_x8218_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q11,
	       CASE_x8218_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q12,
	       CASE_x8218_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q13,
	       CASE_x8218_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q14,
	       CASE_x8218_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q15,
	       CASE_x8218_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q16,
	       CASE_x8218_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q17,
	       CASE_x8218_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q18,
	       CASE_x8218_0_n__read_addr8396_1_n__read_addr84_ETC__q21,
	       CASE_x9280_0_n__read_addr9462_1_n__read_addr95_ETC__q8,
	       data64__h22868;
  reg [7 : 0] strb8__h22869;
  reg [2 : 0] x__h49594;
  reg [1 : 0] CASE_d_mmu_cachel1_to_l2_client_request_first_ETC__q3,
	      CASE_d_mmu_cachel1_to_l2_client_request_first_ETC__q4,
	      CASE_d_mmu_cachel2_to_l1_server_response_firs_ETC__q10,
	      CASE_i_mmu_cachel1_to_l2_client_request_first_ETC__q1,
	      CASE_i_mmu_cachel1_to_l2_client_request_first_ETC__q2,
	      CASE_i_mmu_cachel2_to_l1_server_response_firs_ETC__q9,
	      CASE_llcto_child_toC_first_BITS_2_TO_1_0_llc_ETC__q22,
	      CASE_llcto_child_toC_first_BITS_518_TO_517_0__ETC__q23,
	      CASE_x8218_0_IF_propDstData_1_0_dummy2_1Q_OUT_ETC__q19,
	      CASE_x9280_0_IF_propDstData_0_dummy2_1_read__0_ETC__q6,
	      CASE_x9280_0_IF_propDstData_0_dummy2_1_read__0_ETC__q7;
  reg CASE_x8218_0_NOT_propDstData_1_0_dummy2_1_read_ETC__q20,
      CASE_x9280_0_propDstData_0_dummy2_1_read__04_A_ETC__q5,
      SEL_ARR_propDstIdx_0_dummy2_1_read__30_AND_IF__ETC___d297,
      SEL_ARR_propDstIdx_1_0_dummy2_1_read__30_AND_I_ETC___d585,
      x__h49601,
      x__h70634;
  wire [579 : 0] IF_enqDst_1_0_lat_1_whas__75_THEN_enqDst_1_0_l_ETC___d522;
  wire [515 : 0] SEL_ARR_IF_propDstData_1_0_dummy2_1_read__92_T_ETC___d684;
  wire [513 : 0] IF_enqDst_1_0_lat_1_whas__75_THEN_enqDst_1_0_l_ETC___d521;
  wire [511 : 0] IF_enqDst_1_0_lat_0_whas__78_THEN_enqDst_1_0_l_ETC___d513,
		 SEL_ARR_IF_propDstData_1_0_lat_0_whas__02_THEN_ETC___d677,
		 new_cline__h21399;
  wire [383 : 0] SEL_ARR_IF_propDstData_1_0_lat_0_whas__02_THEN_ETC___d660;
  wire [255 : 0] SEL_ARR_IF_propDstData_1_0_lat_0_whas__02_THEN_ETC___d643;
  wire [127 : 0] SEL_ARR_IF_propDstData_1_0_lat_0_whas__02_THEN_ETC___d626;
  wire [63 : 0] IF_enqDst_1_0_lat_0_whas__78_THEN_enqDst_1_0_l_ETC___d493,
		IF_propDstData_1_0_lat_0_whas__02_THEN_propDst_ETC___d407,
		IF_propDstData_1_1_lat_0_whas__40_THEN_propDst_ETC___d445,
		mem_req_rd_addr_araddr__h20827,
		mem_req_wr_addr_awaddr__h22953,
		n__read_addr__h49462,
		n__read_addr__h49547,
		n__read_addr__h68396,
		n__read_addr__h68475;
  wire [8 : 0] SEL_ARR_IF_propDstData_0_dummy2_1_read__04_THE_ETC___d368;
  wire [5 : 0] x__h20877, x__h22987;
  wire [4 : 0] SEL_ARR_propDstData_0_dummy2_1_read__04_AND_IF_ETC___d367;
  wire [3 : 0] b__h20709;
  wire [2 : 0] n__read_id__h49466, n__read_id__h49551;
  wire [1 : 0] IF_enqDst_1_0_lat_0_whas__78_THEN_enqDst_1_0_l_ETC___d498,
	       IF_propDstData_0_dummy2_1_read__04_THEN_IF_pro_ETC___d320,
	       IF_propDstData_0_dummy2_1_read__04_THEN_IF_pro_ETC___d330,
	       IF_propDstData_1_0_lat_0_whas__02_THEN_propDst_ETC___d412,
	       IF_propDstData_1_1_lat_0_whas__40_THEN_propDst_ETC___d450,
	       IF_propDstData_1_dummy2_1_read__09_THEN_IF_pro_ETC___d324,
	       IF_propDstData_1_dummy2_1_read__09_THEN_IF_pro_ETC___d334;
  wire IF_NOT_propDstIdx_0_dummy2_1_read__30_31_OR_IF_ETC___d301,
       IF_NOT_propDstIdx_1_0_dummy2_1_read__30_31_OR__ETC___d589,
       IF_SEL_ARR_propDstIdx_0_dummy2_1_read__30_AND__ETC___d373,
       IF_SEL_ARR_propDstIdx_1_0_dummy2_1_read__30_AN_ETC___d689,
       IF_enqDst_0_lat_0_whas__06_THEN_enqDst_0_lat_0_ETC___d211,
       IF_enqDst_1_0_lat_0_whas__78_THEN_enqDst_1_0_l_ETC___d483,
       IF_enqDst_1_0_lat_0_whas__78_THEN_enqDst_1_0_l_ETC___d503,
       IF_enqDst_1_0_lat_0_whas__78_THEN_enqDst_1_0_l_ETC___d519,
       IF_propDstData_1_0_lat_0_whas__02_THEN_propDst_ETC___d433,
       IF_propDstData_1_1_lat_0_whas__40_THEN_propDst_ETC___d471,
       IF_propDstIdx_0_lat_0_whas__77_THEN_propDstIdx_ETC___d180,
       IF_propDstIdx_1_0_lat_0_whas__87_THEN_propDstI_ETC___d390,
       IF_propDstIdx_1_1_lat_0_whas__94_THEN_propDstI_ETC___d397,
       IF_propDstIdx_1_lat_0_whas__84_THEN_propDstIdx_ETC___d187,
       NOT_cfg_verbosity_read__70_ULE_1_71___d772,
       NOT_enqDst_0_dummy2_0_read__87_88_OR_NOT_enqDs_ETC___d303,
       NOT_enqDst_1_0_dummy2_0_read__75_76_OR_NOT_enq_ETC___d591,
       NOT_llc_axi4_adapter_master_xactor_crg_wr_addr_ETC___d114,
       NOT_propDstData_1_0_dummy2_1_read__92_03_OR_IF_ETC___d604,
       NOT_propDstData_1_1_dummy2_1_read__94_05_OR_IF_ETC___d606,
       NOT_propDstIdx_0_dummy2_1_read__30_31_OR_IF_pr_ETC___d300,
       NOT_propDstIdx_1_0_dummy2_1_read__30_31_OR_IF__ETC___d588,
       NOT_propDstIdx_1_1_dummy2_1_read__55_56_OR_IF__ETC___d695,
       NOT_propDstIdx_1_dummy2_1_read__61_62_OR_IF_pr_ETC___d379,
       n__read_child__h49467,
       n__read_child__h49552,
       n__read_child__h68399,
       n__read_child__h68478,
       propDstData_0_dummy2_1_read__04_AND_IF_propDst_ETC___d340,
       propDstData_1_dummy2_1_read__09_AND_IF_propDst_ETC___d344,
       x__h49280,
       x__h62982,
       x__h68218;

  // action method server_reset_request_put
  assign RDY_server_reset_request_put = CAN_FIRE_server_reset_request_put ;
  assign CAN_FIRE_server_reset_request_put = rg_state == 2'd2 ;
  assign WILL_FIRE_server_reset_request_put = EN_server_reset_request_put ;

  // action method server_reset_response_get
  assign RDY_server_reset_response_get = f_reset_rsps$EMPTY_N ;
  assign CAN_FIRE_server_reset_response_get = f_reset_rsps$EMPTY_N ;
  assign WILL_FIRE_server_reset_response_get = EN_server_reset_response_get ;

  // action method imem_req
  assign CAN_FIRE_imem_req = 1'd1 ;
  assign WILL_FIRE_imem_req = EN_imem_req ;

  // value method imem_valid
  assign imem_valid = i_mmu_cache$valid ;

  // value method imem_is_i32_not_i16
  assign imem_is_i32_not_i16 = 1'd1 ;

  // value method imem_pc
  assign imem_pc = i_mmu_cache$addr ;

  // value method imem_instr
  assign imem_instr = i_mmu_cache$word64[31:0] ;

  // value method imem_exc
  assign imem_exc = i_mmu_cache$exc ;

  // value method imem_exc_code
  assign imem_exc_code = i_mmu_cache$exc_code ;

  // value method imem_tval
  assign imem_tval = i_mmu_cache$addr ;

  // value method imem_master_m_awvalid
  assign imem_master_awvalid = mmio_axi4_adapter$mem_master_awvalid ;

  // value method imem_master_m_awid
  assign imem_master_awid = mmio_axi4_adapter$mem_master_awid ;

  // value method imem_master_m_awaddr
  assign imem_master_awaddr = mmio_axi4_adapter$mem_master_awaddr ;

  // value method imem_master_m_awlen
  assign imem_master_awlen = mmio_axi4_adapter$mem_master_awlen ;

  // value method imem_master_m_awsize
  assign imem_master_awsize = mmio_axi4_adapter$mem_master_awsize ;

  // value method imem_master_m_awburst
  assign imem_master_awburst = mmio_axi4_adapter$mem_master_awburst ;

  // value method imem_master_m_awlock
  assign imem_master_awlock = mmio_axi4_adapter$mem_master_awlock ;

  // value method imem_master_m_awcache
  assign imem_master_awcache = mmio_axi4_adapter$mem_master_awcache ;

  // value method imem_master_m_awprot
  assign imem_master_awprot = mmio_axi4_adapter$mem_master_awprot ;

  // value method imem_master_m_awqos
  assign imem_master_awqos = mmio_axi4_adapter$mem_master_awqos ;

  // value method imem_master_m_awregion
  assign imem_master_awregion = mmio_axi4_adapter$mem_master_awregion ;

  // action method imem_master_m_awready
  assign CAN_FIRE_imem_master_m_awready = 1'd1 ;
  assign WILL_FIRE_imem_master_m_awready = 1'd1 ;

  // value method imem_master_m_wvalid
  assign imem_master_wvalid = mmio_axi4_adapter$mem_master_wvalid ;

  // value method imem_master_m_wdata
  assign imem_master_wdata = mmio_axi4_adapter$mem_master_wdata ;

  // value method imem_master_m_wstrb
  assign imem_master_wstrb = mmio_axi4_adapter$mem_master_wstrb ;

  // value method imem_master_m_wlast
  assign imem_master_wlast = mmio_axi4_adapter$mem_master_wlast ;

  // action method imem_master_m_wready
  assign CAN_FIRE_imem_master_m_wready = 1'd1 ;
  assign WILL_FIRE_imem_master_m_wready = 1'd1 ;

  // action method imem_master_m_bvalid
  assign CAN_FIRE_imem_master_m_bvalid = 1'd1 ;
  assign WILL_FIRE_imem_master_m_bvalid = 1'd1 ;

  // value method imem_master_m_bready
  assign imem_master_bready = mmio_axi4_adapter$mem_master_bready ;

  // value method imem_master_m_arvalid
  assign imem_master_arvalid = mmio_axi4_adapter$mem_master_arvalid ;

  // value method imem_master_m_arid
  assign imem_master_arid = mmio_axi4_adapter$mem_master_arid ;

  // value method imem_master_m_araddr
  assign imem_master_araddr = mmio_axi4_adapter$mem_master_araddr ;

  // value method imem_master_m_arlen
  assign imem_master_arlen = mmio_axi4_adapter$mem_master_arlen ;

  // value method imem_master_m_arsize
  assign imem_master_arsize = mmio_axi4_adapter$mem_master_arsize ;

  // value method imem_master_m_arburst
  assign imem_master_arburst = mmio_axi4_adapter$mem_master_arburst ;

  // value method imem_master_m_arlock
  assign imem_master_arlock = mmio_axi4_adapter$mem_master_arlock ;

  // value method imem_master_m_arcache
  assign imem_master_arcache = mmio_axi4_adapter$mem_master_arcache ;

  // value method imem_master_m_arprot
  assign imem_master_arprot = mmio_axi4_adapter$mem_master_arprot ;

  // value method imem_master_m_arqos
  assign imem_master_arqos = mmio_axi4_adapter$mem_master_arqos ;

  // value method imem_master_m_arregion
  assign imem_master_arregion = mmio_axi4_adapter$mem_master_arregion ;

  // action method imem_master_m_arready
  assign CAN_FIRE_imem_master_m_arready = 1'd1 ;
  assign WILL_FIRE_imem_master_m_arready = 1'd1 ;

  // action method imem_master_m_rvalid
  assign CAN_FIRE_imem_master_m_rvalid = 1'd1 ;
  assign WILL_FIRE_imem_master_m_rvalid = 1'd1 ;

  // value method imem_master_m_rready
  assign imem_master_rready = mmio_axi4_adapter$mem_master_rready ;

  // action method dmem_req
  assign CAN_FIRE_dmem_req = 1'd1 ;
  assign WILL_FIRE_dmem_req = EN_dmem_req ;

  // value method dmem_valid
  assign dmem_valid = d_mmu_cache$valid ;

  // value method dmem_word64
  assign dmem_word64 = d_mmu_cache$word64 ;

  // value method dmem_st_amo_val
  assign dmem_st_amo_val = d_mmu_cache$st_amo_val ;

  // value method dmem_exc
  assign dmem_exc = d_mmu_cache$exc ;

  // value method dmem_exc_code
  assign dmem_exc_code = d_mmu_cache$exc_code ;

  // value method mem_master_m_awvalid
  assign mem_master_awvalid =
	     llc_axi4_adapter_master_xactor_crg_wr_addr_full ;

  // value method mem_master_m_awid
  assign mem_master_awid = llc_axi4_adapter_master_xactor_rg_wr_addr[108:93] ;

  // value method mem_master_m_awaddr
  assign mem_master_awaddr =
	     llc_axi4_adapter_master_xactor_rg_wr_addr[92:29] ;

  // value method mem_master_m_awlen
  assign mem_master_awlen = llc_axi4_adapter_master_xactor_rg_wr_addr[28:21] ;

  // value method mem_master_m_awsize
  assign mem_master_awsize =
	     llc_axi4_adapter_master_xactor_rg_wr_addr[20:18] ;

  // value method mem_master_m_awburst
  assign mem_master_awburst =
	     llc_axi4_adapter_master_xactor_rg_wr_addr[17:16] ;

  // value method mem_master_m_awlock
  assign mem_master_awlock = llc_axi4_adapter_master_xactor_rg_wr_addr[15] ;

  // value method mem_master_m_awcache
  assign mem_master_awcache =
	     llc_axi4_adapter_master_xactor_rg_wr_addr[14:11] ;

  // value method mem_master_m_awprot
  assign mem_master_awprot = llc_axi4_adapter_master_xactor_rg_wr_addr[10:8] ;

  // value method mem_master_m_awqos
  assign mem_master_awqos = llc_axi4_adapter_master_xactor_rg_wr_addr[7:4] ;

  // value method mem_master_m_awregion
  assign mem_master_awregion =
	     llc_axi4_adapter_master_xactor_rg_wr_addr[3:0] ;

  // action method mem_master_m_awready
  assign CAN_FIRE_mem_master_m_awready = 1'd1 ;
  assign WILL_FIRE_mem_master_m_awready = 1'd1 ;

  // value method mem_master_m_wvalid
  assign mem_master_wvalid = llc_axi4_adapter_master_xactor_crg_wr_data_full ;

  // value method mem_master_m_wdata
  assign mem_master_wdata = llc_axi4_adapter_master_xactor_rg_wr_data[72:9] ;

  // value method mem_master_m_wstrb
  assign mem_master_wstrb = llc_axi4_adapter_master_xactor_rg_wr_data[8:1] ;

  // value method mem_master_m_wlast
  assign mem_master_wlast = llc_axi4_adapter_master_xactor_rg_wr_data[0] ;

  // action method mem_master_m_wready
  assign CAN_FIRE_mem_master_m_wready = 1'd1 ;
  assign WILL_FIRE_mem_master_m_wready = 1'd1 ;

  // action method mem_master_m_bvalid
  assign CAN_FIRE_mem_master_m_bvalid = 1'd1 ;
  assign WILL_FIRE_mem_master_m_bvalid = 1'd1 ;

  // value method mem_master_m_bready
  assign mem_master_bready =
	     !llc_axi4_adapter_master_xactor_crg_wr_resp_full$port2__read ;

  // value method mem_master_m_arvalid
  assign mem_master_arvalid =
	     llc_axi4_adapter_master_xactor_crg_rd_addr_full ;

  // value method mem_master_m_arid
  assign mem_master_arid = llc_axi4_adapter_master_xactor_rg_rd_addr[108:93] ;

  // value method mem_master_m_araddr
  assign mem_master_araddr =
	     llc_axi4_adapter_master_xactor_rg_rd_addr[92:29] ;

  // value method mem_master_m_arlen
  assign mem_master_arlen = llc_axi4_adapter_master_xactor_rg_rd_addr[28:21] ;

  // value method mem_master_m_arsize
  assign mem_master_arsize =
	     llc_axi4_adapter_master_xactor_rg_rd_addr[20:18] ;

  // value method mem_master_m_arburst
  assign mem_master_arburst =
	     llc_axi4_adapter_master_xactor_rg_rd_addr[17:16] ;

  // value method mem_master_m_arlock
  assign mem_master_arlock = llc_axi4_adapter_master_xactor_rg_rd_addr[15] ;

  // value method mem_master_m_arcache
  assign mem_master_arcache =
	     llc_axi4_adapter_master_xactor_rg_rd_addr[14:11] ;

  // value method mem_master_m_arprot
  assign mem_master_arprot = llc_axi4_adapter_master_xactor_rg_rd_addr[10:8] ;

  // value method mem_master_m_arqos
  assign mem_master_arqos = llc_axi4_adapter_master_xactor_rg_rd_addr[7:4] ;

  // value method mem_master_m_arregion
  assign mem_master_arregion =
	     llc_axi4_adapter_master_xactor_rg_rd_addr[3:0] ;

  // action method mem_master_m_arready
  assign CAN_FIRE_mem_master_m_arready = 1'd1 ;
  assign WILL_FIRE_mem_master_m_arready = 1'd1 ;

  // action method mem_master_m_rvalid
  assign CAN_FIRE_mem_master_m_rvalid = 1'd1 ;
  assign WILL_FIRE_mem_master_m_rvalid = 1'd1 ;

  // value method mem_master_m_rready
  assign mem_master_rready =
	     !llc_axi4_adapter_master_xactor_crg_rd_data_full$port2__read ;

  // action method server_fence_i_request_put
  assign RDY_server_fence_i_request_put = 1'd1 ;
  assign CAN_FIRE_server_fence_i_request_put = 1'd1 ;
  assign WILL_FIRE_server_fence_i_request_put =
	     EN_server_fence_i_request_put ;

  // action method server_fence_i_response_get
  assign RDY_server_fence_i_response_get = 1'd1 ;
  assign CAN_FIRE_server_fence_i_response_get = 1'd1 ;
  assign WILL_FIRE_server_fence_i_response_get =
	     EN_server_fence_i_response_get ;

  // action method server_fence_request_put
  assign RDY_server_fence_request_put = 1'd1 ;
  assign CAN_FIRE_server_fence_request_put = 1'd1 ;
  assign WILL_FIRE_server_fence_request_put = EN_server_fence_request_put ;

  // action method server_fence_response_get
  assign RDY_server_fence_response_get = 1'd1 ;
  assign CAN_FIRE_server_fence_response_get = 1'd1 ;
  assign WILL_FIRE_server_fence_response_get = EN_server_fence_response_get ;

  // action method sfence_vma_server_request_put
  assign RDY_sfence_vma_server_request_put = 1'd1 ;
  assign CAN_FIRE_sfence_vma_server_request_put = 1'd1 ;
  assign WILL_FIRE_sfence_vma_server_request_put =
	     EN_sfence_vma_server_request_put ;

  // action method sfence_vma_server_response_get
  assign RDY_sfence_vma_server_response_get = 1'd1 ;
  assign CAN_FIRE_sfence_vma_server_response_get = 1'd1 ;
  assign WILL_FIRE_sfence_vma_server_response_get =
	     EN_sfence_vma_server_response_get ;

  // action method dma_server_m_awvalid
  assign CAN_FIRE_dma_server_m_awvalid = 1'd1 ;
  assign WILL_FIRE_dma_server_m_awvalid = 1'd1 ;

  // value method dma_server_m_awready
  assign dma_server_awready =
	     llc_dma_axi4_adapter_axi4_slave_xactor_f_wr_addr$FULL_N ;

  // action method dma_server_m_wvalid
  assign CAN_FIRE_dma_server_m_wvalid = 1'd1 ;
  assign WILL_FIRE_dma_server_m_wvalid = 1'd1 ;

  // value method dma_server_m_wready
  assign dma_server_wready =
	     llc_dma_axi4_adapter_axi4_slave_xactor_f_wr_data$FULL_N ;

  // value method dma_server_m_bvalid
  assign dma_server_bvalid =
	     llc_dma_axi4_adapter_axi4_slave_xactor_f_wr_resp$EMPTY_N ;

  // value method dma_server_m_bid
  assign dma_server_bid =
	     llc_dma_axi4_adapter_axi4_slave_xactor_f_wr_resp$D_OUT[17:2] ;

  // value method dma_server_m_bresp
  assign dma_server_bresp =
	     llc_dma_axi4_adapter_axi4_slave_xactor_f_wr_resp$D_OUT[1:0] ;

  // action method dma_server_m_bready
  assign CAN_FIRE_dma_server_m_bready = 1'd1 ;
  assign WILL_FIRE_dma_server_m_bready = 1'd1 ;

  // action method dma_server_m_arvalid
  assign CAN_FIRE_dma_server_m_arvalid = 1'd1 ;
  assign WILL_FIRE_dma_server_m_arvalid = 1'd1 ;

  // value method dma_server_m_arready
  assign dma_server_arready =
	     llc_dma_axi4_adapter_axi4_slave_xactor_f_rd_addr$FULL_N ;

  // value method dma_server_m_rvalid
  assign dma_server_rvalid =
	     llc_dma_axi4_adapter_axi4_slave_xactor_f_rd_data$EMPTY_N ;

  // value method dma_server_m_rid
  assign dma_server_rid =
	     llc_dma_axi4_adapter_axi4_slave_xactor_f_rd_data$D_OUT[530:515] ;

  // value method dma_server_m_rdata
  assign dma_server_rdata =
	     llc_dma_axi4_adapter_axi4_slave_xactor_f_rd_data$D_OUT[514:3] ;

  // value method dma_server_m_rresp
  assign dma_server_rresp =
	     llc_dma_axi4_adapter_axi4_slave_xactor_f_rd_data$D_OUT[2:1] ;

  // value method dma_server_m_rlast
  assign dma_server_rlast =
	     llc_dma_axi4_adapter_axi4_slave_xactor_f_rd_data$D_OUT[0] ;

  // action method dma_server_m_rready
  assign CAN_FIRE_dma_server_m_rready = 1'd1 ;
  assign WILL_FIRE_dma_server_m_rready = 1'd1 ;

  // action method ma_ddr4_ready
  assign RDY_ma_ddr4_ready = 1'd1 ;
  assign CAN_FIRE_ma_ddr4_ready = 1'd1 ;
  assign WILL_FIRE_ma_ddr4_ready = EN_ma_ddr4_ready ;

  // value method mv_status
  assign mv_status = llc_axi4_adapter_rg_AXI4_error ? 8'd1 : 8'd0 ;

  // submodule d_mmu_cache
  mkD_MMU_Cache d_mmu_cache(.CLK(CLK),
			    .RST_N(RST_N),
			    .flush_server_request_put(d_mmu_cache$flush_server_request_put),
			    .imem_pte_writeback_p_put(d_mmu_cache$imem_pte_writeback_p_put),
			    .imem_ptw_server_request_put(d_mmu_cache$imem_ptw_server_request_put),
			    .l1_to_l2_client_response_enq_x(d_mmu_cache$l1_to_l2_client_response_enq_x),
			    .l2_to_l1_server_request_enq_x(d_mmu_cache$l2_to_l1_server_request_enq_x),
			    .ma_req_amo_funct7(d_mmu_cache$ma_req_amo_funct7),
			    .ma_req_f3(d_mmu_cache$ma_req_f3),
			    .ma_req_mstatus_MXR(d_mmu_cache$ma_req_mstatus_MXR),
			    .ma_req_op(d_mmu_cache$ma_req_op),
			    .ma_req_priv(d_mmu_cache$ma_req_priv),
			    .ma_req_satp(d_mmu_cache$ma_req_satp),
			    .ma_req_sstatus_SUM(d_mmu_cache$ma_req_sstatus_SUM),
			    .ma_req_st_value(d_mmu_cache$ma_req_st_value),
			    .ma_req_va(d_mmu_cache$ma_req_va),
			    .mmio_client_response_put(d_mmu_cache$mmio_client_response_put),
			    .EN_ma_req(d_mmu_cache$EN_ma_req),
			    .EN_flush_server_request_put(d_mmu_cache$EN_flush_server_request_put),
			    .EN_flush_server_response_get(d_mmu_cache$EN_flush_server_response_get),
			    .EN_tlb_flush(d_mmu_cache$EN_tlb_flush),
			    .EN_imem_ptw_server_request_put(d_mmu_cache$EN_imem_ptw_server_request_put),
			    .EN_imem_ptw_server_response_get(d_mmu_cache$EN_imem_ptw_server_response_get),
			    .EN_imem_pte_writeback_p_put(d_mmu_cache$EN_imem_pte_writeback_p_put),
			    .EN_l1_to_l2_client_request_deq(d_mmu_cache$EN_l1_to_l2_client_request_deq),
			    .EN_l1_to_l2_client_response_enq(d_mmu_cache$EN_l1_to_l2_client_response_enq),
			    .EN_l2_to_l1_server_request_enq(d_mmu_cache$EN_l2_to_l1_server_request_enq),
			    .EN_l2_to_l1_server_response_deq(d_mmu_cache$EN_l2_to_l1_server_response_deq),
			    .EN_mmio_client_request_get(d_mmu_cache$EN_mmio_client_request_get),
			    .EN_mmio_client_response_put(d_mmu_cache$EN_mmio_client_response_put),
			    .valid(d_mmu_cache$valid),
			    .addr(),
			    .word64(d_mmu_cache$word64),
			    .st_amo_val(d_mmu_cache$st_amo_val),
			    .exc(d_mmu_cache$exc),
			    .exc_code(d_mmu_cache$exc_code),
			    .RDY_flush_server_request_put(),
			    .RDY_flush_server_response_get(),
			    .RDY_tlb_flush(),
			    .RDY_imem_ptw_server_request_put(d_mmu_cache$RDY_imem_ptw_server_request_put),
			    .imem_ptw_server_response_get(d_mmu_cache$imem_ptw_server_response_get),
			    .RDY_imem_ptw_server_response_get(d_mmu_cache$RDY_imem_ptw_server_response_get),
			    .RDY_imem_pte_writeback_p_put(d_mmu_cache$RDY_imem_pte_writeback_p_put),
			    .l1_to_l2_client_request_first(d_mmu_cache$l1_to_l2_client_request_first),
			    .RDY_l1_to_l2_client_request_first(d_mmu_cache$RDY_l1_to_l2_client_request_first),
			    .RDY_l1_to_l2_client_request_deq(d_mmu_cache$RDY_l1_to_l2_client_request_deq),
			    .l1_to_l2_client_request_notEmpty(),
			    .RDY_l1_to_l2_client_request_notEmpty(),
			    .RDY_l1_to_l2_client_response_enq(d_mmu_cache$RDY_l1_to_l2_client_response_enq),
			    .l1_to_l2_client_response_notFull(),
			    .RDY_l1_to_l2_client_response_notFull(),
			    .RDY_l2_to_l1_server_request_enq(d_mmu_cache$RDY_l2_to_l1_server_request_enq),
			    .l2_to_l1_server_request_notFull(),
			    .RDY_l2_to_l1_server_request_notFull(),
			    .l2_to_l1_server_response_first(d_mmu_cache$l2_to_l1_server_response_first),
			    .RDY_l2_to_l1_server_response_first(d_mmu_cache$RDY_l2_to_l1_server_response_first),
			    .RDY_l2_to_l1_server_response_deq(d_mmu_cache$RDY_l2_to_l1_server_response_deq),
			    .l2_to_l1_server_response_notEmpty(),
			    .RDY_l2_to_l1_server_response_notEmpty(),
			    .mmio_client_request_get(d_mmu_cache$mmio_client_request_get),
			    .RDY_mmio_client_request_get(d_mmu_cache$RDY_mmio_client_request_get),
			    .RDY_mmio_client_response_put(d_mmu_cache$RDY_mmio_client_response_put));

  // submodule enqDst_0_dummy2_0
  RevertReg #(.width(32'd1), .init(1'd1)) enqDst_0_dummy2_0(.CLK(CLK),
							    .D_IN(enqDst_0_dummy2_0$D_IN),
							    .EN(enqDst_0_dummy2_0$EN),
							    .Q_OUT(enqDst_0_dummy2_0$Q_OUT));

  // submodule enqDst_0_dummy2_1
  RevertReg #(.width(32'd1), .init(1'd1)) enqDst_0_dummy2_1(.CLK(CLK),
							    .D_IN(enqDst_0_dummy2_1$D_IN),
							    .EN(enqDst_0_dummy2_1$EN),
							    .Q_OUT(enqDst_0_dummy2_1$Q_OUT));

  // submodule enqDst_1_0_dummy2_0
  RevertReg #(.width(32'd1), .init(1'd1)) enqDst_1_0_dummy2_0(.CLK(CLK),
							      .D_IN(enqDst_1_0_dummy2_0$D_IN),
							      .EN(enqDst_1_0_dummy2_0$EN),
							      .Q_OUT(enqDst_1_0_dummy2_0$Q_OUT));

  // submodule enqDst_1_0_dummy2_1
  RevertReg #(.width(32'd1), .init(1'd1)) enqDst_1_0_dummy2_1(.CLK(CLK),
							      .D_IN(enqDst_1_0_dummy2_1$D_IN),
							      .EN(enqDst_1_0_dummy2_1$EN),
							      .Q_OUT(enqDst_1_0_dummy2_1$Q_OUT));

  // submodule f_reset_rsps
  FIFO20 #(.guarded(32'd1)) f_reset_rsps(.RST(RST_N),
					 .CLK(CLK),
					 .ENQ(f_reset_rsps$ENQ),
					 .DEQ(f_reset_rsps$DEQ),
					 .CLR(f_reset_rsps$CLR),
					 .FULL_N(f_reset_rsps$FULL_N),
					 .EMPTY_N(f_reset_rsps$EMPTY_N));

  // submodule i_mmu_cache
  mkI_MMU_Cache i_mmu_cache(.CLK(CLK),
			    .RST_N(RST_N),
			    .flush_server_request_put(i_mmu_cache$flush_server_request_put),
			    .l1_to_l2_client_response_enq_x(i_mmu_cache$l1_to_l2_client_response_enq_x),
			    .l2_to_l1_server_request_enq_x(i_mmu_cache$l2_to_l1_server_request_enq_x),
			    .ma_req_mstatus_MXR(i_mmu_cache$ma_req_mstatus_MXR),
			    .ma_req_priv(i_mmu_cache$ma_req_priv),
			    .ma_req_satp(i_mmu_cache$ma_req_satp),
			    .ma_req_sstatus_SUM(i_mmu_cache$ma_req_sstatus_SUM),
			    .ma_req_va(i_mmu_cache$ma_req_va),
			    .mmio_client_response_put(i_mmu_cache$mmio_client_response_put),
			    .ptw_client_response_put(i_mmu_cache$ptw_client_response_put),
			    .EN_ma_req(i_mmu_cache$EN_ma_req),
			    .EN_flush_server_request_put(i_mmu_cache$EN_flush_server_request_put),
			    .EN_flush_server_response_get(i_mmu_cache$EN_flush_server_response_get),
			    .EN_tlb_flush(i_mmu_cache$EN_tlb_flush),
			    .EN_ptw_client_request_get(i_mmu_cache$EN_ptw_client_request_get),
			    .EN_ptw_client_response_put(i_mmu_cache$EN_ptw_client_response_put),
			    .EN_pte_writeback_g_get(i_mmu_cache$EN_pte_writeback_g_get),
			    .EN_l1_to_l2_client_request_deq(i_mmu_cache$EN_l1_to_l2_client_request_deq),
			    .EN_l1_to_l2_client_response_enq(i_mmu_cache$EN_l1_to_l2_client_response_enq),
			    .EN_l2_to_l1_server_request_enq(i_mmu_cache$EN_l2_to_l1_server_request_enq),
			    .EN_l2_to_l1_server_response_deq(i_mmu_cache$EN_l2_to_l1_server_response_deq),
			    .EN_mmio_client_request_get(i_mmu_cache$EN_mmio_client_request_get),
			    .EN_mmio_client_response_put(i_mmu_cache$EN_mmio_client_response_put),
			    .valid(i_mmu_cache$valid),
			    .addr(i_mmu_cache$addr),
			    .word64(i_mmu_cache$word64),
			    .exc(i_mmu_cache$exc),
			    .exc_code(i_mmu_cache$exc_code),
			    .RDY_flush_server_request_put(),
			    .RDY_flush_server_response_get(),
			    .RDY_tlb_flush(),
			    .ptw_client_request_get(i_mmu_cache$ptw_client_request_get),
			    .RDY_ptw_client_request_get(i_mmu_cache$RDY_ptw_client_request_get),
			    .RDY_ptw_client_response_put(i_mmu_cache$RDY_ptw_client_response_put),
			    .pte_writeback_g_get(i_mmu_cache$pte_writeback_g_get),
			    .RDY_pte_writeback_g_get(i_mmu_cache$RDY_pte_writeback_g_get),
			    .l1_to_l2_client_request_first(i_mmu_cache$l1_to_l2_client_request_first),
			    .RDY_l1_to_l2_client_request_first(i_mmu_cache$RDY_l1_to_l2_client_request_first),
			    .RDY_l1_to_l2_client_request_deq(i_mmu_cache$RDY_l1_to_l2_client_request_deq),
			    .l1_to_l2_client_request_notEmpty(),
			    .RDY_l1_to_l2_client_request_notEmpty(),
			    .RDY_l1_to_l2_client_response_enq(i_mmu_cache$RDY_l1_to_l2_client_response_enq),
			    .l1_to_l2_client_response_notFull(),
			    .RDY_l1_to_l2_client_response_notFull(),
			    .RDY_l2_to_l1_server_request_enq(i_mmu_cache$RDY_l2_to_l1_server_request_enq),
			    .l2_to_l1_server_request_notFull(),
			    .RDY_l2_to_l1_server_request_notFull(),
			    .l2_to_l1_server_response_first(i_mmu_cache$l2_to_l1_server_response_first),
			    .RDY_l2_to_l1_server_response_first(i_mmu_cache$RDY_l2_to_l1_server_response_first),
			    .RDY_l2_to_l1_server_response_deq(i_mmu_cache$RDY_l2_to_l1_server_response_deq),
			    .l2_to_l1_server_response_notEmpty(),
			    .RDY_l2_to_l1_server_response_notEmpty(),
			    .mmio_client_request_get(i_mmu_cache$mmio_client_request_get),
			    .RDY_mmio_client_request_get(i_mmu_cache$RDY_mmio_client_request_get),
			    .RDY_mmio_client_response_put(i_mmu_cache$RDY_mmio_client_response_put));

  // submodule llc
  mkLLCache llc(.CLK(CLK),
		.RST_N(RST_N),
		.dma_memReq_enq_x(llc$dma_memReq_enq_x),
		.perf_req_r(llc$perf_req_r),
		.perf_setStatus_doStats(llc$perf_setStatus_doStats),
		.to_child_rqFromC_enq_x(llc$to_child_rqFromC_enq_x),
		.to_child_rsFromC_enq_x(llc$to_child_rsFromC_enq_x),
		.to_mem_rsFromM_enq_x(llc$to_mem_rsFromM_enq_x),
		.EN_to_child_rsFromC_enq(llc$EN_to_child_rsFromC_enq),
		.EN_to_child_rqFromC_enq(llc$EN_to_child_rqFromC_enq),
		.EN_to_child_toC_deq(llc$EN_to_child_toC_deq),
		.EN_dma_memReq_enq(llc$EN_dma_memReq_enq),
		.EN_dma_respLd_deq(llc$EN_dma_respLd_deq),
		.EN_dma_respSt_deq(llc$EN_dma_respSt_deq),
		.EN_to_mem_toM_deq(llc$EN_to_mem_toM_deq),
		.EN_to_mem_rsFromM_enq(llc$EN_to_mem_rsFromM_enq),
		.EN_cRqStuck_get(llc$EN_cRqStuck_get),
		.EN_perf_setStatus(llc$EN_perf_setStatus),
		.EN_perf_req(llc$EN_perf_req),
		.EN_perf_resp(llc$EN_perf_resp),
		.to_child_rsFromC_notFull(),
		.RDY_to_child_rsFromC_notFull(),
		.RDY_to_child_rsFromC_enq(llc$RDY_to_child_rsFromC_enq),
		.to_child_rqFromC_notFull(),
		.RDY_to_child_rqFromC_notFull(),
		.RDY_to_child_rqFromC_enq(llc$RDY_to_child_rqFromC_enq),
		.to_child_toC_notEmpty(),
		.RDY_to_child_toC_notEmpty(),
		.RDY_to_child_toC_deq(llc$RDY_to_child_toC_deq),
		.to_child_toC_first(llc$to_child_toC_first),
		.RDY_to_child_toC_first(llc$RDY_to_child_toC_first),
		.dma_memReq_notFull(),
		.RDY_dma_memReq_notFull(),
		.RDY_dma_memReq_enq(llc$RDY_dma_memReq_enq),
		.dma_respLd_notEmpty(),
		.RDY_dma_respLd_notEmpty(),
		.RDY_dma_respLd_deq(llc$RDY_dma_respLd_deq),
		.dma_respLd_first(llc$dma_respLd_first),
		.RDY_dma_respLd_first(llc$RDY_dma_respLd_first),
		.dma_respSt_notEmpty(),
		.RDY_dma_respSt_notEmpty(),
		.RDY_dma_respSt_deq(llc$RDY_dma_respSt_deq),
		.dma_respSt_first(llc$dma_respSt_first),
		.RDY_dma_respSt_first(llc$RDY_dma_respSt_first),
		.to_mem_toM_notEmpty(),
		.RDY_to_mem_toM_notEmpty(),
		.RDY_to_mem_toM_deq(llc$RDY_to_mem_toM_deq),
		.to_mem_toM_first(llc$to_mem_toM_first),
		.RDY_to_mem_toM_first(llc$RDY_to_mem_toM_first),
		.to_mem_rsFromM_notFull(),
		.RDY_to_mem_rsFromM_notFull(),
		.RDY_to_mem_rsFromM_enq(llc$RDY_to_mem_rsFromM_enq),
		.cRqStuck_get(),
		.RDY_cRqStuck_get(),
		.RDY_perf_setStatus(),
		.RDY_perf_req(),
		.perf_resp(),
		.RDY_perf_resp(),
		.perf_respValid(),
		.RDY_perf_respValid());

  // submodule llc_axi4_adapter_f_pending_reads
  FIFO2 #(.width(32'd69),
	  .guarded(32'd1)) llc_axi4_adapter_f_pending_reads(.RST(RST_N),
							    .CLK(CLK),
							    .D_IN(llc_axi4_adapter_f_pending_reads$D_IN),
							    .ENQ(llc_axi4_adapter_f_pending_reads$ENQ),
							    .DEQ(llc_axi4_adapter_f_pending_reads$DEQ),
							    .CLR(llc_axi4_adapter_f_pending_reads$CLR),
							    .D_OUT(llc_axi4_adapter_f_pending_reads$D_OUT),
							    .FULL_N(llc_axi4_adapter_f_pending_reads$FULL_N),
							    .EMPTY_N(llc_axi4_adapter_f_pending_reads$EMPTY_N));

  // submodule llc_axi4_adapter_f_pending_writes
  FIFO2 #(.width(32'd640),
	  .guarded(32'd1)) llc_axi4_adapter_f_pending_writes(.RST(RST_N),
							     .CLK(CLK),
							     .D_IN(llc_axi4_adapter_f_pending_writes$D_IN),
							     .ENQ(llc_axi4_adapter_f_pending_writes$ENQ),
							     .DEQ(llc_axi4_adapter_f_pending_writes$DEQ),
							     .CLR(llc_axi4_adapter_f_pending_writes$CLR),
							     .D_OUT(),
							     .FULL_N(llc_axi4_adapter_f_pending_writes$FULL_N),
							     .EMPTY_N(llc_axi4_adapter_f_pending_writes$EMPTY_N));

  // submodule llc_dma_axi4_adapter_axi4_slave_xactor_f_rd_addr
  FIFO2 #(.width(32'd109),
	  .guarded(32'd1)) llc_dma_axi4_adapter_axi4_slave_xactor_f_rd_addr(.RST(RST_N),
									    .CLK(CLK),
									    .D_IN(llc_dma_axi4_adapter_axi4_slave_xactor_f_rd_addr$D_IN),
									    .ENQ(llc_dma_axi4_adapter_axi4_slave_xactor_f_rd_addr$ENQ),
									    .DEQ(llc_dma_axi4_adapter_axi4_slave_xactor_f_rd_addr$DEQ),
									    .CLR(llc_dma_axi4_adapter_axi4_slave_xactor_f_rd_addr$CLR),
									    .D_OUT(llc_dma_axi4_adapter_axi4_slave_xactor_f_rd_addr$D_OUT),
									    .FULL_N(llc_dma_axi4_adapter_axi4_slave_xactor_f_rd_addr$FULL_N),
									    .EMPTY_N(llc_dma_axi4_adapter_axi4_slave_xactor_f_rd_addr$EMPTY_N));

  // submodule llc_dma_axi4_adapter_axi4_slave_xactor_f_rd_data
  FIFO2 #(.width(32'd531),
	  .guarded(32'd1)) llc_dma_axi4_adapter_axi4_slave_xactor_f_rd_data(.RST(RST_N),
									    .CLK(CLK),
									    .D_IN(llc_dma_axi4_adapter_axi4_slave_xactor_f_rd_data$D_IN),
									    .ENQ(llc_dma_axi4_adapter_axi4_slave_xactor_f_rd_data$ENQ),
									    .DEQ(llc_dma_axi4_adapter_axi4_slave_xactor_f_rd_data$DEQ),
									    .CLR(llc_dma_axi4_adapter_axi4_slave_xactor_f_rd_data$CLR),
									    .D_OUT(llc_dma_axi4_adapter_axi4_slave_xactor_f_rd_data$D_OUT),
									    .FULL_N(llc_dma_axi4_adapter_axi4_slave_xactor_f_rd_data$FULL_N),
									    .EMPTY_N(llc_dma_axi4_adapter_axi4_slave_xactor_f_rd_data$EMPTY_N));

  // submodule llc_dma_axi4_adapter_axi4_slave_xactor_f_wr_addr
  FIFO2 #(.width(32'd109),
	  .guarded(32'd1)) llc_dma_axi4_adapter_axi4_slave_xactor_f_wr_addr(.RST(RST_N),
									    .CLK(CLK),
									    .D_IN(llc_dma_axi4_adapter_axi4_slave_xactor_f_wr_addr$D_IN),
									    .ENQ(llc_dma_axi4_adapter_axi4_slave_xactor_f_wr_addr$ENQ),
									    .DEQ(llc_dma_axi4_adapter_axi4_slave_xactor_f_wr_addr$DEQ),
									    .CLR(llc_dma_axi4_adapter_axi4_slave_xactor_f_wr_addr$CLR),
									    .D_OUT(llc_dma_axi4_adapter_axi4_slave_xactor_f_wr_addr$D_OUT),
									    .FULL_N(llc_dma_axi4_adapter_axi4_slave_xactor_f_wr_addr$FULL_N),
									    .EMPTY_N(llc_dma_axi4_adapter_axi4_slave_xactor_f_wr_addr$EMPTY_N));

  // submodule llc_dma_axi4_adapter_axi4_slave_xactor_f_wr_data
  FIFO2 #(.width(32'd577),
	  .guarded(32'd1)) llc_dma_axi4_adapter_axi4_slave_xactor_f_wr_data(.RST(RST_N),
									    .CLK(CLK),
									    .D_IN(llc_dma_axi4_adapter_axi4_slave_xactor_f_wr_data$D_IN),
									    .ENQ(llc_dma_axi4_adapter_axi4_slave_xactor_f_wr_data$ENQ),
									    .DEQ(llc_dma_axi4_adapter_axi4_slave_xactor_f_wr_data$DEQ),
									    .CLR(llc_dma_axi4_adapter_axi4_slave_xactor_f_wr_data$CLR),
									    .D_OUT(llc_dma_axi4_adapter_axi4_slave_xactor_f_wr_data$D_OUT),
									    .FULL_N(llc_dma_axi4_adapter_axi4_slave_xactor_f_wr_data$FULL_N),
									    .EMPTY_N(llc_dma_axi4_adapter_axi4_slave_xactor_f_wr_data$EMPTY_N));

  // submodule llc_dma_axi4_adapter_axi4_slave_xactor_f_wr_resp
  FIFO2 #(.width(32'd18),
	  .guarded(32'd1)) llc_dma_axi4_adapter_axi4_slave_xactor_f_wr_resp(.RST(RST_N),
									    .CLK(CLK),
									    .D_IN(llc_dma_axi4_adapter_axi4_slave_xactor_f_wr_resp$D_IN),
									    .ENQ(llc_dma_axi4_adapter_axi4_slave_xactor_f_wr_resp$ENQ),
									    .DEQ(llc_dma_axi4_adapter_axi4_slave_xactor_f_wr_resp$DEQ),
									    .CLR(llc_dma_axi4_adapter_axi4_slave_xactor_f_wr_resp$CLR),
									    .D_OUT(llc_dma_axi4_adapter_axi4_slave_xactor_f_wr_resp$D_OUT),
									    .FULL_N(llc_dma_axi4_adapter_axi4_slave_xactor_f_wr_resp$FULL_N),
									    .EMPTY_N(llc_dma_axi4_adapter_axi4_slave_xactor_f_wr_resp$EMPTY_N));

  // submodule mmio_axi4_adapter
  mkMMIO_AXI4_Adapter_2 #(.verbosity(3'd0)) mmio_axi4_adapter(.CLK(CLK),
							      .RST_N(RST_N),
							      .mem_master_arready(mmio_axi4_adapter$mem_master_arready),
							      .mem_master_awready(mmio_axi4_adapter$mem_master_awready),
							      .mem_master_bid(mmio_axi4_adapter$mem_master_bid),
							      .mem_master_bresp(mmio_axi4_adapter$mem_master_bresp),
							      .mem_master_bvalid(mmio_axi4_adapter$mem_master_bvalid),
							      .mem_master_rdata(mmio_axi4_adapter$mem_master_rdata),
							      .mem_master_rid(mmio_axi4_adapter$mem_master_rid),
							      .mem_master_rlast(mmio_axi4_adapter$mem_master_rlast),
							      .mem_master_rresp(mmio_axi4_adapter$mem_master_rresp),
							      .mem_master_rvalid(mmio_axi4_adapter$mem_master_rvalid),
							      .mem_master_wready(mmio_axi4_adapter$mem_master_wready),
							      .v_mmio_server_0_request_put(mmio_axi4_adapter$v_mmio_server_0_request_put),
							      .v_mmio_server_1_request_put(mmio_axi4_adapter$v_mmio_server_1_request_put),
							      .EN_v_mmio_server_0_request_put(mmio_axi4_adapter$EN_v_mmio_server_0_request_put),
							      .EN_v_mmio_server_0_response_get(mmio_axi4_adapter$EN_v_mmio_server_0_response_get),
							      .EN_v_mmio_server_1_request_put(mmio_axi4_adapter$EN_v_mmio_server_1_request_put),
							      .EN_v_mmio_server_1_response_get(mmio_axi4_adapter$EN_v_mmio_server_1_response_get),
							      .RDY_v_mmio_server_0_request_put(mmio_axi4_adapter$RDY_v_mmio_server_0_request_put),
							      .v_mmio_server_0_response_get(mmio_axi4_adapter$v_mmio_server_0_response_get),
							      .RDY_v_mmio_server_0_response_get(mmio_axi4_adapter$RDY_v_mmio_server_0_response_get),
							      .RDY_v_mmio_server_1_request_put(mmio_axi4_adapter$RDY_v_mmio_server_1_request_put),
							      .v_mmio_server_1_response_get(mmio_axi4_adapter$v_mmio_server_1_response_get),
							      .RDY_v_mmio_server_1_response_get(mmio_axi4_adapter$RDY_v_mmio_server_1_response_get),
							      .mem_master_awvalid(mmio_axi4_adapter$mem_master_awvalid),
							      .mem_master_awid(mmio_axi4_adapter$mem_master_awid),
							      .mem_master_awaddr(mmio_axi4_adapter$mem_master_awaddr),
							      .mem_master_awlen(mmio_axi4_adapter$mem_master_awlen),
							      .mem_master_awsize(mmio_axi4_adapter$mem_master_awsize),
							      .mem_master_awburst(mmio_axi4_adapter$mem_master_awburst),
							      .mem_master_awlock(mmio_axi4_adapter$mem_master_awlock),
							      .mem_master_awcache(mmio_axi4_adapter$mem_master_awcache),
							      .mem_master_awprot(mmio_axi4_adapter$mem_master_awprot),
							      .mem_master_awqos(mmio_axi4_adapter$mem_master_awqos),
							      .mem_master_awregion(mmio_axi4_adapter$mem_master_awregion),
							      .mem_master_wvalid(mmio_axi4_adapter$mem_master_wvalid),
							      .mem_master_wdata(mmio_axi4_adapter$mem_master_wdata),
							      .mem_master_wstrb(mmio_axi4_adapter$mem_master_wstrb),
							      .mem_master_wlast(mmio_axi4_adapter$mem_master_wlast),
							      .mem_master_bready(mmio_axi4_adapter$mem_master_bready),
							      .mem_master_arvalid(mmio_axi4_adapter$mem_master_arvalid),
							      .mem_master_arid(mmio_axi4_adapter$mem_master_arid),
							      .mem_master_araddr(mmio_axi4_adapter$mem_master_araddr),
							      .mem_master_arlen(mmio_axi4_adapter$mem_master_arlen),
							      .mem_master_arsize(mmio_axi4_adapter$mem_master_arsize),
							      .mem_master_arburst(mmio_axi4_adapter$mem_master_arburst),
							      .mem_master_arlock(mmio_axi4_adapter$mem_master_arlock),
							      .mem_master_arcache(mmio_axi4_adapter$mem_master_arcache),
							      .mem_master_arprot(mmio_axi4_adapter$mem_master_arprot),
							      .mem_master_arqos(mmio_axi4_adapter$mem_master_arqos),
							      .mem_master_arregion(mmio_axi4_adapter$mem_master_arregion),
							      .mem_master_rready(mmio_axi4_adapter$mem_master_rready),
							      .mv_write_error());

  // submodule propDstData_0_dummy2_0
  RevertReg #(.width(32'd1), .init(1'd1)) propDstData_0_dummy2_0(.CLK(CLK),
								 .D_IN(propDstData_0_dummy2_0$D_IN),
								 .EN(propDstData_0_dummy2_0$EN),
								 .Q_OUT());

  // submodule propDstData_0_dummy2_1
  RevertReg #(.width(32'd1), .init(1'd1)) propDstData_0_dummy2_1(.CLK(CLK),
								 .D_IN(propDstData_0_dummy2_1$D_IN),
								 .EN(propDstData_0_dummy2_1$EN),
								 .Q_OUT(propDstData_0_dummy2_1$Q_OUT));

  // submodule propDstData_1_0_dummy2_0
  RevertReg #(.width(32'd1), .init(1'd1)) propDstData_1_0_dummy2_0(.CLK(CLK),
								   .D_IN(propDstData_1_0_dummy2_0$D_IN),
								   .EN(propDstData_1_0_dummy2_0$EN),
								   .Q_OUT());

  // submodule propDstData_1_0_dummy2_1
  RevertReg #(.width(32'd1), .init(1'd1)) propDstData_1_0_dummy2_1(.CLK(CLK),
								   .D_IN(propDstData_1_0_dummy2_1$D_IN),
								   .EN(propDstData_1_0_dummy2_1$EN),
								   .Q_OUT(propDstData_1_0_dummy2_1$Q_OUT));

  // submodule propDstData_1_1_dummy2_0
  RevertReg #(.width(32'd1), .init(1'd1)) propDstData_1_1_dummy2_0(.CLK(CLK),
								   .D_IN(propDstData_1_1_dummy2_0$D_IN),
								   .EN(propDstData_1_1_dummy2_0$EN),
								   .Q_OUT());

  // submodule propDstData_1_1_dummy2_1
  RevertReg #(.width(32'd1), .init(1'd1)) propDstData_1_1_dummy2_1(.CLK(CLK),
								   .D_IN(propDstData_1_1_dummy2_1$D_IN),
								   .EN(propDstData_1_1_dummy2_1$EN),
								   .Q_OUT(propDstData_1_1_dummy2_1$Q_OUT));

  // submodule propDstData_1_dummy2_0
  RevertReg #(.width(32'd1), .init(1'd1)) propDstData_1_dummy2_0(.CLK(CLK),
								 .D_IN(propDstData_1_dummy2_0$D_IN),
								 .EN(propDstData_1_dummy2_0$EN),
								 .Q_OUT());

  // submodule propDstData_1_dummy2_1
  RevertReg #(.width(32'd1), .init(1'd1)) propDstData_1_dummy2_1(.CLK(CLK),
								 .D_IN(propDstData_1_dummy2_1$D_IN),
								 .EN(propDstData_1_dummy2_1$EN),
								 .Q_OUT(propDstData_1_dummy2_1$Q_OUT));

  // submodule propDstIdx_0_dummy2_0
  RevertReg #(.width(32'd1), .init(1'd1)) propDstIdx_0_dummy2_0(.CLK(CLK),
								.D_IN(propDstIdx_0_dummy2_0$D_IN),
								.EN(propDstIdx_0_dummy2_0$EN),
								.Q_OUT(propDstIdx_0_dummy2_0$Q_OUT));

  // submodule propDstIdx_0_dummy2_1
  RevertReg #(.width(32'd1), .init(1'd1)) propDstIdx_0_dummy2_1(.CLK(CLK),
								.D_IN(propDstIdx_0_dummy2_1$D_IN),
								.EN(propDstIdx_0_dummy2_1$EN),
								.Q_OUT(propDstIdx_0_dummy2_1$Q_OUT));

  // submodule propDstIdx_1_0_dummy2_0
  RevertReg #(.width(32'd1), .init(1'd1)) propDstIdx_1_0_dummy2_0(.CLK(CLK),
								  .D_IN(propDstIdx_1_0_dummy2_0$D_IN),
								  .EN(propDstIdx_1_0_dummy2_0$EN),
								  .Q_OUT(propDstIdx_1_0_dummy2_0$Q_OUT));

  // submodule propDstIdx_1_0_dummy2_1
  RevertReg #(.width(32'd1), .init(1'd1)) propDstIdx_1_0_dummy2_1(.CLK(CLK),
								  .D_IN(propDstIdx_1_0_dummy2_1$D_IN),
								  .EN(propDstIdx_1_0_dummy2_1$EN),
								  .Q_OUT(propDstIdx_1_0_dummy2_1$Q_OUT));

  // submodule propDstIdx_1_1_dummy2_0
  RevertReg #(.width(32'd1), .init(1'd1)) propDstIdx_1_1_dummy2_0(.CLK(CLK),
								  .D_IN(propDstIdx_1_1_dummy2_0$D_IN),
								  .EN(propDstIdx_1_1_dummy2_0$EN),
								  .Q_OUT(propDstIdx_1_1_dummy2_0$Q_OUT));

  // submodule propDstIdx_1_1_dummy2_1
  RevertReg #(.width(32'd1), .init(1'd1)) propDstIdx_1_1_dummy2_1(.CLK(CLK),
								  .D_IN(propDstIdx_1_1_dummy2_1$D_IN),
								  .EN(propDstIdx_1_1_dummy2_1$EN),
								  .Q_OUT(propDstIdx_1_1_dummy2_1$Q_OUT));

  // submodule propDstIdx_1_dummy2_0
  RevertReg #(.width(32'd1), .init(1'd1)) propDstIdx_1_dummy2_0(.CLK(CLK),
								.D_IN(propDstIdx_1_dummy2_0$D_IN),
								.EN(propDstIdx_1_dummy2_0$EN),
								.Q_OUT(propDstIdx_1_dummy2_0$Q_OUT));

  // submodule propDstIdx_1_dummy2_1
  RevertReg #(.width(32'd1), .init(1'd1)) propDstIdx_1_dummy2_1(.CLK(CLK),
								.D_IN(propDstIdx_1_dummy2_1$D_IN),
								.EN(propDstIdx_1_dummy2_1$EN),
								.Q_OUT(propDstIdx_1_dummy2_1$Q_OUT));

  // submodule soc_map
  mkSoC_Map soc_map(.CLK(CLK),
		    .RST_N(RST_N),
		    .m_is_IO_addr_addr(soc_map$m_is_IO_addr_addr),
		    .m_is_mem_addr_addr(soc_map$m_is_mem_addr_addr),
		    .m_is_near_mem_IO_addr_addr(soc_map$m_is_near_mem_IO_addr_addr),
		    .m_plic_addr_base(),
		    .m_plic_addr_size(),
		    .m_plic_addr_lim(),
		    .m_near_mem_io_addr_base(),
		    .m_near_mem_io_addr_size(),
		    .m_near_mem_io_addr_lim(),
		    .m_flash_mem_addr_base(),
		    .m_flash_mem_addr_size(),
		    .m_flash_mem_addr_lim(),
		    .m_ethernet_0_addr_base(),
		    .m_ethernet_0_addr_size(),
		    .m_ethernet_0_addr_lim(),
		    .m_dma_0_addr_base(),
		    .m_dma_0_addr_size(),
		    .m_dma_0_addr_lim(),
		    .m_uart16550_0_addr_base(),
		    .m_uart16550_0_addr_size(),
		    .m_uart16550_0_addr_lim(),
		    .m_gpio_0_addr_base(),
		    .m_gpio_0_addr_size(),
		    .m_gpio_0_addr_lim(),
		    .m_boot_rom_addr_base(),
		    .m_boot_rom_addr_size(),
		    .m_boot_rom_addr_lim(),
		    .m_ddr4_0_uncached_addr_base(),
		    .m_ddr4_0_uncached_addr_size(),
		    .m_ddr4_0_uncached_addr_lim(),
		    .m_ddr4_0_cached_addr_base(),
		    .m_ddr4_0_cached_addr_size(),
		    .m_ddr4_0_cached_addr_lim(),
		    .m_is_mem_addr(),
		    .m_is_IO_addr(),
		    .m_is_near_mem_IO_addr(),
		    .m_pc_reset_value(),
		    .m_mtvec_reset_value(),
		    .m_nmivec_reset_value());

  // rule RL_ClientServerRequest
  assign CAN_FIRE_RL_ClientServerRequest =
	     d_mmu_cache$RDY_imem_ptw_server_request_put &&
	     i_mmu_cache$RDY_ptw_client_request_get ;
  assign WILL_FIRE_RL_ClientServerRequest = CAN_FIRE_RL_ClientServerRequest ;

  // rule RL_ClientServerResponse
  assign CAN_FIRE_RL_ClientServerResponse =
	     d_mmu_cache$RDY_imem_ptw_server_response_get &&
	     i_mmu_cache$RDY_ptw_client_response_put ;
  assign WILL_FIRE_RL_ClientServerResponse =
	     CAN_FIRE_RL_ClientServerResponse ;

  // rule RL_mkConnectionGetPut
  assign CAN_FIRE_RL_mkConnectionGetPut =
	     d_mmu_cache$RDY_imem_pte_writeback_p_put &&
	     i_mmu_cache$RDY_pte_writeback_g_get ;
  assign WILL_FIRE_RL_mkConnectionGetPut = CAN_FIRE_RL_mkConnectionGetPut ;

  // rule RL_srcPropose
  assign CAN_FIRE_RL_srcPropose =
	     i_mmu_cache$RDY_l1_to_l2_client_request_deq &&
	     i_mmu_cache$RDY_l1_to_l2_client_request_first &&
	     (!propDstIdx_0_dummy2_0$Q_OUT || !propDstIdx_0_dummy2_1$Q_OUT ||
	      !propDstIdx_0_rl) ;
  assign WILL_FIRE_RL_srcPropose = CAN_FIRE_RL_srcPropose ;

  // rule RL_srcPropose_1
  assign CAN_FIRE_RL_srcPropose_1 =
	     d_mmu_cache$RDY_l1_to_l2_client_request_deq &&
	     d_mmu_cache$RDY_l1_to_l2_client_request_first &&
	     (!propDstIdx_1_dummy2_0$Q_OUT || !propDstIdx_1_dummy2_1$Q_OUT ||
	      !propDstIdx_1_rl) ;
  assign WILL_FIRE_RL_srcPropose_1 = CAN_FIRE_RL_srcPropose_1 ;

  // rule RL_dstSelectSrc
  assign CAN_FIRE_RL_dstSelectSrc = 1'd1 ;
  assign WILL_FIRE_RL_dstSelectSrc = 1'd1 ;

  // rule RL_doEnq
  assign CAN_FIRE_RL_doEnq =
	     llc$RDY_to_child_rqFromC_enq && enqDst_0_dummy2_1$Q_OUT &&
	     IF_enqDst_0_lat_0_whas__06_THEN_enqDst_0_lat_0_ETC___d211 ;
  assign WILL_FIRE_RL_doEnq = CAN_FIRE_RL_doEnq ;

  // rule RL_srcPropose_2
  assign CAN_FIRE_RL_srcPropose_2 =
	     i_mmu_cache$RDY_l2_to_l1_server_response_deq &&
	     i_mmu_cache$RDY_l2_to_l1_server_response_first &&
	     (!propDstIdx_1_0_dummy2_0$Q_OUT ||
	      !propDstIdx_1_0_dummy2_1$Q_OUT ||
	      !propDstIdx_1_0_rl) ;
  assign WILL_FIRE_RL_srcPropose_2 = CAN_FIRE_RL_srcPropose_2 ;

  // rule RL_srcPropose_3
  assign CAN_FIRE_RL_srcPropose_3 =
	     d_mmu_cache$RDY_l2_to_l1_server_response_deq &&
	     d_mmu_cache$RDY_l2_to_l1_server_response_first &&
	     (!propDstIdx_1_1_dummy2_0$Q_OUT ||
	      !propDstIdx_1_1_dummy2_1$Q_OUT ||
	      !propDstIdx_1_1_rl) ;
  assign WILL_FIRE_RL_srcPropose_3 = CAN_FIRE_RL_srcPropose_3 ;

  // rule RL_dstSelectSrc_1
  assign CAN_FIRE_RL_dstSelectSrc_1 = 1'd1 ;
  assign WILL_FIRE_RL_dstSelectSrc_1 = 1'd1 ;

  // rule RL_doEnq_1
  assign CAN_FIRE_RL_doEnq_1 =
	     llc$RDY_to_child_rsFromC_enq && enqDst_1_0_dummy2_1$Q_OUT &&
	     IF_enqDst_1_0_lat_0_whas__78_THEN_enqDst_1_0_l_ETC___d483 ;
  assign WILL_FIRE_RL_doEnq_1 = CAN_FIRE_RL_doEnq_1 ;

  // rule RL_sendPRq
  assign CAN_FIRE_RL_sendPRq =
	     i_mmu_cache$RDY_l2_to_l1_server_request_enq &&
	     llc$RDY_to_child_toC_first &&
	     llc$RDY_to_child_toC_deq &&
	     !llc$to_child_toC_first[583] &&
	     !llc$to_child_toC_first[0] ;
  assign WILL_FIRE_RL_sendPRq = CAN_FIRE_RL_sendPRq ;

  // rule RL_sendPRs
  assign CAN_FIRE_RL_sendPRs =
	     i_mmu_cache$RDY_l1_to_l2_client_response_enq &&
	     llc$RDY_to_child_toC_first &&
	     llc$RDY_to_child_toC_deq &&
	     llc$to_child_toC_first[583] &&
	     !llc$to_child_toC_first[516] ;
  assign WILL_FIRE_RL_sendPRs = CAN_FIRE_RL_sendPRs ;

  // rule RL_sendPRq_1
  assign CAN_FIRE_RL_sendPRq_1 =
	     d_mmu_cache$RDY_l2_to_l1_server_request_enq &&
	     llc$RDY_to_child_toC_first &&
	     llc$RDY_to_child_toC_deq &&
	     !llc$to_child_toC_first[583] &&
	     llc$to_child_toC_first[0] ;
  assign WILL_FIRE_RL_sendPRq_1 = CAN_FIRE_RL_sendPRq_1 ;

  // rule RL_sendPRs_1
  assign CAN_FIRE_RL_sendPRs_1 =
	     d_mmu_cache$RDY_l1_to_l2_client_response_enq &&
	     llc$RDY_to_child_toC_first &&
	     llc$RDY_to_child_toC_deq &&
	     llc$to_child_toC_first[583] &&
	     llc$to_child_toC_first[516] ;
  assign WILL_FIRE_RL_sendPRs_1 = CAN_FIRE_RL_sendPRs_1 ;

  // rule RL_ClientServerRequest_1
  assign CAN_FIRE_RL_ClientServerRequest_1 =
	     mmio_axi4_adapter$RDY_v_mmio_server_0_request_put &&
	     i_mmu_cache$RDY_mmio_client_request_get ;
  assign WILL_FIRE_RL_ClientServerRequest_1 =
	     CAN_FIRE_RL_ClientServerRequest_1 ;

  // rule RL_ClientServerResponse_1
  assign CAN_FIRE_RL_ClientServerResponse_1 =
	     mmio_axi4_adapter$RDY_v_mmio_server_0_response_get &&
	     i_mmu_cache$RDY_mmio_client_response_put ;
  assign WILL_FIRE_RL_ClientServerResponse_1 =
	     CAN_FIRE_RL_ClientServerResponse_1 ;

  // rule RL_ClientServerRequest_2
  assign CAN_FIRE_RL_ClientServerRequest_2 =
	     mmio_axi4_adapter$RDY_v_mmio_server_1_request_put &&
	     d_mmu_cache$RDY_mmio_client_request_get ;
  assign WILL_FIRE_RL_ClientServerRequest_2 =
	     CAN_FIRE_RL_ClientServerRequest_2 ;

  // rule RL_ClientServerResponse_2
  assign CAN_FIRE_RL_ClientServerResponse_2 =
	     mmio_axi4_adapter$RDY_v_mmio_server_1_response_get &&
	     d_mmu_cache$RDY_mmio_client_response_put ;
  assign WILL_FIRE_RL_ClientServerResponse_2 =
	     CAN_FIRE_RL_ClientServerResponse_2 ;

  // rule RL_rl_reset
  assign CAN_FIRE_RL_rl_reset = rg_state == 2'd0 ;
  assign WILL_FIRE_RL_rl_reset = CAN_FIRE_RL_rl_reset ;

  // rule RL_rl_reset_complete
  assign CAN_FIRE_RL_rl_reset_complete = MUX_rg_state$write_1__SEL_3 ;
  assign WILL_FIRE_RL_rl_reset_complete = MUX_rg_state$write_1__SEL_3 ;

  // rule RL_llc_dma_axi4_adapter_rl_wr_req
  assign CAN_FIRE_RL_llc_dma_axi4_adapter_rl_wr_req =
	     llc$RDY_dma_memReq_enq &&
	     llc_dma_axi4_adapter_axi4_slave_xactor_f_wr_addr$EMPTY_N &&
	     llc_dma_axi4_adapter_axi4_slave_xactor_f_wr_data$EMPTY_N ;
  assign WILL_FIRE_RL_llc_dma_axi4_adapter_rl_wr_req =
	     CAN_FIRE_RL_llc_dma_axi4_adapter_rl_wr_req ;

  // rule RL_llc_dma_axi4_adapter_rl_wr_rsp
  assign CAN_FIRE_RL_llc_dma_axi4_adapter_rl_wr_rsp =
	     llc$RDY_dma_respSt_first && llc$RDY_dma_respSt_deq &&
	     llc_dma_axi4_adapter_axi4_slave_xactor_f_wr_resp$FULL_N ;
  assign WILL_FIRE_RL_llc_dma_axi4_adapter_rl_wr_rsp =
	     CAN_FIRE_RL_llc_dma_axi4_adapter_rl_wr_rsp ;

  // rule RL_llc_dma_axi4_adapter_rl_rd_req
  assign CAN_FIRE_RL_llc_dma_axi4_adapter_rl_rd_req =
	     llc$RDY_dma_memReq_enq &&
	     llc_dma_axi4_adapter_axi4_slave_xactor_f_rd_addr$EMPTY_N ;
  assign WILL_FIRE_RL_llc_dma_axi4_adapter_rl_rd_req =
	     CAN_FIRE_RL_llc_dma_axi4_adapter_rl_rd_req &&
	     !WILL_FIRE_RL_llc_dma_axi4_adapter_rl_wr_req ;

  // rule RL_llc_dma_axi4_adapter_rl_rd_rsp
  assign CAN_FIRE_RL_llc_dma_axi4_adapter_rl_rd_rsp =
	     llc$RDY_dma_respLd_first && llc$RDY_dma_respLd_deq &&
	     llc_dma_axi4_adapter_axi4_slave_xactor_f_rd_data$FULL_N ;
  assign WILL_FIRE_RL_llc_dma_axi4_adapter_rl_rd_rsp =
	     CAN_FIRE_RL_llc_dma_axi4_adapter_rl_rd_rsp ;

  // rule RL_llc_axi4_adapter_rl_handle_read_rsps
  assign CAN_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps =
	     llc_axi4_adapter_master_xactor_crg_rd_data_full &&
	     (llc_axi4_adapter_rg_rd_rsp_beat != 3'd7 ||
	      llc$RDY_to_mem_rsFromM_enq &&
	      llc_axi4_adapter_f_pending_reads$EMPTY_N) ;
  assign WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps =
	     CAN_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps ;

  // rule RL_llc_axi4_adapter_rl_handle_write_req
  assign CAN_FIRE_RL_llc_axi4_adapter_rl_handle_write_req =
	     NOT_llc_axi4_adapter_master_xactor_crg_wr_addr_ETC___d114 &&
	     llc$to_mem_toM_first[640] &&
	     llc_axi4_adapter_rg_ddr4_ready ;
  assign WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req =
	     CAN_FIRE_RL_llc_axi4_adapter_rl_handle_write_req ;

  // rule RL_llc_axi4_adapter_rl_handle_read_req
  assign CAN_FIRE_RL_llc_axi4_adapter_rl_handle_read_req =
	     !llc_axi4_adapter_master_xactor_crg_rd_addr_full$port2__read &&
	     llc$RDY_to_mem_toM_first &&
	     (llc_axi4_adapter_rg_rd_req_beat != 3'd0 ||
	      llc_axi4_adapter_f_pending_reads$FULL_N) &&
	     (llc_axi4_adapter_rg_rd_req_beat != 3'd7 ||
	      llc$RDY_to_mem_toM_deq) &&
	     !llc$to_mem_toM_first[640] &&
	     b__h20709 == 4'd0 &&
	     llc_axi4_adapter_rg_ddr4_ready ;
  assign WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req =
	     CAN_FIRE_RL_llc_axi4_adapter_rl_handle_read_req ;

  // rule RL_llc_axi4_adapter_rl_discard_write_rsp
  assign CAN_FIRE_RL_llc_axi4_adapter_rl_discard_write_rsp =
	     b__h20709 != 4'd0 &&
	     llc_axi4_adapter_master_xactor_crg_wr_resp_full &&
	     (llc_axi4_adapter_rg_wr_rsp_beat != 3'd7 ||
	      llc_axi4_adapter_f_pending_writes$EMPTY_N) ;
  assign WILL_FIRE_RL_llc_axi4_adapter_rl_discard_write_rsp =
	     CAN_FIRE_RL_llc_axi4_adapter_rl_discard_write_rsp ;

  // rule RL_propDstIdx_0_canon
  assign CAN_FIRE_RL_propDstIdx_0_canon = 1'd1 ;
  assign WILL_FIRE_RL_propDstIdx_0_canon = 1'd1 ;

  // rule RL_propDstIdx_1_canon
  assign CAN_FIRE_RL_propDstIdx_1_canon = 1'd1 ;
  assign WILL_FIRE_RL_propDstIdx_1_canon = 1'd1 ;

  // rule RL_propDstData_0_canon
  assign CAN_FIRE_RL_propDstData_0_canon = 1'd1 ;
  assign WILL_FIRE_RL_propDstData_0_canon = 1'd1 ;

  // rule RL_propDstData_1_canon
  assign CAN_FIRE_RL_propDstData_1_canon = 1'd1 ;
  assign WILL_FIRE_RL_propDstData_1_canon = 1'd1 ;

  // rule RL_enqDst_0_canon
  assign CAN_FIRE_RL_enqDst_0_canon = 1'd1 ;
  assign WILL_FIRE_RL_enqDst_0_canon = 1'd1 ;

  // rule RL_propDstIdx_1_0_canon
  assign CAN_FIRE_RL_propDstIdx_1_0_canon = 1'd1 ;
  assign WILL_FIRE_RL_propDstIdx_1_0_canon = 1'd1 ;

  // rule RL_propDstIdx_1_1_canon
  assign CAN_FIRE_RL_propDstIdx_1_1_canon = 1'd1 ;
  assign WILL_FIRE_RL_propDstIdx_1_1_canon = 1'd1 ;

  // rule RL_propDstData_1_0_canon
  assign CAN_FIRE_RL_propDstData_1_0_canon = 1'd1 ;
  assign WILL_FIRE_RL_propDstData_1_0_canon = 1'd1 ;

  // rule RL_propDstData_1_1_canon
  assign CAN_FIRE_RL_propDstData_1_1_canon = 1'd1 ;
  assign WILL_FIRE_RL_propDstData_1_1_canon = 1'd1 ;

  // rule RL_enqDst_1_0_canon
  assign CAN_FIRE_RL_enqDst_1_0_canon = 1'd1 ;
  assign WILL_FIRE_RL_enqDst_1_0_canon = 1'd1 ;

  // inputs to muxes for submodule ports
  assign MUX_rg_state$write_1__SEL_3 =
	     f_reset_rsps$FULL_N && rg_state == 2'd1 ;
  assign MUX_llc$dma_memReq_enq_1__VAL_1 =
	     { llc_dma_axi4_adapter_axi4_slave_xactor_f_wr_addr$D_OUT[92:29],
	       llc_dma_axi4_adapter_axi4_slave_xactor_f_wr_data$D_OUT[64:1],
	       llc_dma_axi4_adapter_axi4_slave_xactor_f_wr_data$D_OUT[576:65],
	       llc_dma_axi4_adapter_axi4_slave_xactor_f_wr_addr$D_OUT[108:93] } ;
  assign MUX_llc$dma_memReq_enq_1__VAL_2 =
	     { llc_dma_axi4_adapter_axi4_slave_xactor_f_rd_addr$D_OUT[92:29],
	       576'h0000000000000000AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA,
	       llc_dma_axi4_adapter_axi4_slave_xactor_f_rd_addr$D_OUT[108:93] } ;

  // inlined wires
  assign propDstIdx_0_lat_1$whas =
	     NOT_enqDst_0_dummy2_0_read__87_88_OR_NOT_enqDs_ETC___d303 &&
	     IF_SEL_ARR_propDstIdx_0_dummy2_1_read__30_AND__ETC___d373 ;
  assign propDstIdx_1_lat_1$whas =
	     NOT_enqDst_0_dummy2_0_read__87_88_OR_NOT_enqDs_ETC___d303 &&
	     x__h49280 ;
  assign propDstData_0_lat_0$wget =
	     { i_mmu_cache$l1_to_l2_client_request_first[68:5],
	       CASE_i_mmu_cachel1_to_l2_client_request_first_ETC__q1,
	       CASE_i_mmu_cachel1_to_l2_client_request_first_ETC__q2,
	       i_mmu_cache$l1_to_l2_client_request_first[0],
	       4'h4 } ;
  assign propDstData_1_lat_0$wget =
	     { d_mmu_cache$l1_to_l2_client_request_first[68:5],
	       CASE_d_mmu_cachel1_to_l2_client_request_first_ETC__q3,
	       CASE_d_mmu_cachel1_to_l2_client_request_first_ETC__q4,
	       d_mmu_cache$l1_to_l2_client_request_first[0],
	       4'h5 } ;
  assign enqDst_0_lat_0$wget =
	     { 1'd1,
	       CASE_x9280_0_n__read_addr9462_1_n__read_addr95_ETC__q8,
	       SEL_ARR_IF_propDstData_0_dummy2_1_read__04_THE_ETC___d368 } ;
  assign propDstIdx_1_0_lat_1$whas =
	     NOT_enqDst_1_0_dummy2_0_read__75_76_OR_NOT_enq_ETC___d591 &&
	     IF_SEL_ARR_propDstIdx_1_0_dummy2_1_read__30_AN_ETC___d689 ;
  assign propDstIdx_1_1_lat_1$whas =
	     NOT_enqDst_1_0_dummy2_0_read__75_76_OR_NOT_enq_ETC___d591 &&
	     x__h68218 ;
  assign propDstData_1_0_lat_0$wget =
	     { i_mmu_cache$l2_to_l1_server_response_first[578:515],
	       CASE_i_mmu_cachel2_to_l1_server_response_firs_ETC__q9,
	       i_mmu_cache$l2_to_l1_server_response_first[512:0],
	       1'd0 } ;
  assign propDstData_1_1_lat_0$wget =
	     { d_mmu_cache$l2_to_l1_server_response_first[578:515],
	       CASE_d_mmu_cachel2_to_l1_server_response_firs_ETC__q10,
	       d_mmu_cache$l2_to_l1_server_response_first[512:0],
	       1'd1 } ;
  assign enqDst_1_0_lat_0$wget =
	     { 1'd1,
	       CASE_x8218_0_n__read_addr8396_1_n__read_addr84_ETC__q21,
	       SEL_ARR_IF_propDstData_1_0_dummy2_1_read__92_T_ETC___d684 } ;
  assign llc_axi4_adapter_master_xactor_crg_wr_addr_full$EN_port1__write =
	     llc_axi4_adapter_master_xactor_crg_wr_addr_full &&
	     mem_master_awready ;
  assign llc_axi4_adapter_master_xactor_crg_wr_addr_full$port2__read =
	     !llc_axi4_adapter_master_xactor_crg_wr_addr_full$EN_port1__write &&
	     llc_axi4_adapter_master_xactor_crg_wr_addr_full ;
  assign llc_axi4_adapter_master_xactor_crg_wr_addr_full$port3__read =
	     CAN_FIRE_RL_llc_axi4_adapter_rl_handle_write_req ||
	     llc_axi4_adapter_master_xactor_crg_wr_addr_full$port2__read ;
  assign llc_axi4_adapter_master_xactor_crg_wr_data_full$EN_port1__write =
	     llc_axi4_adapter_master_xactor_crg_wr_data_full &&
	     mem_master_wready ;
  assign llc_axi4_adapter_master_xactor_crg_wr_data_full$port2__read =
	     !llc_axi4_adapter_master_xactor_crg_wr_data_full$EN_port1__write &&
	     llc_axi4_adapter_master_xactor_crg_wr_data_full ;
  assign llc_axi4_adapter_master_xactor_crg_wr_data_full$port3__read =
	     CAN_FIRE_RL_llc_axi4_adapter_rl_handle_write_req ||
	     llc_axi4_adapter_master_xactor_crg_wr_data_full$port2__read ;
  assign llc_axi4_adapter_master_xactor_crg_wr_resp_full$port2__read =
	     !CAN_FIRE_RL_llc_axi4_adapter_rl_discard_write_rsp &&
	     llc_axi4_adapter_master_xactor_crg_wr_resp_full ;
  assign llc_axi4_adapter_master_xactor_crg_wr_resp_full$EN_port2__write =
	     mem_master_bvalid &&
	     !llc_axi4_adapter_master_xactor_crg_wr_resp_full$port2__read ;
  assign llc_axi4_adapter_master_xactor_crg_wr_resp_full$port3__read =
	     llc_axi4_adapter_master_xactor_crg_wr_resp_full$EN_port2__write ||
	     llc_axi4_adapter_master_xactor_crg_wr_resp_full$port2__read ;
  assign llc_axi4_adapter_master_xactor_crg_rd_addr_full$EN_port1__write =
	     llc_axi4_adapter_master_xactor_crg_rd_addr_full &&
	     mem_master_arready ;
  assign llc_axi4_adapter_master_xactor_crg_rd_addr_full$port2__read =
	     !llc_axi4_adapter_master_xactor_crg_rd_addr_full$EN_port1__write &&
	     llc_axi4_adapter_master_xactor_crg_rd_addr_full ;
  assign llc_axi4_adapter_master_xactor_crg_rd_addr_full$port3__read =
	     CAN_FIRE_RL_llc_axi4_adapter_rl_handle_read_req ||
	     llc_axi4_adapter_master_xactor_crg_rd_addr_full$port2__read ;
  assign llc_axi4_adapter_master_xactor_crg_rd_data_full$port2__read =
	     !CAN_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps &&
	     llc_axi4_adapter_master_xactor_crg_rd_data_full ;
  assign llc_axi4_adapter_master_xactor_crg_rd_data_full$EN_port2__write =
	     mem_master_rvalid &&
	     !llc_axi4_adapter_master_xactor_crg_rd_data_full$port2__read ;
  assign llc_axi4_adapter_master_xactor_crg_rd_data_full$port3__read =
	     llc_axi4_adapter_master_xactor_crg_rd_data_full$EN_port2__write ||
	     llc_axi4_adapter_master_xactor_crg_rd_data_full$port2__read ;
  assign llc_axi4_adapter_ctr_wr_rsps_pending_crg$port0__write_1 =
	     llc_axi4_adapter_ctr_wr_rsps_pending_crg + 4'd1 ;
  assign llc_axi4_adapter_ctr_wr_rsps_pending_crg$port1__write_1 =
	     b__h20709 - 4'd1 ;
  assign llc_axi4_adapter_ctr_wr_rsps_pending_crg$port2__read =
	     CAN_FIRE_RL_llc_axi4_adapter_rl_discard_write_rsp ?
	       llc_axi4_adapter_ctr_wr_rsps_pending_crg$port1__write_1 :
	       b__h20709 ;

  // register cfg_verbosity
  assign cfg_verbosity$D_IN = 4'h0 ;
  assign cfg_verbosity$EN = 1'b0 ;

  // register enqDst_0_rl
  assign enqDst_0_rl$D_IN =
	     { !CAN_FIRE_RL_doEnq &&
	       IF_enqDst_0_lat_0_whas__06_THEN_enqDst_0_lat_0_ETC___d211,
	       CAN_FIRE_RL_doEnq ?
		 73'h0AAAAAAAAAAAAAAAAAA :
		 (NOT_enqDst_0_dummy2_0_read__87_88_OR_NOT_enqDs_ETC___d303 ?
		    enqDst_0_lat_0$wget[72:0] :
		    enqDst_0_rl[72:0]) } ;
  assign enqDst_0_rl$EN = 1'd1 ;

  // register enqDst_1_0_rl
  assign enqDst_1_0_rl$D_IN =
	     { !CAN_FIRE_RL_doEnq_1 &&
	       IF_enqDst_1_0_lat_0_whas__78_THEN_enqDst_1_0_l_ETC___d483,
	       IF_enqDst_1_0_lat_1_whas__75_THEN_enqDst_1_0_l_ETC___d522 } ;
  assign enqDst_1_0_rl$EN = 1'd1 ;

  // register llc_axi4_adapter_ctr_wr_rsps_pending_crg
  assign llc_axi4_adapter_ctr_wr_rsps_pending_crg$D_IN =
	     llc_axi4_adapter_ctr_wr_rsps_pending_crg$port2__read ;
  assign llc_axi4_adapter_ctr_wr_rsps_pending_crg$EN = 1'b1 ;

  // register llc_axi4_adapter_master_xactor_crg_rd_addr_full
  assign llc_axi4_adapter_master_xactor_crg_rd_addr_full$D_IN =
	     llc_axi4_adapter_master_xactor_crg_rd_addr_full$port3__read ;
  assign llc_axi4_adapter_master_xactor_crg_rd_addr_full$EN = 1'b1 ;

  // register llc_axi4_adapter_master_xactor_crg_rd_data_full
  assign llc_axi4_adapter_master_xactor_crg_rd_data_full$D_IN =
	     llc_axi4_adapter_master_xactor_crg_rd_data_full$port3__read ;
  assign llc_axi4_adapter_master_xactor_crg_rd_data_full$EN = 1'b1 ;

  // register llc_axi4_adapter_master_xactor_crg_wr_addr_full
  assign llc_axi4_adapter_master_xactor_crg_wr_addr_full$D_IN =
	     llc_axi4_adapter_master_xactor_crg_wr_addr_full$port3__read ;
  assign llc_axi4_adapter_master_xactor_crg_wr_addr_full$EN = 1'b1 ;

  // register llc_axi4_adapter_master_xactor_crg_wr_data_full
  assign llc_axi4_adapter_master_xactor_crg_wr_data_full$D_IN =
	     llc_axi4_adapter_master_xactor_crg_wr_data_full$port3__read ;
  assign llc_axi4_adapter_master_xactor_crg_wr_data_full$EN = 1'b1 ;

  // register llc_axi4_adapter_master_xactor_crg_wr_resp_full
  assign llc_axi4_adapter_master_xactor_crg_wr_resp_full$D_IN =
	     llc_axi4_adapter_master_xactor_crg_wr_resp_full$port3__read ;
  assign llc_axi4_adapter_master_xactor_crg_wr_resp_full$EN = 1'b1 ;

  // register llc_axi4_adapter_master_xactor_rg_rd_addr
  assign llc_axi4_adapter_master_xactor_rg_rd_addr$D_IN =
	     { 16'd0, mem_req_rd_addr_araddr__h20827, 29'd851968 } ;
  assign llc_axi4_adapter_master_xactor_rg_rd_addr$EN =
	     CAN_FIRE_RL_llc_axi4_adapter_rl_handle_read_req ;

  // register llc_axi4_adapter_master_xactor_rg_rd_data
  assign llc_axi4_adapter_master_xactor_rg_rd_data$D_IN =
	     { mem_master_rid,
	       mem_master_rdata,
	       mem_master_rresp,
	       mem_master_rlast } ;
  assign llc_axi4_adapter_master_xactor_rg_rd_data$EN = 1'd1 ;

  // register llc_axi4_adapter_master_xactor_rg_wr_addr
  assign llc_axi4_adapter_master_xactor_rg_wr_addr$D_IN =
	     { 16'd0, mem_req_wr_addr_awaddr__h22953, 29'd851968 } ;
  assign llc_axi4_adapter_master_xactor_rg_wr_addr$EN =
	     CAN_FIRE_RL_llc_axi4_adapter_rl_handle_write_req ;

  // register llc_axi4_adapter_master_xactor_rg_wr_data
  assign llc_axi4_adapter_master_xactor_rg_wr_data$D_IN =
	     { data64__h22868, strb8__h22869, 1'd1 } ;
  assign llc_axi4_adapter_master_xactor_rg_wr_data$EN =
	     CAN_FIRE_RL_llc_axi4_adapter_rl_handle_write_req ;

  // register llc_axi4_adapter_master_xactor_rg_wr_resp
  assign llc_axi4_adapter_master_xactor_rg_wr_resp$D_IN =
	     { mem_master_bid, mem_master_bresp } ;
  assign llc_axi4_adapter_master_xactor_rg_wr_resp$EN =
	     mem_master_bvalid &&
	     !llc_axi4_adapter_master_xactor_crg_wr_resp_full$port2__read ;

  // register llc_axi4_adapter_rg_AXI4_error
  assign llc_axi4_adapter_rg_AXI4_error$D_IN = 1'd1 ;
  assign llc_axi4_adapter_rg_AXI4_error$EN =
	     WILL_FIRE_RL_llc_axi4_adapter_rl_discard_write_rsp &&
	     llc_axi4_adapter_master_xactor_rg_wr_resp[1:0] != 2'b0 ;

  // register llc_axi4_adapter_rg_cline
  assign llc_axi4_adapter_rg_cline$D_IN = new_cline__h21399 ;
  assign llc_axi4_adapter_rg_cline$EN =
	     CAN_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps ;

  // register llc_axi4_adapter_rg_ddr4_ready
  assign llc_axi4_adapter_rg_ddr4_ready$D_IN = 1'd1 ;
  assign llc_axi4_adapter_rg_ddr4_ready$EN = EN_ma_ddr4_ready ;

  // register llc_axi4_adapter_rg_rd_req_beat
  assign llc_axi4_adapter_rg_rd_req_beat$D_IN =
	     llc_axi4_adapter_rg_rd_req_beat + 3'd1 ;
  assign llc_axi4_adapter_rg_rd_req_beat$EN =
	     CAN_FIRE_RL_llc_axi4_adapter_rl_handle_read_req ;

  // register llc_axi4_adapter_rg_rd_rsp_beat
  assign llc_axi4_adapter_rg_rd_rsp_beat$D_IN =
	     llc_axi4_adapter_rg_rd_rsp_beat + 3'd1 ;
  assign llc_axi4_adapter_rg_rd_rsp_beat$EN =
	     CAN_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps ;

  // register llc_axi4_adapter_rg_wr_req_beat
  assign llc_axi4_adapter_rg_wr_req_beat$D_IN =
	     llc_axi4_adapter_rg_wr_req_beat + 3'd1 ;
  assign llc_axi4_adapter_rg_wr_req_beat$EN =
	     CAN_FIRE_RL_llc_axi4_adapter_rl_handle_write_req ;

  // register llc_axi4_adapter_rg_wr_rsp_beat
  assign llc_axi4_adapter_rg_wr_rsp_beat$D_IN =
	     llc_axi4_adapter_rg_wr_rsp_beat + 3'd1 ;
  assign llc_axi4_adapter_rg_wr_rsp_beat$EN =
	     CAN_FIRE_RL_llc_axi4_adapter_rl_discard_write_rsp ;

  // register propDstData_0_rl
  assign propDstData_0_rl$D_IN =
	     CAN_FIRE_RL_srcPropose ?
	       propDstData_0_lat_0$wget :
	       propDstData_0_rl ;
  assign propDstData_0_rl$EN = 1'd1 ;

  // register propDstData_1_0_rl
  assign propDstData_1_0_rl$D_IN =
	     { IF_propDstData_1_0_lat_0_whas__02_THEN_propDst_ETC___d407,
	       IF_propDstData_1_0_lat_0_whas__02_THEN_propDst_ETC___d412,
	       CAN_FIRE_RL_srcPropose_2 ?
		 propDstData_1_0_lat_0$wget[513] :
		 propDstData_1_0_rl[513],
	       CAN_FIRE_RL_srcPropose_2 ?
		 propDstData_1_0_lat_0$wget[512:1] :
		 propDstData_1_0_rl[512:1],
	       IF_propDstData_1_0_lat_0_whas__02_THEN_propDst_ETC___d433 } ;
  assign propDstData_1_0_rl$EN = 1'd1 ;

  // register propDstData_1_1_rl
  assign propDstData_1_1_rl$D_IN =
	     { IF_propDstData_1_1_lat_0_whas__40_THEN_propDst_ETC___d445,
	       IF_propDstData_1_1_lat_0_whas__40_THEN_propDst_ETC___d450,
	       CAN_FIRE_RL_srcPropose_3 ?
		 propDstData_1_1_lat_0$wget[513] :
		 propDstData_1_1_rl[513],
	       CAN_FIRE_RL_srcPropose_3 ?
		 propDstData_1_1_lat_0$wget[512:1] :
		 propDstData_1_1_rl[512:1],
	       IF_propDstData_1_1_lat_0_whas__40_THEN_propDst_ETC___d471 } ;
  assign propDstData_1_1_rl$EN = 1'd1 ;

  // register propDstData_1_rl
  assign propDstData_1_rl$D_IN =
	     CAN_FIRE_RL_srcPropose_1 ?
	       propDstData_1_lat_0$wget :
	       propDstData_1_rl ;
  assign propDstData_1_rl$EN = 1'd1 ;

  // register propDstIdx_0_rl
  assign propDstIdx_0_rl$D_IN =
	     !propDstIdx_0_lat_1$whas &&
	     IF_propDstIdx_0_lat_0_whas__77_THEN_propDstIdx_ETC___d180 ;
  assign propDstIdx_0_rl$EN = 1'd1 ;

  // register propDstIdx_1_0_rl
  assign propDstIdx_1_0_rl$D_IN =
	     !propDstIdx_1_0_lat_1$whas &&
	     IF_propDstIdx_1_0_lat_0_whas__87_THEN_propDstI_ETC___d390 ;
  assign propDstIdx_1_0_rl$EN = 1'd1 ;

  // register propDstIdx_1_1_rl
  assign propDstIdx_1_1_rl$D_IN =
	     !propDstIdx_1_1_lat_1$whas &&
	     IF_propDstIdx_1_1_lat_0_whas__94_THEN_propDstI_ETC___d397 ;
  assign propDstIdx_1_1_rl$EN = 1'd1 ;

  // register propDstIdx_1_rl
  assign propDstIdx_1_rl$D_IN =
	     !propDstIdx_1_lat_1$whas &&
	     IF_propDstIdx_1_lat_0_whas__84_THEN_propDstIdx_ETC___d187 ;
  assign propDstIdx_1_rl$EN = 1'd1 ;

  // register rg_state
  always@(EN_server_reset_request_put or
	  WILL_FIRE_RL_rl_reset or WILL_FIRE_RL_rl_reset_complete)
  begin
    case (1'b1) // synopsys parallel_case
      EN_server_reset_request_put: rg_state$D_IN = 2'd0;
      WILL_FIRE_RL_rl_reset: rg_state$D_IN = 2'd1;
      WILL_FIRE_RL_rl_reset_complete: rg_state$D_IN = 2'd2;
      default: rg_state$D_IN = 2'b10 /* unspecified value */ ;
    endcase
  end
  assign rg_state$EN =
	     EN_server_reset_request_put || WILL_FIRE_RL_rl_reset ||
	     WILL_FIRE_RL_rl_reset_complete ;

  // register srcRR_0
  assign srcRR_0$D_IN = srcRR_0 + 1'd1 ;
  assign srcRR_0$EN =
	     NOT_enqDst_0_dummy2_0_read__87_88_OR_NOT_enqDs_ETC___d303 ;

  // register srcRR_1_0
  assign srcRR_1_0$D_IN = srcRR_1_0 + 1'd1 ;
  assign srcRR_1_0$EN =
	     NOT_enqDst_1_0_dummy2_0_read__75_76_OR_NOT_enq_ETC___d591 ;

  // submodule d_mmu_cache
  assign d_mmu_cache$flush_server_request_put = 1'b0 ;
  assign d_mmu_cache$imem_pte_writeback_p_put =
	     i_mmu_cache$pte_writeback_g_get ;
  assign d_mmu_cache$imem_ptw_server_request_put =
	     i_mmu_cache$ptw_client_request_get ;
  assign d_mmu_cache$l1_to_l2_client_response_enq_x =
	     { llc$to_child_toC_first[582:519],
	       CASE_llcto_child_toC_first_BITS_518_TO_517_0__ETC__q23,
	       llc$to_child_toC_first[515:3] } ;
  assign d_mmu_cache$l2_to_l1_server_request_enq_x =
	     { llc$to_child_toC_first[66:3],
	       CASE_llcto_child_toC_first_BITS_2_TO_1_0_llc_ETC__q22 } ;
  assign d_mmu_cache$ma_req_amo_funct7 = dmem_req_amo_funct7 ;
  assign d_mmu_cache$ma_req_f3 = dmem_req_f3 ;
  assign d_mmu_cache$ma_req_mstatus_MXR = dmem_req_mstatus_MXR ;
  assign d_mmu_cache$ma_req_op = dmem_req_op ;
  assign d_mmu_cache$ma_req_priv = dmem_req_priv ;
  assign d_mmu_cache$ma_req_satp = dmem_req_satp ;
  assign d_mmu_cache$ma_req_sstatus_SUM = dmem_req_sstatus_SUM ;
  assign d_mmu_cache$ma_req_st_value = dmem_req_store_value ;
  assign d_mmu_cache$ma_req_va = dmem_req_addr ;
  assign d_mmu_cache$mmio_client_response_put =
	     mmio_axi4_adapter$v_mmio_server_1_response_get ;
  assign d_mmu_cache$EN_ma_req = EN_dmem_req ;
  assign d_mmu_cache$EN_flush_server_request_put = 1'b0 ;
  assign d_mmu_cache$EN_flush_server_response_get = 1'b0 ;
  assign d_mmu_cache$EN_tlb_flush = EN_sfence_vma_server_request_put ;
  assign d_mmu_cache$EN_imem_ptw_server_request_put =
	     CAN_FIRE_RL_ClientServerRequest ;
  assign d_mmu_cache$EN_imem_ptw_server_response_get =
	     CAN_FIRE_RL_ClientServerResponse ;
  assign d_mmu_cache$EN_imem_pte_writeback_p_put =
	     CAN_FIRE_RL_mkConnectionGetPut ;
  assign d_mmu_cache$EN_l1_to_l2_client_request_deq =
	     CAN_FIRE_RL_srcPropose_1 ;
  assign d_mmu_cache$EN_l1_to_l2_client_response_enq = CAN_FIRE_RL_sendPRs_1 ;
  assign d_mmu_cache$EN_l2_to_l1_server_request_enq = CAN_FIRE_RL_sendPRq_1 ;
  assign d_mmu_cache$EN_l2_to_l1_server_response_deq =
	     CAN_FIRE_RL_srcPropose_3 ;
  assign d_mmu_cache$EN_mmio_client_request_get =
	     CAN_FIRE_RL_ClientServerRequest_2 ;
  assign d_mmu_cache$EN_mmio_client_response_put =
	     CAN_FIRE_RL_ClientServerResponse_2 ;

  // submodule enqDst_0_dummy2_0
  assign enqDst_0_dummy2_0$D_IN = 1'd1 ;
  assign enqDst_0_dummy2_0$EN =
	     NOT_enqDst_0_dummy2_0_read__87_88_OR_NOT_enqDs_ETC___d303 ;

  // submodule enqDst_0_dummy2_1
  assign enqDst_0_dummy2_1$D_IN = 1'd1 ;
  assign enqDst_0_dummy2_1$EN = CAN_FIRE_RL_doEnq ;

  // submodule enqDst_1_0_dummy2_0
  assign enqDst_1_0_dummy2_0$D_IN = 1'd1 ;
  assign enqDst_1_0_dummy2_0$EN =
	     NOT_enqDst_1_0_dummy2_0_read__75_76_OR_NOT_enq_ETC___d591 ;

  // submodule enqDst_1_0_dummy2_1
  assign enqDst_1_0_dummy2_1$D_IN = 1'd1 ;
  assign enqDst_1_0_dummy2_1$EN = CAN_FIRE_RL_doEnq_1 ;

  // submodule f_reset_rsps
  assign f_reset_rsps$ENQ = f_reset_rsps$FULL_N && rg_state == 2'd1 ;
  assign f_reset_rsps$DEQ = EN_server_reset_response_get ;
  assign f_reset_rsps$CLR = 1'b0 ;

  // submodule i_mmu_cache
  assign i_mmu_cache$flush_server_request_put = 1'b0 ;
  assign i_mmu_cache$l1_to_l2_client_response_enq_x =
	     { llc$to_child_toC_first[582:519],
	       CASE_llcto_child_toC_first_BITS_518_TO_517_0__ETC__q23,
	       llc$to_child_toC_first[515:3] } ;
  assign i_mmu_cache$l2_to_l1_server_request_enq_x =
	     { llc$to_child_toC_first[66:3],
	       CASE_llcto_child_toC_first_BITS_2_TO_1_0_llc_ETC__q22 } ;
  assign i_mmu_cache$ma_req_mstatus_MXR = imem_req_mstatus_MXR ;
  assign i_mmu_cache$ma_req_priv = imem_req_priv ;
  assign i_mmu_cache$ma_req_satp = imem_req_satp ;
  assign i_mmu_cache$ma_req_sstatus_SUM = imem_req_sstatus_SUM ;
  assign i_mmu_cache$ma_req_va = imem_req_addr ;
  assign i_mmu_cache$mmio_client_response_put =
	     mmio_axi4_adapter$v_mmio_server_0_response_get ;
  assign i_mmu_cache$ptw_client_response_put =
	     d_mmu_cache$imem_ptw_server_response_get ;
  assign i_mmu_cache$EN_ma_req = EN_imem_req ;
  assign i_mmu_cache$EN_flush_server_request_put = 1'b0 ;
  assign i_mmu_cache$EN_flush_server_response_get = 1'b0 ;
  assign i_mmu_cache$EN_tlb_flush = EN_sfence_vma_server_request_put ;
  assign i_mmu_cache$EN_ptw_client_request_get =
	     CAN_FIRE_RL_ClientServerRequest ;
  assign i_mmu_cache$EN_ptw_client_response_put =
	     CAN_FIRE_RL_ClientServerResponse ;
  assign i_mmu_cache$EN_pte_writeback_g_get = CAN_FIRE_RL_mkConnectionGetPut ;
  assign i_mmu_cache$EN_l1_to_l2_client_request_deq = CAN_FIRE_RL_srcPropose ;
  assign i_mmu_cache$EN_l1_to_l2_client_response_enq = CAN_FIRE_RL_sendPRs ;
  assign i_mmu_cache$EN_l2_to_l1_server_request_enq = CAN_FIRE_RL_sendPRq ;
  assign i_mmu_cache$EN_l2_to_l1_server_response_deq =
	     CAN_FIRE_RL_srcPropose_2 ;
  assign i_mmu_cache$EN_mmio_client_request_get =
	     CAN_FIRE_RL_ClientServerRequest_1 ;
  assign i_mmu_cache$EN_mmio_client_response_put =
	     CAN_FIRE_RL_ClientServerResponse_1 ;

  // submodule llc
  assign llc$dma_memReq_enq_x =
	     WILL_FIRE_RL_llc_dma_axi4_adapter_rl_wr_req ?
	       MUX_llc$dma_memReq_enq_1__VAL_1 :
	       MUX_llc$dma_memReq_enq_1__VAL_2 ;
  assign llc$perf_req_r = 4'h0 ;
  assign llc$perf_setStatus_doStats = 1'b0 ;
  assign llc$to_child_rqFromC_enq_x =
	     NOT_enqDst_0_dummy2_0_read__87_88_OR_NOT_enqDs_ETC___d303 ?
	       enqDst_0_lat_0$wget[72:0] :
	       enqDst_0_rl[72:0] ;
  assign llc$to_child_rsFromC_enq_x =
	     { IF_enqDst_1_0_lat_0_whas__78_THEN_enqDst_1_0_l_ETC___d493,
	       IF_enqDst_1_0_lat_0_whas__78_THEN_enqDst_1_0_l_ETC___d498,
	       IF_enqDst_1_0_lat_0_whas__78_THEN_enqDst_1_0_l_ETC___d503,
	       IF_enqDst_1_0_lat_0_whas__78_THEN_enqDst_1_0_l_ETC___d513,
	       IF_enqDst_1_0_lat_0_whas__78_THEN_enqDst_1_0_l_ETC___d519 } ;
  assign llc$to_mem_rsFromM_enq_x =
	     { new_cline__h21399,
	       llc_axi4_adapter_f_pending_reads$D_OUT[4:0] } ;
  assign llc$EN_to_child_rsFromC_enq = CAN_FIRE_RL_doEnq_1 ;
  assign llc$EN_to_child_rqFromC_enq = CAN_FIRE_RL_doEnq ;
  assign llc$EN_to_child_toC_deq =
	     WILL_FIRE_RL_sendPRs_1 || WILL_FIRE_RL_sendPRq_1 ||
	     WILL_FIRE_RL_sendPRs ||
	     WILL_FIRE_RL_sendPRq ;
  assign llc$EN_dma_memReq_enq =
	     WILL_FIRE_RL_llc_dma_axi4_adapter_rl_wr_req ||
	     WILL_FIRE_RL_llc_dma_axi4_adapter_rl_rd_req ;
  assign llc$EN_dma_respLd_deq = CAN_FIRE_RL_llc_dma_axi4_adapter_rl_rd_rsp ;
  assign llc$EN_dma_respSt_deq = CAN_FIRE_RL_llc_dma_axi4_adapter_rl_wr_rsp ;
  assign llc$EN_to_mem_toM_deq =
	     WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req &&
	     llc_axi4_adapter_rg_rd_req_beat == 3'd7 ||
	     WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req &&
	     llc_axi4_adapter_rg_wr_req_beat == 3'd7 ;
  assign llc$EN_to_mem_rsFromM_enq =
	     WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps &&
	     llc_axi4_adapter_rg_rd_rsp_beat == 3'd7 ;
  assign llc$EN_cRqStuck_get = 1'b0 ;
  assign llc$EN_perf_setStatus = 1'b0 ;
  assign llc$EN_perf_req = 1'b0 ;
  assign llc$EN_perf_resp = 1'b0 ;

  // submodule llc_axi4_adapter_f_pending_reads
  assign llc_axi4_adapter_f_pending_reads$D_IN = llc$to_mem_toM_first[68:0] ;
  assign llc_axi4_adapter_f_pending_reads$ENQ =
	     WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req &&
	     llc_axi4_adapter_rg_rd_req_beat == 3'd0 ;
  assign llc_axi4_adapter_f_pending_reads$DEQ =
	     WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps &&
	     llc_axi4_adapter_rg_rd_rsp_beat == 3'd7 ;
  assign llc_axi4_adapter_f_pending_reads$CLR = 1'b0 ;

  // submodule llc_axi4_adapter_f_pending_writes
  assign llc_axi4_adapter_f_pending_writes$D_IN =
	     llc$to_mem_toM_first[639:0] ;
  assign llc_axi4_adapter_f_pending_writes$ENQ =
	     WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req &&
	     llc_axi4_adapter_rg_wr_req_beat == 3'd0 ;
  assign llc_axi4_adapter_f_pending_writes$DEQ =
	     WILL_FIRE_RL_llc_axi4_adapter_rl_discard_write_rsp &&
	     llc_axi4_adapter_rg_wr_rsp_beat == 3'd7 ;
  assign llc_axi4_adapter_f_pending_writes$CLR = 1'b0 ;

  // submodule llc_dma_axi4_adapter_axi4_slave_xactor_f_rd_addr
  assign llc_dma_axi4_adapter_axi4_slave_xactor_f_rd_addr$D_IN =
	     { dma_server_arid,
	       dma_server_araddr,
	       dma_server_arlen,
	       dma_server_arsize,
	       dma_server_arburst,
	       dma_server_arlock,
	       dma_server_arcache,
	       dma_server_arprot,
	       dma_server_arqos,
	       dma_server_arregion } ;
  assign llc_dma_axi4_adapter_axi4_slave_xactor_f_rd_addr$ENQ =
	     dma_server_arvalid &&
	     llc_dma_axi4_adapter_axi4_slave_xactor_f_rd_addr$FULL_N ;
  assign llc_dma_axi4_adapter_axi4_slave_xactor_f_rd_addr$DEQ =
	     WILL_FIRE_RL_llc_dma_axi4_adapter_rl_rd_req ;
  assign llc_dma_axi4_adapter_axi4_slave_xactor_f_rd_addr$CLR = 1'b0 ;

  // submodule llc_dma_axi4_adapter_axi4_slave_xactor_f_rd_data
  assign llc_dma_axi4_adapter_axi4_slave_xactor_f_rd_data$D_IN =
	     { llc$dma_respLd_first[15:0],
	       llc$dma_respLd_first[527:16],
	       3'd1 } ;
  assign llc_dma_axi4_adapter_axi4_slave_xactor_f_rd_data$ENQ =
	     CAN_FIRE_RL_llc_dma_axi4_adapter_rl_rd_rsp ;
  assign llc_dma_axi4_adapter_axi4_slave_xactor_f_rd_data$DEQ =
	     dma_server_rready &&
	     llc_dma_axi4_adapter_axi4_slave_xactor_f_rd_data$EMPTY_N ;
  assign llc_dma_axi4_adapter_axi4_slave_xactor_f_rd_data$CLR = 1'b0 ;

  // submodule llc_dma_axi4_adapter_axi4_slave_xactor_f_wr_addr
  assign llc_dma_axi4_adapter_axi4_slave_xactor_f_wr_addr$D_IN =
	     { dma_server_awid,
	       dma_server_awaddr,
	       dma_server_awlen,
	       dma_server_awsize,
	       dma_server_awburst,
	       dma_server_awlock,
	       dma_server_awcache,
	       dma_server_awprot,
	       dma_server_awqos,
	       dma_server_awregion } ;
  assign llc_dma_axi4_adapter_axi4_slave_xactor_f_wr_addr$ENQ =
	     dma_server_awvalid &&
	     llc_dma_axi4_adapter_axi4_slave_xactor_f_wr_addr$FULL_N ;
  assign llc_dma_axi4_adapter_axi4_slave_xactor_f_wr_addr$DEQ =
	     CAN_FIRE_RL_llc_dma_axi4_adapter_rl_wr_req ;
  assign llc_dma_axi4_adapter_axi4_slave_xactor_f_wr_addr$CLR = 1'b0 ;

  // submodule llc_dma_axi4_adapter_axi4_slave_xactor_f_wr_data
  assign llc_dma_axi4_adapter_axi4_slave_xactor_f_wr_data$D_IN =
	     { dma_server_wdata, dma_server_wstrb, dma_server_wlast } ;
  assign llc_dma_axi4_adapter_axi4_slave_xactor_f_wr_data$ENQ =
	     dma_server_wvalid &&
	     llc_dma_axi4_adapter_axi4_slave_xactor_f_wr_data$FULL_N ;
  assign llc_dma_axi4_adapter_axi4_slave_xactor_f_wr_data$DEQ =
	     CAN_FIRE_RL_llc_dma_axi4_adapter_rl_wr_req ;
  assign llc_dma_axi4_adapter_axi4_slave_xactor_f_wr_data$CLR = 1'b0 ;

  // submodule llc_dma_axi4_adapter_axi4_slave_xactor_f_wr_resp
  assign llc_dma_axi4_adapter_axi4_slave_xactor_f_wr_resp$D_IN =
	     { llc$dma_respSt_first, 2'b0 } ;
  assign llc_dma_axi4_adapter_axi4_slave_xactor_f_wr_resp$ENQ =
	     CAN_FIRE_RL_llc_dma_axi4_adapter_rl_wr_rsp ;
  assign llc_dma_axi4_adapter_axi4_slave_xactor_f_wr_resp$DEQ =
	     dma_server_bready &&
	     llc_dma_axi4_adapter_axi4_slave_xactor_f_wr_resp$EMPTY_N ;
  assign llc_dma_axi4_adapter_axi4_slave_xactor_f_wr_resp$CLR = 1'b0 ;

  // submodule mmio_axi4_adapter
  assign mmio_axi4_adapter$mem_master_arready = imem_master_arready ;
  assign mmio_axi4_adapter$mem_master_awready = imem_master_awready ;
  assign mmio_axi4_adapter$mem_master_bid = imem_master_bid ;
  assign mmio_axi4_adapter$mem_master_bresp = imem_master_bresp ;
  assign mmio_axi4_adapter$mem_master_bvalid = imem_master_bvalid ;
  assign mmio_axi4_adapter$mem_master_rdata = imem_master_rdata ;
  assign mmio_axi4_adapter$mem_master_rid = imem_master_rid ;
  assign mmio_axi4_adapter$mem_master_rlast = imem_master_rlast ;
  assign mmio_axi4_adapter$mem_master_rresp = imem_master_rresp ;
  assign mmio_axi4_adapter$mem_master_rvalid = imem_master_rvalid ;
  assign mmio_axi4_adapter$mem_master_wready = imem_master_wready ;
  assign mmio_axi4_adapter$v_mmio_server_0_request_put =
	     i_mmu_cache$mmio_client_request_get ;
  assign mmio_axi4_adapter$v_mmio_server_1_request_put =
	     d_mmu_cache$mmio_client_request_get ;
  assign mmio_axi4_adapter$EN_v_mmio_server_0_request_put =
	     CAN_FIRE_RL_ClientServerRequest_1 ;
  assign mmio_axi4_adapter$EN_v_mmio_server_0_response_get =
	     CAN_FIRE_RL_ClientServerResponse_1 ;
  assign mmio_axi4_adapter$EN_v_mmio_server_1_request_put =
	     CAN_FIRE_RL_ClientServerRequest_2 ;
  assign mmio_axi4_adapter$EN_v_mmio_server_1_response_get =
	     CAN_FIRE_RL_ClientServerResponse_2 ;

  // submodule propDstData_0_dummy2_0
  assign propDstData_0_dummy2_0$D_IN = 1'd1 ;
  assign propDstData_0_dummy2_0$EN = CAN_FIRE_RL_srcPropose ;

  // submodule propDstData_0_dummy2_1
  assign propDstData_0_dummy2_1$D_IN = 1'b0 ;
  assign propDstData_0_dummy2_1$EN = 1'b0 ;

  // submodule propDstData_1_0_dummy2_0
  assign propDstData_1_0_dummy2_0$D_IN = 1'd1 ;
  assign propDstData_1_0_dummy2_0$EN = CAN_FIRE_RL_srcPropose_2 ;

  // submodule propDstData_1_0_dummy2_1
  assign propDstData_1_0_dummy2_1$D_IN = 1'b0 ;
  assign propDstData_1_0_dummy2_1$EN = 1'b0 ;

  // submodule propDstData_1_1_dummy2_0
  assign propDstData_1_1_dummy2_0$D_IN = 1'd1 ;
  assign propDstData_1_1_dummy2_0$EN = CAN_FIRE_RL_srcPropose_3 ;

  // submodule propDstData_1_1_dummy2_1
  assign propDstData_1_1_dummy2_1$D_IN = 1'b0 ;
  assign propDstData_1_1_dummy2_1$EN = 1'b0 ;

  // submodule propDstData_1_dummy2_0
  assign propDstData_1_dummy2_0$D_IN = 1'd1 ;
  assign propDstData_1_dummy2_0$EN = CAN_FIRE_RL_srcPropose_1 ;

  // submodule propDstData_1_dummy2_1
  assign propDstData_1_dummy2_1$D_IN = 1'b0 ;
  assign propDstData_1_dummy2_1$EN = 1'b0 ;

  // submodule propDstIdx_0_dummy2_0
  assign propDstIdx_0_dummy2_0$D_IN = 1'd1 ;
  assign propDstIdx_0_dummy2_0$EN = CAN_FIRE_RL_srcPropose ;

  // submodule propDstIdx_0_dummy2_1
  assign propDstIdx_0_dummy2_1$D_IN = 1'd1 ;
  assign propDstIdx_0_dummy2_1$EN = propDstIdx_0_lat_1$whas ;

  // submodule propDstIdx_1_0_dummy2_0
  assign propDstIdx_1_0_dummy2_0$D_IN = 1'd1 ;
  assign propDstIdx_1_0_dummy2_0$EN = CAN_FIRE_RL_srcPropose_2 ;

  // submodule propDstIdx_1_0_dummy2_1
  assign propDstIdx_1_0_dummy2_1$D_IN = 1'd1 ;
  assign propDstIdx_1_0_dummy2_1$EN = propDstIdx_1_0_lat_1$whas ;

  // submodule propDstIdx_1_1_dummy2_0
  assign propDstIdx_1_1_dummy2_0$D_IN = 1'd1 ;
  assign propDstIdx_1_1_dummy2_0$EN = CAN_FIRE_RL_srcPropose_3 ;

  // submodule propDstIdx_1_1_dummy2_1
  assign propDstIdx_1_1_dummy2_1$D_IN = 1'd1 ;
  assign propDstIdx_1_1_dummy2_1$EN = propDstIdx_1_1_lat_1$whas ;

  // submodule propDstIdx_1_dummy2_0
  assign propDstIdx_1_dummy2_0$D_IN = 1'd1 ;
  assign propDstIdx_1_dummy2_0$EN = CAN_FIRE_RL_srcPropose_1 ;

  // submodule propDstIdx_1_dummy2_1
  assign propDstIdx_1_dummy2_1$D_IN = 1'd1 ;
  assign propDstIdx_1_dummy2_1$EN = propDstIdx_1_lat_1$whas ;

  // submodule soc_map
  assign soc_map$m_is_IO_addr_addr = 64'h0 ;
  assign soc_map$m_is_mem_addr_addr = 64'h0 ;
  assign soc_map$m_is_near_mem_IO_addr_addr = 64'h0 ;

  // remaining internal signals
  assign IF_NOT_propDstIdx_0_dummy2_1_read__30_31_OR_IF_ETC___d301 =
	     NOT_propDstIdx_0_dummy2_1_read__30_31_OR_IF_pr_ETC___d300 ?
	       propDstIdx_1_dummy2_1$Q_OUT &&
	       IF_propDstIdx_1_lat_0_whas__84_THEN_propDstIdx_ETC___d187 :
	       propDstIdx_0_dummy2_1$Q_OUT &&
	       IF_propDstIdx_0_lat_0_whas__77_THEN_propDstIdx_ETC___d180 ;
  assign IF_NOT_propDstIdx_1_0_dummy2_1_read__30_31_OR__ETC___d589 =
	     NOT_propDstIdx_1_0_dummy2_1_read__30_31_OR_IF__ETC___d588 ?
	       propDstIdx_1_1_dummy2_1$Q_OUT &&
	       IF_propDstIdx_1_1_lat_0_whas__94_THEN_propDstI_ETC___d397 :
	       propDstIdx_1_0_dummy2_1$Q_OUT &&
	       IF_propDstIdx_1_0_lat_0_whas__87_THEN_propDstI_ETC___d390 ;
  assign IF_SEL_ARR_propDstIdx_0_dummy2_1_read__30_AND__ETC___d373 =
	     SEL_ARR_propDstIdx_0_dummy2_1_read__30_AND_IF__ETC___d297 ?
	       !srcRR_0 :
	       propDstIdx_0_dummy2_1$Q_OUT &&
	       IF_propDstIdx_0_lat_0_whas__77_THEN_propDstIdx_ETC___d180 ;
  assign IF_SEL_ARR_propDstIdx_1_0_dummy2_1_read__30_AN_ETC___d689 =
	     SEL_ARR_propDstIdx_1_0_dummy2_1_read__30_AND_I_ETC___d585 ?
	       !srcRR_1_0 :
	       propDstIdx_1_0_dummy2_1$Q_OUT &&
	       IF_propDstIdx_1_0_lat_0_whas__87_THEN_propDstI_ETC___d390 ;
  assign IF_enqDst_0_lat_0_whas__06_THEN_enqDst_0_lat_0_ETC___d211 =
	     NOT_enqDst_0_dummy2_0_read__87_88_OR_NOT_enqDs_ETC___d303 ?
	       enqDst_0_lat_0$wget[73] :
	       enqDst_0_rl[73] ;
  assign IF_enqDst_1_0_lat_0_whas__78_THEN_enqDst_1_0_l_ETC___d483 =
	     NOT_enqDst_1_0_dummy2_0_read__75_76_OR_NOT_enq_ETC___d591 ?
	       enqDst_1_0_lat_0$wget[580] :
	       enqDst_1_0_rl[580] ;
  assign IF_enqDst_1_0_lat_0_whas__78_THEN_enqDst_1_0_l_ETC___d493 =
	     NOT_enqDst_1_0_dummy2_0_read__75_76_OR_NOT_enq_ETC___d591 ?
	       enqDst_1_0_lat_0$wget[579:516] :
	       enqDst_1_0_rl[579:516] ;
  assign IF_enqDst_1_0_lat_0_whas__78_THEN_enqDst_1_0_l_ETC___d498 =
	     NOT_enqDst_1_0_dummy2_0_read__75_76_OR_NOT_enq_ETC___d591 ?
	       enqDst_1_0_lat_0$wget[515:514] :
	       enqDst_1_0_rl[515:514] ;
  assign IF_enqDst_1_0_lat_0_whas__78_THEN_enqDst_1_0_l_ETC___d503 =
	     NOT_enqDst_1_0_dummy2_0_read__75_76_OR_NOT_enq_ETC___d591 ?
	       enqDst_1_0_lat_0$wget[513] :
	       enqDst_1_0_rl[513] ;
  assign IF_enqDst_1_0_lat_0_whas__78_THEN_enqDst_1_0_l_ETC___d513 =
	     NOT_enqDst_1_0_dummy2_0_read__75_76_OR_NOT_enq_ETC___d591 ?
	       enqDst_1_0_lat_0$wget[512:1] :
	       enqDst_1_0_rl[512:1] ;
  assign IF_enqDst_1_0_lat_0_whas__78_THEN_enqDst_1_0_l_ETC___d519 =
	     NOT_enqDst_1_0_dummy2_0_read__75_76_OR_NOT_enq_ETC___d591 ?
	       enqDst_1_0_lat_0$wget[0] :
	       enqDst_1_0_rl[0] ;
  assign IF_enqDst_1_0_lat_1_whas__75_THEN_enqDst_1_0_l_ETC___d521 =
	     { CAN_FIRE_RL_doEnq_1 ||
	       IF_enqDst_1_0_lat_0_whas__78_THEN_enqDst_1_0_l_ETC___d503,
	       CAN_FIRE_RL_doEnq_1 ?
		 512'h55555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555 :
		 IF_enqDst_1_0_lat_0_whas__78_THEN_enqDst_1_0_l_ETC___d513,
	       x__h62982 } ;
  assign IF_enqDst_1_0_lat_1_whas__75_THEN_enqDst_1_0_l_ETC___d522 =
	     { CAN_FIRE_RL_doEnq_1 ?
		 64'hAAAAAAAAAAAAAAAA :
		 IF_enqDst_1_0_lat_0_whas__78_THEN_enqDst_1_0_l_ETC___d493,
	       CAN_FIRE_RL_doEnq_1 ?
		 2'b10 :
		 IF_enqDst_1_0_lat_0_whas__78_THEN_enqDst_1_0_l_ETC___d498,
	       IF_enqDst_1_0_lat_1_whas__75_THEN_enqDst_1_0_l_ETC___d521 } ;
  assign IF_propDstData_0_dummy2_1_read__04_THEN_IF_pro_ETC___d320 =
	     propDstData_0_dummy2_1$Q_OUT ?
	       (CAN_FIRE_RL_srcPropose ?
		  propDstData_0_lat_0$wget[8:7] :
		  propDstData_0_rl[8:7]) :
	       2'd0 ;
  assign IF_propDstData_0_dummy2_1_read__04_THEN_IF_pro_ETC___d330 =
	     propDstData_0_dummy2_1$Q_OUT ?
	       (CAN_FIRE_RL_srcPropose ?
		  propDstData_0_lat_0$wget[6:5] :
		  propDstData_0_rl[6:5]) :
	       2'd0 ;
  assign IF_propDstData_1_0_lat_0_whas__02_THEN_propDst_ETC___d407 =
	     CAN_FIRE_RL_srcPropose_2 ?
	       propDstData_1_0_lat_0$wget[579:516] :
	       propDstData_1_0_rl[579:516] ;
  assign IF_propDstData_1_0_lat_0_whas__02_THEN_propDst_ETC___d412 =
	     CAN_FIRE_RL_srcPropose_2 ?
	       propDstData_1_0_lat_0$wget[515:514] :
	       propDstData_1_0_rl[515:514] ;
  assign IF_propDstData_1_0_lat_0_whas__02_THEN_propDst_ETC___d433 =
	     CAN_FIRE_RL_srcPropose_2 ?
	       propDstData_1_0_lat_0$wget[0] :
	       propDstData_1_0_rl[0] ;
  assign IF_propDstData_1_1_lat_0_whas__40_THEN_propDst_ETC___d445 =
	     CAN_FIRE_RL_srcPropose_3 ?
	       propDstData_1_1_lat_0$wget[579:516] :
	       propDstData_1_1_rl[579:516] ;
  assign IF_propDstData_1_1_lat_0_whas__40_THEN_propDst_ETC___d450 =
	     CAN_FIRE_RL_srcPropose_3 ?
	       propDstData_1_1_lat_0$wget[515:514] :
	       propDstData_1_1_rl[515:514] ;
  assign IF_propDstData_1_1_lat_0_whas__40_THEN_propDst_ETC___d471 =
	     CAN_FIRE_RL_srcPropose_3 ?
	       propDstData_1_1_lat_0$wget[0] :
	       propDstData_1_1_rl[0] ;
  assign IF_propDstData_1_dummy2_1_read__09_THEN_IF_pro_ETC___d324 =
	     propDstData_1_dummy2_1$Q_OUT ?
	       (CAN_FIRE_RL_srcPropose_1 ?
		  propDstData_1_lat_0$wget[8:7] :
		  propDstData_1_rl[8:7]) :
	       2'd0 ;
  assign IF_propDstData_1_dummy2_1_read__09_THEN_IF_pro_ETC___d334 =
	     propDstData_1_dummy2_1$Q_OUT ?
	       (CAN_FIRE_RL_srcPropose_1 ?
		  propDstData_1_lat_0$wget[6:5] :
		  propDstData_1_rl[6:5]) :
	       2'd0 ;
  assign IF_propDstIdx_0_lat_0_whas__77_THEN_propDstIdx_ETC___d180 =
	     CAN_FIRE_RL_srcPropose || propDstIdx_0_rl ;
  assign IF_propDstIdx_1_0_lat_0_whas__87_THEN_propDstI_ETC___d390 =
	     CAN_FIRE_RL_srcPropose_2 || propDstIdx_1_0_rl ;
  assign IF_propDstIdx_1_1_lat_0_whas__94_THEN_propDstI_ETC___d397 =
	     CAN_FIRE_RL_srcPropose_3 || propDstIdx_1_1_rl ;
  assign IF_propDstIdx_1_lat_0_whas__84_THEN_propDstIdx_ETC___d187 =
	     CAN_FIRE_RL_srcPropose_1 || propDstIdx_1_rl ;
  assign NOT_cfg_verbosity_read__70_ULE_1_71___d772 = cfg_verbosity > 4'd1 ;
  assign NOT_enqDst_0_dummy2_0_read__87_88_OR_NOT_enqDs_ETC___d303 =
	     (!enqDst_0_dummy2_0$Q_OUT || !enqDst_0_dummy2_1$Q_OUT ||
	      !enqDst_0_rl[73]) &&
	     (SEL_ARR_propDstIdx_0_dummy2_1_read__30_AND_IF__ETC___d297 ||
	      IF_NOT_propDstIdx_0_dummy2_1_read__30_31_OR_IF_ETC___d301) ;
  assign NOT_enqDst_1_0_dummy2_0_read__75_76_OR_NOT_enq_ETC___d591 =
	     (!enqDst_1_0_dummy2_0$Q_OUT || !enqDst_1_0_dummy2_1$Q_OUT ||
	      !enqDst_1_0_rl[580]) &&
	     (SEL_ARR_propDstIdx_1_0_dummy2_1_read__30_AND_I_ETC___d585 ||
	      IF_NOT_propDstIdx_1_0_dummy2_1_read__30_31_OR__ETC___d589) ;
  assign NOT_llc_axi4_adapter_master_xactor_crg_wr_addr_ETC___d114 =
	     !llc_axi4_adapter_master_xactor_crg_wr_addr_full$port2__read &&
	     !llc_axi4_adapter_master_xactor_crg_wr_data_full$port2__read &&
	     llc_axi4_adapter_ctr_wr_rsps_pending_crg != 4'd15 &&
	     llc$RDY_to_mem_toM_first &&
	     (llc_axi4_adapter_rg_wr_req_beat != 3'd0 ||
	      llc_axi4_adapter_f_pending_writes$FULL_N) &&
	     (llc_axi4_adapter_rg_wr_req_beat != 3'd7 ||
	      llc$RDY_to_mem_toM_deq) ;
  assign NOT_propDstData_1_0_dummy2_1_read__92_03_OR_IF_ETC___d604 =
	     !propDstData_1_0_dummy2_1$Q_OUT ||
	     (CAN_FIRE_RL_srcPropose_2 ?
		!propDstData_1_0_lat_0$wget[513] :
		!propDstData_1_0_rl[513]) ;
  assign NOT_propDstData_1_1_dummy2_1_read__94_05_OR_IF_ETC___d606 =
	     !propDstData_1_1_dummy2_1$Q_OUT ||
	     (CAN_FIRE_RL_srcPropose_3 ?
		!propDstData_1_1_lat_0$wget[513] :
		!propDstData_1_1_rl[513]) ;
  assign NOT_propDstIdx_0_dummy2_1_read__30_31_OR_IF_pr_ETC___d300 =
	     !propDstIdx_0_dummy2_1$Q_OUT ||
	     !CAN_FIRE_RL_srcPropose && !propDstIdx_0_rl ;
  assign NOT_propDstIdx_1_0_dummy2_1_read__30_31_OR_IF__ETC___d588 =
	     !propDstIdx_1_0_dummy2_1$Q_OUT ||
	     !CAN_FIRE_RL_srcPropose_2 && !propDstIdx_1_0_rl ;
  assign NOT_propDstIdx_1_1_dummy2_1_read__55_56_OR_IF__ETC___d695 =
	     !propDstIdx_1_1_dummy2_1$Q_OUT ||
	     !CAN_FIRE_RL_srcPropose_3 && !propDstIdx_1_1_rl ;
  assign NOT_propDstIdx_1_dummy2_1_read__61_62_OR_IF_pr_ETC___d379 =
	     !propDstIdx_1_dummy2_1$Q_OUT ||
	     !CAN_FIRE_RL_srcPropose_1 && !propDstIdx_1_rl ;
  assign SEL_ARR_IF_propDstData_0_dummy2_1_read__04_THE_ETC___d368 =
	     { CASE_x9280_0_IF_propDstData_0_dummy2_1_read__0_ETC__q6,
	       CASE_x9280_0_IF_propDstData_0_dummy2_1_read__0_ETC__q7,
	       SEL_ARR_propDstData_0_dummy2_1_read__04_AND_IF_ETC___d367 } ;
  assign SEL_ARR_IF_propDstData_1_0_dummy2_1_read__92_T_ETC___d684 =
	     { CASE_x8218_0_IF_propDstData_1_0_dummy2_1Q_OUT_ETC__q19,
	       !CASE_x8218_0_NOT_propDstData_1_0_dummy2_1_read_ETC__q20,
	       SEL_ARR_IF_propDstData_1_0_lat_0_whas__02_THEN_ETC___d677,
	       x__h70634 } ;
  assign SEL_ARR_IF_propDstData_1_0_lat_0_whas__02_THEN_ETC___d626 =
	     { CASE_x8218_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q11,
	       CASE_x8218_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q12 } ;
  assign SEL_ARR_IF_propDstData_1_0_lat_0_whas__02_THEN_ETC___d643 =
	     { SEL_ARR_IF_propDstData_1_0_lat_0_whas__02_THEN_ETC___d626,
	       CASE_x8218_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q13,
	       CASE_x8218_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q14 } ;
  assign SEL_ARR_IF_propDstData_1_0_lat_0_whas__02_THEN_ETC___d660 =
	     { SEL_ARR_IF_propDstData_1_0_lat_0_whas__02_THEN_ETC___d643,
	       CASE_x8218_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q15,
	       CASE_x8218_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q16 } ;
  assign SEL_ARR_IF_propDstData_1_0_lat_0_whas__02_THEN_ETC___d677 =
	     { SEL_ARR_IF_propDstData_1_0_lat_0_whas__02_THEN_ETC___d660,
	       CASE_x8218_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q17,
	       CASE_x8218_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q18 } ;
  assign SEL_ARR_propDstData_0_dummy2_1_read__04_AND_IF_ETC___d367 =
	     { CASE_x9280_0_propDstData_0_dummy2_1_read__04_A_ETC__q5,
	       x__h49594,
	       x__h49601 } ;
  assign b__h20709 =
	     CAN_FIRE_RL_llc_axi4_adapter_rl_handle_write_req ?
	       llc_axi4_adapter_ctr_wr_rsps_pending_crg$port0__write_1 :
	       llc_axi4_adapter_ctr_wr_rsps_pending_crg ;
  assign mem_req_rd_addr_araddr__h20827 =
	     { llc$to_mem_toM_first[68:11], x__h20877 } ;
  assign mem_req_wr_addr_awaddr__h22953 =
	     { llc$to_mem_toM_first[639:582], x__h22987 } ;
  assign n__read_addr__h49462 =
	     propDstData_0_dummy2_1$Q_OUT ?
	       (CAN_FIRE_RL_srcPropose ?
		  propDstData_0_lat_0$wget[72:9] :
		  propDstData_0_rl[72:9]) :
	       64'd0 ;
  assign n__read_addr__h49547 =
	     propDstData_1_dummy2_1$Q_OUT ?
	       (CAN_FIRE_RL_srcPropose_1 ?
		  propDstData_1_lat_0$wget[72:9] :
		  propDstData_1_rl[72:9]) :
	       64'd0 ;
  assign n__read_addr__h68396 =
	     propDstData_1_0_dummy2_1$Q_OUT ?
	       IF_propDstData_1_0_lat_0_whas__02_THEN_propDst_ETC___d407 :
	       64'd0 ;
  assign n__read_addr__h68475 =
	     propDstData_1_1_dummy2_1$Q_OUT ?
	       IF_propDstData_1_1_lat_0_whas__40_THEN_propDst_ETC___d445 :
	       64'd0 ;
  assign n__read_child__h49467 =
	     propDstData_0_dummy2_1$Q_OUT &&
	     (CAN_FIRE_RL_srcPropose ?
		propDstData_0_lat_0$wget[0] :
		propDstData_0_rl[0]) ;
  assign n__read_child__h49552 =
	     propDstData_1_dummy2_1$Q_OUT &&
	     (CAN_FIRE_RL_srcPropose_1 ?
		propDstData_1_lat_0$wget[0] :
		propDstData_1_rl[0]) ;
  assign n__read_child__h68399 =
	     propDstData_1_0_dummy2_1$Q_OUT &&
	     IF_propDstData_1_0_lat_0_whas__02_THEN_propDst_ETC___d433 ;
  assign n__read_child__h68478 =
	     propDstData_1_1_dummy2_1$Q_OUT &&
	     IF_propDstData_1_1_lat_0_whas__40_THEN_propDst_ETC___d471 ;
  assign n__read_id__h49466 =
	     propDstData_0_dummy2_1$Q_OUT ?
	       (CAN_FIRE_RL_srcPropose ?
		  propDstData_0_lat_0$wget[3:1] :
		  propDstData_0_rl[3:1]) :
	       3'd0 ;
  assign n__read_id__h49551 =
	     propDstData_1_dummy2_1$Q_OUT ?
	       (CAN_FIRE_RL_srcPropose_1 ?
		  propDstData_1_lat_0$wget[3:1] :
		  propDstData_1_rl[3:1]) :
	       3'd0 ;
  assign new_cline__h21399 =
	     { llc_axi4_adapter_master_xactor_rg_rd_data[66:3],
	       llc_axi4_adapter_rg_cline[511:64] } ;
  assign propDstData_0_dummy2_1_read__04_AND_IF_propDst_ETC___d340 =
	     propDstData_0_dummy2_1$Q_OUT &&
	     (CAN_FIRE_RL_srcPropose ?
		propDstData_0_lat_0$wget[4] :
		propDstData_0_rl[4]) ;
  assign propDstData_1_dummy2_1_read__09_AND_IF_propDst_ETC___d344 =
	     propDstData_1_dummy2_1$Q_OUT &&
	     (CAN_FIRE_RL_srcPropose_1 ?
		propDstData_1_lat_0$wget[4] :
		propDstData_1_rl[4]) ;
  assign x__h20877 = { llc_axi4_adapter_rg_rd_req_beat, 3'b0 } ;
  assign x__h22987 = { llc_axi4_adapter_rg_wr_req_beat, 3'b0 } ;
  assign x__h49280 =
	     SEL_ARR_propDstIdx_0_dummy2_1_read__30_AND_IF__ETC___d297 ?
	       srcRR_0 :
	       NOT_propDstIdx_0_dummy2_1_read__30_31_OR_IF_pr_ETC___d300 ;
  assign x__h62982 =
	     !CAN_FIRE_RL_doEnq_1 &&
	     IF_enqDst_1_0_lat_0_whas__78_THEN_enqDst_1_0_l_ETC___d519 ;
  assign x__h68218 =
	     SEL_ARR_propDstIdx_1_0_dummy2_1_read__30_AND_I_ETC___d585 ?
	       srcRR_1_0 :
	       NOT_propDstIdx_1_0_dummy2_1_read__30_31_OR_IF__ETC___d588 ;
  always@(llc_axi4_adapter_rg_wr_req_beat or llc$to_mem_toM_first)
  begin
    case (llc_axi4_adapter_rg_wr_req_beat)
      3'd0: data64__h22868 = llc$to_mem_toM_first[63:0];
      3'd1: data64__h22868 = llc$to_mem_toM_first[127:64];
      3'd2: data64__h22868 = llc$to_mem_toM_first[191:128];
      3'd3: data64__h22868 = llc$to_mem_toM_first[255:192];
      3'd4: data64__h22868 = llc$to_mem_toM_first[319:256];
      3'd5: data64__h22868 = llc$to_mem_toM_first[383:320];
      3'd6: data64__h22868 = llc$to_mem_toM_first[447:384];
      3'd7: data64__h22868 = llc$to_mem_toM_first[511:448];
    endcase
  end
  always@(llc_axi4_adapter_rg_wr_req_beat or llc$to_mem_toM_first)
  begin
    case (llc_axi4_adapter_rg_wr_req_beat)
      3'd0: strb8__h22869 = llc$to_mem_toM_first[519:512];
      3'd1: strb8__h22869 = llc$to_mem_toM_first[527:520];
      3'd2: strb8__h22869 = llc$to_mem_toM_first[535:528];
      3'd3: strb8__h22869 = llc$to_mem_toM_first[543:536];
      3'd4: strb8__h22869 = llc$to_mem_toM_first[551:544];
      3'd5: strb8__h22869 = llc$to_mem_toM_first[559:552];
      3'd6: strb8__h22869 = llc$to_mem_toM_first[567:560];
      3'd7: strb8__h22869 = llc$to_mem_toM_first[575:568];
    endcase
  end
  always@(srcRR_0 or
	  propDstIdx_0_dummy2_1$Q_OUT or
	  IF_propDstIdx_0_lat_0_whas__77_THEN_propDstIdx_ETC___d180 or
	  propDstIdx_1_dummy2_1$Q_OUT or
	  IF_propDstIdx_1_lat_0_whas__84_THEN_propDstIdx_ETC___d187)
  begin
    case (srcRR_0)
      1'd0:
	  SEL_ARR_propDstIdx_0_dummy2_1_read__30_AND_IF__ETC___d297 =
	      propDstIdx_0_dummy2_1$Q_OUT &&
	      IF_propDstIdx_0_lat_0_whas__77_THEN_propDstIdx_ETC___d180;
      1'd1:
	  SEL_ARR_propDstIdx_0_dummy2_1_read__30_AND_IF__ETC___d297 =
	      propDstIdx_1_dummy2_1$Q_OUT &&
	      IF_propDstIdx_1_lat_0_whas__84_THEN_propDstIdx_ETC___d187;
    endcase
  end
  always@(srcRR_1_0 or
	  propDstIdx_1_0_dummy2_1$Q_OUT or
	  IF_propDstIdx_1_0_lat_0_whas__87_THEN_propDstI_ETC___d390 or
	  propDstIdx_1_1_dummy2_1$Q_OUT or
	  IF_propDstIdx_1_1_lat_0_whas__94_THEN_propDstI_ETC___d397)
  begin
    case (srcRR_1_0)
      1'd0:
	  SEL_ARR_propDstIdx_1_0_dummy2_1_read__30_AND_I_ETC___d585 =
	      propDstIdx_1_0_dummy2_1$Q_OUT &&
	      IF_propDstIdx_1_0_lat_0_whas__87_THEN_propDstI_ETC___d390;
      1'd1:
	  SEL_ARR_propDstIdx_1_0_dummy2_1_read__30_AND_I_ETC___d585 =
	      propDstIdx_1_1_dummy2_1$Q_OUT &&
	      IF_propDstIdx_1_1_lat_0_whas__94_THEN_propDstI_ETC___d397;
    endcase
  end
  always@(i_mmu_cache$l1_to_l2_client_request_first)
  begin
    case (i_mmu_cache$l1_to_l2_client_request_first[4:3])
      2'd0, 2'd1, 2'd2:
	  CASE_i_mmu_cachel1_to_l2_client_request_first_ETC__q1 =
	      i_mmu_cache$l1_to_l2_client_request_first[4:3];
      2'd3: CASE_i_mmu_cachel1_to_l2_client_request_first_ETC__q1 = 2'd3;
    endcase
  end
  always@(i_mmu_cache$l1_to_l2_client_request_first)
  begin
    case (i_mmu_cache$l1_to_l2_client_request_first[2:1])
      2'd0, 2'd1, 2'd2:
	  CASE_i_mmu_cachel1_to_l2_client_request_first_ETC__q2 =
	      i_mmu_cache$l1_to_l2_client_request_first[2:1];
      2'd3: CASE_i_mmu_cachel1_to_l2_client_request_first_ETC__q2 = 2'd3;
    endcase
  end
  always@(d_mmu_cache$l1_to_l2_client_request_first)
  begin
    case (d_mmu_cache$l1_to_l2_client_request_first[4:3])
      2'd0, 2'd1, 2'd2:
	  CASE_d_mmu_cachel1_to_l2_client_request_first_ETC__q3 =
	      d_mmu_cache$l1_to_l2_client_request_first[4:3];
      2'd3: CASE_d_mmu_cachel1_to_l2_client_request_first_ETC__q3 = 2'd3;
    endcase
  end
  always@(d_mmu_cache$l1_to_l2_client_request_first)
  begin
    case (d_mmu_cache$l1_to_l2_client_request_first[2:1])
      2'd0, 2'd1, 2'd2:
	  CASE_d_mmu_cachel1_to_l2_client_request_first_ETC__q4 =
	      d_mmu_cache$l1_to_l2_client_request_first[2:1];
      2'd3: CASE_d_mmu_cachel1_to_l2_client_request_first_ETC__q4 = 2'd3;
    endcase
  end
  always@(x__h49280 or n__read_id__h49466 or n__read_id__h49551)
  begin
    case (x__h49280)
      1'd0: x__h49594 = n__read_id__h49466;
      1'd1: x__h49594 = n__read_id__h49551;
    endcase
  end
  always@(x__h49280 or n__read_child__h49467 or n__read_child__h49552)
  begin
    case (x__h49280)
      1'd0: x__h49601 = n__read_child__h49467;
      1'd1: x__h49601 = n__read_child__h49552;
    endcase
  end
  always@(x__h49280 or
	  propDstData_0_dummy2_1_read__04_AND_IF_propDst_ETC___d340 or
	  propDstData_1_dummy2_1_read__09_AND_IF_propDst_ETC___d344)
  begin
    case (x__h49280)
      1'd0:
	  CASE_x9280_0_propDstData_0_dummy2_1_read__04_A_ETC__q5 =
	      propDstData_0_dummy2_1_read__04_AND_IF_propDst_ETC___d340;
      1'd1:
	  CASE_x9280_0_propDstData_0_dummy2_1_read__04_A_ETC__q5 =
	      propDstData_1_dummy2_1_read__09_AND_IF_propDst_ETC___d344;
    endcase
  end
  always@(x__h49280 or
	  IF_propDstData_0_dummy2_1_read__04_THEN_IF_pro_ETC___d320 or
	  IF_propDstData_1_dummy2_1_read__09_THEN_IF_pro_ETC___d324)
  begin
    case (x__h49280)
      1'd0:
	  CASE_x9280_0_IF_propDstData_0_dummy2_1_read__0_ETC__q6 =
	      IF_propDstData_0_dummy2_1_read__04_THEN_IF_pro_ETC___d320;
      1'd1:
	  CASE_x9280_0_IF_propDstData_0_dummy2_1_read__0_ETC__q6 =
	      IF_propDstData_1_dummy2_1_read__09_THEN_IF_pro_ETC___d324;
    endcase
  end
  always@(x__h49280 or
	  IF_propDstData_0_dummy2_1_read__04_THEN_IF_pro_ETC___d330 or
	  IF_propDstData_1_dummy2_1_read__09_THEN_IF_pro_ETC___d334)
  begin
    case (x__h49280)
      1'd0:
	  CASE_x9280_0_IF_propDstData_0_dummy2_1_read__0_ETC__q7 =
	      IF_propDstData_0_dummy2_1_read__04_THEN_IF_pro_ETC___d330;
      1'd1:
	  CASE_x9280_0_IF_propDstData_0_dummy2_1_read__0_ETC__q7 =
	      IF_propDstData_1_dummy2_1_read__09_THEN_IF_pro_ETC___d334;
    endcase
  end
  always@(x__h49280 or n__read_addr__h49462 or n__read_addr__h49547)
  begin
    case (x__h49280)
      1'd0:
	  CASE_x9280_0_n__read_addr9462_1_n__read_addr95_ETC__q8 =
	      n__read_addr__h49462;
      1'd1:
	  CASE_x9280_0_n__read_addr9462_1_n__read_addr95_ETC__q8 =
	      n__read_addr__h49547;
    endcase
  end
  always@(i_mmu_cache$l2_to_l1_server_response_first)
  begin
    case (i_mmu_cache$l2_to_l1_server_response_first[514:513])
      2'd0, 2'd1, 2'd2:
	  CASE_i_mmu_cachel2_to_l1_server_response_firs_ETC__q9 =
	      i_mmu_cache$l2_to_l1_server_response_first[514:513];
      2'd3: CASE_i_mmu_cachel2_to_l1_server_response_firs_ETC__q9 = 2'd3;
    endcase
  end
  always@(d_mmu_cache$l2_to_l1_server_response_first)
  begin
    case (d_mmu_cache$l2_to_l1_server_response_first[514:513])
      2'd0, 2'd1, 2'd2:
	  CASE_d_mmu_cachel2_to_l1_server_response_firs_ETC__q10 =
	      d_mmu_cache$l2_to_l1_server_response_first[514:513];
      2'd3: CASE_d_mmu_cachel2_to_l1_server_response_firs_ETC__q10 = 2'd3;
    endcase
  end
  always@(x__h68218 or n__read_child__h68399 or n__read_child__h68478)
  begin
    case (x__h68218)
      1'd0: x__h70634 = n__read_child__h68399;
      1'd1: x__h70634 = n__read_child__h68478;
    endcase
  end
  always@(x__h68218 or
	  CAN_FIRE_RL_srcPropose_2 or
	  propDstData_1_0_lat_0$wget or
	  propDstData_1_0_rl or
	  CAN_FIRE_RL_srcPropose_3 or
	  propDstData_1_1_lat_0$wget or propDstData_1_1_rl)
  begin
    case (x__h68218)
      1'd0:
	  CASE_x8218_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q11 =
	      CAN_FIRE_RL_srcPropose_2 ?
		propDstData_1_0_lat_0$wget[512:449] :
		propDstData_1_0_rl[512:449];
      1'd1:
	  CASE_x8218_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q11 =
	      CAN_FIRE_RL_srcPropose_3 ?
		propDstData_1_1_lat_0$wget[512:449] :
		propDstData_1_1_rl[512:449];
    endcase
  end
  always@(x__h68218 or
	  CAN_FIRE_RL_srcPropose_2 or
	  propDstData_1_0_lat_0$wget or
	  propDstData_1_0_rl or
	  CAN_FIRE_RL_srcPropose_3 or
	  propDstData_1_1_lat_0$wget or propDstData_1_1_rl)
  begin
    case (x__h68218)
      1'd0:
	  CASE_x8218_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q12 =
	      CAN_FIRE_RL_srcPropose_2 ?
		propDstData_1_0_lat_0$wget[448:385] :
		propDstData_1_0_rl[448:385];
      1'd1:
	  CASE_x8218_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q12 =
	      CAN_FIRE_RL_srcPropose_3 ?
		propDstData_1_1_lat_0$wget[448:385] :
		propDstData_1_1_rl[448:385];
    endcase
  end
  always@(x__h68218 or
	  CAN_FIRE_RL_srcPropose_2 or
	  propDstData_1_0_lat_0$wget or
	  propDstData_1_0_rl or
	  CAN_FIRE_RL_srcPropose_3 or
	  propDstData_1_1_lat_0$wget or propDstData_1_1_rl)
  begin
    case (x__h68218)
      1'd0:
	  CASE_x8218_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q13 =
	      CAN_FIRE_RL_srcPropose_2 ?
		propDstData_1_0_lat_0$wget[384:321] :
		propDstData_1_0_rl[384:321];
      1'd1:
	  CASE_x8218_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q13 =
	      CAN_FIRE_RL_srcPropose_3 ?
		propDstData_1_1_lat_0$wget[384:321] :
		propDstData_1_1_rl[384:321];
    endcase
  end
  always@(x__h68218 or
	  CAN_FIRE_RL_srcPropose_2 or
	  propDstData_1_0_lat_0$wget or
	  propDstData_1_0_rl or
	  CAN_FIRE_RL_srcPropose_3 or
	  propDstData_1_1_lat_0$wget or propDstData_1_1_rl)
  begin
    case (x__h68218)
      1'd0:
	  CASE_x8218_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q14 =
	      CAN_FIRE_RL_srcPropose_2 ?
		propDstData_1_0_lat_0$wget[320:257] :
		propDstData_1_0_rl[320:257];
      1'd1:
	  CASE_x8218_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q14 =
	      CAN_FIRE_RL_srcPropose_3 ?
		propDstData_1_1_lat_0$wget[320:257] :
		propDstData_1_1_rl[320:257];
    endcase
  end
  always@(x__h68218 or
	  CAN_FIRE_RL_srcPropose_2 or
	  propDstData_1_0_lat_0$wget or
	  propDstData_1_0_rl or
	  CAN_FIRE_RL_srcPropose_3 or
	  propDstData_1_1_lat_0$wget or propDstData_1_1_rl)
  begin
    case (x__h68218)
      1'd0:
	  CASE_x8218_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q15 =
	      CAN_FIRE_RL_srcPropose_2 ?
		propDstData_1_0_lat_0$wget[256:193] :
		propDstData_1_0_rl[256:193];
      1'd1:
	  CASE_x8218_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q15 =
	      CAN_FIRE_RL_srcPropose_3 ?
		propDstData_1_1_lat_0$wget[256:193] :
		propDstData_1_1_rl[256:193];
    endcase
  end
  always@(x__h68218 or
	  CAN_FIRE_RL_srcPropose_2 or
	  propDstData_1_0_lat_0$wget or
	  propDstData_1_0_rl or
	  CAN_FIRE_RL_srcPropose_3 or
	  propDstData_1_1_lat_0$wget or propDstData_1_1_rl)
  begin
    case (x__h68218)
      1'd0:
	  CASE_x8218_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q16 =
	      CAN_FIRE_RL_srcPropose_2 ?
		propDstData_1_0_lat_0$wget[192:129] :
		propDstData_1_0_rl[192:129];
      1'd1:
	  CASE_x8218_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q16 =
	      CAN_FIRE_RL_srcPropose_3 ?
		propDstData_1_1_lat_0$wget[192:129] :
		propDstData_1_1_rl[192:129];
    endcase
  end
  always@(x__h68218 or
	  CAN_FIRE_RL_srcPropose_2 or
	  propDstData_1_0_lat_0$wget or
	  propDstData_1_0_rl or
	  CAN_FIRE_RL_srcPropose_3 or
	  propDstData_1_1_lat_0$wget or propDstData_1_1_rl)
  begin
    case (x__h68218)
      1'd0:
	  CASE_x8218_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q17 =
	      CAN_FIRE_RL_srcPropose_2 ?
		propDstData_1_0_lat_0$wget[128:65] :
		propDstData_1_0_rl[128:65];
      1'd1:
	  CASE_x8218_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q17 =
	      CAN_FIRE_RL_srcPropose_3 ?
		propDstData_1_1_lat_0$wget[128:65] :
		propDstData_1_1_rl[128:65];
    endcase
  end
  always@(x__h68218 or
	  CAN_FIRE_RL_srcPropose_2 or
	  propDstData_1_0_lat_0$wget or
	  propDstData_1_0_rl or
	  CAN_FIRE_RL_srcPropose_3 or
	  propDstData_1_1_lat_0$wget or propDstData_1_1_rl)
  begin
    case (x__h68218)
      1'd0:
	  CASE_x8218_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q18 =
	      CAN_FIRE_RL_srcPropose_2 ?
		propDstData_1_0_lat_0$wget[64:1] :
		propDstData_1_0_rl[64:1];
      1'd1:
	  CASE_x8218_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q18 =
	      CAN_FIRE_RL_srcPropose_3 ?
		propDstData_1_1_lat_0$wget[64:1] :
		propDstData_1_1_rl[64:1];
    endcase
  end
  always@(x__h68218 or
	  propDstData_1_0_dummy2_1$Q_OUT or
	  IF_propDstData_1_0_lat_0_whas__02_THEN_propDst_ETC___d412 or
	  propDstData_1_1_dummy2_1$Q_OUT or
	  IF_propDstData_1_1_lat_0_whas__40_THEN_propDst_ETC___d450)
  begin
    case (x__h68218)
      1'd0:
	  CASE_x8218_0_IF_propDstData_1_0_dummy2_1Q_OUT_ETC__q19 =
	      propDstData_1_0_dummy2_1$Q_OUT ?
		IF_propDstData_1_0_lat_0_whas__02_THEN_propDst_ETC___d412 :
		2'd0;
      1'd1:
	  CASE_x8218_0_IF_propDstData_1_0_dummy2_1Q_OUT_ETC__q19 =
	      propDstData_1_1_dummy2_1$Q_OUT ?
		IF_propDstData_1_1_lat_0_whas__40_THEN_propDst_ETC___d450 :
		2'd0;
    endcase
  end
  always@(x__h68218 or
	  NOT_propDstData_1_0_dummy2_1_read__92_03_OR_IF_ETC___d604 or
	  NOT_propDstData_1_1_dummy2_1_read__94_05_OR_IF_ETC___d606)
  begin
    case (x__h68218)
      1'd0:
	  CASE_x8218_0_NOT_propDstData_1_0_dummy2_1_read_ETC__q20 =
	      NOT_propDstData_1_0_dummy2_1_read__92_03_OR_IF_ETC___d604;
      1'd1:
	  CASE_x8218_0_NOT_propDstData_1_0_dummy2_1_read_ETC__q20 =
	      NOT_propDstData_1_1_dummy2_1_read__94_05_OR_IF_ETC___d606;
    endcase
  end
  always@(x__h68218 or n__read_addr__h68396 or n__read_addr__h68475)
  begin
    case (x__h68218)
      1'd0:
	  CASE_x8218_0_n__read_addr8396_1_n__read_addr84_ETC__q21 =
	      n__read_addr__h68396;
      1'd1:
	  CASE_x8218_0_n__read_addr8396_1_n__read_addr84_ETC__q21 =
	      n__read_addr__h68475;
    endcase
  end
  always@(llc$to_child_toC_first)
  begin
    case (llc$to_child_toC_first[2:1])
      2'd0, 2'd1, 2'd2:
	  CASE_llcto_child_toC_first_BITS_2_TO_1_0_llc_ETC__q22 =
	      llc$to_child_toC_first[2:1];
      2'd3: CASE_llcto_child_toC_first_BITS_2_TO_1_0_llc_ETC__q22 = 2'd3;
    endcase
  end
  always@(llc$to_child_toC_first)
  begin
    case (llc$to_child_toC_first[518:517])
      2'd0, 2'd1, 2'd2:
	  CASE_llcto_child_toC_first_BITS_518_TO_517_0__ETC__q23 =
	      llc$to_child_toC_first[518:517];
      2'd3: CASE_llcto_child_toC_first_BITS_518_TO_517_0__ETC__q23 = 2'd3;
    endcase
  end

  // handling of inlined registers

  always@(posedge CLK)
  begin
    if (RST_N == `BSV_RESET_VALUE)
      begin
        cfg_verbosity <= `BSV_ASSIGNMENT_DELAY 4'd0;
	enqDst_0_rl <= `BSV_ASSIGNMENT_DELAY 74'h0AAAAAAAAAAAAAAAAAA;
	enqDst_1_0_rl <= `BSV_ASSIGNMENT_DELAY
	    581'h0AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA;
	llc_axi4_adapter_ctr_wr_rsps_pending_crg <= `BSV_ASSIGNMENT_DELAY
	    4'd0;
	llc_axi4_adapter_master_xactor_crg_rd_addr_full <= `BSV_ASSIGNMENT_DELAY
	    1'd0;
	llc_axi4_adapter_master_xactor_crg_rd_data_full <= `BSV_ASSIGNMENT_DELAY
	    1'd0;
	llc_axi4_adapter_master_xactor_crg_wr_addr_full <= `BSV_ASSIGNMENT_DELAY
	    1'd0;
	llc_axi4_adapter_master_xactor_crg_wr_data_full <= `BSV_ASSIGNMENT_DELAY
	    1'd0;
	llc_axi4_adapter_master_xactor_crg_wr_resp_full <= `BSV_ASSIGNMENT_DELAY
	    1'd0;
	llc_axi4_adapter_rg_AXI4_error <= `BSV_ASSIGNMENT_DELAY 1'd0;
	llc_axi4_adapter_rg_ddr4_ready <= `BSV_ASSIGNMENT_DELAY 1'd0;
	llc_axi4_adapter_rg_rd_req_beat <= `BSV_ASSIGNMENT_DELAY 3'd0;
	llc_axi4_adapter_rg_rd_rsp_beat <= `BSV_ASSIGNMENT_DELAY 3'd0;
	llc_axi4_adapter_rg_wr_req_beat <= `BSV_ASSIGNMENT_DELAY 3'd0;
	llc_axi4_adapter_rg_wr_rsp_beat <= `BSV_ASSIGNMENT_DELAY 3'd0;
	propDstData_0_rl <= `BSV_ASSIGNMENT_DELAY 73'h0AAAAAAAAAAAAAAAAAA;
	propDstData_1_0_rl <= `BSV_ASSIGNMENT_DELAY
	    580'hAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA;
	propDstData_1_1_rl <= `BSV_ASSIGNMENT_DELAY
	    580'hAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA;
	propDstData_1_rl <= `BSV_ASSIGNMENT_DELAY 73'h0AAAAAAAAAAAAAAAAAA;
	propDstIdx_0_rl <= `BSV_ASSIGNMENT_DELAY 1'd0;
	propDstIdx_1_0_rl <= `BSV_ASSIGNMENT_DELAY 1'd0;
	propDstIdx_1_1_rl <= `BSV_ASSIGNMENT_DELAY 1'd0;
	propDstIdx_1_rl <= `BSV_ASSIGNMENT_DELAY 1'd0;
	rg_state <= `BSV_ASSIGNMENT_DELAY 2'd2;
	srcRR_0 <= `BSV_ASSIGNMENT_DELAY 1'd0;
	srcRR_1_0 <= `BSV_ASSIGNMENT_DELAY 1'd0;
      end
    else
      begin
        if (cfg_verbosity$EN)
	  cfg_verbosity <= `BSV_ASSIGNMENT_DELAY cfg_verbosity$D_IN;
	if (enqDst_0_rl$EN)
	  enqDst_0_rl <= `BSV_ASSIGNMENT_DELAY enqDst_0_rl$D_IN;
	if (enqDst_1_0_rl$EN)
	  enqDst_1_0_rl <= `BSV_ASSIGNMENT_DELAY enqDst_1_0_rl$D_IN;
	if (llc_axi4_adapter_ctr_wr_rsps_pending_crg$EN)
	  llc_axi4_adapter_ctr_wr_rsps_pending_crg <= `BSV_ASSIGNMENT_DELAY
	      llc_axi4_adapter_ctr_wr_rsps_pending_crg$D_IN;
	if (llc_axi4_adapter_master_xactor_crg_rd_addr_full$EN)
	  llc_axi4_adapter_master_xactor_crg_rd_addr_full <= `BSV_ASSIGNMENT_DELAY
	      llc_axi4_adapter_master_xactor_crg_rd_addr_full$D_IN;
	if (llc_axi4_adapter_master_xactor_crg_rd_data_full$EN)
	  llc_axi4_adapter_master_xactor_crg_rd_data_full <= `BSV_ASSIGNMENT_DELAY
	      llc_axi4_adapter_master_xactor_crg_rd_data_full$D_IN;
	if (llc_axi4_adapter_master_xactor_crg_wr_addr_full$EN)
	  llc_axi4_adapter_master_xactor_crg_wr_addr_full <= `BSV_ASSIGNMENT_DELAY
	      llc_axi4_adapter_master_xactor_crg_wr_addr_full$D_IN;
	if (llc_axi4_adapter_master_xactor_crg_wr_data_full$EN)
	  llc_axi4_adapter_master_xactor_crg_wr_data_full <= `BSV_ASSIGNMENT_DELAY
	      llc_axi4_adapter_master_xactor_crg_wr_data_full$D_IN;
	if (llc_axi4_adapter_master_xactor_crg_wr_resp_full$EN)
	  llc_axi4_adapter_master_xactor_crg_wr_resp_full <= `BSV_ASSIGNMENT_DELAY
	      llc_axi4_adapter_master_xactor_crg_wr_resp_full$D_IN;
	if (llc_axi4_adapter_rg_AXI4_error$EN)
	  llc_axi4_adapter_rg_AXI4_error <= `BSV_ASSIGNMENT_DELAY
	      llc_axi4_adapter_rg_AXI4_error$D_IN;
	if (llc_axi4_adapter_rg_ddr4_ready$EN)
	  llc_axi4_adapter_rg_ddr4_ready <= `BSV_ASSIGNMENT_DELAY
	      llc_axi4_adapter_rg_ddr4_ready$D_IN;
	if (llc_axi4_adapter_rg_rd_req_beat$EN)
	  llc_axi4_adapter_rg_rd_req_beat <= `BSV_ASSIGNMENT_DELAY
	      llc_axi4_adapter_rg_rd_req_beat$D_IN;
	if (llc_axi4_adapter_rg_rd_rsp_beat$EN)
	  llc_axi4_adapter_rg_rd_rsp_beat <= `BSV_ASSIGNMENT_DELAY
	      llc_axi4_adapter_rg_rd_rsp_beat$D_IN;
	if (llc_axi4_adapter_rg_wr_req_beat$EN)
	  llc_axi4_adapter_rg_wr_req_beat <= `BSV_ASSIGNMENT_DELAY
	      llc_axi4_adapter_rg_wr_req_beat$D_IN;
	if (llc_axi4_adapter_rg_wr_rsp_beat$EN)
	  llc_axi4_adapter_rg_wr_rsp_beat <= `BSV_ASSIGNMENT_DELAY
	      llc_axi4_adapter_rg_wr_rsp_beat$D_IN;
	if (propDstData_0_rl$EN)
	  propDstData_0_rl <= `BSV_ASSIGNMENT_DELAY propDstData_0_rl$D_IN;
	if (propDstData_1_0_rl$EN)
	  propDstData_1_0_rl <= `BSV_ASSIGNMENT_DELAY propDstData_1_0_rl$D_IN;
	if (propDstData_1_1_rl$EN)
	  propDstData_1_1_rl <= `BSV_ASSIGNMENT_DELAY propDstData_1_1_rl$D_IN;
	if (propDstData_1_rl$EN)
	  propDstData_1_rl <= `BSV_ASSIGNMENT_DELAY propDstData_1_rl$D_IN;
	if (propDstIdx_0_rl$EN)
	  propDstIdx_0_rl <= `BSV_ASSIGNMENT_DELAY propDstIdx_0_rl$D_IN;
	if (propDstIdx_1_0_rl$EN)
	  propDstIdx_1_0_rl <= `BSV_ASSIGNMENT_DELAY propDstIdx_1_0_rl$D_IN;
	if (propDstIdx_1_1_rl$EN)
	  propDstIdx_1_1_rl <= `BSV_ASSIGNMENT_DELAY propDstIdx_1_1_rl$D_IN;
	if (propDstIdx_1_rl$EN)
	  propDstIdx_1_rl <= `BSV_ASSIGNMENT_DELAY propDstIdx_1_rl$D_IN;
	if (rg_state$EN) rg_state <= `BSV_ASSIGNMENT_DELAY rg_state$D_IN;
	if (srcRR_0$EN) srcRR_0 <= `BSV_ASSIGNMENT_DELAY srcRR_0$D_IN;
	if (srcRR_1_0$EN) srcRR_1_0 <= `BSV_ASSIGNMENT_DELAY srcRR_1_0$D_IN;
      end
    if (llc_axi4_adapter_master_xactor_rg_rd_addr$EN)
      llc_axi4_adapter_master_xactor_rg_rd_addr <= `BSV_ASSIGNMENT_DELAY
	  llc_axi4_adapter_master_xactor_rg_rd_addr$D_IN;
    if (llc_axi4_adapter_master_xactor_rg_rd_data$EN)
      llc_axi4_adapter_master_xactor_rg_rd_data <= `BSV_ASSIGNMENT_DELAY
	  llc_axi4_adapter_master_xactor_rg_rd_data$D_IN;
    if (llc_axi4_adapter_master_xactor_rg_wr_addr$EN)
      llc_axi4_adapter_master_xactor_rg_wr_addr <= `BSV_ASSIGNMENT_DELAY
	  llc_axi4_adapter_master_xactor_rg_wr_addr$D_IN;
    if (llc_axi4_adapter_master_xactor_rg_wr_data$EN)
      llc_axi4_adapter_master_xactor_rg_wr_data <= `BSV_ASSIGNMENT_DELAY
	  llc_axi4_adapter_master_xactor_rg_wr_data$D_IN;
    if (llc_axi4_adapter_master_xactor_rg_wr_resp$EN)
      llc_axi4_adapter_master_xactor_rg_wr_resp <= `BSV_ASSIGNMENT_DELAY
	  llc_axi4_adapter_master_xactor_rg_wr_resp$D_IN;
    if (llc_axi4_adapter_rg_cline$EN)
      llc_axi4_adapter_rg_cline <= `BSV_ASSIGNMENT_DELAY
	  llc_axi4_adapter_rg_cline$D_IN;
  end

  // synopsys translate_off
  `ifdef BSV_NO_INITIAL_BLOCKS
  `else // not BSV_NO_INITIAL_BLOCKS
  initial
  begin
    cfg_verbosity = 4'hA;
    enqDst_0_rl = 74'h2AAAAAAAAAAAAAAAAAA;
    enqDst_1_0_rl =
	581'h0AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA;
    llc_axi4_adapter_ctr_wr_rsps_pending_crg = 4'hA;
    llc_axi4_adapter_master_xactor_crg_rd_addr_full = 1'h0;
    llc_axi4_adapter_master_xactor_crg_rd_data_full = 1'h0;
    llc_axi4_adapter_master_xactor_crg_wr_addr_full = 1'h0;
    llc_axi4_adapter_master_xactor_crg_wr_data_full = 1'h0;
    llc_axi4_adapter_master_xactor_crg_wr_resp_full = 1'h0;
    llc_axi4_adapter_master_xactor_rg_rd_addr =
	109'h0AAAAAAAAAAAAAAAAAAAAAAAAAAA;
    llc_axi4_adapter_master_xactor_rg_rd_data = 83'h2AAAAAAAAAAAAAAAAAAAA;
    llc_axi4_adapter_master_xactor_rg_wr_addr =
	109'h0AAAAAAAAAAAAAAAAAAAAAAAAAAA;
    llc_axi4_adapter_master_xactor_rg_wr_data = 73'h0AAAAAAAAAAAAAAAAAA;
    llc_axi4_adapter_master_xactor_rg_wr_resp = 18'h2AAAA;
    llc_axi4_adapter_rg_AXI4_error = 1'h0;
    llc_axi4_adapter_rg_cline =
	512'hAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA;
    llc_axi4_adapter_rg_ddr4_ready = 1'h0;
    llc_axi4_adapter_rg_rd_req_beat = 3'h2;
    llc_axi4_adapter_rg_rd_rsp_beat = 3'h2;
    llc_axi4_adapter_rg_wr_req_beat = 3'h2;
    llc_axi4_adapter_rg_wr_rsp_beat = 3'h2;
    propDstData_0_rl = 73'h0AAAAAAAAAAAAAAAAAA;
    propDstData_1_0_rl =
	580'hAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA;
    propDstData_1_1_rl =
	580'hAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA;
    propDstData_1_rl = 73'h0AAAAAAAAAAAAAAAAAA;
    propDstIdx_0_rl = 1'h0;
    propDstIdx_1_0_rl = 1'h0;
    propDstIdx_1_1_rl = 1'h0;
    propDstIdx_1_rl = 1'h0;
    rg_state = 2'h2;
    srcRR_0 = 1'h0;
    srcRR_1_0 = 1'h0;
  end
  `endif // BSV_NO_INITIAL_BLOCKS
  // synopsys translate_on

  // handling of system tasks

  // synopsys translate_off
  always@(negedge CLK)
  begin
    #0;
    if (RST_N != `BSV_RESET_VALUE)
      if (NOT_enqDst_0_dummy2_0_read__87_88_OR_NOT_enqDs_ETC___d303 &&
	  IF_SEL_ARR_propDstIdx_0_dummy2_1_read__30_AND__ETC___d373 &&
	  NOT_propDstIdx_0_dummy2_1_read__30_31_OR_IF_pr_ETC___d300)
	$display("Dynamic assertion failed: \"../src_Core/Near_Mem_VM_WB_L1_L2/src_LLCache/coherence/src/CrossBar.bsv\", line 123, column 53\nsrc must be proposing");
    if (RST_N != `BSV_RESET_VALUE)
      if (NOT_enqDst_0_dummy2_0_read__87_88_OR_NOT_enqDs_ETC___d303 &&
	  IF_SEL_ARR_propDstIdx_0_dummy2_1_read__30_AND__ETC___d373 &&
	  NOT_propDstIdx_0_dummy2_1_read__30_31_OR_IF_pr_ETC___d300)
	$finish(32'd0);
    if (RST_N != `BSV_RESET_VALUE)
      if (NOT_enqDst_0_dummy2_0_read__87_88_OR_NOT_enqDs_ETC___d303 &&
	  x__h49280 &&
	  NOT_propDstIdx_1_dummy2_1_read__61_62_OR_IF_pr_ETC___d379)
	$display("Dynamic assertion failed: \"../src_Core/Near_Mem_VM_WB_L1_L2/src_LLCache/coherence/src/CrossBar.bsv\", line 123, column 53\nsrc must be proposing");
    if (RST_N != `BSV_RESET_VALUE)
      if (NOT_enqDst_0_dummy2_0_read__87_88_OR_NOT_enqDs_ETC___d303 &&
	  x__h49280 &&
	  NOT_propDstIdx_1_dummy2_1_read__61_62_OR_IF_pr_ETC___d379)
	$finish(32'd0);
    if (RST_N != `BSV_RESET_VALUE)
      if (NOT_enqDst_1_0_dummy2_0_read__75_76_OR_NOT_enq_ETC___d591 &&
	  IF_SEL_ARR_propDstIdx_1_0_dummy2_1_read__30_AN_ETC___d689 &&
	  NOT_propDstIdx_1_0_dummy2_1_read__30_31_OR_IF__ETC___d588)
	$display("Dynamic assertion failed: \"../src_Core/Near_Mem_VM_WB_L1_L2/src_LLCache/coherence/src/CrossBar.bsv\", line 123, column 53\nsrc must be proposing");
    if (RST_N != `BSV_RESET_VALUE)
      if (NOT_enqDst_1_0_dummy2_0_read__75_76_OR_NOT_enq_ETC___d591 &&
	  IF_SEL_ARR_propDstIdx_1_0_dummy2_1_read__30_AN_ETC___d689 &&
	  NOT_propDstIdx_1_0_dummy2_1_read__30_31_OR_IF__ETC___d588)
	$finish(32'd0);
    if (RST_N != `BSV_RESET_VALUE)
      if (NOT_enqDst_1_0_dummy2_0_read__75_76_OR_NOT_enq_ETC___d591 &&
	  x__h68218 &&
	  NOT_propDstIdx_1_1_dummy2_1_read__55_56_OR_IF__ETC___d695)
	$display("Dynamic assertion failed: \"../src_Core/Near_Mem_VM_WB_L1_L2/src_LLCache/coherence/src/CrossBar.bsv\", line 123, column 53\nsrc must be proposing");
    if (RST_N != `BSV_RESET_VALUE)
      if (NOT_enqDst_1_0_dummy2_0_read__75_76_OR_NOT_enq_ETC___d591 &&
	  x__h68218 &&
	  NOT_propDstIdx_1_1_dummy2_1_read__55_56_OR_IF__ETC___d695)
	$finish(32'd0);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_reset && NOT_cfg_verbosity_read__70_ULE_1_71___d772)
	begin
	  v__h77688 = $stime;
	  #0;
	end
    v__h77682 = v__h77688 / 32'd10;
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_reset && NOT_cfg_verbosity_read__70_ULE_1_71___d772)
	$display("%0d: Near_Mem.rl_reset", v__h77682);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_reset_complete &&
	  NOT_cfg_verbosity_read__70_ULE_1_71___d772)
	begin
	  v__h77791 = $stime;
	  #0;
	end
    v__h77785 = v__h77791 / 32'd10;
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_reset_complete &&
	  NOT_cfg_verbosity_read__70_ULE_1_71___d772)
	$display("%0d: Near_Mem.rl_reset_complete", v__h77785);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps &&
	  llc_axi4_adapter_master_xactor_rg_rd_data[2:1] != 2'b0)
	begin
	  v__h21259 = $stime;
	  #0;
	end
    v__h21253 = v__h21259 / 32'd10;
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps &&
	  llc_axi4_adapter_master_xactor_rg_rd_data[2:1] != 2'b0)
	$display("%0d: LLC_AXI4_Adapter.rl_handle_read_rsp: fabric response error; exit",
		 v__h21253);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps &&
	  llc_axi4_adapter_master_xactor_rg_rd_data[2:1] != 2'b0)
	$write("    ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps &&
	  llc_axi4_adapter_master_xactor_rg_rd_data[2:1] != 2'b0)
	$write("AXI4_Rd_Data { ", "rid: ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps &&
	  llc_axi4_adapter_master_xactor_rg_rd_data[2:1] != 2'b0)
	$write("'h%h", llc_axi4_adapter_master_xactor_rg_rd_data[82:67]);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps &&
	  llc_axi4_adapter_master_xactor_rg_rd_data[2:1] != 2'b0)
	$write(", ", "rdata: ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps &&
	  llc_axi4_adapter_master_xactor_rg_rd_data[2:1] != 2'b0)
	$write("'h%h", llc_axi4_adapter_master_xactor_rg_rd_data[66:3]);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps &&
	  llc_axi4_adapter_master_xactor_rg_rd_data[2:1] != 2'b0)
	$write(", ", "rresp: ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps &&
	  llc_axi4_adapter_master_xactor_rg_rd_data[2:1] != 2'b0)
	$write("'h%h", llc_axi4_adapter_master_xactor_rg_rd_data[2:1]);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps &&
	  llc_axi4_adapter_master_xactor_rg_rd_data[2:1] != 2'b0)
	$write(", ", "rlast: ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps &&
	  llc_axi4_adapter_master_xactor_rg_rd_data[2:1] != 2'b0 &&
	  llc_axi4_adapter_master_xactor_rg_rd_data[0])
	$write("True");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps &&
	  llc_axi4_adapter_master_xactor_rg_rd_data[2:1] != 2'b0 &&
	  !llc_axi4_adapter_master_xactor_rg_rd_data[0])
	$write("False");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps &&
	  llc_axi4_adapter_master_xactor_rg_rd_data[2:1] != 2'b0)
	$write(", ", "ruser: ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps &&
	  llc_axi4_adapter_master_xactor_rg_rd_data[2:1] != 2'b0)
	$write("'h%h", 1'd0, " }");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps &&
	  llc_axi4_adapter_master_xactor_rg_rd_data[2:1] != 2'b0)
	$write("\n");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps &&
	  llc_axi4_adapter_master_xactor_rg_rd_data[2:1] != 2'b0)
	$finish(32'd1);
    if (RST_N != `BSV_RESET_VALUE)
      if (EN_ma_ddr4_ready)
	begin
	  v__h79349 = $stime;
	  #0;
	end
    v__h79343 = v__h79349 / 32'd10;
    if (RST_N != `BSV_RESET_VALUE)
      if (EN_ma_ddr4_ready)
	$display("%0d: %m.LLC_AXI4_Adapter.ma_ddr4_ready: enabling all rules",
		 v__h79343);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_llc_axi4_adapter_rl_discard_write_rsp &&
	  llc_axi4_adapter_master_xactor_rg_wr_resp[1:0] != 2'b0)
	begin
	  v__h39273 = $stime;
	  #0;
	end
    v__h39267 = v__h39273 / 32'd10;
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_llc_axi4_adapter_rl_discard_write_rsp &&
	  llc_axi4_adapter_master_xactor_rg_wr_resp[1:0] != 2'b0)
	$display("%0d: %m.LLC_AXI4_Adapter.rl_discard_write_rsp", v__h39267);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_llc_axi4_adapter_rl_discard_write_rsp &&
	  llc_axi4_adapter_master_xactor_rg_wr_resp[1:0] != 2'b0)
	$display("    ERROR: fabric response error: exit");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_llc_axi4_adapter_rl_discard_write_rsp &&
	  llc_axi4_adapter_master_xactor_rg_wr_resp[1:0] != 2'b0)
	$write("    ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_llc_axi4_adapter_rl_discard_write_rsp &&
	  llc_axi4_adapter_master_xactor_rg_wr_resp[1:0] != 2'b0)
	$write("AXI4_Wr_Resp { ", "bid: ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_llc_axi4_adapter_rl_discard_write_rsp &&
	  llc_axi4_adapter_master_xactor_rg_wr_resp[1:0] != 2'b0)
	$write("'h%h", llc_axi4_adapter_master_xactor_rg_wr_resp[17:2]);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_llc_axi4_adapter_rl_discard_write_rsp &&
	  llc_axi4_adapter_master_xactor_rg_wr_resp[1:0] != 2'b0)
	$write(", ", "bresp: ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_llc_axi4_adapter_rl_discard_write_rsp &&
	  llc_axi4_adapter_master_xactor_rg_wr_resp[1:0] != 2'b0)
	$write("'h%h", llc_axi4_adapter_master_xactor_rg_wr_resp[1:0]);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_llc_axi4_adapter_rl_discard_write_rsp &&
	  llc_axi4_adapter_master_xactor_rg_wr_resp[1:0] != 2'b0)
	$write(", ", "buser: ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_llc_axi4_adapter_rl_discard_write_rsp &&
	  llc_axi4_adapter_master_xactor_rg_wr_resp[1:0] != 2'b0)
	$write("'h%h", 1'd0, " }");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_llc_axi4_adapter_rl_discard_write_rsp &&
	  llc_axi4_adapter_master_xactor_rg_wr_resp[1:0] != 2'b0)
	$write("\n");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_llc_axi4_adapter_rl_discard_write_rsp &&
	  llc_axi4_adapter_master_xactor_rg_wr_resp[1:0] != 2'b0)
	$finish(32'd1);
  end
  // synopsys translate_on
endmodule  // mkNear_Mem

