//
// Generated by Bluespec Compiler, version 2022.01 (build 066c7a8)
//
//
// Ports:
// Name                         I/O  size props
// RDY_req                        O     1 const
// RDY_start                      O     1 const
// result_fst                     O     1 reg
// RDY_result_fst                 O     1
// result_snd_fst                 O    64 reg
// RDY_result_snd_fst             O     1
// result_snd_snd                 O    64 reg
// RDY_result_snd_snd             O     1
// mmio_client_request_get        O   131 reg
// RDY_mmio_client_request_get    O     1 reg
// RDY_mmio_client_response_put   O     1 reg
// CLK                            I     1 clock
// RST_N                          I     1 reset
// req_mmu_cache_req              I   208 reg
// start_pa                       I    64 reg
// mmio_client_response_put       I    65 reg
// EN_req                         I     1
// EN_start                       I     1
// EN_mmio_client_response_put    I     1
// EN_mmio_client_request_get     I     1
//
// No combinational paths from inputs to outputs
//
//

`ifdef BSV_ASSIGNMENT_DELAY
`else
  `define BSV_ASSIGNMENT_DELAY
`endif

`ifdef BSV_POSITIVE_RESET
  `define BSV_RESET_VALUE 1'b1
  `define BSV_RESET_EDGE posedge
`else
  `define BSV_RESET_VALUE 1'b0
  `define BSV_RESET_EDGE negedge
`endif

module mkMMIO(CLK,
	      RST_N,

	      req_mmu_cache_req,
	      EN_req,
	      RDY_req,

	      start_pa,
	      EN_start,
	      RDY_start,

	      result_fst,
	      RDY_result_fst,

	      result_snd_fst,
	      RDY_result_snd_fst,

	      result_snd_snd,
	      RDY_result_snd_snd,

	      EN_mmio_client_request_get,
	      mmio_client_request_get,
	      RDY_mmio_client_request_get,

	      mmio_client_response_put,
	      EN_mmio_client_response_put,
	      RDY_mmio_client_response_put);
  parameter [2 : 0] verbosity = 3'b0;
  input  CLK;
  input  RST_N;

  // action method req
  input  [207 : 0] req_mmu_cache_req;
  input  EN_req;
  output RDY_req;

  // action method start
  input  [63 : 0] start_pa;
  input  EN_start;
  output RDY_start;

  // value method result_fst
  output result_fst;
  output RDY_result_fst;

  // value method result_snd_fst
  output [63 : 0] result_snd_fst;
  output RDY_result_snd_fst;

  // value method result_snd_snd
  output [63 : 0] result_snd_snd;
  output RDY_result_snd_snd;

  // actionvalue method mmio_client_request_get
  input  EN_mmio_client_request_get;
  output [130 : 0] mmio_client_request_get;
  output RDY_mmio_client_request_get;

  // action method mmio_client_response_put
  input  [64 : 0] mmio_client_response_put;
  input  EN_mmio_client_response_put;
  output RDY_mmio_client_response_put;

  // signals for module outputs
  wire [130 : 0] mmio_client_request_get;
  wire [63 : 0] result_snd_fst, result_snd_snd;
  wire RDY_mmio_client_request_get,
       RDY_mmio_client_response_put,
       RDY_req,
       RDY_result_fst,
       RDY_result_snd_fst,
       RDY_result_snd_snd,
       RDY_start,
       result_fst;

  // register rg_err
  reg rg_err;
  wire rg_err$D_IN, rg_err$EN;

  // register rg_final_st_val
  reg [63 : 0] rg_final_st_val;
  wire [63 : 0] rg_final_st_val$D_IN;
  wire rg_final_st_val$EN;

  // register rg_fsm_state
  reg [1 : 0] rg_fsm_state;
  reg [1 : 0] rg_fsm_state$D_IN;
  wire rg_fsm_state$EN;

  // register rg_ld_val
  reg [63 : 0] rg_ld_val;
  wire [63 : 0] rg_ld_val$D_IN;
  wire rg_ld_val$EN;

  // register rg_pa
  reg [63 : 0] rg_pa;
  wire [63 : 0] rg_pa$D_IN;
  wire rg_pa$EN;

  // register rg_req
  reg [207 : 0] rg_req;
  wire [207 : 0] rg_req$D_IN;
  wire rg_req$EN;

  // ports of submodule f_single_reqs
  reg [130 : 0] f_single_reqs$D_IN;
  wire [130 : 0] f_single_reqs$D_OUT;
  wire f_single_reqs$CLR,
       f_single_reqs$DEQ,
       f_single_reqs$EMPTY_N,
       f_single_reqs$ENQ,
       f_single_reqs$FULL_N;

  // ports of submodule f_single_rsps
  wire [64 : 0] f_single_rsps$D_IN, f_single_rsps$D_OUT;
  wire f_single_rsps$CLR,
       f_single_rsps$DEQ,
       f_single_rsps$EMPTY_N,
       f_single_rsps$ENQ,
       f_single_rsps$FULL_N;

  // rule scheduling signals
  wire CAN_FIRE_RL_rl_AMO_SC,
       CAN_FIRE_RL_rl_read_req,
       CAN_FIRE_RL_rl_read_rsp,
       CAN_FIRE_RL_rl_write_req,
       CAN_FIRE_mmio_client_request_get,
       CAN_FIRE_mmio_client_response_put,
       CAN_FIRE_req,
       CAN_FIRE_start,
       WILL_FIRE_RL_rl_AMO_SC,
       WILL_FIRE_RL_rl_read_req,
       WILL_FIRE_RL_rl_read_rsp,
       WILL_FIRE_RL_rl_write_req,
       WILL_FIRE_mmio_client_request_get,
       WILL_FIRE_mmio_client_response_put,
       WILL_FIRE_req,
       WILL_FIRE_start;

  // inputs to muxes for submodule ports
  wire [130 : 0] MUX_f_single_reqs$enq_1__VAL_1,
		 MUX_f_single_reqs$enq_1__VAL_2,
		 MUX_f_single_reqs$enq_1__VAL_3;
  wire [63 : 0] MUX_rg_ld_val$write_1__VAL_1;
  wire MUX_f_single_reqs$enq_1__SEL_1,
       MUX_rg_fsm_state$write_1__SEL_2,
       MUX_rg_fsm_state$write_1__SEL_3,
       MUX_rg_fsm_state$write_1__SEL_4,
       MUX_rg_fsm_state$write_1__SEL_5,
       MUX_rg_ld_val$write_1__SEL_1;

  // declarations used by system tasks
  // synopsys translate_off
  reg [31 : 0] v__h559;
  reg [31 : 0] v__h774;
  reg [31 : 0] v__h1989;
  reg [31 : 0] v__h2297;
  reg [31 : 0] v__h2548;
  reg [31 : 0] v__h2727;
  reg [31 : 0] v__h553;
  reg [31 : 0] v__h768;
  reg [31 : 0] v__h1983;
  reg [31 : 0] v__h2291;
  reg [31 : 0] v__h2542;
  reg [31 : 0] v__h2721;
  // synopsys translate_on

  // remaining internal signals
  reg [63 : 0] _theResult_____2__h1468, mask__h1029, y__h1286;
  reg CASE_rg_req_BITS_204_TO_203_0b0_f_single_rsps_ETC__q2;
  wire [63 : 0] IF_rg_req_BITS_204_TO_203_6_EQ_0b10_1_THEN_SEX_ETC___d88,
		final_ld_val__h1410,
		final_st_val__h1411,
		final_st_val__h1492,
		final_st_val__h1582,
		final_st_val__h1659,
		final_st_val__h1663,
		final_st_val__h1667,
		final_st_val__h1671,
		final_st_val__h1676,
		final_st_val__h1682,
		final_st_val__h1687,
		ld_val__h1000,
		result__h1274,
		result__h1341,
		w1___1__h1551,
		w1__h1461,
		w2___1__h1552,
		w2__h1463;
  wire [31 : 0] f_single_rspsD_OUT_BITS_31_TO_0__q1,
		rg_req_BITS_106_TO_75__q3;
  wire f_single_rsps_first__7_BIT_64_8_AND_NOT_rg_req_ETC___d125;

  // action method req
  assign RDY_req = 1'd1 ;
  assign CAN_FIRE_req = 1'd1 ;
  assign WILL_FIRE_req = EN_req ;

  // action method start
  assign RDY_start = 1'd1 ;
  assign CAN_FIRE_start = 1'd1 ;
  assign WILL_FIRE_start = EN_start ;

  // value method result_fst
  assign result_fst = rg_err ;
  assign RDY_result_fst = rg_fsm_state == 2'd0 ;

  // value method result_snd_fst
  assign result_snd_fst = rg_ld_val ;
  assign RDY_result_snd_fst = rg_fsm_state == 2'd0 ;

  // value method result_snd_snd
  assign result_snd_snd = rg_final_st_val ;
  assign RDY_result_snd_snd = rg_fsm_state == 2'd0 ;

  // actionvalue method mmio_client_request_get
  assign mmio_client_request_get = f_single_reqs$D_OUT ;
  assign RDY_mmio_client_request_get = f_single_reqs$EMPTY_N ;
  assign CAN_FIRE_mmio_client_request_get = f_single_reqs$EMPTY_N ;
  assign WILL_FIRE_mmio_client_request_get = EN_mmio_client_request_get ;

  // action method mmio_client_response_put
  assign RDY_mmio_client_response_put = f_single_rsps$FULL_N ;
  assign CAN_FIRE_mmio_client_response_put = f_single_rsps$FULL_N ;
  assign WILL_FIRE_mmio_client_response_put = EN_mmio_client_response_put ;

  // submodule f_single_reqs
  FIFO2 #(.width(32'd131), .guarded(1'd1)) f_single_reqs(.RST(RST_N),
							 .CLK(CLK),
							 .D_IN(f_single_reqs$D_IN),
							 .ENQ(f_single_reqs$ENQ),
							 .DEQ(f_single_reqs$DEQ),
							 .CLR(f_single_reqs$CLR),
							 .D_OUT(f_single_reqs$D_OUT),
							 .FULL_N(f_single_reqs$FULL_N),
							 .EMPTY_N(f_single_reqs$EMPTY_N));

  // submodule f_single_rsps
  FIFO2 #(.width(32'd65), .guarded(1'd1)) f_single_rsps(.RST(RST_N),
							.CLK(CLK),
							.D_IN(f_single_rsps$D_IN),
							.ENQ(f_single_rsps$ENQ),
							.DEQ(f_single_rsps$DEQ),
							.CLR(f_single_rsps$CLR),
							.D_OUT(f_single_rsps$D_OUT),
							.FULL_N(f_single_rsps$FULL_N),
							.EMPTY_N(f_single_rsps$EMPTY_N));

  // rule RL_rl_read_req
  assign CAN_FIRE_RL_rl_read_req = MUX_rg_fsm_state$write_1__SEL_5 ;
  assign WILL_FIRE_RL_rl_read_req = MUX_rg_fsm_state$write_1__SEL_5 ;

  // rule RL_rl_read_rsp
  assign CAN_FIRE_RL_rl_read_rsp = MUX_rg_fsm_state$write_1__SEL_4 ;
  assign WILL_FIRE_RL_rl_read_rsp = MUX_rg_fsm_state$write_1__SEL_4 ;

  // rule RL_rl_write_req
  assign CAN_FIRE_RL_rl_write_req = MUX_rg_fsm_state$write_1__SEL_3 ;
  assign WILL_FIRE_RL_rl_write_req = MUX_rg_fsm_state$write_1__SEL_3 ;

  // rule RL_rl_AMO_SC
  assign CAN_FIRE_RL_rl_AMO_SC = MUX_rg_fsm_state$write_1__SEL_2 ;
  assign WILL_FIRE_RL_rl_AMO_SC = MUX_rg_fsm_state$write_1__SEL_2 ;

  // inputs to muxes for submodule ports
  assign MUX_f_single_reqs$enq_1__SEL_1 =
	     WILL_FIRE_RL_rl_read_rsp && f_single_rsps$D_OUT[64] &&
	     rg_req[207:206] != 2'd0 &&
	     (rg_req[207:206] != 2'd2 || rg_req[74:70] != 5'b00010) ;
  assign MUX_rg_fsm_state$write_1__SEL_2 =
	     rg_fsm_state == 2'd1 && rg_req[207:206] == 2'd2 &&
	     rg_req[74:70] == 5'b00011 ;
  assign MUX_rg_fsm_state$write_1__SEL_3 =
	     f_single_reqs$FULL_N && rg_fsm_state == 2'd1 &&
	     rg_req[207:206] == 2'd1 ;
  assign MUX_rg_fsm_state$write_1__SEL_4 =
	     f_single_rsps$EMPTY_N &&
	     (!f_single_rsps$D_OUT[64] || rg_req[207:206] == 2'd0 ||
	      rg_req[207:206] == 2'd2 && rg_req[74:70] == 5'b00010 ||
	      f_single_reqs$FULL_N) &&
	     rg_fsm_state == 2'd2 ;
  assign MUX_rg_fsm_state$write_1__SEL_5 =
	     f_single_reqs$FULL_N && rg_fsm_state == 2'd1 &&
	     rg_req[207:206] != 2'd1 &&
	     (rg_req[207:206] != 2'd2 || rg_req[74:70] != 5'b00011) ;
  assign MUX_rg_ld_val$write_1__SEL_1 =
	     WILL_FIRE_RL_rl_read_rsp && f_single_rsps$D_OUT[64] ;
  assign MUX_f_single_reqs$enq_1__VAL_1 =
	     { 1'd0, rg_pa, rg_req[204:203], final_st_val__h1411 } ;
  assign MUX_f_single_reqs$enq_1__VAL_2 = { 1'd1, rg_pa, rg_req[204:139] } ;
  assign MUX_f_single_reqs$enq_1__VAL_3 =
	     { 1'd0, rg_pa, rg_req[204:203], rg_req[138:75] } ;
  assign MUX_rg_ld_val$write_1__VAL_1 =
	     (rg_req[207:206] == 2'd0 ||
	      rg_req[207:206] == 2'd2 && rg_req[74:70] == 5'b00010) ?
	       ld_val__h1000 :
	       final_ld_val__h1410 ;

  // register rg_err
  assign rg_err$D_IN = !EN_req ;
  assign rg_err$EN =
	     WILL_FIRE_RL_rl_read_rsp && !f_single_rsps$D_OUT[64] || EN_req ;

  // register rg_final_st_val
  assign rg_final_st_val$D_IN =
	     MUX_f_single_reqs$enq_1__SEL_1 ?
	       final_st_val__h1411 :
	       rg_req[138:75] ;
  assign rg_final_st_val$EN =
	     WILL_FIRE_RL_rl_read_rsp && f_single_rsps$D_OUT[64] &&
	     rg_req[207:206] != 2'd0 &&
	     (rg_req[207:206] != 2'd2 || rg_req[74:70] != 5'b00010) ||
	     WILL_FIRE_RL_rl_write_req ;

  // register rg_fsm_state
  always@(EN_start or
	  WILL_FIRE_RL_rl_AMO_SC or
	  WILL_FIRE_RL_rl_write_req or
	  WILL_FIRE_RL_rl_read_rsp or WILL_FIRE_RL_rl_read_req)
  case (1'b1)
    EN_start: rg_fsm_state$D_IN = 2'd1;
    WILL_FIRE_RL_rl_AMO_SC || WILL_FIRE_RL_rl_write_req ||
    WILL_FIRE_RL_rl_read_rsp:
	rg_fsm_state$D_IN = 2'd0;
    WILL_FIRE_RL_rl_read_req: rg_fsm_state$D_IN = 2'd2;
    default: rg_fsm_state$D_IN = 2'b10 /* unspecified value */ ;
  endcase
  assign rg_fsm_state$EN =
	     WILL_FIRE_RL_rl_AMO_SC || WILL_FIRE_RL_rl_write_req ||
	     WILL_FIRE_RL_rl_read_rsp ||
	     EN_start ||
	     WILL_FIRE_RL_rl_read_req ;

  // register rg_ld_val
  assign rg_ld_val$D_IN =
	     MUX_rg_ld_val$write_1__SEL_1 ?
	       MUX_rg_ld_val$write_1__VAL_1 :
	       64'd1 ;
  assign rg_ld_val$EN =
	     WILL_FIRE_RL_rl_read_rsp && f_single_rsps$D_OUT[64] ||
	     WILL_FIRE_RL_rl_AMO_SC ;

  // register rg_pa
  assign rg_pa$D_IN = start_pa ;
  assign rg_pa$EN = EN_start ;

  // register rg_req
  assign rg_req$D_IN = req_mmu_cache_req ;
  assign rg_req$EN = EN_req ;

  // submodule f_single_reqs
  always@(MUX_f_single_reqs$enq_1__SEL_1 or
	  MUX_f_single_reqs$enq_1__VAL_1 or
	  WILL_FIRE_RL_rl_read_req or
	  MUX_f_single_reqs$enq_1__VAL_2 or
	  WILL_FIRE_RL_rl_write_req or MUX_f_single_reqs$enq_1__VAL_3)
  begin
    case (1'b1) // synopsys parallel_case
      MUX_f_single_reqs$enq_1__SEL_1:
	  f_single_reqs$D_IN = MUX_f_single_reqs$enq_1__VAL_1;
      WILL_FIRE_RL_rl_read_req:
	  f_single_reqs$D_IN = MUX_f_single_reqs$enq_1__VAL_2;
      WILL_FIRE_RL_rl_write_req:
	  f_single_reqs$D_IN = MUX_f_single_reqs$enq_1__VAL_3;
      default: f_single_reqs$D_IN =
		   131'h2AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA /* unspecified value */ ;
    endcase
  end
  assign f_single_reqs$ENQ =
	     WILL_FIRE_RL_rl_read_rsp && f_single_rsps$D_OUT[64] &&
	     rg_req[207:206] != 2'd0 &&
	     (rg_req[207:206] != 2'd2 || rg_req[74:70] != 5'b00010) ||
	     WILL_FIRE_RL_rl_read_req ||
	     WILL_FIRE_RL_rl_write_req ;
  assign f_single_reqs$DEQ = EN_mmio_client_request_get ;
  assign f_single_reqs$CLR = 1'b0 ;

  // submodule f_single_rsps
  assign f_single_rsps$D_IN = mmio_client_response_put ;
  assign f_single_rsps$ENQ = EN_mmio_client_response_put ;
  assign f_single_rsps$DEQ = MUX_rg_fsm_state$write_1__SEL_4 ;
  assign f_single_rsps$CLR = 1'b0 ;

  // remaining internal signals
  assign IF_rg_req_BITS_204_TO_203_6_EQ_0b10_1_THEN_SEX_ETC___d88 =
	     (rg_req[204:203] == 2'b10) ?
	       { {32{rg_req_BITS_106_TO_75__q3[31]}},
		 rg_req_BITS_106_TO_75__q3 } :
	       rg_req[138:75] ;
  assign f_single_rspsD_OUT_BITS_31_TO_0__q1 = f_single_rsps$D_OUT[31:0] ;
  assign f_single_rsps_first__7_BIT_64_8_AND_NOT_rg_req_ETC___d125 =
	     f_single_rsps$D_OUT[64] && rg_req[207:206] != 2'd0 &&
	     (rg_req[207:206] != 2'd2 || rg_req[74:70] != 5'b00010) &&
	     verbosity != 3'd0 ;
  assign final_ld_val__h1410 =
	     (rg_req[204:203] == 2'b10) ?
	       { {32{f_single_rspsD_OUT_BITS_31_TO_0__q1[31]}},
		 f_single_rspsD_OUT_BITS_31_TO_0__q1 } :
	       f_single_rsps$D_OUT[63:0] ;
  assign final_st_val__h1411 =
	     (rg_req[204:203] == 2'b10) ?
	       final_st_val__h1492 :
	       _theResult_____2__h1468 ;
  assign final_st_val__h1492 = { 32'd0, _theResult_____2__h1468[31:0] } ;
  assign final_st_val__h1582 =
	     final_ld_val__h1410 +
	     IF_rg_req_BITS_204_TO_203_6_EQ_0b10_1_THEN_SEX_ETC___d88 ;
  assign final_st_val__h1659 = w1__h1461 ^ w2__h1463 ;
  assign final_st_val__h1663 = w1__h1461 & w2__h1463 ;
  assign final_st_val__h1667 = w1__h1461 | w2__h1463 ;
  assign final_st_val__h1671 =
	     (w1__h1461 < w2__h1463) ? w1__h1461 : w2__h1463 ;
  assign final_st_val__h1676 =
	     (w1__h1461 <= w2__h1463) ? w2__h1463 : w1__h1461 ;
  assign final_st_val__h1682 =
	     ((final_ld_val__h1410 ^ 64'h8000000000000000) <
	      (IF_rg_req_BITS_204_TO_203_6_EQ_0b10_1_THEN_SEX_ETC___d88 ^
	       64'h8000000000000000)) ?
	       w1__h1461 :
	       w2__h1463 ;
  assign final_st_val__h1687 =
	     ((final_ld_val__h1410 ^ 64'h8000000000000000) <=
	      (IF_rg_req_BITS_204_TO_203_6_EQ_0b10_1_THEN_SEX_ETC___d88 ^
	       64'h8000000000000000)) ?
	       w2__h1463 :
	       w1__h1461 ;
  assign ld_val__h1000 =
	     (!rg_req[205] &&
	      CASE_rg_req_BITS_204_TO_203_0b0_f_single_rsps_ETC__q2) ?
	       result__h1274 :
	       result__h1341 ;
  assign result__h1274 = f_single_rsps$D_OUT[63:0] | y__h1286 ;
  assign result__h1341 = f_single_rsps$D_OUT[63:0] & mask__h1029 ;
  assign rg_req_BITS_106_TO_75__q3 = rg_req[106:75] ;
  assign w1___1__h1551 = { 32'd0, f_single_rsps$D_OUT[31:0] } ;
  assign w1__h1461 =
	     (rg_req[204:203] == 2'b10) ?
	       w1___1__h1551 :
	       f_single_rsps$D_OUT[63:0] ;
  assign w2___1__h1552 = { 32'd0, rg_req[106:75] } ;
  assign w2__h1463 =
	     (rg_req[204:203] == 2'b10) ? w2___1__h1552 : rg_req[138:75] ;
  always@(rg_req)
  begin
    case (rg_req[204:203])
      2'b0: mask__h1029 = 64'h00000000000000FF;
      2'b01: mask__h1029 = 64'h000000000000FFFF;
      2'b10: mask__h1029 = 64'h00000000FFFFFFFF;
      2'd3: mask__h1029 = 64'hFFFFFFFFFFFFFFFF;
    endcase
  end
  always@(rg_req)
  begin
    case (rg_req[204:203])
      2'b0: y__h1286 = 64'hFFFFFFFFFFFFFF00;
      2'b01: y__h1286 = 64'hFFFFFFFFFFFF0000;
      2'b10: y__h1286 = 64'hFFFFFFFF00000000;
      2'd3: y__h1286 = 64'd0;
    endcase
  end
  always@(rg_req or f_single_rsps$D_OUT)
  begin
    case (rg_req[204:203])
      2'b0:
	  CASE_rg_req_BITS_204_TO_203_0b0_f_single_rsps_ETC__q2 =
	      f_single_rsps$D_OUT[7];
      2'b01:
	  CASE_rg_req_BITS_204_TO_203_0b0_f_single_rsps_ETC__q2 =
	      f_single_rsps$D_OUT[15];
      2'b10:
	  CASE_rg_req_BITS_204_TO_203_0b0_f_single_rsps_ETC__q2 =
	      f_single_rsps$D_OUT[31];
      2'd3:
	  CASE_rg_req_BITS_204_TO_203_0b0_f_single_rsps_ETC__q2 =
	      f_single_rsps$D_OUT[63];
    endcase
  end
  always@(rg_req or
	  final_st_val__h1687 or
	  final_st_val__h1582 or
	  w2__h1463 or
	  final_st_val__h1659 or
	  final_st_val__h1667 or
	  final_st_val__h1663 or
	  final_st_val__h1682 or final_st_val__h1671 or final_st_val__h1676)
  begin
    case (rg_req[74:70])
      5'b0: _theResult_____2__h1468 = final_st_val__h1582;
      5'b00001: _theResult_____2__h1468 = w2__h1463;
      5'b00100: _theResult_____2__h1468 = final_st_val__h1659;
      5'b01000: _theResult_____2__h1468 = final_st_val__h1667;
      5'b01100: _theResult_____2__h1468 = final_st_val__h1663;
      5'b10000: _theResult_____2__h1468 = final_st_val__h1682;
      5'b11000: _theResult_____2__h1468 = final_st_val__h1671;
      5'b11100: _theResult_____2__h1468 = final_st_val__h1676;
      default: _theResult_____2__h1468 = final_st_val__h1687;
    endcase
  end

  // handling of inlined registers

  always@(posedge CLK)
  begin
    if (RST_N == `BSV_RESET_VALUE)
      begin
        rg_err <= `BSV_ASSIGNMENT_DELAY 1'd0;
	rg_final_st_val <= `BSV_ASSIGNMENT_DELAY 64'd0;
	rg_fsm_state <= `BSV_ASSIGNMENT_DELAY 2'd0;
	rg_ld_val <= `BSV_ASSIGNMENT_DELAY 64'd0;
      end
    else
      begin
        if (rg_err$EN) rg_err <= `BSV_ASSIGNMENT_DELAY rg_err$D_IN;
	if (rg_final_st_val$EN)
	  rg_final_st_val <= `BSV_ASSIGNMENT_DELAY rg_final_st_val$D_IN;
	if (rg_fsm_state$EN)
	  rg_fsm_state <= `BSV_ASSIGNMENT_DELAY rg_fsm_state$D_IN;
	if (rg_ld_val$EN) rg_ld_val <= `BSV_ASSIGNMENT_DELAY rg_ld_val$D_IN;
      end
    if (rg_pa$EN) rg_pa <= `BSV_ASSIGNMENT_DELAY rg_pa$D_IN;
    if (rg_req$EN) rg_req <= `BSV_ASSIGNMENT_DELAY rg_req$D_IN;
  end

  // synopsys translate_off
  `ifdef BSV_NO_INITIAL_BLOCKS
  `else // not BSV_NO_INITIAL_BLOCKS
  initial
  begin
    rg_err = 1'h0;
    rg_final_st_val = 64'hAAAAAAAAAAAAAAAA;
    rg_fsm_state = 2'h2;
    rg_ld_val = 64'hAAAAAAAAAAAAAAAA;
    rg_pa = 64'hAAAAAAAAAAAAAAAA;
    rg_req = 208'hAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA;
  end
  `endif // BSV_NO_INITIAL_BLOCKS
  // synopsys translate_on

  // handling of system tasks

  // synopsys translate_off
  always@(negedge CLK)
  begin
    #0;
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_read_req && verbosity != 3'd0)
	begin
	  v__h559 = $stime;
	  #0;
	end
    v__h553 = v__h559 / 32'd10;
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_read_req && verbosity != 3'd0)
	$display("%0d: %m.rl_read_req: f3 %0h vaddr %0h  paddr %0h",
		 v__h553,
		 rg_req[205:203],
		 rg_req[202:139],
		 rg_pa);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_read_rsp && verbosity != 3'd0)
	begin
	  v__h774 = $stime;
	  #0;
	end
    v__h768 = v__h774 / 32'd10;
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_read_rsp && verbosity != 3'd0)
	$display("%0d: %m.rl_read_rsp: vaddr %0h  paddr %0h",
		 v__h768,
		 rg_req[202:139],
		 rg_pa);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_read_rsp && verbosity != 3'd0) $write("    ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_read_rsp && verbosity != 3'd0)
	$write("Single_Rsp { ", "ok: ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_read_rsp && verbosity != 3'd0 &&
	  f_single_rsps$D_OUT[64])
	$write("True");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_read_rsp && verbosity != 3'd0 &&
	  !f_single_rsps$D_OUT[64])
	$write("False");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_read_rsp && verbosity != 3'd0)
	$write(", ", "data: ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_read_rsp && verbosity != 3'd0)
	$write("'h%h", f_single_rsps$D_OUT[63:0], " }");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_read_rsp && verbosity != 3'd0) $write("\n");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_read_rsp && f_single_rsps$D_OUT[64] &&
	  (rg_req[207:206] == 2'd0 ||
	   rg_req[207:206] == 2'd2 && rg_req[74:70] == 5'b00010) &&
	  verbosity != 3'd0)
	$display("    Load or LR: f3 %0h ld_val %0h",
		 rg_req[205:203],
		 ld_val__h1000);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_read_rsp &&
	  f_single_rsps_first__7_BIT_64_8_AND_NOT_rg_req_ETC___d125)
	$display("    AMO: f3 %0d  f7 %0h  ld_val %0h st_val %0h",
		 rg_req[205:203],
		 rg_req[74:68],
		 f_single_rsps$D_OUT[63:0],
		 rg_req[138:75]);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_read_rsp &&
	  f_single_rsps_first__7_BIT_64_8_AND_NOT_rg_req_ETC___d125)
	$display("    => final_ld_val %0h final_st_val %0h",
		 final_ld_val__h1410,
		 final_st_val__h1411);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_read_rsp && !f_single_rsps$D_OUT[64] &&
	  verbosity != 3'd0)
	$display("    MEM_RSP_ERR");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_write_req && verbosity != 3'd0)
	begin
	  v__h1989 = $stime;
	  #0;
	end
    v__h1983 = v__h1989 / 32'd10;
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_write_req && verbosity != 3'd0)
	$display("%0d: %m.rl_write_req; f3 %0h  vaddr %0h  paddr %0h  word64 %0h",
		 v__h1983,
		 rg_req[205:203],
		 rg_req[202:139],
		 rg_pa,
		 rg_req[138:75]);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_write_req && verbosity >= 3'd2)
	$display("    => FSM_IDLE");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_AMO_SC && verbosity != 3'd0)
	begin
	  v__h2297 = $stime;
	  #0;
	end
    v__h2291 = v__h2297 / 32'd10;
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_AMO_SC && verbosity != 3'd0)
	$display("%0d: %m.rl_AMO_SC; f3 %0h  vaddr %0h  paddr %0h  st_value %0h",
		 v__h2291,
		 rg_req[205:203],
		 rg_req[202:139],
		 rg_pa,
		 rg_req[138:75]);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_AMO_SC && verbosity != 3'd0)
	$display("    FAIL due to I/O address.");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_AMO_SC && verbosity != 3'd0)
	$display("    => FSM_IDLE");
    if (RST_N != `BSV_RESET_VALUE)
      if (EN_req && verbosity != 3'd0)
	begin
	  v__h2548 = $stime;
	  #0;
	end
    v__h2542 = v__h2548 / 32'd10;
    if (RST_N != `BSV_RESET_VALUE)
      if (EN_req && verbosity != 3'd0) $display("%0d: %m.ma_req", v__h2542);
    if (RST_N != `BSV_RESET_VALUE)
      if (EN_req && verbosity != 3'd0) $write("    ");
    if (RST_N != `BSV_RESET_VALUE)
      if (EN_req && verbosity != 3'd0) $write("MMU_Cache_Req { ", "op: ");
    if (RST_N != `BSV_RESET_VALUE)
      if (EN_req && verbosity != 3'd0 && req_mmu_cache_req[207:206] == 2'd0)
	$write("CACHE_LD");
    if (RST_N != `BSV_RESET_VALUE)
      if (EN_req && verbosity != 3'd0 && req_mmu_cache_req[207:206] == 2'd1)
	$write("CACHE_ST");
    if (RST_N != `BSV_RESET_VALUE)
      if (EN_req && verbosity != 3'd0 && req_mmu_cache_req[207:206] != 2'd0 &&
	  req_mmu_cache_req[207:206] != 2'd1)
	$write("CACHE_AMO");
    if (RST_N != `BSV_RESET_VALUE)
      if (EN_req && verbosity != 3'd0) $write(", ", "f3: ");
    if (RST_N != `BSV_RESET_VALUE)
      if (EN_req && verbosity != 3'd0)
	$write("'h%h", req_mmu_cache_req[205:203]);
    if (RST_N != `BSV_RESET_VALUE)
      if (EN_req && verbosity != 3'd0) $write(", ", "va: ");
    if (RST_N != `BSV_RESET_VALUE)
      if (EN_req && verbosity != 3'd0)
	$write("'h%h", req_mmu_cache_req[202:139]);
    if (RST_N != `BSV_RESET_VALUE)
      if (EN_req && verbosity != 3'd0) $write(", ", "st_value: ");
    if (RST_N != `BSV_RESET_VALUE)
      if (EN_req && verbosity != 3'd0)
	$write("'h%h", req_mmu_cache_req[138:75]);
    if (RST_N != `BSV_RESET_VALUE)
      if (EN_req && verbosity != 3'd0) $write(", ", "amo_funct7: ");
    if (RST_N != `BSV_RESET_VALUE)
      if (EN_req && verbosity != 3'd0)
	$write("'h%h", req_mmu_cache_req[74:68]);
    if (RST_N != `BSV_RESET_VALUE)
      if (EN_req && verbosity != 3'd0) $write(", ", "priv: ");
    if (RST_N != `BSV_RESET_VALUE)
      if (EN_req && verbosity != 3'd0)
	$write("'h%h", req_mmu_cache_req[67:66]);
    if (RST_N != `BSV_RESET_VALUE)
      if (EN_req && verbosity != 3'd0) $write(", ", "sstatus_SUM: ");
    if (RST_N != `BSV_RESET_VALUE)
      if (EN_req && verbosity != 3'd0) $write("'h%h", req_mmu_cache_req[65]);
    if (RST_N != `BSV_RESET_VALUE)
      if (EN_req && verbosity != 3'd0) $write(", ", "mstatus_MXR: ");
    if (RST_N != `BSV_RESET_VALUE)
      if (EN_req && verbosity != 3'd0) $write("'h%h", req_mmu_cache_req[64]);
    if (RST_N != `BSV_RESET_VALUE)
      if (EN_req && verbosity != 3'd0) $write(", ", "satp: ");
    if (RST_N != `BSV_RESET_VALUE)
      if (EN_req && verbosity != 3'd0)
	$write("'h%h", req_mmu_cache_req[63:0], " }");
    if (RST_N != `BSV_RESET_VALUE)
      if (EN_req && verbosity != 3'd0) $write("\n");
    if (RST_N != `BSV_RESET_VALUE)
      if (EN_start && verbosity != 3'd0)
	begin
	  v__h2727 = $stime;
	  #0;
	end
    v__h2721 = v__h2727 / 32'd10;
    if (RST_N != `BSV_RESET_VALUE)
      if (EN_start && verbosity != 3'd0)
	$display("%0d: %m.ma_start", v__h2721);
    if (RST_N != `BSV_RESET_VALUE)
      if (EN_start && verbosity != 3'd0) $display("    add %0h", start_pa);
  end
  // synopsys translate_on
endmodule  // mkMMIO

