read_verilog -sv /eda/processor_ci/rtl/Flute.sv
read_verilog /var/jenkins_home/workspace/Flute/Flute/builds/Flute_RV32CI_MU_WT_L1_iverilog_tohost/Verilog_RTL/mkAXI4_Deburster_A.v
read_verilog /var/jenkins_home/workspace/Flute/Flute/builds/Flute_RV32CI_MU_WT_L1_iverilog_tohost/Verilog_RTL/mkBoot_ROM.v
read_verilog /var/jenkins_home/workspace/Flute/Flute/builds/Flute_RV32CI_MU_WT_L1_iverilog_tohost/Verilog_RTL/mkBranch_Predictor.v
read_verilog /var/jenkins_home/workspace/Flute/Flute/builds/Flute_RV32CI_MU_WT_L1_iverilog_tohost/Verilog_RTL/mkCPU.v
read_verilog /var/jenkins_home/workspace/Flute/Flute/builds/Flute_RV32CI_MU_WT_L1_iverilog_tohost/Verilog_RTL/mkCSR_MIE.v
read_verilog /var/jenkins_home/workspace/Flute/Flute/builds/Flute_RV32CI_MU_WT_L1_iverilog_tohost/Verilog_RTL/mkCSR_MIP.v
read_verilog /var/jenkins_home/workspace/Flute/Flute/builds/Flute_RV32CI_MU_WT_L1_iverilog_tohost/Verilog_RTL/mkCSR_RegFile.v
read_verilog /var/jenkins_home/workspace/Flute/Flute/builds/Flute_RV32CI_MU_WT_L1_iverilog_tohost/Verilog_RTL/mkCore.v
read_verilog /var/jenkins_home/workspace/Flute/Flute/builds/Flute_RV32CI_MU_WT_L1_iverilog_tohost/Verilog_RTL/mkFabric_2x3.v
read_verilog /var/jenkins_home/workspace/Flute/Flute/builds/Flute_RV32CI_MU_WT_L1_iverilog_tohost/Verilog_RTL/mkFabric_AXI4.v
read_verilog /var/jenkins_home/workspace/Flute/Flute/builds/Flute_RV32CI_MU_WT_L1_iverilog_tohost/Verilog_RTL/mkGPR_RegFile.v
read_verilog /var/jenkins_home/workspace/Flute/Flute/builds/Flute_RV32CI_MU_WT_L1_iverilog_tohost/Verilog_RTL/mkMMU_Cache.v
read_verilog /var/jenkins_home/workspace/Flute/Flute/builds/Flute_RV32CI_MU_WT_L1_iverilog_tohost/Verilog_RTL/mkMem_Controller.v
read_verilog /var/jenkins_home/workspace/Flute/Flute/builds/Flute_RV32CI_MU_WT_L1_iverilog_tohost/Verilog_RTL/mkMem_Model.v
read_verilog /var/jenkins_home/workspace/Flute/Flute/builds/Flute_RV32CI_MU_WT_L1_iverilog_tohost/Verilog_RTL/mkNear_Mem.v
read_verilog /var/jenkins_home/workspace/Flute/Flute/builds/Flute_RV32CI_MU_WT_L1_iverilog_tohost/Verilog_RTL/mkNear_Mem_IO_AXI4.v
read_verilog /var/jenkins_home/workspace/Flute/Flute/builds/Flute_RV32CI_MU_WT_L1_iverilog_tohost/Verilog_RTL/mkPLIC_16_2_7.v
read_verilog /var/jenkins_home/workspace/Flute/Flute/builds/Flute_RV32CI_MU_WT_L1_iverilog_tohost/Verilog_RTL/mkSoC_Map.v
read_verilog /var/jenkins_home/workspace/Flute/Flute/builds/Flute_RV32CI_MU_WT_L1_iverilog_tohost/Verilog_RTL/mkSoC_Top.v
read_verilog /var/jenkins_home/workspace/Flute/Flute/builds/Flute_RV32CI_MU_WT_L1_iverilog_tohost/Verilog_RTL/mkTop_HW_Side.v
read_verilog /var/jenkins_home/workspace/Flute/Flute/builds/Flute_RV32CI_MU_WT_L1_iverilog_tohost/Verilog_RTL/mkUART.v
read_verilog /var/jenkins_home/workspace/Flute/Flute/builds/Flute_RV64GC_MSU_WB_L1_L2_verilator_tohost/Verilog_RTL/mkAXI4_Deburster_A.v
read_verilog /var/jenkins_home/workspace/Flute/Flute/builds/Flute_RV64GC_MSU_WB_L1_L2_verilator_tohost/Verilog_RTL/mkBoot_ROM.v
read_verilog /var/jenkins_home/workspace/Flute/Flute/builds/Flute_RV64GC_MSU_WB_L1_L2_verilator_tohost/Verilog_RTL/mkBranch_Predictor.v
read_verilog /var/jenkins_home/workspace/Flute/Flute/builds/Flute_RV64GC_MSU_WB_L1_L2_verilator_tohost/Verilog_RTL/mkCPU.v
read_verilog /var/jenkins_home/workspace/Flute/Flute/builds/Flute_RV64GC_MSU_WB_L1_L2_verilator_tohost/Verilog_RTL/mkCSR_MIE.v
read_verilog /var/jenkins_home/workspace/Flute/Flute/builds/Flute_RV64GC_MSU_WB_L1_L2_verilator_tohost/Verilog_RTL/mkCSR_MIP.v
read_verilog /var/jenkins_home/workspace/Flute/Flute/builds/Flute_RV64GC_MSU_WB_L1_L2_verilator_tohost/Verilog_RTL/mkCSR_RegFile.v
read_verilog /var/jenkins_home/workspace/Flute/Flute/builds/Flute_RV64GC_MSU_WB_L1_L2_verilator_tohost/Verilog_RTL/mkCache.v
read_verilog /var/jenkins_home/workspace/Flute/Flute/builds/Flute_RV64GC_MSU_WB_L1_L2_verilator_tohost/Verilog_RTL/mkCore.v
read_verilog /var/jenkins_home/workspace/Flute/Flute/builds/Flute_RV64GC_MSU_WB_L1_L2_verilator_tohost/Verilog_RTL/mkDMA_Cache.v
read_verilog /var/jenkins_home/workspace/Flute/Flute/builds/Flute_RV64GC_MSU_WB_L1_L2_verilator_tohost/Verilog_RTL/mkD_MMU_Cache.v
read_verilog /var/jenkins_home/workspace/Flute/Flute/builds/Flute_RV64GC_MSU_WB_L1_L2_verilator_tohost/Verilog_RTL/mkFBox_Core.v
read_verilog /var/jenkins_home/workspace/Flute/Flute/builds/Flute_RV64GC_MSU_WB_L1_L2_verilator_tohost/Verilog_RTL/mkFBox_Top.v
read_verilog /var/jenkins_home/workspace/Flute/Flute/builds/Flute_RV64GC_MSU_WB_L1_L2_verilator_tohost/Verilog_RTL/mkFPR_RegFile.v
read_verilog /var/jenkins_home/workspace/Flute/Flute/builds/Flute_RV64GC_MSU_WB_L1_L2_verilator_tohost/Verilog_RTL/mkFPU.v
read_verilog /var/jenkins_home/workspace/Flute/Flute/builds/Flute_RV64GC_MSU_WB_L1_L2_verilator_tohost/Verilog_RTL/mkFabric_1x3.v
read_verilog /var/jenkins_home/workspace/Flute/Flute/builds/Flute_RV64GC_MSU_WB_L1_L2_verilator_tohost/Verilog_RTL/mkFabric_AXI4.v
read_verilog /var/jenkins_home/workspace/Flute/Flute/builds/Flute_RV64GC_MSU_WB_L1_L2_verilator_tohost/Verilog_RTL/mkGPR_RegFile.v
read_verilog /var/jenkins_home/workspace/Flute/Flute/builds/Flute_RV64GC_MSU_WB_L1_L2_verilator_tohost/Verilog_RTL/mkI_MMU_Cache.v
read_verilog /var/jenkins_home/workspace/Flute/Flute/builds/Flute_RV64GC_MSU_WB_L1_L2_verilator_tohost/Verilog_RTL/mkIntMul_32.v
read_verilog /var/jenkins_home/workspace/Flute/Flute/builds/Flute_RV64GC_MSU_WB_L1_L2_verilator_tohost/Verilog_RTL/mkIntMul_64.v
read_verilog /var/jenkins_home/workspace/Flute/Flute/builds/Flute_RV64GC_MSU_WB_L1_L2_verilator_tohost/Verilog_RTL/mkLLCache.v
read_verilog /var/jenkins_home/workspace/Flute/Flute/builds/Flute_RV64GC_MSU_WB_L1_L2_verilator_tohost/Verilog_RTL/mkLLPipeline.v
read_verilog /var/jenkins_home/workspace/Flute/Flute/builds/Flute_RV64GC_MSU_WB_L1_L2_verilator_tohost/Verilog_RTL/mkLastLvCRqMshr.v
read_verilog /var/jenkins_home/workspace/Flute/Flute/builds/Flute_RV64GC_MSU_WB_L1_L2_verilator_tohost/Verilog_RTL/mkMMIO.v
read_verilog /var/jenkins_home/workspace/Flute/Flute/builds/Flute_RV64GC_MSU_WB_L1_L2_verilator_tohost/Verilog_RTL/mkMMIO_AXI4_Adapter_2.v
read_verilog /var/jenkins_home/workspace/Flute/Flute/builds/Flute_RV64GC_MSU_WB_L1_L2_verilator_tohost/Verilog_RTL/mkMem_Controller.v
read_verilog /var/jenkins_home/workspace/Flute/Flute/builds/Flute_RV64GC_MSU_WB_L1_L2_verilator_tohost/Verilog_RTL/mkMem_Model.v
read_verilog /var/jenkins_home/workspace/Flute/Flute/builds/Flute_RV64GC_MSU_WB_L1_L2_verilator_tohost/Verilog_RTL/mkNear_Mem.v
read_verilog /var/jenkins_home/workspace/Flute/Flute/builds/Flute_RV64GC_MSU_WB_L1_L2_verilator_tohost/Verilog_RTL/mkNear_Mem_IO_AXI4.v
read_verilog /var/jenkins_home/workspace/Flute/Flute/builds/Flute_RV64GC_MSU_WB_L1_L2_verilator_tohost/Verilog_RTL/mkPLIC_16_2_7.v
read_verilog /var/jenkins_home/workspace/Flute/Flute/builds/Flute_RV64GC_MSU_WB_L1_L2_verilator_tohost/Verilog_RTL/mkPTW.v
read_verilog /var/jenkins_home/workspace/Flute/Flute/builds/Flute_RV64GC_MSU_WB_L1_L2_verilator_tohost/Verilog_RTL/mkRISCV_MBox.v
read_verilog /var/jenkins_home/workspace/Flute/Flute/builds/Flute_RV64GC_MSU_WB_L1_L2_verilator_tohost/Verilog_RTL/mkSoC_Map.v
read_verilog /var/jenkins_home/workspace/Flute/Flute/builds/Flute_RV64GC_MSU_WB_L1_L2_verilator_tohost/Verilog_RTL/mkSoC_Top.v
read_verilog /var/jenkins_home/workspace/Flute/Flute/builds/Flute_RV64GC_MSU_WB_L1_L2_verilator_tohost/Verilog_RTL/mkTLB.v
read_verilog /var/jenkins_home/workspace/Flute/Flute/builds/Flute_RV64GC_MSU_WB_L1_L2_verilator_tohost/Verilog_RTL/mkTop_HW_Side.v
read_verilog /var/jenkins_home/workspace/Flute/Flute/builds/Flute_RV64GC_MSU_WB_L1_L2_verilator_tohost/Verilog_RTL/mkUART.v
read_verilog /var/jenkins_home/workspace/Flute/Flute/builds/RV32ACDFIMSU_Flute_iverilog/Verilog_RTL/mkAXI4_Deburster_A.v
read_verilog /var/jenkins_home/workspace/Flute/Flute/builds/RV32ACDFIMSU_Flute_iverilog/Verilog_RTL/mkBoot_ROM.v
read_verilog /var/jenkins_home/workspace/Flute/Flute/builds/RV32ACDFIMSU_Flute_iverilog/Verilog_RTL/mkBranch_Predictor.v
read_verilog /var/jenkins_home/workspace/Flute/Flute/builds/RV32ACDFIMSU_Flute_iverilog/Verilog_RTL/mkCPU.v
read_verilog /var/jenkins_home/workspace/Flute/Flute/builds/RV32ACDFIMSU_Flute_iverilog/Verilog_RTL/mkCSR_MIE.v
read_verilog /var/jenkins_home/workspace/Flute/Flute/builds/RV32ACDFIMSU_Flute_iverilog/Verilog_RTL/mkCSR_MIP.v
read_verilog /var/jenkins_home/workspace/Flute/Flute/builds/RV32ACDFIMSU_Flute_iverilog/Verilog_RTL/mkCSR_RegFile.v
read_verilog /var/jenkins_home/workspace/Flute/Flute/builds/RV32ACDFIMSU_Flute_iverilog/Verilog_RTL/mkCore.v
read_verilog /var/jenkins_home/workspace/Flute/Flute/builds/RV32ACDFIMSU_Flute_iverilog/Verilog_RTL/mkFBox_Core.v
read_verilog /var/jenkins_home/workspace/Flute/Flute/builds/RV32ACDFIMSU_Flute_iverilog/Verilog_RTL/mkFBox_Top.v
read_verilog /var/jenkins_home/workspace/Flute/Flute/builds/RV32ACDFIMSU_Flute_iverilog/Verilog_RTL/mkFPR_RegFile.v
read_verilog /var/jenkins_home/workspace/Flute/Flute/builds/RV32ACDFIMSU_Flute_iverilog/Verilog_RTL/mkFPU.v
read_verilog /var/jenkins_home/workspace/Flute/Flute/builds/RV32ACDFIMSU_Flute_iverilog/Verilog_RTL/mkFabric.v
read_verilog /var/jenkins_home/workspace/Flute/Flute/builds/RV32ACDFIMSU_Flute_iverilog/Verilog_RTL/mkFabric_2x3.v
read_verilog /var/jenkins_home/workspace/Flute/Flute/builds/RV32ACDFIMSU_Flute_iverilog/Verilog_RTL/mkFabric_AXI4.v
read_verilog /var/jenkins_home/workspace/Flute/Flute/builds/RV32ACDFIMSU_Flute_iverilog/Verilog_RTL/mkGPR_RegFile.v
read_verilog /var/jenkins_home/workspace/Flute/Flute/builds/RV32ACDFIMSU_Flute_iverilog/Verilog_RTL/mkIntMul_32.v
read_verilog /var/jenkins_home/workspace/Flute/Flute/builds/RV32ACDFIMSU_Flute_iverilog/Verilog_RTL/mkIntMul_64.v
read_verilog /var/jenkins_home/workspace/Flute/Flute/builds/RV32ACDFIMSU_Flute_iverilog/Verilog_RTL/mkMMU_Cache.v
read_verilog /var/jenkins_home/workspace/Flute/Flute/builds/RV32ACDFIMSU_Flute_iverilog/Verilog_RTL/mkMem_Controller.v
read_verilog /var/jenkins_home/workspace/Flute/Flute/builds/RV32ACDFIMSU_Flute_iverilog/Verilog_RTL/mkMem_Model.v
read_verilog /var/jenkins_home/workspace/Flute/Flute/builds/RV32ACDFIMSU_Flute_iverilog/Verilog_RTL/mkNear_Mem.v
read_verilog /var/jenkins_home/workspace/Flute/Flute/builds/RV32ACDFIMSU_Flute_iverilog/Verilog_RTL/mkNear_Mem_IO.v
read_verilog /var/jenkins_home/workspace/Flute/Flute/builds/RV32ACDFIMSU_Flute_iverilog/Verilog_RTL/mkNear_Mem_IO_AXI4.v
read_verilog /var/jenkins_home/workspace/Flute/Flute/builds/RV32ACDFIMSU_Flute_iverilog/Verilog_RTL/mkPLIC_16_2_7.v
read_verilog /var/jenkins_home/workspace/Flute/Flute/builds/RV32ACDFIMSU_Flute_iverilog/Verilog_RTL/mkRISCV_FBox.v
read_verilog /var/jenkins_home/workspace/Flute/Flute/builds/RV32ACDFIMSU_Flute_iverilog/Verilog_RTL/mkRISCV_MBox.v
read_verilog /var/jenkins_home/workspace/Flute/Flute/builds/RV32ACDFIMSU_Flute_iverilog/Verilog_RTL/mkSoC_Map.v
read_verilog /var/jenkins_home/workspace/Flute/Flute/builds/RV32ACDFIMSU_Flute_iverilog/Verilog_RTL/mkSoC_Top.v
read_verilog /var/jenkins_home/workspace/Flute/Flute/builds/RV32ACDFIMSU_Flute_iverilog/Verilog_RTL/mkTLB.v
read_verilog /var/jenkins_home/workspace/Flute/Flute/builds/RV32ACDFIMSU_Flute_iverilog/Verilog_RTL/mkTop_HW_Side.v
read_verilog /var/jenkins_home/workspace/Flute/Flute/builds/RV32ACDFIMSU_Flute_iverilog/Verilog_RTL/mkUART.v
read_verilog /var/jenkins_home/workspace/Flute/Flute/builds/RV32ACDFIMSU_Flute_verilator/Verilog_RTL/mkAXI4_Deburster_A.v
read_verilog /var/jenkins_home/workspace/Flute/Flute/builds/RV32ACDFIMSU_Flute_verilator/Verilog_RTL/mkBoot_ROM.v
read_verilog /var/jenkins_home/workspace/Flute/Flute/builds/RV32ACDFIMSU_Flute_verilator/Verilog_RTL/mkBranch_Predictor.v
read_verilog /var/jenkins_home/workspace/Flute/Flute/builds/RV32ACDFIMSU_Flute_verilator/Verilog_RTL/mkCPU.v
read_verilog /var/jenkins_home/workspace/Flute/Flute/builds/RV32ACDFIMSU_Flute_verilator/Verilog_RTL/mkCSR_MIE.v
read_verilog /var/jenkins_home/workspace/Flute/Flute/builds/RV32ACDFIMSU_Flute_verilator/Verilog_RTL/mkCSR_MIP.v
read_verilog /var/jenkins_home/workspace/Flute/Flute/builds/RV32ACDFIMSU_Flute_verilator/Verilog_RTL/mkCSR_RegFile.v
read_verilog /var/jenkins_home/workspace/Flute/Flute/builds/RV32ACDFIMSU_Flute_verilator/Verilog_RTL/mkCore.v
read_verilog /var/jenkins_home/workspace/Flute/Flute/builds/RV32ACDFIMSU_Flute_verilator/Verilog_RTL/mkFBox_Core.v
read_verilog /var/jenkins_home/workspace/Flute/Flute/builds/RV32ACDFIMSU_Flute_verilator/Verilog_RTL/mkFBox_Top.v
read_verilog /var/jenkins_home/workspace/Flute/Flute/builds/RV32ACDFIMSU_Flute_verilator/Verilog_RTL/mkFPR_RegFile.v
read_verilog /var/jenkins_home/workspace/Flute/Flute/builds/RV32ACDFIMSU_Flute_verilator/Verilog_RTL/mkFPU.v
read_verilog /var/jenkins_home/workspace/Flute/Flute/builds/RV32ACDFIMSU_Flute_verilator/Verilog_RTL/mkFabric.v
read_verilog /var/jenkins_home/workspace/Flute/Flute/builds/RV32ACDFIMSU_Flute_verilator/Verilog_RTL/mkFabric_2x3.v
read_verilog /var/jenkins_home/workspace/Flute/Flute/builds/RV32ACDFIMSU_Flute_verilator/Verilog_RTL/mkFabric_AXI4.v
read_verilog /var/jenkins_home/workspace/Flute/Flute/builds/RV32ACDFIMSU_Flute_verilator/Verilog_RTL/mkGPR_RegFile.v
read_verilog /var/jenkins_home/workspace/Flute/Flute/builds/RV32ACDFIMSU_Flute_verilator/Verilog_RTL/mkIntMul_32.v
read_verilog /var/jenkins_home/workspace/Flute/Flute/builds/RV32ACDFIMSU_Flute_verilator/Verilog_RTL/mkIntMul_64.v
read_verilog /var/jenkins_home/workspace/Flute/Flute/builds/RV32ACDFIMSU_Flute_verilator/Verilog_RTL/mkMMU_Cache.v
read_verilog /var/jenkins_home/workspace/Flute/Flute/builds/RV32ACDFIMSU_Flute_verilator/Verilog_RTL/mkMem_Controller.v
read_verilog /var/jenkins_home/workspace/Flute/Flute/builds/RV32ACDFIMSU_Flute_verilator/Verilog_RTL/mkMem_Model.v
read_verilog /var/jenkins_home/workspace/Flute/Flute/builds/RV32ACDFIMSU_Flute_verilator/Verilog_RTL/mkNear_Mem.v
read_verilog /var/jenkins_home/workspace/Flute/Flute/builds/RV32ACDFIMSU_Flute_verilator/Verilog_RTL/mkNear_Mem_IO.v
read_verilog /var/jenkins_home/workspace/Flute/Flute/builds/RV32ACDFIMSU_Flute_verilator/Verilog_RTL/mkNear_Mem_IO_AXI4.v
read_verilog /var/jenkins_home/workspace/Flute/Flute/builds/RV32ACDFIMSU_Flute_verilator/Verilog_RTL/mkPLIC_16_2_7.v
read_verilog /var/jenkins_home/workspace/Flute/Flute/builds/RV32ACDFIMSU_Flute_verilator/Verilog_RTL/mkRISCV_FBox.v
read_verilog /var/jenkins_home/workspace/Flute/Flute/builds/RV32ACDFIMSU_Flute_verilator/Verilog_RTL/mkRISCV_MBox.v
read_verilog /var/jenkins_home/workspace/Flute/Flute/builds/RV32ACDFIMSU_Flute_verilator/Verilog_RTL/mkSoC_Map.v
read_verilog /var/jenkins_home/workspace/Flute/Flute/builds/RV32ACDFIMSU_Flute_verilator/Verilog_RTL/mkSoC_Top.v
read_verilog /var/jenkins_home/workspace/Flute/Flute/builds/RV32ACDFIMSU_Flute_verilator/Verilog_RTL/mkTLB.v
read_verilog /var/jenkins_home/workspace/Flute/Flute/builds/RV32ACDFIMSU_Flute_verilator/Verilog_RTL/mkTop_HW_Side.v
read_verilog /var/jenkins_home/workspace/Flute/Flute/builds/RV32ACDFIMSU_Flute_verilator/Verilog_RTL/mkUART.v
read_verilog /var/jenkins_home/workspace/Flute/Flute/builds/RV32ACIMU_Flute_iverilog/Verilog_RTL/mkAXI4_Deburster_A.v
read_verilog /var/jenkins_home/workspace/Flute/Flute/builds/RV32ACIMU_Flute_iverilog/Verilog_RTL/mkBoot_ROM.v
read_verilog /var/jenkins_home/workspace/Flute/Flute/builds/RV32ACIMU_Flute_iverilog/Verilog_RTL/mkBranch_Predictor.v
read_verilog /var/jenkins_home/workspace/Flute/Flute/builds/RV32ACIMU_Flute_iverilog/Verilog_RTL/mkCPU.v
read_verilog /var/jenkins_home/workspace/Flute/Flute/builds/RV32ACIMU_Flute_iverilog/Verilog_RTL/mkCSR_MIE.v
read_verilog /var/jenkins_home/workspace/Flute/Flute/builds/RV32ACIMU_Flute_iverilog/Verilog_RTL/mkCSR_MIP.v
read_verilog /var/jenkins_home/workspace/Flute/Flute/builds/RV32ACIMU_Flute_iverilog/Verilog_RTL/mkCSR_RegFile.v
read_verilog /var/jenkins_home/workspace/Flute/Flute/builds/RV32ACIMU_Flute_iverilog/Verilog_RTL/mkCore.v
read_verilog /var/jenkins_home/workspace/Flute/Flute/builds/RV32ACIMU_Flute_iverilog/Verilog_RTL/mkFabric.v
read_verilog /var/jenkins_home/workspace/Flute/Flute/builds/RV32ACIMU_Flute_iverilog/Verilog_RTL/mkFabric_2x3.v
read_verilog /var/jenkins_home/workspace/Flute/Flute/builds/RV32ACIMU_Flute_iverilog/Verilog_RTL/mkFabric_AXI4.v
read_verilog /var/jenkins_home/workspace/Flute/Flute/builds/RV32ACIMU_Flute_iverilog/Verilog_RTL/mkGPR_RegFile.v
read_verilog /var/jenkins_home/workspace/Flute/Flute/builds/RV32ACIMU_Flute_iverilog/Verilog_RTL/mkIntMul_32.v
read_verilog /var/jenkins_home/workspace/Flute/Flute/builds/RV32ACIMU_Flute_iverilog/Verilog_RTL/mkIntMul_64.v
read_verilog /var/jenkins_home/workspace/Flute/Flute/builds/RV32ACIMU_Flute_iverilog/Verilog_RTL/mkMMU_Cache.v
read_verilog /var/jenkins_home/workspace/Flute/Flute/builds/RV32ACIMU_Flute_iverilog/Verilog_RTL/mkMem_Controller.v
read_verilog /var/jenkins_home/workspace/Flute/Flute/builds/RV32ACIMU_Flute_iverilog/Verilog_RTL/mkMem_Model.v
read_verilog /var/jenkins_home/workspace/Flute/Flute/builds/RV32ACIMU_Flute_iverilog/Verilog_RTL/mkNear_Mem.v
read_verilog /var/jenkins_home/workspace/Flute/Flute/builds/RV32ACIMU_Flute_iverilog/Verilog_RTL/mkNear_Mem_IO.v
read_verilog /var/jenkins_home/workspace/Flute/Flute/builds/RV32ACIMU_Flute_iverilog/Verilog_RTL/mkNear_Mem_IO_AXI4.v
read_verilog /var/jenkins_home/workspace/Flute/Flute/builds/RV32ACIMU_Flute_iverilog/Verilog_RTL/mkPLIC_16_2_7.v
read_verilog /var/jenkins_home/workspace/Flute/Flute/builds/RV32ACIMU_Flute_iverilog/Verilog_RTL/mkRISCV_MBox.v
read_verilog /var/jenkins_home/workspace/Flute/Flute/builds/RV32ACIMU_Flute_iverilog/Verilog_RTL/mkSoC_Map.v
read_verilog /var/jenkins_home/workspace/Flute/Flute/builds/RV32ACIMU_Flute_iverilog/Verilog_RTL/mkSoC_Top.v
read_verilog /var/jenkins_home/workspace/Flute/Flute/builds/RV32ACIMU_Flute_iverilog/Verilog_RTL/mkTop_HW_Side.v
read_verilog /var/jenkins_home/workspace/Flute/Flute/builds/RV32ACIMU_Flute_iverilog/Verilog_RTL/mkUART.v
read_verilog /var/jenkins_home/workspace/Flute/Flute/builds/RV32ACIMU_Flute_verilator/Verilog_RTL/mkAXI4_Deburster_A.v
read_verilog /var/jenkins_home/workspace/Flute/Flute/builds/RV32ACIMU_Flute_verilator/Verilog_RTL/mkBoot_ROM.v
read_verilog /var/jenkins_home/workspace/Flute/Flute/builds/RV32ACIMU_Flute_verilator/Verilog_RTL/mkBranch_Predictor.v
read_verilog /var/jenkins_home/workspace/Flute/Flute/builds/RV32ACIMU_Flute_verilator/Verilog_RTL/mkCPU.v
read_verilog /var/jenkins_home/workspace/Flute/Flute/builds/RV32ACIMU_Flute_verilator/Verilog_RTL/mkCSR_MIE.v
read_verilog /var/jenkins_home/workspace/Flute/Flute/builds/RV32ACIMU_Flute_verilator/Verilog_RTL/mkCSR_MIP.v
read_verilog /var/jenkins_home/workspace/Flute/Flute/builds/RV32ACIMU_Flute_verilator/Verilog_RTL/mkCSR_RegFile.v
read_verilog /var/jenkins_home/workspace/Flute/Flute/builds/RV32ACIMU_Flute_verilator/Verilog_RTL/mkCore.v
read_verilog /var/jenkins_home/workspace/Flute/Flute/builds/RV32ACIMU_Flute_verilator/Verilog_RTL/mkFabric.v
read_verilog /var/jenkins_home/workspace/Flute/Flute/builds/RV32ACIMU_Flute_verilator/Verilog_RTL/mkFabric_2x3.v
read_verilog /var/jenkins_home/workspace/Flute/Flute/builds/RV32ACIMU_Flute_verilator/Verilog_RTL/mkFabric_AXI4.v
read_verilog /var/jenkins_home/workspace/Flute/Flute/builds/RV32ACIMU_Flute_verilator/Verilog_RTL/mkGPR_RegFile.v
read_verilog /var/jenkins_home/workspace/Flute/Flute/builds/RV32ACIMU_Flute_verilator/Verilog_RTL/mkIntMul_32.v
read_verilog /var/jenkins_home/workspace/Flute/Flute/builds/RV32ACIMU_Flute_verilator/Verilog_RTL/mkIntMul_64.v
read_verilog /var/jenkins_home/workspace/Flute/Flute/builds/RV32ACIMU_Flute_verilator/Verilog_RTL/mkMMU_Cache.v
read_verilog /var/jenkins_home/workspace/Flute/Flute/builds/RV32ACIMU_Flute_verilator/Verilog_RTL/mkMem_Controller.v
read_verilog /var/jenkins_home/workspace/Flute/Flute/builds/RV32ACIMU_Flute_verilator/Verilog_RTL/mkMem_Model.v
read_verilog /var/jenkins_home/workspace/Flute/Flute/builds/RV32ACIMU_Flute_verilator/Verilog_RTL/mkNear_Mem.v
read_verilog /var/jenkins_home/workspace/Flute/Flute/builds/RV32ACIMU_Flute_verilator/Verilog_RTL/mkNear_Mem_IO.v
read_verilog /var/jenkins_home/workspace/Flute/Flute/builds/RV32ACIMU_Flute_verilator/Verilog_RTL/mkNear_Mem_IO_AXI4.v
read_verilog /var/jenkins_home/workspace/Flute/Flute/builds/RV32ACIMU_Flute_verilator/Verilog_RTL/mkPLIC_16_2_7.v
read_verilog /var/jenkins_home/workspace/Flute/Flute/builds/RV32ACIMU_Flute_verilator/Verilog_RTL/mkRISCV_MBox.v
read_verilog /var/jenkins_home/workspace/Flute/Flute/builds/RV32ACIMU_Flute_verilator/Verilog_RTL/mkSoC_Map.v
read_verilog /var/jenkins_home/workspace/Flute/Flute/builds/RV32ACIMU_Flute_verilator/Verilog_RTL/mkSoC_Top.v
read_verilog /var/jenkins_home/workspace/Flute/Flute/builds/RV32ACIMU_Flute_verilator/Verilog_RTL/mkTop_HW_Side.v
read_verilog /var/jenkins_home/workspace/Flute/Flute/builds/RV32ACIMU_Flute_verilator/Verilog_RTL/mkUART.v
read_verilog /var/jenkins_home/workspace/Flute/Flute/builds/RV64ACDFIMSU_Flute_iverilog/Verilog_RTL/mkAXI4_Deburster_A.v
read_verilog /var/jenkins_home/workspace/Flute/Flute/builds/RV64ACDFIMSU_Flute_iverilog/Verilog_RTL/mkBoot_ROM.v
read_verilog /var/jenkins_home/workspace/Flute/Flute/builds/RV64ACDFIMSU_Flute_iverilog/Verilog_RTL/mkBranch_Predictor.v
read_verilog /var/jenkins_home/workspace/Flute/Flute/builds/RV64ACDFIMSU_Flute_iverilog/Verilog_RTL/mkCPU.v
read_verilog /var/jenkins_home/workspace/Flute/Flute/builds/RV64ACDFIMSU_Flute_iverilog/Verilog_RTL/mkCSR_MIE.v
read_verilog /var/jenkins_home/workspace/Flute/Flute/builds/RV64ACDFIMSU_Flute_iverilog/Verilog_RTL/mkCSR_MIP.v
read_verilog /var/jenkins_home/workspace/Flute/Flute/builds/RV64ACDFIMSU_Flute_iverilog/Verilog_RTL/mkCSR_RegFile.v
read_verilog /var/jenkins_home/workspace/Flute/Flute/builds/RV64ACDFIMSU_Flute_iverilog/Verilog_RTL/mkCore.v
read_verilog /var/jenkins_home/workspace/Flute/Flute/builds/RV64ACDFIMSU_Flute_iverilog/Verilog_RTL/mkFBox_Core.v
read_verilog /var/jenkins_home/workspace/Flute/Flute/builds/RV64ACDFIMSU_Flute_iverilog/Verilog_RTL/mkFBox_Top.v
read_verilog /var/jenkins_home/workspace/Flute/Flute/builds/RV64ACDFIMSU_Flute_iverilog/Verilog_RTL/mkFPR_RegFile.v
read_verilog /var/jenkins_home/workspace/Flute/Flute/builds/RV64ACDFIMSU_Flute_iverilog/Verilog_RTL/mkFPU.v
read_verilog /var/jenkins_home/workspace/Flute/Flute/builds/RV64ACDFIMSU_Flute_iverilog/Verilog_RTL/mkFabric.v
read_verilog /var/jenkins_home/workspace/Flute/Flute/builds/RV64ACDFIMSU_Flute_iverilog/Verilog_RTL/mkFabric_2x3.v
read_verilog /var/jenkins_home/workspace/Flute/Flute/builds/RV64ACDFIMSU_Flute_iverilog/Verilog_RTL/mkFabric_AXI4.v
read_verilog /var/jenkins_home/workspace/Flute/Flute/builds/RV64ACDFIMSU_Flute_iverilog/Verilog_RTL/mkGPR_RegFile.v
read_verilog /var/jenkins_home/workspace/Flute/Flute/builds/RV64ACDFIMSU_Flute_iverilog/Verilog_RTL/mkIntMul_32.v
read_verilog /var/jenkins_home/workspace/Flute/Flute/builds/RV64ACDFIMSU_Flute_iverilog/Verilog_RTL/mkIntMul_64.v
read_verilog /var/jenkins_home/workspace/Flute/Flute/builds/RV64ACDFIMSU_Flute_iverilog/Verilog_RTL/mkMMU_Cache.v
read_verilog /var/jenkins_home/workspace/Flute/Flute/builds/RV64ACDFIMSU_Flute_iverilog/Verilog_RTL/mkMem_Controller.v
read_verilog /var/jenkins_home/workspace/Flute/Flute/builds/RV64ACDFIMSU_Flute_iverilog/Verilog_RTL/mkMem_Model.v
read_verilog /var/jenkins_home/workspace/Flute/Flute/builds/RV64ACDFIMSU_Flute_iverilog/Verilog_RTL/mkNear_Mem.v
read_verilog /var/jenkins_home/workspace/Flute/Flute/builds/RV64ACDFIMSU_Flute_iverilog/Verilog_RTL/mkNear_Mem_IO.v
read_verilog /var/jenkins_home/workspace/Flute/Flute/builds/RV64ACDFIMSU_Flute_iverilog/Verilog_RTL/mkNear_Mem_IO_AXI4.v
read_verilog /var/jenkins_home/workspace/Flute/Flute/builds/RV64ACDFIMSU_Flute_iverilog/Verilog_RTL/mkPLIC_16_2_7.v
read_verilog /var/jenkins_home/workspace/Flute/Flute/builds/RV64ACDFIMSU_Flute_iverilog/Verilog_RTL/mkRISCV_FBox.v
read_verilog /var/jenkins_home/workspace/Flute/Flute/builds/RV64ACDFIMSU_Flute_iverilog/Verilog_RTL/mkRISCV_MBox.v
read_verilog /var/jenkins_home/workspace/Flute/Flute/builds/RV64ACDFIMSU_Flute_iverilog/Verilog_RTL/mkSoC_Map.v
read_verilog /var/jenkins_home/workspace/Flute/Flute/builds/RV64ACDFIMSU_Flute_iverilog/Verilog_RTL/mkSoC_Top.v
read_verilog /var/jenkins_home/workspace/Flute/Flute/builds/RV64ACDFIMSU_Flute_iverilog/Verilog_RTL/mkTLB.v
read_verilog /var/jenkins_home/workspace/Flute/Flute/builds/RV64ACDFIMSU_Flute_iverilog/Verilog_RTL/mkTop_HW_Side.v
read_verilog /var/jenkins_home/workspace/Flute/Flute/builds/RV64ACDFIMSU_Flute_iverilog/Verilog_RTL/mkUART.v
read_verilog /var/jenkins_home/workspace/Flute/Flute/builds/RV64ACDFIMSU_Flute_verilator/Verilog_RTL/mkAXI4_Deburster_A.v
read_verilog /var/jenkins_home/workspace/Flute/Flute/builds/RV64ACDFIMSU_Flute_verilator/Verilog_RTL/mkBoot_ROM.v
read_verilog /var/jenkins_home/workspace/Flute/Flute/builds/RV64ACDFIMSU_Flute_verilator/Verilog_RTL/mkBranch_Predictor.v
read_verilog /var/jenkins_home/workspace/Flute/Flute/builds/RV64ACDFIMSU_Flute_verilator/Verilog_RTL/mkCPU.v
read_verilog /var/jenkins_home/workspace/Flute/Flute/builds/RV64ACDFIMSU_Flute_verilator/Verilog_RTL/mkCSR_MIE.v
read_verilog /var/jenkins_home/workspace/Flute/Flute/builds/RV64ACDFIMSU_Flute_verilator/Verilog_RTL/mkCSR_MIP.v
read_verilog /var/jenkins_home/workspace/Flute/Flute/builds/RV64ACDFIMSU_Flute_verilator/Verilog_RTL/mkCSR_RegFile.v
read_verilog /var/jenkins_home/workspace/Flute/Flute/builds/RV64ACDFIMSU_Flute_verilator/Verilog_RTL/mkCore.v
read_verilog /var/jenkins_home/workspace/Flute/Flute/builds/RV64ACDFIMSU_Flute_verilator/Verilog_RTL/mkFBox_Core.v
read_verilog /var/jenkins_home/workspace/Flute/Flute/builds/RV64ACDFIMSU_Flute_verilator/Verilog_RTL/mkFBox_Top.v
read_verilog /var/jenkins_home/workspace/Flute/Flute/builds/RV64ACDFIMSU_Flute_verilator/Verilog_RTL/mkFPR_RegFile.v
read_verilog /var/jenkins_home/workspace/Flute/Flute/builds/RV64ACDFIMSU_Flute_verilator/Verilog_RTL/mkFPU.v
read_verilog /var/jenkins_home/workspace/Flute/Flute/builds/RV64ACDFIMSU_Flute_verilator/Verilog_RTL/mkFabric.v
read_verilog /var/jenkins_home/workspace/Flute/Flute/builds/RV64ACDFIMSU_Flute_verilator/Verilog_RTL/mkFabric_2x3.v
read_verilog /var/jenkins_home/workspace/Flute/Flute/builds/RV64ACDFIMSU_Flute_verilator/Verilog_RTL/mkFabric_AXI4.v
read_verilog /var/jenkins_home/workspace/Flute/Flute/builds/RV64ACDFIMSU_Flute_verilator/Verilog_RTL/mkGPR_RegFile.v
read_verilog /var/jenkins_home/workspace/Flute/Flute/builds/RV64ACDFIMSU_Flute_verilator/Verilog_RTL/mkIntMul_32.v
read_verilog /var/jenkins_home/workspace/Flute/Flute/builds/RV64ACDFIMSU_Flute_verilator/Verilog_RTL/mkIntMul_64.v
read_verilog /var/jenkins_home/workspace/Flute/Flute/builds/RV64ACDFIMSU_Flute_verilator/Verilog_RTL/mkMMU_Cache.v
read_verilog /var/jenkins_home/workspace/Flute/Flute/builds/RV64ACDFIMSU_Flute_verilator/Verilog_RTL/mkMem_Controller.v
read_verilog /var/jenkins_home/workspace/Flute/Flute/builds/RV64ACDFIMSU_Flute_verilator/Verilog_RTL/mkMem_Model.v
read_verilog /var/jenkins_home/workspace/Flute/Flute/builds/RV64ACDFIMSU_Flute_verilator/Verilog_RTL/mkNear_Mem.v
read_verilog /var/jenkins_home/workspace/Flute/Flute/builds/RV64ACDFIMSU_Flute_verilator/Verilog_RTL/mkNear_Mem_IO_AXI4.v
read_verilog /var/jenkins_home/workspace/Flute/Flute/builds/RV64ACDFIMSU_Flute_verilator/Verilog_RTL/mkPLIC_16_2_7.v
read_verilog /var/jenkins_home/workspace/Flute/Flute/builds/RV64ACDFIMSU_Flute_verilator/Verilog_RTL/mkRISCV_MBox.v
read_verilog /var/jenkins_home/workspace/Flute/Flute/builds/RV64ACDFIMSU_Flute_verilator/Verilog_RTL/mkSoC_Map.v
read_verilog /var/jenkins_home/workspace/Flute/Flute/builds/RV64ACDFIMSU_Flute_verilator/Verilog_RTL/mkSoC_Top.v
read_verilog /var/jenkins_home/workspace/Flute/Flute/builds/RV64ACDFIMSU_Flute_verilator/Verilog_RTL/mkTLB.v
read_verilog /var/jenkins_home/workspace/Flute/Flute/builds/RV64ACDFIMSU_Flute_verilator/Verilog_RTL/mkTop_HW_Side.v
read_verilog /var/jenkins_home/workspace/Flute/Flute/builds/RV64ACDFIMSU_Flute_verilator/Verilog_RTL/mkUART.v
read_verilog /var/jenkins_home/workspace/Flute/Flute/builds/RV64ACIMU_Flute_iverilog/Verilog_RTL/mkBoot_ROM.v
read_verilog /var/jenkins_home/workspace/Flute/Flute/builds/RV64ACIMU_Flute_iverilog/Verilog_RTL/mkBranch_Predictor.v
read_verilog /var/jenkins_home/workspace/Flute/Flute/builds/RV64ACIMU_Flute_iverilog/Verilog_RTL/mkCPU.v
read_verilog /var/jenkins_home/workspace/Flute/Flute/builds/RV64ACIMU_Flute_iverilog/Verilog_RTL/mkCSR_MIE.v
read_verilog /var/jenkins_home/workspace/Flute/Flute/builds/RV64ACIMU_Flute_iverilog/Verilog_RTL/mkCSR_MIP.v
read_verilog /var/jenkins_home/workspace/Flute/Flute/builds/RV64ACIMU_Flute_iverilog/Verilog_RTL/mkCSR_RegFile.v
read_verilog /var/jenkins_home/workspace/Flute/Flute/builds/RV64ACIMU_Flute_iverilog/Verilog_RTL/mkCore.v
read_verilog /var/jenkins_home/workspace/Flute/Flute/builds/RV64ACIMU_Flute_iverilog/Verilog_RTL/mkFabric.v
read_verilog /var/jenkins_home/workspace/Flute/Flute/builds/RV64ACIMU_Flute_iverilog/Verilog_RTL/mkFabric_2x3.v
read_verilog /var/jenkins_home/workspace/Flute/Flute/builds/RV64ACIMU_Flute_iverilog/Verilog_RTL/mkFabric_AXI4.v
read_verilog /var/jenkins_home/workspace/Flute/Flute/builds/RV64ACIMU_Flute_iverilog/Verilog_RTL/mkGPR_RegFile.v
read_verilog /var/jenkins_home/workspace/Flute/Flute/builds/RV64ACIMU_Flute_iverilog/Verilog_RTL/mkIntMul_32.v
read_verilog /var/jenkins_home/workspace/Flute/Flute/builds/RV64ACIMU_Flute_iverilog/Verilog_RTL/mkIntMul_64.v
read_verilog /var/jenkins_home/workspace/Flute/Flute/builds/RV64ACIMU_Flute_iverilog/Verilog_RTL/mkMMU_Cache.v
read_verilog /var/jenkins_home/workspace/Flute/Flute/builds/RV64ACIMU_Flute_iverilog/Verilog_RTL/mkMem_Controller.v
read_verilog /var/jenkins_home/workspace/Flute/Flute/builds/RV64ACIMU_Flute_iverilog/Verilog_RTL/mkMem_Model.v
read_verilog /var/jenkins_home/workspace/Flute/Flute/builds/RV64ACIMU_Flute_iverilog/Verilog_RTL/mkNear_Mem.v
read_verilog /var/jenkins_home/workspace/Flute/Flute/builds/RV64ACIMU_Flute_iverilog/Verilog_RTL/mkNear_Mem_IO.v
read_verilog /var/jenkins_home/workspace/Flute/Flute/builds/RV64ACIMU_Flute_iverilog/Verilog_RTL/mkNear_Mem_IO_AXI4.v
read_verilog /var/jenkins_home/workspace/Flute/Flute/builds/RV64ACIMU_Flute_iverilog/Verilog_RTL/mkPLIC_16_2_7.v
read_verilog /var/jenkins_home/workspace/Flute/Flute/builds/RV64ACIMU_Flute_iverilog/Verilog_RTL/mkRISCV_MBox.v
read_verilog /var/jenkins_home/workspace/Flute/Flute/builds/RV64ACIMU_Flute_iverilog/Verilog_RTL/mkSoC_Map.v
read_verilog /var/jenkins_home/workspace/Flute/Flute/builds/RV64ACIMU_Flute_iverilog/Verilog_RTL/mkSoC_Top.v
read_verilog /var/jenkins_home/workspace/Flute/Flute/builds/RV64ACIMU_Flute_iverilog/Verilog_RTL/mkTop_HW_Side.v
read_verilog /var/jenkins_home/workspace/Flute/Flute/builds/RV64ACIMU_Flute_iverilog/Verilog_RTL/mkUART.v
read_verilog /var/jenkins_home/workspace/Flute/Flute/builds/RV64ACIMU_Flute_verilator/Verilog_RTL/mkAXI4_Deburster_A.v
read_verilog /var/jenkins_home/workspace/Flute/Flute/builds/RV64ACIMU_Flute_verilator/Verilog_RTL/mkBoot_ROM.v
read_verilog /var/jenkins_home/workspace/Flute/Flute/builds/RV64ACIMU_Flute_verilator/Verilog_RTL/mkBranch_Predictor.v
read_verilog /var/jenkins_home/workspace/Flute/Flute/builds/RV64ACIMU_Flute_verilator/Verilog_RTL/mkCPU.v
read_verilog /var/jenkins_home/workspace/Flute/Flute/builds/RV64ACIMU_Flute_verilator/Verilog_RTL/mkCSR_MIE.v
read_verilog /var/jenkins_home/workspace/Flute/Flute/builds/RV64ACIMU_Flute_verilator/Verilog_RTL/mkCSR_MIP.v
read_verilog /var/jenkins_home/workspace/Flute/Flute/builds/RV64ACIMU_Flute_verilator/Verilog_RTL/mkCSR_RegFile.v
read_verilog /var/jenkins_home/workspace/Flute/Flute/builds/RV64ACIMU_Flute_verilator/Verilog_RTL/mkCore.v
read_verilog /var/jenkins_home/workspace/Flute/Flute/builds/RV64ACIMU_Flute_verilator/Verilog_RTL/mkFabric.v
read_verilog /var/jenkins_home/workspace/Flute/Flute/builds/RV64ACIMU_Flute_verilator/Verilog_RTL/mkFabric_2x3.v
read_verilog /var/jenkins_home/workspace/Flute/Flute/builds/RV64ACIMU_Flute_verilator/Verilog_RTL/mkFabric_AXI4.v
read_verilog /var/jenkins_home/workspace/Flute/Flute/builds/RV64ACIMU_Flute_verilator/Verilog_RTL/mkGPR_RegFile.v
read_verilog /var/jenkins_home/workspace/Flute/Flute/builds/RV64ACIMU_Flute_verilator/Verilog_RTL/mkIntMul_32.v
read_verilog /var/jenkins_home/workspace/Flute/Flute/builds/RV64ACIMU_Flute_verilator/Verilog_RTL/mkIntMul_64.v
read_verilog /var/jenkins_home/workspace/Flute/Flute/builds/RV64ACIMU_Flute_verilator/Verilog_RTL/mkMMU_Cache.v
read_verilog /var/jenkins_home/workspace/Flute/Flute/builds/RV64ACIMU_Flute_verilator/Verilog_RTL/mkMem_Controller.v
read_verilog /var/jenkins_home/workspace/Flute/Flute/builds/RV64ACIMU_Flute_verilator/Verilog_RTL/mkMem_Model.v
read_verilog /var/jenkins_home/workspace/Flute/Flute/builds/RV64ACIMU_Flute_verilator/Verilog_RTL/mkNear_Mem.v
read_verilog /var/jenkins_home/workspace/Flute/Flute/builds/RV64ACIMU_Flute_verilator/Verilog_RTL/mkNear_Mem_IO.v
read_verilog /var/jenkins_home/workspace/Flute/Flute/builds/RV64ACIMU_Flute_verilator/Verilog_RTL/mkNear_Mem_IO_AXI4.v
read_verilog /var/jenkins_home/workspace/Flute/Flute/builds/RV64ACIMU_Flute_verilator/Verilog_RTL/mkPLIC_16_2_7.v
read_verilog /var/jenkins_home/workspace/Flute/Flute/builds/RV64ACIMU_Flute_verilator/Verilog_RTL/mkRISCV_MBox.v
read_verilog /var/jenkins_home/workspace/Flute/Flute/builds/RV64ACIMU_Flute_verilator/Verilog_RTL/mkSoC_Map.v
read_verilog /var/jenkins_home/workspace/Flute/Flute/builds/RV64ACIMU_Flute_verilator/Verilog_RTL/mkSoC_Top.v
read_verilog /var/jenkins_home/workspace/Flute/Flute/builds/RV64ACIMU_Flute_verilator/Verilog_RTL/mkTop_HW_Side.v
read_verilog /var/jenkins_home/workspace/Flute/Flute/builds/RV64ACIMU_Flute_verilator/Verilog_RTL/mkUART.v
read_verilog /var/jenkins_home/workspace/Flute/Flute/builds/Resources/Verilator_resources/import_DPI_C_decls.v
read_verilog /var/jenkins_home/workspace/Flute/Flute/src_SSITH_P2/Verilog_RTL/mkAxiLowPower.v
read_verilog /var/jenkins_home/workspace/Flute/Flute/src_SSITH_P2/Verilog_RTL/mkBranch_Predictor.v
read_verilog /var/jenkins_home/workspace/Flute/Flute/src_SSITH_P2/Verilog_RTL/mkCPU.v
read_verilog /var/jenkins_home/workspace/Flute/Flute/src_SSITH_P2/Verilog_RTL/mkCSR_MIE.v
read_verilog /var/jenkins_home/workspace/Flute/Flute/src_SSITH_P2/Verilog_RTL/mkCSR_MIP.v
read_verilog /var/jenkins_home/workspace/Flute/Flute/src_SSITH_P2/Verilog_RTL/mkCSR_RegFile.v
read_verilog /var/jenkins_home/workspace/Flute/Flute/src_SSITH_P2/Verilog_RTL/mkCache.v
read_verilog /var/jenkins_home/workspace/Flute/Flute/src_SSITH_P2/Verilog_RTL/mkCore.v
read_verilog /var/jenkins_home/workspace/Flute/Flute/src_SSITH_P2/Verilog_RTL/mkDM_Abstract_Commands.v
read_verilog /var/jenkins_home/workspace/Flute/Flute/src_SSITH_P2/Verilog_RTL/mkDM_CSR_Tap.v
read_verilog /var/jenkins_home/workspace/Flute/Flute/src_SSITH_P2/Verilog_RTL/mkDM_FPR_Tap.v
read_verilog /var/jenkins_home/workspace/Flute/Flute/src_SSITH_P2/Verilog_RTL/mkDM_GPR_Tap.v
read_verilog /var/jenkins_home/workspace/Flute/Flute/src_SSITH_P2/Verilog_RTL/mkDM_Mem_Tap.v
read_verilog /var/jenkins_home/workspace/Flute/Flute/src_SSITH_P2/Verilog_RTL/mkDM_Run_Control.v
read_verilog /var/jenkins_home/workspace/Flute/Flute/src_SSITH_P2/Verilog_RTL/mkDM_System_Bus.v
read_verilog /var/jenkins_home/workspace/Flute/Flute/src_SSITH_P2/Verilog_RTL/mkD_MMU_Cache.v
read_verilog /var/jenkins_home/workspace/Flute/Flute/src_SSITH_P2/Verilog_RTL/mkDebug_Module.v
read_verilog /var/jenkins_home/workspace/Flute/Flute/src_SSITH_P2/Verilog_RTL/mkDma_Server_Mux.v
read_verilog /var/jenkins_home/workspace/Flute/Flute/src_SSITH_P2/Verilog_RTL/mkDma_Server_Mux_Fabric.v
read_verilog /var/jenkins_home/workspace/Flute/Flute/src_SSITH_P2/Verilog_RTL/mkFBox_Core.v
read_verilog /var/jenkins_home/workspace/Flute/Flute/src_SSITH_P2/Verilog_RTL/mkFBox_Top.v
read_verilog /var/jenkins_home/workspace/Flute/Flute/src_SSITH_P2/Verilog_RTL/mkFPR_RegFile.v
read_verilog /var/jenkins_home/workspace/Flute/Flute/src_SSITH_P2/Verilog_RTL/mkFPU.v
read_verilog /var/jenkins_home/workspace/Flute/Flute/src_SSITH_P2/Verilog_RTL/mkFabric_1x3.v
read_verilog /var/jenkins_home/workspace/Flute/Flute/src_SSITH_P2/Verilog_RTL/mkGPR_RegFile.v
read_verilog /var/jenkins_home/workspace/Flute/Flute/src_SSITH_P2/Verilog_RTL/mkI_MMU_Cache.v
read_verilog /var/jenkins_home/workspace/Flute/Flute/src_SSITH_P2/Verilog_RTL/mkIntMul_32.v
read_verilog /var/jenkins_home/workspace/Flute/Flute/src_SSITH_P2/Verilog_RTL/mkIntMul_64.v
read_verilog /var/jenkins_home/workspace/Flute/Flute/src_SSITH_P2/Verilog_RTL/mkJtagTap.v
read_verilog /var/jenkins_home/workspace/Flute/Flute/src_SSITH_P2/Verilog_RTL/mkLLCache.v
read_verilog /var/jenkins_home/workspace/Flute/Flute/src_SSITH_P2/Verilog_RTL/mkLLPipeline.v
read_verilog /var/jenkins_home/workspace/Flute/Flute/src_SSITH_P2/Verilog_RTL/mkLastLvCRqMshr.v
read_verilog /var/jenkins_home/workspace/Flute/Flute/src_SSITH_P2/Verilog_RTL/mkMMIO.v
read_verilog /var/jenkins_home/workspace/Flute/Flute/src_SSITH_P2/Verilog_RTL/mkMMIO_AXI4_Adapter_2.v
read_verilog /var/jenkins_home/workspace/Flute/Flute/src_SSITH_P2/Verilog_RTL/mkNear_Mem.v
read_verilog /var/jenkins_home/workspace/Flute/Flute/src_SSITH_P2/Verilog_RTL/mkNear_Mem_IO_AXI4.v
read_verilog /var/jenkins_home/workspace/Flute/Flute/src_SSITH_P2/Verilog_RTL/mkP2_Core.v
read_verilog /var/jenkins_home/workspace/Flute/Flute/src_SSITH_P2/Verilog_RTL/mkPLIC_16_2_7.v
read_verilog /var/jenkins_home/workspace/Flute/Flute/src_SSITH_P2/Verilog_RTL/mkPTW.v
read_verilog /var/jenkins_home/workspace/Flute/Flute/src_SSITH_P2/Verilog_RTL/mkRISCV_MBox.v
read_verilog /var/jenkins_home/workspace/Flute/Flute/src_SSITH_P2/Verilog_RTL/mkSoC_Map.v
read_verilog /var/jenkins_home/workspace/Flute/Flute/src_SSITH_P2/Verilog_RTL/mkTLB.v
read_verilog /var/jenkins_home/workspace/Flute/Flute/src_SSITH_P2/Verilog_RTL/mkTLM2Source.v
read_verilog /var/jenkins_home/workspace/Flute/Flute/src_SSITH_P2/Verilog_RTL/mkTV_Encode.v
read_verilog /var/jenkins_home/workspace/Flute/Flute/src_SSITH_P2/Verilog_RTL/mkTV_Xactor.v
read_verilog /var/jenkins_home/workspace/Flute/Flute/src_SSITH_P2/xilinx_ip/hdl/ASSIGN1.v
read_verilog /var/jenkins_home/workspace/Flute/Flute/src_SSITH_P2/xilinx_ip/hdl/BRAM2.v
read_verilog /var/jenkins_home/workspace/Flute/Flute/src_SSITH_P2/xilinx_ip/hdl/ClockGen.v
read_verilog /var/jenkins_home/workspace/Flute/Flute/src_SSITH_P2/xilinx_ip/hdl/FIFO1.v
read_verilog /var/jenkins_home/workspace/Flute/Flute/src_SSITH_P2/xilinx_ip/hdl/FIFO2.v
read_verilog /var/jenkins_home/workspace/Flute/Flute/src_SSITH_P2/xilinx_ip/hdl/FIFO20.v
read_verilog /var/jenkins_home/workspace/Flute/Flute/src_SSITH_P2/xilinx_ip/hdl/FIFOL1.v
read_verilog /var/jenkins_home/workspace/Flute/Flute/src_SSITH_P2/xilinx_ip/hdl/MakeClock.v
read_verilog /var/jenkins_home/workspace/Flute/Flute/src_SSITH_P2/xilinx_ip/hdl/RegFile.v
read_verilog /var/jenkins_home/workspace/Flute/Flute/src_SSITH_P2/xilinx_ip/hdl/SizedFIFO.v
read_verilog /var/jenkins_home/workspace/Flute/Flute/src_SSITH_P2/xilinx_ip/hdl/SizedFIFO0.v
read_verilog /var/jenkins_home/workspace/Flute/Flute/src_SSITH_P2/xilinx_ip/hdl/SyncFIFOLevel.v
read_verilog /var/jenkins_home/workspace/Flute/Flute/src_SSITH_P2/xilinx_ip/hdl/SyncHandshake.v
read_verilog /var/jenkins_home/workspace/Flute/Flute/src_SSITH_P2/xilinx_ip/hdl/SyncResetA.v
read_verilog /var/jenkins_home/workspace/Flute/Flute/src_SSITH_P2/xilinx_ip/hdl/SyncWire.v
read_verilog /var/jenkins_home/workspace/Flute/Flute/src_SSITH_P2/xilinx_ip/hdl/mkAxiLowPower.v
read_verilog /var/jenkins_home/workspace/Flute/Flute/src_SSITH_P2/xilinx_ip/hdl/mkBranch_Predictor.v
read_verilog /var/jenkins_home/workspace/Flute/Flute/src_SSITH_P2/xilinx_ip/hdl/mkCPU.v
read_verilog /var/jenkins_home/workspace/Flute/Flute/src_SSITH_P2/xilinx_ip/hdl/mkCSR_MIE.v
read_verilog /var/jenkins_home/workspace/Flute/Flute/src_SSITH_P2/xilinx_ip/hdl/mkCSR_MIP.v
read_verilog /var/jenkins_home/workspace/Flute/Flute/src_SSITH_P2/xilinx_ip/hdl/mkCSR_RegFile.v
read_verilog /var/jenkins_home/workspace/Flute/Flute/src_SSITH_P2/xilinx_ip/hdl/mkCache.v
read_verilog /var/jenkins_home/workspace/Flute/Flute/src_SSITH_P2/xilinx_ip/hdl/mkCore.v
read_verilog /var/jenkins_home/workspace/Flute/Flute/src_SSITH_P2/xilinx_ip/hdl/mkDM_Abstract_Commands.v
read_verilog /var/jenkins_home/workspace/Flute/Flute/src_SSITH_P2/xilinx_ip/hdl/mkDM_CSR_Tap.v
read_verilog /var/jenkins_home/workspace/Flute/Flute/src_SSITH_P2/xilinx_ip/hdl/mkDM_FPR_Tap.v
read_verilog /var/jenkins_home/workspace/Flute/Flute/src_SSITH_P2/xilinx_ip/hdl/mkDM_GPR_Tap.v
read_verilog /var/jenkins_home/workspace/Flute/Flute/src_SSITH_P2/xilinx_ip/hdl/mkDM_Mem_Tap.v
read_verilog /var/jenkins_home/workspace/Flute/Flute/src_SSITH_P2/xilinx_ip/hdl/mkDM_Run_Control.v
read_verilog /var/jenkins_home/workspace/Flute/Flute/src_SSITH_P2/xilinx_ip/hdl/mkDM_System_Bus.v
read_verilog /var/jenkins_home/workspace/Flute/Flute/src_SSITH_P2/xilinx_ip/hdl/mkD_MMU_Cache.v
read_verilog /var/jenkins_home/workspace/Flute/Flute/src_SSITH_P2/xilinx_ip/hdl/mkDebug_Module.v
read_verilog /var/jenkins_home/workspace/Flute/Flute/src_SSITH_P2/xilinx_ip/hdl/mkDma_Server_Mux.v
read_verilog /var/jenkins_home/workspace/Flute/Flute/src_SSITH_P2/xilinx_ip/hdl/mkDma_Server_Mux_Fabric.v
read_verilog /var/jenkins_home/workspace/Flute/Flute/src_SSITH_P2/xilinx_ip/hdl/mkFBox_Core.v
read_verilog /var/jenkins_home/workspace/Flute/Flute/src_SSITH_P2/xilinx_ip/hdl/mkFBox_Top.v
read_verilog /var/jenkins_home/workspace/Flute/Flute/src_SSITH_P2/xilinx_ip/hdl/mkFPR_RegFile.v
read_verilog /var/jenkins_home/workspace/Flute/Flute/src_SSITH_P2/xilinx_ip/hdl/mkFPU.v
read_verilog /var/jenkins_home/workspace/Flute/Flute/src_SSITH_P2/xilinx_ip/hdl/mkFabric_1x3.v
read_verilog /var/jenkins_home/workspace/Flute/Flute/src_SSITH_P2/xilinx_ip/hdl/mkFabric_2x3.v
read_verilog /var/jenkins_home/workspace/Flute/Flute/src_SSITH_P2/xilinx_ip/hdl/mkGPR_RegFile.v
read_verilog /var/jenkins_home/workspace/Flute/Flute/src_SSITH_P2/xilinx_ip/hdl/mkI_MMU_Cache.v
read_verilog /var/jenkins_home/workspace/Flute/Flute/src_SSITH_P2/xilinx_ip/hdl/mkIntMul_32.v
read_verilog /var/jenkins_home/workspace/Flute/Flute/src_SSITH_P2/xilinx_ip/hdl/mkIntMul_64.v
read_verilog /var/jenkins_home/workspace/Flute/Flute/src_SSITH_P2/xilinx_ip/hdl/mkJtagTap.v
read_verilog /var/jenkins_home/workspace/Flute/Flute/src_SSITH_P2/xilinx_ip/hdl/mkLLCache.v
read_verilog /var/jenkins_home/workspace/Flute/Flute/src_SSITH_P2/xilinx_ip/hdl/mkLLPipeline.v
read_verilog /var/jenkins_home/workspace/Flute/Flute/src_SSITH_P2/xilinx_ip/hdl/mkLastLvCRqMshr.v
read_verilog /var/jenkins_home/workspace/Flute/Flute/src_SSITH_P2/xilinx_ip/hdl/mkMMIO.v
read_verilog /var/jenkins_home/workspace/Flute/Flute/src_SSITH_P2/xilinx_ip/hdl/mkMMIO_AXI4_Adapter_2.v
read_verilog /var/jenkins_home/workspace/Flute/Flute/src_SSITH_P2/xilinx_ip/hdl/mkMMU_Cache.v
read_verilog /var/jenkins_home/workspace/Flute/Flute/src_SSITH_P2/xilinx_ip/hdl/mkNear_Mem.v
read_verilog /var/jenkins_home/workspace/Flute/Flute/src_SSITH_P2/xilinx_ip/hdl/mkNear_Mem_IO_AXI4.v
read_verilog /var/jenkins_home/workspace/Flute/Flute/src_SSITH_P2/xilinx_ip/hdl/mkP2_Core.v
read_verilog /var/jenkins_home/workspace/Flute/Flute/src_SSITH_P2/xilinx_ip/hdl/mkPLIC_16_2_7.v
read_verilog /var/jenkins_home/workspace/Flute/Flute/src_SSITH_P2/xilinx_ip/hdl/mkPTW.v
read_verilog /var/jenkins_home/workspace/Flute/Flute/src_SSITH_P2/xilinx_ip/hdl/mkRISCV_MBox.v
read_verilog /var/jenkins_home/workspace/Flute/Flute/src_SSITH_P2/xilinx_ip/hdl/mkSoC_Map.v
read_verilog /var/jenkins_home/workspace/Flute/Flute/src_SSITH_P2/xilinx_ip/hdl/mkTLB.v
read_verilog /var/jenkins_home/workspace/Flute/Flute/src_SSITH_P2/xilinx_ip/hdl/mkTLM2Source.v
read_verilog /var/jenkins_home/workspace/Flute/Flute/src_SSITH_P2/xilinx_ip/hdl/mkTV_Encode.v
read_verilog /var/jenkins_home/workspace/Flute/Flute/src_SSITH_P2/xilinx_ip/hdl/mkTV_Xactor.v
read_verilog /var/jenkins_home/workspace/Flute/Flute/src_bsc_lib_RTL/BRAM1BE.v
read_verilog /var/jenkins_home/workspace/Flute/Flute/src_bsc_lib_RTL/BRAM1BELoad.v
read_verilog /var/jenkins_home/workspace/Flute/Flute/src_bsc_lib_RTL/BRAM2.v
read_verilog /var/jenkins_home/workspace/Flute/Flute/src_bsc_lib_RTL/BRAM2BE.v
read_verilog /var/jenkins_home/workspace/Flute/Flute/src_bsc_lib_RTL/BRAM2BELoad.v
read_verilog /var/jenkins_home/workspace/Flute/Flute/src_bsc_lib_RTL/FIFO1.v
read_verilog /var/jenkins_home/workspace/Flute/Flute/src_bsc_lib_RTL/FIFO10.v
read_verilog /var/jenkins_home/workspace/Flute/Flute/src_bsc_lib_RTL/FIFO2.v
read_verilog /var/jenkins_home/workspace/Flute/Flute/src_bsc_lib_RTL/FIFO20.v
read_verilog /var/jenkins_home/workspace/Flute/Flute/src_bsc_lib_RTL/FIFOL1.v
read_verilog /var/jenkins_home/workspace/Flute/Flute/src_bsc_lib_RTL/MakeResetA.v
read_verilog /var/jenkins_home/workspace/Flute/Flute/src_bsc_lib_RTL/RegFile.v
read_verilog /var/jenkins_home/workspace/Flute/Flute/src_bsc_lib_RTL/RegFileLoad.v
read_verilog /var/jenkins_home/workspace/Flute/Flute/src_bsc_lib_RTL/ResetInverter.v
read_verilog /var/jenkins_home/workspace/Flute/Flute/src_bsc_lib_RTL/RevertReg.v
read_verilog /var/jenkins_home/workspace/Flute/Flute/src_bsc_lib_RTL/SizedFIFO.v
read_verilog /var/jenkins_home/workspace/Flute/Flute/src_bsc_lib_RTL/SizedFIFO0.v
read_verilog /var/jenkins_home/workspace/Flute/Flute/src_bsc_lib_RTL/SyncFIFO.v
read_verilog /var/jenkins_home/workspace/Flute/Flute/src_bsc_lib_RTL/SyncFIFO0.v
read_verilog /var/jenkins_home/workspace/Flute/Flute/src_bsc_lib_RTL/SyncResetA.v
read_verilog /var/jenkins_home/workspace/Flute/Flute/src_bsc_lib_RTL/main.v
read_verilog -sv /eda/processor-ci-controller/modules/uart.sv
read_verilog /eda/processor-ci-controller/modules/UART/rtl/uart_rx.v
read_verilog /eda/processor-ci-controller/modules/UART/rtl/uart_tx.v

#read_verilog -sv /eda/processor-ci-controller/modules/spi.sv;
#read_verilog -sv /eda/processor-ci-controller/modules/SPI-Slave/rtl/spi_slave.sv;

read_verilog -sv /eda/processor_ci/internal/ahblite_to_wishbone.sv
read_verilog -sv /eda/processor_ci/internal/axi4_to_wishbone.sv
read_verilog -sv /eda/processor_ci/internal/axi4lite_to_wishbone.sv
read_verilog -sv /eda/processor-ci-controller/rtl/fifo.sv
read_verilog -sv /eda/processor-ci-controller/rtl/reset.sv
read_verilog -sv /eda/processor-ci-controller/rtl/clk_divider.sv
read_verilog -sv /eda/processor-ci-controller/rtl/memory.sv
read_verilog -sv /eda/processor-ci-controller/rtl/interpreter.sv
read_verilog -sv /eda/processor-ci-controller/rtl/controller.sv
read_verilog -sv /eda/processor-ci-controller/rtl/timer.sv
read_verilog -sv /eda/processor_ci/internal/fpga_top.sv

set_param general.maxThreads 16

read_xdc "/eda/processor_ci/constraints/digilent_arty_a7_100t.xdc"
set_property PROCESSING_ORDER EARLY [get_files /eda/processor_ci/constraints/digilent_arty_a7_100t.xdc]

# synth
synth_design -top "fpga_top" -part "xc7a100tcsg324-1"

# place and route
opt_design
place_design

report_utilization -hierarchical -file digilent_arty_a7_utilization_hierarchical_place.rpt
report_utilization               -file digilent_arty_a7_utilization_place.rpt
report_io                        -file digilent_arty_a7_io.rpt
report_control_sets -verbose     -file digilent_arty_a7_control_sets.rpt
report_clock_utilization         -file digilent_arty_a7_clock_utilization.rpt


route_design

report_timing_summary -no_header -no_detailed_paths
report_route_status                            -file digilent_arty_a7_route_status.rpt
report_drc                                     -file digilent_arty_a7_drc.rpt
report_timing_summary -datasheet -max_paths 10 -file digilent_arty_a7_timing.rpt
report_power                                   -file digilent_arty_a7_power.rpt


# write bitstream
write_bitstream -force "digilent_arty_a7_100t.bit"

exit