Copyright (c) 2022-2023 Bluespec, Inc.  All Rights Reserved.

This directory is for creating Verilog RTL files for the
"Catamaran_Core" sub-system for a Catamaran system.

The top-level generated module here is 'mkAWSteria_Core' (in file
mkAWSteria_Core.v).  This module is instantiated inside module
mkAWSteria_System in the Catamaran system.

[ NOTE: 'Catamaran' is the new name for 'AWSteria'; we are migrating
        module names gradually to minimize disruption. ]

// ================================================================
***** IMPORTANT! IMPORTANT! IMPORTANT! *****

FOR CORRECT USE OF THIS GENERATED VERILOG, PLEASE PEFORM THE FOLLOWING
CONSISTENCY CHECKS WITH THE Catamaran ENVIRONMENT INTO WHICH
mkAWSteria_Core WILL BE INSTANTIATED!

* The interface for module mkAWSteria_Core must be consistent with
    the interface expected by mkAWSteria_System.

    For the BSV interface see source files:
        Flute/src_Core/AWSteria_Core/AWSteria_Core_IFC.bsv
        Flute/src_Core/Debug_Module/DM_Common.bsv
        Flute/src_Core/ISA/PC_Trace.bsv
        Flute/src_Core/ISA/TV_Info.bsv

    For the Verilog interface, see the generated Verilog file:
        ./Verilog_RTL/mkAWSteria_Core.v.
    (this is generated by bsc from the BSV interface).

* The address map assumed by this core must be consistent with the
    address map of the overall Catamaran hardware, and with the
    address map of Linux/software running on Flute.

    The file Flute/src_Core/AWSteria_Core/SoC_Map.bsv specifies the
    (partial) address-map built into mkAWSteria_Core.

// ----------------

The Verilog generated here depends on other Verilog modules in the
    'bsc' (Bluespec BSV compiler) library.  The Makefile copies these
    here after bsc-compiling the Flute BSV code, from the bsc repo:
        https://github.com/B-Lang-org/bsc
    in the directory:
        bsc/src/Verilog/

// ================================================================
