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Started by timer [Pipeline] Start of Pipeline [Pipeline] node Running on Jenkins in /var/jenkins_home/workspace/Grande-Risco-5 [Pipeline] { [Pipeline] stage [Pipeline] { (Git Clone) [Pipeline] sh + rm -rf Grande-Risco-5 [Pipeline] sh + git clone --recursive --depth=1 https://github.com/JN513/Grande-Risco-5 Grande-Risco-5 Cloning into 'Grande-Risco-5'... [Pipeline] } [Pipeline] // stage [Pipeline] stage [Pipeline] { (Simulation) [Pipeline] dir Running in /var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5 [Pipeline] { [Pipeline] sh + /eda/oss-cad-suite/bin/iverilog -o simulation.out -g2005 -s Grande_Risco5 src/core/alu.v src/core/alu_control.v src/core/core.v src/core/forwarding_unit.v src/core/immediate_generator.v src/core/mux.v src/core/registers.v [Pipeline] } [Pipeline] // dir [Pipeline] } [Pipeline] // stage [Pipeline] stage [Pipeline] { (FPGA Build Pipeline) [Pipeline] parallel [Pipeline] { (Branch: colorlight_i9) [Pipeline] { (Branch: digilent_nexys4_ddr) [Pipeline] stage [Pipeline] { (colorlight_i9) [Pipeline] stage [Pipeline] { (digilent_nexys4_ddr) [Pipeline] lock Trying to acquire lock on [Resource: colorlight_i9] Resource [colorlight_i9] did not exist. Created. Lock acquired on [Resource: colorlight_i9] [Pipeline] { [Pipeline] lock Trying to acquire lock on [Resource: digilent_nexys4_ddr] The resource [digilent_nexys4_ddr] is locked by build Risco-5 #459 #459 since Dec 14, 2024, 1:11 AM. [Resource: digilent_nexys4_ddr] is not free, waiting for execution ... [Required resources: [digilent_nexys4_ddr]] added into queue at position 0 [Pipeline] stage [Pipeline] { (Synthesis and PnR) [Pipeline] dir Running in /var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5 [Pipeline] { [Pipeline] echo Starting synthesis for FPGA colorlight_i9. [Pipeline] sh + python3 /eda/processor-ci/main.py -c /eda/processor-ci/config.json -p Grande-Risco-5 -b colorlight_i9 Lock acquired on [Resource: digilent_nexys4_ddr] [Pipeline] { [Pipeline] stage [Pipeline] { (Synthesis and PnR) [Pipeline] dir Running in /var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5 [Pipeline] { [Pipeline] echo Starting synthesis for FPGA digilent_nexys4_ddr. [Pipeline] sh + python3 /eda/processor-ci/main.py -c /eda/processor-ci/config.json -p Grande-Risco-5 -b digilent_nexys4_ddr Final configuration file generated at /var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/build_colorlight_i9.tcl Makefile executed successfully. Makefile output: /eda/oss-cad-suite/bin/yosys -c /var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/build_colorlight_i9.tcl -DID=0x6a6a6a6a -DCLOCK_FREQ=25000000 -DMEMORY_SIZE=4096 /----------------------------------------------------------------------------\ | yosys -- Yosys Open SYnthesis Suite | | Copyright (C) 2012 - 2024 Claire Xenia Wolf <claire@yosyshq.com> | | Distributed under an ISC-like license, type "license" to see terms | \----------------------------------------------------------------------------/ Yosys 0.45+139 (git sha1 4d581a97d, clang++ 14.0.0-1ubuntu1.1 -fPIC -O3) -- Running command `read -define ID=0x6a6a6a6a CLOCK_FREQ=25000000 MEMORY_SIZE=4096' -- 1. Executing Verilog-2005 frontend: /eda/processor-ci/rtl/Grande-Risco-5.v Parsing Verilog input from `/eda/processor-ci/rtl/Grande-Risco-5.v' to AST representation. Generating RTLIL representation for module `\processorci_top'. Successfully finished Verilog frontend. 2. Executing Verilog-2005 frontend: /var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/src/core/alu.v Parsing Verilog input from `/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/src/core/alu.v' to AST representation. Generating RTLIL representation for module `\Alu'. Successfully finished Verilog frontend. 3. Executing Verilog-2005 frontend: /var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/src/core/alu_control.v Parsing Verilog input from `/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/src/core/alu_control.v' to AST representation. Generating RTLIL representation for module `\ALU_Control'. Successfully finished Verilog frontend. 4. Executing Verilog-2005 frontend: /var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/src/core/core.v Parsing Verilog input from `/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/src/core/core.v' to AST representation. Generating RTLIL representation for module `\Grande_Risco5'. Successfully finished Verilog frontend. 5. Executing Verilog-2005 frontend: /var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/src/core/forwarding_unit.v Parsing Verilog input from `/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/src/core/forwarding_unit.v' to AST representation. Generating RTLIL representation for module `\Forwarding_Unit'. Successfully finished Verilog frontend. 6. Executing Verilog-2005 frontend: /var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/src/core/immediate_generator.v Parsing Verilog input from `/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/src/core/immediate_generator.v' to AST representation. Generating RTLIL representation for module `\Immediate_Generator'. Successfully finished Verilog frontend. 7. Executing Verilog-2005 frontend: /var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/src/core/mux.v Parsing Verilog input from `/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/src/core/mux.v' to AST representation. Generating RTLIL representation for module `\MUX'. Successfully finished Verilog frontend. 8. Executing Verilog-2005 frontend: /var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/src/core/registers.v Parsing Verilog input from `/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/src/core/registers.v' to AST representation. Generating RTLIL representation for module `\Registers'. Successfully finished Verilog frontend. 9. Executing Verilog-2005 frontend: /eda/processor-ci-controller/modules/uart.v Parsing Verilog input from `/eda/processor-ci-controller/modules/uart.v' to AST representation. Generating RTLIL representation for module `\UART'. Successfully finished Verilog frontend. 10. Executing Verilog-2005 frontend: /eda/processor-ci-controller/modules/UART/rtl/uart_rx.v Parsing Verilog input from `/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v' to AST representation. Generating RTLIL representation for module `\uart_rx'. Successfully finished Verilog frontend. 11. Executing Verilog-2005 frontend: /eda/processor-ci-controller/modules/UART/rtl/uart_tx.v Parsing Verilog input from `/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v' to AST representation. Generating RTLIL representation for module `\uart_tx'. Successfully finished Verilog frontend. 12. Executing Verilog-2005 frontend: /eda/processor-ci-controller/src/fifo.v Parsing Verilog input from `/eda/processor-ci-controller/src/fifo.v' to AST representation. Generating RTLIL representation for module `\FIFO'. Successfully finished Verilog frontend. 13. Executing Verilog-2005 frontend: /eda/processor-ci-controller/src/reset.v Parsing Verilog input from `/eda/processor-ci-controller/src/reset.v' to AST representation. Generating RTLIL representation for module `\ResetBootSystem'. Successfully finished Verilog frontend. 14. Executing Verilog-2005 frontend: /eda/processor-ci-controller/src/clk_divider.v Parsing Verilog input from `/eda/processor-ci-controller/src/clk_divider.v' to AST representation. Generating RTLIL representation for module `\ClkDivider'. Successfully finished Verilog frontend. 15. Executing Verilog-2005 frontend: /eda/processor-ci-controller/src/memory.v Parsing Verilog input from `/eda/processor-ci-controller/src/memory.v' to AST representation. Generating RTLIL representation for module `\Memory'. Successfully finished Verilog frontend. 16. Executing Verilog-2005 frontend: /eda/processor-ci-controller/src/interpreter.v Parsing Verilog input from `/eda/processor-ci-controller/src/interpreter.v' to AST representation. Generating RTLIL representation for module `\Interpreter'. Successfully finished Verilog frontend. 17. Executing Verilog-2005 frontend: /eda/processor-ci-controller/src/controller.v Parsing Verilog input from `/eda/processor-ci-controller/src/controller.v' to AST representation. Generating RTLIL representation for module `\Controller'. Successfully finished Verilog frontend. 18. Executing SYNTH_ECP5 pass. 18.1. Executing Verilog-2005 frontend: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v Parsing Verilog input from `/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v' to AST representation. Generating RTLIL representation for module `\LUT4'. Generating RTLIL representation for module `\$__ABC9_LUT5'. Generating RTLIL representation for module `\$__ABC9_LUT6'. Generating RTLIL representation for module `\$__ABC9_LUT7'. Generating RTLIL representation for module `\L6MUX21'. Generating RTLIL representation for module `\CCU2C'. Generating RTLIL representation for module `\TRELLIS_RAM16X2'. Generating RTLIL representation for module `\PFUMX'. Generating RTLIL representation for module `\TRELLIS_DPR16X4'. Generating RTLIL representation for module `\DPR16X4C'. Generating RTLIL representation for module `\LUT2'. Generating RTLIL representation for module `\TRELLIS_FF'. Generating RTLIL representation for module `\TRELLIS_IO'. Generating RTLIL representation for module `\INV'. Generating RTLIL representation for module `\TRELLIS_COMB'. Generating RTLIL representation for module `\DP16KD'. Generating RTLIL representation for module `\FD1P3AX'. Generating RTLIL representation for module `\FD1P3AY'. Generating RTLIL representation for module `\FD1P3BX'. Generating RTLIL representation for module `\FD1P3DX'. Generating RTLIL representation for module `\FD1P3IX'. Generating RTLIL representation for module `\FD1P3JX'. Generating RTLIL representation for module `\FD1S3AX'. Generating RTLIL representation for module `\FD1S3AY'. Generating RTLIL representation for module `\FD1S3BX'. Generating RTLIL representation for module `\FD1S3DX'. Generating RTLIL representation for module `\FD1S3IX'. Generating RTLIL representation for module `\FD1S3JX'. Generating RTLIL representation for module `\IFS1P3BX'. Generating RTLIL representation for module `\IFS1P3DX'. Generating RTLIL representation for module `\IFS1P3IX'. Generating RTLIL representation for module `\IFS1P3JX'. Generating RTLIL representation for module `\OFS1P3BX'. Generating RTLIL representation for module `\OFS1P3DX'. Generating RTLIL representation for module `\OFS1P3IX'. Generating RTLIL representation for module `\OFS1P3JX'. Generating RTLIL representation for module `\IB'. Generating RTLIL representation for module `\IBPU'. Generating RTLIL representation for module `\IBPD'. Generating RTLIL representation for module `\OB'. Generating RTLIL representation for module `\OBZ'. Generating RTLIL representation for module `\OBZPU'. Generating RTLIL representation for module `\OBZPD'. Generating RTLIL representation for module `\OBCO'. Generating RTLIL representation for module `\BB'. Generating RTLIL representation for module `\BBPU'. Generating RTLIL representation for module `\BBPD'. Generating RTLIL representation for module `\ILVDS'. Generating RTLIL representation for module `\OLVDS'. Successfully finished Verilog frontend. 18.2. Executing Verilog-2005 frontend: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_bb.v Parsing Verilog input from `/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_bb.v' to AST representation. Generating RTLIL representation for module `\MULT18X18D'. Generating RTLIL representation for module `\ALU54B'. Generating RTLIL representation for module `\EHXPLLL'. Generating RTLIL representation for module `\DTR'. Generating RTLIL representation for module `\OSCG'. Generating RTLIL representation for module `\USRMCLK'. Generating RTLIL representation for module `\JTAGG'. Generating RTLIL representation for module `\DELAYF'. Generating RTLIL representation for module `\DELAYG'. Generating RTLIL representation for module `\IDDRX1F'. Generating RTLIL representation for module `\IDDRX2F'. Generating RTLIL representation for module `\IDDR71B'. Generating RTLIL representation for module `\IDDRX2DQA'. Generating RTLIL representation for module `\ODDRX1F'. Generating RTLIL representation for module `\ODDRX2F'. Generating RTLIL representation for module `\ODDR71B'. Generating RTLIL representation for module `\OSHX2A'. Generating RTLIL representation for module `\ODDRX2DQA'. Generating RTLIL representation for module `\ODDRX2DQSB'. Generating RTLIL representation for module `\TSHX2DQA'. Generating RTLIL representation for module `\TSHX2DQSA'. Generating RTLIL representation for module `\DQSBUFM'. Generating RTLIL representation for module `\DDRDLLA'. Generating RTLIL representation for module `\DLLDELD'. Generating RTLIL representation for module `\CLKDIVF'. Generating RTLIL representation for module `\ECLKSYNCB'. Generating RTLIL representation for module `\ECLKBRIDGECS'. Generating RTLIL representation for module `\DCCA'. Generating RTLIL representation for module `\DCSC'. Generating RTLIL representation for module `\DCUA'. Generating RTLIL representation for module `\EXTREFB'. Generating RTLIL representation for module `\PCSCLKDIV'. Generating RTLIL representation for module `\PUR'. Generating RTLIL representation for module `\GSR'. Generating RTLIL representation for module `\SGSR'. Generating RTLIL representation for module `\PDPW16KD'. Successfully finished Verilog frontend. 18.3. Executing HIERARCHY pass (managing design hierarchy). 18.3.1. Analyzing design hierarchy.. Top module: \processorci_top Used module: \ResetBootSystem Used module: \Grande_Risco5 Used module: \MUX Used module: \Forwarding_Unit Used module: \Immediate_Generator Used module: \Alu Used module: \ALU_Control Used module: \Registers Used module: \Controller Used module: \Memory Used module: \UART Used module: \uart_tx Used module: \uart_rx Used module: \FIFO Used module: \Interpreter Used module: \ClkDivider Parameter \CYCLES = 20 18.3.2. Executing AST frontend in derive mode using pre-parsed AST for module `\ResetBootSystem'. Parameter \CYCLES = 20 Generating RTLIL representation for module `$paramod\ResetBootSystem\CYCLES=s32'00000000000000000000000000010100'. Parameter \CLK_FREQ = 25000000 Parameter \BIT_RATE = 115200 Parameter \PAYLOAD_BITS = 8 Parameter \BUFFER_SIZE = 8 Parameter \PULSE_CONTROL_BITS = 32 Parameter \BUS_WIDTH = 32 Parameter \WORD_SIZE_BY = 4 Parameter \ID = 0 Parameter \RESET_CLK_CYCLES = 20 Parameter \MEMORY_FILE = { } Parameter \MEMORY_SIZE = 4096 18.3.3. Executing AST frontend in derive mode using pre-parsed AST for module `\Controller'. Parameter \CLK_FREQ = 25000000 Parameter \BIT_RATE = 115200 Parameter \PAYLOAD_BITS = 8 Parameter \BUFFER_SIZE = 8 Parameter \PULSE_CONTROL_BITS = 32 Parameter \BUS_WIDTH = 32 Parameter \WORD_SIZE_BY = 4 Parameter \ID = 0 Parameter \RESET_CLK_CYCLES = 20 Parameter \MEMORY_FILE = { } Parameter \MEMORY_SIZE = 4096 Generating RTLIL representation for module `$paramod$be568a6683087bc1c783fd234d0a3f16819ced17\Controller'. Parameter \MEMORY_FILE = { } Parameter \MEMORY_SIZE = 4096 18.3.4. Executing AST frontend in derive mode using pre-parsed AST for module `\Memory'. Parameter \MEMORY_FILE = { } Parameter \MEMORY_SIZE = 4096 Generating RTLIL representation for module `$paramod$860abc9b363840d7b46a2d1e00ea80d20a30d2ee\Memory'. Parameter \MEMORY_FILE = { } Parameter \MEMORY_SIZE = 4096 Found cached RTLIL representation for module `$paramod$860abc9b363840d7b46a2d1e00ea80d20a30d2ee\Memory'. Parameter \CLK_FREQ = 25000000 Parameter \BIT_RATE = 9600 Parameter \PAYLOAD_BITS = 8 Parameter \BUFFER_SIZE = 8 Parameter \WORD_SIZE_BY = 4 18.3.5. Executing AST frontend in derive mode using pre-parsed AST for module `\UART'. Parameter \CLK_FREQ = 25000000 Parameter \BIT_RATE = 9600 Parameter \PAYLOAD_BITS = 8 Parameter \BUFFER_SIZE = 8 Parameter \WORD_SIZE_BY = 4 Generating RTLIL representation for module `$paramod$0ebcb351531b968e3a65ee57624639e797f21099\UART'. Parameter \CLK_FREQ = 25000000 Parameter \PULSE_CONTROL_BITS = 12 Parameter \BUS_WIDTH = 32 Parameter \ID = 1 Parameter \RESET_CLK_CYCLES = 20 18.3.6. Executing AST frontend in derive mode using pre-parsed AST for module `\Interpreter'. Parameter \CLK_FREQ = 25000000 Parameter \PULSE_CONTROL_BITS = 12 Parameter \BUS_WIDTH = 32 Parameter \ID = 1 Parameter \RESET_CLK_CYCLES = 20 Generating RTLIL representation for module `$paramod$6cc68bce6e5ef8358e4f854f8e1607a73728e8ac\Interpreter'. Parameter \COUNTER_BITS = 32 Parameter \PULSE_CONTROL_BITS = 12 18.3.7. Executing AST frontend in derive mode using pre-parsed AST for module `\ClkDivider'. Parameter \COUNTER_BITS = 32 Parameter \PULSE_CONTROL_BITS = 12 Generating RTLIL representation for module `$paramod$d236a3555e5fe48231d3a0bdd0f1031eebbe67d5\ClkDivider'. Parameter \BIT_RATE = 9600 Parameter \CLK_HZ = 25000000 Parameter \PAYLOAD_BITS = 8 18.3.8. Executing AST frontend in derive mode using pre-parsed AST for module `\uart_tx'. Parameter \BIT_RATE = 9600 Parameter \CLK_HZ = 25000000 Parameter \PAYLOAD_BITS = 8 Generating RTLIL representation for module `$paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tx'. Parameter \BIT_RATE = 9600 Parameter \CLK_HZ = 25000000 Parameter \PAYLOAD_BITS = 8 18.3.9. Executing AST frontend in derive mode using pre-parsed AST for module `\uart_rx'. Parameter \BIT_RATE = 9600 Parameter \CLK_HZ = 25000000 Parameter \PAYLOAD_BITS = 8 Generating RTLIL representation for module `$paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_rx'. Parameter \DEPTH = 8 Parameter \WIDTH = 8 18.3.10. Executing AST frontend in derive mode using pre-parsed AST for module `\FIFO'. Parameter \DEPTH = 8 Parameter \WIDTH = 8 Generating RTLIL representation for module `$paramod$fb00a4f1e01b6404091dd91fbb53b046994f1d61\FIFO'. Parameter \DEPTH = 8 Parameter \WIDTH = 8 Found cached RTLIL representation for module `$paramod$fb00a4f1e01b6404091dd91fbb53b046994f1d61\FIFO'. 18.3.11. Analyzing design hierarchy.. Top module: \processorci_top Used module: $paramod\ResetBootSystem\CYCLES=s32'00000000000000000000000000010100 Used module: \Grande_Risco5 Used module: \MUX Used module: \Forwarding_Unit Used module: \Immediate_Generator Used module: \Alu Used module: \ALU_Control Used module: \Registers Used module: $paramod$be568a6683087bc1c783fd234d0a3f16819ced17\Controller Used module: \Memory Used module: \UART Used module: $paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tx Used module: $paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_rx Used module: $paramod$fb00a4f1e01b6404091dd91fbb53b046994f1d61\FIFO Used module: \Interpreter Used module: \ClkDivider Parameter \MEMORY_FILE = { } Parameter \MEMORY_SIZE = 4096 Found cached RTLIL representation for module `$paramod$860abc9b363840d7b46a2d1e00ea80d20a30d2ee\Memory'. Parameter \MEMORY_FILE = { } Parameter \MEMORY_SIZE = 4096 Found cached RTLIL representation for module `$paramod$860abc9b363840d7b46a2d1e00ea80d20a30d2ee\Memory'. Parameter \CLK_FREQ = 25000000 Parameter \BIT_RATE = 115200 Parameter \PAYLOAD_BITS = 8 Parameter \BUFFER_SIZE = 8 Parameter \WORD_SIZE_BY = 4 18.3.12. Executing AST frontend in derive mode using pre-parsed AST for module `\UART'. Parameter \CLK_FREQ = 25000000 Parameter \BIT_RATE = 115200 Parameter \PAYLOAD_BITS = 8 Parameter \BUFFER_SIZE = 8 Parameter \WORD_SIZE_BY = 4 Generating RTLIL representation for module `$paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART'. Parameter \CLK_FREQ = 25000000 Parameter \PULSE_CONTROL_BITS = 32 Parameter \BUS_WIDTH = 32 Parameter \ID = 0 Parameter \RESET_CLK_CYCLES = 20 18.3.13. Executing AST frontend in derive mode using pre-parsed AST for module `\Interpreter'. Parameter \CLK_FREQ = 25000000 Parameter \PULSE_CONTROL_BITS = 32 Parameter \BUS_WIDTH = 32 Parameter \ID = 0 Parameter \RESET_CLK_CYCLES = 20 Generating RTLIL representation for module `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter'. Parameter \COUNTER_BITS = 32 Parameter \PULSE_CONTROL_BITS = 32 18.3.14. Executing AST frontend in derive mode using pre-parsed AST for module `\ClkDivider'. Parameter \COUNTER_BITS = 32 Parameter \PULSE_CONTROL_BITS = 32 Generating RTLIL representation for module `$paramod$1849aaf56e55fcd2c7df624bf67aa48a75c68e43\ClkDivider'. 18.3.15. Analyzing design hierarchy.. Top module: \processorci_top Used module: $paramod\ResetBootSystem\CYCLES=s32'00000000000000000000000000010100 Used module: \Grande_Risco5 Used module: \MUX Used module: \Forwarding_Unit Used module: \Immediate_Generator Used module: \Alu Used module: \ALU_Control Used module: \Registers Used module: $paramod$be568a6683087bc1c783fd234d0a3f16819ced17\Controller Used module: $paramod$860abc9b363840d7b46a2d1e00ea80d20a30d2ee\Memory Used module: $paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART Used module: \uart_tx Used module: \uart_rx Used module: \FIFO Used module: $paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter Used module: $paramod$1849aaf56e55fcd2c7df624bf67aa48a75c68e43\ClkDivider Parameter \BIT_RATE = 115200 Parameter \CLK_HZ = 25000000 Parameter \PAYLOAD_BITS = 8 18.3.16. Executing AST frontend in derive mode using pre-parsed AST for module `\uart_tx'. Parameter \BIT_RATE = 115200 Parameter \CLK_HZ = 25000000 Parameter \PAYLOAD_BITS = 8 Generating RTLIL representation for module `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tx'. Parameter \BIT_RATE = 115200 Parameter \CLK_HZ = 25000000 Parameter \PAYLOAD_BITS = 8 18.3.17. Executing AST frontend in derive mode using pre-parsed AST for module `\uart_rx'. Parameter \BIT_RATE = 115200 Parameter \CLK_HZ = 25000000 Parameter \PAYLOAD_BITS = 8 Generating RTLIL representation for module `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx'. Parameter \DEPTH = 8 Parameter \WIDTH = 8 Found cached RTLIL representation for module `$paramod$fb00a4f1e01b6404091dd91fbb53b046994f1d61\FIFO'. Parameter \DEPTH = 8 Parameter \WIDTH = 8 Found cached RTLIL representation for module `$paramod$fb00a4f1e01b6404091dd91fbb53b046994f1d61\FIFO'. 18.3.18. Analyzing design hierarchy.. Top module: \processorci_top Used module: $paramod\ResetBootSystem\CYCLES=s32'00000000000000000000000000010100 Used module: \Grande_Risco5 Used module: \MUX Used module: \Forwarding_Unit Used module: \Immediate_Generator Used module: \Alu Used module: \ALU_Control Used module: \Registers Used module: $paramod$be568a6683087bc1c783fd234d0a3f16819ced17\Controller Used module: $paramod$860abc9b363840d7b46a2d1e00ea80d20a30d2ee\Memory Used module: $paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART Used module: $paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tx Used module: $paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx Used module: $paramod$fb00a4f1e01b6404091dd91fbb53b046994f1d61\FIFO Used module: $paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter Used module: $paramod$1849aaf56e55fcd2c7df624bf67aa48a75c68e43\ClkDivider 18.3.19. Analyzing design hierarchy.. Top module: \processorci_top Used module: $paramod\ResetBootSystem\CYCLES=s32'00000000000000000000000000010100 Used module: \Grande_Risco5 Used module: \MUX Used module: \Forwarding_Unit Used module: \Immediate_Generator Used module: \Alu Used module: \ALU_Control Used module: \Registers Used module: $paramod$be568a6683087bc1c783fd234d0a3f16819ced17\Controller Used module: $paramod$860abc9b363840d7b46a2d1e00ea80d20a30d2ee\Memory Used module: $paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART Used module: $paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tx Used module: $paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx Used module: $paramod$fb00a4f1e01b6404091dd91fbb53b046994f1d61\FIFO Used module: $paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter Used module: $paramod$1849aaf56e55fcd2c7df624bf67aa48a75c68e43\ClkDivider Removing unused module `$paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_rx'. Removing unused module `$paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tx'. Removing unused module `$paramod$d236a3555e5fe48231d3a0bdd0f1031eebbe67d5\ClkDivider'. Removing unused module `$paramod$6cc68bce6e5ef8358e4f854f8e1607a73728e8ac\Interpreter'. Removing unused module `$paramod$0ebcb351531b968e3a65ee57624639e797f21099\UART'. Removing unused module `\Controller'. Removing unused module `\Interpreter'. Removing unused module `\Memory'. Removing unused module `\ClkDivider'. Removing unused module `\ResetBootSystem'. Removing unused module `\FIFO'. Removing unused module `\uart_tx'. Removing unused module `\uart_rx'. Removing unused module `\UART'. Removed 14 unused modules. 18.4. Executing PROC pass (convert processes to netlists). 18.4.1. Executing PROC_CLEAN pass (remove empty switches from decision trees). Found and cleaned up 1 empty switch in `\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$559'. Found and cleaned up 1 empty switch in `$paramod$860abc9b363840d7b46a2d1e00ea80d20a30d2ee\Memory.$proc$/eda/processor-ci-controller/src/memory.v:0$741'. Removing empty process `$paramod$860abc9b363840d7b46a2d1e00ea80d20a30d2ee\Memory.$proc$/eda/processor-ci-controller/src/memory.v:0$741'. Cleaned up 2 empty switches. 18.4.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees). Marked 1 switch rules as full_case in process $proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:350$666 in module TRELLIS_FF. Marked 1 switch rules as full_case in process $proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:285$618 in module DPR16X4C. Marked 1 switch rules as full_case in process $proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$560 in module TRELLIS_DPR16X4. Marked 2 switch rules as full_case in process $proc$/eda/processor-ci-controller/src/fifo.v:36$921 in module $paramod$fb00a4f1e01b6404091dd91fbb53b046994f1d61\FIFO. Marked 1 switch rules as full_case in process $proc$/eda/processor-ci-controller/src/fifo.v:25$913 in module $paramod$fb00a4f1e01b6404091dd91fbb53b046994f1d61\FIFO. Marked 1 switch rules as full_case in process $proc$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:196$1114 in module $paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx. Marked 1 switch rules as full_case in process $proc$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:185$1112 in module $paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx. Marked 2 switch rules as full_case in process $proc$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:170$1104 in module $paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx. Marked 1 switch rules as full_case in process $proc$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:159$1101 in module $paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx. Marked 2 switch rules as full_case in process $proc$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:147$1095 in module $paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx. Marked 3 switch rules as full_case in process $proc$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:132$1090 in module $paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx. Marked 1 switch rules as full_case in process $proc$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:115$1085 in module $paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx. Marked 1 switch rules as full_case in process $proc$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:96$1076 in module $paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx. Marked 4 switch rules as full_case in process $proc$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:173$1063 in module $paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tx. Marked 1 switch rules as full_case in process $proc$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:162$1061 in module $paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tx. Marked 2 switch rules as full_case in process $proc$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:147$1053 in module $paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tx. Marked 4 switch rules as full_case in process $proc$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:130$1039 in module $paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tx. Marked 3 switch rules as full_case in process $proc$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:115$1033 in module $paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tx. Marked 1 switch rules as full_case in process $proc$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:98$1028 in module $paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tx. Marked 1 switch rules as full_case in process $proc$/eda/processor-ci-controller/src/clk_divider.v:57$1015 in module $paramod$1849aaf56e55fcd2c7df624bf67aa48a75c68e43\ClkDivider. Marked 3 switch rules as full_case in process $proc$/eda/processor-ci-controller/src/clk_divider.v:36$1006 in module $paramod$1849aaf56e55fcd2c7df624bf67aa48a75c68e43\ClkDivider. Marked 15 switch rules as full_case in process $proc$/eda/processor-ci-controller/src/interpreter.v:116$970 in module $paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter. Removed 1 dead cases from process $proc$/eda/processor-ci-controller/modules/uart.v:203$962 in module $paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART. Marked 2 switch rules as full_case in process $proc$/eda/processor-ci-controller/modules/uart.v:203$962 in module $paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART. Marked 1 switch rules as full_case in process $proc$/eda/processor-ci-controller/modules/uart.v:187$957 in module $paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART. Marked 4 switch rules as full_case in process $proc$/eda/processor-ci-controller/modules/uart.v:132$952 in module $paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART. Marked 4 switch rules as full_case in process $proc$/eda/processor-ci-controller/modules/uart.v:74$947 in module $paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART. Marked 1 switch rules as full_case in process $proc$/eda/processor-ci-controller/src/memory.v:36$730 in module $paramod$860abc9b363840d7b46a2d1e00ea80d20a30d2ee\Memory. Marked 2 switch rules as full_case in process $proc$/eda/processor-ci-controller/src/controller.v:113$719 in module $paramod$be568a6683087bc1c783fd234d0a3f16819ced17\Controller. Marked 5 switch rules as full_case in process $proc$/eda/processor-ci-controller/src/reset.v:25$669 in module $paramod\ResetBootSystem\CYCLES=s32'00000000000000000000000000010100. Marked 1 switch rules as full_case in process $proc$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/src/core/registers.v:26$154 in module Registers. Removed 1 dead cases from process $proc$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/src/core/mux.v:10$139 in module MUX. Marked 1 switch rules as full_case in process $proc$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/src/core/mux.v:10$139 in module MUX. Marked 2 switch rules as full_case in process $proc$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/src/core/immediate_generator.v:18$138 in module Immediate_Generator. Marked 6 switch rules as full_case in process $proc$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/src/core/forwarding_unit.v:13$123 in module Forwarding_Unit. Marked 1 switch rules as full_case in process $proc$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/src/core/core.v:270$120 in module Grande_Risco5. Marked 1 switch rules as full_case in process $proc$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/src/core/core.v:258$119 in module Grande_Risco5. Marked 1 switch rules as full_case in process $proc$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/src/core/core.v:226$98 in module Grande_Risco5. Marked 2 switch rules as full_case in process $proc$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/src/core/core.v:190$85 in module Grande_Risco5. Marked 2 switch rules as full_case in process $proc$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/src/core/core.v:169$77 in module Grande_Risco5. Marked 4 switch rules as full_case in process $proc$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/src/core/core.v:122$50 in module Grande_Risco5. Marked 5 switch rules as full_case in process $proc$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/src/core/core.v:80$31 in module Grande_Risco5. Removed 1 dead cases from process $proc$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/src/core/alu_control.v:9$25 in module ALU_Control. Marked 4 switch rules as full_case in process $proc$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/src/core/alu_control.v:9$25 in module ALU_Control. Marked 1 switch rules as full_case in process $proc$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/src/core/alu.v:26$5 in module Alu. Removed a total of 3 dead cases. 18.4.3. Executing PROC_PRUNE pass (remove redundant assignments in processes). Removed 6 redundant assignments. Promoted 104 assignments to connections. 18.4.4. Executing PROC_INIT pass (extract init attributes). Found init rule in `\TRELLIS_FF.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$667'. Set init value: \Q = 1'0 Found init rule in `$paramod$fb00a4f1e01b6404091dd91fbb53b046994f1d61\FIFO.$proc$/eda/processor-ci-controller/src/fifo.v:0$946'. Set init value: \read_ptr = 6'000000 Set init value: \write_ptr = 6'000000 Found init rule in `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:131$1116'. Set init value: \i = 0 Found init rule in `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:114$1069'. Set init value: \i = 0 Found init rule in `$paramod$1849aaf56e55fcd2c7df624bf67aa48a75c68e43\ClkDivider.$proc$/eda/processor-ci-controller/src/clk_divider.v:0$1021'. Set init value: \clk_o_auto = 1'0 Set init value: \clk_counter = 0 Set init value: \pulse_counter = 0 Found init rule in `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.$proc$/eda/processor-ci-controller/src/interpreter.v:0$999'. Set init value: \state = 8'00000000 Set init value: \counter = 8'00000000 Set init value: \read_buffer = 0 Set init value: \timeout = 0 Set init value: \accumulator = 64'0000000000000000000000000000000000000000000000000000000000000000 Found init rule in `$paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART.$proc$/eda/processor-ci-controller/modules/uart.v:0$969'. Set init value: \read_data = 0 Set init value: \read_response = 1'0 Set init value: \write_response = 1'0 Set init value: \uart_tx_en = 1'0 Set init value: \tx_fifo_read = 1'0 Set init value: \tx_fifo_write = 1'0 Set init value: \rx_fifo_read = 1'0 Set init value: \rx_fifo_write = 1'0 Set init value: \uart_tx_data = 8'00000000 Set init value: \tx_fifo_write_data = 8'00000000 Set init value: \rx_fifo_write_data = 8'00000000 Set init value: \counter_write = 3'000 Set init value: \counter_read = 3'000 Set init value: \state_read = 4'0000 Set init value: \state_write = 4'0000 Found init rule in `$paramod\ResetBootSystem\CYCLES=s32'00000000000000000000000000010100.$proc$/eda/processor-ci-controller/src/reset.v:0$676'. Set init value: \reset_o = 1'0 Set init value: \state = 2'01 Set init value: \counter = 6'000000 18.4.5. Executing PROC_ARST pass (detect async resets in processes). 18.4.6. Executing PROC_ROM pass (convert switches to ROMs). Converted 0 switches. <suppressed ~135 debug messages> 18.4.7. Executing PROC_MUX pass (convert decision trees to multiplexers). Creating decoders for process `\TRELLIS_FF.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$667'. Creating decoders for process `\TRELLIS_FF.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:350$666'. 1/1: $0\Q[0:0] Creating decoders for process `\DPR16X4C.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$641'. Creating decoders for process `\DPR16X4C.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:285$618'. 1/3: $1$memwr$\ram$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:287$617_EN[3:0]$624 2/3: $1$memwr$\ram$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:287$617_DATA[3:0]$623 3/3: $1$memwr$\ram$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:287$617_ADDR[3:0]$622 Creating decoders for process `\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$584'. Creating decoders for process `\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$560'. 1/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$558_EN[3:0]$566 2/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$558_DATA[3:0]$565 3/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$558_ADDR[3:0]$564 Creating decoders for process `\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$559'. Creating decoders for process `$paramod$fb00a4f1e01b6404091dd91fbb53b046994f1d61\FIFO.$proc$/eda/processor-ci-controller/src/fifo.v:0$946'. Creating decoders for process `$paramod$fb00a4f1e01b6404091dd91fbb53b046994f1d61\FIFO.$proc$/eda/processor-ci-controller/src/fifo.v:36$921'. 1/7: $2$memwr$\memory$/eda/processor-ci-controller/src/fifo.v:41$912_EN[7:0]$933 2/7: $2$memwr$\memory$/eda/processor-ci-controller/src/fifo.v:41$912_DATA[7:0]$932 3/7: $2$memwr$\memory$/eda/processor-ci-controller/src/fifo.v:41$912_ADDR[5:0]$931 4/7: $1$memwr$\memory$/eda/processor-ci-controller/src/fifo.v:41$912_EN[7:0]$927 5/7: $1$memwr$\memory$/eda/processor-ci-controller/src/fifo.v:41$912_DATA[7:0]$926 6/7: $1$memwr$\memory$/eda/processor-ci-controller/src/fifo.v:41$912_ADDR[5:0]$925 7/7: $0\write_ptr[5:0] Creating decoders for process `$paramod$fb00a4f1e01b6404091dd91fbb53b046994f1d61\FIFO.$proc$/eda/processor-ci-controller/src/fifo.v:25$913'. 1/2: $0\read_ptr[5:0] 2/2: $0\read_data[7:0] Creating decoders for process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:131$1116'. Creating decoders for process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:196$1114'. 1/2: $0\rxd_reg_0[0:0] 2/2: $0\rxd_reg[0:0] Creating decoders for process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:185$1112'. 1/1: $0\fsm_state[2:0] Creating decoders for process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:170$1104'. 1/1: $0\cycle_counter[8:0] Creating decoders for process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:159$1101'. 1/1: $0\bit_sample[0:0] Creating decoders for process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:147$1095'. 1/1: $0\bit_counter[3:0] Creating decoders for process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:132$1090'. 1/11: $3\i[31:0] 2/11: $0\recieved_data[7:0] [1] 3/11: $0\recieved_data[7:0] [0] 4/11: $0\recieved_data[7:0] [2] 5/11: $0\recieved_data[7:0] [3] 6/11: $0\recieved_data[7:0] [4] 7/11: $0\recieved_data[7:0] [5] 8/11: $0\recieved_data[7:0] [6] 9/11: $0\recieved_data[7:0] [7] 10/11: $1\i[31:0] 11/11: $2\i[31:0] Creating decoders for process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:115$1085'. 1/1: $1\n_fsm_state[2:0] Creating decoders for process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:96$1076'. 1/1: $0\uart_rx_data[7:0] Creating decoders for process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:114$1069'. Creating decoders for process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:173$1063'. 1/1: $0\txd_reg[0:0] Creating decoders for process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:162$1061'. 1/1: $0\fsm_state[2:0] Creating decoders for process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:147$1053'. 1/1: $0\cycle_counter[8:0] Creating decoders for process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:130$1039'. 1/1: $0\bit_counter[3:0] Creating decoders for process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:115$1033'. 1/11: $3\i[31:0] 2/11: $0\data_to_send[7:0] [1] 3/11: $0\data_to_send[7:0] [0] 4/11: $0\data_to_send[7:0] [2] 5/11: $0\data_to_send[7:0] [3] 6/11: $0\data_to_send[7:0] [4] 7/11: $0\data_to_send[7:0] [5] 8/11: $0\data_to_send[7:0] [6] 9/11: $0\data_to_send[7:0] [7] 10/11: $1\i[31:0] 11/11: $2\i[31:0] Creating decoders for process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:98$1028'. 1/1: $1\n_fsm_state[2:0] Creating decoders for process `$paramod$1849aaf56e55fcd2c7df624bf67aa48a75c68e43\ClkDivider.$proc$/eda/processor-ci-controller/src/clk_divider.v:0$1021'. Creating decoders for process `$paramod$1849aaf56e55fcd2c7df624bf67aa48a75c68e43\ClkDivider.$proc$/eda/processor-ci-controller/src/clk_divider.v:57$1015'. 1/1: $0\pulse_counter[31:0] Creating decoders for process `$paramod$1849aaf56e55fcd2c7df624bf67aa48a75c68e43\ClkDivider.$proc$/eda/processor-ci-controller/src/clk_divider.v:36$1006'. 1/2: $0\clk_counter[31:0] 2/2: $0\clk_o_auto[0:0] Creating decoders for process `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.$proc$/eda/processor-ci-controller/src/interpreter.v:0$999'. Creating decoders for process `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.$proc$/eda/processor-ci-controller/src/interpreter.v:116$970'. 1/28: $0\state[7:0] 2/28: $0\reset_bus[0:0] 3/28: $0\memory_write[0:0] 4/28: $0\memory_read[0:0] 5/28: $0\write_pulse[0:0] 6/28: $0\core_reset[0:0] 7/28: $0\communication_write[0:0] 8/28: $0\communication_read[0:0] 9/28: $0\temp_buffer[63:0] 10/28: $0\accumulator[63:0] 11/28: $0\timeout_counter[31:0] 12/28: $0\timeout[31:0] 13/28: $0\read_buffer[31:0] 14/28: $0\communication_buffer[31:0] 15/28: $0\num_of_positions[23:0] 16/28: $0\num_of_pages[23:0] 17/28: $0\return_state[7:0] 18/28: $0\memory_page_number[23:0] 19/28: $0\memory_mux_selector[0:0] 20/28: $0\end_position[31:0] 21/28: $0\memory_page_size[23:0] 22/28: $0\bus_mode[0:0] 23/28: $0\num_of_cycles_to_pulse[31:0] 24/28: $0\core_clk_enable[0:0] 25/28: $0\communication_write_data[31:0] 26/28: $0\address[31:0] 27/28: $0\counter[7:0] 28/28: $0\write_data[31:0] Creating decoders for process `$paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART.$proc$/eda/processor-ci-controller/modules/uart.v:0$969'. Creating decoders for process `$paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART.$proc$/eda/processor-ci-controller/modules/uart.v:203$962'. 1/4: $0\tx_fifo_read[0:0] 2/4: $0\uart_tx_en[0:0] 3/4: $0\tx_fifo_read_state[1:0] 4/4: $0\uart_tx_data[7:0] Creating decoders for process `$paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART.$proc$/eda/processor-ci-controller/modules/uart.v:187$957'. 1/2: $0\rx_fifo_write[0:0] 2/2: $0\rx_fifo_write_data[7:0] Creating decoders for process `$paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART.$proc$/eda/processor-ci-controller/modules/uart.v:132$952'. 1/6: $0\tx_fifo_write[0:0] 2/6: $0\write_response[0:0] 3/6: $0\state_write[3:0] 4/6: $0\counter_write[2:0] 5/6: $0\write_data_buffer[31:0] 6/6: $0\tx_fifo_write_data[7:0] Creating decoders for process `$paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART.$proc$/eda/processor-ci-controller/modules/uart.v:74$947'. 1/5: $0\read_response[0:0] 2/5: $0\rx_fifo_read[0:0] 3/5: $0\state_read[3:0] 4/5: $0\counter_read[2:0] 5/5: $0\read_data[31:0] Creating decoders for process `$paramod$860abc9b363840d7b46a2d1e00ea80d20a30d2ee\Memory.$proc$/eda/processor-ci-controller/src/memory.v:45$740'. Creating decoders for process `$paramod$860abc9b363840d7b46a2d1e00ea80d20a30d2ee\Memory.$proc$/eda/processor-ci-controller/src/memory.v:36$730'. 1/4: $1$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$725_EN[31:0]$739 2/4: $1$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$725_DATA[31:0]$738 3/4: $1$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$725_ADDR[31:0]$737 4/4: $0\read_sync[31:0] Creating decoders for process `$paramod$be568a6683087bc1c783fd234d0a3f16819ced17\Controller.$proc$/eda/processor-ci-controller/src/controller.v:113$719'. 1/1: $0\finish_execution[0:0] Creating decoders for process `$paramod\ResetBootSystem\CYCLES=s32'00000000000000000000000000010100.$proc$/eda/processor-ci-controller/src/reset.v:0$676'. Creating decoders for process `$paramod\ResetBootSystem\CYCLES=s32'00000000000000000000000000010100.$proc$/eda/processor-ci-controller/src/reset.v:25$669'. 1/3: $0\counter[5:0] 2/3: $0\state[1:0] 3/3: $0\reset_o[0:0] Creating decoders for process `\Registers.$proc$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/src/core/registers.v:26$154'. 1/3: $1$memwr$\registers$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/src/core/registers.v:28$140_EN[31:0]$161 2/3: $1$memwr$\registers$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/src/core/registers.v:28$140_DATA[31:0]$160 3/3: $1$memwr$\registers$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/src/core/registers.v:28$140_ADDR[4:0]$159 Creating decoders for process `\MUX.$proc$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/src/core/mux.v:10$139'. 1/1: $1\S[31:0] Creating decoders for process `\Immediate_Generator.$proc$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/src/core/immediate_generator.v:18$138'. 1/2: $2\immediate[31:0] 2/2: $1\immediate[31:0] Creating decoders for process `\Forwarding_Unit.$proc$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/src/core/forwarding_unit.v:13$123'. 1/6: $3\op_rs2[1:0] 2/6: $2\op_rs2[1:0] 3/6: $1\op_rs2[1:0] 4/6: $3\op_rs1[1:0] 5/6: $2\op_rs1[1:0] 6/6: $1\op_rs1[1:0] Creating decoders for process `\Grande_Risco5.$proc$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/src/core/core.v:270$120'. 1/1: $1\aluop[1:0] Creating decoders for process `\Grande_Risco5.$proc$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/src/core/core.v:258$119'. 1/1: $0\is_immediate[0:0] Creating decoders for process `\Grande_Risco5.$proc$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/src/core/core.v:226$98'. 1/5: $0\MEMWBIR[31:0] 2/5: $0\mem_to_reg[0:0] 3/5: $0\reg_write[0:0] 4/5: $0\MEMWBALUOut[31:0] 5/5: $0\MEMWB_mem_read_data[31:0] Creating decoders for process `\Grande_Risco5.$proc$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/src/core/core.v:190$85'. 1/6: $0\memory_read[0:0] 2/6: $0\memory_write[0:0] 3/6: $0\EXMEMIR[31:0] 4/6: $0\EXMEMALUOut[31:0] 5/6: $0\EXMEM_mem_data_value[31:0] 6/6: $0\IMMEDIATE_REG[31:0] Creating decoders for process `\Grande_Risco5.$proc$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/src/core/core.v:169$77'. 1/3: $0\memory_write_data[31:0] 2/3: $0\EXEXIR[31:0] 3/3: $0\EXEXPC[31:0] Creating decoders for process `\Grande_Risco5.$proc$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/src/core/core.v:122$50'. 1/7: $0\IDEXIR[31:0] 2/7: $0\aluop_out_reg[3:0] 3/7: $0\alu_input_b[31:0] 4/7: $0\alu_input_a[31:0] 5/7: $0\IDEXPC[31:0] 6/7: $0\IDEXB[31:0] 7/7: $0\IDEXA[31:0] Creating decoders for process `\Grande_Risco5.$proc$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/src/core/core.v:80$31'. 1/3: $0\IFIDIR[31:0] 2/3: $0\IFIDPC[31:0] 3/3: $0\PC[31:0] Creating decoders for process `\ALU_Control.$proc$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/src/core/alu_control.v:9$25'. 1/1: $0\aluop_out[3:0] Creating decoders for process `\Alu.$proc$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/src/core/alu.v:26$5'. 1/1: $1\ALU_out_S[31:0] 18.4.8. Executing PROC_DLATCH pass (convert process syncs to latches). No latch inferred for signal `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx.\n_fsm_state' from process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:115$1085'. No latch inferred for signal `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tx.\n_fsm_state' from process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:98$1028'. No latch inferred for signal `\MUX.\S' from process `\MUX.$proc$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/src/core/mux.v:10$139'. No latch inferred for signal `\Immediate_Generator.\immediate' from process `\Immediate_Generator.$proc$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/src/core/immediate_generator.v:18$138'. No latch inferred for signal `\Forwarding_Unit.\op_rs1' from process `\Forwarding_Unit.$proc$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/src/core/forwarding_unit.v:13$123'. No latch inferred for signal `\Forwarding_Unit.\op_rs2' from process `\Forwarding_Unit.$proc$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/src/core/forwarding_unit.v:13$123'. No latch inferred for signal `\Grande_Risco5.\aluop' from process `\Grande_Risco5.$proc$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/src/core/core.v:270$120'. No latch inferred for signal `\ALU_Control.\aluop_out' from process `\ALU_Control.$proc$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/src/core/alu_control.v:9$25'. No latch inferred for signal `\Alu.\ALU_out_S' from process `\Alu.$proc$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/src/core/alu.v:26$5'. 18.4.9. Executing PROC_DFF pass (convert process syncs to FFs). Creating register for signal `\TRELLIS_FF.\Q' using process `\TRELLIS_FF.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:350$666'. created $dff cell `$procdff$2757' with positive edge clock. Creating register for signal `\DPR16X4C.\i' using process `\DPR16X4C.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$641'. created direct connection (no actual register cell created). Creating register for signal `\DPR16X4C.$memwr$\ram$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:281$602_EN' using process `\DPR16X4C.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$641'. created direct connection (no actual register cell created). Creating register for signal `\DPR16X4C.$memwr$\ram$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:281$603_EN' using process `\DPR16X4C.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$641'. created direct connection (no actual register cell created). Creating register for signal `\DPR16X4C.$memwr$\ram$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:281$604_EN' using process `\DPR16X4C.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$641'. created direct connection (no actual register cell created). Creating register for signal `\DPR16X4C.$memwr$\ram$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:281$605_EN' using process `\DPR16X4C.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$641'. created direct connection (no actual register cell created). Creating register for signal `\DPR16X4C.$memwr$\ram$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:281$606_EN' using process `\DPR16X4C.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$641'. created direct connection (no actual register cell created). Creating register for signal `\DPR16X4C.$memwr$\ram$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:281$607_EN' using process `\DPR16X4C.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$641'. created direct connection (no actual register cell created). Creating register for signal `\DPR16X4C.$memwr$\ram$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:281$608_EN' using process `\DPR16X4C.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$641'. created direct connection (no actual register cell created). Creating register for signal `\DPR16X4C.$memwr$\ram$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:281$609_EN' using process `\DPR16X4C.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$641'. created direct connection (no actual register cell created). Creating register for signal `\DPR16X4C.$memwr$\ram$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:281$610_EN' using process `\DPR16X4C.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$641'. created direct connection (no actual register cell created). Creating register for signal `\DPR16X4C.$memwr$\ram$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:281$611_EN' using process `\DPR16X4C.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$641'. created direct connection (no actual register cell created). Creating register for signal `\DPR16X4C.$memwr$\ram$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:281$612_EN' using process `\DPR16X4C.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$641'. created direct connection (no actual register cell created). Creating register for signal `\DPR16X4C.$memwr$\ram$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:281$613_EN' using process `\DPR16X4C.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$641'. created direct connection (no actual register cell created). Creating register for signal `\DPR16X4C.$memwr$\ram$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:281$614_EN' using process `\DPR16X4C.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$641'. created direct connection (no actual register cell created). Creating register for signal `\DPR16X4C.$memwr$\ram$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:281$615_EN' using process `\DPR16X4C.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$641'. created direct connection (no actual register cell created). Creating register for signal `\DPR16X4C.$memwr$\ram$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:281$616_EN' using process `\DPR16X4C.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$641'. created direct connection (no actual register cell created). Creating register for signal `\DPR16X4C.$memwr$\ram$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:287$617_ADDR' using process `\DPR16X4C.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:285$618'. created $dff cell `$procdff$2758' with positive edge clock. Creating register for signal `\DPR16X4C.$memwr$\ram$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:287$617_DATA' using process `\DPR16X4C.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:285$618'. created $dff cell `$procdff$2759' with positive edge clock. Creating register for signal `\DPR16X4C.$memwr$\ram$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:287$617_EN' using process `\DPR16X4C.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:285$618'. created $dff cell `$procdff$2760' with positive edge clock. Creating register for signal `\TRELLIS_DPR16X4.\i' using process `\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$584'. created direct connection (no actual register cell created). Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$542_EN' using process `\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$584'. created direct connection (no actual register cell created). Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$543_EN' using process `\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$584'. created direct connection (no actual register cell created). Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$544_EN' using process `\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$584'. created direct connection (no actual register cell created). Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$545_EN' using process `\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$584'. created direct connection (no actual register cell created). Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$546_EN' using process `\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$584'. created direct connection (no actual register cell created). Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$547_EN' using process `\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$584'. created direct connection (no actual register cell created). Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$548_EN' using process `\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$584'. created direct connection (no actual register cell created). Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$549_EN' using process `\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$584'. created direct connection (no actual register cell created). Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$550_EN' using process `\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$584'. created direct connection (no actual register cell created). Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$551_EN' using process `\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$584'. created direct connection (no actual register cell created). Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$552_EN' using process `\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$584'. created direct connection (no actual register cell created). Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$553_EN' using process `\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$584'. created direct connection (no actual register cell created). Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$554_EN' using process `\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$584'. created direct connection (no actual register cell created). Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$555_EN' using process `\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$584'. created direct connection (no actual register cell created). Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$556_EN' using process `\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$584'. created direct connection (no actual register cell created). Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$557_EN' using process `\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$584'. created direct connection (no actual register cell created). Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$558_ADDR' using process `\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$560'. created $dff cell `$procdff$2761' with positive edge clock. Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$558_DATA' using process `\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$560'. created $dff cell `$procdff$2762' with positive edge clock. Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$558_EN' using process `\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$560'. created $dff cell `$procdff$2763' with positive edge clock. Creating register for signal `\TRELLIS_DPR16X4.\muxwre' using process `\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$559'. created direct connection (no actual register cell created). Creating register for signal `$paramod$fb00a4f1e01b6404091dd91fbb53b046994f1d61\FIFO.\write_ptr' using process `$paramod$fb00a4f1e01b6404091dd91fbb53b046994f1d61\FIFO.$proc$/eda/processor-ci-controller/src/fifo.v:36$921'. created $dff cell `$procdff$2764' with positive edge clock. Creating register for signal `$paramod$fb00a4f1e01b6404091dd91fbb53b046994f1d61\FIFO.$memwr$\memory$/eda/processor-ci-controller/src/fifo.v:41$912_ADDR' using process `$paramod$fb00a4f1e01b6404091dd91fbb53b046994f1d61\FIFO.$proc$/eda/processor-ci-controller/src/fifo.v:36$921'. created $dff cell `$procdff$2765' with positive edge clock. Creating register for signal `$paramod$fb00a4f1e01b6404091dd91fbb53b046994f1d61\FIFO.$memwr$\memory$/eda/processor-ci-controller/src/fifo.v:41$912_DATA' using process `$paramod$fb00a4f1e01b6404091dd91fbb53b046994f1d61\FIFO.$proc$/eda/processor-ci-controller/src/fifo.v:36$921'. created $dff cell `$procdff$2766' with positive edge clock. Creating register for signal `$paramod$fb00a4f1e01b6404091dd91fbb53b046994f1d61\FIFO.$memwr$\memory$/eda/processor-ci-controller/src/fifo.v:41$912_EN' using process `$paramod$fb00a4f1e01b6404091dd91fbb53b046994f1d61\FIFO.$proc$/eda/processor-ci-controller/src/fifo.v:36$921'. created $dff cell `$procdff$2767' with positive edge clock. Creating register for signal `$paramod$fb00a4f1e01b6404091dd91fbb53b046994f1d61\FIFO.\read_data' using process `$paramod$fb00a4f1e01b6404091dd91fbb53b046994f1d61\FIFO.$proc$/eda/processor-ci-controller/src/fifo.v:25$913'. created $dff cell `$procdff$2768' with positive edge clock. Creating register for signal `$paramod$fb00a4f1e01b6404091dd91fbb53b046994f1d61\FIFO.\read_ptr' using process `$paramod$fb00a4f1e01b6404091dd91fbb53b046994f1d61\FIFO.$proc$/eda/processor-ci-controller/src/fifo.v:25$913'. created $dff cell `$procdff$2769' with positive edge clock. Creating register for signal `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx.\rxd_reg' using process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:196$1114'. created $dff cell `$procdff$2770' with positive edge clock. Creating register for signal `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx.\rxd_reg_0' using process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:196$1114'. created $dff cell `$procdff$2771' with positive edge clock. Creating register for signal `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx.\fsm_state' using process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:185$1112'. created $dff cell `$procdff$2772' with positive edge clock. Creating register for signal `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx.\cycle_counter' using process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:170$1104'. created $dff cell `$procdff$2773' with positive edge clock. Creating register for signal `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx.\bit_sample' using process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:159$1101'. created $dff cell `$procdff$2774' with positive edge clock. Creating register for signal `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx.\bit_counter' using process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:147$1095'. created $dff cell `$procdff$2775' with positive edge clock. Creating register for signal `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx.\recieved_data' using process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:132$1090'. created $dff cell `$procdff$2776' with positive edge clock. Creating register for signal `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx.\i' using process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:132$1090'. created $dff cell `$procdff$2777' with positive edge clock. Creating register for signal `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx.\uart_rx_data' using process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:96$1076'. created $dff cell `$procdff$2778' with positive edge clock. Creating register for signal `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tx.\txd_reg' using process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:173$1063'. created $dff cell `$procdff$2779' with positive edge clock. Creating register for signal `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tx.\fsm_state' using process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:162$1061'. created $dff cell `$procdff$2780' with positive edge clock. Creating register for signal `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tx.\cycle_counter' using process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:147$1053'. created $dff cell `$procdff$2781' with positive edge clock. Creating register for signal `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tx.\bit_counter' using process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:130$1039'. created $dff cell `$procdff$2782' with positive edge clock. Creating register for signal `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tx.\i' using process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:115$1033'. created $dff cell `$procdff$2783' with positive edge clock. Creating register for signal `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tx.\data_to_send' using process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:115$1033'. created $dff cell `$procdff$2784' with positive edge clock. Creating register for signal `$paramod$1849aaf56e55fcd2c7df624bf67aa48a75c68e43\ClkDivider.\pulse_counter' using process `$paramod$1849aaf56e55fcd2c7df624bf67aa48a75c68e43\ClkDivider.$proc$/eda/processor-ci-controller/src/clk_divider.v:57$1015'. created $dff cell `$procdff$2785' with positive edge clock. Creating register for signal `$paramod$1849aaf56e55fcd2c7df624bf67aa48a75c68e43\ClkDivider.\clk_o_auto' using process `$paramod$1849aaf56e55fcd2c7df624bf67aa48a75c68e43\ClkDivider.$proc$/eda/processor-ci-controller/src/clk_divider.v:36$1006'. created $dff cell `$procdff$2786' with positive edge clock. Creating register for signal `$paramod$1849aaf56e55fcd2c7df624bf67aa48a75c68e43\ClkDivider.\clk_counter' using process `$paramod$1849aaf56e55fcd2c7df624bf67aa48a75c68e43\ClkDivider.$proc$/eda/processor-ci-controller/src/clk_divider.v:36$1006'. created $dff cell `$procdff$2787' with positive edge clock. Creating register for signal `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.\write_data' using process `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.$proc$/eda/processor-ci-controller/src/interpreter.v:116$970'. created $dff cell `$procdff$2788' with positive edge clock. Creating register for signal `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.\memory_write' using process `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.$proc$/eda/processor-ci-controller/src/interpreter.v:116$970'. created $dff cell `$procdff$2789' with positive edge clock. Creating register for signal `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.\memory_read' using process `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.$proc$/eda/processor-ci-controller/src/interpreter.v:116$970'. created $dff cell `$procdff$2790' with positive edge clock. Creating register for signal `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.\state' using process `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.$proc$/eda/processor-ci-controller/src/interpreter.v:116$970'. created $dff cell `$procdff$2791' with positive edge clock. Creating register for signal `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.\counter' using process `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.$proc$/eda/processor-ci-controller/src/interpreter.v:116$970'. created $dff cell `$procdff$2792' with positive edge clock. Creating register for signal `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.\write_pulse' using process `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.$proc$/eda/processor-ci-controller/src/interpreter.v:116$970'. created $dff cell `$procdff$2793' with positive edge clock. Creating register for signal `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.\address' using process `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.$proc$/eda/processor-ci-controller/src/interpreter.v:116$970'. created $dff cell `$procdff$2794' with positive edge clock. Creating register for signal `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.\communication_read' using process `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.$proc$/eda/processor-ci-controller/src/interpreter.v:116$970'. created $dff cell `$procdff$2795' with positive edge clock. Creating register for signal `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.\communication_write' using process `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.$proc$/eda/processor-ci-controller/src/interpreter.v:116$970'. created $dff cell `$procdff$2796' with positive edge clock. Creating register for signal `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.\communication_write_data' using process `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.$proc$/eda/processor-ci-controller/src/interpreter.v:116$970'. created $dff cell `$procdff$2797' with positive edge clock. Creating register for signal `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.\core_clk_enable' using process `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.$proc$/eda/processor-ci-controller/src/interpreter.v:116$970'. created $dff cell `$procdff$2798' with positive edge clock. Creating register for signal `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.\core_reset' using process `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.$proc$/eda/processor-ci-controller/src/interpreter.v:116$970'. created $dff cell `$procdff$2799' with positive edge clock. Creating register for signal `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.\num_of_cycles_to_pulse' using process `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.$proc$/eda/processor-ci-controller/src/interpreter.v:116$970'. created $dff cell `$procdff$2800' with positive edge clock. Creating register for signal `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.\reset_bus' using process `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.$proc$/eda/processor-ci-controller/src/interpreter.v:116$970'. created $dff cell `$procdff$2801' with positive edge clock. Creating register for signal `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.\bus_mode' using process `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.$proc$/eda/processor-ci-controller/src/interpreter.v:116$970'. created $dff cell `$procdff$2802' with positive edge clock. Creating register for signal `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.\memory_page_size' using process `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.$proc$/eda/processor-ci-controller/src/interpreter.v:116$970'. created $dff cell `$procdff$2803' with positive edge clock. Creating register for signal `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.\end_position' using process `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.$proc$/eda/processor-ci-controller/src/interpreter.v:116$970'. created $dff cell `$procdff$2804' with positive edge clock. Creating register for signal `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.\memory_mux_selector' using process `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.$proc$/eda/processor-ci-controller/src/interpreter.v:116$970'. created $dff cell `$procdff$2805' with positive edge clock. Creating register for signal `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.\memory_page_number' using process `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.$proc$/eda/processor-ci-controller/src/interpreter.v:116$970'. created $dff cell `$procdff$2806' with positive edge clock. Creating register for signal `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.\return_state' using process `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.$proc$/eda/processor-ci-controller/src/interpreter.v:116$970'. created $dff cell `$procdff$2807' with positive edge clock. Creating register for signal `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.\num_of_pages' using process `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.$proc$/eda/processor-ci-controller/src/interpreter.v:116$970'. created $dff cell `$procdff$2808' with positive edge clock. Creating register for signal `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.\num_of_positions' using process `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.$proc$/eda/processor-ci-controller/src/interpreter.v:116$970'. created $dff cell `$procdff$2809' with positive edge clock. Creating register for signal `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.\communication_buffer' using process `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.$proc$/eda/processor-ci-controller/src/interpreter.v:116$970'. created $dff cell `$procdff$2810' with positive edge clock. Creating register for signal `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.\read_buffer' using process `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.$proc$/eda/processor-ci-controller/src/interpreter.v:116$970'. created $dff cell `$procdff$2811' with positive edge clock. Creating register for signal `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.\timeout' using process `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.$proc$/eda/processor-ci-controller/src/interpreter.v:116$970'. created $dff cell `$procdff$2812' with positive edge clock. Creating register for signal `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.\timeout_counter' using process `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.$proc$/eda/processor-ci-controller/src/interpreter.v:116$970'. created $dff cell `$procdff$2813' with positive edge clock. Creating register for signal `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.\accumulator' using process `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.$proc$/eda/processor-ci-controller/src/interpreter.v:116$970'. created $dff cell `$procdff$2814' with positive edge clock. Creating register for signal `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.\temp_buffer' using process `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.$proc$/eda/processor-ci-controller/src/interpreter.v:116$970'. created $dff cell `$procdff$2815' with positive edge clock. Creating register for signal `$paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART.\uart_tx_en' using process `$paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART.$proc$/eda/processor-ci-controller/modules/uart.v:203$962'. created $dff cell `$procdff$2816' with positive edge clock. Creating register for signal `$paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART.\tx_fifo_read' using process `$paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART.$proc$/eda/processor-ci-controller/modules/uart.v:203$962'. created $dff cell `$procdff$2817' with positive edge clock. Creating register for signal `$paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART.\uart_tx_data' using process `$paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART.$proc$/eda/processor-ci-controller/modules/uart.v:203$962'. created $dff cell `$procdff$2818' with positive edge clock. Creating register for signal `$paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART.\tx_fifo_read_state' using process `$paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART.$proc$/eda/processor-ci-controller/modules/uart.v:203$962'. created $dff cell `$procdff$2819' with positive edge clock. Creating register for signal `$paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART.\rx_fifo_write' using process `$paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART.$proc$/eda/processor-ci-controller/modules/uart.v:187$957'. created $dff cell `$procdff$2820' with positive edge clock. Creating register for signal `$paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART.\rx_fifo_write_data' using process `$paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART.$proc$/eda/processor-ci-controller/modules/uart.v:187$957'. created $dff cell `$procdff$2821' with positive edge clock. Creating register for signal `$paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART.\write_response' using process `$paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART.$proc$/eda/processor-ci-controller/modules/uart.v:132$952'. created $dff cell `$procdff$2822' with positive edge clock. Creating register for signal `$paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART.\tx_fifo_write' using process `$paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART.$proc$/eda/processor-ci-controller/modules/uart.v:132$952'. created $dff cell `$procdff$2823' with positive edge clock. Creating register for signal `$paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART.\tx_fifo_write_data' using process `$paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART.$proc$/eda/processor-ci-controller/modules/uart.v:132$952'. created $dff cell `$procdff$2824' with positive edge clock. Creating register for signal `$paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART.\write_data_buffer' using process `$paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART.$proc$/eda/processor-ci-controller/modules/uart.v:132$952'. created $dff cell `$procdff$2825' with positive edge clock. Creating register for signal `$paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART.\counter_write' using process `$paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART.$proc$/eda/processor-ci-controller/modules/uart.v:132$952'. created $dff cell `$procdff$2826' with positive edge clock. Creating register for signal `$paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART.\state_write' using process `$paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART.$proc$/eda/processor-ci-controller/modules/uart.v:132$952'. created $dff cell `$procdff$2827' with positive edge clock. Creating register for signal `$paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART.\read_data' using process `$paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART.$proc$/eda/processor-ci-controller/modules/uart.v:74$947'. created $dff cell `$procdff$2828' with positive edge clock. Creating register for signal `$paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART.\read_response' using process `$paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART.$proc$/eda/processor-ci-controller/modules/uart.v:74$947'. created $dff cell `$procdff$2829' with positive edge clock. Creating register for signal `$paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART.\rx_fifo_read' using process `$paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART.$proc$/eda/processor-ci-controller/modules/uart.v:74$947'. created $dff cell `$procdff$2830' with positive edge clock. Creating register for signal `$paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART.\counter_read' using process `$paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART.$proc$/eda/processor-ci-controller/modules/uart.v:74$947'. created $dff cell `$procdff$2831' with positive edge clock. Creating register for signal `$paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART.\state_read' using process `$paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART.$proc$/eda/processor-ci-controller/modules/uart.v:74$947'. created $dff cell `$procdff$2832' with positive edge clock. Creating register for signal `$paramod$860abc9b363840d7b46a2d1e00ea80d20a30d2ee\Memory.\sync_write_response' using process `$paramod$860abc9b363840d7b46a2d1e00ea80d20a30d2ee\Memory.$proc$/eda/processor-ci-controller/src/memory.v:45$740'. created $dff cell `$procdff$2833' with positive edge clock. Creating register for signal `$paramod$860abc9b363840d7b46a2d1e00ea80d20a30d2ee\Memory.\sync_read_response' using process `$paramod$860abc9b363840d7b46a2d1e00ea80d20a30d2ee\Memory.$proc$/eda/processor-ci-controller/src/memory.v:45$740'. created $dff cell `$procdff$2834' with positive edge clock. Creating register for signal `$paramod$860abc9b363840d7b46a2d1e00ea80d20a30d2ee\Memory.\read_sync' using process `$paramod$860abc9b363840d7b46a2d1e00ea80d20a30d2ee\Memory.$proc$/eda/processor-ci-controller/src/memory.v:36$730'. created $dff cell `$procdff$2835' with positive edge clock. Creating register for signal `$paramod$860abc9b363840d7b46a2d1e00ea80d20a30d2ee\Memory.$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$725_ADDR' using process `$paramod$860abc9b363840d7b46a2d1e00ea80d20a30d2ee\Memory.$proc$/eda/processor-ci-controller/src/memory.v:36$730'. created $dff cell `$procdff$2836' with positive edge clock. Creating register for signal `$paramod$860abc9b363840d7b46a2d1e00ea80d20a30d2ee\Memory.$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$725_DATA' using process `$paramod$860abc9b363840d7b46a2d1e00ea80d20a30d2ee\Memory.$proc$/eda/processor-ci-controller/src/memory.v:36$730'. created $dff cell `$procdff$2837' with positive edge clock. Creating register for signal `$paramod$860abc9b363840d7b46a2d1e00ea80d20a30d2ee\Memory.$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$725_EN' using process `$paramod$860abc9b363840d7b46a2d1e00ea80d20a30d2ee\Memory.$proc$/eda/processor-ci-controller/src/memory.v:36$730'. created $dff cell `$procdff$2838' with positive edge clock. Creating register for signal `$paramod$be568a6683087bc1c783fd234d0a3f16819ced17\Controller.\finish_execution' using process `$paramod$be568a6683087bc1c783fd234d0a3f16819ced17\Controller.$proc$/eda/processor-ci-controller/src/controller.v:113$719'. created $dff cell `$procdff$2839' with positive edge clock. Creating register for signal `$paramod\ResetBootSystem\CYCLES=s32'00000000000000000000000000010100.\reset_o' using process `$paramod\ResetBootSystem\CYCLES=s32'00000000000000000000000000010100.$proc$/eda/processor-ci-controller/src/reset.v:25$669'. created $dff cell `$procdff$2840' with positive edge clock. Creating register for signal `$paramod\ResetBootSystem\CYCLES=s32'00000000000000000000000000010100.\state' using process `$paramod\ResetBootSystem\CYCLES=s32'00000000000000000000000000010100.$proc$/eda/processor-ci-controller/src/reset.v:25$669'. created $dff cell `$procdff$2841' with positive edge clock. Creating register for signal `$paramod\ResetBootSystem\CYCLES=s32'00000000000000000000000000010100.\counter' using process `$paramod\ResetBootSystem\CYCLES=s32'00000000000000000000000000010100.$proc$/eda/processor-ci-controller/src/reset.v:25$669'. created $dff cell `$procdff$2842' with positive edge clock. Creating register for signal `\Registers.$memwr$\registers$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/src/core/registers.v:28$140_ADDR' using process `\Registers.$proc$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/src/core/registers.v:26$154'. created $dff cell `$procdff$2843' with positive edge clock. Creating register for signal `\Registers.$memwr$\registers$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/src/core/registers.v:28$140_DATA' using process `\Registers.$proc$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/src/core/registers.v:26$154'. created $dff cell `$procdff$2844' with positive edge clock. Creating register for signal `\Registers.$memwr$\registers$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/src/core/registers.v:28$140_EN' using process `\Registers.$proc$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/src/core/registers.v:26$154'. created $dff cell `$procdff$2845' with positive edge clock. Creating register for signal `\Registers.$memwr$\registers$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/src/core/registers.v:31$141_EN' using process `\Registers.$proc$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/src/core/registers.v:26$154'. created $dff cell `$procdff$2846' with positive edge clock. Creating register for signal `\Grande_Risco5.\is_immediate' using process `\Grande_Risco5.$proc$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/src/core/core.v:258$119'. created $dff cell `$procdff$2847' with positive edge clock. Creating register for signal `\Grande_Risco5.\mem_to_reg' using process `\Grande_Risco5.$proc$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/src/core/core.v:226$98'. created $dff cell `$procdff$2848' with positive edge clock. Creating register for signal `\Grande_Risco5.\reg_write' using process `\Grande_Risco5.$proc$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/src/core/core.v:226$98'. created $dff cell `$procdff$2849' with positive edge clock. Creating register for signal `\Grande_Risco5.\MEMWB_mem_read_data' using process `\Grande_Risco5.$proc$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/src/core/core.v:226$98'. created $dff cell `$procdff$2850' with positive edge clock. Creating register for signal `\Grande_Risco5.\MEMWBALUOut' using process `\Grande_Risco5.$proc$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/src/core/core.v:226$98'. created $dff cell `$procdff$2851' with positive edge clock. Creating register for signal `\Grande_Risco5.\MEMWBIR' using process `\Grande_Risco5.$proc$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/src/core/core.v:226$98'. created $dff cell `$procdff$2852' with positive edge clock. Creating register for signal `\Grande_Risco5.\memory_write' using process `\Grande_Risco5.$proc$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/src/core/core.v:190$85'. created $dff cell `$procdff$2853' with positive edge clock. Creating register for signal `\Grande_Risco5.\memory_read' using process `\Grande_Risco5.$proc$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/src/core/core.v:190$85'. created $dff cell `$procdff$2854' with positive edge clock. Creating register for signal `\Grande_Risco5.\memory_operation' using process `\Grande_Risco5.$proc$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/src/core/core.v:190$85'. created $dff cell `$procdff$2855' with positive edge clock. Creating register for signal `\Grande_Risco5.\IMMEDIATE_REG' using process `\Grande_Risco5.$proc$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/src/core/core.v:190$85'. created $dff cell `$procdff$2856' with positive edge clock. Creating register for signal `\Grande_Risco5.\EXMEM_mem_data_value' using process `\Grande_Risco5.$proc$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/src/core/core.v:190$85'. created $dff cell `$procdff$2857' with positive edge clock. Creating register for signal `\Grande_Risco5.\EXMEMALUOut' using process `\Grande_Risco5.$proc$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/src/core/core.v:190$85'. created $dff cell `$procdff$2858' with positive edge clock. Creating register for signal `\Grande_Risco5.\EXMEMIR' using process `\Grande_Risco5.$proc$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/src/core/core.v:190$85'. created $dff cell `$procdff$2859' with positive edge clock. Creating register for signal `\Grande_Risco5.\is_branch' using process `\Grande_Risco5.$proc$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/src/core/core.v:169$77'. created $dff cell `$procdff$2860' with positive edge clock. Creating register for signal `\Grande_Risco5.\IMMEDIATE_REG_BRANCH' using process `\Grande_Risco5.$proc$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/src/core/core.v:169$77'. created $dff cell `$procdff$2861' with positive edge clock. Creating register for signal `\Grande_Risco5.\BRANCH_ADDRESS' using process `\Grande_Risco5.$proc$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/src/core/core.v:169$77'. created $dff cell `$procdff$2862' with positive edge clock. Creating register for signal `\Grande_Risco5.\EXEXPC' using process `\Grande_Risco5.$proc$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/src/core/core.v:169$77'. created $dff cell `$procdff$2863' with positive edge clock. Creating register for signal `\Grande_Risco5.\EXEXIR' using process `\Grande_Risco5.$proc$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/src/core/core.v:169$77'. created $dff cell `$procdff$2864' with positive edge clock. Creating register for signal `\Grande_Risco5.\memory_write_data' using process `\Grande_Risco5.$proc$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/src/core/core.v:169$77'. created $dff cell `$procdff$2865' with positive edge clock. Creating register for signal `\Grande_Risco5.\IDEXA' using process `\Grande_Risco5.$proc$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/src/core/core.v:122$50'. created $dff cell `$procdff$2866' with positive edge clock. Creating register for signal `\Grande_Risco5.\IDEXB' using process `\Grande_Risco5.$proc$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/src/core/core.v:122$50'. created $dff cell `$procdff$2867' with positive edge clock. Creating register for signal `\Grande_Risco5.\IDEXPC' using process `\Grande_Risco5.$proc$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/src/core/core.v:122$50'. created $dff cell `$procdff$2868' with positive edge clock. Creating register for signal `\Grande_Risco5.\alu_input_a' using process `\Grande_Risco5.$proc$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/src/core/core.v:122$50'. created $dff cell `$procdff$2869' with positive edge clock. Creating register for signal `\Grande_Risco5.\alu_input_b' using process `\Grande_Risco5.$proc$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/src/core/core.v:122$50'. created $dff cell `$procdff$2870' with positive edge clock. Creating register for signal `\Grande_Risco5.\aluop_out_reg' using process `\Grande_Risco5.$proc$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/src/core/core.v:122$50'. created $dff cell `$procdff$2871' with positive edge clock. Creating register for signal `\Grande_Risco5.\IDEXIR' using process `\Grande_Risco5.$proc$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/src/core/core.v:122$50'. created $dff cell `$procdff$2872' with positive edge clock. Creating register for signal `\Grande_Risco5.\Zero_EXMEMB' using process `\Grande_Risco5.$proc$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/src/core/core.v:80$31'. created $dff cell `$procdff$2873' with positive edge clock. Creating register for signal `\Grande_Risco5.\is_jal' using process `\Grande_Risco5.$proc$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/src/core/core.v:80$31'. created $dff cell `$procdff$2874' with positive edge clock. Creating register for signal `\Grande_Risco5.\branch_flush' using process `\Grande_Risco5.$proc$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/src/core/core.v:80$31'. created $dff cell `$procdff$2875' with positive edge clock. Creating register for signal `\Grande_Risco5.\is_jalr' using process `\Grande_Risco5.$proc$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/src/core/core.v:80$31'. created $dff cell `$procdff$2876' with positive edge clock. Creating register for signal `\Grande_Risco5.\PC' using process `\Grande_Risco5.$proc$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/src/core/core.v:80$31'. created $dff cell `$procdff$2877' with positive edge clock. Creating register for signal `\Grande_Risco5.\IFIDPC' using process `\Grande_Risco5.$proc$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/src/core/core.v:80$31'. created $dff cell `$procdff$2878' with positive edge clock. Creating register for signal `\Grande_Risco5.\JAL_PC' using process `\Grande_Risco5.$proc$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/src/core/core.v:80$31'. created $dff cell `$procdff$2879' with positive edge clock. Creating register for signal `\Grande_Risco5.\JALR_PC' using process `\Grande_Risco5.$proc$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/src/core/core.v:80$31'. created $dff cell `$procdff$2880' with positive edge clock. Creating register for signal `\Grande_Risco5.\IFIDIR' using process `\Grande_Risco5.$proc$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/src/core/core.v:80$31'. created $dff cell `$procdff$2881' with positive edge clock. 18.4.10. Executing PROC_MEMWR pass (convert process memory writes to cells). 18.4.11. Executing PROC_CLEAN pass (remove empty switches from decision trees). Removing empty process `TRELLIS_FF.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$667'. Found and cleaned up 2 empty switches in `\TRELLIS_FF.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:350$666'. Removing empty process `TRELLIS_FF.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:350$666'. Removing empty process `DPR16X4C.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$641'. Found and cleaned up 1 empty switch in `\DPR16X4C.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:285$618'. Removing empty process `TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$584'. Found and cleaned up 1 empty switch in `\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$560'. Removing empty process `TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$559'. Removing empty process `$paramod$fb00a4f1e01b6404091dd91fbb53b046994f1d61\FIFO.$proc$/eda/processor-ci-controller/src/fifo.v:0$946'. Found and cleaned up 2 empty switches in `$paramod$fb00a4f1e01b6404091dd91fbb53b046994f1d61\FIFO.$proc$/eda/processor-ci-controller/src/fifo.v:36$921'. Removing empty process `$paramod$fb00a4f1e01b6404091dd91fbb53b046994f1d61\FIFO.$proc$/eda/processor-ci-controller/src/fifo.v:36$921'. Found and cleaned up 2 empty switches in `$paramod$fb00a4f1e01b6404091dd91fbb53b046994f1d61\FIFO.$proc$/eda/processor-ci-controller/src/fifo.v:25$913'. Removing empty process `$paramod$fb00a4f1e01b6404091dd91fbb53b046994f1d61\FIFO.$proc$/eda/processor-ci-controller/src/fifo.v:25$913'. Removing empty process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:131$1116'. Found and cleaned up 2 empty switches in `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:196$1114'. Removing empty process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:196$1114'. Found and cleaned up 1 empty switch in `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:185$1112'. Removing empty process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:185$1112'. Found and cleaned up 3 empty switches in `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:170$1104'. Removing empty process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:170$1104'. Found and cleaned up 2 empty switches in `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:159$1101'. Removing empty process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:159$1101'. Found and cleaned up 3 empty switches in `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:147$1095'. Removing empty process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:147$1095'. Found and cleaned up 3 empty switches in `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:132$1090'. Removing empty process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:132$1090'. Found and cleaned up 1 empty switch in `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:115$1085'. Removing empty process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:115$1085'. Found and cleaned up 2 empty switches in `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:96$1076'. Removing empty process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:96$1076'. Removing empty process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:114$1069'. Found and cleaned up 5 empty switches in `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:173$1063'. Removing empty process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:173$1063'. Found and cleaned up 1 empty switch in `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:162$1061'. Removing empty process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:162$1061'. Found and cleaned up 3 empty switches in `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:147$1053'. Removing empty process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:147$1053'. Found and cleaned up 5 empty switches in `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:130$1039'. Removing empty process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:130$1039'. Found and cleaned up 3 empty switches in `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:115$1033'. Removing empty process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:115$1033'. Found and cleaned up 1 empty switch in `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:98$1028'. Removing empty process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:98$1028'. Removing empty process `$paramod$1849aaf56e55fcd2c7df624bf67aa48a75c68e43\ClkDivider.$proc$/eda/processor-ci-controller/src/clk_divider.v:0$1021'. Found and cleaned up 4 empty switches in `$paramod$1849aaf56e55fcd2c7df624bf67aa48a75c68e43\ClkDivider.$proc$/eda/processor-ci-controller/src/clk_divider.v:57$1015'. Removing empty process `$paramod$1849aaf56e55fcd2c7df624bf67aa48a75c68e43\ClkDivider.$proc$/eda/processor-ci-controller/src/clk_divider.v:57$1015'. Found and cleaned up 4 empty switches in `$paramod$1849aaf56e55fcd2c7df624bf67aa48a75c68e43\ClkDivider.$proc$/eda/processor-ci-controller/src/clk_divider.v:36$1006'. Removing empty process `$paramod$1849aaf56e55fcd2c7df624bf67aa48a75c68e43\ClkDivider.$proc$/eda/processor-ci-controller/src/clk_divider.v:36$1006'. Removing empty process `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.$proc$/eda/processor-ci-controller/src/interpreter.v:0$999'. Found and cleaned up 15 empty switches in `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.$proc$/eda/processor-ci-controller/src/interpreter.v:116$970'. Removing empty process `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.$proc$/eda/processor-ci-controller/src/interpreter.v:116$970'. Removing empty process `$paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART.$proc$/eda/processor-ci-controller/modules/uart.v:0$969'. Found and cleaned up 3 empty switches in `$paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART.$proc$/eda/processor-ci-controller/modules/uart.v:203$962'. Removing empty process `$paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART.$proc$/eda/processor-ci-controller/modules/uart.v:203$962'. Found and cleaned up 2 empty switches in `$paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART.$proc$/eda/processor-ci-controller/modules/uart.v:187$957'. Removing empty process `$paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART.$proc$/eda/processor-ci-controller/modules/uart.v:187$957'. Found and cleaned up 5 empty switches in `$paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART.$proc$/eda/processor-ci-controller/modules/uart.v:132$952'. Removing empty process `$paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART.$proc$/eda/processor-ci-controller/modules/uart.v:132$952'. Found and cleaned up 5 empty switches in `$paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART.$proc$/eda/processor-ci-controller/modules/uart.v:74$947'. Removing empty process `$paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART.$proc$/eda/processor-ci-controller/modules/uart.v:74$947'. Removing empty process `$paramod$860abc9b363840d7b46a2d1e00ea80d20a30d2ee\Memory.$proc$/eda/processor-ci-controller/src/memory.v:45$740'. Found and cleaned up 2 empty switches in `$paramod$860abc9b363840d7b46a2d1e00ea80d20a30d2ee\Memory.$proc$/eda/processor-ci-controller/src/memory.v:36$730'. Removing empty process `$paramod$860abc9b363840d7b46a2d1e00ea80d20a30d2ee\Memory.$proc$/eda/processor-ci-controller/src/memory.v:36$730'. Found and cleaned up 4 empty switches in `$paramod$be568a6683087bc1c783fd234d0a3f16819ced17\Controller.$proc$/eda/processor-ci-controller/src/controller.v:113$719'. Removing empty process `$paramod$be568a6683087bc1c783fd234d0a3f16819ced17\Controller.$proc$/eda/processor-ci-controller/src/controller.v:113$719'. Removing empty process `$paramod\ResetBootSystem\CYCLES=s32'00000000000000000000000000010100.$proc$/eda/processor-ci-controller/src/reset.v:0$676'. Found and cleaned up 6 empty switches in `$paramod\ResetBootSystem\CYCLES=s32'00000000000000000000000000010100.$proc$/eda/processor-ci-controller/src/reset.v:25$669'. Removing empty process `$paramod\ResetBootSystem\CYCLES=s32'00000000000000000000000000010100.$proc$/eda/processor-ci-controller/src/reset.v:25$669'. Found and cleaned up 1 empty switch in `\Registers.$proc$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/src/core/registers.v:26$154'. Removing empty process `Registers.$proc$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/src/core/registers.v:26$154'. Found and cleaned up 1 empty switch in `\MUX.$proc$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/src/core/mux.v:10$139'. Removing empty process `MUX.$proc$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/src/core/mux.v:10$139'. Found and cleaned up 2 empty switches in `\Immediate_Generator.$proc$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/src/core/immediate_generator.v:18$138'. Removing empty process `Immediate_Generator.$proc$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/src/core/immediate_generator.v:18$138'. Found and cleaned up 6 empty switches in `\Forwarding_Unit.$proc$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/src/core/forwarding_unit.v:13$123'. Removing empty process `Forwarding_Unit.$proc$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/src/core/forwarding_unit.v:13$123'. Found and cleaned up 1 empty switch in `\Grande_Risco5.$proc$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/src/core/core.v:270$120'. Removing empty process `Grande_Risco5.$proc$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/src/core/core.v:270$120'. Found and cleaned up 1 empty switch in `\Grande_Risco5.$proc$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/src/core/core.v:258$119'. Removing empty process `Grande_Risco5.$proc$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/src/core/core.v:258$119'. Found and cleaned up 3 empty switches in `\Grande_Risco5.$proc$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/src/core/core.v:226$98'. Removing empty process `Grande_Risco5.$proc$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/src/core/core.v:226$98'. Found and cleaned up 7 empty switches in `\Grande_Risco5.$proc$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/src/core/core.v:190$85'. Removing empty process `Grande_Risco5.$proc$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/src/core/core.v:190$85'. Found and cleaned up 3 empty switches in `\Grande_Risco5.$proc$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/src/core/core.v:169$77'. Removing empty process `Grande_Risco5.$proc$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/src/core/core.v:169$77'. Found and cleaned up 5 empty switches in `\Grande_Risco5.$proc$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/src/core/core.v:122$50'. Removing empty process `Grande_Risco5.$proc$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/src/core/core.v:122$50'. Found and cleaned up 6 empty switches in `\Grande_Risco5.$proc$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/src/core/core.v:80$31'. Removing empty process `Grande_Risco5.$proc$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/src/core/core.v:80$31'. Found and cleaned up 5 empty switches in `\ALU_Control.$proc$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/src/core/alu_control.v:9$25'. Removing empty process `ALU_Control.$proc$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/src/core/alu_control.v:9$25'. Found and cleaned up 1 empty switch in `\Alu.$proc$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/src/core/alu.v:26$5'. Removing empty process `Alu.$proc$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/src/core/alu.v:26$5'. Cleaned up 135 empty switches. 18.4.12. Executing OPT_EXPR pass (perform const folding). Optimizing module $paramod$fb00a4f1e01b6404091dd91fbb53b046994f1d61\FIFO. <suppressed ~5 debug messages> Optimizing module $paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx. <suppressed ~21 debug messages> Optimizing module $paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tx. <suppressed ~19 debug messages> Optimizing module $paramod$1849aaf56e55fcd2c7df624bf67aa48a75c68e43\ClkDivider. <suppressed ~9 debug messages> Optimizing module $paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter. <suppressed ~15 debug messages> Optimizing module $paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART. <suppressed ~24 debug messages> Optimizing module $paramod$860abc9b363840d7b46a2d1e00ea80d20a30d2ee\Memory. <suppressed ~3 debug messages> Optimizing module $paramod$be568a6683087bc1c783fd234d0a3f16819ced17\Controller. <suppressed ~26 debug messages> Optimizing module $paramod\ResetBootSystem\CYCLES=s32'00000000000000000000000000010100. <suppressed ~8 debug messages> Optimizing module Registers. Optimizing module MUX. <suppressed ~1 debug messages> Optimizing module Immediate_Generator. Optimizing module Forwarding_Unit. Optimizing module Grande_Risco5. <suppressed ~8 debug messages> Optimizing module ALU_Control. <suppressed ~4 debug messages> Optimizing module Alu. <suppressed ~1 debug messages> Optimizing module processorci_top. 18.5. Executing FLATTEN pass (flatten design). Deleting now unused module $paramod$fb00a4f1e01b6404091dd91fbb53b046994f1d61\FIFO. Deleting now unused module $paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx. Deleting now unused module $paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tx. Deleting now unused module $paramod$1849aaf56e55fcd2c7df624bf67aa48a75c68e43\ClkDivider. Deleting now unused module $paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter. Deleting now unused module $paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART. Deleting now unused module $paramod$860abc9b363840d7b46a2d1e00ea80d20a30d2ee\Memory. Deleting now unused module $paramod$be568a6683087bc1c783fd234d0a3f16819ced17\Controller. Deleting now unused module $paramod\ResetBootSystem\CYCLES=s32'00000000000000000000000000010100. Deleting now unused module Registers. Deleting now unused module MUX. Deleting now unused module Immediate_Generator. Deleting now unused module Forwarding_Unit. Deleting now unused module Grande_Risco5. Deleting now unused module ALU_Control. Deleting now unused module Alu. <suppressed ~19 debug messages> 18.6. Executing TRIBUF pass. 18.7. Executing DEMINOUT pass (demote inout ports to input or output). 18.8. Executing OPT_EXPR pass (perform const folding). Optimizing module processorci_top. <suppressed ~49 debug messages> 18.9. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \processorci_top.. Removed 81 unused cells and 749 unused wires. <suppressed ~108 debug messages> 18.10. Executing CHECK pass (checking for obvious problems). Checking module processorci_top... Warning: Wire processorci_top.\miso is used but has no driver. Warning: Wire processorci_top.\intr is used but has no driver. Warning: Wire processorci_top.\ResetBootSystem.start is used but has no driver. Warning: Wire processorci_top.\Core.ForwardBMUX.D [31] is used but has no driver. Warning: Wire processorci_top.\Core.ForwardBMUX.D [30] is used but has no driver. Warning: Wire processorci_top.\Core.ForwardBMUX.D [29] is used but has no driver. Warning: Wire processorci_top.\Core.ForwardBMUX.D [28] is used but has no driver. Warning: Wire processorci_top.\Core.ForwardBMUX.D [27] is used but has no driver. Warning: Wire processorci_top.\Core.ForwardBMUX.D [26] is used but has no driver. Warning: Wire processorci_top.\Core.ForwardBMUX.D [25] is used but has no driver. Warning: Wire processorci_top.\Core.ForwardBMUX.D [24] is used but has no driver. Warning: Wire processorci_top.\Core.ForwardBMUX.D [23] is used but has no driver. Warning: Wire processorci_top.\Core.ForwardBMUX.D [22] is used but has no driver. Warning: Wire processorci_top.\Core.ForwardBMUX.D [21] is used but has no driver. Warning: Wire processorci_top.\Core.ForwardBMUX.D [20] is used but has no driver. Warning: Wire processorci_top.\Core.ForwardBMUX.D [19] is used but has no driver. Warning: Wire processorci_top.\Core.ForwardBMUX.D [18] is used but has no driver. Warning: Wire processorci_top.\Core.ForwardBMUX.D [17] is used but has no driver. Warning: Wire processorci_top.\Core.ForwardBMUX.D [16] is used but has no driver. Warning: Wire processorci_top.\Core.ForwardBMUX.D [15] is used but has no driver. Warning: Wire processorci_top.\Core.ForwardBMUX.D [14] is used but has no driver. Warning: Wire processorci_top.\Core.ForwardBMUX.D [13] is used but has no driver. Warning: Wire processorci_top.\Core.ForwardBMUX.D [12] is used but has no driver. Warning: Wire processorci_top.\Core.ForwardBMUX.D [11] is used but has no driver. Warning: Wire processorci_top.\Core.ForwardBMUX.D [10] is used but has no driver. Warning: Wire processorci_top.\Core.ForwardBMUX.D [9] is used but has no driver. Warning: Wire processorci_top.\Core.ForwardBMUX.D [8] is used but has no driver. Warning: Wire processorci_top.\Core.ForwardBMUX.D [7] is used but has no driver. Warning: Wire processorci_top.\Core.ForwardBMUX.D [6] is used but has no driver. Warning: Wire processorci_top.\Core.ForwardBMUX.D [5] is used but has no driver. Warning: Wire processorci_top.\Core.ForwardBMUX.D [4] is used but has no driver. Warning: Wire processorci_top.\Core.ForwardBMUX.D [3] is used but has no driver. Warning: Wire processorci_top.\Core.ForwardBMUX.D [2] is used but has no driver. Warning: Wire processorci_top.\Core.ForwardBMUX.D [1] is used but has no driver. Warning: Wire processorci_top.\Core.ForwardBMUX.D [0] is used but has no driver. Warning: Wire processorci_top.\Core.ForwardAMUX.D [31] is used but has no driver. Warning: Wire processorci_top.\Core.ForwardAMUX.D [30] is used but has no driver. Warning: Wire processorci_top.\Core.ForwardAMUX.D [29] is used but has no driver. Warning: Wire processorci_top.\Core.ForwardAMUX.D [28] is used but has no driver. Warning: Wire processorci_top.\Core.ForwardAMUX.D [27] is used but has no driver. Warning: Wire processorci_top.\Core.ForwardAMUX.D [26] is used but has no driver. Warning: Wire processorci_top.\Core.ForwardAMUX.D [25] is used but has no driver. Warning: Wire processorci_top.\Core.ForwardAMUX.D [24] is used but has no driver. Warning: Wire processorci_top.\Core.ForwardAMUX.D [23] is used but has no driver. Warning: Wire processorci_top.\Core.ForwardAMUX.D [22] is used but has no driver. Warning: Wire processorci_top.\Core.ForwardAMUX.D [21] is used but has no driver. Warning: Wire processorci_top.\Core.ForwardAMUX.D [20] is used but has no driver. Warning: Wire processorci_top.\Core.ForwardAMUX.D [19] is used but has no driver. Warning: Wire processorci_top.\Core.ForwardAMUX.D [18] is used but has no driver. Warning: Wire processorci_top.\Core.ForwardAMUX.D [17] is used but has no driver. Warning: Wire processorci_top.\Core.ForwardAMUX.D [16] is used but has no driver. Warning: Wire processorci_top.\Core.ForwardAMUX.D [15] is used but has no driver. Warning: Wire processorci_top.\Core.ForwardAMUX.D [14] is used but has no driver. Warning: Wire processorci_top.\Core.ForwardAMUX.D [13] is used but has no driver. Warning: Wire processorci_top.\Core.ForwardAMUX.D [12] is used but has no driver. Warning: Wire processorci_top.\Core.ForwardAMUX.D [11] is used but has no driver. Warning: Wire processorci_top.\Core.ForwardAMUX.D [10] is used but has no driver. Warning: Wire processorci_top.\Core.ForwardAMUX.D [9] is used but has no driver. Warning: Wire processorci_top.\Core.ForwardAMUX.D [8] is used but has no driver. Warning: Wire processorci_top.\Core.ForwardAMUX.D [7] is used but has no driver. Warning: Wire processorci_top.\Core.ForwardAMUX.D [6] is used but has no driver. Warning: Wire processorci_top.\Core.ForwardAMUX.D [5] is used but has no driver. Warning: Wire processorci_top.\Core.ForwardAMUX.D [4] is used but has no driver. Warning: Wire processorci_top.\Core.ForwardAMUX.D [3] is used but has no driver. Warning: Wire processorci_top.\Core.ForwardAMUX.D [2] is used but has no driver. Warning: Wire processorci_top.\Core.ForwardAMUX.D [1] is used but has no driver. Warning: Wire processorci_top.\Core.ForwardAMUX.D [0] is used but has no driver. Found and reported 67 problems. 18.11. Executing OPT pass (performing simple optimizations). 18.11.1. Executing OPT_EXPR pass (perform const folding). Optimizing module processorci_top. 18.11.2. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\processorci_top'. <suppressed ~591 debug messages> Removed a total of 197 cells. 18.11.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees). Running muxtree optimizer on module \processorci_top.. Creating internal representation of mux trees. Evaluating internal representation of mux trees. Analyzing evaluation results. dead port 1/2 on $mux $flatten\Controller.\Uart.\RX_FIFO.$procmux$1144. dead port 1/2 on $mux $flatten\Controller.\Uart.\RX_FIFO.$procmux$1150. dead port 1/2 on $mux $flatten\Controller.\Uart.\RX_FIFO.$procmux$1156. dead port 1/2 on $mux $flatten\Controller.\Uart.\TX_FIFO.$procmux$1144. dead port 1/2 on $mux $flatten\Controller.\Uart.\TX_FIFO.$procmux$1150. dead port 1/2 on $mux $flatten\Controller.\Uart.\TX_FIFO.$procmux$1156. dead port 1/2 on $mux $flatten\Core.\Forwarding_Unit.$procmux$2490. dead port 2/2 on $mux $flatten\Core.\Forwarding_Unit.$procmux$2496. dead port 1/2 on $mux $flatten\Core.\Forwarding_Unit.$procmux$2505. dead port 2/2 on $mux $flatten\Core.\Forwarding_Unit.$procmux$2511. dead port 2/2 on $mux $flatten\Core.\Immediate_Generator.$procmux$2473. Removed 11 multiplexer ports. <suppressed ~149 debug messages> 18.11.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). Optimizing cells in module \processorci_top. New ctrl vector for $pmux cell $flatten\Controller.\Interpreter.$procmux$1874: $auto$opt_reduce.cc:134:opt_pmux$2906 New ctrl vector for $pmux cell $flatten\Controller.\Interpreter.$procmux$1899: { $flatten\Controller.\Interpreter.$procmux$1520_CMP $auto$opt_reduce.cc:134:opt_pmux$2908 $flatten\Controller.\Interpreter.$procmux$1510_CMP } Consolidated identical input bits for $mux cell $flatten\Controller.\Data_Memory.$procmux$2390: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Controller.\Data_Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$725_EN[31:0]$733 New ports: A=1'0, B=1'1, Y=$flatten\Controller.\Data_Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$725_EN[31:0]$733 [0] New connections: $flatten\Controller.\Data_Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$725_EN[31:0]$733 [31:1] = { $flatten\Controller.\Data_Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$725_EN[31:0]$733 [0] $flatten\Controller.\Data_Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$725_EN[31:0]$733 [0] $flatten\Controller.\Data_Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$725_EN[31:0]$733 [0] $flatten\Controller.\Data_Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$725_EN[31:0]$733 [0] $flatten\Controller.\Data_Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$725_EN[31:0]$733 [0] $flatten\Controller.\Data_Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$725_EN[31:0]$733 [0] $flatten\Controller.\Data_Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$725_EN[31:0]$733 [0] $flatten\Controller.\Data_Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$725_EN[31:0]$733 [0] $flatten\Controller.\Data_Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$725_EN[31:0]$733 [0] $flatten\Controller.\Data_Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$725_EN[31:0]$733 [0] $flatten\Controller.\Data_Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$725_EN[31:0]$733 [0] $flatten\Controller.\Data_Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$725_EN[31:0]$733 [0] $flatten\Controller.\Data_Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$725_EN[31:0]$733 [0] $flatten\Controller.\Data_Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$725_EN[31:0]$733 [0] $flatten\Controller.\Data_Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$725_EN[31:0]$733 [0] $flatten\Controller.\Data_Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$725_EN[31:0]$733 [0] $flatten\Controller.\Data_Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$725_EN[31:0]$733 [0] $flatten\Controller.\Data_Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$725_EN[31:0]$733 [0] $flatten\Controller.\Data_Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$725_EN[31:0]$733 [0] $flatten\Controller.\Data_Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$725_EN[31:0]$733 [0] $flatten\Controller.\Data_Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$725_EN[31:0]$733 [0] $flatten\Controller.\Data_Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$725_EN[31:0]$733 [0] $flatten\Controller.\Data_Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$725_EN[31:0]$733 [0] $flatten\Controller.\Data_Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$725_EN[31:0]$733 [0] $flatten\Controller.\Data_Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$725_EN[31:0]$733 [0] $flatten\Controller.\Data_Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$725_EN[31:0]$733 [0] $flatten\Controller.\Data_Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$725_EN[31:0]$733 [0] $flatten\Controller.\Data_Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$725_EN[31:0]$733 [0] $flatten\Controller.\Data_Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$725_EN[31:0]$733 [0] $flatten\Controller.\Data_Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$725_EN[31:0]$733 [0] $flatten\Controller.\Data_Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$725_EN[31:0]$733 [0] } New ctrl vector for $pmux cell $flatten\Controller.\Interpreter.$procmux$1927: { $flatten\Controller.\Interpreter.$procmux$1506_CMP $flatten\Controller.\Interpreter.$procmux$1499_CMP $flatten\Controller.\Interpreter.$procmux$1488_CMP $flatten\Controller.\Interpreter.$procmux$1482_CMP $auto$opt_reduce.cc:134:opt_pmux$2910 } New ctrl vector for $pmux cell $flatten\Controller.\Interpreter.$procmux$1959: { $auto$opt_reduce.cc:134:opt_pmux$2914 $auto$opt_reduce.cc:134:opt_pmux$2912 } New ctrl vector for $pmux cell $flatten\Controller.\Interpreter.$procmux$2041: { $flatten\Controller.\Interpreter.$procmux$1500_CMP $auto$opt_reduce.cc:134:opt_pmux$2916 } New ctrl vector for $pmux cell $flatten\Controller.\Interpreter.$procmux$2052: { $flatten\Controller.\Interpreter.$procmux$1641_CMP $flatten\Controller.\Interpreter.$procmux$1540_CMP $auto$opt_reduce.cc:134:opt_pmux$2918 } New ctrl vector for $pmux cell $flatten\Controller.\Interpreter.$procmux$2062: { $flatten\Controller.\Interpreter.$procmux$1539_CMP $auto$opt_reduce.cc:134:opt_pmux$2922 $auto$opt_reduce.cc:134:opt_pmux$2920 } New ctrl vector for $pmux cell $flatten\Controller.\Interpreter.$procmux$2116: { $auto$opt_reduce.cc:134:opt_pmux$2924 $flatten\Controller.\Interpreter.$procmux$1606_CMP $flatten\Controller.\Interpreter.$procmux$1525_CMP $flatten\Controller.\Interpreter.$procmux$1520_CMP $flatten\Controller.\Interpreter.$procmux$1510_CMP } New ctrl vector for $pmux cell $flatten\Controller.\Interpreter.$procmux$1480: { $flatten\Controller.\Interpreter.$procmux$1574_CMP $flatten\Controller.\Interpreter.$procmux$1570_CMP $flatten\Controller.\Interpreter.$procmux$1566_CMP $flatten\Controller.\Interpreter.$procmux$1540_CMP $flatten\Controller.\Interpreter.$procmux$1539_CMP $flatten\Controller.\Interpreter.$procmux$1535_CMP $flatten\Controller.\Interpreter.$procmux$1534_CMP $flatten\Controller.\Interpreter.$procmux$1530_CMP $flatten\Controller.\Interpreter.$procmux$1520_CMP $flatten\Controller.\Interpreter.$procmux$1516_CMP $auto$opt_reduce.cc:134:opt_pmux$2932 $flatten\Controller.\Interpreter.$procmux$1511_CMP $flatten\Controller.\Interpreter.$procmux$1510_CMP $auto$opt_reduce.cc:134:opt_pmux$2930 $flatten\Controller.\Interpreter.$procmux$1505_CMP $flatten\Controller.\Interpreter.$procmux$1504_CMP $flatten\Controller.\Interpreter.$procmux$1499_CMP $flatten\Controller.\Interpreter.$procmux$1495_CMP $flatten\Controller.\Interpreter.$procmux$1494_CMP $auto$opt_reduce.cc:134:opt_pmux$2928 $flatten\Controller.\Interpreter.$procmux$1488_CMP $flatten\Controller.\Interpreter.$procmux$1487_CMP $flatten\Controller.\Interpreter.$procmux$1486_CMP $auto$opt_reduce.cc:134:opt_pmux$2926 } New ctrl vector for $pmux cell $flatten\Controller.\Interpreter.$procmux$2170: { $auto$opt_reduce.cc:134:opt_pmux$2934 $flatten\Controller.\Interpreter.$procmux$1539_CMP } New ctrl vector for $pmux cell $flatten\Controller.\Interpreter.$procmux$2194: { $flatten\Controller.\Interpreter.$procmux$1607_CMP $flatten\Controller.\Interpreter.$procmux$1606_CMP $auto$opt_reduce.cc:134:opt_pmux$2936 } Consolidated identical input bits for $mux cell $flatten\Controller.\Memory.$procmux$2390: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Controller.\Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$725_EN[31:0]$733 New ports: A=1'0, B=1'1, Y=$flatten\Controller.\Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$725_EN[31:0]$733 [0] New connections: $flatten\Controller.\Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$725_EN[31:0]$733 [31:1] = { $flatten\Controller.\Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$725_EN[31:0]$733 [0] $flatten\Controller.\Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$725_EN[31:0]$733 [0] $flatten\Controller.\Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$725_EN[31:0]$733 [0] $flatten\Controller.\Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$725_EN[31:0]$733 [0] $flatten\Controller.\Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$725_EN[31:0]$733 [0] $flatten\Controller.\Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$725_EN[31:0]$733 [0] $flatten\Controller.\Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$725_EN[31:0]$733 [0] $flatten\Controller.\Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$725_EN[31:0]$733 [0] $flatten\Controller.\Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$725_EN[31:0]$733 [0] $flatten\Controller.\Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$725_EN[31:0]$733 [0] $flatten\Controller.\Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$725_EN[31:0]$733 [0] $flatten\Controller.\Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$725_EN[31:0]$733 [0] $flatten\Controller.\Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$725_EN[31:0]$733 [0] $flatten\Controller.\Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$725_EN[31:0]$733 [0] $flatten\Controller.\Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$725_EN[31:0]$733 [0] $flatten\Controller.\Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$725_EN[31:0]$733 [0] $flatten\Controller.\Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$725_EN[31:0]$733 [0] $flatten\Controller.\Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$725_EN[31:0]$733 [0] $flatten\Controller.\Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$725_EN[31:0]$733 [0] $flatten\Controller.\Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$725_EN[31:0]$733 [0] $flatten\Controller.\Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$725_EN[31:0]$733 [0] $flatten\Controller.\Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$725_EN[31:0]$733 [0] $flatten\Controller.\Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$725_EN[31:0]$733 [0] $flatten\Controller.\Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$725_EN[31:0]$733 [0] $flatten\Controller.\Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$725_EN[31:0]$733 [0] $flatten\Controller.\Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$725_EN[31:0]$733 [0] $flatten\Controller.\Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$725_EN[31:0]$733 [0] $flatten\Controller.\Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$725_EN[31:0]$733 [0] $flatten\Controller.\Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$725_EN[31:0]$733 [0] $flatten\Controller.\Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$725_EN[31:0]$733 [0] $flatten\Controller.\Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$725_EN[31:0]$733 [0] } New ctrl vector for $pmux cell $flatten\Controller.\Uart.$procmux$2258: $auto$opt_reduce.cc:134:opt_pmux$2938 New ctrl vector for $pmux cell $flatten\Controller.\Uart.$procmux$2322: $auto$opt_reduce.cc:134:opt_pmux$2940 Consolidated identical input bits for $mux cell $flatten\Controller.\Uart.\RX_FIFO.$procmux$1141: Old ports: A=8'00000000, B=8'11111111, Y=$flatten\Controller.\Uart.\RX_FIFO.$procmux$1141_Y New ports: A=1'0, B=1'1, Y=$flatten\Controller.\Uart.\RX_FIFO.$procmux$1141_Y [0] New connections: $flatten\Controller.\Uart.\RX_FIFO.$procmux$1141_Y [7:1] = { $flatten\Controller.\Uart.\RX_FIFO.$procmux$1141_Y [0] $flatten\Controller.\Uart.\RX_FIFO.$procmux$1141_Y [0] $flatten\Controller.\Uart.\RX_FIFO.$procmux$1141_Y [0] $flatten\Controller.\Uart.\RX_FIFO.$procmux$1141_Y [0] $flatten\Controller.\Uart.\RX_FIFO.$procmux$1141_Y [0] $flatten\Controller.\Uart.\RX_FIFO.$procmux$1141_Y [0] $flatten\Controller.\Uart.\RX_FIFO.$procmux$1141_Y [0] } Consolidated identical input bits for $mux cell $flatten\Controller.\Uart.\TX_FIFO.$procmux$1141: Old ports: A=8'00000000, B=8'11111111, Y=$flatten\Controller.\Uart.\TX_FIFO.$procmux$1141_Y New ports: A=1'0, B=1'1, Y=$flatten\Controller.\Uart.\TX_FIFO.$procmux$1141_Y [0] New connections: $flatten\Controller.\Uart.\TX_FIFO.$procmux$1141_Y [7:1] = { $flatten\Controller.\Uart.\TX_FIFO.$procmux$1141_Y [0] $flatten\Controller.\Uart.\TX_FIFO.$procmux$1141_Y [0] $flatten\Controller.\Uart.\TX_FIFO.$procmux$1141_Y [0] $flatten\Controller.\Uart.\TX_FIFO.$procmux$1141_Y [0] $flatten\Controller.\Uart.\TX_FIFO.$procmux$1141_Y [0] $flatten\Controller.\Uart.\TX_FIFO.$procmux$1141_Y [0] $flatten\Controller.\Uart.\TX_FIFO.$procmux$1141_Y [0] } New ctrl vector for $pmux cell $flatten\Controller.\Interpreter.$procmux$1752: { $flatten\Controller.\Interpreter.$procmux$1520_CMP $auto$opt_reduce.cc:134:opt_pmux$2942 $flatten\Controller.\Interpreter.$procmux$1510_CMP } New ctrl vector for $pmux cell $flatten\Controller.\Interpreter.$procmux$1580: $auto$opt_reduce.cc:134:opt_pmux$2944 New ctrl vector for $pmux cell $flatten\Core.$procmux$2517: { $flatten\Core.$procmux$2522_CMP $auto$opt_reduce.cc:134:opt_pmux$2946 } New ctrl vector for $pmux cell $flatten\Core.$procmux$2524: $auto$opt_reduce.cc:134:opt_pmux$2948 New ctrl vector for $pmux cell $flatten\Core.$procmux$2629: { $auto$opt_reduce.cc:134:opt_pmux$2952 $auto$opt_reduce.cc:134:opt_pmux$2950 } New ctrl vector for $pmux cell $flatten\Controller.\Interpreter.$procmux$1604: $auto$opt_reduce.cc:134:opt_pmux$2954 New ctrl vector for $pmux cell $flatten\Core.$procmux$2640: { $auto$opt_reduce.cc:134:opt_pmux$2956 $flatten\Core.$procmux$2525_CMP } New ctrl vector for $pmux cell $flatten\Controller.\Interpreter.$procmux$1626: $auto$opt_reduce.cc:134:opt_pmux$2958 New ctrl vector for $pmux cell $flatten\Controller.\Interpreter.$procmux$1637: $auto$opt_reduce.cc:134:opt_pmux$2960 New ctrl vector for $pmux cell $flatten\Controller.\Interpreter.$procmux$1685: $auto$opt_reduce.cc:134:opt_pmux$2962 New ctrl vector for $pmux cell $flatten\Controller.\Interpreter.$procmux$1805: { $auto$opt_reduce.cc:134:opt_pmux$2966 $auto$opt_reduce.cc:134:opt_pmux$2964 } New ctrl vector for $pmux cell $flatten\Core.\Immediate_Generator.$procmux$2476: { $flatten\Core.\Immediate_Generator.$procmux$2485_CMP $flatten\Core.$eq$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/src/core/core.v:82$32_Y $auto$opt_reduce.cc:134:opt_pmux$2970 $flatten\Core.\Immediate_Generator.$procmux$2474_CMP $auto$opt_reduce.cc:134:opt_pmux$2968 $flatten\Core.\Immediate_Generator.$procmux$2478_CMP $flatten\Core.\Immediate_Generator.$procmux$2477_CMP } Consolidated identical input bits for $mux cell $flatten\Core.\RegisterBank.$procmux$2451: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\RegisterBank.$0$memwr$\registers$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/src/core/registers.v:28$140_EN[31:0]$157 New ports: A=1'0, B=1'1, Y=$flatten\Core.\RegisterBank.$0$memwr$\registers$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/src/core/registers.v:28$140_EN[31:0]$157 [0] New connections: $flatten\Core.\RegisterBank.$0$memwr$\registers$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/src/core/registers.v:28$140_EN[31:0]$157 [31:1] = { $flatten\Core.\RegisterBank.$0$memwr$\registers$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/src/core/registers.v:28$140_EN[31:0]$157 [0] $flatten\Core.\RegisterBank.$0$memwr$\registers$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/src/core/registers.v:28$140_EN[31:0]$157 [0] $flatten\Core.\RegisterBank.$0$memwr$\registers$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/src/core/registers.v:28$140_EN[31:0]$157 [0] $flatten\Core.\RegisterBank.$0$memwr$\registers$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/src/core/registers.v:28$140_EN[31:0]$157 [0] $flatten\Core.\RegisterBank.$0$memwr$\registers$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/src/core/registers.v:28$140_EN[31:0]$157 [0] $flatten\Core.\RegisterBank.$0$memwr$\registers$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/src/core/registers.v:28$140_EN[31:0]$157 [0] $flatten\Core.\RegisterBank.$0$memwr$\registers$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/src/core/registers.v:28$140_EN[31:0]$157 [0] $flatten\Core.\RegisterBank.$0$memwr$\registers$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/src/core/registers.v:28$140_EN[31:0]$157 [0] $flatten\Core.\RegisterBank.$0$memwr$\registers$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/src/core/registers.v:28$140_EN[31:0]$157 [0] $flatten\Core.\RegisterBank.$0$memwr$\registers$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/src/core/registers.v:28$140_EN[31:0]$157 [0] $flatten\Core.\RegisterBank.$0$memwr$\registers$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/src/core/registers.v:28$140_EN[31:0]$157 [0] $flatten\Core.\RegisterBank.$0$memwr$\registers$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/src/core/registers.v:28$140_EN[31:0]$157 [0] $flatten\Core.\RegisterBank.$0$memwr$\registers$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/src/core/registers.v:28$140_EN[31:0]$157 [0] $flatten\Core.\RegisterBank.$0$memwr$\registers$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/src/core/registers.v:28$140_EN[31:0]$157 [0] $flatten\Core.\RegisterBank.$0$memwr$\registers$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/src/core/registers.v:28$140_EN[31:0]$157 [0] $flatten\Core.\RegisterBank.$0$memwr$\registers$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/src/core/registers.v:28$140_EN[31:0]$157 [0] $flatten\Core.\RegisterBank.$0$memwr$\registers$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/src/core/registers.v:28$140_EN[31:0]$157 [0] $flatten\Core.\RegisterBank.$0$memwr$\registers$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/src/core/registers.v:28$140_EN[31:0]$157 [0] $flatten\Core.\RegisterBank.$0$memwr$\registers$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/src/core/registers.v:28$140_EN[31:0]$157 [0] $flatten\Core.\RegisterBank.$0$memwr$\registers$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/src/core/registers.v:28$140_EN[31:0]$157 [0] $flatten\Core.\RegisterBank.$0$memwr$\registers$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/src/core/registers.v:28$140_EN[31:0]$157 [0] $flatten\Core.\RegisterBank.$0$memwr$\registers$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/src/core/registers.v:28$140_EN[31:0]$157 [0] $flatten\Core.\RegisterBank.$0$memwr$\registers$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/src/core/registers.v:28$140_EN[31:0]$157 [0] $flatten\Core.\RegisterBank.$0$memwr$\registers$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/src/core/registers.v:28$140_EN[31:0]$157 [0] $flatten\Core.\RegisterBank.$0$memwr$\registers$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/src/core/registers.v:28$140_EN[31:0]$157 [0] $flatten\Core.\RegisterBank.$0$memwr$\registers$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/src/core/registers.v:28$140_EN[31:0]$157 [0] $flatten\Core.\RegisterBank.$0$memwr$\registers$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/src/core/registers.v:28$140_EN[31:0]$157 [0] $flatten\Core.\RegisterBank.$0$memwr$\registers$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/src/core/registers.v:28$140_EN[31:0]$157 [0] $flatten\Core.\RegisterBank.$0$memwr$\registers$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/src/core/registers.v:28$140_EN[31:0]$157 [0] $flatten\Core.\RegisterBank.$0$memwr$\registers$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/src/core/registers.v:28$140_EN[31:0]$157 [0] $flatten\Core.\RegisterBank.$0$memwr$\registers$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/src/core/registers.v:28$140_EN[31:0]$157 [0] } New ctrl vector for $pmux cell $flatten\Controller.\Interpreter.$procmux$1727: $auto$opt_reduce.cc:134:opt_pmux$2972 Optimizing cells in module \processorci_top. Consolidated identical input bits for $mux cell $flatten\Controller.\Uart.\RX_FIFO.$procmux$1159: Old ports: A=$flatten\Controller.\Uart.\RX_FIFO.$2$memwr$\memory$/eda/processor-ci-controller/src/fifo.v:41$912_EN[7:0]$933, B=8'00000000, Y=$flatten\Controller.\Uart.\RX_FIFO.$0$memwr$\memory$/eda/processor-ci-controller/src/fifo.v:41$912_EN[7:0]$924 New ports: A=$flatten\Controller.\Uart.\RX_FIFO.$procmux$1141_Y [0], B=1'0, Y=$flatten\Controller.\Uart.\RX_FIFO.$0$memwr$\memory$/eda/processor-ci-controller/src/fifo.v:41$912_EN[7:0]$924 [0] New connections: $flatten\Controller.\Uart.\RX_FIFO.$0$memwr$\memory$/eda/processor-ci-controller/src/fifo.v:41$912_EN[7:0]$924 [7:1] = { $flatten\Controller.\Uart.\RX_FIFO.$0$memwr$\memory$/eda/processor-ci-controller/src/fifo.v:41$912_EN[7:0]$924 [0] $flatten\Controller.\Uart.\RX_FIFO.$0$memwr$\memory$/eda/processor-ci-controller/src/fifo.v:41$912_EN[7:0]$924 [0] $flatten\Controller.\Uart.\RX_FIFO.$0$memwr$\memory$/eda/processor-ci-controller/src/fifo.v:41$912_EN[7:0]$924 [0] $flatten\Controller.\Uart.\RX_FIFO.$0$memwr$\memory$/eda/processor-ci-controller/src/fifo.v:41$912_EN[7:0]$924 [0] $flatten\Controller.\Uart.\RX_FIFO.$0$memwr$\memory$/eda/processor-ci-controller/src/fifo.v:41$912_EN[7:0]$924 [0] $flatten\Controller.\Uart.\RX_FIFO.$0$memwr$\memory$/eda/processor-ci-controller/src/fifo.v:41$912_EN[7:0]$924 [0] $flatten\Controller.\Uart.\RX_FIFO.$0$memwr$\memory$/eda/processor-ci-controller/src/fifo.v:41$912_EN[7:0]$924 [0] } Consolidated identical input bits for $mux cell $flatten\Controller.\Uart.\TX_FIFO.$procmux$1159: Old ports: A=$flatten\Controller.\Uart.\TX_FIFO.$2$memwr$\memory$/eda/processor-ci-controller/src/fifo.v:41$912_EN[7:0]$933, B=8'00000000, Y=$flatten\Controller.\Uart.\TX_FIFO.$0$memwr$\memory$/eda/processor-ci-controller/src/fifo.v:41$912_EN[7:0]$924 New ports: A=$flatten\Controller.\Uart.\TX_FIFO.$procmux$1141_Y [0], B=1'0, Y=$flatten\Controller.\Uart.\TX_FIFO.$0$memwr$\memory$/eda/processor-ci-controller/src/fifo.v:41$912_EN[7:0]$924 [0] New connections: $flatten\Controller.\Uart.\TX_FIFO.$0$memwr$\memory$/eda/processor-ci-controller/src/fifo.v:41$912_EN[7:0]$924 [7:1] = { $flatten\Controller.\Uart.\TX_FIFO.$0$memwr$\memory$/eda/processor-ci-controller/src/fifo.v:41$912_EN[7:0]$924 [0] $flatten\Controller.\Uart.\TX_FIFO.$0$memwr$\memory$/eda/processor-ci-controller/src/fifo.v:41$912_EN[7:0]$924 [0] $flatten\Controller.\Uart.\TX_FIFO.$0$memwr$\memory$/eda/processor-ci-controller/src/fifo.v:41$912_EN[7:0]$924 [0] $flatten\Controller.\Uart.\TX_FIFO.$0$memwr$\memory$/eda/processor-ci-controller/src/fifo.v:41$912_EN[7:0]$924 [0] $flatten\Controller.\Uart.\TX_FIFO.$0$memwr$\memory$/eda/processor-ci-controller/src/fifo.v:41$912_EN[7:0]$924 [0] $flatten\Controller.\Uart.\TX_FIFO.$0$memwr$\memory$/eda/processor-ci-controller/src/fifo.v:41$912_EN[7:0]$924 [0] $flatten\Controller.\Uart.\TX_FIFO.$0$memwr$\memory$/eda/processor-ci-controller/src/fifo.v:41$912_EN[7:0]$924 [0] } Optimizing cells in module \processorci_top. Performed a total of 33 changes. 18.11.5. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\processorci_top'. <suppressed ~33 debug messages> Removed a total of 11 cells. 18.11.6. Executing OPT_DFF pass (perform DFF optimizations). 18.11.7. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \processorci_top.. Removed 0 unused cells and 221 unused wires. <suppressed ~3 debug messages> 18.11.8. Executing OPT_EXPR pass (perform const folding). Optimizing module processorci_top. 18.11.9. Rerunning OPT passes. (Maybe there is more to do..) 18.11.10. Executing OPT_MUXTREE pass (detect dead branches in mux trees). Running muxtree optimizer on module \processorci_top.. Creating internal representation of mux trees. Evaluating internal representation of mux trees. Analyzing evaluation results. Removed 0 multiplexer ports. <suppressed ~151 debug messages> 18.11.11. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). Optimizing cells in module \processorci_top. New ctrl vector for $pmux cell $flatten\Controller.\Interpreter.$procmux$1752: { $auto$opt_reduce.cc:134:opt_pmux$2908 $auto$opt_reduce.cc:134:opt_pmux$2974 } New ctrl vector for $pmux cell $flatten\Controller.\Interpreter.$procmux$1899: { $auto$opt_reduce.cc:134:opt_pmux$2908 $auto$opt_reduce.cc:134:opt_pmux$2976 } New ctrl vector for $pmux cell $flatten\Controller.\Interpreter.$procmux$2116: { $auto$opt_reduce.cc:134:opt_pmux$2924 $flatten\Controller.\Interpreter.$procmux$1606_CMP $flatten\Controller.\Interpreter.$procmux$1525_CMP $auto$opt_reduce.cc:134:opt_pmux$2978 } New ctrl vector for $pmux cell $flatten\Core.\Alu.$procmux$2742: { $flatten\Core.\Alu.$procmux$2756_CMP $flatten\Core.\Alu.$procmux$2755_CMP $flatten\Core.\Alu.$procmux$2754_CMP $flatten\Core.\Alu.$procmux$2753_CMP $auto$opt_reduce.cc:134:opt_pmux$2982 $flatten\Core.\Alu.$procmux$2750_CMP $flatten\Core.\Alu.$procmux$2749_CMP $flatten\Core.\Alu.$procmux$2748_CMP $flatten\Core.\Alu.$procmux$2747_CMP $flatten\Core.\Alu.$procmux$2746_CMP $flatten\Core.\Alu.$procmux$2745_CMP $auto$opt_reduce.cc:134:opt_pmux$2980 } Optimizing cells in module \processorci_top. Performed a total of 4 changes. 18.11.12. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\processorci_top'. <suppressed ~6 debug messages> Removed a total of 2 cells. 18.11.13. Executing OPT_DFF pass (perform DFF optimizations). 18.11.14. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \processorci_top.. Removed 0 unused cells and 2 unused wires. <suppressed ~1 debug messages> 18.11.15. Executing OPT_EXPR pass (perform const folding). Optimizing module processorci_top. 18.11.16. Rerunning OPT passes. (Maybe there is more to do..) 18.11.17. Executing OPT_MUXTREE pass (detect dead branches in mux trees). Running muxtree optimizer on module \processorci_top.. Creating internal representation of mux trees. Evaluating internal representation of mux trees. Analyzing evaluation results. Removed 0 multiplexer ports. <suppressed ~151 debug messages> 18.11.18. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). Optimizing cells in module \processorci_top. Performed a total of 0 changes. 18.11.19. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\processorci_top'. Removed a total of 0 cells. 18.11.20. Executing OPT_DFF pass (perform DFF optimizations). 18.11.21. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \processorci_top.. 18.11.22. Executing OPT_EXPR pass (perform const folding). Optimizing module processorci_top. 18.11.23. Finished OPT passes. (There is nothing left to do.) 18.12. Executing FSM pass (extract and optimize FSM). 18.12.1. Executing FSM_DETECT pass (finding FSMs in design). Not marking processorci_top.Controller.Interpreter.return_state as FSM state register: Users of register don't seem to benefit from recoding. Found FSM state register processorci_top.Controller.Uart.i_uart_rx.fsm_state. Not marking processorci_top.Controller.Uart.i_uart_tx.fsm_state as FSM state register: Users of register don't seem to benefit from recoding. Not marking processorci_top.Controller.Uart.state_read as FSM state register: Register has an initialization value. Not marking processorci_top.Controller.Uart.state_write as FSM state register: Register has an initialization value. Found FSM state register processorci_top.Controller.Uart.tx_fifo_read_state. Not marking processorci_top.Core.aluop_out_reg as FSM state register: Users of register don't seem to benefit from recoding. Not marking processorci_top.ResetBootSystem.state as FSM state register: Register has an initialization value. Circuit seems to be self-resetting. 18.12.2. Executing FSM_EXTRACT pass (extracting FSM from design). Extracting FSM `\Controller.Uart.i_uart_rx.fsm_state' from module `\processorci_top'. found $dff cell for state register: $flatten\Controller.\Uart.\i_uart_rx.$procdff$2772 root of input selection tree: $flatten\Controller.\Uart.\i_uart_rx.$0\fsm_state[2:0] found reset state: 3'000 (guessed from mux tree) found ctrl input: \ResetBootSystem.reset_o found ctrl input: $flatten\Controller.\Uart.\i_uart_rx.$eq$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:109$1080_Y found ctrl input: $flatten\Controller.\Uart.\i_uart_rx.$eq$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:137$1093_Y found ctrl input: $flatten\Controller.\Uart.\i_uart_rx.$eq$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:175$1106_Y found ctrl input: $flatten\Controller.\Uart.\i_uart_rx.$eq$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:135$1092_Y found state code: 3'000 found ctrl input: \Controller.Uart.i_uart_rx.next_bit found state code: 3'011 found ctrl input: \Controller.Uart.i_uart_rx.payload_done found state code: 3'010 found state code: 3'001 found ctrl input: \Controller.Uart.i_uart_rx.rxd_reg found ctrl output: $flatten\Controller.\Uart.\i_uart_rx.$eq$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:175$1106_Y found ctrl output: $flatten\Controller.\Uart.\i_uart_rx.$ne$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:150$1097_Y found ctrl output: $flatten\Controller.\Uart.\i_uart_rx.$eq$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:137$1093_Y found ctrl output: $flatten\Controller.\Uart.\i_uart_rx.$eq$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:135$1092_Y found ctrl output: $flatten\Controller.\Uart.\i_uart_rx.$eq$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:109$1080_Y ctrl inputs: { \ResetBootSystem.reset_o \Controller.Uart.i_uart_rx.rxd_reg \Controller.Uart.i_uart_rx.next_bit \Controller.Uart.i_uart_rx.payload_done } ctrl outputs: { $flatten\Controller.\Uart.\i_uart_rx.$eq$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:109$1080_Y $flatten\Controller.\Uart.\i_uart_rx.$eq$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:135$1092_Y $flatten\Controller.\Uart.\i_uart_rx.$eq$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:137$1093_Y $flatten\Controller.\Uart.\i_uart_rx.$ne$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:150$1097_Y $flatten\Controller.\Uart.\i_uart_rx.$eq$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:175$1106_Y $flatten\Controller.\Uart.\i_uart_rx.$0\fsm_state[2:0] } transition: 3'000 4'00-- -> 3'001 8'01010001 transition: 3'000 4'01-- -> 3'000 8'01010000 transition: 3'000 4'1--- -> 3'000 8'01010000 transition: 3'010 4'0--0 -> 3'010 8'00100010 transition: 3'010 4'0--1 -> 3'011 8'00100011 transition: 3'010 4'1--- -> 3'000 8'00100000 transition: 3'001 4'0-0- -> 3'001 8'00011001 transition: 3'001 4'0-1- -> 3'010 8'00011010 transition: 3'001 4'1--- -> 3'000 8'00011000 transition: 3'011 4'0-0- -> 3'011 8'10010011 transition: 3'011 4'0-1- -> 3'000 8'10010000 transition: 3'011 4'1--- -> 3'000 8'10010000 Extracting FSM `\Controller.Uart.tx_fifo_read_state' from module `\processorci_top'. found $dff cell for state register: $flatten\Controller.\Uart.$procdff$2819 root of input selection tree: $flatten\Controller.\Uart.$0\tx_fifo_read_state[1:0] found reset state: 2'00 (guessed from mux tree) found ctrl input: \ResetBootSystem.reset_o found ctrl input: $flatten\Controller.\Uart.$procmux$2219_CMP found ctrl input: $flatten\Controller.\Uart.$procmux$2214_CMP found ctrl input: $flatten\Controller.\Uart.$procmux$2221_CMP found ctrl input: $flatten\Controller.\Uart.$procmux$2208_CMP found state code: 2'00 found state code: 2'11 found state code: 2'10 found ctrl input: $flatten\Controller.\Uart.$logic_and$/eda/processor-ci-controller/modules/uart.v:215$966_Y found state code: 2'01 found ctrl output: $flatten\Controller.\Uart.$procmux$2208_CMP found ctrl output: $flatten\Controller.\Uart.$procmux$2214_CMP found ctrl output: $flatten\Controller.\Uart.$procmux$2219_CMP found ctrl output: $flatten\Controller.\Uart.$procmux$2221_CMP ctrl inputs: { \ResetBootSystem.reset_o $flatten\Controller.\Uart.$logic_and$/eda/processor-ci-controller/modules/uart.v:215$966_Y } ctrl outputs: { $flatten\Controller.\Uart.$procmux$2221_CMP $flatten\Controller.\Uart.$procmux$2219_CMP $flatten\Controller.\Uart.$procmux$2214_CMP $flatten\Controller.\Uart.$procmux$2208_CMP $flatten\Controller.\Uart.$0\tx_fifo_read_state[1:0] } transition: 2'00 2'00 -> 2'00 6'000100 transition: 2'00 2'01 -> 2'01 6'000101 transition: 2'00 2'1- -> 2'00 6'000100 transition: 2'10 2'0- -> 2'11 6'001011 transition: 2'10 2'1- -> 2'00 6'001000 transition: 2'01 2'0- -> 2'10 6'100010 transition: 2'01 2'1- -> 2'00 6'100000 transition: 2'11 2'0- -> 2'00 6'010000 transition: 2'11 2'1- -> 2'00 6'010000 18.12.3. Executing FSM_OPT pass (simple optimizations of FSMs). Optimizing FSM `$fsm$\Controller.Uart.tx_fifo_read_state$2990' from module `\processorci_top'. Merging pattern 2'0- and 2'1- from group (3 0 6'010000). Merging pattern 2'1- and 2'0- from group (3 0 6'010000). Optimizing FSM `$fsm$\Controller.Uart.i_uart_rx.fsm_state$2983' from module `\processorci_top'. 18.12.4. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \processorci_top.. Removed 15 unused cells and 15 unused wires. <suppressed ~16 debug messages> 18.12.5. Executing FSM_OPT pass (simple optimizations of FSMs). Optimizing FSM `$fsm$\Controller.Uart.i_uart_rx.fsm_state$2983' from module `\processorci_top'. Removing unused output signal $flatten\Controller.\Uart.\i_uart_rx.$0\fsm_state[2:0] [0]. Removing unused output signal $flatten\Controller.\Uart.\i_uart_rx.$0\fsm_state[2:0] [1]. Removing unused output signal $flatten\Controller.\Uart.\i_uart_rx.$0\fsm_state[2:0] [2]. Optimizing FSM `$fsm$\Controller.Uart.tx_fifo_read_state$2990' from module `\processorci_top'. Removing unused output signal $flatten\Controller.\Uart.$0\tx_fifo_read_state[1:0] [0]. Removing unused output signal $flatten\Controller.\Uart.$0\tx_fifo_read_state[1:0] [1]. Removing unused output signal $flatten\Controller.\Uart.$procmux$2219_CMP. Removing unused output signal $flatten\Controller.\Uart.$procmux$2221_CMP. 18.12.6. Executing FSM_RECODE pass (re-assigning FSM state encoding). Recoding FSM `$fsm$\Controller.Uart.i_uart_rx.fsm_state$2983' from module `\processorci_top' using `auto' encoding: mapping auto encoding to `one-hot` for this FSM. 000 -> ---1 010 -> --1- 001 -> -1-- 011 -> 1--- Recoding FSM `$fsm$\Controller.Uart.tx_fifo_read_state$2990' from module `\processorci_top' using `auto' encoding: mapping auto encoding to `one-hot` for this FSM. 00 -> ---1 10 -> --1- 01 -> -1-- 11 -> 1--- 18.12.7. Executing FSM_INFO pass (dumping all available information on FSM cells). FSM `$fsm$\Controller.Uart.i_uart_rx.fsm_state$2983' from module `processorci_top': ------------------------------------- Information on FSM $fsm$\Controller.Uart.i_uart_rx.fsm_state$2983 (\Controller.Uart.i_uart_rx.fsm_state): Number of input signals: 4 Number of output signals: 5 Number of state bits: 4 Input signals: 0: \Controller.Uart.i_uart_rx.payload_done 1: \Controller.Uart.i_uart_rx.next_bit 2: \Controller.Uart.i_uart_rx.rxd_reg 3: \ResetBootSystem.reset_o Output signals: 0: $flatten\Controller.\Uart.\i_uart_rx.$eq$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:175$1106_Y 1: $flatten\Controller.\Uart.\i_uart_rx.$ne$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:150$1097_Y 2: $flatten\Controller.\Uart.\i_uart_rx.$eq$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:137$1093_Y 3: $flatten\Controller.\Uart.\i_uart_rx.$eq$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:135$1092_Y 4: $flatten\Controller.\Uart.\i_uart_rx.$eq$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:109$1080_Y State encoding: 0: 4'---1 <RESET STATE> 1: 4'--1- 2: 4'-1-- 3: 4'1--- Transition Table (state_in, ctrl_in, state_out, ctrl_out): 0: 0 4'01-- -> 0 5'01010 1: 0 4'1--- -> 0 5'01010 2: 0 4'00-- -> 2 5'01010 3: 1 4'1--- -> 0 5'00100 4: 1 4'0--0 -> 1 5'00100 5: 1 4'0--1 -> 3 5'00100 6: 2 4'1--- -> 0 5'00011 7: 2 4'0-1- -> 1 5'00011 8: 2 4'0-0- -> 2 5'00011 9: 3 4'0-1- -> 0 5'10010 10: 3 4'1--- -> 0 5'10010 11: 3 4'0-0- -> 3 5'10010 ------------------------------------- FSM `$fsm$\Controller.Uart.tx_fifo_read_state$2990' from module `processorci_top': ------------------------------------- Information on FSM $fsm$\Controller.Uart.tx_fifo_read_state$2990 (\Controller.Uart.tx_fifo_read_state): Number of input signals: 2 Number of output signals: 2 Number of state bits: 4 Input signals: 0: $flatten\Controller.\Uart.$logic_and$/eda/processor-ci-controller/modules/uart.v:215$966_Y 1: \ResetBootSystem.reset_o Output signals: 0: $flatten\Controller.\Uart.$procmux$2208_CMP 1: $flatten\Controller.\Uart.$procmux$2214_CMP State encoding: 0: 4'---1 <RESET STATE> 1: 4'--1- 2: 4'-1-- 3: 4'1--- Transition Table (state_in, ctrl_in, state_out, ctrl_out): 0: 0 2'00 -> 0 2'01 1: 0 2'1- -> 0 2'01 2: 0 2'01 -> 2 2'01 3: 1 2'1- -> 0 2'10 4: 1 2'0- -> 3 2'10 5: 2 2'1- -> 0 2'00 6: 2 2'0- -> 1 2'00 7: 3 2'-- -> 0 2'00 ------------------------------------- 18.12.8. Executing FSM_MAP pass (mapping FSMs to basic logic). Mapping FSM `$fsm$\Controller.Uart.i_uart_rx.fsm_state$2983' from module `\processorci_top'. Mapping FSM `$fsm$\Controller.Uart.tx_fifo_read_state$2990' from module `\processorci_top'. 18.13. Executing OPT pass (performing simple optimizations). 18.13.1. Executing OPT_EXPR pass (perform const folding). Optimizing module processorci_top. <suppressed ~9 debug messages> 18.13.2. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\processorci_top'. <suppressed ~9 debug messages> Removed a total of 3 cells. 18.13.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees). Running muxtree optimizer on module \processorci_top.. Creating internal representation of mux trees. Evaluating internal representation of mux trees. Analyzing evaluation results. Removed 0 multiplexer ports. <suppressed ~149 debug messages> 18.13.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). Optimizing cells in module \processorci_top. Performed a total of 0 changes. 18.13.5. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\processorci_top'. Removed a total of 0 cells. 18.13.6. Executing OPT_DFF pass (perform DFF optimizations). Adding EN signal on $flatten\ResetBootSystem.$procdff$2842 ($dff) from module processorci_top (D = $flatten\ResetBootSystem.$0\counter[5:0], Q = \ResetBootSystem.counter). Adding EN signal on $flatten\ResetBootSystem.$procdff$2840 ($dff) from module processorci_top (D = $flatten\ResetBootSystem.$0\reset_o[0:0], Q = \ResetBootSystem.reset_o). Adding SRST signal on $flatten\Core.$procdff$2881 ($dff) from module processorci_top (D = $flatten\Core.$procmux$2665_Y, Q = \Core.IFIDIR, rval = 51). Adding EN signal on $auto$ff.cc:266:slice$3078 ($sdff) from module processorci_top (D = \Core.instruction_data, Q = \Core.IFIDIR). Adding EN signal on $flatten\Core.$procdff$2878 ($dff) from module processorci_top (D = $flatten\Core.$procmux$2694_Y, Q = \Core.IFIDPC). Adding SRST signal on $auto$ff.cc:266:slice$3082 ($dffe) from module processorci_top (D = $flatten\Core.$procmux$2682_Y, Q = \Core.IFIDPC, rval = 0). Adding SRST signal on $flatten\Core.$procdff$2877 ($dff) from module processorci_top (D = $flatten\Core.$procmux$2711_Y, Q = \Core.PC, rval = 0). Adding EN signal on $auto$ff.cc:266:slice$3092 ($sdff) from module processorci_top (D = $flatten\Core.$procmux$2711_Y, Q = \Core.PC). Adding SRST signal on $flatten\Core.$procdff$2872 ($dff) from module processorci_top (D = $flatten\Core.$procmux$2617_Y, Q = \Core.IDEXIR, rval = 51). Adding EN signal on $auto$ff.cc:266:slice$3100 ($sdff) from module processorci_top (D = \Core.IFIDIR, Q = \Core.IDEXIR). Adding EN signal on $flatten\Core.$procdff$2871 ($dff) from module processorci_top (D = \Core.aluop_out, Q = \Core.aluop_out_reg). Adding EN signal on $flatten\Core.$procdff$2870 ($dff) from module processorci_top (D = $flatten\Core.$procmux$2629_Y, Q = \Core.alu_input_b). Adding EN signal on $flatten\Core.$procdff$2869 ($dff) from module processorci_top (D = $flatten\Core.$procmux$2640_Y, Q = \Core.alu_input_a). Adding EN signal on $flatten\Core.$procdff$2868 ($dff) from module processorci_top (D = \Core.IFIDPC, Q = \Core.IDEXPC). Adding EN signal on $flatten\Core.$procdff$2867 ($dff) from module processorci_top (D = $flatten\Core.$procmux$2654_Y, Q = \Core.IDEXB). Adding EN signal on $flatten\Core.$procdff$2866 ($dff) from module processorci_top (D = $flatten\Core.$procmux$2660_Y, Q = \Core.IDEXA). Adding EN signal on $flatten\Core.$procdff$2865 ($dff) from module processorci_top (D = \Core.forward_out_b, Q = \Core.memory_write_data). Adding SRST signal on $flatten\Core.$procdff$2864 ($dff) from module processorci_top (D = $flatten\Core.$procmux$2600_Y, Q = \Core.EXEXIR, rval = 51). Adding EN signal on $auto$ff.cc:266:slice$3125 ($sdff) from module processorci_top (D = \Core.IDEXIR, Q = \Core.EXEXIR). Adding EN signal on $flatten\Core.$procdff$2863 ($dff) from module processorci_top (D = \Core.IDEXPC, Q = \Core.EXEXPC). Adding SRST signal on $flatten\Core.$procdff$2859 ($dff) from module processorci_top (D = $flatten\Core.$procmux$2570_Y, Q = \Core.EXMEMIR, rval = 51). Adding EN signal on $auto$ff.cc:266:slice$3138 ($sdff) from module processorci_top (D = \Core.EXEXIR, Q = \Core.EXMEMIR). Adding EN signal on $flatten\Core.$procdff$2858 ($dff) from module processorci_top (D = \Core.Alu.ALU_out_S, Q = \Core.EXMEMALUOut). Adding EN signal on $flatten\Core.$procdff$2857 ($dff) from module processorci_top (D = \Core.memory_write_data, Q = \Core.EXMEM_mem_data_value). Adding EN signal on $flatten\Core.$procdff$2856 ($dff) from module processorci_top (D = \Core.immediate, Q = \Core.IMMEDIATE_REG). Adding SRST signal on $flatten\Core.$procdff$2854 ($dff) from module processorci_top (D = $flatten\Core.$procmux$2554_Y, Q = \Core.memory_read, rval = 1'0). Adding SRST signal on $flatten\Core.$procdff$2853 ($dff) from module processorci_top (D = $flatten\Core.$procmux$2564_Y, Q = \Core.memory_write, rval = 1'0). Adding SRST signal on $flatten\Core.$procdff$2852 ($dff) from module processorci_top (D = \Core.EXMEMIR, Q = \Core.MEMWBIR, rval = 51). Adding EN signal on $flatten\Core.$procdff$2851 ($dff) from module processorci_top (D = \Core.EXMEMALUOut, Q = \Core.MEMWBALUOut). Adding EN signal on $flatten\Core.$procdff$2850 ($dff) from module processorci_top (D = \Core.read_data, Q = \Core.MEMWB_mem_read_data). Adding SRST signal on $auto$ff.cc:266:slice$3163 ($dffe) from module processorci_top (D = \Controller.data_memory_read_data, Q = \Core.MEMWB_mem_read_data, rval = 0). Adding SRST signal on $flatten\Core.$procdff$2849 ($dff) from module processorci_top (D = $flatten\Core.$procmux$2538_Y, Q = \Core.reg_write, rval = 1'0). Adding SRST signal on $flatten\Core.$procdff$2848 ($dff) from module processorci_top (D = $flatten\Core.$procmux$2533_Y, Q = \Core.mem_to_reg, rval = 1'0). Adding SRST signal on $flatten\Controller.\Uart.\i_uart_tx.$procdff$2784 ($dff) from module processorci_top (D = { $flatten\Controller.\Uart.\i_uart_tx.$procmux$1430_Y $flatten\Controller.\Uart.\i_uart_tx.$procmux$1424_Y $flatten\Controller.\Uart.\i_uart_tx.$procmux$1415_Y $flatten\Controller.\Uart.\i_uart_tx.$procmux$1406_Y $flatten\Controller.\Uart.\i_uart_tx.$procmux$1397_Y $flatten\Controller.\Uart.\i_uart_tx.$procmux$1388_Y $flatten\Controller.\Uart.\i_uart_tx.$procmux$1370_Y $flatten\Controller.\Uart.\i_uart_tx.$procmux$1379_Y }, Q = \Controller.Uart.i_uart_tx.data_to_send, rval = 8'00000000). Adding EN signal on $auto$ff.cc:266:slice$3167 ($sdff) from module processorci_top (D = \Controller.Uart.uart_tx_data [7], Q = \Controller.Uart.i_uart_tx.data_to_send [7]). Adding EN signal on $auto$ff.cc:266:slice$3167 ($sdff) from module processorci_top (D = { $flatten\Controller.\Uart.\i_uart_tx.$procmux$1424_Y $flatten\Controller.\Uart.\i_uart_tx.$procmux$1415_Y $flatten\Controller.\Uart.\i_uart_tx.$procmux$1406_Y $flatten\Controller.\Uart.\i_uart_tx.$procmux$1397_Y $flatten\Controller.\Uart.\i_uart_tx.$procmux$1388_Y $flatten\Controller.\Uart.\i_uart_tx.$procmux$1370_Y $flatten\Controller.\Uart.\i_uart_tx.$procmux$1379_Y }, Q = \Controller.Uart.i_uart_tx.data_to_send [6:0]). Adding SRST signal on $flatten\Controller.\Uart.\i_uart_tx.$procdff$2782 ($dff) from module processorci_top (D = $flatten\Controller.\Uart.\i_uart_tx.$procmux$1346_Y, Q = \Controller.Uart.i_uart_tx.bit_counter, rval = 4'0000). Adding EN signal on $auto$ff.cc:266:slice$3172 ($sdff) from module processorci_top (D = $flatten\Controller.\Uart.\i_uart_tx.$procmux$1346_Y, Q = \Controller.Uart.i_uart_tx.bit_counter). Adding SRST signal on $flatten\Controller.\Uart.\i_uart_tx.$procdff$2781 ($dff) from module processorci_top (D = $flatten\Controller.\Uart.\i_uart_tx.$procmux$1335_Y, Q = \Controller.Uart.i_uart_tx.cycle_counter, rval = 9'000000000). Adding EN signal on $auto$ff.cc:266:slice$3178 ($sdff) from module processorci_top (D = $flatten\Controller.\Uart.\i_uart_tx.$add$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:155$1060_Y, Q = \Controller.Uart.i_uart_tx.cycle_counter). Adding SRST signal on $flatten\Controller.\Uart.\i_uart_tx.$procdff$2780 ($dff) from module processorci_top (D = \Controller.Uart.i_uart_tx.n_fsm_state, Q = \Controller.Uart.i_uart_tx.fsm_state, rval = 3'000). Adding SRST signal on $flatten\Controller.\Uart.\i_uart_tx.$procdff$2779 ($dff) from module processorci_top (D = $flatten\Controller.\Uart.\i_uart_tx.$procmux$1324_Y, Q = \Controller.Uart.i_uart_tx.txd_reg, rval = 1'1). Adding EN signal on $auto$ff.cc:266:slice$3183 ($sdff) from module processorci_top (D = $flatten\Controller.\Uart.\i_uart_tx.$procmux$1324_Y, Q = \Controller.Uart.i_uart_tx.txd_reg). Adding SRST signal on $flatten\Controller.\Uart.\i_uart_rx.$procdff$2778 ($dff) from module processorci_top (D = $flatten\Controller.\Uart.\i_uart_rx.$procmux$1313_Y, Q = \Controller.Uart.i_uart_rx.uart_rx_data, rval = 8'00000000). Adding EN signal on $auto$ff.cc:266:slice$3189 ($sdff) from module processorci_top (D = \Controller.Uart.i_uart_rx.recieved_data, Q = \Controller.Uart.i_uart_rx.uart_rx_data). Adding SRST signal on $flatten\Controller.\Uart.\i_uart_rx.$procdff$2776 ($dff) from module processorci_top (D = { $flatten\Controller.\Uart.\i_uart_rx.$procmux$1290_Y $flatten\Controller.\Uart.\i_uart_rx.$procmux$1281_Y $flatten\Controller.\Uart.\i_uart_rx.$procmux$1272_Y $flatten\Controller.\Uart.\i_uart_rx.$procmux$1263_Y $flatten\Controller.\Uart.\i_uart_rx.$procmux$1254_Y $flatten\Controller.\Uart.\i_uart_rx.$procmux$1245_Y $flatten\Controller.\Uart.\i_uart_rx.$procmux$1227_Y $flatten\Controller.\Uart.\i_uart_rx.$procmux$1236_Y }, Q = \Controller.Uart.i_uart_rx.recieved_data, rval = 8'00000000). Adding EN signal on $auto$ff.cc:266:slice$3191 ($sdff) from module processorci_top (D = { \Controller.Uart.i_uart_rx.bit_sample \Controller.Uart.i_uart_rx.recieved_data [7:1] }, Q = \Controller.Uart.i_uart_rx.recieved_data). Adding SRST signal on $flatten\Controller.\Uart.\i_uart_rx.$procdff$2775 ($dff) from module processorci_top (D = $flatten\Controller.\Uart.\i_uart_rx.$procmux$1209_Y, Q = \Controller.Uart.i_uart_rx.bit_counter, rval = 4'0000). Adding EN signal on $auto$ff.cc:266:slice$3195 ($sdff) from module processorci_top (D = $flatten\Controller.\Uart.\i_uart_rx.$add$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:153$1100_Y, Q = \Controller.Uart.i_uart_rx.bit_counter). Adding SRST signal on $flatten\Controller.\Uart.\i_uart_rx.$procdff$2774 ($dff) from module processorci_top (D = $flatten\Controller.\Uart.\i_uart_rx.$procmux$1204_Y, Q = \Controller.Uart.i_uart_rx.bit_sample, rval = 1'0). Adding EN signal on $auto$ff.cc:266:slice$3199 ($sdff) from module processorci_top (D = \Controller.Uart.i_uart_rx.rxd_reg, Q = \Controller.Uart.i_uart_rx.bit_sample). Adding SRST signal on $flatten\Controller.\Uart.\i_uart_rx.$procdff$2773 ($dff) from module processorci_top (D = $flatten\Controller.\Uart.\i_uart_rx.$procmux$1196_Y, Q = \Controller.Uart.i_uart_rx.cycle_counter, rval = 9'000000000). Adding EN signal on $auto$ff.cc:266:slice$3201 ($sdff) from module processorci_top (D = $flatten\Controller.\Uart.\i_uart_rx.$add$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:178$1111_Y, Q = \Controller.Uart.i_uart_rx.cycle_counter). Adding SRST signal on $flatten\Controller.\Uart.\i_uart_rx.$procdff$2771 ($dff) from module processorci_top (D = \rx, Q = \Controller.Uart.i_uart_rx.rxd_reg_0, rval = 1'1). Adding SRST signal on $flatten\Controller.\Uart.\i_uart_rx.$procdff$2770 ($dff) from module processorci_top (D = \Controller.Uart.i_uart_rx.rxd_reg_0, Q = \Controller.Uart.i_uart_rx.rxd_reg, rval = 1'1). Adding SRST signal on $flatten\Controller.\Uart.\TX_FIFO.$procdff$2769 ($dff) from module processorci_top (D = $flatten\Controller.\Uart.\TX_FIFO.$procmux$1173_Y, Q = \Controller.Uart.TX_FIFO.read_ptr, rval = 6'000000). Adding EN signal on $auto$ff.cc:266:slice$3207 ($sdff) from module processorci_top (D = $flatten\Controller.\Uart.\TX_FIFO.$ternary$/eda/processor-ci-controller/src/fifo.v:31$920_Y [5:0], Q = \Controller.Uart.TX_FIFO.read_ptr). Adding EN signal on $flatten\Controller.\Uart.\TX_FIFO.$procdff$2768 ($dff) from module processorci_top (D = $flatten\Controller.\Uart.\TX_FIFO.$memrd$\memory$/eda/processor-ci-controller/src/fifo.v:30$917_DATA, Q = \Controller.Uart.TX_FIFO.read_data). Adding SRST signal on $flatten\Controller.\Uart.\TX_FIFO.$procdff$2764 ($dff) from module processorci_top (D = $flatten\Controller.\Uart.\TX_FIFO.$procmux$1168_Y, Q = \Controller.Uart.TX_FIFO.write_ptr, rval = 6'000000). Adding EN signal on $auto$ff.cc:266:slice$3214 ($sdff) from module processorci_top (D = $flatten\Controller.\Uart.\TX_FIFO.$ternary$/eda/processor-ci-controller/src/fifo.v:42$936_Y [5:0], Q = \Controller.Uart.TX_FIFO.write_ptr). Adding SRST signal on $flatten\Controller.\Uart.\RX_FIFO.$procdff$2769 ($dff) from module processorci_top (D = $flatten\Controller.\Uart.\RX_FIFO.$procmux$1173_Y, Q = \Controller.Uart.RX_FIFO.read_ptr, rval = 6'000000). Adding EN signal on $auto$ff.cc:266:slice$3216 ($sdff) from module processorci_top (D = $flatten\Controller.\Uart.\RX_FIFO.$ternary$/eda/processor-ci-controller/src/fifo.v:31$920_Y [5:0], Q = \Controller.Uart.RX_FIFO.read_ptr). Adding EN signal on $flatten\Controller.\Uart.\RX_FIFO.$procdff$2768 ($dff) from module processorci_top (D = $flatten\Controller.\Uart.\RX_FIFO.$memrd$\memory$/eda/processor-ci-controller/src/fifo.v:30$917_DATA, Q = \Controller.Uart.RX_FIFO.read_data). Adding SRST signal on $flatten\Controller.\Uart.\RX_FIFO.$procdff$2764 ($dff) from module processorci_top (D = $flatten\Controller.\Uart.\RX_FIFO.$procmux$1168_Y, Q = \Controller.Uart.RX_FIFO.write_ptr, rval = 6'000000). Adding EN signal on $auto$ff.cc:266:slice$3223 ($sdff) from module processorci_top (D = $flatten\Controller.\Uart.\RX_FIFO.$ternary$/eda/processor-ci-controller/src/fifo.v:42$936_Y [5:0], Q = \Controller.Uart.RX_FIFO.write_ptr). Adding SRST signal on $flatten\Controller.\Uart.$procdff$2832 ($dff) from module processorci_top (D = $flatten\Controller.\Uart.$procmux$2344_Y, Q = \Controller.Uart.state_read, rval = 4'0000). Adding EN signal on $auto$ff.cc:266:slice$3225 ($sdff) from module processorci_top (D = $flatten\Controller.\Uart.$procmux$2344_Y, Q = \Controller.Uart.state_read). Adding SRST signal on $flatten\Controller.\Uart.$procdff$2831 ($dff) from module processorci_top (D = $flatten\Controller.\Uart.$procmux$2369_Y, Q = \Controller.Uart.counter_read, rval = 3'000). Adding EN signal on $auto$ff.cc:266:slice$3229 ($sdff) from module processorci_top (D = $flatten\Controller.\Uart.$procmux$2369_Y, Q = \Controller.Uart.counter_read). Adding SRST signal on $flatten\Controller.\Uart.$procdff$2830 ($dff) from module processorci_top (D = $flatten\Controller.\Uart.$procmux$2333_Y, Q = \Controller.Uart.rx_fifo_read, rval = 1'0). Adding SRST signal on $flatten\Controller.\Uart.$procdff$2829 ($dff) from module processorci_top (D = $flatten\Controller.\Uart.$procmux$2322_Y, Q = \Controller.Uart.read_response, rval = 1'0). Adding SRST signal on $flatten\Controller.\Uart.$procdff$2828 ($dff) from module processorci_top (D = $flatten\Controller.\Uart.$procmux$2384_Y, Q = \Controller.Uart.read_data, rval = 0). Adding EN signal on $auto$ff.cc:266:slice$3247 ($sdff) from module processorci_top (D = $flatten\Controller.\Uart.$procmux$2382_Y, Q = \Controller.Uart.read_data). Adding SRST signal on $flatten\Controller.\Uart.$procdff$2827 ($dff) from module processorci_top (D = $flatten\Controller.\Uart.$procmux$2266_Y, Q = \Controller.Uart.state_write, rval = 4'0000). Adding EN signal on $auto$ff.cc:266:slice$3253 ($sdff) from module processorci_top (D = $flatten\Controller.\Uart.$procmux$2266_Y, Q = \Controller.Uart.state_write). Adding SRST signal on $flatten\Controller.\Uart.$procdff$2826 ($dff) from module processorci_top (D = $flatten\Controller.\Uart.$procmux$2288_Y, Q = \Controller.Uart.counter_write, rval = 3'000). Adding EN signal on $auto$ff.cc:266:slice$3257 ($sdff) from module processorci_top (D = $flatten\Controller.\Uart.$procmux$2288_Y, Q = \Controller.Uart.counter_write). Adding SRST signal on $flatten\Controller.\Uart.$procdff$2825 ($dff) from module processorci_top (D = $flatten\Controller.\Uart.$procmux$2302_Y, Q = \Controller.Uart.write_data_buffer, rval = 0). Adding EN signal on $auto$ff.cc:266:slice$3267 ($sdff) from module processorci_top (D = $flatten\Controller.\Uart.$procmux$2302_Y, Q = \Controller.Uart.write_data_buffer). Adding SRST signal on $flatten\Controller.\Uart.$procdff$2824 ($dff) from module processorci_top (D = $flatten\Controller.\Uart.$procmux$2316_Y, Q = \Controller.Uart.tx_fifo_write_data, rval = 8'00000000). Adding EN signal on $auto$ff.cc:266:slice$3277 ($sdff) from module processorci_top (D = \Controller.Uart.write_data_buffer [31:24], Q = \Controller.Uart.tx_fifo_write_data). Adding SRST signal on $flatten\Controller.\Uart.$procdff$2823 ($dff) from module processorci_top (D = $flatten\Controller.\Uart.$procmux$2248_Y, Q = \Controller.Uart.tx_fifo_write, rval = 1'0). Adding SRST signal on $flatten\Controller.\Uart.$procdff$2822 ($dff) from module processorci_top (D = $flatten\Controller.\Uart.$procmux$2258_Y, Q = \Controller.Uart.write_response, rval = 1'0). Adding SRST signal on $flatten\Controller.\Uart.$procdff$2821 ($dff) from module processorci_top (D = $flatten\Controller.\Uart.$procmux$2239_Y, Q = \Controller.Uart.rx_fifo_write_data, rval = 8'00000000). Adding EN signal on $auto$ff.cc:266:slice$3291 ($sdff) from module processorci_top (D = \Controller.Uart.i_uart_rx.uart_rx_data, Q = \Controller.Uart.rx_fifo_write_data). Adding SRST signal on $flatten\Controller.\Uart.$procdff$2820 ($dff) from module processorci_top (D = $flatten\Controller.\Uart.$procmux$2234_Y, Q = \Controller.Uart.rx_fifo_write, rval = 1'0). Adding SRST signal on $flatten\Controller.\Uart.$procdff$2818 ($dff) from module processorci_top (D = $flatten\Controller.\Uart.$procmux$2229_Y, Q = \Controller.Uart.uart_tx_data, rval = 8'00000000). Adding EN signal on $auto$ff.cc:266:slice$3294 ($sdff) from module processorci_top (D = \Controller.Uart.TX_FIFO.read_data, Q = \Controller.Uart.uart_tx_data). Adding SRST signal on $flatten\Controller.\Uart.$procdff$2817 ($dff) from module processorci_top (D = $flatten\Controller.\Uart.$procmux$2205_Y, Q = \Controller.Uart.tx_fifo_read, rval = 1'0). Adding SRST signal on $flatten\Controller.\Uart.$procdff$2816 ($dff) from module processorci_top (D = $flatten\Controller.\Uart.$procmux$2213_Y, Q = \Controller.Uart.uart_tx_en, rval = 1'0). Adding EN signal on $flatten\Controller.\Interpreter.$procdff$2815 ($dff) from module processorci_top (D = $flatten\Controller.\Interpreter.$procmux$1752_Y, Q = \Controller.Interpreter.temp_buffer). Adding SRST signal on $flatten\Controller.\Interpreter.$procdff$2814 ($dff) from module processorci_top (D = $flatten\Controller.\Interpreter.$procmux$1795_Y, Q = \Controller.Interpreter.accumulator, rval = 64'0000000000000000000000000000000000000000000000000000000000000000). Adding EN signal on $auto$ff.cc:266:slice$3311 ($sdff) from module processorci_top (D = $flatten\Controller.\Interpreter.$procmux$1795_Y [63:8], Q = \Controller.Interpreter.accumulator [63:8]). Adding EN signal on $auto$ff.cc:266:slice$3311 ($sdff) from module processorci_top (D = $flatten\Controller.\Interpreter.$procmux$1795_Y [7:0], Q = \Controller.Interpreter.accumulator [7:0]). Adding SRST signal on $flatten\Controller.\Interpreter.$procdff$2813 ($dff) from module processorci_top (D = $flatten\Controller.\Interpreter.$procmux$1805_Y, Q = \Controller.Interpreter.timeout_counter, rval = 0). Adding EN signal on $auto$ff.cc:266:slice$3326 ($sdff) from module processorci_top (D = $flatten\Controller.\Interpreter.$procmux$1805_Y, Q = \Controller.Interpreter.timeout_counter). Adding EN signal on $flatten\Controller.\Interpreter.$procdff$2812 ($dff) from module processorci_top (D = { 8'00000000 \Controller.Interpreter.communication_buffer [31:8] }, Q = \Controller.Interpreter.timeout). Adding EN signal on $flatten\Controller.\Interpreter.$procdff$2811 ($dff) from module processorci_top (D = $flatten\Controller.\Interpreter.$procmux$1846_Y, Q = \Controller.Interpreter.read_buffer). Adding SRST signal on $flatten\Controller.\Interpreter.$procdff$2810 ($dff) from module processorci_top (D = $flatten\Controller.\Interpreter.$procmux$1874_Y, Q = \Controller.Interpreter.communication_buffer, rval = 0). Adding EN signal on $auto$ff.cc:266:slice$3342 ($sdff) from module processorci_top (D = \Controller.Uart.read_data, Q = \Controller.Interpreter.communication_buffer). Adding EN signal on $flatten\Controller.\Interpreter.$procdff$2809 ($dff) from module processorci_top (D = $flatten\Controller.\Interpreter.$procmux$1899_Y, Q = \Controller.Interpreter.num_of_positions). Adding SRST signal on $flatten\Controller.\Interpreter.$procdff$2808 ($dff) from module processorci_top (D = $flatten\Controller.\Interpreter.$procmux$1921_Y, Q = \Controller.Interpreter.num_of_pages, rval = 24'000000000000000000000000). Adding EN signal on $auto$ff.cc:266:slice$3353 ($sdff) from module processorci_top (D = \Controller.Interpreter.communication_buffer [31:8], Q = \Controller.Interpreter.num_of_pages). Adding SRST signal on $flatten\Controller.\Interpreter.$procdff$2807 ($dff) from module processorci_top (D = $flatten\Controller.\Interpreter.$procmux$1927_Y, Q = \Controller.Interpreter.return_state, rval = 8'00000000). Adding EN signal on $auto$ff.cc:266:slice$3355 ($sdff) from module processorci_top (D = $flatten\Controller.\Interpreter.$procmux$1927_Y, Q = \Controller.Interpreter.return_state). Adding EN signal on $flatten\Controller.\Interpreter.$procdff$2806 ($dff) from module processorci_top (D = $flatten\Controller.\Interpreter.$procmux$1951_Y, Q = \Controller.Interpreter.memory_page_number). Adding SRST signal on $flatten\Controller.\Interpreter.$procdff$2805 ($dff) from module processorci_top (D = $flatten\Controller.\Interpreter.$procmux$1959_Y, Q = \Controller.Interpreter.memory_mux_selector, rval = 1'0). Adding EN signal on $auto$ff.cc:266:slice$3370 ($sdff) from module processorci_top (D = $flatten\Controller.\Interpreter.$procmux$1959_Y, Q = \Controller.Interpreter.memory_mux_selector). Adding SRST signal on $flatten\Controller.\Interpreter.$procdff$2804 ($dff) from module processorci_top (D = $flatten\Controller.\Interpreter.$procmux$1999_Y, Q = \Controller.Interpreter.end_position, rval = 0). Adding EN signal on $auto$ff.cc:266:slice$3374 ($sdff) from module processorci_top (D = $flatten\Controller.\Interpreter.$procmux$1999_Y, Q = \Controller.Interpreter.end_position). Adding SRST signal on $flatten\Controller.\Interpreter.$procdff$2802 ($dff) from module processorci_top (D = $flatten\Controller.\Interpreter.$procmux$2041_Y, Q = \Controller.Interpreter.bus_mode, rval = 1'0). Adding EN signal on $auto$ff.cc:266:slice$3378 ($sdff) from module processorci_top (D = $flatten\Controller.\Interpreter.$procmux$2041_Y, Q = \Controller.Interpreter.bus_mode). Adding SRST signal on $flatten\Controller.\Interpreter.$procdff$2801 ($dff) from module processorci_top (D = $flatten\Controller.\Interpreter.$procmux$1580_Y, Q = \Controller.Interpreter.reset_bus, rval = 1'1). Adding EN signal on $flatten\Controller.\Interpreter.$procdff$2800 ($dff) from module processorci_top (D = $flatten\Controller.\Interpreter.$procmux$2052_Y, Q = \Controller.Interpreter.num_of_cycles_to_pulse). Adding SRST signal on $flatten\Controller.\Interpreter.$procdff$2799 ($dff) from module processorci_top (D = $flatten\Controller.\Interpreter.$procmux$1685_Y, Q = \Controller.Interpreter.core_reset, rval = 1'0). Adding SRST signal on $flatten\Controller.\Interpreter.$procdff$2798 ($dff) from module processorci_top (D = $flatten\Controller.\Interpreter.$procmux$2062_Y, Q = \Controller.Interpreter.core_clk_enable, rval = 1'0). Adding EN signal on $auto$ff.cc:266:slice$3391 ($sdff) from module processorci_top (D = $flatten\Controller.\Interpreter.$procmux$2062_Y, Q = \Controller.Interpreter.core_clk_enable). Adding EN signal on $flatten\Controller.\Interpreter.$procdff$2797 ($dff) from module processorci_top (D = \Controller.Interpreter.read_buffer, Q = \Controller.Interpreter.communication_write_data). Adding SRST signal on $flatten\Controller.\Interpreter.$procdff$2796 ($dff) from module processorci_top (D = $flatten\Controller.\Interpreter.$procmux$1704_Y, Q = \Controller.Interpreter.communication_write, rval = 1'0). Adding SRST signal on $flatten\Controller.\Interpreter.$procdff$2795 ($dff) from module processorci_top (D = $flatten\Controller.\Interpreter.$procmux$1727_Y, Q = \Controller.Interpreter.communication_read, rval = 1'0). Adding EN signal on $flatten\Controller.\Interpreter.$procdff$2794 ($dff) from module processorci_top (D = $flatten\Controller.\Interpreter.$procmux$2116_Y, Q = \Controller.Interpreter.address). Adding SRST signal on $flatten\Controller.\Interpreter.$procdff$2793 ($dff) from module processorci_top (D = $flatten\Controller.\Interpreter.$procmux$1637_Y, Q = \Controller.Interpreter.write_pulse, rval = 1'0). Adding SRST signal on $flatten\Controller.\Interpreter.$procdff$2792 ($dff) from module processorci_top (D = $flatten\Controller.\Interpreter.$procmux$2170_Y, Q = \Controller.Interpreter.counter, rval = 8'00000000). Adding EN signal on $auto$ff.cc:266:slice$3416 ($sdff) from module processorci_top (D = $flatten\Controller.\Interpreter.$procmux$2170_Y, Q = \Controller.Interpreter.counter). Adding SRST signal on $flatten\Controller.\Interpreter.$procdff$2791 ($dff) from module processorci_top (D = $flatten\Controller.\Interpreter.$procmux$1480_Y, Q = \Controller.Interpreter.state, rval = 8'00000000). Adding SRST signal on $flatten\Controller.\Interpreter.$procdff$2790 ($dff) from module processorci_top (D = $flatten\Controller.\Interpreter.$procmux$1626_Y, Q = \Controller.Interpreter.memory_read, rval = 1'0). Adding SRST signal on $flatten\Controller.\Interpreter.$procdff$2789 ($dff) from module processorci_top (D = $flatten\Controller.\Interpreter.$procmux$1604_Y, Q = \Controller.Interpreter.memory_write, rval = 1'0). Adding EN signal on $flatten\Controller.\Interpreter.$procdff$2788 ($dff) from module processorci_top (D = $flatten\Controller.\Interpreter.$procmux$2194_Y, Q = \Controller.Interpreter.write_data). Adding SRST signal on $flatten\Controller.\ClkDivider.$procdff$2785 ($dff) from module processorci_top (D = $flatten\Controller.\ClkDivider.$procmux$1454_Y, Q = \Controller.ClkDivider.pulse_counter, rval = 0). Adding EN signal on $auto$ff.cc:266:slice$3430 ($sdff) from module processorci_top (D = $flatten\Controller.\ClkDivider.$procmux$1454_Y, Q = \Controller.ClkDivider.pulse_counter). Adding SRST signal on $flatten\Controller.$procdff$2839 ($dff) from module processorci_top (D = $flatten\Controller.$procmux$2405_Y, Q = \Controller.finish_execution, rval = 1'0). Adding EN signal on $auto$ff.cc:266:slice$3438 ($sdff) from module processorci_top (D = $flatten\Controller.$procmux$2405_Y, Q = \Controller.finish_execution). Setting constant 0-bit at position 24 on $auto$ff.cc:266:slice$3330 ($dffe) from module processorci_top. Setting constant 0-bit at position 25 on $auto$ff.cc:266:slice$3330 ($dffe) from module processorci_top. Setting constant 0-bit at position 26 on $auto$ff.cc:266:slice$3330 ($dffe) from module processorci_top. Setting constant 0-bit at position 27 on $auto$ff.cc:266:slice$3330 ($dffe) from module processorci_top. Setting constant 0-bit at position 28 on $auto$ff.cc:266:slice$3330 ($dffe) from module processorci_top. Setting constant 0-bit at position 29 on $auto$ff.cc:266:slice$3330 ($dffe) from module processorci_top. Setting constant 0-bit at position 30 on $auto$ff.cc:266:slice$3330 ($dffe) from module processorci_top. Setting constant 0-bit at position 31 on $auto$ff.cc:266:slice$3330 ($dffe) from module processorci_top. 18.13.7. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \processorci_top.. Removed 173 unused cells and 180 unused wires. <suppressed ~177 debug messages> 18.13.8. Executing OPT_EXPR pass (perform const folding). Optimizing module processorci_top. <suppressed ~30 debug messages> 18.13.9. Rerunning OPT passes. (Maybe there is more to do..) 18.13.10. Executing OPT_MUXTREE pass (detect dead branches in mux trees). Running muxtree optimizer on module \processorci_top.. Creating internal representation of mux trees. Evaluating internal representation of mux trees. Analyzing evaluation results. Removed 0 multiplexer ports. <suppressed ~110 debug messages> 18.13.11. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). Optimizing cells in module \processorci_top. New input vector for $reduce_or cell $auto$opt_dff.cc:254:combine_resets$3197: { \ResetBootSystem.reset_o \Controller.Uart.i_uart_rx.fsm_state [3:2] \Controller.Uart.i_uart_rx.fsm_state [0] } Optimizing cells in module \processorci_top. Performed a total of 1 changes. 18.13.12. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\processorci_top'. <suppressed ~102 debug messages> Removed a total of 34 cells. 18.13.13. Executing OPT_DFF pass (perform DFF optimizations). 18.13.14. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \processorci_top.. Removed 1 unused cells and 35 unused wires. <suppressed ~2 debug messages> 18.13.15. Executing OPT_EXPR pass (perform const folding). Optimizing module processorci_top. 18.13.16. Rerunning OPT passes. (Maybe there is more to do..) 18.13.17. Executing OPT_MUXTREE pass (detect dead branches in mux trees). Running muxtree optimizer on module \processorci_top.. Creating internal representation of mux trees. Evaluating internal representation of mux trees. Analyzing evaluation results. Removed 0 multiplexer ports. <suppressed ~110 debug messages> 18.13.18. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). Optimizing cells in module \processorci_top. Performed a total of 0 changes. 18.13.19. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\processorci_top'. Removed a total of 0 cells. 18.13.20. Executing OPT_DFF pass (perform DFF optimizations). 18.13.21. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \processorci_top.. 18.13.22. Executing OPT_EXPR pass (perform const folding). Optimizing module processorci_top. 18.13.23. Finished OPT passes. (There is nothing left to do.) 18.14. Executing WREDUCE pass (reducing word size of cells). Removed top 22 address bits (of 32) from memory init port processorci_top.$flatten\Controller.\Data_Memory.$auto$proc_memwr.cc:45:proc_memwr$2883 (Controller.Data_Memory.memory). Removed top 22 address bits (of 32) from memory read port processorci_top.$flatten\Controller.\Data_Memory.$memrd$\memory$/eda/processor-ci-controller/src/memory.v:21$727 (Controller.Data_Memory.memory). Removed top 22 address bits (of 32) from memory init port processorci_top.$flatten\Controller.\Memory.$auto$proc_memwr.cc:45:proc_memwr$2883 (Controller.Memory.memory). Removed top 22 address bits (of 32) from memory read port processorci_top.$flatten\Controller.\Memory.$memrd$\memory$/eda/processor-ci-controller/src/memory.v:21$727 (Controller.Memory.memory). Removed top 3 address bits (of 6) from memory init port processorci_top.$flatten\Controller.\Uart.\RX_FIFO.$auto$proc_memwr.cc:45:proc_memwr$2882 (Controller.Uart.RX_FIFO.memory). Removed top 3 address bits (of 6) from memory read port processorci_top.$flatten\Controller.\Uart.\RX_FIFO.$memrd$\memory$/eda/processor-ci-controller/src/fifo.v:30$917 (Controller.Uart.RX_FIFO.memory). Removed top 3 address bits (of 6) from memory init port processorci_top.$flatten\Controller.\Uart.\TX_FIFO.$auto$proc_memwr.cc:45:proc_memwr$2882 (Controller.Uart.TX_FIFO.memory). Removed top 3 address bits (of 6) from memory read port processorci_top.$flatten\Controller.\Uart.\TX_FIFO.$memrd$\memory$/eda/processor-ci-controller/src/fifo.v:30$917 (Controller.Uart.TX_FIFO.memory). Removed top 27 address bits (of 32) from memory init port processorci_top.$flatten\Core.\RegisterBank.$auto$proc_memwr.cc:45:proc_memwr$2885 (Core.RegisterBank.registers). Removed top 1 bits (of 2) from port B of cell processorci_top.$auto$fsm_map.cc:77:implement_pattern_cache$3030 ($eq). Removed top 1 bits (of 2) from port B of cell processorci_top.$auto$fsm_map.cc:77:implement_pattern_cache$3055 ($eq). Removed top 1 bits (of 2) from port B of cell processorci_top.$auto$opt_dff.cc:195:make_patterns_logic$3068 ($ne). Removed top 3 bits (of 4) from port B of cell processorci_top.$auto$opt_dff.cc:195:make_patterns_logic$3097 ($ne). Removed top 1 bits (of 2) from port B of cell processorci_top.$auto$fsm_map.cc:77:implement_pattern_cache$3005 ($eq). Removed top 31 bits (of 32) from port B of cell processorci_top.$flatten\Controller.\ClkDivider.$gt$/eda/processor-ci-controller/src/clk_divider.v:62$1018 ($gt). Removed top 3 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$eq$/eda/processor-ci-controller/src/interpreter.v:219$975 ($eq). Removed top 6 bits (of 32) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$add$/eda/processor-ci-controller/src/interpreter.v:302$979 ($add). Removed top 29 bits (of 32) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$add$/eda/processor-ci-controller/src/interpreter.v:364$982 ($add). Removed top 8 bits (of 32) from port A of cell processorci_top.$flatten\Controller.\Interpreter.$lt$/eda/processor-ci-controller/src/interpreter.v:455$991 ($lt). Removed top 8 bits (of 32) from port A of cell processorci_top.$flatten\Controller.\Interpreter.$eq$/eda/processor-ci-controller/src/interpreter.v:494$996 ($eq). Removed top 8 bits (of 32) from port A of cell processorci_top.$flatten\Controller.\Interpreter.$ge$/eda/processor-ci-controller/src/interpreter.v:511$998 ($ge). Removed top 3 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$1481_CMP0 ($eq). Removed top 3 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$1482_CMP0 ($eq). Removed top 7 bits (of 8) from mux cell processorci_top.$flatten\Controller.\Interpreter.$procmux$1484 ($mux). Removed top 3 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$1486_CMP0 ($eq). Removed top 4 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$1487_CMP0 ($eq). Removed top 1 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$1488_CMP0 ($eq). Removed top 3 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$1489_CMP0 ($eq). Removed top 3 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$1490_CMP0 ($eq). Removed top 5 bits (of 8) from mux cell processorci_top.$flatten\Controller.\Interpreter.$procmux$1492 ($mux). Removed top 3 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$1494_CMP0 ($eq). Removed top 3 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$1495_CMP0 ($eq). Removed top 1 bits (of 8) from mux cell processorci_top.$flatten\Controller.\Interpreter.$procmux$1497 ($mux). Removed top 3 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$1499_CMP0 ($eq). Removed top 1 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$1500_CMP0 ($eq). Removed top 5 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$1504_CMP0 ($eq). Removed top 6 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$1505_CMP0 ($eq). Removed top 4 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$1506_CMP0 ($eq). Removed top 4 bits (of 8) from mux cell processorci_top.$flatten\Controller.\Interpreter.$procmux$1508 ($mux). Removed top 4 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$1510_CMP0 ($eq). Removed top 1 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$1511_CMP0 ($eq). Removed top 4 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$1512_CMP0 ($eq). Removed top 6 bits (of 8) from mux cell processorci_top.$flatten\Controller.\Interpreter.$procmux$1514 ($mux). Removed top 4 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$1516_CMP0 ($eq). Removed top 4 bits (of 8) from mux cell processorci_top.$flatten\Controller.\Interpreter.$procmux$1518 ($mux). Removed top 4 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$1520_CMP0 ($eq). Removed top 1 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$1521_CMP0 ($eq). Removed top 1 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$1522_CMP0 ($eq). Removed top 1 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$1523_CMP0 ($eq). Removed top 5 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$1524_CMP0 ($eq). Removed top 1 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$1525_CMP0 ($eq). Removed top 1 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$1526_CMP0 ($eq). Removed top 7 bits (of 8) from mux cell processorci_top.$flatten\Controller.\Interpreter.$procmux$1528 ($mux). Removed top 5 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$1530_CMP0 ($eq). Removed top 1 bits (of 8) from mux cell processorci_top.$flatten\Controller.\Interpreter.$procmux$1532 ($mux). Removed top 1 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$1534_CMP0 ($eq). Removed top 4 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$1535_CMP0 ($eq). Removed top 6 bits (of 8) from mux cell processorci_top.$flatten\Controller.\Interpreter.$procmux$1537 ($mux). Removed top 4 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$1539_CMP0 ($eq). Removed top 1 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$1540_CMP0 ($eq). Removed top 1 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$1543_CMP0 ($eq). Removed top 1 bits (of 8) from mux cell processorci_top.$flatten\Controller.\Interpreter.$procmux$1542 ($pmux). Removed top 1 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$1544_CMP0 ($eq). Removed top 1 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$1545_CMP0 ($eq). Removed top 1 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$1546_CMP0 ($eq). Removed top 1 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$1547_CMP0 ($eq). Removed top 1 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$1548_CMP0 ($eq). Removed top 1 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$1549_CMP0 ($eq). Removed top 1 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$1550_CMP0 ($eq). Removed top 1 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$1551_CMP0 ($eq). Removed top 1 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$1552_CMP0 ($eq). Removed top 1 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$1553_CMP0 ($eq). Removed top 1 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$1554_CMP0 ($eq). Removed top 1 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$1555_CMP0 ($eq). Removed top 1 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$1556_CMP0 ($eq). Removed top 1 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$1557_CMP0 ($eq). Removed top 1 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$1558_CMP0 ($eq). Removed top 1 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$1559_CMP0 ($eq). Removed top 1 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$1560_CMP0 ($eq). Removed top 1 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$1561_CMP0 ($eq). Removed top 1 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$1562_CMP0 ($eq). Removed top 1 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$1563_CMP0 ($eq). Removed top 1 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$1564_CMP0 ($eq). Removed top 1 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$1565_CMP0 ($eq). Removed top 6 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$1566_CMP0 ($eq). Removed top 6 bits (of 8) from mux cell processorci_top.$flatten\Controller.\Interpreter.$procmux$1568 ($mux). Removed top 7 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$1570_CMP0 ($eq). Removed top 7 bits (of 8) from mux cell processorci_top.$flatten\Controller.\Interpreter.$procmux$1572 ($mux). Removed top 1 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$1606_CMP0 ($eq). Removed top 1 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$1607_CMP0 ($eq). Removed top 5 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$1608_CMP0 ($eq). Removed top 1 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$1641_CMP0 ($eq). Removed top 1 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$1796_CMP0 ($eq). Removed top 1 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$1797_CMP0 ($eq). Removed top 1 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$1798_CMP0 ($eq). Removed top 1 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$1841_CMP0 ($eq). Removed top 1 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$1967_CMP0 ($eq). Removed top 1 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$2000_CMP0 ($eq). Removed top 1 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$2001_CMP0 ($eq). Removed top 1 bits (of 2) from port B of cell processorci_top.$auto$opt_dff.cc:195:make_patterns_logic$3443 ($ne). Removed top 1 bits (of 3) from port B of cell processorci_top.$auto$opt_dff.cc:195:make_patterns_logic$3433 ($ne). Removed top 1 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$2074_CMP0 ($eq). Removed top 1 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$2075_CMP0 ($eq). Removed top 29 bits (of 32) from port B of cell processorci_top.$flatten\Controller.\Uart.$lt$/eda/processor-ci-controller/modules/uart.v:95$949 ($lt). Removed top 29 bits (of 32) from port B of cell processorci_top.$flatten\Controller.\Uart.$lt$/eda/processor-ci-controller/modules/uart.v:159$954 ($lt). Removed top 3 bits (of 4) from port B of cell processorci_top.$flatten\Controller.\Uart.$procmux$2253_CMP0 ($eq). Removed top 2 bits (of 4) from port B of cell processorci_top.$flatten\Controller.\Uart.$procmux$2259_CMP0 ($eq). Removed top 2 bits (of 4) from port B of cell processorci_top.$flatten\Controller.\Uart.$procmux$2260_CMP0 ($eq). Removed top 1 bits (of 4) from port B of cell processorci_top.$flatten\Controller.\Uart.$procmux$2272_CMP0 ($eq). Removed top 1 bits (of 4) from mux cell processorci_top.$flatten\Controller.\Uart.$procmux$2274 ($mux). Removed top 2 bits (of 4) from port B of cell processorci_top.$flatten\Controller.\Uart.$procmux$2323_CMP0 ($eq). Removed top 2 bits (of 4) from port B of cell processorci_top.$flatten\Controller.\Uart.$procmux$2324_CMP0 ($eq). Removed top 3 bits (of 4) from port B of cell processorci_top.$flatten\Controller.\Uart.$procmux$2338_CMP0 ($eq). Removed top 1 bits (of 4) from port B of cell processorci_top.$flatten\Controller.\Uart.$procmux$2346_CMP0 ($eq). Removed top 3 bits (of 4) from mux cell processorci_top.$flatten\Controller.\Uart.$procmux$2354 ($mux). Removed top 3 bits (of 6) from mux cell processorci_top.$flatten\Controller.\Uart.\TX_FIFO.$procmux$1165 ($mux). Removed top 3 bits (of 6) from mux cell processorci_top.$flatten\Controller.\Uart.\TX_FIFO.$procmux$1153 ($mux). Removed top 31 bits (of 32) from port B of cell processorci_top.$flatten\Controller.\Uart.\TX_FIFO.$sub$/eda/processor-ci-controller/src/fifo.v:47$937 ($sub). Removed top 25 bits (of 32) from port Y of cell processorci_top.$flatten\Controller.\Uart.\TX_FIFO.$sub$/eda/processor-ci-controller/src/fifo.v:47$937 ($sub). Removed top 26 bits (of 32) from mux cell processorci_top.$flatten\Controller.\Uart.\TX_FIFO.$ternary$/eda/processor-ci-controller/src/fifo.v:42$936 ($mux). Removed top 26 bits (of 32) from port Y of cell processorci_top.$flatten\Controller.\Uart.\TX_FIFO.$add$/eda/processor-ci-controller/src/fifo.v:42$935 ($add). Removed top 3 bits (of 6) from port B of cell processorci_top.$flatten\Controller.\Uart.\TX_FIFO.$eq$/eda/processor-ci-controller/src/fifo.v:42$934 ($eq). Removed top 26 bits (of 32) from mux cell processorci_top.$flatten\Controller.\Uart.\TX_FIFO.$ternary$/eda/processor-ci-controller/src/fifo.v:31$920 ($mux). Removed top 26 bits (of 32) from port Y of cell processorci_top.$flatten\Controller.\Uart.\TX_FIFO.$add$/eda/processor-ci-controller/src/fifo.v:31$919 ($add). Removed top 3 bits (of 6) from port B of cell processorci_top.$flatten\Controller.\Uart.\TX_FIFO.$eq$/eda/processor-ci-controller/src/fifo.v:31$918 ($eq). Removed top 3 bits (of 6) from mux cell processorci_top.$flatten\Controller.\Uart.\RX_FIFO.$procmux$1165 ($mux). Removed top 3 bits (of 6) from mux cell processorci_top.$flatten\Controller.\Uart.\RX_FIFO.$procmux$1153 ($mux). Removed top 31 bits (of 32) from port B of cell processorci_top.$flatten\Controller.\Uart.\RX_FIFO.$sub$/eda/processor-ci-controller/src/fifo.v:47$937 ($sub). Removed top 25 bits (of 32) from port Y of cell processorci_top.$flatten\Controller.\Uart.\RX_FIFO.$sub$/eda/processor-ci-controller/src/fifo.v:47$937 ($sub). Removed top 26 bits (of 32) from mux cell processorci_top.$flatten\Controller.\Uart.\RX_FIFO.$ternary$/eda/processor-ci-controller/src/fifo.v:42$936 ($mux). Removed top 26 bits (of 32) from port Y of cell processorci_top.$flatten\Controller.\Uart.\RX_FIFO.$add$/eda/processor-ci-controller/src/fifo.v:42$935 ($add). Removed top 3 bits (of 6) from port B of cell processorci_top.$flatten\Controller.\Uart.\RX_FIFO.$eq$/eda/processor-ci-controller/src/fifo.v:42$934 ($eq). Removed top 26 bits (of 32) from mux cell processorci_top.$flatten\Controller.\Uart.\RX_FIFO.$ternary$/eda/processor-ci-controller/src/fifo.v:31$920 ($mux). Removed top 26 bits (of 32) from port Y of cell processorci_top.$flatten\Controller.\Uart.\RX_FIFO.$add$/eda/processor-ci-controller/src/fifo.v:31$919 ($add). Removed top 3 bits (of 6) from port B of cell processorci_top.$flatten\Controller.\Uart.\RX_FIFO.$eq$/eda/processor-ci-controller/src/fifo.v:31$918 ($eq). Removed top 1 bits (of 2) from port B of cell processorci_top.$auto$fsm_map.cc:77:implement_pattern_cache$3016 ($eq). Removed top 30 bits (of 32) from mux cell processorci_top.$flatten\Controller.\Uart.\i_uart_rx.$ternary$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:120$1089 ($mux). Removed top 31 bits (of 32) from mux cell processorci_top.$flatten\Controller.\Uart.\i_uart_rx.$ternary$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:119$1088 ($mux). Removed top 30 bits (of 32) from mux cell processorci_top.$flatten\Controller.\Uart.\i_uart_rx.$ternary$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:118$1087 ($mux). Removed top 31 bits (of 32) from mux cell processorci_top.$flatten\Controller.\Uart.\i_uart_rx.$ternary$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:117$1086 ($mux). Removed top 2 bits (of 9) from port B of cell processorci_top.$flatten\Controller.\Uart.\i_uart_rx.$eq$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:110$1081 ($eq). Removed top 1 bits (of 9) from port B of cell processorci_top.$flatten\Controller.\Uart.\i_uart_rx.$eq$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:108$1079 ($eq). Removed top 2 bits (of 3) from port B of cell processorci_top.$flatten\Controller.\Uart.\i_uart_tx.$eq$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:152$1055 ($eq). Removed top 1 bits (of 3) from port B of cell processorci_top.$flatten\Controller.\Uart.\i_uart_tx.$eq$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:137$1047 ($eq). Removed top 1 bits (of 3) from port B of cell processorci_top.$flatten\Controller.\Uart.\i_uart_tx.$eq$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:135$1045 ($eq). Removed top 1 bits (of 3) from port B of cell processorci_top.$flatten\Controller.\Uart.\i_uart_tx.$ne$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:133$1042 ($ne). Removed top 1 bits (of 3) from port B of cell processorci_top.$flatten\Controller.\Uart.\i_uart_tx.$ne$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:133$1041 ($ne). Removed top 1 bits (of 3) from port B of cell processorci_top.$flatten\Controller.\Uart.\i_uart_tx.$eq$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:120$1037 ($eq). Removed top 30 bits (of 32) from mux cell processorci_top.$flatten\Controller.\Uart.\i_uart_tx.$ternary$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:103$1032 ($mux). Removed top 31 bits (of 32) from mux cell processorci_top.$flatten\Controller.\Uart.\i_uart_tx.$ternary$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:102$1031 ($mux). Removed top 30 bits (of 32) from mux cell processorci_top.$flatten\Controller.\Uart.\i_uart_tx.$ternary$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:101$1030 ($mux). Removed top 31 bits (of 32) from mux cell processorci_top.$flatten\Controller.\Uart.\i_uart_tx.$ternary$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:100$1029 ($mux). Removed top 3 bits (of 4) from port B of cell processorci_top.$flatten\Controller.\Uart.\i_uart_tx.$eq$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:94$1025 ($eq). Removed top 1 bits (of 9) from port B of cell processorci_top.$flatten\Controller.\Uart.\i_uart_tx.$eq$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:92$1023 ($eq). Removed top 22 bits (of 32) from mux cell processorci_top.$flatten\Controller.\Memory.$procmux$2396 ($mux). Removed top 22 bits (of 32) from mux cell processorci_top.$flatten\Controller.\Data_Memory.$procmux$2396 ($mux). Removed top 20 bits (of 32) from mux cell processorci_top.$flatten\Controller.$ternary$/eda/processor-ci-controller/src/controller.v:96$704 ($mux). Removed top 20 bits (of 32) from mux cell processorci_top.$flatten\Controller.$ternary$/eda/processor-ci-controller/src/controller.v:84$688 ($mux). Removed top 20 bits (of 32) from mux cell processorci_top.$flatten\Controller.$ternary$/eda/processor-ci-controller/src/controller.v:84$687 ($mux). Removed top 1 bits (of 2) from port B of cell processorci_top.$flatten\Core.\ForwardBMUX.$procmux$2462_CMP0 ($eq). Removed top 1 bits (of 2) from port B of cell processorci_top.$flatten\Core.\ForwardAMUX.$procmux$2462_CMP0 ($eq). Removed top 1 bits (of 2) from mux cell processorci_top.$flatten\Core.\Forwarding_Unit.$procmux$2487 ($mux). Removed top 1 bits (of 2) from mux cell processorci_top.$flatten\Core.\Forwarding_Unit.$procmux$2494 ($mux). Removed top 1 bits (of 2) from mux cell processorci_top.$flatten\Core.\Forwarding_Unit.$procmux$2502 ($mux). Removed top 1 bits (of 3) from port B of cell processorci_top.$flatten\Core.\Immediate_Generator.$procmux$2471_CMP0 ($eq). Removed top 2 bits (of 3) from port B of cell processorci_top.$flatten\Core.\Immediate_Generator.$procmux$2472_CMP0 ($eq). Removed top 2 bits (of 7) from port B of cell processorci_top.$flatten\Core.\Immediate_Generator.$procmux$2474_CMP0 ($eq). Removed top 1 bits (of 7) from port B of cell processorci_top.$flatten\Core.\Immediate_Generator.$procmux$2477_CMP0 ($eq). Removed top 5 bits (of 7) from port B of cell processorci_top.$flatten\Core.\Immediate_Generator.$procmux$2481_CMP0 ($eq). Removed top 1 bits (of 7) from port B of cell processorci_top.$flatten\Core.\Immediate_Generator.$procmux$2482_CMP0 ($eq). Removed top 2 bits (of 7) from port B of cell processorci_top.$flatten\Core.\Immediate_Generator.$procmux$2483_CMP0 ($eq). Removed top 1 bits (of 2) from port B of cell processorci_top.$flatten\Core.\Alu.$ne$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/src/core/alu.v:24$3 ($ne). Removed top 31 bits (of 32) from mux cell processorci_top.$flatten\Core.\Alu.$ternary$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/src/core/alu.v:37$11 ($mux). Removed top 31 bits (of 32) from mux cell processorci_top.$flatten\Core.\Alu.$ternary$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/src/core/alu.v:53$22 ($mux). Removed top 1 bits (of 4) from port B of cell processorci_top.$flatten\Core.\Alu.$procmux$2745_CMP0 ($eq). Removed top 1 bits (of 4) from port B of cell processorci_top.$flatten\Core.\Alu.$procmux$2746_CMP0 ($eq). Removed top 1 bits (of 4) from port B of cell processorci_top.$flatten\Core.\Alu.$procmux$2747_CMP0 ($eq). Removed top 2 bits (of 4) from port B of cell processorci_top.$flatten\Core.\Alu.$procmux$2748_CMP0 ($eq). Removed top 2 bits (of 4) from port B of cell processorci_top.$flatten\Core.\Alu.$procmux$2754_CMP0 ($eq). Removed top 3 bits (of 4) from port B of cell processorci_top.$flatten\Core.\Alu.$procmux$2755_CMP0 ($eq). Removed top 1 bits (of 2) from port B of cell processorci_top.$flatten\Core.\ALU_Control.$procmux$2740_CMP0 ($eq). Removed top 2 bits (of 4) from mux cell processorci_top.$flatten\Core.\ALU_Control.$procmux$2720 ($mux). Removed top 1 bits (of 3) from port B of cell processorci_top.$flatten\Core.\ALU_Control.$procmux$2724_CMP0 ($eq). Removed top 1 bits (of 3) from port B of cell processorci_top.$flatten\Core.\ALU_Control.$procmux$2725_CMP0 ($eq). Removed top 2 bits (of 3) from port B of cell processorci_top.$flatten\Core.\ALU_Control.$procmux$2726_CMP0 ($eq). Removed top 20 bits (of 32) from FF cell processorci_top.$auto$ff.cc:266:slice$3161 ($sdff). Removed top 5 bits (of 7) from port B of cell processorci_top.$flatten\Core.$procmux$2528_CMP0 ($eq). Removed top 1 bits (of 7) from port B of cell processorci_top.$flatten\Core.$procmux$2527_CMP0 ($eq). Removed top 2 bits (of 7) from port B of cell processorci_top.$flatten\Core.$procmux$2526_CMP0 ($eq). Removed top 1 bits (of 7) from port B of cell processorci_top.$flatten\Core.$procmux$2525_CMP0 ($eq). Removed top 2 bits (of 7) from port B of cell processorci_top.$flatten\Core.$procmux$2521_CMP0 ($eq). Removed top 1 bits (of 7) from port B of cell processorci_top.$flatten\Core.$procmux$2518_CMP0 ($eq). Removed top 1 bits (of 7) from port B of cell processorci_top.$flatten\Core.$eq$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/src/core/core.v:243$107 ($eq). Removed top 2 bits (of 7) from port B of cell processorci_top.$flatten\Core.$eq$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/src/core/core.v:241$103 ($eq). Removed top 2 bits (of 7) from port B of cell processorci_top.$flatten\Core.$eq$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/src/core/core.v:240$101 ($eq). Removed top 1 bits (of 7) from port B of cell processorci_top.$flatten\Core.$eq$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/src/core/core.v:239$100 ($eq). Removed top 1 bits (of 7) from port B of cell processorci_top.$flatten\Core.$eq$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/src/core/core.v:219$97 ($eq). Removed top 5 bits (of 7) from port B of cell processorci_top.$flatten\Core.$eq$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/src/core/core.v:216$96 ($eq). Removed top 1 bits (of 7) from port B of cell processorci_top.$flatten\Core.$eq$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/src/core/core.v:194$87 ($eq). Removed top 5 bits (of 7) from port B of cell processorci_top.$flatten\Core.$eq$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/src/core/core.v:194$86 ($eq). Removed top 29 bits (of 32) from port B of cell processorci_top.$flatten\Core.$add$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/src/core/core.v:112$49 ($add). Removed top 1 bits (of 2) from port B of cell processorci_top.$flatten\ResetBootSystem.$procmux$2422_CMP0 ($eq). Removed top 1 bits (of 6) from port B of cell processorci_top.$flatten\ResetBootSystem.$eq$/eda/processor-ci-controller/src/reset.v:43$674 ($eq). Removed top 31 bits (of 32) from port B of cell processorci_top.$flatten\ResetBootSystem.$add$/eda/processor-ci-controller/src/reset.v:42$673 ($add). Removed top 26 bits (of 32) from port Y of cell processorci_top.$flatten\ResetBootSystem.$add$/eda/processor-ci-controller/src/reset.v:42$673 ($add). Removed top 27 bits (of 32) from port B of cell processorci_top.$flatten\ResetBootSystem.$lt$/eda/processor-ci-controller/src/reset.v:41$672 ($lt). Removed top 20 bits (of 32) from FF cell processorci_top.$auto$ff.cc:266:slice$3139 ($sdffe). Removed top 20 bits (of 32) from FF cell processorci_top.$auto$ff.cc:266:slice$3128 ($sdffe). Removed top 1 bits (of 32) from FF cell processorci_top.$auto$ff.cc:266:slice$3101 ($sdffe). Removed top 20 bits (of 32) from wire processorci_top.$flatten\Controller.$ternary$/eda/processor-ci-controller/src/controller.v:84$687_Y. Removed top 22 bits (of 32) from wire processorci_top.$flatten\Controller.\Data_Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$725_ADDR[31:0]$731. Removed top 7 bits (of 8) from wire processorci_top.$flatten\Controller.\Interpreter.$procmux$1484_Y. Removed top 5 bits (of 8) from wire processorci_top.$flatten\Controller.\Interpreter.$procmux$1492_Y. Removed top 1 bits (of 8) from wire processorci_top.$flatten\Controller.\Interpreter.$procmux$1497_Y. Removed top 4 bits (of 8) from wire processorci_top.$flatten\Controller.\Interpreter.$procmux$1508_Y. Removed top 6 bits (of 8) from wire processorci_top.$flatten\Controller.\Interpreter.$procmux$1514_Y. Removed top 4 bits (of 8) from wire processorci_top.$flatten\Controller.\Interpreter.$procmux$1518_Y. Removed top 7 bits (of 8) from wire processorci_top.$flatten\Controller.\Interpreter.$procmux$1528_Y. Removed top 1 bits (of 8) from wire processorci_top.$flatten\Controller.\Interpreter.$procmux$1532_Y. Removed top 6 bits (of 8) from wire processorci_top.$flatten\Controller.\Interpreter.$procmux$1537_Y. Removed top 1 bits (of 8) from wire processorci_top.$flatten\Controller.\Interpreter.$procmux$1542_Y. Removed top 6 bits (of 8) from wire processorci_top.$flatten\Controller.\Interpreter.$procmux$1568_Y. Removed top 7 bits (of 8) from wire processorci_top.$flatten\Controller.\Interpreter.$procmux$1572_Y. Removed top 22 bits (of 32) from wire processorci_top.$flatten\Controller.\Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$725_ADDR[31:0]$731. Removed top 2 bits (of 32) from wire processorci_top.$flatten\Controller.\Memory.$memrd$\memory$/eda/processor-ci-controller/src/memory.v:21$727_DATA. Removed top 1 bits (of 4) from wire processorci_top.$flatten\Controller.\Uart.$procmux$2274_Y. Removed top 3 bits (of 4) from wire processorci_top.$flatten\Controller.\Uart.$procmux$2354_Y. Removed top 3 bits (of 6) from wire processorci_top.$flatten\Controller.\Uart.\RX_FIFO.$0$memwr$\memory$/eda/processor-ci-controller/src/fifo.v:41$912_ADDR[5:0]$922. Removed top 3 bits (of 6) from wire processorci_top.$flatten\Controller.\Uart.\RX_FIFO.$2$memwr$\memory$/eda/processor-ci-controller/src/fifo.v:41$912_ADDR[5:0]$931. Removed top 1 bits (of 8) from wire processorci_top.$flatten\Controller.\Uart.\RX_FIFO.$2$memwr$\memory$/eda/processor-ci-controller/src/fifo.v:41$912_DATA[7:0]$932. Removed top 26 bits (of 32) from wire processorci_top.$flatten\Controller.\Uart.\RX_FIFO.$add$/eda/processor-ci-controller/src/fifo.v:31$919_Y. Removed top 26 bits (of 32) from wire processorci_top.$flatten\Controller.\Uart.\RX_FIFO.$add$/eda/processor-ci-controller/src/fifo.v:42$935_Y. Removed top 26 bits (of 32) from wire processorci_top.$flatten\Controller.\Uart.\RX_FIFO.$ternary$/eda/processor-ci-controller/src/fifo.v:42$936_Y. Removed top 3 bits (of 6) from wire processorci_top.$flatten\Controller.\Uart.\TX_FIFO.$0$memwr$\memory$/eda/processor-ci-controller/src/fifo.v:41$912_ADDR[5:0]$922. Removed top 3 bits (of 6) from wire processorci_top.$flatten\Controller.\Uart.\TX_FIFO.$2$memwr$\memory$/eda/processor-ci-controller/src/fifo.v:41$912_ADDR[5:0]$931. Removed top 26 bits (of 32) from wire processorci_top.$flatten\Controller.\Uart.\TX_FIFO.$add$/eda/processor-ci-controller/src/fifo.v:31$919_Y. Removed top 26 bits (of 32) from wire processorci_top.$flatten\Controller.\Uart.\TX_FIFO.$add$/eda/processor-ci-controller/src/fifo.v:42$935_Y. Removed top 26 bits (of 32) from wire processorci_top.$flatten\Controller.\Uart.\TX_FIFO.$ternary$/eda/processor-ci-controller/src/fifo.v:42$936_Y. Removed top 31 bits (of 32) from wire processorci_top.$flatten\Controller.\Uart.\i_uart_rx.$ternary$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:117$1086_Y. Removed top 30 bits (of 32) from wire processorci_top.$flatten\Controller.\Uart.\i_uart_rx.$ternary$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:118$1087_Y. Removed top 31 bits (of 32) from wire processorci_top.$flatten\Controller.\Uart.\i_uart_rx.$ternary$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:119$1088_Y. Removed top 30 bits (of 32) from wire processorci_top.$flatten\Controller.\Uart.\i_uart_rx.$ternary$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:120$1089_Y. Removed top 31 bits (of 32) from wire processorci_top.$flatten\Controller.\Uart.\i_uart_tx.$ternary$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:100$1029_Y. Removed top 30 bits (of 32) from wire processorci_top.$flatten\Controller.\Uart.\i_uart_tx.$ternary$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:101$1030_Y. Removed top 31 bits (of 32) from wire processorci_top.$flatten\Controller.\Uart.\i_uart_tx.$ternary$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:102$1031_Y. Removed top 30 bits (of 32) from wire processorci_top.$flatten\Controller.\Uart.\i_uart_tx.$ternary$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:103$1032_Y. Removed top 2 bits (of 4) from wire processorci_top.$flatten\Core.\ALU_Control.$procmux$2720_Y. Removed top 31 bits (of 32) from wire processorci_top.$flatten\Core.\Alu.$eq$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/src/core/alu.v:45$17_Y. Removed top 31 bits (of 32) from wire processorci_top.$flatten\Core.\Alu.$ternary$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/src/core/alu.v:37$11_Y. Removed top 31 bits (of 32) from wire processorci_top.$flatten\Core.\Alu.$ternary$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/src/core/alu.v:53$22_Y. Removed top 1 bits (of 32) from wire processorci_top.$flatten\Core.\Alu.$xor$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/src/core/alu.v:43$16_Y. Removed top 1 bits (of 2) from wire processorci_top.$flatten\Core.\Forwarding_Unit.$2\op_rs1[1:0]. Removed top 1 bits (of 2) from wire processorci_top.$flatten\Core.\Forwarding_Unit.$3\op_rs1[1:0]. Removed top 1 bits (of 2) from wire processorci_top.$flatten\Core.\Forwarding_Unit.$3\op_rs2[1:0]. Removed top 26 bits (of 32) from wire processorci_top.$flatten\ResetBootSystem.$add$/eda/processor-ci-controller/src/reset.v:42$673_Y. 18.15. Executing PEEPOPT pass (run peephole optimizers). 18.16. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \processorci_top.. Removed 0 unused cells and 46 unused wires. <suppressed ~1 debug messages> 18.17. Executing SHARE pass (SAT-based resource sharing). Found 7 cells in module processorci_top that may be considered for resource sharing. Analyzing resource sharing options for $flatten\Core.\RegisterBank.$memrd$\registers$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/src/core/registers.v:23$152 ($memrd): Found 1 activation_patterns using ctrl signal { $flatten\Core.$logic_and$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/src/core/core.v:110$48_Y $flatten\Core.\RegisterBank.$logic_and$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/src/core/registers.v:21$151_Y }. Found 1 candidates: $flatten\Core.\RegisterBank.$memrd$\registers$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/src/core/registers.v:19$146 Analyzing resource sharing with $flatten\Core.\RegisterBank.$memrd$\registers$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/src/core/registers.v:19$146 ($memrd): Found 1 activation_patterns using ctrl signal { $flatten\Core.$logic_and$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/src/core/core.v:110$48_Y $flatten\Core.\RegisterBank.$logic_and$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/src/core/registers.v:17$145_Y }. Activation pattern for cell $flatten\Core.\RegisterBank.$memrd$\registers$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/src/core/registers.v:23$152: { $flatten\Core.$logic_and$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/src/core/core.v:110$48_Y $flatten\Core.\RegisterBank.$logic_and$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/src/core/registers.v:21$151_Y } = 2'10 Activation pattern for cell $flatten\Core.\RegisterBank.$memrd$\registers$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/src/core/registers.v:19$146: { $flatten\Core.$logic_and$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/src/core/core.v:110$48_Y $flatten\Core.\RegisterBank.$logic_and$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/src/core/registers.v:17$145_Y } = 2'10 Size of SAT problem: 0 cells, 450 variables, 1142 clauses According to the SAT solver this pair of cells can not be shared. Model from SAT solver: { $flatten\Core.$logic_and$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/src/core/core.v:110$48_Y $flatten\Core.\RegisterBank.$logic_and$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/src/core/registers.v:21$151_Y $flatten\Core.\RegisterBank.$logic_and$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/src/core/registers.v:17$145_Y } = 3'100 Analyzing resource sharing options for $flatten\Core.\RegisterBank.$memrd$\registers$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/src/core/registers.v:19$146 ($memrd): Found 1 activation_patterns using ctrl signal { $flatten\Core.$logic_and$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/src/core/core.v:110$48_Y $flatten\Core.\RegisterBank.$logic_and$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/src/core/registers.v:17$145_Y }. No candidates found. Analyzing resource sharing options for $flatten\Core.\Alu.$sshr$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/src/core/alu.v:51$20 ($sshr): Found 1 activation_patterns using ctrl signal $flatten\Core.\Alu.$procmux$2745_CMP. No candidates found. Analyzing resource sharing options for $flatten\Core.\Alu.$shr$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/src/core/alu.v:49$19 ($shr): Found 1 activation_patterns using ctrl signal $flatten\Core.\Alu.$procmux$2746_CMP. No candidates found. Analyzing resource sharing options for $flatten\Core.\Alu.$shl$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/src/core/alu.v:47$18 ($shl): Found 1 activation_patterns using ctrl signal $flatten\Core.\Alu.$procmux$2747_CMP. No candidates found. Analyzing resource sharing options for $flatten\Controller.\Memory.$memrd$\memory$/eda/processor-ci-controller/src/memory.v:21$727 ($memrd): Found 2 activation_patterns using ctrl signal { \Controller.Memory.memory_read $flatten\Controller.\Interpreter.$procmux$1524_CMP \Controller.Interpreter.address [31] \Controller.Interpreter.memory_mux_selector }. No candidates found. Analyzing resource sharing options for $flatten\Controller.\Data_Memory.$memrd$\memory$/eda/processor-ci-controller/src/memory.v:21$727 ($memrd): Found 1 activation_patterns using ctrl signal \Controller.Data_Memory.memory_read. No candidates found. 18.18. Executing TECHMAP pass (map to technology primitives). 18.18.1. Executing Verilog-2005 frontend: /eda/oss-cad-suite/lib/../share/yosys/cmp2lut.v Parsing Verilog input from `/eda/oss-cad-suite/lib/../share/yosys/cmp2lut.v' to AST representation. Generating RTLIL representation for module `\_90_lut_cmp_'. Successfully finished Verilog frontend. 18.18.2. Continuing TECHMAP pass. Using template $paramod$141b0f41d8ab4b936f42c52ead39f1f9a7c93200\_90_lut_cmp_ for cells of type $lt. No more expansions possible. <suppressed ~197 debug messages> 18.19. Executing OPT_EXPR pass (perform const folding). Optimizing module processorci_top. 18.20. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \processorci_top.. Removed 0 unused cells and 6 unused wires. <suppressed ~1 debug messages> 18.21. Executing TECHMAP pass (map to technology primitives). 18.21.1. Executing Verilog-2005 frontend: /eda/oss-cad-suite/lib/../share/yosys/mul2dsp.v Parsing Verilog input from `/eda/oss-cad-suite/lib/../share/yosys/mul2dsp.v' to AST representation. Generating RTLIL representation for module `\_80_mul'. Generating RTLIL representation for module `\_90_soft_mul'. Successfully finished Verilog frontend. 18.21.2. Executing Verilog-2005 frontend: /eda/oss-cad-suite/lib/../share/yosys/ecp5/dsp_map.v Parsing Verilog input from `/eda/oss-cad-suite/lib/../share/yosys/ecp5/dsp_map.v' to AST representation. Generating RTLIL representation for module `\$__MUL18X18'. Successfully finished Verilog frontend. 18.21.3. Continuing TECHMAP pass. No more expansions possible. <suppressed ~5 debug messages> 18.22. Executing ALUMACC pass (create $alu and $macc cells). Extracting $alu and $macc cells in module processorci_top: creating $macc model for $flatten\Controller.\ClkDivider.$sub$/eda/processor-ci-controller/src/clk_divider.v:63$1019 ($sub). creating $macc model for $flatten\Controller.\Interpreter.$add$/eda/processor-ci-controller/src/interpreter.v:218$974 ($add). creating $macc model for $flatten\Controller.\Interpreter.$add$/eda/processor-ci-controller/src/interpreter.v:280$978 ($add). creating $macc model for $flatten\Controller.\Interpreter.$add$/eda/processor-ci-controller/src/interpreter.v:302$979 ($add). creating $macc model for $flatten\Controller.\Interpreter.$add$/eda/processor-ci-controller/src/interpreter.v:364$982 ($add). creating $macc model for $flatten\Controller.\Interpreter.$add$/eda/processor-ci-controller/src/interpreter.v:454$989 ($add). creating $macc model for $flatten\Controller.\Interpreter.$add$/eda/processor-ci-controller/src/interpreter.v:464$993 ($add). creating $macc model for $flatten\Controller.\Interpreter.$sub$/eda/processor-ci-controller/src/interpreter.v:361$981 ($sub). creating $macc model for $flatten\Controller.\Uart.$add$/eda/processor-ci-controller/modules/uart.v:163$956 ($add). creating $macc model for $flatten\Controller.\Uart.$add$/eda/processor-ci-controller/modules/uart.v:98$951 ($add). creating $macc model for $flatten\Controller.\Uart.\RX_FIFO.$add$/eda/processor-ci-controller/src/fifo.v:31$919 ($add). creating $macc model for $flatten\Controller.\Uart.\RX_FIFO.$add$/eda/processor-ci-controller/src/fifo.v:42$935 ($add). creating $macc model for $flatten\Controller.\Uart.\RX_FIFO.$sub$/eda/processor-ci-controller/src/fifo.v:47$937 ($sub). creating $macc model for $flatten\Controller.\Uart.\TX_FIFO.$add$/eda/processor-ci-controller/src/fifo.v:31$919 ($add). creating $macc model for $flatten\Controller.\Uart.\TX_FIFO.$add$/eda/processor-ci-controller/src/fifo.v:42$935 ($add). creating $macc model for $flatten\Controller.\Uart.\TX_FIFO.$sub$/eda/processor-ci-controller/src/fifo.v:47$937 ($sub). creating $macc model for $flatten\Controller.\Uart.\i_uart_rx.$add$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:153$1100 ($add). creating $macc model for $flatten\Controller.\Uart.\i_uart_rx.$add$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:178$1111 ($add). creating $macc model for $flatten\Controller.\Uart.\i_uart_tx.$add$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:138$1049 ($add). creating $macc model for $flatten\Controller.\Uart.\i_uart_tx.$add$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:155$1060 ($add). creating $macc model for $flatten\Core.$add$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/src/core/core.v:112$49 ($add). creating $macc model for $flatten\Core.$add$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/src/core/core.v:171$78 ($add). creating $macc model for $flatten\Core.$add$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/src/core/core.v:86$38 ($add). creating $macc model for $flatten\Core.$add$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/src/core/core.v:87$41 ($add). creating $macc model for $flatten\Core.$add$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/src/core/core.v:88$42 ($add). creating $macc model for $flatten\Core.\Alu.$add$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/src/core/alu.v:33$8 ($add). creating $macc model for $flatten\Core.\Alu.$sub$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/src/core/alu.v:35$9 ($sub). creating $macc model for $flatten\ResetBootSystem.$add$/eda/processor-ci-controller/src/reset.v:42$673 ($add). creating $alu model for $macc $flatten\ResetBootSystem.$add$/eda/processor-ci-controller/src/reset.v:42$673. creating $alu model for $macc $flatten\Core.\Alu.$sub$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/src/core/alu.v:35$9. creating $alu model for $macc $flatten\Core.\Alu.$add$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/src/core/alu.v:33$8. creating $alu model for $macc $flatten\Core.$add$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/src/core/core.v:88$42. creating $alu model for $macc $flatten\Core.$add$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/src/core/core.v:87$41. creating $alu model for $macc $flatten\Core.$add$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/src/core/core.v:86$38. creating $alu model for $macc $flatten\Core.$add$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/src/core/core.v:171$78. creating $alu model for $macc $flatten\Core.$add$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/src/core/core.v:112$49. creating $alu model for $macc $flatten\Controller.\Uart.\i_uart_tx.$add$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:155$1060. creating $alu model for $macc $flatten\Controller.\Uart.\i_uart_tx.$add$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:138$1049. creating $alu model for $macc $flatten\Controller.\Uart.\i_uart_rx.$add$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:178$1111. creating $alu model for $macc $flatten\Controller.\Uart.\i_uart_rx.$add$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:153$1100. creating $alu model for $macc $flatten\Controller.\Uart.\TX_FIFO.$sub$/eda/processor-ci-controller/src/fifo.v:47$937. creating $alu model for $macc $flatten\Controller.\Uart.\TX_FIFO.$add$/eda/processor-ci-controller/src/fifo.v:42$935. creating $alu model for $macc $flatten\Controller.\Uart.\TX_FIFO.$add$/eda/processor-ci-controller/src/fifo.v:31$919. creating $alu model for $macc $flatten\Controller.\Uart.\RX_FIFO.$sub$/eda/processor-ci-controller/src/fifo.v:47$937. creating $alu model for $macc $flatten\Controller.\Uart.\RX_FIFO.$add$/eda/processor-ci-controller/src/fifo.v:42$935. creating $alu model for $macc $flatten\Controller.\Uart.\RX_FIFO.$add$/eda/processor-ci-controller/src/fifo.v:31$919. creating $alu model for $macc $flatten\Controller.\Uart.$add$/eda/processor-ci-controller/modules/uart.v:98$951. creating $alu model for $macc $flatten\Controller.\Uart.$add$/eda/processor-ci-controller/modules/uart.v:163$956. creating $alu model for $macc $flatten\Controller.\Interpreter.$sub$/eda/processor-ci-controller/src/interpreter.v:361$981. creating $alu model for $macc $flatten\Controller.\Interpreter.$add$/eda/processor-ci-controller/src/interpreter.v:464$993. creating $alu model for $macc $flatten\Controller.\Interpreter.$add$/eda/processor-ci-controller/src/interpreter.v:454$989. creating $alu model for $macc $flatten\Controller.\Interpreter.$add$/eda/processor-ci-controller/src/interpreter.v:364$982. creating $alu model for $macc $flatten\Controller.\Interpreter.$add$/eda/processor-ci-controller/src/interpreter.v:302$979. creating $alu model for $macc $flatten\Controller.\Interpreter.$add$/eda/processor-ci-controller/src/interpreter.v:280$978. creating $alu model for $macc $flatten\Controller.\Interpreter.$add$/eda/processor-ci-controller/src/interpreter.v:218$974. creating $alu model for $macc $flatten\Controller.\ClkDivider.$sub$/eda/processor-ci-controller/src/clk_divider.v:63$1019. creating $alu model for $flatten\Controller.\ClkDivider.$gt$/eda/processor-ci-controller/src/clk_divider.v:62$1018 ($gt): new $alu creating $alu model for $flatten\Controller.\Interpreter.$ge$/eda/processor-ci-controller/src/interpreter.v:511$998 ($ge): new $alu creating $alu model for $flatten\Controller.\Interpreter.$lt$/eda/processor-ci-controller/src/interpreter.v:455$991 ($lt): merged with $flatten\Controller.\Interpreter.$ge$/eda/processor-ci-controller/src/interpreter.v:511$998. creating $alu model for $flatten\Core.\Alu.$ge$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/src/core/alu.v:53$21 ($ge): merged with $flatten\Core.\Alu.$sub$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/src/core/alu.v:35$9. creating $alu model for $flatten\Core.\Alu.$lt$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/src/core/alu.v:37$10 ($lt): merged with $flatten\Core.\Alu.$sub$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/src/core/alu.v:35$9. creating $alu model for $flatten\ResetBootSystem.$lt$/eda/processor-ci-controller/src/reset.v:41$672 ($lt): new $alu creating $alu model for $flatten\Controller.\Interpreter.$eq$/eda/processor-ci-controller/src/interpreter.v:494$996 ($eq): merged with $flatten\Controller.\Interpreter.$ge$/eda/processor-ci-controller/src/interpreter.v:511$998. creating $alu model for $flatten\Core.\Alu.$eq$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/src/core/alu.v:45$17 ($eq): merged with $flatten\Core.\Alu.$sub$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/src/core/alu.v:35$9. creating $alu model for $flatten\ResetBootSystem.$eq$/eda/processor-ci-controller/src/reset.v:43$674 ($eq): merged with $flatten\ResetBootSystem.$lt$/eda/processor-ci-controller/src/reset.v:41$672. creating $alu cell for $flatten\ResetBootSystem.$lt$/eda/processor-ci-controller/src/reset.v:41$672, $flatten\ResetBootSystem.$eq$/eda/processor-ci-controller/src/reset.v:43$674: $auto$alumacc.cc:485:replace_alu$3500 creating $alu cell for $flatten\Controller.\Interpreter.$ge$/eda/processor-ci-controller/src/interpreter.v:511$998, $flatten\Controller.\Interpreter.$lt$/eda/processor-ci-controller/src/interpreter.v:455$991, $flatten\Controller.\Interpreter.$eq$/eda/processor-ci-controller/src/interpreter.v:494$996: $auto$alumacc.cc:485:replace_alu$3511 creating $alu cell for $flatten\Controller.\ClkDivider.$gt$/eda/processor-ci-controller/src/clk_divider.v:62$1018: $auto$alumacc.cc:485:replace_alu$3524 creating $alu cell for $flatten\Controller.\ClkDivider.$sub$/eda/processor-ci-controller/src/clk_divider.v:63$1019: $auto$alumacc.cc:485:replace_alu$3529 creating $alu cell for $flatten\Controller.\Interpreter.$add$/eda/processor-ci-controller/src/interpreter.v:218$974: $auto$alumacc.cc:485:replace_alu$3532 creating $alu cell for $flatten\Controller.\Interpreter.$add$/eda/processor-ci-controller/src/interpreter.v:280$978: $auto$alumacc.cc:485:replace_alu$3535 creating $alu cell for $flatten\Controller.\Interpreter.$add$/eda/processor-ci-controller/src/interpreter.v:302$979: $auto$alumacc.cc:485:replace_alu$3538 creating $alu cell for $flatten\Controller.\Interpreter.$add$/eda/processor-ci-controller/src/interpreter.v:364$982: $auto$alumacc.cc:485:replace_alu$3541 creating $alu cell for $flatten\Controller.\Interpreter.$add$/eda/processor-ci-controller/src/interpreter.v:454$989: $auto$alumacc.cc:485:replace_alu$3544 creating $alu cell for $flatten\Controller.\Interpreter.$add$/eda/processor-ci-controller/src/interpreter.v:464$993: $auto$alumacc.cc:485:replace_alu$3547 creating $alu cell for $flatten\Controller.\Interpreter.$sub$/eda/processor-ci-controller/src/interpreter.v:361$981: $auto$alumacc.cc:485:replace_alu$3550 creating $alu cell for $flatten\Controller.\Uart.$add$/eda/processor-ci-controller/modules/uart.v:163$956: $auto$alumacc.cc:485:replace_alu$3553 creating $alu cell for $flatten\Controller.\Uart.$add$/eda/processor-ci-controller/modules/uart.v:98$951: $auto$alumacc.cc:485:replace_alu$3556 creating $alu cell for $flatten\Controller.\Uart.\RX_FIFO.$add$/eda/processor-ci-controller/src/fifo.v:31$919: $auto$alumacc.cc:485:replace_alu$3559 creating $alu cell for $flatten\Controller.\Uart.\RX_FIFO.$add$/eda/processor-ci-controller/src/fifo.v:42$935: $auto$alumacc.cc:485:replace_alu$3562 creating $alu cell for $flatten\Controller.\Uart.\RX_FIFO.$sub$/eda/processor-ci-controller/src/fifo.v:47$937: $auto$alumacc.cc:485:replace_alu$3565 creating $alu cell for $flatten\Controller.\Uart.\TX_FIFO.$add$/eda/processor-ci-controller/src/fifo.v:31$919: $auto$alumacc.cc:485:replace_alu$3568 creating $alu cell for $flatten\Controller.\Uart.\TX_FIFO.$add$/eda/processor-ci-controller/src/fifo.v:42$935: $auto$alumacc.cc:485:replace_alu$3571 creating $alu cell for $flatten\Controller.\Uart.\TX_FIFO.$sub$/eda/processor-ci-controller/src/fifo.v:47$937: $auto$alumacc.cc:485:replace_alu$3574 creating $alu cell for $flatten\Controller.\Uart.\i_uart_rx.$add$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:153$1100: $auto$alumacc.cc:485:replace_alu$3577 creating $alu cell for $flatten\Controller.\Uart.\i_uart_rx.$add$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:178$1111: $auto$alumacc.cc:485:replace_alu$3580 creating $alu cell for $flatten\Controller.\Uart.\i_uart_tx.$add$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:138$1049: $auto$alumacc.cc:485:replace_alu$3583 creating $alu cell for $flatten\Controller.\Uart.\i_uart_tx.$add$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:155$1060: $auto$alumacc.cc:485:replace_alu$3586 creating $alu cell for $flatten\Core.$add$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/src/core/core.v:112$49: $auto$alumacc.cc:485:replace_alu$3589 creating $alu cell for $flatten\Core.$add$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/src/core/core.v:171$78: $auto$alumacc.cc:485:replace_alu$3592 creating $alu cell for $flatten\Core.$add$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/src/core/core.v:86$38: $auto$alumacc.cc:485:replace_alu$3595 creating $alu cell for $flatten\Core.$add$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/src/core/core.v:87$41: $auto$alumacc.cc:485:replace_alu$3598 creating $alu cell for $flatten\Core.$add$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/src/core/core.v:88$42: $auto$alumacc.cc:485:replace_alu$3601 creating $alu cell for $flatten\Core.\Alu.$add$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/src/core/alu.v:33$8: $auto$alumacc.cc:485:replace_alu$3604 creating $alu cell for $flatten\Core.\Alu.$sub$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/src/core/alu.v:35$9, $flatten\Core.\Alu.$ge$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/src/core/alu.v:53$21, $flatten\Core.\Alu.$lt$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/src/core/alu.v:37$10, $flatten\Core.\Alu.$eq$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/src/core/alu.v:45$17: $auto$alumacc.cc:485:replace_alu$3607 creating $alu cell for $flatten\ResetBootSystem.$add$/eda/processor-ci-controller/src/reset.v:42$673: $auto$alumacc.cc:485:replace_alu$3620 created 31 $alu and 0 $macc cells. 18.23. Executing OPT pass (performing simple optimizations). 18.23.1. Executing OPT_EXPR pass (perform const folding). Optimizing module processorci_top. <suppressed ~4 debug messages> 18.23.2. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\processorci_top'. Removed a total of 0 cells. 18.23.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees). Running muxtree optimizer on module \processorci_top.. Creating internal representation of mux trees. Evaluating internal representation of mux trees. Analyzing evaluation results. Removed 0 multiplexer ports. <suppressed ~110 debug messages> 18.23.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). Optimizing cells in module \processorci_top. Performed a total of 0 changes. 18.23.5. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\processorci_top'. <suppressed ~9 debug messages> Removed a total of 3 cells. 18.23.6. Executing OPT_DFF pass (perform DFF optimizations). 18.23.7. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \processorci_top.. Removed 0 unused cells and 12 unused wires. <suppressed ~1 debug messages> 18.23.8. Executing OPT_EXPR pass (perform const folding). Optimizing module processorci_top. 18.23.9. Rerunning OPT passes. (Maybe there is more to do..) 18.23.10. Executing OPT_MUXTREE pass (detect dead branches in mux trees). Running muxtree optimizer on module \processorci_top.. Creating internal representation of mux trees. Evaluating internal representation of mux trees. Analyzing evaluation results. Removed 0 multiplexer ports. <suppressed ~109 debug messages> 18.23.11. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). Optimizing cells in module \processorci_top. Performed a total of 0 changes. 18.23.12. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\processorci_top'. Removed a total of 0 cells. 18.23.13. Executing OPT_DFF pass (perform DFF optimizations). 18.23.14. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \processorci_top.. 18.23.15. Executing OPT_EXPR pass (perform const folding). Optimizing module processorci_top. 18.23.16. Finished OPT passes. (There is nothing left to do.) 18.24. Executing MEMORY pass. 18.24.1. Executing OPT_MEM pass (optimize memories). Performed a total of 0 transformations. 18.24.2. Executing OPT_MEM_PRIORITY pass (removing unnecessary memory write priority relations). Performed a total of 0 transformations. 18.24.3. Executing OPT_MEM_FEEDBACK pass (finding memory read-to-write feedback paths). Analyzing processorci_top.Controller.Data_Memory.memory write port 0. Analyzing processorci_top.Controller.Memory.memory write port 0. Analyzing processorci_top.Controller.Uart.RX_FIFO.memory write port 0. Analyzing processorci_top.Controller.Uart.TX_FIFO.memory write port 0. Analyzing processorci_top.Core.RegisterBank.registers write port 0. Analyzing processorci_top.Core.RegisterBank.registers write port 1. 18.24.4. Executing MEMORY_BMUX2ROM pass (converting muxes to ROMs). 18.24.5. Executing MEMORY_DFF pass (merging $dff cells to $memrd). Checking read port `\Controller.Data_Memory.memory'[0] in module `\processorci_top': no output FF found. Checking read port `\Controller.Memory.memory'[0] in module `\processorci_top': no output FF found. Checking read port `\Controller.Uart.RX_FIFO.memory'[0] in module `\processorci_top': merging output FF to cell. Write port 0: non-transparent. Checking read port `\Controller.Uart.TX_FIFO.memory'[0] in module `\processorci_top': merging output FF to cell. Write port 0: non-transparent. Checking read port `\Core.RegisterBank.registers'[0] in module `\processorci_top': FF found, but with a mux select that doesn't seem to correspond to transparency logic. Checking read port `\Core.RegisterBank.registers'[1] in module `\processorci_top': FF found, but with a mux select that doesn't seem to correspond to transparency logic. Checking read port address `\Controller.Data_Memory.memory'[0] in module `\processorci_top': no address FF found. Checking read port address `\Controller.Memory.memory'[0] in module `\processorci_top': no address FF found. Checking read port address `\Core.RegisterBank.registers'[0] in module `\processorci_top': merged address FF to cell. Checking read port address `\Core.RegisterBank.registers'[1] in module `\processorci_top': merged address FF to cell. 18.24.6. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \processorci_top.. Removed 2 unused cells and 18 unused wires. <suppressed ~3 debug messages> 18.24.7. Executing MEMORY_SHARE pass (consolidating $memrd/$memwr cells). Consolidating read ports of memory processorci_top.Core.RegisterBank.registers by address: Consolidating write ports of memory processorci_top.Core.RegisterBank.registers by address: 18.24.8. Executing OPT_MEM_WIDEN pass (optimize memories where all ports are wide). Performed a total of 0 transformations. 18.24.9. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \processorci_top.. 18.24.10. Executing MEMORY_COLLECT pass (generating $mem cells). 18.25. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \processorci_top.. 18.26. Executing MEMORY_LIBMAP pass (mapping memories to cells). mapping memory processorci_top.Controller.Data_Memory.memory via $__TRELLIS_DPR16X4_ mapping memory processorci_top.Controller.Memory.memory via $__TRELLIS_DPR16X4_ mapping memory processorci_top.Controller.Uart.RX_FIFO.memory via $__TRELLIS_DPR16X4_ Extracted data FF from read port 0 of processorci_top.Controller.Uart.RX_FIFO.memory: $\Controller.Uart.RX_FIFO.memory$rdreg[0] mapping memory processorci_top.Controller.Uart.TX_FIFO.memory via $__TRELLIS_DPR16X4_ Extracted data FF from read port 0 of processorci_top.Controller.Uart.TX_FIFO.memory: $\Controller.Uart.TX_FIFO.memory$rdreg[0] using FF mapping for memory processorci_top.Core.RegisterBank.registers <suppressed ~1170 debug messages> 18.27. Executing TECHMAP pass (map to technology primitives). 18.27.1. Executing Verilog-2005 frontend: /eda/oss-cad-suite/lib/../share/yosys/ecp5/lutrams_map.v Parsing Verilog input from `/eda/oss-cad-suite/lib/../share/yosys/ecp5/lutrams_map.v' to AST representation. Generating RTLIL representation for module `\$__TRELLIS_DPR16X4_'. Successfully finished Verilog frontend. 18.27.2. Executing Verilog-2005 frontend: /eda/oss-cad-suite/lib/../share/yosys/ecp5/brams_map.v Parsing Verilog input from `/eda/oss-cad-suite/lib/../share/yosys/ecp5/brams_map.v' to AST representation. Generating RTLIL representation for module `\$__ECP5_DP16KD_'. Generating RTLIL representation for module `\$__ECP5_PDPW16KD_'. Successfully finished Verilog frontend. 18.27.3. Continuing TECHMAP pass. Using template $paramod$04778961cc1285a5efea28f98f28381eb2862208\$__TRELLIS_DPR16X4_ for cells of type $__TRELLIS_DPR16X4_. No more expansions possible. <suppressed ~1046 debug messages> 18.28. Executing OPT pass (performing simple optimizations). 18.28.1. Executing OPT_EXPR pass (perform const folding). Optimizing module processorci_top. <suppressed ~220 debug messages> 18.28.2. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\processorci_top'. Removed a total of 0 cells. 18.28.3. Executing OPT_DFF pass (perform DFF optimizations). Adding EN signal on $flatten\ResetBootSystem.$procdff$2841 ($dff) from module processorci_top (D = $flatten\ResetBootSystem.$0\state[1:0], Q = \ResetBootSystem.state). Adding SRST signal on $auto$ff.cc:266:slice$3363 ($dffe) from module processorci_top (D = $flatten\Controller.\Interpreter.$add$/eda/processor-ci-controller/src/interpreter.v:464$993_Y, Q = \Controller.Interpreter.memory_page_number, rval = 24'000000000000000000000000). Adding EN signal on $auto$ff.cc:266:slice$3302 ($dffe) from module processorci_top (D = $flatten\Controller.\Interpreter.$procmux$1752_Y [1:0], Q = \Controller.Interpreter.temp_buffer [1:0]). Adding EN signal on $auto$ff.cc:266:slice$3093 ($sdffe) from module processorci_top (D = $flatten\Core.$procmux$2711_Y [1:0], Q = \Core.PC [1:0]). Adding SRST signal on $auto$ff.cc:266:slice$3062 ($dffe) from module processorci_top (D = $flatten\ResetBootSystem.$procmux$2419_Y, Q = \ResetBootSystem.counter, rval = 6'000000). 18.28.4. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \processorci_top.. Removed 5 unused cells and 7288 unused wires. <suppressed ~6 debug messages> 18.28.5. Rerunning OPT passes. (Removed registers in this run.) 18.28.6. Executing OPT_EXPR pass (perform const folding). Optimizing module processorci_top. <suppressed ~6 debug messages> 18.28.7. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\processorci_top'. Removed a total of 0 cells. 18.28.8. Executing OPT_DFF pass (perform DFF optimizations). Adding SRST signal on $auto$ff.cc:266:slice$5997 ($sdffce) from module processorci_top (D = $auto$wreduce.cc:461:run$3492 [5:0], Q = \ResetBootSystem.counter, rval = 6'000000). 18.28.9. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \processorci_top.. Removed 3 unused cells and 5 unused wires. <suppressed ~4 debug messages> 18.28.10. Rerunning OPT passes. (Removed registers in this run.) 18.28.11. Executing OPT_EXPR pass (perform const folding). Optimizing module processorci_top. 18.28.12. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\processorci_top'. Removed a total of 0 cells. 18.28.13. Executing OPT_DFF pass (perform DFF optimizations). 18.28.14. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \processorci_top.. 18.28.15. Finished fast OPT passes. 18.29. Executing MEMORY_MAP pass (converting memories to logic and flip-flops). Mapping memory \Core.RegisterBank.registers in module \processorci_top: created 32 $dff cells and 0 static cells of width 32. Extracted addr FF from read port 0 of processorci_top.Core.RegisterBank.registers: $\Core.RegisterBank.registers$rdreg[0] Extracted addr FF from read port 1 of processorci_top.Core.RegisterBank.registers: $\Core.RegisterBank.registers$rdreg[1] read interface: 2 $dff and 62 $mux cells. write interface: 64 write mux blocks. 18.30. Executing OPT pass (performing simple optimizations). 18.30.1. Executing OPT_EXPR pass (perform const folding). Optimizing module processorci_top. <suppressed ~88 debug messages> 18.30.2. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\processorci_top'. Removed a total of 0 cells. 18.30.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees). Running muxtree optimizer on module \processorci_top.. Creating internal representation of mux trees. Evaluating internal representation of mux trees. Analyzing evaluation results. dead port 1/2 on $mux $memory\Core.RegisterBank.registers$wrmux[0][0][0]$6273. dead port 2/2 on $mux $memory\Core.RegisterBank.registers$wrmux[0][0][0]$6273. Removed 2 multiplexer ports. <suppressed ~105 debug messages> 18.30.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). Optimizing cells in module \processorci_top. New input vector for $reduce_and cell $auto$opt_dff.cc:220:make_patterns_logic$5995: { $auto$opt_dff.cc:194:make_patterns_logic$5992 $auto$opt_dff.cc:194:make_patterns_logic$3096 $auto$opt_dff.cc:194:make_patterns_logic$3083 } New input vector for $reduce_and cell $auto$opt_dff.cc:220:make_patterns_logic$5989: { $auto$opt_dff.cc:194:make_patterns_logic$5986 $auto$opt_dff.cc:194:make_patterns_logic$3303 $auto$opt_dff.cc:194:make_patterns_logic$3305 $auto$fsm_map.cc:74:implement_pattern_cache$3050 } Consolidated identical input bits for $mux cell $flatten\Controller.$ternary$/eda/processor-ci-controller/src/controller.v:84$687: Old ports: A=\Core.PC [11:0], B={ \Controller.Interpreter.memory_page_number [5:0] \Core.PC [5:0] }, Y=$auto$wreduce.cc:461:run$3447 [11:0] New ports: A=\Core.PC [11:6], B=\Controller.Interpreter.memory_page_number [5:0], Y=$auto$wreduce.cc:461:run$3447 [11:6] New connections: $auto$wreduce.cc:461:run$3447 [5:0] = \Core.PC [5:0] Consolidated identical input bits for $mux cell $flatten\Controller.\Interpreter.$procmux$1492: Old ports: A=3'011, B=3'100, Y=$auto$wreduce.cc:461:run$3450 [2:0] New ports: A=2'01, B=2'10, Y={ $auto$wreduce.cc:461:run$3450 [2] $auto$wreduce.cc:461:run$3450 [0] } New connections: $auto$wreduce.cc:461:run$3450 [1] = $auto$wreduce.cc:461:run$3450 [0] Consolidated identical input bits for $mux cell $flatten\Controller.\Interpreter.$procmux$1497: Old ports: A=7'1010010, B=7'0010101, Y=$auto$wreduce.cc:461:run$3451 [6:0] New ports: A=2'10, B=2'01, Y=$auto$wreduce.cc:461:run$3451 [1:0] New connections: $auto$wreduce.cc:461:run$3451 [6:2] = { $auto$wreduce.cc:461:run$3451 [1] 3'010 $auto$wreduce.cc:461:run$3451 [0] } Consolidated identical input bits for $mux cell $flatten\Controller.\Interpreter.$procmux$1508: Old ports: A=4'1100, B=4'0000, Y=$auto$wreduce.cc:461:run$3452 [3:0] New ports: A=1'1, B=1'0, Y=$auto$wreduce.cc:461:run$3452 [2] New connections: { $auto$wreduce.cc:461:run$3452 [3] $auto$wreduce.cc:461:run$3452 [1:0] } = { $auto$wreduce.cc:461:run$3452 [2] 2'00 } Consolidated identical input bits for $mux cell $flatten\Controller.\Interpreter.$procmux$1518: Old ports: A=4'1001, B=4'0000, Y=$auto$wreduce.cc:461:run$3454 [3:0] New ports: A=1'1, B=1'0, Y=$auto$wreduce.cc:461:run$3454 [0] New connections: $auto$wreduce.cc:461:run$3454 [3:1] = { $auto$wreduce.cc:461:run$3454 [0] 2'00 } Consolidated identical input bits for $mux cell $flatten\Controller.\Interpreter.$procmux$1532: Old ports: A=7'0000110, B=7'1010111, Y=$auto$wreduce.cc:461:run$3456 [6:0] New ports: A=1'0, B=1'1, Y=$auto$wreduce.cc:461:run$3456 [0] New connections: $auto$wreduce.cc:461:run$3456 [6:1] = { $auto$wreduce.cc:461:run$3456 [0] 1'0 $auto$wreduce.cc:461:run$3456 [0] 3'011 } Consolidated identical input bits for $pmux cell $flatten\Controller.\Interpreter.$procmux$1927: Old ports: A=8'00001011, B=302978816, Y=$flatten\Controller.\Interpreter.$procmux$1927_Y New ports: A=5'01011, B=20'10010011111011100000, Y=$flatten\Controller.\Interpreter.$procmux$1927_Y [4:0] New connections: $flatten\Controller.\Interpreter.$procmux$1927_Y [7:5] = 3'000 Consolidated identical input bits for $pmux cell $flatten\Controller.\Interpreter.$procmux$2052: Old ports: A={ 8'00000000 \Controller.Interpreter.communication_buffer [31:8] }, B={ 40'0000000000000000000000000001010000000000 \Controller.Interpreter.timeout [23:0] }, Y=$flatten\Controller.\Interpreter.$procmux$2052_Y New ports: A=\Controller.Interpreter.communication_buffer [31:8], B={ 24'000000000000000000010100 \Controller.Interpreter.timeout [23:0] }, Y=$flatten\Controller.\Interpreter.$procmux$2052_Y [23:0] New connections: $flatten\Controller.\Interpreter.$procmux$2052_Y [31:24] = 8'00000000 New ctrl vector for $pmux cell $flatten\Controller.\Interpreter.$procmux$2062: $auto$opt_reduce.cc:134:opt_pmux$2922 Consolidated identical input bits for $pmux cell $flatten\Controller.\Uart.$procmux$2266: Old ports: A=4'0000, B={ 1'0 $auto$wreduce.cc:461:run$3463 [2:0] 12'000100100011 }, Y=$flatten\Controller.\Uart.$procmux$2266_Y New ports: A=3'000, B={ $auto$wreduce.cc:461:run$3463 [2:0] 9'001010011 }, Y=$flatten\Controller.\Uart.$procmux$2266_Y [2:0] New connections: $flatten\Controller.\Uart.$procmux$2266_Y [3] = 1'0 Consolidated identical input bits for $mux cell $flatten\Controller.\Uart.$procmux$2274: Old ports: A=3'000, B=3'100, Y=$auto$wreduce.cc:461:run$3463 [2:0] New ports: A=1'0, B=1'1, Y=$auto$wreduce.cc:461:run$3463 [2] New connections: $auto$wreduce.cc:461:run$3463 [1:0] = 2'00 Consolidated identical input bits for $mux cell $flatten\Controller.\Uart.$procmux$2350: Old ports: A=4'0010, B=4'0100, Y=$flatten\Controller.\Uart.$procmux$2350_Y New ports: A=2'01, B=2'10, Y=$flatten\Controller.\Uart.$procmux$2350_Y [2:1] New connections: { $flatten\Controller.\Uart.$procmux$2350_Y [3] $flatten\Controller.\Uart.$procmux$2350_Y [0] } = 2'00 Consolidated identical input bits for $pmux cell $flatten\Controller.\Uart.\i_uart_rx.$procmux$1308: Old ports: A=3'000, B={ 2'00 $auto$wreduce.cc:461:run$3476 [0] 1'0 $auto$wreduce.cc:461:run$3477 [1:0] 2'01 \Controller.Uart.i_uart_rx.payload_done 1'0 $auto$wreduce.cc:461:run$3479 [1:0] }, Y=\Controller.Uart.i_uart_rx.n_fsm_state New ports: A=2'00, B={ 1'0 $auto$wreduce.cc:461:run$3476 [0] $auto$wreduce.cc:461:run$3477 [1:0] 1'1 \Controller.Uart.i_uart_rx.payload_done $auto$wreduce.cc:461:run$3479 [1:0] }, Y=\Controller.Uart.i_uart_rx.n_fsm_state [1:0] New connections: \Controller.Uart.i_uart_rx.n_fsm_state [2] = 1'0 Consolidated identical input bits for $mux cell $flatten\Controller.\Uart.\i_uart_rx.$ternary$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:120$1089: Old ports: A=2'11, B=2'00, Y=$auto$wreduce.cc:461:run$3479 [1:0] New ports: A=1'1, B=1'0, Y=$auto$wreduce.cc:461:run$3479 [0] New connections: $auto$wreduce.cc:461:run$3479 [1] = $auto$wreduce.cc:461:run$3479 [0] Consolidated identical input bits for $pmux cell $flatten\Controller.\Uart.\i_uart_tx.$procmux$1445: Old ports: A=3'000, B={ 2'00 \Controller.Uart.uart_tx_en 1'0 $auto$wreduce.cc:461:run$3481 [1:0] 2'01 \Controller.Uart.i_uart_tx.payload_done 1'0 $auto$wreduce.cc:461:run$3483 [1:0] }, Y=\Controller.Uart.i_uart_tx.n_fsm_state New ports: A=2'00, B={ 1'0 \Controller.Uart.uart_tx_en $auto$wreduce.cc:461:run$3481 [1:0] 1'1 \Controller.Uart.i_uart_tx.payload_done $auto$wreduce.cc:461:run$3483 [1:0] }, Y=\Controller.Uart.i_uart_tx.n_fsm_state [1:0] New connections: \Controller.Uart.i_uart_tx.n_fsm_state [2] = 1'0 Consolidated identical input bits for $mux cell $flatten\Controller.\Uart.\i_uart_tx.$ternary$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:103$1032: Old ports: A=2'11, B=2'00, Y=$auto$wreduce.cc:461:run$3483 [1:0] New ports: A=1'1, B=1'0, Y=$auto$wreduce.cc:461:run$3483 [0] New connections: $auto$wreduce.cc:461:run$3483 [1] = $auto$wreduce.cc:461:run$3483 [0] Consolidated identical input bits for $mux cell $flatten\Core.\ALU_Control.$procmux$2720: Old ports: A=2'01, B=2'11, Y=$auto$wreduce.cc:461:run$3484 [1:0] New ports: A=1'0, B=1'1, Y=$auto$wreduce.cc:461:run$3484 [1] New connections: $auto$wreduce.cc:461:run$3484 [0] = 1'1 Consolidated identical input bits for $mux cell $flatten\Core.\ALU_Control.$procmux$2728: Old ports: A=4'0010, B=4'1010, Y=$flatten\Core.\ALU_Control.$procmux$2728_Y New ports: A=1'0, B=1'1, Y=$flatten\Core.\ALU_Control.$procmux$2728_Y [3] New connections: $flatten\Core.\ALU_Control.$procmux$2728_Y [2:0] = 3'010 Consolidated identical input bits for $pmux cell $flatten\Core.\Immediate_Generator.$procmux$2469: Old ports: A={ \Core.IFIDIR [31] \Core.IFIDIR [31] \Core.IFIDIR [31] \Core.IFIDIR [31] \Core.IFIDIR [31] \Core.IFIDIR [31] \Core.IFIDIR [31] \Core.IFIDIR [31] \Core.IFIDIR [31] \Core.IFIDIR [31] \Core.IFIDIR [31] \Core.IFIDIR [31] \Core.IFIDIR [31] \Core.IFIDIR [31] \Core.IFIDIR [31] \Core.IFIDIR [31] \Core.IFIDIR [31] \Core.IFIDIR [31] \Core.IFIDIR [31] \Core.IFIDIR [31] \Core.IFIDIR [31:20] }, B={ \Core.IFIDIR [24] \Core.IFIDIR [24] \Core.IFIDIR [24] \Core.IFIDIR [24] \Core.IFIDIR [24] \Core.IFIDIR [24] \Core.IFIDIR [24] \Core.IFIDIR [24] \Core.IFIDIR [24] \Core.IFIDIR [24] \Core.IFIDIR [24] \Core.IFIDIR [24] \Core.IFIDIR [24] \Core.IFIDIR [24] \Core.IFIDIR [24] \Core.IFIDIR [24] \Core.IFIDIR [24] \Core.IFIDIR [24] \Core.IFIDIR [24] \Core.IFIDIR [24] \Core.IFIDIR [24] \Core.IFIDIR [24] \Core.IFIDIR [24] \Core.IFIDIR [24] \Core.IFIDIR [24] \Core.IFIDIR [24] \Core.IFIDIR [24] \Core.IFIDIR [24:20] 20'00000000000000000000 \Core.IFIDIR [31:20] 27'000000000000000000000000000 \Core.IFIDIR [24:20] }, Y=$flatten\Core.\Immediate_Generator.$2\immediate[31:0] New ports: A={ \Core.IFIDIR [31] \Core.IFIDIR [31:25] }, B={ \Core.IFIDIR [24] \Core.IFIDIR [24] \Core.IFIDIR [24] \Core.IFIDIR [24] \Core.IFIDIR [24] \Core.IFIDIR [24] \Core.IFIDIR [24] \Core.IFIDIR [24] 1'0 \Core.IFIDIR [31:25] 8'00000000 }, Y=$flatten\Core.\Immediate_Generator.$2\immediate[31:0] [12:5] New connections: { $flatten\Core.\Immediate_Generator.$2\immediate[31:0] [31:13] $flatten\Core.\Immediate_Generator.$2\immediate[31:0] [4:0] } = { $flatten\Core.\Immediate_Generator.$2\immediate[31:0] [12] $flatten\Core.\Immediate_Generator.$2\immediate[31:0] [12] $flatten\Core.\Immediate_Generator.$2\immediate[31:0] [12] $flatten\Core.\Immediate_Generator.$2\immediate[31:0] [12] $flatten\Core.\Immediate_Generator.$2\immediate[31:0] [12] $flatten\Core.\Immediate_Generator.$2\immediate[31:0] [12] $flatten\Core.\Immediate_Generator.$2\immediate[31:0] [12] $flatten\Core.\Immediate_Generator.$2\immediate[31:0] [12] $flatten\Core.\Immediate_Generator.$2\immediate[31:0] [12] $flatten\Core.\Immediate_Generator.$2\immediate[31:0] [12] $flatten\Core.\Immediate_Generator.$2\immediate[31:0] [12] $flatten\Core.\Immediate_Generator.$2\immediate[31:0] [12] $flatten\Core.\Immediate_Generator.$2\immediate[31:0] [12] $flatten\Core.\Immediate_Generator.$2\immediate[31:0] [12] $flatten\Core.\Immediate_Generator.$2\immediate[31:0] [12] $flatten\Core.\Immediate_Generator.$2\immediate[31:0] [12] $flatten\Core.\Immediate_Generator.$2\immediate[31:0] [12] $flatten\Core.\Immediate_Generator.$2\immediate[31:0] [12] $flatten\Core.\Immediate_Generator.$2\immediate[31:0] [12] \Core.IFIDIR [24:20] } New ctrl vector for $pmux cell $flatten\ResetBootSystem.$procmux$2430: { $flatten\ResetBootSystem.$procmux$2423_CMP $flatten\ResetBootSystem.$procmux$2422_CMP } Consolidated identical input bits for $mux cell $flatten\ResetBootSystem.$procmux$2433: Old ports: A=2'00, B=2'10, Y=$flatten\ResetBootSystem.$procmux$2433_Y New ports: A=1'0, B=1'1, Y=$flatten\ResetBootSystem.$procmux$2433_Y [1] New connections: $flatten\ResetBootSystem.$procmux$2433_Y [0] = 1'0 Optimizing cells in module \processorci_top. Consolidated identical input bits for $pmux cell $flatten\Controller.\Uart.$procmux$2344: Old ports: A=4'0000, B={ 3'000 \Controller.Interpreter.communication_read $flatten\Controller.\Uart.$procmux$2350_Y 8'00010011 }, Y=$flatten\Controller.\Uart.$procmux$2344_Y New ports: A=3'000, B={ 2'00 \Controller.Interpreter.communication_read $flatten\Controller.\Uart.$procmux$2350_Y [2:1] 7'0001011 }, Y=$flatten\Controller.\Uart.$procmux$2344_Y [2:0] New connections: $flatten\Controller.\Uart.$procmux$2344_Y [3] = 1'0 Consolidated identical input bits for $mux cell $flatten\ResetBootSystem.$procmux$2439: Old ports: A=2'00, B=$flatten\ResetBootSystem.$procmux$2433_Y, Y=$flatten\ResetBootSystem.$procmux$2439_Y New ports: A=1'0, B=$flatten\ResetBootSystem.$procmux$2433_Y [1], Y=$flatten\ResetBootSystem.$procmux$2439_Y [1] New connections: $flatten\ResetBootSystem.$procmux$2439_Y [0] = 1'0 Optimizing cells in module \processorci_top. Performed a total of 25 changes. 18.30.5. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\processorci_top'. <suppressed ~3 debug messages> Removed a total of 1 cells. 18.30.6. Executing OPT_DFF pass (perform DFF optimizations). Adding SRST signal on $\Core.RegisterBank.registers$rdreg[0] ($dff) from module processorci_top (D = $auto$rtlil.cc:2628:Mux$3649, Q = $\Core.RegisterBank.registers$rdreg[0]$q, rval = 5'00000). Adding SRST signal on $\Core.RegisterBank.registers$rdreg[1] ($dff) from module processorci_top (D = $auto$rtlil.cc:2628:Mux$3654, Q = $\Core.RegisterBank.registers$rdreg[1]$q, rval = 5'00000). Setting constant 0-bit at position 0 on $memory\Core.RegisterBank.registers[0]$6003 ($dff) from module processorci_top. Setting constant 0-bit at position 1 on $memory\Core.RegisterBank.registers[0]$6003 ($dff) from module processorci_top. Setting constant 0-bit at position 2 on $memory\Core.RegisterBank.registers[0]$6003 ($dff) from module processorci_top. Setting constant 0-bit at position 3 on $memory\Core.RegisterBank.registers[0]$6003 ($dff) from module processorci_top. Setting constant 0-bit at position 4 on $memory\Core.RegisterBank.registers[0]$6003 ($dff) from module processorci_top. Setting constant 0-bit at position 5 on $memory\Core.RegisterBank.registers[0]$6003 ($dff) from module processorci_top. Setting constant 0-bit at position 6 on $memory\Core.RegisterBank.registers[0]$6003 ($dff) from module processorci_top. Setting constant 0-bit at position 7 on $memory\Core.RegisterBank.registers[0]$6003 ($dff) from module processorci_top. Setting constant 0-bit at position 8 on $memory\Core.RegisterBank.registers[0]$6003 ($dff) from module processorci_top. Setting constant 0-bit at position 9 on $memory\Core.RegisterBank.registers[0]$6003 ($dff) from module processorci_top. Setting constant 0-bit at position 10 on $memory\Core.RegisterBank.registers[0]$6003 ($dff) from module processorci_top. Setting constant 0-bit at position 11 on $memory\Core.RegisterBank.registers[0]$6003 ($dff) from module processorci_top. Setting constant 0-bit at position 12 on $memory\Core.RegisterBank.registers[0]$6003 ($dff) from module processorci_top. Setting constant 0-bit at position 13 on $memory\Core.RegisterBank.registers[0]$6003 ($dff) from module processorci_top. Setting constant 0-bit at position 14 on $memory\Core.RegisterBank.registers[0]$6003 ($dff) from module processorci_top. Setting constant 0-bit at position 15 on $memory\Core.RegisterBank.registers[0]$6003 ($dff) from module processorci_top. Setting constant 0-bit at position 16 on $memory\Core.RegisterBank.registers[0]$6003 ($dff) from module processorci_top. Setting constant 0-bit at position 17 on $memory\Core.RegisterBank.registers[0]$6003 ($dff) from module processorci_top. Setting constant 0-bit at position 18 on $memory\Core.RegisterBank.registers[0]$6003 ($dff) from module processorci_top. Setting constant 0-bit at position 19 on $memory\Core.RegisterBank.registers[0]$6003 ($dff) from module processorci_top. Setting constant 0-bit at position 20 on $memory\Core.RegisterBank.registers[0]$6003 ($dff) from module processorci_top. Setting constant 0-bit at position 21 on $memory\Core.RegisterBank.registers[0]$6003 ($dff) from module processorci_top. Setting constant 0-bit at position 22 on $memory\Core.RegisterBank.registers[0]$6003 ($dff) from module processorci_top. Setting constant 0-bit at position 23 on $memory\Core.RegisterBank.registers[0]$6003 ($dff) from module processorci_top. Setting constant 0-bit at position 24 on $memory\Core.RegisterBank.registers[0]$6003 ($dff) from module processorci_top. Setting constant 0-bit at position 25 on $memory\Core.RegisterBank.registers[0]$6003 ($dff) from module processorci_top. Setting constant 0-bit at position 26 on $memory\Core.RegisterBank.registers[0]$6003 ($dff) from module processorci_top. Setting constant 0-bit at position 27 on $memory\Core.RegisterBank.registers[0]$6003 ($dff) from module processorci_top. Setting constant 0-bit at position 28 on $memory\Core.RegisterBank.registers[0]$6003 ($dff) from module processorci_top. Setting constant 0-bit at position 29 on $memory\Core.RegisterBank.registers[0]$6003 ($dff) from module processorci_top. Setting constant 0-bit at position 30 on $memory\Core.RegisterBank.registers[0]$6003 ($dff) from module processorci_top. Setting constant 0-bit at position 31 on $memory\Core.RegisterBank.registers[0]$6003 ($dff) from module processorci_top. 18.30.7. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \processorci_top.. Removed 4 unused cells and 185 unused wires. <suppressed ~5 debug messages> 18.30.8. Executing OPT_EXPR pass (perform const folding). Optimizing module processorci_top. <suppressed ~1 debug messages> 18.30.9. Rerunning OPT passes. (Maybe there is more to do..) 18.30.10. Executing OPT_MUXTREE pass (detect dead branches in mux trees). Running muxtree optimizer on module \processorci_top.. Creating internal representation of mux trees. Evaluating internal representation of mux trees. Analyzing evaluation results. Removed 0 multiplexer ports. <suppressed ~105 debug messages> 18.30.11. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). Optimizing cells in module \processorci_top. Performed a total of 0 changes. 18.30.12. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\processorci_top'. Removed a total of 0 cells. 18.30.13. Executing OPT_DFF pass (perform DFF optimizations). Adding EN signal on $memory\Core.RegisterBank.registers[9]$6021 ($dff) from module processorci_top (D = \Core.ForwardAMUX.B, Q = \Core.RegisterBank.registers[9]). Adding EN signal on $memory\Core.RegisterBank.registers[8]$6019 ($dff) from module processorci_top (D = \Core.ForwardAMUX.B, Q = \Core.RegisterBank.registers[8]). Adding EN signal on $memory\Core.RegisterBank.registers[7]$6017 ($dff) from module processorci_top (D = \Core.ForwardAMUX.B, Q = \Core.RegisterBank.registers[7]). Adding EN signal on $memory\Core.RegisterBank.registers[6]$6015 ($dff) from module processorci_top (D = \Core.ForwardAMUX.B, Q = \Core.RegisterBank.registers[6]). Adding EN signal on $memory\Core.RegisterBank.registers[5]$6013 ($dff) from module processorci_top (D = \Core.ForwardAMUX.B, Q = \Core.RegisterBank.registers[5]). Adding EN signal on $memory\Core.RegisterBank.registers[4]$6011 ($dff) from module processorci_top (D = \Core.ForwardAMUX.B, Q = \Core.RegisterBank.registers[4]). Adding EN signal on $memory\Core.RegisterBank.registers[3]$6009 ($dff) from module processorci_top (D = \Core.ForwardAMUX.B, Q = \Core.RegisterBank.registers[3]). Adding EN signal on $memory\Core.RegisterBank.registers[31]$6065 ($dff) from module processorci_top (D = \Core.ForwardAMUX.B, Q = \Core.RegisterBank.registers[31]). Adding EN signal on $memory\Core.RegisterBank.registers[30]$6063 ($dff) from module processorci_top (D = \Core.ForwardAMUX.B, Q = \Core.RegisterBank.registers[30]). Adding EN signal on $memory\Core.RegisterBank.registers[2]$6007 ($dff) from module processorci_top (D = \Core.ForwardAMUX.B, Q = \Core.RegisterBank.registers[2]). Adding EN signal on $memory\Core.RegisterBank.registers[29]$6061 ($dff) from module processorci_top (D = \Core.ForwardAMUX.B, Q = \Core.RegisterBank.registers[29]). Adding EN signal on $memory\Core.RegisterBank.registers[28]$6059 ($dff) from module processorci_top (D = \Core.ForwardAMUX.B, Q = \Core.RegisterBank.registers[28]). Adding EN signal on $memory\Core.RegisterBank.registers[27]$6057 ($dff) from module processorci_top (D = \Core.ForwardAMUX.B, Q = \Core.RegisterBank.registers[27]). Adding EN signal on $memory\Core.RegisterBank.registers[26]$6055 ($dff) from module processorci_top (D = \Core.ForwardAMUX.B, Q = \Core.RegisterBank.registers[26]). Adding EN signal on $memory\Core.RegisterBank.registers[25]$6053 ($dff) from module processorci_top (D = \Core.ForwardAMUX.B, Q = \Core.RegisterBank.registers[25]). Adding EN signal on $memory\Core.RegisterBank.registers[24]$6051 ($dff) from module processorci_top (D = \Core.ForwardAMUX.B, Q = \Core.RegisterBank.registers[24]). Adding EN signal on $memory\Core.RegisterBank.registers[23]$6049 ($dff) from module processorci_top (D = \Core.ForwardAMUX.B, Q = \Core.RegisterBank.registers[23]). Adding EN signal on $memory\Core.RegisterBank.registers[22]$6047 ($dff) from module processorci_top (D = \Core.ForwardAMUX.B, Q = \Core.RegisterBank.registers[22]). Adding EN signal on $memory\Core.RegisterBank.registers[21]$6045 ($dff) from module processorci_top (D = \Core.ForwardAMUX.B, Q = \Core.RegisterBank.registers[21]). Adding EN signal on $memory\Core.RegisterBank.registers[20]$6043 ($dff) from module processorci_top (D = \Core.ForwardAMUX.B, Q = \Core.RegisterBank.registers[20]). Adding EN signal on $memory\Core.RegisterBank.registers[1]$6005 ($dff) from module processorci_top (D = \Core.ForwardAMUX.B, Q = \Core.RegisterBank.registers[1]). Adding EN signal on $memory\Core.RegisterBank.registers[19]$6041 ($dff) from module processorci_top (D = \Core.ForwardAMUX.B, Q = \Core.RegisterBank.registers[19]). Adding EN signal on $memory\Core.RegisterBank.registers[18]$6039 ($dff) from module processorci_top (D = \Core.ForwardAMUX.B, Q = \Core.RegisterBank.registers[18]). Adding EN signal on $memory\Core.RegisterBank.registers[17]$6037 ($dff) from module processorci_top (D = \Core.ForwardAMUX.B, Q = \Core.RegisterBank.registers[17]). Adding EN signal on $memory\Core.RegisterBank.registers[16]$6035 ($dff) from module processorci_top (D = \Core.ForwardAMUX.B, Q = \Core.RegisterBank.registers[16]). Adding EN signal on $memory\Core.RegisterBank.registers[15]$6033 ($dff) from module processorci_top (D = \Core.ForwardAMUX.B, Q = \Core.RegisterBank.registers[15]). Adding EN signal on $memory\Core.RegisterBank.registers[14]$6031 ($dff) from module processorci_top (D = \Core.ForwardAMUX.B, Q = \Core.RegisterBank.registers[14]). Adding EN signal on $memory\Core.RegisterBank.registers[13]$6029 ($dff) from module processorci_top (D = \Core.ForwardAMUX.B, Q = \Core.RegisterBank.registers[13]). Adding EN signal on $memory\Core.RegisterBank.registers[12]$6027 ($dff) from module processorci_top (D = \Core.ForwardAMUX.B, Q = \Core.RegisterBank.registers[12]). Adding EN signal on $memory\Core.RegisterBank.registers[11]$6025 ($dff) from module processorci_top (D = \Core.ForwardAMUX.B, Q = \Core.RegisterBank.registers[11]). Adding EN signal on $memory\Core.RegisterBank.registers[10]$6023 ($dff) from module processorci_top (D = \Core.ForwardAMUX.B, Q = \Core.RegisterBank.registers[10]). Setting constant 0-bit at position 2 on $auto$ff.cc:266:slice$3182 ($sdff) from module processorci_top. Setting constant 0-bit at position 3 on $auto$ff.cc:266:slice$3226 ($sdffe) from module processorci_top. Setting constant 0-bit at position 3 on $auto$ff.cc:266:slice$3254 ($sdffe) from module processorci_top. Setting constant 0-bit at position 5 on $auto$ff.cc:266:slice$3356 ($sdffe) from module processorci_top. Setting constant 0-bit at position 6 on $auto$ff.cc:266:slice$3356 ($sdffe) from module processorci_top. Setting constant 0-bit at position 7 on $auto$ff.cc:266:slice$3356 ($sdffe) from module processorci_top. Setting constant 0-bit at position 24 on $auto$ff.cc:266:slice$3383 ($dffe) from module processorci_top. Setting constant 0-bit at position 25 on $auto$ff.cc:266:slice$3383 ($dffe) from module processorci_top. Setting constant 0-bit at position 26 on $auto$ff.cc:266:slice$3383 ($dffe) from module processorci_top. Setting constant 0-bit at position 27 on $auto$ff.cc:266:slice$3383 ($dffe) from module processorci_top. Setting constant 0-bit at position 28 on $auto$ff.cc:266:slice$3383 ($dffe) from module processorci_top. Setting constant 0-bit at position 29 on $auto$ff.cc:266:slice$3383 ($dffe) from module processorci_top. Setting constant 0-bit at position 30 on $auto$ff.cc:266:slice$3383 ($dffe) from module processorci_top. Setting constant 0-bit at position 31 on $auto$ff.cc:266:slice$3383 ($dffe) from module processorci_top. 18.30.14. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \processorci_top.. Removed 31 unused cells and 31 unused wires. <suppressed ~32 debug messages> 18.30.15. Executing OPT_EXPR pass (perform const folding). Optimizing module processorci_top. <suppressed ~4 debug messages> 18.30.16. Rerunning OPT passes. (Maybe there is more to do..) 18.30.17. Executing OPT_MUXTREE pass (detect dead branches in mux trees). Running muxtree optimizer on module \processorci_top.. Creating internal representation of mux trees. Evaluating internal representation of mux trees. Analyzing evaluation results. Removed 0 multiplexer ports. <suppressed ~74 debug messages> 18.30.18. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). Optimizing cells in module \processorci_top. Consolidated identical input bits for $mux cell $flatten\Controller.\Interpreter.$procmux$1502: Old ports: A=8'00000100, B={ 3'000 \Controller.Interpreter.return_state [4:0] }, Y=$flatten\Controller.\Interpreter.$procmux$1502_Y New ports: A=5'00100, B=\Controller.Interpreter.return_state [4:0], Y=$flatten\Controller.\Interpreter.$procmux$1502_Y [4:0] New connections: $flatten\Controller.\Interpreter.$procmux$1502_Y [7:5] = 3'000 Optimizing cells in module \processorci_top. Consolidated identical input bits for $pmux cell $flatten\Controller.\Interpreter.$procmux$1480: Old ports: A=8'00000000, B={ 7'0000000 $auto$wreduce.cc:461:run$3460 [0] 6'000000 $auto$wreduce.cc:461:run$3453 [1:0] 1'0 $auto$wreduce.cc:461:run$3458 [6:0] 14'00001101000011 $auto$wreduce.cc:461:run$3457 [1:0] 3'000 \Controller.Interpreter.return_state [4:0] 1'0 $auto$wreduce.cc:461:run$3456 [6] 1'0 $auto$wreduce.cc:461:run$3456 [6] 3'011 $auto$wreduce.cc:461:run$3456 [6] 7'0000011 \Controller.Uart.read_response 4'0000 $auto$wreduce.cc:461:run$3452 [3] 2'00 $auto$wreduce.cc:461:run$3452 [3] 6'000010 $auto$wreduce.cc:461:run$3453 [1:0] 20'00001000000010110000 $auto$wreduce.cc:461:run$3452 [3] $auto$wreduce.cc:461:run$3452 [3] 18'000000010100000100 $flatten\Controller.\Interpreter.$procmux$1502_Y 1'0 $auto$wreduce.cc:461:run$3451 [6] 3'010 $auto$wreduce.cc:461:run$3451 [2] $auto$wreduce.cc:461:run$3451 [6] $auto$wreduce.cc:461:run$3451 [2] 13'0001001100010 $auto$wreduce.cc:461:run$3450 [2:1] $auto$wreduce.cc:461:run$3450 [1] 31'0001011001010010000100000001000 $auto$wreduce.cc:461:run$3449 [0] 8'00000011 }, Y=$flatten\Controller.\Interpreter.$procmux$1480_Y New ports: A=7'0000000, B={ 6'000000 $auto$wreduce.cc:461:run$3460 [0] 5'00000 $auto$wreduce.cc:461:run$3453 [1:0] $auto$wreduce.cc:461:run$3458 [6:0] 12'000110100011 $auto$wreduce.cc:461:run$3457 [1:0] 2'00 \Controller.Interpreter.return_state [4:0] $auto$wreduce.cc:461:run$3456 [6] 1'0 $auto$wreduce.cc:461:run$3456 [6] 3'011 $auto$wreduce.cc:461:run$3456 [6] 6'000011 \Controller.Uart.read_response 3'000 $auto$wreduce.cc:461:run$3452 [3] 2'00 $auto$wreduce.cc:461:run$3452 [3] 5'00010 $auto$wreduce.cc:461:run$3453 [1:0] 17'00010000001011000 $auto$wreduce.cc:461:run$3452 [3] $auto$wreduce.cc:461:run$3452 [3] 18'000000101000010000 $flatten\Controller.\Interpreter.$procmux$1502_Y [4:0] $auto$wreduce.cc:461:run$3451 [6] 3'010 $auto$wreduce.cc:461:run$3451 [2] $auto$wreduce.cc:461:run$3451 [6] $auto$wreduce.cc:461:run$3451 [2] 11'00100110010 $auto$wreduce.cc:461:run$3450 [2:1] $auto$wreduce.cc:461:run$3450 [1] 27'001011010100100010000001000 $auto$wreduce.cc:461:run$3449 [0] 7'0000011 }, Y=$flatten\Controller.\Interpreter.$procmux$1480_Y [6:0] New connections: $flatten\Controller.\Interpreter.$procmux$1480_Y [7] = 1'0 Optimizing cells in module \processorci_top. Performed a total of 2 changes. 18.30.19. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\processorci_top'. Removed a total of 0 cells. 18.30.20. Executing OPT_DFF pass (perform DFF optimizations). 18.30.21. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \processorci_top.. 18.30.22. Executing OPT_EXPR pass (perform const folding). Optimizing module processorci_top. 18.30.23. Rerunning OPT passes. (Maybe there is more to do..) 18.30.24. Executing OPT_MUXTREE pass (detect dead branches in mux trees). Running muxtree optimizer on module \processorci_top.. Creating internal representation of mux trees. Evaluating internal representation of mux trees. Analyzing evaluation results. Removed 0 multiplexer ports. <suppressed ~74 debug messages> 18.30.25. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). Optimizing cells in module \processorci_top. Performed a total of 0 changes. 18.30.26. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\processorci_top'. Removed a total of 0 cells. 18.30.27. Executing OPT_DFF pass (perform DFF optimizations). Setting constant 0-bit at position 7 on $auto$ff.cc:266:slice$3420 ($sdff) from module processorci_top. 18.30.28. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \processorci_top.. 18.30.29. Executing OPT_EXPR pass (perform const folding). Optimizing module processorci_top. <suppressed ~1 debug messages> 18.30.30. Rerunning OPT passes. (Maybe there is more to do..) 18.30.31. Executing OPT_MUXTREE pass (detect dead branches in mux trees). Running muxtree optimizer on module \processorci_top.. Creating internal representation of mux trees. Evaluating internal representation of mux trees. Analyzing evaluation results. Removed 0 multiplexer ports. <suppressed ~74 debug messages> 18.30.32. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). Optimizing cells in module \processorci_top. Performed a total of 0 changes. 18.30.33. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\processorci_top'. Removed a total of 0 cells. 18.30.34. Executing OPT_DFF pass (perform DFF optimizations). 18.30.35. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \processorci_top.. 18.30.36. Executing OPT_EXPR pass (perform const folding). Optimizing module processorci_top. 18.30.37. Finished OPT passes. (There is nothing left to do.) 18.31. Executing TECHMAP pass (map to technology primitives). 18.31.1. Executing Verilog-2005 frontend: /eda/oss-cad-suite/lib/../share/yosys/techmap.v Parsing Verilog input from `/eda/oss-cad-suite/lib/../share/yosys/techmap.v' to AST representation. Generating RTLIL representation for module `\_90_simplemap_bool_ops'. Generating RTLIL representation for module `\_90_simplemap_reduce_ops'. Generating RTLIL representation for module `\_90_simplemap_logic_ops'. Generating RTLIL representation for module `\_90_simplemap_compare_ops'. Generating RTLIL representation for module `\_90_simplemap_various'. Generating RTLIL representation for module `\_90_simplemap_registers'. Generating RTLIL representation for module `\_90_shift_ops_shr_shl_sshl_sshr'. Generating RTLIL representation for module `\_90_shift_shiftx'. Generating RTLIL representation for module `\_90_fa'. Generating RTLIL representation for module `\_90_lcu_brent_kung'. Generating RTLIL representation for module `\_90_alu'. Generating RTLIL representation for module `\_90_macc'. Generating RTLIL representation for module `\_90_alumacc'. Generating RTLIL representation for module `\$__div_mod_u'. Generating RTLIL representation for module `\$__div_mod_trunc'. Generating RTLIL representation for module `\_90_div'. Generating RTLIL representation for module `\_90_mod'. Generating RTLIL representation for module `\$__div_mod_floor'. Generating RTLIL representation for module `\_90_divfloor'. Generating RTLIL representation for module `\_90_modfloor'. Generating RTLIL representation for module `\_90_pow'. Generating RTLIL representation for module `\_90_pmux'. Generating RTLIL representation for module `\_90_demux'. Generating RTLIL representation for module `\_90_lut'. Successfully finished Verilog frontend. 18.31.2. Executing Verilog-2005 frontend: /eda/oss-cad-suite/lib/../share/yosys/ecp5/arith_map.v Parsing Verilog input from `/eda/oss-cad-suite/lib/../share/yosys/ecp5/arith_map.v' to AST representation. Generating RTLIL representation for module `\_80_ecp5_alu'. Successfully finished Verilog frontend. 18.31.3. Continuing TECHMAP pass. Using template $paramod$eaeb96106163dbf82031649d189817109fe07c69\_90_demux for cells of type $demux. Using extmapper simplemap for cells of type $dffe. Using extmapper simplemap for cells of type $bmux. Using extmapper simplemap for cells of type $not. Using extmapper simplemap for cells of type $reduce_or. Using extmapper simplemap for cells of type $mux. Using extmapper simplemap for cells of type $or. Using extmapper simplemap for cells of type $reduce_and. Using template $paramod$e04283ca12514baf3d204c6994bec8f178dd89f8\_80_ecp5_alu for cells of type $alu. Using extmapper simplemap for cells of type $ne. Using extmapper simplemap for cells of type $dff. Using extmapper simplemap for cells of type $logic_not. Using extmapper simplemap for cells of type $and. Using extmapper simplemap for cells of type $eq. Using extmapper simplemap for cells of type $reduce_bool. Using extmapper simplemap for cells of type $lut. Using extmapper simplemap for cells of type $sdffe. Using template $paramod$c04af8dbf0e5d1d69bbccb2c7bd8a93fc9ef54dc\_80_ecp5_alu for cells of type $alu. Using template $paramod$c3cd1564c35d873179656addd6052d7ea8b6d991\_80_ecp5_alu for cells of type $alu. Using template $paramod$039520c137afc9cd69dd56c3fb11a4e1fbe5f664\_80_ecp5_alu for cells of type $alu. Using template $paramod$bdc78fe5225b43c64ccdf13e5eb67d9dcf228e8a\_80_ecp5_alu for cells of type $alu. Using template $paramod$ff467a932a72bec5a93c27dba04bf3daba067451\_80_ecp5_alu for cells of type $alu. Using template $paramod$3ef7d3dd227da7627a99c5e5a6a4deb817573e39\_90_alu for cells of type $alu. Using template $paramod$6a42b6fefed750f8a1c58eab59479d960557103c\_80_ecp5_alu for cells of type $alu. Using template $paramod$79aa992f2eb7f354d4aaf651790713cf239111fa\_80_ecp5_alu for cells of type $alu. Using extmapper simplemap for cells of type $logic_or. Using template $paramod$c9511eeb847f2aa95252b1013477609463f67ee0\_80_ecp5_alu for cells of type $alu. Using template $paramod$a7b312e4ba8fdc79d4c5e0789e4e6c41ea3896fb\_90_pmux for cells of type $pmux. Using template $paramod$7a385d5b7a2e603dbc5beef838648775b433f248\_90_pmux for cells of type $pmux. Using extmapper simplemap for cells of type $sdff. Using template $paramod$54a4503cc57b9df40b70c1899504d6aac2650719\_90_pmux for cells of type $pmux. Using template $paramod$59b03ae2620a41577de8da5f5c97b2919e82362b\_90_pmux for cells of type $pmux. Using template $paramod$24fb226dd75c9d3f6955ec2ad61d794776778cf6\_90_pmux for cells of type $pmux. Using template $paramod$cc1e387d9d5ac1d3f6e6bed180038d9c0ac48d0c\_90_pmux for cells of type $pmux. Using template $paramod$54d740639e1393b22262823179ff783ea9f17a35\_90_pmux for cells of type $pmux. Using template $paramod$8fabc56b80a569262acfc42757a02ca0b8e91278\_90_pmux for cells of type $pmux. Using template $paramod$32efbfac1c4dc57230cf86180788fdfd12e3b511\_80_ecp5_alu for cells of type $alu. Using extmapper simplemap for cells of type $logic_and. Using template $paramod$d31bf4d7d72e59528d18fbd4f322e9d608532043\_90_pmux for cells of type $pmux. Using template $paramod$32a7b7b86c07519b7537abc18e96f0331f97914d\_90_alu for cells of type $alu. Using template $paramod$ac45afa5bcd8e16ca475cce13f9d19bb109f1516\_80_ecp5_alu for cells of type $alu. Using template $paramod$068ad458e7761d78e5eed8238508872e7b0aef95\_90_pmux for cells of type $pmux. Using template $paramod$53700bbee849b2010ad0b60a61ccd204a10e24ca\_80_ecp5_alu for cells of type $alu. Using template $paramod$44a13d10af618e7fbe7b9aad2f6151ffcee1e2fa\_80_ecp5_alu for cells of type $alu. Using template $paramod$645fe0cc96ae5edb83bff90cc2c78f4a20ca3e3c\_90_pmux for cells of type $pmux. Using template $paramod$49f1dc3dcd6d2c748486fe94c6744a34a19bbafe\_90_pmux for cells of type $pmux. Using template $paramod$fbc7873bff55778c0b3173955b7e4bce1d9d6834\_80_ecp5_alu for cells of type $alu. Using extmapper simplemap for cells of type $xor. Using template $paramod$constmap:4621fcf06a436d1e2a4080e2ed9866a7d07a6e07$paramod$335cfd09f1afa8139c4aafcbbe5f361887b79c5e\_90_shift_ops_shr_shl_sshl_sshr for cells of type $shl. Using template $paramod$constmap:4621fcf06a436d1e2a4080e2ed9866a7d07a6e07$paramod$feecc7a0dbd012970970f2858f15e786e251f677\_90_shift_ops_shr_shl_sshl_sshr for cells of type $shr. Using template $paramod$constmap:4621fcf06a436d1e2a4080e2ed9866a7d07a6e07$paramod$5180471e6f22625c8e3c4261cd538e11648586b5\_90_shift_ops_shr_shl_sshl_sshr for cells of type $sshr. Using template $paramod$ed6389a5938b09f91843a91d67becca5abedb1bd\_90_pmux for cells of type $pmux. Using template $paramod$33afdd83bf3811dac2de7a968d39eea5718691bc\_90_pmux for cells of type $pmux. Using template $paramod$95ab7b964273918a033d1324366ecc612d202989\_90_pmux for cells of type $pmux. Using template $paramod$bf2533632d512eac76dd186c0da49367e29b8e98\_90_pmux for cells of type $pmux. Using extmapper simplemap for cells of type $sdffce. Using template $paramod$521ce43182eecb9f60c72393a788160d2c356bf5\_90_pmux for cells of type $pmux. Using template $paramod$610911f8769324f781128d641f7fe2120143c328\_80_ecp5_alu for cells of type $alu. Using extmapper simplemap for cells of type $pos. Using template $paramod\_90_lcu_brent_kung\WIDTH=32'00000000000000000000000000000011 for cells of type $lcu. Using template $paramod$46c272b461898a6a76adeeeedb0917ce1a81b478\_90_demux for cells of type $demux. Using template $paramod\_90_lcu_brent_kung\WIDTH=32'00000000000000000000000000000100 for cells of type $lcu. Using template $paramod$63301a5e78ceb1f2c17a4ac1894f292ed5701c1f\_90_demux for cells of type $demux. Using template $paramod$5d1d2614b24accd0f9d06c4779fd9ef771faf494\_90_demux for cells of type $demux. No more expansions possible. <suppressed ~5692 debug messages> 18.32. Executing OPT pass (performing simple optimizations). 18.32.1. Executing OPT_EXPR pass (perform const folding). Optimizing module processorci_top. <suppressed ~10438 debug messages> 18.32.2. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\processorci_top'. <suppressed ~4416 debug messages> Removed a total of 1472 cells. 18.32.3. Executing OPT_DFF pass (perform DFF optimizations). 18.32.4. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \processorci_top.. Removed 1676 unused cells and 5384 unused wires. <suppressed ~1682 debug messages> 18.32.5. Finished fast OPT passes. 18.33. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \processorci_top.. 18.34. Executing DFFLEGALIZE pass (convert FFs to types supported by the target). 18.35. Executing TECHMAP pass (map to technology primitives). 18.35.1. Executing Verilog-2005 frontend: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v Parsing Verilog input from `/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v' to AST representation. Generating RTLIL representation for module `\$_DFF_N_'. Generating RTLIL representation for module `\$_DFF_P_'. Generating RTLIL representation for module `\$_DFFE_NN_'. Generating RTLIL representation for module `\$_DFFE_PN_'. Generating RTLIL representation for module `\$_DFFE_NP_'. Generating RTLIL representation for module `\$_DFFE_PP_'. Generating RTLIL representation for module `\$_DFF_NP0_'. Generating RTLIL representation for module `\$_DFF_NP1_'. Generating RTLIL representation for module `\$_DFF_PP0_'. Generating RTLIL representation for module `\$_DFF_PP1_'. Generating RTLIL representation for module `\$_SDFF_NP0_'. Generating RTLIL representation for module `\$_SDFF_NP1_'. Generating RTLIL representation for module `\$_SDFF_PP0_'. Generating RTLIL representation for module `\$_SDFF_PP1_'. Generating RTLIL representation for module `\$_DFFE_NP0P_'. Generating RTLIL representation for module `\$_DFFE_NP1P_'. Generating RTLIL representation for module `\$_DFFE_PP0P_'. Generating RTLIL representation for module `\$_DFFE_PP1P_'. Generating RTLIL representation for module `\$_DFFE_NP0N_'. Generating RTLIL representation for module `\$_DFFE_NP1N_'. Generating RTLIL representation for module `\$_DFFE_PP0N_'. Generating RTLIL representation for module `\$_DFFE_PP1N_'. Generating RTLIL representation for module `\$_SDFFE_NP0P_'. Generating RTLIL representation for module `\$_SDFFE_NP1P_'. Generating RTLIL representation for module `\$_SDFFE_PP0P_'. Generating RTLIL representation for module `\$_SDFFE_PP1P_'. Generating RTLIL representation for module `\$_SDFFE_NP0N_'. Generating RTLIL representation for module `\$_SDFFE_NP1N_'. Generating RTLIL representation for module `\$_SDFFE_PP0N_'. Generating RTLIL representation for module `\$_SDFFE_PP1N_'. Generating RTLIL representation for module `\$_ALDFF_NP_'. Generating RTLIL representation for module `\$_ALDFF_PP_'. Generating RTLIL representation for module `\$_ALDFFE_NPN_'. Generating RTLIL representation for module `\$_ALDFFE_NPP_'. Generating RTLIL representation for module `\$_ALDFFE_PPN_'. Generating RTLIL representation for module `\$_ALDFFE_PPP_'. Generating RTLIL representation for module `\FD1P3AX'. Generating RTLIL representation for module `\FD1P3AY'. Generating RTLIL representation for module `\FD1P3BX'. Generating RTLIL representation for module `\FD1P3DX'. Generating RTLIL representation for module `\FD1P3IX'. Generating RTLIL representation for module `\FD1P3JX'. Generating RTLIL representation for module `\FD1S3AX'. Generating RTLIL representation for module `\FD1S3AY'. Generating RTLIL representation for module `\FD1S3BX'. Generating RTLIL representation for module `\FD1S3DX'. Generating RTLIL representation for module `\FD1S3IX'. Generating RTLIL representation for module `\FD1S3JX'. Generating RTLIL representation for module `\IFS1P3BX'. Generating RTLIL representation for module `\IFS1P3DX'. Generating RTLIL representation for module `\IFS1P3IX'. Generating RTLIL representation for module `\IFS1P3JX'. Generating RTLIL representation for module `\OFS1P3BX'. Generating RTLIL representation for module `\OFS1P3DX'. Generating RTLIL representation for module `\OFS1P3IX'. Generating RTLIL representation for module `\OFS1P3JX'. Generating RTLIL representation for module `\IB'. Generating RTLIL representation for module `\IBPU'. Generating RTLIL representation for module `\IBPD'. Generating RTLIL representation for module `\OB'. Generating RTLIL representation for module `\OBZ'. Generating RTLIL representation for module `\OBZPU'. Generating RTLIL representation for module `\OBZPD'. Generating RTLIL representation for module `\OBCO'. Generating RTLIL representation for module `\BB'. Generating RTLIL representation for module `\BBPU'. Generating RTLIL representation for module `\BBPD'. Generating RTLIL representation for module `\ILVDS'. Generating RTLIL representation for module `\OLVDS'. Successfully finished Verilog frontend. 18.35.2. Continuing TECHMAP pass. Using template $paramod\$_DFFE_PP_\_TECHMAP_WIREINIT_Q_=1'0 for cells of type $_DFFE_PP_. Using template \$_SDFFE_PP0P_ for cells of type $_SDFFE_PP0P_. Using template $paramod\$_DFFE_PP_\_TECHMAP_WIREINIT_Q_=1'x for cells of type $_DFFE_PP_. Using template $paramod\$_DFF_P_\_TECHMAP_WIREINIT_Q_=1'x for cells of type $_DFF_P_. Using template \$_SDFF_PP0_ for cells of type $_SDFF_PP0_. Using template \$_SDFF_PP1_ for cells of type $_SDFF_PP1_. Using template \$_SDFFE_PP0N_ for cells of type $_SDFFE_PP0N_. Using template \$_SDFFE_PP1P_ for cells of type $_SDFFE_PP1P_. Using template $paramod\$_DFFE_PN_\_TECHMAP_WIREINIT_Q_=1'x for cells of type $_DFFE_PN_. Using template \$_SDFFE_PP1N_ for cells of type $_SDFFE_PP1N_. Using template $paramod\$_DFFE_PP_\_TECHMAP_WIREINIT_Q_=1'1 for cells of type $_DFFE_PP_. No more expansions possible. <suppressed ~2474 debug messages> 18.36. Executing OPT_EXPR pass (perform const folding). Optimizing module processorci_top. <suppressed ~106 debug messages> 18.37. Executing SIMPLEMAP pass (map simple cells to gate primitives). 18.38. Executing LATTICE_GSR pass (implement FF init values). Handling GSR in processorci_top. 18.39. Executing ATTRMVCP pass (move or copy attributes). 18.40. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \processorci_top.. Removed 0 unused cells and 12183 unused wires. <suppressed ~1 debug messages> 18.41. Executing TECHMAP pass (map to technology primitives). 18.41.1. Executing Verilog-2005 frontend: /eda/oss-cad-suite/lib/../share/yosys/ecp5/latches_map.v Parsing Verilog input from `/eda/oss-cad-suite/lib/../share/yosys/ecp5/latches_map.v' to AST representation. Generating RTLIL representation for module `\$_DLATCH_N_'. Generating RTLIL representation for module `\$_DLATCH_P_'. Successfully finished Verilog frontend. 18.41.2. Continuing TECHMAP pass. No more expansions possible. <suppressed ~4 debug messages> 18.42. Executing ABC9 pass. 18.42.1. Executing ABC9_OPS pass (helper functions for ABC9). 18.42.2. Executing ABC9_OPS pass (helper functions for ABC9). 18.42.3. Executing PROC pass (convert processes to netlists). 18.42.3.1. Executing PROC_CLEAN pass (remove empty switches from decision trees). Found and cleaned up 1 empty switch in `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$42125'. Cleaned up 1 empty switch. 18.42.3.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees). Marked 1 switch rules as full_case in process $proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$42126 in module $paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4. Removed a total of 0 dead cases. 18.42.3.3. Executing PROC_PRUNE pass (remove redundant assignments in processes). Removed 0 redundant assignments. Promoted 22 assignments to connections. 18.42.3.4. Executing PROC_INIT pass (extract init attributes). 18.42.3.5. Executing PROC_ARST pass (detect async resets in processes). 18.42.3.6. Executing PROC_ROM pass (convert switches to ROMs). Converted 0 switches. <suppressed ~1 debug messages> 18.42.3.7. Executing PROC_MUX pass (convert decision trees to multiplexers). Creating decoders for process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$42150'. Creating decoders for process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$42126'. 1/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$42124_EN[3:0]$42132 2/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$42124_DATA[3:0]$42131 3/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$42124_ADDR[3:0]$42130 Creating decoders for process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$42125'. 18.42.3.8. Executing PROC_DLATCH pass (convert process syncs to latches). 18.42.3.9. Executing PROC_DFF pass (convert process syncs to FFs). Creating register for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.\i' using process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$42150'. created direct connection (no actual register cell created). Creating register for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$42119_EN' using process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$42150'. created direct connection (no actual register cell created). Creating register for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$42114_EN' using process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$42150'. created direct connection (no actual register cell created). Creating register for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$42109_EN' using process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$42150'. created direct connection (no actual register cell created). Creating register for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$42110_EN' using process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$42150'. created direct connection (no actual register cell created). Creating register for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$42111_EN' using process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$42150'. created direct connection (no actual register cell created). Creating register for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$42115_EN' using process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$42150'. created direct connection (no actual register cell created). Creating register for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$42116_EN' using process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$42150'. created direct connection (no actual register cell created). Creating register for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$42120_EN' using process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$42150'. created direct connection (no actual register cell created). Creating register for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$42112_EN' using process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$42150'. created direct connection (no actual register cell created). Creating register for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$42121_EN' using process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$42150'. created direct connection (no actual register cell created). Creating register for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$42108_EN' using process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$42150'. created direct connection (no actual register cell created). Creating register for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$42117_EN' using process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$42150'. created direct connection (no actual register cell created). Creating register for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$42113_EN' using process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$42150'. created direct connection (no actual register cell created). Creating register for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$42122_EN' using process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$42150'. created direct connection (no actual register cell created). Creating register for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$42118_EN' using process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$42150'. created direct connection (no actual register cell created). Creating register for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$42123_EN' using process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$42150'. created direct connection (no actual register cell created). Creating register for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$42124_ADDR' using process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$42126'. created $dff cell `$procdff$42176' with positive edge clock. Creating register for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$42124_DATA' using process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$42126'. created $dff cell `$procdff$42177' with positive edge clock. Creating register for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$42124_EN' using process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$42126'. created $dff cell `$procdff$42178' with positive edge clock. Creating register for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.\muxwre' using process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$42125'. created direct connection (no actual register cell created). 18.42.3.10. Executing PROC_MEMWR pass (convert process memory writes to cells). 18.42.3.11. Executing PROC_CLEAN pass (remove empty switches from decision trees). Removing empty process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$42150'. Found and cleaned up 1 empty switch in `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$42126'. Removing empty process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$42125'. Cleaned up 1 empty switch. 18.42.3.12. Executing OPT_EXPR pass (perform const folding). 18.42.4. Executing SCC pass (detecting logic loops). Found an SCC: $auto$opt_expr.cc:617:replace_const_cells$38404 $auto$ff.cc:266:slice$13448 $auto$simplemap.cc:126:simplemap_reduce$13617 $auto$simplemap.cc:126:simplemap_reduce$13632 $auto$ff.cc:266:slice$13447 $auto$ff.cc:266:slice$13446 $auto$opt_expr.cc:617:replace_const_cells$38410 $auto$simplemap.cc:267:simplemap_mux$30052 $auto$simplemap.cc:126:simplemap_reduce$30037 $auto$simplemap.cc:126:simplemap_reduce$30034 $auto$simplemap.cc:75:simplemap_bitop$30050 $auto$simplemap.cc:267:simplemap_mux$13601 $auto$simplemap.cc:225:simplemap_logbin$13604 $auto$simplemap.cc:196:simplemap_lognot$13621 $auto$simplemap.cc:126:simplemap_reduce$13619 $auto$simplemap.cc:126:simplemap_reduce$13616 $auto$simplemap.cc:38:simplemap_not$29979 $auto$simplemap.cc:196:simplemap_lognot$13636 $auto$simplemap.cc:126:simplemap_reduce$13634 $auto$simplemap.cc:126:simplemap_reduce$13631 $auto$ff.cc:266:slice$13445 $auto$simplemap.cc:126:simplemap_reduce$9280 $auto$simplemap.cc:126:simplemap_reduce$9278 $auto$simplemap.cc:225:simplemap_logbin$13560 $auto$simplemap.cc:196:simplemap_lognot$13570 $auto$simplemap.cc:126:simplemap_reduce$13568 $auto$opt_expr.cc:617:replace_const_cells$38408 $auto$simplemap.cc:267:simplemap_mux$30051 $auto$simplemap.cc:126:simplemap_reduce$30042 $auto$simplemap.cc:126:simplemap_reduce$30039 $auto$simplemap.cc:75:simplemap_bitop$30047 Found an SCC: $auto$ff.cc:266:slice$19173 $auto$ff.cc:266:slice$19172 $auto$simplemap.cc:126:simplemap_reduce$20359 $auto$ff.cc:266:slice$19171 $auto$ff.cc:266:slice$19170 $auto$simplemap.cc:126:simplemap_reduce$20363 $auto$simplemap.cc:126:simplemap_reduce$20361 $auto$simplemap.cc:126:simplemap_reduce$20358 $auto$ff.cc:266:slice$19169 $auto$simplemap.cc:126:simplemap_reduce$9252 $auto$simplemap.cc:225:simplemap_logbin$20319 $auto$simplemap.cc:225:simplemap_logbin$20419 $auto$simplemap.cc:75:simplemap_bitop$16325 $auto$simplemap.cc:75:simplemap_bitop$16359 $auto$simplemap.cc:75:simplemap_bitop$20367 $auto$ff.cc:266:slice$18927 $auto$simplemap.cc:75:simplemap_bitop$16310 $auto$simplemap.cc:75:simplemap_bitop$19970 $auto$simplemap.cc:75:simplemap_bitop$20389 $auto$ff.cc:266:slice$18926 $auto$simplemap.cc:75:simplemap_bitop$16309 $auto$simplemap.cc:75:simplemap_bitop$19969 $auto$simplemap.cc:75:simplemap_bitop$20388 $auto$ff.cc:266:slice$18925 $auto$simplemap.cc:75:simplemap_bitop$16307 $auto$simplemap.cc:75:simplemap_bitop$19967 $auto$simplemap.cc:75:simplemap_bitop$20386 $auto$ff.cc:266:slice$18923 $auto$simplemap.cc:126:simplemap_reduce$16297 $auto$simplemap.cc:126:simplemap_reduce$16314 $auto$simplemap.cc:75:simplemap_bitop$16306 $auto$simplemap.cc:126:simplemap_reduce$19974 $auto$simplemap.cc:75:simplemap_bitop$19966 $auto$simplemap.cc:126:simplemap_reduce$20393 $auto$simplemap.cc:75:simplemap_bitop$20385 $auto$ff.cc:266:slice$18922 $auto$simplemap.cc:126:simplemap_reduce$16302 $auto$simplemap.cc:126:simplemap_reduce$16300 $auto$simplemap.cc:126:simplemap_reduce$16298 $auto$simplemap.cc:225:simplemap_logbin$16322 $auto$simplemap.cc:196:simplemap_lognot$16321 $auto$simplemap.cc:126:simplemap_reduce$16319 $auto$simplemap.cc:126:simplemap_reduce$16317 $auto$simplemap.cc:126:simplemap_reduce$16315 $auto$simplemap.cc:75:simplemap_bitop$16308 $auto$simplemap.cc:267:simplemap_mux$16388 $auto$simplemap.cc:126:simplemap_reduce$20355 $auto$simplemap.cc:225:simplemap_logbin$16303 $auto$simplemap.cc:196:simplemap_lognot$19981 $auto$simplemap.cc:126:simplemap_reduce$19979 $auto$simplemap.cc:126:simplemap_reduce$19977 $auto$simplemap.cc:126:simplemap_reduce$19975 $auto$simplemap.cc:75:simplemap_bitop$19968 $auto$ff.cc:266:slice$18924 $auto$simplemap.cc:75:simplemap_bitop$16327 $auto$simplemap.cc:75:simplemap_bitop$16361 $auto$simplemap.cc:75:simplemap_bitop$20369 $auto$ff.cc:266:slice$18929 $auto$simplemap.cc:126:simplemap_reduce$16333 $auto$simplemap.cc:75:simplemap_bitop$16326 $auto$simplemap.cc:126:simplemap_reduce$16342 $auto$simplemap.cc:126:simplemap_reduce$16367 $auto$simplemap.cc:75:simplemap_bitop$16360 $auto$simplemap.cc:126:simplemap_reduce$20375 $auto$simplemap.cc:75:simplemap_bitop$20368 $auto$ff.cc:266:slice$18928 $auto$simplemap.cc:75:simplemap_bitop$16329 $auto$simplemap.cc:75:simplemap_bitop$16363 $auto$simplemap.cc:75:simplemap_bitop$20371 $auto$ff.cc:266:slice$18931 $auto$simplemap.cc:196:simplemap_lognot$16340 $auto$simplemap.cc:126:simplemap_reduce$16338 $auto$simplemap.cc:126:simplemap_reduce$16336 $auto$simplemap.cc:126:simplemap_reduce$16334 $auto$simplemap.cc:75:simplemap_bitop$16328 $auto$simplemap.cc:225:simplemap_logbin$16348 $auto$simplemap.cc:126:simplemap_reduce$16347 $auto$simplemap.cc:126:simplemap_reduce$16345 $auto$simplemap.cc:126:simplemap_reduce$16343 $auto$simplemap.cc:225:simplemap_logbin$20349 $auto$simplemap.cc:225:simplemap_logbin$20350 $auto$simplemap.cc:126:simplemap_reduce$20353 $auto$simplemap.cc:267:simplemap_mux$16386 $auto$simplemap.cc:225:simplemap_logbin$16377 $auto$simplemap.cc:196:simplemap_lognot$16374 $auto$simplemap.cc:126:simplemap_reduce$16372 $auto$simplemap.cc:126:simplemap_reduce$16370 $auto$simplemap.cc:126:simplemap_reduce$16368 $auto$simplemap.cc:75:simplemap_bitop$16362 $auto$simplemap.cc:196:simplemap_lognot$20382 $auto$simplemap.cc:126:simplemap_reduce$20380 $auto$simplemap.cc:126:simplemap_reduce$20378 $auto$simplemap.cc:126:simplemap_reduce$20376 $auto$simplemap.cc:75:simplemap_bitop$20370 $auto$ff.cc:266:slice$18930 $auto$simplemap.cc:225:simplemap_logbin$20418 $auto$simplemap.cc:225:simplemap_logbin$20422 $auto$simplemap.cc:225:simplemap_logbin$20423 $auto$simplemap.cc:38:simplemap_not$9246 $auto$simplemap.cc:225:simplemap_logbin$20348 $auto$simplemap.cc:225:simplemap_logbin$20356 $auto$simplemap.cc:225:simplemap_logbin$20364 $auto$simplemap.cc:196:simplemap_lognot$20400 $auto$simplemap.cc:126:simplemap_reduce$20398 $auto$simplemap.cc:126:simplemap_reduce$20396 $auto$simplemap.cc:126:simplemap_reduce$20394 $auto$simplemap.cc:75:simplemap_bitop$20387 Found an SCC: $auto$simplemap.cc:126:simplemap_reduce$9126 $auto$simplemap.cc:126:simplemap_reduce$9193 $auto$simplemap.cc:126:simplemap_reduce$9191 $auto$simplemap.cc:126:simplemap_reduce$9129 $auto$simplemap.cc:126:simplemap_reduce$9127 $auto$simplemap.cc:38:simplemap_not$12632 $auto$ff.cc:266:slice$21088 $auto$ff.cc:479:convert_ce_over_srst$39646 $auto$simplemap.cc:38:simplemap_not$25286 $auto$ff.cc:266:slice$21087 $auto$ff.cc:479:convert_ce_over_srst$39644 $auto$simplemap.cc:126:simplemap_reduce$9254 $auto$simplemap.cc:38:simplemap_not$25285 $auto$alumacc.cc:485:replace_alu$3500.slice[0].ccu2c_i $auto$ff.cc:266:slice$21086 $auto$ff.cc:479:convert_ce_over_srst$39642 $auto$simplemap.cc:38:simplemap_not$33504 $auto$ff.cc:266:slice$21091 $auto$ff.cc:479:convert_ce_over_srst$39652 $auto$simplemap.cc:126:simplemap_reduce$9256 $auto$ff.cc:266:slice$21090 $auto$ff.cc:479:convert_ce_over_srst$39650 $auto$simplemap.cc:38:simplemap_not$9305 $auto$alumacc.cc:485:replace_alu$3500.slice[4].ccu2c_i $auto$alumacc.cc:485:replace_alu$3500.slice[2].ccu2c_i $auto$simplemap.cc:38:simplemap_not$25288 $auto$ff.cc:266:slice$21089 $auto$ff.cc:479:convert_ce_over_srst$39648 $auto$simplemap.cc:126:simplemap_reduce$21099 $auto$simplemap.cc:75:simplemap_bitop$9355 $auto$simplemap.cc:126:simplemap_reduce$9260 $auto$simplemap.cc:126:simplemap_reduce$9258 $auto$simplemap.cc:126:simplemap_reduce$9255 Found an SCC: $auto$opt_expr.cc:617:replace_const_cells$38402 $auto$ff.cc:266:slice$13456 $auto$ff.cc:266:slice$13454 $auto$ff.cc:266:slice$13457 $auto$simplemap.cc:126:simplemap_reduce$13654 $auto$opt_expr.cc:617:replace_const_cells$38400 $auto$ff.cc:266:slice$13455 $auto$simplemap.cc:126:simplemap_reduce$13657 $auto$simplemap.cc:126:simplemap_reduce$13653 $auto$opt_expr.cc:617:replace_const_cells$38398 $auto$ff.cc:266:slice$13453 $auto$ff.cc:266:slice$13452 $auto$ff.cc:266:slice$13451 $auto$ff.cc:266:slice$13450 $auto$simplemap.cc:126:simplemap_reduce$13651 $auto$opt_expr.cc:617:replace_const_cells$38394 $auto$ff.cc:266:slice$13449 $auto$simplemap.cc:126:simplemap_reduce$9318 $auto$simplemap.cc:196:simplemap_lognot$13663 $auto$simplemap.cc:126:simplemap_reduce$13661 $auto$simplemap.cc:126:simplemap_reduce$13659 $auto$simplemap.cc:126:simplemap_reduce$13656 $auto$simplemap.cc:126:simplemap_reduce$13652 $auto$simplemap.cc:38:simplemap_not$30251 Found an SCC: $auto$opt_expr.cc:617:replace_const_cells$38376 $auto$ff.cc:266:slice$13287 $auto$simplemap.cc:126:simplemap_reduce$13397 $auto$simplemap.cc:126:simplemap_reduce$13428 $auto$opt_expr.cc:617:replace_const_cells$38374 $auto$ff.cc:266:slice$13286 $auto$opt_expr.cc:617:replace_const_cells$38364 $auto$ff.cc:266:slice$13285 $auto$ff.cc:266:slice$13281 $auto$ff.cc:266:slice$13288 $auto$simplemap.cc:126:simplemap_reduce$13431 $auto$simplemap.cc:126:simplemap_reduce$13427 $auto$simplemap.cc:38:simplemap_not$30027 $auto$ff.cc:266:slice$13284 $auto$simplemap.cc:38:simplemap_not$30026 $auto$ff.cc:266:slice$13283 $auto$simplemap.cc:126:simplemap_reduce$13426 $auto$simplemap.cc:126:simplemap_reduce$13395 $auto$simplemap.cc:38:simplemap_not$30025 $auto$ff.cc:266:slice$13282 $auto$simplemap.cc:196:simplemap_lognot$13437 $auto$simplemap.cc:126:simplemap_reduce$13435 $auto$simplemap.cc:126:simplemap_reduce$13433 $auto$simplemap.cc:126:simplemap_reduce$13430 $auto$simplemap.cc:126:simplemap_reduce$13425 $auto$simplemap.cc:38:simplemap_not$30023 $auto$simplemap.cc:126:simplemap_reduce$13399 $auto$simplemap.cc:126:simplemap_reduce$13394 $auto$ff.cc:266:slice$13280 $auto$simplemap.cc:167:logic_reduce$9152 $auto$simplemap.cc:225:simplemap_logbin$13378 $auto$simplemap.cc:225:simplemap_logbin$13379 $auto$simplemap.cc:196:simplemap_lognot$13406 $auto$simplemap.cc:126:simplemap_reduce$13404 $auto$simplemap.cc:126:simplemap_reduce$13402 $auto$simplemap.cc:126:simplemap_reduce$13400 $auto$simplemap.cc:126:simplemap_reduce$13396 Found 5 SCCs in module processorci_top. Found 5 SCCs. 18.42.5. Executing ABC9_OPS pass (helper functions for ABC9). 18.42.6. Executing PROC pass (convert processes to netlists). 18.42.6.1. Executing PROC_CLEAN pass (remove empty switches from decision trees). Cleaned up 0 empty switches. 18.42.6.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees). Removed a total of 0 dead cases. 18.42.6.3. Executing PROC_PRUNE pass (remove redundant assignments in processes). Removed 0 redundant assignments. Promoted 0 assignments to connections. 18.42.6.4. Executing PROC_INIT pass (extract init attributes). 18.42.6.5. Executing PROC_ARST pass (detect async resets in processes). 18.42.6.6. Executing PROC_ROM pass (convert switches to ROMs). Converted 0 switches. 18.42.6.7. Executing PROC_MUX pass (convert decision trees to multiplexers). 18.42.6.8. Executing PROC_DLATCH pass (convert process syncs to latches). 18.42.6.9. Executing PROC_DFF pass (convert process syncs to FFs). 18.42.6.10. Executing PROC_MEMWR pass (convert process memory writes to cells). 18.42.6.11. Executing PROC_CLEAN pass (remove empty switches from decision trees). Cleaned up 0 empty switches. 18.42.6.12. Executing OPT_EXPR pass (perform const folding). 18.42.7. Executing TECHMAP pass (map to technology primitives). 18.42.7.1. Executing Verilog-2005 frontend: /eda/oss-cad-suite/lib/../share/yosys/techmap.v Parsing Verilog input from `/eda/oss-cad-suite/lib/../share/yosys/techmap.v' to AST representation. Generating RTLIL representation for module `\_90_simplemap_bool_ops'. Generating RTLIL representation for module `\_90_simplemap_reduce_ops'. Generating RTLIL representation for module `\_90_simplemap_logic_ops'. Generating RTLIL representation for module `\_90_simplemap_compare_ops'. Generating RTLIL representation for module `\_90_simplemap_various'. Generating RTLIL representation for module `\_90_simplemap_registers'. Generating RTLIL representation for module `\_90_shift_ops_shr_shl_sshl_sshr'. Generating RTLIL representation for module `\_90_shift_shiftx'. Generating RTLIL representation for module `\_90_fa'. Generating RTLIL representation for module `\_90_lcu_brent_kung'. Generating RTLIL representation for module `\_90_alu'. Generating RTLIL representation for module `\_90_macc'. Generating RTLIL representation for module `\_90_alumacc'. Generating RTLIL representation for module `\$__div_mod_u'. Generating RTLIL representation for module `\$__div_mod_trunc'. Generating RTLIL representation for module `\_90_div'. Generating RTLIL representation for module `\_90_mod'. Generating RTLIL representation for module `\$__div_mod_floor'. Generating RTLIL representation for module `\_90_divfloor'. Generating RTLIL representation for module `\_90_modfloor'. Generating RTLIL representation for module `\_90_pow'. Generating RTLIL representation for module `\_90_pmux'. Generating RTLIL representation for module `\_90_demux'. Generating RTLIL representation for module `\_90_lut'. Successfully finished Verilog frontend. 18.42.7.2. Continuing TECHMAP pass. No more expansions possible. <suppressed ~162 debug messages> 18.42.8. Executing OPT pass (performing simple optimizations). 18.42.8.1. Executing OPT_EXPR pass (perform const folding). Optimizing module $paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4. 18.42.8.2. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4'. Removed a total of 0 cells. 18.42.8.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees). Running muxtree optimizer on module $paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.. Creating internal representation of mux trees. No muxes found in this module. Removed 0 multiplexer ports. 18.42.8.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). Optimizing cells in module $paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4. Performed a total of 0 changes. 18.42.8.5. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4'. Removed a total of 0 cells. 18.42.8.6. Executing OPT_DFF pass (perform DFF optimizations). 18.42.8.7. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module $paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.. 18.42.8.8. Executing OPT_EXPR pass (perform const folding). Optimizing module $paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4. 18.42.8.9. Finished OPT passes. (There is nothing left to do.) 18.42.9. Executing TECHMAP pass (map to technology primitives). 18.42.9.1. Executing Verilog-2005 frontend: /eda/oss-cad-suite/lib/../share/yosys/abc9_map.v Parsing Verilog input from `/eda/oss-cad-suite/lib/../share/yosys/abc9_map.v' to AST representation. Successfully finished Verilog frontend. 18.42.9.2. Continuing TECHMAP pass. Using template $paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4 for cells of type $paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4. No more expansions possible. <suppressed ~1031 debug messages> 18.42.10. Executing Verilog-2005 frontend: /eda/oss-cad-suite/lib/../share/yosys/abc9_model.v Parsing Verilog input from `/eda/oss-cad-suite/lib/../share/yosys/abc9_model.v' to AST representation. Generating RTLIL representation for module `$__ABC9_DELAY'. Generating RTLIL representation for module `$__ABC9_SCC_BREAKER'. Generating RTLIL representation for module `$__DFF_N__$abc9_flop'. Generating RTLIL representation for module `$__DFF_P__$abc9_flop'. Successfully finished Verilog frontend. 18.42.11. Executing ABC9_OPS pass (helper functions for ABC9). <suppressed ~2 debug messages> 18.42.12. Executing ABC9_OPS pass (helper functions for ABC9). 18.42.13. Executing ABC9_OPS pass (helper functions for ABC9). <suppressed ~2 debug messages> 18.42.14. Executing TECHMAP pass (map to technology primitives). 18.42.14.1. Executing Verilog-2005 frontend: /eda/oss-cad-suite/lib/../share/yosys/techmap.v Parsing Verilog input from `/eda/oss-cad-suite/lib/../share/yosys/techmap.v' to AST representation. Generating RTLIL representation for module `\_90_simplemap_bool_ops'. Generating RTLIL representation for module `\_90_simplemap_reduce_ops'. Generating RTLIL representation for module `\_90_simplemap_logic_ops'. Generating RTLIL representation for module `\_90_simplemap_compare_ops'. Generating RTLIL representation for module `\_90_simplemap_various'. Generating RTLIL representation for module `\_90_simplemap_registers'. Generating RTLIL representation for module `\_90_shift_ops_shr_shl_sshl_sshr'. Generating RTLIL representation for module `\_90_shift_shiftx'. Generating RTLIL representation for module `\_90_fa'. Generating RTLIL representation for module `\_90_lcu_brent_kung'. Generating RTLIL representation for module `\_90_alu'. Generating RTLIL representation for module `\_90_macc'. Generating RTLIL representation for module `\_90_alumacc'. Generating RTLIL representation for module `\$__div_mod_u'. Generating RTLIL representation for module `\$__div_mod_trunc'. Generating RTLIL representation for module `\_90_div'. Generating RTLIL representation for module `\_90_mod'. Generating RTLIL representation for module `\$__div_mod_floor'. Generating RTLIL representation for module `\_90_divfloor'. Generating RTLIL representation for module `\_90_modfloor'. Generating RTLIL representation for module `\_90_pow'. Generating RTLIL representation for module `\_90_pmux'. Generating RTLIL representation for module `\_90_demux'. Generating RTLIL representation for module `\_90_lut'. Successfully finished Verilog frontend. 18.42.14.2. Continuing TECHMAP pass. Using template $paramod$838872d5a4bab89607f53482b205c0fd50d8b82e\CCU2C for cells of type $paramod$838872d5a4bab89607f53482b205c0fd50d8b82e\CCU2C. Using template $paramod\LUT4\INIT=16'1001011010101010 for cells of type LUT4. Using extmapper simplemap for cells of type $or. Using extmapper simplemap for cells of type $and. Using extmapper simplemap for cells of type $not. Using extmapper simplemap for cells of type $xor. Using template $paramod\LUT2\INIT=4'1010 for cells of type LUT2. Using extmapper simplemap for cells of type $mux. No more expansions possible. <suppressed ~201 debug messages> 18.42.15. Executing OPT pass (performing simple optimizations). 18.42.15.1. Executing OPT_EXPR pass (perform const folding). Optimizing module processorci_top. <suppressed ~18 debug messages> 18.42.15.2. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\processorci_top'. <suppressed ~6 debug messages> Removed a total of 2 cells. 18.42.15.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees). Running muxtree optimizer on module \processorci_top.. Creating internal representation of mux trees. No muxes found in this module. Removed 0 multiplexer ports. 18.42.15.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). Optimizing cells in module \processorci_top. Performed a total of 0 changes. 18.42.15.5. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\processorci_top'. Removed a total of 0 cells. 18.42.15.6. Executing OPT_DFF pass (perform DFF optimizations). 18.42.15.7. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \processorci_top.. Removed 0 unused cells and 55 unused wires. <suppressed ~1 debug messages> 18.42.15.8. Executing OPT_EXPR pass (perform const folding). Optimizing module processorci_top. 18.42.15.9. Rerunning OPT passes. (Maybe there is more to do..) 18.42.15.10. Executing OPT_MUXTREE pass (detect dead branches in mux trees). Running muxtree optimizer on module \processorci_top.. Creating internal representation of mux trees. No muxes found in this module. Removed 0 multiplexer ports. 18.42.15.11. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). Optimizing cells in module \processorci_top. Performed a total of 0 changes. 18.42.15.12. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\processorci_top'. Removed a total of 0 cells. 18.42.15.13. Executing OPT_DFF pass (perform DFF optimizations). 18.42.15.14. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \processorci_top.. 18.42.15.15. Executing OPT_EXPR pass (perform const folding). Optimizing module processorci_top. 18.42.15.16. Finished OPT passes. (There is nothing left to do.) 18.42.16. Executing AIGMAP pass (map logic to AIG). Module processorci_top: replaced 18 cells with 120 new cells, skipped 39 cells. replaced 3 cell types: 2 $_OR_ 2 $_XOR_ 14 $_MUX_ not replaced 3 cell types: 31 $specify2 4 $_NOT_ 4 $_AND_ 18.42.17. Executing AIGMAP pass (map logic to AIG). Module processorci_top: replaced 9568 cells with 61915 new cells, skipped 6554 cells. replaced 3 cell types: 1687 $_OR_ 282 $_XOR_ 7599 $_MUX_ not replaced 8 cell types: 19 $scopeinfo 468 $_NOT_ 1377 $_AND_ 2348 TRELLIS_FF 1 $__ABC9_SCC_BREAKER 285 $paramod$838872d5a4bab89607f53482b205c0fd50d8b82e\CCU2C 1028 $paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4_$abc9_byp 1028 $paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4 18.42.17.1. Executing ABC9_OPS pass (helper functions for ABC9). 18.42.17.2. Executing ABC9_OPS pass (helper functions for ABC9). 18.42.17.3. Executing XAIGER backend. <suppressed ~11 debug messages> Extracted 26707 AND gates and 76308 wires from module `processorci_top' to a netlist network with 6472 inputs and 1768 outputs. 18.42.17.4. Executing ABC9_EXE pass (technology mapping using ABC9). 18.42.17.5. Executing ABC9. Running ABC command: "<yosys-exe-dir>/yosys-abc" -s -f <abc-temp-dir>/abc.script 2>&1 ABC: ABC command line: "source <abc-temp-dir>/abc.script". ABC: ABC: + read_lut <abc-temp-dir>/input.lut ABC: + read_box <abc-temp-dir>/input.box ABC: + &read <abc-temp-dir>/input.xaig ABC: + &ps ABC: <abc-temp-dir>/input : i/o = 6472/ 1768 and = 25229 lev = 23 (1.53) mem = 0.66 MB box = 1313 bb = 1028 ABC: + &scorr ABC: Warning: The network is combinational. ABC: + &sweep ABC: + &dc2 ABC: + &dch -f ABC: + &ps ABC: <abc-temp-dir>/input : i/o = 6472/ 1768 and = 35448 lev = 63 (1.40) mem = 0.77 MB ch = 4258 box = 1313 bb = 1028 ABC: + &if -W 300 -v ABC: K = 7. Memory (bytes): Truth = 0. Cut = 64. Obj = 148. Set = 672. CutMin = no ABC: Node = 35448. Ch = 3246. Total mem = 9.30 MB. Peak cut mem = 0.27 MB. ABC: P: Del = 4376.00. Ar = 28559.0. Edge = 33920. Cut = 381058. T = 0.09 sec ABC: P: Del = 4376.00. Ar = 28049.0. Edge = 33466. Cut = 377993. T = 0.09 sec ABC: P: Del = 4376.00. Ar = 10737.0. Edge = 28717. Cut = 886026. T = 0.21 sec ABC: F: Del = 4376.00. Ar = 8507.0. Edge = 26986. Cut = 598486. T = 0.15 sec ABC: A: Del = 4376.00. Ar = 7893.0. Edge = 25051. Cut = 554725. T = 0.23 sec ABC: A: Del = 4376.00. Ar = 7832.0. Edge = 24857. Cut = 575219. T = 0.24 sec ABC: Total time = 1.03 sec ABC: + &write -n <abc-temp-dir>/output.aig ABC: + &mfs ABC: + &ps -l ABC: <abc-temp-dir>/input : i/o = 6472/ 1768 and = 21366 lev = 23 (1.42) mem = 0.61 MB box = 1313 bb = 1028 ABC: Mapping (K=7) : lut = 6286 edge = 24808 lev = 9 (0.76) Boxes are not in a topological order. Switching to level computation without boxes. ABC: levB = 23 mem = 0.32 MB ABC: LUT = 6286 : 2=374 5.9 % 3=916 14.6 % 4=3796 60.4 % 5=1100 17.5 % 6=72 1.1 % 7=28 0.4 % Ave = 3.95 ABC: + &write -n <abc-temp-dir>/output.aig ABC: + time ABC: elapse: 5.07 seconds, total: 5.07 seconds 18.42.17.6. Executing AIGER frontend. <suppressed ~16492 debug messages> Removed 30915 unused cells and 59611 unused wires. 18.42.17.7. Executing ABC9_OPS pass (helper functions for ABC9). ABC RESULTS: $lut cells: 6298 ABC RESULTS: $paramod$838872d5a4bab89607f53482b205c0fd50d8b82e\CCU2C cells: 285 ABC RESULTS: $paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4_$abc9_byp cells: 1028 ABC RESULTS: input signals: 1161 ABC RESULTS: output signals: 335 Removing temp directory. 18.42.18. Executing TECHMAP pass (map to technology primitives). 18.42.18.1. Executing Verilog-2005 frontend: /eda/oss-cad-suite/lib/../share/yosys/abc9_unmap.v Parsing Verilog input from `/eda/oss-cad-suite/lib/../share/yosys/abc9_unmap.v' to AST representation. Generating RTLIL representation for module `\$__DFF_x__$abc9_flop'. Generating RTLIL representation for module `\$__ABC9_SCC_BREAKER'. Successfully finished Verilog frontend. 18.42.18.2. Continuing TECHMAP pass. Using template $paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4 for cells of type $paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4. Using template $paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4_$abc9_byp for cells of type $paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4_$abc9_byp. Using template $paramod$838872d5a4bab89607f53482b205c0fd50d8b82e\CCU2C for cells of type $paramod$838872d5a4bab89607f53482b205c0fd50d8b82e\CCU2C. Using template $paramod\$__ABC9_SCC_BREAKER\WIDTH=32'00000000000000000000000000000111 for cells of type $__ABC9_SCC_BREAKER. No more expansions possible. <suppressed ~2361 debug messages> Removed 480 unused cells and 92408 unused wires. 18.43. Executing TECHMAP pass (map to technology primitives). 18.43.1. Executing Verilog-2005 frontend: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v Parsing Verilog input from `/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v' to AST representation. Generating RTLIL representation for module `\$_DFF_N_'. Generating RTLIL representation for module `\$_DFF_P_'. Generating RTLIL representation for module `\$_DFFE_NN_'. Generating RTLIL representation for module `\$_DFFE_PN_'. Generating RTLIL representation for module `\$_DFFE_NP_'. Generating RTLIL representation for module `\$_DFFE_PP_'. Generating RTLIL representation for module `\$_DFF_NP0_'. Generating RTLIL representation for module `\$_DFF_NP1_'. Generating RTLIL representation for module `\$_DFF_PP0_'. Generating RTLIL representation for module `\$_DFF_PP1_'. Generating RTLIL representation for module `\$_SDFF_NP0_'. Generating RTLIL representation for module `\$_SDFF_NP1_'. Generating RTLIL representation for module `\$_SDFF_PP0_'. Generating RTLIL representation for module `\$_SDFF_PP1_'. Generating RTLIL representation for module `\$_DFFE_NP0P_'. Generating RTLIL representation for module `\$_DFFE_NP1P_'. Generating RTLIL representation for module `\$_DFFE_PP0P_'. Generating RTLIL representation for module `\$_DFFE_PP1P_'. Generating RTLIL representation for module `\$_DFFE_NP0N_'. Generating RTLIL representation for module `\$_DFFE_NP1N_'. Generating RTLIL representation for module `\$_DFFE_PP0N_'. Generating RTLIL representation for module `\$_DFFE_PP1N_'. Generating RTLIL representation for module `\$_SDFFE_NP0P_'. Generating RTLIL representation for module `\$_SDFFE_NP1P_'. Generating RTLIL representation for module `\$_SDFFE_PP0P_'. Generating RTLIL representation for module `\$_SDFFE_PP1P_'. Generating RTLIL representation for module `\$_SDFFE_NP0N_'. Generating RTLIL representation for module `\$_SDFFE_NP1N_'. Generating RTLIL representation for module `\$_SDFFE_PP0N_'. Generating RTLIL representation for module `\$_SDFFE_PP1N_'. Generating RTLIL representation for module `\$_ALDFF_NP_'. Generating RTLIL representation for module `\$_ALDFF_PP_'. Generating RTLIL representation for module `\$_ALDFFE_NPN_'. Generating RTLIL representation for module `\$_ALDFFE_NPP_'. Generating RTLIL representation for module `\$_ALDFFE_PPN_'. Generating RTLIL representation for module `\$_ALDFFE_PPP_'. Generating RTLIL representation for module `\FD1P3AX'. Generating RTLIL representation for module `\FD1P3AY'. Generating RTLIL representation for module `\FD1P3BX'. Generating RTLIL representation for module `\FD1P3DX'. Generating RTLIL representation for module `\FD1P3IX'. Generating RTLIL representation for module `\FD1P3JX'. Generating RTLIL representation for module `\FD1S3AX'. Generating RTLIL representation for module `\FD1S3AY'. Generating RTLIL representation for module `\FD1S3BX'. Generating RTLIL representation for module `\FD1S3DX'. Generating RTLIL representation for module `\FD1S3IX'. Generating RTLIL representation for module `\FD1S3JX'. Generating RTLIL representation for module `\IFS1P3BX'. Generating RTLIL representation for module `\IFS1P3DX'. Generating RTLIL representation for module `\IFS1P3IX'. Generating RTLIL representation for module `\IFS1P3JX'. Generating RTLIL representation for module `\OFS1P3BX'. Generating RTLIL representation for module `\OFS1P3DX'. Generating RTLIL representation for module `\OFS1P3IX'. Generating RTLIL representation for module `\OFS1P3JX'. Generating RTLIL representation for module `\IB'. Generating RTLIL representation for module `\IBPU'. Generating RTLIL representation for module `\IBPD'. Generating RTLIL representation for module `\OB'. Generating RTLIL representation for module `\OBZ'. Generating RTLIL representation for module `\OBZPU'. Generating RTLIL representation for module `\OBZPD'. Generating RTLIL representation for module `\OBCO'. Generating RTLIL representation for module `\BB'. Generating RTLIL representation for module `\BBPU'. Generating RTLIL representation for module `\BBPD'. Generating RTLIL representation for module `\ILVDS'. Generating RTLIL representation for module `\OLVDS'. Generating RTLIL representation for module `\$lut'. Successfully finished Verilog frontend. 18.43.2. Continuing TECHMAP pass. Using template $paramod$cbea2d4d520f64cae694e02ff7f67ddafd2047d5\$lut for cells of type $lut. Using template $paramod$2d07c1a6c53c7b878509360922c4fa5ebedc3011\$lut for cells of type $lut. Using template $paramod$0acc8d601702e9b60288baa3d5cf1d38d4f22457\$lut for cells of type $lut. Using template $paramod$b04f0510561c4bbb703d2e39c6eca682b920366b\$lut for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00000010 for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000010\LUT=4'0001 for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000010\LUT=4'0100 for cells of type $lut. Using template $paramod$8f986caed758d4e6ddf0982fe58e5dab967f469f\$lut for cells of type $lut. Using template $paramod$4045162732ff1ef3063f7c74bcf446c45645f6c6\$lut for cells of type $lut. Using template $paramod$23da582b86241546eace0c8bedadb42614eea4c1\$lut for cells of type $lut. Using template $paramod$086937f2e69afb7c662e45e33f5a7616aa818da8\$lut for cells of type $lut. Using template $paramod$07d604fa63557df73201af3ab3c9bef4e6969c47\$lut for cells of type $lut. Using template $paramod$a63014c5e66a56dc5e61848489c809a59ebe7c34\$lut for cells of type $lut. Using template $paramod$4853050665c020c8d21fb1a749196950a09d9df8\$lut for cells of type $lut. Using template $paramod$7c1f6afe503c0a9d86df3082e3bb8088dcf2d22b\$lut for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000010\LUT=4'1110 for cells of type $lut. Using template $paramod$7bb6a37e65823eeb4b38c370fec30ab082759a14\$lut for cells of type $lut. Using template $paramod$df196ed0a1da5c4a58c5e08a1dac304fd3fccaab\$lut for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00100000 for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'01000101 for cells of type $lut. Using template $paramod$41326ad8644342a66dfb051d050f2b6fbf15015b\$lut for cells of type $lut. Using template $paramod$c2842ed6ac328d347b6d1c2cecf2b583dc6a8707\$lut for cells of type $lut. Using template $paramod$8384e66d408d22ab39dfb451efb7879731befeb8\$lut for cells of type $lut. Using template $paramod$f24ba3ced4b870f8e829f5ac5a8af88573350e6f\$lut for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'10101100 for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'11001010 for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'10000000 for cells of type $lut. Using template $paramod$12d55b60f0f4993cdeef74f2f65f385722841c5f\$lut for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'01000000 for cells of type $lut. Using template $paramod$272652f6c6fbe9a75eff76e45cc7e2788835518b\$lut for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000010\LUT=4'1000 for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00000111 for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00000001 for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000010\LUT=4'0111 for cells of type $lut. Using template $paramod$571404c0889eaf57f492cb5e37f8acb5df5852f9\$lut for cells of type $lut. Using template $paramod$5902906301514119c4dfc3edda247092b16ab7fc\$lut for cells of type $lut. Using template $paramod$5321e04f7ce32c091123c3570ab562efb1c81402\$lut for cells of type $lut. Using template $paramod$e51a8a571bee774247b38f52d6e85fd62ae52cea\$lut for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00010000 for cells of type $lut. Using template $paramod$b4f5c470ef365ae6640a1f15324955674ee0bcf2\$lut for cells of type $lut. Using template $paramod$364c9ffbffac467d60dfec81bba4e18476c15602\$lut for cells of type $lut. Using template $paramod$c4a4cf1f67c598049dd5cb5cdb183838e000e772\$lut for cells of type $lut. Using template $paramod$cf652acbfbf67d2248e3045cd0f09c58ca55886c\$lut for cells of type $lut. Using template $paramod$9becc6376cac3c55b34ebe436ca01b702d34d09e\$lut for cells of type $lut. Using template $paramod$101238f3d8d49ab12a9b49a2f01cd503b26e9c61\$lut for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00000100 for cells of type $lut. Using template $paramod$b2913e9683726f3187a419e0b1c626cded1fc425\$lut for cells of type $lut. Using template $paramod$873c285bdccf0ac2b60d2304ea5cd14bf211d2a6\$lut for cells of type $lut. Using template $paramod$7430138260a25fb02d8664cc688bf9ca4ad41654\$lut for cells of type $lut. Using template $paramod$8ab39d0eb686d10e560e5681855732ba7666ff9f\$lut for cells of type $lut. Using template $paramod$2fd3c42461376c704c07117e7368b2ed8179d1e0\$lut for cells of type $lut. Using template $paramod$f8f63b209b7230e81958663ff24fef1613156af7\$lut for cells of type $lut. Using template $paramod$bf2862f5807fb17bf4143e7c2726d92eab763062\$lut for cells of type $lut. Using template $paramod$66caeb00a39d236782a97659e3bd99621b74681b\$lut for cells of type $lut. Using template $paramod$f3ada871809f362efd8eb0c4fb952bb5c98f0750\$lut for cells of type $lut. Using template $paramod$373d637619c29cb9150902df9528107e5f3b8288\$lut for cells of type $lut. Using template $paramod$bba54c1ef87367812b4c15f4aed5ac70773df775\$lut for cells of type $lut. Using template $paramod$d21d214a5aa271f2d9da3f90f22432c0ecee130f\$lut for cells of type $lut. Using template $paramod$00ffcc628ccb870304683cac36ad3a16cc41b6a4\$lut for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00001000 for cells of type $lut. Using template $paramod$71ee25e9c5d051763351c9d480fc189154f82403\$lut for cells of type $lut. Using template $paramod$edb78bf6097bd1610bf429917d83de43c0242af1\$lut for cells of type $lut. Using template $paramod$fe4e24b614c63965c11dc88a1deafdb9e255213c\$lut for cells of type $lut. Using template $paramod$47a8214374025465e226fa66bee690ff33268a25\$lut for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'01111111 for cells of type $lut. Using template $paramod$43779580bfffd5d5a9f321249a174febf1dac288\$lut for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'10010000 for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000010\LUT=4'0110 for cells of type $lut. Using template $paramod$183ec76ed3429a430a8be24b57f3de734985f568\$lut for cells of type $lut. Using template $paramod$f67ad926234c6216d005ae991aa4cfdf5a71356a\$lut for cells of type $lut. Using template $paramod$992bdc10cff2c6edd722994f0e1044bc863f79f7\$lut for cells of type $lut. Using template $paramod$2382b0dd4cb27fd4312681c40a6dd179c2a7a26a\$lut for cells of type $lut. Using template $paramod$b86b68a00733dbecb31d58a14a13683475a2002a\$lut for cells of type $lut. Using template $paramod$658b9ed803f0d3d335616d3858b53e0a2522f1e8\$lut for cells of type $lut. Using template $paramod$2d73cf21e7a3b53006ebbae47ecc48e73975ec46\$lut for cells of type $lut. Using template $paramod$b26fbfdb68e98cf016d61a8611b449e9f4a30f3c\$lut for cells of type $lut. Using template $paramod$7e5b59d9e4c49b05c353ba4669bf91c851786e5a\$lut for cells of type $lut. Using template $paramod$6d6beead1425af15cf78b27fd9b11b41b5d4bce8\$lut for cells of type $lut. Using template $paramod$ab1de5a7f09e42bfe6a9a80dcc91115410a0d587\$lut for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'10001010 for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000010\LUT=4'0010 for cells of type $lut. Using template $paramod$edc5a73130589b9210f4bdf92e14bdcacac8945d\$lut for cells of type $lut. Using template $paramod$a47d3f6fd9a7aebdb1b556bc977da3380a17c8cf\$lut for cells of type $lut. Using template $paramod$8512f4fb47fa9596f76cdbe5b407a5b54df368e7\$lut for cells of type $lut. Using template $paramod$6e238df02989b317f10820a22773676e71120644\$lut for cells of type $lut. Using template $paramod$2de23df76a24087ecc0fa38a78ecc970cd3f2492\$lut for cells of type $lut. Using template $paramod$c66e7b215e6f80c1915bda1df6f2ae95d0bda68c\$lut for cells of type $lut. Using template $paramod$59f2a3e232df3029c8bc36978b9bbe72a71dfb5a\$lut for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'10001111 for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'11001000 for cells of type $lut. Using template $paramod$52fa1b2073b9054923f466bbb768e0ea7c69c9e3\$lut for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'11100100 for cells of type $lut. Using template $paramod$7d524289d287145619e261b5a02c931069c09e68\$lut for cells of type $lut. Using template $paramod$461cadc1bd5a9a618782c453f75bb6c15ef2c050\$lut for cells of type $lut. Using template $paramod$7ebd053006fefd5a4368bea803813a6c7860a94a\$lut for cells of type $lut. Using template $paramod$6347b1596def8e28985acde3ca00e2448849834c\$lut for cells of type $lut. Using template $paramod$5d5e0bd0963869548336b3a46c3170a573078c4b\$lut for cells of type $lut. Using template $paramod$4ae63e93be88a51e5d89e732c050007fea9fe3ee\$lut for cells of type $lut. Using template $paramod$37f8a8ddd7f446705c5726dd55f78cb60a145a30\$lut for cells of type $lut. Using template $paramod$bffbc92952163360ab46e89e211c634ca2e2cfb5\$lut for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00101010 for cells of type $lut. Using template $paramod$ca357517489332a2cf261ee222c33ad12293e4d5\$lut for cells of type $lut. Using template $paramod$2e9afba29670cc6475874639e7c1b3979c8ebde3\$lut for cells of type $lut. Using template $paramod$adce9c89515a4e83641fc3471eb3c01ec7b082ff\$lut for cells of type $lut. Using template $paramod$30305e55a780880b9c824fe3509a4d981acb0f2b\$lut for cells of type $lut. Using template $paramod$b45308ffeb4031bc5d55ef31b149afd94d3d7565\$lut for cells of type $lut. Using template $paramod$c28a8b7ce0535d090c4cfb52e9c74affd52b110c\$lut for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'11111000 for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00010101 for cells of type $lut. Using template $paramod$179512a187da069f3b79ef6612a41e494e7d54b6\$lut for cells of type $lut. Using template $paramod$e9c77024ca501b890c641f9c0b10e27242db8730\$lut for cells of type $lut. Using template $paramod$47671b68495b53d6eea5a9dd67c114907e17980b\$lut for cells of type $lut. Using template $paramod$2d33a07e648a461a4260bca4d1f8a799349ef6c4\$lut for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000010\LUT=4'1011 for cells of type $lut. Using template $paramod$2c01c78b93f77b5e79eae85526677e695be05a34\$lut for cells of type $lut. Using template $paramod$ba7c22fadfbf9ee7abcb895a21403114111dd201\$lut for cells of type $lut. Using template $paramod$05a6d306cd725e69f51b1165d55b035df9d5a665\$lut for cells of type $lut. Using template $paramod$fcff9a7b1687e357a40264efcefe8443c8b2971a\$lut for cells of type $lut. Using template $paramod$493190373199e5a39be045ba23abb29ecef89037\$lut for cells of type $lut. Using template $paramod$9c10e17a0a1ecd0e2664d222f0eb0cb2cf52c224\$lut for cells of type $lut. Using template $paramod$ab8bb87959c5d7cfa27886cee1355b38e054a61a\$lut for cells of type $lut. Using template $paramod$4acaad3481bccc123482c4010bb095c9612e3455\$lut for cells of type $lut. Using template $paramod$84074f327553574ae98fe7096b1c4ba82310ffce\$lut for cells of type $lut. Using template $paramod$ba7f31f246a278c41fa0648a6e0512f63185dec0\$lut for cells of type $lut. Using template $paramod$e2d96f36ef28053ecd27167cd95b944485ac3146\$lut for cells of type $lut. Using template $paramod$4b9b235bc4444ff899bef0c648e4109b26737f1a\$lut for cells of type $lut. Using template $paramod$18368a3da11a7221c7fb674ec80ee0d0bd64b883\$lut for cells of type $lut. Using template $paramod$1bb2fc47b457abe7e28b98cfa3441b6432237f90\$lut for cells of type $lut. Using template $paramod$577f6b33df787137f4b90a9e4e5b34ba8a5accc0\$lut for cells of type $lut. Using template $paramod$6565e92242a21f5338d449de809baa175c228bcf\$lut for cells of type $lut. Using template $paramod$480d3b9fc7c6a57575657fd8f0dc2a86c4cc650e\$lut for cells of type $lut. Using template $paramod$2ed945693823e972236d8ef3dfa1036e6ba89bd3\$lut for cells of type $lut. Using template $paramod$ce23c8cef76b1a8b8b143bfa07ff3a4e4564b99e\$lut for cells of type $lut. Using template $paramod$50ae037bea16070af222263fc6c06efd57346ae1\$lut for cells of type $lut. Using template $paramod$130a3185152cd3779d37df1e15e0ffb941c3d3d4\$lut for cells of type $lut. Using template $paramod$ee3aee51512c440156b3fdfdf887fb8c17d950f3\$lut for cells of type $lut. Using template $paramod$e49f6e3576ef1a6d2f58c54414dbb786af8cc869\$lut for cells of type $lut. Using template $paramod$d79e8c7f0cb3bd049a34d82ec5fe688d444e5a52\$lut for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00110001 for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'11101111 for cells of type $lut. Using template $paramod$e5f53fb2cb3e702c9422ebddd3ba952e5a8f3401\$lut for cells of type $lut. Using template $paramod$f3e1547c4b47e64c590e75cf09078b2507c8cc75\$lut for cells of type $lut. Using template $paramod$6d05ee5be4fbc817e6482b590e1831ddde15ffbe\$lut for cells of type $lut. Using template $paramod$018d71a0fe325d6362687fe53ac13dd6340e400d\$lut for cells of type $lut. Using template $paramod$a5516fc31d1e552de2435200bb732b4d4ad63a9c\$lut for cells of type $lut. Using template $paramod$df6b12cebabc3b2db650658c5e894d03a346e968\$lut for cells of type $lut. Using template $paramod$26c5052c049ac46222fd07f33e963742075bb127\$lut for cells of type $lut. Using template $paramod$a50be0e6fa3a01511bb234559cb74fb8bd3e2061\$lut for cells of type $lut. Using template $paramod$f9813472aa48e533b3838c6f2316dc2e78c66111\$lut for cells of type $lut. Using template $paramod$6410b45ea4d1e53d7fd209ee0400ef5c9579c44a\$lut for cells of type $lut. Using template $paramod$fea512844f0598125018304dfe86621dbf348f27\$lut for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'11011000 for cells of type $lut. Using template $paramod$9c9c977d4ef412c658600f27af104e72c77928d0\$lut for cells of type $lut. Using template $paramod$a1d323730045824cfc84bb9f4ee8031f1c4dcc9e\$lut for cells of type $lut. Using template $paramod$e3f15dbf386eb2d9773236c73b6cf924ec3294ee\$lut for cells of type $lut. Using template $paramod$44f923c95904319d3fa8619cf7a7ad4dbd1476e0\$lut for cells of type $lut. Using template $paramod$2ea69c779d6c1b79ac5a87b0d1523c67d5628dba\$lut for cells of type $lut. Using template $paramod$7e3d8ac009723e554811ad53385162c0e6a41625\$lut for cells of type $lut. Using template $paramod$31114d87be01f977936de4d238d2be8c5bca7194\$lut for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'01110010 for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'01110000 for cells of type $lut. Using template $paramod$88432289404ea1d6f28ada98a0152b55d4b42efe\$lut for cells of type $lut. Using template $paramod$3e0fd3bac2aece0cf96be02dd2105fbe9185b314\$lut for cells of type $lut. Using template $paramod$e54349d9a634ecff5f53629ed023a0262d334efb\$lut for cells of type $lut. Using template $paramod$f13784ede300b12a5285177c86c7721a54cf9e12\$lut for cells of type $lut. Using template $paramod$a56a39c0f6a5a7dc6beed165205ecc9aaf916f10\$lut for cells of type $lut. Using template $paramod$1ad9ca75a5e52e69f39f16c0b8ffb14773a0b7f2\$lut for cells of type $lut. Using template $paramod$fb4ed309581bcd972f41afa8566ae8b9812c7f6c\$lut for cells of type $lut. Using template $paramod$608f40069c27841a5b3bdf03643a34bdc8974072\$lut for cells of type $lut. Using template $paramod$332a399730bfc61adea04021a76b1c4e4030f37d\$lut for cells of type $lut. Using template $paramod$a5f392bb8a4b3a736c78cc8085fdeee1fa388e5c\$lut for cells of type $lut. Using template $paramod$0c822c65361ce832091b6c90f1a02f1ee0b109d4\$lut for cells of type $lut. Using template $paramod$e4b832d686d12318ec0715f027fe549b42e45c20\$lut for cells of type $lut. Using template $paramod$58df2c605746858c7e53492c8f57d6f1fafa12d2\$lut for cells of type $lut. Using template $paramod$3702268f692b8bf258e428f65d3bca4e1f76d98b\$lut for cells of type $lut. Using template $paramod$a7c07944e10969b2e1fd563a5b72f89493cb3705\$lut for cells of type $lut. Using template $paramod$ffd746130b626320ae0d6157c1d3d2b36752fa5c\$lut for cells of type $lut. Using template $paramod$f0e4a8b607f0a018301991aec7b151de2101f82c\$lut for cells of type $lut. Using template $paramod$ea1c7a640e19b50231e724f683fc40d7a70f36df\$lut for cells of type $lut. Using template $paramod$e718d2f5eb562e6029d6a1b1e060511bf1c65df1\$lut for cells of type $lut. Using template $paramod$8e44661def013b6bf9fe6f8b049ef2c838d749f9\$lut for cells of type $lut. Using template $paramod$00b8dd8b73561ad6988b03b6600fc178778f4822\$lut for cells of type $lut. Using template $paramod$16894c241be5ea1f024e9339dea788b4dbe184ae\$lut for cells of type $lut. Using template $paramod$9516a274323d8927a7042e9106d81753d1675fd7\$lut for cells of type $lut. Using template $paramod$35059585e93e18989247e13034fd6a1ce4de9957\$lut for cells of type $lut. Using template $paramod$0f19b1c588a47c675d00132b243b5e3308ffab5d\$lut for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'11111101 for cells of type $lut. Using template $paramod$d274aed6095c8069213223b6b642a3cff2bd8d89\$lut for cells of type $lut. Using template $paramod$c441dbd41fa7b52ce609b1fb3e8a706905598601\$lut for cells of type $lut. Using template $paramod$94d86303a5ab6c2be14b18d403d3db684b8d85d1\$lut for cells of type $lut. Using template $paramod$98f8d17b25262d98d340140a4a5e512d234da40f\$lut for cells of type $lut. Using template $paramod$d7ec878ecfa8f5f7604d3e91692b5d4c2ee758ad\$lut for cells of type $lut. Using template $paramod$a3bf66c9d49bf8d7c40e202c31aa83841dbcb53e\$lut for cells of type $lut. Using template $paramod$1f6f4e0c38a68ed22c0391bff11c5390c4beec3c\$lut for cells of type $lut. Using template $paramod$7177cb04e5f0ca35855ed40fa4f4e694738e0924\$lut for cells of type $lut. Using template $paramod$1b4942fad7257f60532954b1eb94a6b84f2e5ae3\$lut for cells of type $lut. Using template $paramod$0189d933eed523b159b35d60915e80e53d803bc2\$lut for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'11111011 for cells of type $lut. Using template $paramod$eba7de026ff587370e320127e266317dae097a89\$lut for cells of type $lut. Using template $paramod$821c2723d6171961a34ac5358ff9ec58dbfb33a8\$lut for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'01100000 for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00010011 for cells of type $lut. Using template $paramod$95db1638ec01590b0c70fc881c26eb8d8eaacebd\$lut for cells of type $lut. Using template $paramod$7aa2b65f296524af153560f1ab443e408a2f2091\$lut for cells of type $lut. Using template $paramod$7c4d75174efaf359652c2f537ab21379e907cb8f\$lut for cells of type $lut. Using template $paramod$9ae0f136c9ed34a2deb323e9b2a3a520eea61514\$lut for cells of type $lut. Using template $paramod$085cb83d0db09780ae5aa544a0f286ba9445143f\$lut for cells of type $lut. Using template $paramod$c0875cf41eda4c3d973943d936a3cafee6b9777d\$lut for cells of type $lut. Using template $paramod$f01b27bd3e9f17a779c010dc32b31e32e1d5ecd6\$lut for cells of type $lut. Using template $paramod$f503ae6dd13af4ce255f26a38c5b2bb42d3444fc\$lut for cells of type $lut. Using template $paramod$16773ebb5e5d8dbce266b8a86bb4af4574d61ffd\$lut for cells of type $lut. Using template $paramod$c512da69297918ea54dabf0dafee8b993f0ecd9c\$lut for cells of type $lut. Using template $paramod$07f0a11b15449060aba598a3eced1a16a0f5388f\$lut for cells of type $lut. Using template $paramod$df29fe9e6d6d694a9cc5697e4251bf7d8cd4d8e4\$lut for cells of type $lut. Using template $paramod$b587e1dcd8f8a9800d395e4aeecac52c55d6f585\$lut for cells of type $lut. Using template $paramod$1bf3509a544426de1daa8b6919ee1df60c7165ec\$lut for cells of type $lut. Using template $paramod$849d013d096d73269ca4beb768f8e399745d37f2\$lut for cells of type $lut. Using template $paramod$4ee5adfce5f62948e68f4a01d5847395ac5f6bb3\$lut for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'01001100 for cells of type $lut. Using template $paramod$bc051162dfb23caab98d73c4ec086fe9a67895f2\$lut for cells of type $lut. Using template $paramod$97f21fc6caedb01e3e413e66042b2fa0473d00e4\$lut for cells of type $lut. Using template $paramod$5ad5dab2319eaa393748d74a6ae3cf6d24e40054\$lut for cells of type $lut. Using template $paramod$3a42a4bd8b3ff0028c2ad59f0d85d4c018ea6008\$lut for cells of type $lut. Using template $paramod$de81bb4f24bddd9c01fb4a8d2c0db4e04ac2517e\$lut for cells of type $lut. Using template $paramod$3ec5e45cb3e54de9dbe908707155b5f9917c9370\$lut for cells of type $lut. Using template $paramod$b7602004c975f656d62335e2c16a2b981cd67332\$lut for cells of type $lut. Using template $paramod$f5cf7d48a1d000717a8f14a770131cc7d416cfe6\$lut for cells of type $lut. Using template $paramod$525425bfbe66d72ee88210d059d9a74f55ab8de8\$lut for cells of type $lut. Using template $paramod$ce15874c299a587dd16825ec2d2d2759b547554e\$lut for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000001\LUT=2'01 for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'11011111 for cells of type $lut. Using template $paramod$32ccf65669c41e1e3bce1f16051f6d60ad96a2a0\$lut for cells of type $lut. Using template $paramod$65d5d5c1e01bf41ee659754efba932f3d99198e5\$lut for cells of type $lut. Using template $paramod$8829675bb8c52553aed9f101ec0d5ef0c865e5c7\$lut for cells of type $lut. Using template $paramod$4cf5305612d86489c1a6171729557670bf08582e\$lut for cells of type $lut. Using template $paramod$e3e4230bb990723642112b292aa705ee0cbad0d4\$lut for cells of type $lut. Using template $paramod$f258f431a7c2fc52205873e71cd6683fdc689824\$lut for cells of type $lut. Using template $paramod$d6ca727e39f31d51d29072e0f33aa09c65e37336\$lut for cells of type $lut. Using template $paramod$f45429e380905f064bb0bad3a8bdb941708e63a7\$lut for cells of type $lut. Using template $paramod$18fa685a8cdb30eb6c664aa12d728a07c3fe94f1\$lut for cells of type $lut. Using template $paramod$504c9f1ca6facbed70a8a05210386b24177f23fe\$lut for cells of type $lut. Using template $paramod$c6a1f9ea79b7bb1672d5d3c63312684d0f3defb6\$lut for cells of type $lut. Using template $paramod$3977c724a41263594792e11f1b6eae2f6b247db9\$lut for cells of type $lut. Using template $paramod$f056b3cf42701dfc7f540d463578d46c622fe830\$lut for cells of type $lut. Using template $paramod$38e6aa9546c40949f8135bb018f0d5ef863085b9\$lut for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00000110 for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'10101101 for cells of type $lut. Using template $paramod$5e9374f44a27c3f8a1c38af244ec43ceb4fb8d4f\$lut for cells of type $lut. Using template $paramod$46d981b5eabc08c1691f743d7a017e4435316de4\$lut for cells of type $lut. Using template $paramod$25f748a39f13f638a0dd44b265e145242e43bbc5\$lut for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'11010000 for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00111010 for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000010\LUT=4'1101 for cells of type $lut. Using template $paramod$db08fd84fb3c4d6a41eaec6adfffe445fb7eb17f\$lut for cells of type $lut. Using template $paramod$3b56205e0e57b3ea26d80fc7983017f83663129e\$lut for cells of type $lut. Using template $paramod$2ec6422db00d358fc7469efce6208bffbc8521cd\$lut for cells of type $lut. Using template $paramod$82b4a585d1edcb5c6e755dc9bd3392228a1c1304\$lut for cells of type $lut. Using template $paramod$b4f85a6321a00b090afc4e21d68e7b99eb94d149\$lut for cells of type $lut. Using template $paramod$a9ebd93bc2fc1a9f7fc387533c3e17044ba51058\$lut for cells of type $lut. Using template $paramod$6023c671e114c4eb0467aa8a0b08e183f33ec2fd\$lut for cells of type $lut. Using template $paramod$c6a0421f5b5114b68e9782f0585d571421cf8f01\$lut for cells of type $lut. Using template $paramod$c1a19a87ccbbb03d43a72335db63f692ddf82cc1\$lut for cells of type $lut. Using template $paramod$6f9324703e8fcc3b6df2bc2bec54ec19a446ae96\$lut for cells of type $lut. Using template $paramod$fca001e3e0b52158a872e76e56c01ec10dfbb1de\$lut for cells of type $lut. Using template $paramod$58bd588a49a6a3b9d057d75f907cb4932e1635f6\$lut for cells of type $lut. Using template $paramod$de613b721f82db25f1a023f01c83756ee63d96c4\$lut for cells of type $lut. Using template $paramod$7ca4db46d3cd57dbe2541a389808e6d33af02319\$lut for cells of type $lut. Using template $paramod$ffc2ea81a65101fbef8a332deddf112494d27163\$lut for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'11010001 for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00001101 for cells of type $lut. Using template $paramod$df929792afd0bebf101a124ee890c12e0fed6a8d\$lut for cells of type $lut. Using template $paramod$784f4711405f84982df518be1f8d295ab4d5b427\$lut for cells of type $lut. Using template $paramod$b2eb142b2552937d0c3a0d29a84bb4ba8786e70a\$lut for cells of type $lut. Using template $paramod$cad45b6c9da81941161a13849773fe2ed4bc1c6f\$lut for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00010100 for cells of type $lut. Using template $paramod$23764ef6208c0eba4ffe4afe904943e1ed80e8a4\$lut for cells of type $lut. Using template $paramod$891d17c049ef97ffbed57a5d4edf3f9e83d4f776\$lut for cells of type $lut. Using template $paramod$1c8aea8d15a8caa53bcd106d813c48ea86657836\$lut for cells of type $lut. Using template $paramod$b2192df6f90569fea4015d0a6658bdc192199f95\$lut for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00110101 for cells of type $lut. Using template $paramod$4d1023d1af44531a5a562646dc62ec62ed405ea6\$lut for cells of type $lut. Using template $paramod$766f851776a2d25e13728c9147ddfe7ff70917a3\$lut for cells of type $lut. Using template $paramod$23b135911b7c14b5b19b5329e5903bcf58b44188\$lut for cells of type $lut. Using template $paramod$a03ef989f8f4e1878ce2f5c4e0e3d2dfb54307ef\$lut for cells of type $lut. Using template $paramod$2558c329bb5b4a00f8ccab4e2e8b51b456f1d8b1\$lut for cells of type $lut. Using template $paramod$af01034afe1bdbc87587d263805971d96e724ed7\$lut for cells of type $lut. Using template $paramod$38f9bf4dd2329347b8471f0a98443dd323386889\$lut for cells of type $lut. Using template $paramod$e4ce17fcded6e264148ce0a4c0df3ed1b1b269a4\$lut for cells of type $lut. Using template $paramod$e53493f89400484e4e19015869a8a6f7d3804aa9\$lut for cells of type $lut. Using template $paramod$f2d22947d144afc97fbfe77dd7b67614b454e6ce\$lut for cells of type $lut. Using template $paramod$df23d368a6ae8908771963811f5ab56f622887ca\$lut for cells of type $lut. Using template $paramod$703a13a751e631ef123f38f7d2125aeabec0f94c\$lut for cells of type $lut. Using template $paramod$694c95659b447cef99dd4cdbd49b87dfd5f6c806\$lut for cells of type $lut. Using template $paramod$70b88e4d7bf20d2cae3de43da5e64d2e3a146ee9\$lut for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'10110000 for cells of type $lut. Using template $paramod$e7fa813675354f20c694ab2d4d9ecca5b21f170c\$lut for cells of type $lut. Using template $paramod$39b0d201a18bed5573a88835da3f39d40814d360\$lut for cells of type $lut. Using template $paramod$ddace04fba544e6adc4cdda6a50048ddd7c111af\$lut for cells of type $lut. Using template $paramod$a4bbe892a28ec0471eac4c548ab7ee6abbaf1e36\$lut for cells of type $lut. Using template $paramod$ae1d2871f7118f16e202b697c2220d9e12489e0e\$lut for cells of type $lut. Using template $paramod$4cab3b31c601551ff65536bf4f533afa0b2094ee\$lut for cells of type $lut. Using template $paramod$beae4210b922fc9ba2fcc4008a7474b475e38c50\$lut for cells of type $lut. Using template $paramod$097592bb16245531f0716c5ddb18d7090f9c7d9d\$lut for cells of type $lut. Using template $paramod$3d7168c8134c4765b84a7b86d5ef7e1e65bbf4a0\$lut for cells of type $lut. Using template $paramod$aa117dc02d4f218ed5974b258634c3f38264f15f\$lut for cells of type $lut. Using template $paramod$b2e8d279775d333b39e310bd45fd5952acdde290\$lut for cells of type $lut. Using template $paramod$620586420e818d3afa7e5b51fcf19f5c6ea83ad4\$lut for cells of type $lut. Using template $paramod$037be5c00d8a02858cdb1ab049b58a0133287ff1\$lut for cells of type $lut. Using template $paramod$c2dc8bc4808cd817aa875891b1f3a4dbb8b3c4df\$lut for cells of type $lut. Using template $paramod$71d09d8354f5555fb54ab0bd4f3934a22c793990\$lut for cells of type $lut. Using template $paramod$7f02e251e6e3f7d90360106b4e7bd276dd787a00\$lut for cells of type $lut. Using template $paramod$e4857636d35dc9b5293045a985a317a436a4713f\$lut for cells of type $lut. Using template $paramod$dbdbcb07b9994e498bb1324e5c006c6aa08a7a37\$lut for cells of type $lut. Using template $paramod$b75298744511fa5d41f7b5b681c67bfa1a170053\$lut for cells of type $lut. Using template $paramod$5554e380df5c057ae2483e7b94355e12dd02ad01\$lut for cells of type $lut. Using template $paramod$a0bda095e70ce4bdcf06ba266b1252343fbd8f35\$lut for cells of type $lut. Using template $paramod$9de80d92e8cc66d364ef31ee1a69cde5cb2d00d8\$lut for cells of type $lut. Using template $paramod$11c86b7a6cb6e98dcfb16c5f4d4cc1052b93d8a4\$lut for cells of type $lut. Using template $paramod$865395c0228487a64a8e4011cecafc2c64b79f2b\$lut for cells of type $lut. Using template $paramod$3fcc15be9395ee36f8f007f92fb63b21596e309e\$lut for cells of type $lut. Using template $paramod$6b0849254d6c87461fb93e37cc18f089f61eb912\$lut for cells of type $lut. Using template $paramod$b772929e028aced8081b5fc62b4a4f9cace04851\$lut for cells of type $lut. Using template $paramod$e5758a88c2c156ccb3037f71a73d1b15af5b310d\$lut for cells of type $lut. Using template $paramod$5b72438ff391ef6fcf2c5d407744382a084031d9\$lut for cells of type $lut. Using template $paramod$82a00bf0f959a345aaec45c197de61b70ee9c703\$lut for cells of type $lut. Using template $paramod$e953ca6166af75b2444378071091ce589a6edd9e\$lut for cells of type $lut. Using template $paramod$7491e7206ae8c682d288373efe06a43b67c277cf\$lut for cells of type $lut. Using template $paramod$be48d952fcad8a16b8d84daa4c48a3065f343e5e\$lut for cells of type $lut. Using template $paramod$153c6cdaaddbc43e6ef3facd06aa851de33910ae\$lut for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'01010011 for cells of type $lut. Using template $paramod$c75656bc8af73b1fd37fc2f9580b970bd545f476\$lut for cells of type $lut. Using template $paramod$9e394303e290a474880b56f98766417009256d93\$lut for cells of type $lut. Using template $paramod$6423d726e9a2aeb860255b5262559102a32c1449\$lut for cells of type $lut. Using template $paramod$b95d9aa72ea56ab7b64eabaffd3933ca5c971a4c\$lut for cells of type $lut. Using template $paramod$92c3899764cd8074859d6a5a5b733cffe8a391b3\$lut for cells of type $lut. Using template $paramod$654554314bca97d0c4483dbdc449dda438513ff9\$lut for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'10100011 for cells of type $lut. Using template $paramod$9872883a8c5f0510f215d86938cdd9bc8fa3827b\$lut for cells of type $lut. Using template $paramod$202ef33ed7c16f8af46b2c0a3a76b0741a206df4\$lut for cells of type $lut. Using template $paramod$c8f16510db975553c8b0be1064e8f5234175f8a8\$lut for cells of type $lut. Using template $paramod$a9a0d3da8e2570975000fd954dff796c3807df01\$lut for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'01010100 for cells of type $lut. Using template $paramod$546622899c43ef727e5b1153c016f6c8b490c781\$lut for cells of type $lut. Using template $paramod$4b5a0913bb4ec49700ee884f72bc03d6f3d26566\$lut for cells of type $lut. Using template $paramod$9056e7b0531dc612f301bbf00cbd06bdf9adc361\$lut for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'10111000 for cells of type $lut. Using template $paramod$47c21ed260206bae3c8f3c62dd9f416abc06ccf4\$lut for cells of type $lut. Using template $paramod$20235ca863361fbc253329cfc7eeea38c77404dc\$lut for cells of type $lut. Using template $paramod$11ec7271d8e6e5aeaace08c13e4c601f10e31038\$lut for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00001011 for cells of type $lut. Using template $paramod$81d8a60fd95b1a9f9ef71c12a774ae6988cb9fd5\$lut for cells of type $lut. Using template $paramod$c8beb9642fea9a48a01b5f47c1dc72185ba41d39\$lut for cells of type $lut. Using template $paramod$7667ee60653b518109ce38341e4a8566a12b1d87\$lut for cells of type $lut. Using template $paramod$6665b39ceac26e0ab2d4c34094b2005de33923b9\$lut for cells of type $lut. Using template $paramod$32abbd1d449a67fb913b4733374e345d4c17175b\$lut for cells of type $lut. Using template $paramod$e134ec2a47a2462a591072e65d34fb15b81c90e0\$lut for cells of type $lut. Using template $paramod$9b8ad6ec287ad078c7ff8f3a8ca4083f5a7cb8c9\$lut for cells of type $lut. Using template $paramod$0d32e36bab4cd3e24dbcc94204821aa7f75d106e\$lut for cells of type $lut. Using template $paramod$fe0ec6cf52a74b8e9115c7ff11adb77b1122b4e4\$lut for cells of type $lut. Using template $paramod$4440f25cf172665494cf9c9e87096623181eba7a\$lut for cells of type $lut. Using template $paramod$7fed74f2cef975f9d09dcb0a10cb49d92a5c6372\$lut for cells of type $lut. Using template $paramod$9c669e17239e630696f5bb85b60d7269d3597208\$lut for cells of type $lut. Using template $paramod$1eca256e897d93320fc7527297d9d92267fd541e\$lut for cells of type $lut. Using template $paramod$c91ebb38937ac98aefe8c9a96539c3101997fe63\$lut for cells of type $lut. Using template $paramod$97d846bf889b6a26a7d0013957e121d1a3f99377\$lut for cells of type $lut. Using template $paramod$29de3006330e565f6d0ce6a6e13ddd1b532f7ec1\$lut for cells of type $lut. Using template $paramod$b59bda90a50b84a9eedb7db5f9d43c0b50ba664e\$lut for cells of type $lut. Using template $paramod$e144b215bcd18129bc79dba4ab66871fc4e63076\$lut for cells of type $lut. Using template $paramod$2c64fb4d062136a1f23ae6b1888a0bcad0aa5561\$lut for cells of type $lut. Using template $paramod$dba07f312012fa7fd7154ebb73c28f79f08648ee\$lut for cells of type $lut. Using template $paramod$b5e9451d9a928aade7701281c473c108b4ff8c2d\$lut for cells of type $lut. Using template $paramod$9bdc414229f06e785dc8fd97a243faa9336e164a\$lut for cells of type $lut. Using template $paramod$f8e1bdecd38a1f2a88371fc52b96bff86506a2c7\$lut for cells of type $lut. Using template $paramod$338ce46cf7ff44b9974887dd2adee6c4e0530bed\$lut for cells of type $lut. Using template $paramod$fdcae86fcfd036c1880a04306ae771a9d7579c31\$lut for cells of type $lut. Using template $paramod$09aa8a3143d50cc59564172c2564d6271fb3a300\$lut for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00100011 for cells of type $lut. Using template $paramod$6dc05f9f044ab30f5362b0c302f3cf6295cf2d76\$lut for cells of type $lut. Using template $paramod$ddc6f4fe74ed36832c5cee6594285c38523f3d9c\$lut for cells of type $lut. Using template $paramod$d68c955eab3e0ff857c6b60afe14ca397531beeb\$lut for cells of type $lut. Using template $paramod$faf4b69e2195a9ce52b7c3bce83fa5ea343bc378\$lut for cells of type $lut. Using template $paramod$0397a04659c00318ae76496d241f1d2991537883\$lut for cells of type $lut. Using template $paramod$1076d5b96410dc32bbe68df15017559464728316\$lut for cells of type $lut. Using template $paramod$1c30d08c403f38fa94ec53dfc832770bdc564fe4\$lut for cells of type $lut. Using template $paramod$46337428ce420685467716f9921402709a730c9d\$lut for cells of type $lut. Using template $paramod$5afe21d6fdc7c33aeb338fdb508ea02813207bfd\$lut for cells of type $lut. Using template $paramod$5c6d01824df27a97c3776b3694e8814e23c197cd\$lut for cells of type $lut. Using template $paramod$0394f583dea6d1252f939055c8622881e27fc104\$lut for cells of type $lut. Using template $paramod$ad2f7ea4e482304c44e7a6f6dae5db1a4029e245\$lut for cells of type $lut. Using template $paramod$b9305c669fd883d24574655b402c7ff9f28efb1a\$lut for cells of type $lut. Using template $paramod$55ac124d6496496a64c6f2c29f5ac412a62ef57d\$lut for cells of type $lut. Using template $paramod$95884ef07789cca69cca4bd11ba6c919d1a2b875\$lut for cells of type $lut. Using template $paramod$718179c4766b4ea66e8ece9b944be5b997b67ba5\$lut for cells of type $lut. Using template $paramod$71780946553cf4f012cf430f27c1f53f2aea690e\$lut for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'10001100 for cells of type $lut. Using template $paramod$6f149f4a0a4acdd39ef1c1fa3a4f5a4dfd75ed22\$lut for cells of type $lut. Using template $paramod$78f5590b0462181d8749c9e6ed8a771b22dfb9ed\$lut for cells of type $lut. Using template $paramod$903b13a78e0201d81ee2cb5e579e213337de2eac\$lut for cells of type $lut. Using template $paramod$29fb0dcbea7e19908c494ce4a8a756b15e2a78b6\$lut for cells of type $lut. Using template $paramod$4f950c530ab9181383456419d23923915ecc86c2\$lut for cells of type $lut. Using template $paramod$cdc5bba2585477f1744fd1f869bebc8beb23d707\$lut for cells of type $lut. Using template $paramod$8075729953f49b6cb1b4d863b2fb20da9818d304\$lut for cells of type $lut. Using template $paramod$d847bc8c174b980d6653586bcecf54c2f96da5e6\$lut for cells of type $lut. Using template $paramod$67843137d902c04a2fc07fd23375e29aa1ebf7e2\$lut for cells of type $lut. Using template $paramod$2357431a20f3891da5d1d21801bc815b057e2dac\$lut for cells of type $lut. Using template $paramod$7e3de18263fb7d0a2e12a4401120994e66bde6a4\$lut for cells of type $lut. Using template $paramod$b1680225cc6a5792caa95f54b8b3218fae21705d\$lut for cells of type $lut. Using template $paramod$2bf892cb2b52095d41d96cd0cddc511c2796a989\$lut for cells of type $lut. Using template $paramod$edfe6773e2ae95f1f17ad5bea62c0e1b079fa667\$lut for cells of type $lut. Using template $paramod$f921ab2c451d17e196d1dcad0b6d434881387fe3\$lut for cells of type $lut. Using template $paramod$fa9eb26fcf7e57b4dc534d2b1f531381b1fc4e16\$lut for cells of type $lut. Using template $paramod$5a621b016c894274d07edef48c49b401a15fd796\$lut for cells of type $lut. Using template $paramod$20f3f4b8e32f8a8b038b0056872dc94926194798\$lut for cells of type $lut. Using template $paramod$3ec53e812e56e3a6694e2062d36c6d66c39c4f54\$lut for cells of type $lut. Using template $paramod$ac13e0f6643fb784ba2e8a0549a3c9d0434040e6\$lut for cells of type $lut. Using template $paramod$e942ff15257dd44eb70ae034d1b665e0116c7a3e\$lut for cells of type $lut. Using template $paramod$33b72718c79847c9c03c134c7bec663dbf06983b\$lut for cells of type $lut. Using template $paramod$82abb8f9ddaac453e6ee24bf456879be259b8e87\$lut for cells of type $lut. Using template $paramod$18ac3ef27a3b9646cd1a73a01cd2bd222a2d6e6d\$lut for cells of type $lut. Using template $paramod$94ac66a11090dca84889e55fcf03297912a5b7ec\$lut for cells of type $lut. Using template $paramod$01e96e53d77f79e0721c00741bd5ab06a9e25a93\$lut for cells of type $lut. Using template $paramod$83d27c0aeb0d7c03426161d4ec282322472c86db\$lut for cells of type $lut. Using template $paramod$d933b90fa6fc7bead0929ff16b1488228c26e3d1\$lut for cells of type $lut. Using template $paramod$f6b32330001ae69764af59ec620190bee9e5aae0\$lut for cells of type $lut. Using template $paramod$a743caf801766df40bcc22d49baa12a0bdc2f7fe\$lut for cells of type $lut. Using template $paramod$a7e5ecd791f4c92e8b2c2d34c1f8f9b0f6d98094\$lut for cells of type $lut. Using template $paramod$e197e162644f13ba3d6def1b385f7543969ee569\$lut for cells of type $lut. Using template $paramod$e12a086e609df86330988f9a8b38355fee01b0b4\$lut for cells of type $lut. Using template $paramod$c617a1d231b6fbd82a1d1bf5f8f8a97fa60dc3e7\$lut for cells of type $lut. Using template $paramod$56e6d8a28a52006bb4e50e077743f0a2163235af\$lut for cells of type $lut. Using template $paramod$176a6ceafa512d807921d7dfc76320dfbbfb5fe4\$lut for cells of type $lut. Using template $paramod$434ebc212dc9e39259ca03ae763fb5da9ba38614\$lut for cells of type $lut. Using template $paramod$9972e341775f6616abf98b54625baa17399d8770\$lut for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'11100010 for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'11111110 for cells of type $lut. Using template $paramod$ab4188c7524eec831e9177bc675d62b21a3ccd8b\$lut for cells of type $lut. Using template $paramod$8fb7c2a4174bbb0f9870bcb831d0cc7f5057f41f\$lut for cells of type $lut. Using template $paramod$55c8b41162bae9ccba9478b8f5fd17695513cc6c\$lut for cells of type $lut. Using template $paramod$ee8ddb7f7e0c6c424c34227aa247189035b69c54\$lut for cells of type $lut. Using template $paramod$44236511622e197854fa4814b088d63bb24df320\$lut for cells of type $lut. Using template $paramod$17c27ffdda03355f95b2ba5edc73ca082237c935\$lut for cells of type $lut. Using template $paramod$e4723c78131b859cdb296cc7099a965ce6bf28d9\$lut for cells of type $lut. Using template $paramod$5b4b4ed558983d9f3ab4c896a7a011d129b0db9a\$lut for cells of type $lut. Using template $paramod$8cbea7472fe8ec8b0d9b301f17edad7f1c398048\$lut for cells of type $lut. Using template $paramod$52b8ea99634fe473931545fc2727f1a39cb13e7a\$lut for cells of type $lut. Using template $paramod$b4f15f202f50520dbc381cd0880ac94f830f05a8\$lut for cells of type $lut. Using template $paramod$b89c522b7f70adaee1a35d80e932f38159b6a445\$lut for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'11101100 for cells of type $lut. Using template $paramod$027b71830bd0fbfb04ad11206c5a0de76ed9d3f5\$lut for cells of type $lut. Using template $paramod$53ce561f80f32d4298a3beadc88b6c5c78293221\$lut for cells of type $lut. Using template $paramod$7295da7c5b19f528a428229f2570e0a23ad372af\$lut for cells of type $lut. Using template $paramod$8a10a67809a4c226e7b6ed397585f1b2ade29b11\$lut for cells of type $lut. Using template $paramod$50222e4d0527635d5cf211ed95d1ccfc839e99e8\$lut for cells of type $lut. Using template $paramod$47b2f5a9f58cb4be072657772748a1ab82d6819a\$lut for cells of type $lut. Using template $paramod$4d5fa0c21aaa9745a301eda7465c650b5896bed0\$lut for cells of type $lut. Using template $paramod$1e66e926164e6462a8179be1078ea3b9daa3e399\$lut for cells of type $lut. Using template $paramod$5d91ae8bf13f169f64fe2e993cae12295d19d8d3\$lut for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00101111 for cells of type $lut. Using template $paramod$5a30f63d136a49a2894b540699ec63ef23825e7a\$lut for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'11011100 for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'10111010 for cells of type $lut. Using template $paramod$0d3ac82cf5b8a192d5ff4c23e3143360366ae882\$lut for cells of type $lut. Using template $paramod$34536926332939882b8ff52380fffc08ed1f405f\$lut for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'01011100 for cells of type $lut. Using template $paramod$17c2f243a1da896c622c9087a9b7432bee6819fa\$lut for cells of type $lut. Using template $paramod$f94cf08026d21db794b98b1a8efaec5f34ff8975\$lut for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'01101010 for cells of type $lut. Using template $paramod$18e50808df562b188523e13714b96fedec6427c1\$lut for cells of type $lut. Using template $paramod$de5328836923c44c99600bcab852423201246f91\$lut for cells of type $lut. Using template $paramod$ee7954db7791f7dba0d0a60c296cfdde356f0714\$lut for cells of type $lut. Using template $paramod$cffc8d1fa08931a41971712dc3d39cc5818fb4bc\$lut for cells of type $lut. Using template $paramod$d0a46f8637b2b026d480bf9e8554ef5d086fd1d1\$lut for cells of type $lut. Using template $paramod$3c712553f2f5a448e8c696903ee0800251a0a2fe\$lut for cells of type $lut. Using template $paramod$bab0ea0d717fb03593996e2a9f716c39db2520fb\$lut for cells of type $lut. Using template $paramod$7fcc2f13195f27c397064377984d87a90c06749d\$lut for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'11001110 for cells of type $lut. Using template $paramod$619b7c9a4d44585e10b42f7fb79b16304cca97c5\$lut for cells of type $lut. Using template $paramod$6c543b558919ff57a92ac09985ad349c5934cfed\$lut for cells of type $lut. Using template $paramod$77eba90f08fef1f04e121480501078ac12ffbebb\$lut for cells of type $lut. Using template $paramod$2e37a29808ea9d028852cbc67bbcbc7bc127b77a\$lut for cells of type $lut. Using template $paramod$92313a79c645caaee997f61828723c5df8d65bfa\$lut for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'11110001 for cells of type $lut. Using template $paramod$d35161d1d7976dcc02e7c7d51172431be85143b4\$lut for cells of type $lut. Using template $paramod$d119410bab96963da0139669592048db2c09198b\$lut for cells of type $lut. Using template $paramod$eb764785a67ae0903625e17df40813438d0457e8\$lut for cells of type $lut. Using template $paramod$c79843a7a21eda73c585e76a35dd51b0a4d6fd36\$lut for cells of type $lut. Using template $paramod$1cd06b375642709be429e03b998df9f4765d3287\$lut for cells of type $lut. Using template $paramod$153c36e047f05fb8dde958e7632f5362a93d12c6\$lut for cells of type $lut. Using template $paramod$9e770da810531856009474fabf6048922c710ebb\$lut for cells of type $lut. Using template $paramod$aa79b66d99645f2c6597509fe375a3cb97da6e36\$lut for cells of type $lut. Using template $paramod$f750a4899b19cb23f7f91d895b70d40eaf6b0924\$lut for cells of type $lut. Using template $paramod$a8a7a7b14dd3575ec864cf6639362bd64a43d4ea\$lut for cells of type $lut. Using template $paramod$359fe4e746656bf9c72aecaff84fc7bdea9f55a5\$lut for cells of type $lut. Using template $paramod$cce6b847e730f5f1cfb4a8ef6c78f9f44e4f1145\$lut for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'01011101 for cells of type $lut. Using template $paramod$46e0c58da989560e0dc35528a00016369495a2aa\$lut for cells of type $lut. No more expansions possible. <suppressed ~12818 debug messages> 18.44. Executing OPT_LUT_INS pass (discard unused LUT inputs). Optimizing LUTs in processorci_top. Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$167531.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$167531.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$167519.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$167519.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$167719.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$167719.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$167724.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$167624.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 2) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$167565.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$167565.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$167774.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$167542.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$167542.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$167548.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$167548.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$167833.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$167833.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$167836.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$167836.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$167804.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$167810.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$167641.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$167641.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$167653.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$167653.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$167658.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$167658.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$167666.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$167666.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$167684.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$167684.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$167795.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$167501$lut$aiger167500$32538.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1) Optimizing lut $abc$167501$lut$aiger167500$32538.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1) Optimizing lut $abc$167501$lut$aiger167500$32538.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 1) Optimizing lut $abc$167501$lut$aiger167500$32538.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 1) Optimizing lut $abc$167501$lut$aiger167500$32538.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 1) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$167507.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$167515.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$167501$lut$aiger167500$32000.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3) Optimizing lut $abc$167501$lut$aiger167500$31995.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$167501$lut$aiger167500$31862.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 2) Optimizing lut $abc$167501$lut$aiger167500$31862.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 2) Optimizing lut $abc$167501$lut$aiger167500$31862.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 2) Optimizing lut $abc$167501$lut$aiger167500$31862.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 2) Optimizing lut $abc$167501$lut$aiger167500$31862.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 2) Optimizing lut $abc$167501$lut$flatten\Core.$procmux$2654_Y[29].genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$167523.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$167501$lut$aiger167500$31538.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$167501$lut$aiger167500$31365.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$167501$lut$aiger167500$31227.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$167501$lut$aiger167500$30916.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$167532.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$167923.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$167540.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$167501$lut$aiger167500$30336.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$167501$lut$aiger167500$30336.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3) Optimizing lut $abc$167501$lut$aiger167500$30331.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$167501$lut$aiger167500$30198.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$167547.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$167501$lut$aiger167500$29871.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1) Optimizing lut $abc$167501$lut$aiger167500$29871.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1) Optimizing lut $abc$167501$lut$aiger167500$29871.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 1) Optimizing lut $abc$167501$lut$aiger167500$29871.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 1) Optimizing lut $abc$167501$lut$aiger167500$29871.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 2) Optimizing lut $abc$167501$lut$aiger167500$29871.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 2) Optimizing lut $abc$167501$lut\Controller.data_memory_read_data[26].genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1) Optimizing lut $abc$167501$lut$aiger167500$29385.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$167501$lut$aiger167500$29312.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$167501$lut$aiger167500$29312.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$167558.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$167926.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$167501$lut$aiger167500$28781.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$167501$lut$aiger167500$28710.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2) Optimizing lut $abc$167501$lut$aiger167500$28710.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 2) Optimizing lut $abc$167501$lut$aiger167500$28705.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$167501$lut$aiger167500$28573.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 2) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$167927.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$167501$lut$aiger167500$28553.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$167928.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$167582.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$167501$lut\Controller.data_memory_read_data[22].genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1) Optimizing lut $abc$167501$lut\Controller.data_memory_read_data[20].genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $abc$167501$lut\Controller.data_memory_read_data[20].genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$167931.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$167501$lut$aiger167500$26804.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$167501$lut$aiger167500$26690.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$167501$lut$aiger167500$26690.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3) Optimizing lut $abc$167501$lut$aiger167500$26304.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$167501$lut$aiger167500$26304.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$167620.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$167933.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$167631.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$167636.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$167501$lut\Controller.data_memory_read_data[16].genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $abc$167501$lut\Controller.data_memory_read_data[16].genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$167935.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$167501$lut\Controller.data_memory_read_data[15].genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1) Optimizing lut $abc$167501$lut$aiger167500$24773.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$167501$lut\Controller.data_memory_read_data[14].genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$167670.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$167501$lut$aiger167500$24130.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$167501$lut\Controller.data_memory_read_data[13].genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$167938.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$167501$lut$aiger167500$23780.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$167683.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$167501$lut$aiger167500$23526.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$167501$lut$aiger167500$23117.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$167501$lut$aiger167500$22908.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$167501$lut$aiger167500$22908.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$167501$lut$aiger167500$22900.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1) Optimizing lut $abc$167501$lut$aiger167500$22900.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1) Optimizing lut $abc$167501$lut$aiger167500$22900.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 1) Optimizing lut $abc$167501$lut$aiger167500$22900.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 1) Optimizing lut $abc$167501$lut$aiger167500$22900.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 2) Optimizing lut $abc$167501$lut$aiger167500$22900.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 2) Optimizing lut $abc$167501$lut$aiger167500$22672.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$167501$lut$aiger167500$22672.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3) Optimizing lut $abc$167501$lut$aiger167500$22412.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$167704.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$167501$lut$aiger167500$22133.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$167501$lut$aiger167500$22133.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3) Optimizing lut $abc$167501$lut$aiger167500$22006.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$167716.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$167501$lut$aiger167500$21642.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$167501$lut\Controller.data_memory_read_data[8].genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $abc$167501$lut\Controller.data_memory_read_data[8].genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1) Optimizing lut $abc$167501$lut$aiger167500$20745.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3) Optimizing lut $abc$167501$lut$aiger167500$20740.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$167501$lut$aiger167500$20607.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 2) Optimizing lut $abc$167501$lut$aiger167500$20607.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 2) Optimizing lut $abc$167501$lut$aiger167500$20607.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 2) Optimizing lut $abc$167501$lut$aiger167500$20607.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 2) Optimizing lut $abc$167501$lut$aiger167500$20607.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 2) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$167944.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$167501$lut$aiger167500$20434.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$167501$lut$aiger167500$20342.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3) Optimizing lut $abc$167501$lut$aiger167500$20342.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3) Optimizing lut $abc$167501$lut$aiger167500$20342.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 3) Optimizing lut $abc$167501$lut$aiger167500$20342.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 3) Optimizing lut $abc$167501$lut$aiger167500$20342.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 3) Optimizing lut $abc$167501$lut$aiger167500$20336.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$167501$lut$aiger167500$20204.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 2) Optimizing lut $abc$167501$lut$aiger167500$20204.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 2) Optimizing lut $abc$167501$lut$aiger167500$20204.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 2) Optimizing lut $abc$167501$lut$aiger167500$20204.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 2) Optimizing lut $abc$167501$lut$aiger167500$20204.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 2) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$167748.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$167501$lut$aiger167500$20000.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$167501$lut$aiger167500$19586.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$167501$lut$aiger167500$19586.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3) Optimizing lut $abc$167501$lut$aiger167500$19581.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$167501$lut$aiger167500$19391.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1) Optimizing lut $abc$167501$lut$aiger167500$19391.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1) Optimizing lut $abc$167501$lut$aiger167500$19391.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 1) Optimizing lut $abc$167501$lut$aiger167500$19391.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 1) Optimizing lut $abc$167501$lut$aiger167500$19391.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 2) Optimizing lut $abc$167501$lut$aiger167500$19391.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 2) Optimizing lut $abc$167501$lut$aiger167500$19262.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1) Optimizing lut $abc$167501$lut$aiger167500$19190.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$167501$lut$aiger167500$19190.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$167501$lut$aiger167500$19123.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1) Optimizing lut $abc$167501$lut$aiger167500$19076.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$167501$lut$aiger167500$19069.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $abc$167501$lut$aiger167500$19069.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$167501$lut$aiger167500$19069.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$167501$lut$aiger167500$19069.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 1) Optimizing lut $abc$167501$lut$aiger167500$19069.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 1) Optimizing lut $abc$167501$lut$aiger167500$19069.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 1) Optimizing lut $abc$167501$lut$aiger167500$19069.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0) Optimizing lut $abc$167501$lut$aiger167500$19051.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$167501$lut$aiger167500$19051.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$167501$lut$aiger167500$19051.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1) Optimizing lut $abc$167501$lut$aiger167500$19051.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 1) Optimizing lut $abc$167501$lut$aiger167500$19051.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0) Optimizing lut $abc$167501$lut$aiger167500$19051.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 1) Optimizing lut $abc$167501$lut$aiger167500$19051.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 1) Optimizing lut $abc$167501$lut$aiger167500$19031.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$167501$lut$aiger167500$19031.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$167501$lut$aiger167500$19031.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0) Optimizing lut $abc$167501$lut$aiger167500$19031.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0) Optimizing lut $abc$167501$lut$aiger167500$19031.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0) Optimizing lut $abc$167501$lut$aiger167500$19020.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1) Optimizing lut $abc$167501$lut$aiger167500$19020.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1) Optimizing lut $abc$167501$lut$aiger167500$19020.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 1) Optimizing lut $abc$167501$lut$aiger167500$19020.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 1) Optimizing lut $abc$167501$lut$aiger167500$19020.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 2) Optimizing lut $abc$167501$lut$aiger167500$19020.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 2) Optimizing lut $abc$167501$lut$aiger167500$19011.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$167501$lut$aiger167500$19011.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$167501$lut$aiger167500$19011.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$167501$lut$aiger167500$19011.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0) Optimizing lut $abc$167501$lut$aiger167500$19011.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0) Optimizing lut $abc$167501$lut$aiger167500$19011.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0) Optimizing lut $abc$167501$lut$aiger167500$19000.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1) Optimizing lut $abc$167501$lut$aiger167500$19000.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1) Optimizing lut $abc$167501$lut$aiger167500$19000.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 1) Optimizing lut $abc$167501$lut$aiger167500$19000.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 1) Optimizing lut $abc$167501$lut$aiger167500$19000.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 2) Optimizing lut $abc$167501$lut$aiger167500$19000.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 2) Optimizing lut $abc$167501$lut$aiger167500$18991.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $abc$167501$lut$aiger167500$18987.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$167501$lut$aiger167500$18978.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1) Optimizing lut $abc$167501$lut$aiger167500$18978.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$167501$lut$aiger167500$18978.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0) Optimizing lut $abc$167501$lut$aiger167500$18978.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 1) Optimizing lut $abc$167501$lut$aiger167500$18978.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 1) Optimizing lut $abc$167501$lut$aiger167500$18978.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 1) Optimizing lut $abc$167501$lut$aiger167500$18961.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$167501$lut\Core.instruction_data[19].genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1) Optimizing lut $abc$167501$lut$aiger167500$18856.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1) Optimizing lut $abc$167501$lut$aiger167500$18856.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1) Optimizing lut $abc$167501$lut$aiger167500$18856.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 1) Optimizing lut $abc$167501$lut$aiger167500$18856.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 1) Optimizing lut $abc$167501$lut$aiger167500$18856.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 2) Optimizing lut $abc$167501$lut$aiger167500$18856.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 2) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$167946.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$167501$lut$aiger167500$18742.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$167501$lut$aiger167500$18359.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$167501$lut$aiger167500$18036.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3) Optimizing lut $abc$167501$lut$aiger167500$17965.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$167501$lut$aiger167500$17965.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$167501$lut$aiger167500$17898.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 2) Optimizing lut $abc$167501$lut$aiger167500$17898.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 2) Optimizing lut $abc$167501$lut$aiger167500$17898.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 2) Optimizing lut $abc$167501$lut$aiger167500$17898.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 2) Optimizing lut $abc$167501$lut$aiger167500$17898.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 2) Optimizing lut $abc$167501$lut$aiger167500$17642.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$167815.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$167501$lut$aiger167500$17230.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$167501$lut$aiger167500$17010.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3) Optimizing lut $abc$167501$lut$aiger167500$17010.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 2) Optimizing lut $abc$167501$lut$aiger167500$17010.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0) Optimizing lut $abc$167501$lut$aiger167500$17010.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0) Optimizing lut $abc$167501$lut$aiger167500$17010.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0) Optimizing lut $abc$167501$lut$aiger167500$17010.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0) Optimizing lut $abc$167501$lut$aiger167500$17002.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1) Optimizing lut $abc$167501$lut$aiger167500$17002.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1) Optimizing lut $abc$167501$lut$aiger167500$17002.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 1) Optimizing lut $abc$167501$lut$aiger167500$17002.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 1) Optimizing lut $abc$167501$lut$aiger167500$17002.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 2) Optimizing lut $abc$167501$lut$aiger167500$17002.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 2) Optimizing lut $abc$167501$lut$aiger167500$16935.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$167501$lut$aiger167500$16931.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $abc$167501$lut$aiger167500$16931.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1) Optimizing lut $abc$167501$lut$aiger167500$16856.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3) Optimizing lut $abc$167501$lut$aiger167500$16856.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 2) Optimizing lut $abc$167501$lut$aiger167500$16844.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1) Optimizing lut $abc$167501$lut$aiger167500$16844.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1) Optimizing lut $abc$167501$lut$aiger167500$16844.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 1) Optimizing lut $abc$167501$lut$aiger167500$16844.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 1) Optimizing lut $abc$167501$lut$aiger167500$16844.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 2) Optimizing lut $abc$167501$lut$aiger167500$16844.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 2) Optimizing lut $abc$167501$lut$aiger167500$16828.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$167501$lut$aiger167500$16828.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$167501$lut$aiger167500$16828.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1) Optimizing lut $abc$167501$lut$aiger167500$16828.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0) Optimizing lut $abc$167501$lut$aiger167500$16828.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0) Optimizing lut $abc$167501$lut$aiger167500$16828.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 1) Optimizing lut $abc$167501$lut$aiger167500$16828.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 1) Optimizing lut $abc$167501$lut$aiger167500$16512.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$167949.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$167501$lut$aiger167500$16315.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$167501$lut$aiger167500$16042.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1) Optimizing lut $abc$167501$lut$aiger167500$16042.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1) Optimizing lut $abc$167501$lut$aiger167500$16042.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 1) Optimizing lut $abc$167501$lut$aiger167500$16042.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 1) Optimizing lut $abc$167501$lut$aiger167500$16042.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 2) Optimizing lut $abc$167501$lut$aiger167500$16042.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 2) Optimizing lut $abc$167501$lut$aiger167500$16033.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$167501$lut$aiger167500$16033.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1) Optimizing lut $abc$167501$lut$aiger167500$16033.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1) Optimizing lut $abc$167501$lut$aiger167500$16033.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 1) Optimizing lut $abc$167501$lut$aiger167500$16033.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 1) Optimizing lut $abc$167501$lut$aiger167500$16033.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 2) Optimizing lut $abc$167501$lut$aiger167500$16033.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 2) Optimizing lut $abc$167501$lut$aiger167500$15822.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$167501$lut\Core.zero.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$167501$lut\Core.zero.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$167501$lut\Core.zero.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0) Optimizing lut $abc$167501$lut\Core.zero.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0) Optimizing lut $abc$167501$lut\Core.zero.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0) Optimizing lut $abc$167501$lut$aiger167500$14496.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$167501$lut$aiger167500$14496.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$167864.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$167864.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$167501$lut$aiger167500$14178.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$167501$lut$aiger167500$14178.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$167501$lut$aiger167500$14160.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3) Optimizing lut $abc$167501$lut$aiger167500$13956.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$167501$lut$aiger167500$13947.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$167501$lut$aiger167500$13947.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$167501$lut$aiger167500$13942.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$167501$lut$aiger167500$13942.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3) Optimizing lut $abc$167501$lut$aiger167500$13890.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$167501$lut$aiger167500$13890.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$167501$lut$aiger167500$13576.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$167501$lut$aiger167500$13576.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$167501$lut$aiger167500$13576.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0) Optimizing lut $abc$167501$lut$aiger167500$13576.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0) Optimizing lut $abc$167501$lut$aiger167500$13576.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$167877.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$167501$lut$aiger167500$13470.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$167501$lut$aiger167500$13465.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$167501$lut$aiger167500$13465.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$167501$lut$aiger167500$13231.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$167501$lut$aiger167500$13231.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$167950.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$167501$lut$aiger167500$12650.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$167889.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$167501$lut$aiger167500$12189.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1) Optimizing lut $abc$167501$lut$aiger167500$12189.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1) Optimizing lut $abc$167501$lut$aiger167500$12189.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 1) Optimizing lut $abc$167501$lut$aiger167500$12189.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 1) Optimizing lut $abc$167501$lut$aiger167500$12189.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 2) Optimizing lut $abc$167501$lut$aiger167500$12189.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 2) Optimizing lut $abc$167501$lut$aiger167500$12180.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$167501$lut$aiger167500$12180.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$167501$lut$aiger167500$12180.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$167501$lut$aiger167500$12173.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$167501$lut$aiger167500$12173.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3) Optimizing lut $abc$167501$lut$aiger167500$12173.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3) Optimizing lut $abc$167501$lut$aiger167500$12166.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$167501$lut$aiger167500$12166.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1) Optimizing lut $abc$167501$lut$aiger167500$12166.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1) Optimizing lut $abc$167501$lut$aiger167500$12166.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 1) Optimizing lut $abc$167501$lut$aiger167500$12166.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 1) Optimizing lut $abc$167501$lut$aiger167500$12166.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 2) Optimizing lut $abc$167501$lut$aiger167500$12166.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 2) Optimizing lut $abc$167501$lut$aiger167500$12157.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$167501$lut$aiger167500$12157.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3) Optimizing lut $abc$167501$lut$aiger167500$12157.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3) Optimizing lut $abc$167501$lut$aiger167500$12104.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$167501$lut$aiger167500$12098.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$167501$lut$aiger167500$12058.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$167501$lut\Controller.data_memory_read_data[0].genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1) Optimizing lut $abc$167501$lut$aiger167500$11573.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 2) Optimizing lut $abc$167501$lut$aiger167500$11573.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 2) Optimizing lut $abc$167501$lut$aiger167500$11554.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2) Optimizing lut $abc$167501$lut$aiger167500$11554.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$167501$lut$aiger167500$11554.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$167501$lut$aiger167500$11554.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 2) Optimizing lut $abc$167501$lut$aiger167500$11554.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0) Optimizing lut $abc$167501$lut$aiger167500$11554.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 2) Optimizing lut $abc$167501$lut$aiger167500$11554.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0) Optimizing lut $abc$167501$lut$aiger167500$11547.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$167501$lut$aiger167500$11547.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 2) Optimizing lut $abc$167501$lut$aiger167500$11547.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 2) Optimizing lut $abc$167501$lut$aiger167500$11538.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$167501$lut$aiger167500$11538.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$167501$lut$aiger167500$11471.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$167501$lut$aiger167500$11508.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$167501$lut$aiger167500$11516.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$167501$lut$aiger167500$11538.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $abc$167501$lut$aiger167500$11538.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2) Optimizing lut $abc$167501$lut$aiger167500$11547.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$167501$lut$aiger167500$11554.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $abc$167501$lut$aiger167500$11558.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$167501$lut$aiger167500$11573.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$167501$lut$aiger167500$11573.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$167501$lut$aiger167500$11597.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$167501$lut$aiger167500$11604.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$167501$lut$aiger167500$11616.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$167501$lut$aiger167500$11640.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$167501$lut$aiger167500$11646.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $abc$167501$lut$aiger167500$11653.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$167501$lut$aiger167500$11671.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$167501$lut$aiger167500$11678.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$167501$lut$aiger167500$11690.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$167501$lut$aiger167500$11719.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$167501$lut\Controller.data_memory_read_data[0].genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $abc$167501$lut$aiger167500$11805.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$167501$lut$aiger167500$11816.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$167501$lut$aiger167500$11845.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$167501$lut$aiger167500$11849.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$167501$lut$aiger167500$11869.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$167501$lut$aiger167500$11873.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$167501$lut$aiger167500$11961.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$167501$lut$aiger167500$12058.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$167501$lut$aiger167500$12064.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$167501$lut$aiger167500$12064.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$167501$lut$aiger167500$12098.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$167501$lut$aiger167500$12104.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$167501$lut$aiger167500$12110.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$167501$lut$aiger167500$12110.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$167501$lut$aiger167500$12116.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$167501$lut$aiger167500$12134.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$167501$lut$aiger167500$12157.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$167501$lut$aiger167500$12166.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$167501$lut$aiger167500$12173.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$167501$lut$aiger167500$12180.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$167501$lut$aiger167500$12189.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$167501$lut$aiger167500$12189.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$167501$lut$aiger167500$12199.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$167501$lut$aiger167500$12217.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$167501$lut$aiger167500$12224.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$167501$lut$aiger167500$12236.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$167501$lut$aiger167500$12254.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$167501$lut$aiger167500$12272.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$167501$lut$aiger167500$12338.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$167501$lut$aiger167500$12449.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$167501$lut$aiger167500$12470.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$167501$lut$aiger167500$12493.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$167501$lut$aiger167500$12533.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $abc$167501$lut$aiger167500$12533.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$167501$lut$flatten\Core.$procmux$2654_Y[0].genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$167501$lut$aiger167500$12625.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$167501$lut$aiger167500$12681.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$167501$lut$flatten\Core.$procmux$2660_Y[0].genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$167501$lut$aiger167500$12709.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$167501$lut$aiger167500$12734.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$167501$lut$aiger167500$12750.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$167501$lut$aiger167500$12766.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$167501$lut$aiger167500$12792.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$167501$lut$aiger167500$12819.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$167501$lut$aiger167500$12835.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$167501$lut$aiger167500$12851.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$167501$lut$aiger167500$13101.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$167501$lut$aiger167500$13244.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$167501$lut$aiger167500$13470.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$167501$lut$aiger167500$13470.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2) Optimizing lut $abc$167501$lut$aiger167500$13510.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$167501$lut$aiger167500$13566.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$167501$lut$aiger167500$13576.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$167501$lut$aiger167500$13576.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$167501$lut$aiger167500$13624.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$167876.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$167501$lut$aiger167500$13658.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$167501$lut$aiger167500$13726.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$167501$lut$aiger167500$13767.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$167501$lut$aiger167500$13805.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$167501$lut$aiger167500$13817.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$167501$lut$aiger167500$13845.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$167501$lut$aiger167500$13890.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$167501$lut$aiger167500$13947.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$167501$lut$aiger167500$13956.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$167501$lut$aiger167500$13956.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$167501$lut$aiger167500$13973.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$167501$lut$aiger167500$14016.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$167501$lut$aiger167500$14056.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$167870.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$167501$lut$aiger167500$14103.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$167501$lut$aiger167500$14132.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$167501$lut$aiger167500$14160.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$167501$lut$aiger167500$14182.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$167501$lut$aiger167500$14214.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$167501$lut$aiger167500$14243.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$167501$lut$aiger167500$14267.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$167865.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$167501$lut$aiger167500$14343.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$167501$lut$aiger167500$14406.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$167501$lut$aiger167500$14433.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$167501$lut$aiger167500$14455.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$167501$lut$aiger167500$14459.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$167864.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$167501$lut$aiger167500$14500.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$167501$lut\Core.zero.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$167501$lut$aiger167500$14685.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$167501$lut$aiger167500$14698.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$167501$lut$aiger167500$14780.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$167501$lut$aiger167500$14795.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$167501$lut$aiger167500$14840.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$167501$lut$aiger167500$14897.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$167501$lut$aiger167500$14942.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$167501$lut$aiger167500$14976.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$167501$lut$aiger167500$15038.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$167501$lut$aiger167500$15057.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$167501$lut$aiger167500$15081.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$167501$lut$aiger167500$15094.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$167501$lut$aiger167500$15264.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$167501$lut$aiger167500$15290.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$167501$lut$aiger167500$15404.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$167501$lut$aiger167500$15429.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$167501$lut$aiger167500$15445.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$167501$lut$aiger167500$15465.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$167501$lut$aiger167500$15514.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$167501$lut$aiger167500$15530.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$167501$lut$aiger167500$15643.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$167501$lut$aiger167500$15736.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$167501$lut$aiger167500$15769.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$167501$lut$aiger167500$15785.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$167501$lut$aiger167500$15801.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$167501$lut$aiger167500$15817.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$167501$lut$aiger167500$15822.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$167501$lut$aiger167500$15822.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$167501$lut$aiger167500$15829.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$167501$lut$aiger167500$15862.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$167501$lut$aiger167500$15878.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$167501$lut$aiger167500$15888.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$167501$lut$aiger167500$15937.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$167501$lut$aiger167500$15944.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$167501$lut$aiger167500$15951.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$167501$lut$aiger167500$15993.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$167501$lut$aiger167500$16009.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$167501$lut$aiger167500$16033.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$167501$lut$aiger167500$16042.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$167501$lut$aiger167500$16042.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$167501$lut$aiger167500$16048.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$167501$lut$aiger167500$16097.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$167501$lut$aiger167500$16113.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$167501$lut$auto$fsm_map.cc:170:map_fsm$2996[1].genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$167501$lut$aiger167500$16195.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$167501$lut$aiger167500$16215.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$167501$lut$aiger167500$16256.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$167501$lut$aiger167500$16294.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$167501$lut$aiger167500$16320.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$167501$lut$aiger167500$16349.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $abc$167501$lut$aiger167500$16349.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$167501$lut$aiger167500$16358.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $abc$167501$lut$aiger167500$16358.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$167501$lut$aiger167500$16399.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$167501$lut$aiger167500$16426.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$167501$lut$aiger167500$16450.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$167501$lut$aiger167500$16475.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$167501$lut$aiger167500$16491.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$167501$lut$aiger167500$16507.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$167501$lut$aiger167500$16512.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$167501$lut$aiger167500$16651.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$167501$lut$aiger167500$16664.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$167501$lut$aiger167500$16677.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $abc$167501$lut$aiger167500$16684.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$167501$lut$aiger167500$16700.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$167501$lut$aiger167500$16749.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$167501$lut$aiger167500$16775.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$167501$lut$aiger167500$16779.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$167501$lut$aiger167500$16828.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$167501$lut$aiger167500$16832.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$167501$lut$aiger167500$16844.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$167501$lut$aiger167500$16844.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$167501$lut$aiger167500$16856.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$167501$lut$aiger167500$16872.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$167501$lut$aiger167500$16880.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$167501$lut$aiger167500$16897.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$167501$lut$aiger167500$16922.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$167501$lut$aiger167500$16931.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$167501$lut$aiger167500$16957.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$167501$lut$aiger167500$17002.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$167501$lut$aiger167500$17002.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$167501$lut$aiger167500$17010.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$167501$lut$aiger167500$17033.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$167501$lut$aiger167500$17051.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$167501$lut$aiger167500$17076.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$167501$lut$aiger167500$17108.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$167501$lut$aiger167500$17142.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$167501$lut$aiger167500$17149.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$167501$lut$aiger167500$17157.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$167501$lut$aiger167500$17176.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$167501$lut$aiger167500$17192.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$167501$lut$aiger167500$17208.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$167501$lut$aiger167500$17225.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$167501$lut$aiger167500$17230.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$167501$lut$aiger167500$17263.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $abc$167501$lut$aiger167500$17294.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $abc$167501$lut$aiger167500$17294.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$167501$lut$aiger167500$17304.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $abc$167501$lut$aiger167500$17304.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$167501$lut$aiger167500$17314.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $abc$167501$lut$aiger167500$17314.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$167501$lut$aiger167500$17329.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$167501$lut$flatten\Core.$procmux$2654_Y[2].genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$167501$lut$aiger167500$17396.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$167501$lut$aiger167500$17416.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$167501$lut$aiger167500$17458.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$167501$lut$aiger167500$17556.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$167501$lut$aiger167500$17589.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$167501$lut$aiger167500$17605.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$167501$lut$aiger167500$17621.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$167501$lut$aiger167500$17637.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$167501$lut$aiger167500$17642.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$167501$lut$aiger167500$17667.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $abc$167501$lut$aiger167500$17667.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$167501$lut$aiger167500$17676.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $abc$167501$lut$aiger167500$17676.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$167501$lut$aiger167500$17689.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $abc$167501$lut$aiger167500$17689.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$167501$lut$aiger167500$17698.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $abc$167501$lut$aiger167500$17698.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$167501$lut$aiger167500$17725.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$167501$lut$aiger167500$17746.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$167501$lut$aiger167500$17776.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$167501$lut$aiger167500$17792.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$167501$lut$aiger167500$17808.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$167501$lut$aiger167500$17816.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$167501$lut$aiger167500$17835.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$167501$lut$aiger167500$17860.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$167501$lut$aiger167500$17876.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$167501$lut$aiger167500$17892.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$167501$lut$aiger167500$17898.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $abc$167501$lut$aiger167500$17898.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2) Optimizing lut $abc$167501$lut$aiger167500$17914.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$167501$lut$aiger167500$17921.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$167501$lut$aiger167500$17943.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$167501$lut$aiger167500$17959.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$167501$lut$aiger167500$17965.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$167501$lut$aiger167500$17972.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$167501$lut$aiger167500$17988.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$167501$lut$aiger167500$17995.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$167501$lut$aiger167500$18005.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$167501$lut$aiger167500$18031.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$167501$lut$aiger167500$18036.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$167501$lut$aiger167500$18036.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$167501$lut$aiger167500$18098.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $abc$167501$lut$aiger167500$18098.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$167501$lut$aiger167500$18107.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $abc$167501$lut$aiger167500$18107.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$167501$lut$aiger167500$18120.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $abc$167501$lut$aiger167500$18120.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$167501$lut$aiger167500$18129.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $abc$167501$lut$aiger167500$18129.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$167501$lut$aiger167500$18156.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$167501$lut$aiger167500$18177.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$167501$lut$aiger167500$18238.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$167501$lut$aiger167500$18287.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$167501$lut$aiger167500$18305.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$167501$lut$aiger167500$18321.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$167501$lut$aiger167500$18337.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$167501$lut$aiger167500$18354.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$167501$lut$aiger167500$18359.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$167501$lut$aiger167500$18444.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $abc$167501$lut$aiger167500$18444.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$167501$lut$aiger167500$18453.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $abc$167501$lut$aiger167500$18453.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$167501$lut$aiger167500$18466.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $abc$167501$lut$aiger167500$18466.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$167501$lut$aiger167500$18475.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $abc$167501$lut$aiger167500$18475.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$167501$lut$aiger167500$18502.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$167501$lut$aiger167500$18523.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$167501$lut$aiger167500$18567.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$167501$lut$aiger167500$18583.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$167501$lut$aiger167500$18599.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$167501$lut$aiger167500$18615.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$167501$lut$aiger167500$18634.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$167501$lut$aiger167500$18651.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$167501$lut$aiger167500$18684.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$167501$lut$aiger167500$18721.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$167501$lut$aiger167500$18747.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$167501$lut$aiger167500$18776.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $abc$167501$lut$aiger167500$18776.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$167501$lut$aiger167500$18785.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $abc$167501$lut$aiger167500$18785.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$167501$lut$flatten\Core.$procmux$2660_Y[4].genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$167501$lut$aiger167500$18804.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$167501$lut$aiger167500$18829.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$167501$lut$aiger167500$18856.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$167501$lut$aiger167500$18856.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$167501$lut$aiger167500$18867.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$167501$lut$aiger167500$18874.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$167501$lut$aiger167500$18890.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$167501$lut$aiger167500$18915.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$167501$lut$aiger167500$18931.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$167501$lut$aiger167500$18954.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$167501$lut$aiger167500$18965.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$167501$lut$aiger167500$18978.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$167501$lut$aiger167500$18978.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$167501$lut$aiger167500$18987.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$167501$lut$aiger167500$19000.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$167501$lut$aiger167500$19000.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$167501$lut$aiger167500$19011.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$167501$lut$aiger167500$19020.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$167501$lut$aiger167500$19020.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$167501$lut$aiger167500$19031.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$167501$lut$aiger167500$19031.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$167501$lut$aiger167500$19051.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$167501$lut$aiger167500$19055.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$167501$lut$aiger167500$19069.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$167501$lut$aiger167500$19076.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$167501$lut$aiger167500$19080.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $abc$167501$lut$aiger167500$19097.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$167501$lut$aiger167500$19105.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$167501$lut$aiger167500$19123.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$167501$lut$aiger167500$19123.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $abc$167501$lut$aiger167500$19130.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$167501$lut$aiger167500$19146.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$167501$lut$aiger167500$19190.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$167501$lut$aiger167500$19197.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$167501$lut$aiger167500$19213.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$167501$lut$aiger167500$19220.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$167501$lut$aiger167500$19230.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$167501$lut$aiger167500$19256.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$167501$lut$aiger167500$19262.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $abc$167501$lut$aiger167500$19391.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$167501$lut$aiger167500$19391.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$167501$lut$aiger167500$19402.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$167501$lut$aiger167500$19412.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$167501$lut$aiger167500$19428.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$167501$lut$aiger167500$19444.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$167501$lut$aiger167500$19448.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$167501$lut$aiger167500$19471.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$167501$lut$aiger167500$19487.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$167501$lut$aiger167500$19503.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$167501$lut$aiger167500$19522.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$167501$lut$aiger167500$19538.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$167501$lut$aiger167500$19548.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$167501$lut$aiger167500$19555.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$167501$lut$aiger167500$19571.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$167501$lut$aiger167500$19586.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$167501$lut$aiger167500$19590.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$167501$lut$aiger167500$19641.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$167501$lut$aiger167500$19663.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$167501$lut$aiger167500$19679.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$167501$lut$aiger167500$19745.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$167501$lut$aiger167500$19761.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$167501$lut$aiger167500$19805.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $abc$167501$lut$aiger167500$19805.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$167501$lut$aiger167500$19979.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$167501$lut$aiger167500$20005.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$167501$lut$aiger167500$20034.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $abc$167501$lut$aiger167500$20034.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$167501$lut$aiger167500$20043.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $abc$167501$lut$aiger167500$20043.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$167501$lut$aiger167500$20083.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$167501$lut$aiger167500$20099.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$167501$lut$aiger167500$20115.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$167501$lut$aiger167500$20131.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$167501$lut$aiger167500$20141.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$167501$lut$aiger167500$20166.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$167501$lut$aiger167500$20182.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$167501$lut$aiger167500$20198.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$167501$lut$aiger167500$20204.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $abc$167501$lut$aiger167500$20204.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2) Optimizing lut $abc$167501$lut$aiger167500$20211.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$167501$lut$aiger167500$20237.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$167501$lut$aiger167500$20244.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$167501$lut$aiger167500$20260.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$167501$lut$aiger167500$20270.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$167501$lut$aiger167500$20292.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$167501$lut$aiger167500$20299.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$167501$lut$aiger167500$20303.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$167501$lut$aiger167500$20325.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$167501$lut$aiger167500$20332.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$167501$lut$aiger167500$20342.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$167501$lut$aiger167500$20342.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$167501$lut$aiger167500$20356.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $abc$167501$lut$aiger167500$20356.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$167501$lut$aiger167500$20366.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $abc$167501$lut$aiger167500$20366.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$167501$lut$aiger167500$20376.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $abc$167501$lut$aiger167500$20376.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$167501$lut$aiger167500$20391.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$167501$lut$aiger167500$20407.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$167501$lut$aiger167500$20407.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$167501$lut$aiger167500$20485.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$167501$lut$aiger167500$20501.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$167501$lut$aiger167500$20517.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$167501$lut$aiger167500$20525.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$167501$lut$aiger167500$20544.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$167501$lut$aiger167500$20569.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$167501$lut$aiger167500$20585.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$167501$lut$aiger167500$20601.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$167501$lut$aiger167500$20607.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $abc$167501$lut$aiger167500$20607.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2) Optimizing lut $abc$167501$lut$aiger167500$20614.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$167501$lut$aiger167500$20621.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$167501$lut$aiger167500$20630.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$167501$lut$aiger167500$20646.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$167501$lut$aiger167500$20671.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$167501$lut$aiger167500$20681.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$167501$lut$aiger167500$20697.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$167501$lut$aiger167500$20704.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$167501$lut$aiger167500$20729.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$167501$lut$aiger167500$20736.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$167501$lut$aiger167500$20745.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$167501$lut$aiger167500$20745.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$167501$lut$aiger167500$20846.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$167501$lut$aiger167500$20868.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$167501$lut$aiger167500$20889.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$167501$lut$aiger167500$20912.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $abc$167501$lut$aiger167500$20912.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$167501$lut$aiger167500$20921.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $abc$167501$lut$aiger167500$20921.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$167501$lut$aiger167500$20934.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $abc$167501$lut$aiger167500$20934.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$167501$lut$aiger167500$20943.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $abc$167501$lut$aiger167500$20943.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$167501$lut$aiger167500$20970.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$167501$lut$aiger167500$20991.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$167501$lut$aiger167500$21080.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$167501$lut$aiger167500$21096.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$167501$lut$aiger167500$21112.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$167501$lut$aiger167500$21131.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$167501$lut$aiger167500$21180.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$167501$lut$aiger167500$21196.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$167501$lut$aiger167500$21234.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $abc$167501$lut$aiger167500$21234.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$167501$lut$aiger167500$21243.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $abc$167501$lut$aiger167500$21243.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$167501$lut$aiger167500$21256.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $abc$167501$lut$aiger167500$21256.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$167501$lut$aiger167500$21265.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $abc$167501$lut$aiger167500$21265.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$167501$lut$aiger167500$21292.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$167501$lut$aiger167500$21313.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$167501$lut$aiger167500$21355.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $abc$167501$lut$aiger167500$21355.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$167501$lut$aiger167500$21383.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$167501$lut$aiger167500$21404.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$167501$lut$aiger167500$21433.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$167501$lut$aiger167500$21446.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$167501$lut$aiger167500$21459.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $abc$167501$lut$aiger167500$21466.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$167501$lut$aiger167500$21482.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$167501$lut$aiger167500$21489.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$167501$lut$aiger167500$21499.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$167501$lut$aiger167500$21515.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$167501$lut$aiger167500$21522.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$167501$lut$aiger167500$21532.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$167501$lut$aiger167500$21548.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$167501$lut$aiger167500$21569.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$167501$lut$aiger167500$21621.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$167501$lut$aiger167500$21647.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$167501$lut$aiger167500$21676.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $abc$167501$lut$aiger167500$21676.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$167501$lut$aiger167500$21742.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$167501$lut$aiger167500$21749.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$167501$lut$aiger167500$21758.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$167501$lut$aiger167500$21774.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$167501$lut$aiger167500$21799.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$167501$lut$aiger167500$21809.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$167501$lut$aiger167500$21825.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$167501$lut$aiger167500$21832.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$167501$lut$aiger167500$21842.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$167501$lut$aiger167500$21858.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$167501$lut$aiger167500$21865.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$167501$lut$aiger167500$21887.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$167501$lut$aiger167500$21903.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$167501$lut$aiger167500$21920.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$167501$lut$aiger167500$21944.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$167501$lut$aiger167500$21969.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$167501$lut$aiger167500$21985.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$167501$lut$aiger167500$22001.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$167501$lut$aiger167500$22006.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$167501$lut$aiger167500$22039.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$167501$lut$aiger167500$22057.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$167501$lut$aiger167500$22079.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$167501$lut$aiger167500$22133.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$167501$lut$aiger167500$22137.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$167501$lut$aiger167500$22206.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $abc$167501$lut$aiger167500$22206.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$167501$lut$aiger167500$22216.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $abc$167501$lut$aiger167500$22216.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$167501$lut$flatten\Core.$procmux$2654_Y[10].genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$167501$lut$aiger167500$22326.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$167501$lut$aiger167500$22350.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$167501$lut$aiger167500$22375.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$167501$lut$aiger167500$22391.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$167501$lut$aiger167500$22407.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$167501$lut$aiger167500$22412.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$167501$lut$aiger167500$22426.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$167501$lut$aiger167500$22433.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$167501$lut$aiger167500$22442.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$167501$lut$aiger167500$22449.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$167501$lut$aiger167500$22457.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$167501$lut$aiger167500$22473.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$167501$lut$aiger167500$22486.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$167501$lut$aiger167500$22526.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$167501$lut$aiger167500$22577.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $abc$167501$lut$aiger167500$22577.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$167501$lut$aiger167500$22594.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$167501$lut$aiger167500$22602.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$167501$lut$aiger167500$22615.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$167501$lut$aiger167500$22631.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$167501$lut$aiger167500$22672.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$167501$lut$aiger167500$22676.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$167501$lut$aiger167500$22723.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $abc$167501$lut$aiger167500$22775.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $abc$167501$lut$aiger167500$22775.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$167501$lut$aiger167500$22793.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$167501$lut$aiger167500$22814.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$167501$lut$aiger167500$22855.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$167501$lut$aiger167500$22900.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$167501$lut$aiger167500$22900.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$167501$lut$aiger167500$22908.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$167501$lut$aiger167500$22915.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$167501$lut$aiger167500$22940.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$167501$lut$aiger167500$22957.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$167501$lut$aiger167500$22973.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$167501$lut$aiger167500$22977.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$167501$lut$aiger167500$23000.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$167501$lut$aiger167500$23016.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$167501$lut$aiger167500$23044.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$167501$lut$aiger167500$23051.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$167501$lut$aiger167500$23067.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$167501$lut$aiger167500$23074.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$167501$lut$aiger167500$23093.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$167501$lut$aiger167500$23100.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$167501$lut$aiger167500$23107.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$167501$lut$aiger167500$23173.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$167501$lut$aiger167500$23189.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$167501$lut$aiger167500$23233.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $abc$167501$lut$aiger167500$23233.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$167501$lut$aiger167500$23275.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$167501$lut$aiger167500$23291.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$167501$lut$aiger167500$23307.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$167501$lut$aiger167500$23326.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$167501$lut$aiger167500$23375.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$167501$lut$aiger167500$23391.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$167501$lut$aiger167500$23412.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$167501$lut$aiger167500$23434.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$167501$lut$aiger167500$23450.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$167501$lut$aiger167500$23457.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$167501$lut$aiger167500$23467.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$167501$lut$aiger167500$23515.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$167501$lut$aiger167500$23522.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$167501$lut$aiger167500$23577.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $abc$167501$lut$aiger167500$23577.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$167501$lut$aiger167500$23587.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $abc$167501$lut$aiger167500$23587.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$167501$lut$aiger167500$23720.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $abc$167501$lut$aiger167500$23720.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$167501$lut$aiger167500$23730.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $abc$167501$lut$aiger167500$23730.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$167501$lut$aiger167500$23753.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$167501$lut$aiger167500$23753.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$167501$lut$aiger167500$23866.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$167501$lut$aiger167500$23899.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$167501$lut$aiger167500$23915.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$167501$lut$aiger167500$23922.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$167501$lut$aiger167500$23965.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$167501$lut$aiger167500$23990.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$167501$lut\Controller.data_memory_read_data[13].genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $abc$167501$lut$aiger167500$24044.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$167501$lut$aiger167500$24077.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$167501$lut$aiger167500$24093.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$167501$lut$aiger167500$24109.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$167501$lut$aiger167500$24125.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$167501$lut$aiger167500$24130.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$167501$lut$aiger167500$24138.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $abc$167501$lut$aiger167500$24138.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$167501$lut$aiger167500$24148.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $abc$167501$lut$aiger167500$24148.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$167501$lut$aiger167500$24158.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $abc$167501$lut$aiger167500$24158.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$167501$lut$aiger167500$24173.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$167501$lut$aiger167500$24246.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$167501$lut$aiger167500$24265.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$167501$lut$aiger167500$24281.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$167501$lut$aiger167500$24325.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $abc$167501$lut$aiger167500$24325.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$167501$lut$aiger167500$24394.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$167501$lut$aiger167500$24410.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$167501$lut$aiger167500$24420.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$167501$lut$aiger167500$24427.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$167501$lut$aiger167500$24453.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$167501$lut$aiger167500$24460.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$167501$lut$aiger167500$24486.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$167501$lut$aiger167500$24493.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$167501$lut$aiger167500$24509.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$167501$lut$aiger167500$24539.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$167501$lut$aiger167500$24552.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $abc$167501$lut$aiger167500$24552.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$167501$lut$aiger167500$24580.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$167501$lut$aiger167500$24601.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$167501$lut$aiger167500$24687.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$167501$lut$aiger167500$24720.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$167501$lut$aiger167500$24736.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$167501$lut$aiger167500$24752.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$167501$lut$aiger167500$24768.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$167501$lut$aiger167500$24773.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$167501$lut$aiger167500$24778.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$167501$lut$aiger167500$24819.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$167501$lut$aiger167500$24842.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$167501$lut$aiger167500$24863.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$167501$lut$aiger167500$24904.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$167501$lut$aiger167500$24917.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$167501$lut$aiger167500$24930.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $abc$167501$lut$aiger167500$24937.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$167501$lut$aiger167500$24953.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$167501$lut$aiger167500$24960.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$167501$lut$aiger167500$24979.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$167501$lut$aiger167500$25003.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$167501$lut$aiger167500$25019.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$167501$lut\Controller.data_memory_read_data[15].genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $abc$167501$lut$aiger167500$25080.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $abc$167501$lut$aiger167500$25080.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$167501$lut$aiger167500$25089.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $abc$167501$lut$aiger167500$25089.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$167501$lut$aiger167500$25102.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $abc$167501$lut$aiger167500$25102.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$167501$lut$aiger167500$25111.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $abc$167501$lut$aiger167500$25111.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$167501$lut$aiger167500$25138.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$167501$lut$aiger167500$25159.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$167501$lut$aiger167500$25178.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $abc$167501$lut$aiger167500$25178.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$167501$lut$aiger167500$25188.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $abc$167501$lut$aiger167500$25188.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$167501$lut$aiger167500$25198.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $abc$167501$lut$aiger167500$25198.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$167501$lut$aiger167500$25213.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$167501$lut$aiger167500$25328.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$167501$lut$aiger167500$25344.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$167501$lut$aiger167500$25351.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$167501$lut$aiger167500$25361.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$167501$lut$aiger167500$25377.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$167501$lut$aiger167500$25387.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$167501$lut$aiger167500$25427.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$167501$lut$aiger167500$25443.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$167501$lut$aiger167500$25461.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$167501$lut$aiger167500$25521.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $abc$167501$lut$aiger167500$25521.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$167501$lut$aiger167500$25531.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $abc$167501$lut$aiger167500$25531.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$167501$lut$flatten\Core.$procmux$2654_Y[16].genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$167501$lut$aiger167500$25629.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $abc$167501$lut$aiger167500$25629.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$167501$lut$aiger167500$25647.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$167501$lut$aiger167500$25668.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$167501$lut$aiger167500$25745.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $abc$167501$lut$aiger167500$25745.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$167501$lut$aiger167500$25755.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $abc$167501$lut$aiger167500$25755.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$167501$lut$aiger167500$25832.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $abc$167501$lut$aiger167500$25832.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$167501$lut$aiger167500$25841.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $abc$167501$lut$aiger167500$25841.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$167501$lut$aiger167500$25863.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $abc$167501$lut$aiger167500$25863.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$167501$lut$aiger167500$25885.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$167501$lut$aiger167500$25885.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$167501$lut$aiger167500$25913.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$167501$lut$aiger167500$25942.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$167501$lut$aiger167500$25955.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$167501$lut$aiger167500$25968.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $abc$167501$lut$aiger167500$25975.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$167501$lut$aiger167500$25988.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$167501$lut$aiger167500$26001.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $abc$167501$lut$aiger167500$26008.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$167501$lut$aiger167500$26024.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$167501$lut$aiger167500$26049.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$167501$lut$aiger167500$26056.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$167501$lut$aiger167500$26063.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$167501$lut$aiger167500$26070.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$167501$lut$aiger167500$26155.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $abc$167501$lut$aiger167500$26155.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$167501$lut$aiger167500$26165.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $abc$167501$lut$aiger167500$26165.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$167501$lut$aiger167500$26244.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$167501$lut$aiger167500$26260.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$167501$lut$aiger167500$26276.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$167501$lut$aiger167500$26292.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$167501$lut$aiger167500$26299.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$167501$lut$aiger167500$26304.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$167501$lut$aiger167500$26311.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$167501$lut$aiger167500$26344.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$167501$lut$aiger167500$26360.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$167501$lut$aiger167500$26377.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$167501$lut$aiger167500$26427.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $abc$167501$lut$aiger167500$26427.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$167501$lut$aiger167500$26455.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$167501$lut$aiger167500$26476.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$167501$lut$aiger167500$26565.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$167501$lut$aiger167500$26572.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$167501$lut$aiger167500$26579.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$167501$lut$aiger167500$26589.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$167501$lut$aiger167500$26605.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$167501$lut$aiger167500$26616.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$167501$lut$aiger167500$26623.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$167501$lut$aiger167500$26639.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$167501$lut$aiger167500$26649.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$167501$lut$aiger167500$26656.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$167501$lut$aiger167500$26690.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$167501$lut$aiger167500$26694.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$167501$lut$aiger167500$26744.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $abc$167501$lut$aiger167500$26744.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$167501$lut$aiger167500$26754.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $abc$167501$lut$aiger167500$26754.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$167501$lut$aiger167500$26777.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$167501$lut$aiger167500$26777.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$167501$lut$aiger167500$26832.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$167501$lut$aiger167500$26848.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$167501$lut$aiger167500$26896.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$167501$lut$aiger167500$26948.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$167501$lut$aiger167500$26968.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$167501$lut$aiger167500$27006.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $abc$167501$lut$aiger167500$27006.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$167501$lut$aiger167500$27080.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$167501$lut$aiger167500$27098.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$167501$lut$aiger167500$27120.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$167501$lut$aiger167500$27164.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$167501$lut$aiger167500$27171.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$167501$lut$aiger167500$27204.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$167501$lut$aiger167500$27220.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$167501$lut$aiger167500$27230.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$167501$lut$aiger167500$27237.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$167501$lut$aiger167500$27270.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$167501$lut$aiger167500$27286.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$167501$lut$aiger167500$27389.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$167501$lut$aiger167500$27405.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$167501$lut$aiger167500$27421.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$167501$lut$aiger167500$27437.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$167501$lut$aiger167500$27456.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$167501$lut$aiger167500$27489.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$167501$lut$aiger167500$27505.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$167501$lut$aiger167500$27522.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$167501$lut$aiger167500$27546.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $abc$167501$lut$aiger167500$27546.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$167501$lut$aiger167500$27585.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$167501$lut$aiger167500$27606.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$167501$lut$aiger167500$27659.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $abc$167501$lut$aiger167500$27659.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$167501$lut$aiger167500$27687.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$167501$lut$aiger167500$27708.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$167501$lut$aiger167500$27746.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$167501$lut$aiger167500$27759.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$167501$lut$aiger167500$27772.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $abc$167501$lut$aiger167500$27779.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$167501$lut$aiger167500$27810.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$167501$lut$aiger167500$27817.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$167501$lut$aiger167500$27821.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$167501$lut$aiger167500$27837.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$167501$lut$aiger167500$27844.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$167501$lut$aiger167500$27854.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$167501$lut$aiger167500$27861.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$167501$lut$aiger167500$27894.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$167501$lut$aiger167500$27898.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$167501$lut$aiger167500$27932.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $abc$167501$lut$aiger167500$27932.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$167501$lut$aiger167500$28043.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $abc$167501$lut$aiger167500$28043.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$167501$lut$aiger167500$28053.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $abc$167501$lut$aiger167500$28053.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$167501$lut$aiger167500$28063.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $abc$167501$lut$aiger167500$28063.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$167501$lut$aiger167500$28078.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$167501$lut$aiger167500$28196.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$167501$lut$aiger167500$28218.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$167501$lut$aiger167500$28234.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$167501$lut$aiger167500$28300.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$167501$lut$aiger167500$28316.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$167501$lut$aiger167500$28332.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$167501$lut$aiger167500$28348.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$167501$lut$aiger167500$28367.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$167501$lut$aiger167500$28383.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$167501$lut$aiger167500$28390.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$167501$lut$aiger167500$28415.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$167501$lut$aiger167500$28422.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$167501$lut$aiger167500$28493.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $abc$167501$lut$aiger167500$28493.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$167501$lut$aiger167500$28503.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $abc$167501$lut$aiger167500$28503.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$167501$lut$aiger167500$28526.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$167501$lut$aiger167500$28526.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$167501$lut$aiger167500$28573.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $abc$167501$lut$aiger167500$28573.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2) Optimizing lut $abc$167501$lut$aiger167500$28580.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$167501$lut$aiger167500$28593.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$167501$lut$aiger167500$28606.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $abc$167501$lut$aiger167500$28613.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$167501$lut$aiger167500$28629.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$167501$lut$aiger167500$28636.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$167501$lut$aiger167500$28646.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$167501$lut$aiger167500$28662.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$167501$lut$aiger167500$28672.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$167501$lut$aiger167500$28694.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$167501$lut$aiger167500$28701.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$167501$lut$aiger167500$28710.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $abc$167501$lut$aiger167500$28760.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$167501$lut$aiger167500$28786.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$167501$lut$aiger167500$28815.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $abc$167501$lut$aiger167500$28815.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$167501$lut$flatten\Core.$procmux$2660_Y[24].genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$167501$lut$aiger167500$28893.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $abc$167501$lut$aiger167500$28893.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$167501$lut$aiger167500$28903.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $abc$167501$lut$aiger167500$28903.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$167501$lut$flatten\Core.$procmux$2654_Y[24].genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$167501$lut$aiger167500$29025.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $abc$167501$lut$aiger167500$29025.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$167501$lut$aiger167500$29064.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$167501$lut$aiger167500$29084.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$167501$lut$aiger167500$29122.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$167501$lut$aiger167500$29138.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$167501$lut$aiger167500$29154.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$167501$lut$aiger167500$29173.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$167501$lut$aiger167500$29222.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$167501$lut$aiger167500$29238.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$167501$lut$aiger167500$29261.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$167501$lut$aiger167500$29268.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$167501$lut$aiger167500$29284.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$167501$lut$aiger167500$29306.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$167501$lut$aiger167500$29312.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$167501$lut$aiger167500$29319.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$167501$lut$aiger167500$29335.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$167501$lut$aiger167500$29342.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$167501$lut$aiger167500$29367.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$167501$lut$aiger167500$29374.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$167501$lut$aiger167500$29398.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $abc$167501$lut$aiger167500$29398.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$167501$lut$aiger167500$29407.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $abc$167501$lut$aiger167500$29407.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$167501$lut$aiger167500$29420.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $abc$167501$lut$aiger167500$29420.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$167501$lut$aiger167500$29429.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $abc$167501$lut$aiger167500$29429.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$167501$lut$aiger167500$29456.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$167501$lut$aiger167500$29477.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$167501$lut$aiger167500$29531.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$167501$lut$aiger167500$29547.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$167501$lut$aiger167500$29557.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$167501$lut$aiger167500$29597.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$167501$lut$aiger167500$29623.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$167501$lut$aiger167500$29630.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$167501$lut$aiger167500$29655.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$167501$lut$aiger167500$29668.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $abc$167501$lut$aiger167500$29668.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$167501$lut$aiger167500$29677.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $abc$167501$lut$aiger167500$29677.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$167501$lut$aiger167500$29690.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $abc$167501$lut$aiger167500$29690.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$167501$lut$aiger167500$29699.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $abc$167501$lut$aiger167500$29699.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$167501$lut$aiger167500$29726.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$167501$lut$aiger167500$29747.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$167501$lut$aiger167500$29871.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$167501$lut$aiger167500$29871.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$167501$lut$aiger167500$29882.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$167501$lut$aiger167500$29892.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$167501$lut$aiger167500$29908.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$167501$lut$aiger167500$29912.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$167501$lut$aiger167500$29916.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$167501$lut$aiger167500$29936.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $abc$167501$lut$aiger167500$29936.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$167501$lut$aiger167500$29946.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $abc$167501$lut$aiger167500$29946.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$167501$lut$aiger167500$29956.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $abc$167501$lut$aiger167500$29956.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$167501$lut$aiger167500$29971.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$167501$lut$aiger167500$30069.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$167501$lut$aiger167500$30145.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$167501$lut$aiger167500$30161.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$167501$lut$aiger167500$30177.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$167501$lut$aiger167500$30193.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$167501$lut$aiger167500$30198.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$167501$lut$aiger167500$30198.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$167501$lut$aiger167500$30205.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$167501$lut$aiger167500$30221.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$167501$lut$aiger167500$30237.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$167501$lut$aiger167500$30244.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$167501$lut$aiger167500$30262.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$167501$lut$aiger167500$30272.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$167501$lut$aiger167500$30288.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$167501$lut$aiger167500$30295.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$167501$lut$aiger167500$30320.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$167501$lut$aiger167500$30327.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$167501$lut$aiger167500$30336.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$167501$lut$aiger167500$30378.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $abc$167501$lut$aiger167500$30378.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$167501$lut$aiger167500$30388.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $abc$167501$lut$aiger167500$30388.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$167501$lut$flatten\Core.$procmux$2654_Y[27].genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$167501$lut$aiger167500$30475.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$167501$lut$aiger167500$30475.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$167501$lut$aiger167500$30491.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$167501$lut$aiger167500$30525.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$167501$lut$aiger167500$30579.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $abc$167501$lut$aiger167500$30579.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$167501$lut$aiger167500$30589.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $abc$167501$lut$aiger167500$30589.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$167501$lut$aiger167500$30599.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $abc$167501$lut$aiger167500$30599.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$167501$lut$aiger167500$30614.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$167501$lut$aiger167500$30709.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$167501$lut$aiger167500$30732.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$167501$lut$aiger167500$30748.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$167501$lut$aiger167500$30830.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$167501$lut$aiger167500$30863.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$167501$lut$aiger167500$30879.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$167501$lut$aiger167500$30895.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$167501$lut$aiger167500$30911.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$167501$lut$aiger167500$30916.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$167501$lut$aiger167500$30916.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$167501$lut$aiger167500$30923.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$167501$lut$aiger167500$30939.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$167501$lut$aiger167500$30949.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$167501$lut$aiger167500$30956.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$167501$lut$aiger167500$30972.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$167501$lut$aiger167500$30979.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$167501$lut$aiger167500$30989.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$167501$lut$aiger167500$31005.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$167501$lut$aiger167500$31012.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$167501$lut$aiger167500$31022.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$167501$lut$aiger167500$31038.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$167501$lut$aiger167500$31045.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$167501$lut$aiger167500$31140.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$167501$lut$aiger167500$31164.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$167501$lut$aiger167500$31189.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$167501$lut$aiger167500$31205.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$167501$lut$aiger167500$31222.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$167501$lut$aiger167500$31227.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$167501$lut$aiger167500$31240.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$167501$lut$aiger167500$31256.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$167501$lut$aiger167500$31273.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$167501$lut$aiger167500$31299.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$167501$lut$aiger167500$31306.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$167501$lut$aiger167500$31319.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$167501$lut$aiger167500$31332.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $abc$167501$lut$aiger167500$31348.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$167501$lut$aiger167500$31355.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$167501$lut$aiger167500$31398.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$167501$lut$aiger167500$31414.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$167501$lut$aiger167500$31440.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$167501$lut$aiger167500$31461.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$167501$lut$aiger167500$31469.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$167501$lut$aiger167500$31517.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$167501$lut$aiger167500$31543.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$167501$lut$aiger167500$31572.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $abc$167501$lut$aiger167500$31572.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$167501$lut$aiger167500$31581.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $abc$167501$lut$aiger167500$31581.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$167501$lut$aiger167500$31597.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$167501$lut$aiger167500$31644.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$167501$lut$aiger167500$31666.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$167501$lut$aiger167500$31682.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$167501$lut$aiger167500$31739.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$167501$lut$aiger167500$31755.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$167501$lut$aiger167500$31763.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$167501$lut$aiger167500$31780.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$167501$lut$aiger167500$31799.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$167501$lut$aiger167500$31824.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$167501$lut$aiger167500$31840.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$167501$lut$aiger167500$31856.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$167501$lut$aiger167500$31862.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $abc$167501$lut$aiger167500$31862.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2) Optimizing lut $abc$167501$lut$aiger167500$31869.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$167501$lut$aiger167500$31885.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$167501$lut$aiger167500$31910.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$167501$lut$aiger167500$31917.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$167501$lut$aiger167500$31936.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$167501$lut$aiger167500$31952.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$167501$lut$aiger167500$31962.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$167501$lut$aiger167500$31984.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$167501$lut$aiger167500$31991.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$167501$lut$aiger167500$32000.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$167501$lut$aiger167500$32000.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$167501$lut$aiger167500$32054.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $abc$167501$lut$aiger167500$32054.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$167501$lut$aiger167500$32064.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $abc$167501$lut$aiger167500$32064.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$167501$lut$aiger167500$32187.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$167501$lut$aiger167500$32212.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$167501$lut$aiger167500$32228.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$167501$lut$aiger167500$32236.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$167501$lut$aiger167500$32256.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$167501$lut$aiger167500$32298.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$167501$lut$aiger167500$32364.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $abc$167501$lut$aiger167500$32364.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$167501$lut$aiger167500$32374.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $abc$167501$lut$aiger167500$32374.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$167501$lut$flatten\Core.$procmux$2654_Y[31].genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$167501$lut$aiger167500$32463.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $abc$167501$lut$aiger167500$32463.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$167501$lut$aiger167500$32491.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$167501$lut$aiger167500$32507.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$167501$lut$aiger167500$32538.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$167501$lut$aiger167500$32538.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $abc$167501$lut$aiger167500$32545.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$167501$lut$aiger167500$32561.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$167501$lut$aiger167500$32571.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$167501$lut$aiger167500$32578.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$167501$lut$aiger167500$32604.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$167501$lut$aiger167500$32611.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$167501$lut$aiger167500$32644.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$167501$lut$aiger167500$32660.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$167501$lut$aiger167500$32667.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$167501$lut$flatten\Core.$procmux$2660_Y[12].genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$167501$lut\Controller.data_memory_read_data[14].genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $abc$167501$lut$flatten\Core.$procmux$2660_Y[22].genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$167501$lut$flatten\Core.$procmux$2660_Y[6].genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$167501$lut$aiger167500$27304.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$167501$lut\Controller.data_memory_read_data[26].genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $abc$167501$lut$auto$opt_dff.cc:219:make_patterns_logic$3237.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$167501$lut$auto$opt_dff.cc:219:make_patterns_logic$3069.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$167501$lut$aiger167500$17642.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$167501$lut$flatten\Core.$procmux$2654_Y[30].genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$167501$lut$flatten\Controller.\Interpreter.$procmux$1480.Y[5].genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$167501$lut$aiger167500$30340.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$167501$lut$flatten\Core.$procmux$2654_Y[17].genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$167501$lut$aiger167500$26698.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$167501$lut$aiger167500$28714.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$167501$lut$flatten\Core.$procmux$2654_Y[6].genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$167501$lut$flatten\Core.$procmux$2654_Y[18].genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$167501$lut$aiger167500$18401.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$167501$lut$flatten\Core.$procmux$2654_Y[9].genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$167501$lut$aiger167500$16512.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$167501$lut$aiger167500$15962.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$167501$lut$aiger167500$17230.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$167501$lut$flatten\Core.$0\branch_flush[0:0].genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$167501$lut$aiger167500$11884.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$167501$lut$flatten\Core.$procmux$2654_Y[0].genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$167501$lut$flatten\Core.$procmux$2654_Y[10].genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$167690.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$167501$lut$flatten\Core.$procmux$2654_Y[12].genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$167501$lut$flatten\Core.$procmux$2654_Y[13].genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$167664.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$167652.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$167501$lut$flatten\Core.$procmux$2654_Y[16].genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$167501$lut$flatten\Core.$procmux$2654_Y[17].genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$167501$lut$flatten\Core.$procmux$2654_Y[18].genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$167612.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$167830.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$167602.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$167589.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$167501$lut$flatten\Core.$procmux$2654_Y[22].genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$167571.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$167501$lut$flatten\Core.$procmux$2654_Y[24].genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$167551.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$167501$lut$flatten\Core.$procmux$2654_Y[26].genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$167501$lut$flatten\Core.$procmux$2654_Y[27].genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$167501$lut$flatten\Core.$procmux$2654_Y[28].genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$167501$lut$flatten\Core.$procmux$2654_Y[29].genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$167501$lut$flatten\Core.$procmux$2654_Y[2].genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$167501$lut$flatten\Core.$procmux$2654_Y[30].genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$167501$lut$flatten\Core.$procmux$2654_Y[31].genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$167798.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$167780.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$167763.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$167501$lut$flatten\Core.$procmux$2654_Y[6].genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$167737.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$167727.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$167501$lut$flatten\Core.$procmux$2654_Y[9].genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$167501$lut$flatten\Core.$procmux$2660_Y[0].genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$167940.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$167939.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$167501$lut$flatten\Core.$procmux$2660_Y[12].genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$167937.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$167936.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$167501$lut$flatten\Core.$procmux$2660_Y[15].genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$167934.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$167501$lut$flatten\Core.$procmux$2660_Y[17].genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$167932.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$167501$lut$flatten\Core.$procmux$2660_Y[19].genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$167501$lut$flatten\Core.$procmux$2660_Y[1].genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$167930.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$167929.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$167501$lut$flatten\Core.$procmux$2660_Y[22].genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$167501$lut$flatten\Core.$procmux$2660_Y[23].genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$167501$lut$flatten\Core.$procmux$2660_Y[24].genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$167925.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$167924.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$167501$lut$flatten\Core.$procmux$2660_Y[27].genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$167922.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$167921.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$167948.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$167920.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$167919.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$167947.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$167501$lut$flatten\Core.$procmux$2660_Y[4].genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$167945.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$167501$lut$flatten\Core.$procmux$2660_Y[6].genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$167943.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$167942.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$167941.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$167501$lut$flatten\Core.$procmux$2654_Y[13].genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$167501$lut$flatten\Core.$procmux$2660_Y[19].genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$167501$lut$flatten\Core.$procmux$2654_Y[22].genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$167501$lut$flatten\Core.$procmux$2654_Y[28].genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$167501$lut$aiger167500$18359.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$167501$lut$flatten\Core.$procmux$2660_Y[15].genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$167501$lut$aiger167500$26104.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$167501$lut\Core.instruction_data[19].genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $abc$167501$lut\Controller.data_memory_read_data[0].genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$167501$lut\Controller.data_memory_read_data[12].genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$167501$lut\Controller.data_memory_read_data[13].genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$167501$lut\Controller.data_memory_read_data[14].genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$167501$lut\Controller.data_memory_read_data[15].genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$167501$lut\Controller.data_memory_read_data[16].genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$167501$lut\Controller.data_memory_read_data[18].genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$167501$lut\Controller.data_memory_read_data[1].genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$167501$lut\Controller.data_memory_read_data[20].genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$167501$lut\Controller.data_memory_read_data[21].genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$167501$lut\Controller.data_memory_read_data[22].genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$167501$lut$aiger167500$28426.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$167501$lut\Controller.data_memory_read_data[24].genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$167501$lut$aiger167500$29378.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$167501$lut\Controller.data_memory_read_data[26].genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$167501$lut\Controller.data_memory_read_data[28].genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$167501$lut\Controller.data_memory_read_data[29].genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$167501$lut\Controller.data_memory_read_data[6].genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$167501$lut\Controller.data_memory_read_data[8].genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$167501$lut\Controller.data_memory_read_data[22].genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $abc$167501$lut$aiger167500$22412.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$167501$lut\Core.instruction_data[11].genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$167501$lut$flatten\Core.$procmux$2654_Y[12].genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$167501$lut$aiger167500$24130.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$167501$lut$aiger167500$24773.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$167501$lut\Core.instruction_data[16].genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$167501$lut$flatten\Core.$procmux$2660_Y[17].genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$167501$lut\Core.instruction_data[19].genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$167501$lut$flatten\Core.$procmux$2660_Y[1].genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$167501$lut\Core.instruction_data[20].genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$167501$lut\Core.instruction_data[22].genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$167501$lut$flatten\Core.$procmux$2660_Y[23].genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$167501$lut$flatten\Core.$procmux$2654_Y[26].genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$167501$lut$flatten\Core.$procmux$2660_Y[27].genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$167501$lut$aiger167500$31227.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$167501$lut\Core.instruction_data[2].genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$167501$lut\Core.instruction_data[30].genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$167501$lut\Core.instruction_data[3].genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$167501$lut\Core.instruction_data[4].genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$167501$lut\Core.instruction_data[6].genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$167501$lut\Core.instruction_data[7].genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$167501$lut$aiger167500$22006.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$167501$lut\Core.zero.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$167823.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$167507.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$167508.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$167703.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$167515.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$167523.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$167532.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$167540.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$167547.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$167551.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$167558.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$167563.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$167563.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$167571.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$167583.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$167579.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$167579.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$167582.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$167583.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$167586.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$167589.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$167818.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$167594.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$167604.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$167602.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$167604.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$167609.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$167612.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$167619.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$167618.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$167628.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$167619.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$167620.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$167624.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$167628.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$167631.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$167636.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$167643.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$167643.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$167647.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$167647.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$167652.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$167662.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$167662.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$167664.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$167671.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$167670.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$167671.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$167676.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$167676.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$167683.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$167687.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$167690.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$167694.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$167698.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$167700.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$167703.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$167704.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$167707.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$167710.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$167718.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$167716.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$167718.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$167723.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$167724.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$167727.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$167731.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$167731.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$167734.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$167737.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$167748.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$167751.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$167751.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$167752.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$167754.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$167754.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$167760.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$167763.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$167767.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$167771.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$167771.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$167765.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$167780.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$167536.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$167812.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$167821.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$167794.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$167795.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$167798.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$167804.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$167843.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$167790.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$167815.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$167817.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$167821.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$167594.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$167823.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$167830.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$167898.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$167501$lut$aiger167500$14069.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$167501$lut$aiger167500$13240.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$167889.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$167898.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$167501$lut$flatten\Core.$procmux$2629.S.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$167919.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$167920.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$167921.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$167922.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$167923.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$167924.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$167925.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$167926.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$167927.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$167928.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$167929.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$167930.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$167931.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$167932.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$167933.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$167934.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$167935.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$167936.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$167937.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$167938.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$167939.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$167940.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$167941.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$167942.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$167943.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$167944.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$167945.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$167946.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$167947.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$167948.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$167949.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$167950.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$167694.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Removed 0 unused cells and 18016 unused wires. 18.45. Executing AUTONAME pass. Renamed 649419 objects in module processorci_top (223 iterations). <suppressed ~19762 debug messages> 18.46. Executing HIERARCHY pass (managing design hierarchy). 18.46.1. Analyzing design hierarchy.. Top module: \processorci_top 18.46.2. Analyzing design hierarchy.. Top module: \processorci_top Removed 0 unused modules. 18.47. Printing statistics. === processorci_top === Number of wires: 8118 Number of wire bits: 26315 Number of public wires: 8118 Number of public wire bits: 26315 Number of ports: 10 Number of port bits: 10 Number of memories: 0 Number of memory bits: 0 Number of processes: 0 Number of cells: 13002 $scopeinfo 19 CCU2C 285 L6MUX21 156 LUT4 7810 PFUMX 1356 TRELLIS_DPR16X4 1028 TRELLIS_FF 2348 18.48. Executing CHECK pass (checking for obvious problems). Checking module processorci_top... Found and reported 0 problems. 18.49. Executing JSON backend. Warnings: 67 unique messages, 67 total End of script. Logfile hash: 666ad750cd, CPU: user 13.24s system 0.14s, MEM: 297.33 MB peak Yosys 0.45+139 (git sha1 4d581a97d, clang++ 14.0.0-1ubuntu1.1 -fPIC -O3) Time spent: 27% 1x abc9_exe (5 sec), 12% 11x techmap (2 sec), ... /eda/oss-cad-suite/bin/nextpnr-ecp5 --json colorlight_i9.json --write colorlight_i9_pnr.json --45k \ --lpf /eda/processor-ci/constraints/colorlight_i9.lpf --textcfg colorlight_i9.config --package CABGA381 \ --speed 6 --lpf-allow-unconstrained --ignore-loops /eda/oss-cad-suite/bin/ecppack --compress --input colorlight_i9.config --bit colorlight_i9.bit [Pipeline] } [Pipeline] // dir [Pipeline] } [Pipeline] // stage [Pipeline] stage [Pipeline] { (Flash colorlight_i9) [Pipeline] dir Running in /var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5 [Pipeline] { [Pipeline] echo Flashing FPGA colorlight_i9. [Pipeline] sh + python3 /eda/processor-ci/main.py -c /eda/processor-ci/config.json -p Grande-Risco-5 -b colorlight_i9 -l Final configuration file generated at /var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/build_colorlight_i9.tcl Error executing Makefile. JTAG init failed with: Couldn't open device. Check permissions for 2-1.5:1.3 make: *** [/eda/processor-ci/makefiles/colorlight_i9.mk:18: load] Error 1 Traceback (most recent call last): File "/eda/processor-ci/main.py", line 135, in <module> main( File "/eda/processor-ci/main.py", line 80, in main flash(board_name, toolchain_path) File "/eda/processor-ci/core/fpga.py", line 254, in flash raise subprocess.CalledProcessError(process.returncode, 'make') subprocess.CalledProcessError: Command 'make' returned non-zero exit status 2. [Pipeline] } [Pipeline] // dir [Pipeline] } [Pipeline] // stage [Pipeline] stage [Pipeline] { (Test colorlight_i9) Stage "Test colorlight_i9" skipped due to earlier failure(s) [Pipeline] getContext [Pipeline] } [Pipeline] // stage [Pipeline] } Lock released on resource [Resource: colorlight_i9] [Pipeline] // lock [Pipeline] } [Pipeline] // stage [Pipeline] } Failed in branch colorlight_i9 Final configuration file generated at /var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/build_digilent_nexys4_ddr.tcl Makefile executed successfully. Makefile output: Building the Design... /eda/vivado/Vivado/2023.2/bin/vivado -mode batch -nolog -nojournal -source /var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/build_digilent_nexys4_ddr.tcl -tclargs "ID=0x6a6a6a6a" "CLOCK_FREQ=50000000" "MEMORY_SIZE=4096" ****** Vivado v2023.2 (64-bit) **** SW Build 4029153 on Fri Oct 13 20:13:54 MDT 2023 **** IP Build 4028589 on Sat Oct 14 00:45:43 MDT 2023 **** SharedData Build 4025554 on Tue Oct 10 17:18:54 MDT 2023 ** Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. ** Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved. source /var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/build_digilent_nexys4_ddr.tcl # read_verilog /eda/processor-ci/rtl/Grande-Risco-5.v read_verilog: Time (s): cpu = 00:00:08 ; elapsed = 00:00:08 . Memory (MB): peak = 1281.566 ; gain = 12.898 ; free physical = 1454 ; free virtual = 26831 # read_verilog /var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/src/core/alu.v # read_verilog /var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/src/core/alu_control.v # read_verilog /var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/src/core/core.v # read_verilog /var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/src/core/forwarding_unit.v # read_verilog /var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/src/core/immediate_generator.v # read_verilog /var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/src/core/mux.v # read_verilog /var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/src/core/registers.v # set ID 0x6a6a6a6a # set CLOCK_FREQ 50000000 # read_verilog /eda/processor-ci-controller/modules/uart.v # read_verilog /eda/processor-ci-controller/modules/UART/rtl/uart_rx.v # read_verilog /eda/processor-ci-controller/modules/UART/rtl/uart_tx.v # read_verilog /eda/processor-ci-controller/src/fifo.v # read_verilog /eda/processor-ci-controller/src/reset.v # read_verilog /eda/processor-ci-controller/src/clk_divider.v # read_verilog /eda/processor-ci-controller/src/memory.v # read_verilog /eda/processor-ci-controller/src/interpreter.v # read_verilog /eda/processor-ci-controller/src/controller.v # set ID [lindex $argv 0] # set CLOCK_FREQ [lindex $argv 1] # set MEMORY_SIZE [lindex $argv 2] # set HIGH_CLK 1 # read_xdc "/eda/processor-ci/constraints/digilent_nexys4_ddr.xdc" # set_property PROCESSING_ORDER EARLY [get_files /eda/processor-ci/constraints/digilent_nexys4_ddr.xdc] # synth_design -top "processorci_top" -part "xc7a100tcsg324-1" -verilog_define $ID -verilog_define $CLOCK_FREQ -verilog_define $MEMORY_SIZE \ # -verilog_define $HIGH_CLK Command: synth_design -top processorci_top -part xc7a100tcsg324-1 -verilog_define ID=0x6a6a6a6a -verilog_define CLOCK_FREQ=50000000 -verilog_define MEMORY_SIZE=4096 -verilog_define 1 Starting synth_design Attempting to get a license for feature 'Synthesis' and/or device 'xc7a100t' INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7a100t' INFO: [Device 21-403] Loading part xc7a100tcsg324-1 INFO: [Synth 8-7079] Multithreading enabled for synth_design using a maximum of 4 processes. INFO: [Synth 8-7078] Launching helper process for spawning children vivado processes INFO: [Synth 8-7075] Helper process launched with PID 239890 --------------------------------------------------------------------------------- Starting RTL Elaboration : Time (s): cpu = 00:00:05 ; elapsed = 00:00:05 . Memory (MB): peak = 2034.141 ; gain = 405.598 ; free physical = 335 ; free virtual = 25713 --------------------------------------------------------------------------------- CRITICAL WARNING: [Synth 8-9339] data object 'reset_o' is already declared [/eda/processor-ci/rtl/Grande-Risco-5.v:144] INFO: [Synth 8-6826] previous declaration of 'reset_o' is from here [/eda/processor-ci/rtl/Grande-Risco-5.v:29] CRITICAL WARNING: [Synth 8-11152] second declaration of 'reset_o' is ignored [/eda/processor-ci/rtl/Grande-Risco-5.v:144] WARNING: [Synth 8-6901] identifier 'PAYLOAD_BITS' is used before its declaration [/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:16] WARNING: [Synth 8-6901] identifier 'PAYLOAD_BITS' is used before its declaration [/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:16] WARNING: [Synth 8-11065] parameter 'INIT' becomes localparam in 'ResetBootSystem' with formal parameter declaration list [/eda/processor-ci-controller/src/reset.v:15] WARNING: [Synth 8-11065] parameter 'RESET_COUNTER' becomes localparam in 'ResetBootSystem' with formal parameter declaration list [/eda/processor-ci-controller/src/reset.v:16] WARNING: [Synth 8-11065] parameter 'IDLE' becomes localparam in 'ResetBootSystem' with formal parameter declaration list [/eda/processor-ci-controller/src/reset.v:17] WARNING: [Synth 8-6901] identifier 'bus_mode' is used before its declaration [/eda/processor-ci-controller/src/controller.v:84] WARNING: [Synth 8-6901] identifier 'memory_page_number' is used before its declaration [/eda/processor-ci-controller/src/controller.v:85] INFO: [Synth 8-6157] synthesizing module 'processorci_top' [/eda/processor-ci/rtl/Grande-Risco-5.v:1] INFO: [Synth 8-6157] synthesizing module 'Controller' [/eda/processor-ci-controller/src/controller.v:1] Parameter CLK_FREQ bound to: 50000000 - type: integer Parameter BIT_RATE bound to: 115200 - type: integer Parameter PAYLOAD_BITS bound to: 8 - type: integer Parameter BUFFER_SIZE bound to: 8 - type: integer Parameter PULSE_CONTROL_BITS bound to: 32 - type: integer Parameter BUS_WIDTH bound to: 32 - type: integer Parameter WORD_SIZE_BY bound to: 4 - type: integer Parameter ID bound to: 0 - type: integer Parameter RESET_CLK_CYCLES bound to: 20 - type: integer Parameter MEMORY_FILE bound to: (null) - type: string Parameter MEMORY_SIZE bound to: 4096 - type: integer INFO: [Synth 8-6157] synthesizing module 'ClkDivider' [/eda/processor-ci-controller/src/clk_divider.v:1] Parameter COUNTER_BITS bound to: 32 - type: integer Parameter PULSE_CONTROL_BITS bound to: 32 - type: integer INFO: [Synth 8-6155] done synthesizing module 'ClkDivider' (0#1) [/eda/processor-ci-controller/src/clk_divider.v:1] INFO: [Synth 8-6157] synthesizing module 'Interpreter' [/eda/processor-ci-controller/src/interpreter.v:1] Parameter CLK_FREQ bound to: 50000000 - type: integer Parameter PULSE_CONTROL_BITS bound to: 32 - type: integer Parameter BUS_WIDTH bound to: 32 - type: integer Parameter ID bound to: 0 - type: integer Parameter RESET_CLK_CYCLES bound to: 20 - type: integer INFO: [Synth 8-6155] done synthesizing module 'Interpreter' (0#1) [/eda/processor-ci-controller/src/interpreter.v:1] INFO: [Synth 8-6157] synthesizing module 'UART' [/eda/processor-ci-controller/modules/uart.v:1] Parameter CLK_FREQ bound to: 50000000 - type: integer Parameter BIT_RATE bound to: 115200 - type: integer Parameter PAYLOAD_BITS bound to: 8 - type: integer Parameter BUFFER_SIZE bound to: 8 - type: integer Parameter WORD_SIZE_BY bound to: 4 - type: integer INFO: [Synth 8-226] default block is never used [/eda/processor-ci-controller/modules/uart.v:213] INFO: [Synth 8-6157] synthesizing module 'FIFO' [/eda/processor-ci-controller/src/fifo.v:1] Parameter DEPTH bound to: 8 - type: integer Parameter WIDTH bound to: 8 - type: integer INFO: [Synth 8-6155] done synthesizing module 'FIFO' (0#1) [/eda/processor-ci-controller/src/fifo.v:1] INFO: [Synth 8-6157] synthesizing module 'uart_rx' [/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:9] Parameter BIT_RATE bound to: 115200 - type: integer Parameter CLK_HZ bound to: 50000000 - type: integer Parameter PAYLOAD_BITS bound to: 8 - type: integer INFO: [Synth 8-6155] done synthesizing module 'uart_rx' (0#1) [/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:9] INFO: [Synth 8-6157] synthesizing module 'uart_tx' [/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:10] Parameter BIT_RATE bound to: 115200 - type: integer Parameter CLK_HZ bound to: 50000000 - type: integer Parameter PAYLOAD_BITS bound to: 8 - type: integer INFO: [Synth 8-6155] done synthesizing module 'uart_tx' (0#1) [/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:10] INFO: [Synth 8-6155] done synthesizing module 'UART' (0#1) [/eda/processor-ci-controller/modules/uart.v:1] INFO: [Synth 8-6157] synthesizing module 'Memory' [/eda/processor-ci-controller/src/memory.v:1] Parameter MEMORY_FILE bound to: (null) - type: string Parameter MEMORY_SIZE bound to: 4096 - type: integer INFO: [Synth 8-6155] done synthesizing module 'Memory' (0#1) [/eda/processor-ci-controller/src/memory.v:1] WARNING: [Synth 8-7071] port 'read_sync' of module 'Memory' is unconnected for instance 'Data_Memory' [/eda/processor-ci-controller/src/controller.v:268] WARNING: [Synth 8-7071] port 'sync_write_response' of module 'Memory' is unconnected for instance 'Data_Memory' [/eda/processor-ci-controller/src/controller.v:268] WARNING: [Synth 8-7071] port 'sync_read_response' of module 'Memory' is unconnected for instance 'Data_Memory' [/eda/processor-ci-controller/src/controller.v:268] WARNING: [Synth 8-7023] instance 'Data_Memory' of module 'Memory' has 11 connections declared, but only 8 given [/eda/processor-ci-controller/src/controller.v:268] INFO: [Synth 8-6155] done synthesizing module 'Controller' (0#1) [/eda/processor-ci-controller/src/controller.v:1] WARNING: [Synth 8-7071] port 'core_read_data_memory_sync' of module 'Controller' is unconnected for instance 'Controller' [/eda/processor-ci/rtl/Grande-Risco-5.v:47] WARNING: [Synth 8-7071] port 'core_memory_read_response_sync' of module 'Controller' is unconnected for instance 'Controller' [/eda/processor-ci/rtl/Grande-Risco-5.v:47] WARNING: [Synth 8-7071] port 'core_memory_write_response_sync' of module 'Controller' is unconnected for instance 'Controller' [/eda/processor-ci/rtl/Grande-Risco-5.v:47] WARNING: [Synth 8-7023] instance 'Controller' of module 'Controller' has 27 connections declared, but only 24 given [/eda/processor-ci/rtl/Grande-Risco-5.v:47] INFO: [Synth 8-6157] synthesizing module 'Grande_Risco5' [/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/src/core/core.v:1] INFO: [Synth 8-6157] synthesizing module 'Registers' [/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/src/core/registers.v:1] INFO: [Synth 8-6155] done synthesizing module 'Registers' (0#1) [/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/src/core/registers.v:1] INFO: [Synth 8-6157] synthesizing module 'ALU_Control' [/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/src/core/alu_control.v:1] INFO: [Synth 8-226] default block is never used [/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/src/core/alu_control.v:34] INFO: [Synth 8-155] case statement is not full and has no default [/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/src/core/alu_control.v:11] INFO: [Synth 8-6155] done synthesizing module 'ALU_Control' (0#1) [/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/src/core/alu_control.v:1] INFO: [Synth 8-6157] synthesizing module 'Alu' [/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/src/core/alu.v:1] INFO: [Synth 8-6155] done synthesizing module 'Alu' (0#1) [/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/src/core/alu.v:1] INFO: [Synth 8-6157] synthesizing module 'Immediate_Generator' [/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/src/core/immediate_generator.v:1] INFO: [Synth 8-6155] done synthesizing module 'Immediate_Generator' (0#1) [/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/src/core/immediate_generator.v:1] INFO: [Synth 8-6157] synthesizing module 'Forwarding_Unit' [/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/src/core/forwarding_unit.v:1] INFO: [Synth 8-6155] done synthesizing module 'Forwarding_Unit' (0#1) [/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/src/core/forwarding_unit.v:1] INFO: [Synth 8-6157] synthesizing module 'MUX' [/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/src/core/mux.v:1] INFO: [Synth 8-226] default block is never used [/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/src/core/mux.v:11] INFO: [Synth 8-6155] done synthesizing module 'MUX' (0#1) [/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/src/core/mux.v:1] WARNING: [Synth 8-7071] port 'D' of module 'MUX' is unconnected for instance 'ForwardAMUX' [/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/src/core/core.v:324] WARNING: [Synth 8-7023] instance 'ForwardAMUX' of module 'MUX' has 6 connections declared, but only 5 given [/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/src/core/core.v:324] WARNING: [Synth 8-7071] port 'D' of module 'MUX' is unconnected for instance 'ForwardBMUX' [/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/src/core/core.v:332] WARNING: [Synth 8-7023] instance 'ForwardBMUX' of module 'MUX' has 6 connections declared, but only 5 given [/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/src/core/core.v:332] INFO: [Synth 8-6155] done synthesizing module 'Grande_Risco5' (0#1) [/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/src/core/core.v:1] INFO: [Synth 8-6157] synthesizing module 'ResetBootSystem' [/eda/processor-ci-controller/src/reset.v:1] Parameter CYCLES bound to: 20 - type: integer INFO: [Synth 8-6155] done synthesizing module 'ResetBootSystem' (0#1) [/eda/processor-ci-controller/src/reset.v:1] WARNING: [Synth 8-7071] port 'start' of module 'ResetBootSystem' is unconnected for instance 'ResetBootSystem' [/eda/processor-ci/rtl/Grande-Risco-5.v:148] WARNING: [Synth 8-7071] port 'resetn_o' of module 'ResetBootSystem' is unconnected for instance 'ResetBootSystem' [/eda/processor-ci/rtl/Grande-Risco-5.v:148] WARNING: [Synth 8-7023] instance 'ResetBootSystem' of module 'ResetBootSystem' has 4 connections declared, but only 2 given [/eda/processor-ci/rtl/Grande-Risco-5.v:148] INFO: [Synth 8-6155] done synthesizing module 'processorci_top' (0#1) [/eda/processor-ci/rtl/Grande-Risco-5.v:1] WARNING: [Synth 8-3848] Net intr in module/entity Controller does not have driver. [/eda/processor-ci-controller/src/controller.v:25] WARNING: [Synth 8-3848] Net miso in module/entity processorci_top does not have driver. [/eda/processor-ci/rtl/Grande-Risco-5.v:21] WARNING: [Synth 8-7129] Port func7[6] in module ALU_Control is either unconnected or has no load WARNING: [Synth 8-7129] Port func7[4] in module ALU_Control is either unconnected or has no load WARNING: [Synth 8-7129] Port func7[3] in module ALU_Control is either unconnected or has no load WARNING: [Synth 8-7129] Port func7[2] in module ALU_Control is either unconnected or has no load WARNING: [Synth 8-7129] Port func7[1] in module ALU_Control is either unconnected or has no load WARNING: [Synth 8-7129] Port func7[0] in module ALU_Control is either unconnected or has no load WARNING: [Synth 8-7129] Port reset in module Memory is either unconnected or has no load WARNING: [Synth 8-7129] Port address[31] in module Memory is either unconnected or has no load WARNING: [Synth 8-7129] Port address[30] in module Memory is either unconnected or has no load WARNING: [Synth 8-7129] Port address[29] in module Memory is either unconnected or has no load WARNING: [Synth 8-7129] Port address[28] in module Memory is either unconnected or has no load WARNING: [Synth 8-7129] Port address[27] in module Memory is either unconnected or has no load WARNING: [Synth 8-7129] Port address[26] in module Memory is either unconnected or has no load WARNING: [Synth 8-7129] Port address[25] in module Memory is either unconnected or has no load WARNING: [Synth 8-7129] Port address[24] in module Memory is either unconnected or has no load WARNING: [Synth 8-7129] Port address[23] in module Memory is either unconnected or has no load WARNING: [Synth 8-7129] Port address[22] in module Memory is either unconnected or has no load WARNING: [Synth 8-7129] Port address[21] in module Memory is either unconnected or has no load WARNING: [Synth 8-7129] Port address[20] in module Memory is either unconnected or has no load WARNING: [Synth 8-7129] Port address[19] in module Memory is either unconnected or has no load WARNING: [Synth 8-7129] Port address[18] in module Memory is either unconnected or has no load WARNING: [Synth 8-7129] Port address[17] in module Memory is either unconnected or has no load WARNING: [Synth 8-7129] Port address[16] in module Memory is either unconnected or has no load WARNING: [Synth 8-7129] Port address[15] in module Memory is either unconnected or has no load WARNING: [Synth 8-7129] Port address[14] in module Memory is either unconnected or has no load WARNING: [Synth 8-7129] Port address[13] in module Memory is either unconnected or has no load WARNING: [Synth 8-7129] Port address[12] in module Memory is either unconnected or has no load WARNING: [Synth 8-7129] Port address[1] in module Memory is either unconnected or has no load WARNING: [Synth 8-7129] Port address[0] in module Memory is either unconnected or has no load WARNING: [Synth 8-7129] Port communication_tx_empty in module Interpreter is either unconnected or has no load WARNING: [Synth 8-7129] Port memory_response in module Interpreter is either unconnected or has no load WARNING: [Synth 8-7129] Port intr in module Controller is either unconnected or has no load WARNING: [Synth 8-7129] Port sck in module Controller is either unconnected or has no load WARNING: [Synth 8-7129] Port cs in module Controller is either unconnected or has no load WARNING: [Synth 8-7129] Port mosi in module Controller is either unconnected or has no load WARNING: [Synth 8-7129] Port miso in module Controller is either unconnected or has no load WARNING: [Synth 8-7129] Port rw in module Controller is either unconnected or has no load WARNING: [Synth 8-7129] Port reset in module processorci_top is either unconnected or has no load --------------------------------------------------------------------------------- Finished RTL Elaboration : Time (s): cpu = 00:00:07 ; elapsed = 00:00:07 . Memory (MB): peak = 2132.109 ; gain = 503.566 ; free physical = 217 ; free virtual = 25596 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Handling Custom Attributes --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Handling Custom Attributes : Time (s): cpu = 00:00:07 ; elapsed = 00:00:07 . Memory (MB): peak = 2149.922 ; gain = 521.379 ; free physical = 214 ; free virtual = 25593 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished RTL Optimization Phase 1 : Time (s): cpu = 00:00:07 ; elapsed = 00:00:07 . Memory (MB): peak = 2149.922 ; gain = 521.379 ; free physical = 214 ; free virtual = 25593 --------------------------------------------------------------------------------- Netlist sorting complete. Time (s): cpu = 00:00:00.03 ; elapsed = 00:00:00.03 . Memory (MB): peak = 2149.922 ; gain = 0.000 ; free physical = 214 ; free virtual = 25593 INFO: [Project 1-570] Preparing netlist for logic optimization Processing XDC Constraints Initializing timing engine Parsing XDC File [/eda/processor-ci/constraints/digilent_nexys4_ddr.xdc] Finished Parsing XDC File [/eda/processor-ci/constraints/digilent_nexys4_ddr.xdc] INFO: [Project 1-236] Implementation specific constraints were found while reading constraint file [/eda/processor-ci/constraints/digilent_nexys4_ddr.xdc]. These constraints will be ignored for synthesis but will be used in implementation. Impacted constraints are listed in the file [.Xil/processorci_top_propImpl.xdc]. Resolution: To avoid this warning, move constraints listed in [.Xil/processorci_top_propImpl.xdc] to another XDC file and exclude this new file from synthesis with the used_in_synthesis property (File Properties dialog in GUI) and re-run elaboration/synthesis. Completed Processing XDC Constraints Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2296.672 ; gain = 0.000 ; free physical = 199 ; free virtual = 25567 INFO: [Project 1-111] Unisim Transformation Summary: No Unisim elements were transformed. Constraint Validation Runtime : Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 2296.707 ; gain = 0.000 ; free physical = 198 ; free virtual = 25567 --------------------------------------------------------------------------------- Finished Constraint Validation : Time (s): cpu = 00:00:15 ; elapsed = 00:00:15 . Memory (MB): peak = 2296.707 ; gain = 668.164 ; free physical = 218 ; free virtual = 25564 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Loading Part and Timing Information --------------------------------------------------------------------------------- Loading part: xc7a100tcsg324-1 --------------------------------------------------------------------------------- Finished Loading Part and Timing Information : Time (s): cpu = 00:00:15 ; elapsed = 00:00:15 . Memory (MB): peak = 2296.707 ; gain = 668.164 ; free physical = 218 ; free virtual = 25564 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Applying 'set_property' XDC Constraints --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished applying 'set_property' XDC Constraints : Time (s): cpu = 00:00:15 ; elapsed = 00:00:15 . Memory (MB): peak = 2296.707 ; gain = 668.164 ; free physical = 218 ; free virtual = 25564 --------------------------------------------------------------------------------- INFO: [Synth 8-802] inferred FSM for state register 'fsm_state_reg' in module 'uart_rx' INFO: [Synth 8-802] inferred FSM for state register 'fsm_state_reg' in module 'uart_tx' INFO: [Synth 8-802] inferred FSM for state register 'state_read_reg' in module 'UART' INFO: [Synth 8-802] inferred FSM for state register 'state_write_reg' in module 'UART' INFO: [Synth 8-802] inferred FSM for state register 'tx_fifo_read_state_reg' in module 'UART' INFO: [Synth 8-802] inferred FSM for state register 'state_reg' in module 'ResetBootSystem' --------------------------------------------------------------------------------------------------- State | New Encoding | Previous Encoding --------------------------------------------------------------------------------------------------- FSM_IDLE | 00 | 000 FSM_START | 11 | 001 FSM_RECV | 10 | 010 FSM_STOP | 01 | 011 --------------------------------------------------------------------------------------------------- INFO: [Synth 8-3354] encoded FSM with state register 'fsm_state_reg' using encoding 'sequential' in module 'uart_rx' --------------------------------------------------------------------------------------------------- State | New Encoding | Previous Encoding --------------------------------------------------------------------------------------------------- FSM_IDLE | 00 | 000 FSM_START | 11 | 001 FSM_SEND | 10 | 010 FSM_STOP | 01 | 011 --------------------------------------------------------------------------------------------------- INFO: [Synth 8-3354] encoded FSM with state register 'fsm_state_reg' using encoding 'sequential' in module 'uart_tx' --------------------------------------------------------------------------------------------------- State | New Encoding | Previous Encoding --------------------------------------------------------------------------------------------------- IDLE | 000 | 0000 READ | 001 | 0001 COPY_READ_BUFFER | 010 | 0100 WB | 011 | 0010 FINISH | 100 | 0011 --------------------------------------------------------------------------------------------------- INFO: [Synth 8-3354] encoded FSM with state register 'state_read_reg' using encoding 'sequential' in module 'UART' --------------------------------------------------------------------------------------------------- State | New Encoding | Previous Encoding --------------------------------------------------------------------------------------------------- IDLE | 000 | 0000 COPY_WRITE_BUFFER | 001 | 0100 WRITE | 010 | 0001 WB | 011 | 0010 FINISH | 100 | 0011 --------------------------------------------------------------------------------------------------- INFO: [Synth 8-3354] encoded FSM with state register 'state_write_reg' using encoding 'sequential' in module 'UART' --------------------------------------------------------------------------------------------------- State | New Encoding | Previous Encoding --------------------------------------------------------------------------------------------------- iSTATE | 0001 | 00 iSTATE0 | 0010 | 01 iSTATE1 | 0100 | 10 iSTATE2 | 1000 | 11 --------------------------------------------------------------------------------------------------- INFO: [Synth 8-3354] encoded FSM with state register 'tx_fifo_read_state_reg' using encoding 'one-hot' in module 'UART' --------------------------------------------------------------------------------------------------- State | New Encoding | Previous Encoding --------------------------------------------------------------------------------------------------- RESET_COUNTER | 00 | 01 IDLE | 01 | 10 INIT | 10 | 00 --------------------------------------------------------------------------------------------------- INFO: [Synth 8-3354] encoded FSM with state register 'state_reg' using encoding 'sequential' in module 'ResetBootSystem' --------------------------------------------------------------------------------- Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:16 ; elapsed = 00:00:17 . Memory (MB): peak = 2296.707 ; gain = 668.164 ; free physical = 220 ; free virtual = 25562 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start RTL Component Statistics --------------------------------------------------------------------------------- Detailed RTL Component Info : +---Adders : 2 Input 64 Bit Adders := 2 2 Input 32 Bit Adders := 12 3 Input 32 Bit Adders := 1 2 Input 24 Bit Adders := 2 2 Input 10 Bit Adders := 2 2 Input 8 Bit Adders := 1 2 Input 6 Bit Adders := 4 2 Input 5 Bit Adders := 1 2 Input 4 Bit Adders := 2 2 Input 3 Bit Adders := 2 +---XORs : 2 Input 32 Bit XORs := 1 +---Registers : 64 Bit Registers := 2 32 Bit Registers := 68 24 Bit Registers := 5 10 Bit Registers := 2 8 Bit Registers := 11 6 Bit Registers := 1 4 Bit Registers := 3 3 Bit Registers := 2 1 Bit Registers := 39 +---RAMs : 32K Bit (1024 X 32 bit) RAMs := 2 64 Bit (8 X 8 bit) RAMs := 2 +---Muxes : 4 Input 64 Bit Muxes := 1 2 Input 64 Bit Muxes := 1 48 Input 64 Bit Muxes := 2 2 Input 32 Bit Muxes := 20 5 Input 32 Bit Muxes := 1 8 Input 32 Bit Muxes := 1 4 Input 32 Bit Muxes := 2 3 Input 32 Bit Muxes := 2 48 Input 24 Bit Muxes := 1 48 Input 8 Bit Muxes := 2 2 Input 8 Bit Muxes := 4 24 Input 7 Bit Muxes := 1 2 Input 7 Bit Muxes := 2 2 Input 6 Bit Muxes := 4 3 Input 6 Bit Muxes := 1 2 Input 5 Bit Muxes := 2 2 Input 4 Bit Muxes := 4 9 Input 4 Bit Muxes := 1 10 Input 4 Bit Muxes := 1 5 Input 3 Bit Muxes := 4 2 Input 3 Bit Muxes := 3 10 Input 3 Bit Muxes := 1 2 Input 2 Bit Muxes := 19 48 Input 2 Bit Muxes := 1 4 Input 2 Bit Muxes := 4 5 Input 2 Bit Muxes := 1 8 Input 2 Bit Muxes := 1 6 Input 2 Bit Muxes := 1 3 Input 2 Bit Muxes := 1 2 Input 1 Bit Muxes := 94 48 Input 1 Bit Muxes := 22 3 Input 1 Bit Muxes := 7 4 Input 1 Bit Muxes := 3 5 Input 1 Bit Muxes := 11 6 Input 1 Bit Muxes := 1 --------------------------------------------------------------------------------- Finished RTL Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Part Resource Summary --------------------------------------------------------------------------------- Part Resources: DSPs: 240 (col length:80) BRAMs: 270 (col length: RAMB18 80 RAMB36 40) --------------------------------------------------------------------------------- Finished Part Resource Summary --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Cross Boundary and Area Optimization --------------------------------------------------------------------------------- WARNING: [Synth 8-7080] Parallel synthesis criteria is not met WARNING: [Synth 8-7129] Port reset in module Memory is either unconnected or has no load WARNING: [Synth 8-7129] Port address[31] in module Memory is either unconnected or has no load WARNING: [Synth 8-7129] Port address[30] in module Memory is either unconnected or has no load WARNING: [Synth 8-7129] Port address[29] in module Memory is either unconnected or has no load WARNING: [Synth 8-7129] Port address[28] in module Memory is either unconnected or has no load WARNING: [Synth 8-7129] Port address[27] in module Memory is either unconnected or has no load WARNING: [Synth 8-7129] Port address[26] in module Memory is either unconnected or has no load WARNING: [Synth 8-7129] Port address[25] in module Memory is either unconnected or has no load WARNING: [Synth 8-7129] Port address[24] in module Memory is either unconnected or has no load WARNING: [Synth 8-7129] Port address[23] in module Memory is either unconnected or has no load WARNING: [Synth 8-7129] Port address[22] in module Memory is either unconnected or has no load WARNING: [Synth 8-7129] Port address[21] in module Memory is either unconnected or has no load WARNING: [Synth 8-7129] Port address[20] in module Memory is either unconnected or has no load WARNING: [Synth 8-7129] Port address[19] in module Memory is either unconnected or has no load WARNING: [Synth 8-7129] Port address[18] in module Memory is either unconnected or has no load WARNING: [Synth 8-7129] Port address[17] in module Memory is either unconnected or has no load WARNING: [Synth 8-7129] Port address[16] in module Memory is either unconnected or has no load WARNING: [Synth 8-7129] Port address[15] in module Memory is either unconnected or has no load WARNING: [Synth 8-7129] Port address[14] in module Memory is either unconnected or has no load WARNING: [Synth 8-7129] Port address[13] in module Memory is either unconnected or has no load WARNING: [Synth 8-7129] Port address[12] in module Memory is either unconnected or has no load WARNING: [Synth 8-7129] Port address[1] in module Memory is either unconnected or has no load WARNING: [Synth 8-7129] Port address[0] in module Memory is either unconnected or has no load WARNING: [Synth 8-7129] Port communication_tx_empty in module Interpreter is either unconnected or has no load WARNING: [Synth 8-7129] Port memory_response in module Interpreter is either unconnected or has no load WARNING: [Synth 8-7129] Port intr in module Controller is either unconnected or has no load WARNING: [Synth 8-7129] Port sck in module Controller is either unconnected or has no load WARNING: [Synth 8-7129] Port cs in module Controller is either unconnected or has no load WARNING: [Synth 8-7129] Port mosi in module Controller is either unconnected or has no load WARNING: [Synth 8-7129] Port miso in module Controller is either unconnected or has no load WARNING: [Synth 8-7129] Port rw in module Controller is either unconnected or has no load WARNING: [Synth 8-7129] Port reset in module processorci_top is either unconnected or has no load --------------------------------------------------------------------------------- Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:01:30 ; elapsed = 00:01:31 . Memory (MB): peak = 2296.707 ; gain = 668.164 ; free physical = 355 ; free virtual = 25582 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start ROM, RAM, DSP, Shift Register and Retiming Reporting --------------------------------------------------------------------------------- ROM: Preliminary Mapping Report +------------+---------------------+---------------+----------------+ |Module Name | RTL Object | Depth x Width | Implemented As | +------------+---------------------+---------------+----------------+ |Interpreter | memory_mux_selector | 256x1 | LUT | |Interpreter | memory_mux_selector | 256x1 | LUT | +------------+---------------------+---------------+----------------+ Distributed RAM: Preliminary Mapping Report (see note below) +------------+-------------------------+-----------+----------------------+------------------+ |Module Name | RTL Object | Inference | Size (Depth x Width) | Primitives | +------------+-------------------------+-----------+----------------------+------------------+ |Controller | Uart/TX_FIFO/memory_reg | Implied | 8 x 8 | RAM32M x 2 | |Controller | Uart/RX_FIFO/memory_reg | Implied | 8 x 8 | RAM32M x 2 | |Controller | Memory/memory_reg | Implied | 1 K x 32 | RAM256X1S x 128 | |Controller | Data_Memory/memory_reg | Implied | 1 K x 32 | RAM256X1S x 128 | +------------+-------------------------+-----------+----------------------+------------------+ Note: The table above is a preliminary report that shows the Distributed RAMs at the current stage of the synthesis flow. Some Distributed RAMs may be reimplemented as non Distributed RAM primitives later in the synthesis flow. Multiple instantiated RAMs are reported only once. --------------------------------------------------------------------------------- Finished ROM, RAM, DSP, Shift Register and Retiming Reporting --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Applying XDC Timing Constraints --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Applying XDC Timing Constraints : Time (s): cpu = 00:01:35 ; elapsed = 00:01:35 . Memory (MB): peak = 2296.707 ; gain = 668.164 ; free physical = 351 ; free virtual = 25579 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Timing Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Timing Optimization : Time (s): cpu = 00:01:39 ; elapsed = 00:01:40 . Memory (MB): peak = 2296.707 ; gain = 668.164 ; free physical = 346 ; free virtual = 25573 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start ROM, RAM, DSP, Shift Register and Retiming Reporting --------------------------------------------------------------------------------- Distributed RAM: Final Mapping Report +------------+-------------------------+-----------+----------------------+------------------+ |Module Name | RTL Object | Inference | Size (Depth x Width) | Primitives | +------------+-------------------------+-----------+----------------------+------------------+ |Controller | Uart/TX_FIFO/memory_reg | Implied | 8 x 8 | RAM32M x 2 | |Controller | Uart/RX_FIFO/memory_reg | Implied | 8 x 8 | RAM32M x 2 | |Controller | Memory/memory_reg | Implied | 1 K x 32 | RAM256X1S x 128 | |Controller | Data_Memory/memory_reg | Implied | 1 K x 32 | RAM256X1S x 128 | +------------+-------------------------+-----------+----------------------+------------------+ --------------------------------------------------------------------------------- Finished ROM, RAM, DSP, Shift Register and Retiming Reporting --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Technology Mapping --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Technology Mapping : Time (s): cpu = 00:01:41 ; elapsed = 00:01:42 . Memory (MB): peak = 2296.707 ; gain = 668.164 ; free physical = 352 ; free virtual = 25579 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Final Netlist Cleanup --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Final Netlist Cleanup --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished IO Insertion : Time (s): cpu = 00:01:46 ; elapsed = 00:01:46 . Memory (MB): peak = 2296.707 ; gain = 668.164 ; free physical = 347 ; free virtual = 25575 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Instances --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Instances : Time (s): cpu = 00:01:46 ; elapsed = 00:01:46 . Memory (MB): peak = 2296.707 ; gain = 668.164 ; free physical = 347 ; free virtual = 25575 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Rebuilding User Hierarchy --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Rebuilding User Hierarchy : Time (s): cpu = 00:01:46 ; elapsed = 00:01:47 . Memory (MB): peak = 2296.707 ; gain = 668.164 ; free physical = 346 ; free virtual = 25574 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Ports --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Ports : Time (s): cpu = 00:01:46 ; elapsed = 00:01:47 . Memory (MB): peak = 2296.707 ; gain = 668.164 ; free physical = 346 ; free virtual = 25574 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Handling Custom Attributes --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Handling Custom Attributes : Time (s): cpu = 00:01:47 ; elapsed = 00:01:47 . Memory (MB): peak = 2296.707 ; gain = 668.164 ; free physical = 346 ; free virtual = 25574 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Nets --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Nets : Time (s): cpu = 00:01:47 ; elapsed = 00:01:47 . Memory (MB): peak = 2296.707 ; gain = 668.164 ; free physical = 346 ; free virtual = 25573 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Writing Synthesis Report --------------------------------------------------------------------------------- Report BlackBoxes: +-+--------------+----------+ | |BlackBox name |Instances | +-+--------------+----------+ +-+--------------+----------+ Report Cell Usage: +------+----------+------+ | |Cell |Count | +------+----------+------+ |1 |BUFG | 2| |2 |CARRY4 | 139| |3 |LUT1 | 36| |4 |LUT2 | 397| |5 |LUT3 | 477| |6 |LUT4 | 176| |7 |LUT5 | 418| |8 |LUT6 | 1273| |9 |MUXF7 | 197| |10 |RAM256X1S | 256| |11 |RAM32M | 2| |12 |RAM32X1D | 4| |13 |FDRE | 2325| |14 |FDSE | 21| |15 |IBUF | 2| |16 |OBUF | 1| |17 |OBUFT | 2| +------+----------+------+ --------------------------------------------------------------------------------- Finished Writing Synthesis Report : Time (s): cpu = 00:01:47 ; elapsed = 00:01:47 . Memory (MB): peak = 2296.707 ; gain = 668.164 ; free physical = 344 ; free virtual = 25572 --------------------------------------------------------------------------------- Synthesis finished with 0 errors, 0 critical warnings and 33 warnings. Synthesis Optimization Runtime : Time (s): cpu = 00:01:44 ; elapsed = 00:01:45 . Memory (MB): peak = 2296.707 ; gain = 521.379 ; free physical = 346 ; free virtual = 25573 Synthesis Optimization Complete : Time (s): cpu = 00:01:47 ; elapsed = 00:01:47 . Memory (MB): peak = 2296.707 ; gain = 668.164 ; free physical = 346 ; free virtual = 25573 INFO: [Project 1-571] Translating synthesized netlist Netlist sorting complete. Time (s): cpu = 00:00:00.03 ; elapsed = 00:00:00.03 . Memory (MB): peak = 2296.707 ; gain = 0.000 ; free physical = 622 ; free virtual = 25849 INFO: [Netlist 29-17] Analyzing 598 Unisim elements for replacement INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds INFO: [Project 1-570] Preparing netlist for logic optimization Parsing XDC File [/eda/processor-ci/constraints/digilent_nexys4_ddr.xdc] Finished Parsing XDC File [/eda/processor-ci/constraints/digilent_nexys4_ddr.xdc] INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2360.703 ; gain = 0.000 ; free physical = 621 ; free virtual = 25848 INFO: [Project 1-111] Unisim Transformation Summary: A total of 262 instances were transformed. RAM256X1S => RAM256X1S (MUXF7(x2), MUXF8, RAMS64E(x4)): 256 instances RAM32M => RAM32M (RAMD32(x6), RAMS32(x2)): 2 instances RAM32X1D => RAM32X1D (RAMD32(x2)): 4 instances Synth Design complete | Checksum: 1cddca49 INFO: [Common 17-83] Releasing license: Synthesis 66 Infos, 95 Warnings, 2 Critical Warnings and 0 Errors encountered. synth_design completed successfully synth_design: Time (s): cpu = 00:01:56 ; elapsed = 00:01:54 . Memory (MB): peak = 2360.738 ; gain = 1079.172 ; free physical = 619 ; free virtual = 25847 INFO: [Common 17-2834] synth_design peak Physical Memory [PSS] (MB): overall = 2056.221; main = 1770.378; forked = 428.161 INFO: [Common 17-2834] synth_design peak Virtual Memory [VSS] (MB): overall = 3246.992; main = 2360.707; forked = 982.332 # opt_design Command: opt_design Attempting to get a license for feature 'Implementation' and/or device 'xc7a100t' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7a100t' Running DRC as a precondition to command opt_design Starting DRC Task INFO: [DRC 23-27] Running DRC with 8 threads INFO: [Project 1-461] DRC finished with 0 Errors INFO: [Project 1-462] Please refer to the DRC report (report_drc) for more information. Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.71 . Memory (MB): peak = 2424.734 ; gain = 63.996 ; free physical = 622 ; free virtual = 25850 Starting Cache Timing Information Task INFO: [Timing 38-35] Done setting XDC timing constraints. Ending Cache Timing Information Task | Checksum: df61d546 Time (s): cpu = 00:00:03 ; elapsed = 00:00:02 . Memory (MB): peak = 2525.547 ; gain = 100.812 ; free physical = 581 ; free virtual = 25809 Starting Logic Optimization Task Phase 1 Initialization Phase 1.1 Core Generation And Design Setup Phase 1.1 Core Generation And Design Setup | Checksum: df61d546 Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 2772.453 ; gain = 0.000 ; free physical = 271 ; free virtual = 25442 Phase 1.2 Setup Constraints And Sort Netlist Phase 1.2 Setup Constraints And Sort Netlist | Checksum: df61d546 Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 2772.453 ; gain = 0.000 ; free physical = 270 ; free virtual = 25441 Phase 1 Initialization | Checksum: df61d546 Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 2772.453 ; gain = 0.000 ; free physical = 270 ; free virtual = 25441 Phase 2 Timer Update And Timing Data Collection Phase 2.1 Timer Update Phase 2.1 Timer Update | Checksum: df61d546 Time (s): cpu = 00:00:00.83 ; elapsed = 00:00:00.2 . Memory (MB): peak = 2772.453 ; gain = 0.000 ; free physical = 292 ; free virtual = 25457 Phase 2.2 Timing Data Collection Phase 2.2 Timing Data Collection | Checksum: df61d546 Time (s): cpu = 00:00:00.84 ; elapsed = 00:00:00.22 . Memory (MB): peak = 2772.453 ; gain = 0.000 ; free physical = 293 ; free virtual = 25458 Phase 2 Timer Update And Timing Data Collection | Checksum: df61d546 Time (s): cpu = 00:00:00.84 ; elapsed = 00:00:00.22 . Memory (MB): peak = 2772.453 ; gain = 0.000 ; free physical = 292 ; free virtual = 25458 Phase 3 Retarget INFO: [Opt 31-1566] Pulled 1 inverters resulting in an inversion of 70 pins INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). INFO: [Opt 31-49] Retargeted 0 cell(s). Phase 3 Retarget | Checksum: 2209afe2c Time (s): cpu = 00:00:00.99 ; elapsed = 00:00:00.33 . Memory (MB): peak = 2772.453 ; gain = 0.000 ; free physical = 283 ; free virtual = 25448 Retarget | Checksum: 2209afe2c INFO: [Opt 31-389] Phase Retarget created 0 cells and removed 1 cells Phase 4 Constant propagation INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). Phase 4 Constant propagation | Checksum: 239a9e7bb Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.38 . Memory (MB): peak = 2772.453 ; gain = 0.000 ; free physical = 284 ; free virtual = 25449 Constant propagation | Checksum: 239a9e7bb INFO: [Opt 31-389] Phase Constant propagation created 0 cells and removed 0 cells Phase 5 Sweep Phase 5 Sweep | Checksum: 1be66a90b Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.45 . Memory (MB): peak = 2772.453 ; gain = 0.000 ; free physical = 280 ; free virtual = 25446 Sweep | Checksum: 1be66a90b INFO: [Opt 31-389] Phase Sweep created 0 cells and removed 0 cells Phase 6 BUFG optimization Phase 6 BUFG optimization | Checksum: 1be66a90b Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.54 . Memory (MB): peak = 2804.469 ; gain = 32.016 ; free physical = 280 ; free virtual = 25445 BUFG optimization | Checksum: 1be66a90b INFO: [Opt 31-662] Phase BUFG optimization created 0 cells of which 0 are BUFGs and removed 0 cells. Phase 7 Shift Register Optimization INFO: [Opt 31-1064] SRL Remap converted 0 SRLs to 0 registers and converted 0 registers of register chains to 0 SRLs Phase 7 Shift Register Optimization | Checksum: 1be66a90b Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.54 . Memory (MB): peak = 2804.469 ; gain = 32.016 ; free physical = 280 ; free virtual = 25445 Shift Register Optimization | Checksum: 1be66a90b INFO: [Opt 31-389] Phase Shift Register Optimization created 0 cells and removed 0 cells Phase 8 Post Processing Netlist Phase 8 Post Processing Netlist | Checksum: 1be66a90b Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.57 . Memory (MB): peak = 2804.469 ; gain = 32.016 ; free physical = 280 ; free virtual = 25445 Post Processing Netlist | Checksum: 1be66a90b INFO: [Opt 31-389] Phase Post Processing Netlist created 0 cells and removed 0 cells Phase 9 Finalization Phase 9.1 Finalizing Design Cores and Updating Shapes Phase 9.1 Finalizing Design Cores and Updating Shapes | Checksum: 1d6904b8e Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.64 . Memory (MB): peak = 2804.469 ; gain = 32.016 ; free physical = 279 ; free virtual = 25445 Phase 9.2 Verifying Netlist Connectivity Starting Connectivity Check Task Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 2804.469 ; gain = 0.000 ; free physical = 278 ; free virtual = 25443 Phase 9.2 Verifying Netlist Connectivity | Checksum: 1d6904b8e Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.66 . Memory (MB): peak = 2804.469 ; gain = 32.016 ; free physical = 277 ; free virtual = 25443 Phase 9 Finalization | Checksum: 1d6904b8e Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.66 . Memory (MB): peak = 2804.469 ; gain = 32.016 ; free physical = 277 ; free virtual = 25443 Opt_design Change Summary ========================= ------------------------------------------------------------------------------------------------------------------------- | Phase | #Cells created | #Cells Removed | #Constrained objects preventing optimizations | ------------------------------------------------------------------------------------------------------------------------- | Retarget | 0 | 1 | 0 | | Constant propagation | 0 | 0 | 0 | | Sweep | 0 | 0 | 0 | | BUFG optimization | 0 | 0 | 0 | | Shift Register Optimization | 0 | 0 | 0 | | Post Processing Netlist | 0 | 0 | 0 | ------------------------------------------------------------------------------------------------------------------------- Ending Logic Optimization Task | Checksum: 1d6904b8e Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.66 . Memory (MB): peak = 2804.469 ; gain = 32.016 ; free physical = 277 ; free virtual = 25442 INFO: [Constraints 18-11670] Building netlist checker database with flags, 0x8 Done building netlist checker database: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.01 . Memory (MB): peak = 2804.469 ; gain = 0.000 ; free physical = 276 ; free virtual = 25441 Starting Power Optimization Task INFO: [Pwropt 34-132] Skipping clock gating for clocks with a period < 2.00 ns. Ending Power Optimization Task | Checksum: 1d6904b8e Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 2804.469 ; gain = 0.000 ; free physical = 279 ; free virtual = 25444 Starting Final Cleanup Task Ending Final Cleanup Task | Checksum: 1d6904b8e Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2804.469 ; gain = 0.000 ; free physical = 279 ; free virtual = 25444 Starting Netlist Obfuscation Task Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2804.469 ; gain = 0.000 ; free physical = 279 ; free virtual = 25444 Ending Netlist Obfuscation Task | Checksum: 1d6904b8e Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2804.469 ; gain = 0.000 ; free physical = 279 ; free virtual = 25444 INFO: [Common 17-83] Releasing license: Implementation 19 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered. opt_design completed successfully opt_design: Time (s): cpu = 00:00:08 ; elapsed = 00:00:06 . Memory (MB): peak = 2804.469 ; gain = 443.730 ; free physical = 279 ; free virtual = 25444 # place_design Command: place_design Attempting to get a license for feature 'Implementation' and/or device 'xc7a100t' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7a100t' INFO: [Common 17-83] Releasing license: Implementation INFO: [DRC 23-27] Running DRC with 8 threads INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Running DRC as a precondition to command place_design INFO: [DRC 23-27] Running DRC with 8 threads INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 8 CPUs Starting Placer Task Phase 1 Placer Initialization Phase 1.1 Placer Initialization Netlist Sorting Netlist sorting complete. Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00 . Memory (MB): peak = 2836.484 ; gain = 0.000 ; free physical = 397 ; free virtual = 25563 Phase 1.1 Placer Initialization Netlist Sorting | Checksum: 1471991d9 Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 2836.484 ; gain = 0.000 ; free physical = 397 ; free virtual = 25563 Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2836.484 ; gain = 0.000 ; free physical = 397 ; free virtual = 25563 Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device INFO: [Timing 38-35] Done setting XDC timing constraints. Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: 1247ef319 Time (s): cpu = 00:00:02 ; elapsed = 00:00:00.87 . Memory (MB): peak = 2836.484 ; gain = 0.000 ; free physical = 387 ; free virtual = 25565 Phase 1.3 Build Placer Netlist Model Phase 1.3 Build Placer Netlist Model | Checksum: 202858f90 Time (s): cpu = 00:00:06 ; elapsed = 00:00:03 . Memory (MB): peak = 2843.512 ; gain = 7.027 ; free physical = 846 ; free virtual = 26058 Phase 1.4 Constrain Clocks/Macros Phase 1.4 Constrain Clocks/Macros | Checksum: 202858f90 Time (s): cpu = 00:00:06 ; elapsed = 00:00:03 . Memory (MB): peak = 2843.512 ; gain = 7.027 ; free physical = 846 ; free virtual = 26058 Phase 1 Placer Initialization | Checksum: 202858f90 Time (s): cpu = 00:00:06 ; elapsed = 00:00:03 . Memory (MB): peak = 2843.512 ; gain = 7.027 ; free physical = 846 ; free virtual = 26058 Phase 2 Global Placement Phase 2.1 Floorplanning Phase 2.1 Floorplanning | Checksum: 1cca23f85 Time (s): cpu = 00:00:08 ; elapsed = 00:00:03 . Memory (MB): peak = 2843.512 ; gain = 7.027 ; free physical = 840 ; free virtual = 26052 Phase 2.2 Update Timing before SLR Path Opt Phase 2.2 Update Timing before SLR Path Opt | Checksum: 18c4f3a3b Time (s): cpu = 00:00:10 ; elapsed = 00:00:03 . Memory (MB): peak = 2843.512 ; gain = 7.027 ; free physical = 841 ; free virtual = 26053 Phase 2.3 Post-Processing in Floorplanning Phase 2.3 Post-Processing in Floorplanning | Checksum: 18c4f3a3b Time (s): cpu = 00:00:10 ; elapsed = 00:00:03 . Memory (MB): peak = 2843.512 ; gain = 7.027 ; free physical = 841 ; free virtual = 26053 Phase 2.4 Global Placement Core Phase 2.4.1 UpdateTiming Before Physical Synthesis Phase 2.4.1 UpdateTiming Before Physical Synthesis | Checksum: 12c674497 Time (s): cpu = 00:00:19 ; elapsed = 00:00:06 . Memory (MB): peak = 2843.512 ; gain = 7.027 ; free physical = 856 ; free virtual = 26068 Phase 2.4.2 Physical Synthesis In Placer INFO: [Physopt 32-1035] Found 0 LUTNM shape to break, 191 LUT instances to create LUTNM shape INFO: [Physopt 32-1044] Break lutnm for timing: one critical 0, two critical 0, total 0, new lutff created 0 INFO: [Physopt 32-1138] End 1 Pass. Optimized 92 nets or LUTs. Breaked 0 LUT, combined 92 existing LUTs and moved 0 existing LUT INFO: [Physopt 32-65] No nets found for high-fanout optimization. INFO: [Physopt 32-232] Optimized 0 net. Created 0 new instance. INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell INFO: [Physopt 32-456] No candidate cells for DSP register optimization found in the design. INFO: [Physopt 32-775] End 2 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell INFO: [Physopt 32-1123] No candidate cells found for Shift Register to Pipeline optimization INFO: [Physopt 32-775] End 2 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell INFO: [Physopt 32-1401] No candidate cells found for Shift Register optimization. INFO: [Physopt 32-677] No candidate cells for Shift Register optimization found in the design INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell INFO: [Physopt 32-526] No candidate cells for BRAM register optimization found in the design INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell INFO: [Physopt 32-846] No candidate cells for URAM register optimization found in the design INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell INFO: [Physopt 32-846] No candidate cells for URAM register optimization found in the design INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell INFO: [Physopt 32-949] No candidate nets found for dynamic/static region interface net replication INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2843.512 ; gain = 0.000 ; free physical = 1197 ; free virtual = 26409 Summary of Physical Synthesis Optimizations ============================================ ----------------------------------------------------------------------------------------------------------------------------------------------------------- | Optimization | Added Cells | Removed Cells | Optimized Cells/Nets | Dont Touch | Iterations | Elapsed | ----------------------------------------------------------------------------------------------------------------------------------------------------------- | LUT Combining | 0 | 92 | 92 | 0 | 1 | 00:00:00 | | Retime | 0 | 0 | 0 | 0 | 1 | 00:00:00 | | Very High Fanout | 0 | 0 | 0 | 0 | 1 | 00:00:00 | | DSP Register | 0 | 0 | 0 | 0 | 1 | 00:00:00 | | Shift Register to Pipeline | 0 | 0 | 0 | 0 | 1 | 00:00:00 | | Shift Register | 0 | 0 | 0 | 0 | 1 | 00:00:00 | | BRAM Register | 0 | 0 | 0 | 0 | 1 | 00:00:00 | | URAM Register | 0 | 0 | 0 | 0 | 1 | 00:00:00 | | Dynamic/Static Region Interface Net Replication | 0 | 0 | 0 | 0 | 1 | 00:00:00 | | Total | 0 | 92 | 92 | 0 | 9 | 00:00:01 | ----------------------------------------------------------------------------------------------------------------------------------------------------------- Phase 2.4.2 Physical Synthesis In Placer | Checksum: 1eb228742 Time (s): cpu = 00:00:22 ; elapsed = 00:00:07 . Memory (MB): peak = 2843.512 ; gain = 7.027 ; free physical = 1310 ; free virtual = 26522 Phase 2.4 Global Placement Core | Checksum: 1d5048f7a Time (s): cpu = 00:00:22 ; elapsed = 00:00:07 . Memory (MB): peak = 2843.512 ; gain = 7.027 ; free physical = 1309 ; free virtual = 26521 Phase 2 Global Placement | Checksum: 1d5048f7a Time (s): cpu = 00:00:22 ; elapsed = 00:00:07 . Memory (MB): peak = 2843.512 ; gain = 7.027 ; free physical = 1309 ; free virtual = 26521 Phase 3 Detail Placement Phase 3.1 Commit Multi Column Macros Phase 3.1 Commit Multi Column Macros | Checksum: 14ed257e5 Time (s): cpu = 00:00:24 ; elapsed = 00:00:08 . Memory (MB): peak = 2843.512 ; gain = 7.027 ; free physical = 1302 ; free virtual = 26514 Phase 3.2 Commit Most Macros & LUTRAMs Phase 3.2 Commit Most Macros & LUTRAMs | Checksum: 1de41feb8 Time (s): cpu = 00:00:28 ; elapsed = 00:00:09 . Memory (MB): peak = 2843.512 ; gain = 7.027 ; free physical = 1299 ; free virtual = 26511 Phase 3.3 Area Swap Optimization Phase 3.3 Area Swap Optimization | Checksum: 18aaa3fc7 Time (s): cpu = 00:00:28 ; elapsed = 00:00:09 . Memory (MB): peak = 2843.512 ; gain = 7.027 ; free physical = 1299 ; free virtual = 26511 Phase 3.4 Pipeline Register Optimization Phase 3.4 Pipeline Register Optimization | Checksum: 21570d42d Time (s): cpu = 00:00:28 ; elapsed = 00:00:09 . Memory (MB): peak = 2843.512 ; gain = 7.027 ; free physical = 1299 ; free virtual = 26511 Phase 3.5 Small Shape Detail Placement Phase 3.5 Small Shape Detail Placement | Checksum: 16b0a777c Time (s): cpu = 00:00:30 ; elapsed = 00:00:10 . Memory (MB): peak = 2843.512 ; gain = 7.027 ; free physical = 1293 ; free virtual = 26505 Phase 3.6 Re-assign LUT pins Phase 3.6 Re-assign LUT pins | Checksum: 15e35a8b7 Time (s): cpu = 00:00:30 ; elapsed = 00:00:10 . Memory (MB): peak = 2843.512 ; gain = 7.027 ; free physical = 1286 ; free virtual = 26498 Phase 3.7 Pipeline Register Optimization Phase 3.7 Pipeline Register Optimization | Checksum: 1fcfebbf7 Time (s): cpu = 00:00:30 ; elapsed = 00:00:11 . Memory (MB): peak = 2843.512 ; gain = 7.027 ; free physical = 1286 ; free virtual = 26498 Phase 3 Detail Placement | Checksum: 1fcfebbf7 Time (s): cpu = 00:00:30 ; elapsed = 00:00:11 . Memory (MB): peak = 2843.512 ; gain = 7.027 ; free physical = 1286 ; free virtual = 26498 Phase 4 Post Placement Optimization and Clean-Up Phase 4.1 Post Commit Optimization INFO: [Timing 38-35] Done setting XDC timing constraints. Phase 4.1.1 Post Placement Optimization Post Placement Optimization Initialization | Checksum: e67ef10d Phase 4.1.1.1 BUFG Insertion Starting Physical Synthesis Task Phase 1 Physical Synthesis Initialization INFO: [Physopt 32-721] Multithreading enabled for phys_opt_design using a maximum of 8 CPUs INFO: [Physopt 32-619] Estimated Timing Summary | WNS=0.081 | TNS=0.000 | Phase 1 Physical Synthesis Initialization | Checksum: 1291cbac6 Time (s): cpu = 00:00:02 ; elapsed = 00:00:00.59 . Memory (MB): peak = 2843.512 ; gain = 0.000 ; free physical = 1300 ; free virtual = 26512 INFO: [Place 46-56] BUFG insertion identified 0 candidate nets. Inserted BUFG: 0, Replicated BUFG Driver: 0, Skipped due to Placement/Routing Conflicts: 0, Skipped due to Timing Degradation: 0, Skipped due to netlist editing failed: 0. Ending Physical Synthesis Task | Checksum: 1291cbac6 Time (s): cpu = 00:00:02 ; elapsed = 00:00:00.66 . Memory (MB): peak = 2843.512 ; gain = 0.000 ; free physical = 1300 ; free virtual = 26512 Phase 4.1.1.1 BUFG Insertion | Checksum: e67ef10d Time (s): cpu = 00:00:37 ; elapsed = 00:00:13 . Memory (MB): peak = 2843.512 ; gain = 7.027 ; free physical = 1300 ; free virtual = 26512 Phase 4.1.1.2 Post Placement Timing Optimization INFO: [Place 30-746] Post Placement Timing Summary WNS=0.509. For the most accurate timing information please run report_timing. Phase 4.1.1.2 Post Placement Timing Optimization | Checksum: 169ca90cc Time (s): cpu = 00:00:42 ; elapsed = 00:00:17 . Memory (MB): peak = 2843.512 ; gain = 7.027 ; free physical = 1287 ; free virtual = 26499 Time (s): cpu = 00:00:42 ; elapsed = 00:00:17 . Memory (MB): peak = 2843.512 ; gain = 7.027 ; free physical = 1287 ; free virtual = 26499 Phase 4.1 Post Commit Optimization | Checksum: 169ca90cc Time (s): cpu = 00:00:42 ; elapsed = 00:00:17 . Memory (MB): peak = 2843.512 ; gain = 7.027 ; free physical = 1287 ; free virtual = 26499 Phase 4.2 Post Placement Cleanup Phase 4.2 Post Placement Cleanup | Checksum: 169ca90cc Time (s): cpu = 00:00:42 ; elapsed = 00:00:17 . Memory (MB): peak = 2843.512 ; gain = 7.027 ; free physical = 1287 ; free virtual = 26499 Phase 4.3 Placer Reporting Phase 4.3.1 Print Estimated Congestion INFO: [Place 30-612] Post-Placement Estimated Congestion ____________________________________________________ | | Global Congestion | Short Congestion | | Direction | Region Size | Region Size | |___________|___________________|___________________| | North| 1x1| 4x4| |___________|___________________|___________________| | South| 1x1| 1x1| |___________|___________________|___________________| | East| 1x1| 1x1| |___________|___________________|___________________| | West| 1x1| 1x1| |___________|___________________|___________________| Phase 4.3.1 Print Estimated Congestion | Checksum: 169ca90cc Time (s): cpu = 00:00:42 ; elapsed = 00:00:17 . Memory (MB): peak = 2843.512 ; gain = 7.027 ; free physical = 1287 ; free virtual = 26499 Phase 4.3 Placer Reporting | Checksum: 169ca90cc Time (s): cpu = 00:00:42 ; elapsed = 00:00:17 . Memory (MB): peak = 2843.512 ; gain = 7.027 ; free physical = 1287 ; free virtual = 26499 Phase 4.4 Final Placement Cleanup Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2843.512 ; gain = 0.000 ; free physical = 1287 ; free virtual = 26499 Time (s): cpu = 00:00:42 ; elapsed = 00:00:17 . Memory (MB): peak = 2843.512 ; gain = 7.027 ; free physical = 1287 ; free virtual = 26499 Phase 4 Post Placement Optimization and Clean-Up | Checksum: 18228c536 Time (s): cpu = 00:00:42 ; elapsed = 00:00:17 . Memory (MB): peak = 2843.512 ; gain = 7.027 ; free physical = 1287 ; free virtual = 26499 Ending Placer Task | Checksum: cb3efb62 Time (s): cpu = 00:00:42 ; elapsed = 00:00:17 . Memory (MB): peak = 2843.512 ; gain = 7.027 ; free physical = 1287 ; free virtual = 26499 37 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered. place_design completed successfully place_design: Time (s): cpu = 00:00:43 ; elapsed = 00:00:18 . Memory (MB): peak = 2843.512 ; gain = 39.043 ; free physical = 1287 ; free virtual = 26499 # report_utilization -hierarchical -file digilent_nexys4ddr_utilization_hierarchical_place.rpt # report_utilization -file digilent_nexys4ddr_utilization_place.rpt # report_io -file digilent_nexys4ddr_io.rpt report_io: Time (s): cpu = 00:00:00.07 ; elapsed = 00:00:00.07 . Memory (MB): peak = 2843.512 ; gain = 0.000 ; free physical = 1287 ; free virtual = 26499 # report_control_sets -verbose -file digilent_nexys4ddr_control_sets.rpt report_control_sets: Time (s): cpu = 00:00:00.02 ; elapsed = 00:00:00.02 . Memory (MB): peak = 2843.512 ; gain = 0.000 ; free physical = 1287 ; free virtual = 26499 # report_clock_utilization -file digilent_nexys4ddr_clock_utilization.rpt # route_design Command: route_design Attempting to get a license for feature 'Implementation' and/or device 'xc7a100t' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7a100t' Running DRC as a precondition to command route_design INFO: [DRC 23-27] Running DRC with 8 threads INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Routing Task INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 8 CPUs Phase 1 Build RT Design Checksum: PlaceDB: 2e5a7e7e ConstDB: 0 ShapeSum: 9ce47ce4 RouteDB: 0 Post Restoration Checksum: NetGraph: a88d1ba4 | NumContArr: f22d70e8 | Constraints: c2a8fa9d | Timing: c2a8fa9d Phase 1 Build RT Design | Checksum: 3200c81c6 Time (s): cpu = 00:00:34 ; elapsed = 00:00:26 . Memory (MB): peak = 2843.512 ; gain = 0.000 ; free physical = 1250 ; free virtual = 26463 Phase 2 Router Initialization Phase 2.1 Fix Topology Constraints Phase 2.1 Fix Topology Constraints | Checksum: 3200c81c6 Time (s): cpu = 00:00:34 ; elapsed = 00:00:26 . Memory (MB): peak = 2843.512 ; gain = 0.000 ; free physical = 1250 ; free virtual = 26463 Phase 2.2 Pre Route Cleanup Phase 2.2 Pre Route Cleanup | Checksum: 3200c81c6 Time (s): cpu = 00:00:34 ; elapsed = 00:00:26 . Memory (MB): peak = 2843.512 ; gain = 0.000 ; free physical = 1250 ; free virtual = 26463 Number of Nodes with overlaps = 0 Phase 2.3 Update Timing Phase 2.3 Update Timing | Checksum: 1bee320e8 Time (s): cpu = 00:00:44 ; elapsed = 00:00:29 . Memory (MB): peak = 2843.512 ; gain = 0.000 ; free physical = 1221 ; free virtual = 26434 INFO: [Route 35-416] Intermediate Timing Summary | WNS=1.532 | TNS=0.000 | WHS=-0.744 | THS=-287.857| Router Utilization Summary Global Vertical Routing Utilization = 0.0116638 % Global Horizontal Routing Utilization = 0.00660699 % Routable Net Status* *Does not include unroutable nets such as driverless and loadless. Run report_route_status for detailed report. Number of Failed Nets = 4468 (Failed Nets is the sum of unrouted and partially routed nets) Number of Unrouted Nets = 4432 Number of Partially Routed Nets = 36 Number of Node Overlaps = 25 Phase 2 Router Initialization | Checksum: 21185dba9 Time (s): cpu = 00:00:47 ; elapsed = 00:00:30 . Memory (MB): peak = 2843.512 ; gain = 0.000 ; free physical = 1217 ; free virtual = 26431 Phase 3 Initial Routing Phase 3.1 Global Routing Phase 3.1 Global Routing | Checksum: 21185dba9 Time (s): cpu = 00:00:47 ; elapsed = 00:00:30 . Memory (MB): peak = 2843.512 ; gain = 0.000 ; free physical = 1217 ; free virtual = 26431 Phase 3.2 Initial Net Routing Phase 3.2 Initial Net Routing | Checksum: 23987c8ea Time (s): cpu = 00:01:04 ; elapsed = 00:00:32 . Memory (MB): peak = 2900.152 ; gain = 56.641 ; free physical = 1167 ; free virtual = 26381 Phase 3 Initial Routing | Checksum: 23987c8ea Time (s): cpu = 00:01:04 ; elapsed = 00:00:32 . Memory (MB): peak = 2900.152 ; gain = 56.641 ; free physical = 1166 ; free virtual = 26380 Phase 4 Rip-up And Reroute Phase 4.1 Global Iteration 0 Number of Nodes with overlaps = 1156 Number of Nodes with overlaps = 171 Number of Nodes with overlaps = 60 Number of Nodes with overlaps = 34 Number of Nodes with overlaps = 15 Number of Nodes with overlaps = 5 Number of Nodes with overlaps = 2 Number of Nodes with overlaps = 1 Number of Nodes with overlaps = 1 Number of Nodes with overlaps = 0 INFO: [Route 35-416] Intermediate Timing Summary | WNS=1.139 | TNS=0.000 | WHS=N/A | THS=N/A | Phase 4.1 Global Iteration 0 | Checksum: 12e6c2578 Time (s): cpu = 00:02:38 ; elapsed = 00:01:27 . Memory (MB): peak = 3002.152 ; gain = 158.641 ; free physical = 1021 ; free virtual = 26234 Phase 4 Rip-up And Reroute | Checksum: 12e6c2578 Time (s): cpu = 00:02:38 ; elapsed = 00:01:27 . Memory (MB): peak = 3002.152 ; gain = 158.641 ; free physical = 1021 ; free virtual = 26234 Phase 5 Delay and Skew Optimization Phase 5.1 Delay CleanUp Phase 5.1.1 Update Timing Phase 5.1.1 Update Timing | Checksum: 1690a4ce3 Time (s): cpu = 00:02:39 ; elapsed = 00:01:28 . Memory (MB): peak = 3002.152 ; gain = 158.641 ; free physical = 1019 ; free virtual = 26233 INFO: [Route 35-416] Intermediate Timing Summary | WNS=1.139 | TNS=0.000 | WHS=N/A | THS=N/A | Phase 5.1 Delay CleanUp | Checksum: 1690a4ce3 Time (s): cpu = 00:02:39 ; elapsed = 00:01:28 . Memory (MB): peak = 3002.152 ; gain = 158.641 ; free physical = 1019 ; free virtual = 26233 Phase 5.2 Clock Skew Optimization Phase 5.2 Clock Skew Optimization | Checksum: 1690a4ce3 Time (s): cpu = 00:02:39 ; elapsed = 00:01:28 . Memory (MB): peak = 3002.152 ; gain = 158.641 ; free physical = 1019 ; free virtual = 26233 Phase 5 Delay and Skew Optimization | Checksum: 1690a4ce3 Time (s): cpu = 00:02:39 ; elapsed = 00:01:28 . Memory (MB): peak = 3002.152 ; gain = 158.641 ; free physical = 1019 ; free virtual = 26233 Phase 6 Post Hold Fix Phase 6.1 Hold Fix Iter Phase 6.1.1 Update Timing Phase 6.1.1 Update Timing | Checksum: 1a9d8dc28 Time (s): cpu = 00:02:42 ; elapsed = 00:01:28 . Memory (MB): peak = 3002.152 ; gain = 158.641 ; free physical = 1031 ; free virtual = 26244 INFO: [Route 35-416] Intermediate Timing Summary | WNS=1.139 | TNS=0.000 | WHS=0.033 | THS=0.000 | Phase 6.1 Hold Fix Iter | Checksum: 1e162409b Time (s): cpu = 00:02:42 ; elapsed = 00:01:28 . Memory (MB): peak = 3002.152 ; gain = 158.641 ; free physical = 1031 ; free virtual = 26244 Phase 6 Post Hold Fix | Checksum: 1e162409b Time (s): cpu = 00:02:42 ; elapsed = 00:01:28 . Memory (MB): peak = 3002.152 ; gain = 158.641 ; free physical = 1031 ; free virtual = 26244 Phase 7 Route finalize Router Utilization Summary Global Vertical Routing Utilization = 1.29617 % Global Horizontal Routing Utilization = 1.58497 % Routable Net Status* *Does not include unroutable nets such as driverless and loadless. Run report_route_status for detailed report. Number of Failed Nets = 0 (Failed Nets is the sum of unrouted and partially routed nets) Number of Unrouted Nets = 0 Number of Partially Routed Nets = 0 Number of Node Overlaps = 0 Phase 7 Route finalize | Checksum: 1e162409b Time (s): cpu = 00:02:42 ; elapsed = 00:01:29 . Memory (MB): peak = 3002.152 ; gain = 158.641 ; free physical = 1031 ; free virtual = 26244 Phase 8 Verifying routed nets Verification completed successfully Phase 8 Verifying routed nets | Checksum: 1e162409b Time (s): cpu = 00:02:42 ; elapsed = 00:01:29 . Memory (MB): peak = 3002.152 ; gain = 158.641 ; free physical = 1030 ; free virtual = 26244 Phase 9 Depositing Routes Phase 9 Depositing Routes | Checksum: 2718c4977 Time (s): cpu = 00:02:43 ; elapsed = 00:01:29 . Memory (MB): peak = 3002.152 ; gain = 158.641 ; free physical = 1030 ; free virtual = 26244 Phase 10 Post Router Timing INFO: [Route 35-57] Estimated Timing Summary | WNS=1.139 | TNS=0.000 | WHS=0.033 | THS=0.000 | INFO: [Route 35-327] The final timing numbers are based on the router estimated timing analysis. For a complete and accurate timing signoff, please run report_timing_summary. Phase 10 Post Router Timing | Checksum: 2718c4977 Time (s): cpu = 00:02:45 ; elapsed = 00:01:30 . Memory (MB): peak = 3002.152 ; gain = 158.641 ; free physical = 1030 ; free virtual = 26244 INFO: [Route 35-16] Router Completed Successfully Phase 11 Post-Route Event Processing Phase 11 Post-Route Event Processing | Checksum: 1a32e3c12 Time (s): cpu = 00:02:45 ; elapsed = 00:01:30 . Memory (MB): peak = 3002.152 ; gain = 158.641 ; free physical = 1030 ; free virtual = 26244 Ending Routing Task | Checksum: 1a32e3c12 Time (s): cpu = 00:02:45 ; elapsed = 00:01:30 . Memory (MB): peak = 3002.152 ; gain = 158.641 ; free physical = 1030 ; free virtual = 26244 Routing Is Done. INFO: [Common 17-83] Releasing license: Implementation 13 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered. route_design completed successfully route_design: Time (s): cpu = 00:02:47 ; elapsed = 00:01:31 . Memory (MB): peak = 3002.152 ; gain = 158.641 ; free physical = 1024 ; free virtual = 26237 # report_timing_summary -no_header -no_detailed_paths INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -1, Delay Type: min_max. INFO: [Timing 38-191] Multithreading enabled for timing update using a maximum of 8 CPUs ------------------------------------------------------------------------------------------------ | Timer Settings | -------------- ------------------------------------------------------------------------------------------------ Enable Multi Corner Analysis : Yes Enable Pessimism Removal : Yes Pessimism Removal Resolution : Nearest Common Node Enable Input Delay Default Clock : No Enable Preset / Clear Arcs : No Disable Flight Delays : No Ignore I/O Paths : No Timing Early Launch at Borrowing Latches : No Borrow Time for Max Delay Exceptions : Yes Merge Timing Exceptions : Yes Inter-SLR Compensation : Conservative Corner Analyze Analyze Name Max Paths Min Paths ------ --------- --------- Slow Yes Yes Fast Yes Yes ------------------------------------------------------------------------------------------------ | Report Methodology | ------------------ ------------------------------------------------------------------------------------------------ No report available as report_methodology has not been run prior. Run report_methodology on the current design for the summary of methodology violations. check_timing report Table of Contents ----------------- 1. checking no_clock (0) 2. checking constant_clock (0) 3. checking pulse_width_clock (0) 4. checking unconstrained_internal_endpoints (0) 5. checking no_input_delay (1) 6. checking no_output_delay (1) 7. checking multiple_clock (0) 8. checking generated_clocks (0) 9. checking loops (0) 10. checking partial_input_delay (0) 11. checking partial_output_delay (0) 12. checking latch_loops (0) 1. checking no_clock (0) ------------------------ There are 0 register/latch pins with no clock. 2. checking constant_clock (0) ------------------------------ There are 0 register/latch pins with constant_clock. 3. checking pulse_width_clock (0) --------------------------------- There are 0 register/latch pins which need pulse_width check 4. checking unconstrained_internal_endpoints (0) ------------------------------------------------ There are 0 pins that are not constrained for maximum delay. There are 0 pins that are not constrained for maximum delay due to constant clock. 5. checking no_input_delay (1) ------------------------------ There is 1 input port with no input delay specified. (HIGH) There are 0 input ports with no input delay but user has a false path constraint. 6. checking no_output_delay (1) ------------------------------- There is 1 port with no output delay specified. (HIGH) There are 0 ports with no output delay but user has a false path constraint There are 0 ports with no output delay but with a timing clock defined on it or propagating through it 7. checking multiple_clock (0) ------------------------------ There are 0 register/latch pins with multiple clocks. 8. checking generated_clocks (0) -------------------------------- There are 0 generated clocks that are not connected to a clock source. 9. checking loops (0) --------------------- There are 0 combinational loops in the design. 10. checking partial_input_delay (0) ------------------------------------ There are 0 input ports with partial input delay specified. 11. checking partial_output_delay (0) ------------------------------------- There are 0 ports with partial output delay specified. 12. checking latch_loops (0) ---------------------------- There are 0 combinational latch loops in the design through latch input ------------------------------------------------------------------------------------------------ | Design Timing Summary | --------------------- ------------------------------------------------------------------------------------------------ WNS(ns) TNS(ns) TNS Failing Endpoints TNS Total Endpoints WHS(ns) THS(ns) THS Failing Endpoints THS Total Endpoints WPWS(ns) TPWS(ns) TPWS Failing Endpoints TPWS Total Endpoints ------- ------- --------------------- ------------------- ------- ------- --------------------- ------------------- -------- -------- ---------------------- -------------------- 1.139 0.000 0 15540 0.033 0.000 0 15540 3.750 0.000 0 3396 All user specified timing constraints are met. ------------------------------------------------------------------------------------------------ | Clock Summary | ------------- ------------------------------------------------------------------------------------------------ Clock Waveform(ns) Period(ns) Frequency(MHz) ----- ------------ ---------- -------------- sys_clk_pin {0.000 5.000} 10.000 100.000 ------------------------------------------------------------------------------------------------ | Intra Clock Table | ----------------- ------------------------------------------------------------------------------------------------ Clock WNS(ns) TNS(ns) TNS Failing Endpoints TNS Total Endpoints WHS(ns) THS(ns) THS Failing Endpoints THS Total Endpoints WPWS(ns) TPWS(ns) TPWS Failing Endpoints TPWS Total Endpoints ----- ------- ------- --------------------- ------------------- ------- ------- --------------------- ------------------- -------- -------- ---------------------- -------------------- sys_clk_pin 1.139 0.000 0 15540 0.033 0.000 0 15540 3.750 0.000 0 3396 ------------------------------------------------------------------------------------------------ | Inter Clock Table | ----------------- ------------------------------------------------------------------------------------------------ From Clock To Clock WNS(ns) TNS(ns) TNS Failing Endpoints TNS Total Endpoints WHS(ns) THS(ns) THS Failing Endpoints THS Total Endpoints ---------- -------- ------- ------- --------------------- ------------------- ------- ------- --------------------- ------------------- ------------------------------------------------------------------------------------------------ | Other Path Groups Table | ----------------------- ------------------------------------------------------------------------------------------------ Path Group From Clock To Clock WNS(ns) TNS(ns) TNS Failing Endpoints TNS Total Endpoints WHS(ns) THS(ns) THS Failing Endpoints THS Total Endpoints ---------- ---------- -------- ------- ------- --------------------- ------------------- ------- ------- --------------------- ------------------- # report_route_status -file digilent_nexys4ddr_route_status.rpt # report_drc -file digilent_nexys4ddr_drc.rpt Command: report_drc -file digilent_nexys4ddr_drc.rpt INFO: [IP_Flow 19-234] Refreshing IP repositories INFO: [IP_Flow 19-1704] No user IP repositories specified INFO: [IP_Flow 19-2313] Loaded Vivado IP repository '/eda/vivado/Vivado/2023.2/data/ip'. INFO: [DRC 23-27] Running DRC with 8 threads INFO: [Vivado_Tcl 2-168] The results of DRC are in file /var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/digilent_nexys4ddr_drc.rpt. report_drc completed successfully # report_timing_summary -datasheet -max_paths 10 -file digilent_nexys4ddr_timing.rpt INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -1, Delay Type: min_max. INFO: [Timing 38-191] Multithreading enabled for timing update using a maximum of 8 CPUs # report_power -file digilent_nexys4ddr_power.rpt Command: report_power -file digilent_nexys4ddr_power.rpt Running Vector-less Activity Propagation... Finished Running Vector-less Activity Propagation WARNING: [Power 33-332] Found switching activity that implies high-fanout reset nets being asserted for excessive periods of time which may result in inaccurate power analysis. Resolution: To review and fix problems, please run Power Constraints Advisor in the GUI from Tools > Power Constraints Advisor or run report_power with the -advisory option to generate a text report. 0 Infos, 1 Warnings, 0 Critical Warnings and 0 Errors encountered. report_power completed successfully # write_bitstream -force "digilent_nexys4_ddr.bit" Command: write_bitstream -force digilent_nexys4_ddr.bit Attempting to get a license for feature 'Implementation' and/or device 'xc7a100t' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7a100t' Running DRC as a precondition to command write_bitstream INFO: [IP_Flow 19-1839] IP Catalog is up to date. INFO: [DRC 23-27] Running DRC with 8 threads WARNING: [DRC CFGBVS-1] Missing CFGBVS and CONFIG_VOLTAGE Design Properties: Neither the CFGBVS nor CONFIG_VOLTAGE voltage property is set in the current_design. Configuration bank voltage select (CFGBVS) must be set to VCCO or GND, and CONFIG_VOLTAGE must be set to the correct configuration voltage, in order to determine the I/O voltage support for the pins in bank 0. It is suggested to specify these either using the 'Edit Device Properties' function in the GUI or directly in the XDC file using the following syntax: set_property CFGBVS value1 [current_design] #where value1 is either VCCO or GND set_property CONFIG_VOLTAGE value2 [current_design] #where value2 is the voltage provided to configuration bank 0 Refer to the device configuration user guide for more information. INFO: [Vivado 12-3199] DRC finished with 0 Errors, 1 Warnings INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information. INFO: [Designutils 20-2272] Running write_bitstream with 8 threads. Loading data files... Loading site data... Loading route data... Processing options... Creating bitmap... Creating bitstream... Writing bitstream ./digilent_nexys4_ddr.bit... INFO: [Vivado 12-1842] Bitgen Completed Successfully. INFO: [Project 1-1876] WebTalk data collection is mandatory when using a ULT device. To see the specific WebTalk data collected for your design, open the usage_statistics_webtalk.html or usage_statistics_webtalk.xml file in the implementation directory. INFO: [Common 17-83] Releasing license: Implementation 9 Infos, 1 Warnings, 0 Critical Warnings and 0 Errors encountered. write_bitstream completed successfully write_bitstream: Time (s): cpu = 00:00:15 ; elapsed = 00:00:20 . Memory (MB): peak = 3171.543 ; gain = 113.363 ; free physical = 869 ; free virtual = 26087 INFO: [Common 17-206] Exiting Vivado at Fri Dec 13 20:19:55 2024... [Pipeline] } [Pipeline] // dir [Pipeline] } [Pipeline] // stage [Pipeline] stage [Pipeline] { (Flash digilent_nexys4_ddr) [Pipeline] dir Running in /var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5 [Pipeline] { [Pipeline] echo Flashing FPGA digilent_nexys4_ddr. [Pipeline] sh + python3 /eda/processor-ci/main.py -c /eda/processor-ci/config.json -p Grande-Risco-5 -b digilent_nexys4_ddr -l Final configuration file generated at /var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/build_digilent_nexys4_ddr.tcl Makefile executed successfully. Makefile output: Flashing the FPGA... /eda/oss-cad-suite/bin/openFPGALoader -b nexys_a7_100 digilent_nexys4_ddr.bit empty Jtag frequency : requested 6.00MHz -> real 6.00MHz Open file DONE Parse file DONE load program Load SRAM: [========= ] 18.00% Load SRAM: [=================== ] 38.00% Load SRAM: [============================= ] 58.00% Load SRAM: [======================================= ] 78.00% Load SRAM: [================================================= ] 98.00% Load SRAM: [===================================================] 100.00% Done Shift IR 35 ir: 1 isc_done 1 isc_ena 0 init 1 done 1 [Pipeline] } [Pipeline] // dir [Pipeline] } [Pipeline] // stage [Pipeline] stage [Pipeline] { (Test digilent_nexys4_ddr) [Pipeline] echo Testing FPGA digilent_nexys4_ddr. [Pipeline] dir Running in /var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5 [Pipeline] { [Pipeline] sh + PYTHONPATH=/eda/processor-ci-communication PORT=/dev/ttyUSB1 python /eda/processor-ci-communication/run_tests.py python: can't open file '/eda/processor-ci-communication/run_tests.py': [Errno 2] No such file or directory [Pipeline] } [Pipeline] // dir [Pipeline] } [Pipeline] // stage [Pipeline] } Lock released on resource [Resource: digilent_nexys4_ddr] [Pipeline] // lock [Pipeline] } [Pipeline] // stage [Pipeline] } Failed in branch digilent_nexys4_ddr [Pipeline] // parallel [Pipeline] } [Pipeline] // stage [Pipeline] stage [Pipeline] { (Declarative: Post Actions) [Pipeline] junit Recording test results No test report files were found. Configuration error? Error when executing always post condition: Also: org.jenkinsci.plugins.workflow.actions.ErrorAction$ErrorId: b5e67142-293d-4510-8e41-10ba704edb77 hudson.AbortException: No test report files were found. Configuration error? at PluginClassLoader for junit//hudson.tasks.junit.JUnitParser$ParseResultCallable.invoke(JUnitParser.java:253) at hudson.FilePath.act(FilePath.java:1234) at hudson.FilePath.act(FilePath.java:1217) at PluginClassLoader for junit//hudson.tasks.junit.JUnitParser.parseResult(JUnitParser.java:146) at PluginClassLoader for junit//hudson.tasks.junit.JUnitResultArchiver.parse(JUnitResultArchiver.java:177) at PluginClassLoader for junit//hudson.tasks.junit.JUnitResultArchiver.parseAndSummarize(JUnitResultArchiver.java:282) at PluginClassLoader for junit//hudson.tasks.junit.pipeline.JUnitResultsStepExecution.run(JUnitResultsStepExecution.java:62) at PluginClassLoader for junit//hudson.tasks.junit.pipeline.JUnitResultsStepExecution.run(JUnitResultsStepExecution.java:27) at PluginClassLoader for workflow-step-api//org.jenkinsci.plugins.workflow.steps.SynchronousNonBlockingStepExecution.lambda$start$0(SynchronousNonBlockingStepExecution.java:47) at java.base/java.util.concurrent.Executors$RunnableAdapter.call(Unknown Source) at java.base/java.util.concurrent.FutureTask.run(Unknown Source) at java.base/java.util.concurrent.ThreadPoolExecutor.runWorker(Unknown Source) at java.base/java.util.concurrent.ThreadPoolExecutor$Worker.run(Unknown Source) at java.base/java.lang.Thread.run(Unknown Source) [Pipeline] } [Pipeline] // stage [Pipeline] } [Pipeline] // node [Pipeline] End of Pipeline ERROR: script returned exit code 1 Finished: FAILURE