+====================+===================+=======================================================================================================================================================================================================================================================================+
| Launch Setup Clock | Launch Hold Clock | Pin                                                                                                                                                                                                                                                                   |
+====================+===================+=======================================================================================================================================================================================================================================================================+
| oserdes_clk_1      | oserdes_clk_1     | u_dram_controller/mig_7series_0_inst/u_mig_7series_0_mig/u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/ddr_byte_group_io/output_[8].oserdes_dq_.sdr.oserdes_dq_i/RST  |
| oserdes_clk_5      | oserdes_clk_5     | u_dram_controller/mig_7series_0_inst/u_mig_7series_0_mig/u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/ddr_byte_group_io/output_[8].oserdes_dq_.ddr.oserdes_dq_i/RST  |
| oserdes_clk_3      | oserdes_clk_3     | u_dram_controller/mig_7series_0_inst/u_mig_7series_0_mig/u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/ddr_byte_group_io/output_[0].oserdes_dq_.sdr.oserdes_dq_i/RST  |
| oserdes_clk_6      | oserdes_clk_6     | u_dram_controller/mig_7series_0_inst/u_mig_7series_0_mig/u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/ddr_byte_group_io/output_[2].oserdes_dq_.ddr.oserdes_dq_i/RST  |
| oserdes_clk_1      | oserdes_clk_1     | u_dram_controller/mig_7series_0_inst/u_mig_7series_0_mig/u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/ddr_byte_group_io/output_[6].oserdes_dq_.sdr.oserdes_dq_i/RST  |
| oserdes_clk_5      | oserdes_clk_5     | u_dram_controller/mig_7series_0_inst/u_mig_7series_0_mig/u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/ddr_byte_group_io/output_[6].oserdes_dq_.ddr.oserdes_dq_i/RST  |
| oserdes_clk_6      | oserdes_clk_6     | u_dram_controller/mig_7series_0_inst/u_mig_7series_0_mig/u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/ddr_byte_group_io/output_[4].oserdes_dq_.ddr.oserdes_dq_i/RST  |
| oserdes_clk_1      | oserdes_clk_1     | u_dram_controller/mig_7series_0_inst/u_mig_7series_0_mig/u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/ddr_byte_group_io/output_[9].oserdes_dq_.sdr.oserdes_dq_i/RST  |
| oserdes_clk_5      | oserdes_clk_5     | u_dram_controller/mig_7series_0_inst/u_mig_7series_0_mig/u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/ddr_byte_group_io/output_[9].oserdes_dq_.ddr.oserdes_dq_i/RST  |
| oserdes_clk_3      | oserdes_clk_3     | u_dram_controller/mig_7series_0_inst/u_mig_7series_0_mig/u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/ddr_byte_group_io/output_[1].oserdes_dq_.sdr.oserdes_dq_i/RST  |
| oserdes_clk_7      | oserdes_clk_7     | u_dram_controller/mig_7series_0_inst/u_mig_7series_0_mig/u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/ddr_byte_group_io/output_[2].oserdes_dq_.ddr.oserdes_dq_i/RST  |
| oserdes_clk_7      | oserdes_clk_7     | u_dram_controller/mig_7series_0_inst/u_mig_7series_0_mig/u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/ddr_byte_group_io/output_[1].oserdes_dq_.ddr.oserdes_dq_i/RST  |
| oserdes_clk_4      | oserdes_clk_4     | u_dram_controller/mig_7series_0_inst/u_mig_7series_0_mig/u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/ddr_byte_group_io/output_[6].oserdes_dq_.ddr.oserdes_dq_i/RST  |
| oserdes_clk_5      | oserdes_clk_5     | u_dram_controller/mig_7series_0_inst/u_mig_7series_0_mig/u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/ddr_byte_group_io/output_[1].oserdes_dq_.ddr.oserdes_dq_i/RST  |
| oserdes_clk_2      | oserdes_clk_2     | u_dram_controller/mig_7series_0_inst/u_mig_7series_0_mig/u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/ddr_byte_group_io/output_[7].oserdes_dq_.sdr.oserdes_dq_i/RST  |
| oserdes_clk_2      | oserdes_clk_2     | u_dram_controller/mig_7series_0_inst/u_mig_7series_0_mig/u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/ddr_byte_group_io/output_[0].oserdes_dq_.sdr.oserdes_dq_i/RST  |
| oserdes_clk_6      | oserdes_clk_6     | u_dram_controller/mig_7series_0_inst/u_mig_7series_0_mig/u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/ddr_byte_group_io/output_[7].oserdes_dq_.ddr.oserdes_dq_i/RST  |
| oserdes_clk_6      | oserdes_clk_6     | u_dram_controller/mig_7series_0_inst/u_mig_7series_0_mig/u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/ddr_byte_group_io/output_[3].oserdes_dq_.ddr.oserdes_dq_i/RST  |
| oserdes_clk_1      | oserdes_clk_1     | u_dram_controller/mig_7series_0_inst/u_mig_7series_0_mig/u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/ddr_byte_group_io/output_[7].oserdes_dq_.sdr.oserdes_dq_i/RST  |
| oserdes_clk_5      | oserdes_clk_5     | u_dram_controller/mig_7series_0_inst/u_mig_7series_0_mig/u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/ddr_byte_group_io/output_[7].oserdes_dq_.ddr.oserdes_dq_i/RST  |
| oserdes_clk_2      | oserdes_clk_2     | u_dram_controller/mig_7series_0_inst/u_mig_7series_0_mig/u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/ddr_byte_group_io/output_[1].oserdes_dq_.sdr.oserdes_dq_i/RST  |
| oserdes_clk_6      | oserdes_clk_6     | u_dram_controller/mig_7series_0_inst/u_mig_7series_0_mig/u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/ddr_byte_group_io/output_[1].oserdes_dq_.ddr.oserdes_dq_i/RST  |
| oserdes_clk_2      | oserdes_clk_2     | u_dram_controller/mig_7series_0_inst/u_mig_7series_0_mig/u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/ddr_byte_group_io/output_[8].oserdes_dq_.sdr.oserdes_dq_i/RST  |
| oserdes_clk_5      | oserdes_clk_5     | u_dram_controller/mig_7series_0_inst/u_mig_7series_0_mig/u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/ddr_byte_group_io/slave_ts.oserdes_slave_ts/RST                |
| oserdes_clk_6      | oserdes_clk_6     | u_dram_controller/mig_7series_0_inst/u_mig_7series_0_mig/u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/ddr_byte_group_io/output_[9].oserdes_dq_.ddr.oserdes_dq_i/RST  |
| oserdes_clk_6      | oserdes_clk_6     | u_dram_controller/mig_7series_0_inst/u_mig_7series_0_mig/u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/ddr_byte_group_io/output_[8].oserdes_dq_.ddr.oserdes_dq_i/RST  |
| oserdes_clk_2      | oserdes_clk_2     | u_dram_controller/mig_7series_0_inst/u_mig_7series_0_mig/u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/ddr_byte_group_io/output_[5].oserdes_dq_.sdr.oserdes_dq_i/RST  |
| oserdes_clk_6      | oserdes_clk_6     | u_dram_controller/mig_7series_0_inst/u_mig_7series_0_mig/u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/ddr_byte_group_io/output_[5].oserdes_dq_.ddr.oserdes_dq_i/RST  |
| oserdes_clk_7      | oserdes_clk_7     | u_dram_controller/mig_7series_0_inst/u_mig_7series_0_mig/u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/ddr_byte_group_io/slave_ts.oserdes_slave_ts/RST                |
| oserdes_clk_3      | oserdes_clk_3     | u_dram_controller/mig_7series_0_inst/u_mig_7series_0_mig/u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/ddr_byte_group_io/output_[10].oserdes_dq_.sdr.oserdes_dq_i/RST |
| oserdes_clk_2      | oserdes_clk_2     | u_dram_controller/mig_7series_0_inst/u_mig_7series_0_mig/u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/ddr_byte_group_io/output_[10].oserdes_dq_.sdr.oserdes_dq_i/RST |
| oserdes_clk_6      | oserdes_clk_6     | u_dram_controller/mig_7series_0_inst/u_mig_7series_0_mig/u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/ddr_byte_group_io/slave_ts.oserdes_slave_ts/RST                |
| oserdes_clk_5      | oserdes_clk_5     | u_dram_controller/mig_7series_0_inst/u_mig_7series_0_mig/u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/ddr_byte_group_io/output_[5].oserdes_dq_.ddr.oserdes_dq_i/RST  |
| oserdes_clk_3      | oserdes_clk_3     | u_dram_controller/mig_7series_0_inst/u_mig_7series_0_mig/u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/ddr_byte_group_io/output_[3].oserdes_dq_.sdr.oserdes_dq_i/RST  |
| oserdes_clk_7      | oserdes_clk_7     | u_dram_controller/mig_7series_0_inst/u_mig_7series_0_mig/u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/ddr_byte_group_io/output_[3].oserdes_dq_.ddr.oserdes_dq_i/RST  |
| oserdes_clk_4      | oserdes_clk_4     | u_dram_controller/mig_7series_0_inst/u_mig_7series_0_mig/u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/ddr_byte_group_io/slave_ts.oserdes_slave_ts/RST                |
| oserdes_clk_3      | oserdes_clk_3     | u_dram_controller/mig_7series_0_inst/u_mig_7series_0_mig/u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/ddr_byte_group_io/output_[11].oserdes_dq_.sdr.oserdes_dq_i/RST |
| oserdes_clk_7      | oserdes_clk_7     | u_dram_controller/mig_7series_0_inst/u_mig_7series_0_mig/u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/ddr_byte_group_io/output_[6].oserdes_dq_.ddr.oserdes_dq_i/RST  |
| oserdes_clk        | oserdes_clk       | u_dram_controller/mig_7series_0_inst/u_mig_7series_0_mig/u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/ddr_byte_group_io/output_[4].oserdes_dq_.sdr.oserdes_dq_i/RST  |
| oserdes_clk_3      | oserdes_clk_3     | u_dram_controller/mig_7series_0_inst/u_mig_7series_0_mig/u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/ddr_byte_group_io/output_[6].oserdes_dq_.sdr.oserdes_dq_i/RST  |
| oserdes_clk_4      | oserdes_clk_4     | u_dram_controller/mig_7series_0_inst/u_mig_7series_0_mig/u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/ddr_byte_group_io/output_[2].oserdes_dq_.ddr.oserdes_dq_i/RST  |
| oserdes_clk_4      | oserdes_clk_4     | u_dram_controller/mig_7series_0_inst/u_mig_7series_0_mig/u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/ddr_byte_group_io/output_[4].oserdes_dq_.ddr.oserdes_dq_i/RST  |
| oserdes_clk_5      | oserdes_clk_5     | u_dram_controller/mig_7series_0_inst/u_mig_7series_0_mig/u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/ddr_byte_group_io/output_[3].oserdes_dq_.ddr.oserdes_dq_i/RST  |
| oserdes_clk_4      | oserdes_clk_4     | u_dram_controller/mig_7series_0_inst/u_mig_7series_0_mig/u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/ddr_byte_group_io/output_[9].oserdes_dq_.ddr.oserdes_dq_i/RST  |
| oserdes_clk_2      | oserdes_clk_2     | u_dram_controller/mig_7series_0_inst/u_mig_7series_0_mig/u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/ddr_byte_group_io/output_[11].oserdes_dq_.sdr.oserdes_dq_i/RST |
| oserdes_clk_7      | oserdes_clk_7     | u_dram_controller/mig_7series_0_inst/u_mig_7series_0_mig/u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/ddr_byte_group_io/output_[8].oserdes_dq_.ddr.oserdes_dq_i/RST  |
| oserdes_clk_7      | oserdes_clk_7     | u_dram_controller/mig_7series_0_inst/u_mig_7series_0_mig/u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/ddr_byte_group_io/output_[7].oserdes_dq_.ddr.oserdes_dq_i/RST  |
| oserdes_clk_3      | oserdes_clk_3     | u_dram_controller/mig_7series_0_inst/u_mig_7series_0_mig/u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/ddr_byte_group_io/output_[7].oserdes_dq_.sdr.oserdes_dq_i/RST  |
| oserdes_clk_4      | oserdes_clk_4     | u_dram_controller/mig_7series_0_inst/u_mig_7series_0_mig/u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/ddr_byte_group_io/output_[5].oserdes_dq_.ddr.oserdes_dq_i/RST  |
| oserdes_clk_3      | oserdes_clk_3     | u_dram_controller/mig_7series_0_inst/u_mig_7series_0_mig/u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/ddr_byte_group_io/output_[4].oserdes_dq_.sdr.oserdes_dq_i/RST  |
| oserdes_clk_7      | oserdes_clk_7     | u_dram_controller/mig_7series_0_inst/u_mig_7series_0_mig/u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/ddr_byte_group_io/output_[4].oserdes_dq_.ddr.oserdes_dq_i/RST  |
| oserdes_clk_4      | oserdes_clk_4     | u_dram_controller/mig_7series_0_inst/u_mig_7series_0_mig/u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/ddr_byte_group_io/output_[7].oserdes_dq_.ddr.oserdes_dq_i/RST  |
| oserdes_clk        | oserdes_clk       | u_dram_controller/mig_7series_0_inst/u_mig_7series_0_mig/u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/ddr_byte_group_io/output_[1].oserdes_dq_.sdr.oserdes_dq_i/RST  |
| oserdes_clk_4      | oserdes_clk_4     | u_dram_controller/mig_7series_0_inst/u_mig_7series_0_mig/u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/ddr_byte_group_io/output_[1].oserdes_dq_.ddr.oserdes_dq_i/RST  |
| oserdes_clk_5      | oserdes_clk_5     | u_dram_controller/mig_7series_0_inst/u_mig_7series_0_mig/u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/ddr_byte_group_io/output_[2].oserdes_dq_.ddr.oserdes_dq_i/RST  |
| oserdes_clk        | oserdes_clk       | u_dram_controller/mig_7series_0_inst/u_mig_7series_0_mig/u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/ddr_byte_group_io/output_[0].oserdes_dq_.sdr.oserdes_dq_i/RST  |
| oserdes_clk_7      | oserdes_clk_7     | u_dram_controller/mig_7series_0_inst/u_mig_7series_0_mig/u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/ddr_byte_group_io/output_[9].oserdes_dq_.ddr.oserdes_dq_i/RST  |
| oserdes_clk_4      | oserdes_clk_4     | u_dram_controller/mig_7series_0_inst/u_mig_7series_0_mig/u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/ddr_byte_group_io/output_[0].oserdes_dq_.ddr.oserdes_dq_i/RST  |
| oserdes_clk_2      | oserdes_clk_2     | u_dram_controller/mig_7series_0_inst/u_mig_7series_0_mig/u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/ddr_byte_group_io/output_[6].oserdes_dq_.sdr.oserdes_dq_i/RST  |
| oserdes_clk_6      | oserdes_clk_6     | u_dram_controller/mig_7series_0_inst/u_mig_7series_0_mig/u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/ddr_byte_group_io/output_[6].oserdes_dq_.ddr.oserdes_dq_i/RST  |
| oserdes_clk_5      | oserdes_clk_5     | u_dram_controller/mig_7series_0_inst/u_mig_7series_0_mig/u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/ddr_byte_group_io/output_[4].oserdes_dq_.ddr.oserdes_dq_i/RST  |
| oserdes_clk_4      | oserdes_clk_4     | u_dram_controller/mig_7series_0_inst/u_mig_7series_0_mig/u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/ddr_byte_group_io/output_[3].oserdes_dq_.ddr.oserdes_dq_i/RST  |
| oserdes_clk_3      | oserdes_clk_3     | u_dram_controller/mig_7series_0_inst/u_mig_7series_0_mig/u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/ddr_byte_group_io/output_[5].oserdes_dq_.sdr.oserdes_dq_i/RST  |
| oserdes_clk_7      | oserdes_clk_7     | u_dram_controller/mig_7series_0_inst/u_mig_7series_0_mig/u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/ddr_byte_group_io/output_[5].oserdes_dq_.ddr.oserdes_dq_i/RST  |
+--------------------+-------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
