################################################################################
# IO constraints
################################################################################
# uart:0.tx
set_property LOC X [get_ports {uart_tx}]

# uart:0.rx
set_property LOC X [get_ports {uart_rx}]

# clk:0
set_property LOC X [get_ports {clk}]

# rst:0
set_property LOC X [get_ports {rst}]

# pll_locked:0
set_property LOC X [get_ports {pll_locked}]

# ddram:0.a
set_property LOC X [get_ports {ddram_a[0]}]

# ddram:0.a
set_property LOC X [get_ports {ddram_a[1]}]

# ddram:0.a
set_property LOC X [get_ports {ddram_a[2]}]

# ddram:0.a
set_property LOC X [get_ports {ddram_a[3]}]

# ddram:0.a
set_property LOC X [get_ports {ddram_a[4]}]

# ddram:0.a
set_property LOC X [get_ports {ddram_a[5]}]

# ddram:0.a
set_property LOC X [get_ports {ddram_a[6]}]

# ddram:0.a
set_property LOC X [get_ports {ddram_a[7]}]

# ddram:0.a
set_property LOC X [get_ports {ddram_a[8]}]

# ddram:0.a
set_property LOC X [get_ports {ddram_a[9]}]

# ddram:0.a
set_property LOC X [get_ports {ddram_a[10]}]

# ddram:0.a
set_property LOC X [get_ports {ddram_a[11]}]

# ddram:0.a
set_property LOC X [get_ports {ddram_a[12]}]

# ddram:0.a
set_property LOC X [get_ports {ddram_a[13]}]

# ddram:0.a
set_property LOC X [get_ports {ddram_a[14]}]

# ddram:0.ba
set_property LOC X [get_ports {ddram_ba[0]}]

# ddram:0.ba
set_property LOC X [get_ports {ddram_ba[1]}]

# ddram:0.ba
set_property LOC X [get_ports {ddram_ba[2]}]

# ddram:0.ras_n
set_property LOC X [get_ports {ddram_ras_n}]

# ddram:0.cas_n
set_property LOC X [get_ports {ddram_cas_n}]

# ddram:0.we_n
set_property LOC X [get_ports {ddram_we_n}]

# ddram:0.cs_n
set_property LOC X [get_ports {ddram_cs_n}]

# ddram:0.dm
set_property LOC X [get_ports {ddram_dm[0]}]

# ddram:0.dm
set_property LOC X [get_ports {ddram_dm[1]}]

# ddram:0.dm
set_property LOC X [get_ports {ddram_dm[2]}]

# ddram:0.dm
set_property LOC X [get_ports {ddram_dm[3]}]

# ddram:0.dq
set_property LOC X [get_ports {ddram_dq[0]}]

# ddram:0.dq
set_property LOC X [get_ports {ddram_dq[1]}]

# ddram:0.dq
set_property LOC X [get_ports {ddram_dq[2]}]

# ddram:0.dq
set_property LOC X [get_ports {ddram_dq[3]}]

# ddram:0.dq
set_property LOC X [get_ports {ddram_dq[4]}]

# ddram:0.dq
set_property LOC X [get_ports {ddram_dq[5]}]

# ddram:0.dq
set_property LOC X [get_ports {ddram_dq[6]}]

# ddram:0.dq
set_property LOC X [get_ports {ddram_dq[7]}]

# ddram:0.dq
set_property LOC X [get_ports {ddram_dq[8]}]

# ddram:0.dq
set_property LOC X [get_ports {ddram_dq[9]}]

# ddram:0.dq
set_property LOC X [get_ports {ddram_dq[10]}]

# ddram:0.dq
set_property LOC X [get_ports {ddram_dq[11]}]

# ddram:0.dq
set_property LOC X [get_ports {ddram_dq[12]}]

# ddram:0.dq
set_property LOC X [get_ports {ddram_dq[13]}]

# ddram:0.dq
set_property LOC X [get_ports {ddram_dq[14]}]

# ddram:0.dq
set_property LOC X [get_ports {ddram_dq[15]}]

# ddram:0.dq
set_property LOC X [get_ports {ddram_dq[16]}]

# ddram:0.dq
set_property LOC X [get_ports {ddram_dq[17]}]

# ddram:0.dq
set_property LOC X [get_ports {ddram_dq[18]}]

# ddram:0.dq
set_property LOC X [get_ports {ddram_dq[19]}]

# ddram:0.dq
set_property LOC X [get_ports {ddram_dq[20]}]

# ddram:0.dq
set_property LOC X [get_ports {ddram_dq[21]}]

# ddram:0.dq
set_property LOC X [get_ports {ddram_dq[22]}]

# ddram:0.dq
set_property LOC X [get_ports {ddram_dq[23]}]

# ddram:0.dq
set_property LOC X [get_ports {ddram_dq[24]}]

# ddram:0.dq
set_property LOC X [get_ports {ddram_dq[25]}]

# ddram:0.dq
set_property LOC X [get_ports {ddram_dq[26]}]

# ddram:0.dq
set_property LOC X [get_ports {ddram_dq[27]}]

# ddram:0.dq
set_property LOC X [get_ports {ddram_dq[28]}]

# ddram:0.dq
set_property LOC X [get_ports {ddram_dq[29]}]

# ddram:0.dq
set_property LOC X [get_ports {ddram_dq[30]}]

# ddram:0.dq
set_property LOC X [get_ports {ddram_dq[31]}]

# ddram:0.dqs_p
set_property LOC X [get_ports {ddram_dqs_p[0]}]

# ddram:0.dqs_p
set_property LOC X [get_ports {ddram_dqs_p[1]}]

# ddram:0.dqs_p
set_property LOC X [get_ports {ddram_dqs_p[2]}]

# ddram:0.dqs_p
set_property LOC X [get_ports {ddram_dqs_p[3]}]

# ddram:0.dqs_n
set_property LOC X [get_ports {ddram_dqs_n[0]}]

# ddram:0.dqs_n
set_property LOC X [get_ports {ddram_dqs_n[1]}]

# ddram:0.dqs_n
set_property LOC X [get_ports {ddram_dqs_n[2]}]

# ddram:0.dqs_n
set_property LOC X [get_ports {ddram_dqs_n[3]}]

# ddram:0.clk_p
set_property LOC X [get_ports {ddram_clk_p}]

# ddram:0.clk_n
set_property LOC X [get_ports {ddram_clk_n}]

# ddram:0.cke
set_property LOC X [get_ports {ddram_cke}]

# ddram:0.odt
set_property LOC X [get_ports {ddram_odt}]

# ddram:0.reset_n
set_property LOC X [get_ports {ddram_reset_n}]

# init_done:0
set_property LOC X [get_ports {init_done}]

# init_error:0
set_property LOC X [get_ports {init_error}]

# user_clk:0
set_property LOC X [get_ports {user_clk}]

# user_rst:0
set_property LOC X [get_ports {user_rst}]

# user_port_wishbone_0:0.adr
set_property LOC X [get_ports {user_port_wishbone_0_adr[0]}]

# user_port_wishbone_0:0.adr
set_property LOC X [get_ports {user_port_wishbone_0_adr[1]}]

# user_port_wishbone_0:0.adr
set_property LOC X [get_ports {user_port_wishbone_0_adr[2]}]

# user_port_wishbone_0:0.adr
set_property LOC X [get_ports {user_port_wishbone_0_adr[3]}]

# user_port_wishbone_0:0.adr
set_property LOC X [get_ports {user_port_wishbone_0_adr[4]}]

# user_port_wishbone_0:0.adr
set_property LOC X [get_ports {user_port_wishbone_0_adr[5]}]

# user_port_wishbone_0:0.adr
set_property LOC X [get_ports {user_port_wishbone_0_adr[6]}]

# user_port_wishbone_0:0.adr
set_property LOC X [get_ports {user_port_wishbone_0_adr[7]}]

# user_port_wishbone_0:0.adr
set_property LOC X [get_ports {user_port_wishbone_0_adr[8]}]

# user_port_wishbone_0:0.adr
set_property LOC X [get_ports {user_port_wishbone_0_adr[9]}]

# user_port_wishbone_0:0.adr
set_property LOC X [get_ports {user_port_wishbone_0_adr[10]}]

# user_port_wishbone_0:0.adr
set_property LOC X [get_ports {user_port_wishbone_0_adr[11]}]

# user_port_wishbone_0:0.adr
set_property LOC X [get_ports {user_port_wishbone_0_adr[12]}]

# user_port_wishbone_0:0.adr
set_property LOC X [get_ports {user_port_wishbone_0_adr[13]}]

# user_port_wishbone_0:0.adr
set_property LOC X [get_ports {user_port_wishbone_0_adr[14]}]

# user_port_wishbone_0:0.adr
set_property LOC X [get_ports {user_port_wishbone_0_adr[15]}]

# user_port_wishbone_0:0.adr
set_property LOC X [get_ports {user_port_wishbone_0_adr[16]}]

# user_port_wishbone_0:0.adr
set_property LOC X [get_ports {user_port_wishbone_0_adr[17]}]

# user_port_wishbone_0:0.adr
set_property LOC X [get_ports {user_port_wishbone_0_adr[18]}]

# user_port_wishbone_0:0.adr
set_property LOC X [get_ports {user_port_wishbone_0_adr[19]}]

# user_port_wishbone_0:0.adr
set_property LOC X [get_ports {user_port_wishbone_0_adr[20]}]

# user_port_wishbone_0:0.adr
set_property LOC X [get_ports {user_port_wishbone_0_adr[21]}]

# user_port_wishbone_0:0.adr
set_property LOC X [get_ports {user_port_wishbone_0_adr[22]}]

# user_port_wishbone_0:0.adr
set_property LOC X [get_ports {user_port_wishbone_0_adr[23]}]

# user_port_wishbone_0:0.adr
set_property LOC X [get_ports {user_port_wishbone_0_adr[24]}]

# user_port_wishbone_0:0.adr
set_property LOC X [get_ports {user_port_wishbone_0_adr[25]}]

# user_port_wishbone_0:0.adr
set_property LOC X [get_ports {user_port_wishbone_0_adr[26]}]

# user_port_wishbone_0:0.adr
set_property LOC X [get_ports {user_port_wishbone_0_adr[27]}]

# user_port_wishbone_0:0.dat_w
set_property LOC X [get_ports {user_port_wishbone_0_dat_w[0]}]

# user_port_wishbone_0:0.dat_w
set_property LOC X [get_ports {user_port_wishbone_0_dat_w[1]}]

# user_port_wishbone_0:0.dat_w
set_property LOC X [get_ports {user_port_wishbone_0_dat_w[2]}]

# user_port_wishbone_0:0.dat_w
set_property LOC X [get_ports {user_port_wishbone_0_dat_w[3]}]

# user_port_wishbone_0:0.dat_w
set_property LOC X [get_ports {user_port_wishbone_0_dat_w[4]}]

# user_port_wishbone_0:0.dat_w
set_property LOC X [get_ports {user_port_wishbone_0_dat_w[5]}]

# user_port_wishbone_0:0.dat_w
set_property LOC X [get_ports {user_port_wishbone_0_dat_w[6]}]

# user_port_wishbone_0:0.dat_w
set_property LOC X [get_ports {user_port_wishbone_0_dat_w[7]}]

# user_port_wishbone_0:0.dat_w
set_property LOC X [get_ports {user_port_wishbone_0_dat_w[8]}]

# user_port_wishbone_0:0.dat_w
set_property LOC X [get_ports {user_port_wishbone_0_dat_w[9]}]

# user_port_wishbone_0:0.dat_w
set_property LOC X [get_ports {user_port_wishbone_0_dat_w[10]}]

# user_port_wishbone_0:0.dat_w
set_property LOC X [get_ports {user_port_wishbone_0_dat_w[11]}]

# user_port_wishbone_0:0.dat_w
set_property LOC X [get_ports {user_port_wishbone_0_dat_w[12]}]

# user_port_wishbone_0:0.dat_w
set_property LOC X [get_ports {user_port_wishbone_0_dat_w[13]}]

# user_port_wishbone_0:0.dat_w
set_property LOC X [get_ports {user_port_wishbone_0_dat_w[14]}]

# user_port_wishbone_0:0.dat_w
set_property LOC X [get_ports {user_port_wishbone_0_dat_w[15]}]

# user_port_wishbone_0:0.dat_w
set_property LOC X [get_ports {user_port_wishbone_0_dat_w[16]}]

# user_port_wishbone_0:0.dat_w
set_property LOC X [get_ports {user_port_wishbone_0_dat_w[17]}]

# user_port_wishbone_0:0.dat_w
set_property LOC X [get_ports {user_port_wishbone_0_dat_w[18]}]

# user_port_wishbone_0:0.dat_w
set_property LOC X [get_ports {user_port_wishbone_0_dat_w[19]}]

# user_port_wishbone_0:0.dat_w
set_property LOC X [get_ports {user_port_wishbone_0_dat_w[20]}]

# user_port_wishbone_0:0.dat_w
set_property LOC X [get_ports {user_port_wishbone_0_dat_w[21]}]

# user_port_wishbone_0:0.dat_w
set_property LOC X [get_ports {user_port_wishbone_0_dat_w[22]}]

# user_port_wishbone_0:0.dat_w
set_property LOC X [get_ports {user_port_wishbone_0_dat_w[23]}]

# user_port_wishbone_0:0.dat_w
set_property LOC X [get_ports {user_port_wishbone_0_dat_w[24]}]

# user_port_wishbone_0:0.dat_w
set_property LOC X [get_ports {user_port_wishbone_0_dat_w[25]}]

# user_port_wishbone_0:0.dat_w
set_property LOC X [get_ports {user_port_wishbone_0_dat_w[26]}]

# user_port_wishbone_0:0.dat_w
set_property LOC X [get_ports {user_port_wishbone_0_dat_w[27]}]

# user_port_wishbone_0:0.dat_w
set_property LOC X [get_ports {user_port_wishbone_0_dat_w[28]}]

# user_port_wishbone_0:0.dat_w
set_property LOC X [get_ports {user_port_wishbone_0_dat_w[29]}]

# user_port_wishbone_0:0.dat_w
set_property LOC X [get_ports {user_port_wishbone_0_dat_w[30]}]

# user_port_wishbone_0:0.dat_w
set_property LOC X [get_ports {user_port_wishbone_0_dat_w[31]}]

# user_port_wishbone_0:0.dat_r
set_property LOC X [get_ports {user_port_wishbone_0_dat_r[0]}]

# user_port_wishbone_0:0.dat_r
set_property LOC X [get_ports {user_port_wishbone_0_dat_r[1]}]

# user_port_wishbone_0:0.dat_r
set_property LOC X [get_ports {user_port_wishbone_0_dat_r[2]}]

# user_port_wishbone_0:0.dat_r
set_property LOC X [get_ports {user_port_wishbone_0_dat_r[3]}]

# user_port_wishbone_0:0.dat_r
set_property LOC X [get_ports {user_port_wishbone_0_dat_r[4]}]

# user_port_wishbone_0:0.dat_r
set_property LOC X [get_ports {user_port_wishbone_0_dat_r[5]}]

# user_port_wishbone_0:0.dat_r
set_property LOC X [get_ports {user_port_wishbone_0_dat_r[6]}]

# user_port_wishbone_0:0.dat_r
set_property LOC X [get_ports {user_port_wishbone_0_dat_r[7]}]

# user_port_wishbone_0:0.dat_r
set_property LOC X [get_ports {user_port_wishbone_0_dat_r[8]}]

# user_port_wishbone_0:0.dat_r
set_property LOC X [get_ports {user_port_wishbone_0_dat_r[9]}]

# user_port_wishbone_0:0.dat_r
set_property LOC X [get_ports {user_port_wishbone_0_dat_r[10]}]

# user_port_wishbone_0:0.dat_r
set_property LOC X [get_ports {user_port_wishbone_0_dat_r[11]}]

# user_port_wishbone_0:0.dat_r
set_property LOC X [get_ports {user_port_wishbone_0_dat_r[12]}]

# user_port_wishbone_0:0.dat_r
set_property LOC X [get_ports {user_port_wishbone_0_dat_r[13]}]

# user_port_wishbone_0:0.dat_r
set_property LOC X [get_ports {user_port_wishbone_0_dat_r[14]}]

# user_port_wishbone_0:0.dat_r
set_property LOC X [get_ports {user_port_wishbone_0_dat_r[15]}]

# user_port_wishbone_0:0.dat_r
set_property LOC X [get_ports {user_port_wishbone_0_dat_r[16]}]

# user_port_wishbone_0:0.dat_r
set_property LOC X [get_ports {user_port_wishbone_0_dat_r[17]}]

# user_port_wishbone_0:0.dat_r
set_property LOC X [get_ports {user_port_wishbone_0_dat_r[18]}]

# user_port_wishbone_0:0.dat_r
set_property LOC X [get_ports {user_port_wishbone_0_dat_r[19]}]

# user_port_wishbone_0:0.dat_r
set_property LOC X [get_ports {user_port_wishbone_0_dat_r[20]}]

# user_port_wishbone_0:0.dat_r
set_property LOC X [get_ports {user_port_wishbone_0_dat_r[21]}]

# user_port_wishbone_0:0.dat_r
set_property LOC X [get_ports {user_port_wishbone_0_dat_r[22]}]

# user_port_wishbone_0:0.dat_r
set_property LOC X [get_ports {user_port_wishbone_0_dat_r[23]}]

# user_port_wishbone_0:0.dat_r
set_property LOC X [get_ports {user_port_wishbone_0_dat_r[24]}]

# user_port_wishbone_0:0.dat_r
set_property LOC X [get_ports {user_port_wishbone_0_dat_r[25]}]

# user_port_wishbone_0:0.dat_r
set_property LOC X [get_ports {user_port_wishbone_0_dat_r[26]}]

# user_port_wishbone_0:0.dat_r
set_property LOC X [get_ports {user_port_wishbone_0_dat_r[27]}]

# user_port_wishbone_0:0.dat_r
set_property LOC X [get_ports {user_port_wishbone_0_dat_r[28]}]

# user_port_wishbone_0:0.dat_r
set_property LOC X [get_ports {user_port_wishbone_0_dat_r[29]}]

# user_port_wishbone_0:0.dat_r
set_property LOC X [get_ports {user_port_wishbone_0_dat_r[30]}]

# user_port_wishbone_0:0.dat_r
set_property LOC X [get_ports {user_port_wishbone_0_dat_r[31]}]

# user_port_wishbone_0:0.sel
set_property LOC X [get_ports {user_port_wishbone_0_sel[0]}]

# user_port_wishbone_0:0.sel
set_property LOC X [get_ports {user_port_wishbone_0_sel[1]}]

# user_port_wishbone_0:0.sel
set_property LOC X [get_ports {user_port_wishbone_0_sel[2]}]

# user_port_wishbone_0:0.sel
set_property LOC X [get_ports {user_port_wishbone_0_sel[3]}]

# user_port_wishbone_0:0.cyc
set_property LOC X [get_ports {user_port_wishbone_0_cyc}]

# user_port_wishbone_0:0.stb
set_property LOC X [get_ports {user_port_wishbone_0_stb}]

# user_port_wishbone_0:0.ack
set_property LOC X [get_ports {user_port_wishbone_0_ack}]

# user_port_wishbone_0:0.we
set_property LOC X [get_ports {user_port_wishbone_0_we}]

# user_port_wishbone_0:0.err
set_property LOC X [get_ports {user_port_wishbone_0_err}]

################################################################################
# Design constraints
################################################################################

################################################################################
# Clock constraints
################################################################################


################################################################################
# False path constraints
################################################################################


set_false_path -quiet -through [get_nets -hierarchical -filter {mr_ff == TRUE}]

set_false_path -quiet -to [get_pins -filter {REF_PIN_NAME == PRE} -of_objects [get_cells -hierarchical -filter {ars_ff1 == TRUE || ars_ff2 == TRUE}]]

set_max_delay 2 -quiet -from [get_pins -filter {REF_PIN_NAME == C} -of_objects [get_cells -hierarchical -filter {ars_ff1 == TRUE}]] -to [get_pins -filter {REF_PIN_NAME == D} -of_objects [get_cells -hierarchical -filter {ars_ff2 == TRUE}]]