{
    # General ------------------------------------------------------------------
    "speedgrade": -2,         # FPGA speedgrade
    "cpu":        "vexriscv", # CPU type (ex vexriscv, serv, None)
    "memtype":    "DDR3",     # DRAM type
    "uart":       "rs232",    # Type of UART interface (rs232, fifo)

    # PHY ----------------------------------------------------------------------
    "cmd_latency":     1,             # Command additional latency
    "sdram_module":    "MT41K256M16", # SDRAM modules of the board or SO-DIMM
    "sdram_module_nb": 4,             # Number of byte groups
    "sdram_rank_nb":   1,             # Number of ranks
    "sdram_phy":       K7DDRPHY,      # Type of FPGA PHY

    # Electrical ---------------------------------------------------------------
    "rtt_nom": "60ohm", # Nominal termination
    "rtt_wr":  "60ohm", # Write termination
    "ron":     "34ohm", # Output driver impedance

    # Frequency ----------------------------------------------------------------
    "input_clk_freq":   100e6, # Input clock frequency
    "sys_clk_freq":     200e6, # System clock frequency (DDR_clk = 4 x sys_clk)
    "iodelay_clk_freq": 200e6, # IODELAYs reference clock frequency

    # Core ---------------------------------------------------------------------
    "cmd_buffer_depth": 16,    # Depth of the command buffer

    # User Ports ---------------------------------------------------------------
    "user_ports": {
        "wishbone_0" : {
            "type": "wishbone",
            "data_width": 32,
            "block_until_ready": True,
        },
    },
}
