set_property SRC_FILE_INFO {cfile:/eda/projetos/Risco-5-family/Grande-Risco-5/fpga/vc709/ip/clk_wiz_0/clk_wiz_0.xdc rfile:../ip/clk_wiz_0/clk_wiz_0.xdc id:1 order:EARLY} [current_design]
set_property SRC_FILE_INFO {cfile:/eda/projetos/Risco-5-family/Grande-Risco-5/fpga/vc709/pinout.xdc rfile:../pinout.xdc id:2 order:EARLY} [current_design]
set_property src_info {type:XDC file:1 line:53 export:INPUT save:INPUT read:READ} [current_design]
create_clock -period 5.000 [get_ports clk_in1]
set_property src_info {type:XDC file:1 line:54 export:INPUT save:INPUT read:READ} [current_design]
set_input_jitter [get_clocks -of_objects [get_ports clk_in1]] 0.050
set_property src_info {type:XDC file:2 line:11 export:INPUT save:INPUT read:READ} [current_design]
set_property PACKAGE_PIN H19 [get_ports clk_ref_p]
set_property src_info {type:XDC file:2 line:12 export:INPUT save:INPUT read:READ} [current_design]
set_property PACKAGE_PIN G18 [get_ports clk_ref_n]
set_property src_info {type:XDC file:2 line:14 export:INPUT save:INPUT read:READ} [current_design]
create_clock -period 6.400 -name xgemac_clk_156 [get_ports xphy_refclk_p]
set_property src_info {type:XDC file:2 line:17 export:INPUT save:INPUT read:READ} [current_design]
set_property PACKAGE_PIN AH8 [get_ports xphy_refclk_p]
set_property src_info {type:XDC file:2 line:18 export:INPUT save:INPUT read:READ} [current_design]
set_property PACKAGE_PIN AH7 [get_ports xphy_refclk_n]
set_property src_info {type:XDC file:2 line:21 export:INPUT save:INPUT read:READ} [current_design]
create_generated_clock -name clk50 -source [get_ports clk_ref_p] -divide_by 4 [get_pins n10g_interface_inst/clk_divide_reg[1]/Q]
set_property src_info {type:XDC file:2 line:26 export:INPUT save:INPUT read:READ} [current_design]
set_property PACKAGE_PIN AU38 [get_ports button_east]
set_property src_info {type:XDC file:2 line:27 export:INPUT save:INPUT read:READ} [current_design]
set_property IOSTANDARD LVCMOS18 [get_ports button_east]
set_property src_info {type:XDC file:2 line:28 export:INPUT save:INPUT read:READ} [current_design]
set_property PACKAGE_PIN AW40 [get_ports button_west]
set_property src_info {type:XDC file:2 line:29 export:INPUT save:INPUT read:READ} [current_design]
set_property IOSTANDARD LVCMOS18 [get_ports button_west]
set_property src_info {type:XDC file:2 line:31 export:INPUT save:INPUT read:READ} [current_design]
set_property PACKAGE_PIN AR40 [get_ports button_north]
set_property src_info {type:XDC file:2 line:32 export:INPUT save:INPUT read:READ} [current_design]
set_property IOSTANDARD LVCMOS18 [get_ports button_north]
set_property src_info {type:XDC file:2 line:33 export:INPUT save:INPUT read:READ} [current_design]
set_property PACKAGE_PIN AP40 [get_ports button_south]
set_property src_info {type:XDC file:2 line:34 export:INPUT save:INPUT read:READ} [current_design]
set_property IOSTANDARD LVCMOS18 [get_ports button_south]
set_property src_info {type:XDC file:2 line:35 export:INPUT save:INPUT read:READ} [current_design]
set_property PACKAGE_PIN AV39 [get_ports button_center]
set_property src_info {type:XDC file:2 line:40 export:INPUT save:INPUT read:READ} [current_design]
set_property PACKAGE_PIN AU36 [get_ports TxD]
set_property src_info {type:XDC file:2 line:43 export:INPUT save:INPUT read:READ} [current_design]
set_property PACKAGE_PIN AU33 [get_ports RxD]
set_property src_info {type:XDC file:2 line:51 export:INPUT save:INPUT read:READ} [current_design]
create_clock -name clk156 -period 6.400 [get_pins n10g_interface_inst/xgbaser_gt_wrapper_inst/clk156_bufg_inst/O]
set_property src_info {type:XDC file:2 line:52 export:INPUT save:INPUT read:READ} [current_design]
create_clock -name dclk -period 12.800 [get_pins n10g_interface_inst/xgbaser_gt_wrapper_inst/dclk_bufg_inst/O]
set_property src_info {type:XDC file:2 line:53 export:INPUT save:INPUT read:READ} [current_design]
create_clock -name refclk -period 6.400 [get_pins n10g_interface_inst/xgphy_refclk_ibuf/O]
set_property src_info {type:XDC file:2 line:64 export:INPUT save:INPUT read:READ} [current_design]
set_property LOC AB41  [get_ports {sfp_tx_disable[0]}]
set_property src_info {type:XDC file:2 line:65 export:INPUT save:INPUT read:READ} [current_design]
set_property IOSTANDARD LVCMOS18 [get_ports {sfp_tx_disable[0]}]
set_property src_info {type:XDC file:2 line:66 export:INPUT save:INPUT read:READ} [current_design]
set_property LOC Y42  [get_ports {sfp_tx_disable[1]}]
set_property src_info {type:XDC file:2 line:67 export:INPUT save:INPUT read:READ} [current_design]
set_property IOSTANDARD LVCMOS18 [get_ports {sfp_tx_disable[1]}]
set_property src_info {type:XDC file:2 line:68 export:INPUT save:INPUT read:READ} [current_design]
set_property LOC AC38  [get_ports {sfp_tx_disable[2]}]
set_property src_info {type:XDC file:2 line:69 export:INPUT save:INPUT read:READ} [current_design]
set_property IOSTANDARD LVCMOS18 [get_ports {sfp_tx_disable[2]}]
set_property src_info {type:XDC file:2 line:70 export:INPUT save:INPUT read:READ} [current_design]
set_property LOC AC40  [get_ports {sfp_tx_disable[3]}]
set_property src_info {type:XDC file:2 line:71 export:INPUT save:INPUT read:READ} [current_design]
set_property IOSTANDARD LVCMOS18 [get_ports {sfp_tx_disable[3]}]
set_property src_info {type:XDC file:2 line:118 export:INPUT save:INPUT read:READ} [current_design]
set_property PACKAGE_PIN AP4 [get_ports xphy0_txp]
set_property src_info {type:XDC file:2 line:119 export:INPUT save:INPUT read:READ} [current_design]
set_property PACKAGE_PIN AP3 [get_ports xphy0_txn]
set_property src_info {type:XDC file:2 line:120 export:INPUT save:INPUT read:READ} [current_design]
set_property PACKAGE_PIN AN6 [get_ports xphy0_rxp]
set_property src_info {type:XDC file:2 line:121 export:INPUT save:INPUT read:READ} [current_design]
set_property PACKAGE_PIN AN5 [get_ports xphy0_rxn]
set_property src_info {type:XDC file:2 line:151 export:INPUT save:INPUT read:READ} [current_design]
set_property PACKAGE_PIN AM39 [get_ports {led[0]}]
set_property src_info {type:XDC file:2 line:152 export:INPUT save:INPUT read:READ} [current_design]
set_property PACKAGE_PIN AN39 [get_ports {led[1]}]
set_property src_info {type:XDC file:2 line:153 export:INPUT save:INPUT read:READ} [current_design]
set_property PACKAGE_PIN AR37 [get_ports {led[2]}]
set_property src_info {type:XDC file:2 line:154 export:INPUT save:INPUT read:READ} [current_design]
set_property PACKAGE_PIN AT37 [get_ports {led[3]}]
set_property src_info {type:XDC file:2 line:155 export:INPUT save:INPUT read:READ} [current_design]
set_property PACKAGE_PIN AR35 [get_ports {led[4]}]
set_property src_info {type:XDC file:2 line:156 export:INPUT save:INPUT read:READ} [current_design]
set_property PACKAGE_PIN AP41 [get_ports {led[5]}]
set_property src_info {type:XDC file:2 line:157 export:INPUT save:INPUT read:READ} [current_design]
set_property PACKAGE_PIN AP42 [get_ports {led[6]}]
set_property src_info {type:XDC file:2 line:158 export:INPUT save:INPUT read:READ} [current_design]
set_property PACKAGE_PIN AU39 [get_ports {led[7]}]
set_property src_info {type:XDC file:2 line:190 export:INPUT save:INPUT read:READ} [current_design]
set_property PACKAGE_PIN AV30 [get_ports {gpio_switch[0]}]
set_property src_info {type:XDC file:2 line:191 export:INPUT save:INPUT read:READ} [current_design]
set_property PACKAGE_PIN AY33 [get_ports {gpio_switch[1]}]
set_property src_info {type:XDC file:2 line:192 export:INPUT save:INPUT read:READ} [current_design]
set_property PACKAGE_PIN BA31 [get_ports {gpio_switch[2]}]
set_property src_info {type:XDC file:2 line:193 export:INPUT save:INPUT read:READ} [current_design]
set_property PACKAGE_PIN BA32 [get_ports {gpio_switch[3]}]
set_property src_info {type:XDC file:2 line:194 export:INPUT save:INPUT read:READ} [current_design]
set_property PACKAGE_PIN AW30 [get_ports {gpio_switch[4]}]
set_property src_info {type:XDC file:2 line:195 export:INPUT save:INPUT read:READ} [current_design]
set_property PACKAGE_PIN AY30 [get_ports {gpio_switch[5]}]
set_property src_info {type:XDC file:2 line:196 export:INPUT save:INPUT read:READ} [current_design]
set_property PACKAGE_PIN BA30 [get_ports {gpio_switch[6]}]
set_property src_info {type:XDC file:2 line:197 export:INPUT save:INPUT read:READ} [current_design]
set_property PACKAGE_PIN BB31 [get_ports {gpio_switch[7]}]
set_property src_info {type:XDC file:2 line:209 export:INPUT save:INPUT read:READ} [current_design]
set_property IOSTANDARD LVCMOS18 [get_ports i2c_clk]
set_property src_info {type:XDC file:2 line:210 export:INPUT save:INPUT read:READ} [current_design]
set_property SLEW SLOW [get_ports i2c_clk]
set_property src_info {type:XDC file:2 line:211 export:INPUT save:INPUT read:READ} [current_design]
set_property DRIVE 16 [get_ports i2c_clk]
set_property src_info {type:XDC file:2 line:212 export:INPUT save:INPUT read:READ} [current_design]
set_property PULLUP TRUE [get_ports i2c_clk]
set_property src_info {type:XDC file:2 line:213 export:INPUT save:INPUT read:READ} [current_design]
set_property LOC AT35 [get_ports i2c_clk]
set_property src_info {type:XDC file:2 line:215 export:INPUT save:INPUT read:READ} [current_design]
set_property IOSTANDARD LVCMOS18 [get_ports i2c_data]
set_property src_info {type:XDC file:2 line:216 export:INPUT save:INPUT read:READ} [current_design]
set_property SLEW SLOW [get_ports i2c_data]
set_property src_info {type:XDC file:2 line:217 export:INPUT save:INPUT read:READ} [current_design]
set_property DRIVE 16 [get_ports i2c_data]
set_property src_info {type:XDC file:2 line:218 export:INPUT save:INPUT read:READ} [current_design]
set_property PULLUP TRUE [get_ports i2c_data]
set_property src_info {type:XDC file:2 line:219 export:INPUT save:INPUT read:READ} [current_design]
set_property LOC AU32 [get_ports i2c_data]
set_property src_info {type:XDC file:2 line:221 export:INPUT save:INPUT read:READ} [current_design]
set_property IOSTANDARD LVCMOS18 [get_ports i2c_mux_rst_n]
set_property src_info {type:XDC file:2 line:222 export:INPUT save:INPUT read:READ} [current_design]
set_property SLEW SLOW [get_ports i2c_mux_rst_n]
set_property src_info {type:XDC file:2 line:223 export:INPUT save:INPUT read:READ} [current_design]
set_property DRIVE 16 [get_ports i2c_mux_rst_n]
set_property src_info {type:XDC file:2 line:224 export:INPUT save:INPUT read:READ} [current_design]
set_property LOC AY42 [get_ports i2c_mux_rst_n]
set_property src_info {type:XDC file:2 line:226 export:INPUT save:INPUT read:READ} [current_design]
set_property IOSTANDARD LVCMOS18 [get_ports si5324_rst_n]
set_property src_info {type:XDC file:2 line:227 export:INPUT save:INPUT read:READ} [current_design]
set_property SLEW SLOW [get_ports si5324_rst_n]
set_property src_info {type:XDC file:2 line:228 export:INPUT save:INPUT read:READ} [current_design]
set_property DRIVE 16 [get_ports si5324_rst_n]
set_property src_info {type:XDC file:2 line:229 export:INPUT save:INPUT read:READ} [current_design]
set_property LOC AT36 [get_ports si5324_rst_n]
set_property src_info {type:XDC file:2 line:233 export:INPUT save:INPUT read:READ} [current_design]
set_clock_groups -name async_mcb_xgemac -asynchronous -group [get_clocks  mcb_clk_ref] -group [get_clocks  clk156]
set_property src_info {type:XDC file:2 line:239 export:INPUT save:INPUT read:READ} [current_design]
set_clock_groups -name async_mig_ref_clk50 -asynchronous -group [get_clocks mcb_clk_ref] -group [get_clocks clk50]
set_property src_info {type:XDC file:2 line:257 export:INPUT save:INPUT read:READ} [current_design]
set_clock_groups -name async_xgemac_drpclk -asynchronous -group [get_clocks -include_generated_clocks clk156] -group [get_clocks -include_generated_clocks dclk]
set_property src_info {type:XDC file:2 line:261 export:INPUT save:INPUT read:READ} [current_design]
set_clock_groups -name async_xgemac_clk50 -asynchronous -group [get_clocks -include_generated_clocks clk156] -group [get_clocks clk50]
set_property src_info {type:XDC file:2 line:266 export:INPUT save:INPUT read:READ} [current_design]
create_clock -period 4.708 -name sys_clk [get_ports sys_clk_p]
set_property src_info {type:XDC file:2 line:269 export:INPUT save:INPUT read:READ} [current_design]
set_property VCCAUX_IO DONTCARE [get_ports {sys_clk_p}]
set_property src_info {type:XDC file:2 line:270 export:INPUT save:INPUT read:READ} [current_design]
set_property IOSTANDARD DIFF_SSTL15 [get_ports {sys_clk_p}]
set_property src_info {type:XDC file:2 line:271 export:INPUT save:INPUT read:READ} [current_design]
set_property PACKAGE_PIN AY18 [get_ports {sys_clk_p}]
set_property src_info {type:XDC file:2 line:274 export:INPUT save:INPUT read:READ} [current_design]
set_property VCCAUX_IO DONTCARE [get_ports {sys_clk_n}]
set_property src_info {type:XDC file:2 line:275 export:INPUT save:INPUT read:READ} [current_design]
set_property IOSTANDARD DIFF_SSTL15 [get_ports {sys_clk_n}]
set_property src_info {type:XDC file:2 line:276 export:INPUT save:INPUT read:READ} [current_design]
set_property PACKAGE_PIN AY17 [get_ports {sys_clk_n}]
set_property src_info {type:XDC file:2 line:282 export:INPUT save:INPUT read:READ} [current_design]
set_property PACKAGE_PIN AV40 [get_ports {sys_rst_i}]
set_property src_info {type:XDC file:2 line:285 export:INPUT save:INPUT read:READ} [current_design]
set_property CLOCK_DEDICATED_ROUTE BACKBONE [get_nets clk233]
set_property src_info {type:XDC file:2 line:287 export:INPUT save:INPUT read:READ} [current_design]
set_clock_groups -name clk156_pll_i -asynchronous -group [get_clocks clk_pll_i] -group [get_clocks clk156]
set_property src_info {type:XDC file:2 line:288 export:INPUT save:INPUT read:READ} [current_design]
set_clock_groups -name clk156_pll_i_1 -asynchronous -group [get_clocks clk_pll_i_1] -group [get_clocks clk156]
