Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
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| Tool Version : Vivado v.2023.2 (lin64) Build 4029153 Fri Oct 13 20:13:54 MDT 2023
| Date         : Mon Jun 29 21:24:40 2026
| Host         : 685a421e500f running 64-bit unknown
| Command      : report_control_sets -verbose -file digilent_arty_a7_control_sets.rpt
| Design       : fpga_top
| Device       : xc7a100t
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Control Set Information

Table of Contents
-----------------
1. Summary
2. Histogram
3. Flip-Flop Distribution
4. Detailed Control Set Information

1. Summary
----------

+----------------------------------------------------------+-------+
|                          Status                          | Count |
+----------------------------------------------------------+-------+
| Total control sets                                       |   127 |
|    Minimum number of control sets                        |   127 |
|    Addition due to synthesis replication                 |     0 |
|    Addition due to physical synthesis replication        |     0 |
| Unused register locations in slices containing registers |   134 |
+----------------------------------------------------------+-------+
* Control sets can be merged at opt_design using control_set_merge or merge_equivalent_drivers
** Run report_qor_suggestions for automated merging and remapping suggestions


2. Histogram
------------

+--------------------+-------+
|       Fanout       | Count |
+--------------------+-------+
| Total control sets |   127 |
| >= 0 to < 4        |     2 |
| >= 4 to < 6        |     8 |
| >= 6 to < 8        |     2 |
| >= 8 to < 10       |    12 |
| >= 10 to < 12      |     4 |
| >= 12 to < 14      |     3 |
| >= 14 to < 16      |     1 |
| >= 16              |    95 |
+--------------------+-------+
* Control sets can be remapped at either synth_design or opt_design


3. Flip-Flop Distribution
-------------------------

+--------------+-----------------------+------------------------+-----------------+--------------+
| Clock Enable | Synchronous Set/Reset | Asynchronous Set/Reset | Total Registers | Total Slices |
+--------------+-----------------------+------------------------+-----------------+--------------+
| No           | No                    | No                     |              94 |           36 |
| No           | No                    | Yes                    |               0 |            0 |
| No           | Yes                   | No                     |             588 |          258 |
| Yes          | No                    | No                     |            1757 |          902 |
| Yes          | No                    | Yes                    |              32 |            8 |
| Yes          | Yes                   | No                     |            1091 |          358 |
+--------------+-----------------------+------------------------+-----------------+--------------+


4. Detailed Control Set Information
-----------------------------------

+--------------------------------------+-----------------------------------------------------------------------------------+---------------------------------------------------------------+------------------+----------------+--------------+
|             Clock Signal             |                                   Enable Signal                                   |                        Set/Reset Signal                       | Slice Load Count | Bel Load Count | Bels / Slice |
+--------------------------------------+-----------------------------------------------------------------------------------+---------------------------------------------------------------+------------------+----------------+--------------+
|  clk_IBUF_BUFG                       |                                                                                   |                                                               |                1 |              1 |         1.00 |
|  clk_o_BUFG                          | ptop/u_Controller/Uart/i_uart_tx/txd_reg_i_2_n_0                                  | ptop/u_Controller/Uart/i_uart_tx/txd_reg_i_1_n_0              |                1 |              1 |         1.00 |
|  u_Controller/ClkDivider/clk_o_pulse | ptop/Processor/Core1/IDEX_Stage/Mdu/E[0]                                          |                                                               |                2 |              4 |         2.00 |
|  u_Controller/ClkDivider/clk_o_pulse | ptop/Processor/Core1/EXMEM_Stage/FSM_sequential_unaligned_access_state[3]_i_2_n_0 | ptop/Processor/Core1/IDEX_Stage/take_jalr_reg_2               |                3 |              4 |         1.33 |
|  clk_o_BUFG                          | ptop/u_Controller/Uart/i_uart_tx/E[0]                                             |                                                               |                1 |              4 |         4.00 |
|  clk_o_BUFG                          | ptop/u_Controller/Uart/i_uart_tx/bit_counter[3]_i_2__0_n_0                        | ptop/u_Controller/Uart/i_uart_tx/bit_counter[3]_i_1__0_n_0    |                1 |              4 |         4.00 |
|  clk_o_BUFG                          | ptop/u_Controller/Uart/i_uart_rx/next_bit                                         | ptop/u_Controller/Uart/i_uart_rx/bit_counter[3]_i_1_n_0       |                1 |              4 |         4.00 |
|  clk_o_BUFG                          |                                                                                   |                                                               |                3 |              5 |         1.67 |
|  clk_o_BUFG                          | ptop/u_Controller/Interpreter/return_state                                        | ResetBootSystem/rst_o_reg_0                                   |                2 |              5 |         2.50 |
|  clk_o_BUFG                          | ResetBootSystem/counter                                                           |                                                               |                2 |              5 |         2.50 |
|  u_Controller/ClkDivider/clk_o_pulse | ptop/Processor/Core1/IDEX_Stage/Mdu/take_jalr_reg_7                               | ptop/Processor/Core1/IFID_Stage/IFID_IR_o_reg[4]_0            |                2 |              6 |         3.00 |
|  clk_o_BUFG                          | ptop/u_Controller/Uart/i_uart_tx/data_to_send[6]_i_1_n_0                          | ResetBootSystem/rst_o_reg_0                                   |                2 |              7 |         3.50 |
|  u_Controller/ClkDivider/clk_o_pulse |                                                                                   | ptop/u_Controller/Interpreter/SR[0]                           |                3 |              8 |         2.67 |
|  clk_o_BUFG                          | ptop/u_Controller/Uart/uart_tx_en                                                 | ResetBootSystem/rst_o_reg_0                                   |                1 |              8 |         8.00 |
|  clk_o_BUFG                          | ptop/u_Controller/Interpreter/accumulator[7]_i_1_n_0                              | ResetBootSystem/rst_o_reg_0                                   |                1 |              8 |         8.00 |
|  u_Controller/ClkDivider/clk_o_pulse | ptop/Processor/Core1/EXMEM_Stage/EXMEM_mem_data_value[7]_i_1_n_0                  |                                                               |                3 |              8 |         2.67 |
|  clk_o_BUFG                          | ptop/u_Controller/Uart/i_uart_rx/uart_rx_data[7]_i_1_n_0                          | ResetBootSystem/rst_o_reg_0                                   |                1 |              8 |         8.00 |
|  clk_o_BUFG                          | ptop/u_Controller/Uart/i_uart_rx/E[0]                                             | ResetBootSystem/rst_o_reg_0                                   |                2 |              8 |         4.00 |
|  clk_o_BUFG                          | ptop/u_Controller/Uart/tx_fifo/FSM_sequential_state_write_reg[2][0]               | ResetBootSystem/rst_o_reg_0                                   |                1 |              8 |         8.00 |
|  u_Controller/ClkDivider/clk_o_pulse | ptop/Processor/Core1/EXMEM_Stage/Merged_Word_o[7]_i_1_n_0                         |                                                               |                3 |              8 |         2.67 |
|  u_Controller/ClkDivider/clk_o_pulse | ptop/Processor/Core1/EXMEM_Stage/EXMEM_mem_data_value[15]_i_1_n_0                 |                                                               |                6 |              8 |         1.33 |
|  clk_o_BUFG                          | ptop/u_Controller/Interpreter/counter                                             | ResetBootSystem/rst_o_reg_0                                   |                4 |              8 |         2.00 |
|  u_Controller/ClkDivider/clk_o_pulse | ptop/Processor/Core1/EXMEM_Stage/Merged_Word_o[15]_i_1_n_0                        |                                                               |                6 |              8 |         1.33 |
|  clk_o_BUFG                          | ptop/u_Controller/Uart/i_uart_rx/recieved_data0                                   | ptop/u_Controller/Uart/i_uart_rx/recieved_data[7]_i_1_n_0     |                1 |              8 |         8.00 |
|  clk_o_BUFG                          | ptop/u_Controller/Uart/i_uart_tx/txd_reg_i_2_n_0                                  | ResetBootSystem/SR[0]                                         |                2 |             10 |         5.00 |
|  clk_o_BUFG                          | ptop/u_Controller/Uart/i_uart_rx/cycle_counter0                                   | ptop/u_Controller/Uart/i_uart_rx/cycle_counter[9]_i_1__0_n_0  |                3 |             10 |         3.33 |
|  clk_o_BUFG                          | ptop/u_Controller/Uart/rx_fifo/read_ptr0                                          | ResetBootSystem/rst_o_reg_0                                   |                3 |             11 |         3.67 |
|  clk_o_BUFG                          | ptop/u_Controller/Uart/tx_fifo/read_ptr[2]_i_1_n_0                                | ResetBootSystem/rst_o_reg_0                                   |                3 |             11 |         3.67 |
|  clk_o_BUFG                          | ptop/u_Controller/Uart/tx_fifo/memory_reg_0_7_0_5_i_1_n_0                         |                                                               |                2 |             12 |         6.00 |
|  clk_o_BUFG                          | ptop/u_Controller/Interpreter/address[31]_i_1_n_0                                 |                                                               |                8 |             12 |         1.50 |
|  clk_o_BUFG                          | ptop/u_Controller/Uart/rx_fifo/memory_reg_0_7_0_5_i_1__0_n_0                      |                                                               |                2 |             12 |         6.00 |
|  u_Controller/ClkDivider/clk_o_pulse | ptop/Processor/Core1/IDEX_Stage/Mdu/FSM_onehot_state_mul[1]_i_1_n_0               | ptop/u_Controller/Interpreter/rst_core                        |                3 |             15 |         5.00 |
|  u_Controller/ClkDivider/clk_o_pulse | ptop/Processor/Core1/EXMEM_Stage/EXMEM_mem_data_value[31]_i_1_n_0                 |                                                               |                8 |             16 |         2.00 |
|  u_Controller/ClkDivider/clk_o_pulse | ptop/Processor/Core1/EXMEM_Stage/Merged_Word_o[31]_i_1_n_0                        |                                                               |                6 |             16 |         2.67 |
|  u_Controller/ClkDivider/clk_o_pulse | ptop/Processor/Core1/EXMEM_Stage/EXMEMIR_o[14]_i_2_n_0                            | ptop/Processor/Core1/EXMEM_Stage/EXMEMIR_o[14]_i_1_n_0        |                6 |             22 |         3.67 |
|  clk_o_BUFG                          | ptop/u_Controller/Interpreter/num_of_pages                                        | ResetBootSystem/rst_o_reg_0                                   |                6 |             24 |         4.00 |
|  clk_o_BUFG                          | ptop/u_Controller/Interpreter/accumulator0                                        | ResetBootSystem/rst_o_reg_0                                   |                5 |             24 |         4.80 |
|  clk_o_BUFG                          | ptop/u_Controller/Interpreter/num_of_cycles_to_pulse[23]_i_1_n_0                  |                                                               |                9 |             24 |         2.67 |
|  clk_o_BUFG                          | ptop/u_Controller/Interpreter/memory_page_number[23]_i_2_n_0                      | ptop/u_Controller/Interpreter/memory_page_number[23]_i_1_n_0  |                7 |             24 |         3.43 |
|  clk_o_BUFG                          | ptop/u_Controller/Interpreter/timeout                                             | ResetBootSystem/rst_o_reg_0                                   |                4 |             24 |         6.00 |
|  u_Controller/ClkDivider/clk_o_pulse | ptop/Processor/Core1/IDEX_Stage/Mdu/take_jalr_reg_7                               | ptop/Processor/Core1/IFID_Stage/IFID_IR_o_reg[0]_0            |               10 |             25 |         2.50 |
|  u_Controller/ClkDivider/clk_o_pulse | ptop/Processor/Core1/IDEX_Stage/Mdu/quociente                                     | ptop/u_Controller/Interpreter/rst_core                        |                8 |             32 |         4.00 |
|  u_Controller/ClkDivider/clk_o_pulse | ptop/Processor/Core1/MEMWB_Stage/registers_reg[18]0                               |                                                               |               19 |             32 |         1.68 |
|  u_Controller/ClkDivider/clk_o_pulse | ptop/Processor/Core1/EXMEM_Stage/First_Word[31]_i_1_n_0                           |                                                               |               11 |             32 |         2.91 |
|  u_Controller/ClkDivider/clk_o_pulse | ptop/Processor/Core1/MEMWB_Stage/registers_reg[27]0                               |                                                               |               24 |             32 |         1.33 |
|  u_Controller/ClkDivider/clk_o_pulse | ptop/Processor/M1/i_cache_read_data[31]_i_1_n_0                                   |                                                               |               12 |             32 |         2.67 |
|  u_Controller/ClkDivider/clk_o_pulse | ptop/Processor/Core1/MEMWB_Stage/registers_reg[6]0                                |                                                               |               19 |             32 |         1.68 |
|  u_Controller/ClkDivider/clk_o_pulse | ptop/Processor/Core1/IDEX_Stage/Mdu/mul_ready_o                                   | ptop/u_Controller/Interpreter/rst_core                        |                9 |             32 |         3.56 |
|  u_Controller/ClkDivider/clk_o_pulse | ptop/Processor/Core1/MEMWB_Stage/registers_reg[29]0                               |                                                               |               19 |             32 |         1.68 |
|  u_Controller/ClkDivider/clk_o_pulse | ptop/Processor/Core1/MEMWB_Stage/registers_reg[19]0                               |                                                               |               22 |             32 |         1.45 |
|  u_Controller/ClkDivider/clk_o_pulse | ptop/Processor/Core1/EXMEM_Stage/Second_Word[31]_i_1_n_0                          |                                                               |               10 |             32 |         3.20 |
|  u_Controller/ClkDivider/clk_o_pulse | ptop/Processor/Core1/MEMWB_Stage/registers_reg[2]0                                |                                                               |               18 |             32 |         1.78 |
|  u_Controller/ClkDivider/clk_o_pulse | ptop/Processor/Core1/MEMWB_Stage/registers_reg[24]0                               |                                                               |               20 |             32 |         1.60 |
|  u_Controller/ClkDivider/clk_o_pulse | ptop/Processor/Core1/MEMWB_Stage/registers_reg[5]0                                |                                                               |               19 |             32 |         1.68 |
|  u_Controller/ClkDivider/clk_o_pulse | ptop/Processor/Core1/MEMWB_Stage/registers_reg[1]0                                |                                                               |               24 |             32 |         1.33 |
|  u_Controller/ClkDivider/clk_o_pulse | ptop/Processor/Core1/MEMWB_Stage/registers_reg[13]0                               |                                                               |               17 |             32 |         1.88 |
|  u_Controller/ClkDivider/clk_o_pulse | ptop/Processor/Core1/MEMWB_Stage/registers_reg[11]0                               |                                                               |               18 |             32 |         1.78 |
|  u_Controller/ClkDivider/clk_o_pulse | ptop/Processor/Core1/MEMWB_Stage/registers_reg[8]0                                |                                                               |               21 |             32 |         1.52 |
|  u_Controller/ClkDivider/clk_o_pulse | ptop/Processor/Core1/MEMWB_Stage/registers_reg[17]0                               |                                                               |               18 |             32 |         1.78 |
|  u_Controller/ClkDivider/clk_o_pulse | ptop/Processor/M1/d_cache_read_data[31]_i_1_n_0                                   |                                                               |               11 |             32 |         2.91 |
|  u_Controller/ClkDivider/clk_o_pulse | ptop/Processor/Core1/IDEX_Stage/Mdu/dividendo[31]_i_1_n_0                         |                                                               |               11 |             32 |         2.91 |
|  u_Controller/ClkDivider/clk_o_pulse | ptop/Processor/Core1/IDEX_Stage/Mdu/DIV_RD[31]_i_1_n_0                            |                                                               |                9 |             32 |         3.56 |
|  u_Controller/ClkDivider/clk_o_pulse | ptop/Processor/Core1/MEMWB_Stage/registers_reg[30]0                               |                                                               |               22 |             32 |         1.45 |
|  u_Controller/ClkDivider/clk_o_pulse | ptop/Processor/Core1/IDEX_Stage/IDEXIR_o_reg[26]_1[0]                             | ptop/u_Controller/Interpreter/rst_core                        |               12 |             32 |         2.67 |
|  u_Controller/ClkDivider/clk_o_pulse | ptop/Processor/Core1/MEMWB_Stage/registers_reg[31]0                               |                                                               |               21 |             32 |         1.52 |
|  u_Controller/ClkDivider/clk_o_pulse | ptop/Processor/Core1/MEMWB_Stage/registers_reg[28]0                               |                                                               |               22 |             32 |         1.45 |
|  u_Controller/ClkDivider/clk_o_pulse | ptop/Processor/M1/write_data                                                      |                                                               |               13 |             32 |         2.46 |
|  u_Controller/ClkDivider/clk_o_pulse | ptop/Processor/Core1/MEMWB_Stage/registers_reg[9]0                                |                                                               |               19 |             32 |         1.68 |
|  u_Controller/ClkDivider/clk_o_pulse | ptop/Processor/Core1/MEMWB_Stage/registers_reg[26]0                               |                                                               |               19 |             32 |         1.68 |
|  u_Controller/ClkDivider/clk_o_pulse | ptop/Processor/Core1/IDEX_Stage/IDEXIR_o_reg[25]_0[0]                             | ptop/u_Controller/Interpreter/rst_core                        |               11 |             32 |         2.91 |
|  u_Controller/ClkDivider/clk_o_pulse | ptop/Processor/Core1/MEMWB_Stage/registers_reg[14]0                               |                                                               |               15 |             32 |         2.13 |
|  u_Controller/ClkDivider/clk_o_pulse | ptop/Processor/Core1/MEMWB_Stage/registers_reg[10]0                               |                                                               |               18 |             32 |         1.78 |
|  u_Controller/ClkDivider/clk_o_pulse | ptop/Processor/Core1/MEMWB_Stage/registers_reg[20]0                               |                                                               |               19 |             32 |         1.68 |
|  u_Controller/ClkDivider/clk_o_pulse | ptop/Processor/Core1/MEMWB_Stage/registers_reg[7]0                                |                                                               |               20 |             32 |         1.60 |
|  u_Controller/ClkDivider/clk_o_pulse | ptop/Processor/Core1/MEMWB_Stage/registers_reg[25]0                               |                                                               |               18 |             32 |         1.78 |
|  u_Controller/ClkDivider/clk_o_pulse | ptop/Processor/Core1/MEMWB_Stage/registers_reg[21]0                               |                                                               |               21 |             32 |         1.52 |
|  u_Controller/ClkDivider/clk_o_pulse | ptop/Processor/Core1/MEMWB_Stage/registers_reg[4]0                                |                                                               |               19 |             32 |         1.68 |
|  u_Controller/ClkDivider/clk_o_pulse | ptop/Processor/Core1/MEMWB_Stage/registers_reg[22]0                               |                                                               |               20 |             32 |         1.60 |
|  clk_o_BUFG                          | ptop/u_Controller/Uart/tx_fifo/E[0]                                               | ResetBootSystem/rst_o_reg_0                                   |                7 |             32 |         4.57 |
|  clk_o_BUFG                          | ptop/u_Controller/Interpreter/end_position[31]_i_1_n_0                            | ResetBootSystem/rst_o_reg_0                                   |                8 |             32 |         4.00 |
|  clk_o_BUFG                          | ptop/u_Controller/Uart/rx_fifo/E[0]                                               | ResetBootSystem/rst_o_reg_0                                   |                5 |             32 |         6.40 |
|  clk_o_BUFG                          | ptop/u_Controller/Interpreter/communication_buffer[31]_i_1_n_0                    | ResetBootSystem/rst_o_reg_0                                   |                7 |             32 |         4.57 |
|  clk_o_BUFG                          | ptop/u_Controller/Interpreter/timeout_counter                                     | ResetBootSystem/rst_o_reg_0                                   |                7 |             32 |         4.57 |
|  clk_o_BUFG                          | ptop/u_Controller/Interpreter/communication_write_data[31]_i_1_n_0                |                                                               |               13 |             32 |         2.46 |
|  clk_o_BUFG                          | ptop/u_Controller/ClkDivider/pulse_counter[0]_i_1_n_0                             | ResetBootSystem/rst_o_reg_0                                   |                8 |             32 |         4.00 |
|  clk_o_BUFG                          | ptop/u_Controller/Interpreter/read_buffer                                         | ResetBootSystem/rst_o_reg_0                                   |               16 |             32 |         2.00 |
|  clk_o_BUFG                          | ptop/u_Controller/Interpreter/write_data[31]_i_1_n_0                              |                                                               |               13 |             32 |         2.46 |
|  u_Controller/ClkDivider/clk_o_pulse | ptop/Processor/Core1/IFID_Stage/IFID_is_compressed_instruction_o112_out           | ptop/Processor/Core1/IFID_Stage/IFID_IR_o[31]_i_1_n_0         |               24 |             32 |         1.33 |
|  u_Controller/ClkDivider/clk_o_pulse | ptop/Processor/Core1/IFID_Stage/IFID_PC_o[31]_i_2_n_0                             | ptop/Processor/Core1/IFID_Stage/IFID_PC_o[31]_i_1_n_0         |                7 |             32 |         4.57 |
|  u_Controller/ClkDivider/clk_o_pulse | ptop/Processor/Core1/IDEX_Stage/IDEXIR_o_reg[25]_3[0]                             | ptop/u_Controller/Interpreter/rst_core                        |               12 |             32 |         2.67 |
|  u_Controller/ClkDivider/clk_o_pulse | ptop/Processor/Core1/IDEX_Stage/IDEXIR_o_reg[25]_4[0]                             | ptop/u_Controller/Interpreter/rst_core                        |               15 |             32 |         2.13 |
|  u_Controller/ClkDivider/clk_o_pulse | ptop/Processor/Core1/IDEX_Stage/IDEXIR_o_reg[25]_5[0]                             | ptop/u_Controller/Interpreter/rst_core                        |               17 |             32 |         1.88 |
|  u_Controller/ClkDivider/clk_o_pulse | ptop/Processor/Core1/IDEX_Stage/IDEXIR_o_reg[25]_2[0]                             | ptop/u_Controller/Interpreter/rst_core                        |               12 |             32 |         2.67 |
|  u_Controller/ClkDivider/clk_o_pulse | ptop/Processor/Core1/MEMWB_Stage/registers_reg[3]0                                |                                                               |               23 |             32 |         1.39 |
|  u_Controller/ClkDivider/clk_o_pulse | ptop/Processor/Core1/MEMWB_Stage/registers_reg[12]0                               |                                                               |               22 |             32 |         1.45 |
|  u_Controller/ClkDivider/clk_o_pulse | ptop/Processor/Core1/MEMWB_Stage/registers_reg[23]0                               |                                                               |               22 |             32 |         1.45 |
|  u_Controller/ClkDivider/clk_o_pulse | ptop/Processor/Core1/EXMEM_Stage/Data_Address[0]_i_1_n_0                          |                                                               |                9 |             32 |         3.56 |
|  u_Controller/ClkDivider/clk_o_pulse | ptop/Processor/Core1/IDEX_Stage/IDEXIR_o_reg[25]_1[0]                             | ptop/u_Controller/Interpreter/rst_core                        |               10 |             32 |         3.20 |
|  u_Controller/ClkDivider/clk_o_pulse | ptop/Processor/Core1/MEMWB_Stage/registers_reg[16]0                               |                                                               |               22 |             32 |         1.45 |
|  u_Controller/ClkDivider/clk_o_pulse | ptop/Processor/Core1/MEMWB_Stage/registers_reg[15]0                               |                                                               |               17 |             32 |         1.88 |
|  u_Controller/ClkDivider/clk_o_pulse | ptop/Processor/M1/E[0]                                                            | ptop/u_Controller/Interpreter/rst_core                        |               12 |             33 |         2.75 |
|  u_Controller/ClkDivider/clk_o_pulse | ptop/Processor/Core1/IDEX_Stage/Mdu/quociente_msk[31]_i_1_n_0                     |                                                               |               11 |             33 |         3.00 |
|  u_Controller/ClkDivider/clk_o_pulse | ptop/Processor/Core1/EXMEM_Stage/EXMEMALUOut_o[31]_i_1_n_0                        |                                                               |               15 |             33 |         2.20 |
|  u_Controller/ClkDivider/clk_o_pulse | ptop/Processor/Core1/IDEX_Stage/Mdu/acumulador0_i_1_n_0                           |                                                               |                7 |             34 |         4.86 |
|  u_Controller/ClkDivider/clk_o_pulse | ptop/Processor/Core1/IDEX_Stage/Mdu/finish_unaligned_pc_reg[0]                    | ptop/u_Controller/Interpreter/rst_core                        |               24 |             34 |         1.42 |
|  u_Controller/ClkDivider/clk_o_pulse | ptop/Processor/Core1/IFID_Stage/temp_instruction                                  |                                                               |               20 |             48 |         2.40 |
|  clk_o_BUFG                          | ptop/u_Controller/Interpreter/num_of_positions[23]_i_1_n_0                        |                                                               |               13 |             55 |         4.23 |
|  u_Controller/ClkDivider/clk_o_pulse | ptop/Processor/ICache/cache_tag_reg_0_63_0_0_i_1_n_0                              |                                                               |               14 |             56 |         4.00 |
|  u_Controller/ClkDivider/clk_o_pulse | ptop/Processor/Core1/EXMEM_Stage/memory_write_reg_1                               |                                                               |               14 |             56 |         4.00 |
|  u_Controller/ClkDivider/clk_o_pulse | ptop/Processor/Core1/IDEX_Stage/Mdu/quociente_msk[31]_i_1_n_0                     | ptop/Processor/Core1/IDEX_Stage/Mdu/quociente_msk[30]_i_1_n_0 |               18 |             62 |         3.44 |
|  u_Controller/ClkDivider/clk_o_pulse | ptop/Processor/Core1/IDEX_Stage/Mdu/take_jalr_reg_4[0]                            |                                                               |               31 |             64 |         2.06 |
|  u_Controller/ClkDivider/clk_o_pulse | ptop/Processor/Core1/MEMWB_Stage/instruction_finished_o                           | ptop/u_Controller/Interpreter/rst_core                        |               16 |             64 |         4.00 |
|  u_Controller/ClkDivider/clk_o_pulse | ptop/u_Controller/Interpreter/E[0]                                                |                                                               |               22 |             65 |         2.95 |
|  u_Controller/ClkDivider/clk_o_pulse | ptop/Processor/Core1/EXMEM_Stage/memory_operation_o_reg_0                         | ptop/Processor/Core1/IDEX_Stage/Mdu/SR[0]                     |               26 |             67 |         2.58 |
|  u_Controller/ClkDivider/clk_o_pulse |                                                                                   |                                                               |               32 |             88 |         2.75 |
|  u_Controller/ClkDivider/clk_o_pulse | ptop/Processor/Core1/IDEX_Stage/core_reset_reg                                    |                                                               |               22 |             88 |         4.00 |
|  u_Controller/ClkDivider/clk_o_pulse | ptop/Processor/Core1/IDEX_Stage/IDEXPC_o_reg[7]_0                                 |                                                               |               22 |             88 |         4.00 |
|  clk_o_BUFG                          |                                                                                   | ResetBootSystem/rst_o_reg_0                                   |               42 |            116 |         2.76 |
|  clk_o_BUFG                          | ptop/Processor/Core1/EXMEM_Stage/memory_mux_selector_reg_4                        |                                                               |               32 |            128 |         4.00 |
|  clk_o_BUFG                          | ptop/Processor/Core1/EXMEM_Stage/Data_Address_reg[10]_1                           |                                                               |               32 |            128 |         4.00 |
|  clk_o_BUFG                          | ptop/Processor/Core1/EXMEM_Stage/Data_Address_reg[11]_1                           |                                                               |               32 |            128 |         4.00 |
|  clk_o_BUFG                          | ptop/Processor/Core1/EXMEM_Stage/memory_mux_selector_reg_1                        |                                                               |               32 |            128 |         4.00 |
|  clk_o_BUFG                          | ptop/Processor/Core1/EXMEM_Stage/memory_mux_selector_reg_2                        |                                                               |               32 |            128 |         4.00 |
|  clk_o_BUFG                          | ptop/Processor/Core1/EXMEM_Stage/Data_Address_reg[10]_2                           |                                                               |               32 |            128 |         4.00 |
|  clk_o_BUFG                          | ptop/Processor/Core1/EXMEM_Stage/memory_mux_selector_reg_3                        |                                                               |               32 |            128 |         4.00 |
|  clk_o_BUFG                          | ptop/Processor/Core1/EXMEM_Stage/Data_Address_reg[12]_2                           |                                                               |               32 |            128 |         4.00 |
|  u_Controller/ClkDivider/clk_o_pulse |                                                                                   | ptop/u_Controller/Interpreter/rst_core                        |              213 |            464 |         2.18 |
+--------------------------------------+-----------------------------------------------------------------------------------+---------------------------------------------------------------+------------------+----------------+--------------+


