
// -----------
// This file was generated by riscv_ctg (https://github.com/riscv-software-src/riscv-ctg)
// version   : 0.11.0
// timestamp : Mon Aug 28 04:33:02 2023 GMT
// usage     : riscv_ctg \
//                  -- cgf //                  --cgf /home/riscv/riscv-ctg/sample_cgfs/dataset.cgf \
//                  --cgf /home/riscv/riscv-ctg/sample_cgfs/sample_cgfs_fext/RV32Zdinx/fcvt.w.d.cgf \
 \
//                  -- xlen 32  \
// -----------
//
// -----------
// Copyright (c) 2020. RISC-V International. All rights reserved.
// SPDX-License-Identifier: BSD-3-Clause
// -----------
//
// This assembly file tests the fcvt.w.d instruction of the RISC-V RV32_Zfinx_Zdinx,RV64_Zfinx_Zdinx extension for the fcvt.w.d_b28 covergroup.
// 
#include "model_test.h"
#include "arch_test.h"
RVTEST_ISA("RV32I_Zfinx_Zdinx")

.section .text.init
.globl rvtest_entry_point
rvtest_entry_point:
RVMODEL_BOOT
RVTEST_CODE_BEGIN

#ifdef TEST_CASE_1

RVTEST_CASE(0,"//check ISA:=regex(.*32.*); check ISA:=regex(.*I.*Zfinx.*Zdinx.*);def TEST_CASE_1=True;",fcvt.w.d_b28)

RVTEST_FP_ENABLE()
RVTEST_VALBASEUPD(x3,test_dataset_0)
RVTEST_SIGBASE(x1,signature_x1_1)

inst_0:// rs1==x28, rd==x30,fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fcvt.w.d ; op1:x28; dest:x30; op1val:0x0000000000000000; valaddr_reg:x3;
offset:0*4; correctval:??; testreg:x2;
fcsr_val:0*/
TEST_ZDINX_OP_32(fcvt.w.d, x30, x31, x28, x29,0, 0, 0, 0x00000000, 0x00000000,x3, 0*SIGALIGN, x4,x1, x2)

inst_1:// rs1==x30, rd==x28,fs1 == 0 and fe1 == 0x3fe and fm1 == 0x248ee18215dfa and  fcsr == 0x0 and rm_val == 7   
/* opcode: fcvt.w.d ; op1:x30; dest:x28; op1val:0x3fe248ee18215dfa; valaddr_reg:x3;
offset:1*4; correctval:??; testreg:x2;
fcsr_val:0*/
TEST_ZDINX_OP_32(fcvt.w.d, x28, x29, x30, x31,0, 0, 0, 0x18215dfa, 0x3fe248ee,x3, 1*SIGALIGN, x4,x1, x2)

inst_2:// rs1==x24, rd==x26,fs1 == 0 and fe1 == 0x3ff and fm1 == 0x0000000000000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fcvt.w.d ; op1:x24; dest:x26; op1val:0x3ff0000000000000; valaddr_reg:x3;
offset:2*4; correctval:??; testreg:x2;
fcsr_val:0*/
TEST_ZDINX_OP_32(fcvt.w.d, x26, x27, x24, x25,0, 0, 0, 0x00000000, 0x3ff00000,x3, 2*SIGALIGN, x4,x1, x2)

inst_3:// rs1==x26, rd==x24,fs1 == 0 and fe1 == 0x3ff and fm1 == 0x4000000000000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fcvt.w.d ; op1:x26; dest:x24; op1val:0x3ff4000000000000; valaddr_reg:x3;
offset:3*4; correctval:??; testreg:x2;
fcsr_val:0*/
TEST_ZDINX_OP_32(fcvt.w.d, x24, x25, x26, x27,0, 0, 0, 0x00000000, 0x3ff40000,x3, 3*SIGALIGN, x4,x1, x2)

inst_4:// rs1==x20, rd==x22,fs1 == 0 and fe1 == 0x3ff and fm1 == 0x8000000000000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fcvt.w.d ; op1:x20; dest:x22; op1val:0x3ff8000000000000; valaddr_reg:x3;
offset:4*4; correctval:??; testreg:x2;
fcsr_val:0*/
TEST_ZDINX_OP_32(fcvt.w.d, x22, x23, x20, x21,0, 0, 0, 0x00000000, 0x3ff80000,x3, 4*SIGALIGN, x4,x1, x2)

inst_5:// rs1==x22, rd==x20,fs1 == 0 and fe1 == 0x3ff and fm1 == 0xc000000000000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fcvt.w.d ; op1:x22; dest:x20; op1val:0x3ffc000000000000; valaddr_reg:x3;
offset:5*4; correctval:??; testreg:x2;
fcsr_val:0*/
TEST_ZDINX_OP_32(fcvt.w.d, x20, x21, x22, x23,0, 0, 0, 0x00000000, 0x3ffc0000,x3, 5*SIGALIGN, x4,x1, x2)

inst_6:// rs1==x16, rd==x18,fs1 == 0 and fe1 == 0x400 and fm1 == 0x0000000000000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fcvt.w.d ; op1:x16; dest:x18; op1val:0x4000000000000000; valaddr_reg:x3;
offset:6*4; correctval:??; testreg:x2;
fcsr_val:0*/
TEST_ZDINX_OP_32(fcvt.w.d, x18, x19, x16, x17,0, 0, 0, 0x00000000, 0x40000000,x3, 6*SIGALIGN, x4,x1, x2)

inst_7:// rs1==x18, rd==x16,fs1 == 0 and fe1 == 0x400 and fm1 == 0x2000000000000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fcvt.w.d ; op1:x18; dest:x16; op1val:0x4002000000000000; valaddr_reg:x3;
offset:7*4; correctval:??; testreg:x2;
fcsr_val:0*/
TEST_ZDINX_OP_32(fcvt.w.d, x16, x17, x18, x19,0, 0, 0, 0x00000000, 0x40020000,x3, 7*SIGALIGN, x4,x1, x2)

inst_8:// rs1==x12, rd==x14,fs1 == 0 and fe1 == 0x400 and fm1 == 0x4000000000000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fcvt.w.d ; op1:x12; dest:x14; op1val:0x4004000000000000; valaddr_reg:x3;
offset:8*4; correctval:??; testreg:x2;
fcsr_val:0*/
TEST_ZDINX_OP_32(fcvt.w.d, x14, x15, x12, x13,0, 0, 0, 0x00000000, 0x40040000,x3, 8*SIGALIGN, x4,x1, x2)

inst_9:// rs1==x14, rd==x12,fs1 == 0 and fe1 == 0x400 and fm1 == 0x6000000000000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fcvt.w.d ; op1:x14; dest:x12; op1val:0x4006000000000000; valaddr_reg:x3;
offset:9*4; correctval:??; testreg:x2;
fcsr_val:0*/
TEST_ZDINX_OP_32(fcvt.w.d, x12, x13, x14, x15,0, 0, 0, 0x00000000, 0x40060000,x3, 9*SIGALIGN, x4,x1, x2)

inst_10:// rs1==x8, rd==x10,fs1 == 0 and fe1 == 0x43c and fm1 == 0xb72eb13dc494a and  fcsr == 0x0 and rm_val == 7   
/* opcode: fcvt.w.d ; op1:x8; dest:x10; op1val:0x43cb72eb13dc494a; valaddr_reg:x3;
offset:10*4; correctval:??; testreg:x2;
fcsr_val:0*/
TEST_ZDINX_OP_32(fcvt.w.d, x10, x11, x8, x9,0, 0, 0, 0x13dc494a, 0x43cb72eb,x3, 10*SIGALIGN, x4,x1, x2)
RVTEST_VALBASEUPD(x13,test_dataset_1)

inst_11:// rs1==x10, rd==x8,fs1 == 0 and fe1 == 0x43e and fm1 == 0x0000000000000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fcvt.w.d ; op1:x10; dest:x8; op1val:0x43e0000000000000; valaddr_reg:x13;
offset:0*4; correctval:??; testreg:x12;
fcsr_val:0*/
TEST_ZDINX_OP_32(fcvt.w.d, x8, x9, x10, x11,0, 0, 0, 0x00000000, 0x43e00000,x13, 11*SIGALIGN, x14,x1, x12)

inst_12:// rs1==x4, rd==x6,fs1 == 0 and fe1 == 0x7ff and fm1 == 0x0000000000000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fcvt.w.d ; op1:x4; dest:x6; op1val:0x7ff0000000000000; valaddr_reg:x13;
offset:1*4; correctval:??; testreg:x12;
fcsr_val:0*/
TEST_ZDINX_OP_32(fcvt.w.d, x6, x7, x4, x5,0, 0, 0, 0x00000000, 0x7ff00000,x13, 12*SIGALIGN, x14,x1, x12)
RVTEST_SIGBASE(x1,signature_x1_2)

inst_13:// rs1==x6, rd==x4,fs1 == 0 and fe1 == 0x7ff and fm1 == 0x0000000000001 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fcvt.w.d ; op1:x6; dest:x4; op1val:0x7ff0000000000001; valaddr_reg:x13;
offset:2*4; correctval:??; testreg:x12;
fcsr_val:0*/
TEST_ZDINX_OP_32(fcvt.w.d, x4, x5, x6, x7,0, 0, 0, 0x00000001, 0x7ff00000,x13, 0*SIGALIGN, x14,x1, x12)

inst_14:// rs1==x2,fs1 == 0 and fe1 == 0x7ff and fm1 == 0x8000000000001 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fcvt.w.d ; op1:x2; dest:x30; op1val:0x7ff8000000000001; valaddr_reg:x13;
offset:3*4; correctval:??; testreg:x12;
fcsr_val:0*/
TEST_ZDINX_OP_32(fcvt.w.d, x30, x31, x2, x3,0, 0, 0, 0x00000001, 0x7ff80000,x13, 1*SIGALIGN, x14,x1, x12)

inst_15:// rd==x2,fs1 == 1 and fe1 == 0x000 and fm1 == 0x0000000000000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fcvt.w.d ; op1:x30; dest:x2; op1val:0x8000000000000000; valaddr_reg:x13;
offset:4*4; correctval:??; testreg:x12;
fcsr_val:0*/
TEST_ZDINX_OP_32(fcvt.w.d, x2, x3, x30, x31,0, 0, 0, 0x00000000, 0x80000000,x13, 2*SIGALIGN, x14,x1, x12)

inst_16:// fs1 == 1 and fe1 == 0x3fd and fm1 == 0xb008d57e19f88 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fcvt.w.d ; op1:x28; dest:x30; op1val:0xbfdb008d57e19f88; valaddr_reg:x13;
offset:5*4; correctval:??; testreg:x12;
fcsr_val:0*/
TEST_ZDINX_OP_32(fcvt.w.d, x30, x31, x28, x29,0, 0, 0, 0x57e19f88, 0xbfdb008d,x13, 3*SIGALIGN, x14,x1, x12)

inst_17:// fs1 == 1 and fe1 == 0x3f8 and fm1 == 0x0000000000000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fcvt.w.d ; op1:x28; dest:x30; op1val:0xbf80000000000000; valaddr_reg:x13;
offset:6*4; correctval:??; testreg:x12;
fcsr_val:0*/
TEST_ZDINX_OP_32(fcvt.w.d, x30, x31, x28, x29,0, 0, 0, 0x00000000, 0xbf800000,x13, 4*SIGALIGN, x14,x1, x12)

inst_18:// fs1 == 1 and fe1 == 0x400 and fm1 == 0x6000000000000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fcvt.w.d ; op1:x28; dest:x30; op1val:0xc006000000000000; valaddr_reg:x13;
offset:7*4; correctval:??; testreg:x12;
fcsr_val:0*/
TEST_ZDINX_OP_32(fcvt.w.d, x30, x31, x28, x29,0, 0, 0, 0x00000000, 0xc0060000,x13, 5*SIGALIGN, x14,x1, x12)

inst_19:// fs1 == 1 and fe1 == 0x400 and fm1 == 0x4000000000000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fcvt.w.d ; op1:x28; dest:x30; op1val:0xc004000000000000; valaddr_reg:x13;
offset:8*4; correctval:??; testreg:x12;
fcsr_val:0*/
TEST_ZDINX_OP_32(fcvt.w.d, x30, x31, x28, x29,0, 0, 0, 0x00000000, 0xc0040000,x13, 6*SIGALIGN, x14,x1, x12)

inst_20:// fs1 == 1 and fe1 == 0x400 and fm1 == 0x2000000000000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fcvt.w.d ; op1:x28; dest:x30; op1val:0xc002000000000000; valaddr_reg:x13;
offset:9*4; correctval:??; testreg:x12;
fcsr_val:0*/
TEST_ZDINX_OP_32(fcvt.w.d, x30, x31, x28, x29,0, 0, 0, 0x00000000, 0xc0020000,x13, 7*SIGALIGN, x14,x1, x12)

inst_21:// fs1 == 1 and fe1 == 0x400 and fm1 == 0x0000000000000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fcvt.w.d ; op1:x28; dest:x30; op1val:0xc000000000000000; valaddr_reg:x13;
offset:10*4; correctval:??; testreg:x12;
fcsr_val:0*/
TEST_ZDINX_OP_32(fcvt.w.d, x30, x31, x28, x29,0, 0, 0, 0x00000000, 0xc0000000,x13, 8*SIGALIGN, x14,x1, x12)

inst_22:// fs1 == 1 and fe1 == 0x3ff and fm1 == 0xc000000000000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fcvt.w.d ; op1:x28; dest:x30; op1val:0xbffc000000000000; valaddr_reg:x13;
offset:11*4; correctval:??; testreg:x12;
fcsr_val:0*/
TEST_ZDINX_OP_32(fcvt.w.d, x30, x31, x28, x29,0, 0, 0, 0x00000000, 0xbffc0000,x13, 9*SIGALIGN, x14,x1, x12)

inst_23:// fs1 == 1 and fe1 == 0x3ff and fm1 == 0x8000000000000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fcvt.w.d ; op1:x28; dest:x30; op1val:0xbff8000000000000; valaddr_reg:x13;
offset:12*4; correctval:??; testreg:x12;
fcsr_val:0*/
TEST_ZDINX_OP_32(fcvt.w.d, x30, x31, x28, x29,0, 0, 0, 0x00000000, 0xbff80000,x13, 10*SIGALIGN, x14,x1, x12)

inst_24:// fs1 == 1 and fe1 == 0x3ff and fm1 == 0x4000000000000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fcvt.w.d ; op1:x28; dest:x30; op1val:0xbff4000000000000; valaddr_reg:x13;
offset:13*4; correctval:??; testreg:x12;
fcsr_val:0*/
TEST_ZDINX_OP_32(fcvt.w.d, x30, x31, x28, x29,0, 0, 0, 0x00000000, 0xbff40000,x13, 11*SIGALIGN, x14,x1, x12)

inst_25:// fs1 == 1 and fe1 == 0x43d and fm1 == 0x967a4ae26514c and  fcsr == 0x0 and rm_val == 7   
/* opcode: fcvt.w.d ; op1:x28; dest:x30; op1val:0xc3d967a4ae26514c; valaddr_reg:x13;
offset:14*4; correctval:??; testreg:x12;
fcsr_val:0*/
TEST_ZDINX_OP_32(fcvt.w.d, x30, x31, x28, x29,0, 0, 0, 0xae26514c, 0xc3d967a4,x13, 12*SIGALIGN, x14,x1, x12)

inst_26:// fs1 == 1 and fe1 == 0x43e and fm1 == 0x0000000000000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fcvt.w.d ; op1:x28; dest:x30; op1val:0xc3e0000000000000; valaddr_reg:x13;
offset:15*4; correctval:??; testreg:x12;
fcsr_val:0*/
TEST_ZDINX_OP_32(fcvt.w.d, x30, x31, x28, x29,0, 0, 0, 0x00000000, 0xc3e00000,x13, 13*SIGALIGN, x14,x1, x12)

inst_27:// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x0000000000000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fcvt.w.d ; op1:x28; dest:x30; op1val:0xfff0000000000000; valaddr_reg:x13;
offset:16*4; correctval:??; testreg:x12;
fcsr_val:0*/
TEST_ZDINX_OP_32(fcvt.w.d, x30, x31, x28, x29,0, 0, 0, 0x00000000, 0xfff00000,x13, 14*SIGALIGN, x14,x1, x12)
#endif


RVTEST_CODE_END
RVMODEL_HALT

RVTEST_DATA_BEGIN
.align 4
rvtest_data:
.word 0xbabecafe
.word 0xabecafeb
.word 0xbecafeba
.word 0xecafebab
test_dataset_0:
NAN_BOXED(0x00000000,64,FLEN)
NAN_BOXED(0x18215dfa,64,FLEN)
NAN_BOXED(0x00000000,64,FLEN)
NAN_BOXED(0x00000000,64,FLEN)
NAN_BOXED(0x00000000,64,FLEN)
NAN_BOXED(0x00000000,64,FLEN)
NAN_BOXED(0x00000000,64,FLEN)
NAN_BOXED(0x00000000,64,FLEN)
NAN_BOXED(0x00000000,64,FLEN)
NAN_BOXED(0x00000000,64,FLEN)
NAN_BOXED(0x13dc494a,64,FLEN)
test_dataset_1:
NAN_BOXED(0x00000000,64,FLEN)
NAN_BOXED(0x00000000,64,FLEN)
NAN_BOXED(0x00000001,64,FLEN)
NAN_BOXED(0x00000001,64,FLEN)
NAN_BOXED(0x00000000,64,FLEN)
NAN_BOXED(0x57e19f88,64,FLEN)
NAN_BOXED(0x00000000,64,FLEN)
NAN_BOXED(0x00000000,64,FLEN)
NAN_BOXED(0x00000000,64,FLEN)
NAN_BOXED(0x00000000,64,FLEN)
NAN_BOXED(0x00000000,64,FLEN)
NAN_BOXED(0x00000000,64,FLEN)
NAN_BOXED(0x00000000,64,FLEN)
NAN_BOXED(0x00000000,64,FLEN)
NAN_BOXED(0xae26514c,64,FLEN)
NAN_BOXED(0x00000000,64,FLEN)
NAN_BOXED(0x00000000,64,FLEN)
RVTEST_DATA_END

RVMODEL_DATA_BEGIN
rvtest_sig_begin:
sig_begin_canary:
CANARY;



signature_x1_0:
    .fill 0*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_1:
    .fill 13*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_2:
    .fill 15*((SIGALIGN)/4),4,0xdeadbeef

#ifdef rvtest_mtrap_routine
tsig_begin_canary:
CANARY;

mtrap_sigptr:
    .fill 64*XLEN/32,4,0xdeadbeef

tsig_end_canary:
CANARY;
#endif

#ifdef rvtest_gpr_save

gpr_save:
    .fill 32*XLEN/32,4,0xdeadbeef

#endif


sig_end_canary:
CANARY;
rvtest_sig_end:
RVMODEL_DATA_END
