
// -----------
// This file was generated by riscv_ctg (https://github.com/riscv-software-src/riscv-ctg)
// version   : 0.7.1
// timestamp : Fri Jun 17 14:03:17 2022 GMT
// usage     : riscv_ctg \
//                  -- cgf //                  --cgf /scratch/pawan/work/normalised/RV64F/fcvt.s.lu.cgf \
 \
//                  -- xlen 64  \
//                  --randomize \
// -----------
//
// -----------
// Copyright (c) 2020. RISC-V International. All rights reserved.
// SPDX-License-Identifier: BSD-3-Clause
// -----------
//
// This assembly file tests the fcvt.s.lu instruction of the RISC-V RV64F_Zicsr,RV64FD_Zicsr extension for the fcvt.s.lu_b25 covergroup.
// 
#include "model_test.h"
#include "arch_test.h"
RVTEST_ISA("RV64IF_Zicsr,RV64IFD_Zicsr")

.section .text.init
.globl rvtest_entry_point
rvtest_entry_point:
RVMODEL_BOOT
RVTEST_CODE_BEGIN

#ifdef TEST_CASE_1

RVTEST_CASE(0,"//check ISA:=regex(.*RV64.*I.*F.*);def TEST_CASE_1=True;",fcvt.s.lu_b25)

RVTEST_FP_ENABLE()
RVTEST_VALBASEUPD(x16,test_dataset_0)
RVTEST_SIGBASE(x5,signature_x5_1)

inst_0:// rs1==x26, rd==f0,rs1_val == 0 and  fcsr == 0 and rm_val == 7  
/* opcode: fcvt.s.lu ; op1:x26; dest:f0; op1val:0x0; valaddr_reg:x16;
val_offset:0*8; rmval:dyn; correctval:??; testreg:x6;
fcsr_val: 0*/
TEST_FPIO_OP(fcvt.s.lu, f0, x26, dyn, 0, 0, x16, 0*8, x23, x5, x6,ld)

inst_1:// rs1==x2, rd==f21,rs1_val == 1 and  fcsr == 0 and rm_val == 7  
/* opcode: fcvt.s.lu ; op1:x2; dest:f21; op1val:0x1; valaddr_reg:x16;
val_offset:1*8; rmval:dyn; correctval:??; testreg:x6;
fcsr_val: 0*/
TEST_FPIO_OP(fcvt.s.lu, f21, x2, dyn, 0, 0, x16, 1*8, x23, x5, x6,ld)

inst_2:// rs1==x10, rd==f25,rs1_val == 10540517427298422784 and  fcsr == 0 and rm_val == 7  
/* opcode: fcvt.s.lu ; op1:x10; dest:f25; op1val:0x924770c10aefd000; valaddr_reg:x16;
val_offset:2*8; rmval:dyn; correctval:??; testreg:x6;
fcsr_val: 0*/
TEST_FPIO_OP(fcvt.s.lu, f25, x10, dyn, 0, 0, x16, 2*8, x23, x5, x6,ld)

inst_3:// rs1==x15, rd==f4,rs1_val == 18446744073709551615 and  fcsr == 0 and rm_val == 7  
/* opcode: fcvt.s.lu ; op1:x15; dest:f4; op1val:0xffffffffffffffff; valaddr_reg:x16;
val_offset:3*8; rmval:dyn; correctval:??; testreg:x6;
fcsr_val: 0*/
TEST_FPIO_OP(fcvt.s.lu, f4, x15, dyn, 0, 0, x16, 3*8, x23, x5, x6,ld)

inst_4:// rs1==x25, rd==f15,
/* opcode: fcvt.s.lu ; op1:x25; dest:f15; op1val:0x0; valaddr_reg:x16;
val_offset:4*8; rmval:dyn; correctval:??; testreg:x6;
fcsr_val: 0*/
TEST_FPIO_OP(fcvt.s.lu, f15, x25, dyn, 0, 0, x16, 4*8, x23, x5, x6,ld)

inst_5:// rs1==x7, rd==f19,
/* opcode: fcvt.s.lu ; op1:x7; dest:f19; op1val:0x0; valaddr_reg:x16;
val_offset:5*8; rmval:dyn; correctval:??; testreg:x6;
fcsr_val: 0*/
TEST_FPIO_OP(fcvt.s.lu, f19, x7, dyn, 0, 0, x16, 5*8, x23, x5, x6,ld)

inst_6:// rs1==x27, rd==f11,
/* opcode: fcvt.s.lu ; op1:x27; dest:f11; op1val:0x0; valaddr_reg:x16;
val_offset:6*8; rmval:dyn; correctval:??; testreg:x6;
fcsr_val: 0*/
TEST_FPIO_OP(fcvt.s.lu, f11, x27, dyn, 0, 0, x16, 6*8, x23, x5, x6,ld)

inst_7:// rs1==x1, rd==f5,
/* opcode: fcvt.s.lu ; op1:x1; dest:f5; op1val:0x0; valaddr_reg:x16;
val_offset:7*8; rmval:dyn; correctval:??; testreg:x6;
fcsr_val: 0*/
TEST_FPIO_OP(fcvt.s.lu, f5, x1, dyn, 0, 0, x16, 7*8, x23, x5, x6,ld)

inst_8:// rs1==x14, rd==f31,
/* opcode: fcvt.s.lu ; op1:x14; dest:f31; op1val:0x0; valaddr_reg:x16;
val_offset:8*8; rmval:dyn; correctval:??; testreg:x6;
fcsr_val: 0*/
TEST_FPIO_OP(fcvt.s.lu, f31, x14, dyn, 0, 0, x16, 8*8, x23, x5, x6,ld)

inst_9:// rs1==x8, rd==f1,
/* opcode: fcvt.s.lu ; op1:x8; dest:f1; op1val:0x0; valaddr_reg:x16;
val_offset:9*8; rmval:dyn; correctval:??; testreg:x6;
fcsr_val: 0*/
TEST_FPIO_OP(fcvt.s.lu, f1, x8, dyn, 0, 0, x16, 9*8, x23, x5, x6,ld)

inst_10:// rs1==x4, rd==f6,
/* opcode: fcvt.s.lu ; op1:x4; dest:f6; op1val:0x0; valaddr_reg:x16;
val_offset:10*8; rmval:dyn; correctval:??; testreg:x6;
fcsr_val: 0*/
TEST_FPIO_OP(fcvt.s.lu, f6, x4, dyn, 0, 0, x16, 10*8, x23, x5, x6,ld)

inst_11:// rs1==x13, rd==f17,
/* opcode: fcvt.s.lu ; op1:x13; dest:f17; op1val:0x0; valaddr_reg:x16;
val_offset:11*8; rmval:dyn; correctval:??; testreg:x6;
fcsr_val: 0*/
TEST_FPIO_OP(fcvt.s.lu, f17, x13, dyn, 0, 0, x16, 11*8, x23, x5, x6,ld)

inst_12:// rs1==x11, rd==f23,
/* opcode: fcvt.s.lu ; op1:x11; dest:f23; op1val:0x0; valaddr_reg:x16;
val_offset:12*8; rmval:dyn; correctval:??; testreg:x6;
fcsr_val: 0*/
TEST_FPIO_OP(fcvt.s.lu, f23, x11, dyn, 0, 0, x16, 12*8, x23, x5, x6,ld)

inst_13:// rs1==x20, rd==f28,
/* opcode: fcvt.s.lu ; op1:x20; dest:f28; op1val:0x0; valaddr_reg:x16;
val_offset:13*8; rmval:dyn; correctval:??; testreg:x6;
fcsr_val: 0*/
TEST_FPIO_OP(fcvt.s.lu, f28, x20, dyn, 0, 0, x16, 13*8, x23, x5, x6,ld)

inst_14:// rs1==x22, rd==f14,
/* opcode: fcvt.s.lu ; op1:x22; dest:f14; op1val:0x0; valaddr_reg:x16;
val_offset:14*8; rmval:dyn; correctval:??; testreg:x6;
fcsr_val: 0*/
TEST_FPIO_OP(fcvt.s.lu, f14, x22, dyn, 0, 0, x16, 14*8, x23, x5, x6,ld)

inst_15:// rs1==x17, rd==f30,
/* opcode: fcvt.s.lu ; op1:x17; dest:f30; op1val:0x0; valaddr_reg:x16;
val_offset:15*8; rmval:dyn; correctval:??; testreg:x6;
fcsr_val: 0*/
TEST_FPIO_OP(fcvt.s.lu, f30, x17, dyn, 0, 0, x16, 15*8, x23, x5, x6,ld)

inst_16:// rs1==x0, rd==f3,
/* opcode: fcvt.s.lu ; op1:x0; dest:f3; op1val:0x0; valaddr_reg:x16;
val_offset:16*8; rmval:dyn; correctval:??; testreg:x6;
fcsr_val: 0*/
TEST_FPIO_OP(fcvt.s.lu, f3, x0, dyn, 0, 0, x16, 16*8, x23, x5, x6,ld)

inst_17:// rs1==x9, rd==f29,
/* opcode: fcvt.s.lu ; op1:x9; dest:f29; op1val:0x0; valaddr_reg:x16;
val_offset:17*8; rmval:dyn; correctval:??; testreg:x6;
fcsr_val: 0*/
TEST_FPIO_OP(fcvt.s.lu, f29, x9, dyn, 0, 0, x16, 17*8, x23, x5, x6,ld)

inst_18:// rs1==x3, rd==f7,
/* opcode: fcvt.s.lu ; op1:x3; dest:f7; op1val:0x0; valaddr_reg:x16;
val_offset:18*8; rmval:dyn; correctval:??; testreg:x6;
fcsr_val: 0*/
TEST_FPIO_OP(fcvt.s.lu, f7, x3, dyn, 0, 0, x16, 18*8, x23, x5, x6,ld)

inst_19:// rs1==x28, rd==f27,
/* opcode: fcvt.s.lu ; op1:x28; dest:f27; op1val:0x0; valaddr_reg:x16;
val_offset:19*8; rmval:dyn; correctval:??; testreg:x6;
fcsr_val: 0*/
TEST_FPIO_OP(fcvt.s.lu, f27, x28, dyn, 0, 0, x16, 19*8, x23, x5, x6,ld)

inst_20:// rs1==x21, rd==f22,
/* opcode: fcvt.s.lu ; op1:x21; dest:f22; op1val:0x0; valaddr_reg:x16;
val_offset:20*8; rmval:dyn; correctval:??; testreg:x6;
fcsr_val: 0*/
TEST_FPIO_OP(fcvt.s.lu, f22, x21, dyn, 0, 0, x16, 20*8, x23, x5, x6,ld)

inst_21:// rs1==x30, rd==f26,
/* opcode: fcvt.s.lu ; op1:x30; dest:f26; op1val:0x0; valaddr_reg:x16;
val_offset:21*8; rmval:dyn; correctval:??; testreg:x6;
fcsr_val: 0*/
TEST_FPIO_OP(fcvt.s.lu, f26, x30, dyn, 0, 0, x16, 21*8, x23, x5, x6,ld)

inst_22:// rs1==x19, rd==f10,
/* opcode: fcvt.s.lu ; op1:x19; dest:f10; op1val:0x0; valaddr_reg:x16;
val_offset:22*8; rmval:dyn; correctval:??; testreg:x6;
fcsr_val: 0*/
TEST_FPIO_OP(fcvt.s.lu, f10, x19, dyn, 0, 0, x16, 22*8, x23, x5, x6,ld)

inst_23:// rs1==x12, rd==f20,
/* opcode: fcvt.s.lu ; op1:x12; dest:f20; op1val:0x0; valaddr_reg:x16;
val_offset:23*8; rmval:dyn; correctval:??; testreg:x6;
fcsr_val: 0*/
TEST_FPIO_OP(fcvt.s.lu, f20, x12, dyn, 0, 0, x16, 23*8, x23, x5, x6,ld)

inst_24:// rs1==x18, rd==f12,
/* opcode: fcvt.s.lu ; op1:x18; dest:f12; op1val:0x0; valaddr_reg:x16;
val_offset:24*8; rmval:dyn; correctval:??; testreg:x6;
fcsr_val: 0*/
TEST_FPIO_OP(fcvt.s.lu, f12, x18, dyn, 0, 0, x16, 24*8, x23, x5, x6,ld)
RVTEST_VALBASEUPD(x3,test_dataset_1)

inst_25:// rs1==x24, rd==f2,
/* opcode: fcvt.s.lu ; op1:x24; dest:f2; op1val:0x0; valaddr_reg:x3;
val_offset:0*8; rmval:dyn; correctval:??; testreg:x6;
fcsr_val: 0*/
TEST_FPIO_OP(fcvt.s.lu, f2, x24, dyn, 0, 0, x3, 0*8, x4, x5, x6,ld)

inst_26:// rs1==x16, rd==f8,
/* opcode: fcvt.s.lu ; op1:x16; dest:f8; op1val:0x0; valaddr_reg:x3;
val_offset:1*8; rmval:dyn; correctval:??; testreg:x6;
fcsr_val: 0*/
TEST_FPIO_OP(fcvt.s.lu, f8, x16, dyn, 0, 0, x3, 1*8, x4, x5, x6,ld)

inst_27:// rs1==x29, rd==f13,
/* opcode: fcvt.s.lu ; op1:x29; dest:f13; op1val:0x0; valaddr_reg:x3;
val_offset:2*8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val: 0*/
TEST_FPIO_OP(fcvt.s.lu, f13, x29, dyn, 0, 0, x3, 2*8, x4, x5, x2,ld)
RVTEST_SIGBASE(x1,signature_x1_0)

inst_28:// rs1==x23, rd==f24,
/* opcode: fcvt.s.lu ; op1:x23; dest:f24; op1val:0x0; valaddr_reg:x3;
val_offset:3*8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val: 0*/
TEST_FPIO_OP(fcvt.s.lu, f24, x23, dyn, 0, 0, x3, 3*8, x4, x1, x2,ld)

inst_29:// rs1==x6, rd==f16,
/* opcode: fcvt.s.lu ; op1:x6; dest:f16; op1val:0x0; valaddr_reg:x3;
val_offset:4*8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val: 0*/
TEST_FPIO_OP(fcvt.s.lu, f16, x6, dyn, 0, 0, x3, 4*8, x4, x1, x2,ld)

inst_30:// rs1==x5, rd==f18,
/* opcode: fcvt.s.lu ; op1:x5; dest:f18; op1val:0x0; valaddr_reg:x3;
val_offset:5*8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val: 0*/
TEST_FPIO_OP(fcvt.s.lu, f18, x5, dyn, 0, 0, x3, 5*8, x4, x1, x2,ld)

inst_31:// rs1==x31, rd==f9,
/* opcode: fcvt.s.lu ; op1:x31; dest:f9; op1val:0x0; valaddr_reg:x3;
val_offset:6*8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val: 0*/
TEST_FPIO_OP(fcvt.s.lu, f9, x31, dyn, 0, 0, x3, 6*8, x4, x1, x2,ld)

inst_32:// 
/* opcode: fcvt.s.lu ; op1:x31; dest:f31; op1val:0x0; valaddr_reg:x3;
val_offset:7*8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val: 0*/
TEST_FPIO_OP(fcvt.s.lu, f31, x31, dyn, 0, 0, x3, 7*8, x4, x1, x2,ld)
#endif


RVTEST_CODE_END
RVMODEL_HALT

RVTEST_DATA_BEGIN
.align 4
rvtest_data:
.word 0xbabecafe
.word 0xabecafeb
.word 0xbecafeba
.word 0xecafebab
test_dataset_0:
.dword 0;
.dword 1;
.dword 10540517427298422784;
.dword 18446744073709551615;
.dword 0;
.dword 0;
.dword 0;
.dword 0;
.dword 0;
.dword 0;
.dword 0;
.dword 0;
.dword 0;
.dword 0;
.dword 0;
.dword 0;
.dword 0;
.dword 0;
.dword 0;
.dword 0;
.dword 0;
.dword 0;
.dword 0;
.dword 0;
.dword 0;
test_dataset_1:
.dword 0;
.dword 0;
.dword 0;
.dword 0;
.dword 0;
.dword 0;
.dword 0;
.dword 0;
RVTEST_DATA_END

RVMODEL_DATA_BEGIN
rvtest_sig_begin:
sig_begin_canary:
CANARY;


signature_x5_0:
    .fill 0*((SIGALIGN)/4),4,0xdeadbeef


signature_x5_1:
    .fill 56*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_0:
    .fill 10*((SIGALIGN)/4),4,0xdeadbeef

#ifdef rvtest_mtrap_routine

tsig_begin_canary:
CANARY;
tsig_begin_canary:
CANARY;
mtrap_sigptr:
    .fill 64*(XLEN/32),4,0xdeadbeef
tsig_end_canary:
CANARY;
tsig_end_canary:
CANARY;

#endif

#ifdef rvtest_gpr_save

gpr_save:
    .fill 32*XLEN/32,4,0xdeadbeef

#endif

sig_end_canary:
CANARY;
rvtest_sig_end:
RVMODEL_DATA_END
