
// -----------
// This file was generated by riscv_ctg (https://github.com/riscv-software-src/riscv-ctg)
// version   : 0.11.0
// timestamp : Tue Jan 30 08:43:45 2024 GMT
// usage     : riscv_ctg \
//                  -- cgf //                  --cgf /home/riscv/riscv-ctg/sample_cgfs/dataset.cgf \
//                  --cgf /home/riscv/riscv-ctg/sample_cgfs/sample_cgfs_fext/RV32H/rv32h_fmsub.cgf \
 \
//                  -- xlen 32  \
// -----------
//
// -----------
// Copyright (c) 2020. RISC-V International. All rights reserved.
// SPDX-License-Identifier: BSD-3-Clause
// -----------
//
// This assembly file tests the fmsub.h instruction of the RISC-V RV32F_Zicsr_Zfh,RV64F_Zicsr_Zfh extension for the fmsub_b3 covergroup.
// 
#include "model_test.h"
#include "arch_test.h"
RVTEST_ISA("RV32IF_Zicsr_Zfh,RV64IF_Zicsr_Zfh")

.section .text.init
.globl rvtest_entry_point
rvtest_entry_point:
RVMODEL_BOOT
RVTEST_CODE_BEGIN

#ifdef TEST_CASE_1

RVTEST_CASE(0,"//check ISA:=regex(.*I.*F.*Zfh.*);def TEST_CASE_1=True;",fmsub_b3)

RVTEST_FP_ENABLE()
RVTEST_VALBASEUPD(x3,test_dataset_0)
RVTEST_SIGBASE(x1,signature_x1_1)

inst_0:
// rs1 == rd == rs3 != rs2, rs1==f31, rs2==f30, rs3==f31, rd==f31,fs1 == 0 and fe1 == 0x1d and fm1 == 0x12d and fs2 == 0 and fe2 == 0x0d and fm2 == 0x374 and fs3 == 0 and fe3 == 0x1c and fm3 == 0x0d3 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f31; op2:f30; op3:f31; dest:f31; op1val:0x752d; op2val:0x3774;
op3val:0x752d; valaddr_reg:x3; val_offset:0*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f31, f30, f31, dyn, 0, 0, x3, 0*FLEN/8, x4, x1, x2)

inst_1:
// rs1 == rd != rs2 and rs1 == rd != rs3 and rs3 != rs2, rs1==f30, rs2==f31, rs3==f29, rd==f30,fs1 == 0 and fe1 == 0x1d and fm1 == 0x12d and fs2 == 0 and fe2 == 0x0d and fm2 == 0x374 and fs3 == 0 and fe3 == 0x1c and fm3 == 0x0d3 and fcsr == 0x20 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f31; op3:f29; dest:f30; op1val:0x752d; op2val:0x3774;
op3val:0x70d3; valaddr_reg:x3; val_offset:3*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:32 */
TEST_FPR4_OP(fmsub.h, f30, f30, f31, f29, dyn, 32, 0, x3, 3*FLEN/8, x4, x1, x2)

inst_2:
// rd == rs2 == rs3 != rs1, rs1==f29, rs2==f28, rs3==f28, rd==f28,fs1 == 0 and fe1 == 0x1d and fm1 == 0x12d and fs2 == 0 and fe2 == 0x0d and fm2 == 0x374 and fs3 == 0 and fe3 == 0x1c and fm3 == 0x0d3 and fcsr == 0x40 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f29; op2:f28; op3:f28; dest:f28; op1val:0x752d; op2val:0x3774;
op3val:0x3774; valaddr_reg:x3; val_offset:6*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:64 */
TEST_FPR4_OP(fmsub.h, f28, f29, f28, f28, dyn, 64, 0, x3, 6*FLEN/8, x4, x1, x2)

inst_3:
// rs3 == rd != rs1 and rs3 == rd != rs2 and rs2 != rs1, rs1==f28, rs2==f29, rs3==f27, rd==f27,fs1 == 0 and fe1 == 0x1d and fm1 == 0x12d and fs2 == 0 and fe2 == 0x0d and fm2 == 0x374 and fs3 == 0 and fe3 == 0x1c and fm3 == 0x0d3 and fcsr == 0x60 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f28; op2:f29; op3:f27; dest:f27; op1val:0x752d; op2val:0x3774;
op3val:0x70d3; valaddr_reg:x3; val_offset:9*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fmsub.h, f27, f28, f29, f27, dyn, 96, 0, x3, 9*FLEN/8, x4, x1, x2)

inst_4:
// rs2 == rd != rs1 and rs2 == rd != rs3 and rs3 != rs1, rs1==f27, rs2==f26, rs3==f30, rd==f26,fs1 == 0 and fe1 == 0x1d and fm1 == 0x12d and fs2 == 0 and fe2 == 0x0d and fm2 == 0x374 and fs3 == 0 and fe3 == 0x1c and fm3 == 0x0d3 and fcsr == 0x80 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f27; op2:f26; op3:f30; dest:f26; op1val:0x752d; op2val:0x3774;
op3val:0x70d3; valaddr_reg:x3; val_offset:12*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:128 */
TEST_FPR4_OP(fmsub.h, f26, f27, f26, f30, dyn, 128, 0, x3, 12*FLEN/8, x4, x1, x2)

inst_5:
// rs1 == rs2 == rs3 == rd, rs1==f25, rs2==f25, rs3==f25, rd==f25,fs1 == 0 and fe1 == 0x1e and fm1 == 0x134 and fs2 == 0 and fe2 == 0x0b and fm2 == 0x31f and fs3 == 0 and fe3 == 0x1b and fm3 == 0x0a2 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f25; op2:f25; op3:f25; dest:f25; op1val:0x7934; op2val:0x7934;
op3val:0x7934; valaddr_reg:x3; val_offset:15*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f25, f25, f25, f25, dyn, 0, 0, x3, 15*FLEN/8, x4, x1, x2)

inst_6:
// rs2 == rs3 != rs1 and rs2 == rs3 != rd and rd != rs1, rs1==f26, rs2==f24, rs3==f24, rd==f29,fs1 == 0 and fe1 == 0x1e and fm1 == 0x134 and fs2 == 0 and fe2 == 0x0b and fm2 == 0x31f and fs3 == 0 and fe3 == 0x1b and fm3 == 0x0a2 and fcsr == 0x20 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f26; op2:f24; op3:f24; dest:f29; op1val:0x7934; op2val:0x2f1f;
op3val:0x2f1f; valaddr_reg:x3; val_offset:18*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:32 */
TEST_FPR4_OP(fmsub.h, f29, f26, f24, f24, dyn, 32, 0, x3, 18*FLEN/8, x4, x1, x2)

inst_7:
// rs1 == rs2 == rd != rs3, rs1==f23, rs2==f23, rs3==f26, rd==f23,fs1 == 0 and fe1 == 0x1e and fm1 == 0x134 and fs2 == 0 and fe2 == 0x0b and fm2 == 0x31f and fs3 == 0 and fe3 == 0x1b and fm3 == 0x0a2 and fcsr == 0x40 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f23; op2:f23; op3:f26; dest:f23; op1val:0x7934; op2val:0x7934;
op3val:0x6ca2; valaddr_reg:x3; val_offset:21*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:64 */
TEST_FPR4_OP(fmsub.h, f23, f23, f23, f26, dyn, 64, 0, x3, 21*FLEN/8, x4, x1, x2)

inst_8:
// rs1 == rs2 == rs3 != rd, rs1==f22, rs2==f22, rs3==f22, rd==f24,fs1 == 0 and fe1 == 0x1e and fm1 == 0x134 and fs2 == 0 and fe2 == 0x0b and fm2 == 0x31f and fs3 == 0 and fe3 == 0x1b and fm3 == 0x0a2 and fcsr == 0x60 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f22; op2:f22; op3:f22; dest:f24; op1val:0x7934; op2val:0x7934;
op3val:0x7934; valaddr_reg:x3; val_offset:24*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fmsub.h, f24, f22, f22, f22, dyn, 96, 0, x3, 24*FLEN/8, x4, x1, x2)

inst_9:
// rs1 == rs2 != rs3 and rs1 == rs2 != rd and rd != rs3, rs1==f21, rs2==f21, rs3==f23, rd==f22,fs1 == 0 and fe1 == 0x1e and fm1 == 0x134 and fs2 == 0 and fe2 == 0x0b and fm2 == 0x31f and fs3 == 0 and fe3 == 0x1b and fm3 == 0x0a2 and fcsr == 0x80 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f21; op2:f21; op3:f23; dest:f22; op1val:0x7934; op2val:0x7934;
op3val:0x6ca2; valaddr_reg:x3; val_offset:27*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:128 */
TEST_FPR4_OP(fmsub.h, f22, f21, f21, f23, dyn, 128, 0, x3, 27*FLEN/8, x4, x1, x2)

inst_10:
// rs1 == rs3 != rs2 and rs1 == rs3 != rd and rd != rs2, rs1==f20, rs2==f27, rs3==f20, rd==f21,fs1 == 0 and fe1 == 0x1e and fm1 == 0x048 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x175 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x1d9 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f20; op2:f27; op3:f20; dest:f21; op1val:0x7848; op2val:0x3975;
op3val:0x7848; valaddr_reg:x3; val_offset:30*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f21, f20, f27, f20, dyn, 0, 0, x3, 30*FLEN/8, x4, x1, x2)

inst_11:
// rs1 != rs2 and rs1 != rd and rs1 != rs3 and rs2 != rs3 and rs2 != rd and rs3 != rd, rs1==f24, rs2==f19, rs3==f21, rd==f20,fs1 == 0 and fe1 == 0x1e and fm1 == 0x048 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x175 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x1d9 and fcsr == 0x20 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f24; op2:f19; op3:f21; dest:f20; op1val:0x7848; op2val:0x3975;
op3val:0x75d9; valaddr_reg:x3; val_offset:33*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:32 */
TEST_FPR4_OP(fmsub.h, f20, f24, f19, f21, dyn, 32, 0, x3, 33*FLEN/8, x4, x1, x2)

inst_12:
// rs1==f18, rs2==f20, rs3==f17, rd==f19,fs1 == 0 and fe1 == 0x1e and fm1 == 0x048 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x175 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x1d9 and fcsr == 0x40 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f18; op2:f20; op3:f17; dest:f19; op1val:0x7848; op2val:0x3975;
op3val:0x75d9; valaddr_reg:x3; val_offset:36*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:64 */
TEST_FPR4_OP(fmsub.h, f19, f18, f20, f17, dyn, 64, 0, x3, 36*FLEN/8, x4, x1, x2)

inst_13:
// rs1==f19, rs2==f17, rs3==f16, rd==f18,fs1 == 0 and fe1 == 0x1e and fm1 == 0x048 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x175 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x1d9 and fcsr == 0x60 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f19; op2:f17; op3:f16; dest:f18; op1val:0x7848; op2val:0x3975;
op3val:0x75d9; valaddr_reg:x3; val_offset:39*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fmsub.h, f18, f19, f17, f16, dyn, 96, 0, x3, 39*FLEN/8, x4, x1, x2)

inst_14:
// rs1==f16, rs2==f18, rs3==f19, rd==f17,fs1 == 0 and fe1 == 0x1e and fm1 == 0x048 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x175 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x1d9 and fcsr == 0x80 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f16; op2:f18; op3:f19; dest:f17; op1val:0x7848; op2val:0x3975;
op3val:0x75d9; valaddr_reg:x3; val_offset:42*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:128 */
TEST_FPR4_OP(fmsub.h, f17, f16, f18, f19, dyn, 128, 0, x3, 42*FLEN/8, x4, x1, x2)

inst_15:
// rs1==f17, rs2==f15, rs3==f18, rd==f16,fs1 == 0 and fe1 == 0x1a and fm1 == 0x36c and fs2 == 0 and fe2 == 0x12 and fm2 == 0x05f and fs3 == 0 and fe3 == 0x1e and fm3 == 0x00e and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f17; op2:f15; op3:f18; dest:f16; op1val:0x6b6c; op2val:0x485f;
op3val:0x780e; valaddr_reg:x3; val_offset:45*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f16, f17, f15, f18, dyn, 0, 0, x3, 45*FLEN/8, x4, x1, x2)

inst_16:
// rs1==f14, rs2==f16, rs3==f13, rd==f15,fs1 == 0 and fe1 == 0x1a and fm1 == 0x36c and fs2 == 0 and fe2 == 0x12 and fm2 == 0x05f and fs3 == 0 and fe3 == 0x1e and fm3 == 0x00e and fcsr == 0x20 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f14; op2:f16; op3:f13; dest:f15; op1val:0x6b6c; op2val:0x485f;
op3val:0x780e; valaddr_reg:x3; val_offset:48*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:32 */
TEST_FPR4_OP(fmsub.h, f15, f14, f16, f13, dyn, 32, 0, x3, 48*FLEN/8, x4, x1, x2)

inst_17:
// rs1==f15, rs2==f13, rs3==f12, rd==f14,fs1 == 0 and fe1 == 0x1a and fm1 == 0x36c and fs2 == 0 and fe2 == 0x12 and fm2 == 0x05f and fs3 == 0 and fe3 == 0x1e and fm3 == 0x00e and fcsr == 0x40 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f15; op2:f13; op3:f12; dest:f14; op1val:0x6b6c; op2val:0x485f;
op3val:0x780e; valaddr_reg:x3; val_offset:51*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:64 */
TEST_FPR4_OP(fmsub.h, f14, f15, f13, f12, dyn, 64, 0, x3, 51*FLEN/8, x4, x1, x2)

inst_18:
// rs1==f12, rs2==f14, rs3==f15, rd==f13,fs1 == 0 and fe1 == 0x1a and fm1 == 0x36c and fs2 == 0 and fe2 == 0x12 and fm2 == 0x05f and fs3 == 0 and fe3 == 0x1e and fm3 == 0x00e and fcsr == 0x60 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f12; op2:f14; op3:f15; dest:f13; op1val:0x6b6c; op2val:0x485f;
op3val:0x780e; valaddr_reg:x3; val_offset:54*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fmsub.h, f13, f12, f14, f15, dyn, 96, 0, x3, 54*FLEN/8, x4, x1, x2)

inst_19:
// rs1==f13, rs2==f11, rs3==f14, rd==f12,fs1 == 0 and fe1 == 0x1a and fm1 == 0x36c and fs2 == 0 and fe2 == 0x12 and fm2 == 0x05f and fs3 == 0 and fe3 == 0x1e and fm3 == 0x00e and fcsr == 0x80 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f13; op2:f11; op3:f14; dest:f12; op1val:0x6b6c; op2val:0x485f;
op3val:0x780e; valaddr_reg:x3; val_offset:57*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:128 */
TEST_FPR4_OP(fmsub.h, f12, f13, f11, f14, dyn, 128, 0, x3, 57*FLEN/8, x4, x1, x2)

inst_20:
// rs1==f10, rs2==f12, rs3==f9, rd==f11,fs1 == 0 and fe1 == 0x1a and fm1 == 0x0cc and fs2 == 0 and fe2 == 0x12 and fm2 == 0x1c7 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x2ef and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f10; op2:f12; op3:f9; dest:f11; op1val:0x68cc; op2val:0x49c7;
op3val:0x76ef; valaddr_reg:x3; val_offset:60*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f11, f10, f12, f9, dyn, 0, 0, x3, 60*FLEN/8, x4, x1, x2)

inst_21:
// rs1==f11, rs2==f9, rs3==f8, rd==f10,fs1 == 0 and fe1 == 0x1a and fm1 == 0x0cc and fs2 == 0 and fe2 == 0x12 and fm2 == 0x1c7 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x2ef and fcsr == 0x20 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f11; op2:f9; op3:f8; dest:f10; op1val:0x68cc; op2val:0x49c7;
op3val:0x76ef; valaddr_reg:x3; val_offset:63*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:32 */
TEST_FPR4_OP(fmsub.h, f10, f11, f9, f8, dyn, 32, 0, x3, 63*FLEN/8, x4, x1, x2)

inst_22:
// rs1==f8, rs2==f10, rs3==f11, rd==f9,fs1 == 0 and fe1 == 0x1a and fm1 == 0x0cc and fs2 == 0 and fe2 == 0x12 and fm2 == 0x1c7 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x2ef and fcsr == 0x40 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f8; op2:f10; op3:f11; dest:f9; op1val:0x68cc; op2val:0x49c7;
op3val:0x76ef; valaddr_reg:x3; val_offset:66*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:64 */
TEST_FPR4_OP(fmsub.h, f9, f8, f10, f11, dyn, 64, 0, x3, 66*FLEN/8, x4, x1, x2)

inst_23:
// rs1==f9, rs2==f7, rs3==f10, rd==f8,fs1 == 0 and fe1 == 0x1a and fm1 == 0x0cc and fs2 == 0 and fe2 == 0x12 and fm2 == 0x1c7 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x2ef and fcsr == 0x60 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f9; op2:f7; op3:f10; dest:f8; op1val:0x68cc; op2val:0x49c7;
op3val:0x76ef; valaddr_reg:x3; val_offset:69*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fmsub.h, f8, f9, f7, f10, dyn, 96, 0, x3, 69*FLEN/8, x4, x1, x2)

inst_24:
// rs1==f6, rs2==f8, rs3==f5, rd==f7,fs1 == 0 and fe1 == 0x1a and fm1 == 0x0cc and fs2 == 0 and fe2 == 0x12 and fm2 == 0x1c7 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x2ef and fcsr == 0x80 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f6; op2:f8; op3:f5; dest:f7; op1val:0x68cc; op2val:0x49c7;
op3val:0x76ef; valaddr_reg:x3; val_offset:72*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:128 */
TEST_FPR4_OP(fmsub.h, f7, f6, f8, f5, dyn, 128, 0, x3, 72*FLEN/8, x4, x1, x2)

inst_25:
// rs1==f7, rs2==f5, rs3==f4, rd==f6,fs1 == 0 and fe1 == 0x1b and fm1 == 0x078 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x131 and fs3 == 0 and fe3 == 0x1b and fm3 == 0x1cd and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f7; op2:f5; op3:f4; dest:f6; op1val:0x6c78; op2val:0x3d31;
op3val:0x6dcd; valaddr_reg:x3; val_offset:75*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f6, f7, f5, f4, dyn, 0, 0, x3, 75*FLEN/8, x4, x1, x2)

inst_26:
// rs1==f4, rs2==f6, rs3==f7, rd==f5,fs1 == 0 and fe1 == 0x1b and fm1 == 0x078 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x131 and fs3 == 0 and fe3 == 0x1b and fm3 == 0x1cd and fcsr == 0x20 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f4; op2:f6; op3:f7; dest:f5; op1val:0x6c78; op2val:0x3d31;
op3val:0x6dcd; valaddr_reg:x3; val_offset:78*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:32 */
TEST_FPR4_OP(fmsub.h, f5, f4, f6, f7, dyn, 32, 0, x3, 78*FLEN/8, x4, x1, x2)

inst_27:
// rs1==f5, rs2==f3, rs3==f6, rd==f4,fs1 == 0 and fe1 == 0x1b and fm1 == 0x078 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x131 and fs3 == 0 and fe3 == 0x1b and fm3 == 0x1cd and fcsr == 0x40 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f5; op2:f3; op3:f6; dest:f4; op1val:0x6c78; op2val:0x3d31;
op3val:0x6dcd; valaddr_reg:x3; val_offset:81*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:64 */
TEST_FPR4_OP(fmsub.h, f4, f5, f3, f6, dyn, 64, 0, x3, 81*FLEN/8, x4, x1, x2)

inst_28:
// rs1==f2, rs2==f4, rs3==f1, rd==f3,fs1 == 0 and fe1 == 0x1b and fm1 == 0x078 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x131 and fs3 == 0 and fe3 == 0x1b and fm3 == 0x1cd and fcsr == 0x60 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f2; op2:f4; op3:f1; dest:f3; op1val:0x6c78; op2val:0x3d31;
op3val:0x6dcd; valaddr_reg:x3; val_offset:84*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fmsub.h, f3, f2, f4, f1, dyn, 96, 0, x3, 84*FLEN/8, x4, x1, x2)

inst_29:
// rs1==f3, rs2==f1, rs3==f0, rd==f2,fs1 == 0 and fe1 == 0x1b and fm1 == 0x078 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x131 and fs3 == 0 and fe3 == 0x1b and fm3 == 0x1cd and fcsr == 0x80 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f3; op2:f1; op3:f0; dest:f2; op1val:0x6c78; op2val:0x3d31;
op3val:0x6dcd; valaddr_reg:x3; val_offset:87*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:128 */
TEST_FPR4_OP(fmsub.h, f2, f3, f1, f0, dyn, 128, 0, x3, 87*FLEN/8, x4, x1, x2)

inst_30:
// rs1==f0, rs2==f2, rs3==f3, rd==f1,fs1 == 0 and fe1 == 0x1d and fm1 == 0x2ca and fs2 == 0 and fe2 == 0x0f and fm2 == 0x3ca and fs3 == 0 and fe3 == 0x1e and fm3 == 0x29c and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f0; op2:f2; op3:f3; dest:f1; op1val:0x76ca; op2val:0x3fca;
op3val:0x7a9c; valaddr_reg:x3; val_offset:90*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f1, f0, f2, f3, dyn, 0, 0, x3, 90*FLEN/8, x4, x1, x2)

inst_31:
// rs1==f1,fs1 == 0 and fe1 == 0x1d and fm1 == 0x2ca and fs2 == 0 and fe2 == 0x0f and fm2 == 0x3ca and fs3 == 0 and fe3 == 0x1e and fm3 == 0x29c and fcsr == 0x20 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f1; op2:f30; op3:f29; dest:f31; op1val:0x76ca; op2val:0x3fca;
op3val:0x7a9c; valaddr_reg:x3; val_offset:93*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:32 */
TEST_FPR4_OP(fmsub.h, f31, f1, f30, f29, dyn, 32, 0, x3, 93*FLEN/8, x4, x1, x2)

inst_32:
// rs2==f0,fs1 == 0 and fe1 == 0x1d and fm1 == 0x2ca and fs2 == 0 and fe2 == 0x0f and fm2 == 0x3ca and fs3 == 0 and fe3 == 0x1e and fm3 == 0x29c and fcsr == 0x40 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f0; op3:f29; dest:f31; op1val:0x76ca; op2val:0x3fca;
op3val:0x7a9c; valaddr_reg:x3; val_offset:96*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:64 */
TEST_FPR4_OP(fmsub.h, f31, f30, f0, f29, dyn, 64, 0, x3, 96*FLEN/8, x4, x1, x2)

inst_33:
// rs3==f2,fs1 == 0 and fe1 == 0x1d and fm1 == 0x2ca and fs2 == 0 and fe2 == 0x0f and fm2 == 0x3ca and fs3 == 0 and fe3 == 0x1e and fm3 == 0x29c and fcsr == 0x60 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f2; dest:f31; op1val:0x76ca; op2val:0x3fca;
op3val:0x7a9c; valaddr_reg:x3; val_offset:99*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f2, dyn, 96, 0, x3, 99*FLEN/8, x4, x1, x2)

inst_34:
// rd==f0,fs1 == 0 and fe1 == 0x1d and fm1 == 0x2ca and fs2 == 0 and fe2 == 0x0f and fm2 == 0x3ca and fs3 == 0 and fe3 == 0x1e and fm3 == 0x29c and fcsr == 0x80 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f31; op2:f30; op3:f29; dest:f0; op1val:0x76ca; op2val:0x3fca;
op3val:0x7a9c; valaddr_reg:x3; val_offset:102*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:128 */
TEST_FPR4_OP(fmsub.h, f0, f31, f30, f29, dyn, 128, 0, x3, 102*FLEN/8, x4, x1, x2)

inst_35:
// fs1 == 0 and fe1 == 0x1b and fm1 == 0x3eb and fs2 == 0 and fe2 == 0x0f and fm2 == 0x336 and fs3 == 0 and fe3 == 0x1c and fm3 == 0x323 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x6feb; op2val:0x3f36;
op3val:0x7323; valaddr_reg:x3; val_offset:105*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 105*FLEN/8, x4, x1, x2)

inst_36:
// fs1 == 0 and fe1 == 0x1b and fm1 == 0x3eb and fs2 == 0 and fe2 == 0x0f and fm2 == 0x336 and fs3 == 0 and fe3 == 0x1c and fm3 == 0x323 and fcsr == 0x20 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x6feb; op2val:0x3f36;
op3val:0x7323; valaddr_reg:x3; val_offset:108*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:32 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 32, 0, x3, 108*FLEN/8, x4, x1, x2)

inst_37:
// fs1 == 0 and fe1 == 0x1b and fm1 == 0x3eb and fs2 == 0 and fe2 == 0x0f and fm2 == 0x336 and fs3 == 0 and fe3 == 0x1c and fm3 == 0x323 and fcsr == 0x40 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x6feb; op2val:0x3f36;
op3val:0x7323; valaddr_reg:x3; val_offset:111*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:64 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 64, 0, x3, 111*FLEN/8, x4, x1, x2)

inst_38:
// fs1 == 0 and fe1 == 0x1b and fm1 == 0x3eb and fs2 == 0 and fe2 == 0x0f and fm2 == 0x336 and fs3 == 0 and fe3 == 0x1c and fm3 == 0x323 and fcsr == 0x60 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x6feb; op2val:0x3f36;
op3val:0x7323; valaddr_reg:x3; val_offset:114*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 96, 0, x3, 114*FLEN/8, x4, x1, x2)

inst_39:
// fs1 == 0 and fe1 == 0x1b and fm1 == 0x3eb and fs2 == 0 and fe2 == 0x0f and fm2 == 0x336 and fs3 == 0 and fe3 == 0x1c and fm3 == 0x323 and fcsr == 0x80 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x6feb; op2val:0x3f36;
op3val:0x7323; valaddr_reg:x3; val_offset:117*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:128 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 128, 0, x3, 117*FLEN/8, x4, x1, x2)

inst_40:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x104 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x20a and fs3 == 0 and fe3 == 0x1e and fm3 == 0x393 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7904; op2val:0x3e0a;
op3val:0x7b93; valaddr_reg:x3; val_offset:120*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 120*FLEN/8, x4, x1, x2)

inst_41:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x104 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x20a and fs3 == 0 and fe3 == 0x1e and fm3 == 0x393 and fcsr == 0x20 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7904; op2val:0x3e0a;
op3val:0x7b93; valaddr_reg:x3; val_offset:123*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:32 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 32, 0, x3, 123*FLEN/8, x4, x1, x2)

inst_42:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x104 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x20a and fs3 == 0 and fe3 == 0x1e and fm3 == 0x393 and fcsr == 0x40 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7904; op2val:0x3e0a;
op3val:0x7b93; valaddr_reg:x3; val_offset:126*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:64 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 64, 0, x3, 126*FLEN/8, x4, x1, x2)

inst_43:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x104 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x20a and fs3 == 0 and fe3 == 0x1e and fm3 == 0x393 and fcsr == 0x60 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7904; op2val:0x3e0a;
op3val:0x7b93; valaddr_reg:x3; val_offset:129*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 96, 0, x3, 129*FLEN/8, x4, x1, x2)

inst_44:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x104 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x20a and fs3 == 0 and fe3 == 0x1e and fm3 == 0x393 and fcsr == 0x80 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7904; op2val:0x3e0a;
op3val:0x7b93; valaddr_reg:x3; val_offset:132*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:128 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 128, 0, x3, 132*FLEN/8, x4, x1, x2)

inst_45:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x09d and fs2 == 0 and fe2 == 0x0e and fm2 == 0x17f and fs3 == 0 and fe3 == 0x1d and fm3 == 0x258 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x789d; op2val:0x397f;
op3val:0x7658; valaddr_reg:x3; val_offset:135*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 135*FLEN/8, x4, x1, x2)

inst_46:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x09d and fs2 == 0 and fe2 == 0x0e and fm2 == 0x17f and fs3 == 0 and fe3 == 0x1d and fm3 == 0x258 and fcsr == 0x20 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x789d; op2val:0x397f;
op3val:0x7658; valaddr_reg:x3; val_offset:138*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:32 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 32, 0, x3, 138*FLEN/8, x4, x1, x2)

inst_47:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x09d and fs2 == 0 and fe2 == 0x0e and fm2 == 0x17f and fs3 == 0 and fe3 == 0x1d and fm3 == 0x258 and fcsr == 0x40 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x789d; op2val:0x397f;
op3val:0x7658; valaddr_reg:x3; val_offset:141*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:64 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 64, 0, x3, 141*FLEN/8, x4, x1, x2)

inst_48:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x09d and fs2 == 0 and fe2 == 0x0e and fm2 == 0x17f and fs3 == 0 and fe3 == 0x1d and fm3 == 0x258 and fcsr == 0x60 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x789d; op2val:0x397f;
op3val:0x7658; valaddr_reg:x3; val_offset:144*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 96, 0, x3, 144*FLEN/8, x4, x1, x2)

inst_49:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x09d and fs2 == 0 and fe2 == 0x0e and fm2 == 0x17f and fs3 == 0 and fe3 == 0x1d and fm3 == 0x258 and fcsr == 0x80 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x789d; op2val:0x397f;
op3val:0x7658; valaddr_reg:x3; val_offset:147*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:128 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 128, 0, x3, 147*FLEN/8, x4, x1, x2)

inst_50:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ce and fs2 == 0 and fe2 == 0x0a and fm2 == 0x21c and fs3 == 0 and fe3 == 0x1a and fm3 == 0x1f6 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7bce; op2val:0x2a1c;
op3val:0x69f6; valaddr_reg:x3; val_offset:150*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 150*FLEN/8, x4, x1, x2)

inst_51:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ce and fs2 == 0 and fe2 == 0x0a and fm2 == 0x21c and fs3 == 0 and fe3 == 0x1a and fm3 == 0x1f6 and fcsr == 0x20 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7bce; op2val:0x2a1c;
op3val:0x69f6; valaddr_reg:x3; val_offset:153*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:32 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 32, 0, x3, 153*FLEN/8, x4, x1, x2)

inst_52:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ce and fs2 == 0 and fe2 == 0x0a and fm2 == 0x21c and fs3 == 0 and fe3 == 0x1a and fm3 == 0x1f6 and fcsr == 0x40 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7bce; op2val:0x2a1c;
op3val:0x69f6; valaddr_reg:x3; val_offset:156*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:64 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 64, 0, x3, 156*FLEN/8, x4, x1, x2)

inst_53:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ce and fs2 == 0 and fe2 == 0x0a and fm2 == 0x21c and fs3 == 0 and fe3 == 0x1a and fm3 == 0x1f6 and fcsr == 0x60 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7bce; op2val:0x2a1c;
op3val:0x69f6; valaddr_reg:x3; val_offset:159*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 96, 0, x3, 159*FLEN/8, x4, x1, x2)

inst_54:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ce and fs2 == 0 and fe2 == 0x0a and fm2 == 0x21c and fs3 == 0 and fe3 == 0x1a and fm3 == 0x1f6 and fcsr == 0x80 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7bce; op2val:0x2a1c;
op3val:0x69f6; valaddr_reg:x3; val_offset:162*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:128 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 128, 0, x3, 162*FLEN/8, x4, x1, x2)

inst_55:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2dd and fs2 == 0 and fe2 == 0x0d and fm2 == 0x165 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x0a1 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7add; op2val:0x3565;
op3val:0x74a1; valaddr_reg:x3; val_offset:165*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 165*FLEN/8, x4, x1, x2)

inst_56:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2dd and fs2 == 0 and fe2 == 0x0d and fm2 == 0x165 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x0a1 and fcsr == 0x20 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7add; op2val:0x3565;
op3val:0x74a1; valaddr_reg:x3; val_offset:168*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:32 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 32, 0, x3, 168*FLEN/8, x4, x1, x2)

inst_57:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2dd and fs2 == 0 and fe2 == 0x0d and fm2 == 0x165 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x0a1 and fcsr == 0x40 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7add; op2val:0x3565;
op3val:0x74a1; valaddr_reg:x3; val_offset:171*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:64 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 64, 0, x3, 171*FLEN/8, x4, x1, x2)

inst_58:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2dd and fs2 == 0 and fe2 == 0x0d and fm2 == 0x165 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x0a1 and fcsr == 0x60 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7add; op2val:0x3565;
op3val:0x74a1; valaddr_reg:x3; val_offset:174*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 96, 0, x3, 174*FLEN/8, x4, x1, x2)

inst_59:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2dd and fs2 == 0 and fe2 == 0x0d and fm2 == 0x165 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x0a1 and fcsr == 0x80 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7add; op2val:0x3565;
op3val:0x74a1; valaddr_reg:x3; val_offset:177*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:128 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 128, 0, x3, 177*FLEN/8, x4, x1, x2)

inst_60:
// fs1 == 0 and fe1 == 0x1c and fm1 == 0x09d and fs2 == 0 and fe2 == 0x0e and fm2 == 0x288 and fs3 == 0 and fe3 == 0x1b and fm3 == 0x389 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x709d; op2val:0x3a88;
op3val:0x6f89; valaddr_reg:x3; val_offset:180*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 180*FLEN/8, x4, x1, x2)

inst_61:
// fs1 == 0 and fe1 == 0x1c and fm1 == 0x09d and fs2 == 0 and fe2 == 0x0e and fm2 == 0x288 and fs3 == 0 and fe3 == 0x1b and fm3 == 0x389 and fcsr == 0x20 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x709d; op2val:0x3a88;
op3val:0x6f89; valaddr_reg:x3; val_offset:183*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:32 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 32, 0, x3, 183*FLEN/8, x4, x1, x2)

inst_62:
// fs1 == 0 and fe1 == 0x1c and fm1 == 0x09d and fs2 == 0 and fe2 == 0x0e and fm2 == 0x288 and fs3 == 0 and fe3 == 0x1b and fm3 == 0x389 and fcsr == 0x40 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x709d; op2val:0x3a88;
op3val:0x6f89; valaddr_reg:x3; val_offset:186*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:64 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 64, 0, x3, 186*FLEN/8, x4, x1, x2)

inst_63:
// fs1 == 0 and fe1 == 0x1c and fm1 == 0x09d and fs2 == 0 and fe2 == 0x0e and fm2 == 0x288 and fs3 == 0 and fe3 == 0x1b and fm3 == 0x389 and fcsr == 0x60 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x709d; op2val:0x3a88;
op3val:0x6f89; valaddr_reg:x3; val_offset:189*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 96, 0, x3, 189*FLEN/8, x4, x1, x2)

inst_64:
// fs1 == 0 and fe1 == 0x1c and fm1 == 0x09d and fs2 == 0 and fe2 == 0x0e and fm2 == 0x288 and fs3 == 0 and fe3 == 0x1b and fm3 == 0x389 and fcsr == 0x80 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x709d; op2val:0x3a88;
op3val:0x6f89; valaddr_reg:x3; val_offset:192*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:128 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 128, 0, x3, 192*FLEN/8, x4, x1, x2)

inst_65:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x0ee and fs2 == 0 and fe2 == 0x10 and fm2 == 0x14a and fs3 == 0 and fe3 == 0x1e and fm3 == 0x286 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x74ee; op2val:0x414a;
op3val:0x7a86; valaddr_reg:x3; val_offset:195*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 195*FLEN/8, x4, x1, x2)

inst_66:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x0ee and fs2 == 0 and fe2 == 0x10 and fm2 == 0x14a and fs3 == 0 and fe3 == 0x1e and fm3 == 0x286 and fcsr == 0x20 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x74ee; op2val:0x414a;
op3val:0x7a86; valaddr_reg:x3; val_offset:198*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:32 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 32, 0, x3, 198*FLEN/8, x4, x1, x2)

inst_67:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x0ee and fs2 == 0 and fe2 == 0x10 and fm2 == 0x14a and fs3 == 0 and fe3 == 0x1e and fm3 == 0x286 and fcsr == 0x40 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x74ee; op2val:0x414a;
op3val:0x7a86; valaddr_reg:x3; val_offset:201*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:64 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 64, 0, x3, 201*FLEN/8, x4, x1, x2)

inst_68:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x0ee and fs2 == 0 and fe2 == 0x10 and fm2 == 0x14a and fs3 == 0 and fe3 == 0x1e and fm3 == 0x286 and fcsr == 0x60 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x74ee; op2val:0x414a;
op3val:0x7a86; valaddr_reg:x3; val_offset:204*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 96, 0, x3, 204*FLEN/8, x4, x1, x2)

inst_69:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x0ee and fs2 == 0 and fe2 == 0x10 and fm2 == 0x14a and fs3 == 0 and fe3 == 0x1e and fm3 == 0x286 and fcsr == 0x80 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x74ee; op2val:0x414a;
op3val:0x7a86; valaddr_reg:x3; val_offset:207*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:128 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 128, 0, x3, 207*FLEN/8, x4, x1, x2)

inst_70:
// fs1 == 0 and fe1 == 0x1c and fm1 == 0x1c7 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x26f and fs3 == 0 and fe3 == 0x1e and fm3 == 0x0a6 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x71c7; op2val:0x426f;
op3val:0x78a6; valaddr_reg:x3; val_offset:210*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 210*FLEN/8, x4, x1, x2)

inst_71:
// fs1 == 0 and fe1 == 0x1c and fm1 == 0x1c7 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x26f and fs3 == 0 and fe3 == 0x1e and fm3 == 0x0a6 and fcsr == 0x20 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x71c7; op2val:0x426f;
op3val:0x78a6; valaddr_reg:x3; val_offset:213*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:32 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 32, 0, x3, 213*FLEN/8, x4, x1, x2)

inst_72:
// fs1 == 0 and fe1 == 0x1c and fm1 == 0x1c7 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x26f and fs3 == 0 and fe3 == 0x1e and fm3 == 0x0a6 and fcsr == 0x40 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x71c7; op2val:0x426f;
op3val:0x78a6; valaddr_reg:x3; val_offset:216*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:64 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 64, 0, x3, 216*FLEN/8, x4, x1, x2)

inst_73:
// fs1 == 0 and fe1 == 0x1c and fm1 == 0x1c7 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x26f and fs3 == 0 and fe3 == 0x1e and fm3 == 0x0a6 and fcsr == 0x60 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x71c7; op2val:0x426f;
op3val:0x78a6; valaddr_reg:x3; val_offset:219*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 96, 0, x3, 219*FLEN/8, x4, x1, x2)

inst_74:
// fs1 == 0 and fe1 == 0x1c and fm1 == 0x1c7 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x26f and fs3 == 0 and fe3 == 0x1e and fm3 == 0x0a6 and fcsr == 0x80 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x71c7; op2val:0x426f;
op3val:0x78a6; valaddr_reg:x3; val_offset:222*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:128 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 128, 0, x3, 222*FLEN/8, x4, x1, x2)

inst_75:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x11b and fs2 == 0 and fe2 == 0x0e and fm2 == 0x0a9 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x1f4 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x791b; op2val:0x38a9;
op3val:0x75f4; valaddr_reg:x3; val_offset:225*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 225*FLEN/8, x4, x1, x2)

inst_76:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x11b and fs2 == 0 and fe2 == 0x0e and fm2 == 0x0a9 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x1f4 and fcsr == 0x20 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x791b; op2val:0x38a9;
op3val:0x75f4; valaddr_reg:x3; val_offset:228*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:32 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 32, 0, x3, 228*FLEN/8, x4, x1, x2)

inst_77:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x11b and fs2 == 0 and fe2 == 0x0e and fm2 == 0x0a9 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x1f4 and fcsr == 0x40 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x791b; op2val:0x38a9;
op3val:0x75f4; valaddr_reg:x3; val_offset:231*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:64 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 64, 0, x3, 231*FLEN/8, x4, x1, x2)

inst_78:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x11b and fs2 == 0 and fe2 == 0x0e and fm2 == 0x0a9 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x1f4 and fcsr == 0x60 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x791b; op2val:0x38a9;
op3val:0x75f4; valaddr_reg:x3; val_offset:234*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 96, 0, x3, 234*FLEN/8, x4, x1, x2)

inst_79:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x11b and fs2 == 0 and fe2 == 0x0e and fm2 == 0x0a9 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x1f4 and fcsr == 0x80 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x791b; op2val:0x38a9;
op3val:0x75f4; valaddr_reg:x3; val_offset:237*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:128 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 128, 0, x3, 237*FLEN/8, x4, x1, x2)

inst_80:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x061 and fs2 == 0 and fe2 == 0x0b and fm2 == 0x356 and fs3 == 0 and fe3 == 0x1b and fm3 == 0x004 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7861; op2val:0x2f56;
op3val:0x6c04; valaddr_reg:x3; val_offset:240*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 240*FLEN/8, x4, x1, x2)

inst_81:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x061 and fs2 == 0 and fe2 == 0x0b and fm2 == 0x356 and fs3 == 0 and fe3 == 0x1b and fm3 == 0x004 and fcsr == 0x20 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7861; op2val:0x2f56;
op3val:0x6c04; valaddr_reg:x3; val_offset:243*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:32 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 32, 0, x3, 243*FLEN/8, x4, x1, x2)

inst_82:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x061 and fs2 == 0 and fe2 == 0x0b and fm2 == 0x356 and fs3 == 0 and fe3 == 0x1b and fm3 == 0x004 and fcsr == 0x40 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7861; op2val:0x2f56;
op3val:0x6c04; valaddr_reg:x3; val_offset:246*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:64 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 64, 0, x3, 246*FLEN/8, x4, x1, x2)

inst_83:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x061 and fs2 == 0 and fe2 == 0x0b and fm2 == 0x356 and fs3 == 0 and fe3 == 0x1b and fm3 == 0x004 and fcsr == 0x60 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7861; op2val:0x2f56;
op3val:0x6c04; valaddr_reg:x3; val_offset:249*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 96, 0, x3, 249*FLEN/8, x4, x1, x2)

inst_84:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x061 and fs2 == 0 and fe2 == 0x0b and fm2 == 0x356 and fs3 == 0 and fe3 == 0x1b and fm3 == 0x004 and fcsr == 0x80 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7861; op2val:0x2f56;
op3val:0x6c04; valaddr_reg:x3; val_offset:252*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:128 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 128, 0, x3, 252*FLEN/8, x4, x1, x2)

inst_85:
// fs1 == 0 and fe1 == 0x1a and fm1 == 0x3a0 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x2e8 and fs3 == 0 and fe3 == 0x1c and fm3 == 0x296 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x6ba0; op2val:0x42e8;
op3val:0x7296; valaddr_reg:x3; val_offset:255*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 255*FLEN/8, x4, x1, x2)

inst_86:
// fs1 == 0 and fe1 == 0x1a and fm1 == 0x3a0 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x2e8 and fs3 == 0 and fe3 == 0x1c and fm3 == 0x296 and fcsr == 0x20 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x6ba0; op2val:0x42e8;
op3val:0x7296; valaddr_reg:x3; val_offset:258*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:32 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 32, 0, x3, 258*FLEN/8, x4, x1, x2)

inst_87:
// fs1 == 0 and fe1 == 0x1a and fm1 == 0x3a0 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x2e8 and fs3 == 0 and fe3 == 0x1c and fm3 == 0x296 and fcsr == 0x40 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x6ba0; op2val:0x42e8;
op3val:0x7296; valaddr_reg:x3; val_offset:261*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:64 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 64, 0, x3, 261*FLEN/8, x4, x1, x2)

inst_88:
// fs1 == 0 and fe1 == 0x1a and fm1 == 0x3a0 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x2e8 and fs3 == 0 and fe3 == 0x1c and fm3 == 0x296 and fcsr == 0x60 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x6ba0; op2val:0x42e8;
op3val:0x7296; valaddr_reg:x3; val_offset:264*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 96, 0, x3, 264*FLEN/8, x4, x1, x2)

inst_89:
// fs1 == 0 and fe1 == 0x1a and fm1 == 0x3a0 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x2e8 and fs3 == 0 and fe3 == 0x1c and fm3 == 0x296 and fcsr == 0x80 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x6ba0; op2val:0x42e8;
op3val:0x7296; valaddr_reg:x3; val_offset:267*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:128 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 128, 0, x3, 267*FLEN/8, x4, x1, x2)

inst_90:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x170 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x107 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x2d6 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7970; op2val:0x3907;
op3val:0x76d6; valaddr_reg:x3; val_offset:270*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 270*FLEN/8, x4, x1, x2)

inst_91:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x170 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x107 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x2d6 and fcsr == 0x20 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7970; op2val:0x3907;
op3val:0x76d6; valaddr_reg:x3; val_offset:273*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:32 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 32, 0, x3, 273*FLEN/8, x4, x1, x2)

inst_92:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x170 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x107 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x2d6 and fcsr == 0x40 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7970; op2val:0x3907;
op3val:0x76d6; valaddr_reg:x3; val_offset:276*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:64 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 64, 0, x3, 276*FLEN/8, x4, x1, x2)

inst_93:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x170 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x107 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x2d6 and fcsr == 0x60 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7970; op2val:0x3907;
op3val:0x76d6; valaddr_reg:x3; val_offset:279*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 96, 0, x3, 279*FLEN/8, x4, x1, x2)

inst_94:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x170 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x107 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x2d6 and fcsr == 0x80 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7970; op2val:0x3907;
op3val:0x76d6; valaddr_reg:x3; val_offset:282*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:128 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 128, 0, x3, 282*FLEN/8, x4, x1, x2)

inst_95:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x106 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x374 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x0ae and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7506; op2val:0x3f74;
op3val:0x78ae; valaddr_reg:x3; val_offset:285*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 285*FLEN/8, x4, x1, x2)

inst_96:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x106 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x374 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x0ae and fcsr == 0x20 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7506; op2val:0x3f74;
op3val:0x78ae; valaddr_reg:x3; val_offset:288*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:32 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 32, 0, x3, 288*FLEN/8, x4, x1, x2)

inst_97:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x106 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x374 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x0ae and fcsr == 0x40 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7506; op2val:0x3f74;
op3val:0x78ae; valaddr_reg:x3; val_offset:291*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:64 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 64, 0, x3, 291*FLEN/8, x4, x1, x2)

inst_98:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x106 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x374 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x0ae and fcsr == 0x60 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7506; op2val:0x3f74;
op3val:0x78ae; valaddr_reg:x3; val_offset:294*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 96, 0, x3, 294*FLEN/8, x4, x1, x2)

inst_99:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x106 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x374 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x0ae and fcsr == 0x80 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7506; op2val:0x3f74;
op3val:0x78ae; valaddr_reg:x3; val_offset:297*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:128 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 128, 0, x3, 297*FLEN/8, x4, x1, x2)

inst_100:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x33f and fs2 == 0 and fe2 == 0x0e and fm2 == 0x14a and fs3 == 0 and fe3 == 0x1d and fm3 == 0x0cb and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x773f; op2val:0x394a;
op3val:0x74cb; valaddr_reg:x3; val_offset:300*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 300*FLEN/8, x4, x1, x2)

inst_101:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x33f and fs2 == 0 and fe2 == 0x0e and fm2 == 0x14a and fs3 == 0 and fe3 == 0x1d and fm3 == 0x0cb and fcsr == 0x20 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x773f; op2val:0x394a;
op3val:0x74cb; valaddr_reg:x3; val_offset:303*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:32 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 32, 0, x3, 303*FLEN/8, x4, x1, x2)

inst_102:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x33f and fs2 == 0 and fe2 == 0x0e and fm2 == 0x14a and fs3 == 0 and fe3 == 0x1d and fm3 == 0x0cb and fcsr == 0x40 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x773f; op2val:0x394a;
op3val:0x74cb; valaddr_reg:x3; val_offset:306*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:64 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 64, 0, x3, 306*FLEN/8, x4, x1, x2)

inst_103:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x33f and fs2 == 0 and fe2 == 0x0e and fm2 == 0x14a and fs3 == 0 and fe3 == 0x1d and fm3 == 0x0cb and fcsr == 0x60 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x773f; op2val:0x394a;
op3val:0x74cb; valaddr_reg:x3; val_offset:309*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 96, 0, x3, 309*FLEN/8, x4, x1, x2)

inst_104:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x33f and fs2 == 0 and fe2 == 0x0e and fm2 == 0x14a and fs3 == 0 and fe3 == 0x1d and fm3 == 0x0cb and fcsr == 0x80 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x773f; op2val:0x394a;
op3val:0x74cb; valaddr_reg:x3; val_offset:312*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:128 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 128, 0, x3, 312*FLEN/8, x4, x1, x2)

inst_105:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x25a and fs2 == 0 and fe2 == 0x0e and fm2 == 0x30a and fs3 == 0 and fe3 == 0x1e and fm3 == 0x196 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7a5a; op2val:0x3b0a;
op3val:0x7996; valaddr_reg:x3; val_offset:315*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 315*FLEN/8, x4, x1, x2)

inst_106:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x25a and fs2 == 0 and fe2 == 0x0e and fm2 == 0x30a and fs3 == 0 and fe3 == 0x1e and fm3 == 0x196 and fcsr == 0x20 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7a5a; op2val:0x3b0a;
op3val:0x7996; valaddr_reg:x3; val_offset:318*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:32 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 32, 0, x3, 318*FLEN/8, x4, x1, x2)

inst_107:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x25a and fs2 == 0 and fe2 == 0x0e and fm2 == 0x30a and fs3 == 0 and fe3 == 0x1e and fm3 == 0x196 and fcsr == 0x40 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7a5a; op2val:0x3b0a;
op3val:0x7996; valaddr_reg:x3; val_offset:321*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:64 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 64, 0, x3, 321*FLEN/8, x4, x1, x2)

inst_108:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x25a and fs2 == 0 and fe2 == 0x0e and fm2 == 0x30a and fs3 == 0 and fe3 == 0x1e and fm3 == 0x196 and fcsr == 0x60 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7a5a; op2val:0x3b0a;
op3val:0x7996; valaddr_reg:x3; val_offset:324*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 96, 0, x3, 324*FLEN/8, x4, x1, x2)

inst_109:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x25a and fs2 == 0 and fe2 == 0x0e and fm2 == 0x30a and fs3 == 0 and fe3 == 0x1e and fm3 == 0x196 and fcsr == 0x80 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7a5a; op2val:0x3b0a;
op3val:0x7996; valaddr_reg:x3; val_offset:327*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:128 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 128, 0, x3, 327*FLEN/8, x4, x1, x2)

inst_110:
// fs1 == 0 and fe1 == 0x1c and fm1 == 0x3ce and fs2 == 0 and fe2 == 0x10 and fm2 == 0x0b4 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x097 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x73ce; op2val:0x40b4;
op3val:0x7897; valaddr_reg:x3; val_offset:330*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 330*FLEN/8, x4, x1, x2)

inst_111:
// fs1 == 0 and fe1 == 0x1c and fm1 == 0x3ce and fs2 == 0 and fe2 == 0x10 and fm2 == 0x0b4 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x097 and fcsr == 0x20 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x73ce; op2val:0x40b4;
op3val:0x7897; valaddr_reg:x3; val_offset:333*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:32 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 32, 0, x3, 333*FLEN/8, x4, x1, x2)

inst_112:
// fs1 == 0 and fe1 == 0x1c and fm1 == 0x3ce and fs2 == 0 and fe2 == 0x10 and fm2 == 0x0b4 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x097 and fcsr == 0x40 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x73ce; op2val:0x40b4;
op3val:0x7897; valaddr_reg:x3; val_offset:336*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:64 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 64, 0, x3, 336*FLEN/8, x4, x1, x2)

inst_113:
// fs1 == 0 and fe1 == 0x1c and fm1 == 0x3ce and fs2 == 0 and fe2 == 0x10 and fm2 == 0x0b4 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x097 and fcsr == 0x60 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x73ce; op2val:0x40b4;
op3val:0x7897; valaddr_reg:x3; val_offset:339*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 96, 0, x3, 339*FLEN/8, x4, x1, x2)

inst_114:
// fs1 == 0 and fe1 == 0x1c and fm1 == 0x3ce and fs2 == 0 and fe2 == 0x10 and fm2 == 0x0b4 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x097 and fcsr == 0x80 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x73ce; op2val:0x40b4;
op3val:0x7897; valaddr_reg:x3; val_offset:342*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:128 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 128, 0, x3, 342*FLEN/8, x4, x1, x2)

inst_115:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x033 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x2aa and fs3 == 0 and fe3 == 0x1e and fm3 == 0x2ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7833; op2val:0x3eaa;
op3val:0x7aff; valaddr_reg:x3; val_offset:345*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 345*FLEN/8, x4, x1, x2)

inst_116:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x033 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x2aa and fs3 == 0 and fe3 == 0x1e and fm3 == 0x2ff and fcsr == 0x20 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7833; op2val:0x3eaa;
op3val:0x7aff; valaddr_reg:x3; val_offset:348*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:32 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 32, 0, x3, 348*FLEN/8, x4, x1, x2)

inst_117:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x033 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x2aa and fs3 == 0 and fe3 == 0x1e and fm3 == 0x2ff and fcsr == 0x40 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7833; op2val:0x3eaa;
op3val:0x7aff; valaddr_reg:x3; val_offset:351*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:64 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 64, 0, x3, 351*FLEN/8, x4, x1, x2)

inst_118:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x033 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x2aa and fs3 == 0 and fe3 == 0x1e and fm3 == 0x2ff and fcsr == 0x60 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7833; op2val:0x3eaa;
op3val:0x7aff; valaddr_reg:x3; val_offset:354*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 96, 0, x3, 354*FLEN/8, x4, x1, x2)

inst_119:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x033 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x2aa and fs3 == 0 and fe3 == 0x1e and fm3 == 0x2ff and fcsr == 0x80 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7833; op2val:0x3eaa;
op3val:0x7aff; valaddr_reg:x3; val_offset:357*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:128 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 128, 0, x3, 357*FLEN/8, x4, x1, x2)

inst_120:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1d5 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x250 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x09a and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x79d5; op2val:0x3650;
op3val:0x749a; valaddr_reg:x3; val_offset:360*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 360*FLEN/8, x4, x1, x2)

inst_121:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1d5 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x250 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x09a and fcsr == 0x20 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x79d5; op2val:0x3650;
op3val:0x749a; valaddr_reg:x3; val_offset:363*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:32 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 32, 0, x3, 363*FLEN/8, x4, x1, x2)

inst_122:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1d5 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x250 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x09a and fcsr == 0x40 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x79d5; op2val:0x3650;
op3val:0x749a; valaddr_reg:x3; val_offset:366*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:64 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 64, 0, x3, 366*FLEN/8, x4, x1, x2)

inst_123:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1d5 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x250 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x09a and fcsr == 0x60 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x79d5; op2val:0x3650;
op3val:0x749a; valaddr_reg:x3; val_offset:369*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 96, 0, x3, 369*FLEN/8, x4, x1, x2)

inst_124:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1d5 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x250 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x09a and fcsr == 0x80 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x79d5; op2val:0x3650;
op3val:0x749a; valaddr_reg:x3; val_offset:372*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:128 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 128, 0, x3, 372*FLEN/8, x4, x1, x2)

inst_125:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3d6 and fs2 == 0 and fe2 == 0x0b and fm2 == 0x3b5 and fs3 == 0 and fe3 == 0x1b and fm3 == 0x38d and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7bd6; op2val:0x2fb5;
op3val:0x6f8d; valaddr_reg:x3; val_offset:375*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 375*FLEN/8, x4, x1, x2)

inst_126:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3d6 and fs2 == 0 and fe2 == 0x0b and fm2 == 0x3b5 and fs3 == 0 and fe3 == 0x1b and fm3 == 0x38d and fcsr == 0x20 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7bd6; op2val:0x2fb5;
op3val:0x6f8d; valaddr_reg:x3; val_offset:378*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:32 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 32, 0, x3, 378*FLEN/8, x4, x1, x2)

inst_127:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3d6 and fs2 == 0 and fe2 == 0x0b and fm2 == 0x3b5 and fs3 == 0 and fe3 == 0x1b and fm3 == 0x38d and fcsr == 0x40 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7bd6; op2val:0x2fb5;
op3val:0x6f8d; valaddr_reg:x3; val_offset:381*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:64 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 64, 0, x3, 381*FLEN/8, x4, x1, x2)
RVTEST_SIGBASE(x1,signature_x1_2)

inst_128:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3d6 and fs2 == 0 and fe2 == 0x0b and fm2 == 0x3b5 and fs3 == 0 and fe3 == 0x1b and fm3 == 0x38d and fcsr == 0x60 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7bd6; op2val:0x2fb5;
op3val:0x6f8d; valaddr_reg:x3; val_offset:384*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 96, 0, x3, 384*FLEN/8, x4, x1, x2)

inst_129:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3d6 and fs2 == 0 and fe2 == 0x0b and fm2 == 0x3b5 and fs3 == 0 and fe3 == 0x1b and fm3 == 0x38d and fcsr == 0x80 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7bd6; op2val:0x2fb5;
op3val:0x6f8d; valaddr_reg:x3; val_offset:387*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:128 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 128, 0, x3, 387*FLEN/8, x4, x1, x2)

inst_130:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x2af and fs2 == 0 and fe2 == 0x0f and fm2 == 0x33e and fs3 == 0 and fe3 == 0x1e and fm3 == 0x20d and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x76af; op2val:0x3f3e;
op3val:0x7a0d; valaddr_reg:x3; val_offset:390*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 390*FLEN/8, x4, x1, x2)

inst_131:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x2af and fs2 == 0 and fe2 == 0x0f and fm2 == 0x33e and fs3 == 0 and fe3 == 0x1e and fm3 == 0x20d and fcsr == 0x20 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x76af; op2val:0x3f3e;
op3val:0x7a0d; valaddr_reg:x3; val_offset:393*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:32 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 32, 0, x3, 393*FLEN/8, x4, x1, x2)

inst_132:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x2af and fs2 == 0 and fe2 == 0x0f and fm2 == 0x33e and fs3 == 0 and fe3 == 0x1e and fm3 == 0x20d and fcsr == 0x40 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x76af; op2val:0x3f3e;
op3val:0x7a0d; valaddr_reg:x3; val_offset:396*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:64 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 64, 0, x3, 396*FLEN/8, x4, x1, x2)

inst_133:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x2af and fs2 == 0 and fe2 == 0x0f and fm2 == 0x33e and fs3 == 0 and fe3 == 0x1e and fm3 == 0x20d and fcsr == 0x60 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x76af; op2val:0x3f3e;
op3val:0x7a0d; valaddr_reg:x3; val_offset:399*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 96, 0, x3, 399*FLEN/8, x4, x1, x2)

inst_134:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x2af and fs2 == 0 and fe2 == 0x0f and fm2 == 0x33e and fs3 == 0 and fe3 == 0x1e and fm3 == 0x20d and fcsr == 0x80 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x76af; op2val:0x3f3e;
op3val:0x7a0d; valaddr_reg:x3; val_offset:402*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:128 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 128, 0, x3, 402*FLEN/8, x4, x1, x2)

inst_135:
// fs1 == 0 and fe1 == 0x1c and fm1 == 0x0dc and fs2 == 0 and fe2 == 0x10 and fm2 == 0x26f and fs3 == 0 and fe3 == 0x1d and fm3 == 0x3d1 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x70dc; op2val:0x426f;
op3val:0x77d1; valaddr_reg:x3; val_offset:405*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 405*FLEN/8, x4, x1, x2)

inst_136:
// fs1 == 0 and fe1 == 0x1c and fm1 == 0x0dc and fs2 == 0 and fe2 == 0x10 and fm2 == 0x26f and fs3 == 0 and fe3 == 0x1d and fm3 == 0x3d1 and fcsr == 0x20 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x70dc; op2val:0x426f;
op3val:0x77d1; valaddr_reg:x3; val_offset:408*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:32 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 32, 0, x3, 408*FLEN/8, x4, x1, x2)

inst_137:
// fs1 == 0 and fe1 == 0x1c and fm1 == 0x0dc and fs2 == 0 and fe2 == 0x10 and fm2 == 0x26f and fs3 == 0 and fe3 == 0x1d and fm3 == 0x3d1 and fcsr == 0x40 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x70dc; op2val:0x426f;
op3val:0x77d1; valaddr_reg:x3; val_offset:411*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:64 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 64, 0, x3, 411*FLEN/8, x4, x1, x2)

inst_138:
// fs1 == 0 and fe1 == 0x1c and fm1 == 0x0dc and fs2 == 0 and fe2 == 0x10 and fm2 == 0x26f and fs3 == 0 and fe3 == 0x1d and fm3 == 0x3d1 and fcsr == 0x60 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x70dc; op2val:0x426f;
op3val:0x77d1; valaddr_reg:x3; val_offset:414*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 96, 0, x3, 414*FLEN/8, x4, x1, x2)

inst_139:
// fs1 == 0 and fe1 == 0x1c and fm1 == 0x0dc and fs2 == 0 and fe2 == 0x10 and fm2 == 0x26f and fs3 == 0 and fe3 == 0x1d and fm3 == 0x3d1 and fcsr == 0x80 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x70dc; op2val:0x426f;
op3val:0x77d1; valaddr_reg:x3; val_offset:417*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:128 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 128, 0, x3, 417*FLEN/8, x4, x1, x2)

inst_140:
// fs1 == 0 and fe1 == 0x1a and fm1 == 0x104 and fs2 == 0 and fe2 == 0x13 and fm2 == 0x042 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x157 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x6904; op2val:0x4c42;
op3val:0x7957; valaddr_reg:x3; val_offset:420*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 420*FLEN/8, x4, x1, x2)

inst_141:
// fs1 == 0 and fe1 == 0x1a and fm1 == 0x104 and fs2 == 0 and fe2 == 0x13 and fm2 == 0x042 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x157 and fcsr == 0x20 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x6904; op2val:0x4c42;
op3val:0x7957; valaddr_reg:x3; val_offset:423*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:32 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 32, 0, x3, 423*FLEN/8, x4, x1, x2)

inst_142:
// fs1 == 0 and fe1 == 0x1a and fm1 == 0x104 and fs2 == 0 and fe2 == 0x13 and fm2 == 0x042 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x157 and fcsr == 0x40 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x6904; op2val:0x4c42;
op3val:0x7957; valaddr_reg:x3; val_offset:426*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:64 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 64, 0, x3, 426*FLEN/8, x4, x1, x2)

inst_143:
// fs1 == 0 and fe1 == 0x1a and fm1 == 0x104 and fs2 == 0 and fe2 == 0x13 and fm2 == 0x042 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x157 and fcsr == 0x60 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x6904; op2val:0x4c42;
op3val:0x7957; valaddr_reg:x3; val_offset:429*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 96, 0, x3, 429*FLEN/8, x4, x1, x2)

inst_144:
// fs1 == 0 and fe1 == 0x1a and fm1 == 0x104 and fs2 == 0 and fe2 == 0x13 and fm2 == 0x042 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x157 and fcsr == 0x80 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x6904; op2val:0x4c42;
op3val:0x7957; valaddr_reg:x3; val_offset:432*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:128 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 128, 0, x3, 432*FLEN/8, x4, x1, x2)

inst_145:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x21d and fs2 == 0 and fe2 == 0x0e and fm2 == 0x1fe and fs3 == 0 and fe3 == 0x1e and fm3 == 0x094 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7a1d; op2val:0x39fe;
op3val:0x7894; valaddr_reg:x3; val_offset:435*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 435*FLEN/8, x4, x1, x2)

inst_146:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x21d and fs2 == 0 and fe2 == 0x0e and fm2 == 0x1fe and fs3 == 0 and fe3 == 0x1e and fm3 == 0x094 and fcsr == 0x20 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7a1d; op2val:0x39fe;
op3val:0x7894; valaddr_reg:x3; val_offset:438*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:32 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 32, 0, x3, 438*FLEN/8, x4, x1, x2)

inst_147:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x21d and fs2 == 0 and fe2 == 0x0e and fm2 == 0x1fe and fs3 == 0 and fe3 == 0x1e and fm3 == 0x094 and fcsr == 0x40 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7a1d; op2val:0x39fe;
op3val:0x7894; valaddr_reg:x3; val_offset:441*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:64 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 64, 0, x3, 441*FLEN/8, x4, x1, x2)

inst_148:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x21d and fs2 == 0 and fe2 == 0x0e and fm2 == 0x1fe and fs3 == 0 and fe3 == 0x1e and fm3 == 0x094 and fcsr == 0x60 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7a1d; op2val:0x39fe;
op3val:0x7894; valaddr_reg:x3; val_offset:444*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 96, 0, x3, 444*FLEN/8, x4, x1, x2)

inst_149:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x21d and fs2 == 0 and fe2 == 0x0e and fm2 == 0x1fe and fs3 == 0 and fe3 == 0x1e and fm3 == 0x094 and fcsr == 0x80 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7a1d; op2val:0x39fe;
op3val:0x7894; valaddr_reg:x3; val_offset:447*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:128 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 128, 0, x3, 447*FLEN/8, x4, x1, x2)

inst_150:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x300 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x1bb and fs3 == 0 and fe3 == 0x1d and fm3 == 0x104 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7b00; op2val:0x35bb;
op3val:0x7504; valaddr_reg:x3; val_offset:450*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 450*FLEN/8, x4, x1, x2)

inst_151:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x300 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x1bb and fs3 == 0 and fe3 == 0x1d and fm3 == 0x104 and fcsr == 0x20 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7b00; op2val:0x35bb;
op3val:0x7504; valaddr_reg:x3; val_offset:453*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:32 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 32, 0, x3, 453*FLEN/8, x4, x1, x2)

inst_152:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x300 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x1bb and fs3 == 0 and fe3 == 0x1d and fm3 == 0x104 and fcsr == 0x40 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7b00; op2val:0x35bb;
op3val:0x7504; valaddr_reg:x3; val_offset:456*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:64 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 64, 0, x3, 456*FLEN/8, x4, x1, x2)

inst_153:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x300 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x1bb and fs3 == 0 and fe3 == 0x1d and fm3 == 0x104 and fcsr == 0x60 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7b00; op2val:0x35bb;
op3val:0x7504; valaddr_reg:x3; val_offset:459*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 96, 0, x3, 459*FLEN/8, x4, x1, x2)

inst_154:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x300 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x1bb and fs3 == 0 and fe3 == 0x1d and fm3 == 0x104 and fcsr == 0x80 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7b00; op2val:0x35bb;
op3val:0x7504; valaddr_reg:x3; val_offset:462*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:128 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 128, 0, x3, 462*FLEN/8, x4, x1, x2)

inst_155:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x18f and fs2 == 0 and fe2 == 0x0e and fm2 == 0x2d6 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x0c0 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x798f; op2val:0x3ad6;
op3val:0x78c0; valaddr_reg:x3; val_offset:465*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 465*FLEN/8, x4, x1, x2)

inst_156:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x18f and fs2 == 0 and fe2 == 0x0e and fm2 == 0x2d6 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x0c0 and fcsr == 0x20 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x798f; op2val:0x3ad6;
op3val:0x78c0; valaddr_reg:x3; val_offset:468*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:32 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 32, 0, x3, 468*FLEN/8, x4, x1, x2)

inst_157:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x18f and fs2 == 0 and fe2 == 0x0e and fm2 == 0x2d6 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x0c0 and fcsr == 0x40 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x798f; op2val:0x3ad6;
op3val:0x78c0; valaddr_reg:x3; val_offset:471*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:64 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 64, 0, x3, 471*FLEN/8, x4, x1, x2)

inst_158:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x18f and fs2 == 0 and fe2 == 0x0e and fm2 == 0x2d6 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x0c0 and fcsr == 0x60 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x798f; op2val:0x3ad6;
op3val:0x78c0; valaddr_reg:x3; val_offset:474*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 96, 0, x3, 474*FLEN/8, x4, x1, x2)

inst_159:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x18f and fs2 == 0 and fe2 == 0x0e and fm2 == 0x2d6 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x0c0 and fcsr == 0x80 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x798f; op2val:0x3ad6;
op3val:0x78c0; valaddr_reg:x3; val_offset:477*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:128 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 128, 0, x3, 477*FLEN/8, x4, x1, x2)

inst_160:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0a3 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x24b and fs3 == 0 and fe3 == 0x1d and fm3 == 0x34b and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x78a3; op2val:0x3a4b;
op3val:0x774b; valaddr_reg:x3; val_offset:480*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 480*FLEN/8, x4, x1, x2)

inst_161:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0a3 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x24b and fs3 == 0 and fe3 == 0x1d and fm3 == 0x34b and fcsr == 0x20 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x78a3; op2val:0x3a4b;
op3val:0x774b; valaddr_reg:x3; val_offset:483*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:32 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 32, 0, x3, 483*FLEN/8, x4, x1, x2)

inst_162:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0a3 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x24b and fs3 == 0 and fe3 == 0x1d and fm3 == 0x34b and fcsr == 0x40 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x78a3; op2val:0x3a4b;
op3val:0x774b; valaddr_reg:x3; val_offset:486*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:64 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 64, 0, x3, 486*FLEN/8, x4, x1, x2)

inst_163:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0a3 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x24b and fs3 == 0 and fe3 == 0x1d and fm3 == 0x34b and fcsr == 0x60 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x78a3; op2val:0x3a4b;
op3val:0x774b; valaddr_reg:x3; val_offset:489*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 96, 0, x3, 489*FLEN/8, x4, x1, x2)

inst_164:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0a3 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x24b and fs3 == 0 and fe3 == 0x1d and fm3 == 0x34b and fcsr == 0x80 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x78a3; op2val:0x3a4b;
op3val:0x774b; valaddr_reg:x3; val_offset:492*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:128 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 128, 0, x3, 492*FLEN/8, x4, x1, x2)

inst_165:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2b7 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x07f and fs3 == 0 and fe3 == 0x1e and fm3 == 0x38d and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7ab7; op2val:0x3c7f;
op3val:0x7b8d; valaddr_reg:x3; val_offset:495*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 495*FLEN/8, x4, x1, x2)

inst_166:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2b7 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x07f and fs3 == 0 and fe3 == 0x1e and fm3 == 0x38d and fcsr == 0x20 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7ab7; op2val:0x3c7f;
op3val:0x7b8d; valaddr_reg:x3; val_offset:498*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:32 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 32, 0, x3, 498*FLEN/8, x4, x1, x2)

inst_167:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2b7 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x07f and fs3 == 0 and fe3 == 0x1e and fm3 == 0x38d and fcsr == 0x40 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7ab7; op2val:0x3c7f;
op3val:0x7b8d; valaddr_reg:x3; val_offset:501*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:64 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 64, 0, x3, 501*FLEN/8, x4, x1, x2)

inst_168:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2b7 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x07f and fs3 == 0 and fe3 == 0x1e and fm3 == 0x38d and fcsr == 0x60 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7ab7; op2val:0x3c7f;
op3val:0x7b8d; valaddr_reg:x3; val_offset:504*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 96, 0, x3, 504*FLEN/8, x4, x1, x2)

inst_169:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2b7 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x07f and fs3 == 0 and fe3 == 0x1e and fm3 == 0x38d and fcsr == 0x80 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7ab7; op2val:0x3c7f;
op3val:0x7b8d; valaddr_reg:x3; val_offset:507*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:128 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 128, 0, x3, 507*FLEN/8, x4, x1, x2)

inst_170:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x394 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x19a and fs3 == 0 and fe3 == 0x1e and fm3 == 0x14f and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7794; op2val:0x3d9a;
op3val:0x794f; valaddr_reg:x3; val_offset:510*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 510*FLEN/8, x4, x1, x2)

inst_171:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x394 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x19a and fs3 == 0 and fe3 == 0x1e and fm3 == 0x14f and fcsr == 0x20 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7794; op2val:0x3d9a;
op3val:0x794f; valaddr_reg:x3; val_offset:513*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:32 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 32, 0, x3, 513*FLEN/8, x4, x1, x2)

inst_172:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x394 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x19a and fs3 == 0 and fe3 == 0x1e and fm3 == 0x14f and fcsr == 0x40 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7794; op2val:0x3d9a;
op3val:0x794f; valaddr_reg:x3; val_offset:516*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:64 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 64, 0, x3, 516*FLEN/8, x4, x1, x2)

inst_173:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x394 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x19a and fs3 == 0 and fe3 == 0x1e and fm3 == 0x14f and fcsr == 0x60 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7794; op2val:0x3d9a;
op3val:0x794f; valaddr_reg:x3; val_offset:519*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 96, 0, x3, 519*FLEN/8, x4, x1, x2)

inst_174:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x394 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x19a and fs3 == 0 and fe3 == 0x1e and fm3 == 0x14f and fcsr == 0x80 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7794; op2val:0x3d9a;
op3val:0x794f; valaddr_reg:x3; val_offset:522*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:128 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 128, 0, x3, 522*FLEN/8, x4, x1, x2)

inst_175:
// fs1 == 0 and fe1 == 0x1a and fm1 == 0x3c3 and fs2 == 0 and fe2 == 0x12 and fm2 == 0x1c7 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x19b and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x6bc3; op2val:0x49c7;
op3val:0x799b; valaddr_reg:x3; val_offset:525*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 525*FLEN/8, x4, x1, x2)

inst_176:
// fs1 == 0 and fe1 == 0x1a and fm1 == 0x3c3 and fs2 == 0 and fe2 == 0x12 and fm2 == 0x1c7 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x19b and fcsr == 0x20 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x6bc3; op2val:0x49c7;
op3val:0x799b; valaddr_reg:x3; val_offset:528*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:32 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 32, 0, x3, 528*FLEN/8, x4, x1, x2)

inst_177:
// fs1 == 0 and fe1 == 0x1a and fm1 == 0x3c3 and fs2 == 0 and fe2 == 0x12 and fm2 == 0x1c7 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x19b and fcsr == 0x40 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x6bc3; op2val:0x49c7;
op3val:0x799b; valaddr_reg:x3; val_offset:531*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:64 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 64, 0, x3, 531*FLEN/8, x4, x1, x2)

inst_178:
// fs1 == 0 and fe1 == 0x1a and fm1 == 0x3c3 and fs2 == 0 and fe2 == 0x12 and fm2 == 0x1c7 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x19b and fcsr == 0x60 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x6bc3; op2val:0x49c7;
op3val:0x799b; valaddr_reg:x3; val_offset:534*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 96, 0, x3, 534*FLEN/8, x4, x1, x2)

inst_179:
// fs1 == 0 and fe1 == 0x1a and fm1 == 0x3c3 and fs2 == 0 and fe2 == 0x12 and fm2 == 0x1c7 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x19b and fcsr == 0x80 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x6bc3; op2val:0x49c7;
op3val:0x799b; valaddr_reg:x3; val_offset:537*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:128 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 128, 0, x3, 537*FLEN/8, x4, x1, x2)

inst_180:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x12c and fs2 == 0 and fe2 == 0x0f and fm2 == 0x223 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3f0 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x792c; op2val:0x3e23;
op3val:0x7bf0; valaddr_reg:x3; val_offset:540*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 540*FLEN/8, x4, x1, x2)

inst_181:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x12c and fs2 == 0 and fe2 == 0x0f and fm2 == 0x223 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3f0 and fcsr == 0x20 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x792c; op2val:0x3e23;
op3val:0x7bf0; valaddr_reg:x3; val_offset:543*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:32 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 32, 0, x3, 543*FLEN/8, x4, x1, x2)

inst_182:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x12c and fs2 == 0 and fe2 == 0x0f and fm2 == 0x223 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3f0 and fcsr == 0x40 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x792c; op2val:0x3e23;
op3val:0x7bf0; valaddr_reg:x3; val_offset:546*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:64 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 64, 0, x3, 546*FLEN/8, x4, x1, x2)

inst_183:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x12c and fs2 == 0 and fe2 == 0x0f and fm2 == 0x223 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3f0 and fcsr == 0x60 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x792c; op2val:0x3e23;
op3val:0x7bf0; valaddr_reg:x3; val_offset:549*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 96, 0, x3, 549*FLEN/8, x4, x1, x2)

inst_184:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x12c and fs2 == 0 and fe2 == 0x0f and fm2 == 0x223 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3f0 and fcsr == 0x80 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x792c; op2val:0x3e23;
op3val:0x7bf0; valaddr_reg:x3; val_offset:552*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:128 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 128, 0, x3, 552*FLEN/8, x4, x1, x2)

inst_185:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x292 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x18a and fs3 == 0 and fe3 == 0x1d and fm3 == 0x08d and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7a92; op2val:0x358a;
op3val:0x748d; valaddr_reg:x3; val_offset:555*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 555*FLEN/8, x4, x1, x2)

inst_186:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x292 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x18a and fs3 == 0 and fe3 == 0x1d and fm3 == 0x08d and fcsr == 0x20 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7a92; op2val:0x358a;
op3val:0x748d; valaddr_reg:x3; val_offset:558*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:32 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 32, 0, x3, 558*FLEN/8, x4, x1, x2)

inst_187:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x292 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x18a and fs3 == 0 and fe3 == 0x1d and fm3 == 0x08d and fcsr == 0x40 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7a92; op2val:0x358a;
op3val:0x748d; valaddr_reg:x3; val_offset:561*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:64 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 64, 0, x3, 561*FLEN/8, x4, x1, x2)

inst_188:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x292 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x18a and fs3 == 0 and fe3 == 0x1d and fm3 == 0x08d and fcsr == 0x60 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7a92; op2val:0x358a;
op3val:0x748d; valaddr_reg:x3; val_offset:564*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 96, 0, x3, 564*FLEN/8, x4, x1, x2)

inst_189:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x292 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x18a and fs3 == 0 and fe3 == 0x1d and fm3 == 0x08d and fcsr == 0x80 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7a92; op2val:0x358a;
op3val:0x748d; valaddr_reg:x3; val_offset:567*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:128 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 128, 0, x3, 567*FLEN/8, x4, x1, x2)

inst_190:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x22b and fs2 == 0 and fe2 == 0x0f and fm2 == 0x2ee and fs3 == 0 and fe3 == 0x1e and fm3 == 0x158 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x762b; op2val:0x3eee;
op3val:0x7958; valaddr_reg:x3; val_offset:570*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 570*FLEN/8, x4, x1, x2)

inst_191:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x22b and fs2 == 0 and fe2 == 0x0f and fm2 == 0x2ee and fs3 == 0 and fe3 == 0x1e and fm3 == 0x158 and fcsr == 0x20 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x762b; op2val:0x3eee;
op3val:0x7958; valaddr_reg:x3; val_offset:573*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:32 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 32, 0, x3, 573*FLEN/8, x4, x1, x2)

inst_192:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x22b and fs2 == 0 and fe2 == 0x0f and fm2 == 0x2ee and fs3 == 0 and fe3 == 0x1e and fm3 == 0x158 and fcsr == 0x40 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x762b; op2val:0x3eee;
op3val:0x7958; valaddr_reg:x3; val_offset:576*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:64 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 64, 0, x3, 576*FLEN/8, x4, x1, x2)

inst_193:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x22b and fs2 == 0 and fe2 == 0x0f and fm2 == 0x2ee and fs3 == 0 and fe3 == 0x1e and fm3 == 0x158 and fcsr == 0x60 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x762b; op2val:0x3eee;
op3val:0x7958; valaddr_reg:x3; val_offset:579*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 96, 0, x3, 579*FLEN/8, x4, x1, x2)

inst_194:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x22b and fs2 == 0 and fe2 == 0x0f and fm2 == 0x2ee and fs3 == 0 and fe3 == 0x1e and fm3 == 0x158 and fcsr == 0x80 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x762b; op2val:0x3eee;
op3val:0x7958; valaddr_reg:x3; val_offset:582*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:128 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 128, 0, x3, 582*FLEN/8, x4, x1, x2)

inst_195:
// fs1 == 0 and fe1 == 0x19 and fm1 == 0x1c6 and fs2 == 0 and fe2 == 0x13 and fm2 == 0x11c and fs3 == 0 and fe3 == 0x1d and fm3 == 0x362 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x65c6; op2val:0x4d1c;
op3val:0x7762; valaddr_reg:x3; val_offset:585*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 585*FLEN/8, x4, x1, x2)

inst_196:
// fs1 == 0 and fe1 == 0x19 and fm1 == 0x1c6 and fs2 == 0 and fe2 == 0x13 and fm2 == 0x11c and fs3 == 0 and fe3 == 0x1d and fm3 == 0x362 and fcsr == 0x20 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x65c6; op2val:0x4d1c;
op3val:0x7762; valaddr_reg:x3; val_offset:588*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:32 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 32, 0, x3, 588*FLEN/8, x4, x1, x2)

inst_197:
// fs1 == 0 and fe1 == 0x19 and fm1 == 0x1c6 and fs2 == 0 and fe2 == 0x13 and fm2 == 0x11c and fs3 == 0 and fe3 == 0x1d and fm3 == 0x362 and fcsr == 0x40 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x65c6; op2val:0x4d1c;
op3val:0x7762; valaddr_reg:x3; val_offset:591*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:64 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 64, 0, x3, 591*FLEN/8, x4, x1, x2)

inst_198:
// fs1 == 0 and fe1 == 0x19 and fm1 == 0x1c6 and fs2 == 0 and fe2 == 0x13 and fm2 == 0x11c and fs3 == 0 and fe3 == 0x1d and fm3 == 0x362 and fcsr == 0x60 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x65c6; op2val:0x4d1c;
op3val:0x7762; valaddr_reg:x3; val_offset:594*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 96, 0, x3, 594*FLEN/8, x4, x1, x2)

inst_199:
// fs1 == 0 and fe1 == 0x19 and fm1 == 0x1c6 and fs2 == 0 and fe2 == 0x13 and fm2 == 0x11c and fs3 == 0 and fe3 == 0x1d and fm3 == 0x362 and fcsr == 0x80 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x65c6; op2val:0x4d1c;
op3val:0x7762; valaddr_reg:x3; val_offset:597*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:128 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 128, 0, x3, 597*FLEN/8, x4, x1, x2)

inst_200:
// fs1 == 0 and fe1 == 0x1c and fm1 == 0x160 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x193 and fs3 == 0 and fe3 == 0x1b and fm3 == 0x37d and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7160; op2val:0x3993;
op3val:0x6f7d; valaddr_reg:x3; val_offset:600*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 600*FLEN/8, x4, x1, x2)

inst_201:
// fs1 == 0 and fe1 == 0x1c and fm1 == 0x160 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x193 and fs3 == 0 and fe3 == 0x1b and fm3 == 0x37d and fcsr == 0x20 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7160; op2val:0x3993;
op3val:0x6f7d; valaddr_reg:x3; val_offset:603*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:32 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 32, 0, x3, 603*FLEN/8, x4, x1, x2)

inst_202:
// fs1 == 0 and fe1 == 0x1c and fm1 == 0x160 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x193 and fs3 == 0 and fe3 == 0x1b and fm3 == 0x37d and fcsr == 0x40 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7160; op2val:0x3993;
op3val:0x6f7d; valaddr_reg:x3; val_offset:606*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:64 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 64, 0, x3, 606*FLEN/8, x4, x1, x2)

inst_203:
// fs1 == 0 and fe1 == 0x1c and fm1 == 0x160 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x193 and fs3 == 0 and fe3 == 0x1b and fm3 == 0x37d and fcsr == 0x60 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7160; op2val:0x3993;
op3val:0x6f7d; valaddr_reg:x3; val_offset:609*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 96, 0, x3, 609*FLEN/8, x4, x1, x2)

inst_204:
// fs1 == 0 and fe1 == 0x1c and fm1 == 0x160 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x193 and fs3 == 0 and fe3 == 0x1b and fm3 == 0x37d and fcsr == 0x80 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7160; op2val:0x3993;
op3val:0x6f7d; valaddr_reg:x3; val_offset:612*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:128 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 128, 0, x3, 612*FLEN/8, x4, x1, x2)

inst_205:
// fs1 == 0 and fe1 == 0x1a and fm1 == 0x38b and fs2 == 0 and fe2 == 0x12 and fm2 == 0x283 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x224 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x6b8b; op2val:0x4a83;
op3val:0x7a24; valaddr_reg:x3; val_offset:615*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 615*FLEN/8, x4, x1, x2)

inst_206:
// fs1 == 0 and fe1 == 0x1a and fm1 == 0x38b and fs2 == 0 and fe2 == 0x12 and fm2 == 0x283 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x224 and fcsr == 0x20 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x6b8b; op2val:0x4a83;
op3val:0x7a24; valaddr_reg:x3; val_offset:618*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:32 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 32, 0, x3, 618*FLEN/8, x4, x1, x2)

inst_207:
// fs1 == 0 and fe1 == 0x1a and fm1 == 0x38b and fs2 == 0 and fe2 == 0x12 and fm2 == 0x283 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x224 and fcsr == 0x40 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x6b8b; op2val:0x4a83;
op3val:0x7a24; valaddr_reg:x3; val_offset:621*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:64 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 64, 0, x3, 621*FLEN/8, x4, x1, x2)

inst_208:
// fs1 == 0 and fe1 == 0x1a and fm1 == 0x38b and fs2 == 0 and fe2 == 0x12 and fm2 == 0x283 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x224 and fcsr == 0x60 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x6b8b; op2val:0x4a83;
op3val:0x7a24; valaddr_reg:x3; val_offset:624*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 96, 0, x3, 624*FLEN/8, x4, x1, x2)

inst_209:
// fs1 == 0 and fe1 == 0x1a and fm1 == 0x38b and fs2 == 0 and fe2 == 0x12 and fm2 == 0x283 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x224 and fcsr == 0x80 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x6b8b; op2val:0x4a83;
op3val:0x7a24; valaddr_reg:x3; val_offset:627*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:128 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 128, 0, x3, 627*FLEN/8, x4, x1, x2)

inst_210:
// fs1 == 0 and fe1 == 0x1c and fm1 == 0x023 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x3a8 and fs3 == 0 and fe3 == 0x1c and fm3 == 0x3eb and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7023; op2val:0x3fa8;
op3val:0x73eb; valaddr_reg:x3; val_offset:630*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 630*FLEN/8, x4, x1, x2)

inst_211:
// fs1 == 0 and fe1 == 0x1c and fm1 == 0x023 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x3a8 and fs3 == 0 and fe3 == 0x1c and fm3 == 0x3eb and fcsr == 0x20 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7023; op2val:0x3fa8;
op3val:0x73eb; valaddr_reg:x3; val_offset:633*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:32 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 32, 0, x3, 633*FLEN/8, x4, x1, x2)

inst_212:
// fs1 == 0 and fe1 == 0x1c and fm1 == 0x023 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x3a8 and fs3 == 0 and fe3 == 0x1c and fm3 == 0x3eb and fcsr == 0x40 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7023; op2val:0x3fa8;
op3val:0x73eb; valaddr_reg:x3; val_offset:636*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:64 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 64, 0, x3, 636*FLEN/8, x4, x1, x2)

inst_213:
// fs1 == 0 and fe1 == 0x1c and fm1 == 0x023 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x3a8 and fs3 == 0 and fe3 == 0x1c and fm3 == 0x3eb and fcsr == 0x60 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7023; op2val:0x3fa8;
op3val:0x73eb; valaddr_reg:x3; val_offset:639*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 96, 0, x3, 639*FLEN/8, x4, x1, x2)

inst_214:
// fs1 == 0 and fe1 == 0x1c and fm1 == 0x023 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x3a8 and fs3 == 0 and fe3 == 0x1c and fm3 == 0x3eb and fcsr == 0x80 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7023; op2val:0x3fa8;
op3val:0x73eb; valaddr_reg:x3; val_offset:642*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:128 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 128, 0, x3, 642*FLEN/8, x4, x1, x2)

inst_215:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x240 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x075 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x2f7 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7640; op2val:0x4075;
op3val:0x7af7; valaddr_reg:x3; val_offset:645*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 645*FLEN/8, x4, x1, x2)

inst_216:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x240 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x075 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x2f7 and fcsr == 0x20 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7640; op2val:0x4075;
op3val:0x7af7; valaddr_reg:x3; val_offset:648*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:32 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 32, 0, x3, 648*FLEN/8, x4, x1, x2)

inst_217:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x240 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x075 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x2f7 and fcsr == 0x40 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7640; op2val:0x4075;
op3val:0x7af7; valaddr_reg:x3; val_offset:651*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:64 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 64, 0, x3, 651*FLEN/8, x4, x1, x2)

inst_218:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x240 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x075 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x2f7 and fcsr == 0x60 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7640; op2val:0x4075;
op3val:0x7af7; valaddr_reg:x3; val_offset:654*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 96, 0, x3, 654*FLEN/8, x4, x1, x2)

inst_219:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x240 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x075 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x2f7 and fcsr == 0x80 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7640; op2val:0x4075;
op3val:0x7af7; valaddr_reg:x3; val_offset:657*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:128 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 128, 0, x3, 657*FLEN/8, x4, x1, x2)

inst_220:
// fs1 == 0 and fe1 == 0x1b and fm1 == 0x127 and fs2 == 0 and fe2 == 0x11 and fm2 == 0x192 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x32f and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x6d27; op2val:0x4592;
op3val:0x772f; valaddr_reg:x3; val_offset:660*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 660*FLEN/8, x4, x1, x2)

inst_221:
// fs1 == 0 and fe1 == 0x1b and fm1 == 0x127 and fs2 == 0 and fe2 == 0x11 and fm2 == 0x192 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x32f and fcsr == 0x20 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x6d27; op2val:0x4592;
op3val:0x772f; valaddr_reg:x3; val_offset:663*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:32 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 32, 0, x3, 663*FLEN/8, x4, x1, x2)

inst_222:
// fs1 == 0 and fe1 == 0x1b and fm1 == 0x127 and fs2 == 0 and fe2 == 0x11 and fm2 == 0x192 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x32f and fcsr == 0x40 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x6d27; op2val:0x4592;
op3val:0x772f; valaddr_reg:x3; val_offset:666*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:64 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 64, 0, x3, 666*FLEN/8, x4, x1, x2)

inst_223:
// fs1 == 0 and fe1 == 0x1b and fm1 == 0x127 and fs2 == 0 and fe2 == 0x11 and fm2 == 0x192 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x32f and fcsr == 0x60 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x6d27; op2val:0x4592;
op3val:0x772f; valaddr_reg:x3; val_offset:669*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 96, 0, x3, 669*FLEN/8, x4, x1, x2)

inst_224:
// fs1 == 0 and fe1 == 0x1b and fm1 == 0x127 and fs2 == 0 and fe2 == 0x11 and fm2 == 0x192 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x32f and fcsr == 0x80 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x6d27; op2val:0x4592;
op3val:0x772f; valaddr_reg:x3; val_offset:672*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:128 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 128, 0, x3, 672*FLEN/8, x4, x1, x2)

inst_225:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x064 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x26e and fs3 == 0 and fe3 == 0x1e and fm3 == 0x310 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7864; op2val:0x3e6e;
op3val:0x7b10; valaddr_reg:x3; val_offset:675*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 675*FLEN/8, x4, x1, x2)

inst_226:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x064 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x26e and fs3 == 0 and fe3 == 0x1e and fm3 == 0x310 and fcsr == 0x20 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7864; op2val:0x3e6e;
op3val:0x7b10; valaddr_reg:x3; val_offset:678*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:32 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 32, 0, x3, 678*FLEN/8, x4, x1, x2)

inst_227:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x064 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x26e and fs3 == 0 and fe3 == 0x1e and fm3 == 0x310 and fcsr == 0x40 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7864; op2val:0x3e6e;
op3val:0x7b10; valaddr_reg:x3; val_offset:681*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:64 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 64, 0, x3, 681*FLEN/8, x4, x1, x2)

inst_228:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x064 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x26e and fs3 == 0 and fe3 == 0x1e and fm3 == 0x310 and fcsr == 0x60 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7864; op2val:0x3e6e;
op3val:0x7b10; valaddr_reg:x3; val_offset:684*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 96, 0, x3, 684*FLEN/8, x4, x1, x2)

inst_229:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x064 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x26e and fs3 == 0 and fe3 == 0x1e and fm3 == 0x310 and fcsr == 0x80 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7864; op2val:0x3e6e;
op3val:0x7b10; valaddr_reg:x3; val_offset:687*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:128 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 128, 0, x3, 687*FLEN/8, x4, x1, x2)

inst_230:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x28d and fs2 == 0 and fe2 == 0x0f and fm2 == 0x037 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x2e8 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7a8d; op2val:0x3c37;
op3val:0x7ae8; valaddr_reg:x3; val_offset:690*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 690*FLEN/8, x4, x1, x2)

inst_231:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x28d and fs2 == 0 and fe2 == 0x0f and fm2 == 0x037 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x2e8 and fcsr == 0x20 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7a8d; op2val:0x3c37;
op3val:0x7ae8; valaddr_reg:x3; val_offset:693*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:32 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 32, 0, x3, 693*FLEN/8, x4, x1, x2)

inst_232:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x28d and fs2 == 0 and fe2 == 0x0f and fm2 == 0x037 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x2e8 and fcsr == 0x40 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7a8d; op2val:0x3c37;
op3val:0x7ae8; valaddr_reg:x3; val_offset:696*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:64 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 64, 0, x3, 696*FLEN/8, x4, x1, x2)

inst_233:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x28d and fs2 == 0 and fe2 == 0x0f and fm2 == 0x037 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x2e8 and fcsr == 0x60 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7a8d; op2val:0x3c37;
op3val:0x7ae8; valaddr_reg:x3; val_offset:699*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 96, 0, x3, 699*FLEN/8, x4, x1, x2)

inst_234:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x28d and fs2 == 0 and fe2 == 0x0f and fm2 == 0x037 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x2e8 and fcsr == 0x80 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7a8d; op2val:0x3c37;
op3val:0x7ae8; valaddr_reg:x3; val_offset:702*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:128 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 128, 0, x3, 702*FLEN/8, x4, x1, x2)

inst_235:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x073 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x1f7 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x2a4 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7473; op2val:0x3df7;
op3val:0x76a4; valaddr_reg:x3; val_offset:705*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 705*FLEN/8, x4, x1, x2)

inst_236:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x073 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x1f7 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x2a4 and fcsr == 0x20 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7473; op2val:0x3df7;
op3val:0x76a4; valaddr_reg:x3; val_offset:708*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:32 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 32, 0, x3, 708*FLEN/8, x4, x1, x2)

inst_237:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x073 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x1f7 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x2a4 and fcsr == 0x40 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7473; op2val:0x3df7;
op3val:0x76a4; valaddr_reg:x3; val_offset:711*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:64 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 64, 0, x3, 711*FLEN/8, x4, x1, x2)

inst_238:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x073 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x1f7 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x2a4 and fcsr == 0x60 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7473; op2val:0x3df7;
op3val:0x76a4; valaddr_reg:x3; val_offset:714*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 96, 0, x3, 714*FLEN/8, x4, x1, x2)

inst_239:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x073 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x1f7 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x2a4 and fcsr == 0x80 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7473; op2val:0x3df7;
op3val:0x76a4; valaddr_reg:x3; val_offset:717*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:128 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 128, 0, x3, 717*FLEN/8, x4, x1, x2)

inst_240:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x1bc and fs2 == 0 and fe2 == 0x10 and fm2 == 0x0ed and fs3 == 0 and fe3 == 0x1e and fm3 == 0x311 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x75bc; op2val:0x40ed;
op3val:0x7b11; valaddr_reg:x3; val_offset:720*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 720*FLEN/8, x4, x1, x2)

inst_241:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x1bc and fs2 == 0 and fe2 == 0x10 and fm2 == 0x0ed and fs3 == 0 and fe3 == 0x1e and fm3 == 0x311 and fcsr == 0x20 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x75bc; op2val:0x40ed;
op3val:0x7b11; valaddr_reg:x3; val_offset:723*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:32 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 32, 0, x3, 723*FLEN/8, x4, x1, x2)

inst_242:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x1bc and fs2 == 0 and fe2 == 0x10 and fm2 == 0x0ed and fs3 == 0 and fe3 == 0x1e and fm3 == 0x311 and fcsr == 0x40 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x75bc; op2val:0x40ed;
op3val:0x7b11; valaddr_reg:x3; val_offset:726*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:64 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 64, 0, x3, 726*FLEN/8, x4, x1, x2)

inst_243:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x1bc and fs2 == 0 and fe2 == 0x10 and fm2 == 0x0ed and fs3 == 0 and fe3 == 0x1e and fm3 == 0x311 and fcsr == 0x60 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x75bc; op2val:0x40ed;
op3val:0x7b11; valaddr_reg:x3; val_offset:729*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 96, 0, x3, 729*FLEN/8, x4, x1, x2)

inst_244:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x1bc and fs2 == 0 and fe2 == 0x10 and fm2 == 0x0ed and fs3 == 0 and fe3 == 0x1e and fm3 == 0x311 and fcsr == 0x80 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x75bc; op2val:0x40ed;
op3val:0x7b11; valaddr_reg:x3; val_offset:732*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:128 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 128, 0, x3, 732*FLEN/8, x4, x1, x2)

inst_245:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3a8 and fs2 == 0 and fe2 == 0x0c and fm2 == 0x10b and fs3 == 0 and fe3 == 0x1c and fm3 == 0x0d3 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7ba8; op2val:0x310b;
op3val:0x70d3; valaddr_reg:x3; val_offset:735*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 735*FLEN/8, x4, x1, x2)

inst_246:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3a8 and fs2 == 0 and fe2 == 0x0c and fm2 == 0x10b and fs3 == 0 and fe3 == 0x1c and fm3 == 0x0d3 and fcsr == 0x20 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7ba8; op2val:0x310b;
op3val:0x70d3; valaddr_reg:x3; val_offset:738*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:32 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 32, 0, x3, 738*FLEN/8, x4, x1, x2)

inst_247:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3a8 and fs2 == 0 and fe2 == 0x0c and fm2 == 0x10b and fs3 == 0 and fe3 == 0x1c and fm3 == 0x0d3 and fcsr == 0x40 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7ba8; op2val:0x310b;
op3val:0x70d3; valaddr_reg:x3; val_offset:741*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:64 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 64, 0, x3, 741*FLEN/8, x4, x1, x2)

inst_248:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3a8 and fs2 == 0 and fe2 == 0x0c and fm2 == 0x10b and fs3 == 0 and fe3 == 0x1c and fm3 == 0x0d3 and fcsr == 0x60 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7ba8; op2val:0x310b;
op3val:0x70d3; valaddr_reg:x3; val_offset:744*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 96, 0, x3, 744*FLEN/8, x4, x1, x2)

inst_249:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3a8 and fs2 == 0 and fe2 == 0x0c and fm2 == 0x10b and fs3 == 0 and fe3 == 0x1c and fm3 == 0x0d3 and fcsr == 0x80 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7ba8; op2val:0x310b;
op3val:0x70d3; valaddr_reg:x3; val_offset:747*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:128 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 128, 0, x3, 747*FLEN/8, x4, x1, x2)

inst_250:
// fs1 == 0 and fe1 == 0x1c and fm1 == 0x1a2 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x143 and fs3 == 0 and fe3 == 0x1c and fm3 == 0x36b and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x71a2; op2val:0x3d43;
op3val:0x736b; valaddr_reg:x3; val_offset:750*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 750*FLEN/8, x4, x1, x2)

inst_251:
// fs1 == 0 and fe1 == 0x1c and fm1 == 0x1a2 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x143 and fs3 == 0 and fe3 == 0x1c and fm3 == 0x36b and fcsr == 0x20 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x71a2; op2val:0x3d43;
op3val:0x736b; valaddr_reg:x3; val_offset:753*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:32 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 32, 0, x3, 753*FLEN/8, x4, x1, x2)

inst_252:
// fs1 == 0 and fe1 == 0x1c and fm1 == 0x1a2 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x143 and fs3 == 0 and fe3 == 0x1c and fm3 == 0x36b and fcsr == 0x40 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x71a2; op2val:0x3d43;
op3val:0x736b; valaddr_reg:x3; val_offset:756*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:64 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 64, 0, x3, 756*FLEN/8, x4, x1, x2)

inst_253:
// fs1 == 0 and fe1 == 0x1c and fm1 == 0x1a2 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x143 and fs3 == 0 and fe3 == 0x1c and fm3 == 0x36b and fcsr == 0x60 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x71a2; op2val:0x3d43;
op3val:0x736b; valaddr_reg:x3; val_offset:759*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 96, 0, x3, 759*FLEN/8, x4, x1, x2)

inst_254:
// fs1 == 0 and fe1 == 0x1c and fm1 == 0x1a2 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x143 and fs3 == 0 and fe3 == 0x1c and fm3 == 0x36b and fcsr == 0x80 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x71a2; op2val:0x3d43;
op3val:0x736b; valaddr_reg:x3; val_offset:762*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:128 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 128, 0, x3, 762*FLEN/8, x4, x1, x2)

inst_255:
// fs1 == 0 and fe1 == 0x1c and fm1 == 0x376 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x028 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x3c1 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7376; op2val:0x4028;
op3val:0x77c1; valaddr_reg:x3; val_offset:765*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 765*FLEN/8, x4, x1, x2)
RVTEST_SIGBASE(x1,signature_x1_3)

inst_256:
// fs1 == 0 and fe1 == 0x1c and fm1 == 0x376 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x028 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x3c1 and fcsr == 0x20 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7376; op2val:0x4028;
op3val:0x77c1; valaddr_reg:x3; val_offset:768*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:32 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 32, 0, x3, 768*FLEN/8, x4, x1, x2)

inst_257:
// fs1 == 0 and fe1 == 0x1c and fm1 == 0x376 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x028 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x3c1 and fcsr == 0x40 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7376; op2val:0x4028;
op3val:0x77c1; valaddr_reg:x3; val_offset:771*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:64 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 64, 0, x3, 771*FLEN/8, x4, x1, x2)

inst_258:
// fs1 == 0 and fe1 == 0x1c and fm1 == 0x376 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x028 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x3c1 and fcsr == 0x60 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7376; op2val:0x4028;
op3val:0x77c1; valaddr_reg:x3; val_offset:774*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 96, 0, x3, 774*FLEN/8, x4, x1, x2)

inst_259:
// fs1 == 0 and fe1 == 0x1c and fm1 == 0x376 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x028 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x3c1 and fcsr == 0x80 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7376; op2val:0x4028;
op3val:0x77c1; valaddr_reg:x3; val_offset:777*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:128 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 128, 0, x3, 777*FLEN/8, x4, x1, x2)

inst_260:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0b5 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x322 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x033 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x78b5; op2val:0x3722;
op3val:0x7433; valaddr_reg:x3; val_offset:780*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 780*FLEN/8, x4, x1, x2)

inst_261:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0b5 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x322 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x033 and fcsr == 0x20 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x78b5; op2val:0x3722;
op3val:0x7433; valaddr_reg:x3; val_offset:783*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:32 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 32, 0, x3, 783*FLEN/8, x4, x1, x2)

inst_262:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0b5 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x322 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x033 and fcsr == 0x40 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x78b5; op2val:0x3722;
op3val:0x7433; valaddr_reg:x3; val_offset:786*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:64 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 64, 0, x3, 786*FLEN/8, x4, x1, x2)

inst_263:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0b5 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x322 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x033 and fcsr == 0x60 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x78b5; op2val:0x3722;
op3val:0x7433; valaddr_reg:x3; val_offset:789*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 96, 0, x3, 789*FLEN/8, x4, x1, x2)

inst_264:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0b5 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x322 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x033 and fcsr == 0x80 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x78b5; op2val:0x3722;
op3val:0x7433; valaddr_reg:x3; val_offset:792*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:128 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 128, 0, x3, 792*FLEN/8, x4, x1, x2)

inst_265:
// fs1 == 0 and fe1 == 0x17 and fm1 == 0x034 and fs2 == 0 and fe2 == 0x15 and fm2 == 0x25f and fs3 == 0 and fe3 == 0x1d and fm3 == 0x2b3 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x5c34; op2val:0x565f;
op3val:0x76b3; valaddr_reg:x3; val_offset:795*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 795*FLEN/8, x4, x1, x2)

inst_266:
// fs1 == 0 and fe1 == 0x17 and fm1 == 0x034 and fs2 == 0 and fe2 == 0x15 and fm2 == 0x25f and fs3 == 0 and fe3 == 0x1d and fm3 == 0x2b3 and fcsr == 0x20 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x5c34; op2val:0x565f;
op3val:0x76b3; valaddr_reg:x3; val_offset:798*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:32 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 32, 0, x3, 798*FLEN/8, x4, x1, x2)

inst_267:
// fs1 == 0 and fe1 == 0x17 and fm1 == 0x034 and fs2 == 0 and fe2 == 0x15 and fm2 == 0x25f and fs3 == 0 and fe3 == 0x1d and fm3 == 0x2b3 and fcsr == 0x40 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x5c34; op2val:0x565f;
op3val:0x76b3; valaddr_reg:x3; val_offset:801*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:64 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 64, 0, x3, 801*FLEN/8, x4, x1, x2)

inst_268:
// fs1 == 0 and fe1 == 0x17 and fm1 == 0x034 and fs2 == 0 and fe2 == 0x15 and fm2 == 0x25f and fs3 == 0 and fe3 == 0x1d and fm3 == 0x2b3 and fcsr == 0x60 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x5c34; op2val:0x565f;
op3val:0x76b3; valaddr_reg:x3; val_offset:804*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 96, 0, x3, 804*FLEN/8, x4, x1, x2)

inst_269:
// fs1 == 0 and fe1 == 0x17 and fm1 == 0x034 and fs2 == 0 and fe2 == 0x15 and fm2 == 0x25f and fs3 == 0 and fe3 == 0x1d and fm3 == 0x2b3 and fcsr == 0x80 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x5c34; op2val:0x565f;
op3val:0x76b3; valaddr_reg:x3; val_offset:807*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:128 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 128, 0, x3, 807*FLEN/8, x4, x1, x2)

inst_270:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x1e7 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x222 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x087 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x75e7; op2val:0x3e22;
op3val:0x7887; valaddr_reg:x3; val_offset:810*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 810*FLEN/8, x4, x1, x2)

inst_271:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x1e7 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x222 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x087 and fcsr == 0x20 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x75e7; op2val:0x3e22;
op3val:0x7887; valaddr_reg:x3; val_offset:813*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:32 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 32, 0, x3, 813*FLEN/8, x4, x1, x2)

inst_272:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x1e7 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x222 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x087 and fcsr == 0x40 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x75e7; op2val:0x3e22;
op3val:0x7887; valaddr_reg:x3; val_offset:816*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:64 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 64, 0, x3, 816*FLEN/8, x4, x1, x2)

inst_273:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x1e7 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x222 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x087 and fcsr == 0x60 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x75e7; op2val:0x3e22;
op3val:0x7887; valaddr_reg:x3; val_offset:819*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 96, 0, x3, 819*FLEN/8, x4, x1, x2)

inst_274:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x1e7 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x222 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x087 and fcsr == 0x80 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x75e7; op2val:0x3e22;
op3val:0x7887; valaddr_reg:x3; val_offset:822*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:128 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 128, 0, x3, 822*FLEN/8, x4, x1, x2)

inst_275:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x39e and fs2 == 0 and fe2 == 0x0e and fm2 == 0x1cb and fs3 == 0 and fe3 == 0x1e and fm3 == 0x185 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7b9e; op2val:0x39cb;
op3val:0x7985; valaddr_reg:x3; val_offset:825*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 825*FLEN/8, x4, x1, x2)

inst_276:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x39e and fs2 == 0 and fe2 == 0x0e and fm2 == 0x1cb and fs3 == 0 and fe3 == 0x1e and fm3 == 0x185 and fcsr == 0x20 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7b9e; op2val:0x39cb;
op3val:0x7985; valaddr_reg:x3; val_offset:828*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:32 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 32, 0, x3, 828*FLEN/8, x4, x1, x2)

inst_277:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x39e and fs2 == 0 and fe2 == 0x0e and fm2 == 0x1cb and fs3 == 0 and fe3 == 0x1e and fm3 == 0x185 and fcsr == 0x40 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7b9e; op2val:0x39cb;
op3val:0x7985; valaddr_reg:x3; val_offset:831*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:64 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 64, 0, x3, 831*FLEN/8, x4, x1, x2)

inst_278:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x39e and fs2 == 0 and fe2 == 0x0e and fm2 == 0x1cb and fs3 == 0 and fe3 == 0x1e and fm3 == 0x185 and fcsr == 0x60 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7b9e; op2val:0x39cb;
op3val:0x7985; valaddr_reg:x3; val_offset:834*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 96, 0, x3, 834*FLEN/8, x4, x1, x2)

inst_279:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x39e and fs2 == 0 and fe2 == 0x0e and fm2 == 0x1cb and fs3 == 0 and fe3 == 0x1e and fm3 == 0x185 and fcsr == 0x80 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7b9e; op2val:0x39cb;
op3val:0x7985; valaddr_reg:x3; val_offset:837*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:128 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 128, 0, x3, 837*FLEN/8, x4, x1, x2)

inst_280:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x01f and fs2 == 0 and fe2 == 0x0f and fm2 == 0x0ca and fs3 == 0 and fe3 == 0x1e and fm3 == 0x0f0 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x781f; op2val:0x3cca;
op3val:0x78f0; valaddr_reg:x3; val_offset:840*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 840*FLEN/8, x4, x1, x2)

inst_281:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x01f and fs2 == 0 and fe2 == 0x0f and fm2 == 0x0ca and fs3 == 0 and fe3 == 0x1e and fm3 == 0x0f0 and fcsr == 0x20 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x781f; op2val:0x3cca;
op3val:0x78f0; valaddr_reg:x3; val_offset:843*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:32 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 32, 0, x3, 843*FLEN/8, x4, x1, x2)

inst_282:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x01f and fs2 == 0 and fe2 == 0x0f and fm2 == 0x0ca and fs3 == 0 and fe3 == 0x1e and fm3 == 0x0f0 and fcsr == 0x40 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x781f; op2val:0x3cca;
op3val:0x78f0; valaddr_reg:x3; val_offset:846*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:64 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 64, 0, x3, 846*FLEN/8, x4, x1, x2)

inst_283:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x01f and fs2 == 0 and fe2 == 0x0f and fm2 == 0x0ca and fs3 == 0 and fe3 == 0x1e and fm3 == 0x0f0 and fcsr == 0x60 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x781f; op2val:0x3cca;
op3val:0x78f0; valaddr_reg:x3; val_offset:849*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 96, 0, x3, 849*FLEN/8, x4, x1, x2)

inst_284:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x01f and fs2 == 0 and fe2 == 0x0f and fm2 == 0x0ca and fs3 == 0 and fe3 == 0x1e and fm3 == 0x0f0 and fcsr == 0x80 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x781f; op2val:0x3cca;
op3val:0x78f0; valaddr_reg:x3; val_offset:852*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:128 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 128, 0, x3, 852*FLEN/8, x4, x1, x2)

inst_285:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x168 and fs2 == 0 and fe2 == 0x0b and fm2 == 0x11c and fs3 == 0 and fe3 == 0x1a and fm3 == 0x2e8 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7968; op2val:0x2d1c;
op3val:0x6ae8; valaddr_reg:x3; val_offset:855*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 855*FLEN/8, x4, x1, x2)

inst_286:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x168 and fs2 == 0 and fe2 == 0x0b and fm2 == 0x11c and fs3 == 0 and fe3 == 0x1a and fm3 == 0x2e8 and fcsr == 0x20 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7968; op2val:0x2d1c;
op3val:0x6ae8; valaddr_reg:x3; val_offset:858*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:32 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 32, 0, x3, 858*FLEN/8, x4, x1, x2)

inst_287:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x168 and fs2 == 0 and fe2 == 0x0b and fm2 == 0x11c and fs3 == 0 and fe3 == 0x1a and fm3 == 0x2e8 and fcsr == 0x40 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7968; op2val:0x2d1c;
op3val:0x6ae8; valaddr_reg:x3; val_offset:861*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:64 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 64, 0, x3, 861*FLEN/8, x4, x1, x2)

inst_288:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x168 and fs2 == 0 and fe2 == 0x0b and fm2 == 0x11c and fs3 == 0 and fe3 == 0x1a and fm3 == 0x2e8 and fcsr == 0x60 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7968; op2val:0x2d1c;
op3val:0x6ae8; valaddr_reg:x3; val_offset:864*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 96, 0, x3, 864*FLEN/8, x4, x1, x2)

inst_289:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x168 and fs2 == 0 and fe2 == 0x0b and fm2 == 0x11c and fs3 == 0 and fe3 == 0x1a and fm3 == 0x2e8 and fcsr == 0x80 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7968; op2val:0x2d1c;
op3val:0x6ae8; valaddr_reg:x3; val_offset:867*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:128 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 128, 0, x3, 867*FLEN/8, x4, x1, x2)

inst_290:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x331 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x2ef and fs3 == 0 and fe3 == 0x1e and fm3 == 0x23c and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7b31; op2val:0x3aef;
op3val:0x7a3c; valaddr_reg:x3; val_offset:870*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 870*FLEN/8, x4, x1, x2)

inst_291:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x331 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x2ef and fs3 == 0 and fe3 == 0x1e and fm3 == 0x23c and fcsr == 0x20 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7b31; op2val:0x3aef;
op3val:0x7a3c; valaddr_reg:x3; val_offset:873*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:32 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 32, 0, x3, 873*FLEN/8, x4, x1, x2)

inst_292:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x331 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x2ef and fs3 == 0 and fe3 == 0x1e and fm3 == 0x23c and fcsr == 0x40 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7b31; op2val:0x3aef;
op3val:0x7a3c; valaddr_reg:x3; val_offset:876*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:64 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 64, 0, x3, 876*FLEN/8, x4, x1, x2)

inst_293:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x331 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x2ef and fs3 == 0 and fe3 == 0x1e and fm3 == 0x23c and fcsr == 0x60 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7b31; op2val:0x3aef;
op3val:0x7a3c; valaddr_reg:x3; val_offset:879*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 96, 0, x3, 879*FLEN/8, x4, x1, x2)

inst_294:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x331 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x2ef and fs3 == 0 and fe3 == 0x1e and fm3 == 0x23c and fcsr == 0x80 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7b31; op2val:0x3aef;
op3val:0x7a3c; valaddr_reg:x3; val_offset:882*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:128 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 128, 0, x3, 882*FLEN/8, x4, x1, x2)

inst_295:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2fe and fs2 == 0 and fe2 == 0x0e and fm2 == 0x34c and fs3 == 0 and fe3 == 0x1e and fm3 == 0x261 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7afe; op2val:0x3b4c;
op3val:0x7a61; valaddr_reg:x3; val_offset:885*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 885*FLEN/8, x4, x1, x2)

inst_296:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2fe and fs2 == 0 and fe2 == 0x0e and fm2 == 0x34c and fs3 == 0 and fe3 == 0x1e and fm3 == 0x261 and fcsr == 0x20 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7afe; op2val:0x3b4c;
op3val:0x7a61; valaddr_reg:x3; val_offset:888*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:32 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 32, 0, x3, 888*FLEN/8, x4, x1, x2)

inst_297:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2fe and fs2 == 0 and fe2 == 0x0e and fm2 == 0x34c and fs3 == 0 and fe3 == 0x1e and fm3 == 0x261 and fcsr == 0x40 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7afe; op2val:0x3b4c;
op3val:0x7a61; valaddr_reg:x3; val_offset:891*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:64 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 64, 0, x3, 891*FLEN/8, x4, x1, x2)

inst_298:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2fe and fs2 == 0 and fe2 == 0x0e and fm2 == 0x34c and fs3 == 0 and fe3 == 0x1e and fm3 == 0x261 and fcsr == 0x60 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7afe; op2val:0x3b4c;
op3val:0x7a61; valaddr_reg:x3; val_offset:894*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 96, 0, x3, 894*FLEN/8, x4, x1, x2)

inst_299:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2fe and fs2 == 0 and fe2 == 0x0e and fm2 == 0x34c and fs3 == 0 and fe3 == 0x1e and fm3 == 0x261 and fcsr == 0x80 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7afe; op2val:0x3b4c;
op3val:0x7a61; valaddr_reg:x3; val_offset:897*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:128 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 128, 0, x3, 897*FLEN/8, x4, x1, x2)

inst_300:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x246 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x011 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x261 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7646; op2val:0x3c11;
op3val:0x7661; valaddr_reg:x3; val_offset:900*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 900*FLEN/8, x4, x1, x2)

inst_301:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x246 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x011 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x261 and fcsr == 0x20 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7646; op2val:0x3c11;
op3val:0x7661; valaddr_reg:x3; val_offset:903*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:32 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 32, 0, x3, 903*FLEN/8, x4, x1, x2)

inst_302:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x246 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x011 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x261 and fcsr == 0x40 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7646; op2val:0x3c11;
op3val:0x7661; valaddr_reg:x3; val_offset:906*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:64 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 64, 0, x3, 906*FLEN/8, x4, x1, x2)

inst_303:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x246 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x011 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x261 and fcsr == 0x60 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7646; op2val:0x3c11;
op3val:0x7661; valaddr_reg:x3; val_offset:909*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 96, 0, x3, 909*FLEN/8, x4, x1, x2)

inst_304:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x246 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x011 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x261 and fcsr == 0x80 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7646; op2val:0x3c11;
op3val:0x7661; valaddr_reg:x3; val_offset:912*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:128 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 128, 0, x3, 912*FLEN/8, x4, x1, x2)

inst_305:
// fs1 == 0 and fe1 == 0x1b and fm1 == 0x29f and fs2 == 0 and fe2 == 0x11 and fm2 == 0x220 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x112 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x6e9f; op2val:0x4620;
op3val:0x7912; valaddr_reg:x3; val_offset:915*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 915*FLEN/8, x4, x1, x2)

inst_306:
// fs1 == 0 and fe1 == 0x1b and fm1 == 0x29f and fs2 == 0 and fe2 == 0x11 and fm2 == 0x220 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x112 and fcsr == 0x20 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x6e9f; op2val:0x4620;
op3val:0x7912; valaddr_reg:x3; val_offset:918*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:32 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 32, 0, x3, 918*FLEN/8, x4, x1, x2)

inst_307:
// fs1 == 0 and fe1 == 0x1b and fm1 == 0x29f and fs2 == 0 and fe2 == 0x11 and fm2 == 0x220 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x112 and fcsr == 0x40 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x6e9f; op2val:0x4620;
op3val:0x7912; valaddr_reg:x3; val_offset:921*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:64 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 64, 0, x3, 921*FLEN/8, x4, x1, x2)

inst_308:
// fs1 == 0 and fe1 == 0x1b and fm1 == 0x29f and fs2 == 0 and fe2 == 0x11 and fm2 == 0x220 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x112 and fcsr == 0x60 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x6e9f; op2val:0x4620;
op3val:0x7912; valaddr_reg:x3; val_offset:924*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 96, 0, x3, 924*FLEN/8, x4, x1, x2)

inst_309:
// fs1 == 0 and fe1 == 0x1b and fm1 == 0x29f and fs2 == 0 and fe2 == 0x11 and fm2 == 0x220 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x112 and fcsr == 0x80 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x6e9f; op2val:0x4620;
op3val:0x7912; valaddr_reg:x3; val_offset:927*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:128 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 128, 0, x3, 927*FLEN/8, x4, x1, x2)

inst_310:
// fs1 == 0 and fe1 == 0x1a and fm1 == 0x3f7 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x053 and fs3 == 0 and fe3 == 0x1b and fm3 == 0x04f and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x6bf7; op2val:0x3c53;
op3val:0x6c4f; valaddr_reg:x3; val_offset:930*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 930*FLEN/8, x4, x1, x2)

inst_311:
// fs1 == 0 and fe1 == 0x1a and fm1 == 0x3f7 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x053 and fs3 == 0 and fe3 == 0x1b and fm3 == 0x04f and fcsr == 0x20 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x6bf7; op2val:0x3c53;
op3val:0x6c4f; valaddr_reg:x3; val_offset:933*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:32 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 32, 0, x3, 933*FLEN/8, x4, x1, x2)

inst_312:
// fs1 == 0 and fe1 == 0x1a and fm1 == 0x3f7 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x053 and fs3 == 0 and fe3 == 0x1b and fm3 == 0x04f and fcsr == 0x40 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x6bf7; op2val:0x3c53;
op3val:0x6c4f; valaddr_reg:x3; val_offset:936*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:64 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 64, 0, x3, 936*FLEN/8, x4, x1, x2)

inst_313:
// fs1 == 0 and fe1 == 0x1a and fm1 == 0x3f7 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x053 and fs3 == 0 and fe3 == 0x1b and fm3 == 0x04f and fcsr == 0x60 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x6bf7; op2val:0x3c53;
op3val:0x6c4f; valaddr_reg:x3; val_offset:939*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 96, 0, x3, 939*FLEN/8, x4, x1, x2)

inst_314:
// fs1 == 0 and fe1 == 0x1a and fm1 == 0x3f7 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x053 and fs3 == 0 and fe3 == 0x1b and fm3 == 0x04f and fcsr == 0x80 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x6bf7; op2val:0x3c53;
op3val:0x6c4f; valaddr_reg:x3; val_offset:942*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:128 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 128, 0, x3, 942*FLEN/8, x4, x1, x2)

inst_315:
// fs1 == 0 and fe1 == 0x1c and fm1 == 0x2ad and fs2 == 0 and fe2 == 0x0e and fm2 == 0x238 and fs3 == 0 and fe3 == 0x1c and fm3 == 0x131 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x72ad; op2val:0x3a38;
op3val:0x7131; valaddr_reg:x3; val_offset:945*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 945*FLEN/8, x4, x1, x2)

inst_316:
// fs1 == 0 and fe1 == 0x1c and fm1 == 0x2ad and fs2 == 0 and fe2 == 0x0e and fm2 == 0x238 and fs3 == 0 and fe3 == 0x1c and fm3 == 0x131 and fcsr == 0x20 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x72ad; op2val:0x3a38;
op3val:0x7131; valaddr_reg:x3; val_offset:948*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:32 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 32, 0, x3, 948*FLEN/8, x4, x1, x2)

inst_317:
// fs1 == 0 and fe1 == 0x1c and fm1 == 0x2ad and fs2 == 0 and fe2 == 0x0e and fm2 == 0x238 and fs3 == 0 and fe3 == 0x1c and fm3 == 0x131 and fcsr == 0x40 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x72ad; op2val:0x3a38;
op3val:0x7131; valaddr_reg:x3; val_offset:951*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:64 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 64, 0, x3, 951*FLEN/8, x4, x1, x2)

inst_318:
// fs1 == 0 and fe1 == 0x1c and fm1 == 0x2ad and fs2 == 0 and fe2 == 0x0e and fm2 == 0x238 and fs3 == 0 and fe3 == 0x1c and fm3 == 0x131 and fcsr == 0x60 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x72ad; op2val:0x3a38;
op3val:0x7131; valaddr_reg:x3; val_offset:954*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 96, 0, x3, 954*FLEN/8, x4, x1, x2)

inst_319:
// fs1 == 0 and fe1 == 0x1c and fm1 == 0x2ad and fs2 == 0 and fe2 == 0x0e and fm2 == 0x238 and fs3 == 0 and fe3 == 0x1c and fm3 == 0x131 and fcsr == 0x80 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x72ad; op2val:0x3a38;
op3val:0x7131; valaddr_reg:x3; val_offset:957*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:128 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 128, 0, x3, 957*FLEN/8, x4, x1, x2)

inst_320:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x170 and fs2 == 0 and fe2 == 0x0c and fm2 == 0x0f2 and fs3 == 0 and fe3 == 0x1a and fm3 == 0x2ba and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7570; op2val:0x30f2;
op3val:0x6aba; valaddr_reg:x3; val_offset:960*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 960*FLEN/8, x4, x1, x2)

inst_321:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x170 and fs2 == 0 and fe2 == 0x0c and fm2 == 0x0f2 and fs3 == 0 and fe3 == 0x1a and fm3 == 0x2ba and fcsr == 0x20 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7570; op2val:0x30f2;
op3val:0x6aba; valaddr_reg:x3; val_offset:963*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:32 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 32, 0, x3, 963*FLEN/8, x4, x1, x2)

inst_322:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x170 and fs2 == 0 and fe2 == 0x0c and fm2 == 0x0f2 and fs3 == 0 and fe3 == 0x1a and fm3 == 0x2ba and fcsr == 0x40 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7570; op2val:0x30f2;
op3val:0x6aba; valaddr_reg:x3; val_offset:966*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:64 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 64, 0, x3, 966*FLEN/8, x4, x1, x2)

inst_323:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x170 and fs2 == 0 and fe2 == 0x0c and fm2 == 0x0f2 and fs3 == 0 and fe3 == 0x1a and fm3 == 0x2ba and fcsr == 0x60 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7570; op2val:0x30f2;
op3val:0x6aba; valaddr_reg:x3; val_offset:969*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 96, 0, x3, 969*FLEN/8, x4, x1, x2)

inst_324:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x170 and fs2 == 0 and fe2 == 0x0c and fm2 == 0x0f2 and fs3 == 0 and fe3 == 0x1a and fm3 == 0x2ba and fcsr == 0x80 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7570; op2val:0x30f2;
op3val:0x6aba; valaddr_reg:x3; val_offset:972*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:128 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 128, 0, x3, 972*FLEN/8, x4, x1, x2)

inst_325:
// fs1 == 0 and fe1 == 0x13 and fm1 == 0x011 and fs2 == 0 and fe2 == 0x18 and fm2 == 0x0c1 and fs3 == 0 and fe3 == 0x1c and fm3 == 0x0d6 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x4c11; op2val:0x60c1;
op3val:0x70d6; valaddr_reg:x3; val_offset:975*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 975*FLEN/8, x4, x1, x2)

inst_326:
// fs1 == 0 and fe1 == 0x13 and fm1 == 0x011 and fs2 == 0 and fe2 == 0x18 and fm2 == 0x0c1 and fs3 == 0 and fe3 == 0x1c and fm3 == 0x0d6 and fcsr == 0x20 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x4c11; op2val:0x60c1;
op3val:0x70d6; valaddr_reg:x3; val_offset:978*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:32 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 32, 0, x3, 978*FLEN/8, x4, x1, x2)

inst_327:
// fs1 == 0 and fe1 == 0x13 and fm1 == 0x011 and fs2 == 0 and fe2 == 0x18 and fm2 == 0x0c1 and fs3 == 0 and fe3 == 0x1c and fm3 == 0x0d6 and fcsr == 0x40 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x4c11; op2val:0x60c1;
op3val:0x70d6; valaddr_reg:x3; val_offset:981*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:64 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 64, 0, x3, 981*FLEN/8, x4, x1, x2)

inst_328:
// fs1 == 0 and fe1 == 0x13 and fm1 == 0x011 and fs2 == 0 and fe2 == 0x18 and fm2 == 0x0c1 and fs3 == 0 and fe3 == 0x1c and fm3 == 0x0d6 and fcsr == 0x60 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x4c11; op2val:0x60c1;
op3val:0x70d6; valaddr_reg:x3; val_offset:984*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 96, 0, x3, 984*FLEN/8, x4, x1, x2)

inst_329:
// fs1 == 0 and fe1 == 0x13 and fm1 == 0x011 and fs2 == 0 and fe2 == 0x18 and fm2 == 0x0c1 and fs3 == 0 and fe3 == 0x1c and fm3 == 0x0d6 and fcsr == 0x80 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x4c11; op2val:0x60c1;
op3val:0x70d6; valaddr_reg:x3; val_offset:987*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:128 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 128, 0, x3, 987*FLEN/8, x4, x1, x2)

inst_330:
// fs1 == 0 and fe1 == 0x1b and fm1 == 0x27d and fs2 == 0 and fe2 == 0x10 and fm2 == 0x32a and fs3 == 0 and fe3 == 0x1d and fm3 == 0x1d0 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x6e7d; op2val:0x432a;
op3val:0x75d0; valaddr_reg:x3; val_offset:990*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 990*FLEN/8, x4, x1, x2)

inst_331:
// fs1 == 0 and fe1 == 0x1b and fm1 == 0x27d and fs2 == 0 and fe2 == 0x10 and fm2 == 0x32a and fs3 == 0 and fe3 == 0x1d and fm3 == 0x1d0 and fcsr == 0x20 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x6e7d; op2val:0x432a;
op3val:0x75d0; valaddr_reg:x3; val_offset:993*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:32 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 32, 0, x3, 993*FLEN/8, x4, x1, x2)

inst_332:
// fs1 == 0 and fe1 == 0x1b and fm1 == 0x27d and fs2 == 0 and fe2 == 0x10 and fm2 == 0x32a and fs3 == 0 and fe3 == 0x1d and fm3 == 0x1d0 and fcsr == 0x40 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x6e7d; op2val:0x432a;
op3val:0x75d0; valaddr_reg:x3; val_offset:996*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:64 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 64, 0, x3, 996*FLEN/8, x4, x1, x2)

inst_333:
// fs1 == 0 and fe1 == 0x1b and fm1 == 0x27d and fs2 == 0 and fe2 == 0x10 and fm2 == 0x32a and fs3 == 0 and fe3 == 0x1d and fm3 == 0x1d0 and fcsr == 0x60 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x6e7d; op2val:0x432a;
op3val:0x75d0; valaddr_reg:x3; val_offset:999*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 96, 0, x3, 999*FLEN/8, x4, x1, x2)

inst_334:
// fs1 == 0 and fe1 == 0x1b and fm1 == 0x27d and fs2 == 0 and fe2 == 0x10 and fm2 == 0x32a and fs3 == 0 and fe3 == 0x1d and fm3 == 0x1d0 and fcsr == 0x80 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x6e7d; op2val:0x432a;
op3val:0x75d0; valaddr_reg:x3; val_offset:1002*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:128 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 128, 0, x3, 1002*FLEN/8, x4, x1, x2)

inst_335:
// fs1 == 0 and fe1 == 0x19 and fm1 == 0x287 and fs2 == 0 and fe2 == 0x14 and fm2 == 0x048 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x2fd and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x6687; op2val:0x5048;
op3val:0x7afd; valaddr_reg:x3; val_offset:1005*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 1005*FLEN/8, x4, x1, x2)

inst_336:
// fs1 == 0 and fe1 == 0x19 and fm1 == 0x287 and fs2 == 0 and fe2 == 0x14 and fm2 == 0x048 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x2fd and fcsr == 0x20 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x6687; op2val:0x5048;
op3val:0x7afd; valaddr_reg:x3; val_offset:1008*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:32 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 32, 0, x3, 1008*FLEN/8, x4, x1, x2)

inst_337:
// fs1 == 0 and fe1 == 0x19 and fm1 == 0x287 and fs2 == 0 and fe2 == 0x14 and fm2 == 0x048 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x2fd and fcsr == 0x40 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x6687; op2val:0x5048;
op3val:0x7afd; valaddr_reg:x3; val_offset:1011*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:64 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 64, 0, x3, 1011*FLEN/8, x4, x1, x2)

inst_338:
// fs1 == 0 and fe1 == 0x19 and fm1 == 0x287 and fs2 == 0 and fe2 == 0x14 and fm2 == 0x048 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x2fd and fcsr == 0x60 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x6687; op2val:0x5048;
op3val:0x7afd; valaddr_reg:x3; val_offset:1014*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 96, 0, x3, 1014*FLEN/8, x4, x1, x2)

inst_339:
// fs1 == 0 and fe1 == 0x19 and fm1 == 0x287 and fs2 == 0 and fe2 == 0x14 and fm2 == 0x048 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x2fd and fcsr == 0x80 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x6687; op2val:0x5048;
op3val:0x7afd; valaddr_reg:x3; val_offset:1017*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:128 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 128, 0, x3, 1017*FLEN/8, x4, x1, x2)

inst_340:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0e9 and fs2 == 0 and fe2 == 0x0c and fm2 == 0x3bd and fs3 == 0 and fe3 == 0x1c and fm3 == 0x0c0 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x78e9; op2val:0x33bd;
op3val:0x70c0; valaddr_reg:x3; val_offset:1020*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 1020*FLEN/8, x4, x1, x2)

inst_341:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0e9 and fs2 == 0 and fe2 == 0x0c and fm2 == 0x3bd and fs3 == 0 and fe3 == 0x1c and fm3 == 0x0c0 and fcsr == 0x20 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x78e9; op2val:0x33bd;
op3val:0x70c0; valaddr_reg:x3; val_offset:1023*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:32 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 32, 0, x3, 1023*FLEN/8, x4, x1, x2)

inst_342:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0e9 and fs2 == 0 and fe2 == 0x0c and fm2 == 0x3bd and fs3 == 0 and fe3 == 0x1c and fm3 == 0x0c0 and fcsr == 0x40 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x78e9; op2val:0x33bd;
op3val:0x70c0; valaddr_reg:x3; val_offset:1026*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:64 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 64, 0, x3, 1026*FLEN/8, x4, x1, x2)

inst_343:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0e9 and fs2 == 0 and fe2 == 0x0c and fm2 == 0x3bd and fs3 == 0 and fe3 == 0x1c and fm3 == 0x0c0 and fcsr == 0x60 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x78e9; op2val:0x33bd;
op3val:0x70c0; valaddr_reg:x3; val_offset:1029*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 96, 0, x3, 1029*FLEN/8, x4, x1, x2)

inst_344:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0e9 and fs2 == 0 and fe2 == 0x0c and fm2 == 0x3bd and fs3 == 0 and fe3 == 0x1c and fm3 == 0x0c0 and fcsr == 0x80 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x78e9; op2val:0x33bd;
op3val:0x70c0; valaddr_reg:x3; val_offset:1032*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:128 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 128, 0, x3, 1032*FLEN/8, x4, x1, x2)

inst_345:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x008 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x182 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x18e and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7408; op2val:0x3d82;
op3val:0x758e; valaddr_reg:x3; val_offset:1035*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 1035*FLEN/8, x4, x1, x2)

inst_346:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x008 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x182 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x18e and fcsr == 0x20 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7408; op2val:0x3d82;
op3val:0x758e; valaddr_reg:x3; val_offset:1038*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:32 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 32, 0, x3, 1038*FLEN/8, x4, x1, x2)

inst_347:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x008 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x182 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x18e and fcsr == 0x40 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7408; op2val:0x3d82;
op3val:0x758e; valaddr_reg:x3; val_offset:1041*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:64 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 64, 0, x3, 1041*FLEN/8, x4, x1, x2)

inst_348:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x008 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x182 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x18e and fcsr == 0x60 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7408; op2val:0x3d82;
op3val:0x758e; valaddr_reg:x3; val_offset:1044*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 96, 0, x3, 1044*FLEN/8, x4, x1, x2)

inst_349:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x008 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x182 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x18e and fcsr == 0x80 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7408; op2val:0x3d82;
op3val:0x758e; valaddr_reg:x3; val_offset:1047*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:128 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 128, 0, x3, 1047*FLEN/8, x4, x1, x2)

inst_350:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x1d2 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x165 and fs3 == 0 and fe3 == 0x1b and fm3 == 0x3db and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x75d2; op2val:0x3565;
op3val:0x6fdb; valaddr_reg:x3; val_offset:1050*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 1050*FLEN/8, x4, x1, x2)

inst_351:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x1d2 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x165 and fs3 == 0 and fe3 == 0x1b and fm3 == 0x3db and fcsr == 0x20 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x75d2; op2val:0x3565;
op3val:0x6fdb; valaddr_reg:x3; val_offset:1053*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:32 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 32, 0, x3, 1053*FLEN/8, x4, x1, x2)

inst_352:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x1d2 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x165 and fs3 == 0 and fe3 == 0x1b and fm3 == 0x3db and fcsr == 0x40 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x75d2; op2val:0x3565;
op3val:0x6fdb; valaddr_reg:x3; val_offset:1056*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:64 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 64, 0, x3, 1056*FLEN/8, x4, x1, x2)

inst_353:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x1d2 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x165 and fs3 == 0 and fe3 == 0x1b and fm3 == 0x3db and fcsr == 0x60 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x75d2; op2val:0x3565;
op3val:0x6fdb; valaddr_reg:x3; val_offset:1059*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 96, 0, x3, 1059*FLEN/8, x4, x1, x2)

inst_354:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x1d2 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x165 and fs3 == 0 and fe3 == 0x1b and fm3 == 0x3db and fcsr == 0x80 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x75d2; op2val:0x3565;
op3val:0x6fdb; valaddr_reg:x3; val_offset:1062*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:128 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 128, 0, x3, 1062*FLEN/8, x4, x1, x2)

inst_355:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2c9 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x0ad and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3f0 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7ac9; op2val:0x3cad;
op3val:0x7bf0; valaddr_reg:x3; val_offset:1065*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 1065*FLEN/8, x4, x1, x2)

inst_356:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2c9 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x0ad and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3f0 and fcsr == 0x20 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7ac9; op2val:0x3cad;
op3val:0x7bf0; valaddr_reg:x3; val_offset:1068*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:32 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 32, 0, x3, 1068*FLEN/8, x4, x1, x2)

inst_357:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2c9 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x0ad and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3f0 and fcsr == 0x40 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7ac9; op2val:0x3cad;
op3val:0x7bf0; valaddr_reg:x3; val_offset:1071*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:64 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 64, 0, x3, 1071*FLEN/8, x4, x1, x2)

inst_358:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2c9 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x0ad and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3f0 and fcsr == 0x60 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7ac9; op2val:0x3cad;
op3val:0x7bf0; valaddr_reg:x3; val_offset:1074*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 96, 0, x3, 1074*FLEN/8, x4, x1, x2)

inst_359:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2c9 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x0ad and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3f0 and fcsr == 0x80 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7ac9; op2val:0x3cad;
op3val:0x7bf0; valaddr_reg:x3; val_offset:1077*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:128 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 128, 0, x3, 1077*FLEN/8, x4, x1, x2)

inst_360:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x373 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x027 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x3bc and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7773; op2val:0x3c27;
op3val:0x77bc; valaddr_reg:x3; val_offset:1080*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 1080*FLEN/8, x4, x1, x2)

inst_361:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x373 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x027 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x3bc and fcsr == 0x20 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7773; op2val:0x3c27;
op3val:0x77bc; valaddr_reg:x3; val_offset:1083*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:32 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 32, 0, x3, 1083*FLEN/8, x4, x1, x2)

inst_362:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x373 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x027 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x3bc and fcsr == 0x40 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7773; op2val:0x3c27;
op3val:0x77bc; valaddr_reg:x3; val_offset:1086*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:64 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 64, 0, x3, 1086*FLEN/8, x4, x1, x2)

inst_363:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x373 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x027 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x3bc and fcsr == 0x60 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7773; op2val:0x3c27;
op3val:0x77bc; valaddr_reg:x3; val_offset:1089*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 96, 0, x3, 1089*FLEN/8, x4, x1, x2)

inst_364:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x373 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x027 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x3bc and fcsr == 0x80 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7773; op2val:0x3c27;
op3val:0x77bc; valaddr_reg:x3; val_offset:1092*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:128 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 128, 0, x3, 1092*FLEN/8, x4, x1, x2)

inst_365:
// fs1 == 0 and fe1 == 0x1b and fm1 == 0x17e and fs2 == 0 and fe2 == 0x0f and fm2 == 0x0c2 and fs3 == 0 and fe3 == 0x1b and fm3 == 0x289 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x6d7e; op2val:0x3cc2;
op3val:0x6e89; valaddr_reg:x3; val_offset:1095*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 1095*FLEN/8, x4, x1, x2)

inst_366:
// fs1 == 0 and fe1 == 0x1b and fm1 == 0x17e and fs2 == 0 and fe2 == 0x0f and fm2 == 0x0c2 and fs3 == 0 and fe3 == 0x1b and fm3 == 0x289 and fcsr == 0x20 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x6d7e; op2val:0x3cc2;
op3val:0x6e89; valaddr_reg:x3; val_offset:1098*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:32 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 32, 0, x3, 1098*FLEN/8, x4, x1, x2)

inst_367:
// fs1 == 0 and fe1 == 0x1b and fm1 == 0x17e and fs2 == 0 and fe2 == 0x0f and fm2 == 0x0c2 and fs3 == 0 and fe3 == 0x1b and fm3 == 0x289 and fcsr == 0x40 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x6d7e; op2val:0x3cc2;
op3val:0x6e89; valaddr_reg:x3; val_offset:1101*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:64 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 64, 0, x3, 1101*FLEN/8, x4, x1, x2)

inst_368:
// fs1 == 0 and fe1 == 0x1b and fm1 == 0x17e and fs2 == 0 and fe2 == 0x0f and fm2 == 0x0c2 and fs3 == 0 and fe3 == 0x1b and fm3 == 0x289 and fcsr == 0x60 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x6d7e; op2val:0x3cc2;
op3val:0x6e89; valaddr_reg:x3; val_offset:1104*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 96, 0, x3, 1104*FLEN/8, x4, x1, x2)

inst_369:
// fs1 == 0 and fe1 == 0x1b and fm1 == 0x17e and fs2 == 0 and fe2 == 0x0f and fm2 == 0x0c2 and fs3 == 0 and fe3 == 0x1b and fm3 == 0x289 and fcsr == 0x80 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x6d7e; op2val:0x3cc2;
op3val:0x6e89; valaddr_reg:x3; val_offset:1107*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:128 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 128, 0, x3, 1107*FLEN/8, x4, x1, x2)

inst_370:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x17a and fs2 == 0 and fe2 == 0x0e and fm2 == 0x22e and fs3 == 0 and fe3 == 0x1d and fm3 == 0x03b and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x757a; op2val:0x3a2e;
op3val:0x743b; valaddr_reg:x3; val_offset:1110*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 1110*FLEN/8, x4, x1, x2)

inst_371:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x17a and fs2 == 0 and fe2 == 0x0e and fm2 == 0x22e and fs3 == 0 and fe3 == 0x1d and fm3 == 0x03b and fcsr == 0x20 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x757a; op2val:0x3a2e;
op3val:0x743b; valaddr_reg:x3; val_offset:1113*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:32 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 32, 0, x3, 1113*FLEN/8, x4, x1, x2)

inst_372:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x17a and fs2 == 0 and fe2 == 0x0e and fm2 == 0x22e and fs3 == 0 and fe3 == 0x1d and fm3 == 0x03b and fcsr == 0x40 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x757a; op2val:0x3a2e;
op3val:0x743b; valaddr_reg:x3; val_offset:1116*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:64 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 64, 0, x3, 1116*FLEN/8, x4, x1, x2)

inst_373:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x17a and fs2 == 0 and fe2 == 0x0e and fm2 == 0x22e and fs3 == 0 and fe3 == 0x1d and fm3 == 0x03b and fcsr == 0x60 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x757a; op2val:0x3a2e;
op3val:0x743b; valaddr_reg:x3; val_offset:1119*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 96, 0, x3, 1119*FLEN/8, x4, x1, x2)

inst_374:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x17a and fs2 == 0 and fe2 == 0x0e and fm2 == 0x22e and fs3 == 0 and fe3 == 0x1d and fm3 == 0x03b and fcsr == 0x80 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x757a; op2val:0x3a2e;
op3val:0x743b; valaddr_reg:x3; val_offset:1122*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:128 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 128, 0, x3, 1122*FLEN/8, x4, x1, x2)

inst_375:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2a0 and fs2 == 0 and fe2 == 0x0c and fm2 == 0x23b and fs3 == 0 and fe3 == 0x1c and fm3 == 0x129 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7aa0; op2val:0x323b;
op3val:0x7129; valaddr_reg:x3; val_offset:1125*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 1125*FLEN/8, x4, x1, x2)

inst_376:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2a0 and fs2 == 0 and fe2 == 0x0c and fm2 == 0x23b and fs3 == 0 and fe3 == 0x1c and fm3 == 0x129 and fcsr == 0x20 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7aa0; op2val:0x323b;
op3val:0x7129; valaddr_reg:x3; val_offset:1128*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:32 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 32, 0, x3, 1128*FLEN/8, x4, x1, x2)

inst_377:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2a0 and fs2 == 0 and fe2 == 0x0c and fm2 == 0x23b and fs3 == 0 and fe3 == 0x1c and fm3 == 0x129 and fcsr == 0x40 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7aa0; op2val:0x323b;
op3val:0x7129; valaddr_reg:x3; val_offset:1131*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:64 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 64, 0, x3, 1131*FLEN/8, x4, x1, x2)

inst_378:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2a0 and fs2 == 0 and fe2 == 0x0c and fm2 == 0x23b and fs3 == 0 and fe3 == 0x1c and fm3 == 0x129 and fcsr == 0x60 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7aa0; op2val:0x323b;
op3val:0x7129; valaddr_reg:x3; val_offset:1134*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 96, 0, x3, 1134*FLEN/8, x4, x1, x2)

inst_379:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2a0 and fs2 == 0 and fe2 == 0x0c and fm2 == 0x23b and fs3 == 0 and fe3 == 0x1c and fm3 == 0x129 and fcsr == 0x80 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7aa0; op2val:0x323b;
op3val:0x7129; valaddr_reg:x3; val_offset:1137*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:128 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 128, 0, x3, 1137*FLEN/8, x4, x1, x2)

inst_380:
// fs1 == 0 and fe1 == 0x19 and fm1 == 0x1e9 and fs2 == 0 and fe2 == 0x14 and fm2 == 0x124 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x39a and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x65e9; op2val:0x5124;
op3val:0x7b9a; valaddr_reg:x3; val_offset:1140*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 1140*FLEN/8, x4, x1, x2)

inst_381:
// fs1 == 0 and fe1 == 0x19 and fm1 == 0x1e9 and fs2 == 0 and fe2 == 0x14 and fm2 == 0x124 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x39a and fcsr == 0x20 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x65e9; op2val:0x5124;
op3val:0x7b9a; valaddr_reg:x3; val_offset:1143*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:32 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 32, 0, x3, 1143*FLEN/8, x4, x1, x2)

inst_382:
// fs1 == 0 and fe1 == 0x19 and fm1 == 0x1e9 and fs2 == 0 and fe2 == 0x14 and fm2 == 0x124 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x39a and fcsr == 0x40 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x65e9; op2val:0x5124;
op3val:0x7b9a; valaddr_reg:x3; val_offset:1146*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:64 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 64, 0, x3, 1146*FLEN/8, x4, x1, x2)

inst_383:
// fs1 == 0 and fe1 == 0x19 and fm1 == 0x1e9 and fs2 == 0 and fe2 == 0x14 and fm2 == 0x124 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x39a and fcsr == 0x60 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x65e9; op2val:0x5124;
op3val:0x7b9a; valaddr_reg:x3; val_offset:1149*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 96, 0, x3, 1149*FLEN/8, x4, x1, x2)
RVTEST_SIGBASE(x1,signature_x1_4)

inst_384:
// fs1 == 0 and fe1 == 0x19 and fm1 == 0x1e9 and fs2 == 0 and fe2 == 0x14 and fm2 == 0x124 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x39a and fcsr == 0x80 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x65e9; op2val:0x5124;
op3val:0x7b9a; valaddr_reg:x3; val_offset:1152*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:128 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 128, 0, x3, 1152*FLEN/8, x4, x1, x2)

inst_385:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x039 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x070 and fs3 == 0 and fe3 == 0x1c and fm3 == 0x0b0 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7839; op2val:0x3470;
op3val:0x70b0; valaddr_reg:x3; val_offset:1155*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 1155*FLEN/8, x4, x1, x2)

inst_386:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x039 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x070 and fs3 == 0 and fe3 == 0x1c and fm3 == 0x0b0 and fcsr == 0x20 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7839; op2val:0x3470;
op3val:0x70b0; valaddr_reg:x3; val_offset:1158*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:32 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 32, 0, x3, 1158*FLEN/8, x4, x1, x2)

inst_387:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x039 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x070 and fs3 == 0 and fe3 == 0x1c and fm3 == 0x0b0 and fcsr == 0x40 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7839; op2val:0x3470;
op3val:0x70b0; valaddr_reg:x3; val_offset:1161*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:64 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 64, 0, x3, 1161*FLEN/8, x4, x1, x2)

inst_388:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x039 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x070 and fs3 == 0 and fe3 == 0x1c and fm3 == 0x0b0 and fcsr == 0x60 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7839; op2val:0x3470;
op3val:0x70b0; valaddr_reg:x3; val_offset:1164*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 96, 0, x3, 1164*FLEN/8, x4, x1, x2)

inst_389:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x039 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x070 and fs3 == 0 and fe3 == 0x1c and fm3 == 0x0b0 and fcsr == 0x80 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7839; op2val:0x3470;
op3val:0x70b0; valaddr_reg:x3; val_offset:1167*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:128 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 128, 0, x3, 1167*FLEN/8, x4, x1, x2)

inst_390:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x057 and fs2 == 0 and fe2 == 0x0a and fm2 == 0x260 and fs3 == 0 and fe3 == 0x19 and fm3 == 0x2ec and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7857; op2val:0x2a60;
op3val:0x66ec; valaddr_reg:x3; val_offset:1170*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 1170*FLEN/8, x4, x1, x2)

inst_391:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x057 and fs2 == 0 and fe2 == 0x0a and fm2 == 0x260 and fs3 == 0 and fe3 == 0x19 and fm3 == 0x2ec and fcsr == 0x20 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7857; op2val:0x2a60;
op3val:0x66ec; valaddr_reg:x3; val_offset:1173*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:32 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 32, 0, x3, 1173*FLEN/8, x4, x1, x2)

inst_392:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x057 and fs2 == 0 and fe2 == 0x0a and fm2 == 0x260 and fs3 == 0 and fe3 == 0x19 and fm3 == 0x2ec and fcsr == 0x40 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7857; op2val:0x2a60;
op3val:0x66ec; valaddr_reg:x3; val_offset:1176*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:64 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 64, 0, x3, 1176*FLEN/8, x4, x1, x2)

inst_393:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x057 and fs2 == 0 and fe2 == 0x0a and fm2 == 0x260 and fs3 == 0 and fe3 == 0x19 and fm3 == 0x2ec and fcsr == 0x60 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7857; op2val:0x2a60;
op3val:0x66ec; valaddr_reg:x3; val_offset:1179*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 96, 0, x3, 1179*FLEN/8, x4, x1, x2)

inst_394:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x057 and fs2 == 0 and fe2 == 0x0a and fm2 == 0x260 and fs3 == 0 and fe3 == 0x19 and fm3 == 0x2ec and fcsr == 0x80 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7857; op2val:0x2a60;
op3val:0x66ec; valaddr_reg:x3; val_offset:1182*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:128 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 128, 0, x3, 1182*FLEN/8, x4, x1, x2)

inst_395:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x039 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x369 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3d2 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7839; op2val:0x3f69;
op3val:0x7bd2; valaddr_reg:x3; val_offset:1185*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 1185*FLEN/8, x4, x1, x2)

inst_396:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x039 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x369 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3d2 and fcsr == 0x20 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7839; op2val:0x3f69;
op3val:0x7bd2; valaddr_reg:x3; val_offset:1188*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:32 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 32, 0, x3, 1188*FLEN/8, x4, x1, x2)

inst_397:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x039 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x369 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3d2 and fcsr == 0x40 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7839; op2val:0x3f69;
op3val:0x7bd2; valaddr_reg:x3; val_offset:1191*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:64 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 64, 0, x3, 1191*FLEN/8, x4, x1, x2)

inst_398:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x039 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x369 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3d2 and fcsr == 0x60 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7839; op2val:0x3f69;
op3val:0x7bd2; valaddr_reg:x3; val_offset:1194*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 96, 0, x3, 1194*FLEN/8, x4, x1, x2)

inst_399:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x039 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x369 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3d2 and fcsr == 0x80 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7839; op2val:0x3f69;
op3val:0x7bd2; valaddr_reg:x3; val_offset:1197*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:128 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 128, 0, x3, 1197*FLEN/8, x4, x1, x2)

inst_400:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2e7 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x273 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x191 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7ae7; op2val:0x3a73;
op3val:0x7991; valaddr_reg:x3; val_offset:1200*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 1200*FLEN/8, x4, x1, x2)

inst_401:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2e7 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x273 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x191 and fcsr == 0x20 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7ae7; op2val:0x3a73;
op3val:0x7991; valaddr_reg:x3; val_offset:1203*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:32 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 32, 0, x3, 1203*FLEN/8, x4, x1, x2)

inst_402:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2e7 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x273 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x191 and fcsr == 0x40 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7ae7; op2val:0x3a73;
op3val:0x7991; valaddr_reg:x3; val_offset:1206*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:64 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 64, 0, x3, 1206*FLEN/8, x4, x1, x2)

inst_403:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2e7 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x273 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x191 and fcsr == 0x60 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7ae7; op2val:0x3a73;
op3val:0x7991; valaddr_reg:x3; val_offset:1209*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 96, 0, x3, 1209*FLEN/8, x4, x1, x2)

inst_404:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2e7 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x273 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x191 and fcsr == 0x80 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7ae7; op2val:0x3a73;
op3val:0x7991; valaddr_reg:x3; val_offset:1212*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:128 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 128, 0, x3, 1212*FLEN/8, x4, x1, x2)

inst_405:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x02d and fs2 == 0 and fe2 == 0x0f and fm2 == 0x19e and fs3 == 0 and fe3 == 0x1d and fm3 == 0x1dd and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x742d; op2val:0x3d9e;
op3val:0x75dd; valaddr_reg:x3; val_offset:1215*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 1215*FLEN/8, x4, x1, x2)

inst_406:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x02d and fs2 == 0 and fe2 == 0x0f and fm2 == 0x19e and fs3 == 0 and fe3 == 0x1d and fm3 == 0x1dd and fcsr == 0x20 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x742d; op2val:0x3d9e;
op3val:0x75dd; valaddr_reg:x3; val_offset:1218*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:32 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 32, 0, x3, 1218*FLEN/8, x4, x1, x2)

inst_407:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x02d and fs2 == 0 and fe2 == 0x0f and fm2 == 0x19e and fs3 == 0 and fe3 == 0x1d and fm3 == 0x1dd and fcsr == 0x40 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x742d; op2val:0x3d9e;
op3val:0x75dd; valaddr_reg:x3; val_offset:1221*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:64 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 64, 0, x3, 1221*FLEN/8, x4, x1, x2)

inst_408:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x02d and fs2 == 0 and fe2 == 0x0f and fm2 == 0x19e and fs3 == 0 and fe3 == 0x1d and fm3 == 0x1dd and fcsr == 0x60 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x742d; op2val:0x3d9e;
op3val:0x75dd; valaddr_reg:x3; val_offset:1224*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 96, 0, x3, 1224*FLEN/8, x4, x1, x2)

inst_409:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x02d and fs2 == 0 and fe2 == 0x0f and fm2 == 0x19e and fs3 == 0 and fe3 == 0x1d and fm3 == 0x1dd and fcsr == 0x80 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x742d; op2val:0x3d9e;
op3val:0x75dd; valaddr_reg:x3; val_offset:1227*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:128 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 128, 0, x3, 1227*FLEN/8, x4, x1, x2)

inst_410:
// fs1 == 0 and fe1 == 0x1c and fm1 == 0x157 and fs2 == 0 and fe2 == 0x11 and fm2 == 0x09e and fs3 == 0 and fe3 == 0x1e and fm3 == 0x22c and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7157; op2val:0x449e;
op3val:0x7a2c; valaddr_reg:x3; val_offset:1230*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 1230*FLEN/8, x4, x1, x2)

inst_411:
// fs1 == 0 and fe1 == 0x1c and fm1 == 0x157 and fs2 == 0 and fe2 == 0x11 and fm2 == 0x09e and fs3 == 0 and fe3 == 0x1e and fm3 == 0x22c and fcsr == 0x20 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7157; op2val:0x449e;
op3val:0x7a2c; valaddr_reg:x3; val_offset:1233*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:32 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 32, 0, x3, 1233*FLEN/8, x4, x1, x2)

inst_412:
// fs1 == 0 and fe1 == 0x1c and fm1 == 0x157 and fs2 == 0 and fe2 == 0x11 and fm2 == 0x09e and fs3 == 0 and fe3 == 0x1e and fm3 == 0x22c and fcsr == 0x40 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7157; op2val:0x449e;
op3val:0x7a2c; valaddr_reg:x3; val_offset:1236*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:64 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 64, 0, x3, 1236*FLEN/8, x4, x1, x2)

inst_413:
// fs1 == 0 and fe1 == 0x1c and fm1 == 0x157 and fs2 == 0 and fe2 == 0x11 and fm2 == 0x09e and fs3 == 0 and fe3 == 0x1e and fm3 == 0x22c and fcsr == 0x60 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7157; op2val:0x449e;
op3val:0x7a2c; valaddr_reg:x3; val_offset:1239*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 96, 0, x3, 1239*FLEN/8, x4, x1, x2)

inst_414:
// fs1 == 0 and fe1 == 0x1c and fm1 == 0x157 and fs2 == 0 and fe2 == 0x11 and fm2 == 0x09e and fs3 == 0 and fe3 == 0x1e and fm3 == 0x22c and fcsr == 0x80 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7157; op2val:0x449e;
op3val:0x7a2c; valaddr_reg:x3; val_offset:1242*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:128 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 128, 0, x3, 1242*FLEN/8, x4, x1, x2)

inst_415:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x042 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x1d9 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x23a and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7842; op2val:0x3dd9;
op3val:0x7a3a; valaddr_reg:x3; val_offset:1245*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 1245*FLEN/8, x4, x1, x2)

inst_416:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x042 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x1d9 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x23a and fcsr == 0x20 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7842; op2val:0x3dd9;
op3val:0x7a3a; valaddr_reg:x3; val_offset:1248*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:32 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 32, 0, x3, 1248*FLEN/8, x4, x1, x2)

inst_417:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x042 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x1d9 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x23a and fcsr == 0x40 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7842; op2val:0x3dd9;
op3val:0x7a3a; valaddr_reg:x3; val_offset:1251*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:64 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 64, 0, x3, 1251*FLEN/8, x4, x1, x2)

inst_418:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x042 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x1d9 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x23a and fcsr == 0x60 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7842; op2val:0x3dd9;
op3val:0x7a3a; valaddr_reg:x3; val_offset:1254*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 96, 0, x3, 1254*FLEN/8, x4, x1, x2)

inst_419:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x042 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x1d9 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x23a and fcsr == 0x80 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7842; op2val:0x3dd9;
op3val:0x7a3a; valaddr_reg:x3; val_offset:1257*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:128 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 128, 0, x3, 1257*FLEN/8, x4, x1, x2)

inst_420:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x145 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x169 and fs3 == 0 and fe3 == 0x1c and fm3 == 0x322 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7545; op2val:0x3969;
op3val:0x7322; valaddr_reg:x3; val_offset:1260*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 1260*FLEN/8, x4, x1, x2)

inst_421:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x145 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x169 and fs3 == 0 and fe3 == 0x1c and fm3 == 0x322 and fcsr == 0x20 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7545; op2val:0x3969;
op3val:0x7322; valaddr_reg:x3; val_offset:1263*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:32 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 32, 0, x3, 1263*FLEN/8, x4, x1, x2)

inst_422:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x145 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x169 and fs3 == 0 and fe3 == 0x1c and fm3 == 0x322 and fcsr == 0x40 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7545; op2val:0x3969;
op3val:0x7322; valaddr_reg:x3; val_offset:1266*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:64 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 64, 0, x3, 1266*FLEN/8, x4, x1, x2)

inst_423:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x145 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x169 and fs3 == 0 and fe3 == 0x1c and fm3 == 0x322 and fcsr == 0x60 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7545; op2val:0x3969;
op3val:0x7322; valaddr_reg:x3; val_offset:1269*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 96, 0, x3, 1269*FLEN/8, x4, x1, x2)

inst_424:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x145 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x169 and fs3 == 0 and fe3 == 0x1c and fm3 == 0x322 and fcsr == 0x80 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7545; op2val:0x3969;
op3val:0x7322; valaddr_reg:x3; val_offset:1272*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:128 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 128, 0, x3, 1272*FLEN/8, x4, x1, x2)

inst_425:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x27d and fs2 == 0 and fe2 == 0x0f and fm2 == 0x0da and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3e0 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7a7d; op2val:0x3cda;
op3val:0x7be0; valaddr_reg:x3; val_offset:1275*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 1275*FLEN/8, x4, x1, x2)

inst_426:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x27d and fs2 == 0 and fe2 == 0x0f and fm2 == 0x0da and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3e0 and fcsr == 0x20 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7a7d; op2val:0x3cda;
op3val:0x7be0; valaddr_reg:x3; val_offset:1278*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:32 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 32, 0, x3, 1278*FLEN/8, x4, x1, x2)

inst_427:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x27d and fs2 == 0 and fe2 == 0x0f and fm2 == 0x0da and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3e0 and fcsr == 0x40 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7a7d; op2val:0x3cda;
op3val:0x7be0; valaddr_reg:x3; val_offset:1281*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:64 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 64, 0, x3, 1281*FLEN/8, x4, x1, x2)

inst_428:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x27d and fs2 == 0 and fe2 == 0x0f and fm2 == 0x0da and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3e0 and fcsr == 0x60 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7a7d; op2val:0x3cda;
op3val:0x7be0; valaddr_reg:x3; val_offset:1284*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 96, 0, x3, 1284*FLEN/8, x4, x1, x2)

inst_429:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x27d and fs2 == 0 and fe2 == 0x0f and fm2 == 0x0da and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3e0 and fcsr == 0x80 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7a7d; op2val:0x3cda;
op3val:0x7be0; valaddr_reg:x3; val_offset:1287*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:128 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 128, 0, x3, 1287*FLEN/8, x4, x1, x2)

inst_430:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2d1 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x390 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x272 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7ad1; op2val:0x3b90;
op3val:0x7a72; valaddr_reg:x3; val_offset:1290*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 1290*FLEN/8, x4, x1, x2)

inst_431:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2d1 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x390 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x272 and fcsr == 0x20 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7ad1; op2val:0x3b90;
op3val:0x7a72; valaddr_reg:x3; val_offset:1293*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:32 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 32, 0, x3, 1293*FLEN/8, x4, x1, x2)

inst_432:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2d1 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x390 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x272 and fcsr == 0x40 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7ad1; op2val:0x3b90;
op3val:0x7a72; valaddr_reg:x3; val_offset:1296*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:64 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 64, 0, x3, 1296*FLEN/8, x4, x1, x2)

inst_433:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2d1 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x390 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x272 and fcsr == 0x60 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7ad1; op2val:0x3b90;
op3val:0x7a72; valaddr_reg:x3; val_offset:1299*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 96, 0, x3, 1299*FLEN/8, x4, x1, x2)

inst_434:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2d1 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x390 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x272 and fcsr == 0x80 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7ad1; op2val:0x3b90;
op3val:0x7a72; valaddr_reg:x3; val_offset:1302*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:128 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 128, 0, x3, 1302*FLEN/8, x4, x1, x2)

inst_435:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x28b and fs2 == 0 and fe2 == 0x0e and fm2 == 0x33b and fs3 == 0 and fe3 == 0x1e and fm3 == 0x1ea and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7a8b; op2val:0x3b3b;
op3val:0x79ea; valaddr_reg:x3; val_offset:1305*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 1305*FLEN/8, x4, x1, x2)

inst_436:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x28b and fs2 == 0 and fe2 == 0x0e and fm2 == 0x33b and fs3 == 0 and fe3 == 0x1e and fm3 == 0x1ea and fcsr == 0x20 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7a8b; op2val:0x3b3b;
op3val:0x79ea; valaddr_reg:x3; val_offset:1308*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:32 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 32, 0, x3, 1308*FLEN/8, x4, x1, x2)

inst_437:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x28b and fs2 == 0 and fe2 == 0x0e and fm2 == 0x33b and fs3 == 0 and fe3 == 0x1e and fm3 == 0x1ea and fcsr == 0x40 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7a8b; op2val:0x3b3b;
op3val:0x79ea; valaddr_reg:x3; val_offset:1311*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:64 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 64, 0, x3, 1311*FLEN/8, x4, x1, x2)

inst_438:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x28b and fs2 == 0 and fe2 == 0x0e and fm2 == 0x33b and fs3 == 0 and fe3 == 0x1e and fm3 == 0x1ea and fcsr == 0x60 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7a8b; op2val:0x3b3b;
op3val:0x79ea; valaddr_reg:x3; val_offset:1314*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 96, 0, x3, 1314*FLEN/8, x4, x1, x2)

inst_439:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x28b and fs2 == 0 and fe2 == 0x0e and fm2 == 0x33b and fs3 == 0 and fe3 == 0x1e and fm3 == 0x1ea and fcsr == 0x80 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7a8b; op2val:0x3b3b;
op3val:0x79ea; valaddr_reg:x3; val_offset:1317*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:128 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 128, 0, x3, 1317*FLEN/8, x4, x1, x2)

inst_440:
// fs1 == 0 and fe1 == 0x1c and fm1 == 0x340 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x090 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x023 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7340; op2val:0x4090;
op3val:0x7823; valaddr_reg:x3; val_offset:1320*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 1320*FLEN/8, x4, x1, x2)

inst_441:
// fs1 == 0 and fe1 == 0x1c and fm1 == 0x340 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x090 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x023 and fcsr == 0x20 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7340; op2val:0x4090;
op3val:0x7823; valaddr_reg:x3; val_offset:1323*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:32 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 32, 0, x3, 1323*FLEN/8, x4, x1, x2)

inst_442:
// fs1 == 0 and fe1 == 0x1c and fm1 == 0x340 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x090 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x023 and fcsr == 0x40 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7340; op2val:0x4090;
op3val:0x7823; valaddr_reg:x3; val_offset:1326*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:64 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 64, 0, x3, 1326*FLEN/8, x4, x1, x2)

inst_443:
// fs1 == 0 and fe1 == 0x1c and fm1 == 0x340 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x090 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x023 and fcsr == 0x60 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7340; op2val:0x4090;
op3val:0x7823; valaddr_reg:x3; val_offset:1329*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 96, 0, x3, 1329*FLEN/8, x4, x1, x2)

inst_444:
// fs1 == 0 and fe1 == 0x1c and fm1 == 0x340 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x090 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x023 and fcsr == 0x80 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7340; op2val:0x4090;
op3val:0x7823; valaddr_reg:x3; val_offset:1332*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:128 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 128, 0, x3, 1332*FLEN/8, x4, x1, x2)

inst_445:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x1af and fs2 == 0 and fe2 == 0x0b and fm2 == 0x138 and fs3 == 0 and fe3 == 0x19 and fm3 == 0x36b and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x75af; op2val:0x2d38;
op3val:0x676b; valaddr_reg:x3; val_offset:1335*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 1335*FLEN/8, x4, x1, x2)

inst_446:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x1af and fs2 == 0 and fe2 == 0x0b and fm2 == 0x138 and fs3 == 0 and fe3 == 0x19 and fm3 == 0x36b and fcsr == 0x20 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x75af; op2val:0x2d38;
op3val:0x676b; valaddr_reg:x3; val_offset:1338*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:32 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 32, 0, x3, 1338*FLEN/8, x4, x1, x2)

inst_447:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x1af and fs2 == 0 and fe2 == 0x0b and fm2 == 0x138 and fs3 == 0 and fe3 == 0x19 and fm3 == 0x36b and fcsr == 0x40 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x75af; op2val:0x2d38;
op3val:0x676b; valaddr_reg:x3; val_offset:1341*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:64 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 64, 0, x3, 1341*FLEN/8, x4, x1, x2)

inst_448:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x1af and fs2 == 0 and fe2 == 0x0b and fm2 == 0x138 and fs3 == 0 and fe3 == 0x19 and fm3 == 0x36b and fcsr == 0x60 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x75af; op2val:0x2d38;
op3val:0x676b; valaddr_reg:x3; val_offset:1344*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 96, 0, x3, 1344*FLEN/8, x4, x1, x2)

inst_449:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x1af and fs2 == 0 and fe2 == 0x0b and fm2 == 0x138 and fs3 == 0 and fe3 == 0x19 and fm3 == 0x36b and fcsr == 0x80 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x75af; op2val:0x2d38;
op3val:0x676b; valaddr_reg:x3; val_offset:1347*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:128 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 128, 0, x3, 1347*FLEN/8, x4, x1, x2)

inst_450:
// fs1 == 0 and fe1 == 0x19 and fm1 == 0x326 and fs2 == 0 and fe2 == 0x12 and fm2 == 0x0ff and fs3 == 0 and fe3 == 0x1d and fm3 == 0x077 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x6726; op2val:0x48ff;
op3val:0x7477; valaddr_reg:x3; val_offset:1350*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 1350*FLEN/8, x4, x1, x2)

inst_451:
// fs1 == 0 and fe1 == 0x19 and fm1 == 0x326 and fs2 == 0 and fe2 == 0x12 and fm2 == 0x0ff and fs3 == 0 and fe3 == 0x1d and fm3 == 0x077 and fcsr == 0x20 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x6726; op2val:0x48ff;
op3val:0x7477; valaddr_reg:x3; val_offset:1353*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:32 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 32, 0, x3, 1353*FLEN/8, x4, x1, x2)

inst_452:
// fs1 == 0 and fe1 == 0x19 and fm1 == 0x326 and fs2 == 0 and fe2 == 0x12 and fm2 == 0x0ff and fs3 == 0 and fe3 == 0x1d and fm3 == 0x077 and fcsr == 0x40 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x6726; op2val:0x48ff;
op3val:0x7477; valaddr_reg:x3; val_offset:1356*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:64 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 64, 0, x3, 1356*FLEN/8, x4, x1, x2)

inst_453:
// fs1 == 0 and fe1 == 0x19 and fm1 == 0x326 and fs2 == 0 and fe2 == 0x12 and fm2 == 0x0ff and fs3 == 0 and fe3 == 0x1d and fm3 == 0x077 and fcsr == 0x60 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x6726; op2val:0x48ff;
op3val:0x7477; valaddr_reg:x3; val_offset:1359*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 96, 0, x3, 1359*FLEN/8, x4, x1, x2)

inst_454:
// fs1 == 0 and fe1 == 0x19 and fm1 == 0x326 and fs2 == 0 and fe2 == 0x12 and fm2 == 0x0ff and fs3 == 0 and fe3 == 0x1d and fm3 == 0x077 and fcsr == 0x80 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x6726; op2val:0x48ff;
op3val:0x7477; valaddr_reg:x3; val_offset:1362*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:128 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 128, 0, x3, 1362*FLEN/8, x4, x1, x2)

inst_455:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x025 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x158 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x189 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7425; op2val:0x4158;
op3val:0x7989; valaddr_reg:x3; val_offset:1365*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 1365*FLEN/8, x4, x1, x2)

inst_456:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x025 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x158 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x189 and fcsr == 0x20 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7425; op2val:0x4158;
op3val:0x7989; valaddr_reg:x3; val_offset:1368*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:32 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 32, 0, x3, 1368*FLEN/8, x4, x1, x2)

inst_457:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x025 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x158 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x189 and fcsr == 0x40 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7425; op2val:0x4158;
op3val:0x7989; valaddr_reg:x3; val_offset:1371*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:64 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 64, 0, x3, 1371*FLEN/8, x4, x1, x2)

inst_458:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x025 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x158 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x189 and fcsr == 0x60 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7425; op2val:0x4158;
op3val:0x7989; valaddr_reg:x3; val_offset:1374*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 96, 0, x3, 1374*FLEN/8, x4, x1, x2)

inst_459:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x025 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x158 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x189 and fcsr == 0x80 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7425; op2val:0x4158;
op3val:0x7989; valaddr_reg:x3; val_offset:1377*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:128 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 128, 0, x3, 1377*FLEN/8, x4, x1, x2)

inst_460:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3a5 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x37b and fs3 == 0 and fe3 == 0x1d and fm3 == 0x326 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7ba5; op2val:0x377b;
op3val:0x7726; valaddr_reg:x3; val_offset:1380*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 1380*FLEN/8, x4, x1, x2)

inst_461:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3a5 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x37b and fs3 == 0 and fe3 == 0x1d and fm3 == 0x326 and fcsr == 0x20 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7ba5; op2val:0x377b;
op3val:0x7726; valaddr_reg:x3; val_offset:1383*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:32 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 32, 0, x3, 1383*FLEN/8, x4, x1, x2)

inst_462:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3a5 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x37b and fs3 == 0 and fe3 == 0x1d and fm3 == 0x326 and fcsr == 0x40 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7ba5; op2val:0x377b;
op3val:0x7726; valaddr_reg:x3; val_offset:1386*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:64 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 64, 0, x3, 1386*FLEN/8, x4, x1, x2)

inst_463:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3a5 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x37b and fs3 == 0 and fe3 == 0x1d and fm3 == 0x326 and fcsr == 0x60 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7ba5; op2val:0x377b;
op3val:0x7726; valaddr_reg:x3; val_offset:1389*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 96, 0, x3, 1389*FLEN/8, x4, x1, x2)

inst_464:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3a5 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x37b and fs3 == 0 and fe3 == 0x1d and fm3 == 0x326 and fcsr == 0x80 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7ba5; op2val:0x377b;
op3val:0x7726; valaddr_reg:x3; val_offset:1392*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:128 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 128, 0, x3, 1392*FLEN/8, x4, x1, x2)

inst_465:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x37e and fs2 == 0 and fe2 == 0x0f and fm2 == 0x037 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3e6 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7b7e; op2val:0x3c37;
op3val:0x7be6; valaddr_reg:x3; val_offset:1395*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 1395*FLEN/8, x4, x1, x2)

inst_466:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x37e and fs2 == 0 and fe2 == 0x0f and fm2 == 0x037 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3e6 and fcsr == 0x20 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7b7e; op2val:0x3c37;
op3val:0x7be6; valaddr_reg:x3; val_offset:1398*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:32 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 32, 0, x3, 1398*FLEN/8, x4, x1, x2)

inst_467:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x37e and fs2 == 0 and fe2 == 0x0f and fm2 == 0x037 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3e6 and fcsr == 0x40 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7b7e; op2val:0x3c37;
op3val:0x7be6; valaddr_reg:x3; val_offset:1401*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:64 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 64, 0, x3, 1401*FLEN/8, x4, x1, x2)

inst_468:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x37e and fs2 == 0 and fe2 == 0x0f and fm2 == 0x037 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3e6 and fcsr == 0x60 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7b7e; op2val:0x3c37;
op3val:0x7be6; valaddr_reg:x3; val_offset:1404*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 96, 0, x3, 1404*FLEN/8, x4, x1, x2)

inst_469:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x37e and fs2 == 0 and fe2 == 0x0f and fm2 == 0x037 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3e6 and fcsr == 0x80 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7b7e; op2val:0x3c37;
op3val:0x7be6; valaddr_reg:x3; val_offset:1407*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:128 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 128, 0, x3, 1407*FLEN/8, x4, x1, x2)

inst_470:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3a2 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x21b and fs3 == 0 and fe3 == 0x1d and fm3 == 0x1d4 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7ba2; op2val:0x361b;
op3val:0x75d4; valaddr_reg:x3; val_offset:1410*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 1410*FLEN/8, x4, x1, x2)

inst_471:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3a2 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x21b and fs3 == 0 and fe3 == 0x1d and fm3 == 0x1d4 and fcsr == 0x20 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7ba2; op2val:0x361b;
op3val:0x75d4; valaddr_reg:x3; val_offset:1413*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:32 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 32, 0, x3, 1413*FLEN/8, x4, x1, x2)

inst_472:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3a2 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x21b and fs3 == 0 and fe3 == 0x1d and fm3 == 0x1d4 and fcsr == 0x40 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7ba2; op2val:0x361b;
op3val:0x75d4; valaddr_reg:x3; val_offset:1416*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:64 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 64, 0, x3, 1416*FLEN/8, x4, x1, x2)

inst_473:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3a2 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x21b and fs3 == 0 and fe3 == 0x1d and fm3 == 0x1d4 and fcsr == 0x60 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7ba2; op2val:0x361b;
op3val:0x75d4; valaddr_reg:x3; val_offset:1419*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 96, 0, x3, 1419*FLEN/8, x4, x1, x2)

inst_474:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3a2 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x21b and fs3 == 0 and fe3 == 0x1d and fm3 == 0x1d4 and fcsr == 0x80 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7ba2; op2val:0x361b;
op3val:0x75d4; valaddr_reg:x3; val_offset:1422*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:128 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 128, 0, x3, 1422*FLEN/8, x4, x1, x2)

inst_475:
// fs1 == 0 and fe1 == 0x1c and fm1 == 0x30d and fs2 == 0 and fe2 == 0x0f and fm2 == 0x01d and fs3 == 0 and fe3 == 0x1c and fm3 == 0x341 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x730d; op2val:0x3c1d;
op3val:0x7341; valaddr_reg:x3; val_offset:1425*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 1425*FLEN/8, x4, x1, x2)

inst_476:
// fs1 == 0 and fe1 == 0x1c and fm1 == 0x30d and fs2 == 0 and fe2 == 0x0f and fm2 == 0x01d and fs3 == 0 and fe3 == 0x1c and fm3 == 0x341 and fcsr == 0x20 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x730d; op2val:0x3c1d;
op3val:0x7341; valaddr_reg:x3; val_offset:1428*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:32 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 32, 0, x3, 1428*FLEN/8, x4, x1, x2)

inst_477:
// fs1 == 0 and fe1 == 0x1c and fm1 == 0x30d and fs2 == 0 and fe2 == 0x0f and fm2 == 0x01d and fs3 == 0 and fe3 == 0x1c and fm3 == 0x341 and fcsr == 0x40 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x730d; op2val:0x3c1d;
op3val:0x7341; valaddr_reg:x3; val_offset:1431*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:64 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 64, 0, x3, 1431*FLEN/8, x4, x1, x2)

inst_478:
// fs1 == 0 and fe1 == 0x1c and fm1 == 0x30d and fs2 == 0 and fe2 == 0x0f and fm2 == 0x01d and fs3 == 0 and fe3 == 0x1c and fm3 == 0x341 and fcsr == 0x60 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x730d; op2val:0x3c1d;
op3val:0x7341; valaddr_reg:x3; val_offset:1434*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 96, 0, x3, 1434*FLEN/8, x4, x1, x2)

inst_479:
// fs1 == 0 and fe1 == 0x1c and fm1 == 0x30d and fs2 == 0 and fe2 == 0x0f and fm2 == 0x01d and fs3 == 0 and fe3 == 0x1c and fm3 == 0x341 and fcsr == 0x80 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x730d; op2val:0x3c1d;
op3val:0x7341; valaddr_reg:x3; val_offset:1437*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:128 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 128, 0, x3, 1437*FLEN/8, x4, x1, x2)

inst_480:
// fs1 == 0 and fe1 == 0x1c and fm1 == 0x24a and fs2 == 0 and fe2 == 0x0f and fm2 == 0x027 and fs3 == 0 and fe3 == 0x1c and fm3 == 0x289 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x724a; op2val:0x3c27;
op3val:0x7289; valaddr_reg:x3; val_offset:1440*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 1440*FLEN/8, x4, x1, x2)

inst_481:
// fs1 == 0 and fe1 == 0x1c and fm1 == 0x24a and fs2 == 0 and fe2 == 0x0f and fm2 == 0x027 and fs3 == 0 and fe3 == 0x1c and fm3 == 0x289 and fcsr == 0x20 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x724a; op2val:0x3c27;
op3val:0x7289; valaddr_reg:x3; val_offset:1443*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:32 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 32, 0, x3, 1443*FLEN/8, x4, x1, x2)

inst_482:
// fs1 == 0 and fe1 == 0x1c and fm1 == 0x24a and fs2 == 0 and fe2 == 0x0f and fm2 == 0x027 and fs3 == 0 and fe3 == 0x1c and fm3 == 0x289 and fcsr == 0x40 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x724a; op2val:0x3c27;
op3val:0x7289; valaddr_reg:x3; val_offset:1446*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:64 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 64, 0, x3, 1446*FLEN/8, x4, x1, x2)

inst_483:
// fs1 == 0 and fe1 == 0x1c and fm1 == 0x24a and fs2 == 0 and fe2 == 0x0f and fm2 == 0x027 and fs3 == 0 and fe3 == 0x1c and fm3 == 0x289 and fcsr == 0x60 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x724a; op2val:0x3c27;
op3val:0x7289; valaddr_reg:x3; val_offset:1449*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 96, 0, x3, 1449*FLEN/8, x4, x1, x2)

inst_484:
// fs1 == 0 and fe1 == 0x1c and fm1 == 0x24a and fs2 == 0 and fe2 == 0x0f and fm2 == 0x027 and fs3 == 0 and fe3 == 0x1c and fm3 == 0x289 and fcsr == 0x80 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x724a; op2val:0x3c27;
op3val:0x7289; valaddr_reg:x3; val_offset:1452*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:128 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 128, 0, x3, 1452*FLEN/8, x4, x1, x2)

inst_485:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0fd and fs2 == 0 and fe2 == 0x0f and fm2 == 0x1c5 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x332 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x78fd; op2val:0x3dc5;
op3val:0x7b32; valaddr_reg:x3; val_offset:1455*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 1455*FLEN/8, x4, x1, x2)

inst_486:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0fd and fs2 == 0 and fe2 == 0x0f and fm2 == 0x1c5 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x332 and fcsr == 0x20 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x78fd; op2val:0x3dc5;
op3val:0x7b32; valaddr_reg:x3; val_offset:1458*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:32 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 32, 0, x3, 1458*FLEN/8, x4, x1, x2)

inst_487:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0fd and fs2 == 0 and fe2 == 0x0f and fm2 == 0x1c5 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x332 and fcsr == 0x40 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x78fd; op2val:0x3dc5;
op3val:0x7b32; valaddr_reg:x3; val_offset:1461*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:64 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 64, 0, x3, 1461*FLEN/8, x4, x1, x2)

inst_488:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0fd and fs2 == 0 and fe2 == 0x0f and fm2 == 0x1c5 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x332 and fcsr == 0x60 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x78fd; op2val:0x3dc5;
op3val:0x7b32; valaddr_reg:x3; val_offset:1464*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 96, 0, x3, 1464*FLEN/8, x4, x1, x2)

inst_489:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0fd and fs2 == 0 and fe2 == 0x0f and fm2 == 0x1c5 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x332 and fcsr == 0x80 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x78fd; op2val:0x3dc5;
op3val:0x7b32; valaddr_reg:x3; val_offset:1467*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:128 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 128, 0, x3, 1467*FLEN/8, x4, x1, x2)

inst_490:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2b8 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x090 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x3aa and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7ab8; op2val:0x3890;
op3val:0x77aa; valaddr_reg:x3; val_offset:1470*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 1470*FLEN/8, x4, x1, x2)

inst_491:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2b8 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x090 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x3aa and fcsr == 0x20 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7ab8; op2val:0x3890;
op3val:0x77aa; valaddr_reg:x3; val_offset:1473*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:32 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 32, 0, x3, 1473*FLEN/8, x4, x1, x2)

inst_492:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2b8 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x090 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x3aa and fcsr == 0x40 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7ab8; op2val:0x3890;
op3val:0x77aa; valaddr_reg:x3; val_offset:1476*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:64 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 64, 0, x3, 1476*FLEN/8, x4, x1, x2)

inst_493:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2b8 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x090 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x3aa and fcsr == 0x60 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7ab8; op2val:0x3890;
op3val:0x77aa; valaddr_reg:x3; val_offset:1479*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 96, 0, x3, 1479*FLEN/8, x4, x1, x2)

inst_494:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2b8 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x090 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x3aa and fcsr == 0x80 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7ab8; op2val:0x3890;
op3val:0x77aa; valaddr_reg:x3; val_offset:1482*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:128 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 128, 0, x3, 1482*FLEN/8, x4, x1, x2)

inst_495:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x138 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x0e5 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x264 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7938; op2val:0x3ce5;
op3val:0x7a64; valaddr_reg:x3; val_offset:1485*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 1485*FLEN/8, x4, x1, x2)

inst_496:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x138 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x0e5 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x264 and fcsr == 0x20 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7938; op2val:0x3ce5;
op3val:0x7a64; valaddr_reg:x3; val_offset:1488*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:32 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 32, 0, x3, 1488*FLEN/8, x4, x1, x2)

inst_497:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x138 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x0e5 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x264 and fcsr == 0x40 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7938; op2val:0x3ce5;
op3val:0x7a64; valaddr_reg:x3; val_offset:1491*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:64 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 64, 0, x3, 1491*FLEN/8, x4, x1, x2)

inst_498:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x138 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x0e5 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x264 and fcsr == 0x60 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7938; op2val:0x3ce5;
op3val:0x7a64; valaddr_reg:x3; val_offset:1494*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 96, 0, x3, 1494*FLEN/8, x4, x1, x2)

inst_499:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x138 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x0e5 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x264 and fcsr == 0x80 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7938; op2val:0x3ce5;
op3val:0x7a64; valaddr_reg:x3; val_offset:1497*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:128 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 128, 0, x3, 1497*FLEN/8, x4, x1, x2)

inst_500:
// fs1 == 0 and fe1 == 0x1b and fm1 == 0x16c and fs2 == 0 and fe2 == 0x11 and fm2 == 0x3ca and fs3 == 0 and fe3 == 0x1e and fm3 == 0x148 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x6d6c; op2val:0x47ca;
op3val:0x7948; valaddr_reg:x3; val_offset:1500*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 1500*FLEN/8, x4, x1, x2)

inst_501:
// fs1 == 0 and fe1 == 0x1b and fm1 == 0x16c and fs2 == 0 and fe2 == 0x11 and fm2 == 0x3ca and fs3 == 0 and fe3 == 0x1e and fm3 == 0x148 and fcsr == 0x20 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x6d6c; op2val:0x47ca;
op3val:0x7948; valaddr_reg:x3; val_offset:1503*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:32 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 32, 0, x3, 1503*FLEN/8, x4, x1, x2)

inst_502:
// fs1 == 0 and fe1 == 0x1b and fm1 == 0x16c and fs2 == 0 and fe2 == 0x11 and fm2 == 0x3ca and fs3 == 0 and fe3 == 0x1e and fm3 == 0x148 and fcsr == 0x40 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x6d6c; op2val:0x47ca;
op3val:0x7948; valaddr_reg:x3; val_offset:1506*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:64 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 64, 0, x3, 1506*FLEN/8, x4, x1, x2)

inst_503:
// fs1 == 0 and fe1 == 0x1b and fm1 == 0x16c and fs2 == 0 and fe2 == 0x11 and fm2 == 0x3ca and fs3 == 0 and fe3 == 0x1e and fm3 == 0x148 and fcsr == 0x60 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x6d6c; op2val:0x47ca;
op3val:0x7948; valaddr_reg:x3; val_offset:1509*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 96, 0, x3, 1509*FLEN/8, x4, x1, x2)

inst_504:
// fs1 == 0 and fe1 == 0x1b and fm1 == 0x16c and fs2 == 0 and fe2 == 0x11 and fm2 == 0x3ca and fs3 == 0 and fe3 == 0x1e and fm3 == 0x148 and fcsr == 0x80 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x6d6c; op2val:0x47ca;
op3val:0x7948; valaddr_reg:x3; val_offset:1512*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:128 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 128, 0, x3, 1512*FLEN/8, x4, x1, x2)

inst_505:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x346 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x2e1 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x241 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7b46; op2val:0x3ae1;
op3val:0x7a41; valaddr_reg:x3; val_offset:1515*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 1515*FLEN/8, x4, x1, x2)

inst_506:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x346 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x2e1 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x241 and fcsr == 0x20 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7b46; op2val:0x3ae1;
op3val:0x7a41; valaddr_reg:x3; val_offset:1518*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:32 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 32, 0, x3, 1518*FLEN/8, x4, x1, x2)

inst_507:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x346 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x2e1 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x241 and fcsr == 0x40 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7b46; op2val:0x3ae1;
op3val:0x7a41; valaddr_reg:x3; val_offset:1521*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:64 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 64, 0, x3, 1521*FLEN/8, x4, x1, x2)

inst_508:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x346 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x2e1 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x241 and fcsr == 0x60 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7b46; op2val:0x3ae1;
op3val:0x7a41; valaddr_reg:x3; val_offset:1524*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 96, 0, x3, 1524*FLEN/8, x4, x1, x2)

inst_509:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x346 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x2e1 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x241 and fcsr == 0x80 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7b46; op2val:0x3ae1;
op3val:0x7a41; valaddr_reg:x3; val_offset:1527*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:128 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 128, 0, x3, 1527*FLEN/8, x4, x1, x2)

inst_510:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1ff and fs2 == 0 and fe2 == 0x0e and fm2 == 0x119 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x3a5 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x79ff; op2val:0x3919;
op3val:0x77a5; valaddr_reg:x3; val_offset:1530*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 1530*FLEN/8, x4, x1, x2)

inst_511:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1ff and fs2 == 0 and fe2 == 0x0e and fm2 == 0x119 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x3a5 and fcsr == 0x20 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x79ff; op2val:0x3919;
op3val:0x77a5; valaddr_reg:x3; val_offset:1533*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:32 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 32, 0, x3, 1533*FLEN/8, x4, x1, x2)
RVTEST_SIGBASE(x1,signature_x1_5)

inst_512:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1ff and fs2 == 0 and fe2 == 0x0e and fm2 == 0x119 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x3a5 and fcsr == 0x40 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x79ff; op2val:0x3919;
op3val:0x77a5; valaddr_reg:x3; val_offset:1536*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:64 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 64, 0, x3, 1536*FLEN/8, x4, x1, x2)

inst_513:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1ff and fs2 == 0 and fe2 == 0x0e and fm2 == 0x119 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x3a5 and fcsr == 0x60 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x79ff; op2val:0x3919;
op3val:0x77a5; valaddr_reg:x3; val_offset:1539*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 96, 0, x3, 1539*FLEN/8, x4, x1, x2)

inst_514:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1ff and fs2 == 0 and fe2 == 0x0e and fm2 == 0x119 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x3a5 and fcsr == 0x80 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x79ff; op2val:0x3919;
op3val:0x77a5; valaddr_reg:x3; val_offset:1542*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:128 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 128, 0, x3, 1542*FLEN/8, x4, x1, x2)

inst_515:
// fs1 == 0 and fe1 == 0x1c and fm1 == 0x1b5 and fs2 == 0 and fe2 == 0x11 and fm2 == 0x06b and fs3 == 0 and fe3 == 0x1e and fm3 == 0x24f and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x71b5; op2val:0x446b;
op3val:0x7a4f; valaddr_reg:x3; val_offset:1545*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 1545*FLEN/8, x4, x1, x2)

inst_516:
// fs1 == 0 and fe1 == 0x1c and fm1 == 0x1b5 and fs2 == 0 and fe2 == 0x11 and fm2 == 0x06b and fs3 == 0 and fe3 == 0x1e and fm3 == 0x24f and fcsr == 0x20 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x71b5; op2val:0x446b;
op3val:0x7a4f; valaddr_reg:x3; val_offset:1548*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:32 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 32, 0, x3, 1548*FLEN/8, x4, x1, x2)

inst_517:
// fs1 == 0 and fe1 == 0x1c and fm1 == 0x1b5 and fs2 == 0 and fe2 == 0x11 and fm2 == 0x06b and fs3 == 0 and fe3 == 0x1e and fm3 == 0x24f and fcsr == 0x40 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x71b5; op2val:0x446b;
op3val:0x7a4f; valaddr_reg:x3; val_offset:1551*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:64 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 64, 0, x3, 1551*FLEN/8, x4, x1, x2)

inst_518:
// fs1 == 0 and fe1 == 0x1c and fm1 == 0x1b5 and fs2 == 0 and fe2 == 0x11 and fm2 == 0x06b and fs3 == 0 and fe3 == 0x1e and fm3 == 0x24f and fcsr == 0x60 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x71b5; op2val:0x446b;
op3val:0x7a4f; valaddr_reg:x3; val_offset:1554*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 96, 0, x3, 1554*FLEN/8, x4, x1, x2)

inst_519:
// fs1 == 0 and fe1 == 0x1c and fm1 == 0x1b5 and fs2 == 0 and fe2 == 0x11 and fm2 == 0x06b and fs3 == 0 and fe3 == 0x1e and fm3 == 0x24f and fcsr == 0x80 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x71b5; op2val:0x446b;
op3val:0x7a4f; valaddr_reg:x3; val_offset:1557*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:128 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 128, 0, x3, 1557*FLEN/8, x4, x1, x2)

inst_520:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x151 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x0d1 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x267 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7551; op2val:0x40d1;
op3val:0x7a67; valaddr_reg:x3; val_offset:1560*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 1560*FLEN/8, x4, x1, x2)

inst_521:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x151 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x0d1 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x267 and fcsr == 0x20 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7551; op2val:0x40d1;
op3val:0x7a67; valaddr_reg:x3; val_offset:1563*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:32 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 32, 0, x3, 1563*FLEN/8, x4, x1, x2)

inst_522:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x151 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x0d1 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x267 and fcsr == 0x40 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7551; op2val:0x40d1;
op3val:0x7a67; valaddr_reg:x3; val_offset:1566*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:64 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 64, 0, x3, 1566*FLEN/8, x4, x1, x2)

inst_523:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x151 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x0d1 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x267 and fcsr == 0x60 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7551; op2val:0x40d1;
op3val:0x7a67; valaddr_reg:x3; val_offset:1569*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 96, 0, x3, 1569*FLEN/8, x4, x1, x2)

inst_524:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x151 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x0d1 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x267 and fcsr == 0x80 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7551; op2val:0x40d1;
op3val:0x7a67; valaddr_reg:x3; val_offset:1572*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:128 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 128, 0, x3, 1572*FLEN/8, x4, x1, x2)

inst_525:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3c4 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x284 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x254 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7bc4; op2val:0x3684;
op3val:0x7654; valaddr_reg:x3; val_offset:1575*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 1575*FLEN/8, x4, x1, x2)

inst_526:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3c4 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x284 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x254 and fcsr == 0x20 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7bc4; op2val:0x3684;
op3val:0x7654; valaddr_reg:x3; val_offset:1578*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:32 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 32, 0, x3, 1578*FLEN/8, x4, x1, x2)

inst_527:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3c4 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x284 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x254 and fcsr == 0x40 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7bc4; op2val:0x3684;
op3val:0x7654; valaddr_reg:x3; val_offset:1581*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:64 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 64, 0, x3, 1581*FLEN/8, x4, x1, x2)

inst_528:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3c4 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x284 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x254 and fcsr == 0x60 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7bc4; op2val:0x3684;
op3val:0x7654; valaddr_reg:x3; val_offset:1584*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 96, 0, x3, 1584*FLEN/8, x4, x1, x2)

inst_529:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3c4 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x284 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x254 and fcsr == 0x80 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7bc4; op2val:0x3684;
op3val:0x7654; valaddr_reg:x3; val_offset:1587*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:128 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 128, 0, x3, 1587*FLEN/8, x4, x1, x2)

inst_530:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x26b and fs2 == 0 and fe2 == 0x10 and fm2 == 0x0b7 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x392 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x766b; op2val:0x40b7;
op3val:0x7b92; valaddr_reg:x3; val_offset:1590*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 1590*FLEN/8, x4, x1, x2)

inst_531:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x26b and fs2 == 0 and fe2 == 0x10 and fm2 == 0x0b7 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x392 and fcsr == 0x20 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x766b; op2val:0x40b7;
op3val:0x7b92; valaddr_reg:x3; val_offset:1593*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:32 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 32, 0, x3, 1593*FLEN/8, x4, x1, x2)

inst_532:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x26b and fs2 == 0 and fe2 == 0x10 and fm2 == 0x0b7 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x392 and fcsr == 0x40 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x766b; op2val:0x40b7;
op3val:0x7b92; valaddr_reg:x3; val_offset:1596*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:64 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 64, 0, x3, 1596*FLEN/8, x4, x1, x2)

inst_533:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x26b and fs2 == 0 and fe2 == 0x10 and fm2 == 0x0b7 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x392 and fcsr == 0x60 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x766b; op2val:0x40b7;
op3val:0x7b92; valaddr_reg:x3; val_offset:1599*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 96, 0, x3, 1599*FLEN/8, x4, x1, x2)

inst_534:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x26b and fs2 == 0 and fe2 == 0x10 and fm2 == 0x0b7 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x392 and fcsr == 0x80 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x766b; op2val:0x40b7;
op3val:0x7b92; valaddr_reg:x3; val_offset:1602*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:128 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 128, 0, x3, 1602*FLEN/8, x4, x1, x2)

inst_535:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1cb and fs2 == 0 and fe2 == 0x0c and fm2 == 0x381 and fs3 == 0 and fe3 == 0x1c and fm3 == 0x170 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x79cb; op2val:0x3381;
op3val:0x7170; valaddr_reg:x3; val_offset:1605*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 1605*FLEN/8, x4, x1, x2)

inst_536:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1cb and fs2 == 0 and fe2 == 0x0c and fm2 == 0x381 and fs3 == 0 and fe3 == 0x1c and fm3 == 0x170 and fcsr == 0x20 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x79cb; op2val:0x3381;
op3val:0x7170; valaddr_reg:x3; val_offset:1608*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:32 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 32, 0, x3, 1608*FLEN/8, x4, x1, x2)

inst_537:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1cb and fs2 == 0 and fe2 == 0x0c and fm2 == 0x381 and fs3 == 0 and fe3 == 0x1c and fm3 == 0x170 and fcsr == 0x40 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x79cb; op2val:0x3381;
op3val:0x7170; valaddr_reg:x3; val_offset:1611*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:64 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 64, 0, x3, 1611*FLEN/8, x4, x1, x2)

inst_538:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1cb and fs2 == 0 and fe2 == 0x0c and fm2 == 0x381 and fs3 == 0 and fe3 == 0x1c and fm3 == 0x170 and fcsr == 0x60 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x79cb; op2val:0x3381;
op3val:0x7170; valaddr_reg:x3; val_offset:1614*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 96, 0, x3, 1614*FLEN/8, x4, x1, x2)

inst_539:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1cb and fs2 == 0 and fe2 == 0x0c and fm2 == 0x381 and fs3 == 0 and fe3 == 0x1c and fm3 == 0x170 and fcsr == 0x80 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x79cb; op2val:0x3381;
op3val:0x7170; valaddr_reg:x3; val_offset:1617*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:128 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 128, 0, x3, 1617*FLEN/8, x4, x1, x2)

inst_540:
// fs1 == 0 and fe1 == 0x1c and fm1 == 0x010 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x0c2 and fs3 == 0 and fe3 == 0x1c and fm3 == 0x0d5 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7010; op2val:0x3cc2;
op3val:0x70d5; valaddr_reg:x3; val_offset:1620*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 1620*FLEN/8, x4, x1, x2)

inst_541:
// fs1 == 0 and fe1 == 0x1c and fm1 == 0x010 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x0c2 and fs3 == 0 and fe3 == 0x1c and fm3 == 0x0d5 and fcsr == 0x20 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7010; op2val:0x3cc2;
op3val:0x70d5; valaddr_reg:x3; val_offset:1623*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:32 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 32, 0, x3, 1623*FLEN/8, x4, x1, x2)

inst_542:
// fs1 == 0 and fe1 == 0x1c and fm1 == 0x010 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x0c2 and fs3 == 0 and fe3 == 0x1c and fm3 == 0x0d5 and fcsr == 0x40 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7010; op2val:0x3cc2;
op3val:0x70d5; valaddr_reg:x3; val_offset:1626*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:64 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 64, 0, x3, 1626*FLEN/8, x4, x1, x2)

inst_543:
// fs1 == 0 and fe1 == 0x1c and fm1 == 0x010 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x0c2 and fs3 == 0 and fe3 == 0x1c and fm3 == 0x0d5 and fcsr == 0x60 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7010; op2val:0x3cc2;
op3val:0x70d5; valaddr_reg:x3; val_offset:1629*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 96, 0, x3, 1629*FLEN/8, x4, x1, x2)

inst_544:
// fs1 == 0 and fe1 == 0x1c and fm1 == 0x010 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x0c2 and fs3 == 0 and fe3 == 0x1c and fm3 == 0x0d5 and fcsr == 0x80 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7010; op2val:0x3cc2;
op3val:0x70d5; valaddr_reg:x3; val_offset:1632*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:128 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 128, 0, x3, 1632*FLEN/8, x4, x1, x2)

inst_545:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x33c and fs2 == 0 and fe2 == 0x0e and fm2 == 0x321 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x272 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7b3c; op2val:0x3b21;
op3val:0x7a72; valaddr_reg:x3; val_offset:1635*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 1635*FLEN/8, x4, x1, x2)

inst_546:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x33c and fs2 == 0 and fe2 == 0x0e and fm2 == 0x321 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x272 and fcsr == 0x20 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7b3c; op2val:0x3b21;
op3val:0x7a72; valaddr_reg:x3; val_offset:1638*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:32 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 32, 0, x3, 1638*FLEN/8, x4, x1, x2)

inst_547:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x33c and fs2 == 0 and fe2 == 0x0e and fm2 == 0x321 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x272 and fcsr == 0x40 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7b3c; op2val:0x3b21;
op3val:0x7a72; valaddr_reg:x3; val_offset:1641*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:64 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 64, 0, x3, 1641*FLEN/8, x4, x1, x2)

inst_548:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x33c and fs2 == 0 and fe2 == 0x0e and fm2 == 0x321 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x272 and fcsr == 0x60 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7b3c; op2val:0x3b21;
op3val:0x7a72; valaddr_reg:x3; val_offset:1644*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 96, 0, x3, 1644*FLEN/8, x4, x1, x2)

inst_549:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x33c and fs2 == 0 and fe2 == 0x0e and fm2 == 0x321 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x272 and fcsr == 0x80 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7b3c; op2val:0x3b21;
op3val:0x7a72; valaddr_reg:x3; val_offset:1647*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:128 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 128, 0, x3, 1647*FLEN/8, x4, x1, x2)

inst_550:
// fs1 == 0 and fe1 == 0x1c and fm1 == 0x0ac and fs2 == 0 and fe2 == 0x11 and fm2 == 0x1a7 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x29b and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x70ac; op2val:0x45a7;
op3val:0x7a9b; valaddr_reg:x3; val_offset:1650*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 1650*FLEN/8, x4, x1, x2)

inst_551:
// fs1 == 0 and fe1 == 0x1c and fm1 == 0x0ac and fs2 == 0 and fe2 == 0x11 and fm2 == 0x1a7 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x29b and fcsr == 0x20 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x70ac; op2val:0x45a7;
op3val:0x7a9b; valaddr_reg:x3; val_offset:1653*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:32 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 32, 0, x3, 1653*FLEN/8, x4, x1, x2)

inst_552:
// fs1 == 0 and fe1 == 0x1c and fm1 == 0x0ac and fs2 == 0 and fe2 == 0x11 and fm2 == 0x1a7 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x29b and fcsr == 0x40 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x70ac; op2val:0x45a7;
op3val:0x7a9b; valaddr_reg:x3; val_offset:1656*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:64 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 64, 0, x3, 1656*FLEN/8, x4, x1, x2)

inst_553:
// fs1 == 0 and fe1 == 0x1c and fm1 == 0x0ac and fs2 == 0 and fe2 == 0x11 and fm2 == 0x1a7 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x29b and fcsr == 0x60 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x70ac; op2val:0x45a7;
op3val:0x7a9b; valaddr_reg:x3; val_offset:1659*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 96, 0, x3, 1659*FLEN/8, x4, x1, x2)

inst_554:
// fs1 == 0 and fe1 == 0x1c and fm1 == 0x0ac and fs2 == 0 and fe2 == 0x11 and fm2 == 0x1a7 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x29b and fcsr == 0x80 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x70ac; op2val:0x45a7;
op3val:0x7a9b; valaddr_reg:x3; val_offset:1662*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:128 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 128, 0, x3, 1662*FLEN/8, x4, x1, x2)

inst_555:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3d6 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x15d and fs3 == 0 and fe3 == 0x1e and fm3 == 0x141 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7bd6; op2val:0x395d;
op3val:0x7941; valaddr_reg:x3; val_offset:1665*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 1665*FLEN/8, x4, x1, x2)

inst_556:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3d6 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x15d and fs3 == 0 and fe3 == 0x1e and fm3 == 0x141 and fcsr == 0x20 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7bd6; op2val:0x395d;
op3val:0x7941; valaddr_reg:x3; val_offset:1668*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:32 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 32, 0, x3, 1668*FLEN/8, x4, x1, x2)

inst_557:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3d6 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x15d and fs3 == 0 and fe3 == 0x1e and fm3 == 0x141 and fcsr == 0x40 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7bd6; op2val:0x395d;
op3val:0x7941; valaddr_reg:x3; val_offset:1671*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:64 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 64, 0, x3, 1671*FLEN/8, x4, x1, x2)

inst_558:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3d6 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x15d and fs3 == 0 and fe3 == 0x1e and fm3 == 0x141 and fcsr == 0x60 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7bd6; op2val:0x395d;
op3val:0x7941; valaddr_reg:x3; val_offset:1674*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 96, 0, x3, 1674*FLEN/8, x4, x1, x2)

inst_559:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3d6 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x15d and fs3 == 0 and fe3 == 0x1e and fm3 == 0x141 and fcsr == 0x80 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7bd6; op2val:0x395d;
op3val:0x7941; valaddr_reg:x3; val_offset:1677*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:128 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 128, 0, x3, 1677*FLEN/8, x4, x1, x2)

inst_560:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x19a and fs2 == 0 and fe2 == 0x0f and fm2 == 0x243 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x063 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x759a; op2val:0x3e43;
op3val:0x7863; valaddr_reg:x3; val_offset:1680*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 1680*FLEN/8, x4, x1, x2)

inst_561:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x19a and fs2 == 0 and fe2 == 0x0f and fm2 == 0x243 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x063 and fcsr == 0x20 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x759a; op2val:0x3e43;
op3val:0x7863; valaddr_reg:x3; val_offset:1683*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:32 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 32, 0, x3, 1683*FLEN/8, x4, x1, x2)

inst_562:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x19a and fs2 == 0 and fe2 == 0x0f and fm2 == 0x243 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x063 and fcsr == 0x40 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x759a; op2val:0x3e43;
op3val:0x7863; valaddr_reg:x3; val_offset:1686*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:64 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 64, 0, x3, 1686*FLEN/8, x4, x1, x2)

inst_563:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x19a and fs2 == 0 and fe2 == 0x0f and fm2 == 0x243 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x063 and fcsr == 0x60 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x759a; op2val:0x3e43;
op3val:0x7863; valaddr_reg:x3; val_offset:1689*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 96, 0, x3, 1689*FLEN/8, x4, x1, x2)

inst_564:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x19a and fs2 == 0 and fe2 == 0x0f and fm2 == 0x243 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x063 and fcsr == 0x80 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x759a; op2val:0x3e43;
op3val:0x7863; valaddr_reg:x3; val_offset:1692*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:128 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 128, 0, x3, 1692*FLEN/8, x4, x1, x2)

inst_565:
// fs1 == 0 and fe1 == 0x1c and fm1 == 0x030 and fs2 == 0 and fe2 == 0x0b and fm2 == 0x2f7 and fs3 == 0 and fe3 == 0x18 and fm3 == 0x34b and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7030; op2val:0x2ef7;
op3val:0x634b; valaddr_reg:x3; val_offset:1695*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 1695*FLEN/8, x4, x1, x2)

inst_566:
// fs1 == 0 and fe1 == 0x1c and fm1 == 0x030 and fs2 == 0 and fe2 == 0x0b and fm2 == 0x2f7 and fs3 == 0 and fe3 == 0x18 and fm3 == 0x34b and fcsr == 0x20 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7030; op2val:0x2ef7;
op3val:0x634b; valaddr_reg:x3; val_offset:1698*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:32 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 32, 0, x3, 1698*FLEN/8, x4, x1, x2)

inst_567:
// fs1 == 0 and fe1 == 0x1c and fm1 == 0x030 and fs2 == 0 and fe2 == 0x0b and fm2 == 0x2f7 and fs3 == 0 and fe3 == 0x18 and fm3 == 0x34b and fcsr == 0x40 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7030; op2val:0x2ef7;
op3val:0x634b; valaddr_reg:x3; val_offset:1701*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:64 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 64, 0, x3, 1701*FLEN/8, x4, x1, x2)

inst_568:
// fs1 == 0 and fe1 == 0x1c and fm1 == 0x030 and fs2 == 0 and fe2 == 0x0b and fm2 == 0x2f7 and fs3 == 0 and fe3 == 0x18 and fm3 == 0x34b and fcsr == 0x60 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7030; op2val:0x2ef7;
op3val:0x634b; valaddr_reg:x3; val_offset:1704*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 96, 0, x3, 1704*FLEN/8, x4, x1, x2)

inst_569:
// fs1 == 0 and fe1 == 0x1c and fm1 == 0x030 and fs2 == 0 and fe2 == 0x0b and fm2 == 0x2f7 and fs3 == 0 and fe3 == 0x18 and fm3 == 0x34b and fcsr == 0x80 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7030; op2val:0x2ef7;
op3val:0x634b; valaddr_reg:x3; val_offset:1707*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:128 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 128, 0, x3, 1707*FLEN/8, x4, x1, x2)

inst_570:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3c3 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x15a and fs3 == 0 and fe3 == 0x1e and fm3 == 0x131 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7bc3; op2val:0x395a;
op3val:0x7931; valaddr_reg:x3; val_offset:1710*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 1710*FLEN/8, x4, x1, x2)

inst_571:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3c3 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x15a and fs3 == 0 and fe3 == 0x1e and fm3 == 0x131 and fcsr == 0x20 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7bc3; op2val:0x395a;
op3val:0x7931; valaddr_reg:x3; val_offset:1713*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:32 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 32, 0, x3, 1713*FLEN/8, x4, x1, x2)

inst_572:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3c3 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x15a and fs3 == 0 and fe3 == 0x1e and fm3 == 0x131 and fcsr == 0x40 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7bc3; op2val:0x395a;
op3val:0x7931; valaddr_reg:x3; val_offset:1716*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:64 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 64, 0, x3, 1716*FLEN/8, x4, x1, x2)

inst_573:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3c3 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x15a and fs3 == 0 and fe3 == 0x1e and fm3 == 0x131 and fcsr == 0x60 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7bc3; op2val:0x395a;
op3val:0x7931; valaddr_reg:x3; val_offset:1719*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 96, 0, x3, 1719*FLEN/8, x4, x1, x2)

inst_574:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3c3 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x15a and fs3 == 0 and fe3 == 0x1e and fm3 == 0x131 and fcsr == 0x80 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7bc3; op2val:0x395a;
op3val:0x7931; valaddr_reg:x3; val_offset:1722*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:128 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 128, 0, x3, 1722*FLEN/8, x4, x1, x2)

inst_575:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x035 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x317 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x377 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7835; op2val:0x3f17;
op3val:0x7b77; valaddr_reg:x3; val_offset:1725*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 1725*FLEN/8, x4, x1, x2)

inst_576:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x035 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x317 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x377 and fcsr == 0x20 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7835; op2val:0x3f17;
op3val:0x7b77; valaddr_reg:x3; val_offset:1728*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:32 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 32, 0, x3, 1728*FLEN/8, x4, x1, x2)

inst_577:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x035 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x317 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x377 and fcsr == 0x40 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7835; op2val:0x3f17;
op3val:0x7b77; valaddr_reg:x3; val_offset:1731*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:64 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 64, 0, x3, 1731*FLEN/8, x4, x1, x2)

inst_578:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x035 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x317 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x377 and fcsr == 0x60 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7835; op2val:0x3f17;
op3val:0x7b77; valaddr_reg:x3; val_offset:1734*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 96, 0, x3, 1734*FLEN/8, x4, x1, x2)

inst_579:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x035 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x317 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x377 and fcsr == 0x80 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7835; op2val:0x3f17;
op3val:0x7b77; valaddr_reg:x3; val_offset:1737*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:128 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 128, 0, x3, 1737*FLEN/8, x4, x1, x2)

inst_580:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x2f0 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x004 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x2f8 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x76f0; op2val:0x4004;
op3val:0x7af8; valaddr_reg:x3; val_offset:1740*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 1740*FLEN/8, x4, x1, x2)

inst_581:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x2f0 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x004 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x2f8 and fcsr == 0x20 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x76f0; op2val:0x4004;
op3val:0x7af8; valaddr_reg:x3; val_offset:1743*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:32 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 32, 0, x3, 1743*FLEN/8, x4, x1, x2)

inst_582:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x2f0 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x004 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x2f8 and fcsr == 0x40 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x76f0; op2val:0x4004;
op3val:0x7af8; valaddr_reg:x3; val_offset:1746*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:64 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 64, 0, x3, 1746*FLEN/8, x4, x1, x2)

inst_583:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x2f0 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x004 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x2f8 and fcsr == 0x60 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x76f0; op2val:0x4004;
op3val:0x7af8; valaddr_reg:x3; val_offset:1749*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 96, 0, x3, 1749*FLEN/8, x4, x1, x2)

inst_584:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x2f0 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x004 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x2f8 and fcsr == 0x80 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x76f0; op2val:0x4004;
op3val:0x7af8; valaddr_reg:x3; val_offset:1752*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:128 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 128, 0, x3, 1752*FLEN/8, x4, x1, x2)

inst_585:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x29b and fs2 == 0 and fe2 == 0x0d and fm2 == 0x016 and fs3 == 0 and fe3 == 0x1c and fm3 == 0x2c0 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7a9b; op2val:0x3416;
op3val:0x72c0; valaddr_reg:x3; val_offset:1755*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 1755*FLEN/8, x4, x1, x2)

inst_586:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x29b and fs2 == 0 and fe2 == 0x0d and fm2 == 0x016 and fs3 == 0 and fe3 == 0x1c and fm3 == 0x2c0 and fcsr == 0x20 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7a9b; op2val:0x3416;
op3val:0x72c0; valaddr_reg:x3; val_offset:1758*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:32 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 32, 0, x3, 1758*FLEN/8, x4, x1, x2)

inst_587:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x29b and fs2 == 0 and fe2 == 0x0d and fm2 == 0x016 and fs3 == 0 and fe3 == 0x1c and fm3 == 0x2c0 and fcsr == 0x40 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7a9b; op2val:0x3416;
op3val:0x72c0; valaddr_reg:x3; val_offset:1761*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:64 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 64, 0, x3, 1761*FLEN/8, x4, x1, x2)

inst_588:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x29b and fs2 == 0 and fe2 == 0x0d and fm2 == 0x016 and fs3 == 0 and fe3 == 0x1c and fm3 == 0x2c0 and fcsr == 0x60 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7a9b; op2val:0x3416;
op3val:0x72c0; valaddr_reg:x3; val_offset:1764*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 96, 0, x3, 1764*FLEN/8, x4, x1, x2)

inst_589:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x29b and fs2 == 0 and fe2 == 0x0d and fm2 == 0x016 and fs3 == 0 and fe3 == 0x1c and fm3 == 0x2c0 and fcsr == 0x80 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7a9b; op2val:0x3416;
op3val:0x72c0; valaddr_reg:x3; val_offset:1767*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:128 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 128, 0, x3, 1767*FLEN/8, x4, x1, x2)

inst_590:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x007 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x0a7 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x0af and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7407; op2val:0x3ca7;
op3val:0x74af; valaddr_reg:x3; val_offset:1770*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 1770*FLEN/8, x4, x1, x2)

inst_591:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x007 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x0a7 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x0af and fcsr == 0x20 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7407; op2val:0x3ca7;
op3val:0x74af; valaddr_reg:x3; val_offset:1773*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:32 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 32, 0, x3, 1773*FLEN/8, x4, x1, x2)

inst_592:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x007 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x0a7 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x0af and fcsr == 0x40 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7407; op2val:0x3ca7;
op3val:0x74af; valaddr_reg:x3; val_offset:1776*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:64 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 64, 0, x3, 1776*FLEN/8, x4, x1, x2)

inst_593:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x007 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x0a7 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x0af and fcsr == 0x60 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7407; op2val:0x3ca7;
op3val:0x74af; valaddr_reg:x3; val_offset:1779*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 96, 0, x3, 1779*FLEN/8, x4, x1, x2)

inst_594:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x007 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x0a7 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x0af and fcsr == 0x80 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7407; op2val:0x3ca7;
op3val:0x74af; valaddr_reg:x3; val_offset:1782*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:128 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 128, 0, x3, 1782*FLEN/8, x4, x1, x2)

inst_595:
// fs1 == 0 and fe1 == 0x1c and fm1 == 0x3b1 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x0e0 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x0b0 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x73b1; op2val:0x40e0;
op3val:0x78b0; valaddr_reg:x3; val_offset:1785*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 1785*FLEN/8, x4, x1, x2)

inst_596:
// fs1 == 0 and fe1 == 0x1c and fm1 == 0x3b1 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x0e0 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x0b0 and fcsr == 0x20 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x73b1; op2val:0x40e0;
op3val:0x78b0; valaddr_reg:x3; val_offset:1788*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:32 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 32, 0, x3, 1788*FLEN/8, x4, x1, x2)

inst_597:
// fs1 == 0 and fe1 == 0x1c and fm1 == 0x3b1 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x0e0 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x0b0 and fcsr == 0x40 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x73b1; op2val:0x40e0;
op3val:0x78b0; valaddr_reg:x3; val_offset:1791*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:64 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 64, 0, x3, 1791*FLEN/8, x4, x1, x2)

inst_598:
// fs1 == 0 and fe1 == 0x1c and fm1 == 0x3b1 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x0e0 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x0b0 and fcsr == 0x60 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x73b1; op2val:0x40e0;
op3val:0x78b0; valaddr_reg:x3; val_offset:1794*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 96, 0, x3, 1794*FLEN/8, x4, x1, x2)

inst_599:
// fs1 == 0 and fe1 == 0x1c and fm1 == 0x3b1 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x0e0 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x0b0 and fcsr == 0x80 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x73b1; op2val:0x40e0;
op3val:0x78b0; valaddr_reg:x3; val_offset:1797*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:128 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 128, 0, x3, 1797*FLEN/8, x4, x1, x2)

inst_600:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x025 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x276 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x2b3 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7425; op2val:0x3e76;
op3val:0x76b3; valaddr_reg:x3; val_offset:1800*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 1800*FLEN/8, x4, x1, x2)

inst_601:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x025 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x276 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x2b3 and fcsr == 0x20 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7425; op2val:0x3e76;
op3val:0x76b3; valaddr_reg:x3; val_offset:1803*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:32 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 32, 0, x3, 1803*FLEN/8, x4, x1, x2)

inst_602:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x025 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x276 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x2b3 and fcsr == 0x40 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7425; op2val:0x3e76;
op3val:0x76b3; valaddr_reg:x3; val_offset:1806*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:64 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 64, 0, x3, 1806*FLEN/8, x4, x1, x2)

inst_603:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x025 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x276 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x2b3 and fcsr == 0x60 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7425; op2val:0x3e76;
op3val:0x76b3; valaddr_reg:x3; val_offset:1809*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 96, 0, x3, 1809*FLEN/8, x4, x1, x2)

inst_604:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x025 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x276 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x2b3 and fcsr == 0x80 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7425; op2val:0x3e76;
op3val:0x76b3; valaddr_reg:x3; val_offset:1812*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:128 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 128, 0, x3, 1812*FLEN/8, x4, x1, x2)

inst_605:
// fs1 == 0 and fe1 == 0x1c and fm1 == 0x031 and fs2 == 0 and fe2 == 0x11 and fm2 == 0x2f1 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x346 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7031; op2val:0x46f1;
op3val:0x7b46; valaddr_reg:x3; val_offset:1815*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 1815*FLEN/8, x4, x1, x2)

inst_606:
// fs1 == 0 and fe1 == 0x1c and fm1 == 0x031 and fs2 == 0 and fe2 == 0x11 and fm2 == 0x2f1 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x346 and fcsr == 0x20 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7031; op2val:0x46f1;
op3val:0x7b46; valaddr_reg:x3; val_offset:1818*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:32 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 32, 0, x3, 1818*FLEN/8, x4, x1, x2)

inst_607:
// fs1 == 0 and fe1 == 0x1c and fm1 == 0x031 and fs2 == 0 and fe2 == 0x11 and fm2 == 0x2f1 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x346 and fcsr == 0x40 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7031; op2val:0x46f1;
op3val:0x7b46; valaddr_reg:x3; val_offset:1821*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:64 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 64, 0, x3, 1821*FLEN/8, x4, x1, x2)

inst_608:
// fs1 == 0 and fe1 == 0x1c and fm1 == 0x031 and fs2 == 0 and fe2 == 0x11 and fm2 == 0x2f1 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x346 and fcsr == 0x60 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7031; op2val:0x46f1;
op3val:0x7b46; valaddr_reg:x3; val_offset:1824*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 96, 0, x3, 1824*FLEN/8, x4, x1, x2)

inst_609:
// fs1 == 0 and fe1 == 0x1c and fm1 == 0x031 and fs2 == 0 and fe2 == 0x11 and fm2 == 0x2f1 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x346 and fcsr == 0x80 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7031; op2val:0x46f1;
op3val:0x7b46; valaddr_reg:x3; val_offset:1827*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:128 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 128, 0, x3, 1827*FLEN/8, x4, x1, x2)

inst_610:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x1a8 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x12e and fs3 == 0 and fe3 == 0x1d and fm3 == 0x353 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x75a8; op2val:0x3d2e;
op3val:0x7753; valaddr_reg:x3; val_offset:1830*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 1830*FLEN/8, x4, x1, x2)

inst_611:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x1a8 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x12e and fs3 == 0 and fe3 == 0x1d and fm3 == 0x353 and fcsr == 0x20 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x75a8; op2val:0x3d2e;
op3val:0x7753; valaddr_reg:x3; val_offset:1833*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:32 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 32, 0, x3, 1833*FLEN/8, x4, x1, x2)

inst_612:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x1a8 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x12e and fs3 == 0 and fe3 == 0x1d and fm3 == 0x353 and fcsr == 0x40 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x75a8; op2val:0x3d2e;
op3val:0x7753; valaddr_reg:x3; val_offset:1836*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:64 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 64, 0, x3, 1836*FLEN/8, x4, x1, x2)

inst_613:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x1a8 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x12e and fs3 == 0 and fe3 == 0x1d and fm3 == 0x353 and fcsr == 0x60 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x75a8; op2val:0x3d2e;
op3val:0x7753; valaddr_reg:x3; val_offset:1839*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 96, 0, x3, 1839*FLEN/8, x4, x1, x2)

inst_614:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x1a8 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x12e and fs3 == 0 and fe3 == 0x1d and fm3 == 0x353 and fcsr == 0x80 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x75a8; op2val:0x3d2e;
op3val:0x7753; valaddr_reg:x3; val_offset:1842*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:128 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 128, 0, x3, 1842*FLEN/8, x4, x1, x2)

inst_615:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0aa and fs2 == 0 and fe2 == 0x0f and fm2 == 0x233 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x33b and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x78aa; op2val:0x3e33;
op3val:0x7b3b; valaddr_reg:x3; val_offset:1845*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 1845*FLEN/8, x4, x1, x2)

inst_616:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0aa and fs2 == 0 and fe2 == 0x0f and fm2 == 0x233 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x33b and fcsr == 0x20 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x78aa; op2val:0x3e33;
op3val:0x7b3b; valaddr_reg:x3; val_offset:1848*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:32 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 32, 0, x3, 1848*FLEN/8, x4, x1, x2)

inst_617:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0aa and fs2 == 0 and fe2 == 0x0f and fm2 == 0x233 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x33b and fcsr == 0x40 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x78aa; op2val:0x3e33;
op3val:0x7b3b; valaddr_reg:x3; val_offset:1851*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:64 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 64, 0, x3, 1851*FLEN/8, x4, x1, x2)

inst_618:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0aa and fs2 == 0 and fe2 == 0x0f and fm2 == 0x233 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x33b and fcsr == 0x60 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x78aa; op2val:0x3e33;
op3val:0x7b3b; valaddr_reg:x3; val_offset:1854*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 96, 0, x3, 1854*FLEN/8, x4, x1, x2)

inst_619:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0aa and fs2 == 0 and fe2 == 0x0f and fm2 == 0x233 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x33b and fcsr == 0x80 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x78aa; op2val:0x3e33;
op3val:0x7b3b; valaddr_reg:x3; val_offset:1857*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:128 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 128, 0, x3, 1857*FLEN/8, x4, x1, x2)

inst_620:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x2ba and fs2 == 0 and fe2 == 0x10 and fm2 == 0x05d and fs3 == 0 and fe3 == 0x1e and fm3 == 0x356 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x76ba; op2val:0x405d;
op3val:0x7b56; valaddr_reg:x3; val_offset:1860*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 1860*FLEN/8, x4, x1, x2)

inst_621:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x2ba and fs2 == 0 and fe2 == 0x10 and fm2 == 0x05d and fs3 == 0 and fe3 == 0x1e and fm3 == 0x356 and fcsr == 0x20 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x76ba; op2val:0x405d;
op3val:0x7b56; valaddr_reg:x3; val_offset:1863*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:32 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 32, 0, x3, 1863*FLEN/8, x4, x1, x2)

inst_622:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x2ba and fs2 == 0 and fe2 == 0x10 and fm2 == 0x05d and fs3 == 0 and fe3 == 0x1e and fm3 == 0x356 and fcsr == 0x40 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x76ba; op2val:0x405d;
op3val:0x7b56; valaddr_reg:x3; val_offset:1866*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:64 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 64, 0, x3, 1866*FLEN/8, x4, x1, x2)

inst_623:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x2ba and fs2 == 0 and fe2 == 0x10 and fm2 == 0x05d and fs3 == 0 and fe3 == 0x1e and fm3 == 0x356 and fcsr == 0x60 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x76ba; op2val:0x405d;
op3val:0x7b56; valaddr_reg:x3; val_offset:1869*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 96, 0, x3, 1869*FLEN/8, x4, x1, x2)

inst_624:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x2ba and fs2 == 0 and fe2 == 0x10 and fm2 == 0x05d and fs3 == 0 and fe3 == 0x1e and fm3 == 0x356 and fcsr == 0x80 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x76ba; op2val:0x405d;
op3val:0x7b56; valaddr_reg:x3; val_offset:1872*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:128 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 128, 0, x3, 1872*FLEN/8, x4, x1, x2)

inst_625:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x002 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x03d and fs3 == 0 and fe3 == 0x1e and fm3 == 0x040 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7802; op2val:0x3c3d;
op3val:0x7840; valaddr_reg:x3; val_offset:1875*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 1875*FLEN/8, x4, x1, x2)

inst_626:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x002 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x03d and fs3 == 0 and fe3 == 0x1e and fm3 == 0x040 and fcsr == 0x20 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7802; op2val:0x3c3d;
op3val:0x7840; valaddr_reg:x3; val_offset:1878*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:32 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 32, 0, x3, 1878*FLEN/8, x4, x1, x2)

inst_627:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x002 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x03d and fs3 == 0 and fe3 == 0x1e and fm3 == 0x040 and fcsr == 0x40 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7802; op2val:0x3c3d;
op3val:0x7840; valaddr_reg:x3; val_offset:1881*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:64 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 64, 0, x3, 1881*FLEN/8, x4, x1, x2)

inst_628:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x002 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x03d and fs3 == 0 and fe3 == 0x1e and fm3 == 0x040 and fcsr == 0x60 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7802; op2val:0x3c3d;
op3val:0x7840; valaddr_reg:x3; val_offset:1884*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 96, 0, x3, 1884*FLEN/8, x4, x1, x2)

inst_629:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x002 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x03d and fs3 == 0 and fe3 == 0x1e and fm3 == 0x040 and fcsr == 0x80 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7802; op2val:0x3c3d;
op3val:0x7840; valaddr_reg:x3; val_offset:1887*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:128 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 128, 0, x3, 1887*FLEN/8, x4, x1, x2)

inst_630:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x02f and fs2 == 0 and fe2 == 0x0a and fm2 == 0x093 and fs3 == 0 and fe3 == 0x19 and fm3 == 0x0ca and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x782f; op2val:0x2893;
op3val:0x64ca; valaddr_reg:x3; val_offset:1890*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 1890*FLEN/8, x4, x1, x2)

inst_631:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x02f and fs2 == 0 and fe2 == 0x0a and fm2 == 0x093 and fs3 == 0 and fe3 == 0x19 and fm3 == 0x0ca and fcsr == 0x20 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x782f; op2val:0x2893;
op3val:0x64ca; valaddr_reg:x3; val_offset:1893*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:32 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 32, 0, x3, 1893*FLEN/8, x4, x1, x2)

inst_632:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x02f and fs2 == 0 and fe2 == 0x0a and fm2 == 0x093 and fs3 == 0 and fe3 == 0x19 and fm3 == 0x0ca and fcsr == 0x40 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x782f; op2val:0x2893;
op3val:0x64ca; valaddr_reg:x3; val_offset:1896*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:64 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 64, 0, x3, 1896*FLEN/8, x4, x1, x2)

inst_633:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x02f and fs2 == 0 and fe2 == 0x0a and fm2 == 0x093 and fs3 == 0 and fe3 == 0x19 and fm3 == 0x0ca and fcsr == 0x60 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x782f; op2val:0x2893;
op3val:0x64ca; valaddr_reg:x3; val_offset:1899*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 96, 0, x3, 1899*FLEN/8, x4, x1, x2)

inst_634:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x02f and fs2 == 0 and fe2 == 0x0a and fm2 == 0x093 and fs3 == 0 and fe3 == 0x19 and fm3 == 0x0ca and fcsr == 0x80 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x782f; op2val:0x2893;
op3val:0x64ca; valaddr_reg:x3; val_offset:1902*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:128 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 128, 0, x3, 1902*FLEN/8, x4, x1, x2)

inst_635:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x309 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x2a8 and fs3 == 0 and fe3 == 0x1c and fm3 == 0x1db and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7709; op2val:0x36a8;
op3val:0x71db; valaddr_reg:x3; val_offset:1905*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 1905*FLEN/8, x4, x1, x2)

inst_636:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x309 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x2a8 and fs3 == 0 and fe3 == 0x1c and fm3 == 0x1db and fcsr == 0x20 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7709; op2val:0x36a8;
op3val:0x71db; valaddr_reg:x3; val_offset:1908*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:32 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 32, 0, x3, 1908*FLEN/8, x4, x1, x2)

inst_637:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x309 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x2a8 and fs3 == 0 and fe3 == 0x1c and fm3 == 0x1db and fcsr == 0x40 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7709; op2val:0x36a8;
op3val:0x71db; valaddr_reg:x3; val_offset:1911*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:64 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 64, 0, x3, 1911*FLEN/8, x4, x1, x2)

inst_638:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x309 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x2a8 and fs3 == 0 and fe3 == 0x1c and fm3 == 0x1db and fcsr == 0x60 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7709; op2val:0x36a8;
op3val:0x71db; valaddr_reg:x3; val_offset:1914*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 96, 0, x3, 1914*FLEN/8, x4, x1, x2)

inst_639:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x309 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x2a8 and fs3 == 0 and fe3 == 0x1c and fm3 == 0x1db and fcsr == 0x80 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7709; op2val:0x36a8;
op3val:0x71db; valaddr_reg:x3; val_offset:1917*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:128 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 128, 0, x3, 1917*FLEN/8, x4, x1, x2)
RVTEST_SIGBASE(x1,signature_x1_6)

inst_640:
// fs1 == 0 and fe1 == 0x17 and fm1 == 0x00a and fs2 == 0 and fe2 == 0x16 and fm2 == 0x253 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x263 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x5c0a; op2val:0x5a53;
op3val:0x7a63; valaddr_reg:x3; val_offset:1920*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 1920*FLEN/8, x4, x1, x2)

inst_641:
// fs1 == 0 and fe1 == 0x17 and fm1 == 0x00a and fs2 == 0 and fe2 == 0x16 and fm2 == 0x253 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x263 and fcsr == 0x20 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x5c0a; op2val:0x5a53;
op3val:0x7a63; valaddr_reg:x3; val_offset:1923*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:32 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 32, 0, x3, 1923*FLEN/8, x4, x1, x2)

inst_642:
// fs1 == 0 and fe1 == 0x17 and fm1 == 0x00a and fs2 == 0 and fe2 == 0x16 and fm2 == 0x253 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x263 and fcsr == 0x40 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x5c0a; op2val:0x5a53;
op3val:0x7a63; valaddr_reg:x3; val_offset:1926*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:64 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 64, 0, x3, 1926*FLEN/8, x4, x1, x2)

inst_643:
// fs1 == 0 and fe1 == 0x17 and fm1 == 0x00a and fs2 == 0 and fe2 == 0x16 and fm2 == 0x253 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x263 and fcsr == 0x60 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x5c0a; op2val:0x5a53;
op3val:0x7a63; valaddr_reg:x3; val_offset:1929*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 96, 0, x3, 1929*FLEN/8, x4, x1, x2)

inst_644:
// fs1 == 0 and fe1 == 0x17 and fm1 == 0x00a and fs2 == 0 and fe2 == 0x16 and fm2 == 0x253 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x263 and fcsr == 0x80 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x5c0a; op2val:0x5a53;
op3val:0x7a63; valaddr_reg:x3; val_offset:1932*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:128 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 128, 0, x3, 1932*FLEN/8, x4, x1, x2)

inst_645:
// fs1 == 0 and fe1 == 0x1c and fm1 == 0x183 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x17e and fs3 == 0 and fe3 == 0x1d and fm3 == 0x392 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7183; op2val:0x417e;
op3val:0x7792; valaddr_reg:x3; val_offset:1935*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 1935*FLEN/8, x4, x1, x2)

inst_646:
// fs1 == 0 and fe1 == 0x1c and fm1 == 0x183 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x17e and fs3 == 0 and fe3 == 0x1d and fm3 == 0x392 and fcsr == 0x20 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7183; op2val:0x417e;
op3val:0x7792; valaddr_reg:x3; val_offset:1938*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:32 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 32, 0, x3, 1938*FLEN/8, x4, x1, x2)

inst_647:
// fs1 == 0 and fe1 == 0x1c and fm1 == 0x183 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x17e and fs3 == 0 and fe3 == 0x1d and fm3 == 0x392 and fcsr == 0x40 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7183; op2val:0x417e;
op3val:0x7792; valaddr_reg:x3; val_offset:1941*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:64 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 64, 0, x3, 1941*FLEN/8, x4, x1, x2)

inst_648:
// fs1 == 0 and fe1 == 0x1c and fm1 == 0x183 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x17e and fs3 == 0 and fe3 == 0x1d and fm3 == 0x392 and fcsr == 0x60 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7183; op2val:0x417e;
op3val:0x7792; valaddr_reg:x3; val_offset:1944*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 96, 0, x3, 1944*FLEN/8, x4, x1, x2)

inst_649:
// fs1 == 0 and fe1 == 0x1c and fm1 == 0x183 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x17e and fs3 == 0 and fe3 == 0x1d and fm3 == 0x392 and fcsr == 0x80 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7183; op2val:0x417e;
op3val:0x7792; valaddr_reg:x3; val_offset:1947*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:128 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 128, 0, x3, 1947*FLEN/8, x4, x1, x2)

inst_650:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1cc and fs2 == 0 and fe2 == 0x0e and fm2 == 0x223 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x073 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x79cc; op2val:0x3a23;
op3val:0x7873; valaddr_reg:x3; val_offset:1950*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 1950*FLEN/8, x4, x1, x2)

inst_651:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1cc and fs2 == 0 and fe2 == 0x0e and fm2 == 0x223 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x073 and fcsr == 0x20 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x79cc; op2val:0x3a23;
op3val:0x7873; valaddr_reg:x3; val_offset:1953*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:32 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 32, 0, x3, 1953*FLEN/8, x4, x1, x2)

inst_652:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1cc and fs2 == 0 and fe2 == 0x0e and fm2 == 0x223 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x073 and fcsr == 0x40 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x79cc; op2val:0x3a23;
op3val:0x7873; valaddr_reg:x3; val_offset:1956*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:64 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 64, 0, x3, 1956*FLEN/8, x4, x1, x2)

inst_653:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1cc and fs2 == 0 and fe2 == 0x0e and fm2 == 0x223 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x073 and fcsr == 0x60 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x79cc; op2val:0x3a23;
op3val:0x7873; valaddr_reg:x3; val_offset:1959*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 96, 0, x3, 1959*FLEN/8, x4, x1, x2)

inst_654:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1cc and fs2 == 0 and fe2 == 0x0e and fm2 == 0x223 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x073 and fcsr == 0x80 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x79cc; op2val:0x3a23;
op3val:0x7873; valaddr_reg:x3; val_offset:1962*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:128 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 128, 0, x3, 1962*FLEN/8, x4, x1, x2)

inst_655:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x136 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x25c and fs3 == 0 and fe3 == 0x1e and fm3 == 0x025 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7536; op2val:0x3e5c;
op3val:0x7825; valaddr_reg:x3; val_offset:1965*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 1965*FLEN/8, x4, x1, x2)

inst_656:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x136 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x25c and fs3 == 0 and fe3 == 0x1e and fm3 == 0x025 and fcsr == 0x20 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7536; op2val:0x3e5c;
op3val:0x7825; valaddr_reg:x3; val_offset:1968*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:32 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 32, 0, x3, 1968*FLEN/8, x4, x1, x2)

inst_657:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x136 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x25c and fs3 == 0 and fe3 == 0x1e and fm3 == 0x025 and fcsr == 0x40 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7536; op2val:0x3e5c;
op3val:0x7825; valaddr_reg:x3; val_offset:1971*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:64 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 64, 0, x3, 1971*FLEN/8, x4, x1, x2)

inst_658:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x136 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x25c and fs3 == 0 and fe3 == 0x1e and fm3 == 0x025 and fcsr == 0x60 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7536; op2val:0x3e5c;
op3val:0x7825; valaddr_reg:x3; val_offset:1974*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 96, 0, x3, 1974*FLEN/8, x4, x1, x2)

inst_659:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x136 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x25c and fs3 == 0 and fe3 == 0x1e and fm3 == 0x025 and fcsr == 0x80 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7536; op2val:0x3e5c;
op3val:0x7825; valaddr_reg:x3; val_offset:1977*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:128 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 128, 0, x3, 1977*FLEN/8, x4, x1, x2)

inst_660:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x071 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x1a5 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x245 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7871; op2val:0x3da5;
op3val:0x7a45; valaddr_reg:x3; val_offset:1980*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 1980*FLEN/8, x4, x1, x2)

inst_661:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x071 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x1a5 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x245 and fcsr == 0x20 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7871; op2val:0x3da5;
op3val:0x7a45; valaddr_reg:x3; val_offset:1983*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:32 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 32, 0, x3, 1983*FLEN/8, x4, x1, x2)

inst_662:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x071 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x1a5 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x245 and fcsr == 0x40 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7871; op2val:0x3da5;
op3val:0x7a45; valaddr_reg:x3; val_offset:1986*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:64 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 64, 0, x3, 1986*FLEN/8, x4, x1, x2)

inst_663:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x071 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x1a5 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x245 and fcsr == 0x60 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7871; op2val:0x3da5;
op3val:0x7a45; valaddr_reg:x3; val_offset:1989*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 96, 0, x3, 1989*FLEN/8, x4, x1, x2)

inst_664:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x071 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x1a5 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x245 and fcsr == 0x80 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7871; op2val:0x3da5;
op3val:0x7a45; valaddr_reg:x3; val_offset:1992*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:128 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 128, 0, x3, 1992*FLEN/8, x4, x1, x2)

inst_665:
// fs1 == 0 and fe1 == 0x1b and fm1 == 0x2c9 and fs2 == 0 and fe2 == 0x11 and fm2 == 0x147 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x07a and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x6ec9; op2val:0x4547;
op3val:0x787a; valaddr_reg:x3; val_offset:1995*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 1995*FLEN/8, x4, x1, x2)

inst_666:
// fs1 == 0 and fe1 == 0x1b and fm1 == 0x2c9 and fs2 == 0 and fe2 == 0x11 and fm2 == 0x147 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x07a and fcsr == 0x20 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x6ec9; op2val:0x4547;
op3val:0x787a; valaddr_reg:x3; val_offset:1998*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:32 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 32, 0, x3, 1998*FLEN/8, x4, x1, x2)

inst_667:
// fs1 == 0 and fe1 == 0x1b and fm1 == 0x2c9 and fs2 == 0 and fe2 == 0x11 and fm2 == 0x147 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x07a and fcsr == 0x40 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x6ec9; op2val:0x4547;
op3val:0x787a; valaddr_reg:x3; val_offset:2001*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:64 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 64, 0, x3, 2001*FLEN/8, x4, x1, x2)

inst_668:
// fs1 == 0 and fe1 == 0x1b and fm1 == 0x2c9 and fs2 == 0 and fe2 == 0x11 and fm2 == 0x147 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x07a and fcsr == 0x60 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x6ec9; op2val:0x4547;
op3val:0x787a; valaddr_reg:x3; val_offset:2004*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 96, 0, x3, 2004*FLEN/8, x4, x1, x2)

inst_669:
// fs1 == 0 and fe1 == 0x1b and fm1 == 0x2c9 and fs2 == 0 and fe2 == 0x11 and fm2 == 0x147 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x07a and fcsr == 0x80 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x6ec9; op2val:0x4547;
op3val:0x787a; valaddr_reg:x3; val_offset:2007*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:128 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 128, 0, x3, 2007*FLEN/8, x4, x1, x2)

inst_670:
// fs1 == 0 and fe1 == 0x1c and fm1 == 0x3f2 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x075 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x06d and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x73f2; op2val:0x3c75;
op3val:0x746d; valaddr_reg:x3; val_offset:2010*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 2010*FLEN/8, x4, x1, x2)

inst_671:
// fs1 == 0 and fe1 == 0x1c and fm1 == 0x3f2 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x075 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x06d and fcsr == 0x20 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x73f2; op2val:0x3c75;
op3val:0x746d; valaddr_reg:x3; val_offset:2013*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:32 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 32, 0, x3, 2013*FLEN/8, x4, x1, x2)

inst_672:
// fs1 == 0 and fe1 == 0x1c and fm1 == 0x3f2 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x075 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x06d and fcsr == 0x40 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x73f2; op2val:0x3c75;
op3val:0x746d; valaddr_reg:x3; val_offset:2016*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:64 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 64, 0, x3, 2016*FLEN/8, x4, x1, x2)

inst_673:
// fs1 == 0 and fe1 == 0x1c and fm1 == 0x3f2 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x075 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x06d and fcsr == 0x60 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x73f2; op2val:0x3c75;
op3val:0x746d; valaddr_reg:x3; val_offset:2019*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 96, 0, x3, 2019*FLEN/8, x4, x1, x2)

inst_674:
// fs1 == 0 and fe1 == 0x1c and fm1 == 0x3f2 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x075 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x06d and fcsr == 0x80 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x73f2; op2val:0x3c75;
op3val:0x746d; valaddr_reg:x3; val_offset:2022*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:128 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 128, 0, x3, 2022*FLEN/8, x4, x1, x2)

inst_675:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x22c and fs2 == 0 and fe2 == 0x0e and fm2 == 0x142 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x00f and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7a2c; op2val:0x3942;
op3val:0x780f; valaddr_reg:x3; val_offset:2025*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 2025*FLEN/8, x4, x1, x2)

inst_676:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x22c and fs2 == 0 and fe2 == 0x0e and fm2 == 0x142 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x00f and fcsr == 0x20 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7a2c; op2val:0x3942;
op3val:0x780f; valaddr_reg:x3; val_offset:2028*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:32 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 32, 0, x3, 2028*FLEN/8, x4, x1, x2)

inst_677:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x22c and fs2 == 0 and fe2 == 0x0e and fm2 == 0x142 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x00f and fcsr == 0x40 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7a2c; op2val:0x3942;
op3val:0x780f; valaddr_reg:x3; val_offset:2031*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:64 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 64, 0, x3, 2031*FLEN/8, x4, x1, x2)

inst_678:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x22c and fs2 == 0 and fe2 == 0x0e and fm2 == 0x142 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x00f and fcsr == 0x60 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7a2c; op2val:0x3942;
op3val:0x780f; valaddr_reg:x3; val_offset:2034*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 96, 0, x3, 2034*FLEN/8, x4, x1, x2)

inst_679:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x22c and fs2 == 0 and fe2 == 0x0e and fm2 == 0x142 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x00f and fcsr == 0x80 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7a2c; op2val:0x3942;
op3val:0x780f; valaddr_reg:x3; val_offset:2037*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:128 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 128, 0, x3, 2037*FLEN/8, x4, x1, x2)

inst_680:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x07d and fs2 == 0 and fe2 == 0x0f and fm2 == 0x169 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x213 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x787d; op2val:0x3d69;
op3val:0x7a13; valaddr_reg:x3; val_offset:2040*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 2040*FLEN/8, x4, x1, x2)

inst_681:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x07d and fs2 == 0 and fe2 == 0x0f and fm2 == 0x169 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x213 and fcsr == 0x20 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x787d; op2val:0x3d69;
op3val:0x7a13; valaddr_reg:x3; val_offset:2043*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:32 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 32, 0, x3, 2043*FLEN/8, x4, x1, x2)

inst_682:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x07d and fs2 == 0 and fe2 == 0x0f and fm2 == 0x169 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x213 and fcsr == 0x40 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x787d; op2val:0x3d69;
op3val:0x7a13; valaddr_reg:x3; val_offset:2046*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:64 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 64, 0, x3, 2046*FLEN/8, x4, x1, x2)

inst_683:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x07d and fs2 == 0 and fe2 == 0x0f and fm2 == 0x169 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x213 and fcsr == 0x60 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x787d; op2val:0x3d69;
op3val:0x7a13; valaddr_reg:x3; val_offset:2049*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 96, 0, x3, 2049*FLEN/8, x4, x1, x2)

inst_684:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x07d and fs2 == 0 and fe2 == 0x0f and fm2 == 0x169 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x213 and fcsr == 0x80 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x787d; op2val:0x3d69;
op3val:0x7a13; valaddr_reg:x3; val_offset:2052*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:128 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 128, 0, x3, 2052*FLEN/8, x4, x1, x2)

inst_685:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x34b and fs2 == 0 and fe2 == 0x0d and fm2 == 0x3c5 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x316 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7b4b; op2val:0x37c5;
op3val:0x7716; valaddr_reg:x3; val_offset:2055*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 2055*FLEN/8, x4, x1, x2)

inst_686:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x34b and fs2 == 0 and fe2 == 0x0d and fm2 == 0x3c5 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x316 and fcsr == 0x20 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7b4b; op2val:0x37c5;
op3val:0x7716; valaddr_reg:x3; val_offset:2058*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:32 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 32, 0, x3, 2058*FLEN/8, x4, x1, x2)

inst_687:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x34b and fs2 == 0 and fe2 == 0x0d and fm2 == 0x3c5 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x316 and fcsr == 0x40 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7b4b; op2val:0x37c5;
op3val:0x7716; valaddr_reg:x3; val_offset:2061*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:64 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 64, 0, x3, 2061*FLEN/8, x4, x1, x2)

inst_688:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x34b and fs2 == 0 and fe2 == 0x0d and fm2 == 0x3c5 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x316 and fcsr == 0x60 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7b4b; op2val:0x37c5;
op3val:0x7716; valaddr_reg:x3; val_offset:2064*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 96, 0, x3, 2064*FLEN/8, x4, x1, x2)

inst_689:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x34b and fs2 == 0 and fe2 == 0x0d and fm2 == 0x3c5 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x316 and fcsr == 0x80 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7b4b; op2val:0x37c5;
op3val:0x7716; valaddr_reg:x3; val_offset:2067*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:128 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 128, 0, x3, 2067*FLEN/8, x4, x1, x2)

inst_690:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0e5 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x29a and fs3 == 0 and fe3 == 0x1e and fm3 == 0x00a and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x78e5; op2val:0x3a9a;
op3val:0x780a; valaddr_reg:x3; val_offset:2070*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 2070*FLEN/8, x4, x1, x2)

inst_691:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0e5 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x29a and fs3 == 0 and fe3 == 0x1e and fm3 == 0x00a and fcsr == 0x20 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x78e5; op2val:0x3a9a;
op3val:0x780a; valaddr_reg:x3; val_offset:2073*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:32 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 32, 0, x3, 2073*FLEN/8, x4, x1, x2)

inst_692:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0e5 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x29a and fs3 == 0 and fe3 == 0x1e and fm3 == 0x00a and fcsr == 0x40 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x78e5; op2val:0x3a9a;
op3val:0x780a; valaddr_reg:x3; val_offset:2076*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:64 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 64, 0, x3, 2076*FLEN/8, x4, x1, x2)

inst_693:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0e5 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x29a and fs3 == 0 and fe3 == 0x1e and fm3 == 0x00a and fcsr == 0x60 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x78e5; op2val:0x3a9a;
op3val:0x780a; valaddr_reg:x3; val_offset:2079*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 96, 0, x3, 2079*FLEN/8, x4, x1, x2)

inst_694:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0e5 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x29a and fs3 == 0 and fe3 == 0x1e and fm3 == 0x00a and fcsr == 0x80 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x78e5; op2val:0x3a9a;
op3val:0x780a; valaddr_reg:x3; val_offset:2082*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:128 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 128, 0, x3, 2082*FLEN/8, x4, x1, x2)

inst_695:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x018 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x169 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x18a and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7818; op2val:0x3d69;
op3val:0x798a; valaddr_reg:x3; val_offset:2085*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 2085*FLEN/8, x4, x1, x2)

inst_696:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x018 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x169 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x18a and fcsr == 0x20 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7818; op2val:0x3d69;
op3val:0x798a; valaddr_reg:x3; val_offset:2088*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:32 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 32, 0, x3, 2088*FLEN/8, x4, x1, x2)

inst_697:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x018 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x169 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x18a and fcsr == 0x40 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7818; op2val:0x3d69;
op3val:0x798a; valaddr_reg:x3; val_offset:2091*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:64 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 64, 0, x3, 2091*FLEN/8, x4, x1, x2)

inst_698:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x018 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x169 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x18a and fcsr == 0x60 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7818; op2val:0x3d69;
op3val:0x798a; valaddr_reg:x3; val_offset:2094*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 96, 0, x3, 2094*FLEN/8, x4, x1, x2)

inst_699:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x018 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x169 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x18a and fcsr == 0x80 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7818; op2val:0x3d69;
op3val:0x798a; valaddr_reg:x3; val_offset:2097*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:128 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 128, 0, x3, 2097*FLEN/8, x4, x1, x2)

inst_700:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x33b and fs2 == 0 and fe2 == 0x0f and fm2 == 0x0b7 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x043 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x773b; op2val:0x3cb7;
op3val:0x7843; valaddr_reg:x3; val_offset:2100*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 2100*FLEN/8, x4, x1, x2)

inst_701:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x33b and fs2 == 0 and fe2 == 0x0f and fm2 == 0x0b7 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x043 and fcsr == 0x20 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x773b; op2val:0x3cb7;
op3val:0x7843; valaddr_reg:x3; val_offset:2103*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:32 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 32, 0, x3, 2103*FLEN/8, x4, x1, x2)

inst_702:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x33b and fs2 == 0 and fe2 == 0x0f and fm2 == 0x0b7 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x043 and fcsr == 0x40 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x773b; op2val:0x3cb7;
op3val:0x7843; valaddr_reg:x3; val_offset:2106*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:64 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 64, 0, x3, 2106*FLEN/8, x4, x1, x2)

inst_703:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x33b and fs2 == 0 and fe2 == 0x0f and fm2 == 0x0b7 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x043 and fcsr == 0x60 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x773b; op2val:0x3cb7;
op3val:0x7843; valaddr_reg:x3; val_offset:2109*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 96, 0, x3, 2109*FLEN/8, x4, x1, x2)

inst_704:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x33b and fs2 == 0 and fe2 == 0x0f and fm2 == 0x0b7 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x043 and fcsr == 0x80 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x773b; op2val:0x3cb7;
op3val:0x7843; valaddr_reg:x3; val_offset:2112*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:128 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 128, 0, x3, 2112*FLEN/8, x4, x1, x2)

inst_705:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x3a5 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x3e0 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x387 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x77a5; op2val:0x3fe0;
op3val:0x7b87; valaddr_reg:x3; val_offset:2115*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 2115*FLEN/8, x4, x1, x2)

inst_706:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x3a5 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x3e0 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x387 and fcsr == 0x20 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x77a5; op2val:0x3fe0;
op3val:0x7b87; valaddr_reg:x3; val_offset:2118*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:32 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 32, 0, x3, 2118*FLEN/8, x4, x1, x2)

inst_707:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x3a5 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x3e0 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x387 and fcsr == 0x40 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x77a5; op2val:0x3fe0;
op3val:0x7b87; valaddr_reg:x3; val_offset:2121*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:64 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 64, 0, x3, 2121*FLEN/8, x4, x1, x2)

inst_708:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x3a5 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x3e0 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x387 and fcsr == 0x60 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x77a5; op2val:0x3fe0;
op3val:0x7b87; valaddr_reg:x3; val_offset:2124*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 96, 0, x3, 2124*FLEN/8, x4, x1, x2)

inst_709:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x3a5 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x3e0 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x387 and fcsr == 0x80 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x77a5; op2val:0x3fe0;
op3val:0x7b87; valaddr_reg:x3; val_offset:2127*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:128 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 128, 0, x3, 2127*FLEN/8, x4, x1, x2)

inst_710:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x197 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x103 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x302 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7997; op2val:0x3d03;
op3val:0x7b02; valaddr_reg:x3; val_offset:2130*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 2130*FLEN/8, x4, x1, x2)

inst_711:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x197 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x103 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x302 and fcsr == 0x20 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7997; op2val:0x3d03;
op3val:0x7b02; valaddr_reg:x3; val_offset:2133*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:32 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 32, 0, x3, 2133*FLEN/8, x4, x1, x2)

inst_712:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x197 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x103 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x302 and fcsr == 0x40 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7997; op2val:0x3d03;
op3val:0x7b02; valaddr_reg:x3; val_offset:2136*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:64 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 64, 0, x3, 2136*FLEN/8, x4, x1, x2)

inst_713:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x197 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x103 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x302 and fcsr == 0x60 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7997; op2val:0x3d03;
op3val:0x7b02; valaddr_reg:x3; val_offset:2139*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 96, 0, x3, 2139*FLEN/8, x4, x1, x2)

inst_714:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x197 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x103 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x302 and fcsr == 0x80 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7997; op2val:0x3d03;
op3val:0x7b02; valaddr_reg:x3; val_offset:2142*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:128 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 128, 0, x3, 2142*FLEN/8, x4, x1, x2)

inst_715:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x388 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x068 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x026 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7b88; op2val:0x3468;
op3val:0x7426; valaddr_reg:x3; val_offset:2145*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 2145*FLEN/8, x4, x1, x2)

inst_716:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x388 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x068 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x026 and fcsr == 0x20 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7b88; op2val:0x3468;
op3val:0x7426; valaddr_reg:x3; val_offset:2148*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:32 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 32, 0, x3, 2148*FLEN/8, x4, x1, x2)

inst_717:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x388 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x068 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x026 and fcsr == 0x40 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7b88; op2val:0x3468;
op3val:0x7426; valaddr_reg:x3; val_offset:2151*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:64 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 64, 0, x3, 2151*FLEN/8, x4, x1, x2)

inst_718:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x388 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x068 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x026 and fcsr == 0x60 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7b88; op2val:0x3468;
op3val:0x7426; valaddr_reg:x3; val_offset:2154*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 96, 0, x3, 2154*FLEN/8, x4, x1, x2)

inst_719:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x388 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x068 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x026 and fcsr == 0x80 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7b88; op2val:0x3468;
op3val:0x7426; valaddr_reg:x3; val_offset:2157*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:128 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 128, 0, x3, 2157*FLEN/8, x4, x1, x2)

inst_720:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x079 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x2be and fs3 == 0 and fe3 == 0x1e and fm3 == 0x38a and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7879; op2val:0x3ebe;
op3val:0x7b8a; valaddr_reg:x3; val_offset:2160*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 2160*FLEN/8, x4, x1, x2)

inst_721:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x079 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x2be and fs3 == 0 and fe3 == 0x1e and fm3 == 0x38a and fcsr == 0x20 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7879; op2val:0x3ebe;
op3val:0x7b8a; valaddr_reg:x3; val_offset:2163*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:32 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 32, 0, x3, 2163*FLEN/8, x4, x1, x2)

inst_722:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x079 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x2be and fs3 == 0 and fe3 == 0x1e and fm3 == 0x38a and fcsr == 0x40 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7879; op2val:0x3ebe;
op3val:0x7b8a; valaddr_reg:x3; val_offset:2166*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:64 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 64, 0, x3, 2166*FLEN/8, x4, x1, x2)

inst_723:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x079 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x2be and fs3 == 0 and fe3 == 0x1e and fm3 == 0x38a and fcsr == 0x60 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7879; op2val:0x3ebe;
op3val:0x7b8a; valaddr_reg:x3; val_offset:2169*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 96, 0, x3, 2169*FLEN/8, x4, x1, x2)

inst_724:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x079 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x2be and fs3 == 0 and fe3 == 0x1e and fm3 == 0x38a and fcsr == 0x80 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7879; op2val:0x3ebe;
op3val:0x7b8a; valaddr_reg:x3; val_offset:2172*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:128 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 128, 0, x3, 2172*FLEN/8, x4, x1, x2)

inst_725:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2b7 and fs2 == 0 and fe2 == 0x0c and fm2 == 0x139 and fs3 == 0 and fe3 == 0x1c and fm3 == 0x062 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7ab7; op2val:0x3139;
op3val:0x7062; valaddr_reg:x3; val_offset:2175*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 2175*FLEN/8, x4, x1, x2)

inst_726:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2b7 and fs2 == 0 and fe2 == 0x0c and fm2 == 0x139 and fs3 == 0 and fe3 == 0x1c and fm3 == 0x062 and fcsr == 0x20 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7ab7; op2val:0x3139;
op3val:0x7062; valaddr_reg:x3; val_offset:2178*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:32 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 32, 0, x3, 2178*FLEN/8, x4, x1, x2)

inst_727:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2b7 and fs2 == 0 and fe2 == 0x0c and fm2 == 0x139 and fs3 == 0 and fe3 == 0x1c and fm3 == 0x062 and fcsr == 0x40 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7ab7; op2val:0x3139;
op3val:0x7062; valaddr_reg:x3; val_offset:2181*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:64 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 64, 0, x3, 2181*FLEN/8, x4, x1, x2)

inst_728:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2b7 and fs2 == 0 and fe2 == 0x0c and fm2 == 0x139 and fs3 == 0 and fe3 == 0x1c and fm3 == 0x062 and fcsr == 0x60 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7ab7; op2val:0x3139;
op3val:0x7062; valaddr_reg:x3; val_offset:2184*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 96, 0, x3, 2184*FLEN/8, x4, x1, x2)

inst_729:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2b7 and fs2 == 0 and fe2 == 0x0c and fm2 == 0x139 and fs3 == 0 and fe3 == 0x1c and fm3 == 0x062 and fcsr == 0x80 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7ab7; op2val:0x3139;
op3val:0x7062; valaddr_reg:x3; val_offset:2187*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:128 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 128, 0, x3, 2187*FLEN/8, x4, x1, x2)

inst_730:
// fs1 == 0 and fe1 == 0x1b and fm1 == 0x3c7 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x345 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x312 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x6fc7; op2val:0x4345;
op3val:0x7712; valaddr_reg:x3; val_offset:2190*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 2190*FLEN/8, x4, x1, x2)

inst_731:
// fs1 == 0 and fe1 == 0x1b and fm1 == 0x3c7 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x345 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x312 and fcsr == 0x20 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x6fc7; op2val:0x4345;
op3val:0x7712; valaddr_reg:x3; val_offset:2193*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:32 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 32, 0, x3, 2193*FLEN/8, x4, x1, x2)

inst_732:
// fs1 == 0 and fe1 == 0x1b and fm1 == 0x3c7 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x345 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x312 and fcsr == 0x40 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x6fc7; op2val:0x4345;
op3val:0x7712; valaddr_reg:x3; val_offset:2196*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:64 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 64, 0, x3, 2196*FLEN/8, x4, x1, x2)

inst_733:
// fs1 == 0 and fe1 == 0x1b and fm1 == 0x3c7 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x345 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x312 and fcsr == 0x60 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x6fc7; op2val:0x4345;
op3val:0x7712; valaddr_reg:x3; val_offset:2199*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 96, 0, x3, 2199*FLEN/8, x4, x1, x2)

inst_734:
// fs1 == 0 and fe1 == 0x1b and fm1 == 0x3c7 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x345 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x312 and fcsr == 0x80 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x6fc7; op2val:0x4345;
op3val:0x7712; valaddr_reg:x3; val_offset:2202*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:128 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 128, 0, x3, 2202*FLEN/8, x4, x1, x2)

inst_735:
// fs1 == 0 and fe1 == 0x1b and fm1 == 0x0a4 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x2a2 and fs3 == 0 and fe3 == 0x1c and fm3 == 0x3b2 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x6ca4; op2val:0x42a2;
op3val:0x73b2; valaddr_reg:x3; val_offset:2205*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 2205*FLEN/8, x4, x1, x2)

inst_736:
// fs1 == 0 and fe1 == 0x1b and fm1 == 0x0a4 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x2a2 and fs3 == 0 and fe3 == 0x1c and fm3 == 0x3b2 and fcsr == 0x20 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x6ca4; op2val:0x42a2;
op3val:0x73b2; valaddr_reg:x3; val_offset:2208*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:32 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 32, 0, x3, 2208*FLEN/8, x4, x1, x2)

inst_737:
// fs1 == 0 and fe1 == 0x1b and fm1 == 0x0a4 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x2a2 and fs3 == 0 and fe3 == 0x1c and fm3 == 0x3b2 and fcsr == 0x40 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x6ca4; op2val:0x42a2;
op3val:0x73b2; valaddr_reg:x3; val_offset:2211*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:64 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 64, 0, x3, 2211*FLEN/8, x4, x1, x2)

inst_738:
// fs1 == 0 and fe1 == 0x1b and fm1 == 0x0a4 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x2a2 and fs3 == 0 and fe3 == 0x1c and fm3 == 0x3b2 and fcsr == 0x60 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x6ca4; op2val:0x42a2;
op3val:0x73b2; valaddr_reg:x3; val_offset:2214*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 96, 0, x3, 2214*FLEN/8, x4, x1, x2)

inst_739:
// fs1 == 0 and fe1 == 0x1b and fm1 == 0x0a4 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x2a2 and fs3 == 0 and fe3 == 0x1c and fm3 == 0x3b2 and fcsr == 0x80 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x6ca4; op2val:0x42a2;
op3val:0x73b2; valaddr_reg:x3; val_offset:2217*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:128 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 128, 0, x3, 2217*FLEN/8, x4, x1, x2)

inst_740:
// fs1 == 0 and fe1 == 0x1b and fm1 == 0x0ad and fs2 == 0 and fe2 == 0x12 and fm2 == 0x093 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x15a and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x6cad; op2val:0x4893;
op3val:0x795a; valaddr_reg:x3; val_offset:2220*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 2220*FLEN/8, x4, x1, x2)

inst_741:
// fs1 == 0 and fe1 == 0x1b and fm1 == 0x0ad and fs2 == 0 and fe2 == 0x12 and fm2 == 0x093 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x15a and fcsr == 0x20 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x6cad; op2val:0x4893;
op3val:0x795a; valaddr_reg:x3; val_offset:2223*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:32 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 32, 0, x3, 2223*FLEN/8, x4, x1, x2)

inst_742:
// fs1 == 0 and fe1 == 0x1b and fm1 == 0x0ad and fs2 == 0 and fe2 == 0x12 and fm2 == 0x093 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x15a and fcsr == 0x40 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x6cad; op2val:0x4893;
op3val:0x795a; valaddr_reg:x3; val_offset:2226*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:64 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 64, 0, x3, 2226*FLEN/8, x4, x1, x2)

inst_743:
// fs1 == 0 and fe1 == 0x1b and fm1 == 0x0ad and fs2 == 0 and fe2 == 0x12 and fm2 == 0x093 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x15a and fcsr == 0x60 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x6cad; op2val:0x4893;
op3val:0x795a; valaddr_reg:x3; val_offset:2229*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 96, 0, x3, 2229*FLEN/8, x4, x1, x2)

inst_744:
// fs1 == 0 and fe1 == 0x1b and fm1 == 0x0ad and fs2 == 0 and fe2 == 0x12 and fm2 == 0x093 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x15a and fcsr == 0x80 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x6cad; op2val:0x4893;
op3val:0x795a; valaddr_reg:x3; val_offset:2232*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:128 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 128, 0, x3, 2232*FLEN/8, x4, x1, x2)

inst_745:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x244 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x093 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x32c and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7a44; op2val:0x3c93;
op3val:0x7b2c; valaddr_reg:x3; val_offset:2235*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 2235*FLEN/8, x4, x1, x2)

inst_746:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x244 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x093 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x32c and fcsr == 0x20 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7a44; op2val:0x3c93;
op3val:0x7b2c; valaddr_reg:x3; val_offset:2238*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:32 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 32, 0, x3, 2238*FLEN/8, x4, x1, x2)

inst_747:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x244 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x093 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x32c and fcsr == 0x40 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7a44; op2val:0x3c93;
op3val:0x7b2c; valaddr_reg:x3; val_offset:2241*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:64 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 64, 0, x3, 2241*FLEN/8, x4, x1, x2)

inst_748:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x244 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x093 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x32c and fcsr == 0x60 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7a44; op2val:0x3c93;
op3val:0x7b2c; valaddr_reg:x3; val_offset:2244*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 96, 0, x3, 2244*FLEN/8, x4, x1, x2)

inst_749:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x244 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x093 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x32c and fcsr == 0x80 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7a44; op2val:0x3c93;
op3val:0x7b2c; valaddr_reg:x3; val_offset:2247*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:128 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 128, 0, x3, 2247*FLEN/8, x4, x1, x2)

inst_750:
// fs1 == 0 and fe1 == 0x1c and fm1 == 0x0f0 and fs2 == 0 and fe2 == 0x11 and fm2 == 0x0a2 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x1b9 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x70f0; op2val:0x44a2;
op3val:0x79b9; valaddr_reg:x3; val_offset:2250*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 2250*FLEN/8, x4, x1, x2)

inst_751:
// fs1 == 0 and fe1 == 0x1c and fm1 == 0x0f0 and fs2 == 0 and fe2 == 0x11 and fm2 == 0x0a2 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x1b9 and fcsr == 0x20 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x70f0; op2val:0x44a2;
op3val:0x79b9; valaddr_reg:x3; val_offset:2253*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:32 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 32, 0, x3, 2253*FLEN/8, x4, x1, x2)

inst_752:
// fs1 == 0 and fe1 == 0x1c and fm1 == 0x0f0 and fs2 == 0 and fe2 == 0x11 and fm2 == 0x0a2 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x1b9 and fcsr == 0x40 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x70f0; op2val:0x44a2;
op3val:0x79b9; valaddr_reg:x3; val_offset:2256*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:64 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 64, 0, x3, 2256*FLEN/8, x4, x1, x2)

inst_753:
// fs1 == 0 and fe1 == 0x1c and fm1 == 0x0f0 and fs2 == 0 and fe2 == 0x11 and fm2 == 0x0a2 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x1b9 and fcsr == 0x60 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x70f0; op2val:0x44a2;
op3val:0x79b9; valaddr_reg:x3; val_offset:2259*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 96, 0, x3, 2259*FLEN/8, x4, x1, x2)

inst_754:
// fs1 == 0 and fe1 == 0x1c and fm1 == 0x0f0 and fs2 == 0 and fe2 == 0x11 and fm2 == 0x0a2 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x1b9 and fcsr == 0x80 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x70f0; op2val:0x44a2;
op3val:0x79b9; valaddr_reg:x3; val_offset:2262*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:128 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 128, 0, x3, 2262*FLEN/8, x4, x1, x2)

inst_755:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x147 and fs2 == 0 and fe2 == 0x0c and fm2 == 0x2ee and fs3 == 0 and fe3 == 0x1c and fm3 == 0x092 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7947; op2val:0x32ee;
op3val:0x7092; valaddr_reg:x3; val_offset:2265*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 2265*FLEN/8, x4, x1, x2)

inst_756:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x147 and fs2 == 0 and fe2 == 0x0c and fm2 == 0x2ee and fs3 == 0 and fe3 == 0x1c and fm3 == 0x092 and fcsr == 0x20 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7947; op2val:0x32ee;
op3val:0x7092; valaddr_reg:x3; val_offset:2268*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:32 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 32, 0, x3, 2268*FLEN/8, x4, x1, x2)

inst_757:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x147 and fs2 == 0 and fe2 == 0x0c and fm2 == 0x2ee and fs3 == 0 and fe3 == 0x1c and fm3 == 0x092 and fcsr == 0x40 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7947; op2val:0x32ee;
op3val:0x7092; valaddr_reg:x3; val_offset:2271*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:64 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 64, 0, x3, 2271*FLEN/8, x4, x1, x2)

inst_758:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x147 and fs2 == 0 and fe2 == 0x0c and fm2 == 0x2ee and fs3 == 0 and fe3 == 0x1c and fm3 == 0x092 and fcsr == 0x60 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7947; op2val:0x32ee;
op3val:0x7092; valaddr_reg:x3; val_offset:2274*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 96, 0, x3, 2274*FLEN/8, x4, x1, x2)

inst_759:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x147 and fs2 == 0 and fe2 == 0x0c and fm2 == 0x2ee and fs3 == 0 and fe3 == 0x1c and fm3 == 0x092 and fcsr == 0x80 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7947; op2val:0x32ee;
op3val:0x7092; valaddr_reg:x3; val_offset:2277*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:128 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 128, 0, x3, 2277*FLEN/8, x4, x1, x2)

inst_760:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x30f and fs2 == 0 and fe2 == 0x0f and fm2 == 0x062 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3bc and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7b0f; op2val:0x3c62;
op3val:0x7bbc; valaddr_reg:x3; val_offset:2280*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 2280*FLEN/8, x4, x1, x2)

inst_761:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x30f and fs2 == 0 and fe2 == 0x0f and fm2 == 0x062 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3bc and fcsr == 0x20 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7b0f; op2val:0x3c62;
op3val:0x7bbc; valaddr_reg:x3; val_offset:2283*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:32 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 32, 0, x3, 2283*FLEN/8, x4, x1, x2)

inst_762:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x30f and fs2 == 0 and fe2 == 0x0f and fm2 == 0x062 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3bc and fcsr == 0x40 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7b0f; op2val:0x3c62;
op3val:0x7bbc; valaddr_reg:x3; val_offset:2286*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:64 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 64, 0, x3, 2286*FLEN/8, x4, x1, x2)

inst_763:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x30f and fs2 == 0 and fe2 == 0x0f and fm2 == 0x062 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3bc and fcsr == 0x60 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7b0f; op2val:0x3c62;
op3val:0x7bbc; valaddr_reg:x3; val_offset:2289*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 96, 0, x3, 2289*FLEN/8, x4, x1, x2)

inst_764:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x30f and fs2 == 0 and fe2 == 0x0f and fm2 == 0x062 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3bc and fcsr == 0x80 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7b0f; op2val:0x3c62;
op3val:0x7bbc; valaddr_reg:x3; val_offset:2292*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:128 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 128, 0, x3, 2292*FLEN/8, x4, x1, x2)

inst_765:
// fs1 == 0 and fe1 == 0x1c and fm1 == 0x306 and fs2 == 0 and fe2 == 0x11 and fm2 == 0x056 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x39d and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7306; op2val:0x4456;
op3val:0x7b9d; valaddr_reg:x3; val_offset:2295*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 2295*FLEN/8, x4, x1, x2)

inst_766:
// fs1 == 0 and fe1 == 0x1c and fm1 == 0x306 and fs2 == 0 and fe2 == 0x11 and fm2 == 0x056 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x39d and fcsr == 0x20 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7306; op2val:0x4456;
op3val:0x7b9d; valaddr_reg:x3; val_offset:2298*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:32 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 32, 0, x3, 2298*FLEN/8, x4, x1, x2)

inst_767:
// fs1 == 0 and fe1 == 0x1c and fm1 == 0x306 and fs2 == 0 and fe2 == 0x11 and fm2 == 0x056 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x39d and fcsr == 0x40 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7306; op2val:0x4456;
op3val:0x7b9d; valaddr_reg:x3; val_offset:2301*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:64 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 64, 0, x3, 2301*FLEN/8, x4, x1, x2)
RVTEST_SIGBASE(x1,signature_x1_7)

inst_768:
// fs1 == 0 and fe1 == 0x1c and fm1 == 0x306 and fs2 == 0 and fe2 == 0x11 and fm2 == 0x056 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x39d and fcsr == 0x60 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7306; op2val:0x4456;
op3val:0x7b9d; valaddr_reg:x3; val_offset:2304*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 96, 0, x3, 2304*FLEN/8, x4, x1, x2)

inst_769:
// fs1 == 0 and fe1 == 0x1c and fm1 == 0x306 and fs2 == 0 and fe2 == 0x11 and fm2 == 0x056 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x39d and fcsr == 0x80 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7306; op2val:0x4456;
op3val:0x7b9d; valaddr_reg:x3; val_offset:2307*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:128 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 128, 0, x3, 2307*FLEN/8, x4, x1, x2)

inst_770:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x25e and fs2 == 0 and fe2 == 0x0f and fm2 == 0x0e4 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x3ca and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x765e; op2val:0x3ce4;
op3val:0x77ca; valaddr_reg:x3; val_offset:2310*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 2310*FLEN/8, x4, x1, x2)

inst_771:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x25e and fs2 == 0 and fe2 == 0x0f and fm2 == 0x0e4 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x3ca and fcsr == 0x20 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x765e; op2val:0x3ce4;
op3val:0x77ca; valaddr_reg:x3; val_offset:2313*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:32 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 32, 0, x3, 2313*FLEN/8, x4, x1, x2)

inst_772:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x25e and fs2 == 0 and fe2 == 0x0f and fm2 == 0x0e4 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x3ca and fcsr == 0x40 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x765e; op2val:0x3ce4;
op3val:0x77ca; valaddr_reg:x3; val_offset:2316*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:64 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 64, 0, x3, 2316*FLEN/8, x4, x1, x2)

inst_773:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x25e and fs2 == 0 and fe2 == 0x0f and fm2 == 0x0e4 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x3ca and fcsr == 0x60 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x765e; op2val:0x3ce4;
op3val:0x77ca; valaddr_reg:x3; val_offset:2319*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 96, 0, x3, 2319*FLEN/8, x4, x1, x2)

inst_774:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x25e and fs2 == 0 and fe2 == 0x0f and fm2 == 0x0e4 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x3ca and fcsr == 0x80 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x765e; op2val:0x3ce4;
op3val:0x77ca; valaddr_reg:x3; val_offset:2322*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:128 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 128, 0, x3, 2322*FLEN/8, x4, x1, x2)

inst_775:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ea and fs2 == 0 and fe2 == 0x0e and fm2 == 0x2ba and fs3 == 0 and fe3 == 0x1e and fm3 == 0x2a8 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7bea; op2val:0x3aba;
op3val:0x7aa8; valaddr_reg:x3; val_offset:2325*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 2325*FLEN/8, x4, x1, x2)

inst_776:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ea and fs2 == 0 and fe2 == 0x0e and fm2 == 0x2ba and fs3 == 0 and fe3 == 0x1e and fm3 == 0x2a8 and fcsr == 0x20 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7bea; op2val:0x3aba;
op3val:0x7aa8; valaddr_reg:x3; val_offset:2328*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:32 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 32, 0, x3, 2328*FLEN/8, x4, x1, x2)

inst_777:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ea and fs2 == 0 and fe2 == 0x0e and fm2 == 0x2ba and fs3 == 0 and fe3 == 0x1e and fm3 == 0x2a8 and fcsr == 0x40 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7bea; op2val:0x3aba;
op3val:0x7aa8; valaddr_reg:x3; val_offset:2331*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:64 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 64, 0, x3, 2331*FLEN/8, x4, x1, x2)

inst_778:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ea and fs2 == 0 and fe2 == 0x0e and fm2 == 0x2ba and fs3 == 0 and fe3 == 0x1e and fm3 == 0x2a8 and fcsr == 0x60 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7bea; op2val:0x3aba;
op3val:0x7aa8; valaddr_reg:x3; val_offset:2334*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 96, 0, x3, 2334*FLEN/8, x4, x1, x2)

inst_779:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ea and fs2 == 0 and fe2 == 0x0e and fm2 == 0x2ba and fs3 == 0 and fe3 == 0x1e and fm3 == 0x2a8 and fcsr == 0x80 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7bea; op2val:0x3aba;
op3val:0x7aa8; valaddr_reg:x3; val_offset:2337*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:128 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 128, 0, x3, 2337*FLEN/8, x4, x1, x2)

inst_780:
// fs1 == 0 and fe1 == 0x1c and fm1 == 0x12a and fs2 == 0 and fe2 == 0x10 and fm2 == 0x158 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x2e6 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x712a; op2val:0x4158;
op3val:0x76e6; valaddr_reg:x3; val_offset:2340*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 2340*FLEN/8, x4, x1, x2)

inst_781:
// fs1 == 0 and fe1 == 0x1c and fm1 == 0x12a and fs2 == 0 and fe2 == 0x10 and fm2 == 0x158 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x2e6 and fcsr == 0x20 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x712a; op2val:0x4158;
op3val:0x76e6; valaddr_reg:x3; val_offset:2343*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:32 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 32, 0, x3, 2343*FLEN/8, x4, x1, x2)

inst_782:
// fs1 == 0 and fe1 == 0x1c and fm1 == 0x12a and fs2 == 0 and fe2 == 0x10 and fm2 == 0x158 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x2e6 and fcsr == 0x40 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x712a; op2val:0x4158;
op3val:0x76e6; valaddr_reg:x3; val_offset:2346*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:64 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 64, 0, x3, 2346*FLEN/8, x4, x1, x2)

inst_783:
// fs1 == 0 and fe1 == 0x1c and fm1 == 0x12a and fs2 == 0 and fe2 == 0x10 and fm2 == 0x158 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x2e6 and fcsr == 0x60 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x712a; op2val:0x4158;
op3val:0x76e6; valaddr_reg:x3; val_offset:2349*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 96, 0, x3, 2349*FLEN/8, x4, x1, x2)

inst_784:
// fs1 == 0 and fe1 == 0x1c and fm1 == 0x12a and fs2 == 0 and fe2 == 0x10 and fm2 == 0x158 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x2e6 and fcsr == 0x80 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x712a; op2val:0x4158;
op3val:0x76e6; valaddr_reg:x3; val_offset:2352*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:128 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 128, 0, x3, 2352*FLEN/8, x4, x1, x2)

inst_785:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x01f and fs2 == 0 and fe2 == 0x0e and fm2 == 0x143 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x16c and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x781f; op2val:0x3943;
op3val:0x756c; valaddr_reg:x3; val_offset:2355*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 2355*FLEN/8, x4, x1, x2)

inst_786:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x01f and fs2 == 0 and fe2 == 0x0e and fm2 == 0x143 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x16c and fcsr == 0x20 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x781f; op2val:0x3943;
op3val:0x756c; valaddr_reg:x3; val_offset:2358*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:32 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 32, 0, x3, 2358*FLEN/8, x4, x1, x2)

inst_787:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x01f and fs2 == 0 and fe2 == 0x0e and fm2 == 0x143 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x16c and fcsr == 0x40 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x781f; op2val:0x3943;
op3val:0x756c; valaddr_reg:x3; val_offset:2361*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:64 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 64, 0, x3, 2361*FLEN/8, x4, x1, x2)

inst_788:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x01f and fs2 == 0 and fe2 == 0x0e and fm2 == 0x143 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x16c and fcsr == 0x60 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x781f; op2val:0x3943;
op3val:0x756c; valaddr_reg:x3; val_offset:2364*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 96, 0, x3, 2364*FLEN/8, x4, x1, x2)

inst_789:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x01f and fs2 == 0 and fe2 == 0x0e and fm2 == 0x143 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x16c and fcsr == 0x80 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x781f; op2val:0x3943;
op3val:0x756c; valaddr_reg:x3; val_offset:2367*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:128 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 128, 0, x3, 2367*FLEN/8, x4, x1, x2)

inst_790:
// fs1 == 0 and fe1 == 0x1c and fm1 == 0x242 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x282 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x118 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7242; op2val:0x3e82;
op3val:0x7518; valaddr_reg:x3; val_offset:2370*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 2370*FLEN/8, x4, x1, x2)

inst_791:
// fs1 == 0 and fe1 == 0x1c and fm1 == 0x242 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x282 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x118 and fcsr == 0x20 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7242; op2val:0x3e82;
op3val:0x7518; valaddr_reg:x3; val_offset:2373*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:32 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 32, 0, x3, 2373*FLEN/8, x4, x1, x2)

inst_792:
// fs1 == 0 and fe1 == 0x1c and fm1 == 0x242 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x282 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x118 and fcsr == 0x40 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7242; op2val:0x3e82;
op3val:0x7518; valaddr_reg:x3; val_offset:2376*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:64 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 64, 0, x3, 2376*FLEN/8, x4, x1, x2)

inst_793:
// fs1 == 0 and fe1 == 0x1c and fm1 == 0x242 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x282 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x118 and fcsr == 0x60 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7242; op2val:0x3e82;
op3val:0x7518; valaddr_reg:x3; val_offset:2379*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 96, 0, x3, 2379*FLEN/8, x4, x1, x2)

inst_794:
// fs1 == 0 and fe1 == 0x1c and fm1 == 0x242 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x282 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x118 and fcsr == 0x80 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7242; op2val:0x3e82;
op3val:0x7518; valaddr_reg:x3; val_offset:2382*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:128 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 128, 0, x3, 2382*FLEN/8, x4, x1, x2)

inst_795:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1c6 and fs2 == 0 and fe2 == 0x09 and fm2 == 0x2e9 and fs3 == 0 and fe3 == 0x19 and fm3 == 0x0fd and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x79c6; op2val:0x26e9;
op3val:0x64fd; valaddr_reg:x3; val_offset:2385*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 2385*FLEN/8, x4, x1, x2)

inst_796:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1c6 and fs2 == 0 and fe2 == 0x09 and fm2 == 0x2e9 and fs3 == 0 and fe3 == 0x19 and fm3 == 0x0fd and fcsr == 0x20 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x79c6; op2val:0x26e9;
op3val:0x64fd; valaddr_reg:x3; val_offset:2388*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:32 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 32, 0, x3, 2388*FLEN/8, x4, x1, x2)

inst_797:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1c6 and fs2 == 0 and fe2 == 0x09 and fm2 == 0x2e9 and fs3 == 0 and fe3 == 0x19 and fm3 == 0x0fd and fcsr == 0x40 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x79c6; op2val:0x26e9;
op3val:0x64fd; valaddr_reg:x3; val_offset:2391*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:64 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 64, 0, x3, 2391*FLEN/8, x4, x1, x2)

inst_798:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1c6 and fs2 == 0 and fe2 == 0x09 and fm2 == 0x2e9 and fs3 == 0 and fe3 == 0x19 and fm3 == 0x0fd and fcsr == 0x60 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x79c6; op2val:0x26e9;
op3val:0x64fd; valaddr_reg:x3; val_offset:2394*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 96, 0, x3, 2394*FLEN/8, x4, x1, x2)

inst_799:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1c6 and fs2 == 0 and fe2 == 0x09 and fm2 == 0x2e9 and fs3 == 0 and fe3 == 0x19 and fm3 == 0x0fd and fcsr == 0x80 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x79c6; op2val:0x26e9;
op3val:0x64fd; valaddr_reg:x3; val_offset:2397*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:128 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 128, 0, x3, 2397*FLEN/8, x4, x1, x2)

inst_800:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x06e and fs2 == 0 and fe2 == 0x0e and fm2 == 0x25c and fs3 == 0 and fe3 == 0x1d and fm3 == 0x30b and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x786e; op2val:0x3a5c;
op3val:0x770b; valaddr_reg:x3; val_offset:2400*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 2400*FLEN/8, x4, x1, x2)

inst_801:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x06e and fs2 == 0 and fe2 == 0x0e and fm2 == 0x25c and fs3 == 0 and fe3 == 0x1d and fm3 == 0x30b and fcsr == 0x20 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x786e; op2val:0x3a5c;
op3val:0x770b; valaddr_reg:x3; val_offset:2403*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:32 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 32, 0, x3, 2403*FLEN/8, x4, x1, x2)

inst_802:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x06e and fs2 == 0 and fe2 == 0x0e and fm2 == 0x25c and fs3 == 0 and fe3 == 0x1d and fm3 == 0x30b and fcsr == 0x40 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x786e; op2val:0x3a5c;
op3val:0x770b; valaddr_reg:x3; val_offset:2406*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:64 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 64, 0, x3, 2406*FLEN/8, x4, x1, x2)

inst_803:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x06e and fs2 == 0 and fe2 == 0x0e and fm2 == 0x25c and fs3 == 0 and fe3 == 0x1d and fm3 == 0x30b and fcsr == 0x60 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x786e; op2val:0x3a5c;
op3val:0x770b; valaddr_reg:x3; val_offset:2409*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 96, 0, x3, 2409*FLEN/8, x4, x1, x2)

inst_804:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x06e and fs2 == 0 and fe2 == 0x0e and fm2 == 0x25c and fs3 == 0 and fe3 == 0x1d and fm3 == 0x30b and fcsr == 0x80 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x786e; op2val:0x3a5c;
op3val:0x770b; valaddr_reg:x3; val_offset:2412*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:128 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 128, 0, x3, 2412*FLEN/8, x4, x1, x2)

inst_805:
// fs1 == 0 and fe1 == 0x19 and fm1 == 0x0a1 and fs2 == 0 and fe2 == 0x13 and fm2 == 0x094 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x14d and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x64a1; op2val:0x4c94;
op3val:0x754d; valaddr_reg:x3; val_offset:2415*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 2415*FLEN/8, x4, x1, x2)

inst_806:
// fs1 == 0 and fe1 == 0x19 and fm1 == 0x0a1 and fs2 == 0 and fe2 == 0x13 and fm2 == 0x094 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x14d and fcsr == 0x20 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x64a1; op2val:0x4c94;
op3val:0x754d; valaddr_reg:x3; val_offset:2418*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:32 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 32, 0, x3, 2418*FLEN/8, x4, x1, x2)

inst_807:
// fs1 == 0 and fe1 == 0x19 and fm1 == 0x0a1 and fs2 == 0 and fe2 == 0x13 and fm2 == 0x094 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x14d and fcsr == 0x40 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x64a1; op2val:0x4c94;
op3val:0x754d; valaddr_reg:x3; val_offset:2421*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:64 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 64, 0, x3, 2421*FLEN/8, x4, x1, x2)

inst_808:
// fs1 == 0 and fe1 == 0x19 and fm1 == 0x0a1 and fs2 == 0 and fe2 == 0x13 and fm2 == 0x094 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x14d and fcsr == 0x60 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x64a1; op2val:0x4c94;
op3val:0x754d; valaddr_reg:x3; val_offset:2424*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 96, 0, x3, 2424*FLEN/8, x4, x1, x2)

inst_809:
// fs1 == 0 and fe1 == 0x19 and fm1 == 0x0a1 and fs2 == 0 and fe2 == 0x13 and fm2 == 0x094 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x14d and fcsr == 0x80 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x64a1; op2val:0x4c94;
op3val:0x754d; valaddr_reg:x3; val_offset:2427*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:128 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 128, 0, x3, 2427*FLEN/8, x4, x1, x2)

inst_810:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0fd and fs2 == 0 and fe2 == 0x0e and fm2 == 0x291 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x018 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x78fd; op2val:0x3a91;
op3val:0x7818; valaddr_reg:x3; val_offset:2430*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 2430*FLEN/8, x4, x1, x2)

inst_811:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0fd and fs2 == 0 and fe2 == 0x0e and fm2 == 0x291 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x018 and fcsr == 0x20 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x78fd; op2val:0x3a91;
op3val:0x7818; valaddr_reg:x3; val_offset:2433*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:32 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 32, 0, x3, 2433*FLEN/8, x4, x1, x2)

inst_812:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0fd and fs2 == 0 and fe2 == 0x0e and fm2 == 0x291 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x018 and fcsr == 0x40 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x78fd; op2val:0x3a91;
op3val:0x7818; valaddr_reg:x3; val_offset:2436*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:64 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 64, 0, x3, 2436*FLEN/8, x4, x1, x2)

inst_813:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0fd and fs2 == 0 and fe2 == 0x0e and fm2 == 0x291 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x018 and fcsr == 0x60 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x78fd; op2val:0x3a91;
op3val:0x7818; valaddr_reg:x3; val_offset:2439*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 96, 0, x3, 2439*FLEN/8, x4, x1, x2)

inst_814:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0fd and fs2 == 0 and fe2 == 0x0e and fm2 == 0x291 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x018 and fcsr == 0x80 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x78fd; op2val:0x3a91;
op3val:0x7818; valaddr_reg:x3; val_offset:2442*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:128 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 128, 0, x3, 2442*FLEN/8, x4, x1, x2)

inst_815:
// fs1 == 0 and fe1 == 0x1b and fm1 == 0x01d and fs2 == 0 and fe2 == 0x12 and fm2 == 0x3a8 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3e0 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x6c1d; op2val:0x4ba8;
op3val:0x7be0; valaddr_reg:x3; val_offset:2445*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 2445*FLEN/8, x4, x1, x2)

inst_816:
// fs1 == 0 and fe1 == 0x1b and fm1 == 0x01d and fs2 == 0 and fe2 == 0x12 and fm2 == 0x3a8 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3e0 and fcsr == 0x20 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x6c1d; op2val:0x4ba8;
op3val:0x7be0; valaddr_reg:x3; val_offset:2448*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:32 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 32, 0, x3, 2448*FLEN/8, x4, x1, x2)

inst_817:
// fs1 == 0 and fe1 == 0x1b and fm1 == 0x01d and fs2 == 0 and fe2 == 0x12 and fm2 == 0x3a8 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3e0 and fcsr == 0x40 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x6c1d; op2val:0x4ba8;
op3val:0x7be0; valaddr_reg:x3; val_offset:2451*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:64 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 64, 0, x3, 2451*FLEN/8, x4, x1, x2)

inst_818:
// fs1 == 0 and fe1 == 0x1b and fm1 == 0x01d and fs2 == 0 and fe2 == 0x12 and fm2 == 0x3a8 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3e0 and fcsr == 0x60 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x6c1d; op2val:0x4ba8;
op3val:0x7be0; valaddr_reg:x3; val_offset:2454*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 96, 0, x3, 2454*FLEN/8, x4, x1, x2)

inst_819:
// fs1 == 0 and fe1 == 0x1b and fm1 == 0x01d and fs2 == 0 and fe2 == 0x12 and fm2 == 0x3a8 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3e0 and fcsr == 0x80 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x6c1d; op2val:0x4ba8;
op3val:0x7be0; valaddr_reg:x3; val_offset:2457*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:128 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 128, 0, x3, 2457*FLEN/8, x4, x1, x2)

inst_820:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x24d and fs2 == 0 and fe2 == 0x0f and fm2 == 0x0ee and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3c5 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7a4d; op2val:0x3cee;
op3val:0x7bc5; valaddr_reg:x3; val_offset:2460*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 2460*FLEN/8, x4, x1, x2)

inst_821:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x24d and fs2 == 0 and fe2 == 0x0f and fm2 == 0x0ee and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3c5 and fcsr == 0x20 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7a4d; op2val:0x3cee;
op3val:0x7bc5; valaddr_reg:x3; val_offset:2463*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:32 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 32, 0, x3, 2463*FLEN/8, x4, x1, x2)

inst_822:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x24d and fs2 == 0 and fe2 == 0x0f and fm2 == 0x0ee and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3c5 and fcsr == 0x40 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7a4d; op2val:0x3cee;
op3val:0x7bc5; valaddr_reg:x3; val_offset:2466*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:64 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 64, 0, x3, 2466*FLEN/8, x4, x1, x2)

inst_823:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x24d and fs2 == 0 and fe2 == 0x0f and fm2 == 0x0ee and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3c5 and fcsr == 0x60 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7a4d; op2val:0x3cee;
op3val:0x7bc5; valaddr_reg:x3; val_offset:2469*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 96, 0, x3, 2469*FLEN/8, x4, x1, x2)

inst_824:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x24d and fs2 == 0 and fe2 == 0x0f and fm2 == 0x0ee and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3c5 and fcsr == 0x80 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7a4d; op2val:0x3cee;
op3val:0x7bc5; valaddr_reg:x3; val_offset:2472*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:128 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 128, 0, x3, 2472*FLEN/8, x4, x1, x2)

inst_825:
// fs1 == 0 and fe1 == 0x1b and fm1 == 0x2b4 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x111 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x03f and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x6eb4; op2val:0x4111;
op3val:0x743f; valaddr_reg:x3; val_offset:2475*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 2475*FLEN/8, x4, x1, x2)

inst_826:
// fs1 == 0 and fe1 == 0x1b and fm1 == 0x2b4 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x111 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x03f and fcsr == 0x20 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x6eb4; op2val:0x4111;
op3val:0x743f; valaddr_reg:x3; val_offset:2478*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:32 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 32, 0, x3, 2478*FLEN/8, x4, x1, x2)

inst_827:
// fs1 == 0 and fe1 == 0x1b and fm1 == 0x2b4 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x111 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x03f and fcsr == 0x40 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x6eb4; op2val:0x4111;
op3val:0x743f; valaddr_reg:x3; val_offset:2481*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:64 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 64, 0, x3, 2481*FLEN/8, x4, x1, x2)

inst_828:
// fs1 == 0 and fe1 == 0x1b and fm1 == 0x2b4 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x111 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x03f and fcsr == 0x60 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x6eb4; op2val:0x4111;
op3val:0x743f; valaddr_reg:x3; val_offset:2484*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 96, 0, x3, 2484*FLEN/8, x4, x1, x2)

inst_829:
// fs1 == 0 and fe1 == 0x1b and fm1 == 0x2b4 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x111 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x03f and fcsr == 0x80 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x6eb4; op2val:0x4111;
op3val:0x743f; valaddr_reg:x3; val_offset:2487*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:128 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 128, 0, x3, 2487*FLEN/8, x4, x1, x2)

inst_830:
// fs1 == 0 and fe1 == 0x1a and fm1 == 0x111 and fs2 == 0 and fe2 == 0x13 and fm2 == 0x0ea and fs3 == 0 and fe3 == 0x1e and fm3 == 0x23a and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x6911; op2val:0x4cea;
op3val:0x7a3a; valaddr_reg:x3; val_offset:2490*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 2490*FLEN/8, x4, x1, x2)

inst_831:
// fs1 == 0 and fe1 == 0x1a and fm1 == 0x111 and fs2 == 0 and fe2 == 0x13 and fm2 == 0x0ea and fs3 == 0 and fe3 == 0x1e and fm3 == 0x23a and fcsr == 0x20 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x6911; op2val:0x4cea;
op3val:0x7a3a; valaddr_reg:x3; val_offset:2493*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:32 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 32, 0, x3, 2493*FLEN/8, x4, x1, x2)

inst_832:
// fs1 == 0 and fe1 == 0x1a and fm1 == 0x111 and fs2 == 0 and fe2 == 0x13 and fm2 == 0x0ea and fs3 == 0 and fe3 == 0x1e and fm3 == 0x23a and fcsr == 0x40 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x6911; op2val:0x4cea;
op3val:0x7a3a; valaddr_reg:x3; val_offset:2496*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:64 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 64, 0, x3, 2496*FLEN/8, x4, x1, x2)

inst_833:
// fs1 == 0 and fe1 == 0x1a and fm1 == 0x111 and fs2 == 0 and fe2 == 0x13 and fm2 == 0x0ea and fs3 == 0 and fe3 == 0x1e and fm3 == 0x23a and fcsr == 0x60 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x6911; op2val:0x4cea;
op3val:0x7a3a; valaddr_reg:x3; val_offset:2499*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 96, 0, x3, 2499*FLEN/8, x4, x1, x2)

inst_834:
// fs1 == 0 and fe1 == 0x1a and fm1 == 0x111 and fs2 == 0 and fe2 == 0x13 and fm2 == 0x0ea and fs3 == 0 and fe3 == 0x1e and fm3 == 0x23a and fcsr == 0x80 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x6911; op2val:0x4cea;
op3val:0x7a3a; valaddr_reg:x3; val_offset:2502*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:128 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 128, 0, x3, 2502*FLEN/8, x4, x1, x2)

inst_835:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x053 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x3aa and fs3 == 0 and fe3 == 0x1c and fm3 == 0x024 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7453; op2val:0x37aa;
op3val:0x7024; valaddr_reg:x3; val_offset:2505*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 2505*FLEN/8, x4, x1, x2)

inst_836:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x053 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x3aa and fs3 == 0 and fe3 == 0x1c and fm3 == 0x024 and fcsr == 0x20 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7453; op2val:0x37aa;
op3val:0x7024; valaddr_reg:x3; val_offset:2508*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:32 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 32, 0, x3, 2508*FLEN/8, x4, x1, x2)

inst_837:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x053 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x3aa and fs3 == 0 and fe3 == 0x1c and fm3 == 0x024 and fcsr == 0x40 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7453; op2val:0x37aa;
op3val:0x7024; valaddr_reg:x3; val_offset:2511*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:64 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 64, 0, x3, 2511*FLEN/8, x4, x1, x2)

inst_838:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x053 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x3aa and fs3 == 0 and fe3 == 0x1c and fm3 == 0x024 and fcsr == 0x60 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7453; op2val:0x37aa;
op3val:0x7024; valaddr_reg:x3; val_offset:2514*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 96, 0, x3, 2514*FLEN/8, x4, x1, x2)

inst_839:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x053 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x3aa and fs3 == 0 and fe3 == 0x1c and fm3 == 0x024 and fcsr == 0x80 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7453; op2val:0x37aa;
op3val:0x7024; valaddr_reg:x3; val_offset:2517*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:128 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 128, 0, x3, 2517*FLEN/8, x4, x1, x2)

inst_840:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x2c0 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x052 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x349 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x76c0; op2val:0x4052;
op3val:0x7b49; valaddr_reg:x3; val_offset:2520*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 2520*FLEN/8, x4, x1, x2)

inst_841:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x2c0 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x052 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x349 and fcsr == 0x20 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x76c0; op2val:0x4052;
op3val:0x7b49; valaddr_reg:x3; val_offset:2523*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:32 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 32, 0, x3, 2523*FLEN/8, x4, x1, x2)

inst_842:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x2c0 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x052 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x349 and fcsr == 0x40 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x76c0; op2val:0x4052;
op3val:0x7b49; valaddr_reg:x3; val_offset:2526*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:64 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 64, 0, x3, 2526*FLEN/8, x4, x1, x2)

inst_843:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x2c0 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x052 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x349 and fcsr == 0x60 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x76c0; op2val:0x4052;
op3val:0x7b49; valaddr_reg:x3; val_offset:2529*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 96, 0, x3, 2529*FLEN/8, x4, x1, x2)

inst_844:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x2c0 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x052 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x349 and fcsr == 0x80 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x76c0; op2val:0x4052;
op3val:0x7b49; valaddr_reg:x3; val_offset:2532*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:128 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 128, 0, x3, 2532*FLEN/8, x4, x1, x2)

inst_845:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x28c and fs2 == 0 and fe2 == 0x0d and fm2 == 0x112 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x022 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7a8c; op2val:0x3512;
op3val:0x7422; valaddr_reg:x3; val_offset:2535*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 2535*FLEN/8, x4, x1, x2)

inst_846:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x28c and fs2 == 0 and fe2 == 0x0d and fm2 == 0x112 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x022 and fcsr == 0x20 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7a8c; op2val:0x3512;
op3val:0x7422; valaddr_reg:x3; val_offset:2538*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:32 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 32, 0, x3, 2538*FLEN/8, x4, x1, x2)

inst_847:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x28c and fs2 == 0 and fe2 == 0x0d and fm2 == 0x112 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x022 and fcsr == 0x40 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7a8c; op2val:0x3512;
op3val:0x7422; valaddr_reg:x3; val_offset:2541*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:64 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 64, 0, x3, 2541*FLEN/8, x4, x1, x2)

inst_848:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x28c and fs2 == 0 and fe2 == 0x0d and fm2 == 0x112 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x022 and fcsr == 0x60 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7a8c; op2val:0x3512;
op3val:0x7422; valaddr_reg:x3; val_offset:2544*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 96, 0, x3, 2544*FLEN/8, x4, x1, x2)

inst_849:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x28c and fs2 == 0 and fe2 == 0x0d and fm2 == 0x112 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x022 and fcsr == 0x80 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7a8c; op2val:0x3512;
op3val:0x7422; valaddr_reg:x3; val_offset:2547*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:128 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 128, 0, x3, 2547*FLEN/8, x4, x1, x2)

inst_850:
// fs1 == 0 and fe1 == 0x1c and fm1 == 0x0c7 and fs2 == 0 and fe2 == 0x11 and fm2 == 0x228 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x359 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x70c7; op2val:0x4628;
op3val:0x7b59; valaddr_reg:x3; val_offset:2550*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 2550*FLEN/8, x4, x1, x2)

inst_851:
// fs1 == 0 and fe1 == 0x1c and fm1 == 0x0c7 and fs2 == 0 and fe2 == 0x11 and fm2 == 0x228 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x359 and fcsr == 0x20 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x70c7; op2val:0x4628;
op3val:0x7b59; valaddr_reg:x3; val_offset:2553*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:32 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 32, 0, x3, 2553*FLEN/8, x4, x1, x2)

inst_852:
// fs1 == 0 and fe1 == 0x1c and fm1 == 0x0c7 and fs2 == 0 and fe2 == 0x11 and fm2 == 0x228 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x359 and fcsr == 0x40 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x70c7; op2val:0x4628;
op3val:0x7b59; valaddr_reg:x3; val_offset:2556*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:64 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 64, 0, x3, 2556*FLEN/8, x4, x1, x2)

inst_853:
// fs1 == 0 and fe1 == 0x1c and fm1 == 0x0c7 and fs2 == 0 and fe2 == 0x11 and fm2 == 0x228 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x359 and fcsr == 0x60 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x70c7; op2val:0x4628;
op3val:0x7b59; valaddr_reg:x3; val_offset:2559*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 96, 0, x3, 2559*FLEN/8, x4, x1, x2)

inst_854:
// fs1 == 0 and fe1 == 0x1c and fm1 == 0x0c7 and fs2 == 0 and fe2 == 0x11 and fm2 == 0x228 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x359 and fcsr == 0x80 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x70c7; op2val:0x4628;
op3val:0x7b59; valaddr_reg:x3; val_offset:2562*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:128 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 128, 0, x3, 2562*FLEN/8, x4, x1, x2)

inst_855:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x090 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x0ea and fs3 == 0 and fe3 == 0x1e and fm3 == 0x199 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7890; op2val:0x3cea;
op3val:0x7999; valaddr_reg:x3; val_offset:2565*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 2565*FLEN/8, x4, x1, x2)

inst_856:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x090 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x0ea and fs3 == 0 and fe3 == 0x1e and fm3 == 0x199 and fcsr == 0x20 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7890; op2val:0x3cea;
op3val:0x7999; valaddr_reg:x3; val_offset:2568*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:32 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 32, 0, x3, 2568*FLEN/8, x4, x1, x2)

inst_857:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x090 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x0ea and fs3 == 0 and fe3 == 0x1e and fm3 == 0x199 and fcsr == 0x40 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7890; op2val:0x3cea;
op3val:0x7999; valaddr_reg:x3; val_offset:2571*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:64 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 64, 0, x3, 2571*FLEN/8, x4, x1, x2)

inst_858:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x090 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x0ea and fs3 == 0 and fe3 == 0x1e and fm3 == 0x199 and fcsr == 0x60 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7890; op2val:0x3cea;
op3val:0x7999; valaddr_reg:x3; val_offset:2574*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 96, 0, x3, 2574*FLEN/8, x4, x1, x2)

inst_859:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x090 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x0ea and fs3 == 0 and fe3 == 0x1e and fm3 == 0x199 and fcsr == 0x80 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7890; op2val:0x3cea;
op3val:0x7999; valaddr_reg:x3; val_offset:2577*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:128 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 128, 0, x3, 2577*FLEN/8, x4, x1, x2)

inst_860:
// fs1 == 0 and fe1 == 0x1b and fm1 == 0x1b9 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x13b and fs3 == 0 and fe3 == 0x1a and fm3 == 0x35c and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x6db9; op2val:0x393b;
op3val:0x6b5c; valaddr_reg:x3; val_offset:2580*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 2580*FLEN/8, x4, x1, x2)

inst_861:
// fs1 == 0 and fe1 == 0x1b and fm1 == 0x1b9 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x13b and fs3 == 0 and fe3 == 0x1a and fm3 == 0x35c and fcsr == 0x20 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x6db9; op2val:0x393b;
op3val:0x6b5c; valaddr_reg:x3; val_offset:2583*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:32 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 32, 0, x3, 2583*FLEN/8, x4, x1, x2)

inst_862:
// fs1 == 0 and fe1 == 0x1b and fm1 == 0x1b9 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x13b and fs3 == 0 and fe3 == 0x1a and fm3 == 0x35c and fcsr == 0x40 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x6db9; op2val:0x393b;
op3val:0x6b5c; valaddr_reg:x3; val_offset:2586*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:64 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 64, 0, x3, 2586*FLEN/8, x4, x1, x2)

inst_863:
// fs1 == 0 and fe1 == 0x1b and fm1 == 0x1b9 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x13b and fs3 == 0 and fe3 == 0x1a and fm3 == 0x35c and fcsr == 0x60 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x6db9; op2val:0x393b;
op3val:0x6b5c; valaddr_reg:x3; val_offset:2589*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 96, 0, x3, 2589*FLEN/8, x4, x1, x2)

inst_864:
// fs1 == 0 and fe1 == 0x1b and fm1 == 0x1b9 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x13b and fs3 == 0 and fe3 == 0x1a and fm3 == 0x35c and fcsr == 0x80 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x6db9; op2val:0x393b;
op3val:0x6b5c; valaddr_reg:x3; val_offset:2592*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:128 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 128, 0, x3, 2592*FLEN/8, x4, x1, x2)

inst_865:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x180 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x0f4 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x2cd and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7980; op2val:0x38f4;
op3val:0x76cd; valaddr_reg:x3; val_offset:2595*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 2595*FLEN/8, x4, x1, x2)

inst_866:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x180 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x0f4 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x2cd and fcsr == 0x20 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7980; op2val:0x38f4;
op3val:0x76cd; valaddr_reg:x3; val_offset:2598*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:32 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 32, 0, x3, 2598*FLEN/8, x4, x1, x2)

inst_867:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x180 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x0f4 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x2cd and fcsr == 0x40 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7980; op2val:0x38f4;
op3val:0x76cd; valaddr_reg:x3; val_offset:2601*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:64 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 64, 0, x3, 2601*FLEN/8, x4, x1, x2)

inst_868:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x180 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x0f4 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x2cd and fcsr == 0x60 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7980; op2val:0x38f4;
op3val:0x76cd; valaddr_reg:x3; val_offset:2604*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 96, 0, x3, 2604*FLEN/8, x4, x1, x2)

inst_869:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x180 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x0f4 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x2cd and fcsr == 0x80 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7980; op2val:0x38f4;
op3val:0x76cd; valaddr_reg:x3; val_offset:2607*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:128 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 128, 0, x3, 2607*FLEN/8, x4, x1, x2)

inst_870:
// fs1 == 0 and fe1 == 0x1b and fm1 == 0x0a2 and fs2 == 0 and fe2 == 0x12 and fm2 == 0x27c and fs3 == 0 and fe3 == 0x1e and fm3 == 0x380 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x6ca2; op2val:0x4a7c;
op3val:0x7b80; valaddr_reg:x3; val_offset:2610*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 2610*FLEN/8, x4, x1, x2)

inst_871:
// fs1 == 0 and fe1 == 0x1b and fm1 == 0x0a2 and fs2 == 0 and fe2 == 0x12 and fm2 == 0x27c and fs3 == 0 and fe3 == 0x1e and fm3 == 0x380 and fcsr == 0x20 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x6ca2; op2val:0x4a7c;
op3val:0x7b80; valaddr_reg:x3; val_offset:2613*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:32 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 32, 0, x3, 2613*FLEN/8, x4, x1, x2)

inst_872:
// fs1 == 0 and fe1 == 0x1b and fm1 == 0x0a2 and fs2 == 0 and fe2 == 0x12 and fm2 == 0x27c and fs3 == 0 and fe3 == 0x1e and fm3 == 0x380 and fcsr == 0x40 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x6ca2; op2val:0x4a7c;
op3val:0x7b80; valaddr_reg:x3; val_offset:2616*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:64 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 64, 0, x3, 2616*FLEN/8, x4, x1, x2)

inst_873:
// fs1 == 0 and fe1 == 0x1b and fm1 == 0x0a2 and fs2 == 0 and fe2 == 0x12 and fm2 == 0x27c and fs3 == 0 and fe3 == 0x1e and fm3 == 0x380 and fcsr == 0x60 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x6ca2; op2val:0x4a7c;
op3val:0x7b80; valaddr_reg:x3; val_offset:2619*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 96, 0, x3, 2619*FLEN/8, x4, x1, x2)

inst_874:
// fs1 == 0 and fe1 == 0x1b and fm1 == 0x0a2 and fs2 == 0 and fe2 == 0x12 and fm2 == 0x27c and fs3 == 0 and fe3 == 0x1e and fm3 == 0x380 and fcsr == 0x80 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x6ca2; op2val:0x4a7c;
op3val:0x7b80; valaddr_reg:x3; val_offset:2622*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:128 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 128, 0, x3, 2622*FLEN/8, x4, x1, x2)

inst_875:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x112 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x10c and fs3 == 0 and fe3 == 0x1e and fm3 == 0x268 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7912; op2val:0x3d0c;
op3val:0x7a68; valaddr_reg:x3; val_offset:2625*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 2625*FLEN/8, x4, x1, x2)

inst_876:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x112 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x10c and fs3 == 0 and fe3 == 0x1e and fm3 == 0x268 and fcsr == 0x20 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7912; op2val:0x3d0c;
op3val:0x7a68; valaddr_reg:x3; val_offset:2628*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:32 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 32, 0, x3, 2628*FLEN/8, x4, x1, x2)

inst_877:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x112 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x10c and fs3 == 0 and fe3 == 0x1e and fm3 == 0x268 and fcsr == 0x40 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7912; op2val:0x3d0c;
op3val:0x7a68; valaddr_reg:x3; val_offset:2631*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:64 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 64, 0, x3, 2631*FLEN/8, x4, x1, x2)

inst_878:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x112 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x10c and fs3 == 0 and fe3 == 0x1e and fm3 == 0x268 and fcsr == 0x60 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7912; op2val:0x3d0c;
op3val:0x7a68; valaddr_reg:x3; val_offset:2634*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 96, 0, x3, 2634*FLEN/8, x4, x1, x2)

inst_879:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x112 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x10c and fs3 == 0 and fe3 == 0x1e and fm3 == 0x268 and fcsr == 0x80 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7912; op2val:0x3d0c;
op3val:0x7a68; valaddr_reg:x3; val_offset:2637*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:128 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 128, 0, x3, 2637*FLEN/8, x4, x1, x2)

inst_880:
// fs1 == 0 and fe1 == 0x1b and fm1 == 0x15b and fs2 == 0 and fe2 == 0x12 and fm2 == 0x11b and fs3 == 0 and fe3 == 0x1e and fm3 == 0x2d8 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x6d5b; op2val:0x491b;
op3val:0x7ad8; valaddr_reg:x3; val_offset:2640*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 2640*FLEN/8, x4, x1, x2)

inst_881:
// fs1 == 0 and fe1 == 0x1b and fm1 == 0x15b and fs2 == 0 and fe2 == 0x12 and fm2 == 0x11b and fs3 == 0 and fe3 == 0x1e and fm3 == 0x2d8 and fcsr == 0x20 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x6d5b; op2val:0x491b;
op3val:0x7ad8; valaddr_reg:x3; val_offset:2643*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:32 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 32, 0, x3, 2643*FLEN/8, x4, x1, x2)

inst_882:
// fs1 == 0 and fe1 == 0x1b and fm1 == 0x15b and fs2 == 0 and fe2 == 0x12 and fm2 == 0x11b and fs3 == 0 and fe3 == 0x1e and fm3 == 0x2d8 and fcsr == 0x40 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x6d5b; op2val:0x491b;
op3val:0x7ad8; valaddr_reg:x3; val_offset:2646*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:64 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 64, 0, x3, 2646*FLEN/8, x4, x1, x2)

inst_883:
// fs1 == 0 and fe1 == 0x1b and fm1 == 0x15b and fs2 == 0 and fe2 == 0x12 and fm2 == 0x11b and fs3 == 0 and fe3 == 0x1e and fm3 == 0x2d8 and fcsr == 0x60 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x6d5b; op2val:0x491b;
op3val:0x7ad8; valaddr_reg:x3; val_offset:2649*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 96, 0, x3, 2649*FLEN/8, x4, x1, x2)

inst_884:
// fs1 == 0 and fe1 == 0x1b and fm1 == 0x15b and fs2 == 0 and fe2 == 0x12 and fm2 == 0x11b and fs3 == 0 and fe3 == 0x1e and fm3 == 0x2d8 and fcsr == 0x80 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x6d5b; op2val:0x491b;
op3val:0x7ad8; valaddr_reg:x3; val_offset:2652*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:128 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 128, 0, x3, 2652*FLEN/8, x4, x1, x2)

inst_885:
// fs1 == 0 and fe1 == 0x1b and fm1 == 0x043 and fs2 == 0 and fe2 == 0x12 and fm2 == 0x277 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x2e6 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x6c43; op2val:0x4a77;
op3val:0x7ae6; valaddr_reg:x3; val_offset:2655*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 2655*FLEN/8, x4, x1, x2)

inst_886:
// fs1 == 0 and fe1 == 0x1b and fm1 == 0x043 and fs2 == 0 and fe2 == 0x12 and fm2 == 0x277 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x2e6 and fcsr == 0x20 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x6c43; op2val:0x4a77;
op3val:0x7ae6; valaddr_reg:x3; val_offset:2658*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:32 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 32, 0, x3, 2658*FLEN/8, x4, x1, x2)

inst_887:
// fs1 == 0 and fe1 == 0x1b and fm1 == 0x043 and fs2 == 0 and fe2 == 0x12 and fm2 == 0x277 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x2e6 and fcsr == 0x40 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x6c43; op2val:0x4a77;
op3val:0x7ae6; valaddr_reg:x3; val_offset:2661*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:64 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 64, 0, x3, 2661*FLEN/8, x4, x1, x2)

inst_888:
// fs1 == 0 and fe1 == 0x1b and fm1 == 0x043 and fs2 == 0 and fe2 == 0x12 and fm2 == 0x277 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x2e6 and fcsr == 0x60 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x6c43; op2val:0x4a77;
op3val:0x7ae6; valaddr_reg:x3; val_offset:2664*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 96, 0, x3, 2664*FLEN/8, x4, x1, x2)

inst_889:
// fs1 == 0 and fe1 == 0x1b and fm1 == 0x043 and fs2 == 0 and fe2 == 0x12 and fm2 == 0x277 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x2e6 and fcsr == 0x80 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x6c43; op2val:0x4a77;
op3val:0x7ae6; valaddr_reg:x3; val_offset:2667*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:128 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 128, 0, x3, 2667*FLEN/8, x4, x1, x2)

inst_890:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x341 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x1f6 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x16c and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7741; op2val:0x39f6;
op3val:0x756c; valaddr_reg:x3; val_offset:2670*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 2670*FLEN/8, x4, x1, x2)

inst_891:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x341 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x1f6 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x16c and fcsr == 0x20 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7741; op2val:0x39f6;
op3val:0x756c; valaddr_reg:x3; val_offset:2673*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:32 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 32, 0, x3, 2673*FLEN/8, x4, x1, x2)

inst_892:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x341 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x1f6 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x16c and fcsr == 0x40 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7741; op2val:0x39f6;
op3val:0x756c; valaddr_reg:x3; val_offset:2676*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:64 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 64, 0, x3, 2676*FLEN/8, x4, x1, x2)

inst_893:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x341 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x1f6 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x16c and fcsr == 0x60 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7741; op2val:0x39f6;
op3val:0x756c; valaddr_reg:x3; val_offset:2679*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 96, 0, x3, 2679*FLEN/8, x4, x1, x2)

inst_894:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x341 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x1f6 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x16c and fcsr == 0x80 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7741; op2val:0x39f6;
op3val:0x756c; valaddr_reg:x3; val_offset:2682*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:128 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 128, 0, x3, 2682*FLEN/8, x4, x1, x2)

inst_895:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x06c and fs2 == 0 and fe2 == 0x0f and fm2 == 0x2b1 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x368 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x786c; op2val:0x3eb1;
op3val:0x7b68; valaddr_reg:x3; val_offset:2685*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 2685*FLEN/8, x4, x1, x2)
RVTEST_SIGBASE(x1,signature_x1_8)

inst_896:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x06c and fs2 == 0 and fe2 == 0x0f and fm2 == 0x2b1 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x368 and fcsr == 0x20 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x786c; op2val:0x3eb1;
op3val:0x7b68; valaddr_reg:x3; val_offset:2688*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:32 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 32, 0, x3, 2688*FLEN/8, x4, x1, x2)

inst_897:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x06c and fs2 == 0 and fe2 == 0x0f and fm2 == 0x2b1 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x368 and fcsr == 0x40 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x786c; op2val:0x3eb1;
op3val:0x7b68; valaddr_reg:x3; val_offset:2691*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:64 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 64, 0, x3, 2691*FLEN/8, x4, x1, x2)

inst_898:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x06c and fs2 == 0 and fe2 == 0x0f and fm2 == 0x2b1 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x368 and fcsr == 0x60 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x786c; op2val:0x3eb1;
op3val:0x7b68; valaddr_reg:x3; val_offset:2694*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 96, 0, x3, 2694*FLEN/8, x4, x1, x2)

inst_899:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x06c and fs2 == 0 and fe2 == 0x0f and fm2 == 0x2b1 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x368 and fcsr == 0x80 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x786c; op2val:0x3eb1;
op3val:0x7b68; valaddr_reg:x3; val_offset:2697*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:128 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 128, 0, x3, 2697*FLEN/8, x4, x1, x2)

inst_900:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x048 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x3a9 and fs3 == 0 and fe3 == 0x1c and fm3 == 0x022 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7448; op2val:0x37a9;
op3val:0x7022; valaddr_reg:x3; val_offset:2700*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 2700*FLEN/8, x4, x1, x2)

inst_901:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x048 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x3a9 and fs3 == 0 and fe3 == 0x1c and fm3 == 0x022 and fcsr == 0x20 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7448; op2val:0x37a9;
op3val:0x7022; valaddr_reg:x3; val_offset:2703*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:32 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 32, 0, x3, 2703*FLEN/8, x4, x1, x2)

inst_902:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x048 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x3a9 and fs3 == 0 and fe3 == 0x1c and fm3 == 0x022 and fcsr == 0x40 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7448; op2val:0x37a9;
op3val:0x7022; valaddr_reg:x3; val_offset:2706*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:64 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 64, 0, x3, 2706*FLEN/8, x4, x1, x2)

inst_903:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x048 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x3a9 and fs3 == 0 and fe3 == 0x1c and fm3 == 0x022 and fcsr == 0x60 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7448; op2val:0x37a9;
op3val:0x7022; valaddr_reg:x3; val_offset:2709*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 96, 0, x3, 2709*FLEN/8, x4, x1, x2)

inst_904:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x048 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x3a9 and fs3 == 0 and fe3 == 0x1c and fm3 == 0x022 and fcsr == 0x80 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7448; op2val:0x37a9;
op3val:0x7022; valaddr_reg:x3; val_offset:2712*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:128 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 128, 0, x3, 2712*FLEN/8, x4, x1, x2)

inst_905:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x036 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x335 and fs3 == 0 and fe3 == 0x1c and fm3 == 0x3a0 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7836; op2val:0x3735;
op3val:0x73a0; valaddr_reg:x3; val_offset:2715*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 2715*FLEN/8, x4, x1, x2)

inst_906:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x036 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x335 and fs3 == 0 and fe3 == 0x1c and fm3 == 0x3a0 and fcsr == 0x20 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7836; op2val:0x3735;
op3val:0x73a0; valaddr_reg:x3; val_offset:2718*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:32 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 32, 0, x3, 2718*FLEN/8, x4, x1, x2)

inst_907:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x036 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x335 and fs3 == 0 and fe3 == 0x1c and fm3 == 0x3a0 and fcsr == 0x40 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7836; op2val:0x3735;
op3val:0x73a0; valaddr_reg:x3; val_offset:2721*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:64 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 64, 0, x3, 2721*FLEN/8, x4, x1, x2)

inst_908:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x036 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x335 and fs3 == 0 and fe3 == 0x1c and fm3 == 0x3a0 and fcsr == 0x60 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7836; op2val:0x3735;
op3val:0x73a0; valaddr_reg:x3; val_offset:2724*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 96, 0, x3, 2724*FLEN/8, x4, x1, x2)

inst_909:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x036 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x335 and fs3 == 0 and fe3 == 0x1c and fm3 == 0x3a0 and fcsr == 0x80 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7836; op2val:0x3735;
op3val:0x73a0; valaddr_reg:x3; val_offset:2727*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:128 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 128, 0, x3, 2727*FLEN/8, x4, x1, x2)

inst_910:
// fs1 == 0 and fe1 == 0x1b and fm1 == 0x300 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x1dd and fs3 == 0 and fe3 == 0x1c and fm3 == 0x12a and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x6f00; op2val:0x3ddd;
op3val:0x712a; valaddr_reg:x3; val_offset:2730*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 2730*FLEN/8, x4, x1, x2)

inst_911:
// fs1 == 0 and fe1 == 0x1b and fm1 == 0x300 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x1dd and fs3 == 0 and fe3 == 0x1c and fm3 == 0x12a and fcsr == 0x20 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x6f00; op2val:0x3ddd;
op3val:0x712a; valaddr_reg:x3; val_offset:2733*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:32 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 32, 0, x3, 2733*FLEN/8, x4, x1, x2)

inst_912:
// fs1 == 0 and fe1 == 0x1b and fm1 == 0x300 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x1dd and fs3 == 0 and fe3 == 0x1c and fm3 == 0x12a and fcsr == 0x40 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x6f00; op2val:0x3ddd;
op3val:0x712a; valaddr_reg:x3; val_offset:2736*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:64 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 64, 0, x3, 2736*FLEN/8, x4, x1, x2)

inst_913:
// fs1 == 0 and fe1 == 0x1b and fm1 == 0x300 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x1dd and fs3 == 0 and fe3 == 0x1c and fm3 == 0x12a and fcsr == 0x60 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x6f00; op2val:0x3ddd;
op3val:0x712a; valaddr_reg:x3; val_offset:2739*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 96, 0, x3, 2739*FLEN/8, x4, x1, x2)

inst_914:
// fs1 == 0 and fe1 == 0x1b and fm1 == 0x300 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x1dd and fs3 == 0 and fe3 == 0x1c and fm3 == 0x12a and fcsr == 0x80 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x6f00; op2val:0x3ddd;
op3val:0x712a; valaddr_reg:x3; val_offset:2742*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:128 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 128, 0, x3, 2742*FLEN/8, x4, x1, x2)

inst_915:
// fs1 == 0 and fe1 == 0x1a and fm1 == 0x272 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x3f8 and fs3 == 0 and fe3 == 0x1c and fm3 == 0x274 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x6a72; op2val:0x43f8;
op3val:0x7274; valaddr_reg:x3; val_offset:2745*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 2745*FLEN/8, x4, x1, x2)

inst_916:
// fs1 == 0 and fe1 == 0x1a and fm1 == 0x272 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x3f8 and fs3 == 0 and fe3 == 0x1c and fm3 == 0x274 and fcsr == 0x20 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x6a72; op2val:0x43f8;
op3val:0x7274; valaddr_reg:x3; val_offset:2748*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:32 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 32, 0, x3, 2748*FLEN/8, x4, x1, x2)

inst_917:
// fs1 == 0 and fe1 == 0x1a and fm1 == 0x272 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x3f8 and fs3 == 0 and fe3 == 0x1c and fm3 == 0x274 and fcsr == 0x40 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x6a72; op2val:0x43f8;
op3val:0x7274; valaddr_reg:x3; val_offset:2751*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:64 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 64, 0, x3, 2751*FLEN/8, x4, x1, x2)

inst_918:
// fs1 == 0 and fe1 == 0x1a and fm1 == 0x272 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x3f8 and fs3 == 0 and fe3 == 0x1c and fm3 == 0x274 and fcsr == 0x60 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x6a72; op2val:0x43f8;
op3val:0x7274; valaddr_reg:x3; val_offset:2754*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 96, 0, x3, 2754*FLEN/8, x4, x1, x2)

inst_919:
// fs1 == 0 and fe1 == 0x1a and fm1 == 0x272 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x3f8 and fs3 == 0 and fe3 == 0x1c and fm3 == 0x274 and fcsr == 0x80 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x6a72; op2val:0x43f8;
op3val:0x7274; valaddr_reg:x3; val_offset:2757*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:128 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 128, 0, x3, 2757*FLEN/8, x4, x1, x2)

inst_920:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x0fd and fs2 == 0 and fe2 == 0x0e and fm2 == 0x3cb and fs3 == 0 and fe3 == 0x1d and fm3 == 0x0e0 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x74fd; op2val:0x3bcb;
op3val:0x74e0; valaddr_reg:x3; val_offset:2760*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 2760*FLEN/8, x4, x1, x2)

inst_921:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x0fd and fs2 == 0 and fe2 == 0x0e and fm2 == 0x3cb and fs3 == 0 and fe3 == 0x1d and fm3 == 0x0e0 and fcsr == 0x20 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x74fd; op2val:0x3bcb;
op3val:0x74e0; valaddr_reg:x3; val_offset:2763*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:32 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 32, 0, x3, 2763*FLEN/8, x4, x1, x2)

inst_922:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x0fd and fs2 == 0 and fe2 == 0x0e and fm2 == 0x3cb and fs3 == 0 and fe3 == 0x1d and fm3 == 0x0e0 and fcsr == 0x40 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x74fd; op2val:0x3bcb;
op3val:0x74e0; valaddr_reg:x3; val_offset:2766*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:64 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 64, 0, x3, 2766*FLEN/8, x4, x1, x2)

inst_923:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x0fd and fs2 == 0 and fe2 == 0x0e and fm2 == 0x3cb and fs3 == 0 and fe3 == 0x1d and fm3 == 0x0e0 and fcsr == 0x60 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x74fd; op2val:0x3bcb;
op3val:0x74e0; valaddr_reg:x3; val_offset:2769*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 96, 0, x3, 2769*FLEN/8, x4, x1, x2)

inst_924:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x0fd and fs2 == 0 and fe2 == 0x0e and fm2 == 0x3cb and fs3 == 0 and fe3 == 0x1d and fm3 == 0x0e0 and fcsr == 0x80 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x74fd; op2val:0x3bcb;
op3val:0x74e0; valaddr_reg:x3; val_offset:2772*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:128 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 128, 0, x3, 2772*FLEN/8, x4, x1, x2)

inst_925:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x212 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x216 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x0a3 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7a12; op2val:0x3616;
op3val:0x74a3; valaddr_reg:x3; val_offset:2775*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 2775*FLEN/8, x4, x1, x2)

inst_926:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x212 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x216 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x0a3 and fcsr == 0x20 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7a12; op2val:0x3616;
op3val:0x74a3; valaddr_reg:x3; val_offset:2778*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:32 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 32, 0, x3, 2778*FLEN/8, x4, x1, x2)

inst_927:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x212 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x216 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x0a3 and fcsr == 0x40 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7a12; op2val:0x3616;
op3val:0x74a3; valaddr_reg:x3; val_offset:2781*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:64 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 64, 0, x3, 2781*FLEN/8, x4, x1, x2)

inst_928:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x212 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x216 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x0a3 and fcsr == 0x60 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7a12; op2val:0x3616;
op3val:0x74a3; valaddr_reg:x3; val_offset:2784*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 96, 0, x3, 2784*FLEN/8, x4, x1, x2)

inst_929:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x212 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x216 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x0a3 and fcsr == 0x80 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7a12; op2val:0x3616;
op3val:0x74a3; valaddr_reg:x3; val_offset:2787*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:128 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 128, 0, x3, 2787*FLEN/8, x4, x1, x2)

inst_930:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x0d and fm2 == 0x1a9 and fs3 == 0 and fe3 == 0x1c and fm3 == 0x1b0 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x77ff; op2val:0x35a9;
op3val:0x71b0; valaddr_reg:x3; val_offset:2790*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 2790*FLEN/8, x4, x1, x2)

inst_931:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x0d and fm2 == 0x1a9 and fs3 == 0 and fe3 == 0x1c and fm3 == 0x1b0 and fcsr == 0x20 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x77ff; op2val:0x35a9;
op3val:0x71b0; valaddr_reg:x3; val_offset:2793*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:32 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 32, 0, x3, 2793*FLEN/8, x4, x1, x2)

inst_932:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x0d and fm2 == 0x1a9 and fs3 == 0 and fe3 == 0x1c and fm3 == 0x1b0 and fcsr == 0x40 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x77ff; op2val:0x35a9;
op3val:0x71b0; valaddr_reg:x3; val_offset:2796*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:64 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 64, 0, x3, 2796*FLEN/8, x4, x1, x2)

inst_933:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x0d and fm2 == 0x1a9 and fs3 == 0 and fe3 == 0x1c and fm3 == 0x1b0 and fcsr == 0x60 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x77ff; op2val:0x35a9;
op3val:0x71b0; valaddr_reg:x3; val_offset:2799*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 96, 0, x3, 2799*FLEN/8, x4, x1, x2)

inst_934:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x0d and fm2 == 0x1a9 and fs3 == 0 and fe3 == 0x1c and fm3 == 0x1b0 and fcsr == 0x80 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x77ff; op2val:0x35a9;
op3val:0x71b0; valaddr_reg:x3; val_offset:2802*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:128 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 128, 0, x3, 2802*FLEN/8, x4, x1, x2)

inst_935:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x18c and fs2 == 0 and fe2 == 0x0a and fm2 == 0x258 and fs3 == 0 and fe3 == 0x19 and fm3 == 0x0a6 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x758c; op2val:0x2a58;
op3val:0x64a6; valaddr_reg:x3; val_offset:2805*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 2805*FLEN/8, x4, x1, x2)

inst_936:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x18c and fs2 == 0 and fe2 == 0x0a and fm2 == 0x258 and fs3 == 0 and fe3 == 0x19 and fm3 == 0x0a6 and fcsr == 0x20 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x758c; op2val:0x2a58;
op3val:0x64a6; valaddr_reg:x3; val_offset:2808*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:32 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 32, 0, x3, 2808*FLEN/8, x4, x1, x2)

inst_937:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x18c and fs2 == 0 and fe2 == 0x0a and fm2 == 0x258 and fs3 == 0 and fe3 == 0x19 and fm3 == 0x0a6 and fcsr == 0x40 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x758c; op2val:0x2a58;
op3val:0x64a6; valaddr_reg:x3; val_offset:2811*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:64 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 64, 0, x3, 2811*FLEN/8, x4, x1, x2)

inst_938:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x18c and fs2 == 0 and fe2 == 0x0a and fm2 == 0x258 and fs3 == 0 and fe3 == 0x19 and fm3 == 0x0a6 and fcsr == 0x60 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x758c; op2val:0x2a58;
op3val:0x64a6; valaddr_reg:x3; val_offset:2814*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 96, 0, x3, 2814*FLEN/8, x4, x1, x2)

inst_939:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x18c and fs2 == 0 and fe2 == 0x0a and fm2 == 0x258 and fs3 == 0 and fe3 == 0x19 and fm3 == 0x0a6 and fcsr == 0x80 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x758c; op2val:0x2a58;
op3val:0x64a6; valaddr_reg:x3; val_offset:2817*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:128 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 128, 0, x3, 2817*FLEN/8, x4, x1, x2)

inst_940:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x001 and fs2 == 0 and fe2 == 0x0a and fm2 == 0x359 and fs3 == 0 and fe3 == 0x18 and fm3 == 0x3dc and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7401; op2val:0x2b59;
op3val:0x63dc; valaddr_reg:x3; val_offset:2820*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 2820*FLEN/8, x4, x1, x2)

inst_941:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x001 and fs2 == 0 and fe2 == 0x0a and fm2 == 0x359 and fs3 == 0 and fe3 == 0x18 and fm3 == 0x3dc and fcsr == 0x20 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7401; op2val:0x2b59;
op3val:0x63dc; valaddr_reg:x3; val_offset:2823*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:32 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 32, 0, x3, 2823*FLEN/8, x4, x1, x2)

inst_942:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x001 and fs2 == 0 and fe2 == 0x0a and fm2 == 0x359 and fs3 == 0 and fe3 == 0x18 and fm3 == 0x3dc and fcsr == 0x40 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7401; op2val:0x2b59;
op3val:0x63dc; valaddr_reg:x3; val_offset:2826*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:64 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 64, 0, x3, 2826*FLEN/8, x4, x1, x2)

inst_943:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x001 and fs2 == 0 and fe2 == 0x0a and fm2 == 0x359 and fs3 == 0 and fe3 == 0x18 and fm3 == 0x3dc and fcsr == 0x60 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7401; op2val:0x2b59;
op3val:0x63dc; valaddr_reg:x3; val_offset:2829*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 96, 0, x3, 2829*FLEN/8, x4, x1, x2)

inst_944:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x001 and fs2 == 0 and fe2 == 0x0a and fm2 == 0x359 and fs3 == 0 and fe3 == 0x18 and fm3 == 0x3dc and fcsr == 0x80 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7401; op2val:0x2b59;
op3val:0x63dc; valaddr_reg:x3; val_offset:2832*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:128 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 128, 0, x3, 2832*FLEN/8, x4, x1, x2)

inst_945:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1dc and fs2 == 0 and fe2 == 0x0e and fm2 == 0x206 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x068 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x79dc; op2val:0x3a06;
op3val:0x7868; valaddr_reg:x3; val_offset:2835*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 2835*FLEN/8, x4, x1, x2)

inst_946:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1dc and fs2 == 0 and fe2 == 0x0e and fm2 == 0x206 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x068 and fcsr == 0x20 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x79dc; op2val:0x3a06;
op3val:0x7868; valaddr_reg:x3; val_offset:2838*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:32 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 32, 0, x3, 2838*FLEN/8, x4, x1, x2)

inst_947:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1dc and fs2 == 0 and fe2 == 0x0e and fm2 == 0x206 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x068 and fcsr == 0x40 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x79dc; op2val:0x3a06;
op3val:0x7868; valaddr_reg:x3; val_offset:2841*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:64 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 64, 0, x3, 2841*FLEN/8, x4, x1, x2)

inst_948:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1dc and fs2 == 0 and fe2 == 0x0e and fm2 == 0x206 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x068 and fcsr == 0x60 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x79dc; op2val:0x3a06;
op3val:0x7868; valaddr_reg:x3; val_offset:2844*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 96, 0, x3, 2844*FLEN/8, x4, x1, x2)

inst_949:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1dc and fs2 == 0 and fe2 == 0x0e and fm2 == 0x206 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x068 and fcsr == 0x80 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x79dc; op2val:0x3a06;
op3val:0x7868; valaddr_reg:x3; val_offset:2847*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:128 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 128, 0, x3, 2847*FLEN/8, x4, x1, x2)

inst_950:
// fs1 == 0 and fe1 == 0x1c and fm1 == 0x20f and fs2 == 0 and fe2 == 0x10 and fm2 == 0x105 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x397 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x720f; op2val:0x4105;
op3val:0x7797; valaddr_reg:x3; val_offset:2850*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 2850*FLEN/8, x4, x1, x2)

inst_951:
// fs1 == 0 and fe1 == 0x1c and fm1 == 0x20f and fs2 == 0 and fe2 == 0x10 and fm2 == 0x105 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x397 and fcsr == 0x20 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x720f; op2val:0x4105;
op3val:0x7797; valaddr_reg:x3; val_offset:2853*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:32 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 32, 0, x3, 2853*FLEN/8, x4, x1, x2)

inst_952:
// fs1 == 0 and fe1 == 0x1c and fm1 == 0x20f and fs2 == 0 and fe2 == 0x10 and fm2 == 0x105 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x397 and fcsr == 0x40 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x720f; op2val:0x4105;
op3val:0x7797; valaddr_reg:x3; val_offset:2856*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:64 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 64, 0, x3, 2856*FLEN/8, x4, x1, x2)

inst_953:
// fs1 == 0 and fe1 == 0x1c and fm1 == 0x20f and fs2 == 0 and fe2 == 0x10 and fm2 == 0x105 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x397 and fcsr == 0x60 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x720f; op2val:0x4105;
op3val:0x7797; valaddr_reg:x3; val_offset:2859*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 96, 0, x3, 2859*FLEN/8, x4, x1, x2)

inst_954:
// fs1 == 0 and fe1 == 0x1c and fm1 == 0x20f and fs2 == 0 and fe2 == 0x10 and fm2 == 0x105 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x397 and fcsr == 0x80 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x720f; op2val:0x4105;
op3val:0x7797; valaddr_reg:x3; val_offset:2862*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:128 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 128, 0, x3, 2862*FLEN/8, x4, x1, x2)

inst_955:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x379 and fs2 == 0 and fe2 == 0x0b and fm2 == 0x358 and fs3 == 0 and fe3 == 0x1b and fm3 == 0x2cc and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7b79; op2val:0x2f58;
op3val:0x6ecc; valaddr_reg:x3; val_offset:2865*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 2865*FLEN/8, x4, x1, x2)

inst_956:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x379 and fs2 == 0 and fe2 == 0x0b and fm2 == 0x358 and fs3 == 0 and fe3 == 0x1b and fm3 == 0x2cc and fcsr == 0x20 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7b79; op2val:0x2f58;
op3val:0x6ecc; valaddr_reg:x3; val_offset:2868*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:32 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 32, 0, x3, 2868*FLEN/8, x4, x1, x2)

inst_957:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x379 and fs2 == 0 and fe2 == 0x0b and fm2 == 0x358 and fs3 == 0 and fe3 == 0x1b and fm3 == 0x2cc and fcsr == 0x40 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7b79; op2val:0x2f58;
op3val:0x6ecc; valaddr_reg:x3; val_offset:2871*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:64 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 64, 0, x3, 2871*FLEN/8, x4, x1, x2)

inst_958:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x379 and fs2 == 0 and fe2 == 0x0b and fm2 == 0x358 and fs3 == 0 and fe3 == 0x1b and fm3 == 0x2cc and fcsr == 0x60 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7b79; op2val:0x2f58;
op3val:0x6ecc; valaddr_reg:x3; val_offset:2874*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 96, 0, x3, 2874*FLEN/8, x4, x1, x2)

inst_959:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x379 and fs2 == 0 and fe2 == 0x0b and fm2 == 0x358 and fs3 == 0 and fe3 == 0x1b and fm3 == 0x2cc and fcsr == 0x80 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7b79; op2val:0x2f58;
op3val:0x6ecc; valaddr_reg:x3; val_offset:2877*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:128 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 128, 0, x3, 2877*FLEN/8, x4, x1, x2)

inst_960:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x28c and fs2 == 0 and fe2 == 0x0e and fm2 == 0x03b and fs3 == 0 and fe3 == 0x1d and fm3 == 0x2e9 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7a8c; op2val:0x383b;
op3val:0x76e9; valaddr_reg:x3; val_offset:2880*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 2880*FLEN/8, x4, x1, x2)

inst_961:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x28c and fs2 == 0 and fe2 == 0x0e and fm2 == 0x03b and fs3 == 0 and fe3 == 0x1d and fm3 == 0x2e9 and fcsr == 0x20 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7a8c; op2val:0x383b;
op3val:0x76e9; valaddr_reg:x3; val_offset:2883*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:32 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 32, 0, x3, 2883*FLEN/8, x4, x1, x2)

inst_962:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x28c and fs2 == 0 and fe2 == 0x0e and fm2 == 0x03b and fs3 == 0 and fe3 == 0x1d and fm3 == 0x2e9 and fcsr == 0x40 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7a8c; op2val:0x383b;
op3val:0x76e9; valaddr_reg:x3; val_offset:2886*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:64 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 64, 0, x3, 2886*FLEN/8, x4, x1, x2)

inst_963:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x28c and fs2 == 0 and fe2 == 0x0e and fm2 == 0x03b and fs3 == 0 and fe3 == 0x1d and fm3 == 0x2e9 and fcsr == 0x60 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7a8c; op2val:0x383b;
op3val:0x76e9; valaddr_reg:x3; val_offset:2889*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 96, 0, x3, 2889*FLEN/8, x4, x1, x2)

inst_964:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x28c and fs2 == 0 and fe2 == 0x0e and fm2 == 0x03b and fs3 == 0 and fe3 == 0x1d and fm3 == 0x2e9 and fcsr == 0x80 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7a8c; op2val:0x383b;
op3val:0x76e9; valaddr_reg:x3; val_offset:2892*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:128 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 128, 0, x3, 2892*FLEN/8, x4, x1, x2)

inst_965:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x3ea and fs2 == 0 and fe2 == 0x0f and fm2 == 0x2c0 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x2ac and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x77ea; op2val:0x3ec0;
op3val:0x7aac; valaddr_reg:x3; val_offset:2895*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 2895*FLEN/8, x4, x1, x2)

inst_966:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x3ea and fs2 == 0 and fe2 == 0x0f and fm2 == 0x2c0 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x2ac and fcsr == 0x20 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x77ea; op2val:0x3ec0;
op3val:0x7aac; valaddr_reg:x3; val_offset:2898*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:32 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 32, 0, x3, 2898*FLEN/8, x4, x1, x2)

inst_967:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x3ea and fs2 == 0 and fe2 == 0x0f and fm2 == 0x2c0 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x2ac and fcsr == 0x40 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x77ea; op2val:0x3ec0;
op3val:0x7aac; valaddr_reg:x3; val_offset:2901*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:64 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 64, 0, x3, 2901*FLEN/8, x4, x1, x2)

inst_968:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x3ea and fs2 == 0 and fe2 == 0x0f and fm2 == 0x2c0 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x2ac and fcsr == 0x60 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x77ea; op2val:0x3ec0;
op3val:0x7aac; valaddr_reg:x3; val_offset:2904*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 96, 0, x3, 2904*FLEN/8, x4, x1, x2)

inst_969:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x3ea and fs2 == 0 and fe2 == 0x0f and fm2 == 0x2c0 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x2ac and fcsr == 0x80 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x77ea; op2val:0x3ec0;
op3val:0x7aac; valaddr_reg:x3; val_offset:2907*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:128 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 128, 0, x3, 2907*FLEN/8, x4, x1, x2)

inst_970:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x249 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x12a and fs3 == 0 and fe3 == 0x1e and fm3 == 0x00d and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7649; op2val:0x3d2a;
op3val:0x780d; valaddr_reg:x3; val_offset:2910*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 2910*FLEN/8, x4, x1, x2)

inst_971:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x249 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x12a and fs3 == 0 and fe3 == 0x1e and fm3 == 0x00d and fcsr == 0x20 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7649; op2val:0x3d2a;
op3val:0x780d; valaddr_reg:x3; val_offset:2913*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:32 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 32, 0, x3, 2913*FLEN/8, x4, x1, x2)

inst_972:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x249 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x12a and fs3 == 0 and fe3 == 0x1e and fm3 == 0x00d and fcsr == 0x40 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7649; op2val:0x3d2a;
op3val:0x780d; valaddr_reg:x3; val_offset:2916*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:64 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 64, 0, x3, 2916*FLEN/8, x4, x1, x2)

inst_973:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x249 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x12a and fs3 == 0 and fe3 == 0x1e and fm3 == 0x00d and fcsr == 0x60 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7649; op2val:0x3d2a;
op3val:0x780d; valaddr_reg:x3; val_offset:2919*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 96, 0, x3, 2919*FLEN/8, x4, x1, x2)

inst_974:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x249 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x12a and fs3 == 0 and fe3 == 0x1e and fm3 == 0x00d and fcsr == 0x80 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7649; op2val:0x3d2a;
op3val:0x780d; valaddr_reg:x3; val_offset:2922*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:128 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 128, 0, x3, 2922*FLEN/8, x4, x1, x2)

inst_975:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x17f and fs2 == 0 and fe2 == 0x0f and fm2 == 0x1b8 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3db and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x797f; op2val:0x3db8;
op3val:0x7bdb; valaddr_reg:x3; val_offset:2925*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 2925*FLEN/8, x4, x1, x2)

inst_976:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x17f and fs2 == 0 and fe2 == 0x0f and fm2 == 0x1b8 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3db and fcsr == 0x20 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x797f; op2val:0x3db8;
op3val:0x7bdb; valaddr_reg:x3; val_offset:2928*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:32 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 32, 0, x3, 2928*FLEN/8, x4, x1, x2)

inst_977:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x17f and fs2 == 0 and fe2 == 0x0f and fm2 == 0x1b8 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3db and fcsr == 0x40 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x797f; op2val:0x3db8;
op3val:0x7bdb; valaddr_reg:x3; val_offset:2931*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:64 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 64, 0, x3, 2931*FLEN/8, x4, x1, x2)

inst_978:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x17f and fs2 == 0 and fe2 == 0x0f and fm2 == 0x1b8 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3db and fcsr == 0x60 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x797f; op2val:0x3db8;
op3val:0x7bdb; valaddr_reg:x3; val_offset:2934*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 96, 0, x3, 2934*FLEN/8, x4, x1, x2)

inst_979:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x17f and fs2 == 0 and fe2 == 0x0f and fm2 == 0x1b8 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3db and fcsr == 0x80 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x797f; op2val:0x3db8;
op3val:0x7bdb; valaddr_reg:x3; val_offset:2937*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:128 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 128, 0, x3, 2937*FLEN/8, x4, x1, x2)

inst_980:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x17b and fs2 == 0 and fe2 == 0x10 and fm2 == 0x0db and fs3 == 0 and fe3 == 0x1e and fm3 == 0x2a7 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x757b; op2val:0x40db;
op3val:0x7aa7; valaddr_reg:x3; val_offset:2940*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 2940*FLEN/8, x4, x1, x2)

inst_981:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x17b and fs2 == 0 and fe2 == 0x10 and fm2 == 0x0db and fs3 == 0 and fe3 == 0x1e and fm3 == 0x2a7 and fcsr == 0x20 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x757b; op2val:0x40db;
op3val:0x7aa7; valaddr_reg:x3; val_offset:2943*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:32 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 32, 0, x3, 2943*FLEN/8, x4, x1, x2)

inst_982:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x17b and fs2 == 0 and fe2 == 0x10 and fm2 == 0x0db and fs3 == 0 and fe3 == 0x1e and fm3 == 0x2a7 and fcsr == 0x40 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x757b; op2val:0x40db;
op3val:0x7aa7; valaddr_reg:x3; val_offset:2946*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:64 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 64, 0, x3, 2946*FLEN/8, x4, x1, x2)

inst_983:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x17b and fs2 == 0 and fe2 == 0x10 and fm2 == 0x0db and fs3 == 0 and fe3 == 0x1e and fm3 == 0x2a7 and fcsr == 0x60 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x757b; op2val:0x40db;
op3val:0x7aa7; valaddr_reg:x3; val_offset:2949*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 96, 0, x3, 2949*FLEN/8, x4, x1, x2)

inst_984:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x17b and fs2 == 0 and fe2 == 0x10 and fm2 == 0x0db and fs3 == 0 and fe3 == 0x1e and fm3 == 0x2a7 and fcsr == 0x80 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x757b; op2val:0x40db;
op3val:0x7aa7; valaddr_reg:x3; val_offset:2952*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:128 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 128, 0, x3, 2952*FLEN/8, x4, x1, x2)

inst_985:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1a6 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x332 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x115 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x79a6; op2val:0x3b32;
op3val:0x7915; valaddr_reg:x3; val_offset:2955*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 2955*FLEN/8, x4, x1, x2)

inst_986:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1a6 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x332 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x115 and fcsr == 0x20 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x79a6; op2val:0x3b32;
op3val:0x7915; valaddr_reg:x3; val_offset:2958*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:32 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 32, 0, x3, 2958*FLEN/8, x4, x1, x2)

inst_987:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1a6 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x332 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x115 and fcsr == 0x40 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x79a6; op2val:0x3b32;
op3val:0x7915; valaddr_reg:x3; val_offset:2961*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:64 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 64, 0, x3, 2961*FLEN/8, x4, x1, x2)

inst_988:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1a6 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x332 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x115 and fcsr == 0x60 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x79a6; op2val:0x3b32;
op3val:0x7915; valaddr_reg:x3; val_offset:2964*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 96, 0, x3, 2964*FLEN/8, x4, x1, x2)

inst_989:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1a6 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x332 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x115 and fcsr == 0x80 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x79a6; op2val:0x3b32;
op3val:0x7915; valaddr_reg:x3; val_offset:2967*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:128 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 128, 0, x3, 2967*FLEN/8, x4, x1, x2)

inst_990:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x278 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x2de and fs3 == 0 and fe3 == 0x1d and fm3 == 0x18e and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7678; op2val:0x3ade;
op3val:0x758e; valaddr_reg:x3; val_offset:2970*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 2970*FLEN/8, x4, x1, x2)

inst_991:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x278 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x2de and fs3 == 0 and fe3 == 0x1d and fm3 == 0x18e and fcsr == 0x20 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7678; op2val:0x3ade;
op3val:0x758e; valaddr_reg:x3; val_offset:2973*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:32 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 32, 0, x3, 2973*FLEN/8, x4, x1, x2)

inst_992:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x278 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x2de and fs3 == 0 and fe3 == 0x1d and fm3 == 0x18e and fcsr == 0x40 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7678; op2val:0x3ade;
op3val:0x758e; valaddr_reg:x3; val_offset:2976*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:64 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 64, 0, x3, 2976*FLEN/8, x4, x1, x2)

inst_993:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x278 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x2de and fs3 == 0 and fe3 == 0x1d and fm3 == 0x18e and fcsr == 0x60 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7678; op2val:0x3ade;
op3val:0x758e; valaddr_reg:x3; val_offset:2979*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 96, 0, x3, 2979*FLEN/8, x4, x1, x2)

inst_994:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x278 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x2de and fs3 == 0 and fe3 == 0x1d and fm3 == 0x18e and fcsr == 0x80 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7678; op2val:0x3ade;
op3val:0x758e; valaddr_reg:x3; val_offset:2982*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:128 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 128, 0, x3, 2982*FLEN/8, x4, x1, x2)

inst_995:
// fs1 == 0 and fe1 == 0x1a and fm1 == 0x2f5 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x0c5 and fs3 == 0 and fe3 == 0x1c and fm3 == 0x027 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x6af5; op2val:0x40c5;
op3val:0x7027; valaddr_reg:x3; val_offset:2985*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 2985*FLEN/8, x4, x1, x2)

inst_996:
// fs1 == 0 and fe1 == 0x1a and fm1 == 0x2f5 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x0c5 and fs3 == 0 and fe3 == 0x1c and fm3 == 0x027 and fcsr == 0x20 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x6af5; op2val:0x40c5;
op3val:0x7027; valaddr_reg:x3; val_offset:2988*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:32 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 32, 0, x3, 2988*FLEN/8, x4, x1, x2)

inst_997:
// fs1 == 0 and fe1 == 0x1a and fm1 == 0x2f5 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x0c5 and fs3 == 0 and fe3 == 0x1c and fm3 == 0x027 and fcsr == 0x40 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x6af5; op2val:0x40c5;
op3val:0x7027; valaddr_reg:x3; val_offset:2991*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:64 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 64, 0, x3, 2991*FLEN/8, x4, x1, x2)

inst_998:
// fs1 == 0 and fe1 == 0x1a and fm1 == 0x2f5 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x0c5 and fs3 == 0 and fe3 == 0x1c and fm3 == 0x027 and fcsr == 0x60 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x6af5; op2val:0x40c5;
op3val:0x7027; valaddr_reg:x3; val_offset:2994*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 96, 0, x3, 2994*FLEN/8, x4, x1, x2)

inst_999:
// fs1 == 0 and fe1 == 0x1a and fm1 == 0x2f5 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x0c5 and fs3 == 0 and fe3 == 0x1c and fm3 == 0x027 and fcsr == 0x80 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x6af5; op2val:0x40c5;
op3val:0x7027; valaddr_reg:x3; val_offset:2997*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:128 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 128, 0, x3, 2997*FLEN/8, x4, x1, x2)

inst_1000:
// fs1 == 0 and fe1 == 0x1b and fm1 == 0x086 and fs2 == 0 and fe2 == 0x12 and fm2 == 0x13c and fs3 == 0 and fe3 == 0x1e and fm3 == 0x1ec and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x6c86; op2val:0x493c;
op3val:0x79ec; valaddr_reg:x3; val_offset:3000*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 3000*FLEN/8, x4, x1, x2)

inst_1001:
// fs1 == 0 and fe1 == 0x1b and fm1 == 0x086 and fs2 == 0 and fe2 == 0x12 and fm2 == 0x13c and fs3 == 0 and fe3 == 0x1e and fm3 == 0x1ec and fcsr == 0x20 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x6c86; op2val:0x493c;
op3val:0x79ec; valaddr_reg:x3; val_offset:3003*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:32 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 32, 0, x3, 3003*FLEN/8, x4, x1, x2)

inst_1002:
// fs1 == 0 and fe1 == 0x1b and fm1 == 0x086 and fs2 == 0 and fe2 == 0x12 and fm2 == 0x13c and fs3 == 0 and fe3 == 0x1e and fm3 == 0x1ec and fcsr == 0x40 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x6c86; op2val:0x493c;
op3val:0x79ec; valaddr_reg:x3; val_offset:3006*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:64 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 64, 0, x3, 3006*FLEN/8, x4, x1, x2)

inst_1003:
// fs1 == 0 and fe1 == 0x1b and fm1 == 0x086 and fs2 == 0 and fe2 == 0x12 and fm2 == 0x13c and fs3 == 0 and fe3 == 0x1e and fm3 == 0x1ec and fcsr == 0x60 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x6c86; op2val:0x493c;
op3val:0x79ec; valaddr_reg:x3; val_offset:3009*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 96, 0, x3, 3009*FLEN/8, x4, x1, x2)

inst_1004:
// fs1 == 0 and fe1 == 0x1b and fm1 == 0x086 and fs2 == 0 and fe2 == 0x12 and fm2 == 0x13c and fs3 == 0 and fe3 == 0x1e and fm3 == 0x1ec and fcsr == 0x80 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x6c86; op2val:0x493c;
op3val:0x79ec; valaddr_reg:x3; val_offset:3012*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:128 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 128, 0, x3, 3012*FLEN/8, x4, x1, x2)

inst_1005:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x016 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x11c and fs3 == 0 and fe3 == 0x1c and fm3 == 0x138 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7416; op2val:0x391c;
op3val:0x7138; valaddr_reg:x3; val_offset:3015*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 3015*FLEN/8, x4, x1, x2)

inst_1006:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x016 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x11c and fs3 == 0 and fe3 == 0x1c and fm3 == 0x138 and fcsr == 0x20 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7416; op2val:0x391c;
op3val:0x7138; valaddr_reg:x3; val_offset:3018*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:32 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 32, 0, x3, 3018*FLEN/8, x4, x1, x2)

inst_1007:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x016 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x11c and fs3 == 0 and fe3 == 0x1c and fm3 == 0x138 and fcsr == 0x40 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7416; op2val:0x391c;
op3val:0x7138; valaddr_reg:x3; val_offset:3021*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:64 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 64, 0, x3, 3021*FLEN/8, x4, x1, x2)

inst_1008:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x016 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x11c and fs3 == 0 and fe3 == 0x1c and fm3 == 0x138 and fcsr == 0x60 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7416; op2val:0x391c;
op3val:0x7138; valaddr_reg:x3; val_offset:3024*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 96, 0, x3, 3024*FLEN/8, x4, x1, x2)

inst_1009:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x016 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x11c and fs3 == 0 and fe3 == 0x1c and fm3 == 0x138 and fcsr == 0x80 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7416; op2val:0x391c;
op3val:0x7138; valaddr_reg:x3; val_offset:3027*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:128 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 128, 0, x3, 3027*FLEN/8, x4, x1, x2)

inst_1010:
// fs1 == 0 and fe1 == 0x1b and fm1 == 0x167 and fs2 == 0 and fe2 == 0x12 and fm2 == 0x0fa and fs3 == 0 and fe3 == 0x1e and fm3 == 0x2ba and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x6d67; op2val:0x48fa;
op3val:0x7aba; valaddr_reg:x3; val_offset:3030*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 3030*FLEN/8, x4, x1, x2)

inst_1011:
// fs1 == 0 and fe1 == 0x1b and fm1 == 0x167 and fs2 == 0 and fe2 == 0x12 and fm2 == 0x0fa and fs3 == 0 and fe3 == 0x1e and fm3 == 0x2ba and fcsr == 0x20 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x6d67; op2val:0x48fa;
op3val:0x7aba; valaddr_reg:x3; val_offset:3033*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:32 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 32, 0, x3, 3033*FLEN/8, x4, x1, x2)

inst_1012:
// fs1 == 0 and fe1 == 0x1b and fm1 == 0x167 and fs2 == 0 and fe2 == 0x12 and fm2 == 0x0fa and fs3 == 0 and fe3 == 0x1e and fm3 == 0x2ba and fcsr == 0x40 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x6d67; op2val:0x48fa;
op3val:0x7aba; valaddr_reg:x3; val_offset:3036*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:64 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 64, 0, x3, 3036*FLEN/8, x4, x1, x2)

inst_1013:
// fs1 == 0 and fe1 == 0x1b and fm1 == 0x167 and fs2 == 0 and fe2 == 0x12 and fm2 == 0x0fa and fs3 == 0 and fe3 == 0x1e and fm3 == 0x2ba and fcsr == 0x60 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x6d67; op2val:0x48fa;
op3val:0x7aba; valaddr_reg:x3; val_offset:3039*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 96, 0, x3, 3039*FLEN/8, x4, x1, x2)

inst_1014:
// fs1 == 0 and fe1 == 0x1b and fm1 == 0x167 and fs2 == 0 and fe2 == 0x12 and fm2 == 0x0fa and fs3 == 0 and fe3 == 0x1e and fm3 == 0x2ba and fcsr == 0x80 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x6d67; op2val:0x48fa;
op3val:0x7aba; valaddr_reg:x3; val_offset:3042*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:128 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 128, 0, x3, 3042*FLEN/8, x4, x1, x2)

inst_1015:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2f5 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x229 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x15c and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7af5; op2val:0x3a29;
op3val:0x795c; valaddr_reg:x3; val_offset:3045*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 3045*FLEN/8, x4, x1, x2)

inst_1016:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2f5 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x229 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x15c and fcsr == 0x20 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7af5; op2val:0x3a29;
op3val:0x795c; valaddr_reg:x3; val_offset:3048*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:32 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 32, 0, x3, 3048*FLEN/8, x4, x1, x2)

inst_1017:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2f5 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x229 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x15c and fcsr == 0x40 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7af5; op2val:0x3a29;
op3val:0x795c; valaddr_reg:x3; val_offset:3051*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:64 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 64, 0, x3, 3051*FLEN/8, x4, x1, x2)

inst_1018:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2f5 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x229 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x15c and fcsr == 0x60 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7af5; op2val:0x3a29;
op3val:0x795c; valaddr_reg:x3; val_offset:3054*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 96, 0, x3, 3054*FLEN/8, x4, x1, x2)

inst_1019:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2f5 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x229 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x15c and fcsr == 0x80 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7af5; op2val:0x3a29;
op3val:0x795c; valaddr_reg:x3; val_offset:3057*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:128 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 128, 0, x3, 3057*FLEN/8, x4, x1, x2)

inst_1020:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x082 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x2df and fs3 == 0 and fe3 == 0x1c and fm3 == 0x3bf and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7482; op2val:0x3adf;
op3val:0x73bf; valaddr_reg:x3; val_offset:3060*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 3060*FLEN/8, x4, x1, x2)

inst_1021:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x082 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x2df and fs3 == 0 and fe3 == 0x1c and fm3 == 0x3bf and fcsr == 0x20 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7482; op2val:0x3adf;
op3val:0x73bf; valaddr_reg:x3; val_offset:3063*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:32 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 32, 0, x3, 3063*FLEN/8, x4, x1, x2)

inst_1022:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x082 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x2df and fs3 == 0 and fe3 == 0x1c and fm3 == 0x3bf and fcsr == 0x40 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7482; op2val:0x3adf;
op3val:0x73bf; valaddr_reg:x3; val_offset:3066*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:64 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 64, 0, x3, 3066*FLEN/8, x4, x1, x2)

inst_1023:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x082 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x2df and fs3 == 0 and fe3 == 0x1c and fm3 == 0x3bf and fcsr == 0x60 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7482; op2val:0x3adf;
op3val:0x73bf; valaddr_reg:x3; val_offset:3069*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 96, 0, x3, 3069*FLEN/8, x4, x1, x2)
RVTEST_SIGBASE(x1,signature_x1_9)

inst_1024:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x082 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x2df and fs3 == 0 and fe3 == 0x1c and fm3 == 0x3bf and fcsr == 0x80 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7482; op2val:0x3adf;
op3val:0x73bf; valaddr_reg:x3; val_offset:3072*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:128 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 128, 0, x3, 3072*FLEN/8, x4, x1, x2)

inst_1025:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x0af and fs2 == 0 and fe2 == 0x0f and fm2 == 0x245 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x359 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x74af; op2val:0x3e45;
op3val:0x7759; valaddr_reg:x3; val_offset:3075*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 3075*FLEN/8, x4, x1, x2)

inst_1026:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x0af and fs2 == 0 and fe2 == 0x0f and fm2 == 0x245 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x359 and fcsr == 0x20 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x74af; op2val:0x3e45;
op3val:0x7759; valaddr_reg:x3; val_offset:3078*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:32 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 32, 0, x3, 3078*FLEN/8, x4, x1, x2)

inst_1027:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x0af and fs2 == 0 and fe2 == 0x0f and fm2 == 0x245 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x359 and fcsr == 0x40 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x74af; op2val:0x3e45;
op3val:0x7759; valaddr_reg:x3; val_offset:3081*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:64 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 64, 0, x3, 3081*FLEN/8, x4, x1, x2)

inst_1028:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x0af and fs2 == 0 and fe2 == 0x0f and fm2 == 0x245 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x359 and fcsr == 0x60 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x74af; op2val:0x3e45;
op3val:0x7759; valaddr_reg:x3; val_offset:3084*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 96, 0, x3, 3084*FLEN/8, x4, x1, x2)

inst_1029:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x0af and fs2 == 0 and fe2 == 0x0f and fm2 == 0x245 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x359 and fcsr == 0x80 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x74af; op2val:0x3e45;
op3val:0x7759; valaddr_reg:x3; val_offset:3087*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:128 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 128, 0, x3, 3087*FLEN/8, x4, x1, x2)

inst_1030:
// fs1 == 0 and fe1 == 0x1c and fm1 == 0x109 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x1a8 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x321 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7109; op2val:0x41a8;
op3val:0x7721; valaddr_reg:x3; val_offset:3090*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 3090*FLEN/8, x4, x1, x2)

inst_1031:
// fs1 == 0 and fe1 == 0x1c and fm1 == 0x109 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x1a8 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x321 and fcsr == 0x20 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7109; op2val:0x41a8;
op3val:0x7721; valaddr_reg:x3; val_offset:3093*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:32 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 32, 0, x3, 3093*FLEN/8, x4, x1, x2)

inst_1032:
// fs1 == 0 and fe1 == 0x1c and fm1 == 0x109 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x1a8 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x321 and fcsr == 0x40 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7109; op2val:0x41a8;
op3val:0x7721; valaddr_reg:x3; val_offset:3096*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:64 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 64, 0, x3, 3096*FLEN/8, x4, x1, x2)

inst_1033:
// fs1 == 0 and fe1 == 0x1c and fm1 == 0x109 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x1a8 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x321 and fcsr == 0x60 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7109; op2val:0x41a8;
op3val:0x7721; valaddr_reg:x3; val_offset:3099*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 96, 0, x3, 3099*FLEN/8, x4, x1, x2)

inst_1034:
// fs1 == 0 and fe1 == 0x1c and fm1 == 0x109 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x1a8 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x321 and fcsr == 0x80 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7109; op2val:0x41a8;
op3val:0x7721; valaddr_reg:x3; val_offset:3102*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:128 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 128, 0, x3, 3102*FLEN/8, x4, x1, x2)

inst_1035:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x035 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x34e and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3b0 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7435; op2val:0x434e;
op3val:0x7bb0; valaddr_reg:x3; val_offset:3105*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 3105*FLEN/8, x4, x1, x2)

inst_1036:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x035 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x34e and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3b0 and fcsr == 0x20 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7435; op2val:0x434e;
op3val:0x7bb0; valaddr_reg:x3; val_offset:3108*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:32 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 32, 0, x3, 3108*FLEN/8, x4, x1, x2)

inst_1037:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x035 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x34e and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3b0 and fcsr == 0x40 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7435; op2val:0x434e;
op3val:0x7bb0; valaddr_reg:x3; val_offset:3111*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:64 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 64, 0, x3, 3111*FLEN/8, x4, x1, x2)

inst_1038:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x035 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x34e and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3b0 and fcsr == 0x60 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7435; op2val:0x434e;
op3val:0x7bb0; valaddr_reg:x3; val_offset:3114*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 96, 0, x3, 3114*FLEN/8, x4, x1, x2)

inst_1039:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x035 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x34e and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3b0 and fcsr == 0x80 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7435; op2val:0x434e;
op3val:0x7bb0; valaddr_reg:x3; val_offset:3117*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:128 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 128, 0, x3, 3117*FLEN/8, x4, x1, x2)

inst_1040:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3c6 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x07f and fs3 == 0 and fe3 == 0x1e and fm3 == 0x05f and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7bc6; op2val:0x387f;
op3val:0x785f; valaddr_reg:x3; val_offset:3120*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 3120*FLEN/8, x4, x1, x2)

inst_1041:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3c6 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x07f and fs3 == 0 and fe3 == 0x1e and fm3 == 0x05f and fcsr == 0x20 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7bc6; op2val:0x387f;
op3val:0x785f; valaddr_reg:x3; val_offset:3123*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:32 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 32, 0, x3, 3123*FLEN/8, x4, x1, x2)

inst_1042:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3c6 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x07f and fs3 == 0 and fe3 == 0x1e and fm3 == 0x05f and fcsr == 0x40 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7bc6; op2val:0x387f;
op3val:0x785f; valaddr_reg:x3; val_offset:3126*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:64 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 64, 0, x3, 3126*FLEN/8, x4, x1, x2)

inst_1043:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3c6 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x07f and fs3 == 0 and fe3 == 0x1e and fm3 == 0x05f and fcsr == 0x60 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7bc6; op2val:0x387f;
op3val:0x785f; valaddr_reg:x3; val_offset:3129*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 96, 0, x3, 3129*FLEN/8, x4, x1, x2)

inst_1044:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3c6 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x07f and fs3 == 0 and fe3 == 0x1e and fm3 == 0x05f and fcsr == 0x80 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7bc6; op2val:0x387f;
op3val:0x785f; valaddr_reg:x3; val_offset:3132*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:128 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 128, 0, x3, 3132*FLEN/8, x4, x1, x2)

inst_1045:
// fs1 == 0 and fe1 == 0x1c and fm1 == 0x3d1 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x3e6 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3b8 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x73d1; op2val:0x43e6;
op3val:0x7bb8; valaddr_reg:x3; val_offset:3135*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 3135*FLEN/8, x4, x1, x2)

inst_1046:
// fs1 == 0 and fe1 == 0x1c and fm1 == 0x3d1 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x3e6 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3b8 and fcsr == 0x20 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x73d1; op2val:0x43e6;
op3val:0x7bb8; valaddr_reg:x3; val_offset:3138*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:32 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 32, 0, x3, 3138*FLEN/8, x4, x1, x2)

inst_1047:
// fs1 == 0 and fe1 == 0x1c and fm1 == 0x3d1 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x3e6 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3b8 and fcsr == 0x40 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x73d1; op2val:0x43e6;
op3val:0x7bb8; valaddr_reg:x3; val_offset:3141*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:64 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 64, 0, x3, 3141*FLEN/8, x4, x1, x2)

inst_1048:
// fs1 == 0 and fe1 == 0x1c and fm1 == 0x3d1 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x3e6 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3b8 and fcsr == 0x60 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x73d1; op2val:0x43e6;
op3val:0x7bb8; valaddr_reg:x3; val_offset:3144*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 96, 0, x3, 3144*FLEN/8, x4, x1, x2)

inst_1049:
// fs1 == 0 and fe1 == 0x1c and fm1 == 0x3d1 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x3e6 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3b8 and fcsr == 0x80 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x73d1; op2val:0x43e6;
op3val:0x7bb8; valaddr_reg:x3; val_offset:3147*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:128 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 128, 0, x3, 3147*FLEN/8, x4, x1, x2)

inst_1050:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x0f3 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x09b and fs3 == 0 and fe3 == 0x1d and fm3 == 0x1b3 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x74f3; op2val:0x3c9b;
op3val:0x75b3; valaddr_reg:x3; val_offset:3150*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 3150*FLEN/8, x4, x1, x2)

inst_1051:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x0f3 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x09b and fs3 == 0 and fe3 == 0x1d and fm3 == 0x1b3 and fcsr == 0x20 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x74f3; op2val:0x3c9b;
op3val:0x75b3; valaddr_reg:x3; val_offset:3153*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:32 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 32, 0, x3, 3153*FLEN/8, x4, x1, x2)

inst_1052:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x0f3 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x09b and fs3 == 0 and fe3 == 0x1d and fm3 == 0x1b3 and fcsr == 0x40 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x74f3; op2val:0x3c9b;
op3val:0x75b3; valaddr_reg:x3; val_offset:3156*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:64 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 64, 0, x3, 3156*FLEN/8, x4, x1, x2)

inst_1053:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x0f3 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x09b and fs3 == 0 and fe3 == 0x1d and fm3 == 0x1b3 and fcsr == 0x60 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x74f3; op2val:0x3c9b;
op3val:0x75b3; valaddr_reg:x3; val_offset:3159*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 96, 0, x3, 3159*FLEN/8, x4, x1, x2)

inst_1054:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x0f3 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x09b and fs3 == 0 and fe3 == 0x1d and fm3 == 0x1b3 and fcsr == 0x80 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x74f3; op2val:0x3c9b;
op3val:0x75b3; valaddr_reg:x3; val_offset:3162*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:128 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 128, 0, x3, 3162*FLEN/8, x4, x1, x2)

inst_1055:
// fs1 == 0 and fe1 == 0x15 and fm1 == 0x070 and fs2 == 0 and fe2 == 0x17 and fm2 == 0x180 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x21a and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x5470; op2val:0x5d80;
op3val:0x761a; valaddr_reg:x3; val_offset:3165*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 3165*FLEN/8, x4, x1, x2)

inst_1056:
// fs1 == 0 and fe1 == 0x15 and fm1 == 0x070 and fs2 == 0 and fe2 == 0x17 and fm2 == 0x180 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x21a and fcsr == 0x20 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x5470; op2val:0x5d80;
op3val:0x761a; valaddr_reg:x3; val_offset:3168*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:32 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 32, 0, x3, 3168*FLEN/8, x4, x1, x2)

inst_1057:
// fs1 == 0 and fe1 == 0x15 and fm1 == 0x070 and fs2 == 0 and fe2 == 0x17 and fm2 == 0x180 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x21a and fcsr == 0x40 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x5470; op2val:0x5d80;
op3val:0x761a; valaddr_reg:x3; val_offset:3171*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:64 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 64, 0, x3, 3171*FLEN/8, x4, x1, x2)

inst_1058:
// fs1 == 0 and fe1 == 0x15 and fm1 == 0x070 and fs2 == 0 and fe2 == 0x17 and fm2 == 0x180 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x21a and fcsr == 0x60 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x5470; op2val:0x5d80;
op3val:0x761a; valaddr_reg:x3; val_offset:3174*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 96, 0, x3, 3174*FLEN/8, x4, x1, x2)

inst_1059:
// fs1 == 0 and fe1 == 0x15 and fm1 == 0x070 and fs2 == 0 and fe2 == 0x17 and fm2 == 0x180 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x21a and fcsr == 0x80 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x5470; op2val:0x5d80;
op3val:0x761a; valaddr_reg:x3; val_offset:3177*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:128 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 128, 0, x3, 3177*FLEN/8, x4, x1, x2)

inst_1060:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x397 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x03c and fs3 == 0 and fe3 == 0x1e and fm3 == 0x005 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7797; op2val:0x3c3c;
op3val:0x7805; valaddr_reg:x3; val_offset:3180*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 3180*FLEN/8, x4, x1, x2)

inst_1061:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x397 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x03c and fs3 == 0 and fe3 == 0x1e and fm3 == 0x005 and fcsr == 0x20 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7797; op2val:0x3c3c;
op3val:0x7805; valaddr_reg:x3; val_offset:3183*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:32 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 32, 0, x3, 3183*FLEN/8, x4, x1, x2)

inst_1062:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x397 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x03c and fs3 == 0 and fe3 == 0x1e and fm3 == 0x005 and fcsr == 0x40 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7797; op2val:0x3c3c;
op3val:0x7805; valaddr_reg:x3; val_offset:3186*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:64 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 64, 0, x3, 3186*FLEN/8, x4, x1, x2)

inst_1063:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x397 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x03c and fs3 == 0 and fe3 == 0x1e and fm3 == 0x005 and fcsr == 0x60 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7797; op2val:0x3c3c;
op3val:0x7805; valaddr_reg:x3; val_offset:3189*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 96, 0, x3, 3189*FLEN/8, x4, x1, x2)

inst_1064:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x397 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x03c and fs3 == 0 and fe3 == 0x1e and fm3 == 0x005 and fcsr == 0x80 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7797; op2val:0x3c3c;
op3val:0x7805; valaddr_reg:x3; val_offset:3192*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:128 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 128, 0, x3, 3192*FLEN/8, x4, x1, x2)

inst_1065:
// fs1 == 0 and fe1 == 0x1c and fm1 == 0x26d and fs2 == 0 and fe2 == 0x10 and fm2 == 0x105 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x009 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x726d; op2val:0x4105;
op3val:0x7809; valaddr_reg:x3; val_offset:3195*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 3195*FLEN/8, x4, x1, x2)

inst_1066:
// fs1 == 0 and fe1 == 0x1c and fm1 == 0x26d and fs2 == 0 and fe2 == 0x10 and fm2 == 0x105 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x009 and fcsr == 0x20 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x726d; op2val:0x4105;
op3val:0x7809; valaddr_reg:x3; val_offset:3198*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:32 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 32, 0, x3, 3198*FLEN/8, x4, x1, x2)

inst_1067:
// fs1 == 0 and fe1 == 0x1c and fm1 == 0x26d and fs2 == 0 and fe2 == 0x10 and fm2 == 0x105 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x009 and fcsr == 0x40 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x726d; op2val:0x4105;
op3val:0x7809; valaddr_reg:x3; val_offset:3201*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:64 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 64, 0, x3, 3201*FLEN/8, x4, x1, x2)

inst_1068:
// fs1 == 0 and fe1 == 0x1c and fm1 == 0x26d and fs2 == 0 and fe2 == 0x10 and fm2 == 0x105 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x009 and fcsr == 0x60 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x726d; op2val:0x4105;
op3val:0x7809; valaddr_reg:x3; val_offset:3204*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 96, 0, x3, 3204*FLEN/8, x4, x1, x2)

inst_1069:
// fs1 == 0 and fe1 == 0x1c and fm1 == 0x26d and fs2 == 0 and fe2 == 0x10 and fm2 == 0x105 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x009 and fcsr == 0x80 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x726d; op2val:0x4105;
op3val:0x7809; valaddr_reg:x3; val_offset:3207*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:128 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 128, 0, x3, 3207*FLEN/8, x4, x1, x2)

inst_1070:
// fs1 == 0 and fe1 == 0x17 and fm1 == 0x115 and fs2 == 0 and fe2 == 0x14 and fm2 == 0x2a6 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x039 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x5d15; op2val:0x52a6;
op3val:0x7439; valaddr_reg:x3; val_offset:3210*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 3210*FLEN/8, x4, x1, x2)

inst_1071:
// fs1 == 0 and fe1 == 0x17 and fm1 == 0x115 and fs2 == 0 and fe2 == 0x14 and fm2 == 0x2a6 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x039 and fcsr == 0x20 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x5d15; op2val:0x52a6;
op3val:0x7439; valaddr_reg:x3; val_offset:3213*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:32 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 32, 0, x3, 3213*FLEN/8, x4, x1, x2)

inst_1072:
// fs1 == 0 and fe1 == 0x17 and fm1 == 0x115 and fs2 == 0 and fe2 == 0x14 and fm2 == 0x2a6 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x039 and fcsr == 0x40 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x5d15; op2val:0x52a6;
op3val:0x7439; valaddr_reg:x3; val_offset:3216*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:64 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 64, 0, x3, 3216*FLEN/8, x4, x1, x2)

inst_1073:
// fs1 == 0 and fe1 == 0x17 and fm1 == 0x115 and fs2 == 0 and fe2 == 0x14 and fm2 == 0x2a6 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x039 and fcsr == 0x60 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x5d15; op2val:0x52a6;
op3val:0x7439; valaddr_reg:x3; val_offset:3219*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 96, 0, x3, 3219*FLEN/8, x4, x1, x2)

inst_1074:
// fs1 == 0 and fe1 == 0x17 and fm1 == 0x115 and fs2 == 0 and fe2 == 0x14 and fm2 == 0x2a6 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x039 and fcsr == 0x80 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x5d15; op2val:0x52a6;
op3val:0x7439; valaddr_reg:x3; val_offset:3222*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:128 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 128, 0, x3, 3222*FLEN/8, x4, x1, x2)

inst_1075:
// fs1 == 0 and fe1 == 0x1b and fm1 == 0x1be and fs2 == 0 and fe2 == 0x11 and fm2 == 0x073 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x263 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x6dbe; op2val:0x4473;
op3val:0x7663; valaddr_reg:x3; val_offset:3225*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 3225*FLEN/8, x4, x1, x2)

inst_1076:
// fs1 == 0 and fe1 == 0x1b and fm1 == 0x1be and fs2 == 0 and fe2 == 0x11 and fm2 == 0x073 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x263 and fcsr == 0x20 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x6dbe; op2val:0x4473;
op3val:0x7663; valaddr_reg:x3; val_offset:3228*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:32 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 32, 0, x3, 3228*FLEN/8, x4, x1, x2)

inst_1077:
// fs1 == 0 and fe1 == 0x1b and fm1 == 0x1be and fs2 == 0 and fe2 == 0x11 and fm2 == 0x073 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x263 and fcsr == 0x40 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x6dbe; op2val:0x4473;
op3val:0x7663; valaddr_reg:x3; val_offset:3231*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:64 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 64, 0, x3, 3231*FLEN/8, x4, x1, x2)

inst_1078:
// fs1 == 0 and fe1 == 0x1b and fm1 == 0x1be and fs2 == 0 and fe2 == 0x11 and fm2 == 0x073 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x263 and fcsr == 0x60 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x6dbe; op2val:0x4473;
op3val:0x7663; valaddr_reg:x3; val_offset:3234*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 96, 0, x3, 3234*FLEN/8, x4, x1, x2)

inst_1079:
// fs1 == 0 and fe1 == 0x1b and fm1 == 0x1be and fs2 == 0 and fe2 == 0x11 and fm2 == 0x073 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x263 and fcsr == 0x80 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x6dbe; op2val:0x4473;
op3val:0x7663; valaddr_reg:x3; val_offset:3237*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:128 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 128, 0, x3, 3237*FLEN/8, x4, x1, x2)

inst_1080:
// fs1 == 0 and fe1 == 0x1a and fm1 == 0x155 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x051 and fs3 == 0 and fe3 == 0x19 and fm3 == 0x1c2 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x6955; op2val:0x3851;
op3val:0x65c2; valaddr_reg:x3; val_offset:3240*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 3240*FLEN/8, x4, x1, x2)

inst_1081:
// fs1 == 0 and fe1 == 0x1a and fm1 == 0x155 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x051 and fs3 == 0 and fe3 == 0x19 and fm3 == 0x1c2 and fcsr == 0x20 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x6955; op2val:0x3851;
op3val:0x65c2; valaddr_reg:x3; val_offset:3243*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:32 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 32, 0, x3, 3243*FLEN/8, x4, x1, x2)

inst_1082:
// fs1 == 0 and fe1 == 0x1a and fm1 == 0x155 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x051 and fs3 == 0 and fe3 == 0x19 and fm3 == 0x1c2 and fcsr == 0x40 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x6955; op2val:0x3851;
op3val:0x65c2; valaddr_reg:x3; val_offset:3246*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:64 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 64, 0, x3, 3246*FLEN/8, x4, x1, x2)

inst_1083:
// fs1 == 0 and fe1 == 0x1a and fm1 == 0x155 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x051 and fs3 == 0 and fe3 == 0x19 and fm3 == 0x1c2 and fcsr == 0x60 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x6955; op2val:0x3851;
op3val:0x65c2; valaddr_reg:x3; val_offset:3249*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 96, 0, x3, 3249*FLEN/8, x4, x1, x2)

inst_1084:
// fs1 == 0 and fe1 == 0x1a and fm1 == 0x155 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x051 and fs3 == 0 and fe3 == 0x19 and fm3 == 0x1c2 and fcsr == 0x80 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x6955; op2val:0x3851;
op3val:0x65c2; valaddr_reg:x3; val_offset:3252*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:128 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 128, 0, x3, 3252*FLEN/8, x4, x1, x2)

inst_1085:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x0dd and fs2 == 0 and fe2 == 0x0e and fm2 == 0x21f and fs3 == 0 and fe3 == 0x1c and fm3 == 0x372 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x74dd; op2val:0x3a1f;
op3val:0x7372; valaddr_reg:x3; val_offset:3255*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 3255*FLEN/8, x4, x1, x2)

inst_1086:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x0dd and fs2 == 0 and fe2 == 0x0e and fm2 == 0x21f and fs3 == 0 and fe3 == 0x1c and fm3 == 0x372 and fcsr == 0x20 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x74dd; op2val:0x3a1f;
op3val:0x7372; valaddr_reg:x3; val_offset:3258*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:32 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 32, 0, x3, 3258*FLEN/8, x4, x1, x2)

inst_1087:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x0dd and fs2 == 0 and fe2 == 0x0e and fm2 == 0x21f and fs3 == 0 and fe3 == 0x1c and fm3 == 0x372 and fcsr == 0x40 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x74dd; op2val:0x3a1f;
op3val:0x7372; valaddr_reg:x3; val_offset:3261*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:64 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 64, 0, x3, 3261*FLEN/8, x4, x1, x2)

inst_1088:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x0dd and fs2 == 0 and fe2 == 0x0e and fm2 == 0x21f and fs3 == 0 and fe3 == 0x1c and fm3 == 0x372 and fcsr == 0x60 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x74dd; op2val:0x3a1f;
op3val:0x7372; valaddr_reg:x3; val_offset:3264*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 96, 0, x3, 3264*FLEN/8, x4, x1, x2)

inst_1089:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x0dd and fs2 == 0 and fe2 == 0x0e and fm2 == 0x21f and fs3 == 0 and fe3 == 0x1c and fm3 == 0x372 and fcsr == 0x80 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x74dd; op2val:0x3a1f;
op3val:0x7372; valaddr_reg:x3; val_offset:3267*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:128 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 128, 0, x3, 3267*FLEN/8, x4, x1, x2)

inst_1090:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0ae and fs2 == 0 and fe2 == 0x0e and fm2 == 0x33a and fs3 == 0 and fe3 == 0x1e and fm3 == 0x03b and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x78ae; op2val:0x3b3a;
op3val:0x783b; valaddr_reg:x3; val_offset:3270*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 3270*FLEN/8, x4, x1, x2)

inst_1091:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0ae and fs2 == 0 and fe2 == 0x0e and fm2 == 0x33a and fs3 == 0 and fe3 == 0x1e and fm3 == 0x03b and fcsr == 0x20 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x78ae; op2val:0x3b3a;
op3val:0x783b; valaddr_reg:x3; val_offset:3273*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:32 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 32, 0, x3, 3273*FLEN/8, x4, x1, x2)

inst_1092:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0ae and fs2 == 0 and fe2 == 0x0e and fm2 == 0x33a and fs3 == 0 and fe3 == 0x1e and fm3 == 0x03b and fcsr == 0x40 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x78ae; op2val:0x3b3a;
op3val:0x783b; valaddr_reg:x3; val_offset:3276*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:64 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 64, 0, x3, 3276*FLEN/8, x4, x1, x2)

inst_1093:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0ae and fs2 == 0 and fe2 == 0x0e and fm2 == 0x33a and fs3 == 0 and fe3 == 0x1e and fm3 == 0x03b and fcsr == 0x60 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x78ae; op2val:0x3b3a;
op3val:0x783b; valaddr_reg:x3; val_offset:3279*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 96, 0, x3, 3279*FLEN/8, x4, x1, x2)

inst_1094:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0ae and fs2 == 0 and fe2 == 0x0e and fm2 == 0x33a and fs3 == 0 and fe3 == 0x1e and fm3 == 0x03b and fcsr == 0x80 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x78ae; op2val:0x3b3a;
op3val:0x783b; valaddr_reg:x3; val_offset:3282*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:128 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 128, 0, x3, 3282*FLEN/8, x4, x1, x2)

inst_1095:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x200 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x302 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x142 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7a00; op2val:0x3b02;
op3val:0x7942; valaddr_reg:x3; val_offset:3285*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 3285*FLEN/8, x4, x1, x2)

inst_1096:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x200 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x302 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x142 and fcsr == 0x20 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7a00; op2val:0x3b02;
op3val:0x7942; valaddr_reg:x3; val_offset:3288*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:32 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 32, 0, x3, 3288*FLEN/8, x4, x1, x2)

inst_1097:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x200 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x302 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x142 and fcsr == 0x40 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7a00; op2val:0x3b02;
op3val:0x7942; valaddr_reg:x3; val_offset:3291*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:64 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 64, 0, x3, 3291*FLEN/8, x4, x1, x2)

inst_1098:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x200 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x302 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x142 and fcsr == 0x60 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7a00; op2val:0x3b02;
op3val:0x7942; valaddr_reg:x3; val_offset:3294*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 96, 0, x3, 3294*FLEN/8, x4, x1, x2)

inst_1099:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x200 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x302 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x142 and fcsr == 0x80 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7a00; op2val:0x3b02;
op3val:0x7942; valaddr_reg:x3; val_offset:3297*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:128 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 128, 0, x3, 3297*FLEN/8, x4, x1, x2)

inst_1100:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1b9 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x0e9 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x307 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x79b9; op2val:0x3ce9;
op3val:0x7b07; valaddr_reg:x3; val_offset:3300*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 3300*FLEN/8, x4, x1, x2)

inst_1101:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1b9 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x0e9 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x307 and fcsr == 0x20 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x79b9; op2val:0x3ce9;
op3val:0x7b07; valaddr_reg:x3; val_offset:3303*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:32 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 32, 0, x3, 3303*FLEN/8, x4, x1, x2)

inst_1102:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1b9 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x0e9 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x307 and fcsr == 0x40 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x79b9; op2val:0x3ce9;
op3val:0x7b07; valaddr_reg:x3; val_offset:3306*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:64 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 64, 0, x3, 3306*FLEN/8, x4, x1, x2)

inst_1103:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1b9 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x0e9 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x307 and fcsr == 0x60 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x79b9; op2val:0x3ce9;
op3val:0x7b07; valaddr_reg:x3; val_offset:3309*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 96, 0, x3, 3309*FLEN/8, x4, x1, x2)

inst_1104:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1b9 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x0e9 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x307 and fcsr == 0x80 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x79b9; op2val:0x3ce9;
op3val:0x7b07; valaddr_reg:x3; val_offset:3312*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:128 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 128, 0, x3, 3312*FLEN/8, x4, x1, x2)

inst_1105:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x23a and fs2 == 0 and fe2 == 0x0e and fm2 == 0x2b2 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x137 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x763a; op2val:0x3ab2;
op3val:0x7537; valaddr_reg:x3; val_offset:3315*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 3315*FLEN/8, x4, x1, x2)

inst_1106:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x23a and fs2 == 0 and fe2 == 0x0e and fm2 == 0x2b2 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x137 and fcsr == 0x20 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x763a; op2val:0x3ab2;
op3val:0x7537; valaddr_reg:x3; val_offset:3318*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:32 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 32, 0, x3, 3318*FLEN/8, x4, x1, x2)

inst_1107:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x23a and fs2 == 0 and fe2 == 0x0e and fm2 == 0x2b2 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x137 and fcsr == 0x40 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x763a; op2val:0x3ab2;
op3val:0x7537; valaddr_reg:x3; val_offset:3321*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:64 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 64, 0, x3, 3321*FLEN/8, x4, x1, x2)

inst_1108:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x23a and fs2 == 0 and fe2 == 0x0e and fm2 == 0x2b2 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x137 and fcsr == 0x60 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x763a; op2val:0x3ab2;
op3val:0x7537; valaddr_reg:x3; val_offset:3324*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 96, 0, x3, 3324*FLEN/8, x4, x1, x2)

inst_1109:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x23a and fs2 == 0 and fe2 == 0x0e and fm2 == 0x2b2 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x137 and fcsr == 0x80 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x763a; op2val:0x3ab2;
op3val:0x7537; valaddr_reg:x3; val_offset:3327*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:128 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 128, 0, x3, 3327*FLEN/8, x4, x1, x2)

inst_1110:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3df and fs2 == 0 and fe2 == 0x0c and fm2 == 0x0db and fs3 == 0 and fe3 == 0x1c and fm3 == 0x0c7 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7bdf; op2val:0x30db;
op3val:0x70c7; valaddr_reg:x3; val_offset:3330*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 3330*FLEN/8, x4, x1, x2)

inst_1111:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3df and fs2 == 0 and fe2 == 0x0c and fm2 == 0x0db and fs3 == 0 and fe3 == 0x1c and fm3 == 0x0c7 and fcsr == 0x20 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7bdf; op2val:0x30db;
op3val:0x70c7; valaddr_reg:x3; val_offset:3333*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:32 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 32, 0, x3, 3333*FLEN/8, x4, x1, x2)

inst_1112:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3df and fs2 == 0 and fe2 == 0x0c and fm2 == 0x0db and fs3 == 0 and fe3 == 0x1c and fm3 == 0x0c7 and fcsr == 0x40 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7bdf; op2val:0x30db;
op3val:0x70c7; valaddr_reg:x3; val_offset:3336*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:64 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 64, 0, x3, 3336*FLEN/8, x4, x1, x2)

inst_1113:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3df and fs2 == 0 and fe2 == 0x0c and fm2 == 0x0db and fs3 == 0 and fe3 == 0x1c and fm3 == 0x0c7 and fcsr == 0x60 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7bdf; op2val:0x30db;
op3val:0x70c7; valaddr_reg:x3; val_offset:3339*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 96, 0, x3, 3339*FLEN/8, x4, x1, x2)

inst_1114:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3df and fs2 == 0 and fe2 == 0x0c and fm2 == 0x0db and fs3 == 0 and fe3 == 0x1c and fm3 == 0x0c7 and fcsr == 0x80 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7bdf; op2val:0x30db;
op3val:0x70c7; valaddr_reg:x3; val_offset:3342*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:128 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 128, 0, x3, 3342*FLEN/8, x4, x1, x2)

inst_1115:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1ca and fs2 == 0 and fe2 == 0x0e and fm2 == 0x31b and fs3 == 0 and fe3 == 0x1e and fm3 == 0x124 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x79ca; op2val:0x3b1b;
op3val:0x7924; valaddr_reg:x3; val_offset:3345*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 3345*FLEN/8, x4, x1, x2)

inst_1116:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1ca and fs2 == 0 and fe2 == 0x0e and fm2 == 0x31b and fs3 == 0 and fe3 == 0x1e and fm3 == 0x124 and fcsr == 0x20 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x79ca; op2val:0x3b1b;
op3val:0x7924; valaddr_reg:x3; val_offset:3348*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:32 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 32, 0, x3, 3348*FLEN/8, x4, x1, x2)

inst_1117:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1ca and fs2 == 0 and fe2 == 0x0e and fm2 == 0x31b and fs3 == 0 and fe3 == 0x1e and fm3 == 0x124 and fcsr == 0x40 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x79ca; op2val:0x3b1b;
op3val:0x7924; valaddr_reg:x3; val_offset:3351*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:64 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 64, 0, x3, 3351*FLEN/8, x4, x1, x2)

inst_1118:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1ca and fs2 == 0 and fe2 == 0x0e and fm2 == 0x31b and fs3 == 0 and fe3 == 0x1e and fm3 == 0x124 and fcsr == 0x60 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x79ca; op2val:0x3b1b;
op3val:0x7924; valaddr_reg:x3; val_offset:3354*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 96, 0, x3, 3354*FLEN/8, x4, x1, x2)

inst_1119:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1ca and fs2 == 0 and fe2 == 0x0e and fm2 == 0x31b and fs3 == 0 and fe3 == 0x1e and fm3 == 0x124 and fcsr == 0x80 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x79ca; op2val:0x3b1b;
op3val:0x7924; valaddr_reg:x3; val_offset:3357*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:128 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 128, 0, x3, 3357*FLEN/8, x4, x1, x2)

inst_1120:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x12d and fs2 == 0 and fe2 == 0x0d and fm2 == 0x374 and fs3 == 0 and fe3 == 0x1c and fm3 == 0x0d3 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x752d; op2val:0x3774;
op3val:0x70d3; valaddr_reg:x3; val_offset:3360*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 3360*FLEN/8, x4, x1, x2)

inst_1121:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x12d and fs2 == 0 and fe2 == 0x0d and fm2 == 0x374 and fs3 == 0 and fe3 == 0x1c and fm3 == 0x0d3 and fcsr == 0x40 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x752d; op2val:0x3774;
op3val:0x70d3; valaddr_reg:x3; val_offset:3363*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:64 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 64, 0, x3, 3363*FLEN/8, x4, x1, x2)

inst_1122:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x134 and fs2 == 0 and fe2 == 0x0b and fm2 == 0x31f and fs3 == 0 and fe3 == 0x1b and fm3 == 0x0a2 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7934; op2val:0x2f1f;
op3val:0x6ca2; valaddr_reg:x3; val_offset:3366*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 3366*FLEN/8, x4, x1, x2)

inst_1123:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x134 and fs2 == 0 and fe2 == 0x0b and fm2 == 0x31f and fs3 == 0 and fe3 == 0x1b and fm3 == 0x0a2 and fcsr == 0x20 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7934; op2val:0x2f1f;
op3val:0x6ca2; valaddr_reg:x3; val_offset:3369*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:32 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 32, 0, x3, 3369*FLEN/8, x4, x1, x2)

inst_1124:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x134 and fs2 == 0 and fe2 == 0x0b and fm2 == 0x31f and fs3 == 0 and fe3 == 0x1b and fm3 == 0x0a2 and fcsr == 0x40 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7934; op2val:0x2f1f;
op3val:0x6ca2; valaddr_reg:x3; val_offset:3372*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:64 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 64, 0, x3, 3372*FLEN/8, x4, x1, x2)

inst_1125:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x134 and fs2 == 0 and fe2 == 0x0b and fm2 == 0x31f and fs3 == 0 and fe3 == 0x1b and fm3 == 0x0a2 and fcsr == 0x60 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7934; op2val:0x2f1f;
op3val:0x6ca2; valaddr_reg:x3; val_offset:3375*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 96, 0, x3, 3375*FLEN/8, x4, x1, x2)

inst_1126:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x134 and fs2 == 0 and fe2 == 0x0b and fm2 == 0x31f and fs3 == 0 and fe3 == 0x1b and fm3 == 0x0a2 and fcsr == 0x80 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7934; op2val:0x2f1f;
op3val:0x6ca2; valaddr_reg:x3; val_offset:3378*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:128 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 128, 0, x3, 3378*FLEN/8, x4, x1, x2)

inst_1127:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x048 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x175 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x1d9 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7848; op2val:0x3975;
op3val:0x75d9; valaddr_reg:x3; val_offset:3381*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 3381*FLEN/8, x4, x1, x2)
#endif


RVTEST_CODE_END
RVMODEL_HALT

RVTEST_DATA_BEGIN
.align 4
rvtest_data:
.word 0xbabecafe
.word 0xabecafeb
.word 0xbecafeba
.word 0xecafebab
test_dataset_0:
NAN_BOXED(29997,16,FLEN)
NAN_BOXED(14196,16,FLEN)
NAN_BOXED(29997,16,FLEN)
NAN_BOXED(29997,16,FLEN)
NAN_BOXED(14196,16,FLEN)
NAN_BOXED(28883,16,FLEN)
NAN_BOXED(29997,16,FLEN)
NAN_BOXED(14196,16,FLEN)
NAN_BOXED(14196,16,FLEN)
NAN_BOXED(29997,16,FLEN)
NAN_BOXED(14196,16,FLEN)
NAN_BOXED(28883,16,FLEN)
NAN_BOXED(29997,16,FLEN)
NAN_BOXED(14196,16,FLEN)
NAN_BOXED(28883,16,FLEN)
NAN_BOXED(31028,16,FLEN)
NAN_BOXED(31028,16,FLEN)
NAN_BOXED(31028,16,FLEN)
NAN_BOXED(31028,16,FLEN)
NAN_BOXED(12063,16,FLEN)
NAN_BOXED(12063,16,FLEN)
NAN_BOXED(31028,16,FLEN)
NAN_BOXED(31028,16,FLEN)
NAN_BOXED(27810,16,FLEN)
NAN_BOXED(31028,16,FLEN)
NAN_BOXED(31028,16,FLEN)
NAN_BOXED(31028,16,FLEN)
NAN_BOXED(31028,16,FLEN)
NAN_BOXED(31028,16,FLEN)
NAN_BOXED(27810,16,FLEN)
NAN_BOXED(30792,16,FLEN)
NAN_BOXED(14709,16,FLEN)
NAN_BOXED(30792,16,FLEN)
NAN_BOXED(30792,16,FLEN)
NAN_BOXED(14709,16,FLEN)
NAN_BOXED(30169,16,FLEN)
NAN_BOXED(30792,16,FLEN)
NAN_BOXED(14709,16,FLEN)
NAN_BOXED(30169,16,FLEN)
NAN_BOXED(30792,16,FLEN)
NAN_BOXED(14709,16,FLEN)
NAN_BOXED(30169,16,FLEN)
NAN_BOXED(30792,16,FLEN)
NAN_BOXED(14709,16,FLEN)
NAN_BOXED(30169,16,FLEN)
NAN_BOXED(27500,16,FLEN)
NAN_BOXED(18527,16,FLEN)
NAN_BOXED(30734,16,FLEN)
NAN_BOXED(27500,16,FLEN)
NAN_BOXED(18527,16,FLEN)
NAN_BOXED(30734,16,FLEN)
NAN_BOXED(27500,16,FLEN)
NAN_BOXED(18527,16,FLEN)
NAN_BOXED(30734,16,FLEN)
NAN_BOXED(27500,16,FLEN)
NAN_BOXED(18527,16,FLEN)
NAN_BOXED(30734,16,FLEN)
NAN_BOXED(27500,16,FLEN)
NAN_BOXED(18527,16,FLEN)
NAN_BOXED(30734,16,FLEN)
NAN_BOXED(26828,16,FLEN)
NAN_BOXED(18887,16,FLEN)
NAN_BOXED(30447,16,FLEN)
NAN_BOXED(26828,16,FLEN)
NAN_BOXED(18887,16,FLEN)
NAN_BOXED(30447,16,FLEN)
NAN_BOXED(26828,16,FLEN)
NAN_BOXED(18887,16,FLEN)
NAN_BOXED(30447,16,FLEN)
NAN_BOXED(26828,16,FLEN)
NAN_BOXED(18887,16,FLEN)
NAN_BOXED(30447,16,FLEN)
NAN_BOXED(26828,16,FLEN)
NAN_BOXED(18887,16,FLEN)
NAN_BOXED(30447,16,FLEN)
NAN_BOXED(27768,16,FLEN)
NAN_BOXED(15665,16,FLEN)
NAN_BOXED(28109,16,FLEN)
NAN_BOXED(27768,16,FLEN)
NAN_BOXED(15665,16,FLEN)
NAN_BOXED(28109,16,FLEN)
NAN_BOXED(27768,16,FLEN)
NAN_BOXED(15665,16,FLEN)
NAN_BOXED(28109,16,FLEN)
NAN_BOXED(27768,16,FLEN)
NAN_BOXED(15665,16,FLEN)
NAN_BOXED(28109,16,FLEN)
NAN_BOXED(27768,16,FLEN)
NAN_BOXED(15665,16,FLEN)
NAN_BOXED(28109,16,FLEN)
NAN_BOXED(30410,16,FLEN)
NAN_BOXED(16330,16,FLEN)
NAN_BOXED(31388,16,FLEN)
NAN_BOXED(30410,16,FLEN)
NAN_BOXED(16330,16,FLEN)
NAN_BOXED(31388,16,FLEN)
NAN_BOXED(30410,16,FLEN)
NAN_BOXED(16330,16,FLEN)
NAN_BOXED(31388,16,FLEN)
NAN_BOXED(30410,16,FLEN)
NAN_BOXED(16330,16,FLEN)
NAN_BOXED(31388,16,FLEN)
NAN_BOXED(30410,16,FLEN)
NAN_BOXED(16330,16,FLEN)
NAN_BOXED(31388,16,FLEN)
NAN_BOXED(28651,16,FLEN)
NAN_BOXED(16182,16,FLEN)
NAN_BOXED(29475,16,FLEN)
NAN_BOXED(28651,16,FLEN)
NAN_BOXED(16182,16,FLEN)
NAN_BOXED(29475,16,FLEN)
NAN_BOXED(28651,16,FLEN)
NAN_BOXED(16182,16,FLEN)
NAN_BOXED(29475,16,FLEN)
NAN_BOXED(28651,16,FLEN)
NAN_BOXED(16182,16,FLEN)
NAN_BOXED(29475,16,FLEN)
NAN_BOXED(28651,16,FLEN)
NAN_BOXED(16182,16,FLEN)
NAN_BOXED(29475,16,FLEN)
NAN_BOXED(30980,16,FLEN)
NAN_BOXED(15882,16,FLEN)
NAN_BOXED(31635,16,FLEN)
NAN_BOXED(30980,16,FLEN)
NAN_BOXED(15882,16,FLEN)
NAN_BOXED(31635,16,FLEN)
NAN_BOXED(30980,16,FLEN)
NAN_BOXED(15882,16,FLEN)
NAN_BOXED(31635,16,FLEN)
NAN_BOXED(30980,16,FLEN)
NAN_BOXED(15882,16,FLEN)
NAN_BOXED(31635,16,FLEN)
NAN_BOXED(30980,16,FLEN)
NAN_BOXED(15882,16,FLEN)
NAN_BOXED(31635,16,FLEN)
NAN_BOXED(30877,16,FLEN)
NAN_BOXED(14719,16,FLEN)
NAN_BOXED(30296,16,FLEN)
NAN_BOXED(30877,16,FLEN)
NAN_BOXED(14719,16,FLEN)
NAN_BOXED(30296,16,FLEN)
NAN_BOXED(30877,16,FLEN)
NAN_BOXED(14719,16,FLEN)
NAN_BOXED(30296,16,FLEN)
NAN_BOXED(30877,16,FLEN)
NAN_BOXED(14719,16,FLEN)
NAN_BOXED(30296,16,FLEN)
NAN_BOXED(30877,16,FLEN)
NAN_BOXED(14719,16,FLEN)
NAN_BOXED(30296,16,FLEN)
NAN_BOXED(31694,16,FLEN)
NAN_BOXED(10780,16,FLEN)
NAN_BOXED(27126,16,FLEN)
NAN_BOXED(31694,16,FLEN)
NAN_BOXED(10780,16,FLEN)
NAN_BOXED(27126,16,FLEN)
NAN_BOXED(31694,16,FLEN)
NAN_BOXED(10780,16,FLEN)
NAN_BOXED(27126,16,FLEN)
NAN_BOXED(31694,16,FLEN)
NAN_BOXED(10780,16,FLEN)
NAN_BOXED(27126,16,FLEN)
NAN_BOXED(31694,16,FLEN)
NAN_BOXED(10780,16,FLEN)
NAN_BOXED(27126,16,FLEN)
NAN_BOXED(31453,16,FLEN)
NAN_BOXED(13669,16,FLEN)
NAN_BOXED(29857,16,FLEN)
NAN_BOXED(31453,16,FLEN)
NAN_BOXED(13669,16,FLEN)
NAN_BOXED(29857,16,FLEN)
NAN_BOXED(31453,16,FLEN)
NAN_BOXED(13669,16,FLEN)
NAN_BOXED(29857,16,FLEN)
NAN_BOXED(31453,16,FLEN)
NAN_BOXED(13669,16,FLEN)
NAN_BOXED(29857,16,FLEN)
NAN_BOXED(31453,16,FLEN)
NAN_BOXED(13669,16,FLEN)
NAN_BOXED(29857,16,FLEN)
NAN_BOXED(28829,16,FLEN)
NAN_BOXED(14984,16,FLEN)
NAN_BOXED(28553,16,FLEN)
NAN_BOXED(28829,16,FLEN)
NAN_BOXED(14984,16,FLEN)
NAN_BOXED(28553,16,FLEN)
NAN_BOXED(28829,16,FLEN)
NAN_BOXED(14984,16,FLEN)
NAN_BOXED(28553,16,FLEN)
NAN_BOXED(28829,16,FLEN)
NAN_BOXED(14984,16,FLEN)
NAN_BOXED(28553,16,FLEN)
NAN_BOXED(28829,16,FLEN)
NAN_BOXED(14984,16,FLEN)
NAN_BOXED(28553,16,FLEN)
NAN_BOXED(29934,16,FLEN)
NAN_BOXED(16714,16,FLEN)
NAN_BOXED(31366,16,FLEN)
NAN_BOXED(29934,16,FLEN)
NAN_BOXED(16714,16,FLEN)
NAN_BOXED(31366,16,FLEN)
NAN_BOXED(29934,16,FLEN)
NAN_BOXED(16714,16,FLEN)
NAN_BOXED(31366,16,FLEN)
NAN_BOXED(29934,16,FLEN)
NAN_BOXED(16714,16,FLEN)
NAN_BOXED(31366,16,FLEN)
NAN_BOXED(29934,16,FLEN)
NAN_BOXED(16714,16,FLEN)
NAN_BOXED(31366,16,FLEN)
NAN_BOXED(29127,16,FLEN)
NAN_BOXED(17007,16,FLEN)
NAN_BOXED(30886,16,FLEN)
NAN_BOXED(29127,16,FLEN)
NAN_BOXED(17007,16,FLEN)
NAN_BOXED(30886,16,FLEN)
NAN_BOXED(29127,16,FLEN)
NAN_BOXED(17007,16,FLEN)
NAN_BOXED(30886,16,FLEN)
NAN_BOXED(29127,16,FLEN)
NAN_BOXED(17007,16,FLEN)
NAN_BOXED(30886,16,FLEN)
NAN_BOXED(29127,16,FLEN)
NAN_BOXED(17007,16,FLEN)
NAN_BOXED(30886,16,FLEN)
NAN_BOXED(31003,16,FLEN)
NAN_BOXED(14505,16,FLEN)
NAN_BOXED(30196,16,FLEN)
NAN_BOXED(31003,16,FLEN)
NAN_BOXED(14505,16,FLEN)
NAN_BOXED(30196,16,FLEN)
NAN_BOXED(31003,16,FLEN)
NAN_BOXED(14505,16,FLEN)
NAN_BOXED(30196,16,FLEN)
NAN_BOXED(31003,16,FLEN)
NAN_BOXED(14505,16,FLEN)
NAN_BOXED(30196,16,FLEN)
NAN_BOXED(31003,16,FLEN)
NAN_BOXED(14505,16,FLEN)
NAN_BOXED(30196,16,FLEN)
NAN_BOXED(30817,16,FLEN)
NAN_BOXED(12118,16,FLEN)
NAN_BOXED(27652,16,FLEN)
NAN_BOXED(30817,16,FLEN)
NAN_BOXED(12118,16,FLEN)
NAN_BOXED(27652,16,FLEN)
NAN_BOXED(30817,16,FLEN)
NAN_BOXED(12118,16,FLEN)
NAN_BOXED(27652,16,FLEN)
NAN_BOXED(30817,16,FLEN)
NAN_BOXED(12118,16,FLEN)
NAN_BOXED(27652,16,FLEN)
NAN_BOXED(30817,16,FLEN)
NAN_BOXED(12118,16,FLEN)
NAN_BOXED(27652,16,FLEN)
NAN_BOXED(27552,16,FLEN)
NAN_BOXED(17128,16,FLEN)
NAN_BOXED(29334,16,FLEN)
NAN_BOXED(27552,16,FLEN)
NAN_BOXED(17128,16,FLEN)
NAN_BOXED(29334,16,FLEN)
NAN_BOXED(27552,16,FLEN)
NAN_BOXED(17128,16,FLEN)
NAN_BOXED(29334,16,FLEN)
NAN_BOXED(27552,16,FLEN)
NAN_BOXED(17128,16,FLEN)
NAN_BOXED(29334,16,FLEN)
NAN_BOXED(27552,16,FLEN)
NAN_BOXED(17128,16,FLEN)
NAN_BOXED(29334,16,FLEN)
NAN_BOXED(31088,16,FLEN)
NAN_BOXED(14599,16,FLEN)
NAN_BOXED(30422,16,FLEN)
NAN_BOXED(31088,16,FLEN)
NAN_BOXED(14599,16,FLEN)
NAN_BOXED(30422,16,FLEN)
NAN_BOXED(31088,16,FLEN)
NAN_BOXED(14599,16,FLEN)
NAN_BOXED(30422,16,FLEN)
NAN_BOXED(31088,16,FLEN)
NAN_BOXED(14599,16,FLEN)
NAN_BOXED(30422,16,FLEN)
NAN_BOXED(31088,16,FLEN)
NAN_BOXED(14599,16,FLEN)
NAN_BOXED(30422,16,FLEN)
NAN_BOXED(29958,16,FLEN)
NAN_BOXED(16244,16,FLEN)
NAN_BOXED(30894,16,FLEN)
NAN_BOXED(29958,16,FLEN)
NAN_BOXED(16244,16,FLEN)
NAN_BOXED(30894,16,FLEN)
NAN_BOXED(29958,16,FLEN)
NAN_BOXED(16244,16,FLEN)
NAN_BOXED(30894,16,FLEN)
NAN_BOXED(29958,16,FLEN)
NAN_BOXED(16244,16,FLEN)
NAN_BOXED(30894,16,FLEN)
NAN_BOXED(29958,16,FLEN)
NAN_BOXED(16244,16,FLEN)
NAN_BOXED(30894,16,FLEN)
NAN_BOXED(30527,16,FLEN)
NAN_BOXED(14666,16,FLEN)
NAN_BOXED(29899,16,FLEN)
NAN_BOXED(30527,16,FLEN)
NAN_BOXED(14666,16,FLEN)
NAN_BOXED(29899,16,FLEN)
NAN_BOXED(30527,16,FLEN)
NAN_BOXED(14666,16,FLEN)
NAN_BOXED(29899,16,FLEN)
NAN_BOXED(30527,16,FLEN)
NAN_BOXED(14666,16,FLEN)
NAN_BOXED(29899,16,FLEN)
NAN_BOXED(30527,16,FLEN)
NAN_BOXED(14666,16,FLEN)
NAN_BOXED(29899,16,FLEN)
NAN_BOXED(31322,16,FLEN)
NAN_BOXED(15114,16,FLEN)
NAN_BOXED(31126,16,FLEN)
NAN_BOXED(31322,16,FLEN)
NAN_BOXED(15114,16,FLEN)
NAN_BOXED(31126,16,FLEN)
NAN_BOXED(31322,16,FLEN)
NAN_BOXED(15114,16,FLEN)
NAN_BOXED(31126,16,FLEN)
NAN_BOXED(31322,16,FLEN)
NAN_BOXED(15114,16,FLEN)
NAN_BOXED(31126,16,FLEN)
NAN_BOXED(31322,16,FLEN)
NAN_BOXED(15114,16,FLEN)
NAN_BOXED(31126,16,FLEN)
NAN_BOXED(29646,16,FLEN)
NAN_BOXED(16564,16,FLEN)
NAN_BOXED(30871,16,FLEN)
NAN_BOXED(29646,16,FLEN)
NAN_BOXED(16564,16,FLEN)
NAN_BOXED(30871,16,FLEN)
NAN_BOXED(29646,16,FLEN)
NAN_BOXED(16564,16,FLEN)
NAN_BOXED(30871,16,FLEN)
NAN_BOXED(29646,16,FLEN)
NAN_BOXED(16564,16,FLEN)
NAN_BOXED(30871,16,FLEN)
NAN_BOXED(29646,16,FLEN)
NAN_BOXED(16564,16,FLEN)
NAN_BOXED(30871,16,FLEN)
NAN_BOXED(30771,16,FLEN)
NAN_BOXED(16042,16,FLEN)
NAN_BOXED(31487,16,FLEN)
NAN_BOXED(30771,16,FLEN)
NAN_BOXED(16042,16,FLEN)
NAN_BOXED(31487,16,FLEN)
NAN_BOXED(30771,16,FLEN)
NAN_BOXED(16042,16,FLEN)
NAN_BOXED(31487,16,FLEN)
NAN_BOXED(30771,16,FLEN)
NAN_BOXED(16042,16,FLEN)
NAN_BOXED(31487,16,FLEN)
NAN_BOXED(30771,16,FLEN)
NAN_BOXED(16042,16,FLEN)
NAN_BOXED(31487,16,FLEN)
NAN_BOXED(31189,16,FLEN)
NAN_BOXED(13904,16,FLEN)
NAN_BOXED(29850,16,FLEN)
NAN_BOXED(31189,16,FLEN)
NAN_BOXED(13904,16,FLEN)
NAN_BOXED(29850,16,FLEN)
NAN_BOXED(31189,16,FLEN)
NAN_BOXED(13904,16,FLEN)
NAN_BOXED(29850,16,FLEN)
NAN_BOXED(31189,16,FLEN)
NAN_BOXED(13904,16,FLEN)
NAN_BOXED(29850,16,FLEN)
NAN_BOXED(31189,16,FLEN)
NAN_BOXED(13904,16,FLEN)
NAN_BOXED(29850,16,FLEN)
NAN_BOXED(31702,16,FLEN)
NAN_BOXED(12213,16,FLEN)
NAN_BOXED(28557,16,FLEN)
NAN_BOXED(31702,16,FLEN)
NAN_BOXED(12213,16,FLEN)
NAN_BOXED(28557,16,FLEN)
NAN_BOXED(31702,16,FLEN)
NAN_BOXED(12213,16,FLEN)
NAN_BOXED(28557,16,FLEN)
NAN_BOXED(31702,16,FLEN)
NAN_BOXED(12213,16,FLEN)
NAN_BOXED(28557,16,FLEN)
NAN_BOXED(31702,16,FLEN)
NAN_BOXED(12213,16,FLEN)
NAN_BOXED(28557,16,FLEN)
NAN_BOXED(30383,16,FLEN)
NAN_BOXED(16190,16,FLEN)
NAN_BOXED(31245,16,FLEN)
NAN_BOXED(30383,16,FLEN)
NAN_BOXED(16190,16,FLEN)
NAN_BOXED(31245,16,FLEN)
NAN_BOXED(30383,16,FLEN)
NAN_BOXED(16190,16,FLEN)
NAN_BOXED(31245,16,FLEN)
NAN_BOXED(30383,16,FLEN)
NAN_BOXED(16190,16,FLEN)
NAN_BOXED(31245,16,FLEN)
NAN_BOXED(30383,16,FLEN)
NAN_BOXED(16190,16,FLEN)
NAN_BOXED(31245,16,FLEN)
NAN_BOXED(28892,16,FLEN)
NAN_BOXED(17007,16,FLEN)
NAN_BOXED(30673,16,FLEN)
NAN_BOXED(28892,16,FLEN)
NAN_BOXED(17007,16,FLEN)
NAN_BOXED(30673,16,FLEN)
NAN_BOXED(28892,16,FLEN)
NAN_BOXED(17007,16,FLEN)
NAN_BOXED(30673,16,FLEN)
NAN_BOXED(28892,16,FLEN)
NAN_BOXED(17007,16,FLEN)
NAN_BOXED(30673,16,FLEN)
NAN_BOXED(28892,16,FLEN)
NAN_BOXED(17007,16,FLEN)
NAN_BOXED(30673,16,FLEN)
NAN_BOXED(26884,16,FLEN)
NAN_BOXED(19522,16,FLEN)
NAN_BOXED(31063,16,FLEN)
NAN_BOXED(26884,16,FLEN)
NAN_BOXED(19522,16,FLEN)
NAN_BOXED(31063,16,FLEN)
NAN_BOXED(26884,16,FLEN)
NAN_BOXED(19522,16,FLEN)
NAN_BOXED(31063,16,FLEN)
NAN_BOXED(26884,16,FLEN)
NAN_BOXED(19522,16,FLEN)
NAN_BOXED(31063,16,FLEN)
NAN_BOXED(26884,16,FLEN)
NAN_BOXED(19522,16,FLEN)
NAN_BOXED(31063,16,FLEN)
NAN_BOXED(31261,16,FLEN)
NAN_BOXED(14846,16,FLEN)
NAN_BOXED(30868,16,FLEN)
NAN_BOXED(31261,16,FLEN)
NAN_BOXED(14846,16,FLEN)
NAN_BOXED(30868,16,FLEN)
NAN_BOXED(31261,16,FLEN)
NAN_BOXED(14846,16,FLEN)
NAN_BOXED(30868,16,FLEN)
NAN_BOXED(31261,16,FLEN)
NAN_BOXED(14846,16,FLEN)
NAN_BOXED(30868,16,FLEN)
NAN_BOXED(31261,16,FLEN)
NAN_BOXED(14846,16,FLEN)
NAN_BOXED(30868,16,FLEN)
NAN_BOXED(31488,16,FLEN)
NAN_BOXED(13755,16,FLEN)
NAN_BOXED(29956,16,FLEN)
NAN_BOXED(31488,16,FLEN)
NAN_BOXED(13755,16,FLEN)
NAN_BOXED(29956,16,FLEN)
NAN_BOXED(31488,16,FLEN)
NAN_BOXED(13755,16,FLEN)
NAN_BOXED(29956,16,FLEN)
NAN_BOXED(31488,16,FLEN)
NAN_BOXED(13755,16,FLEN)
NAN_BOXED(29956,16,FLEN)
NAN_BOXED(31488,16,FLEN)
NAN_BOXED(13755,16,FLEN)
NAN_BOXED(29956,16,FLEN)
NAN_BOXED(31119,16,FLEN)
NAN_BOXED(15062,16,FLEN)
NAN_BOXED(30912,16,FLEN)
NAN_BOXED(31119,16,FLEN)
NAN_BOXED(15062,16,FLEN)
NAN_BOXED(30912,16,FLEN)
NAN_BOXED(31119,16,FLEN)
NAN_BOXED(15062,16,FLEN)
NAN_BOXED(30912,16,FLEN)
NAN_BOXED(31119,16,FLEN)
NAN_BOXED(15062,16,FLEN)
NAN_BOXED(30912,16,FLEN)
NAN_BOXED(31119,16,FLEN)
NAN_BOXED(15062,16,FLEN)
NAN_BOXED(30912,16,FLEN)
NAN_BOXED(30883,16,FLEN)
NAN_BOXED(14923,16,FLEN)
NAN_BOXED(30539,16,FLEN)
NAN_BOXED(30883,16,FLEN)
NAN_BOXED(14923,16,FLEN)
NAN_BOXED(30539,16,FLEN)
NAN_BOXED(30883,16,FLEN)
NAN_BOXED(14923,16,FLEN)
NAN_BOXED(30539,16,FLEN)
NAN_BOXED(30883,16,FLEN)
NAN_BOXED(14923,16,FLEN)
NAN_BOXED(30539,16,FLEN)
NAN_BOXED(30883,16,FLEN)
NAN_BOXED(14923,16,FLEN)
NAN_BOXED(30539,16,FLEN)
NAN_BOXED(31415,16,FLEN)
NAN_BOXED(15487,16,FLEN)
NAN_BOXED(31629,16,FLEN)
NAN_BOXED(31415,16,FLEN)
NAN_BOXED(15487,16,FLEN)
NAN_BOXED(31629,16,FLEN)
NAN_BOXED(31415,16,FLEN)
NAN_BOXED(15487,16,FLEN)
NAN_BOXED(31629,16,FLEN)
NAN_BOXED(31415,16,FLEN)
NAN_BOXED(15487,16,FLEN)
NAN_BOXED(31629,16,FLEN)
NAN_BOXED(31415,16,FLEN)
NAN_BOXED(15487,16,FLEN)
NAN_BOXED(31629,16,FLEN)
NAN_BOXED(30612,16,FLEN)
NAN_BOXED(15770,16,FLEN)
NAN_BOXED(31055,16,FLEN)
NAN_BOXED(30612,16,FLEN)
NAN_BOXED(15770,16,FLEN)
NAN_BOXED(31055,16,FLEN)
NAN_BOXED(30612,16,FLEN)
NAN_BOXED(15770,16,FLEN)
NAN_BOXED(31055,16,FLEN)
NAN_BOXED(30612,16,FLEN)
NAN_BOXED(15770,16,FLEN)
NAN_BOXED(31055,16,FLEN)
NAN_BOXED(30612,16,FLEN)
NAN_BOXED(15770,16,FLEN)
NAN_BOXED(31055,16,FLEN)
NAN_BOXED(27587,16,FLEN)
NAN_BOXED(18887,16,FLEN)
NAN_BOXED(31131,16,FLEN)
NAN_BOXED(27587,16,FLEN)
NAN_BOXED(18887,16,FLEN)
NAN_BOXED(31131,16,FLEN)
NAN_BOXED(27587,16,FLEN)
NAN_BOXED(18887,16,FLEN)
NAN_BOXED(31131,16,FLEN)
NAN_BOXED(27587,16,FLEN)
NAN_BOXED(18887,16,FLEN)
NAN_BOXED(31131,16,FLEN)
NAN_BOXED(27587,16,FLEN)
NAN_BOXED(18887,16,FLEN)
NAN_BOXED(31131,16,FLEN)
NAN_BOXED(31020,16,FLEN)
NAN_BOXED(15907,16,FLEN)
NAN_BOXED(31728,16,FLEN)
NAN_BOXED(31020,16,FLEN)
NAN_BOXED(15907,16,FLEN)
NAN_BOXED(31728,16,FLEN)
NAN_BOXED(31020,16,FLEN)
NAN_BOXED(15907,16,FLEN)
NAN_BOXED(31728,16,FLEN)
NAN_BOXED(31020,16,FLEN)
NAN_BOXED(15907,16,FLEN)
NAN_BOXED(31728,16,FLEN)
NAN_BOXED(31020,16,FLEN)
NAN_BOXED(15907,16,FLEN)
NAN_BOXED(31728,16,FLEN)
NAN_BOXED(31378,16,FLEN)
NAN_BOXED(13706,16,FLEN)
NAN_BOXED(29837,16,FLEN)
NAN_BOXED(31378,16,FLEN)
NAN_BOXED(13706,16,FLEN)
NAN_BOXED(29837,16,FLEN)
NAN_BOXED(31378,16,FLEN)
NAN_BOXED(13706,16,FLEN)
NAN_BOXED(29837,16,FLEN)
NAN_BOXED(31378,16,FLEN)
NAN_BOXED(13706,16,FLEN)
NAN_BOXED(29837,16,FLEN)
NAN_BOXED(31378,16,FLEN)
NAN_BOXED(13706,16,FLEN)
NAN_BOXED(29837,16,FLEN)
NAN_BOXED(30251,16,FLEN)
NAN_BOXED(16110,16,FLEN)
NAN_BOXED(31064,16,FLEN)
NAN_BOXED(30251,16,FLEN)
NAN_BOXED(16110,16,FLEN)
NAN_BOXED(31064,16,FLEN)
NAN_BOXED(30251,16,FLEN)
NAN_BOXED(16110,16,FLEN)
NAN_BOXED(31064,16,FLEN)
NAN_BOXED(30251,16,FLEN)
NAN_BOXED(16110,16,FLEN)
NAN_BOXED(31064,16,FLEN)
NAN_BOXED(30251,16,FLEN)
NAN_BOXED(16110,16,FLEN)
NAN_BOXED(31064,16,FLEN)
NAN_BOXED(26054,16,FLEN)
NAN_BOXED(19740,16,FLEN)
NAN_BOXED(30562,16,FLEN)
NAN_BOXED(26054,16,FLEN)
NAN_BOXED(19740,16,FLEN)
NAN_BOXED(30562,16,FLEN)
NAN_BOXED(26054,16,FLEN)
NAN_BOXED(19740,16,FLEN)
NAN_BOXED(30562,16,FLEN)
NAN_BOXED(26054,16,FLEN)
NAN_BOXED(19740,16,FLEN)
NAN_BOXED(30562,16,FLEN)
NAN_BOXED(26054,16,FLEN)
NAN_BOXED(19740,16,FLEN)
NAN_BOXED(30562,16,FLEN)
NAN_BOXED(29024,16,FLEN)
NAN_BOXED(14739,16,FLEN)
NAN_BOXED(28541,16,FLEN)
NAN_BOXED(29024,16,FLEN)
NAN_BOXED(14739,16,FLEN)
NAN_BOXED(28541,16,FLEN)
NAN_BOXED(29024,16,FLEN)
NAN_BOXED(14739,16,FLEN)
NAN_BOXED(28541,16,FLEN)
NAN_BOXED(29024,16,FLEN)
NAN_BOXED(14739,16,FLEN)
NAN_BOXED(28541,16,FLEN)
NAN_BOXED(29024,16,FLEN)
NAN_BOXED(14739,16,FLEN)
NAN_BOXED(28541,16,FLEN)
NAN_BOXED(27531,16,FLEN)
NAN_BOXED(19075,16,FLEN)
NAN_BOXED(31268,16,FLEN)
NAN_BOXED(27531,16,FLEN)
NAN_BOXED(19075,16,FLEN)
NAN_BOXED(31268,16,FLEN)
NAN_BOXED(27531,16,FLEN)
NAN_BOXED(19075,16,FLEN)
NAN_BOXED(31268,16,FLEN)
NAN_BOXED(27531,16,FLEN)
NAN_BOXED(19075,16,FLEN)
NAN_BOXED(31268,16,FLEN)
NAN_BOXED(27531,16,FLEN)
NAN_BOXED(19075,16,FLEN)
NAN_BOXED(31268,16,FLEN)
NAN_BOXED(28707,16,FLEN)
NAN_BOXED(16296,16,FLEN)
NAN_BOXED(29675,16,FLEN)
NAN_BOXED(28707,16,FLEN)
NAN_BOXED(16296,16,FLEN)
NAN_BOXED(29675,16,FLEN)
NAN_BOXED(28707,16,FLEN)
NAN_BOXED(16296,16,FLEN)
NAN_BOXED(29675,16,FLEN)
NAN_BOXED(28707,16,FLEN)
NAN_BOXED(16296,16,FLEN)
NAN_BOXED(29675,16,FLEN)
NAN_BOXED(28707,16,FLEN)
NAN_BOXED(16296,16,FLEN)
NAN_BOXED(29675,16,FLEN)
NAN_BOXED(30272,16,FLEN)
NAN_BOXED(16501,16,FLEN)
NAN_BOXED(31479,16,FLEN)
NAN_BOXED(30272,16,FLEN)
NAN_BOXED(16501,16,FLEN)
NAN_BOXED(31479,16,FLEN)
NAN_BOXED(30272,16,FLEN)
NAN_BOXED(16501,16,FLEN)
NAN_BOXED(31479,16,FLEN)
NAN_BOXED(30272,16,FLEN)
NAN_BOXED(16501,16,FLEN)
NAN_BOXED(31479,16,FLEN)
NAN_BOXED(30272,16,FLEN)
NAN_BOXED(16501,16,FLEN)
NAN_BOXED(31479,16,FLEN)
NAN_BOXED(27943,16,FLEN)
NAN_BOXED(17810,16,FLEN)
NAN_BOXED(30511,16,FLEN)
NAN_BOXED(27943,16,FLEN)
NAN_BOXED(17810,16,FLEN)
NAN_BOXED(30511,16,FLEN)
NAN_BOXED(27943,16,FLEN)
NAN_BOXED(17810,16,FLEN)
NAN_BOXED(30511,16,FLEN)
NAN_BOXED(27943,16,FLEN)
NAN_BOXED(17810,16,FLEN)
NAN_BOXED(30511,16,FLEN)
NAN_BOXED(27943,16,FLEN)
NAN_BOXED(17810,16,FLEN)
NAN_BOXED(30511,16,FLEN)
NAN_BOXED(30820,16,FLEN)
NAN_BOXED(15982,16,FLEN)
NAN_BOXED(31504,16,FLEN)
NAN_BOXED(30820,16,FLEN)
NAN_BOXED(15982,16,FLEN)
NAN_BOXED(31504,16,FLEN)
NAN_BOXED(30820,16,FLEN)
NAN_BOXED(15982,16,FLEN)
NAN_BOXED(31504,16,FLEN)
NAN_BOXED(30820,16,FLEN)
NAN_BOXED(15982,16,FLEN)
NAN_BOXED(31504,16,FLEN)
NAN_BOXED(30820,16,FLEN)
NAN_BOXED(15982,16,FLEN)
NAN_BOXED(31504,16,FLEN)
NAN_BOXED(31373,16,FLEN)
NAN_BOXED(15415,16,FLEN)
NAN_BOXED(31464,16,FLEN)
NAN_BOXED(31373,16,FLEN)
NAN_BOXED(15415,16,FLEN)
NAN_BOXED(31464,16,FLEN)
NAN_BOXED(31373,16,FLEN)
NAN_BOXED(15415,16,FLEN)
NAN_BOXED(31464,16,FLEN)
NAN_BOXED(31373,16,FLEN)
NAN_BOXED(15415,16,FLEN)
NAN_BOXED(31464,16,FLEN)
NAN_BOXED(31373,16,FLEN)
NAN_BOXED(15415,16,FLEN)
NAN_BOXED(31464,16,FLEN)
NAN_BOXED(29811,16,FLEN)
NAN_BOXED(15863,16,FLEN)
NAN_BOXED(30372,16,FLEN)
NAN_BOXED(29811,16,FLEN)
NAN_BOXED(15863,16,FLEN)
NAN_BOXED(30372,16,FLEN)
NAN_BOXED(29811,16,FLEN)
NAN_BOXED(15863,16,FLEN)
NAN_BOXED(30372,16,FLEN)
NAN_BOXED(29811,16,FLEN)
NAN_BOXED(15863,16,FLEN)
NAN_BOXED(30372,16,FLEN)
NAN_BOXED(29811,16,FLEN)
NAN_BOXED(15863,16,FLEN)
NAN_BOXED(30372,16,FLEN)
NAN_BOXED(30140,16,FLEN)
NAN_BOXED(16621,16,FLEN)
NAN_BOXED(31505,16,FLEN)
NAN_BOXED(30140,16,FLEN)
NAN_BOXED(16621,16,FLEN)
NAN_BOXED(31505,16,FLEN)
NAN_BOXED(30140,16,FLEN)
NAN_BOXED(16621,16,FLEN)
NAN_BOXED(31505,16,FLEN)
NAN_BOXED(30140,16,FLEN)
NAN_BOXED(16621,16,FLEN)
NAN_BOXED(31505,16,FLEN)
NAN_BOXED(30140,16,FLEN)
NAN_BOXED(16621,16,FLEN)
NAN_BOXED(31505,16,FLEN)
NAN_BOXED(31656,16,FLEN)
NAN_BOXED(12555,16,FLEN)
NAN_BOXED(28883,16,FLEN)
NAN_BOXED(31656,16,FLEN)
NAN_BOXED(12555,16,FLEN)
NAN_BOXED(28883,16,FLEN)
NAN_BOXED(31656,16,FLEN)
NAN_BOXED(12555,16,FLEN)
NAN_BOXED(28883,16,FLEN)
NAN_BOXED(31656,16,FLEN)
NAN_BOXED(12555,16,FLEN)
NAN_BOXED(28883,16,FLEN)
NAN_BOXED(31656,16,FLEN)
NAN_BOXED(12555,16,FLEN)
NAN_BOXED(28883,16,FLEN)
NAN_BOXED(29090,16,FLEN)
NAN_BOXED(15683,16,FLEN)
NAN_BOXED(29547,16,FLEN)
NAN_BOXED(29090,16,FLEN)
NAN_BOXED(15683,16,FLEN)
NAN_BOXED(29547,16,FLEN)
NAN_BOXED(29090,16,FLEN)
NAN_BOXED(15683,16,FLEN)
NAN_BOXED(29547,16,FLEN)
NAN_BOXED(29090,16,FLEN)
NAN_BOXED(15683,16,FLEN)
NAN_BOXED(29547,16,FLEN)
NAN_BOXED(29090,16,FLEN)
NAN_BOXED(15683,16,FLEN)
NAN_BOXED(29547,16,FLEN)
NAN_BOXED(29558,16,FLEN)
NAN_BOXED(16424,16,FLEN)
NAN_BOXED(30657,16,FLEN)
NAN_BOXED(29558,16,FLEN)
NAN_BOXED(16424,16,FLEN)
NAN_BOXED(30657,16,FLEN)
NAN_BOXED(29558,16,FLEN)
NAN_BOXED(16424,16,FLEN)
NAN_BOXED(30657,16,FLEN)
NAN_BOXED(29558,16,FLEN)
NAN_BOXED(16424,16,FLEN)
NAN_BOXED(30657,16,FLEN)
NAN_BOXED(29558,16,FLEN)
NAN_BOXED(16424,16,FLEN)
NAN_BOXED(30657,16,FLEN)
NAN_BOXED(30901,16,FLEN)
NAN_BOXED(14114,16,FLEN)
NAN_BOXED(29747,16,FLEN)
NAN_BOXED(30901,16,FLEN)
NAN_BOXED(14114,16,FLEN)
NAN_BOXED(29747,16,FLEN)
NAN_BOXED(30901,16,FLEN)
NAN_BOXED(14114,16,FLEN)
NAN_BOXED(29747,16,FLEN)
NAN_BOXED(30901,16,FLEN)
NAN_BOXED(14114,16,FLEN)
NAN_BOXED(29747,16,FLEN)
NAN_BOXED(30901,16,FLEN)
NAN_BOXED(14114,16,FLEN)
NAN_BOXED(29747,16,FLEN)
NAN_BOXED(23604,16,FLEN)
NAN_BOXED(22111,16,FLEN)
NAN_BOXED(30387,16,FLEN)
NAN_BOXED(23604,16,FLEN)
NAN_BOXED(22111,16,FLEN)
NAN_BOXED(30387,16,FLEN)
NAN_BOXED(23604,16,FLEN)
NAN_BOXED(22111,16,FLEN)
NAN_BOXED(30387,16,FLEN)
NAN_BOXED(23604,16,FLEN)
NAN_BOXED(22111,16,FLEN)
NAN_BOXED(30387,16,FLEN)
NAN_BOXED(23604,16,FLEN)
NAN_BOXED(22111,16,FLEN)
NAN_BOXED(30387,16,FLEN)
NAN_BOXED(30183,16,FLEN)
NAN_BOXED(15906,16,FLEN)
NAN_BOXED(30855,16,FLEN)
NAN_BOXED(30183,16,FLEN)
NAN_BOXED(15906,16,FLEN)
NAN_BOXED(30855,16,FLEN)
NAN_BOXED(30183,16,FLEN)
NAN_BOXED(15906,16,FLEN)
NAN_BOXED(30855,16,FLEN)
NAN_BOXED(30183,16,FLEN)
NAN_BOXED(15906,16,FLEN)
NAN_BOXED(30855,16,FLEN)
NAN_BOXED(30183,16,FLEN)
NAN_BOXED(15906,16,FLEN)
NAN_BOXED(30855,16,FLEN)
NAN_BOXED(31646,16,FLEN)
NAN_BOXED(14795,16,FLEN)
NAN_BOXED(31109,16,FLEN)
NAN_BOXED(31646,16,FLEN)
NAN_BOXED(14795,16,FLEN)
NAN_BOXED(31109,16,FLEN)
NAN_BOXED(31646,16,FLEN)
NAN_BOXED(14795,16,FLEN)
NAN_BOXED(31109,16,FLEN)
NAN_BOXED(31646,16,FLEN)
NAN_BOXED(14795,16,FLEN)
NAN_BOXED(31109,16,FLEN)
NAN_BOXED(31646,16,FLEN)
NAN_BOXED(14795,16,FLEN)
NAN_BOXED(31109,16,FLEN)
NAN_BOXED(30751,16,FLEN)
NAN_BOXED(15562,16,FLEN)
NAN_BOXED(30960,16,FLEN)
NAN_BOXED(30751,16,FLEN)
NAN_BOXED(15562,16,FLEN)
NAN_BOXED(30960,16,FLEN)
NAN_BOXED(30751,16,FLEN)
NAN_BOXED(15562,16,FLEN)
NAN_BOXED(30960,16,FLEN)
NAN_BOXED(30751,16,FLEN)
NAN_BOXED(15562,16,FLEN)
NAN_BOXED(30960,16,FLEN)
NAN_BOXED(30751,16,FLEN)
NAN_BOXED(15562,16,FLEN)
NAN_BOXED(30960,16,FLEN)
NAN_BOXED(31080,16,FLEN)
NAN_BOXED(11548,16,FLEN)
NAN_BOXED(27368,16,FLEN)
NAN_BOXED(31080,16,FLEN)
NAN_BOXED(11548,16,FLEN)
NAN_BOXED(27368,16,FLEN)
NAN_BOXED(31080,16,FLEN)
NAN_BOXED(11548,16,FLEN)
NAN_BOXED(27368,16,FLEN)
NAN_BOXED(31080,16,FLEN)
NAN_BOXED(11548,16,FLEN)
NAN_BOXED(27368,16,FLEN)
NAN_BOXED(31080,16,FLEN)
NAN_BOXED(11548,16,FLEN)
NAN_BOXED(27368,16,FLEN)
NAN_BOXED(31537,16,FLEN)
NAN_BOXED(15087,16,FLEN)
NAN_BOXED(31292,16,FLEN)
NAN_BOXED(31537,16,FLEN)
NAN_BOXED(15087,16,FLEN)
NAN_BOXED(31292,16,FLEN)
NAN_BOXED(31537,16,FLEN)
NAN_BOXED(15087,16,FLEN)
NAN_BOXED(31292,16,FLEN)
NAN_BOXED(31537,16,FLEN)
NAN_BOXED(15087,16,FLEN)
NAN_BOXED(31292,16,FLEN)
NAN_BOXED(31537,16,FLEN)
NAN_BOXED(15087,16,FLEN)
NAN_BOXED(31292,16,FLEN)
NAN_BOXED(31486,16,FLEN)
NAN_BOXED(15180,16,FLEN)
NAN_BOXED(31329,16,FLEN)
NAN_BOXED(31486,16,FLEN)
NAN_BOXED(15180,16,FLEN)
NAN_BOXED(31329,16,FLEN)
NAN_BOXED(31486,16,FLEN)
NAN_BOXED(15180,16,FLEN)
NAN_BOXED(31329,16,FLEN)
NAN_BOXED(31486,16,FLEN)
NAN_BOXED(15180,16,FLEN)
NAN_BOXED(31329,16,FLEN)
NAN_BOXED(31486,16,FLEN)
NAN_BOXED(15180,16,FLEN)
NAN_BOXED(31329,16,FLEN)
NAN_BOXED(30278,16,FLEN)
NAN_BOXED(15377,16,FLEN)
NAN_BOXED(30305,16,FLEN)
NAN_BOXED(30278,16,FLEN)
NAN_BOXED(15377,16,FLEN)
NAN_BOXED(30305,16,FLEN)
NAN_BOXED(30278,16,FLEN)
NAN_BOXED(15377,16,FLEN)
NAN_BOXED(30305,16,FLEN)
NAN_BOXED(30278,16,FLEN)
NAN_BOXED(15377,16,FLEN)
NAN_BOXED(30305,16,FLEN)
NAN_BOXED(30278,16,FLEN)
NAN_BOXED(15377,16,FLEN)
NAN_BOXED(30305,16,FLEN)
NAN_BOXED(28319,16,FLEN)
NAN_BOXED(17952,16,FLEN)
NAN_BOXED(30994,16,FLEN)
NAN_BOXED(28319,16,FLEN)
NAN_BOXED(17952,16,FLEN)
NAN_BOXED(30994,16,FLEN)
NAN_BOXED(28319,16,FLEN)
NAN_BOXED(17952,16,FLEN)
NAN_BOXED(30994,16,FLEN)
NAN_BOXED(28319,16,FLEN)
NAN_BOXED(17952,16,FLEN)
NAN_BOXED(30994,16,FLEN)
NAN_BOXED(28319,16,FLEN)
NAN_BOXED(17952,16,FLEN)
NAN_BOXED(30994,16,FLEN)
NAN_BOXED(27639,16,FLEN)
NAN_BOXED(15443,16,FLEN)
NAN_BOXED(27727,16,FLEN)
NAN_BOXED(27639,16,FLEN)
NAN_BOXED(15443,16,FLEN)
NAN_BOXED(27727,16,FLEN)
NAN_BOXED(27639,16,FLEN)
NAN_BOXED(15443,16,FLEN)
NAN_BOXED(27727,16,FLEN)
NAN_BOXED(27639,16,FLEN)
NAN_BOXED(15443,16,FLEN)
NAN_BOXED(27727,16,FLEN)
NAN_BOXED(27639,16,FLEN)
NAN_BOXED(15443,16,FLEN)
NAN_BOXED(27727,16,FLEN)
NAN_BOXED(29357,16,FLEN)
NAN_BOXED(14904,16,FLEN)
NAN_BOXED(28977,16,FLEN)
NAN_BOXED(29357,16,FLEN)
NAN_BOXED(14904,16,FLEN)
NAN_BOXED(28977,16,FLEN)
NAN_BOXED(29357,16,FLEN)
NAN_BOXED(14904,16,FLEN)
NAN_BOXED(28977,16,FLEN)
NAN_BOXED(29357,16,FLEN)
NAN_BOXED(14904,16,FLEN)
NAN_BOXED(28977,16,FLEN)
NAN_BOXED(29357,16,FLEN)
NAN_BOXED(14904,16,FLEN)
NAN_BOXED(28977,16,FLEN)
NAN_BOXED(30064,16,FLEN)
NAN_BOXED(12530,16,FLEN)
NAN_BOXED(27322,16,FLEN)
NAN_BOXED(30064,16,FLEN)
NAN_BOXED(12530,16,FLEN)
NAN_BOXED(27322,16,FLEN)
NAN_BOXED(30064,16,FLEN)
NAN_BOXED(12530,16,FLEN)
NAN_BOXED(27322,16,FLEN)
NAN_BOXED(30064,16,FLEN)
NAN_BOXED(12530,16,FLEN)
NAN_BOXED(27322,16,FLEN)
NAN_BOXED(30064,16,FLEN)
NAN_BOXED(12530,16,FLEN)
NAN_BOXED(27322,16,FLEN)
NAN_BOXED(19473,16,FLEN)
NAN_BOXED(24769,16,FLEN)
NAN_BOXED(28886,16,FLEN)
NAN_BOXED(19473,16,FLEN)
NAN_BOXED(24769,16,FLEN)
NAN_BOXED(28886,16,FLEN)
NAN_BOXED(19473,16,FLEN)
NAN_BOXED(24769,16,FLEN)
NAN_BOXED(28886,16,FLEN)
NAN_BOXED(19473,16,FLEN)
NAN_BOXED(24769,16,FLEN)
NAN_BOXED(28886,16,FLEN)
NAN_BOXED(19473,16,FLEN)
NAN_BOXED(24769,16,FLEN)
NAN_BOXED(28886,16,FLEN)
NAN_BOXED(28285,16,FLEN)
NAN_BOXED(17194,16,FLEN)
NAN_BOXED(30160,16,FLEN)
NAN_BOXED(28285,16,FLEN)
NAN_BOXED(17194,16,FLEN)
NAN_BOXED(30160,16,FLEN)
NAN_BOXED(28285,16,FLEN)
NAN_BOXED(17194,16,FLEN)
NAN_BOXED(30160,16,FLEN)
NAN_BOXED(28285,16,FLEN)
NAN_BOXED(17194,16,FLEN)
NAN_BOXED(30160,16,FLEN)
NAN_BOXED(28285,16,FLEN)
NAN_BOXED(17194,16,FLEN)
NAN_BOXED(30160,16,FLEN)
NAN_BOXED(26247,16,FLEN)
NAN_BOXED(20552,16,FLEN)
NAN_BOXED(31485,16,FLEN)
NAN_BOXED(26247,16,FLEN)
NAN_BOXED(20552,16,FLEN)
NAN_BOXED(31485,16,FLEN)
NAN_BOXED(26247,16,FLEN)
NAN_BOXED(20552,16,FLEN)
NAN_BOXED(31485,16,FLEN)
NAN_BOXED(26247,16,FLEN)
NAN_BOXED(20552,16,FLEN)
NAN_BOXED(31485,16,FLEN)
NAN_BOXED(26247,16,FLEN)
NAN_BOXED(20552,16,FLEN)
NAN_BOXED(31485,16,FLEN)
NAN_BOXED(30953,16,FLEN)
NAN_BOXED(13245,16,FLEN)
NAN_BOXED(28864,16,FLEN)
NAN_BOXED(30953,16,FLEN)
NAN_BOXED(13245,16,FLEN)
NAN_BOXED(28864,16,FLEN)
NAN_BOXED(30953,16,FLEN)
NAN_BOXED(13245,16,FLEN)
NAN_BOXED(28864,16,FLEN)
NAN_BOXED(30953,16,FLEN)
NAN_BOXED(13245,16,FLEN)
NAN_BOXED(28864,16,FLEN)
NAN_BOXED(30953,16,FLEN)
NAN_BOXED(13245,16,FLEN)
NAN_BOXED(28864,16,FLEN)
NAN_BOXED(29704,16,FLEN)
NAN_BOXED(15746,16,FLEN)
NAN_BOXED(30094,16,FLEN)
NAN_BOXED(29704,16,FLEN)
NAN_BOXED(15746,16,FLEN)
NAN_BOXED(30094,16,FLEN)
NAN_BOXED(29704,16,FLEN)
NAN_BOXED(15746,16,FLEN)
NAN_BOXED(30094,16,FLEN)
NAN_BOXED(29704,16,FLEN)
NAN_BOXED(15746,16,FLEN)
NAN_BOXED(30094,16,FLEN)
NAN_BOXED(29704,16,FLEN)
NAN_BOXED(15746,16,FLEN)
NAN_BOXED(30094,16,FLEN)
NAN_BOXED(30162,16,FLEN)
NAN_BOXED(13669,16,FLEN)
NAN_BOXED(28635,16,FLEN)
NAN_BOXED(30162,16,FLEN)
NAN_BOXED(13669,16,FLEN)
NAN_BOXED(28635,16,FLEN)
NAN_BOXED(30162,16,FLEN)
NAN_BOXED(13669,16,FLEN)
NAN_BOXED(28635,16,FLEN)
NAN_BOXED(30162,16,FLEN)
NAN_BOXED(13669,16,FLEN)
NAN_BOXED(28635,16,FLEN)
NAN_BOXED(30162,16,FLEN)
NAN_BOXED(13669,16,FLEN)
NAN_BOXED(28635,16,FLEN)
NAN_BOXED(31433,16,FLEN)
NAN_BOXED(15533,16,FLEN)
NAN_BOXED(31728,16,FLEN)
NAN_BOXED(31433,16,FLEN)
NAN_BOXED(15533,16,FLEN)
NAN_BOXED(31728,16,FLEN)
NAN_BOXED(31433,16,FLEN)
NAN_BOXED(15533,16,FLEN)
NAN_BOXED(31728,16,FLEN)
NAN_BOXED(31433,16,FLEN)
NAN_BOXED(15533,16,FLEN)
NAN_BOXED(31728,16,FLEN)
NAN_BOXED(31433,16,FLEN)
NAN_BOXED(15533,16,FLEN)
NAN_BOXED(31728,16,FLEN)
NAN_BOXED(30579,16,FLEN)
NAN_BOXED(15399,16,FLEN)
NAN_BOXED(30652,16,FLEN)
NAN_BOXED(30579,16,FLEN)
NAN_BOXED(15399,16,FLEN)
NAN_BOXED(30652,16,FLEN)
NAN_BOXED(30579,16,FLEN)
NAN_BOXED(15399,16,FLEN)
NAN_BOXED(30652,16,FLEN)
NAN_BOXED(30579,16,FLEN)
NAN_BOXED(15399,16,FLEN)
NAN_BOXED(30652,16,FLEN)
NAN_BOXED(30579,16,FLEN)
NAN_BOXED(15399,16,FLEN)
NAN_BOXED(30652,16,FLEN)
NAN_BOXED(28030,16,FLEN)
NAN_BOXED(15554,16,FLEN)
NAN_BOXED(28297,16,FLEN)
NAN_BOXED(28030,16,FLEN)
NAN_BOXED(15554,16,FLEN)
NAN_BOXED(28297,16,FLEN)
NAN_BOXED(28030,16,FLEN)
NAN_BOXED(15554,16,FLEN)
NAN_BOXED(28297,16,FLEN)
NAN_BOXED(28030,16,FLEN)
NAN_BOXED(15554,16,FLEN)
NAN_BOXED(28297,16,FLEN)
NAN_BOXED(28030,16,FLEN)
NAN_BOXED(15554,16,FLEN)
NAN_BOXED(28297,16,FLEN)
NAN_BOXED(30074,16,FLEN)
NAN_BOXED(14894,16,FLEN)
NAN_BOXED(29755,16,FLEN)
NAN_BOXED(30074,16,FLEN)
NAN_BOXED(14894,16,FLEN)
NAN_BOXED(29755,16,FLEN)
NAN_BOXED(30074,16,FLEN)
NAN_BOXED(14894,16,FLEN)
NAN_BOXED(29755,16,FLEN)
NAN_BOXED(30074,16,FLEN)
NAN_BOXED(14894,16,FLEN)
NAN_BOXED(29755,16,FLEN)
NAN_BOXED(30074,16,FLEN)
NAN_BOXED(14894,16,FLEN)
NAN_BOXED(29755,16,FLEN)
NAN_BOXED(31392,16,FLEN)
NAN_BOXED(12859,16,FLEN)
NAN_BOXED(28969,16,FLEN)
NAN_BOXED(31392,16,FLEN)
NAN_BOXED(12859,16,FLEN)
NAN_BOXED(28969,16,FLEN)
NAN_BOXED(31392,16,FLEN)
NAN_BOXED(12859,16,FLEN)
NAN_BOXED(28969,16,FLEN)
NAN_BOXED(31392,16,FLEN)
NAN_BOXED(12859,16,FLEN)
NAN_BOXED(28969,16,FLEN)
NAN_BOXED(31392,16,FLEN)
NAN_BOXED(12859,16,FLEN)
NAN_BOXED(28969,16,FLEN)
NAN_BOXED(26089,16,FLEN)
NAN_BOXED(20772,16,FLEN)
NAN_BOXED(31642,16,FLEN)
NAN_BOXED(26089,16,FLEN)
NAN_BOXED(20772,16,FLEN)
NAN_BOXED(31642,16,FLEN)
NAN_BOXED(26089,16,FLEN)
NAN_BOXED(20772,16,FLEN)
NAN_BOXED(31642,16,FLEN)
NAN_BOXED(26089,16,FLEN)
NAN_BOXED(20772,16,FLEN)
NAN_BOXED(31642,16,FLEN)
NAN_BOXED(26089,16,FLEN)
NAN_BOXED(20772,16,FLEN)
NAN_BOXED(31642,16,FLEN)
NAN_BOXED(30777,16,FLEN)
NAN_BOXED(13424,16,FLEN)
NAN_BOXED(28848,16,FLEN)
NAN_BOXED(30777,16,FLEN)
NAN_BOXED(13424,16,FLEN)
NAN_BOXED(28848,16,FLEN)
NAN_BOXED(30777,16,FLEN)
NAN_BOXED(13424,16,FLEN)
NAN_BOXED(28848,16,FLEN)
NAN_BOXED(30777,16,FLEN)
NAN_BOXED(13424,16,FLEN)
NAN_BOXED(28848,16,FLEN)
NAN_BOXED(30777,16,FLEN)
NAN_BOXED(13424,16,FLEN)
NAN_BOXED(28848,16,FLEN)
NAN_BOXED(30807,16,FLEN)
NAN_BOXED(10848,16,FLEN)
NAN_BOXED(26348,16,FLEN)
NAN_BOXED(30807,16,FLEN)
NAN_BOXED(10848,16,FLEN)
NAN_BOXED(26348,16,FLEN)
NAN_BOXED(30807,16,FLEN)
NAN_BOXED(10848,16,FLEN)
NAN_BOXED(26348,16,FLEN)
NAN_BOXED(30807,16,FLEN)
NAN_BOXED(10848,16,FLEN)
NAN_BOXED(26348,16,FLEN)
NAN_BOXED(30807,16,FLEN)
NAN_BOXED(10848,16,FLEN)
NAN_BOXED(26348,16,FLEN)
NAN_BOXED(30777,16,FLEN)
NAN_BOXED(16233,16,FLEN)
NAN_BOXED(31698,16,FLEN)
NAN_BOXED(30777,16,FLEN)
NAN_BOXED(16233,16,FLEN)
NAN_BOXED(31698,16,FLEN)
NAN_BOXED(30777,16,FLEN)
NAN_BOXED(16233,16,FLEN)
NAN_BOXED(31698,16,FLEN)
NAN_BOXED(30777,16,FLEN)
NAN_BOXED(16233,16,FLEN)
NAN_BOXED(31698,16,FLEN)
NAN_BOXED(30777,16,FLEN)
NAN_BOXED(16233,16,FLEN)
NAN_BOXED(31698,16,FLEN)
NAN_BOXED(31463,16,FLEN)
NAN_BOXED(14963,16,FLEN)
NAN_BOXED(31121,16,FLEN)
NAN_BOXED(31463,16,FLEN)
NAN_BOXED(14963,16,FLEN)
NAN_BOXED(31121,16,FLEN)
NAN_BOXED(31463,16,FLEN)
NAN_BOXED(14963,16,FLEN)
NAN_BOXED(31121,16,FLEN)
NAN_BOXED(31463,16,FLEN)
NAN_BOXED(14963,16,FLEN)
NAN_BOXED(31121,16,FLEN)
NAN_BOXED(31463,16,FLEN)
NAN_BOXED(14963,16,FLEN)
NAN_BOXED(31121,16,FLEN)
NAN_BOXED(29741,16,FLEN)
NAN_BOXED(15774,16,FLEN)
NAN_BOXED(30173,16,FLEN)
NAN_BOXED(29741,16,FLEN)
NAN_BOXED(15774,16,FLEN)
NAN_BOXED(30173,16,FLEN)
NAN_BOXED(29741,16,FLEN)
NAN_BOXED(15774,16,FLEN)
NAN_BOXED(30173,16,FLEN)
NAN_BOXED(29741,16,FLEN)
NAN_BOXED(15774,16,FLEN)
NAN_BOXED(30173,16,FLEN)
NAN_BOXED(29741,16,FLEN)
NAN_BOXED(15774,16,FLEN)
NAN_BOXED(30173,16,FLEN)
NAN_BOXED(29015,16,FLEN)
NAN_BOXED(17566,16,FLEN)
NAN_BOXED(31276,16,FLEN)
NAN_BOXED(29015,16,FLEN)
NAN_BOXED(17566,16,FLEN)
NAN_BOXED(31276,16,FLEN)
NAN_BOXED(29015,16,FLEN)
NAN_BOXED(17566,16,FLEN)
NAN_BOXED(31276,16,FLEN)
NAN_BOXED(29015,16,FLEN)
NAN_BOXED(17566,16,FLEN)
NAN_BOXED(31276,16,FLEN)
NAN_BOXED(29015,16,FLEN)
NAN_BOXED(17566,16,FLEN)
NAN_BOXED(31276,16,FLEN)
NAN_BOXED(30786,16,FLEN)
NAN_BOXED(15833,16,FLEN)
NAN_BOXED(31290,16,FLEN)
NAN_BOXED(30786,16,FLEN)
NAN_BOXED(15833,16,FLEN)
NAN_BOXED(31290,16,FLEN)
NAN_BOXED(30786,16,FLEN)
NAN_BOXED(15833,16,FLEN)
NAN_BOXED(31290,16,FLEN)
NAN_BOXED(30786,16,FLEN)
NAN_BOXED(15833,16,FLEN)
NAN_BOXED(31290,16,FLEN)
NAN_BOXED(30786,16,FLEN)
NAN_BOXED(15833,16,FLEN)
NAN_BOXED(31290,16,FLEN)
NAN_BOXED(30021,16,FLEN)
NAN_BOXED(14697,16,FLEN)
NAN_BOXED(29474,16,FLEN)
NAN_BOXED(30021,16,FLEN)
NAN_BOXED(14697,16,FLEN)
NAN_BOXED(29474,16,FLEN)
NAN_BOXED(30021,16,FLEN)
NAN_BOXED(14697,16,FLEN)
NAN_BOXED(29474,16,FLEN)
NAN_BOXED(30021,16,FLEN)
NAN_BOXED(14697,16,FLEN)
NAN_BOXED(29474,16,FLEN)
NAN_BOXED(30021,16,FLEN)
NAN_BOXED(14697,16,FLEN)
NAN_BOXED(29474,16,FLEN)
NAN_BOXED(31357,16,FLEN)
NAN_BOXED(15578,16,FLEN)
NAN_BOXED(31712,16,FLEN)
NAN_BOXED(31357,16,FLEN)
NAN_BOXED(15578,16,FLEN)
NAN_BOXED(31712,16,FLEN)
NAN_BOXED(31357,16,FLEN)
NAN_BOXED(15578,16,FLEN)
NAN_BOXED(31712,16,FLEN)
NAN_BOXED(31357,16,FLEN)
NAN_BOXED(15578,16,FLEN)
NAN_BOXED(31712,16,FLEN)
NAN_BOXED(31357,16,FLEN)
NAN_BOXED(15578,16,FLEN)
NAN_BOXED(31712,16,FLEN)
NAN_BOXED(31441,16,FLEN)
NAN_BOXED(15248,16,FLEN)
NAN_BOXED(31346,16,FLEN)
NAN_BOXED(31441,16,FLEN)
NAN_BOXED(15248,16,FLEN)
NAN_BOXED(31346,16,FLEN)
NAN_BOXED(31441,16,FLEN)
NAN_BOXED(15248,16,FLEN)
NAN_BOXED(31346,16,FLEN)
NAN_BOXED(31441,16,FLEN)
NAN_BOXED(15248,16,FLEN)
NAN_BOXED(31346,16,FLEN)
NAN_BOXED(31441,16,FLEN)
NAN_BOXED(15248,16,FLEN)
NAN_BOXED(31346,16,FLEN)
NAN_BOXED(31371,16,FLEN)
NAN_BOXED(15163,16,FLEN)
NAN_BOXED(31210,16,FLEN)
NAN_BOXED(31371,16,FLEN)
NAN_BOXED(15163,16,FLEN)
NAN_BOXED(31210,16,FLEN)
NAN_BOXED(31371,16,FLEN)
NAN_BOXED(15163,16,FLEN)
NAN_BOXED(31210,16,FLEN)
NAN_BOXED(31371,16,FLEN)
NAN_BOXED(15163,16,FLEN)
NAN_BOXED(31210,16,FLEN)
NAN_BOXED(31371,16,FLEN)
NAN_BOXED(15163,16,FLEN)
NAN_BOXED(31210,16,FLEN)
NAN_BOXED(29504,16,FLEN)
NAN_BOXED(16528,16,FLEN)
NAN_BOXED(30755,16,FLEN)
NAN_BOXED(29504,16,FLEN)
NAN_BOXED(16528,16,FLEN)
NAN_BOXED(30755,16,FLEN)
NAN_BOXED(29504,16,FLEN)
NAN_BOXED(16528,16,FLEN)
NAN_BOXED(30755,16,FLEN)
NAN_BOXED(29504,16,FLEN)
NAN_BOXED(16528,16,FLEN)
NAN_BOXED(30755,16,FLEN)
NAN_BOXED(29504,16,FLEN)
NAN_BOXED(16528,16,FLEN)
NAN_BOXED(30755,16,FLEN)
NAN_BOXED(30127,16,FLEN)
NAN_BOXED(11576,16,FLEN)
NAN_BOXED(26475,16,FLEN)
NAN_BOXED(30127,16,FLEN)
NAN_BOXED(11576,16,FLEN)
NAN_BOXED(26475,16,FLEN)
NAN_BOXED(30127,16,FLEN)
NAN_BOXED(11576,16,FLEN)
NAN_BOXED(26475,16,FLEN)
NAN_BOXED(30127,16,FLEN)
NAN_BOXED(11576,16,FLEN)
NAN_BOXED(26475,16,FLEN)
NAN_BOXED(30127,16,FLEN)
NAN_BOXED(11576,16,FLEN)
NAN_BOXED(26475,16,FLEN)
NAN_BOXED(26406,16,FLEN)
NAN_BOXED(18687,16,FLEN)
NAN_BOXED(29815,16,FLEN)
NAN_BOXED(26406,16,FLEN)
NAN_BOXED(18687,16,FLEN)
NAN_BOXED(29815,16,FLEN)
NAN_BOXED(26406,16,FLEN)
NAN_BOXED(18687,16,FLEN)
NAN_BOXED(29815,16,FLEN)
NAN_BOXED(26406,16,FLEN)
NAN_BOXED(18687,16,FLEN)
NAN_BOXED(29815,16,FLEN)
NAN_BOXED(26406,16,FLEN)
NAN_BOXED(18687,16,FLEN)
NAN_BOXED(29815,16,FLEN)
NAN_BOXED(29733,16,FLEN)
NAN_BOXED(16728,16,FLEN)
NAN_BOXED(31113,16,FLEN)
NAN_BOXED(29733,16,FLEN)
NAN_BOXED(16728,16,FLEN)
NAN_BOXED(31113,16,FLEN)
NAN_BOXED(29733,16,FLEN)
NAN_BOXED(16728,16,FLEN)
NAN_BOXED(31113,16,FLEN)
NAN_BOXED(29733,16,FLEN)
NAN_BOXED(16728,16,FLEN)
NAN_BOXED(31113,16,FLEN)
NAN_BOXED(29733,16,FLEN)
NAN_BOXED(16728,16,FLEN)
NAN_BOXED(31113,16,FLEN)
NAN_BOXED(31653,16,FLEN)
NAN_BOXED(14203,16,FLEN)
NAN_BOXED(30502,16,FLEN)
NAN_BOXED(31653,16,FLEN)
NAN_BOXED(14203,16,FLEN)
NAN_BOXED(30502,16,FLEN)
NAN_BOXED(31653,16,FLEN)
NAN_BOXED(14203,16,FLEN)
NAN_BOXED(30502,16,FLEN)
NAN_BOXED(31653,16,FLEN)
NAN_BOXED(14203,16,FLEN)
NAN_BOXED(30502,16,FLEN)
NAN_BOXED(31653,16,FLEN)
NAN_BOXED(14203,16,FLEN)
NAN_BOXED(30502,16,FLEN)
NAN_BOXED(31614,16,FLEN)
NAN_BOXED(15415,16,FLEN)
NAN_BOXED(31718,16,FLEN)
NAN_BOXED(31614,16,FLEN)
NAN_BOXED(15415,16,FLEN)
NAN_BOXED(31718,16,FLEN)
NAN_BOXED(31614,16,FLEN)
NAN_BOXED(15415,16,FLEN)
NAN_BOXED(31718,16,FLEN)
NAN_BOXED(31614,16,FLEN)
NAN_BOXED(15415,16,FLEN)
NAN_BOXED(31718,16,FLEN)
NAN_BOXED(31614,16,FLEN)
NAN_BOXED(15415,16,FLEN)
NAN_BOXED(31718,16,FLEN)
NAN_BOXED(31650,16,FLEN)
NAN_BOXED(13851,16,FLEN)
NAN_BOXED(30164,16,FLEN)
NAN_BOXED(31650,16,FLEN)
NAN_BOXED(13851,16,FLEN)
NAN_BOXED(30164,16,FLEN)
NAN_BOXED(31650,16,FLEN)
NAN_BOXED(13851,16,FLEN)
NAN_BOXED(30164,16,FLEN)
NAN_BOXED(31650,16,FLEN)
NAN_BOXED(13851,16,FLEN)
NAN_BOXED(30164,16,FLEN)
NAN_BOXED(31650,16,FLEN)
NAN_BOXED(13851,16,FLEN)
NAN_BOXED(30164,16,FLEN)
NAN_BOXED(29453,16,FLEN)
NAN_BOXED(15389,16,FLEN)
NAN_BOXED(29505,16,FLEN)
NAN_BOXED(29453,16,FLEN)
NAN_BOXED(15389,16,FLEN)
NAN_BOXED(29505,16,FLEN)
NAN_BOXED(29453,16,FLEN)
NAN_BOXED(15389,16,FLEN)
NAN_BOXED(29505,16,FLEN)
NAN_BOXED(29453,16,FLEN)
NAN_BOXED(15389,16,FLEN)
NAN_BOXED(29505,16,FLEN)
NAN_BOXED(29453,16,FLEN)
NAN_BOXED(15389,16,FLEN)
NAN_BOXED(29505,16,FLEN)
NAN_BOXED(29258,16,FLEN)
NAN_BOXED(15399,16,FLEN)
NAN_BOXED(29321,16,FLEN)
NAN_BOXED(29258,16,FLEN)
NAN_BOXED(15399,16,FLEN)
NAN_BOXED(29321,16,FLEN)
NAN_BOXED(29258,16,FLEN)
NAN_BOXED(15399,16,FLEN)
NAN_BOXED(29321,16,FLEN)
NAN_BOXED(29258,16,FLEN)
NAN_BOXED(15399,16,FLEN)
NAN_BOXED(29321,16,FLEN)
NAN_BOXED(29258,16,FLEN)
NAN_BOXED(15399,16,FLEN)
NAN_BOXED(29321,16,FLEN)
NAN_BOXED(30973,16,FLEN)
NAN_BOXED(15813,16,FLEN)
NAN_BOXED(31538,16,FLEN)
NAN_BOXED(30973,16,FLEN)
NAN_BOXED(15813,16,FLEN)
NAN_BOXED(31538,16,FLEN)
NAN_BOXED(30973,16,FLEN)
NAN_BOXED(15813,16,FLEN)
NAN_BOXED(31538,16,FLEN)
NAN_BOXED(30973,16,FLEN)
NAN_BOXED(15813,16,FLEN)
NAN_BOXED(31538,16,FLEN)
NAN_BOXED(30973,16,FLEN)
NAN_BOXED(15813,16,FLEN)
NAN_BOXED(31538,16,FLEN)
NAN_BOXED(31416,16,FLEN)
NAN_BOXED(14480,16,FLEN)
NAN_BOXED(30634,16,FLEN)
NAN_BOXED(31416,16,FLEN)
NAN_BOXED(14480,16,FLEN)
NAN_BOXED(30634,16,FLEN)
NAN_BOXED(31416,16,FLEN)
NAN_BOXED(14480,16,FLEN)
NAN_BOXED(30634,16,FLEN)
NAN_BOXED(31416,16,FLEN)
NAN_BOXED(14480,16,FLEN)
NAN_BOXED(30634,16,FLEN)
NAN_BOXED(31416,16,FLEN)
NAN_BOXED(14480,16,FLEN)
NAN_BOXED(30634,16,FLEN)
NAN_BOXED(31032,16,FLEN)
NAN_BOXED(15589,16,FLEN)
NAN_BOXED(31332,16,FLEN)
NAN_BOXED(31032,16,FLEN)
NAN_BOXED(15589,16,FLEN)
NAN_BOXED(31332,16,FLEN)
NAN_BOXED(31032,16,FLEN)
NAN_BOXED(15589,16,FLEN)
NAN_BOXED(31332,16,FLEN)
NAN_BOXED(31032,16,FLEN)
NAN_BOXED(15589,16,FLEN)
NAN_BOXED(31332,16,FLEN)
NAN_BOXED(31032,16,FLEN)
NAN_BOXED(15589,16,FLEN)
NAN_BOXED(31332,16,FLEN)
NAN_BOXED(28012,16,FLEN)
NAN_BOXED(18378,16,FLEN)
NAN_BOXED(31048,16,FLEN)
NAN_BOXED(28012,16,FLEN)
NAN_BOXED(18378,16,FLEN)
NAN_BOXED(31048,16,FLEN)
NAN_BOXED(28012,16,FLEN)
NAN_BOXED(18378,16,FLEN)
NAN_BOXED(31048,16,FLEN)
NAN_BOXED(28012,16,FLEN)
NAN_BOXED(18378,16,FLEN)
NAN_BOXED(31048,16,FLEN)
NAN_BOXED(28012,16,FLEN)
NAN_BOXED(18378,16,FLEN)
NAN_BOXED(31048,16,FLEN)
NAN_BOXED(31558,16,FLEN)
NAN_BOXED(15073,16,FLEN)
NAN_BOXED(31297,16,FLEN)
NAN_BOXED(31558,16,FLEN)
NAN_BOXED(15073,16,FLEN)
NAN_BOXED(31297,16,FLEN)
NAN_BOXED(31558,16,FLEN)
NAN_BOXED(15073,16,FLEN)
NAN_BOXED(31297,16,FLEN)
NAN_BOXED(31558,16,FLEN)
NAN_BOXED(15073,16,FLEN)
NAN_BOXED(31297,16,FLEN)
NAN_BOXED(31558,16,FLEN)
NAN_BOXED(15073,16,FLEN)
NAN_BOXED(31297,16,FLEN)
NAN_BOXED(31231,16,FLEN)
NAN_BOXED(14617,16,FLEN)
NAN_BOXED(30629,16,FLEN)
NAN_BOXED(31231,16,FLEN)
NAN_BOXED(14617,16,FLEN)
NAN_BOXED(30629,16,FLEN)
NAN_BOXED(31231,16,FLEN)
NAN_BOXED(14617,16,FLEN)
NAN_BOXED(30629,16,FLEN)
NAN_BOXED(31231,16,FLEN)
NAN_BOXED(14617,16,FLEN)
NAN_BOXED(30629,16,FLEN)
NAN_BOXED(31231,16,FLEN)
NAN_BOXED(14617,16,FLEN)
NAN_BOXED(30629,16,FLEN)
NAN_BOXED(29109,16,FLEN)
NAN_BOXED(17515,16,FLEN)
NAN_BOXED(31311,16,FLEN)
NAN_BOXED(29109,16,FLEN)
NAN_BOXED(17515,16,FLEN)
NAN_BOXED(31311,16,FLEN)
NAN_BOXED(29109,16,FLEN)
NAN_BOXED(17515,16,FLEN)
NAN_BOXED(31311,16,FLEN)
NAN_BOXED(29109,16,FLEN)
NAN_BOXED(17515,16,FLEN)
NAN_BOXED(31311,16,FLEN)
NAN_BOXED(29109,16,FLEN)
NAN_BOXED(17515,16,FLEN)
NAN_BOXED(31311,16,FLEN)
NAN_BOXED(30033,16,FLEN)
NAN_BOXED(16593,16,FLEN)
NAN_BOXED(31335,16,FLEN)
NAN_BOXED(30033,16,FLEN)
NAN_BOXED(16593,16,FLEN)
NAN_BOXED(31335,16,FLEN)
NAN_BOXED(30033,16,FLEN)
NAN_BOXED(16593,16,FLEN)
NAN_BOXED(31335,16,FLEN)
NAN_BOXED(30033,16,FLEN)
NAN_BOXED(16593,16,FLEN)
NAN_BOXED(31335,16,FLEN)
NAN_BOXED(30033,16,FLEN)
NAN_BOXED(16593,16,FLEN)
NAN_BOXED(31335,16,FLEN)
NAN_BOXED(31684,16,FLEN)
NAN_BOXED(13956,16,FLEN)
NAN_BOXED(30292,16,FLEN)
NAN_BOXED(31684,16,FLEN)
NAN_BOXED(13956,16,FLEN)
NAN_BOXED(30292,16,FLEN)
NAN_BOXED(31684,16,FLEN)
NAN_BOXED(13956,16,FLEN)
NAN_BOXED(30292,16,FLEN)
NAN_BOXED(31684,16,FLEN)
NAN_BOXED(13956,16,FLEN)
NAN_BOXED(30292,16,FLEN)
NAN_BOXED(31684,16,FLEN)
NAN_BOXED(13956,16,FLEN)
NAN_BOXED(30292,16,FLEN)
NAN_BOXED(30315,16,FLEN)
NAN_BOXED(16567,16,FLEN)
NAN_BOXED(31634,16,FLEN)
NAN_BOXED(30315,16,FLEN)
NAN_BOXED(16567,16,FLEN)
NAN_BOXED(31634,16,FLEN)
NAN_BOXED(30315,16,FLEN)
NAN_BOXED(16567,16,FLEN)
NAN_BOXED(31634,16,FLEN)
NAN_BOXED(30315,16,FLEN)
NAN_BOXED(16567,16,FLEN)
NAN_BOXED(31634,16,FLEN)
NAN_BOXED(30315,16,FLEN)
NAN_BOXED(16567,16,FLEN)
NAN_BOXED(31634,16,FLEN)
NAN_BOXED(31179,16,FLEN)
NAN_BOXED(13185,16,FLEN)
NAN_BOXED(29040,16,FLEN)
NAN_BOXED(31179,16,FLEN)
NAN_BOXED(13185,16,FLEN)
NAN_BOXED(29040,16,FLEN)
NAN_BOXED(31179,16,FLEN)
NAN_BOXED(13185,16,FLEN)
NAN_BOXED(29040,16,FLEN)
NAN_BOXED(31179,16,FLEN)
NAN_BOXED(13185,16,FLEN)
NAN_BOXED(29040,16,FLEN)
NAN_BOXED(31179,16,FLEN)
NAN_BOXED(13185,16,FLEN)
NAN_BOXED(29040,16,FLEN)
NAN_BOXED(28688,16,FLEN)
NAN_BOXED(15554,16,FLEN)
NAN_BOXED(28885,16,FLEN)
NAN_BOXED(28688,16,FLEN)
NAN_BOXED(15554,16,FLEN)
NAN_BOXED(28885,16,FLEN)
NAN_BOXED(28688,16,FLEN)
NAN_BOXED(15554,16,FLEN)
NAN_BOXED(28885,16,FLEN)
NAN_BOXED(28688,16,FLEN)
NAN_BOXED(15554,16,FLEN)
NAN_BOXED(28885,16,FLEN)
NAN_BOXED(28688,16,FLEN)
NAN_BOXED(15554,16,FLEN)
NAN_BOXED(28885,16,FLEN)
NAN_BOXED(31548,16,FLEN)
NAN_BOXED(15137,16,FLEN)
NAN_BOXED(31346,16,FLEN)
NAN_BOXED(31548,16,FLEN)
NAN_BOXED(15137,16,FLEN)
NAN_BOXED(31346,16,FLEN)
NAN_BOXED(31548,16,FLEN)
NAN_BOXED(15137,16,FLEN)
NAN_BOXED(31346,16,FLEN)
NAN_BOXED(31548,16,FLEN)
NAN_BOXED(15137,16,FLEN)
NAN_BOXED(31346,16,FLEN)
NAN_BOXED(31548,16,FLEN)
NAN_BOXED(15137,16,FLEN)
NAN_BOXED(31346,16,FLEN)
NAN_BOXED(28844,16,FLEN)
NAN_BOXED(17831,16,FLEN)
NAN_BOXED(31387,16,FLEN)
NAN_BOXED(28844,16,FLEN)
NAN_BOXED(17831,16,FLEN)
NAN_BOXED(31387,16,FLEN)
NAN_BOXED(28844,16,FLEN)
NAN_BOXED(17831,16,FLEN)
NAN_BOXED(31387,16,FLEN)
NAN_BOXED(28844,16,FLEN)
NAN_BOXED(17831,16,FLEN)
NAN_BOXED(31387,16,FLEN)
NAN_BOXED(28844,16,FLEN)
NAN_BOXED(17831,16,FLEN)
NAN_BOXED(31387,16,FLEN)
NAN_BOXED(31702,16,FLEN)
NAN_BOXED(14685,16,FLEN)
NAN_BOXED(31041,16,FLEN)
NAN_BOXED(31702,16,FLEN)
NAN_BOXED(14685,16,FLEN)
NAN_BOXED(31041,16,FLEN)
NAN_BOXED(31702,16,FLEN)
NAN_BOXED(14685,16,FLEN)
NAN_BOXED(31041,16,FLEN)
NAN_BOXED(31702,16,FLEN)
NAN_BOXED(14685,16,FLEN)
NAN_BOXED(31041,16,FLEN)
NAN_BOXED(31702,16,FLEN)
NAN_BOXED(14685,16,FLEN)
NAN_BOXED(31041,16,FLEN)
NAN_BOXED(30106,16,FLEN)
NAN_BOXED(15939,16,FLEN)
NAN_BOXED(30819,16,FLEN)
NAN_BOXED(30106,16,FLEN)
NAN_BOXED(15939,16,FLEN)
NAN_BOXED(30819,16,FLEN)
NAN_BOXED(30106,16,FLEN)
NAN_BOXED(15939,16,FLEN)
NAN_BOXED(30819,16,FLEN)
NAN_BOXED(30106,16,FLEN)
NAN_BOXED(15939,16,FLEN)
NAN_BOXED(30819,16,FLEN)
NAN_BOXED(30106,16,FLEN)
NAN_BOXED(15939,16,FLEN)
NAN_BOXED(30819,16,FLEN)
NAN_BOXED(28720,16,FLEN)
NAN_BOXED(12023,16,FLEN)
NAN_BOXED(25419,16,FLEN)
NAN_BOXED(28720,16,FLEN)
NAN_BOXED(12023,16,FLEN)
NAN_BOXED(25419,16,FLEN)
NAN_BOXED(28720,16,FLEN)
NAN_BOXED(12023,16,FLEN)
NAN_BOXED(25419,16,FLEN)
NAN_BOXED(28720,16,FLEN)
NAN_BOXED(12023,16,FLEN)
NAN_BOXED(25419,16,FLEN)
NAN_BOXED(28720,16,FLEN)
NAN_BOXED(12023,16,FLEN)
NAN_BOXED(25419,16,FLEN)
NAN_BOXED(31683,16,FLEN)
NAN_BOXED(14682,16,FLEN)
NAN_BOXED(31025,16,FLEN)
NAN_BOXED(31683,16,FLEN)
NAN_BOXED(14682,16,FLEN)
NAN_BOXED(31025,16,FLEN)
NAN_BOXED(31683,16,FLEN)
NAN_BOXED(14682,16,FLEN)
NAN_BOXED(31025,16,FLEN)
NAN_BOXED(31683,16,FLEN)
NAN_BOXED(14682,16,FLEN)
NAN_BOXED(31025,16,FLEN)
NAN_BOXED(31683,16,FLEN)
NAN_BOXED(14682,16,FLEN)
NAN_BOXED(31025,16,FLEN)
NAN_BOXED(30773,16,FLEN)
NAN_BOXED(16151,16,FLEN)
NAN_BOXED(31607,16,FLEN)
NAN_BOXED(30773,16,FLEN)
NAN_BOXED(16151,16,FLEN)
NAN_BOXED(31607,16,FLEN)
NAN_BOXED(30773,16,FLEN)
NAN_BOXED(16151,16,FLEN)
NAN_BOXED(31607,16,FLEN)
NAN_BOXED(30773,16,FLEN)
NAN_BOXED(16151,16,FLEN)
NAN_BOXED(31607,16,FLEN)
NAN_BOXED(30773,16,FLEN)
NAN_BOXED(16151,16,FLEN)
NAN_BOXED(31607,16,FLEN)
NAN_BOXED(30448,16,FLEN)
NAN_BOXED(16388,16,FLEN)
NAN_BOXED(31480,16,FLEN)
NAN_BOXED(30448,16,FLEN)
NAN_BOXED(16388,16,FLEN)
NAN_BOXED(31480,16,FLEN)
NAN_BOXED(30448,16,FLEN)
NAN_BOXED(16388,16,FLEN)
NAN_BOXED(31480,16,FLEN)
NAN_BOXED(30448,16,FLEN)
NAN_BOXED(16388,16,FLEN)
NAN_BOXED(31480,16,FLEN)
NAN_BOXED(30448,16,FLEN)
NAN_BOXED(16388,16,FLEN)
NAN_BOXED(31480,16,FLEN)
NAN_BOXED(31387,16,FLEN)
NAN_BOXED(13334,16,FLEN)
NAN_BOXED(29376,16,FLEN)
NAN_BOXED(31387,16,FLEN)
NAN_BOXED(13334,16,FLEN)
NAN_BOXED(29376,16,FLEN)
NAN_BOXED(31387,16,FLEN)
NAN_BOXED(13334,16,FLEN)
NAN_BOXED(29376,16,FLEN)
NAN_BOXED(31387,16,FLEN)
NAN_BOXED(13334,16,FLEN)
NAN_BOXED(29376,16,FLEN)
NAN_BOXED(31387,16,FLEN)
NAN_BOXED(13334,16,FLEN)
NAN_BOXED(29376,16,FLEN)
NAN_BOXED(29703,16,FLEN)
NAN_BOXED(15527,16,FLEN)
NAN_BOXED(29871,16,FLEN)
NAN_BOXED(29703,16,FLEN)
NAN_BOXED(15527,16,FLEN)
NAN_BOXED(29871,16,FLEN)
NAN_BOXED(29703,16,FLEN)
NAN_BOXED(15527,16,FLEN)
NAN_BOXED(29871,16,FLEN)
NAN_BOXED(29703,16,FLEN)
NAN_BOXED(15527,16,FLEN)
NAN_BOXED(29871,16,FLEN)
NAN_BOXED(29703,16,FLEN)
NAN_BOXED(15527,16,FLEN)
NAN_BOXED(29871,16,FLEN)
NAN_BOXED(29617,16,FLEN)
NAN_BOXED(16608,16,FLEN)
NAN_BOXED(30896,16,FLEN)
NAN_BOXED(29617,16,FLEN)
NAN_BOXED(16608,16,FLEN)
NAN_BOXED(30896,16,FLEN)
NAN_BOXED(29617,16,FLEN)
NAN_BOXED(16608,16,FLEN)
NAN_BOXED(30896,16,FLEN)
NAN_BOXED(29617,16,FLEN)
NAN_BOXED(16608,16,FLEN)
NAN_BOXED(30896,16,FLEN)
NAN_BOXED(29617,16,FLEN)
NAN_BOXED(16608,16,FLEN)
NAN_BOXED(30896,16,FLEN)
NAN_BOXED(29733,16,FLEN)
NAN_BOXED(15990,16,FLEN)
NAN_BOXED(30387,16,FLEN)
NAN_BOXED(29733,16,FLEN)
NAN_BOXED(15990,16,FLEN)
NAN_BOXED(30387,16,FLEN)
NAN_BOXED(29733,16,FLEN)
NAN_BOXED(15990,16,FLEN)
NAN_BOXED(30387,16,FLEN)
NAN_BOXED(29733,16,FLEN)
NAN_BOXED(15990,16,FLEN)
NAN_BOXED(30387,16,FLEN)
NAN_BOXED(29733,16,FLEN)
NAN_BOXED(15990,16,FLEN)
NAN_BOXED(30387,16,FLEN)
NAN_BOXED(28721,16,FLEN)
NAN_BOXED(18161,16,FLEN)
NAN_BOXED(31558,16,FLEN)
NAN_BOXED(28721,16,FLEN)
NAN_BOXED(18161,16,FLEN)
NAN_BOXED(31558,16,FLEN)
NAN_BOXED(28721,16,FLEN)
NAN_BOXED(18161,16,FLEN)
NAN_BOXED(31558,16,FLEN)
NAN_BOXED(28721,16,FLEN)
NAN_BOXED(18161,16,FLEN)
NAN_BOXED(31558,16,FLEN)
NAN_BOXED(28721,16,FLEN)
NAN_BOXED(18161,16,FLEN)
NAN_BOXED(31558,16,FLEN)
NAN_BOXED(30120,16,FLEN)
NAN_BOXED(15662,16,FLEN)
NAN_BOXED(30547,16,FLEN)
NAN_BOXED(30120,16,FLEN)
NAN_BOXED(15662,16,FLEN)
NAN_BOXED(30547,16,FLEN)
NAN_BOXED(30120,16,FLEN)
NAN_BOXED(15662,16,FLEN)
NAN_BOXED(30547,16,FLEN)
NAN_BOXED(30120,16,FLEN)
NAN_BOXED(15662,16,FLEN)
NAN_BOXED(30547,16,FLEN)
NAN_BOXED(30120,16,FLEN)
NAN_BOXED(15662,16,FLEN)
NAN_BOXED(30547,16,FLEN)
NAN_BOXED(30890,16,FLEN)
NAN_BOXED(15923,16,FLEN)
NAN_BOXED(31547,16,FLEN)
NAN_BOXED(30890,16,FLEN)
NAN_BOXED(15923,16,FLEN)
NAN_BOXED(31547,16,FLEN)
NAN_BOXED(30890,16,FLEN)
NAN_BOXED(15923,16,FLEN)
NAN_BOXED(31547,16,FLEN)
NAN_BOXED(30890,16,FLEN)
NAN_BOXED(15923,16,FLEN)
NAN_BOXED(31547,16,FLEN)
NAN_BOXED(30890,16,FLEN)
NAN_BOXED(15923,16,FLEN)
NAN_BOXED(31547,16,FLEN)
NAN_BOXED(30394,16,FLEN)
NAN_BOXED(16477,16,FLEN)
NAN_BOXED(31574,16,FLEN)
NAN_BOXED(30394,16,FLEN)
NAN_BOXED(16477,16,FLEN)
NAN_BOXED(31574,16,FLEN)
NAN_BOXED(30394,16,FLEN)
NAN_BOXED(16477,16,FLEN)
NAN_BOXED(31574,16,FLEN)
NAN_BOXED(30394,16,FLEN)
NAN_BOXED(16477,16,FLEN)
NAN_BOXED(31574,16,FLEN)
NAN_BOXED(30394,16,FLEN)
NAN_BOXED(16477,16,FLEN)
NAN_BOXED(31574,16,FLEN)
NAN_BOXED(30722,16,FLEN)
NAN_BOXED(15421,16,FLEN)
NAN_BOXED(30784,16,FLEN)
NAN_BOXED(30722,16,FLEN)
NAN_BOXED(15421,16,FLEN)
NAN_BOXED(30784,16,FLEN)
NAN_BOXED(30722,16,FLEN)
NAN_BOXED(15421,16,FLEN)
NAN_BOXED(30784,16,FLEN)
NAN_BOXED(30722,16,FLEN)
NAN_BOXED(15421,16,FLEN)
NAN_BOXED(30784,16,FLEN)
NAN_BOXED(30722,16,FLEN)
NAN_BOXED(15421,16,FLEN)
NAN_BOXED(30784,16,FLEN)
NAN_BOXED(30767,16,FLEN)
NAN_BOXED(10387,16,FLEN)
NAN_BOXED(25802,16,FLEN)
NAN_BOXED(30767,16,FLEN)
NAN_BOXED(10387,16,FLEN)
NAN_BOXED(25802,16,FLEN)
NAN_BOXED(30767,16,FLEN)
NAN_BOXED(10387,16,FLEN)
NAN_BOXED(25802,16,FLEN)
NAN_BOXED(30767,16,FLEN)
NAN_BOXED(10387,16,FLEN)
NAN_BOXED(25802,16,FLEN)
NAN_BOXED(30767,16,FLEN)
NAN_BOXED(10387,16,FLEN)
NAN_BOXED(25802,16,FLEN)
NAN_BOXED(30473,16,FLEN)
NAN_BOXED(13992,16,FLEN)
NAN_BOXED(29147,16,FLEN)
NAN_BOXED(30473,16,FLEN)
NAN_BOXED(13992,16,FLEN)
NAN_BOXED(29147,16,FLEN)
NAN_BOXED(30473,16,FLEN)
NAN_BOXED(13992,16,FLEN)
NAN_BOXED(29147,16,FLEN)
NAN_BOXED(30473,16,FLEN)
NAN_BOXED(13992,16,FLEN)
NAN_BOXED(29147,16,FLEN)
NAN_BOXED(30473,16,FLEN)
NAN_BOXED(13992,16,FLEN)
NAN_BOXED(29147,16,FLEN)
NAN_BOXED(23562,16,FLEN)
NAN_BOXED(23123,16,FLEN)
NAN_BOXED(31331,16,FLEN)
NAN_BOXED(23562,16,FLEN)
NAN_BOXED(23123,16,FLEN)
NAN_BOXED(31331,16,FLEN)
NAN_BOXED(23562,16,FLEN)
NAN_BOXED(23123,16,FLEN)
NAN_BOXED(31331,16,FLEN)
NAN_BOXED(23562,16,FLEN)
NAN_BOXED(23123,16,FLEN)
NAN_BOXED(31331,16,FLEN)
NAN_BOXED(23562,16,FLEN)
NAN_BOXED(23123,16,FLEN)
NAN_BOXED(31331,16,FLEN)
NAN_BOXED(29059,16,FLEN)
NAN_BOXED(16766,16,FLEN)
NAN_BOXED(30610,16,FLEN)
NAN_BOXED(29059,16,FLEN)
NAN_BOXED(16766,16,FLEN)
NAN_BOXED(30610,16,FLEN)
NAN_BOXED(29059,16,FLEN)
NAN_BOXED(16766,16,FLEN)
NAN_BOXED(30610,16,FLEN)
NAN_BOXED(29059,16,FLEN)
NAN_BOXED(16766,16,FLEN)
NAN_BOXED(30610,16,FLEN)
NAN_BOXED(29059,16,FLEN)
NAN_BOXED(16766,16,FLEN)
NAN_BOXED(30610,16,FLEN)
NAN_BOXED(31180,16,FLEN)
NAN_BOXED(14883,16,FLEN)
NAN_BOXED(30835,16,FLEN)
NAN_BOXED(31180,16,FLEN)
NAN_BOXED(14883,16,FLEN)
NAN_BOXED(30835,16,FLEN)
NAN_BOXED(31180,16,FLEN)
NAN_BOXED(14883,16,FLEN)
NAN_BOXED(30835,16,FLEN)
NAN_BOXED(31180,16,FLEN)
NAN_BOXED(14883,16,FLEN)
NAN_BOXED(30835,16,FLEN)
NAN_BOXED(31180,16,FLEN)
NAN_BOXED(14883,16,FLEN)
NAN_BOXED(30835,16,FLEN)
NAN_BOXED(30006,16,FLEN)
NAN_BOXED(15964,16,FLEN)
NAN_BOXED(30757,16,FLEN)
NAN_BOXED(30006,16,FLEN)
NAN_BOXED(15964,16,FLEN)
NAN_BOXED(30757,16,FLEN)
NAN_BOXED(30006,16,FLEN)
NAN_BOXED(15964,16,FLEN)
NAN_BOXED(30757,16,FLEN)
NAN_BOXED(30006,16,FLEN)
NAN_BOXED(15964,16,FLEN)
NAN_BOXED(30757,16,FLEN)
NAN_BOXED(30006,16,FLEN)
NAN_BOXED(15964,16,FLEN)
NAN_BOXED(30757,16,FLEN)
NAN_BOXED(30833,16,FLEN)
NAN_BOXED(15781,16,FLEN)
NAN_BOXED(31301,16,FLEN)
NAN_BOXED(30833,16,FLEN)
NAN_BOXED(15781,16,FLEN)
NAN_BOXED(31301,16,FLEN)
NAN_BOXED(30833,16,FLEN)
NAN_BOXED(15781,16,FLEN)
NAN_BOXED(31301,16,FLEN)
NAN_BOXED(30833,16,FLEN)
NAN_BOXED(15781,16,FLEN)
NAN_BOXED(31301,16,FLEN)
NAN_BOXED(30833,16,FLEN)
NAN_BOXED(15781,16,FLEN)
NAN_BOXED(31301,16,FLEN)
NAN_BOXED(28361,16,FLEN)
NAN_BOXED(17735,16,FLEN)
NAN_BOXED(30842,16,FLEN)
NAN_BOXED(28361,16,FLEN)
NAN_BOXED(17735,16,FLEN)
NAN_BOXED(30842,16,FLEN)
NAN_BOXED(28361,16,FLEN)
NAN_BOXED(17735,16,FLEN)
NAN_BOXED(30842,16,FLEN)
NAN_BOXED(28361,16,FLEN)
NAN_BOXED(17735,16,FLEN)
NAN_BOXED(30842,16,FLEN)
NAN_BOXED(28361,16,FLEN)
NAN_BOXED(17735,16,FLEN)
NAN_BOXED(30842,16,FLEN)
NAN_BOXED(29682,16,FLEN)
NAN_BOXED(15477,16,FLEN)
NAN_BOXED(29805,16,FLEN)
NAN_BOXED(29682,16,FLEN)
NAN_BOXED(15477,16,FLEN)
NAN_BOXED(29805,16,FLEN)
NAN_BOXED(29682,16,FLEN)
NAN_BOXED(15477,16,FLEN)
NAN_BOXED(29805,16,FLEN)
NAN_BOXED(29682,16,FLEN)
NAN_BOXED(15477,16,FLEN)
NAN_BOXED(29805,16,FLEN)
NAN_BOXED(29682,16,FLEN)
NAN_BOXED(15477,16,FLEN)
NAN_BOXED(29805,16,FLEN)
NAN_BOXED(31276,16,FLEN)
NAN_BOXED(14658,16,FLEN)
NAN_BOXED(30735,16,FLEN)
NAN_BOXED(31276,16,FLEN)
NAN_BOXED(14658,16,FLEN)
NAN_BOXED(30735,16,FLEN)
NAN_BOXED(31276,16,FLEN)
NAN_BOXED(14658,16,FLEN)
NAN_BOXED(30735,16,FLEN)
NAN_BOXED(31276,16,FLEN)
NAN_BOXED(14658,16,FLEN)
NAN_BOXED(30735,16,FLEN)
NAN_BOXED(31276,16,FLEN)
NAN_BOXED(14658,16,FLEN)
NAN_BOXED(30735,16,FLEN)
NAN_BOXED(30845,16,FLEN)
NAN_BOXED(15721,16,FLEN)
NAN_BOXED(31251,16,FLEN)
NAN_BOXED(30845,16,FLEN)
NAN_BOXED(15721,16,FLEN)
NAN_BOXED(31251,16,FLEN)
NAN_BOXED(30845,16,FLEN)
NAN_BOXED(15721,16,FLEN)
NAN_BOXED(31251,16,FLEN)
NAN_BOXED(30845,16,FLEN)
NAN_BOXED(15721,16,FLEN)
NAN_BOXED(31251,16,FLEN)
NAN_BOXED(30845,16,FLEN)
NAN_BOXED(15721,16,FLEN)
NAN_BOXED(31251,16,FLEN)
NAN_BOXED(31563,16,FLEN)
NAN_BOXED(14277,16,FLEN)
NAN_BOXED(30486,16,FLEN)
NAN_BOXED(31563,16,FLEN)
NAN_BOXED(14277,16,FLEN)
NAN_BOXED(30486,16,FLEN)
NAN_BOXED(31563,16,FLEN)
NAN_BOXED(14277,16,FLEN)
NAN_BOXED(30486,16,FLEN)
NAN_BOXED(31563,16,FLEN)
NAN_BOXED(14277,16,FLEN)
NAN_BOXED(30486,16,FLEN)
NAN_BOXED(31563,16,FLEN)
NAN_BOXED(14277,16,FLEN)
NAN_BOXED(30486,16,FLEN)
NAN_BOXED(30949,16,FLEN)
NAN_BOXED(15002,16,FLEN)
NAN_BOXED(30730,16,FLEN)
NAN_BOXED(30949,16,FLEN)
NAN_BOXED(15002,16,FLEN)
NAN_BOXED(30730,16,FLEN)
NAN_BOXED(30949,16,FLEN)
NAN_BOXED(15002,16,FLEN)
NAN_BOXED(30730,16,FLEN)
NAN_BOXED(30949,16,FLEN)
NAN_BOXED(15002,16,FLEN)
NAN_BOXED(30730,16,FLEN)
NAN_BOXED(30949,16,FLEN)
NAN_BOXED(15002,16,FLEN)
NAN_BOXED(30730,16,FLEN)
NAN_BOXED(30744,16,FLEN)
NAN_BOXED(15721,16,FLEN)
NAN_BOXED(31114,16,FLEN)
NAN_BOXED(30744,16,FLEN)
NAN_BOXED(15721,16,FLEN)
NAN_BOXED(31114,16,FLEN)
NAN_BOXED(30744,16,FLEN)
NAN_BOXED(15721,16,FLEN)
NAN_BOXED(31114,16,FLEN)
NAN_BOXED(30744,16,FLEN)
NAN_BOXED(15721,16,FLEN)
NAN_BOXED(31114,16,FLEN)
NAN_BOXED(30744,16,FLEN)
NAN_BOXED(15721,16,FLEN)
NAN_BOXED(31114,16,FLEN)
NAN_BOXED(30523,16,FLEN)
NAN_BOXED(15543,16,FLEN)
NAN_BOXED(30787,16,FLEN)
NAN_BOXED(30523,16,FLEN)
NAN_BOXED(15543,16,FLEN)
NAN_BOXED(30787,16,FLEN)
NAN_BOXED(30523,16,FLEN)
NAN_BOXED(15543,16,FLEN)
NAN_BOXED(30787,16,FLEN)
NAN_BOXED(30523,16,FLEN)
NAN_BOXED(15543,16,FLEN)
NAN_BOXED(30787,16,FLEN)
NAN_BOXED(30523,16,FLEN)
NAN_BOXED(15543,16,FLEN)
NAN_BOXED(30787,16,FLEN)
NAN_BOXED(30629,16,FLEN)
NAN_BOXED(16352,16,FLEN)
NAN_BOXED(31623,16,FLEN)
NAN_BOXED(30629,16,FLEN)
NAN_BOXED(16352,16,FLEN)
NAN_BOXED(31623,16,FLEN)
NAN_BOXED(30629,16,FLEN)
NAN_BOXED(16352,16,FLEN)
NAN_BOXED(31623,16,FLEN)
NAN_BOXED(30629,16,FLEN)
NAN_BOXED(16352,16,FLEN)
NAN_BOXED(31623,16,FLEN)
NAN_BOXED(30629,16,FLEN)
NAN_BOXED(16352,16,FLEN)
NAN_BOXED(31623,16,FLEN)
NAN_BOXED(31127,16,FLEN)
NAN_BOXED(15619,16,FLEN)
NAN_BOXED(31490,16,FLEN)
NAN_BOXED(31127,16,FLEN)
NAN_BOXED(15619,16,FLEN)
NAN_BOXED(31490,16,FLEN)
NAN_BOXED(31127,16,FLEN)
NAN_BOXED(15619,16,FLEN)
NAN_BOXED(31490,16,FLEN)
NAN_BOXED(31127,16,FLEN)
NAN_BOXED(15619,16,FLEN)
NAN_BOXED(31490,16,FLEN)
NAN_BOXED(31127,16,FLEN)
NAN_BOXED(15619,16,FLEN)
NAN_BOXED(31490,16,FLEN)
NAN_BOXED(31624,16,FLEN)
NAN_BOXED(13416,16,FLEN)
NAN_BOXED(29734,16,FLEN)
NAN_BOXED(31624,16,FLEN)
NAN_BOXED(13416,16,FLEN)
NAN_BOXED(29734,16,FLEN)
NAN_BOXED(31624,16,FLEN)
NAN_BOXED(13416,16,FLEN)
NAN_BOXED(29734,16,FLEN)
NAN_BOXED(31624,16,FLEN)
NAN_BOXED(13416,16,FLEN)
NAN_BOXED(29734,16,FLEN)
NAN_BOXED(31624,16,FLEN)
NAN_BOXED(13416,16,FLEN)
NAN_BOXED(29734,16,FLEN)
NAN_BOXED(30841,16,FLEN)
NAN_BOXED(16062,16,FLEN)
NAN_BOXED(31626,16,FLEN)
NAN_BOXED(30841,16,FLEN)
NAN_BOXED(16062,16,FLEN)
NAN_BOXED(31626,16,FLEN)
NAN_BOXED(30841,16,FLEN)
NAN_BOXED(16062,16,FLEN)
NAN_BOXED(31626,16,FLEN)
NAN_BOXED(30841,16,FLEN)
NAN_BOXED(16062,16,FLEN)
NAN_BOXED(31626,16,FLEN)
NAN_BOXED(30841,16,FLEN)
NAN_BOXED(16062,16,FLEN)
NAN_BOXED(31626,16,FLEN)
NAN_BOXED(31415,16,FLEN)
NAN_BOXED(12601,16,FLEN)
NAN_BOXED(28770,16,FLEN)
NAN_BOXED(31415,16,FLEN)
NAN_BOXED(12601,16,FLEN)
NAN_BOXED(28770,16,FLEN)
NAN_BOXED(31415,16,FLEN)
NAN_BOXED(12601,16,FLEN)
NAN_BOXED(28770,16,FLEN)
NAN_BOXED(31415,16,FLEN)
NAN_BOXED(12601,16,FLEN)
NAN_BOXED(28770,16,FLEN)
NAN_BOXED(31415,16,FLEN)
NAN_BOXED(12601,16,FLEN)
NAN_BOXED(28770,16,FLEN)
NAN_BOXED(28615,16,FLEN)
NAN_BOXED(17221,16,FLEN)
NAN_BOXED(30482,16,FLEN)
NAN_BOXED(28615,16,FLEN)
NAN_BOXED(17221,16,FLEN)
NAN_BOXED(30482,16,FLEN)
NAN_BOXED(28615,16,FLEN)
NAN_BOXED(17221,16,FLEN)
NAN_BOXED(30482,16,FLEN)
NAN_BOXED(28615,16,FLEN)
NAN_BOXED(17221,16,FLEN)
NAN_BOXED(30482,16,FLEN)
NAN_BOXED(28615,16,FLEN)
NAN_BOXED(17221,16,FLEN)
NAN_BOXED(30482,16,FLEN)
NAN_BOXED(27812,16,FLEN)
NAN_BOXED(17058,16,FLEN)
NAN_BOXED(29618,16,FLEN)
NAN_BOXED(27812,16,FLEN)
NAN_BOXED(17058,16,FLEN)
NAN_BOXED(29618,16,FLEN)
NAN_BOXED(27812,16,FLEN)
NAN_BOXED(17058,16,FLEN)
NAN_BOXED(29618,16,FLEN)
NAN_BOXED(27812,16,FLEN)
NAN_BOXED(17058,16,FLEN)
NAN_BOXED(29618,16,FLEN)
NAN_BOXED(27812,16,FLEN)
NAN_BOXED(17058,16,FLEN)
NAN_BOXED(29618,16,FLEN)
NAN_BOXED(27821,16,FLEN)
NAN_BOXED(18579,16,FLEN)
NAN_BOXED(31066,16,FLEN)
NAN_BOXED(27821,16,FLEN)
NAN_BOXED(18579,16,FLEN)
NAN_BOXED(31066,16,FLEN)
NAN_BOXED(27821,16,FLEN)
NAN_BOXED(18579,16,FLEN)
NAN_BOXED(31066,16,FLEN)
NAN_BOXED(27821,16,FLEN)
NAN_BOXED(18579,16,FLEN)
NAN_BOXED(31066,16,FLEN)
NAN_BOXED(27821,16,FLEN)
NAN_BOXED(18579,16,FLEN)
NAN_BOXED(31066,16,FLEN)
NAN_BOXED(31300,16,FLEN)
NAN_BOXED(15507,16,FLEN)
NAN_BOXED(31532,16,FLEN)
NAN_BOXED(31300,16,FLEN)
NAN_BOXED(15507,16,FLEN)
NAN_BOXED(31532,16,FLEN)
NAN_BOXED(31300,16,FLEN)
NAN_BOXED(15507,16,FLEN)
NAN_BOXED(31532,16,FLEN)
NAN_BOXED(31300,16,FLEN)
NAN_BOXED(15507,16,FLEN)
NAN_BOXED(31532,16,FLEN)
NAN_BOXED(31300,16,FLEN)
NAN_BOXED(15507,16,FLEN)
NAN_BOXED(31532,16,FLEN)
NAN_BOXED(28912,16,FLEN)
NAN_BOXED(17570,16,FLEN)
NAN_BOXED(31161,16,FLEN)
NAN_BOXED(28912,16,FLEN)
NAN_BOXED(17570,16,FLEN)
NAN_BOXED(31161,16,FLEN)
NAN_BOXED(28912,16,FLEN)
NAN_BOXED(17570,16,FLEN)
NAN_BOXED(31161,16,FLEN)
NAN_BOXED(28912,16,FLEN)
NAN_BOXED(17570,16,FLEN)
NAN_BOXED(31161,16,FLEN)
NAN_BOXED(28912,16,FLEN)
NAN_BOXED(17570,16,FLEN)
NAN_BOXED(31161,16,FLEN)
NAN_BOXED(31047,16,FLEN)
NAN_BOXED(13038,16,FLEN)
NAN_BOXED(28818,16,FLEN)
NAN_BOXED(31047,16,FLEN)
NAN_BOXED(13038,16,FLEN)
NAN_BOXED(28818,16,FLEN)
NAN_BOXED(31047,16,FLEN)
NAN_BOXED(13038,16,FLEN)
NAN_BOXED(28818,16,FLEN)
NAN_BOXED(31047,16,FLEN)
NAN_BOXED(13038,16,FLEN)
NAN_BOXED(28818,16,FLEN)
NAN_BOXED(31047,16,FLEN)
NAN_BOXED(13038,16,FLEN)
NAN_BOXED(28818,16,FLEN)
NAN_BOXED(31503,16,FLEN)
NAN_BOXED(15458,16,FLEN)
NAN_BOXED(31676,16,FLEN)
NAN_BOXED(31503,16,FLEN)
NAN_BOXED(15458,16,FLEN)
NAN_BOXED(31676,16,FLEN)
NAN_BOXED(31503,16,FLEN)
NAN_BOXED(15458,16,FLEN)
NAN_BOXED(31676,16,FLEN)
NAN_BOXED(31503,16,FLEN)
NAN_BOXED(15458,16,FLEN)
NAN_BOXED(31676,16,FLEN)
NAN_BOXED(31503,16,FLEN)
NAN_BOXED(15458,16,FLEN)
NAN_BOXED(31676,16,FLEN)
NAN_BOXED(29446,16,FLEN)
NAN_BOXED(17494,16,FLEN)
NAN_BOXED(31645,16,FLEN)
NAN_BOXED(29446,16,FLEN)
NAN_BOXED(17494,16,FLEN)
NAN_BOXED(31645,16,FLEN)
NAN_BOXED(29446,16,FLEN)
NAN_BOXED(17494,16,FLEN)
NAN_BOXED(31645,16,FLEN)
NAN_BOXED(29446,16,FLEN)
NAN_BOXED(17494,16,FLEN)
NAN_BOXED(31645,16,FLEN)
NAN_BOXED(29446,16,FLEN)
NAN_BOXED(17494,16,FLEN)
NAN_BOXED(31645,16,FLEN)
NAN_BOXED(30302,16,FLEN)
NAN_BOXED(15588,16,FLEN)
NAN_BOXED(30666,16,FLEN)
NAN_BOXED(30302,16,FLEN)
NAN_BOXED(15588,16,FLEN)
NAN_BOXED(30666,16,FLEN)
NAN_BOXED(30302,16,FLEN)
NAN_BOXED(15588,16,FLEN)
NAN_BOXED(30666,16,FLEN)
NAN_BOXED(30302,16,FLEN)
NAN_BOXED(15588,16,FLEN)
NAN_BOXED(30666,16,FLEN)
NAN_BOXED(30302,16,FLEN)
NAN_BOXED(15588,16,FLEN)
NAN_BOXED(30666,16,FLEN)
NAN_BOXED(31722,16,FLEN)
NAN_BOXED(15034,16,FLEN)
NAN_BOXED(31400,16,FLEN)
NAN_BOXED(31722,16,FLEN)
NAN_BOXED(15034,16,FLEN)
NAN_BOXED(31400,16,FLEN)
NAN_BOXED(31722,16,FLEN)
NAN_BOXED(15034,16,FLEN)
NAN_BOXED(31400,16,FLEN)
NAN_BOXED(31722,16,FLEN)
NAN_BOXED(15034,16,FLEN)
NAN_BOXED(31400,16,FLEN)
NAN_BOXED(31722,16,FLEN)
NAN_BOXED(15034,16,FLEN)
NAN_BOXED(31400,16,FLEN)
NAN_BOXED(28970,16,FLEN)
NAN_BOXED(16728,16,FLEN)
NAN_BOXED(30438,16,FLEN)
NAN_BOXED(28970,16,FLEN)
NAN_BOXED(16728,16,FLEN)
NAN_BOXED(30438,16,FLEN)
NAN_BOXED(28970,16,FLEN)
NAN_BOXED(16728,16,FLEN)
NAN_BOXED(30438,16,FLEN)
NAN_BOXED(28970,16,FLEN)
NAN_BOXED(16728,16,FLEN)
NAN_BOXED(30438,16,FLEN)
NAN_BOXED(28970,16,FLEN)
NAN_BOXED(16728,16,FLEN)
NAN_BOXED(30438,16,FLEN)
NAN_BOXED(30751,16,FLEN)
NAN_BOXED(14659,16,FLEN)
NAN_BOXED(30060,16,FLEN)
NAN_BOXED(30751,16,FLEN)
NAN_BOXED(14659,16,FLEN)
NAN_BOXED(30060,16,FLEN)
NAN_BOXED(30751,16,FLEN)
NAN_BOXED(14659,16,FLEN)
NAN_BOXED(30060,16,FLEN)
NAN_BOXED(30751,16,FLEN)
NAN_BOXED(14659,16,FLEN)
NAN_BOXED(30060,16,FLEN)
NAN_BOXED(30751,16,FLEN)
NAN_BOXED(14659,16,FLEN)
NAN_BOXED(30060,16,FLEN)
NAN_BOXED(29250,16,FLEN)
NAN_BOXED(16002,16,FLEN)
NAN_BOXED(29976,16,FLEN)
NAN_BOXED(29250,16,FLEN)
NAN_BOXED(16002,16,FLEN)
NAN_BOXED(29976,16,FLEN)
NAN_BOXED(29250,16,FLEN)
NAN_BOXED(16002,16,FLEN)
NAN_BOXED(29976,16,FLEN)
NAN_BOXED(29250,16,FLEN)
NAN_BOXED(16002,16,FLEN)
NAN_BOXED(29976,16,FLEN)
NAN_BOXED(29250,16,FLEN)
NAN_BOXED(16002,16,FLEN)
NAN_BOXED(29976,16,FLEN)
NAN_BOXED(31174,16,FLEN)
NAN_BOXED(9961,16,FLEN)
NAN_BOXED(25853,16,FLEN)
NAN_BOXED(31174,16,FLEN)
NAN_BOXED(9961,16,FLEN)
NAN_BOXED(25853,16,FLEN)
NAN_BOXED(31174,16,FLEN)
NAN_BOXED(9961,16,FLEN)
NAN_BOXED(25853,16,FLEN)
NAN_BOXED(31174,16,FLEN)
NAN_BOXED(9961,16,FLEN)
NAN_BOXED(25853,16,FLEN)
NAN_BOXED(31174,16,FLEN)
NAN_BOXED(9961,16,FLEN)
NAN_BOXED(25853,16,FLEN)
NAN_BOXED(30830,16,FLEN)
NAN_BOXED(14940,16,FLEN)
NAN_BOXED(30475,16,FLEN)
NAN_BOXED(30830,16,FLEN)
NAN_BOXED(14940,16,FLEN)
NAN_BOXED(30475,16,FLEN)
NAN_BOXED(30830,16,FLEN)
NAN_BOXED(14940,16,FLEN)
NAN_BOXED(30475,16,FLEN)
NAN_BOXED(30830,16,FLEN)
NAN_BOXED(14940,16,FLEN)
NAN_BOXED(30475,16,FLEN)
NAN_BOXED(30830,16,FLEN)
NAN_BOXED(14940,16,FLEN)
NAN_BOXED(30475,16,FLEN)
NAN_BOXED(25761,16,FLEN)
NAN_BOXED(19604,16,FLEN)
NAN_BOXED(30029,16,FLEN)
NAN_BOXED(25761,16,FLEN)
NAN_BOXED(19604,16,FLEN)
NAN_BOXED(30029,16,FLEN)
NAN_BOXED(25761,16,FLEN)
NAN_BOXED(19604,16,FLEN)
NAN_BOXED(30029,16,FLEN)
NAN_BOXED(25761,16,FLEN)
NAN_BOXED(19604,16,FLEN)
NAN_BOXED(30029,16,FLEN)
NAN_BOXED(25761,16,FLEN)
NAN_BOXED(19604,16,FLEN)
NAN_BOXED(30029,16,FLEN)
NAN_BOXED(30973,16,FLEN)
NAN_BOXED(14993,16,FLEN)
NAN_BOXED(30744,16,FLEN)
NAN_BOXED(30973,16,FLEN)
NAN_BOXED(14993,16,FLEN)
NAN_BOXED(30744,16,FLEN)
NAN_BOXED(30973,16,FLEN)
NAN_BOXED(14993,16,FLEN)
NAN_BOXED(30744,16,FLEN)
NAN_BOXED(30973,16,FLEN)
NAN_BOXED(14993,16,FLEN)
NAN_BOXED(30744,16,FLEN)
NAN_BOXED(30973,16,FLEN)
NAN_BOXED(14993,16,FLEN)
NAN_BOXED(30744,16,FLEN)
NAN_BOXED(27677,16,FLEN)
NAN_BOXED(19368,16,FLEN)
NAN_BOXED(31712,16,FLEN)
NAN_BOXED(27677,16,FLEN)
NAN_BOXED(19368,16,FLEN)
NAN_BOXED(31712,16,FLEN)
NAN_BOXED(27677,16,FLEN)
NAN_BOXED(19368,16,FLEN)
NAN_BOXED(31712,16,FLEN)
NAN_BOXED(27677,16,FLEN)
NAN_BOXED(19368,16,FLEN)
NAN_BOXED(31712,16,FLEN)
NAN_BOXED(27677,16,FLEN)
NAN_BOXED(19368,16,FLEN)
NAN_BOXED(31712,16,FLEN)
NAN_BOXED(31309,16,FLEN)
NAN_BOXED(15598,16,FLEN)
NAN_BOXED(31685,16,FLEN)
NAN_BOXED(31309,16,FLEN)
NAN_BOXED(15598,16,FLEN)
NAN_BOXED(31685,16,FLEN)
NAN_BOXED(31309,16,FLEN)
NAN_BOXED(15598,16,FLEN)
NAN_BOXED(31685,16,FLEN)
NAN_BOXED(31309,16,FLEN)
NAN_BOXED(15598,16,FLEN)
NAN_BOXED(31685,16,FLEN)
NAN_BOXED(31309,16,FLEN)
NAN_BOXED(15598,16,FLEN)
NAN_BOXED(31685,16,FLEN)
NAN_BOXED(28340,16,FLEN)
NAN_BOXED(16657,16,FLEN)
NAN_BOXED(29759,16,FLEN)
NAN_BOXED(28340,16,FLEN)
NAN_BOXED(16657,16,FLEN)
NAN_BOXED(29759,16,FLEN)
NAN_BOXED(28340,16,FLEN)
NAN_BOXED(16657,16,FLEN)
NAN_BOXED(29759,16,FLEN)
NAN_BOXED(28340,16,FLEN)
NAN_BOXED(16657,16,FLEN)
NAN_BOXED(29759,16,FLEN)
NAN_BOXED(28340,16,FLEN)
NAN_BOXED(16657,16,FLEN)
NAN_BOXED(29759,16,FLEN)
NAN_BOXED(26897,16,FLEN)
NAN_BOXED(19690,16,FLEN)
NAN_BOXED(31290,16,FLEN)
NAN_BOXED(26897,16,FLEN)
NAN_BOXED(19690,16,FLEN)
NAN_BOXED(31290,16,FLEN)
NAN_BOXED(26897,16,FLEN)
NAN_BOXED(19690,16,FLEN)
NAN_BOXED(31290,16,FLEN)
NAN_BOXED(26897,16,FLEN)
NAN_BOXED(19690,16,FLEN)
NAN_BOXED(31290,16,FLEN)
NAN_BOXED(26897,16,FLEN)
NAN_BOXED(19690,16,FLEN)
NAN_BOXED(31290,16,FLEN)
NAN_BOXED(29779,16,FLEN)
NAN_BOXED(14250,16,FLEN)
NAN_BOXED(28708,16,FLEN)
NAN_BOXED(29779,16,FLEN)
NAN_BOXED(14250,16,FLEN)
NAN_BOXED(28708,16,FLEN)
NAN_BOXED(29779,16,FLEN)
NAN_BOXED(14250,16,FLEN)
NAN_BOXED(28708,16,FLEN)
NAN_BOXED(29779,16,FLEN)
NAN_BOXED(14250,16,FLEN)
NAN_BOXED(28708,16,FLEN)
NAN_BOXED(29779,16,FLEN)
NAN_BOXED(14250,16,FLEN)
NAN_BOXED(28708,16,FLEN)
NAN_BOXED(30400,16,FLEN)
NAN_BOXED(16466,16,FLEN)
NAN_BOXED(31561,16,FLEN)
NAN_BOXED(30400,16,FLEN)
NAN_BOXED(16466,16,FLEN)
NAN_BOXED(31561,16,FLEN)
NAN_BOXED(30400,16,FLEN)
NAN_BOXED(16466,16,FLEN)
NAN_BOXED(31561,16,FLEN)
NAN_BOXED(30400,16,FLEN)
NAN_BOXED(16466,16,FLEN)
NAN_BOXED(31561,16,FLEN)
NAN_BOXED(30400,16,FLEN)
NAN_BOXED(16466,16,FLEN)
NAN_BOXED(31561,16,FLEN)
NAN_BOXED(31372,16,FLEN)
NAN_BOXED(13586,16,FLEN)
NAN_BOXED(29730,16,FLEN)
NAN_BOXED(31372,16,FLEN)
NAN_BOXED(13586,16,FLEN)
NAN_BOXED(29730,16,FLEN)
NAN_BOXED(31372,16,FLEN)
NAN_BOXED(13586,16,FLEN)
NAN_BOXED(29730,16,FLEN)
NAN_BOXED(31372,16,FLEN)
NAN_BOXED(13586,16,FLEN)
NAN_BOXED(29730,16,FLEN)
NAN_BOXED(31372,16,FLEN)
NAN_BOXED(13586,16,FLEN)
NAN_BOXED(29730,16,FLEN)
NAN_BOXED(28871,16,FLEN)
NAN_BOXED(17960,16,FLEN)
NAN_BOXED(31577,16,FLEN)
NAN_BOXED(28871,16,FLEN)
NAN_BOXED(17960,16,FLEN)
NAN_BOXED(31577,16,FLEN)
NAN_BOXED(28871,16,FLEN)
NAN_BOXED(17960,16,FLEN)
NAN_BOXED(31577,16,FLEN)
NAN_BOXED(28871,16,FLEN)
NAN_BOXED(17960,16,FLEN)
NAN_BOXED(31577,16,FLEN)
NAN_BOXED(28871,16,FLEN)
NAN_BOXED(17960,16,FLEN)
NAN_BOXED(31577,16,FLEN)
NAN_BOXED(30864,16,FLEN)
NAN_BOXED(15594,16,FLEN)
NAN_BOXED(31129,16,FLEN)
NAN_BOXED(30864,16,FLEN)
NAN_BOXED(15594,16,FLEN)
NAN_BOXED(31129,16,FLEN)
NAN_BOXED(30864,16,FLEN)
NAN_BOXED(15594,16,FLEN)
NAN_BOXED(31129,16,FLEN)
NAN_BOXED(30864,16,FLEN)
NAN_BOXED(15594,16,FLEN)
NAN_BOXED(31129,16,FLEN)
NAN_BOXED(30864,16,FLEN)
NAN_BOXED(15594,16,FLEN)
NAN_BOXED(31129,16,FLEN)
NAN_BOXED(28089,16,FLEN)
NAN_BOXED(14651,16,FLEN)
NAN_BOXED(27484,16,FLEN)
NAN_BOXED(28089,16,FLEN)
NAN_BOXED(14651,16,FLEN)
NAN_BOXED(27484,16,FLEN)
NAN_BOXED(28089,16,FLEN)
NAN_BOXED(14651,16,FLEN)
NAN_BOXED(27484,16,FLEN)
NAN_BOXED(28089,16,FLEN)
NAN_BOXED(14651,16,FLEN)
NAN_BOXED(27484,16,FLEN)
NAN_BOXED(28089,16,FLEN)
NAN_BOXED(14651,16,FLEN)
NAN_BOXED(27484,16,FLEN)
NAN_BOXED(31104,16,FLEN)
NAN_BOXED(14580,16,FLEN)
NAN_BOXED(30413,16,FLEN)
NAN_BOXED(31104,16,FLEN)
NAN_BOXED(14580,16,FLEN)
NAN_BOXED(30413,16,FLEN)
NAN_BOXED(31104,16,FLEN)
NAN_BOXED(14580,16,FLEN)
NAN_BOXED(30413,16,FLEN)
NAN_BOXED(31104,16,FLEN)
NAN_BOXED(14580,16,FLEN)
NAN_BOXED(30413,16,FLEN)
NAN_BOXED(31104,16,FLEN)
NAN_BOXED(14580,16,FLEN)
NAN_BOXED(30413,16,FLEN)
NAN_BOXED(27810,16,FLEN)
NAN_BOXED(19068,16,FLEN)
NAN_BOXED(31616,16,FLEN)
NAN_BOXED(27810,16,FLEN)
NAN_BOXED(19068,16,FLEN)
NAN_BOXED(31616,16,FLEN)
NAN_BOXED(27810,16,FLEN)
NAN_BOXED(19068,16,FLEN)
NAN_BOXED(31616,16,FLEN)
NAN_BOXED(27810,16,FLEN)
NAN_BOXED(19068,16,FLEN)
NAN_BOXED(31616,16,FLEN)
NAN_BOXED(27810,16,FLEN)
NAN_BOXED(19068,16,FLEN)
NAN_BOXED(31616,16,FLEN)
NAN_BOXED(30994,16,FLEN)
NAN_BOXED(15628,16,FLEN)
NAN_BOXED(31336,16,FLEN)
NAN_BOXED(30994,16,FLEN)
NAN_BOXED(15628,16,FLEN)
NAN_BOXED(31336,16,FLEN)
NAN_BOXED(30994,16,FLEN)
NAN_BOXED(15628,16,FLEN)
NAN_BOXED(31336,16,FLEN)
NAN_BOXED(30994,16,FLEN)
NAN_BOXED(15628,16,FLEN)
NAN_BOXED(31336,16,FLEN)
NAN_BOXED(30994,16,FLEN)
NAN_BOXED(15628,16,FLEN)
NAN_BOXED(31336,16,FLEN)
NAN_BOXED(27995,16,FLEN)
NAN_BOXED(18715,16,FLEN)
NAN_BOXED(31448,16,FLEN)
NAN_BOXED(27995,16,FLEN)
NAN_BOXED(18715,16,FLEN)
NAN_BOXED(31448,16,FLEN)
NAN_BOXED(27995,16,FLEN)
NAN_BOXED(18715,16,FLEN)
NAN_BOXED(31448,16,FLEN)
NAN_BOXED(27995,16,FLEN)
NAN_BOXED(18715,16,FLEN)
NAN_BOXED(31448,16,FLEN)
NAN_BOXED(27995,16,FLEN)
NAN_BOXED(18715,16,FLEN)
NAN_BOXED(31448,16,FLEN)
NAN_BOXED(27715,16,FLEN)
NAN_BOXED(19063,16,FLEN)
NAN_BOXED(31462,16,FLEN)
NAN_BOXED(27715,16,FLEN)
NAN_BOXED(19063,16,FLEN)
NAN_BOXED(31462,16,FLEN)
NAN_BOXED(27715,16,FLEN)
NAN_BOXED(19063,16,FLEN)
NAN_BOXED(31462,16,FLEN)
NAN_BOXED(27715,16,FLEN)
NAN_BOXED(19063,16,FLEN)
NAN_BOXED(31462,16,FLEN)
NAN_BOXED(27715,16,FLEN)
NAN_BOXED(19063,16,FLEN)
NAN_BOXED(31462,16,FLEN)
NAN_BOXED(30529,16,FLEN)
NAN_BOXED(14838,16,FLEN)
NAN_BOXED(30060,16,FLEN)
NAN_BOXED(30529,16,FLEN)
NAN_BOXED(14838,16,FLEN)
NAN_BOXED(30060,16,FLEN)
NAN_BOXED(30529,16,FLEN)
NAN_BOXED(14838,16,FLEN)
NAN_BOXED(30060,16,FLEN)
NAN_BOXED(30529,16,FLEN)
NAN_BOXED(14838,16,FLEN)
NAN_BOXED(30060,16,FLEN)
NAN_BOXED(30529,16,FLEN)
NAN_BOXED(14838,16,FLEN)
NAN_BOXED(30060,16,FLEN)
NAN_BOXED(30828,16,FLEN)
NAN_BOXED(16049,16,FLEN)
NAN_BOXED(31592,16,FLEN)
NAN_BOXED(30828,16,FLEN)
NAN_BOXED(16049,16,FLEN)
NAN_BOXED(31592,16,FLEN)
NAN_BOXED(30828,16,FLEN)
NAN_BOXED(16049,16,FLEN)
NAN_BOXED(31592,16,FLEN)
NAN_BOXED(30828,16,FLEN)
NAN_BOXED(16049,16,FLEN)
NAN_BOXED(31592,16,FLEN)
NAN_BOXED(30828,16,FLEN)
NAN_BOXED(16049,16,FLEN)
NAN_BOXED(31592,16,FLEN)
NAN_BOXED(29768,16,FLEN)
NAN_BOXED(14249,16,FLEN)
NAN_BOXED(28706,16,FLEN)
NAN_BOXED(29768,16,FLEN)
NAN_BOXED(14249,16,FLEN)
NAN_BOXED(28706,16,FLEN)
NAN_BOXED(29768,16,FLEN)
NAN_BOXED(14249,16,FLEN)
NAN_BOXED(28706,16,FLEN)
NAN_BOXED(29768,16,FLEN)
NAN_BOXED(14249,16,FLEN)
NAN_BOXED(28706,16,FLEN)
NAN_BOXED(29768,16,FLEN)
NAN_BOXED(14249,16,FLEN)
NAN_BOXED(28706,16,FLEN)
NAN_BOXED(30774,16,FLEN)
NAN_BOXED(14133,16,FLEN)
NAN_BOXED(29600,16,FLEN)
NAN_BOXED(30774,16,FLEN)
NAN_BOXED(14133,16,FLEN)
NAN_BOXED(29600,16,FLEN)
NAN_BOXED(30774,16,FLEN)
NAN_BOXED(14133,16,FLEN)
NAN_BOXED(29600,16,FLEN)
NAN_BOXED(30774,16,FLEN)
NAN_BOXED(14133,16,FLEN)
NAN_BOXED(29600,16,FLEN)
NAN_BOXED(30774,16,FLEN)
NAN_BOXED(14133,16,FLEN)
NAN_BOXED(29600,16,FLEN)
NAN_BOXED(28416,16,FLEN)
NAN_BOXED(15837,16,FLEN)
NAN_BOXED(28970,16,FLEN)
NAN_BOXED(28416,16,FLEN)
NAN_BOXED(15837,16,FLEN)
NAN_BOXED(28970,16,FLEN)
NAN_BOXED(28416,16,FLEN)
NAN_BOXED(15837,16,FLEN)
NAN_BOXED(28970,16,FLEN)
NAN_BOXED(28416,16,FLEN)
NAN_BOXED(15837,16,FLEN)
NAN_BOXED(28970,16,FLEN)
NAN_BOXED(28416,16,FLEN)
NAN_BOXED(15837,16,FLEN)
NAN_BOXED(28970,16,FLEN)
NAN_BOXED(27250,16,FLEN)
NAN_BOXED(17400,16,FLEN)
NAN_BOXED(29300,16,FLEN)
NAN_BOXED(27250,16,FLEN)
NAN_BOXED(17400,16,FLEN)
NAN_BOXED(29300,16,FLEN)
NAN_BOXED(27250,16,FLEN)
NAN_BOXED(17400,16,FLEN)
NAN_BOXED(29300,16,FLEN)
NAN_BOXED(27250,16,FLEN)
NAN_BOXED(17400,16,FLEN)
NAN_BOXED(29300,16,FLEN)
NAN_BOXED(27250,16,FLEN)
NAN_BOXED(17400,16,FLEN)
NAN_BOXED(29300,16,FLEN)
NAN_BOXED(29949,16,FLEN)
NAN_BOXED(15307,16,FLEN)
NAN_BOXED(29920,16,FLEN)
NAN_BOXED(29949,16,FLEN)
NAN_BOXED(15307,16,FLEN)
NAN_BOXED(29920,16,FLEN)
NAN_BOXED(29949,16,FLEN)
NAN_BOXED(15307,16,FLEN)
NAN_BOXED(29920,16,FLEN)
NAN_BOXED(29949,16,FLEN)
NAN_BOXED(15307,16,FLEN)
NAN_BOXED(29920,16,FLEN)
NAN_BOXED(29949,16,FLEN)
NAN_BOXED(15307,16,FLEN)
NAN_BOXED(29920,16,FLEN)
NAN_BOXED(31250,16,FLEN)
NAN_BOXED(13846,16,FLEN)
NAN_BOXED(29859,16,FLEN)
NAN_BOXED(31250,16,FLEN)
NAN_BOXED(13846,16,FLEN)
NAN_BOXED(29859,16,FLEN)
NAN_BOXED(31250,16,FLEN)
NAN_BOXED(13846,16,FLEN)
NAN_BOXED(29859,16,FLEN)
NAN_BOXED(31250,16,FLEN)
NAN_BOXED(13846,16,FLEN)
NAN_BOXED(29859,16,FLEN)
NAN_BOXED(31250,16,FLEN)
NAN_BOXED(13846,16,FLEN)
NAN_BOXED(29859,16,FLEN)
NAN_BOXED(30719,16,FLEN)
NAN_BOXED(13737,16,FLEN)
NAN_BOXED(29104,16,FLEN)
NAN_BOXED(30719,16,FLEN)
NAN_BOXED(13737,16,FLEN)
NAN_BOXED(29104,16,FLEN)
NAN_BOXED(30719,16,FLEN)
NAN_BOXED(13737,16,FLEN)
NAN_BOXED(29104,16,FLEN)
NAN_BOXED(30719,16,FLEN)
NAN_BOXED(13737,16,FLEN)
NAN_BOXED(29104,16,FLEN)
NAN_BOXED(30719,16,FLEN)
NAN_BOXED(13737,16,FLEN)
NAN_BOXED(29104,16,FLEN)
NAN_BOXED(30092,16,FLEN)
NAN_BOXED(10840,16,FLEN)
NAN_BOXED(25766,16,FLEN)
NAN_BOXED(30092,16,FLEN)
NAN_BOXED(10840,16,FLEN)
NAN_BOXED(25766,16,FLEN)
NAN_BOXED(30092,16,FLEN)
NAN_BOXED(10840,16,FLEN)
NAN_BOXED(25766,16,FLEN)
NAN_BOXED(30092,16,FLEN)
NAN_BOXED(10840,16,FLEN)
NAN_BOXED(25766,16,FLEN)
NAN_BOXED(30092,16,FLEN)
NAN_BOXED(10840,16,FLEN)
NAN_BOXED(25766,16,FLEN)
NAN_BOXED(29697,16,FLEN)
NAN_BOXED(11097,16,FLEN)
NAN_BOXED(25564,16,FLEN)
NAN_BOXED(29697,16,FLEN)
NAN_BOXED(11097,16,FLEN)
NAN_BOXED(25564,16,FLEN)
NAN_BOXED(29697,16,FLEN)
NAN_BOXED(11097,16,FLEN)
NAN_BOXED(25564,16,FLEN)
NAN_BOXED(29697,16,FLEN)
NAN_BOXED(11097,16,FLEN)
NAN_BOXED(25564,16,FLEN)
NAN_BOXED(29697,16,FLEN)
NAN_BOXED(11097,16,FLEN)
NAN_BOXED(25564,16,FLEN)
NAN_BOXED(31196,16,FLEN)
NAN_BOXED(14854,16,FLEN)
NAN_BOXED(30824,16,FLEN)
NAN_BOXED(31196,16,FLEN)
NAN_BOXED(14854,16,FLEN)
NAN_BOXED(30824,16,FLEN)
NAN_BOXED(31196,16,FLEN)
NAN_BOXED(14854,16,FLEN)
NAN_BOXED(30824,16,FLEN)
NAN_BOXED(31196,16,FLEN)
NAN_BOXED(14854,16,FLEN)
NAN_BOXED(30824,16,FLEN)
NAN_BOXED(31196,16,FLEN)
NAN_BOXED(14854,16,FLEN)
NAN_BOXED(30824,16,FLEN)
NAN_BOXED(29199,16,FLEN)
NAN_BOXED(16645,16,FLEN)
NAN_BOXED(30615,16,FLEN)
NAN_BOXED(29199,16,FLEN)
NAN_BOXED(16645,16,FLEN)
NAN_BOXED(30615,16,FLEN)
NAN_BOXED(29199,16,FLEN)
NAN_BOXED(16645,16,FLEN)
NAN_BOXED(30615,16,FLEN)
NAN_BOXED(29199,16,FLEN)
NAN_BOXED(16645,16,FLEN)
NAN_BOXED(30615,16,FLEN)
NAN_BOXED(29199,16,FLEN)
NAN_BOXED(16645,16,FLEN)
NAN_BOXED(30615,16,FLEN)
NAN_BOXED(31609,16,FLEN)
NAN_BOXED(12120,16,FLEN)
NAN_BOXED(28364,16,FLEN)
NAN_BOXED(31609,16,FLEN)
NAN_BOXED(12120,16,FLEN)
NAN_BOXED(28364,16,FLEN)
NAN_BOXED(31609,16,FLEN)
NAN_BOXED(12120,16,FLEN)
NAN_BOXED(28364,16,FLEN)
NAN_BOXED(31609,16,FLEN)
NAN_BOXED(12120,16,FLEN)
NAN_BOXED(28364,16,FLEN)
NAN_BOXED(31609,16,FLEN)
NAN_BOXED(12120,16,FLEN)
NAN_BOXED(28364,16,FLEN)
NAN_BOXED(31372,16,FLEN)
NAN_BOXED(14395,16,FLEN)
NAN_BOXED(30441,16,FLEN)
NAN_BOXED(31372,16,FLEN)
NAN_BOXED(14395,16,FLEN)
NAN_BOXED(30441,16,FLEN)
NAN_BOXED(31372,16,FLEN)
NAN_BOXED(14395,16,FLEN)
NAN_BOXED(30441,16,FLEN)
NAN_BOXED(31372,16,FLEN)
NAN_BOXED(14395,16,FLEN)
NAN_BOXED(30441,16,FLEN)
NAN_BOXED(31372,16,FLEN)
NAN_BOXED(14395,16,FLEN)
NAN_BOXED(30441,16,FLEN)
NAN_BOXED(30698,16,FLEN)
NAN_BOXED(16064,16,FLEN)
NAN_BOXED(31404,16,FLEN)
NAN_BOXED(30698,16,FLEN)
NAN_BOXED(16064,16,FLEN)
NAN_BOXED(31404,16,FLEN)
NAN_BOXED(30698,16,FLEN)
NAN_BOXED(16064,16,FLEN)
NAN_BOXED(31404,16,FLEN)
NAN_BOXED(30698,16,FLEN)
NAN_BOXED(16064,16,FLEN)
NAN_BOXED(31404,16,FLEN)
NAN_BOXED(30698,16,FLEN)
NAN_BOXED(16064,16,FLEN)
NAN_BOXED(31404,16,FLEN)
NAN_BOXED(30281,16,FLEN)
NAN_BOXED(15658,16,FLEN)
NAN_BOXED(30733,16,FLEN)
NAN_BOXED(30281,16,FLEN)
NAN_BOXED(15658,16,FLEN)
NAN_BOXED(30733,16,FLEN)
NAN_BOXED(30281,16,FLEN)
NAN_BOXED(15658,16,FLEN)
NAN_BOXED(30733,16,FLEN)
NAN_BOXED(30281,16,FLEN)
NAN_BOXED(15658,16,FLEN)
NAN_BOXED(30733,16,FLEN)
NAN_BOXED(30281,16,FLEN)
NAN_BOXED(15658,16,FLEN)
NAN_BOXED(30733,16,FLEN)
NAN_BOXED(31103,16,FLEN)
NAN_BOXED(15800,16,FLEN)
NAN_BOXED(31707,16,FLEN)
NAN_BOXED(31103,16,FLEN)
NAN_BOXED(15800,16,FLEN)
NAN_BOXED(31707,16,FLEN)
NAN_BOXED(31103,16,FLEN)
NAN_BOXED(15800,16,FLEN)
NAN_BOXED(31707,16,FLEN)
NAN_BOXED(31103,16,FLEN)
NAN_BOXED(15800,16,FLEN)
NAN_BOXED(31707,16,FLEN)
NAN_BOXED(31103,16,FLEN)
NAN_BOXED(15800,16,FLEN)
NAN_BOXED(31707,16,FLEN)
NAN_BOXED(30075,16,FLEN)
NAN_BOXED(16603,16,FLEN)
NAN_BOXED(31399,16,FLEN)
NAN_BOXED(30075,16,FLEN)
NAN_BOXED(16603,16,FLEN)
NAN_BOXED(31399,16,FLEN)
NAN_BOXED(30075,16,FLEN)
NAN_BOXED(16603,16,FLEN)
NAN_BOXED(31399,16,FLEN)
NAN_BOXED(30075,16,FLEN)
NAN_BOXED(16603,16,FLEN)
NAN_BOXED(31399,16,FLEN)
NAN_BOXED(30075,16,FLEN)
NAN_BOXED(16603,16,FLEN)
NAN_BOXED(31399,16,FLEN)
NAN_BOXED(31142,16,FLEN)
NAN_BOXED(15154,16,FLEN)
NAN_BOXED(30997,16,FLEN)
NAN_BOXED(31142,16,FLEN)
NAN_BOXED(15154,16,FLEN)
NAN_BOXED(30997,16,FLEN)
NAN_BOXED(31142,16,FLEN)
NAN_BOXED(15154,16,FLEN)
NAN_BOXED(30997,16,FLEN)
NAN_BOXED(31142,16,FLEN)
NAN_BOXED(15154,16,FLEN)
NAN_BOXED(30997,16,FLEN)
NAN_BOXED(31142,16,FLEN)
NAN_BOXED(15154,16,FLEN)
NAN_BOXED(30997,16,FLEN)
NAN_BOXED(30328,16,FLEN)
NAN_BOXED(15070,16,FLEN)
NAN_BOXED(30094,16,FLEN)
NAN_BOXED(30328,16,FLEN)
NAN_BOXED(15070,16,FLEN)
NAN_BOXED(30094,16,FLEN)
NAN_BOXED(30328,16,FLEN)
NAN_BOXED(15070,16,FLEN)
NAN_BOXED(30094,16,FLEN)
NAN_BOXED(30328,16,FLEN)
NAN_BOXED(15070,16,FLEN)
NAN_BOXED(30094,16,FLEN)
NAN_BOXED(30328,16,FLEN)
NAN_BOXED(15070,16,FLEN)
NAN_BOXED(30094,16,FLEN)
NAN_BOXED(27381,16,FLEN)
NAN_BOXED(16581,16,FLEN)
NAN_BOXED(28711,16,FLEN)
NAN_BOXED(27381,16,FLEN)
NAN_BOXED(16581,16,FLEN)
NAN_BOXED(28711,16,FLEN)
NAN_BOXED(27381,16,FLEN)
NAN_BOXED(16581,16,FLEN)
NAN_BOXED(28711,16,FLEN)
NAN_BOXED(27381,16,FLEN)
NAN_BOXED(16581,16,FLEN)
NAN_BOXED(28711,16,FLEN)
NAN_BOXED(27381,16,FLEN)
NAN_BOXED(16581,16,FLEN)
NAN_BOXED(28711,16,FLEN)
NAN_BOXED(27782,16,FLEN)
NAN_BOXED(18748,16,FLEN)
NAN_BOXED(31212,16,FLEN)
NAN_BOXED(27782,16,FLEN)
NAN_BOXED(18748,16,FLEN)
NAN_BOXED(31212,16,FLEN)
NAN_BOXED(27782,16,FLEN)
NAN_BOXED(18748,16,FLEN)
NAN_BOXED(31212,16,FLEN)
NAN_BOXED(27782,16,FLEN)
NAN_BOXED(18748,16,FLEN)
NAN_BOXED(31212,16,FLEN)
NAN_BOXED(27782,16,FLEN)
NAN_BOXED(18748,16,FLEN)
NAN_BOXED(31212,16,FLEN)
NAN_BOXED(29718,16,FLEN)
NAN_BOXED(14620,16,FLEN)
NAN_BOXED(28984,16,FLEN)
NAN_BOXED(29718,16,FLEN)
NAN_BOXED(14620,16,FLEN)
NAN_BOXED(28984,16,FLEN)
NAN_BOXED(29718,16,FLEN)
NAN_BOXED(14620,16,FLEN)
NAN_BOXED(28984,16,FLEN)
NAN_BOXED(29718,16,FLEN)
NAN_BOXED(14620,16,FLEN)
NAN_BOXED(28984,16,FLEN)
NAN_BOXED(29718,16,FLEN)
NAN_BOXED(14620,16,FLEN)
NAN_BOXED(28984,16,FLEN)
NAN_BOXED(28007,16,FLEN)
NAN_BOXED(18682,16,FLEN)
NAN_BOXED(31418,16,FLEN)
NAN_BOXED(28007,16,FLEN)
NAN_BOXED(18682,16,FLEN)
NAN_BOXED(31418,16,FLEN)
NAN_BOXED(28007,16,FLEN)
NAN_BOXED(18682,16,FLEN)
NAN_BOXED(31418,16,FLEN)
NAN_BOXED(28007,16,FLEN)
NAN_BOXED(18682,16,FLEN)
NAN_BOXED(31418,16,FLEN)
NAN_BOXED(28007,16,FLEN)
NAN_BOXED(18682,16,FLEN)
NAN_BOXED(31418,16,FLEN)
NAN_BOXED(31477,16,FLEN)
NAN_BOXED(14889,16,FLEN)
NAN_BOXED(31068,16,FLEN)
NAN_BOXED(31477,16,FLEN)
NAN_BOXED(14889,16,FLEN)
NAN_BOXED(31068,16,FLEN)
NAN_BOXED(31477,16,FLEN)
NAN_BOXED(14889,16,FLEN)
NAN_BOXED(31068,16,FLEN)
NAN_BOXED(31477,16,FLEN)
NAN_BOXED(14889,16,FLEN)
NAN_BOXED(31068,16,FLEN)
NAN_BOXED(31477,16,FLEN)
NAN_BOXED(14889,16,FLEN)
NAN_BOXED(31068,16,FLEN)
NAN_BOXED(29826,16,FLEN)
NAN_BOXED(15071,16,FLEN)
NAN_BOXED(29631,16,FLEN)
NAN_BOXED(29826,16,FLEN)
NAN_BOXED(15071,16,FLEN)
NAN_BOXED(29631,16,FLEN)
NAN_BOXED(29826,16,FLEN)
NAN_BOXED(15071,16,FLEN)
NAN_BOXED(29631,16,FLEN)
NAN_BOXED(29826,16,FLEN)
NAN_BOXED(15071,16,FLEN)
NAN_BOXED(29631,16,FLEN)
NAN_BOXED(29826,16,FLEN)
NAN_BOXED(15071,16,FLEN)
NAN_BOXED(29631,16,FLEN)
NAN_BOXED(29871,16,FLEN)
NAN_BOXED(15941,16,FLEN)
NAN_BOXED(30553,16,FLEN)
NAN_BOXED(29871,16,FLEN)
NAN_BOXED(15941,16,FLEN)
NAN_BOXED(30553,16,FLEN)
NAN_BOXED(29871,16,FLEN)
NAN_BOXED(15941,16,FLEN)
NAN_BOXED(30553,16,FLEN)
NAN_BOXED(29871,16,FLEN)
NAN_BOXED(15941,16,FLEN)
NAN_BOXED(30553,16,FLEN)
NAN_BOXED(29871,16,FLEN)
NAN_BOXED(15941,16,FLEN)
NAN_BOXED(30553,16,FLEN)
NAN_BOXED(28937,16,FLEN)
NAN_BOXED(16808,16,FLEN)
NAN_BOXED(30497,16,FLEN)
NAN_BOXED(28937,16,FLEN)
NAN_BOXED(16808,16,FLEN)
NAN_BOXED(30497,16,FLEN)
NAN_BOXED(28937,16,FLEN)
NAN_BOXED(16808,16,FLEN)
NAN_BOXED(30497,16,FLEN)
NAN_BOXED(28937,16,FLEN)
NAN_BOXED(16808,16,FLEN)
NAN_BOXED(30497,16,FLEN)
NAN_BOXED(28937,16,FLEN)
NAN_BOXED(16808,16,FLEN)
NAN_BOXED(30497,16,FLEN)
NAN_BOXED(29749,16,FLEN)
NAN_BOXED(17230,16,FLEN)
NAN_BOXED(31664,16,FLEN)
NAN_BOXED(29749,16,FLEN)
NAN_BOXED(17230,16,FLEN)
NAN_BOXED(31664,16,FLEN)
NAN_BOXED(29749,16,FLEN)
NAN_BOXED(17230,16,FLEN)
NAN_BOXED(31664,16,FLEN)
NAN_BOXED(29749,16,FLEN)
NAN_BOXED(17230,16,FLEN)
NAN_BOXED(31664,16,FLEN)
NAN_BOXED(29749,16,FLEN)
NAN_BOXED(17230,16,FLEN)
NAN_BOXED(31664,16,FLEN)
NAN_BOXED(31686,16,FLEN)
NAN_BOXED(14463,16,FLEN)
NAN_BOXED(30815,16,FLEN)
NAN_BOXED(31686,16,FLEN)
NAN_BOXED(14463,16,FLEN)
NAN_BOXED(30815,16,FLEN)
NAN_BOXED(31686,16,FLEN)
NAN_BOXED(14463,16,FLEN)
NAN_BOXED(30815,16,FLEN)
NAN_BOXED(31686,16,FLEN)
NAN_BOXED(14463,16,FLEN)
NAN_BOXED(30815,16,FLEN)
NAN_BOXED(31686,16,FLEN)
NAN_BOXED(14463,16,FLEN)
NAN_BOXED(30815,16,FLEN)
NAN_BOXED(29649,16,FLEN)
NAN_BOXED(17382,16,FLEN)
NAN_BOXED(31672,16,FLEN)
NAN_BOXED(29649,16,FLEN)
NAN_BOXED(17382,16,FLEN)
NAN_BOXED(31672,16,FLEN)
NAN_BOXED(29649,16,FLEN)
NAN_BOXED(17382,16,FLEN)
NAN_BOXED(31672,16,FLEN)
NAN_BOXED(29649,16,FLEN)
NAN_BOXED(17382,16,FLEN)
NAN_BOXED(31672,16,FLEN)
NAN_BOXED(29649,16,FLEN)
NAN_BOXED(17382,16,FLEN)
NAN_BOXED(31672,16,FLEN)
NAN_BOXED(29939,16,FLEN)
NAN_BOXED(15515,16,FLEN)
NAN_BOXED(30131,16,FLEN)
NAN_BOXED(29939,16,FLEN)
NAN_BOXED(15515,16,FLEN)
NAN_BOXED(30131,16,FLEN)
NAN_BOXED(29939,16,FLEN)
NAN_BOXED(15515,16,FLEN)
NAN_BOXED(30131,16,FLEN)
NAN_BOXED(29939,16,FLEN)
NAN_BOXED(15515,16,FLEN)
NAN_BOXED(30131,16,FLEN)
NAN_BOXED(29939,16,FLEN)
NAN_BOXED(15515,16,FLEN)
NAN_BOXED(30131,16,FLEN)
NAN_BOXED(21616,16,FLEN)
NAN_BOXED(23936,16,FLEN)
NAN_BOXED(30234,16,FLEN)
NAN_BOXED(21616,16,FLEN)
NAN_BOXED(23936,16,FLEN)
NAN_BOXED(30234,16,FLEN)
NAN_BOXED(21616,16,FLEN)
NAN_BOXED(23936,16,FLEN)
NAN_BOXED(30234,16,FLEN)
NAN_BOXED(21616,16,FLEN)
NAN_BOXED(23936,16,FLEN)
NAN_BOXED(30234,16,FLEN)
NAN_BOXED(21616,16,FLEN)
NAN_BOXED(23936,16,FLEN)
NAN_BOXED(30234,16,FLEN)
NAN_BOXED(30615,16,FLEN)
NAN_BOXED(15420,16,FLEN)
NAN_BOXED(30725,16,FLEN)
NAN_BOXED(30615,16,FLEN)
NAN_BOXED(15420,16,FLEN)
NAN_BOXED(30725,16,FLEN)
NAN_BOXED(30615,16,FLEN)
NAN_BOXED(15420,16,FLEN)
NAN_BOXED(30725,16,FLEN)
NAN_BOXED(30615,16,FLEN)
NAN_BOXED(15420,16,FLEN)
NAN_BOXED(30725,16,FLEN)
NAN_BOXED(30615,16,FLEN)
NAN_BOXED(15420,16,FLEN)
NAN_BOXED(30725,16,FLEN)
NAN_BOXED(29293,16,FLEN)
NAN_BOXED(16645,16,FLEN)
NAN_BOXED(30729,16,FLEN)
NAN_BOXED(29293,16,FLEN)
NAN_BOXED(16645,16,FLEN)
NAN_BOXED(30729,16,FLEN)
NAN_BOXED(29293,16,FLEN)
NAN_BOXED(16645,16,FLEN)
NAN_BOXED(30729,16,FLEN)
NAN_BOXED(29293,16,FLEN)
NAN_BOXED(16645,16,FLEN)
NAN_BOXED(30729,16,FLEN)
NAN_BOXED(29293,16,FLEN)
NAN_BOXED(16645,16,FLEN)
NAN_BOXED(30729,16,FLEN)
NAN_BOXED(23829,16,FLEN)
NAN_BOXED(21158,16,FLEN)
NAN_BOXED(29753,16,FLEN)
NAN_BOXED(23829,16,FLEN)
NAN_BOXED(21158,16,FLEN)
NAN_BOXED(29753,16,FLEN)
NAN_BOXED(23829,16,FLEN)
NAN_BOXED(21158,16,FLEN)
NAN_BOXED(29753,16,FLEN)
NAN_BOXED(23829,16,FLEN)
NAN_BOXED(21158,16,FLEN)
NAN_BOXED(29753,16,FLEN)
NAN_BOXED(23829,16,FLEN)
NAN_BOXED(21158,16,FLEN)
NAN_BOXED(29753,16,FLEN)
NAN_BOXED(28094,16,FLEN)
NAN_BOXED(17523,16,FLEN)
NAN_BOXED(30307,16,FLEN)
NAN_BOXED(28094,16,FLEN)
NAN_BOXED(17523,16,FLEN)
NAN_BOXED(30307,16,FLEN)
NAN_BOXED(28094,16,FLEN)
NAN_BOXED(17523,16,FLEN)
NAN_BOXED(30307,16,FLEN)
NAN_BOXED(28094,16,FLEN)
NAN_BOXED(17523,16,FLEN)
NAN_BOXED(30307,16,FLEN)
NAN_BOXED(28094,16,FLEN)
NAN_BOXED(17523,16,FLEN)
NAN_BOXED(30307,16,FLEN)
NAN_BOXED(26965,16,FLEN)
NAN_BOXED(14417,16,FLEN)
NAN_BOXED(26050,16,FLEN)
NAN_BOXED(26965,16,FLEN)
NAN_BOXED(14417,16,FLEN)
NAN_BOXED(26050,16,FLEN)
NAN_BOXED(26965,16,FLEN)
NAN_BOXED(14417,16,FLEN)
NAN_BOXED(26050,16,FLEN)
NAN_BOXED(26965,16,FLEN)
NAN_BOXED(14417,16,FLEN)
NAN_BOXED(26050,16,FLEN)
NAN_BOXED(26965,16,FLEN)
NAN_BOXED(14417,16,FLEN)
NAN_BOXED(26050,16,FLEN)
NAN_BOXED(29917,16,FLEN)
NAN_BOXED(14879,16,FLEN)
NAN_BOXED(29554,16,FLEN)
NAN_BOXED(29917,16,FLEN)
NAN_BOXED(14879,16,FLEN)
NAN_BOXED(29554,16,FLEN)
NAN_BOXED(29917,16,FLEN)
NAN_BOXED(14879,16,FLEN)
NAN_BOXED(29554,16,FLEN)
NAN_BOXED(29917,16,FLEN)
NAN_BOXED(14879,16,FLEN)
NAN_BOXED(29554,16,FLEN)
NAN_BOXED(29917,16,FLEN)
NAN_BOXED(14879,16,FLEN)
NAN_BOXED(29554,16,FLEN)
NAN_BOXED(30894,16,FLEN)
NAN_BOXED(15162,16,FLEN)
NAN_BOXED(30779,16,FLEN)
NAN_BOXED(30894,16,FLEN)
NAN_BOXED(15162,16,FLEN)
NAN_BOXED(30779,16,FLEN)
NAN_BOXED(30894,16,FLEN)
NAN_BOXED(15162,16,FLEN)
NAN_BOXED(30779,16,FLEN)
NAN_BOXED(30894,16,FLEN)
NAN_BOXED(15162,16,FLEN)
NAN_BOXED(30779,16,FLEN)
NAN_BOXED(30894,16,FLEN)
NAN_BOXED(15162,16,FLEN)
NAN_BOXED(30779,16,FLEN)
NAN_BOXED(31232,16,FLEN)
NAN_BOXED(15106,16,FLEN)
NAN_BOXED(31042,16,FLEN)
NAN_BOXED(31232,16,FLEN)
NAN_BOXED(15106,16,FLEN)
NAN_BOXED(31042,16,FLEN)
NAN_BOXED(31232,16,FLEN)
NAN_BOXED(15106,16,FLEN)
NAN_BOXED(31042,16,FLEN)
NAN_BOXED(31232,16,FLEN)
NAN_BOXED(15106,16,FLEN)
NAN_BOXED(31042,16,FLEN)
NAN_BOXED(31232,16,FLEN)
NAN_BOXED(15106,16,FLEN)
NAN_BOXED(31042,16,FLEN)
NAN_BOXED(31161,16,FLEN)
NAN_BOXED(15593,16,FLEN)
NAN_BOXED(31495,16,FLEN)
NAN_BOXED(31161,16,FLEN)
NAN_BOXED(15593,16,FLEN)
NAN_BOXED(31495,16,FLEN)
NAN_BOXED(31161,16,FLEN)
NAN_BOXED(15593,16,FLEN)
NAN_BOXED(31495,16,FLEN)
NAN_BOXED(31161,16,FLEN)
NAN_BOXED(15593,16,FLEN)
NAN_BOXED(31495,16,FLEN)
NAN_BOXED(31161,16,FLEN)
NAN_BOXED(15593,16,FLEN)
NAN_BOXED(31495,16,FLEN)
NAN_BOXED(30266,16,FLEN)
NAN_BOXED(15026,16,FLEN)
NAN_BOXED(30007,16,FLEN)
NAN_BOXED(30266,16,FLEN)
NAN_BOXED(15026,16,FLEN)
NAN_BOXED(30007,16,FLEN)
NAN_BOXED(30266,16,FLEN)
NAN_BOXED(15026,16,FLEN)
NAN_BOXED(30007,16,FLEN)
NAN_BOXED(30266,16,FLEN)
NAN_BOXED(15026,16,FLEN)
NAN_BOXED(30007,16,FLEN)
NAN_BOXED(30266,16,FLEN)
NAN_BOXED(15026,16,FLEN)
NAN_BOXED(30007,16,FLEN)
NAN_BOXED(31711,16,FLEN)
NAN_BOXED(12507,16,FLEN)
NAN_BOXED(28871,16,FLEN)
NAN_BOXED(31711,16,FLEN)
NAN_BOXED(12507,16,FLEN)
NAN_BOXED(28871,16,FLEN)
NAN_BOXED(31711,16,FLEN)
NAN_BOXED(12507,16,FLEN)
NAN_BOXED(28871,16,FLEN)
NAN_BOXED(31711,16,FLEN)
NAN_BOXED(12507,16,FLEN)
NAN_BOXED(28871,16,FLEN)
NAN_BOXED(31711,16,FLEN)
NAN_BOXED(12507,16,FLEN)
NAN_BOXED(28871,16,FLEN)
NAN_BOXED(31178,16,FLEN)
NAN_BOXED(15131,16,FLEN)
NAN_BOXED(31012,16,FLEN)
NAN_BOXED(31178,16,FLEN)
NAN_BOXED(15131,16,FLEN)
NAN_BOXED(31012,16,FLEN)
NAN_BOXED(31178,16,FLEN)
NAN_BOXED(15131,16,FLEN)
NAN_BOXED(31012,16,FLEN)
NAN_BOXED(31178,16,FLEN)
NAN_BOXED(15131,16,FLEN)
NAN_BOXED(31012,16,FLEN)
NAN_BOXED(31178,16,FLEN)
NAN_BOXED(15131,16,FLEN)
NAN_BOXED(31012,16,FLEN)
NAN_BOXED(29997,16,FLEN)
NAN_BOXED(14196,16,FLEN)
NAN_BOXED(28883,16,FLEN)
NAN_BOXED(29997,16,FLEN)
NAN_BOXED(14196,16,FLEN)
NAN_BOXED(28883,16,FLEN)
NAN_BOXED(31028,16,FLEN)
NAN_BOXED(12063,16,FLEN)
NAN_BOXED(27810,16,FLEN)
NAN_BOXED(31028,16,FLEN)
NAN_BOXED(12063,16,FLEN)
NAN_BOXED(27810,16,FLEN)
NAN_BOXED(31028,16,FLEN)
NAN_BOXED(12063,16,FLEN)
NAN_BOXED(27810,16,FLEN)
NAN_BOXED(31028,16,FLEN)
NAN_BOXED(12063,16,FLEN)
NAN_BOXED(27810,16,FLEN)
NAN_BOXED(31028,16,FLEN)
NAN_BOXED(12063,16,FLEN)
NAN_BOXED(27810,16,FLEN)
NAN_BOXED(30792,16,FLEN)
NAN_BOXED(14709,16,FLEN)
NAN_BOXED(30169,16,FLEN)
RVTEST_DATA_END

RVMODEL_DATA_BEGIN
rvtest_sig_begin:
sig_begin_canary:
CANARY;



signature_x1_0:
    .fill 0*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_1:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_2:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_3:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_4:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_5:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_6:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_7:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_8:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_9:
    .fill 208*((SIGALIGN)/4),4,0xdeadbeef

#ifdef rvtest_mtrap_routine
tsig_begin_canary:
CANARY;

mtrap_sigptr:
    .fill 64*XLEN/32,4,0xdeadbeef

tsig_end_canary:
CANARY;
#endif

#ifdef rvtest_gpr_save

gpr_save:
    .fill 32*XLEN/32,4,0xdeadbeef

#endif


sig_end_canary:
CANARY;
rvtest_sig_end:
RVMODEL_DATA_END
