
// -----------
// This file was generated by riscv_ctg (https://github.com/riscv-software-src/riscv-ctg)
// version   : 0.11.0
// timestamp : Tue Jan 30 08:43:45 2024 GMT
// usage     : riscv_ctg \
//                  -- cgf //                  --cgf /home/riscv/riscv-ctg/sample_cgfs/dataset.cgf \
//                  --cgf /home/riscv/riscv-ctg/sample_cgfs/sample_cgfs_fext/RV32H/rv32h_fmsub.cgf \
 \
//                  -- xlen 32  \
// -----------
//
// -----------
// Copyright (c) 2020. RISC-V International. All rights reserved.
// SPDX-License-Identifier: BSD-3-Clause
// -----------
//
// This assembly file tests the fmsub.h instruction of the RISC-V RV32F_Zicsr_Zfh,RV64F_Zicsr_Zfh extension for the fmsub_b8 covergroup.
// 
#include "model_test.h"
#include "arch_test.h"
RVTEST_ISA("RV32IF_Zicsr_Zfh,RV64IF_Zicsr_Zfh")

.section .text.init
.globl rvtest_entry_point
rvtest_entry_point:
RVMODEL_BOOT
RVTEST_CODE_BEGIN

#ifdef TEST_CASE_1

RVTEST_CASE(0,"//check ISA:=regex(.*I.*F.*Zfh.*);def TEST_CASE_1=True;",fmsub_b8)

RVTEST_FP_ENABLE()
RVTEST_VALBASEUPD(x3,test_dataset_0)
RVTEST_SIGBASE(x1,signature_x1_1)

inst_0:
// rs1 == rd == rs3 != rs2, rs1==f31, rs2==f30, rs3==f31, rd==f31,fs1 == 0 and fe1 == 0x0e and fm1 == 0x168 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x105 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x2cb and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f31; op2:f30; op3:f31; dest:f31; op1val:0x3968; op2val:0x3d05;
op3val:0x3968; valaddr_reg:x3; val_offset:0*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f31, f30, f31, dyn, 0, 0, x3, 0*FLEN/8, x4, x1, x2)

inst_1:
// rs1 == rd != rs2 and rs1 == rd != rs3 and rs3 != rs2, rs1==f30, rs2==f31, rs3==f29, rd==f30,fs1 == 0 and fe1 == 0x0e and fm1 == 0x168 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x105 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x2cb and fcsr == 0x20 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f31; op3:f29; dest:f30; op1val:0x3968; op2val:0x3d05;
op3val:0x3acb; valaddr_reg:x3; val_offset:3*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:32 */
TEST_FPR4_OP(fmsub.h, f30, f30, f31, f29, dyn, 32, 0, x3, 3*FLEN/8, x4, x1, x2)

inst_2:
// rd == rs2 == rs3 != rs1, rs1==f29, rs2==f28, rs3==f28, rd==f28,fs1 == 0 and fe1 == 0x0e and fm1 == 0x168 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x105 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x2cb and fcsr == 0x40 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f29; op2:f28; op3:f28; dest:f28; op1val:0x3968; op2val:0x3d05;
op3val:0x3d05; valaddr_reg:x3; val_offset:6*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:64 */
TEST_FPR4_OP(fmsub.h, f28, f29, f28, f28, dyn, 64, 0, x3, 6*FLEN/8, x4, x1, x2)

inst_3:
// rs3 == rd != rs1 and rs3 == rd != rs2 and rs2 != rs1, rs1==f28, rs2==f29, rs3==f27, rd==f27,fs1 == 0 and fe1 == 0x0e and fm1 == 0x168 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x105 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x2cb and fcsr == 0x60 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f28; op2:f29; op3:f27; dest:f27; op1val:0x3968; op2val:0x3d05;
op3val:0x3acb; valaddr_reg:x3; val_offset:9*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fmsub.h, f27, f28, f29, f27, dyn, 96, 0, x3, 9*FLEN/8, x4, x1, x2)

inst_4:
// rs2 == rd != rs1 and rs2 == rd != rs3 and rs3 != rs1, rs1==f27, rs2==f26, rs3==f30, rd==f26,fs1 == 0 and fe1 == 0x0e and fm1 == 0x168 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x105 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x2cb and fcsr == 0x80 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f27; op2:f26; op3:f30; dest:f26; op1val:0x3968; op2val:0x3d05;
op3val:0x3acb; valaddr_reg:x3; val_offset:12*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:128 */
TEST_FPR4_OP(fmsub.h, f26, f27, f26, f30, dyn, 128, 0, x3, 12*FLEN/8, x4, x1, x2)

inst_5:
// rs1 == rs2 == rs3 == rd, rs1==f25, rs2==f25, rs3==f25, rd==f25,fs1 == 0 and fe1 == 0x0d and fm1 == 0x195 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x150 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x36b and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f25; op2:f25; op3:f25; dest:f25; op1val:0x3595; op2val:0x3595;
op3val:0x3595; valaddr_reg:x3; val_offset:15*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f25, f25, f25, f25, dyn, 0, 0, x3, 15*FLEN/8, x4, x1, x2)

inst_6:
// rs2 == rs3 != rs1 and rs2 == rs3 != rd and rd != rs1, rs1==f26, rs2==f24, rs3==f24, rd==f29,fs1 == 0 and fe1 == 0x0d and fm1 == 0x195 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x150 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x36b and fcsr == 0x20 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f26; op2:f24; op3:f24; dest:f29; op1val:0x3595; op2val:0x4150;
op3val:0x4150; valaddr_reg:x3; val_offset:18*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:32 */
TEST_FPR4_OP(fmsub.h, f29, f26, f24, f24, dyn, 32, 0, x3, 18*FLEN/8, x4, x1, x2)

inst_7:
// rs1 == rs2 == rd != rs3, rs1==f23, rs2==f23, rs3==f26, rd==f23,fs1 == 0 and fe1 == 0x0d and fm1 == 0x195 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x150 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x36b and fcsr == 0x40 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f23; op2:f23; op3:f26; dest:f23; op1val:0x3595; op2val:0x3595;
op3val:0x3b6b; valaddr_reg:x3; val_offset:21*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:64 */
TEST_FPR4_OP(fmsub.h, f23, f23, f23, f26, dyn, 64, 0, x3, 21*FLEN/8, x4, x1, x2)

inst_8:
// rs1 == rs2 == rs3 != rd, rs1==f22, rs2==f22, rs3==f22, rd==f24,fs1 == 0 and fe1 == 0x0d and fm1 == 0x195 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x150 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x36b and fcsr == 0x60 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f22; op2:f22; op3:f22; dest:f24; op1val:0x3595; op2val:0x3595;
op3val:0x3595; valaddr_reg:x3; val_offset:24*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fmsub.h, f24, f22, f22, f22, dyn, 96, 0, x3, 24*FLEN/8, x4, x1, x2)

inst_9:
// rs1 == rs2 != rs3 and rs1 == rs2 != rd and rd != rs3, rs1==f21, rs2==f21, rs3==f23, rd==f22,fs1 == 0 and fe1 == 0x0d and fm1 == 0x195 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x150 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x36b and fcsr == 0x80 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f21; op2:f21; op3:f23; dest:f22; op1val:0x3595; op2val:0x3595;
op3val:0x3b6b; valaddr_reg:x3; val_offset:27*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:128 */
TEST_FPR4_OP(fmsub.h, f22, f21, f21, f23, dyn, 128, 0, x3, 27*FLEN/8, x4, x1, x2)

inst_10:
// rs1 == rs3 != rs2 and rs1 == rs3 != rd and rd != rs2, rs1==f20, rs2==f27, rs3==f20, rd==f21,fs1 == 0 and fe1 == 0x0d and fm1 == 0x36d and fs2 == 0 and fe2 == 0x0f and fm2 == 0x177 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x113 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f20; op2:f27; op3:f20; dest:f21; op1val:0x376d; op2val:0x3d77;
op3val:0x376d; valaddr_reg:x3; val_offset:30*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f21, f20, f27, f20, dyn, 0, 0, x3, 30*FLEN/8, x4, x1, x2)

inst_11:
// rs1 != rs2 and rs1 != rd and rs1 != rs3 and rs2 != rs3 and rs2 != rd and rs3 != rd, rs1==f24, rs2==f19, rs3==f21, rd==f20,fs1 == 0 and fe1 == 0x0d and fm1 == 0x36d and fs2 == 0 and fe2 == 0x0f and fm2 == 0x177 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x113 and fcsr == 0x20 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f24; op2:f19; op3:f21; dest:f20; op1val:0x376d; op2val:0x3d77;
op3val:0x3913; valaddr_reg:x3; val_offset:33*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:32 */
TEST_FPR4_OP(fmsub.h, f20, f24, f19, f21, dyn, 32, 0, x3, 33*FLEN/8, x4, x1, x2)

inst_12:
// rs1==f18, rs2==f20, rs3==f17, rd==f19,fs1 == 0 and fe1 == 0x0d and fm1 == 0x36d and fs2 == 0 and fe2 == 0x0f and fm2 == 0x177 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x113 and fcsr == 0x40 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f18; op2:f20; op3:f17; dest:f19; op1val:0x376d; op2val:0x3d77;
op3val:0x3913; valaddr_reg:x3; val_offset:36*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:64 */
TEST_FPR4_OP(fmsub.h, f19, f18, f20, f17, dyn, 64, 0, x3, 36*FLEN/8, x4, x1, x2)

inst_13:
// rs1==f19, rs2==f17, rs3==f16, rd==f18,fs1 == 0 and fe1 == 0x0d and fm1 == 0x36d and fs2 == 0 and fe2 == 0x0f and fm2 == 0x177 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x113 and fcsr == 0x60 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f19; op2:f17; op3:f16; dest:f18; op1val:0x376d; op2val:0x3d77;
op3val:0x3913; valaddr_reg:x3; val_offset:39*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fmsub.h, f18, f19, f17, f16, dyn, 96, 0, x3, 39*FLEN/8, x4, x1, x2)

inst_14:
// rs1==f16, rs2==f18, rs3==f19, rd==f17,fs1 == 0 and fe1 == 0x0d and fm1 == 0x36d and fs2 == 0 and fe2 == 0x0f and fm2 == 0x177 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x113 and fcsr == 0x80 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f16; op2:f18; op3:f19; dest:f17; op1val:0x376d; op2val:0x3d77;
op3val:0x3913; valaddr_reg:x3; val_offset:42*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:128 */
TEST_FPR4_OP(fmsub.h, f17, f16, f18, f19, dyn, 128, 0, x3, 42*FLEN/8, x4, x1, x2)

inst_15:
// rs1==f17, rs2==f15, rs3==f18, rd==f16,fs1 == 0 and fe1 == 0x0e and fm1 == 0x389 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x02e and fs3 == 0 and fe3 == 0x0d and fm3 == 0x3e1 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f17; op2:f15; op3:f18; dest:f16; op1val:0x3b89; op2val:0x382e;
op3val:0x37e1; valaddr_reg:x3; val_offset:45*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f16, f17, f15, f18, dyn, 0, 0, x3, 45*FLEN/8, x4, x1, x2)

inst_16:
// rs1==f14, rs2==f16, rs3==f13, rd==f15,fs1 == 0 and fe1 == 0x0e and fm1 == 0x389 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x02e and fs3 == 0 and fe3 == 0x0d and fm3 == 0x3e1 and fcsr == 0x20 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f14; op2:f16; op3:f13; dest:f15; op1val:0x3b89; op2val:0x382e;
op3val:0x37e1; valaddr_reg:x3; val_offset:48*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:32 */
TEST_FPR4_OP(fmsub.h, f15, f14, f16, f13, dyn, 32, 0, x3, 48*FLEN/8, x4, x1, x2)

inst_17:
// rs1==f15, rs2==f13, rs3==f12, rd==f14,fs1 == 0 and fe1 == 0x0e and fm1 == 0x389 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x02e and fs3 == 0 and fe3 == 0x0d and fm3 == 0x3e1 and fcsr == 0x40 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f15; op2:f13; op3:f12; dest:f14; op1val:0x3b89; op2val:0x382e;
op3val:0x37e1; valaddr_reg:x3; val_offset:51*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:64 */
TEST_FPR4_OP(fmsub.h, f14, f15, f13, f12, dyn, 64, 0, x3, 51*FLEN/8, x4, x1, x2)

inst_18:
// rs1==f12, rs2==f14, rs3==f15, rd==f13,fs1 == 0 and fe1 == 0x0e and fm1 == 0x389 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x02e and fs3 == 0 and fe3 == 0x0d and fm3 == 0x3e1 and fcsr == 0x60 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f12; op2:f14; op3:f15; dest:f13; op1val:0x3b89; op2val:0x382e;
op3val:0x37e1; valaddr_reg:x3; val_offset:54*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fmsub.h, f13, f12, f14, f15, dyn, 96, 0, x3, 54*FLEN/8, x4, x1, x2)

inst_19:
// rs1==f13, rs2==f11, rs3==f14, rd==f12,fs1 == 0 and fe1 == 0x0e and fm1 == 0x389 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x02e and fs3 == 0 and fe3 == 0x0d and fm3 == 0x3e1 and fcsr == 0x80 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f13; op2:f11; op3:f14; dest:f12; op1val:0x3b89; op2val:0x382e;
op3val:0x37e1; valaddr_reg:x3; val_offset:57*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:128 */
TEST_FPR4_OP(fmsub.h, f12, f13, f11, f14, dyn, 128, 0, x3, 57*FLEN/8, x4, x1, x2)

inst_20:
// rs1==f10, rs2==f12, rs3==f9, rd==f11,fs1 == 0 and fe1 == 0x0e and fm1 == 0x3b3 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x0b5 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x087 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f10; op2:f12; op3:f9; dest:f11; op1val:0x3bb3; op2val:0x38b5;
op3val:0x3887; valaddr_reg:x3; val_offset:60*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f11, f10, f12, f9, dyn, 0, 0, x3, 60*FLEN/8, x4, x1, x2)

inst_21:
// rs1==f11, rs2==f9, rs3==f8, rd==f10,fs1 == 0 and fe1 == 0x0e and fm1 == 0x3b3 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x0b5 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x087 and fcsr == 0x20 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f11; op2:f9; op3:f8; dest:f10; op1val:0x3bb3; op2val:0x38b5;
op3val:0x3887; valaddr_reg:x3; val_offset:63*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:32 */
TEST_FPR4_OP(fmsub.h, f10, f11, f9, f8, dyn, 32, 0, x3, 63*FLEN/8, x4, x1, x2)

inst_22:
// rs1==f8, rs2==f10, rs3==f11, rd==f9,fs1 == 0 and fe1 == 0x0e and fm1 == 0x3b3 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x0b5 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x087 and fcsr == 0x40 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f8; op2:f10; op3:f11; dest:f9; op1val:0x3bb3; op2val:0x38b5;
op3val:0x3887; valaddr_reg:x3; val_offset:66*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:64 */
TEST_FPR4_OP(fmsub.h, f9, f8, f10, f11, dyn, 64, 0, x3, 66*FLEN/8, x4, x1, x2)

inst_23:
// rs1==f9, rs2==f7, rs3==f10, rd==f8,fs1 == 0 and fe1 == 0x0e and fm1 == 0x3b3 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x0b5 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x087 and fcsr == 0x60 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f9; op2:f7; op3:f10; dest:f8; op1val:0x3bb3; op2val:0x38b5;
op3val:0x3887; valaddr_reg:x3; val_offset:69*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fmsub.h, f8, f9, f7, f10, dyn, 96, 0, x3, 69*FLEN/8, x4, x1, x2)

inst_24:
// rs1==f6, rs2==f8, rs3==f5, rd==f7,fs1 == 0 and fe1 == 0x0e and fm1 == 0x3b3 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x0b5 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x087 and fcsr == 0x80 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f6; op2:f8; op3:f5; dest:f7; op1val:0x3bb3; op2val:0x38b5;
op3val:0x3887; valaddr_reg:x3; val_offset:72*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:128 */
TEST_FPR4_OP(fmsub.h, f7, f6, f8, f5, dyn, 128, 0, x3, 72*FLEN/8, x4, x1, x2)

inst_25:
// rs1==f7, rs2==f5, rs3==f4, rd==f6,fs1 == 0 and fe1 == 0x0e and fm1 == 0x370 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x3d2 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x346 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f7; op2:f5; op3:f4; dest:f6; op1val:0x3b70; op2val:0x3bd2;
op3val:0x3b46; valaddr_reg:x3; val_offset:75*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f6, f7, f5, f4, dyn, 0, 0, x3, 75*FLEN/8, x4, x1, x2)

inst_26:
// rs1==f4, rs2==f6, rs3==f7, rd==f5,fs1 == 0 and fe1 == 0x0e and fm1 == 0x370 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x3d2 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x346 and fcsr == 0x20 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f4; op2:f6; op3:f7; dest:f5; op1val:0x3b70; op2val:0x3bd2;
op3val:0x3b46; valaddr_reg:x3; val_offset:78*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:32 */
TEST_FPR4_OP(fmsub.h, f5, f4, f6, f7, dyn, 32, 0, x3, 78*FLEN/8, x4, x1, x2)

inst_27:
// rs1==f5, rs2==f3, rs3==f6, rd==f4,fs1 == 0 and fe1 == 0x0e and fm1 == 0x370 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x3d2 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x346 and fcsr == 0x40 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f5; op2:f3; op3:f6; dest:f4; op1val:0x3b70; op2val:0x3bd2;
op3val:0x3b46; valaddr_reg:x3; val_offset:81*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:64 */
TEST_FPR4_OP(fmsub.h, f4, f5, f3, f6, dyn, 64, 0, x3, 81*FLEN/8, x4, x1, x2)

inst_28:
// rs1==f2, rs2==f4, rs3==f1, rd==f3,fs1 == 0 and fe1 == 0x0e and fm1 == 0x370 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x3d2 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x346 and fcsr == 0x60 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f2; op2:f4; op3:f1; dest:f3; op1val:0x3b70; op2val:0x3bd2;
op3val:0x3b46; valaddr_reg:x3; val_offset:84*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fmsub.h, f3, f2, f4, f1, dyn, 96, 0, x3, 84*FLEN/8, x4, x1, x2)

inst_29:
// rs1==f3, rs2==f1, rs3==f0, rd==f2,fs1 == 0 and fe1 == 0x0e and fm1 == 0x370 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x3d2 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x346 and fcsr == 0x80 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f3; op2:f1; op3:f0; dest:f2; op1val:0x3b70; op2val:0x3bd2;
op3val:0x3b46; valaddr_reg:x3; val_offset:87*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:128 */
TEST_FPR4_OP(fmsub.h, f2, f3, f1, f0, dyn, 128, 0, x3, 87*FLEN/8, x4, x1, x2)

inst_30:
// rs1==f0, rs2==f2, rs3==f3, rd==f1,fs1 == 0 and fe1 == 0x0e and fm1 == 0x09a and fs2 == 0 and fe2 == 0x0d and fm2 == 0x0d0 and fs3 == 0 and fe3 == 0x0c and fm3 == 0x18a and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f0; op2:f2; op3:f3; dest:f1; op1val:0x389a; op2val:0x34d0;
op3val:0x318a; valaddr_reg:x3; val_offset:90*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f1, f0, f2, f3, dyn, 0, 0, x3, 90*FLEN/8, x4, x1, x2)

inst_31:
// rs1==f1,fs1 == 0 and fe1 == 0x0e and fm1 == 0x09a and fs2 == 0 and fe2 == 0x0d and fm2 == 0x0d0 and fs3 == 0 and fe3 == 0x0c and fm3 == 0x18a and fcsr == 0x20 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f1; op2:f30; op3:f29; dest:f31; op1val:0x389a; op2val:0x34d0;
op3val:0x318a; valaddr_reg:x3; val_offset:93*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:32 */
TEST_FPR4_OP(fmsub.h, f31, f1, f30, f29, dyn, 32, 0, x3, 93*FLEN/8, x4, x1, x2)

inst_32:
// rs2==f0,fs1 == 0 and fe1 == 0x0e and fm1 == 0x09a and fs2 == 0 and fe2 == 0x0d and fm2 == 0x0d0 and fs3 == 0 and fe3 == 0x0c and fm3 == 0x18a and fcsr == 0x40 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f0; op3:f29; dest:f31; op1val:0x389a; op2val:0x34d0;
op3val:0x318a; valaddr_reg:x3; val_offset:96*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:64 */
TEST_FPR4_OP(fmsub.h, f31, f30, f0, f29, dyn, 64, 0, x3, 96*FLEN/8, x4, x1, x2)

inst_33:
// rs3==f2,fs1 == 0 and fe1 == 0x0e and fm1 == 0x09a and fs2 == 0 and fe2 == 0x0d and fm2 == 0x0d0 and fs3 == 0 and fe3 == 0x0c and fm3 == 0x18a and fcsr == 0x60 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f2; dest:f31; op1val:0x389a; op2val:0x34d0;
op3val:0x318a; valaddr_reg:x3; val_offset:99*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f2, dyn, 96, 0, x3, 99*FLEN/8, x4, x1, x2)

inst_34:
// rd==f0,fs1 == 0 and fe1 == 0x0e and fm1 == 0x09a and fs2 == 0 and fe2 == 0x0d and fm2 == 0x0d0 and fs3 == 0 and fe3 == 0x0c and fm3 == 0x18a and fcsr == 0x80 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f31; op2:f30; op3:f29; dest:f0; op1val:0x389a; op2val:0x34d0;
op3val:0x318a; valaddr_reg:x3; val_offset:102*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:128 */
TEST_FPR4_OP(fmsub.h, f0, f31, f30, f29, dyn, 128, 0, x3, 102*FLEN/8, x4, x1, x2)

inst_35:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x302 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x317 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x236 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3b02; op2val:0x3b17;
op3val:0x3a36; valaddr_reg:x3; val_offset:105*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 105*FLEN/8, x4, x1, x2)

inst_36:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x302 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x317 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x236 and fcsr == 0x20 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3b02; op2val:0x3b17;
op3val:0x3a36; valaddr_reg:x3; val_offset:108*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:32 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 32, 0, x3, 108*FLEN/8, x4, x1, x2)

inst_37:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x302 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x317 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x236 and fcsr == 0x40 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3b02; op2val:0x3b17;
op3val:0x3a36; valaddr_reg:x3; val_offset:111*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:64 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 64, 0, x3, 111*FLEN/8, x4, x1, x2)

inst_38:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x302 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x317 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x236 and fcsr == 0x60 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3b02; op2val:0x3b17;
op3val:0x3a36; valaddr_reg:x3; val_offset:114*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 96, 0, x3, 114*FLEN/8, x4, x1, x2)

inst_39:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x302 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x317 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x236 and fcsr == 0x80 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3b02; op2val:0x3b17;
op3val:0x3a36; valaddr_reg:x3; val_offset:117*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:128 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 128, 0, x3, 117*FLEN/8, x4, x1, x2)

inst_40:
// fs1 == 0 and fe1 == 0x0d and fm1 == 0x1f6 and fs2 == 0 and fe2 == 0x0c and fm2 == 0x07d and fs3 == 0 and fe3 == 0x0a and fm3 == 0x2b1 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x35f6; op2val:0x307d;
op3val:0x2ab1; valaddr_reg:x3; val_offset:120*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 120*FLEN/8, x4, x1, x2)

inst_41:
// fs1 == 0 and fe1 == 0x0d and fm1 == 0x1f6 and fs2 == 0 and fe2 == 0x0c and fm2 == 0x07d and fs3 == 0 and fe3 == 0x0a and fm3 == 0x2b1 and fcsr == 0x20 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x35f6; op2val:0x307d;
op3val:0x2ab1; valaddr_reg:x3; val_offset:123*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:32 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 32, 0, x3, 123*FLEN/8, x4, x1, x2)

inst_42:
// fs1 == 0 and fe1 == 0x0d and fm1 == 0x1f6 and fs2 == 0 and fe2 == 0x0c and fm2 == 0x07d and fs3 == 0 and fe3 == 0x0a and fm3 == 0x2b1 and fcsr == 0x40 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x35f6; op2val:0x307d;
op3val:0x2ab1; valaddr_reg:x3; val_offset:126*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:64 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 64, 0, x3, 126*FLEN/8, x4, x1, x2)

inst_43:
// fs1 == 0 and fe1 == 0x0d and fm1 == 0x1f6 and fs2 == 0 and fe2 == 0x0c and fm2 == 0x07d and fs3 == 0 and fe3 == 0x0a and fm3 == 0x2b1 and fcsr == 0x60 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x35f6; op2val:0x307d;
op3val:0x2ab1; valaddr_reg:x3; val_offset:129*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 96, 0, x3, 129*FLEN/8, x4, x1, x2)

inst_44:
// fs1 == 0 and fe1 == 0x0d and fm1 == 0x1f6 and fs2 == 0 and fe2 == 0x0c and fm2 == 0x07d and fs3 == 0 and fe3 == 0x0a and fm3 == 0x2b1 and fcsr == 0x80 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x35f6; op2val:0x307d;
op3val:0x2ab1; valaddr_reg:x3; val_offset:132*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:128 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 128, 0, x3, 132*FLEN/8, x4, x1, x2)

inst_45:
// fs1 == 0 and fe1 == 0x0d and fm1 == 0x2c4 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x1b4 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x0d3 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x36c4; op2val:0x3db4;
op3val:0x38d3; valaddr_reg:x3; val_offset:135*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 135*FLEN/8, x4, x1, x2)

inst_46:
// fs1 == 0 and fe1 == 0x0d and fm1 == 0x2c4 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x1b4 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x0d3 and fcsr == 0x20 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x36c4; op2val:0x3db4;
op3val:0x38d3; valaddr_reg:x3; val_offset:138*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:32 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 32, 0, x3, 138*FLEN/8, x4, x1, x2)

inst_47:
// fs1 == 0 and fe1 == 0x0d and fm1 == 0x2c4 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x1b4 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x0d3 and fcsr == 0x40 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x36c4; op2val:0x3db4;
op3val:0x38d3; valaddr_reg:x3; val_offset:141*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:64 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 64, 0, x3, 141*FLEN/8, x4, x1, x2)

inst_48:
// fs1 == 0 and fe1 == 0x0d and fm1 == 0x2c4 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x1b4 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x0d3 and fcsr == 0x60 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x36c4; op2val:0x3db4;
op3val:0x38d3; valaddr_reg:x3; val_offset:144*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 96, 0, x3, 144*FLEN/8, x4, x1, x2)

inst_49:
// fs1 == 0 and fe1 == 0x0d and fm1 == 0x2c4 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x1b4 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x0d3 and fcsr == 0x80 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x36c4; op2val:0x3db4;
op3val:0x38d3; valaddr_reg:x3; val_offset:147*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:128 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 128, 0, x3, 147*FLEN/8, x4, x1, x2)

inst_50:
// fs1 == 0 and fe1 == 0x09 and fm1 == 0x214 and fs2 == 0 and fe2 == 0x14 and fm2 == 0x104 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x3a0 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x2614; op2val:0x5104;
op3val:0x3ba0; valaddr_reg:x3; val_offset:150*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 150*FLEN/8, x4, x1, x2)

inst_51:
// fs1 == 0 and fe1 == 0x09 and fm1 == 0x214 and fs2 == 0 and fe2 == 0x14 and fm2 == 0x104 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x3a0 and fcsr == 0x20 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x2614; op2val:0x5104;
op3val:0x3ba0; valaddr_reg:x3; val_offset:153*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:32 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 32, 0, x3, 153*FLEN/8, x4, x1, x2)

inst_52:
// fs1 == 0 and fe1 == 0x09 and fm1 == 0x214 and fs2 == 0 and fe2 == 0x14 and fm2 == 0x104 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x3a0 and fcsr == 0x40 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x2614; op2val:0x5104;
op3val:0x3ba0; valaddr_reg:x3; val_offset:156*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:64 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 64, 0, x3, 156*FLEN/8, x4, x1, x2)

inst_53:
// fs1 == 0 and fe1 == 0x09 and fm1 == 0x214 and fs2 == 0 and fe2 == 0x14 and fm2 == 0x104 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x3a0 and fcsr == 0x60 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x2614; op2val:0x5104;
op3val:0x3ba0; valaddr_reg:x3; val_offset:159*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 96, 0, x3, 159*FLEN/8, x4, x1, x2)

inst_54:
// fs1 == 0 and fe1 == 0x09 and fm1 == 0x214 and fs2 == 0 and fe2 == 0x14 and fm2 == 0x104 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x3a0 and fcsr == 0x80 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x2614; op2val:0x5104;
op3val:0x3ba0; valaddr_reg:x3; val_offset:162*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:128 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 128, 0, x3, 162*FLEN/8, x4, x1, x2)

inst_55:
// fs1 == 0 and fe1 == 0x0c and fm1 == 0x087 and fs2 == 0 and fe2 == 0x11 and fm2 == 0x104 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x1ae and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3087; op2val:0x4504;
op3val:0x39ae; valaddr_reg:x3; val_offset:165*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 165*FLEN/8, x4, x1, x2)

inst_56:
// fs1 == 0 and fe1 == 0x0c and fm1 == 0x087 and fs2 == 0 and fe2 == 0x11 and fm2 == 0x104 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x1ae and fcsr == 0x20 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3087; op2val:0x4504;
op3val:0x39ae; valaddr_reg:x3; val_offset:168*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:32 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 32, 0, x3, 168*FLEN/8, x4, x1, x2)

inst_57:
// fs1 == 0 and fe1 == 0x0c and fm1 == 0x087 and fs2 == 0 and fe2 == 0x11 and fm2 == 0x104 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x1ae and fcsr == 0x40 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3087; op2val:0x4504;
op3val:0x39ae; valaddr_reg:x3; val_offset:171*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:64 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 64, 0, x3, 171*FLEN/8, x4, x1, x2)

inst_58:
// fs1 == 0 and fe1 == 0x0c and fm1 == 0x087 and fs2 == 0 and fe2 == 0x11 and fm2 == 0x104 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x1ae and fcsr == 0x60 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3087; op2val:0x4504;
op3val:0x39ae; valaddr_reg:x3; val_offset:174*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 96, 0, x3, 174*FLEN/8, x4, x1, x2)

inst_59:
// fs1 == 0 and fe1 == 0x0c and fm1 == 0x087 and fs2 == 0 and fe2 == 0x11 and fm2 == 0x104 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x1ae and fcsr == 0x80 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3087; op2val:0x4504;
op3val:0x39ae; valaddr_reg:x3; val_offset:177*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:128 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 128, 0, x3, 177*FLEN/8, x4, x1, x2)

inst_60:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x2d8 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x01f and fs3 == 0 and fe3 == 0x0e and fm3 == 0x30e and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3ad8; op2val:0x3c1f;
op3val:0x3b0e; valaddr_reg:x3; val_offset:180*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 180*FLEN/8, x4, x1, x2)

inst_61:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x2d8 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x01f and fs3 == 0 and fe3 == 0x0e and fm3 == 0x30e and fcsr == 0x20 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3ad8; op2val:0x3c1f;
op3val:0x3b0e; valaddr_reg:x3; val_offset:183*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:32 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 32, 0, x3, 183*FLEN/8, x4, x1, x2)

inst_62:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x2d8 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x01f and fs3 == 0 and fe3 == 0x0e and fm3 == 0x30e and fcsr == 0x40 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3ad8; op2val:0x3c1f;
op3val:0x3b0e; valaddr_reg:x3; val_offset:186*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:64 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 64, 0, x3, 186*FLEN/8, x4, x1, x2)

inst_63:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x2d8 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x01f and fs3 == 0 and fe3 == 0x0e and fm3 == 0x30e and fcsr == 0x60 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3ad8; op2val:0x3c1f;
op3val:0x3b0e; valaddr_reg:x3; val_offset:189*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 96, 0, x3, 189*FLEN/8, x4, x1, x2)

inst_64:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x2d8 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x01f and fs3 == 0 and fe3 == 0x0e and fm3 == 0x30e and fcsr == 0x80 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3ad8; op2val:0x3c1f;
op3val:0x3b0e; valaddr_reg:x3; val_offset:192*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:128 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 128, 0, x3, 192*FLEN/8, x4, x1, x2)

inst_65:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x188 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x041 and fs3 == 0 and fe3 == 0x0c and fm3 == 0x1e2 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3988; op2val:0x3441;
op3val:0x31e2; valaddr_reg:x3; val_offset:195*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 195*FLEN/8, x4, x1, x2)

inst_66:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x188 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x041 and fs3 == 0 and fe3 == 0x0c and fm3 == 0x1e2 and fcsr == 0x20 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3988; op2val:0x3441;
op3val:0x31e2; valaddr_reg:x3; val_offset:198*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:32 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 32, 0, x3, 198*FLEN/8, x4, x1, x2)

inst_67:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x188 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x041 and fs3 == 0 and fe3 == 0x0c and fm3 == 0x1e2 and fcsr == 0x40 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3988; op2val:0x3441;
op3val:0x31e2; valaddr_reg:x3; val_offset:201*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:64 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 64, 0, x3, 201*FLEN/8, x4, x1, x2)

inst_68:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x188 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x041 and fs3 == 0 and fe3 == 0x0c and fm3 == 0x1e2 and fcsr == 0x60 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3988; op2val:0x3441;
op3val:0x31e2; valaddr_reg:x3; val_offset:204*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 96, 0, x3, 204*FLEN/8, x4, x1, x2)

inst_69:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x188 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x041 and fs3 == 0 and fe3 == 0x0c and fm3 == 0x1e2 and fcsr == 0x80 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3988; op2val:0x3441;
op3val:0x31e2; valaddr_reg:x3; val_offset:207*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:128 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 128, 0, x3, 207*FLEN/8, x4, x1, x2)

inst_70:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x28d and fs2 == 0 and fe2 == 0x0e and fm2 == 0x015 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x2b1 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3a8d; op2val:0x3815;
op3val:0x36b1; valaddr_reg:x3; val_offset:210*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 210*FLEN/8, x4, x1, x2)

inst_71:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x28d and fs2 == 0 and fe2 == 0x0e and fm2 == 0x015 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x2b1 and fcsr == 0x20 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3a8d; op2val:0x3815;
op3val:0x36b1; valaddr_reg:x3; val_offset:213*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:32 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 32, 0, x3, 213*FLEN/8, x4, x1, x2)

inst_72:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x28d and fs2 == 0 and fe2 == 0x0e and fm2 == 0x015 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x2b1 and fcsr == 0x40 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3a8d; op2val:0x3815;
op3val:0x36b1; valaddr_reg:x3; val_offset:216*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:64 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 64, 0, x3, 216*FLEN/8, x4, x1, x2)

inst_73:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x28d and fs2 == 0 and fe2 == 0x0e and fm2 == 0x015 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x2b1 and fcsr == 0x60 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3a8d; op2val:0x3815;
op3val:0x36b1; valaddr_reg:x3; val_offset:219*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 96, 0, x3, 219*FLEN/8, x4, x1, x2)

inst_74:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x28d and fs2 == 0 and fe2 == 0x0e and fm2 == 0x015 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x2b1 and fcsr == 0x80 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3a8d; op2val:0x3815;
op3val:0x36b1; valaddr_reg:x3; val_offset:222*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:128 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 128, 0, x3, 222*FLEN/8, x4, x1, x2)

inst_75:
// fs1 == 0 and fe1 == 0x0d and fm1 == 0x1c7 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x2f3 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x105 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x35c7; op2val:0x3ef3;
op3val:0x3905; valaddr_reg:x3; val_offset:225*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 225*FLEN/8, x4, x1, x2)

inst_76:
// fs1 == 0 and fe1 == 0x0d and fm1 == 0x1c7 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x2f3 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x105 and fcsr == 0x20 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x35c7; op2val:0x3ef3;
op3val:0x3905; valaddr_reg:x3; val_offset:228*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:32 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 32, 0, x3, 228*FLEN/8, x4, x1, x2)

inst_77:
// fs1 == 0 and fe1 == 0x0d and fm1 == 0x1c7 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x2f3 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x105 and fcsr == 0x40 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x35c7; op2val:0x3ef3;
op3val:0x3905; valaddr_reg:x3; val_offset:231*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:64 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 64, 0, x3, 231*FLEN/8, x4, x1, x2)

inst_78:
// fs1 == 0 and fe1 == 0x0d and fm1 == 0x1c7 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x2f3 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x105 and fcsr == 0x60 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x35c7; op2val:0x3ef3;
op3val:0x3905; valaddr_reg:x3; val_offset:234*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 96, 0, x3, 234*FLEN/8, x4, x1, x2)

inst_79:
// fs1 == 0 and fe1 == 0x0d and fm1 == 0x1c7 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x2f3 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x105 and fcsr == 0x80 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x35c7; op2val:0x3ef3;
op3val:0x3905; valaddr_reg:x3; val_offset:237*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:128 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 128, 0, x3, 237*FLEN/8, x4, x1, x2)

inst_80:
// fs1 == 0 and fe1 == 0x0d and fm1 == 0x33c and fs2 == 0 and fe2 == 0x10 and fm2 == 0x025 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x37f and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x373c; op2val:0x4025;
op3val:0x3b7f; valaddr_reg:x3; val_offset:240*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 240*FLEN/8, x4, x1, x2)

inst_81:
// fs1 == 0 and fe1 == 0x0d and fm1 == 0x33c and fs2 == 0 and fe2 == 0x10 and fm2 == 0x025 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x37f and fcsr == 0x20 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x373c; op2val:0x4025;
op3val:0x3b7f; valaddr_reg:x3; val_offset:243*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:32 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 32, 0, x3, 243*FLEN/8, x4, x1, x2)

inst_82:
// fs1 == 0 and fe1 == 0x0d and fm1 == 0x33c and fs2 == 0 and fe2 == 0x10 and fm2 == 0x025 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x37f and fcsr == 0x40 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x373c; op2val:0x4025;
op3val:0x3b7f; valaddr_reg:x3; val_offset:246*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:64 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 64, 0, x3, 246*FLEN/8, x4, x1, x2)

inst_83:
// fs1 == 0 and fe1 == 0x0d and fm1 == 0x33c and fs2 == 0 and fe2 == 0x10 and fm2 == 0x025 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x37f and fcsr == 0x60 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x373c; op2val:0x4025;
op3val:0x3b7f; valaddr_reg:x3; val_offset:249*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 96, 0, x3, 249*FLEN/8, x4, x1, x2)

inst_84:
// fs1 == 0 and fe1 == 0x0d and fm1 == 0x33c and fs2 == 0 and fe2 == 0x10 and fm2 == 0x025 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x37f and fcsr == 0x80 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x373c; op2val:0x4025;
op3val:0x3b7f; valaddr_reg:x3; val_offset:252*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:128 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 128, 0, x3, 252*FLEN/8, x4, x1, x2)

inst_85:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x385 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x2c1 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x25a and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3b85; op2val:0x3ac1;
op3val:0x3a5a; valaddr_reg:x3; val_offset:255*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 255*FLEN/8, x4, x1, x2)

inst_86:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x385 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x2c1 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x25a and fcsr == 0x20 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3b85; op2val:0x3ac1;
op3val:0x3a5a; valaddr_reg:x3; val_offset:258*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:32 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 32, 0, x3, 258*FLEN/8, x4, x1, x2)

inst_87:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x385 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x2c1 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x25a and fcsr == 0x40 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3b85; op2val:0x3ac1;
op3val:0x3a5a; valaddr_reg:x3; val_offset:261*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:64 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 64, 0, x3, 261*FLEN/8, x4, x1, x2)

inst_88:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x385 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x2c1 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x25a and fcsr == 0x60 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3b85; op2val:0x3ac1;
op3val:0x3a5a; valaddr_reg:x3; val_offset:264*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 96, 0, x3, 264*FLEN/8, x4, x1, x2)

inst_89:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x385 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x2c1 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x25a and fcsr == 0x80 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3b85; op2val:0x3ac1;
op3val:0x3a5a; valaddr_reg:x3; val_offset:267*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:128 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 128, 0, x3, 267*FLEN/8, x4, x1, x2)

inst_90:
// fs1 == 0 and fe1 == 0x0d and fm1 == 0x11d and fs2 == 0 and fe2 == 0x0f and fm2 == 0x329 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x094 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x351d; op2val:0x3f29;
op3val:0x3894; valaddr_reg:x3; val_offset:270*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 270*FLEN/8, x4, x1, x2)

inst_91:
// fs1 == 0 and fe1 == 0x0d and fm1 == 0x11d and fs2 == 0 and fe2 == 0x0f and fm2 == 0x329 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x094 and fcsr == 0x20 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x351d; op2val:0x3f29;
op3val:0x3894; valaddr_reg:x3; val_offset:273*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:32 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 32, 0, x3, 273*FLEN/8, x4, x1, x2)

inst_92:
// fs1 == 0 and fe1 == 0x0d and fm1 == 0x11d and fs2 == 0 and fe2 == 0x0f and fm2 == 0x329 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x094 and fcsr == 0x40 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x351d; op2val:0x3f29;
op3val:0x3894; valaddr_reg:x3; val_offset:276*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:64 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 64, 0, x3, 276*FLEN/8, x4, x1, x2)

inst_93:
// fs1 == 0 and fe1 == 0x0d and fm1 == 0x11d and fs2 == 0 and fe2 == 0x0f and fm2 == 0x329 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x094 and fcsr == 0x60 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x351d; op2val:0x3f29;
op3val:0x3894; valaddr_reg:x3; val_offset:279*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 96, 0, x3, 279*FLEN/8, x4, x1, x2)

inst_94:
// fs1 == 0 and fe1 == 0x0d and fm1 == 0x11d and fs2 == 0 and fe2 == 0x0f and fm2 == 0x329 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x094 and fcsr == 0x80 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x351d; op2val:0x3f29;
op3val:0x3894; valaddr_reg:x3; val_offset:282*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:128 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 128, 0, x3, 282*FLEN/8, x4, x1, x2)

inst_95:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x17c and fs2 == 0 and fe2 == 0x0e and fm2 == 0x0d5 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x2a1 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x397c; op2val:0x38d5;
op3val:0x36a1; valaddr_reg:x3; val_offset:285*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 285*FLEN/8, x4, x1, x2)

inst_96:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x17c and fs2 == 0 and fe2 == 0x0e and fm2 == 0x0d5 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x2a1 and fcsr == 0x20 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x397c; op2val:0x38d5;
op3val:0x36a1; valaddr_reg:x3; val_offset:288*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:32 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 32, 0, x3, 288*FLEN/8, x4, x1, x2)

inst_97:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x17c and fs2 == 0 and fe2 == 0x0e and fm2 == 0x0d5 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x2a1 and fcsr == 0x40 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x397c; op2val:0x38d5;
op3val:0x36a1; valaddr_reg:x3; val_offset:291*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:64 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 64, 0, x3, 291*FLEN/8, x4, x1, x2)

inst_98:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x17c and fs2 == 0 and fe2 == 0x0e and fm2 == 0x0d5 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x2a1 and fcsr == 0x60 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x397c; op2val:0x38d5;
op3val:0x36a1; valaddr_reg:x3; val_offset:294*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 96, 0, x3, 294*FLEN/8, x4, x1, x2)

inst_99:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x17c and fs2 == 0 and fe2 == 0x0e and fm2 == 0x0d5 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x2a1 and fcsr == 0x80 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x397c; op2val:0x38d5;
op3val:0x36a1; valaddr_reg:x3; val_offset:297*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:128 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 128, 0, x3, 297*FLEN/8, x4, x1, x2)

inst_100:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x05f and fs2 == 0 and fe2 == 0x0f and fm2 == 0x11f and fs3 == 0 and fe3 == 0x0e and fm3 == 0x19a and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x385f; op2val:0x3d1f;
op3val:0x399a; valaddr_reg:x3; val_offset:300*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 300*FLEN/8, x4, x1, x2)

inst_101:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x05f and fs2 == 0 and fe2 == 0x0f and fm2 == 0x11f and fs3 == 0 and fe3 == 0x0e and fm3 == 0x19a and fcsr == 0x20 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x385f; op2val:0x3d1f;
op3val:0x399a; valaddr_reg:x3; val_offset:303*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:32 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 32, 0, x3, 303*FLEN/8, x4, x1, x2)

inst_102:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x05f and fs2 == 0 and fe2 == 0x0f and fm2 == 0x11f and fs3 == 0 and fe3 == 0x0e and fm3 == 0x19a and fcsr == 0x40 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x385f; op2val:0x3d1f;
op3val:0x399a; valaddr_reg:x3; val_offset:306*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:64 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 64, 0, x3, 306*FLEN/8, x4, x1, x2)

inst_103:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x05f and fs2 == 0 and fe2 == 0x0f and fm2 == 0x11f and fs3 == 0 and fe3 == 0x0e and fm3 == 0x19a and fcsr == 0x60 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x385f; op2val:0x3d1f;
op3val:0x399a; valaddr_reg:x3; val_offset:309*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 96, 0, x3, 309*FLEN/8, x4, x1, x2)

inst_104:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x05f and fs2 == 0 and fe2 == 0x0f and fm2 == 0x11f and fs3 == 0 and fe3 == 0x0e and fm3 == 0x19a and fcsr == 0x80 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x385f; op2val:0x3d1f;
op3val:0x399a; valaddr_reg:x3; val_offset:312*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:128 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 128, 0, x3, 312*FLEN/8, x4, x1, x2)

inst_105:
// fs1 == 0 and fe1 == 0x0c and fm1 == 0x294 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x1db and fs3 == 0 and fe3 == 0x0d and fm3 == 0x0d0 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3294; op2val:0x3ddb;
op3val:0x34d0; valaddr_reg:x3; val_offset:315*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 315*FLEN/8, x4, x1, x2)

inst_106:
// fs1 == 0 and fe1 == 0x0c and fm1 == 0x294 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x1db and fs3 == 0 and fe3 == 0x0d and fm3 == 0x0d0 and fcsr == 0x20 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3294; op2val:0x3ddb;
op3val:0x34d0; valaddr_reg:x3; val_offset:318*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:32 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 32, 0, x3, 318*FLEN/8, x4, x1, x2)

inst_107:
// fs1 == 0 and fe1 == 0x0c and fm1 == 0x294 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x1db and fs3 == 0 and fe3 == 0x0d and fm3 == 0x0d0 and fcsr == 0x40 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3294; op2val:0x3ddb;
op3val:0x34d0; valaddr_reg:x3; val_offset:321*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:64 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 64, 0, x3, 321*FLEN/8, x4, x1, x2)

inst_108:
// fs1 == 0 and fe1 == 0x0c and fm1 == 0x294 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x1db and fs3 == 0 and fe3 == 0x0d and fm3 == 0x0d0 and fcsr == 0x60 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3294; op2val:0x3ddb;
op3val:0x34d0; valaddr_reg:x3; val_offset:324*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 96, 0, x3, 324*FLEN/8, x4, x1, x2)

inst_109:
// fs1 == 0 and fe1 == 0x0c and fm1 == 0x294 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x1db and fs3 == 0 and fe3 == 0x0d and fm3 == 0x0d0 and fcsr == 0x80 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3294; op2val:0x3ddb;
op3val:0x34d0; valaddr_reg:x3; val_offset:327*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:128 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 128, 0, x3, 327*FLEN/8, x4, x1, x2)

inst_110:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x20c and fs2 == 0 and fe2 == 0x0e and fm2 == 0x081 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x2cf and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3a0c; op2val:0x3881;
op3val:0x36cf; valaddr_reg:x3; val_offset:330*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 330*FLEN/8, x4, x1, x2)

inst_111:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x20c and fs2 == 0 and fe2 == 0x0e and fm2 == 0x081 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x2cf and fcsr == 0x20 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3a0c; op2val:0x3881;
op3val:0x36cf; valaddr_reg:x3; val_offset:333*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:32 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 32, 0, x3, 333*FLEN/8, x4, x1, x2)

inst_112:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x20c and fs2 == 0 and fe2 == 0x0e and fm2 == 0x081 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x2cf and fcsr == 0x40 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3a0c; op2val:0x3881;
op3val:0x36cf; valaddr_reg:x3; val_offset:336*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:64 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 64, 0, x3, 336*FLEN/8, x4, x1, x2)

inst_113:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x20c and fs2 == 0 and fe2 == 0x0e and fm2 == 0x081 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x2cf and fcsr == 0x60 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3a0c; op2val:0x3881;
op3val:0x36cf; valaddr_reg:x3; val_offset:339*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 96, 0, x3, 339*FLEN/8, x4, x1, x2)

inst_114:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x20c and fs2 == 0 and fe2 == 0x0e and fm2 == 0x081 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x2cf and fcsr == 0x80 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3a0c; op2val:0x3881;
op3val:0x36cf; valaddr_reg:x3; val_offset:342*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:128 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 128, 0, x3, 342*FLEN/8, x4, x1, x2)

inst_115:
// fs1 == 0 and fe1 == 0x0d and fm1 == 0x398 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x035 and fs3 == 0 and fe3 == 0x0b and fm3 == 0x3fd and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3798; op2val:0x3435;
op3val:0x2ffd; valaddr_reg:x3; val_offset:345*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 345*FLEN/8, x4, x1, x2)

inst_116:
// fs1 == 0 and fe1 == 0x0d and fm1 == 0x398 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x035 and fs3 == 0 and fe3 == 0x0b and fm3 == 0x3fd and fcsr == 0x20 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3798; op2val:0x3435;
op3val:0x2ffd; valaddr_reg:x3; val_offset:348*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:32 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 32, 0, x3, 348*FLEN/8, x4, x1, x2)

inst_117:
// fs1 == 0 and fe1 == 0x0d and fm1 == 0x398 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x035 and fs3 == 0 and fe3 == 0x0b and fm3 == 0x3fd and fcsr == 0x40 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3798; op2val:0x3435;
op3val:0x2ffd; valaddr_reg:x3; val_offset:351*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:64 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 64, 0, x3, 351*FLEN/8, x4, x1, x2)

inst_118:
// fs1 == 0 and fe1 == 0x0d and fm1 == 0x398 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x035 and fs3 == 0 and fe3 == 0x0b and fm3 == 0x3fd and fcsr == 0x60 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3798; op2val:0x3435;
op3val:0x2ffd; valaddr_reg:x3; val_offset:354*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 96, 0, x3, 354*FLEN/8, x4, x1, x2)

inst_119:
// fs1 == 0 and fe1 == 0x0d and fm1 == 0x398 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x035 and fs3 == 0 and fe3 == 0x0b and fm3 == 0x3fd and fcsr == 0x80 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3798; op2val:0x3435;
op3val:0x2ffd; valaddr_reg:x3; val_offset:357*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:128 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 128, 0, x3, 357*FLEN/8, x4, x1, x2)

inst_120:
// fs1 == 0 and fe1 == 0x0d and fm1 == 0x054 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x143 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x1b2 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3454; op2val:0x4143;
op3val:0x39b2; valaddr_reg:x3; val_offset:360*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 360*FLEN/8, x4, x1, x2)

inst_121:
// fs1 == 0 and fe1 == 0x0d and fm1 == 0x054 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x143 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x1b2 and fcsr == 0x20 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3454; op2val:0x4143;
op3val:0x39b2; valaddr_reg:x3; val_offset:363*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:32 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 32, 0, x3, 363*FLEN/8, x4, x1, x2)

inst_122:
// fs1 == 0 and fe1 == 0x0d and fm1 == 0x054 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x143 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x1b2 and fcsr == 0x40 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3454; op2val:0x4143;
op3val:0x39b2; valaddr_reg:x3; val_offset:366*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:64 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 64, 0, x3, 366*FLEN/8, x4, x1, x2)

inst_123:
// fs1 == 0 and fe1 == 0x0d and fm1 == 0x054 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x143 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x1b2 and fcsr == 0x60 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3454; op2val:0x4143;
op3val:0x39b2; valaddr_reg:x3; val_offset:369*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 96, 0, x3, 369*FLEN/8, x4, x1, x2)

inst_124:
// fs1 == 0 and fe1 == 0x0d and fm1 == 0x054 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x143 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x1b2 and fcsr == 0x80 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3454; op2val:0x4143;
op3val:0x39b2; valaddr_reg:x3; val_offset:372*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:128 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 128, 0, x3, 372*FLEN/8, x4, x1, x2)

inst_125:
// fs1 == 0 and fe1 == 0x09 and fm1 == 0x113 and fs2 == 0 and fe2 == 0x14 and fm2 == 0x18f and fs3 == 0 and fe3 == 0x0e and fm3 == 0x30e and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x2513; op2val:0x518f;
op3val:0x3b0e; valaddr_reg:x3; val_offset:375*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 375*FLEN/8, x4, x1, x2)

inst_126:
// fs1 == 0 and fe1 == 0x09 and fm1 == 0x113 and fs2 == 0 and fe2 == 0x14 and fm2 == 0x18f and fs3 == 0 and fe3 == 0x0e and fm3 == 0x30e and fcsr == 0x20 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x2513; op2val:0x518f;
op3val:0x3b0e; valaddr_reg:x3; val_offset:378*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:32 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 32, 0, x3, 378*FLEN/8, x4, x1, x2)

inst_127:
// fs1 == 0 and fe1 == 0x09 and fm1 == 0x113 and fs2 == 0 and fe2 == 0x14 and fm2 == 0x18f and fs3 == 0 and fe3 == 0x0e and fm3 == 0x30e and fcsr == 0x40 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x2513; op2val:0x518f;
op3val:0x3b0e; valaddr_reg:x3; val_offset:381*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:64 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 64, 0, x3, 381*FLEN/8, x4, x1, x2)
RVTEST_SIGBASE(x1,signature_x1_2)

inst_128:
// fs1 == 0 and fe1 == 0x09 and fm1 == 0x113 and fs2 == 0 and fe2 == 0x14 and fm2 == 0x18f and fs3 == 0 and fe3 == 0x0e and fm3 == 0x30e and fcsr == 0x60 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x2513; op2val:0x518f;
op3val:0x3b0e; valaddr_reg:x3; val_offset:384*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 96, 0, x3, 384*FLEN/8, x4, x1, x2)

inst_129:
// fs1 == 0 and fe1 == 0x09 and fm1 == 0x113 and fs2 == 0 and fe2 == 0x14 and fm2 == 0x18f and fs3 == 0 and fe3 == 0x0e and fm3 == 0x30e and fcsr == 0x80 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x2513; op2val:0x518f;
op3val:0x3b0e; valaddr_reg:x3; val_offset:387*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:128 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 128, 0, x3, 387*FLEN/8, x4, x1, x2)

inst_130:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x0a7 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x2ad and fs3 == 0 and fe3 == 0x0c and fm3 == 0x3c5 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x38a7; op2val:0x36ad;
op3val:0x33c5; valaddr_reg:x3; val_offset:390*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 390*FLEN/8, x4, x1, x2)

inst_131:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x0a7 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x2ad and fs3 == 0 and fe3 == 0x0c and fm3 == 0x3c5 and fcsr == 0x20 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x38a7; op2val:0x36ad;
op3val:0x33c5; valaddr_reg:x3; val_offset:393*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:32 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 32, 0, x3, 393*FLEN/8, x4, x1, x2)

inst_132:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x0a7 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x2ad and fs3 == 0 and fe3 == 0x0c and fm3 == 0x3c5 and fcsr == 0x40 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x38a7; op2val:0x36ad;
op3val:0x33c5; valaddr_reg:x3; val_offset:396*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:64 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 64, 0, x3, 396*FLEN/8, x4, x1, x2)

inst_133:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x0a7 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x2ad and fs3 == 0 and fe3 == 0x0c and fm3 == 0x3c5 and fcsr == 0x60 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x38a7; op2val:0x36ad;
op3val:0x33c5; valaddr_reg:x3; val_offset:399*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 96, 0, x3, 399*FLEN/8, x4, x1, x2)

inst_134:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x0a7 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x2ad and fs3 == 0 and fe3 == 0x0c and fm3 == 0x3c5 and fcsr == 0x80 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x38a7; op2val:0x36ad;
op3val:0x33c5; valaddr_reg:x3; val_offset:402*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:128 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 128, 0, x3, 402*FLEN/8, x4, x1, x2)

inst_135:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x2c8 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x0d2 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x016 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3ac8; op2val:0x38d2;
op3val:0x3816; valaddr_reg:x3; val_offset:405*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 405*FLEN/8, x4, x1, x2)

inst_136:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x2c8 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x0d2 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x016 and fcsr == 0x20 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3ac8; op2val:0x38d2;
op3val:0x3816; valaddr_reg:x3; val_offset:408*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:32 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 32, 0, x3, 408*FLEN/8, x4, x1, x2)

inst_137:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x2c8 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x0d2 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x016 and fcsr == 0x40 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3ac8; op2val:0x38d2;
op3val:0x3816; valaddr_reg:x3; val_offset:411*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:64 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 64, 0, x3, 411*FLEN/8, x4, x1, x2)

inst_138:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x2c8 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x0d2 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x016 and fcsr == 0x60 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3ac8; op2val:0x38d2;
op3val:0x3816; valaddr_reg:x3; val_offset:414*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 96, 0, x3, 414*FLEN/8, x4, x1, x2)

inst_139:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x2c8 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x0d2 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x016 and fcsr == 0x80 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3ac8; op2val:0x38d2;
op3val:0x3816; valaddr_reg:x3; val_offset:417*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:128 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 128, 0, x3, 417*FLEN/8, x4, x1, x2)

inst_140:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x3af and fs2 == 0 and fe2 == 0x0d and fm2 == 0x186 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x14e and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3baf; op2val:0x3586;
op3val:0x354e; valaddr_reg:x3; val_offset:420*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 420*FLEN/8, x4, x1, x2)

inst_141:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x3af and fs2 == 0 and fe2 == 0x0d and fm2 == 0x186 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x14e and fcsr == 0x20 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3baf; op2val:0x3586;
op3val:0x354e; valaddr_reg:x3; val_offset:423*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:32 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 32, 0, x3, 423*FLEN/8, x4, x1, x2)

inst_142:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x3af and fs2 == 0 and fe2 == 0x0d and fm2 == 0x186 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x14e and fcsr == 0x40 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3baf; op2val:0x3586;
op3val:0x354e; valaddr_reg:x3; val_offset:426*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:64 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 64, 0, x3, 426*FLEN/8, x4, x1, x2)

inst_143:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x3af and fs2 == 0 and fe2 == 0x0d and fm2 == 0x186 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x14e and fcsr == 0x60 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3baf; op2val:0x3586;
op3val:0x354e; valaddr_reg:x3; val_offset:429*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 96, 0, x3, 429*FLEN/8, x4, x1, x2)

inst_144:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x3af and fs2 == 0 and fe2 == 0x0d and fm2 == 0x186 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x14e and fcsr == 0x80 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3baf; op2val:0x3586;
op3val:0x354e; valaddr_reg:x3; val_offset:432*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:128 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 128, 0, x3, 432*FLEN/8, x4, x1, x2)

inst_145:
// fs1 == 0 and fe1 == 0x0c and fm1 == 0x388 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x341 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x2d4 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3388; op2val:0x3f41;
op3val:0x36d4; valaddr_reg:x3; val_offset:435*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 435*FLEN/8, x4, x1, x2)

inst_146:
// fs1 == 0 and fe1 == 0x0c and fm1 == 0x388 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x341 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x2d4 and fcsr == 0x20 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3388; op2val:0x3f41;
op3val:0x36d4; valaddr_reg:x3; val_offset:438*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:32 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 32, 0, x3, 438*FLEN/8, x4, x1, x2)

inst_147:
// fs1 == 0 and fe1 == 0x0c and fm1 == 0x388 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x341 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x2d4 and fcsr == 0x40 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3388; op2val:0x3f41;
op3val:0x36d4; valaddr_reg:x3; val_offset:441*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:64 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 64, 0, x3, 441*FLEN/8, x4, x1, x2)

inst_148:
// fs1 == 0 and fe1 == 0x0c and fm1 == 0x388 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x341 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x2d4 and fcsr == 0x60 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3388; op2val:0x3f41;
op3val:0x36d4; valaddr_reg:x3; val_offset:444*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 96, 0, x3, 444*FLEN/8, x4, x1, x2)

inst_149:
// fs1 == 0 and fe1 == 0x0c and fm1 == 0x388 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x341 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x2d4 and fcsr == 0x80 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3388; op2val:0x3f41;
op3val:0x36d4; valaddr_reg:x3; val_offset:447*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:128 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 128, 0, x3, 447*FLEN/8, x4, x1, x2)

inst_150:
// fs1 == 0 and fe1 == 0x0b and fm1 == 0x3f8 and fs2 == 0 and fe2 == 0x11 and fm2 == 0x182 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x17d and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x2ff8; op2val:0x4582;
op3val:0x397d; valaddr_reg:x3; val_offset:450*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 450*FLEN/8, x4, x1, x2)

inst_151:
// fs1 == 0 and fe1 == 0x0b and fm1 == 0x3f8 and fs2 == 0 and fe2 == 0x11 and fm2 == 0x182 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x17d and fcsr == 0x20 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x2ff8; op2val:0x4582;
op3val:0x397d; valaddr_reg:x3; val_offset:453*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:32 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 32, 0, x3, 453*FLEN/8, x4, x1, x2)

inst_152:
// fs1 == 0 and fe1 == 0x0b and fm1 == 0x3f8 and fs2 == 0 and fe2 == 0x11 and fm2 == 0x182 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x17d and fcsr == 0x40 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x2ff8; op2val:0x4582;
op3val:0x397d; valaddr_reg:x3; val_offset:456*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:64 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 64, 0, x3, 456*FLEN/8, x4, x1, x2)

inst_153:
// fs1 == 0 and fe1 == 0x0b and fm1 == 0x3f8 and fs2 == 0 and fe2 == 0x11 and fm2 == 0x182 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x17d and fcsr == 0x60 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x2ff8; op2val:0x4582;
op3val:0x397d; valaddr_reg:x3; val_offset:459*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 96, 0, x3, 459*FLEN/8, x4, x1, x2)

inst_154:
// fs1 == 0 and fe1 == 0x0b and fm1 == 0x3f8 and fs2 == 0 and fe2 == 0x11 and fm2 == 0x182 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x17d and fcsr == 0x80 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x2ff8; op2val:0x4582;
op3val:0x397d; valaddr_reg:x3; val_offset:462*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:128 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 128, 0, x3, 462*FLEN/8, x4, x1, x2)

inst_155:
// fs1 == 0 and fe1 == 0x0d and fm1 == 0x0e0 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x153 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x27d and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x34e0; op2val:0x3d53;
op3val:0x367d; valaddr_reg:x3; val_offset:465*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 465*FLEN/8, x4, x1, x2)

inst_156:
// fs1 == 0 and fe1 == 0x0d and fm1 == 0x0e0 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x153 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x27d and fcsr == 0x20 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x34e0; op2val:0x3d53;
op3val:0x367d; valaddr_reg:x3; val_offset:468*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:32 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 32, 0, x3, 468*FLEN/8, x4, x1, x2)

inst_157:
// fs1 == 0 and fe1 == 0x0d and fm1 == 0x0e0 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x153 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x27d and fcsr == 0x40 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x34e0; op2val:0x3d53;
op3val:0x367d; valaddr_reg:x3; val_offset:471*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:64 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 64, 0, x3, 471*FLEN/8, x4, x1, x2)

inst_158:
// fs1 == 0 and fe1 == 0x0d and fm1 == 0x0e0 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x153 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x27d and fcsr == 0x60 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x34e0; op2val:0x3d53;
op3val:0x367d; valaddr_reg:x3; val_offset:474*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 96, 0, x3, 474*FLEN/8, x4, x1, x2)

inst_159:
// fs1 == 0 and fe1 == 0x0d and fm1 == 0x0e0 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x153 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x27d and fcsr == 0x80 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x34e0; op2val:0x3d53;
op3val:0x367d; valaddr_reg:x3; val_offset:477*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:128 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 128, 0, x3, 477*FLEN/8, x4, x1, x2)

inst_160:
// fs1 == 0 and fe1 == 0x0d and fm1 == 0x2b8 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x12d and fs3 == 0 and fe3 == 0x0e and fm3 == 0x059 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x36b8; op2val:0x3d2d;
op3val:0x3859; valaddr_reg:x3; val_offset:480*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 480*FLEN/8, x4, x1, x2)

inst_161:
// fs1 == 0 and fe1 == 0x0d and fm1 == 0x2b8 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x12d and fs3 == 0 and fe3 == 0x0e and fm3 == 0x059 and fcsr == 0x20 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x36b8; op2val:0x3d2d;
op3val:0x3859; valaddr_reg:x3; val_offset:483*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:32 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 32, 0, x3, 483*FLEN/8, x4, x1, x2)

inst_162:
// fs1 == 0 and fe1 == 0x0d and fm1 == 0x2b8 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x12d and fs3 == 0 and fe3 == 0x0e and fm3 == 0x059 and fcsr == 0x40 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x36b8; op2val:0x3d2d;
op3val:0x3859; valaddr_reg:x3; val_offset:486*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:64 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 64, 0, x3, 486*FLEN/8, x4, x1, x2)

inst_163:
// fs1 == 0 and fe1 == 0x0d and fm1 == 0x2b8 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x12d and fs3 == 0 and fe3 == 0x0e and fm3 == 0x059 and fcsr == 0x60 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x36b8; op2val:0x3d2d;
op3val:0x3859; valaddr_reg:x3; val_offset:489*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 96, 0, x3, 489*FLEN/8, x4, x1, x2)

inst_164:
// fs1 == 0 and fe1 == 0x0d and fm1 == 0x2b8 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x12d and fs3 == 0 and fe3 == 0x0e and fm3 == 0x059 and fcsr == 0x80 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x36b8; op2val:0x3d2d;
op3val:0x3859; valaddr_reg:x3; val_offset:492*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:128 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 128, 0, x3, 492*FLEN/8, x4, x1, x2)

inst_165:
// fs1 == 0 and fe1 == 0x0c and fm1 == 0x11e and fs2 == 0 and fe2 == 0x0d and fm2 == 0x187 and fs3 == 0 and fe3 == 0x0a and fm3 == 0x314 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x311e; op2val:0x3587;
op3val:0x2b14; valaddr_reg:x3; val_offset:495*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 495*FLEN/8, x4, x1, x2)

inst_166:
// fs1 == 0 and fe1 == 0x0c and fm1 == 0x11e and fs2 == 0 and fe2 == 0x0d and fm2 == 0x187 and fs3 == 0 and fe3 == 0x0a and fm3 == 0x314 and fcsr == 0x20 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x311e; op2val:0x3587;
op3val:0x2b14; valaddr_reg:x3; val_offset:498*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:32 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 32, 0, x3, 498*FLEN/8, x4, x1, x2)

inst_167:
// fs1 == 0 and fe1 == 0x0c and fm1 == 0x11e and fs2 == 0 and fe2 == 0x0d and fm2 == 0x187 and fs3 == 0 and fe3 == 0x0a and fm3 == 0x314 and fcsr == 0x40 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x311e; op2val:0x3587;
op3val:0x2b14; valaddr_reg:x3; val_offset:501*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:64 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 64, 0, x3, 501*FLEN/8, x4, x1, x2)

inst_168:
// fs1 == 0 and fe1 == 0x0c and fm1 == 0x11e and fs2 == 0 and fe2 == 0x0d and fm2 == 0x187 and fs3 == 0 and fe3 == 0x0a and fm3 == 0x314 and fcsr == 0x60 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x311e; op2val:0x3587;
op3val:0x2b14; valaddr_reg:x3; val_offset:504*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 96, 0, x3, 504*FLEN/8, x4, x1, x2)

inst_169:
// fs1 == 0 and fe1 == 0x0c and fm1 == 0x11e and fs2 == 0 and fe2 == 0x0d and fm2 == 0x187 and fs3 == 0 and fe3 == 0x0a and fm3 == 0x314 and fcsr == 0x80 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x311e; op2val:0x3587;
op3val:0x2b14; valaddr_reg:x3; val_offset:507*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:128 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 128, 0, x3, 507*FLEN/8, x4, x1, x2)

inst_170:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x035 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x11b and fs3 == 0 and fe3 == 0x0d and fm3 == 0x15f and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3835; op2val:0x391b;
op3val:0x355f; valaddr_reg:x3; val_offset:510*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 510*FLEN/8, x4, x1, x2)

inst_171:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x035 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x11b and fs3 == 0 and fe3 == 0x0d and fm3 == 0x15f and fcsr == 0x20 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3835; op2val:0x391b;
op3val:0x355f; valaddr_reg:x3; val_offset:513*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:32 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 32, 0, x3, 513*FLEN/8, x4, x1, x2)

inst_172:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x035 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x11b and fs3 == 0 and fe3 == 0x0d and fm3 == 0x15f and fcsr == 0x40 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3835; op2val:0x391b;
op3val:0x355f; valaddr_reg:x3; val_offset:516*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:64 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 64, 0, x3, 516*FLEN/8, x4, x1, x2)

inst_173:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x035 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x11b and fs3 == 0 and fe3 == 0x0d and fm3 == 0x15f and fcsr == 0x60 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3835; op2val:0x391b;
op3val:0x355f; valaddr_reg:x3; val_offset:519*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 96, 0, x3, 519*FLEN/8, x4, x1, x2)

inst_174:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x035 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x11b and fs3 == 0 and fe3 == 0x0d and fm3 == 0x15f and fcsr == 0x80 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3835; op2val:0x391b;
op3val:0x355f; valaddr_reg:x3; val_offset:522*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:128 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 128, 0, x3, 522*FLEN/8, x4, x1, x2)

inst_175:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x383 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x115 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x0c6 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3b83; op2val:0x3515;
op3val:0x34c6; valaddr_reg:x3; val_offset:525*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 525*FLEN/8, x4, x1, x2)

inst_176:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x383 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x115 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x0c6 and fcsr == 0x20 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3b83; op2val:0x3515;
op3val:0x34c6; valaddr_reg:x3; val_offset:528*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:32 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 32, 0, x3, 528*FLEN/8, x4, x1, x2)

inst_177:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x383 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x115 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x0c6 and fcsr == 0x40 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3b83; op2val:0x3515;
op3val:0x34c6; valaddr_reg:x3; val_offset:531*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:64 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 64, 0, x3, 531*FLEN/8, x4, x1, x2)

inst_178:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x383 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x115 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x0c6 and fcsr == 0x60 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3b83; op2val:0x3515;
op3val:0x34c6; valaddr_reg:x3; val_offset:534*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 96, 0, x3, 534*FLEN/8, x4, x1, x2)

inst_179:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x383 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x115 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x0c6 and fcsr == 0x80 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3b83; op2val:0x3515;
op3val:0x34c6; valaddr_reg:x3; val_offset:537*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:128 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 128, 0, x3, 537*FLEN/8, x4, x1, x2)

inst_180:
// fs1 == 0 and fe1 == 0x0d and fm1 == 0x1a5 and fs2 == 0 and fe2 == 0x09 and fm2 == 0x102 and fs3 == 0 and fe3 == 0x07 and fm3 == 0x311 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x35a5; op2val:0x2502;
op3val:0x1f11; valaddr_reg:x3; val_offset:540*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 540*FLEN/8, x4, x1, x2)

inst_181:
// fs1 == 0 and fe1 == 0x0d and fm1 == 0x1a5 and fs2 == 0 and fe2 == 0x09 and fm2 == 0x102 and fs3 == 0 and fe3 == 0x07 and fm3 == 0x311 and fcsr == 0x20 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x35a5; op2val:0x2502;
op3val:0x1f11; valaddr_reg:x3; val_offset:543*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:32 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 32, 0, x3, 543*FLEN/8, x4, x1, x2)

inst_182:
// fs1 == 0 and fe1 == 0x0d and fm1 == 0x1a5 and fs2 == 0 and fe2 == 0x09 and fm2 == 0x102 and fs3 == 0 and fe3 == 0x07 and fm3 == 0x311 and fcsr == 0x40 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x35a5; op2val:0x2502;
op3val:0x1f11; valaddr_reg:x3; val_offset:546*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:64 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 64, 0, x3, 546*FLEN/8, x4, x1, x2)

inst_183:
// fs1 == 0 and fe1 == 0x0d and fm1 == 0x1a5 and fs2 == 0 and fe2 == 0x09 and fm2 == 0x102 and fs3 == 0 and fe3 == 0x07 and fm3 == 0x311 and fcsr == 0x60 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x35a5; op2val:0x2502;
op3val:0x1f11; valaddr_reg:x3; val_offset:549*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 96, 0, x3, 549*FLEN/8, x4, x1, x2)

inst_184:
// fs1 == 0 and fe1 == 0x0d and fm1 == 0x1a5 and fs2 == 0 and fe2 == 0x09 and fm2 == 0x102 and fs3 == 0 and fe3 == 0x07 and fm3 == 0x311 and fcsr == 0x80 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x35a5; op2val:0x2502;
op3val:0x1f11; valaddr_reg:x3; val_offset:552*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:128 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 128, 0, x3, 552*FLEN/8, x4, x1, x2)

inst_185:
// fs1 == 0 and fe1 == 0x0c and fm1 == 0x1b2 and fs2 == 0 and fe2 == 0x11 and fm2 == 0x004 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x1b9 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x31b2; op2val:0x4404;
op3val:0x39b9; valaddr_reg:x3; val_offset:555*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 555*FLEN/8, x4, x1, x2)

inst_186:
// fs1 == 0 and fe1 == 0x0c and fm1 == 0x1b2 and fs2 == 0 and fe2 == 0x11 and fm2 == 0x004 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x1b9 and fcsr == 0x20 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x31b2; op2val:0x4404;
op3val:0x39b9; valaddr_reg:x3; val_offset:558*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:32 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 32, 0, x3, 558*FLEN/8, x4, x1, x2)

inst_187:
// fs1 == 0 and fe1 == 0x0c and fm1 == 0x1b2 and fs2 == 0 and fe2 == 0x11 and fm2 == 0x004 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x1b9 and fcsr == 0x40 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x31b2; op2val:0x4404;
op3val:0x39b9; valaddr_reg:x3; val_offset:561*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:64 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 64, 0, x3, 561*FLEN/8, x4, x1, x2)

inst_188:
// fs1 == 0 and fe1 == 0x0c and fm1 == 0x1b2 and fs2 == 0 and fe2 == 0x11 and fm2 == 0x004 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x1b9 and fcsr == 0x60 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x31b2; op2val:0x4404;
op3val:0x39b9; valaddr_reg:x3; val_offset:564*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 96, 0, x3, 564*FLEN/8, x4, x1, x2)

inst_189:
// fs1 == 0 and fe1 == 0x0c and fm1 == 0x1b2 and fs2 == 0 and fe2 == 0x11 and fm2 == 0x004 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x1b9 and fcsr == 0x80 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x31b2; op2val:0x4404;
op3val:0x39b9; valaddr_reg:x3; val_offset:567*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:128 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 128, 0, x3, 567*FLEN/8, x4, x1, x2)

inst_190:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x0e9 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x050 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x14d and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x38e9; op2val:0x3850;
op3val:0x354d; valaddr_reg:x3; val_offset:570*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 570*FLEN/8, x4, x1, x2)

inst_191:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x0e9 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x050 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x14d and fcsr == 0x20 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x38e9; op2val:0x3850;
op3val:0x354d; valaddr_reg:x3; val_offset:573*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:32 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 32, 0, x3, 573*FLEN/8, x4, x1, x2)

inst_192:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x0e9 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x050 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x14d and fcsr == 0x40 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x38e9; op2val:0x3850;
op3val:0x354d; valaddr_reg:x3; val_offset:576*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:64 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 64, 0, x3, 576*FLEN/8, x4, x1, x2)

inst_193:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x0e9 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x050 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x14d and fcsr == 0x60 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x38e9; op2val:0x3850;
op3val:0x354d; valaddr_reg:x3; val_offset:579*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 96, 0, x3, 579*FLEN/8, x4, x1, x2)

inst_194:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x0e9 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x050 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x14d and fcsr == 0x80 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x38e9; op2val:0x3850;
op3val:0x354d; valaddr_reg:x3; val_offset:582*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:128 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 128, 0, x3, 582*FLEN/8, x4, x1, x2)

inst_195:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x3d1 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x067 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x04e and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3bd1; op2val:0x3867;
op3val:0x384e; valaddr_reg:x3; val_offset:585*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 585*FLEN/8, x4, x1, x2)

inst_196:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x3d1 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x067 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x04e and fcsr == 0x20 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3bd1; op2val:0x3867;
op3val:0x384e; valaddr_reg:x3; val_offset:588*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:32 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 32, 0, x3, 588*FLEN/8, x4, x1, x2)

inst_197:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x3d1 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x067 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x04e and fcsr == 0x40 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3bd1; op2val:0x3867;
op3val:0x384e; valaddr_reg:x3; val_offset:591*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:64 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 64, 0, x3, 591*FLEN/8, x4, x1, x2)

inst_198:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x3d1 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x067 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x04e and fcsr == 0x60 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3bd1; op2val:0x3867;
op3val:0x384e; valaddr_reg:x3; val_offset:594*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 96, 0, x3, 594*FLEN/8, x4, x1, x2)

inst_199:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x3d1 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x067 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x04e and fcsr == 0x80 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3bd1; op2val:0x3867;
op3val:0x384e; valaddr_reg:x3; val_offset:597*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:128 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 128, 0, x3, 597*FLEN/8, x4, x1, x2)

inst_200:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x2a7 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x03e and fs3 == 0 and fe3 == 0x0e and fm3 == 0x310 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3aa7; op2val:0x3c3e;
op3val:0x3b10; valaddr_reg:x3; val_offset:600*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 600*FLEN/8, x4, x1, x2)

inst_201:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x2a7 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x03e and fs3 == 0 and fe3 == 0x0e and fm3 == 0x310 and fcsr == 0x20 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3aa7; op2val:0x3c3e;
op3val:0x3b10; valaddr_reg:x3; val_offset:603*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:32 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 32, 0, x3, 603*FLEN/8, x4, x1, x2)

inst_202:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x2a7 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x03e and fs3 == 0 and fe3 == 0x0e and fm3 == 0x310 and fcsr == 0x40 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3aa7; op2val:0x3c3e;
op3val:0x3b10; valaddr_reg:x3; val_offset:606*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:64 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 64, 0, x3, 606*FLEN/8, x4, x1, x2)

inst_203:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x2a7 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x03e and fs3 == 0 and fe3 == 0x0e and fm3 == 0x310 and fcsr == 0x60 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3aa7; op2val:0x3c3e;
op3val:0x3b10; valaddr_reg:x3; val_offset:609*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 96, 0, x3, 609*FLEN/8, x4, x1, x2)

inst_204:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x2a7 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x03e and fs3 == 0 and fe3 == 0x0e and fm3 == 0x310 and fcsr == 0x80 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3aa7; op2val:0x3c3e;
op3val:0x3b10; valaddr_reg:x3; val_offset:612*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:128 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 128, 0, x3, 612*FLEN/8, x4, x1, x2)

inst_205:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x387 and fs2 == 0 and fe2 == 0x0c and fm2 == 0x3e1 and fs3 == 0 and fe3 == 0x0c and fm3 == 0x36a and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3b87; op2val:0x33e1;
op3val:0x336a; valaddr_reg:x3; val_offset:615*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 615*FLEN/8, x4, x1, x2)

inst_206:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x387 and fs2 == 0 and fe2 == 0x0c and fm2 == 0x3e1 and fs3 == 0 and fe3 == 0x0c and fm3 == 0x36a and fcsr == 0x20 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3b87; op2val:0x33e1;
op3val:0x336a; valaddr_reg:x3; val_offset:618*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:32 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 32, 0, x3, 618*FLEN/8, x4, x1, x2)

inst_207:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x387 and fs2 == 0 and fe2 == 0x0c and fm2 == 0x3e1 and fs3 == 0 and fe3 == 0x0c and fm3 == 0x36a and fcsr == 0x40 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3b87; op2val:0x33e1;
op3val:0x336a; valaddr_reg:x3; val_offset:621*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:64 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 64, 0, x3, 621*FLEN/8, x4, x1, x2)

inst_208:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x387 and fs2 == 0 and fe2 == 0x0c and fm2 == 0x3e1 and fs3 == 0 and fe3 == 0x0c and fm3 == 0x36a and fcsr == 0x60 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3b87; op2val:0x33e1;
op3val:0x336a; valaddr_reg:x3; val_offset:624*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 96, 0, x3, 624*FLEN/8, x4, x1, x2)

inst_209:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x387 and fs2 == 0 and fe2 == 0x0c and fm2 == 0x3e1 and fs3 == 0 and fe3 == 0x0c and fm3 == 0x36a and fcsr == 0x80 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3b87; op2val:0x33e1;
op3val:0x336a; valaddr_reg:x3; val_offset:627*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:128 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 128, 0, x3, 627*FLEN/8, x4, x1, x2)

inst_210:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x2f7 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x2e9 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x204 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3af7; op2val:0x3ae9;
op3val:0x3a04; valaddr_reg:x3; val_offset:630*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 630*FLEN/8, x4, x1, x2)

inst_211:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x2f7 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x2e9 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x204 and fcsr == 0x20 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3af7; op2val:0x3ae9;
op3val:0x3a04; valaddr_reg:x3; val_offset:633*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:32 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 32, 0, x3, 633*FLEN/8, x4, x1, x2)

inst_212:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x2f7 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x2e9 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x204 and fcsr == 0x40 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3af7; op2val:0x3ae9;
op3val:0x3a04; valaddr_reg:x3; val_offset:636*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:64 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 64, 0, x3, 636*FLEN/8, x4, x1, x2)

inst_213:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x2f7 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x2e9 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x204 and fcsr == 0x60 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3af7; op2val:0x3ae9;
op3val:0x3a04; valaddr_reg:x3; val_offset:639*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 96, 0, x3, 639*FLEN/8, x4, x1, x2)

inst_214:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x2f7 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x2e9 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x204 and fcsr == 0x80 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3af7; op2val:0x3ae9;
op3val:0x3a04; valaddr_reg:x3; val_offset:642*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:128 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 128, 0, x3, 642*FLEN/8, x4, x1, x2)

inst_215:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x0df and fs2 == 0 and fe2 == 0x0c and fm2 == 0x2c2 and fs3 == 0 and fe3 == 0x0c and fm3 == 0x01d and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x38df; op2val:0x32c2;
op3val:0x301d; valaddr_reg:x3; val_offset:645*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 645*FLEN/8, x4, x1, x2)

inst_216:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x0df and fs2 == 0 and fe2 == 0x0c and fm2 == 0x2c2 and fs3 == 0 and fe3 == 0x0c and fm3 == 0x01d and fcsr == 0x20 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x38df; op2val:0x32c2;
op3val:0x301d; valaddr_reg:x3; val_offset:648*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:32 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 32, 0, x3, 648*FLEN/8, x4, x1, x2)

inst_217:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x0df and fs2 == 0 and fe2 == 0x0c and fm2 == 0x2c2 and fs3 == 0 and fe3 == 0x0c and fm3 == 0x01d and fcsr == 0x40 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x38df; op2val:0x32c2;
op3val:0x301d; valaddr_reg:x3; val_offset:651*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:64 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 64, 0, x3, 651*FLEN/8, x4, x1, x2)

inst_218:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x0df and fs2 == 0 and fe2 == 0x0c and fm2 == 0x2c2 and fs3 == 0 and fe3 == 0x0c and fm3 == 0x01d and fcsr == 0x60 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x38df; op2val:0x32c2;
op3val:0x301d; valaddr_reg:x3; val_offset:654*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 96, 0, x3, 654*FLEN/8, x4, x1, x2)

inst_219:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x0df and fs2 == 0 and fe2 == 0x0c and fm2 == 0x2c2 and fs3 == 0 and fe3 == 0x0c and fm3 == 0x01d and fcsr == 0x80 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x38df; op2val:0x32c2;
op3val:0x301d; valaddr_reg:x3; val_offset:657*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:128 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 128, 0, x3, 657*FLEN/8, x4, x1, x2)

inst_220:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x35a and fs2 == 0 and fe2 == 0x0e and fm2 == 0x0cb and fs3 == 0 and fe3 == 0x0e and fm3 == 0x068 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3b5a; op2val:0x38cb;
op3val:0x3868; valaddr_reg:x3; val_offset:660*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 660*FLEN/8, x4, x1, x2)

inst_221:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x35a and fs2 == 0 and fe2 == 0x0e and fm2 == 0x0cb and fs3 == 0 and fe3 == 0x0e and fm3 == 0x068 and fcsr == 0x20 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3b5a; op2val:0x38cb;
op3val:0x3868; valaddr_reg:x3; val_offset:663*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:32 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 32, 0, x3, 663*FLEN/8, x4, x1, x2)

inst_222:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x35a and fs2 == 0 and fe2 == 0x0e and fm2 == 0x0cb and fs3 == 0 and fe3 == 0x0e and fm3 == 0x068 and fcsr == 0x40 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3b5a; op2val:0x38cb;
op3val:0x3868; valaddr_reg:x3; val_offset:666*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:64 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 64, 0, x3, 666*FLEN/8, x4, x1, x2)

inst_223:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x35a and fs2 == 0 and fe2 == 0x0e and fm2 == 0x0cb and fs3 == 0 and fe3 == 0x0e and fm3 == 0x068 and fcsr == 0x60 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3b5a; op2val:0x38cb;
op3val:0x3868; valaddr_reg:x3; val_offset:669*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 96, 0, x3, 669*FLEN/8, x4, x1, x2)

inst_224:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x35a and fs2 == 0 and fe2 == 0x0e and fm2 == 0x0cb and fs3 == 0 and fe3 == 0x0e and fm3 == 0x068 and fcsr == 0x80 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3b5a; op2val:0x38cb;
op3val:0x3868; valaddr_reg:x3; val_offset:672*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:128 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 128, 0, x3, 672*FLEN/8, x4, x1, x2)

inst_225:
// fs1 == 0 and fe1 == 0x0d and fm1 == 0x335 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x025 and fs3 == 0 and fe3 == 0x0b and fm3 == 0x377 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3735; op2val:0x3425;
op3val:0x2f77; valaddr_reg:x3; val_offset:675*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 675*FLEN/8, x4, x1, x2)

inst_226:
// fs1 == 0 and fe1 == 0x0d and fm1 == 0x335 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x025 and fs3 == 0 and fe3 == 0x0b and fm3 == 0x377 and fcsr == 0x20 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3735; op2val:0x3425;
op3val:0x2f77; valaddr_reg:x3; val_offset:678*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:32 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 32, 0, x3, 678*FLEN/8, x4, x1, x2)

inst_227:
// fs1 == 0 and fe1 == 0x0d and fm1 == 0x335 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x025 and fs3 == 0 and fe3 == 0x0b and fm3 == 0x377 and fcsr == 0x40 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3735; op2val:0x3425;
op3val:0x2f77; valaddr_reg:x3; val_offset:681*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:64 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 64, 0, x3, 681*FLEN/8, x4, x1, x2)

inst_228:
// fs1 == 0 and fe1 == 0x0d and fm1 == 0x335 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x025 and fs3 == 0 and fe3 == 0x0b and fm3 == 0x377 and fcsr == 0x60 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3735; op2val:0x3425;
op3val:0x2f77; valaddr_reg:x3; val_offset:684*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 96, 0, x3, 684*FLEN/8, x4, x1, x2)

inst_229:
// fs1 == 0 and fe1 == 0x0d and fm1 == 0x335 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x025 and fs3 == 0 and fe3 == 0x0b and fm3 == 0x377 and fcsr == 0x80 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3735; op2val:0x3425;
op3val:0x2f77; valaddr_reg:x3; val_offset:687*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:128 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 128, 0, x3, 687*FLEN/8, x4, x1, x2)

inst_230:
// fs1 == 0 and fe1 == 0x0c and fm1 == 0x1c8 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x206 and fs3 == 0 and fe3 == 0x0c and fm3 == 0x05a and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x31c8; op2val:0x3a06;
op3val:0x305a; valaddr_reg:x3; val_offset:690*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 690*FLEN/8, x4, x1, x2)

inst_231:
// fs1 == 0 and fe1 == 0x0c and fm1 == 0x1c8 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x206 and fs3 == 0 and fe3 == 0x0c and fm3 == 0x05a and fcsr == 0x20 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x31c8; op2val:0x3a06;
op3val:0x305a; valaddr_reg:x3; val_offset:693*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:32 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 32, 0, x3, 693*FLEN/8, x4, x1, x2)

inst_232:
// fs1 == 0 and fe1 == 0x0c and fm1 == 0x1c8 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x206 and fs3 == 0 and fe3 == 0x0c and fm3 == 0x05a and fcsr == 0x40 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x31c8; op2val:0x3a06;
op3val:0x305a; valaddr_reg:x3; val_offset:696*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:64 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 64, 0, x3, 696*FLEN/8, x4, x1, x2)

inst_233:
// fs1 == 0 and fe1 == 0x0c and fm1 == 0x1c8 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x206 and fs3 == 0 and fe3 == 0x0c and fm3 == 0x05a and fcsr == 0x60 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x31c8; op2val:0x3a06;
op3val:0x305a; valaddr_reg:x3; val_offset:699*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 96, 0, x3, 699*FLEN/8, x4, x1, x2)

inst_234:
// fs1 == 0 and fe1 == 0x0c and fm1 == 0x1c8 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x206 and fs3 == 0 and fe3 == 0x0c and fm3 == 0x05a and fcsr == 0x80 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x31c8; op2val:0x3a06;
op3val:0x305a; valaddr_reg:x3; val_offset:702*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:128 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 128, 0, x3, 702*FLEN/8, x4, x1, x2)

inst_235:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x1c5 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x27b and fs3 == 0 and fe3 == 0x0e and fm3 == 0x0ad and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x39c5; op2val:0x3a7b;
op3val:0x38ad; valaddr_reg:x3; val_offset:705*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 705*FLEN/8, x4, x1, x2)

inst_236:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x1c5 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x27b and fs3 == 0 and fe3 == 0x0e and fm3 == 0x0ad and fcsr == 0x20 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x39c5; op2val:0x3a7b;
op3val:0x38ad; valaddr_reg:x3; val_offset:708*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:32 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 32, 0, x3, 708*FLEN/8, x4, x1, x2)

inst_237:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x1c5 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x27b and fs3 == 0 and fe3 == 0x0e and fm3 == 0x0ad and fcsr == 0x40 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x39c5; op2val:0x3a7b;
op3val:0x38ad; valaddr_reg:x3; val_offset:711*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:64 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 64, 0, x3, 711*FLEN/8, x4, x1, x2)

inst_238:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x1c5 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x27b and fs3 == 0 and fe3 == 0x0e and fm3 == 0x0ad and fcsr == 0x60 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x39c5; op2val:0x3a7b;
op3val:0x38ad; valaddr_reg:x3; val_offset:714*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 96, 0, x3, 714*FLEN/8, x4, x1, x2)

inst_239:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x1c5 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x27b and fs3 == 0 and fe3 == 0x0e and fm3 == 0x0ad and fcsr == 0x80 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x39c5; op2val:0x3a7b;
op3val:0x38ad; valaddr_reg:x3; val_offset:717*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:128 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 128, 0, x3, 717*FLEN/8, x4, x1, x2)

inst_240:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x121 and fs2 == 0 and fe2 == 0x0c and fm2 == 0x1c8 and fs3 == 0 and fe3 == 0x0b and fm3 == 0x36a and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3921; op2val:0x31c8;
op3val:0x2f6a; valaddr_reg:x3; val_offset:720*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 720*FLEN/8, x4, x1, x2)

inst_241:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x121 and fs2 == 0 and fe2 == 0x0c and fm2 == 0x1c8 and fs3 == 0 and fe3 == 0x0b and fm3 == 0x36a and fcsr == 0x20 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3921; op2val:0x31c8;
op3val:0x2f6a; valaddr_reg:x3; val_offset:723*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:32 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 32, 0, x3, 723*FLEN/8, x4, x1, x2)

inst_242:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x121 and fs2 == 0 and fe2 == 0x0c and fm2 == 0x1c8 and fs3 == 0 and fe3 == 0x0b and fm3 == 0x36a and fcsr == 0x40 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3921; op2val:0x31c8;
op3val:0x2f6a; valaddr_reg:x3; val_offset:726*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:64 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 64, 0, x3, 726*FLEN/8, x4, x1, x2)

inst_243:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x121 and fs2 == 0 and fe2 == 0x0c and fm2 == 0x1c8 and fs3 == 0 and fe3 == 0x0b and fm3 == 0x36a and fcsr == 0x60 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3921; op2val:0x31c8;
op3val:0x2f6a; valaddr_reg:x3; val_offset:729*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 96, 0, x3, 729*FLEN/8, x4, x1, x2)

inst_244:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x121 and fs2 == 0 and fe2 == 0x0c and fm2 == 0x1c8 and fs3 == 0 and fe3 == 0x0b and fm3 == 0x36a and fcsr == 0x80 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3921; op2val:0x31c8;
op3val:0x2f6a; valaddr_reg:x3; val_offset:732*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:128 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 128, 0, x3, 732*FLEN/8, x4, x1, x2)

inst_245:
// fs1 == 0 and fe1 == 0x0a and fm1 == 0x16a and fs2 == 0 and fe2 == 0x13 and fm2 == 0x103 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x2ca and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x296a; op2val:0x4d03;
op3val:0x3aca; valaddr_reg:x3; val_offset:735*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 735*FLEN/8, x4, x1, x2)

inst_246:
// fs1 == 0 and fe1 == 0x0a and fm1 == 0x16a and fs2 == 0 and fe2 == 0x13 and fm2 == 0x103 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x2ca and fcsr == 0x20 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x296a; op2val:0x4d03;
op3val:0x3aca; valaddr_reg:x3; val_offset:738*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:32 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 32, 0, x3, 738*FLEN/8, x4, x1, x2)

inst_247:
// fs1 == 0 and fe1 == 0x0a and fm1 == 0x16a and fs2 == 0 and fe2 == 0x13 and fm2 == 0x103 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x2ca and fcsr == 0x40 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x296a; op2val:0x4d03;
op3val:0x3aca; valaddr_reg:x3; val_offset:741*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:64 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 64, 0, x3, 741*FLEN/8, x4, x1, x2)

inst_248:
// fs1 == 0 and fe1 == 0x0a and fm1 == 0x16a and fs2 == 0 and fe2 == 0x13 and fm2 == 0x103 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x2ca and fcsr == 0x60 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x296a; op2val:0x4d03;
op3val:0x3aca; valaddr_reg:x3; val_offset:744*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 96, 0, x3, 744*FLEN/8, x4, x1, x2)

inst_249:
// fs1 == 0 and fe1 == 0x0a and fm1 == 0x16a and fs2 == 0 and fe2 == 0x13 and fm2 == 0x103 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x2ca and fcsr == 0x80 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x296a; op2val:0x4d03;
op3val:0x3aca; valaddr_reg:x3; val_offset:747*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:128 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 128, 0, x3, 747*FLEN/8, x4, x1, x2)

inst_250:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x297 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x375 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x224 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3a97; op2val:0x3b75;
op3val:0x3a24; valaddr_reg:x3; val_offset:750*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 750*FLEN/8, x4, x1, x2)

inst_251:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x297 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x375 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x224 and fcsr == 0x20 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3a97; op2val:0x3b75;
op3val:0x3a24; valaddr_reg:x3; val_offset:753*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:32 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 32, 0, x3, 753*FLEN/8, x4, x1, x2)

inst_252:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x297 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x375 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x224 and fcsr == 0x40 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3a97; op2val:0x3b75;
op3val:0x3a24; valaddr_reg:x3; val_offset:756*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:64 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 64, 0, x3, 756*FLEN/8, x4, x1, x2)

inst_253:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x297 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x375 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x224 and fcsr == 0x60 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3a97; op2val:0x3b75;
op3val:0x3a24; valaddr_reg:x3; val_offset:759*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 96, 0, x3, 759*FLEN/8, x4, x1, x2)

inst_254:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x297 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x375 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x224 and fcsr == 0x80 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3a97; op2val:0x3b75;
op3val:0x3a24; valaddr_reg:x3; val_offset:762*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:128 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 128, 0, x3, 762*FLEN/8, x4, x1, x2)

inst_255:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x222 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x160 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x01e and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3a22; op2val:0x3960;
op3val:0x381e; valaddr_reg:x3; val_offset:765*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 765*FLEN/8, x4, x1, x2)
RVTEST_SIGBASE(x1,signature_x1_3)

inst_256:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x222 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x160 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x01e and fcsr == 0x20 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3a22; op2val:0x3960;
op3val:0x381e; valaddr_reg:x3; val_offset:768*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:32 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 32, 0, x3, 768*FLEN/8, x4, x1, x2)

inst_257:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x222 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x160 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x01e and fcsr == 0x40 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3a22; op2val:0x3960;
op3val:0x381e; valaddr_reg:x3; val_offset:771*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:64 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 64, 0, x3, 771*FLEN/8, x4, x1, x2)

inst_258:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x222 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x160 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x01e and fcsr == 0x60 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3a22; op2val:0x3960;
op3val:0x381e; valaddr_reg:x3; val_offset:774*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 96, 0, x3, 774*FLEN/8, x4, x1, x2)

inst_259:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x222 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x160 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x01e and fcsr == 0x80 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3a22; op2val:0x3960;
op3val:0x381e; valaddr_reg:x3; val_offset:777*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:128 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 128, 0, x3, 777*FLEN/8, x4, x1, x2)

inst_260:
// fs1 == 0 and fe1 == 0x0d and fm1 == 0x293 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x32d and fs3 == 0 and fe3 == 0x0e and fm3 == 0x1e5 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3693; op2val:0x3f2d;
op3val:0x39e5; valaddr_reg:x3; val_offset:780*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 780*FLEN/8, x4, x1, x2)

inst_261:
// fs1 == 0 and fe1 == 0x0d and fm1 == 0x293 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x32d and fs3 == 0 and fe3 == 0x0e and fm3 == 0x1e5 and fcsr == 0x20 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3693; op2val:0x3f2d;
op3val:0x39e5; valaddr_reg:x3; val_offset:783*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:32 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 32, 0, x3, 783*FLEN/8, x4, x1, x2)

inst_262:
// fs1 == 0 and fe1 == 0x0d and fm1 == 0x293 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x32d and fs3 == 0 and fe3 == 0x0e and fm3 == 0x1e5 and fcsr == 0x40 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3693; op2val:0x3f2d;
op3val:0x39e5; valaddr_reg:x3; val_offset:786*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:64 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 64, 0, x3, 786*FLEN/8, x4, x1, x2)

inst_263:
// fs1 == 0 and fe1 == 0x0d and fm1 == 0x293 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x32d and fs3 == 0 and fe3 == 0x0e and fm3 == 0x1e5 and fcsr == 0x60 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3693; op2val:0x3f2d;
op3val:0x39e5; valaddr_reg:x3; val_offset:789*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 96, 0, x3, 789*FLEN/8, x4, x1, x2)

inst_264:
// fs1 == 0 and fe1 == 0x0d and fm1 == 0x293 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x32d and fs3 == 0 and fe3 == 0x0e and fm3 == 0x1e5 and fcsr == 0x80 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3693; op2val:0x3f2d;
op3val:0x39e5; valaddr_reg:x3; val_offset:792*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:128 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 128, 0, x3, 792*FLEN/8, x4, x1, x2)

inst_265:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x3f7 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x0ab and fs3 == 0 and fe3 == 0x0e and fm3 == 0x0a6 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3bf7; op2val:0x38ab;
op3val:0x38a6; valaddr_reg:x3; val_offset:795*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 795*FLEN/8, x4, x1, x2)

inst_266:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x3f7 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x0ab and fs3 == 0 and fe3 == 0x0e and fm3 == 0x0a6 and fcsr == 0x20 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3bf7; op2val:0x38ab;
op3val:0x38a6; valaddr_reg:x3; val_offset:798*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:32 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 32, 0, x3, 798*FLEN/8, x4, x1, x2)

inst_267:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x3f7 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x0ab and fs3 == 0 and fe3 == 0x0e and fm3 == 0x0a6 and fcsr == 0x40 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3bf7; op2val:0x38ab;
op3val:0x38a6; valaddr_reg:x3; val_offset:801*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:64 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 64, 0, x3, 801*FLEN/8, x4, x1, x2)

inst_268:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x3f7 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x0ab and fs3 == 0 and fe3 == 0x0e and fm3 == 0x0a6 and fcsr == 0x60 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3bf7; op2val:0x38ab;
op3val:0x38a6; valaddr_reg:x3; val_offset:804*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 96, 0, x3, 804*FLEN/8, x4, x1, x2)

inst_269:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x3f7 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x0ab and fs3 == 0 and fe3 == 0x0e and fm3 == 0x0a6 and fcsr == 0x80 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3bf7; op2val:0x38ab;
op3val:0x38a6; valaddr_reg:x3; val_offset:807*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:128 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 128, 0, x3, 807*FLEN/8, x4, x1, x2)

inst_270:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x10b and fs2 == 0 and fe2 == 0x0e and fm2 == 0x180 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x2f0 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x390b; op2val:0x3980;
op3val:0x36f0; valaddr_reg:x3; val_offset:810*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 810*FLEN/8, x4, x1, x2)

inst_271:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x10b and fs2 == 0 and fe2 == 0x0e and fm2 == 0x180 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x2f0 and fcsr == 0x20 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x390b; op2val:0x3980;
op3val:0x36f0; valaddr_reg:x3; val_offset:813*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:32 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 32, 0, x3, 813*FLEN/8, x4, x1, x2)

inst_272:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x10b and fs2 == 0 and fe2 == 0x0e and fm2 == 0x180 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x2f0 and fcsr == 0x40 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x390b; op2val:0x3980;
op3val:0x36f0; valaddr_reg:x3; val_offset:816*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:64 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 64, 0, x3, 816*FLEN/8, x4, x1, x2)

inst_273:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x10b and fs2 == 0 and fe2 == 0x0e and fm2 == 0x180 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x2f0 and fcsr == 0x60 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x390b; op2val:0x3980;
op3val:0x36f0; valaddr_reg:x3; val_offset:819*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 96, 0, x3, 819*FLEN/8, x4, x1, x2)

inst_274:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x10b and fs2 == 0 and fe2 == 0x0e and fm2 == 0x180 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x2f0 and fcsr == 0x80 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x390b; op2val:0x3980;
op3val:0x36f0; valaddr_reg:x3; val_offset:822*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:128 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 128, 0, x3, 822*FLEN/8, x4, x1, x2)

inst_275:
// fs1 == 0 and fe1 == 0x0a and fm1 == 0x202 and fs2 == 0 and fe2 == 0x11 and fm2 == 0x297 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x0f3 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x2a02; op2val:0x4697;
op3val:0x34f3; valaddr_reg:x3; val_offset:825*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 825*FLEN/8, x4, x1, x2)

inst_276:
// fs1 == 0 and fe1 == 0x0a and fm1 == 0x202 and fs2 == 0 and fe2 == 0x11 and fm2 == 0x297 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x0f3 and fcsr == 0x20 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x2a02; op2val:0x4697;
op3val:0x34f3; valaddr_reg:x3; val_offset:828*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:32 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 32, 0, x3, 828*FLEN/8, x4, x1, x2)

inst_277:
// fs1 == 0 and fe1 == 0x0a and fm1 == 0x202 and fs2 == 0 and fe2 == 0x11 and fm2 == 0x297 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x0f3 and fcsr == 0x40 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x2a02; op2val:0x4697;
op3val:0x34f3; valaddr_reg:x3; val_offset:831*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:64 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 64, 0, x3, 831*FLEN/8, x4, x1, x2)

inst_278:
// fs1 == 0 and fe1 == 0x0a and fm1 == 0x202 and fs2 == 0 and fe2 == 0x11 and fm2 == 0x297 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x0f3 and fcsr == 0x60 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x2a02; op2val:0x4697;
op3val:0x34f3; valaddr_reg:x3; val_offset:834*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 96, 0, x3, 834*FLEN/8, x4, x1, x2)

inst_279:
// fs1 == 0 and fe1 == 0x0a and fm1 == 0x202 and fs2 == 0 and fe2 == 0x11 and fm2 == 0x297 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x0f3 and fcsr == 0x80 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x2a02; op2val:0x4697;
op3val:0x34f3; valaddr_reg:x3; val_offset:837*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:128 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 128, 0, x3, 837*FLEN/8, x4, x1, x2)

inst_280:
// fs1 == 0 and fe1 == 0x0d and fm1 == 0x3c0 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x250 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x21e and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x37c0; op2val:0x3a50;
op3val:0x361e; valaddr_reg:x3; val_offset:840*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 840*FLEN/8, x4, x1, x2)

inst_281:
// fs1 == 0 and fe1 == 0x0d and fm1 == 0x3c0 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x250 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x21e and fcsr == 0x20 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x37c0; op2val:0x3a50;
op3val:0x361e; valaddr_reg:x3; val_offset:843*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:32 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 32, 0, x3, 843*FLEN/8, x4, x1, x2)

inst_282:
// fs1 == 0 and fe1 == 0x0d and fm1 == 0x3c0 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x250 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x21e and fcsr == 0x40 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x37c0; op2val:0x3a50;
op3val:0x361e; valaddr_reg:x3; val_offset:846*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:64 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 64, 0, x3, 846*FLEN/8, x4, x1, x2)

inst_283:
// fs1 == 0 and fe1 == 0x0d and fm1 == 0x3c0 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x250 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x21e and fcsr == 0x60 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x37c0; op2val:0x3a50;
op3val:0x361e; valaddr_reg:x3; val_offset:849*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 96, 0, x3, 849*FLEN/8, x4, x1, x2)

inst_284:
// fs1 == 0 and fe1 == 0x0d and fm1 == 0x3c0 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x250 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x21e and fcsr == 0x80 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x37c0; op2val:0x3a50;
op3val:0x361e; valaddr_reg:x3; val_offset:852*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:128 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 128, 0, x3, 852*FLEN/8, x4, x1, x2)

inst_285:
// fs1 == 0 and fe1 == 0x0d and fm1 == 0x12e and fs2 == 0 and fe2 == 0x10 and fm2 == 0x1d7 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x391 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x352e; op2val:0x41d7;
op3val:0x3b91; valaddr_reg:x3; val_offset:855*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 855*FLEN/8, x4, x1, x2)

inst_286:
// fs1 == 0 and fe1 == 0x0d and fm1 == 0x12e and fs2 == 0 and fe2 == 0x10 and fm2 == 0x1d7 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x391 and fcsr == 0x20 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x352e; op2val:0x41d7;
op3val:0x3b91; valaddr_reg:x3; val_offset:858*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:32 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 32, 0, x3, 858*FLEN/8, x4, x1, x2)

inst_287:
// fs1 == 0 and fe1 == 0x0d and fm1 == 0x12e and fs2 == 0 and fe2 == 0x10 and fm2 == 0x1d7 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x391 and fcsr == 0x40 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x352e; op2val:0x41d7;
op3val:0x3b91; valaddr_reg:x3; val_offset:861*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:64 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 64, 0, x3, 861*FLEN/8, x4, x1, x2)

inst_288:
// fs1 == 0 and fe1 == 0x0d and fm1 == 0x12e and fs2 == 0 and fe2 == 0x10 and fm2 == 0x1d7 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x391 and fcsr == 0x60 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x352e; op2val:0x41d7;
op3val:0x3b91; valaddr_reg:x3; val_offset:864*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 96, 0, x3, 864*FLEN/8, x4, x1, x2)

inst_289:
// fs1 == 0 and fe1 == 0x0d and fm1 == 0x12e and fs2 == 0 and fe2 == 0x10 and fm2 == 0x1d7 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x391 and fcsr == 0x80 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x352e; op2val:0x41d7;
op3val:0x3b91; valaddr_reg:x3; val_offset:867*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:128 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 128, 0, x3, 867*FLEN/8, x4, x1, x2)

inst_290:
// fs1 == 0 and fe1 == 0x0b and fm1 == 0x26e and fs2 == 0 and fe2 == 0x10 and fm2 == 0x061 and fs3 == 0 and fe3 == 0x0c and fm3 == 0x30a and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x2e6e; op2val:0x4061;
op3val:0x330a; valaddr_reg:x3; val_offset:870*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 870*FLEN/8, x4, x1, x2)

inst_291:
// fs1 == 0 and fe1 == 0x0b and fm1 == 0x26e and fs2 == 0 and fe2 == 0x10 and fm2 == 0x061 and fs3 == 0 and fe3 == 0x0c and fm3 == 0x30a and fcsr == 0x20 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x2e6e; op2val:0x4061;
op3val:0x330a; valaddr_reg:x3; val_offset:873*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:32 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 32, 0, x3, 873*FLEN/8, x4, x1, x2)

inst_292:
// fs1 == 0 and fe1 == 0x0b and fm1 == 0x26e and fs2 == 0 and fe2 == 0x10 and fm2 == 0x061 and fs3 == 0 and fe3 == 0x0c and fm3 == 0x30a and fcsr == 0x40 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x2e6e; op2val:0x4061;
op3val:0x330a; valaddr_reg:x3; val_offset:876*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:64 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 64, 0, x3, 876*FLEN/8, x4, x1, x2)

inst_293:
// fs1 == 0 and fe1 == 0x0b and fm1 == 0x26e and fs2 == 0 and fe2 == 0x10 and fm2 == 0x061 and fs3 == 0 and fe3 == 0x0c and fm3 == 0x30a and fcsr == 0x60 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x2e6e; op2val:0x4061;
op3val:0x330a; valaddr_reg:x3; val_offset:879*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 96, 0, x3, 879*FLEN/8, x4, x1, x2)

inst_294:
// fs1 == 0 and fe1 == 0x0b and fm1 == 0x26e and fs2 == 0 and fe2 == 0x10 and fm2 == 0x061 and fs3 == 0 and fe3 == 0x0c and fm3 == 0x30a and fcsr == 0x80 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x2e6e; op2val:0x4061;
op3val:0x330a; valaddr_reg:x3; val_offset:882*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:128 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 128, 0, x3, 882*FLEN/8, x4, x1, x2)

inst_295:
// fs1 == 0 and fe1 == 0x0c and fm1 == 0x004 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x271 and fs3 == 0 and fe3 == 0x0c and fm3 == 0x278 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3004; op2val:0x3e71;
op3val:0x3278; valaddr_reg:x3; val_offset:885*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 885*FLEN/8, x4, x1, x2)

inst_296:
// fs1 == 0 and fe1 == 0x0c and fm1 == 0x004 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x271 and fs3 == 0 and fe3 == 0x0c and fm3 == 0x278 and fcsr == 0x20 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3004; op2val:0x3e71;
op3val:0x3278; valaddr_reg:x3; val_offset:888*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:32 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 32, 0, x3, 888*FLEN/8, x4, x1, x2)

inst_297:
// fs1 == 0 and fe1 == 0x0c and fm1 == 0x004 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x271 and fs3 == 0 and fe3 == 0x0c and fm3 == 0x278 and fcsr == 0x40 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3004; op2val:0x3e71;
op3val:0x3278; valaddr_reg:x3; val_offset:891*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:64 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 64, 0, x3, 891*FLEN/8, x4, x1, x2)

inst_298:
// fs1 == 0 and fe1 == 0x0c and fm1 == 0x004 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x271 and fs3 == 0 and fe3 == 0x0c and fm3 == 0x278 and fcsr == 0x60 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3004; op2val:0x3e71;
op3val:0x3278; valaddr_reg:x3; val_offset:894*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 96, 0, x3, 894*FLEN/8, x4, x1, x2)

inst_299:
// fs1 == 0 and fe1 == 0x0c and fm1 == 0x004 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x271 and fs3 == 0 and fe3 == 0x0c and fm3 == 0x278 and fcsr == 0x80 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3004; op2val:0x3e71;
op3val:0x3278; valaddr_reg:x3; val_offset:897*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:128 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 128, 0, x3, 897*FLEN/8, x4, x1, x2)

inst_300:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x0dc and fs2 == 0 and fe2 == 0x0e and fm2 == 0x3e9 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x0ce and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x38dc; op2val:0x3be9;
op3val:0x38ce; valaddr_reg:x3; val_offset:900*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 900*FLEN/8, x4, x1, x2)

inst_301:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x0dc and fs2 == 0 and fe2 == 0x0e and fm2 == 0x3e9 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x0ce and fcsr == 0x20 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x38dc; op2val:0x3be9;
op3val:0x38ce; valaddr_reg:x3; val_offset:903*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:32 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 32, 0, x3, 903*FLEN/8, x4, x1, x2)

inst_302:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x0dc and fs2 == 0 and fe2 == 0x0e and fm2 == 0x3e9 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x0ce and fcsr == 0x40 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x38dc; op2val:0x3be9;
op3val:0x38ce; valaddr_reg:x3; val_offset:906*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:64 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 64, 0, x3, 906*FLEN/8, x4, x1, x2)

inst_303:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x0dc and fs2 == 0 and fe2 == 0x0e and fm2 == 0x3e9 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x0ce and fcsr == 0x60 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x38dc; op2val:0x3be9;
op3val:0x38ce; valaddr_reg:x3; val_offset:909*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 96, 0, x3, 909*FLEN/8, x4, x1, x2)

inst_304:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x0dc and fs2 == 0 and fe2 == 0x0e and fm2 == 0x3e9 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x0ce and fcsr == 0x80 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x38dc; op2val:0x3be9;
op3val:0x38ce; valaddr_reg:x3; val_offset:912*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:128 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 128, 0, x3, 912*FLEN/8, x4, x1, x2)

inst_305:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x32b and fs2 == 0 and fe2 == 0x0d and fm2 == 0x287 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x1da and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3b2b; op2val:0x3687;
op3val:0x35da; valaddr_reg:x3; val_offset:915*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 915*FLEN/8, x4, x1, x2)

inst_306:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x32b and fs2 == 0 and fe2 == 0x0d and fm2 == 0x287 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x1da and fcsr == 0x20 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3b2b; op2val:0x3687;
op3val:0x35da; valaddr_reg:x3; val_offset:918*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:32 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 32, 0, x3, 918*FLEN/8, x4, x1, x2)

inst_307:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x32b and fs2 == 0 and fe2 == 0x0d and fm2 == 0x287 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x1da and fcsr == 0x40 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3b2b; op2val:0x3687;
op3val:0x35da; valaddr_reg:x3; val_offset:921*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:64 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 64, 0, x3, 921*FLEN/8, x4, x1, x2)

inst_308:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x32b and fs2 == 0 and fe2 == 0x0d and fm2 == 0x287 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x1da and fcsr == 0x60 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3b2b; op2val:0x3687;
op3val:0x35da; valaddr_reg:x3; val_offset:924*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 96, 0, x3, 924*FLEN/8, x4, x1, x2)

inst_309:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x32b and fs2 == 0 and fe2 == 0x0d and fm2 == 0x287 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x1da and fcsr == 0x80 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3b2b; op2val:0x3687;
op3val:0x35da; valaddr_reg:x3; val_offset:927*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:128 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 128, 0, x3, 927*FLEN/8, x4, x1, x2)

inst_310:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x380 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x3f4 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x376 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3b80; op2val:0x3bf4;
op3val:0x3b76; valaddr_reg:x3; val_offset:930*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 930*FLEN/8, x4, x1, x2)

inst_311:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x380 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x3f4 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x376 and fcsr == 0x20 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3b80; op2val:0x3bf4;
op3val:0x3b76; valaddr_reg:x3; val_offset:933*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:32 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 32, 0, x3, 933*FLEN/8, x4, x1, x2)

inst_312:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x380 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x3f4 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x376 and fcsr == 0x40 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3b80; op2val:0x3bf4;
op3val:0x3b76; valaddr_reg:x3; val_offset:936*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:64 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 64, 0, x3, 936*FLEN/8, x4, x1, x2)

inst_313:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x380 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x3f4 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x376 and fcsr == 0x60 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3b80; op2val:0x3bf4;
op3val:0x3b76; valaddr_reg:x3; val_offset:939*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 96, 0, x3, 939*FLEN/8, x4, x1, x2)

inst_314:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x380 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x3f4 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x376 and fcsr == 0x80 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3b80; op2val:0x3bf4;
op3val:0x3b76; valaddr_reg:x3; val_offset:942*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:128 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 128, 0, x3, 942*FLEN/8, x4, x1, x2)

inst_315:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x254 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x03c and fs3 == 0 and fe3 == 0x0e and fm3 == 0x2b3 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3a54; op2val:0x3c3c;
op3val:0x3ab3; valaddr_reg:x3; val_offset:945*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 945*FLEN/8, x4, x1, x2)

inst_316:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x254 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x03c and fs3 == 0 and fe3 == 0x0e and fm3 == 0x2b3 and fcsr == 0x20 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3a54; op2val:0x3c3c;
op3val:0x3ab3; valaddr_reg:x3; val_offset:948*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:32 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 32, 0, x3, 948*FLEN/8, x4, x1, x2)

inst_317:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x254 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x03c and fs3 == 0 and fe3 == 0x0e and fm3 == 0x2b3 and fcsr == 0x40 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3a54; op2val:0x3c3c;
op3val:0x3ab3; valaddr_reg:x3; val_offset:951*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:64 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 64, 0, x3, 951*FLEN/8, x4, x1, x2)

inst_318:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x254 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x03c and fs3 == 0 and fe3 == 0x0e and fm3 == 0x2b3 and fcsr == 0x60 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3a54; op2val:0x3c3c;
op3val:0x3ab3; valaddr_reg:x3; val_offset:954*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 96, 0, x3, 954*FLEN/8, x4, x1, x2)

inst_319:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x254 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x03c and fs3 == 0 and fe3 == 0x0e and fm3 == 0x2b3 and fcsr == 0x80 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3a54; op2val:0x3c3c;
op3val:0x3ab3; valaddr_reg:x3; val_offset:957*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:128 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 128, 0, x3, 957*FLEN/8, x4, x1, x2)

inst_320:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x147 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x1be and fs3 == 0 and fe3 == 0x0e and fm3 == 0x394 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3947; op2val:0x3dbe;
op3val:0x3b94; valaddr_reg:x3; val_offset:960*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 960*FLEN/8, x4, x1, x2)

inst_321:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x147 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x1be and fs3 == 0 and fe3 == 0x0e and fm3 == 0x394 and fcsr == 0x20 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3947; op2val:0x3dbe;
op3val:0x3b94; valaddr_reg:x3; val_offset:963*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:32 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 32, 0, x3, 963*FLEN/8, x4, x1, x2)

inst_322:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x147 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x1be and fs3 == 0 and fe3 == 0x0e and fm3 == 0x394 and fcsr == 0x40 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3947; op2val:0x3dbe;
op3val:0x3b94; valaddr_reg:x3; val_offset:966*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:64 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 64, 0, x3, 966*FLEN/8, x4, x1, x2)

inst_323:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x147 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x1be and fs3 == 0 and fe3 == 0x0e and fm3 == 0x394 and fcsr == 0x60 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3947; op2val:0x3dbe;
op3val:0x3b94; valaddr_reg:x3; val_offset:969*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 96, 0, x3, 969*FLEN/8, x4, x1, x2)

inst_324:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x147 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x1be and fs3 == 0 and fe3 == 0x0e and fm3 == 0x394 and fcsr == 0x80 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3947; op2val:0x3dbe;
op3val:0x3b94; valaddr_reg:x3; val_offset:972*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:128 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 128, 0, x3, 972*FLEN/8, x4, x1, x2)

inst_325:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x0e and fm2 == 0x2ca and fs3 == 0 and fe3 == 0x0e and fm3 == 0x2ca and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3bff; op2val:0x3aca;
op3val:0x3aca; valaddr_reg:x3; val_offset:975*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 975*FLEN/8, x4, x1, x2)

inst_326:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x0e and fm2 == 0x2ca and fs3 == 0 and fe3 == 0x0e and fm3 == 0x2ca and fcsr == 0x20 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3bff; op2val:0x3aca;
op3val:0x3aca; valaddr_reg:x3; val_offset:978*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:32 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 32, 0, x3, 978*FLEN/8, x4, x1, x2)

inst_327:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x0e and fm2 == 0x2ca and fs3 == 0 and fe3 == 0x0e and fm3 == 0x2ca and fcsr == 0x40 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3bff; op2val:0x3aca;
op3val:0x3aca; valaddr_reg:x3; val_offset:981*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:64 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 64, 0, x3, 981*FLEN/8, x4, x1, x2)

inst_328:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x0e and fm2 == 0x2ca and fs3 == 0 and fe3 == 0x0e and fm3 == 0x2ca and fcsr == 0x60 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3bff; op2val:0x3aca;
op3val:0x3aca; valaddr_reg:x3; val_offset:984*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 96, 0, x3, 984*FLEN/8, x4, x1, x2)

inst_329:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x0e and fm2 == 0x2ca and fs3 == 0 and fe3 == 0x0e and fm3 == 0x2ca and fcsr == 0x80 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3bff; op2val:0x3aca;
op3val:0x3aca; valaddr_reg:x3; val_offset:987*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:128 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 128, 0, x3, 987*FLEN/8, x4, x1, x2)

inst_330:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x330 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x1aa and fs3 == 0 and fe3 == 0x0e and fm3 == 0x117 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3b30; op2val:0x39aa;
op3val:0x3917; valaddr_reg:x3; val_offset:990*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 990*FLEN/8, x4, x1, x2)

inst_331:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x330 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x1aa and fs3 == 0 and fe3 == 0x0e and fm3 == 0x117 and fcsr == 0x20 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3b30; op2val:0x39aa;
op3val:0x3917; valaddr_reg:x3; val_offset:993*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:32 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 32, 0, x3, 993*FLEN/8, x4, x1, x2)

inst_332:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x330 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x1aa and fs3 == 0 and fe3 == 0x0e and fm3 == 0x117 and fcsr == 0x40 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3b30; op2val:0x39aa;
op3val:0x3917; valaddr_reg:x3; val_offset:996*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:64 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 64, 0, x3, 996*FLEN/8, x4, x1, x2)

inst_333:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x330 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x1aa and fs3 == 0 and fe3 == 0x0e and fm3 == 0x117 and fcsr == 0x60 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3b30; op2val:0x39aa;
op3val:0x3917; valaddr_reg:x3; val_offset:999*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 96, 0, x3, 999*FLEN/8, x4, x1, x2)

inst_334:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x330 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x1aa and fs3 == 0 and fe3 == 0x0e and fm3 == 0x117 and fcsr == 0x80 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3b30; op2val:0x39aa;
op3val:0x3917; valaddr_reg:x3; val_offset:1002*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:128 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 128, 0, x3, 1002*FLEN/8, x4, x1, x2)

inst_335:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x3cb and fs2 == 0 and fe2 == 0x0c and fm2 == 0x021 and fs3 == 0 and fe3 == 0x0c and fm3 == 0x005 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3bcb; op2val:0x3021;
op3val:0x3005; valaddr_reg:x3; val_offset:1005*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 1005*FLEN/8, x4, x1, x2)

inst_336:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x3cb and fs2 == 0 and fe2 == 0x0c and fm2 == 0x021 and fs3 == 0 and fe3 == 0x0c and fm3 == 0x005 and fcsr == 0x20 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3bcb; op2val:0x3021;
op3val:0x3005; valaddr_reg:x3; val_offset:1008*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:32 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 32, 0, x3, 1008*FLEN/8, x4, x1, x2)

inst_337:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x3cb and fs2 == 0 and fe2 == 0x0c and fm2 == 0x021 and fs3 == 0 and fe3 == 0x0c and fm3 == 0x005 and fcsr == 0x40 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3bcb; op2val:0x3021;
op3val:0x3005; valaddr_reg:x3; val_offset:1011*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:64 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 64, 0, x3, 1011*FLEN/8, x4, x1, x2)

inst_338:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x3cb and fs2 == 0 and fe2 == 0x0c and fm2 == 0x021 and fs3 == 0 and fe3 == 0x0c and fm3 == 0x005 and fcsr == 0x60 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3bcb; op2val:0x3021;
op3val:0x3005; valaddr_reg:x3; val_offset:1014*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 96, 0, x3, 1014*FLEN/8, x4, x1, x2)

inst_339:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x3cb and fs2 == 0 and fe2 == 0x0c and fm2 == 0x021 and fs3 == 0 and fe3 == 0x0c and fm3 == 0x005 and fcsr == 0x80 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3bcb; op2val:0x3021;
op3val:0x3005; valaddr_reg:x3; val_offset:1017*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:128 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 128, 0, x3, 1017*FLEN/8, x4, x1, x2)

inst_340:
// fs1 == 0 and fe1 == 0x0d and fm1 == 0x22c and fs2 == 0 and fe2 == 0x10 and fm2 == 0x069 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x2cf and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x362c; op2val:0x4069;
op3val:0x3acf; valaddr_reg:x3; val_offset:1020*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 1020*FLEN/8, x4, x1, x2)

inst_341:
// fs1 == 0 and fe1 == 0x0d and fm1 == 0x22c and fs2 == 0 and fe2 == 0x10 and fm2 == 0x069 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x2cf and fcsr == 0x20 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x362c; op2val:0x4069;
op3val:0x3acf; valaddr_reg:x3; val_offset:1023*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:32 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 32, 0, x3, 1023*FLEN/8, x4, x1, x2)

inst_342:
// fs1 == 0 and fe1 == 0x0d and fm1 == 0x22c and fs2 == 0 and fe2 == 0x10 and fm2 == 0x069 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x2cf and fcsr == 0x40 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x362c; op2val:0x4069;
op3val:0x3acf; valaddr_reg:x3; val_offset:1026*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:64 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 64, 0, x3, 1026*FLEN/8, x4, x1, x2)

inst_343:
// fs1 == 0 and fe1 == 0x0d and fm1 == 0x22c and fs2 == 0 and fe2 == 0x10 and fm2 == 0x069 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x2cf and fcsr == 0x60 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x362c; op2val:0x4069;
op3val:0x3acf; valaddr_reg:x3; val_offset:1029*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 96, 0, x3, 1029*FLEN/8, x4, x1, x2)

inst_344:
// fs1 == 0 and fe1 == 0x0d and fm1 == 0x22c and fs2 == 0 and fe2 == 0x10 and fm2 == 0x069 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x2cf and fcsr == 0x80 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x362c; op2val:0x4069;
op3val:0x3acf; valaddr_reg:x3; val_offset:1032*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:128 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 128, 0, x3, 1032*FLEN/8, x4, x1, x2)

inst_345:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x1fb and fs2 == 0 and fe2 == 0x0e and fm2 == 0x2fb and fs3 == 0 and fe3 == 0x0e and fm3 == 0x138 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x39fb; op2val:0x3afb;
op3val:0x3938; valaddr_reg:x3; val_offset:1035*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 1035*FLEN/8, x4, x1, x2)

inst_346:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x1fb and fs2 == 0 and fe2 == 0x0e and fm2 == 0x2fb and fs3 == 0 and fe3 == 0x0e and fm3 == 0x138 and fcsr == 0x20 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x39fb; op2val:0x3afb;
op3val:0x3938; valaddr_reg:x3; val_offset:1038*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:32 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 32, 0, x3, 1038*FLEN/8, x4, x1, x2)

inst_347:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x1fb and fs2 == 0 and fe2 == 0x0e and fm2 == 0x2fb and fs3 == 0 and fe3 == 0x0e and fm3 == 0x138 and fcsr == 0x40 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x39fb; op2val:0x3afb;
op3val:0x3938; valaddr_reg:x3; val_offset:1041*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:64 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 64, 0, x3, 1041*FLEN/8, x4, x1, x2)

inst_348:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x1fb and fs2 == 0 and fe2 == 0x0e and fm2 == 0x2fb and fs3 == 0 and fe3 == 0x0e and fm3 == 0x138 and fcsr == 0x60 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x39fb; op2val:0x3afb;
op3val:0x3938; valaddr_reg:x3; val_offset:1044*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 96, 0, x3, 1044*FLEN/8, x4, x1, x2)

inst_349:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x1fb and fs2 == 0 and fe2 == 0x0e and fm2 == 0x2fb and fs3 == 0 and fe3 == 0x0e and fm3 == 0x138 and fcsr == 0x80 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x39fb; op2val:0x3afb;
op3val:0x3938; valaddr_reg:x3; val_offset:1047*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:128 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 128, 0, x3, 1047*FLEN/8, x4, x1, x2)

inst_350:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x116 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x184 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x304 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3916; op2val:0x3d84;
op3val:0x3b04; valaddr_reg:x3; val_offset:1050*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 1050*FLEN/8, x4, x1, x2)

inst_351:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x116 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x184 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x304 and fcsr == 0x20 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3916; op2val:0x3d84;
op3val:0x3b04; valaddr_reg:x3; val_offset:1053*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:32 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 32, 0, x3, 1053*FLEN/8, x4, x1, x2)

inst_352:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x116 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x184 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x304 and fcsr == 0x40 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3916; op2val:0x3d84;
op3val:0x3b04; valaddr_reg:x3; val_offset:1056*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:64 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 64, 0, x3, 1056*FLEN/8, x4, x1, x2)

inst_353:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x116 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x184 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x304 and fcsr == 0x60 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3916; op2val:0x3d84;
op3val:0x3b04; valaddr_reg:x3; val_offset:1059*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 96, 0, x3, 1059*FLEN/8, x4, x1, x2)

inst_354:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x116 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x184 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x304 and fcsr == 0x80 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3916; op2val:0x3d84;
op3val:0x3b04; valaddr_reg:x3; val_offset:1062*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:128 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 128, 0, x3, 1062*FLEN/8, x4, x1, x2)

inst_355:
// fs1 == 0 and fe1 == 0x0c and fm1 == 0x0d5 and fs2 == 0 and fe2 == 0x0a and fm2 == 0x1f1 and fs3 == 0 and fe3 == 0x07 and fm3 == 0x31f and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x30d5; op2val:0x29f1;
op3val:0x1f1f; valaddr_reg:x3; val_offset:1065*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 1065*FLEN/8, x4, x1, x2)

inst_356:
// fs1 == 0 and fe1 == 0x0c and fm1 == 0x0d5 and fs2 == 0 and fe2 == 0x0a and fm2 == 0x1f1 and fs3 == 0 and fe3 == 0x07 and fm3 == 0x31f and fcsr == 0x20 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x30d5; op2val:0x29f1;
op3val:0x1f1f; valaddr_reg:x3; val_offset:1068*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:32 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 32, 0, x3, 1068*FLEN/8, x4, x1, x2)

inst_357:
// fs1 == 0 and fe1 == 0x0c and fm1 == 0x0d5 and fs2 == 0 and fe2 == 0x0a and fm2 == 0x1f1 and fs3 == 0 and fe3 == 0x07 and fm3 == 0x31f and fcsr == 0x40 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x30d5; op2val:0x29f1;
op3val:0x1f1f; valaddr_reg:x3; val_offset:1071*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:64 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 64, 0, x3, 1071*FLEN/8, x4, x1, x2)

inst_358:
// fs1 == 0 and fe1 == 0x0c and fm1 == 0x0d5 and fs2 == 0 and fe2 == 0x0a and fm2 == 0x1f1 and fs3 == 0 and fe3 == 0x07 and fm3 == 0x31f and fcsr == 0x60 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x30d5; op2val:0x29f1;
op3val:0x1f1f; valaddr_reg:x3; val_offset:1074*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 96, 0, x3, 1074*FLEN/8, x4, x1, x2)

inst_359:
// fs1 == 0 and fe1 == 0x0c and fm1 == 0x0d5 and fs2 == 0 and fe2 == 0x0a and fm2 == 0x1f1 and fs3 == 0 and fe3 == 0x07 and fm3 == 0x31f and fcsr == 0x80 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x30d5; op2val:0x29f1;
op3val:0x1f1f; valaddr_reg:x3; val_offset:1077*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:128 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 128, 0, x3, 1077*FLEN/8, x4, x1, x2)

inst_360:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x045 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x3bb and fs3 == 0 and fe3 == 0x0e and fm3 == 0x021 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3845; op2val:0x3bbb;
op3val:0x3821; valaddr_reg:x3; val_offset:1080*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 1080*FLEN/8, x4, x1, x2)

inst_361:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x045 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x3bb and fs3 == 0 and fe3 == 0x0e and fm3 == 0x021 and fcsr == 0x20 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3845; op2val:0x3bbb;
op3val:0x3821; valaddr_reg:x3; val_offset:1083*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:32 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 32, 0, x3, 1083*FLEN/8, x4, x1, x2)

inst_362:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x045 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x3bb and fs3 == 0 and fe3 == 0x0e and fm3 == 0x021 and fcsr == 0x40 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3845; op2val:0x3bbb;
op3val:0x3821; valaddr_reg:x3; val_offset:1086*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:64 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 64, 0, x3, 1086*FLEN/8, x4, x1, x2)

inst_363:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x045 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x3bb and fs3 == 0 and fe3 == 0x0e and fm3 == 0x021 and fcsr == 0x60 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3845; op2val:0x3bbb;
op3val:0x3821; valaddr_reg:x3; val_offset:1089*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 96, 0, x3, 1089*FLEN/8, x4, x1, x2)

inst_364:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x045 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x3bb and fs3 == 0 and fe3 == 0x0e and fm3 == 0x021 and fcsr == 0x80 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3845; op2val:0x3bbb;
op3val:0x3821; valaddr_reg:x3; val_offset:1092*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:128 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 128, 0, x3, 1092*FLEN/8, x4, x1, x2)

inst_365:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x350 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x3db and fs3 == 0 and fe3 == 0x0e and fm3 == 0x32e and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3b50; op2val:0x3bdb;
op3val:0x3b2e; valaddr_reg:x3; val_offset:1095*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 1095*FLEN/8, x4, x1, x2)

inst_366:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x350 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x3db and fs3 == 0 and fe3 == 0x0e and fm3 == 0x32e and fcsr == 0x20 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3b50; op2val:0x3bdb;
op3val:0x3b2e; valaddr_reg:x3; val_offset:1098*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:32 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 32, 0, x3, 1098*FLEN/8, x4, x1, x2)

inst_367:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x350 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x3db and fs3 == 0 and fe3 == 0x0e and fm3 == 0x32e and fcsr == 0x40 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3b50; op2val:0x3bdb;
op3val:0x3b2e; valaddr_reg:x3; val_offset:1101*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:64 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 64, 0, x3, 1101*FLEN/8, x4, x1, x2)

inst_368:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x350 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x3db and fs3 == 0 and fe3 == 0x0e and fm3 == 0x32e and fcsr == 0x60 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3b50; op2val:0x3bdb;
op3val:0x3b2e; valaddr_reg:x3; val_offset:1104*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 96, 0, x3, 1104*FLEN/8, x4, x1, x2)

inst_369:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x350 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x3db and fs3 == 0 and fe3 == 0x0e and fm3 == 0x32e and fcsr == 0x80 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3b50; op2val:0x3bdb;
op3val:0x3b2e; valaddr_reg:x3; val_offset:1107*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:128 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 128, 0, x3, 1107*FLEN/8, x4, x1, x2)

inst_370:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x142 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x079 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x1e1 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3942; op2val:0x3c79;
op3val:0x39e1; valaddr_reg:x3; val_offset:1110*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 1110*FLEN/8, x4, x1, x2)

inst_371:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x142 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x079 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x1e1 and fcsr == 0x20 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3942; op2val:0x3c79;
op3val:0x39e1; valaddr_reg:x3; val_offset:1113*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:32 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 32, 0, x3, 1113*FLEN/8, x4, x1, x2)

inst_372:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x142 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x079 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x1e1 and fcsr == 0x40 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3942; op2val:0x3c79;
op3val:0x39e1; valaddr_reg:x3; val_offset:1116*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:64 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 64, 0, x3, 1116*FLEN/8, x4, x1, x2)

inst_373:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x142 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x079 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x1e1 and fcsr == 0x60 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3942; op2val:0x3c79;
op3val:0x39e1; valaddr_reg:x3; val_offset:1119*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 96, 0, x3, 1119*FLEN/8, x4, x1, x2)

inst_374:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x142 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x079 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x1e1 and fcsr == 0x80 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3942; op2val:0x3c79;
op3val:0x39e1; valaddr_reg:x3; val_offset:1122*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:128 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 128, 0, x3, 1122*FLEN/8, x4, x1, x2)

inst_375:
// fs1 == 0 and fe1 == 0x0c and fm1 == 0x17a and fs2 == 0 and fe2 == 0x11 and fm2 == 0x0e6 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x2b5 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x317a; op2val:0x44e6;
op3val:0x3ab5; valaddr_reg:x3; val_offset:1125*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 1125*FLEN/8, x4, x1, x2)

inst_376:
// fs1 == 0 and fe1 == 0x0c and fm1 == 0x17a and fs2 == 0 and fe2 == 0x11 and fm2 == 0x0e6 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x2b5 and fcsr == 0x20 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x317a; op2val:0x44e6;
op3val:0x3ab5; valaddr_reg:x3; val_offset:1128*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:32 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 32, 0, x3, 1128*FLEN/8, x4, x1, x2)

inst_377:
// fs1 == 0 and fe1 == 0x0c and fm1 == 0x17a and fs2 == 0 and fe2 == 0x11 and fm2 == 0x0e6 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x2b5 and fcsr == 0x40 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x317a; op2val:0x44e6;
op3val:0x3ab5; valaddr_reg:x3; val_offset:1131*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:64 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 64, 0, x3, 1131*FLEN/8, x4, x1, x2)

inst_378:
// fs1 == 0 and fe1 == 0x0c and fm1 == 0x17a and fs2 == 0 and fe2 == 0x11 and fm2 == 0x0e6 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x2b5 and fcsr == 0x60 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x317a; op2val:0x44e6;
op3val:0x3ab5; valaddr_reg:x3; val_offset:1134*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 96, 0, x3, 1134*FLEN/8, x4, x1, x2)

inst_379:
// fs1 == 0 and fe1 == 0x0c and fm1 == 0x17a and fs2 == 0 and fe2 == 0x11 and fm2 == 0x0e6 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x2b5 and fcsr == 0x80 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x317a; op2val:0x44e6;
op3val:0x3ab5; valaddr_reg:x3; val_offset:1137*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:128 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 128, 0, x3, 1137*FLEN/8, x4, x1, x2)

inst_380:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x3d0 and fs2 == 0 and fe2 == 0x0a and fm2 == 0x270 and fs3 == 0 and fe3 == 0x0a and fm3 == 0x248 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3bd0; op2val:0x2a70;
op3val:0x2a48; valaddr_reg:x3; val_offset:1140*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 1140*FLEN/8, x4, x1, x2)

inst_381:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x3d0 and fs2 == 0 and fe2 == 0x0a and fm2 == 0x270 and fs3 == 0 and fe3 == 0x0a and fm3 == 0x248 and fcsr == 0x20 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3bd0; op2val:0x2a70;
op3val:0x2a48; valaddr_reg:x3; val_offset:1143*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:32 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 32, 0, x3, 1143*FLEN/8, x4, x1, x2)

inst_382:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x3d0 and fs2 == 0 and fe2 == 0x0a and fm2 == 0x270 and fs3 == 0 and fe3 == 0x0a and fm3 == 0x248 and fcsr == 0x40 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3bd0; op2val:0x2a70;
op3val:0x2a48; valaddr_reg:x3; val_offset:1146*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:64 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 64, 0, x3, 1146*FLEN/8, x4, x1, x2)

inst_383:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x3d0 and fs2 == 0 and fe2 == 0x0a and fm2 == 0x270 and fs3 == 0 and fe3 == 0x0a and fm3 == 0x248 and fcsr == 0x60 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3bd0; op2val:0x2a70;
op3val:0x2a48; valaddr_reg:x3; val_offset:1149*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 96, 0, x3, 1149*FLEN/8, x4, x1, x2)
RVTEST_SIGBASE(x1,signature_x1_4)

inst_384:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x3d0 and fs2 == 0 and fe2 == 0x0a and fm2 == 0x270 and fs3 == 0 and fe3 == 0x0a and fm3 == 0x248 and fcsr == 0x80 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3bd0; op2val:0x2a70;
op3val:0x2a48; valaddr_reg:x3; val_offset:1152*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:128 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 128, 0, x3, 1152*FLEN/8, x4, x1, x2)

inst_385:
// fs1 == 0 and fe1 == 0x0d and fm1 == 0x38c and fs2 == 0 and fe2 == 0x0f and fm2 == 0x33c and fs3 == 0 and fe3 == 0x0e and fm3 == 0x2d3 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x378c; op2val:0x3f3c;
op3val:0x3ad3; valaddr_reg:x3; val_offset:1155*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 1155*FLEN/8, x4, x1, x2)

inst_386:
// fs1 == 0 and fe1 == 0x0d and fm1 == 0x38c and fs2 == 0 and fe2 == 0x0f and fm2 == 0x33c and fs3 == 0 and fe3 == 0x0e and fm3 == 0x2d3 and fcsr == 0x20 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x378c; op2val:0x3f3c;
op3val:0x3ad3; valaddr_reg:x3; val_offset:1158*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:32 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 32, 0, x3, 1158*FLEN/8, x4, x1, x2)

inst_387:
// fs1 == 0 and fe1 == 0x0d and fm1 == 0x38c and fs2 == 0 and fe2 == 0x0f and fm2 == 0x33c and fs3 == 0 and fe3 == 0x0e and fm3 == 0x2d3 and fcsr == 0x40 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x378c; op2val:0x3f3c;
op3val:0x3ad3; valaddr_reg:x3; val_offset:1161*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:64 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 64, 0, x3, 1161*FLEN/8, x4, x1, x2)

inst_388:
// fs1 == 0 and fe1 == 0x0d and fm1 == 0x38c and fs2 == 0 and fe2 == 0x0f and fm2 == 0x33c and fs3 == 0 and fe3 == 0x0e and fm3 == 0x2d3 and fcsr == 0x60 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x378c; op2val:0x3f3c;
op3val:0x3ad3; valaddr_reg:x3; val_offset:1164*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 96, 0, x3, 1164*FLEN/8, x4, x1, x2)

inst_389:
// fs1 == 0 and fe1 == 0x0d and fm1 == 0x38c and fs2 == 0 and fe2 == 0x0f and fm2 == 0x33c and fs3 == 0 and fe3 == 0x0e and fm3 == 0x2d3 and fcsr == 0x80 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x378c; op2val:0x3f3c;
op3val:0x3ad3; valaddr_reg:x3; val_offset:1167*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:128 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 128, 0, x3, 1167*FLEN/8, x4, x1, x2)

inst_390:
// fs1 == 0 and fe1 == 0x0d and fm1 == 0x34f and fs2 == 0 and fe2 == 0x10 and fm2 == 0x042 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x3c8 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x374f; op2val:0x4042;
op3val:0x3bc8; valaddr_reg:x3; val_offset:1170*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 1170*FLEN/8, x4, x1, x2)

inst_391:
// fs1 == 0 and fe1 == 0x0d and fm1 == 0x34f and fs2 == 0 and fe2 == 0x10 and fm2 == 0x042 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x3c8 and fcsr == 0x20 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x374f; op2val:0x4042;
op3val:0x3bc8; valaddr_reg:x3; val_offset:1173*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:32 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 32, 0, x3, 1173*FLEN/8, x4, x1, x2)

inst_392:
// fs1 == 0 and fe1 == 0x0d and fm1 == 0x34f and fs2 == 0 and fe2 == 0x10 and fm2 == 0x042 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x3c8 and fcsr == 0x40 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x374f; op2val:0x4042;
op3val:0x3bc8; valaddr_reg:x3; val_offset:1176*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:64 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 64, 0, x3, 1176*FLEN/8, x4, x1, x2)

inst_393:
// fs1 == 0 and fe1 == 0x0d and fm1 == 0x34f and fs2 == 0 and fe2 == 0x10 and fm2 == 0x042 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x3c8 and fcsr == 0x60 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x374f; op2val:0x4042;
op3val:0x3bc8; valaddr_reg:x3; val_offset:1179*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 96, 0, x3, 1179*FLEN/8, x4, x1, x2)

inst_394:
// fs1 == 0 and fe1 == 0x0d and fm1 == 0x34f and fs2 == 0 and fe2 == 0x10 and fm2 == 0x042 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x3c8 and fcsr == 0x80 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x374f; op2val:0x4042;
op3val:0x3bc8; valaddr_reg:x3; val_offset:1182*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:128 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 128, 0, x3, 1182*FLEN/8, x4, x1, x2)

inst_395:
// fs1 == 0 and fe1 == 0x0d and fm1 == 0x38c and fs2 == 0 and fe2 == 0x0a and fm2 == 0x1dd and fs3 == 0 and fe3 == 0x09 and fm3 == 0x184 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x378c; op2val:0x29dd;
op3val:0x2584; valaddr_reg:x3; val_offset:1185*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 1185*FLEN/8, x4, x1, x2)

inst_396:
// fs1 == 0 and fe1 == 0x0d and fm1 == 0x38c and fs2 == 0 and fe2 == 0x0a and fm2 == 0x1dd and fs3 == 0 and fe3 == 0x09 and fm3 == 0x184 and fcsr == 0x20 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x378c; op2val:0x29dd;
op3val:0x2584; valaddr_reg:x3; val_offset:1188*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:32 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 32, 0, x3, 1188*FLEN/8, x4, x1, x2)

inst_397:
// fs1 == 0 and fe1 == 0x0d and fm1 == 0x38c and fs2 == 0 and fe2 == 0x0a and fm2 == 0x1dd and fs3 == 0 and fe3 == 0x09 and fm3 == 0x184 and fcsr == 0x40 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x378c; op2val:0x29dd;
op3val:0x2584; valaddr_reg:x3; val_offset:1191*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:64 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 64, 0, x3, 1191*FLEN/8, x4, x1, x2)

inst_398:
// fs1 == 0 and fe1 == 0x0d and fm1 == 0x38c and fs2 == 0 and fe2 == 0x0a and fm2 == 0x1dd and fs3 == 0 and fe3 == 0x09 and fm3 == 0x184 and fcsr == 0x60 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x378c; op2val:0x29dd;
op3val:0x2584; valaddr_reg:x3; val_offset:1194*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 96, 0, x3, 1194*FLEN/8, x4, x1, x2)

inst_399:
// fs1 == 0 and fe1 == 0x0d and fm1 == 0x38c and fs2 == 0 and fe2 == 0x0a and fm2 == 0x1dd and fs3 == 0 and fe3 == 0x09 and fm3 == 0x184 and fcsr == 0x80 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x378c; op2val:0x29dd;
op3val:0x2584; valaddr_reg:x3; val_offset:1197*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:128 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 128, 0, x3, 1197*FLEN/8, x4, x1, x2)

inst_400:
// fs1 == 0 and fe1 == 0x0c and fm1 == 0x060 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x072 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x0dc and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3060; op2val:0x4072;
op3val:0x34dc; valaddr_reg:x3; val_offset:1200*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 1200*FLEN/8, x4, x1, x2)

inst_401:
// fs1 == 0 and fe1 == 0x0c and fm1 == 0x060 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x072 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x0dc and fcsr == 0x20 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3060; op2val:0x4072;
op3val:0x34dc; valaddr_reg:x3; val_offset:1203*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:32 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 32, 0, x3, 1203*FLEN/8, x4, x1, x2)

inst_402:
// fs1 == 0 and fe1 == 0x0c and fm1 == 0x060 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x072 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x0dc and fcsr == 0x40 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3060; op2val:0x4072;
op3val:0x34dc; valaddr_reg:x3; val_offset:1206*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:64 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 64, 0, x3, 1206*FLEN/8, x4, x1, x2)

inst_403:
// fs1 == 0 and fe1 == 0x0c and fm1 == 0x060 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x072 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x0dc and fcsr == 0x60 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3060; op2val:0x4072;
op3val:0x34dc; valaddr_reg:x3; val_offset:1209*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 96, 0, x3, 1209*FLEN/8, x4, x1, x2)

inst_404:
// fs1 == 0 and fe1 == 0x0c and fm1 == 0x060 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x072 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x0dc and fcsr == 0x80 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3060; op2val:0x4072;
op3val:0x34dc; valaddr_reg:x3; val_offset:1212*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:128 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 128, 0, x3, 1212*FLEN/8, x4, x1, x2)

inst_405:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x1e9 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x2db and fs3 == 0 and fe3 == 0x0e and fm3 == 0x111 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x39e9; op2val:0x3adb;
op3val:0x3911; valaddr_reg:x3; val_offset:1215*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 1215*FLEN/8, x4, x1, x2)

inst_406:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x1e9 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x2db and fs3 == 0 and fe3 == 0x0e and fm3 == 0x111 and fcsr == 0x20 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x39e9; op2val:0x3adb;
op3val:0x3911; valaddr_reg:x3; val_offset:1218*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:32 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 32, 0, x3, 1218*FLEN/8, x4, x1, x2)

inst_407:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x1e9 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x2db and fs3 == 0 and fe3 == 0x0e and fm3 == 0x111 and fcsr == 0x40 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x39e9; op2val:0x3adb;
op3val:0x3911; valaddr_reg:x3; val_offset:1221*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:64 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 64, 0, x3, 1221*FLEN/8, x4, x1, x2)

inst_408:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x1e9 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x2db and fs3 == 0 and fe3 == 0x0e and fm3 == 0x111 and fcsr == 0x60 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x39e9; op2val:0x3adb;
op3val:0x3911; valaddr_reg:x3; val_offset:1224*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 96, 0, x3, 1224*FLEN/8, x4, x1, x2)

inst_409:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x1e9 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x2db and fs3 == 0 and fe3 == 0x0e and fm3 == 0x111 and fcsr == 0x80 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x39e9; op2val:0x3adb;
op3val:0x3911; valaddr_reg:x3; val_offset:1227*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:128 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 128, 0, x3, 1227*FLEN/8, x4, x1, x2)

inst_410:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x2a9 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x061 and fs3 == 0 and fe3 == 0x0c and fm3 == 0x34c and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3aa9; op2val:0x3461;
op3val:0x334c; valaddr_reg:x3; val_offset:1230*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 1230*FLEN/8, x4, x1, x2)

inst_411:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x2a9 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x061 and fs3 == 0 and fe3 == 0x0c and fm3 == 0x34c and fcsr == 0x20 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3aa9; op2val:0x3461;
op3val:0x334c; valaddr_reg:x3; val_offset:1233*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:32 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 32, 0, x3, 1233*FLEN/8, x4, x1, x2)

inst_412:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x2a9 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x061 and fs3 == 0 and fe3 == 0x0c and fm3 == 0x34c and fcsr == 0x40 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3aa9; op2val:0x3461;
op3val:0x334c; valaddr_reg:x3; val_offset:1236*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:64 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 64, 0, x3, 1236*FLEN/8, x4, x1, x2)

inst_413:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x2a9 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x061 and fs3 == 0 and fe3 == 0x0c and fm3 == 0x34c and fcsr == 0x60 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3aa9; op2val:0x3461;
op3val:0x334c; valaddr_reg:x3; val_offset:1239*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 96, 0, x3, 1239*FLEN/8, x4, x1, x2)

inst_414:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x2a9 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x061 and fs3 == 0 and fe3 == 0x0c and fm3 == 0x34c and fcsr == 0x80 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3aa9; op2val:0x3461;
op3val:0x334c; valaddr_reg:x3; val_offset:1242*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:128 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 128, 0, x3, 1242*FLEN/8, x4, x1, x2)

inst_415:
// fs1 == 0 and fe1 == 0x0d and fm1 == 0x37a and fs2 == 0 and fe2 == 0x0d and fm2 == 0x391 and fs3 == 0 and fe3 == 0x0c and fm3 == 0x312 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x377a; op2val:0x3791;
op3val:0x3312; valaddr_reg:x3; val_offset:1245*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 1245*FLEN/8, x4, x1, x2)

inst_416:
// fs1 == 0 and fe1 == 0x0d and fm1 == 0x37a and fs2 == 0 and fe2 == 0x0d and fm2 == 0x391 and fs3 == 0 and fe3 == 0x0c and fm3 == 0x312 and fcsr == 0x20 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x377a; op2val:0x3791;
op3val:0x3312; valaddr_reg:x3; val_offset:1248*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:32 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 32, 0, x3, 1248*FLEN/8, x4, x1, x2)

inst_417:
// fs1 == 0 and fe1 == 0x0d and fm1 == 0x37a and fs2 == 0 and fe2 == 0x0d and fm2 == 0x391 and fs3 == 0 and fe3 == 0x0c and fm3 == 0x312 and fcsr == 0x40 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x377a; op2val:0x3791;
op3val:0x3312; valaddr_reg:x3; val_offset:1251*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:64 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 64, 0, x3, 1251*FLEN/8, x4, x1, x2)

inst_418:
// fs1 == 0 and fe1 == 0x0d and fm1 == 0x37a and fs2 == 0 and fe2 == 0x0d and fm2 == 0x391 and fs3 == 0 and fe3 == 0x0c and fm3 == 0x312 and fcsr == 0x60 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x377a; op2val:0x3791;
op3val:0x3312; valaddr_reg:x3; val_offset:1254*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 96, 0, x3, 1254*FLEN/8, x4, x1, x2)

inst_419:
// fs1 == 0 and fe1 == 0x0d and fm1 == 0x37a and fs2 == 0 and fe2 == 0x0d and fm2 == 0x391 and fs3 == 0 and fe3 == 0x0c and fm3 == 0x312 and fcsr == 0x80 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x377a; op2val:0x3791;
op3val:0x3312; valaddr_reg:x3; val_offset:1257*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:128 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 128, 0, x3, 1257*FLEN/8, x4, x1, x2)

inst_420:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x15c and fs2 == 0 and fe2 == 0x0f and fm2 == 0x0a2 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x237 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x395c; op2val:0x3ca2;
op3val:0x3a37; valaddr_reg:x3; val_offset:1260*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 1260*FLEN/8, x4, x1, x2)

inst_421:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x15c and fs2 == 0 and fe2 == 0x0f and fm2 == 0x0a2 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x237 and fcsr == 0x20 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x395c; op2val:0x3ca2;
op3val:0x3a37; valaddr_reg:x3; val_offset:1263*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:32 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 32, 0, x3, 1263*FLEN/8, x4, x1, x2)

inst_422:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x15c and fs2 == 0 and fe2 == 0x0f and fm2 == 0x0a2 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x237 and fcsr == 0x40 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x395c; op2val:0x3ca2;
op3val:0x3a37; valaddr_reg:x3; val_offset:1266*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:64 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 64, 0, x3, 1266*FLEN/8, x4, x1, x2)

inst_423:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x15c and fs2 == 0 and fe2 == 0x0f and fm2 == 0x0a2 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x237 and fcsr == 0x60 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x395c; op2val:0x3ca2;
op3val:0x3a37; valaddr_reg:x3; val_offset:1269*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 96, 0, x3, 1269*FLEN/8, x4, x1, x2)

inst_424:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x15c and fs2 == 0 and fe2 == 0x0f and fm2 == 0x0a2 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x237 and fcsr == 0x80 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x395c; op2val:0x3ca2;
op3val:0x3a37; valaddr_reg:x3; val_offset:1272*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:128 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 128, 0, x3, 1272*FLEN/8, x4, x1, x2)

inst_425:
// fs1 == 0 and fe1 == 0x0c and fm1 == 0x208 and fs2 == 0 and fe2 == 0x0b and fm2 == 0x125 and fs3 == 0 and fe3 == 0x08 and fm3 == 0x3bd and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3208; op2val:0x2d25;
op3val:0x23bd; valaddr_reg:x3; val_offset:1275*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 1275*FLEN/8, x4, x1, x2)

inst_426:
// fs1 == 0 and fe1 == 0x0c and fm1 == 0x208 and fs2 == 0 and fe2 == 0x0b and fm2 == 0x125 and fs3 == 0 and fe3 == 0x08 and fm3 == 0x3bd and fcsr == 0x20 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3208; op2val:0x2d25;
op3val:0x23bd; valaddr_reg:x3; val_offset:1278*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:32 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 32, 0, x3, 1278*FLEN/8, x4, x1, x2)

inst_427:
// fs1 == 0 and fe1 == 0x0c and fm1 == 0x208 and fs2 == 0 and fe2 == 0x0b and fm2 == 0x125 and fs3 == 0 and fe3 == 0x08 and fm3 == 0x3bd and fcsr == 0x40 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3208; op2val:0x2d25;
op3val:0x23bd; valaddr_reg:x3; val_offset:1281*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:64 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 64, 0, x3, 1281*FLEN/8, x4, x1, x2)

inst_428:
// fs1 == 0 and fe1 == 0x0c and fm1 == 0x208 and fs2 == 0 and fe2 == 0x0b and fm2 == 0x125 and fs3 == 0 and fe3 == 0x08 and fm3 == 0x3bd and fcsr == 0x60 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3208; op2val:0x2d25;
op3val:0x23bd; valaddr_reg:x3; val_offset:1284*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 96, 0, x3, 1284*FLEN/8, x4, x1, x2)

inst_429:
// fs1 == 0 and fe1 == 0x0c and fm1 == 0x208 and fs2 == 0 and fe2 == 0x0b and fm2 == 0x125 and fs3 == 0 and fe3 == 0x08 and fm3 == 0x3bd and fcsr == 0x80 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3208; op2val:0x2d25;
op3val:0x23bd; valaddr_reg:x3; val_offset:1287*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:128 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 128, 0, x3, 1287*FLEN/8, x4, x1, x2)

inst_430:
// fs1 == 0 and fe1 == 0x0c and fm1 == 0x0b7 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x143 and fs3 == 0 and fe3 == 0x0c and fm3 == 0x234 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x30b7; op2val:0x3d43;
op3val:0x3234; valaddr_reg:x3; val_offset:1290*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 1290*FLEN/8, x4, x1, x2)

inst_431:
// fs1 == 0 and fe1 == 0x0c and fm1 == 0x0b7 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x143 and fs3 == 0 and fe3 == 0x0c and fm3 == 0x234 and fcsr == 0x20 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x30b7; op2val:0x3d43;
op3val:0x3234; valaddr_reg:x3; val_offset:1293*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:32 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 32, 0, x3, 1293*FLEN/8, x4, x1, x2)

inst_432:
// fs1 == 0 and fe1 == 0x0c and fm1 == 0x0b7 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x143 and fs3 == 0 and fe3 == 0x0c and fm3 == 0x234 and fcsr == 0x40 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x30b7; op2val:0x3d43;
op3val:0x3234; valaddr_reg:x3; val_offset:1296*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:64 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 64, 0, x3, 1296*FLEN/8, x4, x1, x2)

inst_433:
// fs1 == 0 and fe1 == 0x0c and fm1 == 0x0b7 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x143 and fs3 == 0 and fe3 == 0x0c and fm3 == 0x234 and fcsr == 0x60 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x30b7; op2val:0x3d43;
op3val:0x3234; valaddr_reg:x3; val_offset:1299*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 96, 0, x3, 1299*FLEN/8, x4, x1, x2)

inst_434:
// fs1 == 0 and fe1 == 0x0c and fm1 == 0x0b7 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x143 and fs3 == 0 and fe3 == 0x0c and fm3 == 0x234 and fcsr == 0x80 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x30b7; op2val:0x3d43;
op3val:0x3234; valaddr_reg:x3; val_offset:1302*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:128 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 128, 0, x3, 1302*FLEN/8, x4, x1, x2)

inst_435:
// fs1 == 0 and fe1 == 0x0c and fm1 == 0x1d0 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x1ba and fs3 == 0 and fe3 == 0x0d and fm3 == 0x029 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x31d0; op2val:0x3dba;
op3val:0x3429; valaddr_reg:x3; val_offset:1305*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 1305*FLEN/8, x4, x1, x2)

inst_436:
// fs1 == 0 and fe1 == 0x0c and fm1 == 0x1d0 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x1ba and fs3 == 0 and fe3 == 0x0d and fm3 == 0x029 and fcsr == 0x20 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x31d0; op2val:0x3dba;
op3val:0x3429; valaddr_reg:x3; val_offset:1308*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:32 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 32, 0, x3, 1308*FLEN/8, x4, x1, x2)

inst_437:
// fs1 == 0 and fe1 == 0x0c and fm1 == 0x1d0 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x1ba and fs3 == 0 and fe3 == 0x0d and fm3 == 0x029 and fcsr == 0x40 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x31d0; op2val:0x3dba;
op3val:0x3429; valaddr_reg:x3; val_offset:1311*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:64 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 64, 0, x3, 1311*FLEN/8, x4, x1, x2)

inst_438:
// fs1 == 0 and fe1 == 0x0c and fm1 == 0x1d0 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x1ba and fs3 == 0 and fe3 == 0x0d and fm3 == 0x029 and fcsr == 0x60 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x31d0; op2val:0x3dba;
op3val:0x3429; valaddr_reg:x3; val_offset:1314*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 96, 0, x3, 1314*FLEN/8, x4, x1, x2)

inst_439:
// fs1 == 0 and fe1 == 0x0c and fm1 == 0x1d0 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x1ba and fs3 == 0 and fe3 == 0x0d and fm3 == 0x029 and fcsr == 0x80 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x31d0; op2val:0x3dba;
op3val:0x3429; valaddr_reg:x3; val_offset:1317*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:128 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 128, 0, x3, 1317*FLEN/8, x4, x1, x2)

inst_440:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x22f and fs2 == 0 and fe2 == 0x0e and fm2 == 0x0fd and fs3 == 0 and fe3 == 0x0d and fm3 == 0x3b7 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3a2f; op2val:0x38fd;
op3val:0x37b7; valaddr_reg:x3; val_offset:1320*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 1320*FLEN/8, x4, x1, x2)

inst_441:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x22f and fs2 == 0 and fe2 == 0x0e and fm2 == 0x0fd and fs3 == 0 and fe3 == 0x0d and fm3 == 0x3b7 and fcsr == 0x20 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3a2f; op2val:0x38fd;
op3val:0x37b7; valaddr_reg:x3; val_offset:1323*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:32 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 32, 0, x3, 1323*FLEN/8, x4, x1, x2)

inst_442:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x22f and fs2 == 0 and fe2 == 0x0e and fm2 == 0x0fd and fs3 == 0 and fe3 == 0x0d and fm3 == 0x3b7 and fcsr == 0x40 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3a2f; op2val:0x38fd;
op3val:0x37b7; valaddr_reg:x3; val_offset:1326*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:64 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 64, 0, x3, 1326*FLEN/8, x4, x1, x2)

inst_443:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x22f and fs2 == 0 and fe2 == 0x0e and fm2 == 0x0fd and fs3 == 0 and fe3 == 0x0d and fm3 == 0x3b7 and fcsr == 0x60 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3a2f; op2val:0x38fd;
op3val:0x37b7; valaddr_reg:x3; val_offset:1329*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 96, 0, x3, 1329*FLEN/8, x4, x1, x2)

inst_444:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x22f and fs2 == 0 and fe2 == 0x0e and fm2 == 0x0fd and fs3 == 0 and fe3 == 0x0d and fm3 == 0x3b7 and fcsr == 0x80 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3a2f; op2val:0x38fd;
op3val:0x37b7; valaddr_reg:x3; val_offset:1332*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:128 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 128, 0, x3, 1332*FLEN/8, x4, x1, x2)

inst_445:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x127 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x206 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x3c4 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3927; op2val:0x3e06;
op3val:0x3bc4; valaddr_reg:x3; val_offset:1335*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 1335*FLEN/8, x4, x1, x2)

inst_446:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x127 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x206 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x3c4 and fcsr == 0x20 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3927; op2val:0x3e06;
op3val:0x3bc4; valaddr_reg:x3; val_offset:1338*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:32 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 32, 0, x3, 1338*FLEN/8, x4, x1, x2)

inst_447:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x127 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x206 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x3c4 and fcsr == 0x40 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3927; op2val:0x3e06;
op3val:0x3bc4; valaddr_reg:x3; val_offset:1341*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:64 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 64, 0, x3, 1341*FLEN/8, x4, x1, x2)

inst_448:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x127 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x206 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x3c4 and fcsr == 0x60 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3927; op2val:0x3e06;
op3val:0x3bc4; valaddr_reg:x3; val_offset:1344*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 96, 0, x3, 1344*FLEN/8, x4, x1, x2)

inst_449:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x127 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x206 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x3c4 and fcsr == 0x80 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3927; op2val:0x3e06;
op3val:0x3bc4; valaddr_reg:x3; val_offset:1347*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:128 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 128, 0, x3, 1347*FLEN/8, x4, x1, x2)

inst_450:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x3c6 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x1ee and fs3 == 0 and fe3 == 0x0e and fm3 == 0x1c3 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3bc6; op2val:0x39ee;
op3val:0x39c3; valaddr_reg:x3; val_offset:1350*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 1350*FLEN/8, x4, x1, x2)

inst_451:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x3c6 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x1ee and fs3 == 0 and fe3 == 0x0e and fm3 == 0x1c3 and fcsr == 0x20 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3bc6; op2val:0x39ee;
op3val:0x39c3; valaddr_reg:x3; val_offset:1353*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:32 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 32, 0, x3, 1353*FLEN/8, x4, x1, x2)

inst_452:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x3c6 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x1ee and fs3 == 0 and fe3 == 0x0e and fm3 == 0x1c3 and fcsr == 0x40 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3bc6; op2val:0x39ee;
op3val:0x39c3; valaddr_reg:x3; val_offset:1356*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:64 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 64, 0, x3, 1356*FLEN/8, x4, x1, x2)

inst_453:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x3c6 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x1ee and fs3 == 0 and fe3 == 0x0e and fm3 == 0x1c3 and fcsr == 0x60 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3bc6; op2val:0x39ee;
op3val:0x39c3; valaddr_reg:x3; val_offset:1359*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 96, 0, x3, 1359*FLEN/8, x4, x1, x2)

inst_454:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x3c6 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x1ee and fs3 == 0 and fe3 == 0x0e and fm3 == 0x1c3 and fcsr == 0x80 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3bc6; op2val:0x39ee;
op3val:0x39c3; valaddr_reg:x3; val_offset:1362*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:128 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 128, 0, x3, 1362*FLEN/8, x4, x1, x2)

inst_455:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x1ed and fs2 == 0 and fe2 == 0x0d and fm2 == 0x2a4 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x0eb and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x39ed; op2val:0x36a4;
op3val:0x34eb; valaddr_reg:x3; val_offset:1365*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 1365*FLEN/8, x4, x1, x2)

inst_456:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x1ed and fs2 == 0 and fe2 == 0x0d and fm2 == 0x2a4 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x0eb and fcsr == 0x20 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x39ed; op2val:0x36a4;
op3val:0x34eb; valaddr_reg:x3; val_offset:1368*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:32 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 32, 0, x3, 1368*FLEN/8, x4, x1, x2)

inst_457:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x1ed and fs2 == 0 and fe2 == 0x0d and fm2 == 0x2a4 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x0eb and fcsr == 0x40 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x39ed; op2val:0x36a4;
op3val:0x34eb; valaddr_reg:x3; val_offset:1371*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:64 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 64, 0, x3, 1371*FLEN/8, x4, x1, x2)

inst_458:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x1ed and fs2 == 0 and fe2 == 0x0d and fm2 == 0x2a4 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x0eb and fcsr == 0x60 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x39ed; op2val:0x36a4;
op3val:0x34eb; valaddr_reg:x3; val_offset:1374*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 96, 0, x3, 1374*FLEN/8, x4, x1, x2)

inst_459:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x1ed and fs2 == 0 and fe2 == 0x0d and fm2 == 0x2a4 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x0eb and fcsr == 0x80 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x39ed; op2val:0x36a4;
op3val:0x34eb; valaddr_reg:x3; val_offset:1377*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:128 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 128, 0, x3, 1377*FLEN/8, x4, x1, x2)

inst_460:
// fs1 == 0 and fe1 == 0x0a and fm1 == 0x192 and fs2 == 0 and fe2 == 0x12 and fm2 == 0x259 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x06c and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x2992; op2val:0x4a59;
op3val:0x386c; valaddr_reg:x3; val_offset:1380*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 1380*FLEN/8, x4, x1, x2)

inst_461:
// fs1 == 0 and fe1 == 0x0a and fm1 == 0x192 and fs2 == 0 and fe2 == 0x12 and fm2 == 0x259 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x06c and fcsr == 0x20 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x2992; op2val:0x4a59;
op3val:0x386c; valaddr_reg:x3; val_offset:1383*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:32 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 32, 0, x3, 1383*FLEN/8, x4, x1, x2)

inst_462:
// fs1 == 0 and fe1 == 0x0a and fm1 == 0x192 and fs2 == 0 and fe2 == 0x12 and fm2 == 0x259 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x06c and fcsr == 0x40 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x2992; op2val:0x4a59;
op3val:0x386c; valaddr_reg:x3; val_offset:1386*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:64 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 64, 0, x3, 1386*FLEN/8, x4, x1, x2)

inst_463:
// fs1 == 0 and fe1 == 0x0a and fm1 == 0x192 and fs2 == 0 and fe2 == 0x12 and fm2 == 0x259 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x06c and fcsr == 0x60 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x2992; op2val:0x4a59;
op3val:0x386c; valaddr_reg:x3; val_offset:1389*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 96, 0, x3, 1389*FLEN/8, x4, x1, x2)

inst_464:
// fs1 == 0 and fe1 == 0x0a and fm1 == 0x192 and fs2 == 0 and fe2 == 0x12 and fm2 == 0x259 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x06c and fcsr == 0x80 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x2992; op2val:0x4a59;
op3val:0x386c; valaddr_reg:x3; val_offset:1392*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:128 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 128, 0, x3, 1392*FLEN/8, x4, x1, x2)

inst_465:
// fs1 == 0 and fe1 == 0x0b and fm1 == 0x008 and fs2 == 0 and fe2 == 0x0c and fm2 == 0x21d and fs3 == 0 and fe3 == 0x08 and fm3 == 0x225 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x2c08; op2val:0x321d;
op3val:0x2225; valaddr_reg:x3; val_offset:1395*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 1395*FLEN/8, x4, x1, x2)

inst_466:
// fs1 == 0 and fe1 == 0x0b and fm1 == 0x008 and fs2 == 0 and fe2 == 0x0c and fm2 == 0x21d and fs3 == 0 and fe3 == 0x08 and fm3 == 0x225 and fcsr == 0x20 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x2c08; op2val:0x321d;
op3val:0x2225; valaddr_reg:x3; val_offset:1398*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:32 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 32, 0, x3, 1398*FLEN/8, x4, x1, x2)

inst_467:
// fs1 == 0 and fe1 == 0x0b and fm1 == 0x008 and fs2 == 0 and fe2 == 0x0c and fm2 == 0x21d and fs3 == 0 and fe3 == 0x08 and fm3 == 0x225 and fcsr == 0x40 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x2c08; op2val:0x321d;
op3val:0x2225; valaddr_reg:x3; val_offset:1401*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:64 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 64, 0, x3, 1401*FLEN/8, x4, x1, x2)

inst_468:
// fs1 == 0 and fe1 == 0x0b and fm1 == 0x008 and fs2 == 0 and fe2 == 0x0c and fm2 == 0x21d and fs3 == 0 and fe3 == 0x08 and fm3 == 0x225 and fcsr == 0x60 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x2c08; op2val:0x321d;
op3val:0x2225; valaddr_reg:x3; val_offset:1404*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 96, 0, x3, 1404*FLEN/8, x4, x1, x2)

inst_469:
// fs1 == 0 and fe1 == 0x0b and fm1 == 0x008 and fs2 == 0 and fe2 == 0x0c and fm2 == 0x21d and fs3 == 0 and fe3 == 0x08 and fm3 == 0x225 and fcsr == 0x80 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x2c08; op2val:0x321d;
op3val:0x2225; valaddr_reg:x3; val_offset:1407*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:128 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 128, 0, x3, 1407*FLEN/8, x4, x1, x2)

inst_470:
// fs1 == 0 and fe1 == 0x0a and fm1 == 0x1c3 and fs2 == 0 and fe2 == 0x12 and fm2 == 0x30d and fs3 == 0 and fe3 == 0x0e and fm3 == 0x115 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x29c3; op2val:0x4b0d;
op3val:0x3915; valaddr_reg:x3; val_offset:1410*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 1410*FLEN/8, x4, x1, x2)

inst_471:
// fs1 == 0 and fe1 == 0x0a and fm1 == 0x1c3 and fs2 == 0 and fe2 == 0x12 and fm2 == 0x30d and fs3 == 0 and fe3 == 0x0e and fm3 == 0x115 and fcsr == 0x20 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x29c3; op2val:0x4b0d;
op3val:0x3915; valaddr_reg:x3; val_offset:1413*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:32 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 32, 0, x3, 1413*FLEN/8, x4, x1, x2)

inst_472:
// fs1 == 0 and fe1 == 0x0a and fm1 == 0x1c3 and fs2 == 0 and fe2 == 0x12 and fm2 == 0x30d and fs3 == 0 and fe3 == 0x0e and fm3 == 0x115 and fcsr == 0x40 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x29c3; op2val:0x4b0d;
op3val:0x3915; valaddr_reg:x3; val_offset:1416*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:64 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 64, 0, x3, 1416*FLEN/8, x4, x1, x2)

inst_473:
// fs1 == 0 and fe1 == 0x0a and fm1 == 0x1c3 and fs2 == 0 and fe2 == 0x12 and fm2 == 0x30d and fs3 == 0 and fe3 == 0x0e and fm3 == 0x115 and fcsr == 0x60 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x29c3; op2val:0x4b0d;
op3val:0x3915; valaddr_reg:x3; val_offset:1419*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 96, 0, x3, 1419*FLEN/8, x4, x1, x2)

inst_474:
// fs1 == 0 and fe1 == 0x0a and fm1 == 0x1c3 and fs2 == 0 and fe2 == 0x12 and fm2 == 0x30d and fs3 == 0 and fe3 == 0x0e and fm3 == 0x115 and fcsr == 0x80 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x29c3; op2val:0x4b0d;
op3val:0x3915; valaddr_reg:x3; val_offset:1422*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:128 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 128, 0, x3, 1422*FLEN/8, x4, x1, x2)

inst_475:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x23c and fs2 == 0 and fe2 == 0x0e and fm2 == 0x3ef and fs3 == 0 and fe3 == 0x0e and fm3 == 0x22f and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3a3c; op2val:0x3bef;
op3val:0x3a2f; valaddr_reg:x3; val_offset:1425*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 1425*FLEN/8, x4, x1, x2)

inst_476:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x23c and fs2 == 0 and fe2 == 0x0e and fm2 == 0x3ef and fs3 == 0 and fe3 == 0x0e and fm3 == 0x22f and fcsr == 0x20 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3a3c; op2val:0x3bef;
op3val:0x3a2f; valaddr_reg:x3; val_offset:1428*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:32 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 32, 0, x3, 1428*FLEN/8, x4, x1, x2)

inst_477:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x23c and fs2 == 0 and fe2 == 0x0e and fm2 == 0x3ef and fs3 == 0 and fe3 == 0x0e and fm3 == 0x22f and fcsr == 0x40 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3a3c; op2val:0x3bef;
op3val:0x3a2f; valaddr_reg:x3; val_offset:1431*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:64 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 64, 0, x3, 1431*FLEN/8, x4, x1, x2)

inst_478:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x23c and fs2 == 0 and fe2 == 0x0e and fm2 == 0x3ef and fs3 == 0 and fe3 == 0x0e and fm3 == 0x22f and fcsr == 0x60 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3a3c; op2val:0x3bef;
op3val:0x3a2f; valaddr_reg:x3; val_offset:1434*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 96, 0, x3, 1434*FLEN/8, x4, x1, x2)

inst_479:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x23c and fs2 == 0 and fe2 == 0x0e and fm2 == 0x3ef and fs3 == 0 and fe3 == 0x0e and fm3 == 0x22f and fcsr == 0x80 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3a3c; op2val:0x3bef;
op3val:0x3a2f; valaddr_reg:x3; val_offset:1437*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:128 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 128, 0, x3, 1437*FLEN/8, x4, x1, x2)

inst_480:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x26d and fs2 == 0 and fe2 == 0x0e and fm2 == 0x3ec and fs3 == 0 and fe3 == 0x0e and fm3 == 0x25d and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3a6d; op2val:0x3bec;
op3val:0x3a5d; valaddr_reg:x3; val_offset:1440*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 1440*FLEN/8, x4, x1, x2)

inst_481:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x26d and fs2 == 0 and fe2 == 0x0e and fm2 == 0x3ec and fs3 == 0 and fe3 == 0x0e and fm3 == 0x25d and fcsr == 0x20 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3a6d; op2val:0x3bec;
op3val:0x3a5d; valaddr_reg:x3; val_offset:1443*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:32 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 32, 0, x3, 1443*FLEN/8, x4, x1, x2)

inst_482:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x26d and fs2 == 0 and fe2 == 0x0e and fm2 == 0x3ec and fs3 == 0 and fe3 == 0x0e and fm3 == 0x25d and fcsr == 0x40 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3a6d; op2val:0x3bec;
op3val:0x3a5d; valaddr_reg:x3; val_offset:1446*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:64 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 64, 0, x3, 1446*FLEN/8, x4, x1, x2)

inst_483:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x26d and fs2 == 0 and fe2 == 0x0e and fm2 == 0x3ec and fs3 == 0 and fe3 == 0x0e and fm3 == 0x25d and fcsr == 0x60 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3a6d; op2val:0x3bec;
op3val:0x3a5d; valaddr_reg:x3; val_offset:1449*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 96, 0, x3, 1449*FLEN/8, x4, x1, x2)

inst_484:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x26d and fs2 == 0 and fe2 == 0x0e and fm2 == 0x3ec and fs3 == 0 and fe3 == 0x0e and fm3 == 0x25d and fcsr == 0x80 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3a6d; op2val:0x3bec;
op3val:0x3a5d; valaddr_reg:x3; val_offset:1452*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:128 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 128, 0, x3, 1452*FLEN/8, x4, x1, x2)

inst_485:
// fs1 == 0 and fe1 == 0x0d and fm1 == 0x203 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x03e and fs3 == 0 and fe3 == 0x0b and fm3 == 0x261 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3603; op2val:0x343e;
op3val:0x2e61; valaddr_reg:x3; val_offset:1455*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 1455*FLEN/8, x4, x1, x2)

inst_486:
// fs1 == 0 and fe1 == 0x0d and fm1 == 0x203 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x03e and fs3 == 0 and fe3 == 0x0b and fm3 == 0x261 and fcsr == 0x20 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3603; op2val:0x343e;
op3val:0x2e61; valaddr_reg:x3; val_offset:1458*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:32 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 32, 0, x3, 1458*FLEN/8, x4, x1, x2)

inst_487:
// fs1 == 0 and fe1 == 0x0d and fm1 == 0x203 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x03e and fs3 == 0 and fe3 == 0x0b and fm3 == 0x261 and fcsr == 0x40 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3603; op2val:0x343e;
op3val:0x2e61; valaddr_reg:x3; val_offset:1461*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:64 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 64, 0, x3, 1461*FLEN/8, x4, x1, x2)

inst_488:
// fs1 == 0 and fe1 == 0x0d and fm1 == 0x203 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x03e and fs3 == 0 and fe3 == 0x0b and fm3 == 0x261 and fcsr == 0x60 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3603; op2val:0x343e;
op3val:0x2e61; valaddr_reg:x3; val_offset:1464*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 96, 0, x3, 1464*FLEN/8, x4, x1, x2)

inst_489:
// fs1 == 0 and fe1 == 0x0d and fm1 == 0x203 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x03e and fs3 == 0 and fe3 == 0x0b and fm3 == 0x261 and fcsr == 0x80 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3603; op2val:0x343e;
op3val:0x2e61; valaddr_reg:x3; val_offset:1467*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:128 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 128, 0, x3, 1467*FLEN/8, x4, x1, x2)

inst_490:
// fs1 == 0 and fe1 == 0x0c and fm1 == 0x11b and fs2 == 0 and fe2 == 0x10 and fm2 == 0x286 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x02a and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x311b; op2val:0x4286;
op3val:0x382a; valaddr_reg:x3; val_offset:1470*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 1470*FLEN/8, x4, x1, x2)

inst_491:
// fs1 == 0 and fe1 == 0x0c and fm1 == 0x11b and fs2 == 0 and fe2 == 0x10 and fm2 == 0x286 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x02a and fcsr == 0x20 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x311b; op2val:0x4286;
op3val:0x382a; valaddr_reg:x3; val_offset:1473*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:32 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 32, 0, x3, 1473*FLEN/8, x4, x1, x2)

inst_492:
// fs1 == 0 and fe1 == 0x0c and fm1 == 0x11b and fs2 == 0 and fe2 == 0x10 and fm2 == 0x286 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x02a and fcsr == 0x40 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x311b; op2val:0x4286;
op3val:0x382a; valaddr_reg:x3; val_offset:1476*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:64 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 64, 0, x3, 1476*FLEN/8, x4, x1, x2)

inst_493:
// fs1 == 0 and fe1 == 0x0c and fm1 == 0x11b and fs2 == 0 and fe2 == 0x10 and fm2 == 0x286 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x02a and fcsr == 0x60 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x311b; op2val:0x4286;
op3val:0x382a; valaddr_reg:x3; val_offset:1479*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 96, 0, x3, 1479*FLEN/8, x4, x1, x2)

inst_494:
// fs1 == 0 and fe1 == 0x0c and fm1 == 0x11b and fs2 == 0 and fe2 == 0x10 and fm2 == 0x286 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x02a and fcsr == 0x80 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x311b; op2val:0x4286;
op3val:0x382a; valaddr_reg:x3; val_offset:1482*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:128 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 128, 0, x3, 1482*FLEN/8, x4, x1, x2)

inst_495:
// fs1 == 0 and fe1 == 0x0d and fm1 == 0x18d and fs2 == 0 and fe2 == 0x0e and fm2 == 0x09e and fs3 == 0 and fe3 == 0x0c and fm3 == 0x269 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x358d; op2val:0x389e;
op3val:0x3269; valaddr_reg:x3; val_offset:1485*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 1485*FLEN/8, x4, x1, x2)

inst_496:
// fs1 == 0 and fe1 == 0x0d and fm1 == 0x18d and fs2 == 0 and fe2 == 0x0e and fm2 == 0x09e and fs3 == 0 and fe3 == 0x0c and fm3 == 0x269 and fcsr == 0x20 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x358d; op2val:0x389e;
op3val:0x3269; valaddr_reg:x3; val_offset:1488*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:32 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 32, 0, x3, 1488*FLEN/8, x4, x1, x2)

inst_497:
// fs1 == 0 and fe1 == 0x0d and fm1 == 0x18d and fs2 == 0 and fe2 == 0x0e and fm2 == 0x09e and fs3 == 0 and fe3 == 0x0c and fm3 == 0x269 and fcsr == 0x40 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x358d; op2val:0x389e;
op3val:0x3269; valaddr_reg:x3; val_offset:1491*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:64 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 64, 0, x3, 1491*FLEN/8, x4, x1, x2)

inst_498:
// fs1 == 0 and fe1 == 0x0d and fm1 == 0x18d and fs2 == 0 and fe2 == 0x0e and fm2 == 0x09e and fs3 == 0 and fe3 == 0x0c and fm3 == 0x269 and fcsr == 0x60 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x358d; op2val:0x389e;
op3val:0x3269; valaddr_reg:x3; val_offset:1494*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 96, 0, x3, 1494*FLEN/8, x4, x1, x2)

inst_499:
// fs1 == 0 and fe1 == 0x0d and fm1 == 0x18d and fs2 == 0 and fe2 == 0x0e and fm2 == 0x09e and fs3 == 0 and fe3 == 0x0c and fm3 == 0x269 and fcsr == 0x80 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x358d; op2val:0x389e;
op3val:0x3269; valaddr_reg:x3; val_offset:1497*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:128 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 128, 0, x3, 1497*FLEN/8, x4, x1, x2)

inst_500:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x352 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x1ef and fs3 == 0 and fe3 == 0x0d and fm3 == 0x16e and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3b52; op2val:0x35ef;
op3val:0x356e; valaddr_reg:x3; val_offset:1500*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 1500*FLEN/8, x4, x1, x2)

inst_501:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x352 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x1ef and fs3 == 0 and fe3 == 0x0d and fm3 == 0x16e and fcsr == 0x20 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3b52; op2val:0x35ef;
op3val:0x356e; valaddr_reg:x3; val_offset:1503*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:32 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 32, 0, x3, 1503*FLEN/8, x4, x1, x2)

inst_502:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x352 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x1ef and fs3 == 0 and fe3 == 0x0d and fm3 == 0x16e and fcsr == 0x40 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3b52; op2val:0x35ef;
op3val:0x356e; valaddr_reg:x3; val_offset:1506*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:64 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 64, 0, x3, 1506*FLEN/8, x4, x1, x2)

inst_503:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x352 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x1ef and fs3 == 0 and fe3 == 0x0d and fm3 == 0x16e and fcsr == 0x60 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3b52; op2val:0x35ef;
op3val:0x356e; valaddr_reg:x3; val_offset:1509*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 96, 0, x3, 1509*FLEN/8, x4, x1, x2)

inst_504:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x352 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x1ef and fs3 == 0 and fe3 == 0x0d and fm3 == 0x16e and fcsr == 0x80 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3b52; op2val:0x35ef;
op3val:0x356e; valaddr_reg:x3; val_offset:1512*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:128 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 128, 0, x3, 1512*FLEN/8, x4, x1, x2)

inst_505:
// fs1 == 0 and fe1 == 0x0b and fm1 == 0x1c6 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x0d3 and fs3 == 0 and fe3 == 0x0c and fm3 == 0x2f7 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x2dc6; op2val:0x40d3;
op3val:0x32f7; valaddr_reg:x3; val_offset:1515*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 1515*FLEN/8, x4, x1, x2)

inst_506:
// fs1 == 0 and fe1 == 0x0b and fm1 == 0x1c6 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x0d3 and fs3 == 0 and fe3 == 0x0c and fm3 == 0x2f7 and fcsr == 0x20 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x2dc6; op2val:0x40d3;
op3val:0x32f7; valaddr_reg:x3; val_offset:1518*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:32 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 32, 0, x3, 1518*FLEN/8, x4, x1, x2)

inst_507:
// fs1 == 0 and fe1 == 0x0b and fm1 == 0x1c6 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x0d3 and fs3 == 0 and fe3 == 0x0c and fm3 == 0x2f7 and fcsr == 0x40 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x2dc6; op2val:0x40d3;
op3val:0x32f7; valaddr_reg:x3; val_offset:1521*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:64 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 64, 0, x3, 1521*FLEN/8, x4, x1, x2)

inst_508:
// fs1 == 0 and fe1 == 0x0b and fm1 == 0x1c6 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x0d3 and fs3 == 0 and fe3 == 0x0c and fm3 == 0x2f7 and fcsr == 0x60 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x2dc6; op2val:0x40d3;
op3val:0x32f7; valaddr_reg:x3; val_offset:1524*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 96, 0, x3, 1524*FLEN/8, x4, x1, x2)

inst_509:
// fs1 == 0 and fe1 == 0x0b and fm1 == 0x1c6 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x0d3 and fs3 == 0 and fe3 == 0x0c and fm3 == 0x2f7 and fcsr == 0x80 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x2dc6; op2val:0x40d3;
op3val:0x32f7; valaddr_reg:x3; val_offset:1527*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:128 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 128, 0, x3, 1527*FLEN/8, x4, x1, x2)

inst_510:
// fs1 == 0 and fe1 == 0x0c and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x10 and fm2 == 0x02d and fs3 == 0 and fe3 == 0x0e and fm3 == 0x02d and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x33ff; op2val:0x402d;
op3val:0x382d; valaddr_reg:x3; val_offset:1530*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 1530*FLEN/8, x4, x1, x2)

inst_511:
// fs1 == 0 and fe1 == 0x0c and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x10 and fm2 == 0x02d and fs3 == 0 and fe3 == 0x0e and fm3 == 0x02d and fcsr == 0x20 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x33ff; op2val:0x402d;
op3val:0x382d; valaddr_reg:x3; val_offset:1533*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:32 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 32, 0, x3, 1533*FLEN/8, x4, x1, x2)
RVTEST_SIGBASE(x1,signature_x1_5)

inst_512:
// fs1 == 0 and fe1 == 0x0c and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x10 and fm2 == 0x02d and fs3 == 0 and fe3 == 0x0e and fm3 == 0x02d and fcsr == 0x40 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x33ff; op2val:0x402d;
op3val:0x382d; valaddr_reg:x3; val_offset:1536*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:64 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 64, 0, x3, 1536*FLEN/8, x4, x1, x2)

inst_513:
// fs1 == 0 and fe1 == 0x0c and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x10 and fm2 == 0x02d and fs3 == 0 and fe3 == 0x0e and fm3 == 0x02d and fcsr == 0x60 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x33ff; op2val:0x402d;
op3val:0x382d; valaddr_reg:x3; val_offset:1539*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 96, 0, x3, 1539*FLEN/8, x4, x1, x2)

inst_514:
// fs1 == 0 and fe1 == 0x0c and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x10 and fm2 == 0x02d and fs3 == 0 and fe3 == 0x0e and fm3 == 0x02d and fcsr == 0x80 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x33ff; op2val:0x402d;
op3val:0x382d; valaddr_reg:x3; val_offset:1542*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:128 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 128, 0, x3, 1542*FLEN/8, x4, x1, x2)

inst_515:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x292 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x01b and fs3 == 0 and fe3 == 0x0c and fm3 == 0x2bf and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3a92; op2val:0x341b;
op3val:0x32bf; valaddr_reg:x3; val_offset:1545*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 1545*FLEN/8, x4, x1, x2)

inst_516:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x292 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x01b and fs3 == 0 and fe3 == 0x0c and fm3 == 0x2bf and fcsr == 0x20 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3a92; op2val:0x341b;
op3val:0x32bf; valaddr_reg:x3; val_offset:1548*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:32 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 32, 0, x3, 1548*FLEN/8, x4, x1, x2)

inst_517:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x292 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x01b and fs3 == 0 and fe3 == 0x0c and fm3 == 0x2bf and fcsr == 0x40 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3a92; op2val:0x341b;
op3val:0x32bf; valaddr_reg:x3; val_offset:1551*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:64 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 64, 0, x3, 1551*FLEN/8, x4, x1, x2)

inst_518:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x292 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x01b and fs3 == 0 and fe3 == 0x0c and fm3 == 0x2bf and fcsr == 0x60 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3a92; op2val:0x341b;
op3val:0x32bf; valaddr_reg:x3; val_offset:1554*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 96, 0, x3, 1554*FLEN/8, x4, x1, x2)

inst_519:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x292 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x01b and fs3 == 0 and fe3 == 0x0c and fm3 == 0x2bf and fcsr == 0x80 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3a92; op2val:0x341b;
op3val:0x32bf; valaddr_reg:x3; val_offset:1557*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:128 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 128, 0, x3, 1557*FLEN/8, x4, x1, x2)

inst_520:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x157 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x0c6 and fs3 == 0 and fe3 == 0x0c and fm3 == 0x25f and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3957; op2val:0x34c6;
op3val:0x325f; valaddr_reg:x3; val_offset:1560*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 1560*FLEN/8, x4, x1, x2)

inst_521:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x157 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x0c6 and fs3 == 0 and fe3 == 0x0c and fm3 == 0x25f and fcsr == 0x20 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3957; op2val:0x34c6;
op3val:0x325f; valaddr_reg:x3; val_offset:1563*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:32 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 32, 0, x3, 1563*FLEN/8, x4, x1, x2)

inst_522:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x157 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x0c6 and fs3 == 0 and fe3 == 0x0c and fm3 == 0x25f and fcsr == 0x40 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3957; op2val:0x34c6;
op3val:0x325f; valaddr_reg:x3; val_offset:1566*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:64 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 64, 0, x3, 1566*FLEN/8, x4, x1, x2)

inst_523:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x157 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x0c6 and fs3 == 0 and fe3 == 0x0c and fm3 == 0x25f and fcsr == 0x60 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3957; op2val:0x34c6;
op3val:0x325f; valaddr_reg:x3; val_offset:1569*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 96, 0, x3, 1569*FLEN/8, x4, x1, x2)

inst_524:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x157 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x0c6 and fs3 == 0 and fe3 == 0x0c and fm3 == 0x25f and fcsr == 0x80 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3957; op2val:0x34c6;
op3val:0x325f; valaddr_reg:x3; val_offset:1572*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:128 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 128, 0, x3, 1572*FLEN/8, x4, x1, x2)

inst_525:
// fs1 == 0 and fe1 == 0x09 and fm1 == 0x344 and fs2 == 0 and fe2 == 0x13 and fm2 == 0x152 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x0d5 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x2744; op2val:0x4d52;
op3val:0x38d5; valaddr_reg:x3; val_offset:1575*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 1575*FLEN/8, x4, x1, x2)

inst_526:
// fs1 == 0 and fe1 == 0x09 and fm1 == 0x344 and fs2 == 0 and fe2 == 0x13 and fm2 == 0x152 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x0d5 and fcsr == 0x20 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x2744; op2val:0x4d52;
op3val:0x38d5; valaddr_reg:x3; val_offset:1578*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:32 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 32, 0, x3, 1578*FLEN/8, x4, x1, x2)

inst_527:
// fs1 == 0 and fe1 == 0x09 and fm1 == 0x344 and fs2 == 0 and fe2 == 0x13 and fm2 == 0x152 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x0d5 and fcsr == 0x40 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x2744; op2val:0x4d52;
op3val:0x38d5; valaddr_reg:x3; val_offset:1581*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:64 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 64, 0, x3, 1581*FLEN/8, x4, x1, x2)

inst_528:
// fs1 == 0 and fe1 == 0x09 and fm1 == 0x344 and fs2 == 0 and fe2 == 0x13 and fm2 == 0x152 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x0d5 and fcsr == 0x60 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x2744; op2val:0x4d52;
op3val:0x38d5; valaddr_reg:x3; val_offset:1584*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 96, 0, x3, 1584*FLEN/8, x4, x1, x2)

inst_529:
// fs1 == 0 and fe1 == 0x09 and fm1 == 0x344 and fs2 == 0 and fe2 == 0x13 and fm2 == 0x152 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x0d5 and fcsr == 0x80 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x2744; op2val:0x4d52;
op3val:0x38d5; valaddr_reg:x3; val_offset:1587*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:128 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 128, 0, x3, 1587*FLEN/8, x4, x1, x2)

inst_530:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x0c9 and fs2 == 0 and fe2 == 0x0b and fm2 == 0x1b2 and fs3 == 0 and fe3 == 0x0a and fm3 == 0x2d0 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x38c9; op2val:0x2db2;
op3val:0x2ad0; valaddr_reg:x3; val_offset:1590*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 1590*FLEN/8, x4, x1, x2)

inst_531:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x0c9 and fs2 == 0 and fe2 == 0x0b and fm2 == 0x1b2 and fs3 == 0 and fe3 == 0x0a and fm3 == 0x2d0 and fcsr == 0x20 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x38c9; op2val:0x2db2;
op3val:0x2ad0; valaddr_reg:x3; val_offset:1593*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:32 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 32, 0, x3, 1593*FLEN/8, x4, x1, x2)

inst_532:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x0c9 and fs2 == 0 and fe2 == 0x0b and fm2 == 0x1b2 and fs3 == 0 and fe3 == 0x0a and fm3 == 0x2d0 and fcsr == 0x40 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x38c9; op2val:0x2db2;
op3val:0x2ad0; valaddr_reg:x3; val_offset:1596*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:64 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 64, 0, x3, 1596*FLEN/8, x4, x1, x2)

inst_533:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x0c9 and fs2 == 0 and fe2 == 0x0b and fm2 == 0x1b2 and fs3 == 0 and fe3 == 0x0a and fm3 == 0x2d0 and fcsr == 0x60 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x38c9; op2val:0x2db2;
op3val:0x2ad0; valaddr_reg:x3; val_offset:1599*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 96, 0, x3, 1599*FLEN/8, x4, x1, x2)

inst_534:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x0c9 and fs2 == 0 and fe2 == 0x0b and fm2 == 0x1b2 and fs3 == 0 and fe3 == 0x0a and fm3 == 0x2d0 and fcsr == 0x80 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x38c9; op2val:0x2db2;
op3val:0x2ad0; valaddr_reg:x3; val_offset:1602*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:128 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 128, 0, x3, 1602*FLEN/8, x4, x1, x2)

inst_535:
// fs1 == 0 and fe1 == 0x0d and fm1 == 0x067 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x208 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x2a3 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3467; op2val:0x4208;
op3val:0x3aa3; valaddr_reg:x3; val_offset:1605*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 1605*FLEN/8, x4, x1, x2)

inst_536:
// fs1 == 0 and fe1 == 0x0d and fm1 == 0x067 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x208 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x2a3 and fcsr == 0x20 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3467; op2val:0x4208;
op3val:0x3aa3; valaddr_reg:x3; val_offset:1608*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:32 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 32, 0, x3, 1608*FLEN/8, x4, x1, x2)

inst_537:
// fs1 == 0 and fe1 == 0x0d and fm1 == 0x067 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x208 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x2a3 and fcsr == 0x40 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3467; op2val:0x4208;
op3val:0x3aa3; valaddr_reg:x3; val_offset:1611*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:64 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 64, 0, x3, 1611*FLEN/8, x4, x1, x2)

inst_538:
// fs1 == 0 and fe1 == 0x0d and fm1 == 0x067 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x208 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x2a3 and fcsr == 0x60 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3467; op2val:0x4208;
op3val:0x3aa3; valaddr_reg:x3; val_offset:1614*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 96, 0, x3, 1614*FLEN/8, x4, x1, x2)

inst_539:
// fs1 == 0 and fe1 == 0x0d and fm1 == 0x067 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x208 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x2a3 and fcsr == 0x80 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3467; op2val:0x4208;
op3val:0x3aa3; valaddr_reg:x3; val_offset:1617*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:128 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 128, 0, x3, 1617*FLEN/8, x4, x1, x2)

inst_540:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x2fb and fs2 == 0 and fe2 == 0x0e and fm2 == 0x3c7 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x2ca and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3afb; op2val:0x3bc7;
op3val:0x3aca; valaddr_reg:x3; val_offset:1620*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 1620*FLEN/8, x4, x1, x2)

inst_541:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x2fb and fs2 == 0 and fe2 == 0x0e and fm2 == 0x3c7 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x2ca and fcsr == 0x20 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3afb; op2val:0x3bc7;
op3val:0x3aca; valaddr_reg:x3; val_offset:1623*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:32 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 32, 0, x3, 1623*FLEN/8, x4, x1, x2)

inst_542:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x2fb and fs2 == 0 and fe2 == 0x0e and fm2 == 0x3c7 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x2ca and fcsr == 0x40 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3afb; op2val:0x3bc7;
op3val:0x3aca; valaddr_reg:x3; val_offset:1626*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:64 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 64, 0, x3, 1626*FLEN/8, x4, x1, x2)

inst_543:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x2fb and fs2 == 0 and fe2 == 0x0e and fm2 == 0x3c7 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x2ca and fcsr == 0x60 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3afb; op2val:0x3bc7;
op3val:0x3aca; valaddr_reg:x3; val_offset:1629*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 96, 0, x3, 1629*FLEN/8, x4, x1, x2)

inst_544:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x2fb and fs2 == 0 and fe2 == 0x0e and fm2 == 0x3c7 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x2ca and fcsr == 0x80 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3afb; op2val:0x3bc7;
op3val:0x3aca; valaddr_reg:x3; val_offset:1632*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:128 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 128, 0, x3, 1632*FLEN/8, x4, x1, x2)

inst_545:
// fs1 == 0 and fe1 == 0x0b and fm1 == 0x217 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x011 and fs3 == 0 and fe3 == 0x0c and fm3 == 0x231 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x2e17; op2val:0x4011;
op3val:0x3231; valaddr_reg:x3; val_offset:1635*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 1635*FLEN/8, x4, x1, x2)

inst_546:
// fs1 == 0 and fe1 == 0x0b and fm1 == 0x217 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x011 and fs3 == 0 and fe3 == 0x0c and fm3 == 0x231 and fcsr == 0x20 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x2e17; op2val:0x4011;
op3val:0x3231; valaddr_reg:x3; val_offset:1638*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:32 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 32, 0, x3, 1638*FLEN/8, x4, x1, x2)

inst_547:
// fs1 == 0 and fe1 == 0x0b and fm1 == 0x217 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x011 and fs3 == 0 and fe3 == 0x0c and fm3 == 0x231 and fcsr == 0x40 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x2e17; op2val:0x4011;
op3val:0x3231; valaddr_reg:x3; val_offset:1641*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:64 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 64, 0, x3, 1641*FLEN/8, x4, x1, x2)

inst_548:
// fs1 == 0 and fe1 == 0x0b and fm1 == 0x217 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x011 and fs3 == 0 and fe3 == 0x0c and fm3 == 0x231 and fcsr == 0x60 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x2e17; op2val:0x4011;
op3val:0x3231; valaddr_reg:x3; val_offset:1644*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 96, 0, x3, 1644*FLEN/8, x4, x1, x2)

inst_549:
// fs1 == 0 and fe1 == 0x0b and fm1 == 0x217 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x011 and fs3 == 0 and fe3 == 0x0c and fm3 == 0x231 and fcsr == 0x80 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x2e17; op2val:0x4011;
op3val:0x3231; valaddr_reg:x3; val_offset:1647*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:128 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 128, 0, x3, 1647*FLEN/8, x4, x1, x2)

inst_550:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x2d4 and fs2 == 0 and fe2 == 0x0c and fm2 == 0x281 and fs3 == 0 and fe3 == 0x0c and fm3 == 0x18d and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3ad4; op2val:0x3281;
op3val:0x318d; valaddr_reg:x3; val_offset:1650*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 1650*FLEN/8, x4, x1, x2)

inst_551:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x2d4 and fs2 == 0 and fe2 == 0x0c and fm2 == 0x281 and fs3 == 0 and fe3 == 0x0c and fm3 == 0x18d and fcsr == 0x20 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3ad4; op2val:0x3281;
op3val:0x318d; valaddr_reg:x3; val_offset:1653*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:32 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 32, 0, x3, 1653*FLEN/8, x4, x1, x2)

inst_552:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x2d4 and fs2 == 0 and fe2 == 0x0c and fm2 == 0x281 and fs3 == 0 and fe3 == 0x0c and fm3 == 0x18d and fcsr == 0x40 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3ad4; op2val:0x3281;
op3val:0x318d; valaddr_reg:x3; val_offset:1656*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:64 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 64, 0, x3, 1656*FLEN/8, x4, x1, x2)

inst_553:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x2d4 and fs2 == 0 and fe2 == 0x0c and fm2 == 0x281 and fs3 == 0 and fe3 == 0x0c and fm3 == 0x18d and fcsr == 0x60 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3ad4; op2val:0x3281;
op3val:0x318d; valaddr_reg:x3; val_offset:1659*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 96, 0, x3, 1659*FLEN/8, x4, x1, x2)

inst_554:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x2d4 and fs2 == 0 and fe2 == 0x0c and fm2 == 0x281 and fs3 == 0 and fe3 == 0x0c and fm3 == 0x18d and fcsr == 0x80 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3ad4; op2val:0x3281;
op3val:0x318d; valaddr_reg:x3; val_offset:1662*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:128 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 128, 0, x3, 1662*FLEN/8, x4, x1, x2)

inst_555:
// fs1 == 0 and fe1 == 0x09 and fm1 == 0x10d and fs2 == 0 and fe2 == 0x13 and fm2 == 0x057 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x17b and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x250d; op2val:0x4c57;
op3val:0x357b; valaddr_reg:x3; val_offset:1665*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 1665*FLEN/8, x4, x1, x2)

inst_556:
// fs1 == 0 and fe1 == 0x09 and fm1 == 0x10d and fs2 == 0 and fe2 == 0x13 and fm2 == 0x057 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x17b and fcsr == 0x20 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x250d; op2val:0x4c57;
op3val:0x357b; valaddr_reg:x3; val_offset:1668*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:32 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 32, 0, x3, 1668*FLEN/8, x4, x1, x2)

inst_557:
// fs1 == 0 and fe1 == 0x09 and fm1 == 0x10d and fs2 == 0 and fe2 == 0x13 and fm2 == 0x057 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x17b and fcsr == 0x40 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x250d; op2val:0x4c57;
op3val:0x357b; valaddr_reg:x3; val_offset:1671*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:64 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 64, 0, x3, 1671*FLEN/8, x4, x1, x2)

inst_558:
// fs1 == 0 and fe1 == 0x09 and fm1 == 0x10d and fs2 == 0 and fe2 == 0x13 and fm2 == 0x057 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x17b and fcsr == 0x60 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x250d; op2val:0x4c57;
op3val:0x357b; valaddr_reg:x3; val_offset:1674*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 96, 0, x3, 1674*FLEN/8, x4, x1, x2)

inst_559:
// fs1 == 0 and fe1 == 0x09 and fm1 == 0x10d and fs2 == 0 and fe2 == 0x13 and fm2 == 0x057 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x17b and fcsr == 0x80 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x250d; op2val:0x4c57;
op3val:0x357b; valaddr_reg:x3; val_offset:1677*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:128 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 128, 0, x3, 1677*FLEN/8, x4, x1, x2)

inst_560:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x132 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x18f and fs3 == 0 and fe3 == 0x0d and fm3 == 0x338 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3932; op2val:0x398f;
op3val:0x3738; valaddr_reg:x3; val_offset:1680*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 1680*FLEN/8, x4, x1, x2)

inst_561:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x132 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x18f and fs3 == 0 and fe3 == 0x0d and fm3 == 0x338 and fcsr == 0x20 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3932; op2val:0x398f;
op3val:0x3738; valaddr_reg:x3; val_offset:1683*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:32 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 32, 0, x3, 1683*FLEN/8, x4, x1, x2)

inst_562:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x132 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x18f and fs3 == 0 and fe3 == 0x0d and fm3 == 0x338 and fcsr == 0x40 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3932; op2val:0x398f;
op3val:0x3738; valaddr_reg:x3; val_offset:1686*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:64 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 64, 0, x3, 1686*FLEN/8, x4, x1, x2)

inst_563:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x132 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x18f and fs3 == 0 and fe3 == 0x0d and fm3 == 0x338 and fcsr == 0x60 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3932; op2val:0x398f;
op3val:0x3738; valaddr_reg:x3; val_offset:1689*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 96, 0, x3, 1689*FLEN/8, x4, x1, x2)

inst_564:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x132 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x18f and fs3 == 0 and fe3 == 0x0d and fm3 == 0x338 and fcsr == 0x80 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3932; op2val:0x398f;
op3val:0x3738; valaddr_reg:x3; val_offset:1692*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:128 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 128, 0, x3, 1692*FLEN/8, x4, x1, x2)

inst_565:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x2f3 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x089 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x3e2 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3af3; op2val:0x3c89;
op3val:0x3be2; valaddr_reg:x3; val_offset:1695*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 1695*FLEN/8, x4, x1, x2)

inst_566:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x2f3 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x089 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x3e2 and fcsr == 0x20 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3af3; op2val:0x3c89;
op3val:0x3be2; valaddr_reg:x3; val_offset:1698*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:32 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 32, 0, x3, 1698*FLEN/8, x4, x1, x2)

inst_567:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x2f3 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x089 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x3e2 and fcsr == 0x40 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3af3; op2val:0x3c89;
op3val:0x3be2; valaddr_reg:x3; val_offset:1701*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:64 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 64, 0, x3, 1701*FLEN/8, x4, x1, x2)

inst_568:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x2f3 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x089 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x3e2 and fcsr == 0x60 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3af3; op2val:0x3c89;
op3val:0x3be2; valaddr_reg:x3; val_offset:1704*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 96, 0, x3, 1704*FLEN/8, x4, x1, x2)

inst_569:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x2f3 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x089 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x3e2 and fcsr == 0x80 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3af3; op2val:0x3c89;
op3val:0x3be2; valaddr_reg:x3; val_offset:1707*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:128 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 128, 0, x3, 1707*FLEN/8, x4, x1, x2)

inst_570:
// fs1 == 0 and fe1 == 0x09 and fm1 == 0x376 and fs2 == 0 and fe2 == 0x12 and fm2 == 0x202 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x19b and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x2776; op2val:0x4a02;
op3val:0x359b; valaddr_reg:x3; val_offset:1710*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 1710*FLEN/8, x4, x1, x2)

inst_571:
// fs1 == 0 and fe1 == 0x09 and fm1 == 0x376 and fs2 == 0 and fe2 == 0x12 and fm2 == 0x202 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x19b and fcsr == 0x20 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x2776; op2val:0x4a02;
op3val:0x359b; valaddr_reg:x3; val_offset:1713*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:32 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 32, 0, x3, 1713*FLEN/8, x4, x1, x2)

inst_572:
// fs1 == 0 and fe1 == 0x09 and fm1 == 0x376 and fs2 == 0 and fe2 == 0x12 and fm2 == 0x202 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x19b and fcsr == 0x40 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x2776; op2val:0x4a02;
op3val:0x359b; valaddr_reg:x3; val_offset:1716*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:64 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 64, 0, x3, 1716*FLEN/8, x4, x1, x2)

inst_573:
// fs1 == 0 and fe1 == 0x09 and fm1 == 0x376 and fs2 == 0 and fe2 == 0x12 and fm2 == 0x202 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x19b and fcsr == 0x60 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x2776; op2val:0x4a02;
op3val:0x359b; valaddr_reg:x3; val_offset:1719*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 96, 0, x3, 1719*FLEN/8, x4, x1, x2)

inst_574:
// fs1 == 0 and fe1 == 0x09 and fm1 == 0x376 and fs2 == 0 and fe2 == 0x12 and fm2 == 0x202 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x19b and fcsr == 0x80 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x2776; op2val:0x4a02;
op3val:0x359b; valaddr_reg:x3; val_offset:1722*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:128 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 128, 0, x3, 1722*FLEN/8, x4, x1, x2)

inst_575:
// fs1 == 0 and fe1 == 0x0d and fm1 == 0x393 and fs2 == 0 and fe2 == 0x0c and fm2 == 0x07d and fs3 == 0 and fe3 == 0x0b and fm3 == 0x040 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3793; op2val:0x307d;
op3val:0x2c40; valaddr_reg:x3; val_offset:1725*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 1725*FLEN/8, x4, x1, x2)

inst_576:
// fs1 == 0 and fe1 == 0x0d and fm1 == 0x393 and fs2 == 0 and fe2 == 0x0c and fm2 == 0x07d and fs3 == 0 and fe3 == 0x0b and fm3 == 0x040 and fcsr == 0x20 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3793; op2val:0x307d;
op3val:0x2c40; valaddr_reg:x3; val_offset:1728*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:32 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 32, 0, x3, 1728*FLEN/8, x4, x1, x2)

inst_577:
// fs1 == 0 and fe1 == 0x0d and fm1 == 0x393 and fs2 == 0 and fe2 == 0x0c and fm2 == 0x07d and fs3 == 0 and fe3 == 0x0b and fm3 == 0x040 and fcsr == 0x40 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3793; op2val:0x307d;
op3val:0x2c40; valaddr_reg:x3; val_offset:1731*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:64 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 64, 0, x3, 1731*FLEN/8, x4, x1, x2)

inst_578:
// fs1 == 0 and fe1 == 0x0d and fm1 == 0x393 and fs2 == 0 and fe2 == 0x0c and fm2 == 0x07d and fs3 == 0 and fe3 == 0x0b and fm3 == 0x040 and fcsr == 0x60 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3793; op2val:0x307d;
op3val:0x2c40; valaddr_reg:x3; val_offset:1734*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 96, 0, x3, 1734*FLEN/8, x4, x1, x2)

inst_579:
// fs1 == 0 and fe1 == 0x0d and fm1 == 0x393 and fs2 == 0 and fe2 == 0x0c and fm2 == 0x07d and fs3 == 0 and fe3 == 0x0b and fm3 == 0x040 and fcsr == 0x80 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3793; op2val:0x307d;
op3val:0x2c40; valaddr_reg:x3; val_offset:1737*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:128 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 128, 0, x3, 1737*FLEN/8, x4, x1, x2)

inst_580:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x087 and fs2 == 0 and fe2 == 0x0c and fm2 == 0x340 and fs3 == 0 and fe3 == 0x0c and fm3 == 0x01a and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3887; op2val:0x3340;
op3val:0x301a; valaddr_reg:x3; val_offset:1740*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 1740*FLEN/8, x4, x1, x2)

inst_581:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x087 and fs2 == 0 and fe2 == 0x0c and fm2 == 0x340 and fs3 == 0 and fe3 == 0x0c and fm3 == 0x01a and fcsr == 0x20 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3887; op2val:0x3340;
op3val:0x301a; valaddr_reg:x3; val_offset:1743*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:32 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 32, 0, x3, 1743*FLEN/8, x4, x1, x2)

inst_582:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x087 and fs2 == 0 and fe2 == 0x0c and fm2 == 0x340 and fs3 == 0 and fe3 == 0x0c and fm3 == 0x01a and fcsr == 0x40 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3887; op2val:0x3340;
op3val:0x301a; valaddr_reg:x3; val_offset:1746*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:64 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 64, 0, x3, 1746*FLEN/8, x4, x1, x2)

inst_583:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x087 and fs2 == 0 and fe2 == 0x0c and fm2 == 0x340 and fs3 == 0 and fe3 == 0x0c and fm3 == 0x01a and fcsr == 0x60 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3887; op2val:0x3340;
op3val:0x301a; valaddr_reg:x3; val_offset:1749*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 96, 0, x3, 1749*FLEN/8, x4, x1, x2)

inst_584:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x087 and fs2 == 0 and fe2 == 0x0c and fm2 == 0x340 and fs3 == 0 and fe3 == 0x0c and fm3 == 0x01a and fcsr == 0x80 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3887; op2val:0x3340;
op3val:0x301a; valaddr_reg:x3; val_offset:1752*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:128 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 128, 0, x3, 1752*FLEN/8, x4, x1, x2)

inst_585:
// fs1 == 0 and fe1 == 0x0c and fm1 == 0x190 and fs2 == 0 and fe2 == 0x11 and fm2 == 0x089 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x24f and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3190; op2val:0x4489;
op3val:0x3a4f; valaddr_reg:x3; val_offset:1755*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 1755*FLEN/8, x4, x1, x2)

inst_586:
// fs1 == 0 and fe1 == 0x0c and fm1 == 0x190 and fs2 == 0 and fe2 == 0x11 and fm2 == 0x089 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x24f and fcsr == 0x20 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3190; op2val:0x4489;
op3val:0x3a4f; valaddr_reg:x3; val_offset:1758*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:32 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 32, 0, x3, 1758*FLEN/8, x4, x1, x2)

inst_587:
// fs1 == 0 and fe1 == 0x0c and fm1 == 0x190 and fs2 == 0 and fe2 == 0x11 and fm2 == 0x089 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x24f and fcsr == 0x40 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3190; op2val:0x4489;
op3val:0x3a4f; valaddr_reg:x3; val_offset:1761*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:64 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 64, 0, x3, 1761*FLEN/8, x4, x1, x2)

inst_588:
// fs1 == 0 and fe1 == 0x0c and fm1 == 0x190 and fs2 == 0 and fe2 == 0x11 and fm2 == 0x089 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x24f and fcsr == 0x60 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3190; op2val:0x4489;
op3val:0x3a4f; valaddr_reg:x3; val_offset:1764*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 96, 0, x3, 1764*FLEN/8, x4, x1, x2)

inst_589:
// fs1 == 0 and fe1 == 0x0c and fm1 == 0x190 and fs2 == 0 and fe2 == 0x11 and fm2 == 0x089 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x24f and fcsr == 0x80 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3190; op2val:0x4489;
op3val:0x3a4f; valaddr_reg:x3; val_offset:1767*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:128 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 128, 0, x3, 1767*FLEN/8, x4, x1, x2)

inst_590:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x1fc and fs2 == 0 and fe2 == 0x0e and fm2 == 0x38f and fs3 == 0 and fe3 == 0x0e and fm3 == 0x1a8 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x39fc; op2val:0x3b8f;
op3val:0x39a8; valaddr_reg:x3; val_offset:1770*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 1770*FLEN/8, x4, x1, x2)

inst_591:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x1fc and fs2 == 0 and fe2 == 0x0e and fm2 == 0x38f and fs3 == 0 and fe3 == 0x0e and fm3 == 0x1a8 and fcsr == 0x20 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x39fc; op2val:0x3b8f;
op3val:0x39a8; valaddr_reg:x3; val_offset:1773*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:32 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 32, 0, x3, 1773*FLEN/8, x4, x1, x2)

inst_592:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x1fc and fs2 == 0 and fe2 == 0x0e and fm2 == 0x38f and fs3 == 0 and fe3 == 0x0e and fm3 == 0x1a8 and fcsr == 0x40 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x39fc; op2val:0x3b8f;
op3val:0x39a8; valaddr_reg:x3; val_offset:1776*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:64 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 64, 0, x3, 1776*FLEN/8, x4, x1, x2)

inst_593:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x1fc and fs2 == 0 and fe2 == 0x0e and fm2 == 0x38f and fs3 == 0 and fe3 == 0x0e and fm3 == 0x1a8 and fcsr == 0x60 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x39fc; op2val:0x3b8f;
op3val:0x39a8; valaddr_reg:x3; val_offset:1779*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 96, 0, x3, 1779*FLEN/8, x4, x1, x2)

inst_594:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x1fc and fs2 == 0 and fe2 == 0x0e and fm2 == 0x38f and fs3 == 0 and fe3 == 0x0e and fm3 == 0x1a8 and fcsr == 0x80 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x39fc; op2val:0x3b8f;
op3val:0x39a8; valaddr_reg:x3; val_offset:1782*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:128 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 128, 0, x3, 1782*FLEN/8, x4, x1, x2)

inst_595:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x213 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x05b and fs3 == 0 and fe3 == 0x0d and fm3 == 0x29e and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3a13; op2val:0x385b;
op3val:0x369e; valaddr_reg:x3; val_offset:1785*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 1785*FLEN/8, x4, x1, x2)

inst_596:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x213 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x05b and fs3 == 0 and fe3 == 0x0d and fm3 == 0x29e and fcsr == 0x20 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3a13; op2val:0x385b;
op3val:0x369e; valaddr_reg:x3; val_offset:1788*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:32 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 32, 0, x3, 1788*FLEN/8, x4, x1, x2)

inst_597:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x213 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x05b and fs3 == 0 and fe3 == 0x0d and fm3 == 0x29e and fcsr == 0x40 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3a13; op2val:0x385b;
op3val:0x369e; valaddr_reg:x3; val_offset:1791*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:64 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 64, 0, x3, 1791*FLEN/8, x4, x1, x2)

inst_598:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x213 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x05b and fs3 == 0 and fe3 == 0x0d and fm3 == 0x29e and fcsr == 0x60 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3a13; op2val:0x385b;
op3val:0x369e; valaddr_reg:x3; val_offset:1794*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 96, 0, x3, 1794*FLEN/8, x4, x1, x2)

inst_599:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x213 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x05b and fs3 == 0 and fe3 == 0x0d and fm3 == 0x29e and fcsr == 0x80 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3a13; op2val:0x385b;
op3val:0x369e; valaddr_reg:x3; val_offset:1797*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:128 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 128, 0, x3, 1797*FLEN/8, x4, x1, x2)

inst_600:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x1ec and fs2 == 0 and fe2 == 0x0e and fm2 == 0x246 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x0a5 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x39ec; op2val:0x3a46;
op3val:0x38a5; valaddr_reg:x3; val_offset:1800*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 1800*FLEN/8, x4, x1, x2)

inst_601:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x1ec and fs2 == 0 and fe2 == 0x0e and fm2 == 0x246 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x0a5 and fcsr == 0x20 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x39ec; op2val:0x3a46;
op3val:0x38a5; valaddr_reg:x3; val_offset:1803*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:32 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 32, 0, x3, 1803*FLEN/8, x4, x1, x2)

inst_602:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x1ec and fs2 == 0 and fe2 == 0x0e and fm2 == 0x246 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x0a5 and fcsr == 0x40 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x39ec; op2val:0x3a46;
op3val:0x38a5; valaddr_reg:x3; val_offset:1806*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:64 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 64, 0, x3, 1806*FLEN/8, x4, x1, x2)

inst_603:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x1ec and fs2 == 0 and fe2 == 0x0e and fm2 == 0x246 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x0a5 and fcsr == 0x60 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x39ec; op2val:0x3a46;
op3val:0x38a5; valaddr_reg:x3; val_offset:1809*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 96, 0, x3, 1809*FLEN/8, x4, x1, x2)

inst_604:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x1ec and fs2 == 0 and fe2 == 0x0e and fm2 == 0x246 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x0a5 and fcsr == 0x80 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x39ec; op2val:0x3a46;
op3val:0x38a5; valaddr_reg:x3; val_offset:1812*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:128 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 128, 0, x3, 1812*FLEN/8, x4, x1, x2)

inst_605:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x2f3 and fs2 == 0 and fe2 == 0x0b and fm2 == 0x2a2 and fs3 == 0 and fe3 == 0x0b and fm3 == 0x1c2 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3af3; op2val:0x2ea2;
op3val:0x2dc2; valaddr_reg:x3; val_offset:1815*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 1815*FLEN/8, x4, x1, x2)

inst_606:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x2f3 and fs2 == 0 and fe2 == 0x0b and fm2 == 0x2a2 and fs3 == 0 and fe3 == 0x0b and fm3 == 0x1c2 and fcsr == 0x20 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3af3; op2val:0x2ea2;
op3val:0x2dc2; valaddr_reg:x3; val_offset:1818*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:32 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 32, 0, x3, 1818*FLEN/8, x4, x1, x2)

inst_607:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x2f3 and fs2 == 0 and fe2 == 0x0b and fm2 == 0x2a2 and fs3 == 0 and fe3 == 0x0b and fm3 == 0x1c2 and fcsr == 0x40 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3af3; op2val:0x2ea2;
op3val:0x2dc2; valaddr_reg:x3; val_offset:1821*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:64 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 64, 0, x3, 1821*FLEN/8, x4, x1, x2)

inst_608:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x2f3 and fs2 == 0 and fe2 == 0x0b and fm2 == 0x2a2 and fs3 == 0 and fe3 == 0x0b and fm3 == 0x1c2 and fcsr == 0x60 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3af3; op2val:0x2ea2;
op3val:0x2dc2; valaddr_reg:x3; val_offset:1824*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 96, 0, x3, 1824*FLEN/8, x4, x1, x2)

inst_609:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x2f3 and fs2 == 0 and fe2 == 0x0b and fm2 == 0x2a2 and fs3 == 0 and fe3 == 0x0b and fm3 == 0x1c2 and fcsr == 0x80 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3af3; op2val:0x2ea2;
op3val:0x2dc2; valaddr_reg:x3; val_offset:1827*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:128 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 128, 0, x3, 1827*FLEN/8, x4, x1, x2)

inst_610:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x12b and fs2 == 0 and fe2 == 0x0e and fm2 == 0x2b5 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x055 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x392b; op2val:0x3ab5;
op3val:0x3855; valaddr_reg:x3; val_offset:1830*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 1830*FLEN/8, x4, x1, x2)

inst_611:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x12b and fs2 == 0 and fe2 == 0x0e and fm2 == 0x2b5 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x055 and fcsr == 0x20 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x392b; op2val:0x3ab5;
op3val:0x3855; valaddr_reg:x3; val_offset:1833*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:32 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 32, 0, x3, 1833*FLEN/8, x4, x1, x2)

inst_612:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x12b and fs2 == 0 and fe2 == 0x0e and fm2 == 0x2b5 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x055 and fcsr == 0x40 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x392b; op2val:0x3ab5;
op3val:0x3855; valaddr_reg:x3; val_offset:1836*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:64 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 64, 0, x3, 1836*FLEN/8, x4, x1, x2)

inst_613:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x12b and fs2 == 0 and fe2 == 0x0e and fm2 == 0x2b5 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x055 and fcsr == 0x60 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x392b; op2val:0x3ab5;
op3val:0x3855; valaddr_reg:x3; val_offset:1839*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 96, 0, x3, 1839*FLEN/8, x4, x1, x2)

inst_614:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x12b and fs2 == 0 and fe2 == 0x0e and fm2 == 0x2b5 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x055 and fcsr == 0x80 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x392b; op2val:0x3ab5;
op3val:0x3855; valaddr_reg:x3; val_offset:1842*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:128 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 128, 0, x3, 1842*FLEN/8, x4, x1, x2)

inst_615:
// fs1 == 0 and fe1 == 0x0d and fm1 == 0x2aa and fs2 == 0 and fe2 == 0x0c and fm2 == 0x35b and fs3 == 0 and fe3 == 0x0b and fm3 == 0x220 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x36aa; op2val:0x335b;
op3val:0x2e20; valaddr_reg:x3; val_offset:1845*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 1845*FLEN/8, x4, x1, x2)

inst_616:
// fs1 == 0 and fe1 == 0x0d and fm1 == 0x2aa and fs2 == 0 and fe2 == 0x0c and fm2 == 0x35b and fs3 == 0 and fe3 == 0x0b and fm3 == 0x220 and fcsr == 0x20 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x36aa; op2val:0x335b;
op3val:0x2e20; valaddr_reg:x3; val_offset:1848*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:32 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 32, 0, x3, 1848*FLEN/8, x4, x1, x2)

inst_617:
// fs1 == 0 and fe1 == 0x0d and fm1 == 0x2aa and fs2 == 0 and fe2 == 0x0c and fm2 == 0x35b and fs3 == 0 and fe3 == 0x0b and fm3 == 0x220 and fcsr == 0x40 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x36aa; op2val:0x335b;
op3val:0x2e20; valaddr_reg:x3; val_offset:1851*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:64 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 64, 0, x3, 1851*FLEN/8, x4, x1, x2)

inst_618:
// fs1 == 0 and fe1 == 0x0d and fm1 == 0x2aa and fs2 == 0 and fe2 == 0x0c and fm2 == 0x35b and fs3 == 0 and fe3 == 0x0b and fm3 == 0x220 and fcsr == 0x60 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x36aa; op2val:0x335b;
op3val:0x2e20; valaddr_reg:x3; val_offset:1854*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 96, 0, x3, 1854*FLEN/8, x4, x1, x2)

inst_619:
// fs1 == 0 and fe1 == 0x0d and fm1 == 0x2aa and fs2 == 0 and fe2 == 0x0c and fm2 == 0x35b and fs3 == 0 and fe3 == 0x0b and fm3 == 0x220 and fcsr == 0x80 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x36aa; op2val:0x335b;
op3val:0x2e20; valaddr_reg:x3; val_offset:1857*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:128 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 128, 0, x3, 1857*FLEN/8, x4, x1, x2)

inst_620:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x0a2 and fs2 == 0 and fe2 == 0x0c and fm2 == 0x08c and fs3 == 0 and fe3 == 0x0b and fm3 == 0x144 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x38a2; op2val:0x308c;
op3val:0x2d44; valaddr_reg:x3; val_offset:1860*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 1860*FLEN/8, x4, x1, x2)

inst_621:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x0a2 and fs2 == 0 and fe2 == 0x0c and fm2 == 0x08c and fs3 == 0 and fe3 == 0x0b and fm3 == 0x144 and fcsr == 0x20 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x38a2; op2val:0x308c;
op3val:0x2d44; valaddr_reg:x3; val_offset:1863*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:32 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 32, 0, x3, 1863*FLEN/8, x4, x1, x2)

inst_622:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x0a2 and fs2 == 0 and fe2 == 0x0c and fm2 == 0x08c and fs3 == 0 and fe3 == 0x0b and fm3 == 0x144 and fcsr == 0x40 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x38a2; op2val:0x308c;
op3val:0x2d44; valaddr_reg:x3; val_offset:1866*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:64 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 64, 0, x3, 1866*FLEN/8, x4, x1, x2)

inst_623:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x0a2 and fs2 == 0 and fe2 == 0x0c and fm2 == 0x08c and fs3 == 0 and fe3 == 0x0b and fm3 == 0x144 and fcsr == 0x60 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x38a2; op2val:0x308c;
op3val:0x2d44; valaddr_reg:x3; val_offset:1869*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 96, 0, x3, 1869*FLEN/8, x4, x1, x2)

inst_624:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x0a2 and fs2 == 0 and fe2 == 0x0c and fm2 == 0x08c and fs3 == 0 and fe3 == 0x0b and fm3 == 0x144 and fcsr == 0x80 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x38a2; op2val:0x308c;
op3val:0x2d44; valaddr_reg:x3; val_offset:1872*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:128 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 128, 0, x3, 1872*FLEN/8, x4, x1, x2)

inst_625:
// fs1 == 0 and fe1 == 0x0d and fm1 == 0x3f9 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x384 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x37d and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x37f9; op2val:0x3b84;
op3val:0x377d; valaddr_reg:x3; val_offset:1875*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 1875*FLEN/8, x4, x1, x2)

inst_626:
// fs1 == 0 and fe1 == 0x0d and fm1 == 0x3f9 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x384 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x37d and fcsr == 0x20 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x37f9; op2val:0x3b84;
op3val:0x377d; valaddr_reg:x3; val_offset:1878*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:32 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 32, 0, x3, 1878*FLEN/8, x4, x1, x2)

inst_627:
// fs1 == 0 and fe1 == 0x0d and fm1 == 0x3f9 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x384 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x37d and fcsr == 0x40 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x37f9; op2val:0x3b84;
op3val:0x377d; valaddr_reg:x3; val_offset:1881*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:64 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 64, 0, x3, 1881*FLEN/8, x4, x1, x2)

inst_628:
// fs1 == 0 and fe1 == 0x0d and fm1 == 0x3f9 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x384 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x37d and fcsr == 0x60 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x37f9; op2val:0x3b84;
op3val:0x377d; valaddr_reg:x3; val_offset:1884*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 96, 0, x3, 1884*FLEN/8, x4, x1, x2)

inst_629:
// fs1 == 0 and fe1 == 0x0d and fm1 == 0x3f9 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x384 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x37d and fcsr == 0x80 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x37f9; op2val:0x3b84;
op3val:0x377d; valaddr_reg:x3; val_offset:1887*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:128 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 128, 0, x3, 1887*FLEN/8, x4, x1, x2)

inst_630:
// fs1 == 0 and fe1 == 0x0d and fm1 == 0x39f and fs2 == 0 and fe2 == 0x10 and fm2 == 0x01e and fs3 == 0 and fe3 == 0x0e and fm3 == 0x3d9 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x379f; op2val:0x401e;
op3val:0x3bd9; valaddr_reg:x3; val_offset:1890*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 1890*FLEN/8, x4, x1, x2)

inst_631:
// fs1 == 0 and fe1 == 0x0d and fm1 == 0x39f and fs2 == 0 and fe2 == 0x10 and fm2 == 0x01e and fs3 == 0 and fe3 == 0x0e and fm3 == 0x3d9 and fcsr == 0x20 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x379f; op2val:0x401e;
op3val:0x3bd9; valaddr_reg:x3; val_offset:1893*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:32 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 32, 0, x3, 1893*FLEN/8, x4, x1, x2)

inst_632:
// fs1 == 0 and fe1 == 0x0d and fm1 == 0x39f and fs2 == 0 and fe2 == 0x10 and fm2 == 0x01e and fs3 == 0 and fe3 == 0x0e and fm3 == 0x3d9 and fcsr == 0x40 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x379f; op2val:0x401e;
op3val:0x3bd9; valaddr_reg:x3; val_offset:1896*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:64 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 64, 0, x3, 1896*FLEN/8, x4, x1, x2)

inst_633:
// fs1 == 0 and fe1 == 0x0d and fm1 == 0x39f and fs2 == 0 and fe2 == 0x10 and fm2 == 0x01e and fs3 == 0 and fe3 == 0x0e and fm3 == 0x3d9 and fcsr == 0x60 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x379f; op2val:0x401e;
op3val:0x3bd9; valaddr_reg:x3; val_offset:1899*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 96, 0, x3, 1899*FLEN/8, x4, x1, x2)

inst_634:
// fs1 == 0 and fe1 == 0x0d and fm1 == 0x39f and fs2 == 0 and fe2 == 0x10 and fm2 == 0x01e and fs3 == 0 and fe3 == 0x0e and fm3 == 0x3d9 and fcsr == 0x80 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x379f; op2val:0x401e;
op3val:0x3bd9; valaddr_reg:x3; val_offset:1902*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:128 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 128, 0, x3, 1902*FLEN/8, x4, x1, x2)

inst_635:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x07a and fs2 == 0 and fe2 == 0x0f and fm2 == 0x1d6 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x289 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x387a; op2val:0x3dd6;
op3val:0x3a89; valaddr_reg:x3; val_offset:1905*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 1905*FLEN/8, x4, x1, x2)

inst_636:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x07a and fs2 == 0 and fe2 == 0x0f and fm2 == 0x1d6 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x289 and fcsr == 0x20 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x387a; op2val:0x3dd6;
op3val:0x3a89; valaddr_reg:x3; val_offset:1908*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:32 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 32, 0, x3, 1908*FLEN/8, x4, x1, x2)

inst_637:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x07a and fs2 == 0 and fe2 == 0x0f and fm2 == 0x1d6 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x289 and fcsr == 0x40 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x387a; op2val:0x3dd6;
op3val:0x3a89; valaddr_reg:x3; val_offset:1911*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:64 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 64, 0, x3, 1911*FLEN/8, x4, x1, x2)

inst_638:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x07a and fs2 == 0 and fe2 == 0x0f and fm2 == 0x1d6 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x289 and fcsr == 0x60 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x387a; op2val:0x3dd6;
op3val:0x3a89; valaddr_reg:x3; val_offset:1914*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 96, 0, x3, 1914*FLEN/8, x4, x1, x2)

inst_639:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x07a and fs2 == 0 and fe2 == 0x0f and fm2 == 0x1d6 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x289 and fcsr == 0x80 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x387a; op2val:0x3dd6;
op3val:0x3a89; valaddr_reg:x3; val_offset:1917*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:128 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 128, 0, x3, 1917*FLEN/8, x4, x1, x2)
RVTEST_SIGBASE(x1,signature_x1_6)

inst_640:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x3f7 and fs2 == 0 and fe2 == 0x0c and fm2 == 0x274 and fs3 == 0 and fe3 == 0x0c and fm3 == 0x26d and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3bf7; op2val:0x3274;
op3val:0x326d; valaddr_reg:x3; val_offset:1920*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 1920*FLEN/8, x4, x1, x2)

inst_641:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x3f7 and fs2 == 0 and fe2 == 0x0c and fm2 == 0x274 and fs3 == 0 and fe3 == 0x0c and fm3 == 0x26d and fcsr == 0x20 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3bf7; op2val:0x3274;
op3val:0x326d; valaddr_reg:x3; val_offset:1923*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:32 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 32, 0, x3, 1923*FLEN/8, x4, x1, x2)

inst_642:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x3f7 and fs2 == 0 and fe2 == 0x0c and fm2 == 0x274 and fs3 == 0 and fe3 == 0x0c and fm3 == 0x26d and fcsr == 0x40 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3bf7; op2val:0x3274;
op3val:0x326d; valaddr_reg:x3; val_offset:1926*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:64 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 64, 0, x3, 1926*FLEN/8, x4, x1, x2)

inst_643:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x3f7 and fs2 == 0 and fe2 == 0x0c and fm2 == 0x274 and fs3 == 0 and fe3 == 0x0c and fm3 == 0x26d and fcsr == 0x60 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3bf7; op2val:0x3274;
op3val:0x326d; valaddr_reg:x3; val_offset:1929*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 96, 0, x3, 1929*FLEN/8, x4, x1, x2)

inst_644:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x3f7 and fs2 == 0 and fe2 == 0x0c and fm2 == 0x274 and fs3 == 0 and fe3 == 0x0c and fm3 == 0x26d and fcsr == 0x80 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3bf7; op2val:0x3274;
op3val:0x326d; valaddr_reg:x3; val_offset:1932*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:128 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 128, 0, x3, 1932*FLEN/8, x4, x1, x2)

inst_645:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x29f and fs2 == 0 and fe2 == 0x0e and fm2 == 0x117 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x036 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3a9f; op2val:0x3917;
op3val:0x3836; valaddr_reg:x3; val_offset:1935*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 1935*FLEN/8, x4, x1, x2)

inst_646:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x29f and fs2 == 0 and fe2 == 0x0e and fm2 == 0x117 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x036 and fcsr == 0x20 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3a9f; op2val:0x3917;
op3val:0x3836; valaddr_reg:x3; val_offset:1938*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:32 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 32, 0, x3, 1938*FLEN/8, x4, x1, x2)

inst_647:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x29f and fs2 == 0 and fe2 == 0x0e and fm2 == 0x117 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x036 and fcsr == 0x40 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3a9f; op2val:0x3917;
op3val:0x3836; valaddr_reg:x3; val_offset:1941*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:64 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 64, 0, x3, 1941*FLEN/8, x4, x1, x2)

inst_648:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x29f and fs2 == 0 and fe2 == 0x0e and fm2 == 0x117 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x036 and fcsr == 0x60 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3a9f; op2val:0x3917;
op3val:0x3836; valaddr_reg:x3; val_offset:1944*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 96, 0, x3, 1944*FLEN/8, x4, x1, x2)

inst_649:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x29f and fs2 == 0 and fe2 == 0x0e and fm2 == 0x117 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x036 and fcsr == 0x80 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3a9f; op2val:0x3917;
op3val:0x3836; valaddr_reg:x3; val_offset:1947*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:128 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 128, 0, x3, 1947*FLEN/8, x4, x1, x2)

inst_650:
// fs1 == 0 and fe1 == 0x0d and fm1 == 0x065 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x274 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x318 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3465; op2val:0x3e74;
op3val:0x3718; valaddr_reg:x3; val_offset:1950*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 1950*FLEN/8, x4, x1, x2)

inst_651:
// fs1 == 0 and fe1 == 0x0d and fm1 == 0x065 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x274 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x318 and fcsr == 0x20 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3465; op2val:0x3e74;
op3val:0x3718; valaddr_reg:x3; val_offset:1953*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:32 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 32, 0, x3, 1953*FLEN/8, x4, x1, x2)

inst_652:
// fs1 == 0 and fe1 == 0x0d and fm1 == 0x065 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x274 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x318 and fcsr == 0x40 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3465; op2val:0x3e74;
op3val:0x3718; valaddr_reg:x3; val_offset:1956*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:64 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 64, 0, x3, 1956*FLEN/8, x4, x1, x2)

inst_653:
// fs1 == 0 and fe1 == 0x0d and fm1 == 0x065 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x274 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x318 and fcsr == 0x60 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3465; op2val:0x3e74;
op3val:0x3718; valaddr_reg:x3; val_offset:1959*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 96, 0, x3, 1959*FLEN/8, x4, x1, x2)

inst_654:
// fs1 == 0 and fe1 == 0x0d and fm1 == 0x065 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x274 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x318 and fcsr == 0x80 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3465; op2val:0x3e74;
op3val:0x3718; valaddr_reg:x3; val_offset:1962*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:128 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 128, 0, x3, 1962*FLEN/8, x4, x1, x2)

inst_655:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x164 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x1b7 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x3b4 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3964; op2val:0x39b7;
op3val:0x37b4; valaddr_reg:x3; val_offset:1965*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 1965*FLEN/8, x4, x1, x2)

inst_656:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x164 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x1b7 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x3b4 and fcsr == 0x20 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3964; op2val:0x39b7;
op3val:0x37b4; valaddr_reg:x3; val_offset:1968*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:32 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 32, 0, x3, 1968*FLEN/8, x4, x1, x2)

inst_657:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x164 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x1b7 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x3b4 and fcsr == 0x40 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3964; op2val:0x39b7;
op3val:0x37b4; valaddr_reg:x3; val_offset:1971*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:64 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 64, 0, x3, 1971*FLEN/8, x4, x1, x2)

inst_658:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x164 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x1b7 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x3b4 and fcsr == 0x60 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3964; op2val:0x39b7;
op3val:0x37b4; valaddr_reg:x3; val_offset:1974*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 96, 0, x3, 1974*FLEN/8, x4, x1, x2)

inst_659:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x164 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x1b7 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x3b4 and fcsr == 0x80 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3964; op2val:0x39b7;
op3val:0x37b4; valaddr_reg:x3; val_offset:1977*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:128 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 128, 0, x3, 1977*FLEN/8, x4, x1, x2)

inst_660:
// fs1 == 0 and fe1 == 0x0d and fm1 == 0x31d and fs2 == 0 and fe2 == 0x0d and fm2 == 0x3c4 and fs3 == 0 and fe3 == 0x0c and fm3 == 0x2e7 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x371d; op2val:0x37c4;
op3val:0x32e7; valaddr_reg:x3; val_offset:1980*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 1980*FLEN/8, x4, x1, x2)

inst_661:
// fs1 == 0 and fe1 == 0x0d and fm1 == 0x31d and fs2 == 0 and fe2 == 0x0d and fm2 == 0x3c4 and fs3 == 0 and fe3 == 0x0c and fm3 == 0x2e7 and fcsr == 0x20 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x371d; op2val:0x37c4;
op3val:0x32e7; valaddr_reg:x3; val_offset:1983*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:32 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 32, 0, x3, 1983*FLEN/8, x4, x1, x2)

inst_662:
// fs1 == 0 and fe1 == 0x0d and fm1 == 0x31d and fs2 == 0 and fe2 == 0x0d and fm2 == 0x3c4 and fs3 == 0 and fe3 == 0x0c and fm3 == 0x2e7 and fcsr == 0x40 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x371d; op2val:0x37c4;
op3val:0x32e7; valaddr_reg:x3; val_offset:1986*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:64 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 64, 0, x3, 1986*FLEN/8, x4, x1, x2)

inst_663:
// fs1 == 0 and fe1 == 0x0d and fm1 == 0x31d and fs2 == 0 and fe2 == 0x0d and fm2 == 0x3c4 and fs3 == 0 and fe3 == 0x0c and fm3 == 0x2e7 and fcsr == 0x60 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x371d; op2val:0x37c4;
op3val:0x32e7; valaddr_reg:x3; val_offset:1989*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 96, 0, x3, 1989*FLEN/8, x4, x1, x2)

inst_664:
// fs1 == 0 and fe1 == 0x0d and fm1 == 0x31d and fs2 == 0 and fe2 == 0x0d and fm2 == 0x3c4 and fs3 == 0 and fe3 == 0x0c and fm3 == 0x2e7 and fcsr == 0x80 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x371d; op2val:0x37c4;
op3val:0x32e7; valaddr_reg:x3; val_offset:1992*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:128 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 128, 0, x3, 1992*FLEN/8, x4, x1, x2)

inst_665:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x326 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x3df and fs3 == 0 and fe3 == 0x0d and fm3 == 0x309 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3b26; op2val:0x37df;
op3val:0x3709; valaddr_reg:x3; val_offset:1995*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 1995*FLEN/8, x4, x1, x2)

inst_666:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x326 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x3df and fs3 == 0 and fe3 == 0x0d and fm3 == 0x309 and fcsr == 0x20 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3b26; op2val:0x37df;
op3val:0x3709; valaddr_reg:x3; val_offset:1998*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:32 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 32, 0, x3, 1998*FLEN/8, x4, x1, x2)

inst_667:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x326 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x3df and fs3 == 0 and fe3 == 0x0d and fm3 == 0x309 and fcsr == 0x40 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3b26; op2val:0x37df;
op3val:0x3709; valaddr_reg:x3; val_offset:2001*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:64 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 64, 0, x3, 2001*FLEN/8, x4, x1, x2)

inst_668:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x326 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x3df and fs3 == 0 and fe3 == 0x0d and fm3 == 0x309 and fcsr == 0x60 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3b26; op2val:0x37df;
op3val:0x3709; valaddr_reg:x3; val_offset:2004*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 96, 0, x3, 2004*FLEN/8, x4, x1, x2)

inst_669:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x326 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x3df and fs3 == 0 and fe3 == 0x0d and fm3 == 0x309 and fcsr == 0x80 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3b26; op2val:0x37df;
op3val:0x3709; valaddr_reg:x3; val_offset:2007*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:128 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 128, 0, x3, 2007*FLEN/8, x4, x1, x2)

inst_670:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x203 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x3b2 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x1c8 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3a03; op2val:0x3bb2;
op3val:0x39c8; valaddr_reg:x3; val_offset:2010*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 2010*FLEN/8, x4, x1, x2)

inst_671:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x203 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x3b2 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x1c8 and fcsr == 0x20 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3a03; op2val:0x3bb2;
op3val:0x39c8; valaddr_reg:x3; val_offset:2013*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:32 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 32, 0, x3, 2013*FLEN/8, x4, x1, x2)

inst_672:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x203 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x3b2 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x1c8 and fcsr == 0x40 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3a03; op2val:0x3bb2;
op3val:0x39c8; valaddr_reg:x3; val_offset:2016*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:64 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 64, 0, x3, 2016*FLEN/8, x4, x1, x2)

inst_673:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x203 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x3b2 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x1c8 and fcsr == 0x60 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3a03; op2val:0x3bb2;
op3val:0x39c8; valaddr_reg:x3; val_offset:2019*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 96, 0, x3, 2019*FLEN/8, x4, x1, x2)

inst_674:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x203 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x3b2 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x1c8 and fcsr == 0x80 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3a03; op2val:0x3bb2;
op3val:0x39c8; valaddr_reg:x3; val_offset:2022*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:128 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 128, 0, x3, 2022*FLEN/8, x4, x1, x2)

inst_675:
// fs1 == 0 and fe1 == 0x0c and fm1 == 0x34a and fs2 == 0 and fe2 == 0x10 and fm2 == 0x052 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x3e0 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x334a; op2val:0x4052;
op3val:0x37e0; valaddr_reg:x3; val_offset:2025*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 2025*FLEN/8, x4, x1, x2)

inst_676:
// fs1 == 0 and fe1 == 0x0c and fm1 == 0x34a and fs2 == 0 and fe2 == 0x10 and fm2 == 0x052 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x3e0 and fcsr == 0x20 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x334a; op2val:0x4052;
op3val:0x37e0; valaddr_reg:x3; val_offset:2028*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:32 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 32, 0, x3, 2028*FLEN/8, x4, x1, x2)

inst_677:
// fs1 == 0 and fe1 == 0x0c and fm1 == 0x34a and fs2 == 0 and fe2 == 0x10 and fm2 == 0x052 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x3e0 and fcsr == 0x40 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x334a; op2val:0x4052;
op3val:0x37e0; valaddr_reg:x3; val_offset:2031*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:64 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 64, 0, x3, 2031*FLEN/8, x4, x1, x2)

inst_678:
// fs1 == 0 and fe1 == 0x0c and fm1 == 0x34a and fs2 == 0 and fe2 == 0x10 and fm2 == 0x052 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x3e0 and fcsr == 0x60 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x334a; op2val:0x4052;
op3val:0x37e0; valaddr_reg:x3; val_offset:2034*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 96, 0, x3, 2034*FLEN/8, x4, x1, x2)

inst_679:
// fs1 == 0 and fe1 == 0x0c and fm1 == 0x34a and fs2 == 0 and fe2 == 0x10 and fm2 == 0x052 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x3e0 and fcsr == 0x80 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x334a; op2val:0x4052;
op3val:0x37e0; valaddr_reg:x3; val_offset:2037*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:128 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 128, 0, x3, 2037*FLEN/8, x4, x1, x2)

inst_680:
// fs1 == 0 and fe1 == 0x0d and fm1 == 0x303 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x061 and fs3 == 0 and fe3 == 0x0c and fm3 == 0x3ae and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3703; op2val:0x3861;
op3val:0x33ae; valaddr_reg:x3; val_offset:2040*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 2040*FLEN/8, x4, x1, x2)

inst_681:
// fs1 == 0 and fe1 == 0x0d and fm1 == 0x303 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x061 and fs3 == 0 and fe3 == 0x0c and fm3 == 0x3ae and fcsr == 0x20 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3703; op2val:0x3861;
op3val:0x33ae; valaddr_reg:x3; val_offset:2043*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:32 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 32, 0, x3, 2043*FLEN/8, x4, x1, x2)

inst_682:
// fs1 == 0 and fe1 == 0x0d and fm1 == 0x303 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x061 and fs3 == 0 and fe3 == 0x0c and fm3 == 0x3ae and fcsr == 0x40 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3703; op2val:0x3861;
op3val:0x33ae; valaddr_reg:x3; val_offset:2046*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:64 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 64, 0, x3, 2046*FLEN/8, x4, x1, x2)

inst_683:
// fs1 == 0 and fe1 == 0x0d and fm1 == 0x303 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x061 and fs3 == 0 and fe3 == 0x0c and fm3 == 0x3ae and fcsr == 0x60 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3703; op2val:0x3861;
op3val:0x33ae; valaddr_reg:x3; val_offset:2049*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 96, 0, x3, 2049*FLEN/8, x4, x1, x2)

inst_684:
// fs1 == 0 and fe1 == 0x0d and fm1 == 0x303 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x061 and fs3 == 0 and fe3 == 0x0c and fm3 == 0x3ae and fcsr == 0x80 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3703; op2val:0x3861;
op3val:0x33ae; valaddr_reg:x3; val_offset:2052*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:128 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 128, 0, x3, 2052*FLEN/8, x4, x1, x2)

inst_685:
// fs1 == 0 and fe1 == 0x0b and fm1 == 0x19a and fs2 == 0 and fe2 == 0x11 and fm2 == 0x25b and fs3 == 0 and fe3 == 0x0e and fm3 == 0x074 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x2d9a; op2val:0x465b;
op3val:0x3874; valaddr_reg:x3; val_offset:2055*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 2055*FLEN/8, x4, x1, x2)

inst_686:
// fs1 == 0 and fe1 == 0x0b and fm1 == 0x19a and fs2 == 0 and fe2 == 0x11 and fm2 == 0x25b and fs3 == 0 and fe3 == 0x0e and fm3 == 0x074 and fcsr == 0x20 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x2d9a; op2val:0x465b;
op3val:0x3874; valaddr_reg:x3; val_offset:2058*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:32 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 32, 0, x3, 2058*FLEN/8, x4, x1, x2)

inst_687:
// fs1 == 0 and fe1 == 0x0b and fm1 == 0x19a and fs2 == 0 and fe2 == 0x11 and fm2 == 0x25b and fs3 == 0 and fe3 == 0x0e and fm3 == 0x074 and fcsr == 0x40 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x2d9a; op2val:0x465b;
op3val:0x3874; valaddr_reg:x3; val_offset:2061*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:64 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 64, 0, x3, 2061*FLEN/8, x4, x1, x2)

inst_688:
// fs1 == 0 and fe1 == 0x0b and fm1 == 0x19a and fs2 == 0 and fe2 == 0x11 and fm2 == 0x25b and fs3 == 0 and fe3 == 0x0e and fm3 == 0x074 and fcsr == 0x60 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x2d9a; op2val:0x465b;
op3val:0x3874; valaddr_reg:x3; val_offset:2064*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 96, 0, x3, 2064*FLEN/8, x4, x1, x2)

inst_689:
// fs1 == 0 and fe1 == 0x0b and fm1 == 0x19a and fs2 == 0 and fe2 == 0x11 and fm2 == 0x25b and fs3 == 0 and fe3 == 0x0e and fm3 == 0x074 and fcsr == 0x80 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x2d9a; op2val:0x465b;
op3val:0x3874; valaddr_reg:x3; val_offset:2067*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:128 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 128, 0, x3, 2067*FLEN/8, x4, x1, x2)

inst_690:
// fs1 == 0 and fe1 == 0x0d and fm1 == 0x233 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x11a and fs3 == 0 and fe3 == 0x0d and fm3 == 0x3e9 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3633; op2val:0x3d1a;
op3val:0x37e9; valaddr_reg:x3; val_offset:2070*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 2070*FLEN/8, x4, x1, x2)

inst_691:
// fs1 == 0 and fe1 == 0x0d and fm1 == 0x233 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x11a and fs3 == 0 and fe3 == 0x0d and fm3 == 0x3e9 and fcsr == 0x20 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3633; op2val:0x3d1a;
op3val:0x37e9; valaddr_reg:x3; val_offset:2073*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:32 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 32, 0, x3, 2073*FLEN/8, x4, x1, x2)

inst_692:
// fs1 == 0 and fe1 == 0x0d and fm1 == 0x233 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x11a and fs3 == 0 and fe3 == 0x0d and fm3 == 0x3e9 and fcsr == 0x40 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3633; op2val:0x3d1a;
op3val:0x37e9; valaddr_reg:x3; val_offset:2076*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:64 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 64, 0, x3, 2076*FLEN/8, x4, x1, x2)

inst_693:
// fs1 == 0 and fe1 == 0x0d and fm1 == 0x233 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x11a and fs3 == 0 and fe3 == 0x0d and fm3 == 0x3e9 and fcsr == 0x60 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3633; op2val:0x3d1a;
op3val:0x37e9; valaddr_reg:x3; val_offset:2079*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 96, 0, x3, 2079*FLEN/8, x4, x1, x2)

inst_694:
// fs1 == 0 and fe1 == 0x0d and fm1 == 0x233 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x11a and fs3 == 0 and fe3 == 0x0d and fm3 == 0x3e9 and fcsr == 0x80 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3633; op2val:0x3d1a;
op3val:0x37e9; valaddr_reg:x3; val_offset:2082*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:128 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 128, 0, x3, 2082*FLEN/8, x4, x1, x2)

inst_695:
// fs1 == 0 and fe1 == 0x0d and fm1 == 0x3ce and fs2 == 0 and fe2 == 0x0e and fm2 == 0x10a and fs3 == 0 and fe3 == 0x0d and fm3 == 0x0ea and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x37ce; op2val:0x390a;
op3val:0x34ea; valaddr_reg:x3; val_offset:2085*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 2085*FLEN/8, x4, x1, x2)

inst_696:
// fs1 == 0 and fe1 == 0x0d and fm1 == 0x3ce and fs2 == 0 and fe2 == 0x0e and fm2 == 0x10a and fs3 == 0 and fe3 == 0x0d and fm3 == 0x0ea and fcsr == 0x20 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x37ce; op2val:0x390a;
op3val:0x34ea; valaddr_reg:x3; val_offset:2088*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:32 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 32, 0, x3, 2088*FLEN/8, x4, x1, x2)

inst_697:
// fs1 == 0 and fe1 == 0x0d and fm1 == 0x3ce and fs2 == 0 and fe2 == 0x0e and fm2 == 0x10a and fs3 == 0 and fe3 == 0x0d and fm3 == 0x0ea and fcsr == 0x40 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x37ce; op2val:0x390a;
op3val:0x34ea; valaddr_reg:x3; val_offset:2091*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:64 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 64, 0, x3, 2091*FLEN/8, x4, x1, x2)

inst_698:
// fs1 == 0 and fe1 == 0x0d and fm1 == 0x3ce and fs2 == 0 and fe2 == 0x0e and fm2 == 0x10a and fs3 == 0 and fe3 == 0x0d and fm3 == 0x0ea and fcsr == 0x60 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x37ce; op2val:0x390a;
op3val:0x34ea; valaddr_reg:x3; val_offset:2094*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 96, 0, x3, 2094*FLEN/8, x4, x1, x2)

inst_699:
// fs1 == 0 and fe1 == 0x0d and fm1 == 0x3ce and fs2 == 0 and fe2 == 0x0e and fm2 == 0x10a and fs3 == 0 and fe3 == 0x0d and fm3 == 0x0ea and fcsr == 0x80 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x37ce; op2val:0x390a;
op3val:0x34ea; valaddr_reg:x3; val_offset:2097*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:128 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 128, 0, x3, 2097*FLEN/8, x4, x1, x2)

inst_700:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x061 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x2d1 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x377 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3861; op2val:0x3ad1;
op3val:0x3777; valaddr_reg:x3; val_offset:2100*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 2100*FLEN/8, x4, x1, x2)

inst_701:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x061 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x2d1 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x377 and fcsr == 0x20 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3861; op2val:0x3ad1;
op3val:0x3777; valaddr_reg:x3; val_offset:2103*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:32 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 32, 0, x3, 2103*FLEN/8, x4, x1, x2)

inst_702:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x061 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x2d1 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x377 and fcsr == 0x40 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3861; op2val:0x3ad1;
op3val:0x3777; valaddr_reg:x3; val_offset:2106*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:64 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 64, 0, x3, 2106*FLEN/8, x4, x1, x2)

inst_703:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x061 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x2d1 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x377 and fcsr == 0x60 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3861; op2val:0x3ad1;
op3val:0x3777; valaddr_reg:x3; val_offset:2109*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 96, 0, x3, 2109*FLEN/8, x4, x1, x2)

inst_704:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x061 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x2d1 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x377 and fcsr == 0x80 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3861; op2val:0x3ad1;
op3val:0x3777; valaddr_reg:x3; val_offset:2112*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:128 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 128, 0, x3, 2112*FLEN/8, x4, x1, x2)

inst_705:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x02d and fs2 == 0 and fe2 == 0x0b and fm2 == 0x32f and fs3 == 0 and fe3 == 0x0a and fm3 == 0x37e and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x382d; op2val:0x2f2f;
op3val:0x2b7e; valaddr_reg:x3; val_offset:2115*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 2115*FLEN/8, x4, x1, x2)

inst_706:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x02d and fs2 == 0 and fe2 == 0x0b and fm2 == 0x32f and fs3 == 0 and fe3 == 0x0a and fm3 == 0x37e and fcsr == 0x20 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x382d; op2val:0x2f2f;
op3val:0x2b7e; valaddr_reg:x3; val_offset:2118*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:32 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 32, 0, x3, 2118*FLEN/8, x4, x1, x2)

inst_707:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x02d and fs2 == 0 and fe2 == 0x0b and fm2 == 0x32f and fs3 == 0 and fe3 == 0x0a and fm3 == 0x37e and fcsr == 0x40 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x382d; op2val:0x2f2f;
op3val:0x2b7e; valaddr_reg:x3; val_offset:2121*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:64 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 64, 0, x3, 2121*FLEN/8, x4, x1, x2)

inst_708:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x02d and fs2 == 0 and fe2 == 0x0b and fm2 == 0x32f and fs3 == 0 and fe3 == 0x0a and fm3 == 0x37e and fcsr == 0x60 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x382d; op2val:0x2f2f;
op3val:0x2b7e; valaddr_reg:x3; val_offset:2124*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 96, 0, x3, 2124*FLEN/8, x4, x1, x2)

inst_709:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x02d and fs2 == 0 and fe2 == 0x0b and fm2 == 0x32f and fs3 == 0 and fe3 == 0x0a and fm3 == 0x37e and fcsr == 0x80 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x382d; op2val:0x2f2f;
op3val:0x2b7e; valaddr_reg:x3; val_offset:2127*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:128 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 128, 0, x3, 2127*FLEN/8, x4, x1, x2)

inst_710:
// fs1 == 0 and fe1 == 0x0d and fm1 == 0x0d0 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x292 and fs3 == 0 and fe3 == 0x0b and fm3 == 0x3e7 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x34d0; op2val:0x3692;
op3val:0x2fe7; valaddr_reg:x3; val_offset:2130*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 2130*FLEN/8, x4, x1, x2)

inst_711:
// fs1 == 0 and fe1 == 0x0d and fm1 == 0x0d0 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x292 and fs3 == 0 and fe3 == 0x0b and fm3 == 0x3e7 and fcsr == 0x20 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x34d0; op2val:0x3692;
op3val:0x2fe7; valaddr_reg:x3; val_offset:2133*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:32 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 32, 0, x3, 2133*FLEN/8, x4, x1, x2)

inst_712:
// fs1 == 0 and fe1 == 0x0d and fm1 == 0x0d0 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x292 and fs3 == 0 and fe3 == 0x0b and fm3 == 0x3e7 and fcsr == 0x40 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x34d0; op2val:0x3692;
op3val:0x2fe7; valaddr_reg:x3; val_offset:2136*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:64 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 64, 0, x3, 2136*FLEN/8, x4, x1, x2)

inst_713:
// fs1 == 0 and fe1 == 0x0d and fm1 == 0x0d0 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x292 and fs3 == 0 and fe3 == 0x0b and fm3 == 0x3e7 and fcsr == 0x60 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x34d0; op2val:0x3692;
op3val:0x2fe7; valaddr_reg:x3; val_offset:2139*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 96, 0, x3, 2139*FLEN/8, x4, x1, x2)

inst_714:
// fs1 == 0 and fe1 == 0x0d and fm1 == 0x0d0 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x292 and fs3 == 0 and fe3 == 0x0b and fm3 == 0x3e7 and fcsr == 0x80 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x34d0; op2val:0x3692;
op3val:0x2fe7; valaddr_reg:x3; val_offset:2142*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:128 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 128, 0, x3, 2142*FLEN/8, x4, x1, x2)

inst_715:
// fs1 == 0 and fe1 == 0x0a and fm1 == 0x368 and fs2 == 0 and fe2 == 0x12 and fm2 == 0x265 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x1ec and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x2b68; op2val:0x4a65;
op3val:0x39ec; valaddr_reg:x3; val_offset:2145*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 2145*FLEN/8, x4, x1, x2)

inst_716:
// fs1 == 0 and fe1 == 0x0a and fm1 == 0x368 and fs2 == 0 and fe2 == 0x12 and fm2 == 0x265 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x1ec and fcsr == 0x20 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x2b68; op2val:0x4a65;
op3val:0x39ec; valaddr_reg:x3; val_offset:2148*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:32 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 32, 0, x3, 2148*FLEN/8, x4, x1, x2)

inst_717:
// fs1 == 0 and fe1 == 0x0a and fm1 == 0x368 and fs2 == 0 and fe2 == 0x12 and fm2 == 0x265 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x1ec and fcsr == 0x40 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x2b68; op2val:0x4a65;
op3val:0x39ec; valaddr_reg:x3; val_offset:2151*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:64 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 64, 0, x3, 2151*FLEN/8, x4, x1, x2)

inst_718:
// fs1 == 0 and fe1 == 0x0a and fm1 == 0x368 and fs2 == 0 and fe2 == 0x12 and fm2 == 0x265 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x1ec and fcsr == 0x60 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x2b68; op2val:0x4a65;
op3val:0x39ec; valaddr_reg:x3; val_offset:2154*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 96, 0, x3, 2154*FLEN/8, x4, x1, x2)

inst_719:
// fs1 == 0 and fe1 == 0x0a and fm1 == 0x368 and fs2 == 0 and fe2 == 0x12 and fm2 == 0x265 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x1ec and fcsr == 0x80 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x2b68; op2val:0x4a65;
op3val:0x39ec; valaddr_reg:x3; val_offset:2157*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:128 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 128, 0, x3, 2157*FLEN/8, x4, x1, x2)

inst_720:
// fs1 == 0 and fe1 == 0x0d and fm1 == 0x30c and fs2 == 0 and fe2 == 0x0c and fm2 == 0x021 and fs3 == 0 and fe3 == 0x0a and fm3 == 0x344 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x370c; op2val:0x3021;
op3val:0x2b44; valaddr_reg:x3; val_offset:2160*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 2160*FLEN/8, x4, x1, x2)

inst_721:
// fs1 == 0 and fe1 == 0x0d and fm1 == 0x30c and fs2 == 0 and fe2 == 0x0c and fm2 == 0x021 and fs3 == 0 and fe3 == 0x0a and fm3 == 0x344 and fcsr == 0x20 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x370c; op2val:0x3021;
op3val:0x2b44; valaddr_reg:x3; val_offset:2163*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:32 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 32, 0, x3, 2163*FLEN/8, x4, x1, x2)

inst_722:
// fs1 == 0 and fe1 == 0x0d and fm1 == 0x30c and fs2 == 0 and fe2 == 0x0c and fm2 == 0x021 and fs3 == 0 and fe3 == 0x0a and fm3 == 0x344 and fcsr == 0x40 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x370c; op2val:0x3021;
op3val:0x2b44; valaddr_reg:x3; val_offset:2166*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:64 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 64, 0, x3, 2166*FLEN/8, x4, x1, x2)

inst_723:
// fs1 == 0 and fe1 == 0x0d and fm1 == 0x30c and fs2 == 0 and fe2 == 0x0c and fm2 == 0x021 and fs3 == 0 and fe3 == 0x0a and fm3 == 0x344 and fcsr == 0x60 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x370c; op2val:0x3021;
op3val:0x2b44; valaddr_reg:x3; val_offset:2169*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 96, 0, x3, 2169*FLEN/8, x4, x1, x2)

inst_724:
// fs1 == 0 and fe1 == 0x0d and fm1 == 0x30c and fs2 == 0 and fe2 == 0x0c and fm2 == 0x021 and fs3 == 0 and fe3 == 0x0a and fm3 == 0x344 and fcsr == 0x80 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x370c; op2val:0x3021;
op3val:0x2b44; valaddr_reg:x3; val_offset:2172*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:128 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 128, 0, x3, 2172*FLEN/8, x4, x1, x2)

inst_725:
// fs1 == 0 and fe1 == 0x0c and fm1 == 0x11f and fs2 == 0 and fe2 == 0x11 and fm2 == 0x164 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x2e7 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x311f; op2val:0x4564;
op3val:0x3ae7; valaddr_reg:x3; val_offset:2175*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 2175*FLEN/8, x4, x1, x2)

inst_726:
// fs1 == 0 and fe1 == 0x0c and fm1 == 0x11f and fs2 == 0 and fe2 == 0x11 and fm2 == 0x164 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x2e7 and fcsr == 0x20 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x311f; op2val:0x4564;
op3val:0x3ae7; valaddr_reg:x3; val_offset:2178*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:32 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 32, 0, x3, 2178*FLEN/8, x4, x1, x2)

inst_727:
// fs1 == 0 and fe1 == 0x0c and fm1 == 0x11f and fs2 == 0 and fe2 == 0x11 and fm2 == 0x164 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x2e7 and fcsr == 0x40 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x311f; op2val:0x4564;
op3val:0x3ae7; valaddr_reg:x3; val_offset:2181*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:64 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 64, 0, x3, 2181*FLEN/8, x4, x1, x2)

inst_728:
// fs1 == 0 and fe1 == 0x0c and fm1 == 0x11f and fs2 == 0 and fe2 == 0x11 and fm2 == 0x164 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x2e7 and fcsr == 0x60 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x311f; op2val:0x4564;
op3val:0x3ae7; valaddr_reg:x3; val_offset:2184*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 96, 0, x3, 2184*FLEN/8, x4, x1, x2)

inst_729:
// fs1 == 0 and fe1 == 0x0c and fm1 == 0x11f and fs2 == 0 and fe2 == 0x11 and fm2 == 0x164 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x2e7 and fcsr == 0x80 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x311f; op2val:0x4564;
op3val:0x3ae7; valaddr_reg:x3; val_offset:2187*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:128 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 128, 0, x3, 2187*FLEN/8, x4, x1, x2)

inst_730:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x306 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x114 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x076 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3b06; op2val:0x3914;
op3val:0x3876; valaddr_reg:x3; val_offset:2190*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 2190*FLEN/8, x4, x1, x2)

inst_731:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x306 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x114 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x076 and fcsr == 0x20 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3b06; op2val:0x3914;
op3val:0x3876; valaddr_reg:x3; val_offset:2193*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:32 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 32, 0, x3, 2193*FLEN/8, x4, x1, x2)

inst_732:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x306 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x114 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x076 and fcsr == 0x40 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3b06; op2val:0x3914;
op3val:0x3876; valaddr_reg:x3; val_offset:2196*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:64 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 64, 0, x3, 2196*FLEN/8, x4, x1, x2)

inst_733:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x306 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x114 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x076 and fcsr == 0x60 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3b06; op2val:0x3914;
op3val:0x3876; valaddr_reg:x3; val_offset:2199*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 96, 0, x3, 2199*FLEN/8, x4, x1, x2)

inst_734:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x306 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x114 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x076 and fcsr == 0x80 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3b06; op2val:0x3914;
op3val:0x3876; valaddr_reg:x3; val_offset:2202*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:128 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 128, 0, x3, 2202*FLEN/8, x4, x1, x2)

inst_735:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x36b and fs2 == 0 and fe2 == 0x0e and fm2 == 0x28c and fs3 == 0 and fe3 == 0x0e and fm3 == 0x213 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3b6b; op2val:0x3a8c;
op3val:0x3a13; valaddr_reg:x3; val_offset:2205*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 2205*FLEN/8, x4, x1, x2)

inst_736:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x36b and fs2 == 0 and fe2 == 0x0e and fm2 == 0x28c and fs3 == 0 and fe3 == 0x0e and fm3 == 0x213 and fcsr == 0x20 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3b6b; op2val:0x3a8c;
op3val:0x3a13; valaddr_reg:x3; val_offset:2208*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:32 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 32, 0, x3, 2208*FLEN/8, x4, x1, x2)

inst_737:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x36b and fs2 == 0 and fe2 == 0x0e and fm2 == 0x28c and fs3 == 0 and fe3 == 0x0e and fm3 == 0x213 and fcsr == 0x40 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3b6b; op2val:0x3a8c;
op3val:0x3a13; valaddr_reg:x3; val_offset:2211*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:64 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 64, 0, x3, 2211*FLEN/8, x4, x1, x2)

inst_738:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x36b and fs2 == 0 and fe2 == 0x0e and fm2 == 0x28c and fs3 == 0 and fe3 == 0x0e and fm3 == 0x213 and fcsr == 0x60 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3b6b; op2val:0x3a8c;
op3val:0x3a13; valaddr_reg:x3; val_offset:2214*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 96, 0, x3, 2214*FLEN/8, x4, x1, x2)

inst_739:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x36b and fs2 == 0 and fe2 == 0x0e and fm2 == 0x28c and fs3 == 0 and fe3 == 0x0e and fm3 == 0x213 and fcsr == 0x80 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3b6b; op2val:0x3a8c;
op3val:0x3a13; valaddr_reg:x3; val_offset:2217*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:128 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 128, 0, x3, 2217*FLEN/8, x4, x1, x2)

inst_740:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x36a and fs2 == 0 and fe2 == 0x0d and fm2 == 0x1b5 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x14a and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3b6a; op2val:0x35b5;
op3val:0x354a; valaddr_reg:x3; val_offset:2220*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 2220*FLEN/8, x4, x1, x2)

inst_741:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x36a and fs2 == 0 and fe2 == 0x0d and fm2 == 0x1b5 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x14a and fcsr == 0x20 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3b6a; op2val:0x35b5;
op3val:0x354a; valaddr_reg:x3; val_offset:2223*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:32 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 32, 0, x3, 2223*FLEN/8, x4, x1, x2)

inst_742:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x36a and fs2 == 0 and fe2 == 0x0d and fm2 == 0x1b5 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x14a and fcsr == 0x40 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3b6a; op2val:0x35b5;
op3val:0x354a; valaddr_reg:x3; val_offset:2226*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:64 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 64, 0, x3, 2226*FLEN/8, x4, x1, x2)

inst_743:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x36a and fs2 == 0 and fe2 == 0x0d and fm2 == 0x1b5 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x14a and fcsr == 0x60 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3b6a; op2val:0x35b5;
op3val:0x354a; valaddr_reg:x3; val_offset:2229*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 96, 0, x3, 2229*FLEN/8, x4, x1, x2)

inst_744:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x36a and fs2 == 0 and fe2 == 0x0d and fm2 == 0x1b5 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x14a and fcsr == 0x80 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3b6a; op2val:0x35b5;
op3val:0x354a; valaddr_reg:x3; val_offset:2232*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:128 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 128, 0, x3, 2232*FLEN/8, x4, x1, x2)

inst_745:
// fs1 == 0 and fe1 == 0x0c and fm1 == 0x2ea and fs2 == 0 and fe2 == 0x0d and fm2 == 0x3a1 and fs3 == 0 and fe3 == 0x0b and fm3 == 0x298 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x32ea; op2val:0x37a1;
op3val:0x2e98; valaddr_reg:x3; val_offset:2235*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 2235*FLEN/8, x4, x1, x2)

inst_746:
// fs1 == 0 and fe1 == 0x0c and fm1 == 0x2ea and fs2 == 0 and fe2 == 0x0d and fm2 == 0x3a1 and fs3 == 0 and fe3 == 0x0b and fm3 == 0x298 and fcsr == 0x20 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x32ea; op2val:0x37a1;
op3val:0x2e98; valaddr_reg:x3; val_offset:2238*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:32 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 32, 0, x3, 2238*FLEN/8, x4, x1, x2)

inst_747:
// fs1 == 0 and fe1 == 0x0c and fm1 == 0x2ea and fs2 == 0 and fe2 == 0x0d and fm2 == 0x3a1 and fs3 == 0 and fe3 == 0x0b and fm3 == 0x298 and fcsr == 0x40 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x32ea; op2val:0x37a1;
op3val:0x2e98; valaddr_reg:x3; val_offset:2241*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:64 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 64, 0, x3, 2241*FLEN/8, x4, x1, x2)

inst_748:
// fs1 == 0 and fe1 == 0x0c and fm1 == 0x2ea and fs2 == 0 and fe2 == 0x0d and fm2 == 0x3a1 and fs3 == 0 and fe3 == 0x0b and fm3 == 0x298 and fcsr == 0x60 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x32ea; op2val:0x37a1;
op3val:0x2e98; valaddr_reg:x3; val_offset:2244*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 96, 0, x3, 2244*FLEN/8, x4, x1, x2)

inst_749:
// fs1 == 0 and fe1 == 0x0c and fm1 == 0x2ea and fs2 == 0 and fe2 == 0x0d and fm2 == 0x3a1 and fs3 == 0 and fe3 == 0x0b and fm3 == 0x298 and fcsr == 0x80 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x32ea; op2val:0x37a1;
op3val:0x2e98; valaddr_reg:x3; val_offset:2247*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:128 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 128, 0, x3, 2247*FLEN/8, x4, x1, x2)

inst_750:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x2c3 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x15f and fs3 == 0 and fe3 == 0x0d and fm3 == 0x08a and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3ac3; op2val:0x355f;
op3val:0x348a; valaddr_reg:x3; val_offset:2250*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 2250*FLEN/8, x4, x1, x2)

inst_751:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x2c3 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x15f and fs3 == 0 and fe3 == 0x0d and fm3 == 0x08a and fcsr == 0x20 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3ac3; op2val:0x355f;
op3val:0x348a; valaddr_reg:x3; val_offset:2253*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:32 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 32, 0, x3, 2253*FLEN/8, x4, x1, x2)

inst_752:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x2c3 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x15f and fs3 == 0 and fe3 == 0x0d and fm3 == 0x08a and fcsr == 0x40 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3ac3; op2val:0x355f;
op3val:0x348a; valaddr_reg:x3; val_offset:2256*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:64 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 64, 0, x3, 2256*FLEN/8, x4, x1, x2)

inst_753:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x2c3 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x15f and fs3 == 0 and fe3 == 0x0d and fm3 == 0x08a and fcsr == 0x60 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3ac3; op2val:0x355f;
op3val:0x348a; valaddr_reg:x3; val_offset:2259*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 96, 0, x3, 2259*FLEN/8, x4, x1, x2)

inst_754:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x2c3 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x15f and fs3 == 0 and fe3 == 0x0d and fm3 == 0x08a and fcsr == 0x80 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3ac3; op2val:0x355f;
op3val:0x348a; valaddr_reg:x3; val_offset:2262*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:128 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 128, 0, x3, 2262*FLEN/8, x4, x1, x2)

inst_755:
// fs1 == 0 and fe1 == 0x0d and fm1 == 0x16f and fs2 == 0 and fe2 == 0x10 and fm2 == 0x10b and fs3 == 0 and fe3 == 0x0e and fm3 == 0x2db and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x356f; op2val:0x410b;
op3val:0x3adb; valaddr_reg:x3; val_offset:2265*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 2265*FLEN/8, x4, x1, x2)

inst_756:
// fs1 == 0 and fe1 == 0x0d and fm1 == 0x16f and fs2 == 0 and fe2 == 0x10 and fm2 == 0x10b and fs3 == 0 and fe3 == 0x0e and fm3 == 0x2db and fcsr == 0x20 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x356f; op2val:0x410b;
op3val:0x3adb; valaddr_reg:x3; val_offset:2268*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:32 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 32, 0, x3, 2268*FLEN/8, x4, x1, x2)

inst_757:
// fs1 == 0 and fe1 == 0x0d and fm1 == 0x16f and fs2 == 0 and fe2 == 0x10 and fm2 == 0x10b and fs3 == 0 and fe3 == 0x0e and fm3 == 0x2db and fcsr == 0x40 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x356f; op2val:0x410b;
op3val:0x3adb; valaddr_reg:x3; val_offset:2271*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:64 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 64, 0, x3, 2271*FLEN/8, x4, x1, x2)

inst_758:
// fs1 == 0 and fe1 == 0x0d and fm1 == 0x16f and fs2 == 0 and fe2 == 0x10 and fm2 == 0x10b and fs3 == 0 and fe3 == 0x0e and fm3 == 0x2db and fcsr == 0x60 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x356f; op2val:0x410b;
op3val:0x3adb; valaddr_reg:x3; val_offset:2274*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 96, 0, x3, 2274*FLEN/8, x4, x1, x2)

inst_759:
// fs1 == 0 and fe1 == 0x0d and fm1 == 0x16f and fs2 == 0 and fe2 == 0x10 and fm2 == 0x10b and fs3 == 0 and fe3 == 0x0e and fm3 == 0x2db and fcsr == 0x80 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x356f; op2val:0x410b;
op3val:0x3adb; valaddr_reg:x3; val_offset:2277*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:128 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 128, 0, x3, 2277*FLEN/8, x4, x1, x2)

inst_760:
// fs1 == 0 and fe1 == 0x0b and fm1 == 0x380 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x072 and fs3 == 0 and fe3 == 0x0a and fm3 == 0x029 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x2f80; op2val:0x3472;
op3val:0x2829; valaddr_reg:x3; val_offset:2280*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 2280*FLEN/8, x4, x1, x2)

inst_761:
// fs1 == 0 and fe1 == 0x0b and fm1 == 0x380 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x072 and fs3 == 0 and fe3 == 0x0a and fm3 == 0x029 and fcsr == 0x20 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x2f80; op2val:0x3472;
op3val:0x2829; valaddr_reg:x3; val_offset:2283*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:32 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 32, 0, x3, 2283*FLEN/8, x4, x1, x2)

inst_762:
// fs1 == 0 and fe1 == 0x0b and fm1 == 0x380 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x072 and fs3 == 0 and fe3 == 0x0a and fm3 == 0x029 and fcsr == 0x40 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x2f80; op2val:0x3472;
op3val:0x2829; valaddr_reg:x3; val_offset:2286*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:64 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 64, 0, x3, 2286*FLEN/8, x4, x1, x2)

inst_763:
// fs1 == 0 and fe1 == 0x0b and fm1 == 0x380 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x072 and fs3 == 0 and fe3 == 0x0a and fm3 == 0x029 and fcsr == 0x60 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x2f80; op2val:0x3472;
op3val:0x2829; valaddr_reg:x3; val_offset:2289*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 96, 0, x3, 2289*FLEN/8, x4, x1, x2)

inst_764:
// fs1 == 0 and fe1 == 0x0b and fm1 == 0x380 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x072 and fs3 == 0 and fe3 == 0x0a and fm3 == 0x029 and fcsr == 0x80 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x2f80; op2val:0x3472;
op3val:0x2829; valaddr_reg:x3; val_offset:2292*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:128 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 128, 0, x3, 2292*FLEN/8, x4, x1, x2)

inst_765:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x23e and fs2 == 0 and fe2 == 0x0a and fm2 == 0x3cf and fs3 == 0 and fe3 == 0x0a and fm3 == 0x216 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3a3e; op2val:0x2bcf;
op3val:0x2a16; valaddr_reg:x3; val_offset:2295*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 2295*FLEN/8, x4, x1, x2)

inst_766:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x23e and fs2 == 0 and fe2 == 0x0a and fm2 == 0x3cf and fs3 == 0 and fe3 == 0x0a and fm3 == 0x216 and fcsr == 0x20 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3a3e; op2val:0x2bcf;
op3val:0x2a16; valaddr_reg:x3; val_offset:2298*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:32 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 32, 0, x3, 2298*FLEN/8, x4, x1, x2)

inst_767:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x23e and fs2 == 0 and fe2 == 0x0a and fm2 == 0x3cf and fs3 == 0 and fe3 == 0x0a and fm3 == 0x216 and fcsr == 0x40 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3a3e; op2val:0x2bcf;
op3val:0x2a16; valaddr_reg:x3; val_offset:2301*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:64 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 64, 0, x3, 2301*FLEN/8, x4, x1, x2)
RVTEST_SIGBASE(x1,signature_x1_7)

inst_768:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x23e and fs2 == 0 and fe2 == 0x0a and fm2 == 0x3cf and fs3 == 0 and fe3 == 0x0a and fm3 == 0x216 and fcsr == 0x60 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3a3e; op2val:0x2bcf;
op3val:0x2a16; valaddr_reg:x3; val_offset:2304*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 96, 0, x3, 2304*FLEN/8, x4, x1, x2)

inst_769:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x23e and fs2 == 0 and fe2 == 0x0a and fm2 == 0x3cf and fs3 == 0 and fe3 == 0x0a and fm3 == 0x216 and fcsr == 0x80 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3a3e; op2val:0x2bcf;
op3val:0x2a16; valaddr_reg:x3; val_offset:2307*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:128 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 128, 0, x3, 2307*FLEN/8, x4, x1, x2)

inst_770:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x0d0 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x2d1 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x01a and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x38d0; op2val:0x3ad1;
op3val:0x381a; valaddr_reg:x3; val_offset:2310*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 2310*FLEN/8, x4, x1, x2)

inst_771:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x0d0 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x2d1 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x01a and fcsr == 0x20 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x38d0; op2val:0x3ad1;
op3val:0x381a; valaddr_reg:x3; val_offset:2313*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:32 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 32, 0, x3, 2313*FLEN/8, x4, x1, x2)

inst_772:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x0d0 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x2d1 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x01a and fcsr == 0x40 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x38d0; op2val:0x3ad1;
op3val:0x381a; valaddr_reg:x3; val_offset:2316*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:64 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 64, 0, x3, 2316*FLEN/8, x4, x1, x2)

inst_773:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x0d0 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x2d1 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x01a and fcsr == 0x60 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x38d0; op2val:0x3ad1;
op3val:0x381a; valaddr_reg:x3; val_offset:2319*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 96, 0, x3, 2319*FLEN/8, x4, x1, x2)

inst_774:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x0d0 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x2d1 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x01a and fcsr == 0x80 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x38d0; op2val:0x3ad1;
op3val:0x381a; valaddr_reg:x3; val_offset:2322*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:128 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 128, 0, x3, 2322*FLEN/8, x4, x1, x2)

inst_775:
// fs1 == 0 and fe1 == 0x08 and fm1 == 0x137 and fs2 == 0 and fe2 == 0x13 and fm2 == 0x01d and fs3 == 0 and fe3 == 0x0c and fm3 == 0x15d and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x2137; op2val:0x4c1d;
op3val:0x315d; valaddr_reg:x3; val_offset:2325*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 2325*FLEN/8, x4, x1, x2)

inst_776:
// fs1 == 0 and fe1 == 0x08 and fm1 == 0x137 and fs2 == 0 and fe2 == 0x13 and fm2 == 0x01d and fs3 == 0 and fe3 == 0x0c and fm3 == 0x15d and fcsr == 0x20 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x2137; op2val:0x4c1d;
op3val:0x315d; valaddr_reg:x3; val_offset:2328*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:32 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 32, 0, x3, 2328*FLEN/8, x4, x1, x2)

inst_777:
// fs1 == 0 and fe1 == 0x08 and fm1 == 0x137 and fs2 == 0 and fe2 == 0x13 and fm2 == 0x01d and fs3 == 0 and fe3 == 0x0c and fm3 == 0x15d and fcsr == 0x40 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x2137; op2val:0x4c1d;
op3val:0x315d; valaddr_reg:x3; val_offset:2331*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:64 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 64, 0, x3, 2331*FLEN/8, x4, x1, x2)

inst_778:
// fs1 == 0 and fe1 == 0x08 and fm1 == 0x137 and fs2 == 0 and fe2 == 0x13 and fm2 == 0x01d and fs3 == 0 and fe3 == 0x0c and fm3 == 0x15d and fcsr == 0x60 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x2137; op2val:0x4c1d;
op3val:0x315d; valaddr_reg:x3; val_offset:2334*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 96, 0, x3, 2334*FLEN/8, x4, x1, x2)

inst_779:
// fs1 == 0 and fe1 == 0x08 and fm1 == 0x137 and fs2 == 0 and fe2 == 0x13 and fm2 == 0x01d and fs3 == 0 and fe3 == 0x0c and fm3 == 0x15d and fcsr == 0x80 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x2137; op2val:0x4c1d;
op3val:0x315d; valaddr_reg:x3; val_offset:2337*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:128 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 128, 0, x3, 2337*FLEN/8, x4, x1, x2)

inst_780:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x2b5 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x16c and fs3 == 0 and fe3 == 0x0e and fm3 == 0x08c and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3ab5; op2val:0x396c;
op3val:0x388c; valaddr_reg:x3; val_offset:2340*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 2340*FLEN/8, x4, x1, x2)

inst_781:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x2b5 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x16c and fs3 == 0 and fe3 == 0x0e and fm3 == 0x08c and fcsr == 0x20 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3ab5; op2val:0x396c;
op3val:0x388c; valaddr_reg:x3; val_offset:2343*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:32 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 32, 0, x3, 2343*FLEN/8, x4, x1, x2)

inst_782:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x2b5 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x16c and fs3 == 0 and fe3 == 0x0e and fm3 == 0x08c and fcsr == 0x40 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3ab5; op2val:0x396c;
op3val:0x388c; valaddr_reg:x3; val_offset:2346*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:64 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 64, 0, x3, 2346*FLEN/8, x4, x1, x2)

inst_783:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x2b5 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x16c and fs3 == 0 and fe3 == 0x0e and fm3 == 0x08c and fcsr == 0x60 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3ab5; op2val:0x396c;
op3val:0x388c; valaddr_reg:x3; val_offset:2349*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 96, 0, x3, 2349*FLEN/8, x4, x1, x2)

inst_784:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x2b5 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x16c and fs3 == 0 and fe3 == 0x0e and fm3 == 0x08c and fcsr == 0x80 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3ab5; op2val:0x396c;
op3val:0x388c; valaddr_reg:x3; val_offset:2352*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:128 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 128, 0, x3, 2352*FLEN/8, x4, x1, x2)

inst_785:
// fs1 == 0 and fe1 == 0x0d and fm1 == 0x3c0 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x175 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x149 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x37c0; op2val:0x3d75;
op3val:0x3949; valaddr_reg:x3; val_offset:2355*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 2355*FLEN/8, x4, x1, x2)

inst_786:
// fs1 == 0 and fe1 == 0x0d and fm1 == 0x3c0 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x175 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x149 and fcsr == 0x20 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x37c0; op2val:0x3d75;
op3val:0x3949; valaddr_reg:x3; val_offset:2358*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:32 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 32, 0, x3, 2358*FLEN/8, x4, x1, x2)

inst_787:
// fs1 == 0 and fe1 == 0x0d and fm1 == 0x3c0 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x175 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x149 and fcsr == 0x40 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x37c0; op2val:0x3d75;
op3val:0x3949; valaddr_reg:x3; val_offset:2361*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:64 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 64, 0, x3, 2361*FLEN/8, x4, x1, x2)

inst_788:
// fs1 == 0 and fe1 == 0x0d and fm1 == 0x3c0 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x175 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x149 and fcsr == 0x60 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x37c0; op2val:0x3d75;
op3val:0x3949; valaddr_reg:x3; val_offset:2364*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 96, 0, x3, 2364*FLEN/8, x4, x1, x2)

inst_789:
// fs1 == 0 and fe1 == 0x0d and fm1 == 0x3c0 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x175 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x149 and fcsr == 0x80 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x37c0; op2val:0x3d75;
op3val:0x3949; valaddr_reg:x3; val_offset:2367*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:128 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 128, 0, x3, 2367*FLEN/8, x4, x1, x2)

inst_790:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x26f and fs2 == 0 and fe2 == 0x0e and fm2 == 0x2c7 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x173 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3a6f; op2val:0x3ac7;
op3val:0x3973; valaddr_reg:x3; val_offset:2370*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 2370*FLEN/8, x4, x1, x2)

inst_791:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x26f and fs2 == 0 and fe2 == 0x0e and fm2 == 0x2c7 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x173 and fcsr == 0x20 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3a6f; op2val:0x3ac7;
op3val:0x3973; valaddr_reg:x3; val_offset:2373*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:32 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 32, 0, x3, 2373*FLEN/8, x4, x1, x2)

inst_792:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x26f and fs2 == 0 and fe2 == 0x0e and fm2 == 0x2c7 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x173 and fcsr == 0x40 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3a6f; op2val:0x3ac7;
op3val:0x3973; valaddr_reg:x3; val_offset:2376*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:64 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 64, 0, x3, 2376*FLEN/8, x4, x1, x2)

inst_793:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x26f and fs2 == 0 and fe2 == 0x0e and fm2 == 0x2c7 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x173 and fcsr == 0x60 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3a6f; op2val:0x3ac7;
op3val:0x3973; valaddr_reg:x3; val_offset:2379*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 96, 0, x3, 2379*FLEN/8, x4, x1, x2)

inst_794:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x26f and fs2 == 0 and fe2 == 0x0e and fm2 == 0x2c7 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x173 and fcsr == 0x80 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3a6f; op2val:0x3ac7;
op3val:0x3973; valaddr_reg:x3; val_offset:2382*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:128 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 128, 0, x3, 2382*FLEN/8, x4, x1, x2)

inst_795:
// fs1 == 0 and fe1 == 0x0d and fm1 == 0x072 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x30e and fs3 == 0 and fe3 == 0x0e and fm3 == 0x3d8 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3472; op2val:0x430e;
op3val:0x3bd8; valaddr_reg:x3; val_offset:2385*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 2385*FLEN/8, x4, x1, x2)

inst_796:
// fs1 == 0 and fe1 == 0x0d and fm1 == 0x072 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x30e and fs3 == 0 and fe3 == 0x0e and fm3 == 0x3d8 and fcsr == 0x20 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3472; op2val:0x430e;
op3val:0x3bd8; valaddr_reg:x3; val_offset:2388*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:32 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 32, 0, x3, 2388*FLEN/8, x4, x1, x2)

inst_797:
// fs1 == 0 and fe1 == 0x0d and fm1 == 0x072 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x30e and fs3 == 0 and fe3 == 0x0e and fm3 == 0x3d8 and fcsr == 0x40 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3472; op2val:0x430e;
op3val:0x3bd8; valaddr_reg:x3; val_offset:2391*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:64 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 64, 0, x3, 2391*FLEN/8, x4, x1, x2)

inst_798:
// fs1 == 0 and fe1 == 0x0d and fm1 == 0x072 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x30e and fs3 == 0 and fe3 == 0x0e and fm3 == 0x3d8 and fcsr == 0x60 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3472; op2val:0x430e;
op3val:0x3bd8; valaddr_reg:x3; val_offset:2394*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 96, 0, x3, 2394*FLEN/8, x4, x1, x2)

inst_799:
// fs1 == 0 and fe1 == 0x0d and fm1 == 0x072 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x30e and fs3 == 0 and fe3 == 0x0e and fm3 == 0x3d8 and fcsr == 0x80 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3472; op2val:0x430e;
op3val:0x3bd8; valaddr_reg:x3; val_offset:2397*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:128 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 128, 0, x3, 2397*FLEN/8, x4, x1, x2)

inst_800:
// fs1 == 0 and fe1 == 0x0d and fm1 == 0x322 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x104 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x079 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3722; op2val:0x3d04;
op3val:0x3879; valaddr_reg:x3; val_offset:2400*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 2400*FLEN/8, x4, x1, x2)

inst_801:
// fs1 == 0 and fe1 == 0x0d and fm1 == 0x322 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x104 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x079 and fcsr == 0x20 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3722; op2val:0x3d04;
op3val:0x3879; valaddr_reg:x3; val_offset:2403*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:32 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 32, 0, x3, 2403*FLEN/8, x4, x1, x2)

inst_802:
// fs1 == 0 and fe1 == 0x0d and fm1 == 0x322 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x104 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x079 and fcsr == 0x40 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3722; op2val:0x3d04;
op3val:0x3879; valaddr_reg:x3; val_offset:2406*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:64 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 64, 0, x3, 2406*FLEN/8, x4, x1, x2)

inst_803:
// fs1 == 0 and fe1 == 0x0d and fm1 == 0x322 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x104 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x079 and fcsr == 0x60 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3722; op2val:0x3d04;
op3val:0x3879; valaddr_reg:x3; val_offset:2409*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 96, 0, x3, 2409*FLEN/8, x4, x1, x2)

inst_804:
// fs1 == 0 and fe1 == 0x0d and fm1 == 0x322 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x104 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x079 and fcsr == 0x80 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3722; op2val:0x3d04;
op3val:0x3879; valaddr_reg:x3; val_offset:2412*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:128 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 128, 0, x3, 2412*FLEN/8, x4, x1, x2)

inst_805:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x3da and fs2 == 0 and fe2 == 0x0e and fm2 == 0x172 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x159 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3bda; op2val:0x3972;
op3val:0x3959; valaddr_reg:x3; val_offset:2415*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 2415*FLEN/8, x4, x1, x2)

inst_806:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x3da and fs2 == 0 and fe2 == 0x0e and fm2 == 0x172 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x159 and fcsr == 0x20 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3bda; op2val:0x3972;
op3val:0x3959; valaddr_reg:x3; val_offset:2418*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:32 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 32, 0, x3, 2418*FLEN/8, x4, x1, x2)

inst_807:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x3da and fs2 == 0 and fe2 == 0x0e and fm2 == 0x172 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x159 and fcsr == 0x40 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3bda; op2val:0x3972;
op3val:0x3959; valaddr_reg:x3; val_offset:2421*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:64 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 64, 0, x3, 2421*FLEN/8, x4, x1, x2)

inst_808:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x3da and fs2 == 0 and fe2 == 0x0e and fm2 == 0x172 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x159 and fcsr == 0x60 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3bda; op2val:0x3972;
op3val:0x3959; valaddr_reg:x3; val_offset:2424*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 96, 0, x3, 2424*FLEN/8, x4, x1, x2)

inst_809:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x3da and fs2 == 0 and fe2 == 0x0e and fm2 == 0x172 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x159 and fcsr == 0x80 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3bda; op2val:0x3972;
op3val:0x3959; valaddr_reg:x3; val_offset:2427*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:128 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 128, 0, x3, 2427*FLEN/8, x4, x1, x2)

inst_810:
// fs1 == 0 and fe1 == 0x0d and fm1 == 0x204 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x130 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x3cd and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3604; op2val:0x3d30;
op3val:0x37cd; valaddr_reg:x3; val_offset:2430*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 2430*FLEN/8, x4, x1, x2)

inst_811:
// fs1 == 0 and fe1 == 0x0d and fm1 == 0x204 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x130 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x3cd and fcsr == 0x20 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3604; op2val:0x3d30;
op3val:0x37cd; valaddr_reg:x3; val_offset:2433*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:32 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 32, 0, x3, 2433*FLEN/8, x4, x1, x2)

inst_812:
// fs1 == 0 and fe1 == 0x0d and fm1 == 0x204 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x130 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x3cd and fcsr == 0x40 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3604; op2val:0x3d30;
op3val:0x37cd; valaddr_reg:x3; val_offset:2436*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:64 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 64, 0, x3, 2436*FLEN/8, x4, x1, x2)

inst_813:
// fs1 == 0 and fe1 == 0x0d and fm1 == 0x204 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x130 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x3cd and fcsr == 0x60 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3604; op2val:0x3d30;
op3val:0x37cd; valaddr_reg:x3; val_offset:2439*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 96, 0, x3, 2439*FLEN/8, x4, x1, x2)

inst_814:
// fs1 == 0 and fe1 == 0x0d and fm1 == 0x204 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x130 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x3cd and fcsr == 0x80 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3604; op2val:0x3d30;
op3val:0x37cd; valaddr_reg:x3; val_offset:2442*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:128 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 128, 0, x3, 2442*FLEN/8, x4, x1, x2)

inst_815:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x37c and fs2 == 0 and fe2 == 0x09 and fm2 == 0x01d and fs3 == 0 and fe3 == 0x08 and fm3 == 0x3ab and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3b7c; op2val:0x241d;
op3val:0x23ab; valaddr_reg:x3; val_offset:2445*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 2445*FLEN/8, x4, x1, x2)

inst_816:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x37c and fs2 == 0 and fe2 == 0x09 and fm2 == 0x01d and fs3 == 0 and fe3 == 0x08 and fm3 == 0x3ab and fcsr == 0x20 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3b7c; op2val:0x241d;
op3val:0x23ab; valaddr_reg:x3; val_offset:2448*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:32 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 32, 0, x3, 2448*FLEN/8, x4, x1, x2)

inst_817:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x37c and fs2 == 0 and fe2 == 0x09 and fm2 == 0x01d and fs3 == 0 and fe3 == 0x08 and fm3 == 0x3ab and fcsr == 0x40 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3b7c; op2val:0x241d;
op3val:0x23ab; valaddr_reg:x3; val_offset:2451*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:64 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 64, 0, x3, 2451*FLEN/8, x4, x1, x2)

inst_818:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x37c and fs2 == 0 and fe2 == 0x09 and fm2 == 0x01d and fs3 == 0 and fe3 == 0x08 and fm3 == 0x3ab and fcsr == 0x60 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3b7c; op2val:0x241d;
op3val:0x23ab; valaddr_reg:x3; val_offset:2454*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 96, 0, x3, 2454*FLEN/8, x4, x1, x2)

inst_819:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x37c and fs2 == 0 and fe2 == 0x09 and fm2 == 0x01d and fs3 == 0 and fe3 == 0x08 and fm3 == 0x3ab and fcsr == 0x80 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3b7c; op2val:0x241d;
op3val:0x23ab; valaddr_reg:x3; val_offset:2457*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:128 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 128, 0, x3, 2457*FLEN/8, x4, x1, x2)

inst_820:
// fs1 == 0 and fe1 == 0x0c and fm1 == 0x2c6 and fs2 == 0 and fe2 == 0x0c and fm2 == 0x04c and fs3 == 0 and fe3 == 0x09 and fm3 == 0x342 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x32c6; op2val:0x304c;
op3val:0x2742; valaddr_reg:x3; val_offset:2460*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 2460*FLEN/8, x4, x1, x2)

inst_821:
// fs1 == 0 and fe1 == 0x0c and fm1 == 0x2c6 and fs2 == 0 and fe2 == 0x0c and fm2 == 0x04c and fs3 == 0 and fe3 == 0x09 and fm3 == 0x342 and fcsr == 0x20 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x32c6; op2val:0x304c;
op3val:0x2742; valaddr_reg:x3; val_offset:2463*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:32 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 32, 0, x3, 2463*FLEN/8, x4, x1, x2)

inst_822:
// fs1 == 0 and fe1 == 0x0c and fm1 == 0x2c6 and fs2 == 0 and fe2 == 0x0c and fm2 == 0x04c and fs3 == 0 and fe3 == 0x09 and fm3 == 0x342 and fcsr == 0x40 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x32c6; op2val:0x304c;
op3val:0x2742; valaddr_reg:x3; val_offset:2466*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:64 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 64, 0, x3, 2466*FLEN/8, x4, x1, x2)

inst_823:
// fs1 == 0 and fe1 == 0x0c and fm1 == 0x2c6 and fs2 == 0 and fe2 == 0x0c and fm2 == 0x04c and fs3 == 0 and fe3 == 0x09 and fm3 == 0x342 and fcsr == 0x60 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x32c6; op2val:0x304c;
op3val:0x2742; valaddr_reg:x3; val_offset:2469*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 96, 0, x3, 2469*FLEN/8, x4, x1, x2)

inst_824:
// fs1 == 0 and fe1 == 0x0c and fm1 == 0x2c6 and fs2 == 0 and fe2 == 0x0c and fm2 == 0x04c and fs3 == 0 and fe3 == 0x09 and fm3 == 0x342 and fcsr == 0x80 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x32c6; op2val:0x304c;
op3val:0x2742; valaddr_reg:x3; val_offset:2472*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:128 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 128, 0, x3, 2472*FLEN/8, x4, x1, x2)

inst_825:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x329 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x290 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x1e0 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3b29; op2val:0x3a90;
op3val:0x39e0; valaddr_reg:x3; val_offset:2475*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 2475*FLEN/8, x4, x1, x2)

inst_826:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x329 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x290 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x1e0 and fcsr == 0x20 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3b29; op2val:0x3a90;
op3val:0x39e0; valaddr_reg:x3; val_offset:2478*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:32 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 32, 0, x3, 2478*FLEN/8, x4, x1, x2)

inst_827:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x329 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x290 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x1e0 and fcsr == 0x40 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3b29; op2val:0x3a90;
op3val:0x39e0; valaddr_reg:x3; val_offset:2481*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:64 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 64, 0, x3, 2481*FLEN/8, x4, x1, x2)

inst_828:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x329 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x290 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x1e0 and fcsr == 0x60 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3b29; op2val:0x3a90;
op3val:0x39e0; valaddr_reg:x3; val_offset:2484*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 96, 0, x3, 2484*FLEN/8, x4, x1, x2)

inst_829:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x329 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x290 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x1e0 and fcsr == 0x80 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3b29; op2val:0x3a90;
op3val:0x39e0; valaddr_reg:x3; val_offset:2487*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:128 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 128, 0, x3, 2487*FLEN/8, x4, x1, x2)

inst_830:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x3ae and fs2 == 0 and fe2 == 0x0c and fm2 == 0x35e and fs3 == 0 and fe3 == 0x0c and fm3 == 0x312 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3bae; op2val:0x335e;
op3val:0x3312; valaddr_reg:x3; val_offset:2490*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 2490*FLEN/8, x4, x1, x2)

inst_831:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x3ae and fs2 == 0 and fe2 == 0x0c and fm2 == 0x35e and fs3 == 0 and fe3 == 0x0c and fm3 == 0x312 and fcsr == 0x20 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3bae; op2val:0x335e;
op3val:0x3312; valaddr_reg:x3; val_offset:2493*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:32 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 32, 0, x3, 2493*FLEN/8, x4, x1, x2)

inst_832:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x3ae and fs2 == 0 and fe2 == 0x0c and fm2 == 0x35e and fs3 == 0 and fe3 == 0x0c and fm3 == 0x312 and fcsr == 0x40 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3bae; op2val:0x335e;
op3val:0x3312; valaddr_reg:x3; val_offset:2496*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:64 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 64, 0, x3, 2496*FLEN/8, x4, x1, x2)

inst_833:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x3ae and fs2 == 0 and fe2 == 0x0c and fm2 == 0x35e and fs3 == 0 and fe3 == 0x0c and fm3 == 0x312 and fcsr == 0x60 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3bae; op2val:0x335e;
op3val:0x3312; valaddr_reg:x3; val_offset:2499*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 96, 0, x3, 2499*FLEN/8, x4, x1, x2)

inst_834:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x3ae and fs2 == 0 and fe2 == 0x0c and fm2 == 0x35e and fs3 == 0 and fe3 == 0x0c and fm3 == 0x312 and fcsr == 0x80 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3bae; op2val:0x335e;
op3val:0x3312; valaddr_reg:x3; val_offset:2502*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:128 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 128, 0, x3, 2502*FLEN/8, x4, x1, x2)

inst_835:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x1d6 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x0c5 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x2f6 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x39d6; op2val:0x3cc5;
op3val:0x3af6; valaddr_reg:x3; val_offset:2505*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 2505*FLEN/8, x4, x1, x2)

inst_836:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x1d6 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x0c5 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x2f6 and fcsr == 0x20 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x39d6; op2val:0x3cc5;
op3val:0x3af6; valaddr_reg:x3; val_offset:2508*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:32 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 32, 0, x3, 2508*FLEN/8, x4, x1, x2)

inst_837:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x1d6 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x0c5 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x2f6 and fcsr == 0x40 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x39d6; op2val:0x3cc5;
op3val:0x3af6; valaddr_reg:x3; val_offset:2511*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:64 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 64, 0, x3, 2511*FLEN/8, x4, x1, x2)

inst_838:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x1d6 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x0c5 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x2f6 and fcsr == 0x60 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x39d6; op2val:0x3cc5;
op3val:0x3af6; valaddr_reg:x3; val_offset:2514*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 96, 0, x3, 2514*FLEN/8, x4, x1, x2)

inst_839:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x1d6 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x0c5 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x2f6 and fcsr == 0x80 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x39d6; op2val:0x3cc5;
op3val:0x3af6; valaddr_reg:x3; val_offset:2517*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:128 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 128, 0, x3, 2517*FLEN/8, x4, x1, x2)

inst_840:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x09f and fs2 == 0 and fe2 == 0x0c and fm2 == 0x0e9 and fs3 == 0 and fe3 == 0x0b and fm3 == 0x1ac and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x389f; op2val:0x30e9;
op3val:0x2dac; valaddr_reg:x3; val_offset:2520*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 2520*FLEN/8, x4, x1, x2)

inst_841:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x09f and fs2 == 0 and fe2 == 0x0c and fm2 == 0x0e9 and fs3 == 0 and fe3 == 0x0b and fm3 == 0x1ac and fcsr == 0x20 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x389f; op2val:0x30e9;
op3val:0x2dac; valaddr_reg:x3; val_offset:2523*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:32 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 32, 0, x3, 2523*FLEN/8, x4, x1, x2)

inst_842:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x09f and fs2 == 0 and fe2 == 0x0c and fm2 == 0x0e9 and fs3 == 0 and fe3 == 0x0b and fm3 == 0x1ac and fcsr == 0x40 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x389f; op2val:0x30e9;
op3val:0x2dac; valaddr_reg:x3; val_offset:2526*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:64 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 64, 0, x3, 2526*FLEN/8, x4, x1, x2)

inst_843:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x09f and fs2 == 0 and fe2 == 0x0c and fm2 == 0x0e9 and fs3 == 0 and fe3 == 0x0b and fm3 == 0x1ac and fcsr == 0x60 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x389f; op2val:0x30e9;
op3val:0x2dac; valaddr_reg:x3; val_offset:2529*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 96, 0, x3, 2529*FLEN/8, x4, x1, x2)

inst_844:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x09f and fs2 == 0 and fe2 == 0x0c and fm2 == 0x0e9 and fs3 == 0 and fe3 == 0x0b and fm3 == 0x1ac and fcsr == 0x80 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x389f; op2val:0x30e9;
op3val:0x2dac; valaddr_reg:x3; val_offset:2532*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:128 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 128, 0, x3, 2532*FLEN/8, x4, x1, x2)

inst_845:
// fs1 == 0 and fe1 == 0x0c and fm1 == 0x1cb and fs2 == 0 and fe2 == 0x11 and fm2 == 0x018 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x1ee and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x31cb; op2val:0x4418;
op3val:0x39ee; valaddr_reg:x3; val_offset:2535*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 2535*FLEN/8, x4, x1, x2)

inst_846:
// fs1 == 0 and fe1 == 0x0c and fm1 == 0x1cb and fs2 == 0 and fe2 == 0x11 and fm2 == 0x018 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x1ee and fcsr == 0x20 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x31cb; op2val:0x4418;
op3val:0x39ee; valaddr_reg:x3; val_offset:2538*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:32 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 32, 0, x3, 2538*FLEN/8, x4, x1, x2)

inst_847:
// fs1 == 0 and fe1 == 0x0c and fm1 == 0x1cb and fs2 == 0 and fe2 == 0x11 and fm2 == 0x018 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x1ee and fcsr == 0x40 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x31cb; op2val:0x4418;
op3val:0x39ee; valaddr_reg:x3; val_offset:2541*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:64 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 64, 0, x3, 2541*FLEN/8, x4, x1, x2)

inst_848:
// fs1 == 0 and fe1 == 0x0c and fm1 == 0x1cb and fs2 == 0 and fe2 == 0x11 and fm2 == 0x018 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x1ee and fcsr == 0x60 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x31cb; op2val:0x4418;
op3val:0x39ee; valaddr_reg:x3; val_offset:2544*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 96, 0, x3, 2544*FLEN/8, x4, x1, x2)

inst_849:
// fs1 == 0 and fe1 == 0x0c and fm1 == 0x1cb and fs2 == 0 and fe2 == 0x11 and fm2 == 0x018 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x1ee and fcsr == 0x80 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x31cb; op2val:0x4418;
op3val:0x39ee; valaddr_reg:x3; val_offset:2547*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:128 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 128, 0, x3, 2547*FLEN/8, x4, x1, x2)

inst_850:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x2ce and fs2 == 0 and fe2 == 0x0b and fm2 == 0x217 and fs3 == 0 and fe3 == 0x0b and fm3 == 0x12d and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3ace; op2val:0x2e17;
op3val:0x2d2d; valaddr_reg:x3; val_offset:2550*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 2550*FLEN/8, x4, x1, x2)

inst_851:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x2ce and fs2 == 0 and fe2 == 0x0b and fm2 == 0x217 and fs3 == 0 and fe3 == 0x0b and fm3 == 0x12d and fcsr == 0x20 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3ace; op2val:0x2e17;
op3val:0x2d2d; valaddr_reg:x3; val_offset:2553*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:32 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 32, 0, x3, 2553*FLEN/8, x4, x1, x2)

inst_852:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x2ce and fs2 == 0 and fe2 == 0x0b and fm2 == 0x217 and fs3 == 0 and fe3 == 0x0b and fm3 == 0x12d and fcsr == 0x40 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3ace; op2val:0x2e17;
op3val:0x2d2d; valaddr_reg:x3; val_offset:2556*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:64 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 64, 0, x3, 2556*FLEN/8, x4, x1, x2)

inst_853:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x2ce and fs2 == 0 and fe2 == 0x0b and fm2 == 0x217 and fs3 == 0 and fe3 == 0x0b and fm3 == 0x12d and fcsr == 0x60 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3ace; op2val:0x2e17;
op3val:0x2d2d; valaddr_reg:x3; val_offset:2559*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 96, 0, x3, 2559*FLEN/8, x4, x1, x2)

inst_854:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x2ce and fs2 == 0 and fe2 == 0x0b and fm2 == 0x217 and fs3 == 0 and fe3 == 0x0b and fm3 == 0x12d and fcsr == 0x80 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3ace; op2val:0x2e17;
op3val:0x2d2d; valaddr_reg:x3; val_offset:2562*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:128 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 128, 0, x3, 2562*FLEN/8, x4, x1, x2)

inst_855:
// fs1 == 0 and fe1 == 0x0d and fm1 == 0x2de and fs2 == 0 and fe2 == 0x0e and fm2 == 0x195 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x0cb and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x36de; op2val:0x3995;
op3val:0x34cb; valaddr_reg:x3; val_offset:2565*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 2565*FLEN/8, x4, x1, x2)

inst_856:
// fs1 == 0 and fe1 == 0x0d and fm1 == 0x2de and fs2 == 0 and fe2 == 0x0e and fm2 == 0x195 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x0cb and fcsr == 0x20 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x36de; op2val:0x3995;
op3val:0x34cb; valaddr_reg:x3; val_offset:2568*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:32 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 32, 0, x3, 2568*FLEN/8, x4, x1, x2)

inst_857:
// fs1 == 0 and fe1 == 0x0d and fm1 == 0x2de and fs2 == 0 and fe2 == 0x0e and fm2 == 0x195 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x0cb and fcsr == 0x40 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x36de; op2val:0x3995;
op3val:0x34cb; valaddr_reg:x3; val_offset:2571*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:64 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 64, 0, x3, 2571*FLEN/8, x4, x1, x2)

inst_858:
// fs1 == 0 and fe1 == 0x0d and fm1 == 0x2de and fs2 == 0 and fe2 == 0x0e and fm2 == 0x195 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x0cb and fcsr == 0x60 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x36de; op2val:0x3995;
op3val:0x34cb; valaddr_reg:x3; val_offset:2574*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 96, 0, x3, 2574*FLEN/8, x4, x1, x2)

inst_859:
// fs1 == 0 and fe1 == 0x0d and fm1 == 0x2de and fs2 == 0 and fe2 == 0x0e and fm2 == 0x195 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x0cb and fcsr == 0x80 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x36de; op2val:0x3995;
op3val:0x34cb; valaddr_reg:x3; val_offset:2577*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:128 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 128, 0, x3, 2577*FLEN/8, x4, x1, x2)

inst_860:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x348 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x023 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x38a and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3b48; op2val:0x3c23;
op3val:0x3b8a; valaddr_reg:x3; val_offset:2580*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 2580*FLEN/8, x4, x1, x2)

inst_861:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x348 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x023 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x38a and fcsr == 0x20 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3b48; op2val:0x3c23;
op3val:0x3b8a; valaddr_reg:x3; val_offset:2583*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:32 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 32, 0, x3, 2583*FLEN/8, x4, x1, x2)

inst_862:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x348 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x023 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x38a and fcsr == 0x40 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3b48; op2val:0x3c23;
op3val:0x3b8a; valaddr_reg:x3; val_offset:2586*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:64 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 64, 0, x3, 2586*FLEN/8, x4, x1, x2)

inst_863:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x348 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x023 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x38a and fcsr == 0x60 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3b48; op2val:0x3c23;
op3val:0x3b8a; valaddr_reg:x3; val_offset:2589*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 96, 0, x3, 2589*FLEN/8, x4, x1, x2)

inst_864:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x348 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x023 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x38a and fcsr == 0x80 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3b48; op2val:0x3c23;
op3val:0x3b8a; valaddr_reg:x3; val_offset:2592*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:128 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 128, 0, x3, 2592*FLEN/8, x4, x1, x2)

inst_865:
// fs1 == 0 and fe1 == 0x0d and fm1 == 0x0fd and fs2 == 0 and fe2 == 0x0f and fm2 == 0x35f and fs3 == 0 and fe3 == 0x0e and fm3 == 0x099 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x34fd; op2val:0x3f5f;
op3val:0x3899; valaddr_reg:x3; val_offset:2595*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 2595*FLEN/8, x4, x1, x2)

inst_866:
// fs1 == 0 and fe1 == 0x0d and fm1 == 0x0fd and fs2 == 0 and fe2 == 0x0f and fm2 == 0x35f and fs3 == 0 and fe3 == 0x0e and fm3 == 0x099 and fcsr == 0x20 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x34fd; op2val:0x3f5f;
op3val:0x3899; valaddr_reg:x3; val_offset:2598*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:32 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 32, 0, x3, 2598*FLEN/8, x4, x1, x2)

inst_867:
// fs1 == 0 and fe1 == 0x0d and fm1 == 0x0fd and fs2 == 0 and fe2 == 0x0f and fm2 == 0x35f and fs3 == 0 and fe3 == 0x0e and fm3 == 0x099 and fcsr == 0x40 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x34fd; op2val:0x3f5f;
op3val:0x3899; valaddr_reg:x3; val_offset:2601*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:64 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 64, 0, x3, 2601*FLEN/8, x4, x1, x2)

inst_868:
// fs1 == 0 and fe1 == 0x0d and fm1 == 0x0fd and fs2 == 0 and fe2 == 0x0f and fm2 == 0x35f and fs3 == 0 and fe3 == 0x0e and fm3 == 0x099 and fcsr == 0x60 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x34fd; op2val:0x3f5f;
op3val:0x3899; valaddr_reg:x3; val_offset:2604*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 96, 0, x3, 2604*FLEN/8, x4, x1, x2)

inst_869:
// fs1 == 0 and fe1 == 0x0d and fm1 == 0x0fd and fs2 == 0 and fe2 == 0x0f and fm2 == 0x35f and fs3 == 0 and fe3 == 0x0e and fm3 == 0x099 and fcsr == 0x80 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x34fd; op2val:0x3f5f;
op3val:0x3899; valaddr_reg:x3; val_offset:2607*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:128 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 128, 0, x3, 2607*FLEN/8, x4, x1, x2)

inst_870:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x36b and fs2 == 0 and fe2 == 0x0b and fm2 == 0x043 and fs3 == 0 and fe3 == 0x0a and fm3 == 0x3e6 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3b6b; op2val:0x2c43;
op3val:0x2be6; valaddr_reg:x3; val_offset:2610*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 2610*FLEN/8, x4, x1, x2)

inst_871:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x36b and fs2 == 0 and fe2 == 0x0b and fm2 == 0x043 and fs3 == 0 and fe3 == 0x0a and fm3 == 0x3e6 and fcsr == 0x20 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3b6b; op2val:0x2c43;
op3val:0x2be6; valaddr_reg:x3; val_offset:2613*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:32 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 32, 0, x3, 2613*FLEN/8, x4, x1, x2)

inst_872:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x36b and fs2 == 0 and fe2 == 0x0b and fm2 == 0x043 and fs3 == 0 and fe3 == 0x0a and fm3 == 0x3e6 and fcsr == 0x40 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3b6b; op2val:0x2c43;
op3val:0x2be6; valaddr_reg:x3; val_offset:2616*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:64 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 64, 0, x3, 2616*FLEN/8, x4, x1, x2)

inst_873:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x36b and fs2 == 0 and fe2 == 0x0b and fm2 == 0x043 and fs3 == 0 and fe3 == 0x0a and fm3 == 0x3e6 and fcsr == 0x60 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3b6b; op2val:0x2c43;
op3val:0x2be6; valaddr_reg:x3; val_offset:2619*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 96, 0, x3, 2619*FLEN/8, x4, x1, x2)

inst_874:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x36b and fs2 == 0 and fe2 == 0x0b and fm2 == 0x043 and fs3 == 0 and fe3 == 0x0a and fm3 == 0x3e6 and fcsr == 0x80 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3b6b; op2val:0x2c43;
op3val:0x2be6; valaddr_reg:x3; val_offset:2622*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:128 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 128, 0, x3, 2622*FLEN/8, x4, x1, x2)

inst_875:
// fs1 == 0 and fe1 == 0x0d and fm1 == 0x1d9 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x057 and fs3 == 0 and fe3 == 0x0c and fm3 == 0x259 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x35d9; op2val:0x3857;
op3val:0x3259; valaddr_reg:x3; val_offset:2625*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 2625*FLEN/8, x4, x1, x2)

inst_876:
// fs1 == 0 and fe1 == 0x0d and fm1 == 0x1d9 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x057 and fs3 == 0 and fe3 == 0x0c and fm3 == 0x259 and fcsr == 0x20 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x35d9; op2val:0x3857;
op3val:0x3259; valaddr_reg:x3; val_offset:2628*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:32 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 32, 0, x3, 2628*FLEN/8, x4, x1, x2)

inst_877:
// fs1 == 0 and fe1 == 0x0d and fm1 == 0x1d9 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x057 and fs3 == 0 and fe3 == 0x0c and fm3 == 0x259 and fcsr == 0x40 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x35d9; op2val:0x3857;
op3val:0x3259; valaddr_reg:x3; val_offset:2631*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:64 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 64, 0, x3, 2631*FLEN/8, x4, x1, x2)

inst_878:
// fs1 == 0 and fe1 == 0x0d and fm1 == 0x1d9 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x057 and fs3 == 0 and fe3 == 0x0c and fm3 == 0x259 and fcsr == 0x60 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x35d9; op2val:0x3857;
op3val:0x3259; valaddr_reg:x3; val_offset:2634*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 96, 0, x3, 2634*FLEN/8, x4, x1, x2)

inst_879:
// fs1 == 0 and fe1 == 0x0d and fm1 == 0x1d9 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x057 and fs3 == 0 and fe3 == 0x0c and fm3 == 0x259 and fcsr == 0x80 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x35d9; op2val:0x3857;
op3val:0x3259; valaddr_reg:x3; val_offset:2637*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:128 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 128, 0, x3, 2637*FLEN/8, x4, x1, x2)

inst_880:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x354 and fs2 == 0 and fe2 == 0x0c and fm2 == 0x106 and fs3 == 0 and fe3 == 0x0c and fm3 == 0x09a and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3b54; op2val:0x3106;
op3val:0x309a; valaddr_reg:x3; val_offset:2640*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 2640*FLEN/8, x4, x1, x2)

inst_881:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x354 and fs2 == 0 and fe2 == 0x0c and fm2 == 0x106 and fs3 == 0 and fe3 == 0x0c and fm3 == 0x09a and fcsr == 0x20 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3b54; op2val:0x3106;
op3val:0x309a; valaddr_reg:x3; val_offset:2643*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:32 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 32, 0, x3, 2643*FLEN/8, x4, x1, x2)

inst_882:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x354 and fs2 == 0 and fe2 == 0x0c and fm2 == 0x106 and fs3 == 0 and fe3 == 0x0c and fm3 == 0x09a and fcsr == 0x40 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3b54; op2val:0x3106;
op3val:0x309a; valaddr_reg:x3; val_offset:2646*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:64 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 64, 0, x3, 2646*FLEN/8, x4, x1, x2)

inst_883:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x354 and fs2 == 0 and fe2 == 0x0c and fm2 == 0x106 and fs3 == 0 and fe3 == 0x0c and fm3 == 0x09a and fcsr == 0x60 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3b54; op2val:0x3106;
op3val:0x309a; valaddr_reg:x3; val_offset:2649*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 96, 0, x3, 2649*FLEN/8, x4, x1, x2)

inst_884:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x354 and fs2 == 0 and fe2 == 0x0c and fm2 == 0x106 and fs3 == 0 and fe3 == 0x0c and fm3 == 0x09a and fcsr == 0x80 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3b54; op2val:0x3106;
op3val:0x309a; valaddr_reg:x3; val_offset:2652*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:128 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 128, 0, x3, 2652*FLEN/8, x4, x1, x2)

inst_885:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x377 and fs2 == 0 and fe2 == 0x0c and fm2 == 0x0b5 and fs3 == 0 and fe3 == 0x0c and fm3 == 0x064 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3b77; op2val:0x30b5;
op3val:0x3064; valaddr_reg:x3; val_offset:2655*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 2655*FLEN/8, x4, x1, x2)

inst_886:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x377 and fs2 == 0 and fe2 == 0x0c and fm2 == 0x0b5 and fs3 == 0 and fe3 == 0x0c and fm3 == 0x064 and fcsr == 0x20 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3b77; op2val:0x30b5;
op3val:0x3064; valaddr_reg:x3; val_offset:2658*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:32 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 32, 0, x3, 2658*FLEN/8, x4, x1, x2)

inst_887:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x377 and fs2 == 0 and fe2 == 0x0c and fm2 == 0x0b5 and fs3 == 0 and fe3 == 0x0c and fm3 == 0x064 and fcsr == 0x40 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3b77; op2val:0x30b5;
op3val:0x3064; valaddr_reg:x3; val_offset:2661*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:64 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 64, 0, x3, 2661*FLEN/8, x4, x1, x2)

inst_888:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x377 and fs2 == 0 and fe2 == 0x0c and fm2 == 0x0b5 and fs3 == 0 and fe3 == 0x0c and fm3 == 0x064 and fcsr == 0x60 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3b77; op2val:0x30b5;
op3val:0x3064; valaddr_reg:x3; val_offset:2664*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 96, 0, x3, 2664*FLEN/8, x4, x1, x2)

inst_889:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x377 and fs2 == 0 and fe2 == 0x0c and fm2 == 0x0b5 and fs3 == 0 and fe3 == 0x0c and fm3 == 0x064 and fcsr == 0x80 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3b77; op2val:0x30b5;
op3val:0x3064; valaddr_reg:x3; val_offset:2667*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:128 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 128, 0, x3, 2667*FLEN/8, x4, x1, x2)

inst_890:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x05e and fs2 == 0 and fe2 == 0x0f and fm2 == 0x0d6 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x149 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x385e; op2val:0x3cd6;
op3val:0x3949; valaddr_reg:x3; val_offset:2670*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 2670*FLEN/8, x4, x1, x2)

inst_891:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x05e and fs2 == 0 and fe2 == 0x0f and fm2 == 0x0d6 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x149 and fcsr == 0x20 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x385e; op2val:0x3cd6;
op3val:0x3949; valaddr_reg:x3; val_offset:2673*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:32 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 32, 0, x3, 2673*FLEN/8, x4, x1, x2)

inst_892:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x05e and fs2 == 0 and fe2 == 0x0f and fm2 == 0x0d6 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x149 and fcsr == 0x40 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x385e; op2val:0x3cd6;
op3val:0x3949; valaddr_reg:x3; val_offset:2676*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:64 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 64, 0, x3, 2676*FLEN/8, x4, x1, x2)

inst_893:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x05e and fs2 == 0 and fe2 == 0x0f and fm2 == 0x0d6 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x149 and fcsr == 0x60 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x385e; op2val:0x3cd6;
op3val:0x3949; valaddr_reg:x3; val_offset:2679*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 96, 0, x3, 2679*FLEN/8, x4, x1, x2)

inst_894:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x05e and fs2 == 0 and fe2 == 0x0f and fm2 == 0x0d6 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x149 and fcsr == 0x80 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x385e; op2val:0x3cd6;
op3val:0x3949; valaddr_reg:x3; val_offset:2682*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:128 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 128, 0, x3, 2682*FLEN/8, x4, x1, x2)

inst_895:
// fs1 == 0 and fe1 == 0x0d and fm1 == 0x326 and fs2 == 0 and fe2 == 0x0c and fm2 == 0x142 and fs3 == 0 and fe3 == 0x0b and fm3 == 0x0b2 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3726; op2val:0x3142;
op3val:0x2cb2; valaddr_reg:x3; val_offset:2685*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 2685*FLEN/8, x4, x1, x2)
RVTEST_SIGBASE(x1,signature_x1_8)

inst_896:
// fs1 == 0 and fe1 == 0x0d and fm1 == 0x326 and fs2 == 0 and fe2 == 0x0c and fm2 == 0x142 and fs3 == 0 and fe3 == 0x0b and fm3 == 0x0b2 and fcsr == 0x20 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3726; op2val:0x3142;
op3val:0x2cb2; valaddr_reg:x3; val_offset:2688*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:32 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 32, 0, x3, 2688*FLEN/8, x4, x1, x2)

inst_897:
// fs1 == 0 and fe1 == 0x0d and fm1 == 0x326 and fs2 == 0 and fe2 == 0x0c and fm2 == 0x142 and fs3 == 0 and fe3 == 0x0b and fm3 == 0x0b2 and fcsr == 0x40 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3726; op2val:0x3142;
op3val:0x2cb2; valaddr_reg:x3; val_offset:2691*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:64 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 64, 0, x3, 2691*FLEN/8, x4, x1, x2)

inst_898:
// fs1 == 0 and fe1 == 0x0d and fm1 == 0x326 and fs2 == 0 and fe2 == 0x0c and fm2 == 0x142 and fs3 == 0 and fe3 == 0x0b and fm3 == 0x0b2 and fcsr == 0x60 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3726; op2val:0x3142;
op3val:0x2cb2; valaddr_reg:x3; val_offset:2694*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 96, 0, x3, 2694*FLEN/8, x4, x1, x2)

inst_899:
// fs1 == 0 and fe1 == 0x0d and fm1 == 0x326 and fs2 == 0 and fe2 == 0x0c and fm2 == 0x142 and fs3 == 0 and fe3 == 0x0b and fm3 == 0x0b2 and fcsr == 0x80 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3726; op2val:0x3142;
op3val:0x2cb2; valaddr_reg:x3; val_offset:2697*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:128 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 128, 0, x3, 2697*FLEN/8, x4, x1, x2)

inst_900:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x1db and fs2 == 0 and fe2 == 0x0f and fm2 == 0x0c1 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x2f7 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x39db; op2val:0x3cc1;
op3val:0x3af7; valaddr_reg:x3; val_offset:2700*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 2700*FLEN/8, x4, x1, x2)

inst_901:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x1db and fs2 == 0 and fe2 == 0x0f and fm2 == 0x0c1 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x2f7 and fcsr == 0x20 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x39db; op2val:0x3cc1;
op3val:0x3af7; valaddr_reg:x3; val_offset:2703*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:32 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 32, 0, x3, 2703*FLEN/8, x4, x1, x2)

inst_902:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x1db and fs2 == 0 and fe2 == 0x0f and fm2 == 0x0c1 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x2f7 and fcsr == 0x40 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x39db; op2val:0x3cc1;
op3val:0x3af7; valaddr_reg:x3; val_offset:2706*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:64 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 64, 0, x3, 2706*FLEN/8, x4, x1, x2)

inst_903:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x1db and fs2 == 0 and fe2 == 0x0f and fm2 == 0x0c1 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x2f7 and fcsr == 0x60 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x39db; op2val:0x3cc1;
op3val:0x3af7; valaddr_reg:x3; val_offset:2709*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 96, 0, x3, 2709*FLEN/8, x4, x1, x2)

inst_904:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x1db and fs2 == 0 and fe2 == 0x0f and fm2 == 0x0c1 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x2f7 and fcsr == 0x80 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x39db; op2val:0x3cc1;
op3val:0x3af7; valaddr_reg:x3; val_offset:2712*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:128 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 128, 0, x3, 2712*FLEN/8, x4, x1, x2)

inst_905:
// fs1 == 0 and fe1 == 0x0d and fm1 == 0x391 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x270 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x217 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3791; op2val:0x3e70;
op3val:0x3a17; valaddr_reg:x3; val_offset:2715*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 2715*FLEN/8, x4, x1, x2)

inst_906:
// fs1 == 0 and fe1 == 0x0d and fm1 == 0x391 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x270 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x217 and fcsr == 0x20 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3791; op2val:0x3e70;
op3val:0x3a17; valaddr_reg:x3; val_offset:2718*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:32 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 32, 0, x3, 2718*FLEN/8, x4, x1, x2)

inst_907:
// fs1 == 0 and fe1 == 0x0d and fm1 == 0x391 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x270 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x217 and fcsr == 0x40 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3791; op2val:0x3e70;
op3val:0x3a17; valaddr_reg:x3; val_offset:2721*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:64 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 64, 0, x3, 2721*FLEN/8, x4, x1, x2)

inst_908:
// fs1 == 0 and fe1 == 0x0d and fm1 == 0x391 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x270 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x217 and fcsr == 0x60 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3791; op2val:0x3e70;
op3val:0x3a17; valaddr_reg:x3; val_offset:2724*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 96, 0, x3, 2724*FLEN/8, x4, x1, x2)

inst_909:
// fs1 == 0 and fe1 == 0x0d and fm1 == 0x391 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x270 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x217 and fcsr == 0x80 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3791; op2val:0x3e70;
op3val:0x3a17; valaddr_reg:x3; val_offset:2727*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:128 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 128, 0, x3, 2727*FLEN/8, x4, x1, x2)

inst_910:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x31f and fs2 == 0 and fe2 == 0x0e and fm2 == 0x388 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x2b5 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3b1f; op2val:0x3b88;
op3val:0x3ab5; valaddr_reg:x3; val_offset:2730*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 2730*FLEN/8, x4, x1, x2)

inst_911:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x31f and fs2 == 0 and fe2 == 0x0e and fm2 == 0x388 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x2b5 and fcsr == 0x20 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3b1f; op2val:0x3b88;
op3val:0x3ab5; valaddr_reg:x3; val_offset:2733*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:32 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 32, 0, x3, 2733*FLEN/8, x4, x1, x2)

inst_912:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x31f and fs2 == 0 and fe2 == 0x0e and fm2 == 0x388 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x2b5 and fcsr == 0x40 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3b1f; op2val:0x3b88;
op3val:0x3ab5; valaddr_reg:x3; val_offset:2736*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:64 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 64, 0, x3, 2736*FLEN/8, x4, x1, x2)

inst_913:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x31f and fs2 == 0 and fe2 == 0x0e and fm2 == 0x388 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x2b5 and fcsr == 0x60 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3b1f; op2val:0x3b88;
op3val:0x3ab5; valaddr_reg:x3; val_offset:2739*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 96, 0, x3, 2739*FLEN/8, x4, x1, x2)

inst_914:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x31f and fs2 == 0 and fe2 == 0x0e and fm2 == 0x388 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x2b5 and fcsr == 0x80 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3b1f; op2val:0x3b88;
op3val:0x3ab5; valaddr_reg:x3; val_offset:2742*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:128 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 128, 0, x3, 2742*FLEN/8, x4, x1, x2)

inst_915:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x398 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x2b9 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x262 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3b98; op2val:0x3ab9;
op3val:0x3a62; valaddr_reg:x3; val_offset:2745*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 2745*FLEN/8, x4, x1, x2)

inst_916:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x398 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x2b9 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x262 and fcsr == 0x20 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3b98; op2val:0x3ab9;
op3val:0x3a62; valaddr_reg:x3; val_offset:2748*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:32 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 32, 0, x3, 2748*FLEN/8, x4, x1, x2)

inst_917:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x398 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x2b9 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x262 and fcsr == 0x40 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3b98; op2val:0x3ab9;
op3val:0x3a62; valaddr_reg:x3; val_offset:2751*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:64 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 64, 0, x3, 2751*FLEN/8, x4, x1, x2)

inst_918:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x398 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x2b9 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x262 and fcsr == 0x60 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3b98; op2val:0x3ab9;
op3val:0x3a62; valaddr_reg:x3; val_offset:2754*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 96, 0, x3, 2754*FLEN/8, x4, x1, x2)

inst_919:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x398 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x2b9 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x262 and fcsr == 0x80 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3b98; op2val:0x3ab9;
op3val:0x3a62; valaddr_reg:x3; val_offset:2757*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:128 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 128, 0, x3, 2757*FLEN/8, x4, x1, x2)

inst_920:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x181 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x00a and fs3 == 0 and fe3 == 0x0e and fm3 == 0x18f and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3981; op2val:0x3c0a;
op3val:0x398f; valaddr_reg:x3; val_offset:2760*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 2760*FLEN/8, x4, x1, x2)

inst_921:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x181 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x00a and fs3 == 0 and fe3 == 0x0e and fm3 == 0x18f and fcsr == 0x20 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3981; op2val:0x3c0a;
op3val:0x398f; valaddr_reg:x3; val_offset:2763*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:32 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 32, 0, x3, 2763*FLEN/8, x4, x1, x2)

inst_922:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x181 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x00a and fs3 == 0 and fe3 == 0x0e and fm3 == 0x18f and fcsr == 0x40 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3981; op2val:0x3c0a;
op3val:0x398f; valaddr_reg:x3; val_offset:2766*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:64 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 64, 0, x3, 2766*FLEN/8, x4, x1, x2)

inst_923:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x181 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x00a and fs3 == 0 and fe3 == 0x0e and fm3 == 0x18f and fcsr == 0x60 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3981; op2val:0x3c0a;
op3val:0x398f; valaddr_reg:x3; val_offset:2769*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 96, 0, x3, 2769*FLEN/8, x4, x1, x2)

inst_924:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x181 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x00a and fs3 == 0 and fe3 == 0x0e and fm3 == 0x18f and fcsr == 0x80 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3981; op2val:0x3c0a;
op3val:0x398f; valaddr_reg:x3; val_offset:2772*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:128 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 128, 0, x3, 2772*FLEN/8, x4, x1, x2)

inst_925:
// fs1 == 0 and fe1 == 0x0c and fm1 == 0x3b2 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x1e7 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x1ae and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x33b2; op2val:0x41e7;
op3val:0x39ae; valaddr_reg:x3; val_offset:2775*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 2775*FLEN/8, x4, x1, x2)

inst_926:
// fs1 == 0 and fe1 == 0x0c and fm1 == 0x3b2 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x1e7 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x1ae and fcsr == 0x20 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x33b2; op2val:0x41e7;
op3val:0x39ae; valaddr_reg:x3; val_offset:2778*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:32 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 32, 0, x3, 2778*FLEN/8, x4, x1, x2)

inst_927:
// fs1 == 0 and fe1 == 0x0c and fm1 == 0x3b2 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x1e7 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x1ae and fcsr == 0x40 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x33b2; op2val:0x41e7;
op3val:0x39ae; valaddr_reg:x3; val_offset:2781*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:64 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 64, 0, x3, 2781*FLEN/8, x4, x1, x2)

inst_928:
// fs1 == 0 and fe1 == 0x0c and fm1 == 0x3b2 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x1e7 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x1ae and fcsr == 0x60 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x33b2; op2val:0x41e7;
op3val:0x39ae; valaddr_reg:x3; val_offset:2784*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 96, 0, x3, 2784*FLEN/8, x4, x1, x2)

inst_929:
// fs1 == 0 and fe1 == 0x0c and fm1 == 0x3b2 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x1e7 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x1ae and fcsr == 0x80 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x33b2; op2val:0x41e7;
op3val:0x39ae; valaddr_reg:x3; val_offset:2787*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:128 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 128, 0, x3, 2787*FLEN/8, x4, x1, x2)

inst_930:
// fs1 == 0 and fe1 == 0x0d and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x0f and fm2 == 0x294 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x293 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x37ff; op2val:0x3e94;
op3val:0x3a93; valaddr_reg:x3; val_offset:2790*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 2790*FLEN/8, x4, x1, x2)

inst_931:
// fs1 == 0 and fe1 == 0x0d and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x0f and fm2 == 0x294 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x293 and fcsr == 0x20 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x37ff; op2val:0x3e94;
op3val:0x3a93; valaddr_reg:x3; val_offset:2793*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:32 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 32, 0, x3, 2793*FLEN/8, x4, x1, x2)

inst_932:
// fs1 == 0 and fe1 == 0x0d and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x0f and fm2 == 0x294 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x293 and fcsr == 0x40 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x37ff; op2val:0x3e94;
op3val:0x3a93; valaddr_reg:x3; val_offset:2796*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:64 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 64, 0, x3, 2796*FLEN/8, x4, x1, x2)

inst_933:
// fs1 == 0 and fe1 == 0x0d and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x0f and fm2 == 0x294 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x293 and fcsr == 0x60 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x37ff; op2val:0x3e94;
op3val:0x3a93; valaddr_reg:x3; val_offset:2799*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 96, 0, x3, 2799*FLEN/8, x4, x1, x2)

inst_934:
// fs1 == 0 and fe1 == 0x0d and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x0f and fm2 == 0x294 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x293 and fcsr == 0x80 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x37ff; op2val:0x3e94;
op3val:0x3a93; valaddr_reg:x3; val_offset:2802*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:128 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 128, 0, x3, 2802*FLEN/8, x4, x1, x2)

inst_935:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x139 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x203 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x3da and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3939; op2val:0x3e03;
op3val:0x3bda; valaddr_reg:x3; val_offset:2805*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 2805*FLEN/8, x4, x1, x2)

inst_936:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x139 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x203 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x3da and fcsr == 0x20 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3939; op2val:0x3e03;
op3val:0x3bda; valaddr_reg:x3; val_offset:2808*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:32 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 32, 0, x3, 2808*FLEN/8, x4, x1, x2)

inst_937:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x139 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x203 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x3da and fcsr == 0x40 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3939; op2val:0x3e03;
op3val:0x3bda; valaddr_reg:x3; val_offset:2811*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:64 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 64, 0, x3, 2811*FLEN/8, x4, x1, x2)

inst_938:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x139 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x203 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x3da and fcsr == 0x60 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3939; op2val:0x3e03;
op3val:0x3bda; valaddr_reg:x3; val_offset:2814*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 96, 0, x3, 2814*FLEN/8, x4, x1, x2)

inst_939:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x139 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x203 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x3da and fcsr == 0x80 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3939; op2val:0x3e03;
op3val:0x3bda; valaddr_reg:x3; val_offset:2817*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:128 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 128, 0, x3, 2817*FLEN/8, x4, x1, x2)

inst_940:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x1ff and fs2 == 0 and fe2 == 0x0f and fm2 == 0x141 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x3e0 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x39ff; op2val:0x3d41;
op3val:0x3be0; valaddr_reg:x3; val_offset:2820*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 2820*FLEN/8, x4, x1, x2)

inst_941:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x1ff and fs2 == 0 and fe2 == 0x0f and fm2 == 0x141 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x3e0 and fcsr == 0x20 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x39ff; op2val:0x3d41;
op3val:0x3be0; valaddr_reg:x3; val_offset:2823*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:32 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 32, 0, x3, 2823*FLEN/8, x4, x1, x2)

inst_942:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x1ff and fs2 == 0 and fe2 == 0x0f and fm2 == 0x141 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x3e0 and fcsr == 0x40 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x39ff; op2val:0x3d41;
op3val:0x3be0; valaddr_reg:x3; val_offset:2826*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:64 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 64, 0, x3, 2826*FLEN/8, x4, x1, x2)

inst_943:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x1ff and fs2 == 0 and fe2 == 0x0f and fm2 == 0x141 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x3e0 and fcsr == 0x60 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x39ff; op2val:0x3d41;
op3val:0x3be0; valaddr_reg:x3; val_offset:2829*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 96, 0, x3, 2829*FLEN/8, x4, x1, x2)

inst_944:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x1ff and fs2 == 0 and fe2 == 0x0f and fm2 == 0x141 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x3e0 and fcsr == 0x80 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x39ff; op2val:0x3d41;
op3val:0x3be0; valaddr_reg:x3; val_offset:2832*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:128 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 128, 0, x3, 2832*FLEN/8, x4, x1, x2)

inst_945:
// fs1 == 0 and fe1 == 0x0d and fm1 == 0x045 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x2ba and fs3 == 0 and fe3 == 0x0d and fm3 == 0x32f and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3445; op2val:0x3eba;
op3val:0x372f; valaddr_reg:x3; val_offset:2835*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 2835*FLEN/8, x4, x1, x2)

inst_946:
// fs1 == 0 and fe1 == 0x0d and fm1 == 0x045 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x2ba and fs3 == 0 and fe3 == 0x0d and fm3 == 0x32f and fcsr == 0x20 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3445; op2val:0x3eba;
op3val:0x372f; valaddr_reg:x3; val_offset:2838*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:32 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 32, 0, x3, 2838*FLEN/8, x4, x1, x2)

inst_947:
// fs1 == 0 and fe1 == 0x0d and fm1 == 0x045 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x2ba and fs3 == 0 and fe3 == 0x0d and fm3 == 0x32f and fcsr == 0x40 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3445; op2val:0x3eba;
op3val:0x372f; valaddr_reg:x3; val_offset:2841*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:64 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 64, 0, x3, 2841*FLEN/8, x4, x1, x2)

inst_948:
// fs1 == 0 and fe1 == 0x0d and fm1 == 0x045 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x2ba and fs3 == 0 and fe3 == 0x0d and fm3 == 0x32f and fcsr == 0x60 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3445; op2val:0x3eba;
op3val:0x372f; valaddr_reg:x3; val_offset:2844*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 96, 0, x3, 2844*FLEN/8, x4, x1, x2)

inst_949:
// fs1 == 0 and fe1 == 0x0d and fm1 == 0x045 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x2ba and fs3 == 0 and fe3 == 0x0d and fm3 == 0x32f and fcsr == 0x80 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3445; op2val:0x3eba;
op3val:0x372f; valaddr_reg:x3; val_offset:2847*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:128 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 128, 0, x3, 2847*FLEN/8, x4, x1, x2)

inst_950:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x27c and fs2 == 0 and fe2 == 0x0e and fm2 == 0x12f and fs3 == 0 and fe3 == 0x0e and fm3 == 0x033 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3a7c; op2val:0x392f;
op3val:0x3833; valaddr_reg:x3; val_offset:2850*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 2850*FLEN/8, x4, x1, x2)

inst_951:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x27c and fs2 == 0 and fe2 == 0x0e and fm2 == 0x12f and fs3 == 0 and fe3 == 0x0e and fm3 == 0x033 and fcsr == 0x20 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3a7c; op2val:0x392f;
op3val:0x3833; valaddr_reg:x3; val_offset:2853*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:32 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 32, 0, x3, 2853*FLEN/8, x4, x1, x2)

inst_952:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x27c and fs2 == 0 and fe2 == 0x0e and fm2 == 0x12f and fs3 == 0 and fe3 == 0x0e and fm3 == 0x033 and fcsr == 0x40 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3a7c; op2val:0x392f;
op3val:0x3833; valaddr_reg:x3; val_offset:2856*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:64 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 64, 0, x3, 2856*FLEN/8, x4, x1, x2)

inst_953:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x27c and fs2 == 0 and fe2 == 0x0e and fm2 == 0x12f and fs3 == 0 and fe3 == 0x0e and fm3 == 0x033 and fcsr == 0x60 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3a7c; op2val:0x392f;
op3val:0x3833; valaddr_reg:x3; val_offset:2859*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 96, 0, x3, 2859*FLEN/8, x4, x1, x2)

inst_954:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x27c and fs2 == 0 and fe2 == 0x0e and fm2 == 0x12f and fs3 == 0 and fe3 == 0x0e and fm3 == 0x033 and fcsr == 0x80 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3a7c; op2val:0x392f;
op3val:0x3833; valaddr_reg:x3; val_offset:2862*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:128 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 128, 0, x3, 2862*FLEN/8, x4, x1, x2)

inst_955:
// fs1 == 0 and fe1 == 0x0b and fm1 == 0x02f and fs2 == 0 and fe2 == 0x12 and fm2 == 0x2d4 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x326 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x2c2f; op2val:0x4ad4;
op3val:0x3b26; valaddr_reg:x3; val_offset:2865*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 2865*FLEN/8, x4, x1, x2)

inst_956:
// fs1 == 0 and fe1 == 0x0b and fm1 == 0x02f and fs2 == 0 and fe2 == 0x12 and fm2 == 0x2d4 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x326 and fcsr == 0x20 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x2c2f; op2val:0x4ad4;
op3val:0x3b26; valaddr_reg:x3; val_offset:2868*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:32 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 32, 0, x3, 2868*FLEN/8, x4, x1, x2)

inst_957:
// fs1 == 0 and fe1 == 0x0b and fm1 == 0x02f and fs2 == 0 and fe2 == 0x12 and fm2 == 0x2d4 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x326 and fcsr == 0x40 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x2c2f; op2val:0x4ad4;
op3val:0x3b26; valaddr_reg:x3; val_offset:2871*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:64 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 64, 0, x3, 2871*FLEN/8, x4, x1, x2)

inst_958:
// fs1 == 0 and fe1 == 0x0b and fm1 == 0x02f and fs2 == 0 and fe2 == 0x12 and fm2 == 0x2d4 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x326 and fcsr == 0x60 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x2c2f; op2val:0x4ad4;
op3val:0x3b26; valaddr_reg:x3; val_offset:2874*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 96, 0, x3, 2874*FLEN/8, x4, x1, x2)

inst_959:
// fs1 == 0 and fe1 == 0x0b and fm1 == 0x02f and fs2 == 0 and fe2 == 0x12 and fm2 == 0x2d4 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x326 and fcsr == 0x80 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x2c2f; op2val:0x4ad4;
op3val:0x3b26; valaddr_reg:x3; val_offset:2877*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:128 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 128, 0, x3, 2877*FLEN/8, x4, x1, x2)

inst_960:
// fs1 == 0 and fe1 == 0x0c and fm1 == 0x1cb and fs2 == 0 and fe2 == 0x10 and fm2 == 0x245 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x08a and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x31cb; op2val:0x4245;
op3val:0x388a; valaddr_reg:x3; val_offset:2880*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 2880*FLEN/8, x4, x1, x2)

inst_961:
// fs1 == 0 and fe1 == 0x0c and fm1 == 0x1cb and fs2 == 0 and fe2 == 0x10 and fm2 == 0x245 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x08a and fcsr == 0x20 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x31cb; op2val:0x4245;
op3val:0x388a; valaddr_reg:x3; val_offset:2883*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:32 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 32, 0, x3, 2883*FLEN/8, x4, x1, x2)

inst_962:
// fs1 == 0 and fe1 == 0x0c and fm1 == 0x1cb and fs2 == 0 and fe2 == 0x10 and fm2 == 0x245 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x08a and fcsr == 0x40 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x31cb; op2val:0x4245;
op3val:0x388a; valaddr_reg:x3; val_offset:2886*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:64 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 64, 0, x3, 2886*FLEN/8, x4, x1, x2)

inst_963:
// fs1 == 0 and fe1 == 0x0c and fm1 == 0x1cb and fs2 == 0 and fe2 == 0x10 and fm2 == 0x245 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x08a and fcsr == 0x60 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x31cb; op2val:0x4245;
op3val:0x388a; valaddr_reg:x3; val_offset:2889*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 96, 0, x3, 2889*FLEN/8, x4, x1, x2)

inst_964:
// fs1 == 0 and fe1 == 0x0c and fm1 == 0x1cb and fs2 == 0 and fe2 == 0x10 and fm2 == 0x245 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x08a and fcsr == 0x80 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x31cb; op2val:0x4245;
op3val:0x388a; valaddr_reg:x3; val_offset:2892*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:128 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 128, 0, x3, 2892*FLEN/8, x4, x1, x2)

inst_965:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x00a and fs2 == 0 and fe2 == 0x0d and fm2 == 0x13e and fs3 == 0 and fe3 == 0x0c and fm3 == 0x14b and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x380a; op2val:0x353e;
op3val:0x314b; valaddr_reg:x3; val_offset:2895*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 2895*FLEN/8, x4, x1, x2)

inst_966:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x00a and fs2 == 0 and fe2 == 0x0d and fm2 == 0x13e and fs3 == 0 and fe3 == 0x0c and fm3 == 0x14b and fcsr == 0x20 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x380a; op2val:0x353e;
op3val:0x314b; valaddr_reg:x3; val_offset:2898*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:32 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 32, 0, x3, 2898*FLEN/8, x4, x1, x2)

inst_967:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x00a and fs2 == 0 and fe2 == 0x0d and fm2 == 0x13e and fs3 == 0 and fe3 == 0x0c and fm3 == 0x14b and fcsr == 0x40 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x380a; op2val:0x353e;
op3val:0x314b; valaddr_reg:x3; val_offset:2901*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:64 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 64, 0, x3, 2901*FLEN/8, x4, x1, x2)

inst_968:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x00a and fs2 == 0 and fe2 == 0x0d and fm2 == 0x13e and fs3 == 0 and fe3 == 0x0c and fm3 == 0x14b and fcsr == 0x60 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x380a; op2val:0x353e;
op3val:0x314b; valaddr_reg:x3; val_offset:2904*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 96, 0, x3, 2904*FLEN/8, x4, x1, x2)

inst_969:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x00a and fs2 == 0 and fe2 == 0x0d and fm2 == 0x13e and fs3 == 0 and fe3 == 0x0c and fm3 == 0x14b and fcsr == 0x80 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x380a; op2val:0x353e;
op3val:0x314b; valaddr_reg:x3; val_offset:2907*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:128 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 128, 0, x3, 2907*FLEN/8, x4, x1, x2)

inst_970:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x0db and fs2 == 0 and fe2 == 0x0e and fm2 == 0x280 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x3e4 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x38db; op2val:0x3a80;
op3val:0x37e4; valaddr_reg:x3; val_offset:2910*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 2910*FLEN/8, x4, x1, x2)

inst_971:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x0db and fs2 == 0 and fe2 == 0x0e and fm2 == 0x280 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x3e4 and fcsr == 0x20 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x38db; op2val:0x3a80;
op3val:0x37e4; valaddr_reg:x3; val_offset:2913*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:32 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 32, 0, x3, 2913*FLEN/8, x4, x1, x2)

inst_972:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x0db and fs2 == 0 and fe2 == 0x0e and fm2 == 0x280 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x3e4 and fcsr == 0x40 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x38db; op2val:0x3a80;
op3val:0x37e4; valaddr_reg:x3; val_offset:2916*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:64 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 64, 0, x3, 2916*FLEN/8, x4, x1, x2)

inst_973:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x0db and fs2 == 0 and fe2 == 0x0e and fm2 == 0x280 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x3e4 and fcsr == 0x60 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x38db; op2val:0x3a80;
op3val:0x37e4; valaddr_reg:x3; val_offset:2919*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 96, 0, x3, 2919*FLEN/8, x4, x1, x2)

inst_974:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x0db and fs2 == 0 and fe2 == 0x0e and fm2 == 0x280 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x3e4 and fcsr == 0x80 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x38db; op2val:0x3a80;
op3val:0x37e4; valaddr_reg:x3; val_offset:2922*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:128 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 128, 0, x3, 2922*FLEN/8, x4, x1, x2)

inst_975:
// fs1 == 0 and fe1 == 0x0d and fm1 == 0x0ff and fs2 == 0 and fe2 == 0x0a and fm2 == 0x340 and fs3 == 0 and fe3 == 0x09 and fm3 == 0x083 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x34ff; op2val:0x2b40;
op3val:0x2483; valaddr_reg:x3; val_offset:2925*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 2925*FLEN/8, x4, x1, x2)

inst_976:
// fs1 == 0 and fe1 == 0x0d and fm1 == 0x0ff and fs2 == 0 and fe2 == 0x0a and fm2 == 0x340 and fs3 == 0 and fe3 == 0x09 and fm3 == 0x083 and fcsr == 0x20 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x34ff; op2val:0x2b40;
op3val:0x2483; valaddr_reg:x3; val_offset:2928*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:32 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 32, 0, x3, 2928*FLEN/8, x4, x1, x2)

inst_977:
// fs1 == 0 and fe1 == 0x0d and fm1 == 0x0ff and fs2 == 0 and fe2 == 0x0a and fm2 == 0x340 and fs3 == 0 and fe3 == 0x09 and fm3 == 0x083 and fcsr == 0x40 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x34ff; op2val:0x2b40;
op3val:0x2483; valaddr_reg:x3; val_offset:2931*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:64 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 64, 0, x3, 2931*FLEN/8, x4, x1, x2)

inst_978:
// fs1 == 0 and fe1 == 0x0d and fm1 == 0x0ff and fs2 == 0 and fe2 == 0x0a and fm2 == 0x340 and fs3 == 0 and fe3 == 0x09 and fm3 == 0x083 and fcsr == 0x60 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x34ff; op2val:0x2b40;
op3val:0x2483; valaddr_reg:x3; val_offset:2934*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 96, 0, x3, 2934*FLEN/8, x4, x1, x2)

inst_979:
// fs1 == 0 and fe1 == 0x0d and fm1 == 0x0ff and fs2 == 0 and fe2 == 0x0a and fm2 == 0x340 and fs3 == 0 and fe3 == 0x09 and fm3 == 0x083 and fcsr == 0x80 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x34ff; op2val:0x2b40;
op3val:0x2483; valaddr_reg:x3; val_offset:2937*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:128 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 128, 0, x3, 2937*FLEN/8, x4, x1, x2)

inst_980:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x142 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x015 and fs3 == 0 and fe3 == 0x0c and fm3 == 0x15e and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3942; op2val:0x3415;
op3val:0x315e; valaddr_reg:x3; val_offset:2940*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 2940*FLEN/8, x4, x1, x2)

inst_981:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x142 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x015 and fs3 == 0 and fe3 == 0x0c and fm3 == 0x15e and fcsr == 0x20 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3942; op2val:0x3415;
op3val:0x315e; valaddr_reg:x3; val_offset:2943*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:32 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 32, 0, x3, 2943*FLEN/8, x4, x1, x2)

inst_982:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x142 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x015 and fs3 == 0 and fe3 == 0x0c and fm3 == 0x15e and fcsr == 0x40 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3942; op2val:0x3415;
op3val:0x315e; valaddr_reg:x3; val_offset:2946*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:64 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 64, 0, x3, 2946*FLEN/8, x4, x1, x2)

inst_983:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x142 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x015 and fs3 == 0 and fe3 == 0x0c and fm3 == 0x15e and fcsr == 0x60 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3942; op2val:0x3415;
op3val:0x315e; valaddr_reg:x3; val_offset:2949*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 96, 0, x3, 2949*FLEN/8, x4, x1, x2)

inst_984:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x142 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x015 and fs3 == 0 and fe3 == 0x0c and fm3 == 0x15e and fcsr == 0x80 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3942; op2val:0x3415;
op3val:0x315e; valaddr_reg:x3; val_offset:2952*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:128 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 128, 0, x3, 2952*FLEN/8, x4, x1, x2)

inst_985:
// fs1 == 0 and fe1 == 0x0d and fm1 == 0x0b1 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x0f7 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x1d3 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x34b1; op2val:0x3cf7;
op3val:0x35d3; valaddr_reg:x3; val_offset:2955*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 2955*FLEN/8, x4, x1, x2)

inst_986:
// fs1 == 0 and fe1 == 0x0d and fm1 == 0x0b1 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x0f7 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x1d3 and fcsr == 0x20 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x34b1; op2val:0x3cf7;
op3val:0x35d3; valaddr_reg:x3; val_offset:2958*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:32 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 32, 0, x3, 2958*FLEN/8, x4, x1, x2)

inst_987:
// fs1 == 0 and fe1 == 0x0d and fm1 == 0x0b1 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x0f7 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x1d3 and fcsr == 0x40 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x34b1; op2val:0x3cf7;
op3val:0x35d3; valaddr_reg:x3; val_offset:2961*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:64 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 64, 0, x3, 2961*FLEN/8, x4, x1, x2)

inst_988:
// fs1 == 0 and fe1 == 0x0d and fm1 == 0x0b1 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x0f7 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x1d3 and fcsr == 0x60 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x34b1; op2val:0x3cf7;
op3val:0x35d3; valaddr_reg:x3; val_offset:2964*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 96, 0, x3, 2964*FLEN/8, x4, x1, x2)

inst_989:
// fs1 == 0 and fe1 == 0x0d and fm1 == 0x0b1 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x0f7 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x1d3 and fcsr == 0x80 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x34b1; op2val:0x3cf7;
op3val:0x35d3; valaddr_reg:x3; val_offset:2967*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:128 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 128, 0, x3, 2967*FLEN/8, x4, x1, x2)

inst_990:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x0c3 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x062 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x138 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x38c3; op2val:0x3c62;
op3val:0x3938; valaddr_reg:x3; val_offset:2970*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 2970*FLEN/8, x4, x1, x2)

inst_991:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x0c3 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x062 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x138 and fcsr == 0x20 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x38c3; op2val:0x3c62;
op3val:0x3938; valaddr_reg:x3; val_offset:2973*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:32 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 32, 0, x3, 2973*FLEN/8, x4, x1, x2)

inst_992:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x0c3 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x062 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x138 and fcsr == 0x40 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x38c3; op2val:0x3c62;
op3val:0x3938; valaddr_reg:x3; val_offset:2976*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:64 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 64, 0, x3, 2976*FLEN/8, x4, x1, x2)

inst_993:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x0c3 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x062 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x138 and fcsr == 0x60 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x38c3; op2val:0x3c62;
op3val:0x3938; valaddr_reg:x3; val_offset:2979*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 96, 0, x3, 2979*FLEN/8, x4, x1, x2)

inst_994:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x0c3 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x062 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x138 and fcsr == 0x80 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x38c3; op2val:0x3c62;
op3val:0x3938; valaddr_reg:x3; val_offset:2982*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:128 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 128, 0, x3, 2982*FLEN/8, x4, x1, x2)

inst_995:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x390 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x35c and fs3 == 0 and fe3 == 0x0e and fm3 == 0x2f6 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3b90; op2val:0x3b5c;
op3val:0x3af6; valaddr_reg:x3; val_offset:2985*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 2985*FLEN/8, x4, x1, x2)

inst_996:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x390 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x35c and fs3 == 0 and fe3 == 0x0e and fm3 == 0x2f6 and fcsr == 0x20 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3b90; op2val:0x3b5c;
op3val:0x3af6; valaddr_reg:x3; val_offset:2988*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:32 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 32, 0, x3, 2988*FLEN/8, x4, x1, x2)

inst_997:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x390 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x35c and fs3 == 0 and fe3 == 0x0e and fm3 == 0x2f6 and fcsr == 0x40 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3b90; op2val:0x3b5c;
op3val:0x3af6; valaddr_reg:x3; val_offset:2991*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:64 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 64, 0, x3, 2991*FLEN/8, x4, x1, x2)

inst_998:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x390 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x35c and fs3 == 0 and fe3 == 0x0e and fm3 == 0x2f6 and fcsr == 0x60 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3b90; op2val:0x3b5c;
op3val:0x3af6; valaddr_reg:x3; val_offset:2994*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 96, 0, x3, 2994*FLEN/8, x4, x1, x2)

inst_999:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x390 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x35c and fs3 == 0 and fe3 == 0x0e and fm3 == 0x2f6 and fcsr == 0x80 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3b90; op2val:0x3b5c;
op3val:0x3af6; valaddr_reg:x3; val_offset:2997*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:128 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 128, 0, x3, 2997*FLEN/8, x4, x1, x2)

inst_1000:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x36f and fs2 == 0 and fe2 == 0x0d and fm2 == 0x076 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x025 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3b6f; op2val:0x3476;
op3val:0x3425; valaddr_reg:x3; val_offset:3000*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 3000*FLEN/8, x4, x1, x2)

inst_1001:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x36f and fs2 == 0 and fe2 == 0x0d and fm2 == 0x076 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x025 and fcsr == 0x20 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3b6f; op2val:0x3476;
op3val:0x3425; valaddr_reg:x3; val_offset:3003*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:32 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 32, 0, x3, 3003*FLEN/8, x4, x1, x2)

inst_1002:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x36f and fs2 == 0 and fe2 == 0x0d and fm2 == 0x076 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x025 and fcsr == 0x40 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3b6f; op2val:0x3476;
op3val:0x3425; valaddr_reg:x3; val_offset:3006*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:64 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 64, 0, x3, 3006*FLEN/8, x4, x1, x2)

inst_1003:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x36f and fs2 == 0 and fe2 == 0x0d and fm2 == 0x076 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x025 and fcsr == 0x60 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3b6f; op2val:0x3476;
op3val:0x3425; valaddr_reg:x3; val_offset:3009*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 96, 0, x3, 3009*FLEN/8, x4, x1, x2)

inst_1004:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x36f and fs2 == 0 and fe2 == 0x0d and fm2 == 0x076 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x025 and fcsr == 0x80 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3b6f; op2val:0x3476;
op3val:0x3425; valaddr_reg:x3; val_offset:3012*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:128 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 128, 0, x3, 3012*FLEN/8, x4, x1, x2)

inst_1005:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x1f4 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x07f and fs3 == 0 and fe3 == 0x0e and fm3 == 0x2b1 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x39f4; op2val:0x3c7f;
op3val:0x3ab1; valaddr_reg:x3; val_offset:3015*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 3015*FLEN/8, x4, x1, x2)

inst_1006:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x1f4 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x07f and fs3 == 0 and fe3 == 0x0e and fm3 == 0x2b1 and fcsr == 0x20 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x39f4; op2val:0x3c7f;
op3val:0x3ab1; valaddr_reg:x3; val_offset:3018*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:32 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 32, 0, x3, 3018*FLEN/8, x4, x1, x2)

inst_1007:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x1f4 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x07f and fs3 == 0 and fe3 == 0x0e and fm3 == 0x2b1 and fcsr == 0x40 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x39f4; op2val:0x3c7f;
op3val:0x3ab1; valaddr_reg:x3; val_offset:3021*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:64 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 64, 0, x3, 3021*FLEN/8, x4, x1, x2)

inst_1008:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x1f4 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x07f and fs3 == 0 and fe3 == 0x0e and fm3 == 0x2b1 and fcsr == 0x60 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x39f4; op2val:0x3c7f;
op3val:0x3ab1; valaddr_reg:x3; val_offset:3024*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 96, 0, x3, 3024*FLEN/8, x4, x1, x2)

inst_1009:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x1f4 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x07f and fs3 == 0 and fe3 == 0x0e and fm3 == 0x2b1 and fcsr == 0x80 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x39f4; op2val:0x3c7f;
op3val:0x3ab1; valaddr_reg:x3; val_offset:3027*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:128 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 128, 0, x3, 3027*FLEN/8, x4, x1, x2)

inst_1010:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x352 and fs2 == 0 and fe2 == 0x0c and fm2 == 0x18d and fs3 == 0 and fe3 == 0x0c and fm3 == 0x114 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3b52; op2val:0x318d;
op3val:0x3114; valaddr_reg:x3; val_offset:3030*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 3030*FLEN/8, x4, x1, x2)

inst_1011:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x352 and fs2 == 0 and fe2 == 0x0c and fm2 == 0x18d and fs3 == 0 and fe3 == 0x0c and fm3 == 0x114 and fcsr == 0x20 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3b52; op2val:0x318d;
op3val:0x3114; valaddr_reg:x3; val_offset:3033*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:32 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 32, 0, x3, 3033*FLEN/8, x4, x1, x2)

inst_1012:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x352 and fs2 == 0 and fe2 == 0x0c and fm2 == 0x18d and fs3 == 0 and fe3 == 0x0c and fm3 == 0x114 and fcsr == 0x40 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3b52; op2val:0x318d;
op3val:0x3114; valaddr_reg:x3; val_offset:3036*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:64 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 64, 0, x3, 3036*FLEN/8, x4, x1, x2)

inst_1013:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x352 and fs2 == 0 and fe2 == 0x0c and fm2 == 0x18d and fs3 == 0 and fe3 == 0x0c and fm3 == 0x114 and fcsr == 0x60 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3b52; op2val:0x318d;
op3val:0x3114; valaddr_reg:x3; val_offset:3039*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 96, 0, x3, 3039*FLEN/8, x4, x1, x2)

inst_1014:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x352 and fs2 == 0 and fe2 == 0x0c and fm2 == 0x18d and fs3 == 0 and fe3 == 0x0c and fm3 == 0x114 and fcsr == 0x80 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3b52; op2val:0x318d;
op3val:0x3114; valaddr_reg:x3; val_offset:3042*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:128 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 128, 0, x3, 3042*FLEN/8, x4, x1, x2)

inst_1015:
// fs1 == 0 and fe1 == 0x0c and fm1 == 0x025 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x116 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x145 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3025; op2val:0x4116;
op3val:0x3545; valaddr_reg:x3; val_offset:3045*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 3045*FLEN/8, x4, x1, x2)

inst_1016:
// fs1 == 0 and fe1 == 0x0c and fm1 == 0x025 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x116 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x145 and fcsr == 0x20 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3025; op2val:0x4116;
op3val:0x3545; valaddr_reg:x3; val_offset:3048*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:32 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 32, 0, x3, 3048*FLEN/8, x4, x1, x2)

inst_1017:
// fs1 == 0 and fe1 == 0x0c and fm1 == 0x025 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x116 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x145 and fcsr == 0x40 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3025; op2val:0x4116;
op3val:0x3545; valaddr_reg:x3; val_offset:3051*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:64 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 64, 0, x3, 3051*FLEN/8, x4, x1, x2)

inst_1018:
// fs1 == 0 and fe1 == 0x0c and fm1 == 0x025 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x116 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x145 and fcsr == 0x60 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3025; op2val:0x4116;
op3val:0x3545; valaddr_reg:x3; val_offset:3054*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 96, 0, x3, 3054*FLEN/8, x4, x1, x2)

inst_1019:
// fs1 == 0 and fe1 == 0x0c and fm1 == 0x025 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x116 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x145 and fcsr == 0x80 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3025; op2val:0x4116;
op3val:0x3545; valaddr_reg:x3; val_offset:3057*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:128 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 128, 0, x3, 3057*FLEN/8, x4, x1, x2)

inst_1020:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x1be and fs2 == 0 and fe2 == 0x0f and fm2 == 0x038 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x20f and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x39be; op2val:0x3c38;
op3val:0x3a0f; valaddr_reg:x3; val_offset:3060*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 3060*FLEN/8, x4, x1, x2)

inst_1021:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x1be and fs2 == 0 and fe2 == 0x0f and fm2 == 0x038 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x20f and fcsr == 0x20 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x39be; op2val:0x3c38;
op3val:0x3a0f; valaddr_reg:x3; val_offset:3063*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:32 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 32, 0, x3, 3063*FLEN/8, x4, x1, x2)

inst_1022:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x1be and fs2 == 0 and fe2 == 0x0f and fm2 == 0x038 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x20f and fcsr == 0x40 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x39be; op2val:0x3c38;
op3val:0x3a0f; valaddr_reg:x3; val_offset:3066*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:64 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 64, 0, x3, 3066*FLEN/8, x4, x1, x2)

inst_1023:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x1be and fs2 == 0 and fe2 == 0x0f and fm2 == 0x038 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x20f and fcsr == 0x60 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x39be; op2val:0x3c38;
op3val:0x3a0f; valaddr_reg:x3; val_offset:3069*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 96, 0, x3, 3069*FLEN/8, x4, x1, x2)
RVTEST_SIGBASE(x1,signature_x1_9)

inst_1024:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x1be and fs2 == 0 and fe2 == 0x0f and fm2 == 0x038 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x20f and fcsr == 0x80 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x39be; op2val:0x3c38;
op3val:0x3a0f; valaddr_reg:x3; val_offset:3072*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:128 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 128, 0, x3, 3072*FLEN/8, x4, x1, x2)

inst_1025:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x1a7 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x21e and fs3 == 0 and fe3 == 0x0e and fm3 == 0x053 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x39a7; op2val:0x3a1e;
op3val:0x3853; valaddr_reg:x3; val_offset:3075*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 3075*FLEN/8, x4, x1, x2)

inst_1026:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x1a7 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x21e and fs3 == 0 and fe3 == 0x0e and fm3 == 0x053 and fcsr == 0x20 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x39a7; op2val:0x3a1e;
op3val:0x3853; valaddr_reg:x3; val_offset:3078*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:32 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 32, 0, x3, 3078*FLEN/8, x4, x1, x2)

inst_1027:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x1a7 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x21e and fs3 == 0 and fe3 == 0x0e and fm3 == 0x053 and fcsr == 0x40 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x39a7; op2val:0x3a1e;
op3val:0x3853; valaddr_reg:x3; val_offset:3081*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:64 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 64, 0, x3, 3081*FLEN/8, x4, x1, x2)

inst_1028:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x1a7 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x21e and fs3 == 0 and fe3 == 0x0e and fm3 == 0x053 and fcsr == 0x60 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x39a7; op2val:0x3a1e;
op3val:0x3853; valaddr_reg:x3; val_offset:3084*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 96, 0, x3, 3084*FLEN/8, x4, x1, x2)

inst_1029:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x1a7 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x21e and fs3 == 0 and fe3 == 0x0e and fm3 == 0x053 and fcsr == 0x80 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x39a7; op2val:0x3a1e;
op3val:0x3853; valaddr_reg:x3; val_offset:3087*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:128 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 128, 0, x3, 3087*FLEN/8, x4, x1, x2)

inst_1030:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x2bd and fs2 == 0 and fe2 == 0x0e and fm2 == 0x143 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x06f and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3abd; op2val:0x3943;
op3val:0x386f; valaddr_reg:x3; val_offset:3090*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 3090*FLEN/8, x4, x1, x2)

inst_1031:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x2bd and fs2 == 0 and fe2 == 0x0e and fm2 == 0x143 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x06f and fcsr == 0x20 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3abd; op2val:0x3943;
op3val:0x386f; valaddr_reg:x3; val_offset:3093*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:32 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 32, 0, x3, 3093*FLEN/8, x4, x1, x2)

inst_1032:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x2bd and fs2 == 0 and fe2 == 0x0e and fm2 == 0x143 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x06f and fcsr == 0x40 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3abd; op2val:0x3943;
op3val:0x386f; valaddr_reg:x3; val_offset:3096*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:64 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 64, 0, x3, 3096*FLEN/8, x4, x1, x2)

inst_1033:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x2bd and fs2 == 0 and fe2 == 0x0e and fm2 == 0x143 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x06f and fcsr == 0x60 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3abd; op2val:0x3943;
op3val:0x386f; valaddr_reg:x3; val_offset:3099*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 96, 0, x3, 3099*FLEN/8, x4, x1, x2)

inst_1034:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x2bd and fs2 == 0 and fe2 == 0x0e and fm2 == 0x143 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x06f and fcsr == 0x80 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3abd; op2val:0x3943;
op3val:0x386f; valaddr_reg:x3; val_offset:3102*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:128 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 128, 0, x3, 3102*FLEN/8, x4, x1, x2)

inst_1035:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x1e4 and fs2 == 0 and fe2 == 0x0a and fm2 == 0x2a9 and fs3 == 0 and fe3 == 0x0a and fm3 == 0x0e6 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x39e4; op2val:0x2aa9;
op3val:0x28e6; valaddr_reg:x3; val_offset:3105*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 3105*FLEN/8, x4, x1, x2)

inst_1036:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x1e4 and fs2 == 0 and fe2 == 0x0a and fm2 == 0x2a9 and fs3 == 0 and fe3 == 0x0a and fm3 == 0x0e6 and fcsr == 0x20 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x39e4; op2val:0x2aa9;
op3val:0x28e6; valaddr_reg:x3; val_offset:3108*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:32 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 32, 0, x3, 3108*FLEN/8, x4, x1, x2)

inst_1037:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x1e4 and fs2 == 0 and fe2 == 0x0a and fm2 == 0x2a9 and fs3 == 0 and fe3 == 0x0a and fm3 == 0x0e6 and fcsr == 0x40 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x39e4; op2val:0x2aa9;
op3val:0x28e6; valaddr_reg:x3; val_offset:3111*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:64 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 64, 0, x3, 3111*FLEN/8, x4, x1, x2)

inst_1038:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x1e4 and fs2 == 0 and fe2 == 0x0a and fm2 == 0x2a9 and fs3 == 0 and fe3 == 0x0a and fm3 == 0x0e6 and fcsr == 0x60 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x39e4; op2val:0x2aa9;
op3val:0x28e6; valaddr_reg:x3; val_offset:3114*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 96, 0, x3, 3114*FLEN/8, x4, x1, x2)

inst_1039:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x1e4 and fs2 == 0 and fe2 == 0x0a and fm2 == 0x2a9 and fs3 == 0 and fe3 == 0x0a and fm3 == 0x0e6 and fcsr == 0x80 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x39e4; op2val:0x2aa9;
op3val:0x28e6; valaddr_reg:x3; val_offset:3117*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:128 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 128, 0, x3, 3117*FLEN/8, x4, x1, x2)

inst_1040:
// fs1 == 0 and fe1 == 0x09 and fm1 == 0x306 and fs2 == 0 and fe2 == 0x13 and fm2 == 0x020 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x33f and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x2706; op2val:0x4c20;
op3val:0x373f; valaddr_reg:x3; val_offset:3120*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 3120*FLEN/8, x4, x1, x2)

inst_1041:
// fs1 == 0 and fe1 == 0x09 and fm1 == 0x306 and fs2 == 0 and fe2 == 0x13 and fm2 == 0x020 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x33f and fcsr == 0x20 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x2706; op2val:0x4c20;
op3val:0x373f; valaddr_reg:x3; val_offset:3123*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:32 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 32, 0, x3, 3123*FLEN/8, x4, x1, x2)

inst_1042:
// fs1 == 0 and fe1 == 0x09 and fm1 == 0x306 and fs2 == 0 and fe2 == 0x13 and fm2 == 0x020 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x33f and fcsr == 0x40 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x2706; op2val:0x4c20;
op3val:0x373f; valaddr_reg:x3; val_offset:3126*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:64 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 64, 0, x3, 3126*FLEN/8, x4, x1, x2)

inst_1043:
// fs1 == 0 and fe1 == 0x09 and fm1 == 0x306 and fs2 == 0 and fe2 == 0x13 and fm2 == 0x020 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x33f and fcsr == 0x60 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x2706; op2val:0x4c20;
op3val:0x373f; valaddr_reg:x3; val_offset:3129*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 96, 0, x3, 3129*FLEN/8, x4, x1, x2)

inst_1044:
// fs1 == 0 and fe1 == 0x09 and fm1 == 0x306 and fs2 == 0 and fe2 == 0x13 and fm2 == 0x020 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x33f and fcsr == 0x80 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x2706; op2val:0x4c20;
op3val:0x373f; valaddr_reg:x3; val_offset:3132*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:128 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 128, 0, x3, 3132*FLEN/8, x4, x1, x2)

inst_1045:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x20b and fs2 == 0 and fe2 == 0x0a and fm2 == 0x1d6 and fs3 == 0 and fe3 == 0x0a and fm3 == 0x067 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3a0b; op2val:0x29d6;
op3val:0x2867; valaddr_reg:x3; val_offset:3135*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 3135*FLEN/8, x4, x1, x2)

inst_1046:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x20b and fs2 == 0 and fe2 == 0x0a and fm2 == 0x1d6 and fs3 == 0 and fe3 == 0x0a and fm3 == 0x067 and fcsr == 0x20 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3a0b; op2val:0x29d6;
op3val:0x2867; valaddr_reg:x3; val_offset:3138*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:32 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 32, 0, x3, 3138*FLEN/8, x4, x1, x2)

inst_1047:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x20b and fs2 == 0 and fe2 == 0x0a and fm2 == 0x1d6 and fs3 == 0 and fe3 == 0x0a and fm3 == 0x067 and fcsr == 0x40 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3a0b; op2val:0x29d6;
op3val:0x2867; valaddr_reg:x3; val_offset:3141*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:64 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 64, 0, x3, 3141*FLEN/8, x4, x1, x2)

inst_1048:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x20b and fs2 == 0 and fe2 == 0x0a and fm2 == 0x1d6 and fs3 == 0 and fe3 == 0x0a and fm3 == 0x067 and fcsr == 0x60 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3a0b; op2val:0x29d6;
op3val:0x2867; valaddr_reg:x3; val_offset:3144*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 96, 0, x3, 3144*FLEN/8, x4, x1, x2)

inst_1049:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x20b and fs2 == 0 and fe2 == 0x0a and fm2 == 0x1d6 and fs3 == 0 and fe3 == 0x0a and fm3 == 0x067 and fcsr == 0x80 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3a0b; op2val:0x29d6;
op3val:0x2867; valaddr_reg:x3; val_offset:3147*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:128 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 128, 0, x3, 3147*FLEN/8, x4, x1, x2)

inst_1050:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x186 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x374 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x125 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3986; op2val:0x3b74;
op3val:0x3925; valaddr_reg:x3; val_offset:3150*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 3150*FLEN/8, x4, x1, x2)

inst_1051:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x186 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x374 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x125 and fcsr == 0x20 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3986; op2val:0x3b74;
op3val:0x3925; valaddr_reg:x3; val_offset:3153*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:32 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 32, 0, x3, 3153*FLEN/8, x4, x1, x2)

inst_1052:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x186 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x374 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x125 and fcsr == 0x40 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3986; op2val:0x3b74;
op3val:0x3925; valaddr_reg:x3; val_offset:3156*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:64 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 64, 0, x3, 3156*FLEN/8, x4, x1, x2)

inst_1053:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x186 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x374 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x125 and fcsr == 0x60 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3986; op2val:0x3b74;
op3val:0x3925; valaddr_reg:x3; val_offset:3159*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 96, 0, x3, 3159*FLEN/8, x4, x1, x2)

inst_1054:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x186 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x374 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x125 and fcsr == 0x80 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3986; op2val:0x3b74;
op3val:0x3925; valaddr_reg:x3; val_offset:3162*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:128 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 128, 0, x3, 3162*FLEN/8, x4, x1, x2)

inst_1055:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x3fd and fs2 == 0 and fe2 == 0x0e and fm2 == 0x0f3 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x0f2 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3bfd; op2val:0x38f3;
op3val:0x38f2; valaddr_reg:x3; val_offset:3165*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 3165*FLEN/8, x4, x1, x2)

inst_1056:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x3fd and fs2 == 0 and fe2 == 0x0e and fm2 == 0x0f3 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x0f2 and fcsr == 0x20 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3bfd; op2val:0x38f3;
op3val:0x38f2; valaddr_reg:x3; val_offset:3168*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:32 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 32, 0, x3, 3168*FLEN/8, x4, x1, x2)

inst_1057:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x3fd and fs2 == 0 and fe2 == 0x0e and fm2 == 0x0f3 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x0f2 and fcsr == 0x40 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3bfd; op2val:0x38f3;
op3val:0x38f2; valaddr_reg:x3; val_offset:3171*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:64 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 64, 0, x3, 3171*FLEN/8, x4, x1, x2)

inst_1058:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x3fd and fs2 == 0 and fe2 == 0x0e and fm2 == 0x0f3 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x0f2 and fcsr == 0x60 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3bfd; op2val:0x38f3;
op3val:0x38f2; valaddr_reg:x3; val_offset:3174*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 96, 0, x3, 3174*FLEN/8, x4, x1, x2)

inst_1059:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x3fd and fs2 == 0 and fe2 == 0x0e and fm2 == 0x0f3 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x0f2 and fcsr == 0x80 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3bfd; op2val:0x38f3;
op3val:0x38f2; valaddr_reg:x3; val_offset:3177*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:128 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 128, 0, x3, 3177*FLEN/8, x4, x1, x2)

inst_1060:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x033 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x392 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x3f4 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3833; op2val:0x3b92;
op3val:0x37f4; valaddr_reg:x3; val_offset:3180*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 3180*FLEN/8, x4, x1, x2)

inst_1061:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x033 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x392 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x3f4 and fcsr == 0x20 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3833; op2val:0x3b92;
op3val:0x37f4; valaddr_reg:x3; val_offset:3183*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:32 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 32, 0, x3, 3183*FLEN/8, x4, x1, x2)

inst_1062:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x033 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x392 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x3f4 and fcsr == 0x40 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3833; op2val:0x3b92;
op3val:0x37f4; valaddr_reg:x3; val_offset:3186*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:64 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 64, 0, x3, 3186*FLEN/8, x4, x1, x2)

inst_1063:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x033 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x392 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x3f4 and fcsr == 0x60 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3833; op2val:0x3b92;
op3val:0x37f4; valaddr_reg:x3; val_offset:3189*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 96, 0, x3, 3189*FLEN/8, x4, x1, x2)

inst_1064:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x033 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x392 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x3f4 and fcsr == 0x80 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3833; op2val:0x3b92;
op3val:0x37f4; valaddr_reg:x3; val_offset:3192*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:128 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 128, 0, x3, 3192*FLEN/8, x4, x1, x2)

inst_1065:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x264 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x0f5 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x3ec and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3a64; op2val:0x38f5;
op3val:0x37ec; valaddr_reg:x3; val_offset:3195*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 3195*FLEN/8, x4, x1, x2)

inst_1066:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x264 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x0f5 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x3ec and fcsr == 0x20 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3a64; op2val:0x38f5;
op3val:0x37ec; valaddr_reg:x3; val_offset:3198*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:32 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 32, 0, x3, 3198*FLEN/8, x4, x1, x2)

inst_1067:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x264 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x0f5 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x3ec and fcsr == 0x40 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3a64; op2val:0x38f5;
op3val:0x37ec; valaddr_reg:x3; val_offset:3201*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:64 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 64, 0, x3, 3201*FLEN/8, x4, x1, x2)

inst_1068:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x264 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x0f5 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x3ec and fcsr == 0x60 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3a64; op2val:0x38f5;
op3val:0x37ec; valaddr_reg:x3; val_offset:3204*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 96, 0, x3, 3204*FLEN/8, x4, x1, x2)

inst_1069:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x264 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x0f5 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x3ec and fcsr == 0x80 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3a64; op2val:0x38f5;
op3val:0x37ec; valaddr_reg:x3; val_offset:3207*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:128 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 128, 0, x3, 3207*FLEN/8, x4, x1, x2)

inst_1070:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x3f5 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x1ea and fs3 == 0 and fe3 == 0x0e and fm3 == 0x1e3 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3bf5; op2val:0x39ea;
op3val:0x39e3; valaddr_reg:x3; val_offset:3210*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 3210*FLEN/8, x4, x1, x2)

inst_1071:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x3f5 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x1ea and fs3 == 0 and fe3 == 0x0e and fm3 == 0x1e3 and fcsr == 0x20 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3bf5; op2val:0x39ea;
op3val:0x39e3; valaddr_reg:x3; val_offset:3213*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:32 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 32, 0, x3, 3213*FLEN/8, x4, x1, x2)

inst_1072:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x3f5 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x1ea and fs3 == 0 and fe3 == 0x0e and fm3 == 0x1e3 and fcsr == 0x40 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3bf5; op2val:0x39ea;
op3val:0x39e3; valaddr_reg:x3; val_offset:3216*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:64 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 64, 0, x3, 3216*FLEN/8, x4, x1, x2)

inst_1073:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x3f5 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x1ea and fs3 == 0 and fe3 == 0x0e and fm3 == 0x1e3 and fcsr == 0x60 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3bf5; op2val:0x39ea;
op3val:0x39e3; valaddr_reg:x3; val_offset:3219*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 96, 0, x3, 3219*FLEN/8, x4, x1, x2)

inst_1074:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x3f5 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x1ea and fs3 == 0 and fe3 == 0x0e and fm3 == 0x1e3 and fcsr == 0x80 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3bf5; op2val:0x39ea;
op3val:0x39e3; valaddr_reg:x3; val_offset:3222*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:128 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 128, 0, x3, 3222*FLEN/8, x4, x1, x2)

inst_1075:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x348 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x147 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x0cd and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3b48; op2val:0x3947;
op3val:0x38cd; valaddr_reg:x3; val_offset:3225*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 3225*FLEN/8, x4, x1, x2)

inst_1076:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x348 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x147 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x0cd and fcsr == 0x20 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3b48; op2val:0x3947;
op3val:0x38cd; valaddr_reg:x3; val_offset:3228*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:32 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 32, 0, x3, 3228*FLEN/8, x4, x1, x2)

inst_1077:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x348 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x147 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x0cd and fcsr == 0x40 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3b48; op2val:0x3947;
op3val:0x38cd; valaddr_reg:x3; val_offset:3231*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:64 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 64, 0, x3, 3231*FLEN/8, x4, x1, x2)

inst_1078:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x348 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x147 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x0cd and fcsr == 0x60 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3b48; op2val:0x3947;
op3val:0x38cd; valaddr_reg:x3; val_offset:3234*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 96, 0, x3, 3234*FLEN/8, x4, x1, x2)

inst_1079:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x348 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x147 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x0cd and fcsr == 0x80 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3b48; op2val:0x3947;
op3val:0x38cd; valaddr_reg:x3; val_offset:3237*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:128 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 128, 0, x3, 3237*FLEN/8, x4, x1, x2)

inst_1080:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x3aa and fs2 == 0 and fe2 == 0x0f and fm2 == 0x014 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x3d1 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3baa; op2val:0x3c14;
op3val:0x3bd1; valaddr_reg:x3; val_offset:3240*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 3240*FLEN/8, x4, x1, x2)

inst_1081:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x3aa and fs2 == 0 and fe2 == 0x0f and fm2 == 0x014 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x3d1 and fcsr == 0x20 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3baa; op2val:0x3c14;
op3val:0x3bd1; valaddr_reg:x3; val_offset:3243*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:32 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 32, 0, x3, 3243*FLEN/8, x4, x1, x2)

inst_1082:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x3aa and fs2 == 0 and fe2 == 0x0f and fm2 == 0x014 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x3d1 and fcsr == 0x40 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3baa; op2val:0x3c14;
op3val:0x3bd1; valaddr_reg:x3; val_offset:3246*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:64 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 64, 0, x3, 3246*FLEN/8, x4, x1, x2)

inst_1083:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x3aa and fs2 == 0 and fe2 == 0x0f and fm2 == 0x014 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x3d1 and fcsr == 0x60 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3baa; op2val:0x3c14;
op3val:0x3bd1; valaddr_reg:x3; val_offset:3249*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 96, 0, x3, 3249*FLEN/8, x4, x1, x2)

inst_1084:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x3aa and fs2 == 0 and fe2 == 0x0f and fm2 == 0x014 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x3d1 and fcsr == 0x80 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3baa; op2val:0x3c14;
op3val:0x3bd1; valaddr_reg:x3; val_offset:3252*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:128 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 128, 0, x3, 3252*FLEN/8, x4, x1, x2)

inst_1085:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x190 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x069 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x223 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3990; op2val:0x3c69;
op3val:0x3a23; valaddr_reg:x3; val_offset:3255*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 3255*FLEN/8, x4, x1, x2)

inst_1086:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x190 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x069 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x223 and fcsr == 0x20 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3990; op2val:0x3c69;
op3val:0x3a23; valaddr_reg:x3; val_offset:3258*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:32 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 32, 0, x3, 3258*FLEN/8, x4, x1, x2)

inst_1087:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x190 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x069 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x223 and fcsr == 0x40 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3990; op2val:0x3c69;
op3val:0x3a23; valaddr_reg:x3; val_offset:3261*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:64 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 64, 0, x3, 3261*FLEN/8, x4, x1, x2)

inst_1088:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x190 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x069 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x223 and fcsr == 0x60 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3990; op2val:0x3c69;
op3val:0x3a23; valaddr_reg:x3; val_offset:3264*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 96, 0, x3, 3264*FLEN/8, x4, x1, x2)

inst_1089:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x190 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x069 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x223 and fcsr == 0x80 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3990; op2val:0x3c69;
op3val:0x3a23; valaddr_reg:x3; val_offset:3267*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:128 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 128, 0, x3, 3267*FLEN/8, x4, x1, x2)

inst_1090:
// fs1 == 0 and fe1 == 0x0d and fm1 == 0x2a1 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x08b and fs3 == 0 and fe3 == 0x0d and fm3 == 0x388 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x36a1; op2val:0x3c8b;
op3val:0x3788; valaddr_reg:x3; val_offset:3270*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 3270*FLEN/8, x4, x1, x2)

inst_1091:
// fs1 == 0 and fe1 == 0x0d and fm1 == 0x2a1 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x08b and fs3 == 0 and fe3 == 0x0d and fm3 == 0x388 and fcsr == 0x20 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x36a1; op2val:0x3c8b;
op3val:0x3788; valaddr_reg:x3; val_offset:3273*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:32 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 32, 0, x3, 3273*FLEN/8, x4, x1, x2)

inst_1092:
// fs1 == 0 and fe1 == 0x0d and fm1 == 0x2a1 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x08b and fs3 == 0 and fe3 == 0x0d and fm3 == 0x388 and fcsr == 0x40 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x36a1; op2val:0x3c8b;
op3val:0x3788; valaddr_reg:x3; val_offset:3276*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:64 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 64, 0, x3, 3276*FLEN/8, x4, x1, x2)

inst_1093:
// fs1 == 0 and fe1 == 0x0d and fm1 == 0x2a1 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x08b and fs3 == 0 and fe3 == 0x0d and fm3 == 0x388 and fcsr == 0x60 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x36a1; op2val:0x3c8b;
op3val:0x3788; valaddr_reg:x3; val_offset:3279*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 96, 0, x3, 3279*FLEN/8, x4, x1, x2)

inst_1094:
// fs1 == 0 and fe1 == 0x0d and fm1 == 0x2a1 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x08b and fs3 == 0 and fe3 == 0x0d and fm3 == 0x388 and fcsr == 0x80 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x36a1; op2val:0x3c8b;
op3val:0x3788; valaddr_reg:x3; val_offset:3282*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:128 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 128, 0, x3, 3282*FLEN/8, x4, x1, x2)

inst_1095:
// fs1 == 0 and fe1 == 0x0c and fm1 == 0x3fc and fs2 == 0 and fe2 == 0x0f and fm2 == 0x17d and fs3 == 0 and fe3 == 0x0d and fm3 == 0x17a and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x33fc; op2val:0x3d7d;
op3val:0x357a; valaddr_reg:x3; val_offset:3285*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 3285*FLEN/8, x4, x1, x2)

inst_1096:
// fs1 == 0 and fe1 == 0x0c and fm1 == 0x3fc and fs2 == 0 and fe2 == 0x0f and fm2 == 0x17d and fs3 == 0 and fe3 == 0x0d and fm3 == 0x17a and fcsr == 0x20 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x33fc; op2val:0x3d7d;
op3val:0x357a; valaddr_reg:x3; val_offset:3288*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:32 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 32, 0, x3, 3288*FLEN/8, x4, x1, x2)

inst_1097:
// fs1 == 0 and fe1 == 0x0c and fm1 == 0x3fc and fs2 == 0 and fe2 == 0x0f and fm2 == 0x17d and fs3 == 0 and fe3 == 0x0d and fm3 == 0x17a and fcsr == 0x40 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x33fc; op2val:0x3d7d;
op3val:0x357a; valaddr_reg:x3; val_offset:3291*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:64 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 64, 0, x3, 3291*FLEN/8, x4, x1, x2)

inst_1098:
// fs1 == 0 and fe1 == 0x0c and fm1 == 0x3fc and fs2 == 0 and fe2 == 0x0f and fm2 == 0x17d and fs3 == 0 and fe3 == 0x0d and fm3 == 0x17a and fcsr == 0x60 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x33fc; op2val:0x3d7d;
op3val:0x357a; valaddr_reg:x3; val_offset:3294*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 96, 0, x3, 3294*FLEN/8, x4, x1, x2)

inst_1099:
// fs1 == 0 and fe1 == 0x0c and fm1 == 0x3fc and fs2 == 0 and fe2 == 0x0f and fm2 == 0x17d and fs3 == 0 and fe3 == 0x0d and fm3 == 0x17a and fcsr == 0x80 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x33fc; op2val:0x3d7d;
op3val:0x357a; valaddr_reg:x3; val_offset:3297*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:128 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 128, 0, x3, 3297*FLEN/8, x4, x1, x2)

inst_1100:
// fs1 == 0 and fe1 == 0x0d and fm1 == 0x08b and fs2 == 0 and fe2 == 0x0d and fm2 == 0x2d1 and fs3 == 0 and fe3 == 0x0b and fm3 == 0x3be and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x348b; op2val:0x36d1;
op3val:0x2fbe; valaddr_reg:x3; val_offset:3300*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 3300*FLEN/8, x4, x1, x2)

inst_1101:
// fs1 == 0 and fe1 == 0x0d and fm1 == 0x08b and fs2 == 0 and fe2 == 0x0d and fm2 == 0x2d1 and fs3 == 0 and fe3 == 0x0b and fm3 == 0x3be and fcsr == 0x20 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x348b; op2val:0x36d1;
op3val:0x2fbe; valaddr_reg:x3; val_offset:3303*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:32 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 32, 0, x3, 3303*FLEN/8, x4, x1, x2)

inst_1102:
// fs1 == 0 and fe1 == 0x0d and fm1 == 0x08b and fs2 == 0 and fe2 == 0x0d and fm2 == 0x2d1 and fs3 == 0 and fe3 == 0x0b and fm3 == 0x3be and fcsr == 0x40 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x348b; op2val:0x36d1;
op3val:0x2fbe; valaddr_reg:x3; val_offset:3306*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:64 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 64, 0, x3, 3306*FLEN/8, x4, x1, x2)

inst_1103:
// fs1 == 0 and fe1 == 0x0d and fm1 == 0x08b and fs2 == 0 and fe2 == 0x0d and fm2 == 0x2d1 and fs3 == 0 and fe3 == 0x0b and fm3 == 0x3be and fcsr == 0x60 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x348b; op2val:0x36d1;
op3val:0x2fbe; valaddr_reg:x3; val_offset:3309*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 96, 0, x3, 3309*FLEN/8, x4, x1, x2)

inst_1104:
// fs1 == 0 and fe1 == 0x0d and fm1 == 0x08b and fs2 == 0 and fe2 == 0x0d and fm2 == 0x2d1 and fs3 == 0 and fe3 == 0x0b and fm3 == 0x3be and fcsr == 0x80 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x348b; op2val:0x36d1;
op3val:0x2fbe; valaddr_reg:x3; val_offset:3312*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:128 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 128, 0, x3, 3312*FLEN/8, x4, x1, x2)

inst_1105:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x0e2 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x06a and fs3 == 0 and fe3 == 0x0e and fm3 == 0x164 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x38e2; op2val:0x3c6a;
op3val:0x3964; valaddr_reg:x3; val_offset:3315*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 3315*FLEN/8, x4, x1, x2)

inst_1106:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x0e2 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x06a and fs3 == 0 and fe3 == 0x0e and fm3 == 0x164 and fcsr == 0x20 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x38e2; op2val:0x3c6a;
op3val:0x3964; valaddr_reg:x3; val_offset:3318*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:32 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 32, 0, x3, 3318*FLEN/8, x4, x1, x2)

inst_1107:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x0e2 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x06a and fs3 == 0 and fe3 == 0x0e and fm3 == 0x164 and fcsr == 0x40 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x38e2; op2val:0x3c6a;
op3val:0x3964; valaddr_reg:x3; val_offset:3321*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:64 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 64, 0, x3, 3321*FLEN/8, x4, x1, x2)

inst_1108:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x0e2 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x06a and fs3 == 0 and fe3 == 0x0e and fm3 == 0x164 and fcsr == 0x60 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x38e2; op2val:0x3c6a;
op3val:0x3964; valaddr_reg:x3; val_offset:3324*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 96, 0, x3, 3324*FLEN/8, x4, x1, x2)

inst_1109:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x0e2 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x06a and fs3 == 0 and fe3 == 0x0e and fm3 == 0x164 and fcsr == 0x80 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x38e2; op2val:0x3c6a;
op3val:0x3964; valaddr_reg:x3; val_offset:3327*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:128 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 128, 0, x3, 3327*FLEN/8, x4, x1, x2)

inst_1110:
// fs1 == 0 and fe1 == 0x08 and fm1 == 0x3da and fs2 == 0 and fe2 == 0x14 and fm2 == 0x2ee and fs3 == 0 and fe3 == 0x0e and fm3 == 0x2cd and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x23da; op2val:0x52ee;
op3val:0x3acd; valaddr_reg:x3; val_offset:3330*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 3330*FLEN/8, x4, x1, x2)

inst_1111:
// fs1 == 0 and fe1 == 0x08 and fm1 == 0x3da and fs2 == 0 and fe2 == 0x14 and fm2 == 0x2ee and fs3 == 0 and fe3 == 0x0e and fm3 == 0x2cd and fcsr == 0x20 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x23da; op2val:0x52ee;
op3val:0x3acd; valaddr_reg:x3; val_offset:3333*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:32 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 32, 0, x3, 3333*FLEN/8, x4, x1, x2)

inst_1112:
// fs1 == 0 and fe1 == 0x08 and fm1 == 0x3da and fs2 == 0 and fe2 == 0x14 and fm2 == 0x2ee and fs3 == 0 and fe3 == 0x0e and fm3 == 0x2cd and fcsr == 0x40 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x23da; op2val:0x52ee;
op3val:0x3acd; valaddr_reg:x3; val_offset:3336*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:64 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 64, 0, x3, 3336*FLEN/8, x4, x1, x2)

inst_1113:
// fs1 == 0 and fe1 == 0x08 and fm1 == 0x3da and fs2 == 0 and fe2 == 0x14 and fm2 == 0x2ee and fs3 == 0 and fe3 == 0x0e and fm3 == 0x2cd and fcsr == 0x60 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x23da; op2val:0x52ee;
op3val:0x3acd; valaddr_reg:x3; val_offset:3339*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 96, 0, x3, 3339*FLEN/8, x4, x1, x2)

inst_1114:
// fs1 == 0 and fe1 == 0x08 and fm1 == 0x3da and fs2 == 0 and fe2 == 0x14 and fm2 == 0x2ee and fs3 == 0 and fe3 == 0x0e and fm3 == 0x2cd and fcsr == 0x80 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x23da; op2val:0x52ee;
op3val:0x3acd; valaddr_reg:x3; val_offset:3342*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:128 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 128, 0, x3, 3342*FLEN/8, x4, x1, x2)

inst_1115:
// fs1 == 0 and fe1 == 0x0d and fm1 == 0x06a and fs2 == 0 and fe2 == 0x0f and fm2 == 0x12c and fs3 == 0 and fe3 == 0x0d and fm3 == 0x1b5 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x346a; op2val:0x3d2c;
op3val:0x35b5; valaddr_reg:x3; val_offset:3345*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 3345*FLEN/8, x4, x1, x2)

inst_1116:
// fs1 == 0 and fe1 == 0x0d and fm1 == 0x06a and fs2 == 0 and fe2 == 0x0f and fm2 == 0x12c and fs3 == 0 and fe3 == 0x0d and fm3 == 0x1b5 and fcsr == 0x20 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x346a; op2val:0x3d2c;
op3val:0x35b5; valaddr_reg:x3; val_offset:3348*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:32 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 32, 0, x3, 3348*FLEN/8, x4, x1, x2)

inst_1117:
// fs1 == 0 and fe1 == 0x0d and fm1 == 0x06a and fs2 == 0 and fe2 == 0x0f and fm2 == 0x12c and fs3 == 0 and fe3 == 0x0d and fm3 == 0x1b5 and fcsr == 0x40 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x346a; op2val:0x3d2c;
op3val:0x35b5; valaddr_reg:x3; val_offset:3351*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:64 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 64, 0, x3, 3351*FLEN/8, x4, x1, x2)

inst_1118:
// fs1 == 0 and fe1 == 0x0d and fm1 == 0x06a and fs2 == 0 and fe2 == 0x0f and fm2 == 0x12c and fs3 == 0 and fe3 == 0x0d and fm3 == 0x1b5 and fcsr == 0x60 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x346a; op2val:0x3d2c;
op3val:0x35b5; valaddr_reg:x3; val_offset:3354*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 96, 0, x3, 3354*FLEN/8, x4, x1, x2)

inst_1119:
// fs1 == 0 and fe1 == 0x0d and fm1 == 0x06a and fs2 == 0 and fe2 == 0x0f and fm2 == 0x12c and fs3 == 0 and fe3 == 0x0d and fm3 == 0x1b5 and fcsr == 0x80 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x346a; op2val:0x3d2c;
op3val:0x35b5; valaddr_reg:x3; val_offset:3357*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:128 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 128, 0, x3, 3357*FLEN/8, x4, x1, x2)

inst_1120:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x3a6 and fs2 == 0 and fe2 == 0x0c and fm2 == 0x184 and fs3 == 0 and fe3 == 0x0c and fm3 == 0x145 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3ba6; op2val:0x3184;
op3val:0x3145; valaddr_reg:x3; val_offset:3360*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 3360*FLEN/8, x4, x1, x2)

inst_1121:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x3a6 and fs2 == 0 and fe2 == 0x0c and fm2 == 0x184 and fs3 == 0 and fe3 == 0x0c and fm3 == 0x145 and fcsr == 0x20 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3ba6; op2val:0x3184;
op3val:0x3145; valaddr_reg:x3; val_offset:3363*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:32 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 32, 0, x3, 3363*FLEN/8, x4, x1, x2)

inst_1122:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x3a6 and fs2 == 0 and fe2 == 0x0c and fm2 == 0x184 and fs3 == 0 and fe3 == 0x0c and fm3 == 0x145 and fcsr == 0x40 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3ba6; op2val:0x3184;
op3val:0x3145; valaddr_reg:x3; val_offset:3366*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:64 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 64, 0, x3, 3366*FLEN/8, x4, x1, x2)

inst_1123:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x3a6 and fs2 == 0 and fe2 == 0x0c and fm2 == 0x184 and fs3 == 0 and fe3 == 0x0c and fm3 == 0x145 and fcsr == 0x60 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3ba6; op2val:0x3184;
op3val:0x3145; valaddr_reg:x3; val_offset:3369*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 96, 0, x3, 3369*FLEN/8, x4, x1, x2)

inst_1124:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x3a6 and fs2 == 0 and fe2 == 0x0c and fm2 == 0x184 and fs3 == 0 and fe3 == 0x0c and fm3 == 0x145 and fcsr == 0x80 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3ba6; op2val:0x3184;
op3val:0x3145; valaddr_reg:x3; val_offset:3372*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:128 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 128, 0, x3, 3372*FLEN/8, x4, x1, x2)

inst_1125:
// fs1 == 0 and fe1 == 0x0b and fm1 == 0x2eb and fs2 == 0 and fe2 == 0x10 and fm2 == 0x2e5 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x1f6 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x2eeb; op2val:0x42e5;
op3val:0x35f6; valaddr_reg:x3; val_offset:3375*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 3375*FLEN/8, x4, x1, x2)

inst_1126:
// fs1 == 0 and fe1 == 0x0b and fm1 == 0x2eb and fs2 == 0 and fe2 == 0x10 and fm2 == 0x2e5 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x1f6 and fcsr == 0x20 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x2eeb; op2val:0x42e5;
op3val:0x35f6; valaddr_reg:x3; val_offset:3378*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:32 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 32, 0, x3, 3378*FLEN/8, x4, x1, x2)

inst_1127:
// fs1 == 0 and fe1 == 0x0b and fm1 == 0x2eb and fs2 == 0 and fe2 == 0x10 and fm2 == 0x2e5 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x1f6 and fcsr == 0x40 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x2eeb; op2val:0x42e5;
op3val:0x35f6; valaddr_reg:x3; val_offset:3381*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:64 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 64, 0, x3, 3381*FLEN/8, x4, x1, x2)

inst_1128:
// fs1 == 0 and fe1 == 0x0b and fm1 == 0x2eb and fs2 == 0 and fe2 == 0x10 and fm2 == 0x2e5 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x1f6 and fcsr == 0x60 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x2eeb; op2val:0x42e5;
op3val:0x35f6; valaddr_reg:x3; val_offset:3384*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 96, 0, x3, 3384*FLEN/8, x4, x1, x2)

inst_1129:
// fs1 == 0 and fe1 == 0x0b and fm1 == 0x2eb and fs2 == 0 and fe2 == 0x10 and fm2 == 0x2e5 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x1f6 and fcsr == 0x80 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x2eeb; op2val:0x42e5;
op3val:0x35f6; valaddr_reg:x3; val_offset:3387*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:128 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 128, 0, x3, 3387*FLEN/8, x4, x1, x2)

inst_1130:
// fs1 == 0 and fe1 == 0x0d and fm1 == 0x042 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x1a5 and fs3 == 0 and fe3 == 0x0c and fm3 == 0x202 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3442; op2val:0x39a5;
op3val:0x3202; valaddr_reg:x3; val_offset:3390*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 3390*FLEN/8, x4, x1, x2)

inst_1131:
// fs1 == 0 and fe1 == 0x0d and fm1 == 0x042 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x1a5 and fs3 == 0 and fe3 == 0x0c and fm3 == 0x202 and fcsr == 0x20 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3442; op2val:0x39a5;
op3val:0x3202; valaddr_reg:x3; val_offset:3393*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:32 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 32, 0, x3, 3393*FLEN/8, x4, x1, x2)

inst_1132:
// fs1 == 0 and fe1 == 0x0d and fm1 == 0x042 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x1a5 and fs3 == 0 and fe3 == 0x0c and fm3 == 0x202 and fcsr == 0x40 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3442; op2val:0x39a5;
op3val:0x3202; valaddr_reg:x3; val_offset:3396*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:64 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 64, 0, x3, 3396*FLEN/8, x4, x1, x2)

inst_1133:
// fs1 == 0 and fe1 == 0x0d and fm1 == 0x042 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x1a5 and fs3 == 0 and fe3 == 0x0c and fm3 == 0x202 and fcsr == 0x60 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3442; op2val:0x39a5;
op3val:0x3202; valaddr_reg:x3; val_offset:3399*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 96, 0, x3, 3399*FLEN/8, x4, x1, x2)

inst_1134:
// fs1 == 0 and fe1 == 0x0d and fm1 == 0x042 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x1a5 and fs3 == 0 and fe3 == 0x0c and fm3 == 0x202 and fcsr == 0x80 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3442; op2val:0x39a5;
op3val:0x3202; valaddr_reg:x3; val_offset:3402*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:128 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 128, 0, x3, 3402*FLEN/8, x4, x1, x2)

inst_1135:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x2e2 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x06d and fs3 == 0 and fe3 == 0x0d and fm3 == 0x39e and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3ae2; op2val:0x386d;
op3val:0x379e; valaddr_reg:x3; val_offset:3405*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 3405*FLEN/8, x4, x1, x2)

inst_1136:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x2e2 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x06d and fs3 == 0 and fe3 == 0x0d and fm3 == 0x39e and fcsr == 0x20 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3ae2; op2val:0x386d;
op3val:0x379e; valaddr_reg:x3; val_offset:3408*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:32 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 32, 0, x3, 3408*FLEN/8, x4, x1, x2)

inst_1137:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x2e2 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x06d and fs3 == 0 and fe3 == 0x0d and fm3 == 0x39e and fcsr == 0x40 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3ae2; op2val:0x386d;
op3val:0x379e; valaddr_reg:x3; val_offset:3411*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:64 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 64, 0, x3, 3411*FLEN/8, x4, x1, x2)

inst_1138:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x2e2 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x06d and fs3 == 0 and fe3 == 0x0d and fm3 == 0x39e and fcsr == 0x60 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3ae2; op2val:0x386d;
op3val:0x379e; valaddr_reg:x3; val_offset:3414*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 96, 0, x3, 3414*FLEN/8, x4, x1, x2)

inst_1139:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x2e2 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x06d and fs3 == 0 and fe3 == 0x0d and fm3 == 0x39e and fcsr == 0x80 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3ae2; op2val:0x386d;
op3val:0x379e; valaddr_reg:x3; val_offset:3417*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:128 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 128, 0, x3, 3417*FLEN/8, x4, x1, x2)

inst_1140:
// fs1 == 0 and fe1 == 0x0d and fm1 == 0x3ee and fs2 == 0 and fe2 == 0x0d and fm2 == 0x155 and fs3 == 0 and fe3 == 0x0c and fm3 == 0x148 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x37ee; op2val:0x3555;
op3val:0x3148; valaddr_reg:x3; val_offset:3420*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 3420*FLEN/8, x4, x1, x2)

inst_1141:
// fs1 == 0 and fe1 == 0x0d and fm1 == 0x3ee and fs2 == 0 and fe2 == 0x0d and fm2 == 0x155 and fs3 == 0 and fe3 == 0x0c and fm3 == 0x148 and fcsr == 0x20 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x37ee; op2val:0x3555;
op3val:0x3148; valaddr_reg:x3; val_offset:3423*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:32 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 32, 0, x3, 3423*FLEN/8, x4, x1, x2)

inst_1142:
// fs1 == 0 and fe1 == 0x0d and fm1 == 0x3ee and fs2 == 0 and fe2 == 0x0d and fm2 == 0x155 and fs3 == 0 and fe3 == 0x0c and fm3 == 0x148 and fcsr == 0x40 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x37ee; op2val:0x3555;
op3val:0x3148; valaddr_reg:x3; val_offset:3426*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:64 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 64, 0, x3, 3426*FLEN/8, x4, x1, x2)

inst_1143:
// fs1 == 0 and fe1 == 0x0d and fm1 == 0x3ee and fs2 == 0 and fe2 == 0x0d and fm2 == 0x155 and fs3 == 0 and fe3 == 0x0c and fm3 == 0x148 and fcsr == 0x60 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x37ee; op2val:0x3555;
op3val:0x3148; valaddr_reg:x3; val_offset:3429*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 96, 0, x3, 3429*FLEN/8, x4, x1, x2)

inst_1144:
// fs1 == 0 and fe1 == 0x0d and fm1 == 0x3ee and fs2 == 0 and fe2 == 0x0d and fm2 == 0x155 and fs3 == 0 and fe3 == 0x0c and fm3 == 0x148 and fcsr == 0x80 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x37ee; op2val:0x3555;
op3val:0x3148; valaddr_reg:x3; val_offset:3432*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:128 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 128, 0, x3, 3432*FLEN/8, x4, x1, x2)

inst_1145:
// fs1 == 0 and fe1 == 0x0c and fm1 == 0x240 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x31c and fs3 == 0 and fe3 == 0x0c and fm3 == 0x18e and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3240; op2val:0x3b1c;
op3val:0x318e; valaddr_reg:x3; val_offset:3435*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 3435*FLEN/8, x4, x1, x2)

inst_1146:
// fs1 == 0 and fe1 == 0x0c and fm1 == 0x240 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x31c and fs3 == 0 and fe3 == 0x0c and fm3 == 0x18e and fcsr == 0x20 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3240; op2val:0x3b1c;
op3val:0x318e; valaddr_reg:x3; val_offset:3438*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:32 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 32, 0, x3, 3438*FLEN/8, x4, x1, x2)

inst_1147:
// fs1 == 0 and fe1 == 0x0c and fm1 == 0x240 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x31c and fs3 == 0 and fe3 == 0x0c and fm3 == 0x18e and fcsr == 0x40 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3240; op2val:0x3b1c;
op3val:0x318e; valaddr_reg:x3; val_offset:3441*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:64 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 64, 0, x3, 3441*FLEN/8, x4, x1, x2)

inst_1148:
// fs1 == 0 and fe1 == 0x0c and fm1 == 0x240 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x31c and fs3 == 0 and fe3 == 0x0c and fm3 == 0x18e and fcsr == 0x60 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3240; op2val:0x3b1c;
op3val:0x318e; valaddr_reg:x3; val_offset:3444*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 96, 0, x3, 3444*FLEN/8, x4, x1, x2)

inst_1149:
// fs1 == 0 and fe1 == 0x0c and fm1 == 0x240 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x31c and fs3 == 0 and fe3 == 0x0c and fm3 == 0x18e and fcsr == 0x80 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3240; op2val:0x3b1c;
op3val:0x318e; valaddr_reg:x3; val_offset:3447*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:128 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 128, 0, x3, 3447*FLEN/8, x4, x1, x2)

inst_1150:
// fs1 == 0 and fe1 == 0x0d and fm1 == 0x2a7 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x020 and fs3 == 0 and fe3 == 0x0b and fm3 == 0x2dc and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x36a7; op2val:0x3420;
op3val:0x2edc; valaddr_reg:x3; val_offset:3450*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 3450*FLEN/8, x4, x1, x2)

inst_1151:
// fs1 == 0 and fe1 == 0x0d and fm1 == 0x2a7 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x020 and fs3 == 0 and fe3 == 0x0b and fm3 == 0x2dc and fcsr == 0x20 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x36a7; op2val:0x3420;
op3val:0x2edc; valaddr_reg:x3; val_offset:3453*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:32 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 32, 0, x3, 3453*FLEN/8, x4, x1, x2)
RVTEST_SIGBASE(x1,signature_x1_10)

inst_1152:
// fs1 == 0 and fe1 == 0x0d and fm1 == 0x2a7 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x020 and fs3 == 0 and fe3 == 0x0b and fm3 == 0x2dc and fcsr == 0x40 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x36a7; op2val:0x3420;
op3val:0x2edc; valaddr_reg:x3; val_offset:3456*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:64 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 64, 0, x3, 3456*FLEN/8, x4, x1, x2)

inst_1153:
// fs1 == 0 and fe1 == 0x0d and fm1 == 0x2a7 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x020 and fs3 == 0 and fe3 == 0x0b and fm3 == 0x2dc and fcsr == 0x60 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x36a7; op2val:0x3420;
op3val:0x2edc; valaddr_reg:x3; val_offset:3459*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 96, 0, x3, 3459*FLEN/8, x4, x1, x2)

inst_1154:
// fs1 == 0 and fe1 == 0x0d and fm1 == 0x2a7 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x020 and fs3 == 0 and fe3 == 0x0b and fm3 == 0x2dc and fcsr == 0x80 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x36a7; op2val:0x3420;
op3val:0x2edc; valaddr_reg:x3; val_offset:3462*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:128 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 128, 0, x3, 3462*FLEN/8, x4, x1, x2)

inst_1155:
// fs1 == 0 and fe1 == 0x0d and fm1 == 0x113 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x3bd and fs3 == 0 and fe3 == 0x0d and fm3 == 0x0e8 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3513; op2val:0x3bbd;
op3val:0x34e8; valaddr_reg:x3; val_offset:3465*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 3465*FLEN/8, x4, x1, x2)

inst_1156:
// fs1 == 0 and fe1 == 0x0d and fm1 == 0x113 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x3bd and fs3 == 0 and fe3 == 0x0d and fm3 == 0x0e8 and fcsr == 0x20 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3513; op2val:0x3bbd;
op3val:0x34e8; valaddr_reg:x3; val_offset:3468*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:32 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 32, 0, x3, 3468*FLEN/8, x4, x1, x2)

inst_1157:
// fs1 == 0 and fe1 == 0x0d and fm1 == 0x113 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x3bd and fs3 == 0 and fe3 == 0x0d and fm3 == 0x0e8 and fcsr == 0x40 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3513; op2val:0x3bbd;
op3val:0x34e8; valaddr_reg:x3; val_offset:3471*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:64 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 64, 0, x3, 3471*FLEN/8, x4, x1, x2)

inst_1158:
// fs1 == 0 and fe1 == 0x0d and fm1 == 0x113 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x3bd and fs3 == 0 and fe3 == 0x0d and fm3 == 0x0e8 and fcsr == 0x60 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3513; op2val:0x3bbd;
op3val:0x34e8; valaddr_reg:x3; val_offset:3474*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 96, 0, x3, 3474*FLEN/8, x4, x1, x2)

inst_1159:
// fs1 == 0 and fe1 == 0x0d and fm1 == 0x113 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x3bd and fs3 == 0 and fe3 == 0x0d and fm3 == 0x0e8 and fcsr == 0x80 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3513; op2val:0x3bbd;
op3val:0x34e8; valaddr_reg:x3; val_offset:3477*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:128 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 128, 0, x3, 3477*FLEN/8, x4, x1, x2)

inst_1160:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x229 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x108 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x3c0 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3a29; op2val:0x3d08;
op3val:0x3bc0; valaddr_reg:x3; val_offset:3480*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 3480*FLEN/8, x4, x1, x2)

inst_1161:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x229 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x108 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x3c0 and fcsr == 0x20 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3a29; op2val:0x3d08;
op3val:0x3bc0; valaddr_reg:x3; val_offset:3483*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:32 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 32, 0, x3, 3483*FLEN/8, x4, x1, x2)

inst_1162:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x229 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x108 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x3c0 and fcsr == 0x40 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3a29; op2val:0x3d08;
op3val:0x3bc0; valaddr_reg:x3; val_offset:3486*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:64 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 64, 0, x3, 3486*FLEN/8, x4, x1, x2)

inst_1163:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x229 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x108 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x3c0 and fcsr == 0x60 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3a29; op2val:0x3d08;
op3val:0x3bc0; valaddr_reg:x3; val_offset:3489*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 96, 0, x3, 3489*FLEN/8, x4, x1, x2)

inst_1164:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x229 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x108 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x3c0 and fcsr == 0x80 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3a29; op2val:0x3d08;
op3val:0x3bc0; valaddr_reg:x3; val_offset:3492*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:128 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 128, 0, x3, 3492*FLEN/8, x4, x1, x2)

inst_1165:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x2ef and fs2 == 0 and fe2 == 0x0e and fm2 == 0x1e6 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x11d and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3aef; op2val:0x39e6;
op3val:0x391d; valaddr_reg:x3; val_offset:3495*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 3495*FLEN/8, x4, x1, x2)

inst_1166:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x2ef and fs2 == 0 and fe2 == 0x0e and fm2 == 0x1e6 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x11d and fcsr == 0x20 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3aef; op2val:0x39e6;
op3val:0x391d; valaddr_reg:x3; val_offset:3498*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:32 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 32, 0, x3, 3498*FLEN/8, x4, x1, x2)

inst_1167:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x2ef and fs2 == 0 and fe2 == 0x0e and fm2 == 0x1e6 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x11d and fcsr == 0x40 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3aef; op2val:0x39e6;
op3val:0x391d; valaddr_reg:x3; val_offset:3501*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:64 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 64, 0, x3, 3501*FLEN/8, x4, x1, x2)

inst_1168:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x2ef and fs2 == 0 and fe2 == 0x0e and fm2 == 0x1e6 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x11d and fcsr == 0x60 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3aef; op2val:0x39e6;
op3val:0x391d; valaddr_reg:x3; val_offset:3504*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 96, 0, x3, 3504*FLEN/8, x4, x1, x2)

inst_1169:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x2ef and fs2 == 0 and fe2 == 0x0e and fm2 == 0x1e6 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x11d and fcsr == 0x80 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3aef; op2val:0x39e6;
op3val:0x391d; valaddr_reg:x3; val_offset:3507*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:128 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 128, 0, x3, 3507*FLEN/8, x4, x1, x2)

inst_1170:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x329 and fs2 == 0 and fe2 == 0x0c and fm2 == 0x1df and fs3 == 0 and fe3 == 0x0c and fm3 == 0x141 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3b29; op2val:0x31df;
op3val:0x3141; valaddr_reg:x3; val_offset:3510*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 3510*FLEN/8, x4, x1, x2)

inst_1171:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x329 and fs2 == 0 and fe2 == 0x0c and fm2 == 0x1df and fs3 == 0 and fe3 == 0x0c and fm3 == 0x141 and fcsr == 0x20 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3b29; op2val:0x31df;
op3val:0x3141; valaddr_reg:x3; val_offset:3513*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:32 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 32, 0, x3, 3513*FLEN/8, x4, x1, x2)

inst_1172:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x329 and fs2 == 0 and fe2 == 0x0c and fm2 == 0x1df and fs3 == 0 and fe3 == 0x0c and fm3 == 0x141 and fcsr == 0x40 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3b29; op2val:0x31df;
op3val:0x3141; valaddr_reg:x3; val_offset:3516*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:64 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 64, 0, x3, 3516*FLEN/8, x4, x1, x2)

inst_1173:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x329 and fs2 == 0 and fe2 == 0x0c and fm2 == 0x1df and fs3 == 0 and fe3 == 0x0c and fm3 == 0x141 and fcsr == 0x60 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3b29; op2val:0x31df;
op3val:0x3141; valaddr_reg:x3; val_offset:3519*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 96, 0, x3, 3519*FLEN/8, x4, x1, x2)

inst_1174:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x329 and fs2 == 0 and fe2 == 0x0c and fm2 == 0x1df and fs3 == 0 and fe3 == 0x0c and fm3 == 0x141 and fcsr == 0x80 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3b29; op2val:0x31df;
op3val:0x3141; valaddr_reg:x3; val_offset:3522*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:128 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 128, 0, x3, 3522*FLEN/8, x4, x1, x2)

inst_1175:
// fs1 == 0 and fe1 == 0x0d and fm1 == 0x310 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x2bf and fs3 == 0 and fe3 == 0x0d and fm3 == 0x1f4 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3710; op2val:0x3abf;
op3val:0x35f4; valaddr_reg:x3; val_offset:3525*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 3525*FLEN/8, x4, x1, x2)

inst_1176:
// fs1 == 0 and fe1 == 0x0d and fm1 == 0x310 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x2bf and fs3 == 0 and fe3 == 0x0d and fm3 == 0x1f4 and fcsr == 0x20 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3710; op2val:0x3abf;
op3val:0x35f4; valaddr_reg:x3; val_offset:3528*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:32 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 32, 0, x3, 3528*FLEN/8, x4, x1, x2)

inst_1177:
// fs1 == 0 and fe1 == 0x0d and fm1 == 0x310 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x2bf and fs3 == 0 and fe3 == 0x0d and fm3 == 0x1f4 and fcsr == 0x40 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3710; op2val:0x3abf;
op3val:0x35f4; valaddr_reg:x3; val_offset:3531*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:64 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 64, 0, x3, 3531*FLEN/8, x4, x1, x2)

inst_1178:
// fs1 == 0 and fe1 == 0x0d and fm1 == 0x310 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x2bf and fs3 == 0 and fe3 == 0x0d and fm3 == 0x1f4 and fcsr == 0x60 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3710; op2val:0x3abf;
op3val:0x35f4; valaddr_reg:x3; val_offset:3534*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 96, 0, x3, 3534*FLEN/8, x4, x1, x2)

inst_1179:
// fs1 == 0 and fe1 == 0x0d and fm1 == 0x310 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x2bf and fs3 == 0 and fe3 == 0x0d and fm3 == 0x1f4 and fcsr == 0x80 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3710; op2val:0x3abf;
op3val:0x35f4; valaddr_reg:x3; val_offset:3537*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:128 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 128, 0, x3, 3537*FLEN/8, x4, x1, x2)

inst_1180:
// fs1 == 0 and fe1 == 0x0d and fm1 == 0x1fb and fs2 == 0 and fe2 == 0x0e and fm2 == 0x2d6 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x11c and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x35fb; op2val:0x3ad6;
op3val:0x351c; valaddr_reg:x3; val_offset:3540*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 3540*FLEN/8, x4, x1, x2)

inst_1181:
// fs1 == 0 and fe1 == 0x0d and fm1 == 0x1fb and fs2 == 0 and fe2 == 0x0e and fm2 == 0x2d6 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x11c and fcsr == 0x20 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x35fb; op2val:0x3ad6;
op3val:0x351c; valaddr_reg:x3; val_offset:3543*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:32 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 32, 0, x3, 3543*FLEN/8, x4, x1, x2)

inst_1182:
// fs1 == 0 and fe1 == 0x0d and fm1 == 0x1fb and fs2 == 0 and fe2 == 0x0e and fm2 == 0x2d6 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x11c and fcsr == 0x40 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x35fb; op2val:0x3ad6;
op3val:0x351c; valaddr_reg:x3; val_offset:3546*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:64 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 64, 0, x3, 3546*FLEN/8, x4, x1, x2)

inst_1183:
// fs1 == 0 and fe1 == 0x0d and fm1 == 0x1fb and fs2 == 0 and fe2 == 0x0e and fm2 == 0x2d6 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x11c and fcsr == 0x60 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x35fb; op2val:0x3ad6;
op3val:0x351c; valaddr_reg:x3; val_offset:3549*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 96, 0, x3, 3549*FLEN/8, x4, x1, x2)

inst_1184:
// fs1 == 0 and fe1 == 0x0d and fm1 == 0x1fb and fs2 == 0 and fe2 == 0x0e and fm2 == 0x2d6 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x11c and fcsr == 0x80 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x35fb; op2val:0x3ad6;
op3val:0x351c; valaddr_reg:x3; val_offset:3552*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:128 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 128, 0, x3, 3552*FLEN/8, x4, x1, x2)

inst_1185:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x015 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x3ce and fs3 == 0 and fe3 == 0x0e and fm3 == 0x3f9 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3815; op2val:0x3fce;
op3val:0x3bf9; valaddr_reg:x3; val_offset:3555*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 3555*FLEN/8, x4, x1, x2)

inst_1186:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x015 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x3ce and fs3 == 0 and fe3 == 0x0e and fm3 == 0x3f9 and fcsr == 0x20 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3815; op2val:0x3fce;
op3val:0x3bf9; valaddr_reg:x3; val_offset:3558*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:32 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 32, 0, x3, 3558*FLEN/8, x4, x1, x2)

inst_1187:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x015 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x3ce and fs3 == 0 and fe3 == 0x0e and fm3 == 0x3f9 and fcsr == 0x40 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3815; op2val:0x3fce;
op3val:0x3bf9; valaddr_reg:x3; val_offset:3561*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:64 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 64, 0, x3, 3561*FLEN/8, x4, x1, x2)

inst_1188:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x015 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x3ce and fs3 == 0 and fe3 == 0x0e and fm3 == 0x3f9 and fcsr == 0x60 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3815; op2val:0x3fce;
op3val:0x3bf9; valaddr_reg:x3; val_offset:3564*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 96, 0, x3, 3564*FLEN/8, x4, x1, x2)

inst_1189:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x015 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x3ce and fs3 == 0 and fe3 == 0x0e and fm3 == 0x3f9 and fcsr == 0x80 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3815; op2val:0x3fce;
op3val:0x3bf9; valaddr_reg:x3; val_offset:3567*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:128 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 128, 0, x3, 3567*FLEN/8, x4, x1, x2)

inst_1190:
// fs1 == 0 and fe1 == 0x0c and fm1 == 0x279 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x0fa and fs3 == 0 and fe3 == 0x0d and fm3 == 0x007 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3279; op2val:0x3cfa;
op3val:0x3407; valaddr_reg:x3; val_offset:3570*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 3570*FLEN/8, x4, x1, x2)

inst_1191:
// fs1 == 0 and fe1 == 0x0c and fm1 == 0x279 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x0fa and fs3 == 0 and fe3 == 0x0d and fm3 == 0x007 and fcsr == 0x20 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3279; op2val:0x3cfa;
op3val:0x3407; valaddr_reg:x3; val_offset:3573*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:32 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 32, 0, x3, 3573*FLEN/8, x4, x1, x2)

inst_1192:
// fs1 == 0 and fe1 == 0x0c and fm1 == 0x279 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x0fa and fs3 == 0 and fe3 == 0x0d and fm3 == 0x007 and fcsr == 0x40 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3279; op2val:0x3cfa;
op3val:0x3407; valaddr_reg:x3; val_offset:3576*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:64 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 64, 0, x3, 3576*FLEN/8, x4, x1, x2)

inst_1193:
// fs1 == 0 and fe1 == 0x0c and fm1 == 0x279 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x0fa and fs3 == 0 and fe3 == 0x0d and fm3 == 0x007 and fcsr == 0x60 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3279; op2val:0x3cfa;
op3val:0x3407; valaddr_reg:x3; val_offset:3579*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 96, 0, x3, 3579*FLEN/8, x4, x1, x2)

inst_1194:
// fs1 == 0 and fe1 == 0x0c and fm1 == 0x279 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x0fa and fs3 == 0 and fe3 == 0x0d and fm3 == 0x007 and fcsr == 0x80 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3279; op2val:0x3cfa;
op3val:0x3407; valaddr_reg:x3; val_offset:3582*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:128 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 128, 0, x3, 3582*FLEN/8, x4, x1, x2)

inst_1195:
// fs1 == 0 and fe1 == 0x0d and fm1 == 0x3f3 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x37b and fs3 == 0 and fe3 == 0x0d and fm3 == 0x36f and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x37f3; op2val:0x3b7b;
op3val:0x376f; valaddr_reg:x3; val_offset:3585*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 3585*FLEN/8, x4, x1, x2)

inst_1196:
// fs1 == 0 and fe1 == 0x0d and fm1 == 0x3f3 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x37b and fs3 == 0 and fe3 == 0x0d and fm3 == 0x36f and fcsr == 0x20 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x37f3; op2val:0x3b7b;
op3val:0x376f; valaddr_reg:x3; val_offset:3588*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:32 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 32, 0, x3, 3588*FLEN/8, x4, x1, x2)

inst_1197:
// fs1 == 0 and fe1 == 0x0d and fm1 == 0x3f3 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x37b and fs3 == 0 and fe3 == 0x0d and fm3 == 0x36f and fcsr == 0x40 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x37f3; op2val:0x3b7b;
op3val:0x376f; valaddr_reg:x3; val_offset:3591*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:64 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 64, 0, x3, 3591*FLEN/8, x4, x1, x2)

inst_1198:
// fs1 == 0 and fe1 == 0x0d and fm1 == 0x3f3 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x37b and fs3 == 0 and fe3 == 0x0d and fm3 == 0x36f and fcsr == 0x60 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x37f3; op2val:0x3b7b;
op3val:0x376f; valaddr_reg:x3; val_offset:3594*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 96, 0, x3, 3594*FLEN/8, x4, x1, x2)

inst_1199:
// fs1 == 0 and fe1 == 0x0d and fm1 == 0x3f3 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x37b and fs3 == 0 and fe3 == 0x0d and fm3 == 0x36f and fcsr == 0x80 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x37f3; op2val:0x3b7b;
op3val:0x376f; valaddr_reg:x3; val_offset:3597*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:128 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 128, 0, x3, 3597*FLEN/8, x4, x1, x2)

inst_1200:
// fs1 == 0 and fe1 == 0x0d and fm1 == 0x173 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x17b and fs3 == 0 and fe3 == 0x0e and fm3 == 0x378 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3573; op2val:0x417b;
op3val:0x3b78; valaddr_reg:x3; val_offset:3600*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 3600*FLEN/8, x4, x1, x2)

inst_1201:
// fs1 == 0 and fe1 == 0x0d and fm1 == 0x173 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x17b and fs3 == 0 and fe3 == 0x0e and fm3 == 0x378 and fcsr == 0x20 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3573; op2val:0x417b;
op3val:0x3b78; valaddr_reg:x3; val_offset:3603*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:32 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 32, 0, x3, 3603*FLEN/8, x4, x1, x2)

inst_1202:
// fs1 == 0 and fe1 == 0x0d and fm1 == 0x173 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x17b and fs3 == 0 and fe3 == 0x0e and fm3 == 0x378 and fcsr == 0x40 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3573; op2val:0x417b;
op3val:0x3b78; valaddr_reg:x3; val_offset:3606*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:64 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 64, 0, x3, 3606*FLEN/8, x4, x1, x2)

inst_1203:
// fs1 == 0 and fe1 == 0x0d and fm1 == 0x173 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x17b and fs3 == 0 and fe3 == 0x0e and fm3 == 0x378 and fcsr == 0x60 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3573; op2val:0x417b;
op3val:0x3b78; valaddr_reg:x3; val_offset:3609*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 96, 0, x3, 3609*FLEN/8, x4, x1, x2)

inst_1204:
// fs1 == 0 and fe1 == 0x0d and fm1 == 0x173 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x17b and fs3 == 0 and fe3 == 0x0e and fm3 == 0x378 and fcsr == 0x80 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3573; op2val:0x417b;
op3val:0x3b78; valaddr_reg:x3; val_offset:3612*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:128 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 128, 0, x3, 3612*FLEN/8, x4, x1, x2)

inst_1205:
// fs1 == 0 and fe1 == 0x0d and fm1 == 0x036 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x1ae and fs3 == 0 and fe3 == 0x0e and fm3 == 0x1fb and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3436; op2val:0x41ae;
op3val:0x39fb; valaddr_reg:x3; val_offset:3615*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 3615*FLEN/8, x4, x1, x2)

inst_1206:
// fs1 == 0 and fe1 == 0x0d and fm1 == 0x036 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x1ae and fs3 == 0 and fe3 == 0x0e and fm3 == 0x1fb and fcsr == 0x20 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3436; op2val:0x41ae;
op3val:0x39fb; valaddr_reg:x3; val_offset:3618*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:32 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 32, 0, x3, 3618*FLEN/8, x4, x1, x2)

inst_1207:
// fs1 == 0 and fe1 == 0x0d and fm1 == 0x036 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x1ae and fs3 == 0 and fe3 == 0x0e and fm3 == 0x1fb and fcsr == 0x40 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3436; op2val:0x41ae;
op3val:0x39fb; valaddr_reg:x3; val_offset:3621*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:64 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 64, 0, x3, 3621*FLEN/8, x4, x1, x2)

inst_1208:
// fs1 == 0 and fe1 == 0x0d and fm1 == 0x036 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x1ae and fs3 == 0 and fe3 == 0x0e and fm3 == 0x1fb and fcsr == 0x60 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3436; op2val:0x41ae;
op3val:0x39fb; valaddr_reg:x3; val_offset:3624*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 96, 0, x3, 3624*FLEN/8, x4, x1, x2)

inst_1209:
// fs1 == 0 and fe1 == 0x0d and fm1 == 0x036 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x1ae and fs3 == 0 and fe3 == 0x0e and fm3 == 0x1fb and fcsr == 0x80 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3436; op2val:0x41ae;
op3val:0x39fb; valaddr_reg:x3; val_offset:3627*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:128 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 128, 0, x3, 3627*FLEN/8, x4, x1, x2)

inst_1210:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x367 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x259 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x1e0 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3b67; op2val:0x3a59;
op3val:0x39e0; valaddr_reg:x3; val_offset:3630*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 3630*FLEN/8, x4, x1, x2)

inst_1211:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x367 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x259 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x1e0 and fcsr == 0x20 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3b67; op2val:0x3a59;
op3val:0x39e0; valaddr_reg:x3; val_offset:3633*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:32 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 32, 0, x3, 3633*FLEN/8, x4, x1, x2)

inst_1212:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x367 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x259 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x1e0 and fcsr == 0x40 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3b67; op2val:0x3a59;
op3val:0x39e0; valaddr_reg:x3; val_offset:3636*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:64 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 64, 0, x3, 3636*FLEN/8, x4, x1, x2)

inst_1213:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x367 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x259 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x1e0 and fcsr == 0x60 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3b67; op2val:0x3a59;
op3val:0x39e0; valaddr_reg:x3; val_offset:3639*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 96, 0, x3, 3639*FLEN/8, x4, x1, x2)

inst_1214:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x367 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x259 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x1e0 and fcsr == 0x80 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3b67; op2val:0x3a59;
op3val:0x39e0; valaddr_reg:x3; val_offset:3642*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:128 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 128, 0, x3, 3642*FLEN/8, x4, x1, x2)

inst_1215:
// fs1 == 0 and fe1 == 0x0d and fm1 == 0x054 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x1df and fs3 == 0 and fe3 == 0x0e and fm3 == 0x25b and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3454; op2val:0x41df;
op3val:0x3a5b; valaddr_reg:x3; val_offset:3645*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 3645*FLEN/8, x4, x1, x2)

inst_1216:
// fs1 == 0 and fe1 == 0x0d and fm1 == 0x054 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x1df and fs3 == 0 and fe3 == 0x0e and fm3 == 0x25b and fcsr == 0x20 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3454; op2val:0x41df;
op3val:0x3a5b; valaddr_reg:x3; val_offset:3648*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:32 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 32, 0, x3, 3648*FLEN/8, x4, x1, x2)

inst_1217:
// fs1 == 0 and fe1 == 0x0d and fm1 == 0x054 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x1df and fs3 == 0 and fe3 == 0x0e and fm3 == 0x25b and fcsr == 0x40 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3454; op2val:0x41df;
op3val:0x3a5b; valaddr_reg:x3; val_offset:3651*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:64 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 64, 0, x3, 3651*FLEN/8, x4, x1, x2)

inst_1218:
// fs1 == 0 and fe1 == 0x0d and fm1 == 0x054 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x1df and fs3 == 0 and fe3 == 0x0e and fm3 == 0x25b and fcsr == 0x60 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3454; op2val:0x41df;
op3val:0x3a5b; valaddr_reg:x3; val_offset:3654*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 96, 0, x3, 3654*FLEN/8, x4, x1, x2)

inst_1219:
// fs1 == 0 and fe1 == 0x0d and fm1 == 0x054 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x1df and fs3 == 0 and fe3 == 0x0e and fm3 == 0x25b and fcsr == 0x80 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3454; op2val:0x41df;
op3val:0x3a5b; valaddr_reg:x3; val_offset:3657*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:128 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 128, 0, x3, 3657*FLEN/8, x4, x1, x2)

inst_1220:
// fs1 == 0 and fe1 == 0x0d and fm1 == 0x029 and fs2 == 0 and fe2 == 0x0b and fm2 == 0x200 and fs3 == 0 and fe3 == 0x09 and fm3 == 0x23a and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3429; op2val:0x2e00;
op3val:0x263a; valaddr_reg:x3; val_offset:3660*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 3660*FLEN/8, x4, x1, x2)

inst_1221:
// fs1 == 0 and fe1 == 0x0d and fm1 == 0x029 and fs2 == 0 and fe2 == 0x0b and fm2 == 0x200 and fs3 == 0 and fe3 == 0x09 and fm3 == 0x23a and fcsr == 0x20 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3429; op2val:0x2e00;
op3val:0x263a; valaddr_reg:x3; val_offset:3663*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:32 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 32, 0, x3, 3663*FLEN/8, x4, x1, x2)

inst_1222:
// fs1 == 0 and fe1 == 0x0d and fm1 == 0x029 and fs2 == 0 and fe2 == 0x0b and fm2 == 0x200 and fs3 == 0 and fe3 == 0x09 and fm3 == 0x23a and fcsr == 0x40 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3429; op2val:0x2e00;
op3val:0x263a; valaddr_reg:x3; val_offset:3666*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:64 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 64, 0, x3, 3666*FLEN/8, x4, x1, x2)

inst_1223:
// fs1 == 0 and fe1 == 0x0d and fm1 == 0x029 and fs2 == 0 and fe2 == 0x0b and fm2 == 0x200 and fs3 == 0 and fe3 == 0x09 and fm3 == 0x23a and fcsr == 0x60 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3429; op2val:0x2e00;
op3val:0x263a; valaddr_reg:x3; val_offset:3669*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 96, 0, x3, 3669*FLEN/8, x4, x1, x2)

inst_1224:
// fs1 == 0 and fe1 == 0x0d and fm1 == 0x029 and fs2 == 0 and fe2 == 0x0b and fm2 == 0x200 and fs3 == 0 and fe3 == 0x09 and fm3 == 0x23a and fcsr == 0x80 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3429; op2val:0x2e00;
op3val:0x263a; valaddr_reg:x3; val_offset:3672*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:128 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 128, 0, x3, 3672*FLEN/8, x4, x1, x2)

inst_1225:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x00c and fs2 == 0 and fe2 == 0x0f and fm2 == 0x0e1 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x0f0 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x380c; op2val:0x3ce1;
op3val:0x38f0; valaddr_reg:x3; val_offset:3675*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 3675*FLEN/8, x4, x1, x2)

inst_1226:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x00c and fs2 == 0 and fe2 == 0x0f and fm2 == 0x0e1 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x0f0 and fcsr == 0x20 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x380c; op2val:0x3ce1;
op3val:0x38f0; valaddr_reg:x3; val_offset:3678*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:32 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 32, 0, x3, 3678*FLEN/8, x4, x1, x2)

inst_1227:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x00c and fs2 == 0 and fe2 == 0x0f and fm2 == 0x0e1 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x0f0 and fcsr == 0x40 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x380c; op2val:0x3ce1;
op3val:0x38f0; valaddr_reg:x3; val_offset:3681*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:64 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 64, 0, x3, 3681*FLEN/8, x4, x1, x2)

inst_1228:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x00c and fs2 == 0 and fe2 == 0x0f and fm2 == 0x0e1 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x0f0 and fcsr == 0x60 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x380c; op2val:0x3ce1;
op3val:0x38f0; valaddr_reg:x3; val_offset:3684*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 96, 0, x3, 3684*FLEN/8, x4, x1, x2)

inst_1229:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x00c and fs2 == 0 and fe2 == 0x0f and fm2 == 0x0e1 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x0f0 and fcsr == 0x80 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x380c; op2val:0x3ce1;
op3val:0x38f0; valaddr_reg:x3; val_offset:3687*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:128 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 128, 0, x3, 3687*FLEN/8, x4, x1, x2)

inst_1230:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x02b and fs2 == 0 and fe2 == 0x0e and fm2 == 0x0db and fs3 == 0 and fe3 == 0x0d and fm3 == 0x10f and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x382b; op2val:0x38db;
op3val:0x350f; valaddr_reg:x3; val_offset:3690*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 3690*FLEN/8, x4, x1, x2)

inst_1231:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x02b and fs2 == 0 and fe2 == 0x0e and fm2 == 0x0db and fs3 == 0 and fe3 == 0x0d and fm3 == 0x10f and fcsr == 0x20 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x382b; op2val:0x38db;
op3val:0x350f; valaddr_reg:x3; val_offset:3693*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:32 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 32, 0, x3, 3693*FLEN/8, x4, x1, x2)

inst_1232:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x02b and fs2 == 0 and fe2 == 0x0e and fm2 == 0x0db and fs3 == 0 and fe3 == 0x0d and fm3 == 0x10f and fcsr == 0x40 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x382b; op2val:0x38db;
op3val:0x350f; valaddr_reg:x3; val_offset:3696*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:64 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 64, 0, x3, 3696*FLEN/8, x4, x1, x2)

inst_1233:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x02b and fs2 == 0 and fe2 == 0x0e and fm2 == 0x0db and fs3 == 0 and fe3 == 0x0d and fm3 == 0x10f and fcsr == 0x60 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x382b; op2val:0x38db;
op3val:0x350f; valaddr_reg:x3; val_offset:3699*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 96, 0, x3, 3699*FLEN/8, x4, x1, x2)

inst_1234:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x02b and fs2 == 0 and fe2 == 0x0e and fm2 == 0x0db and fs3 == 0 and fe3 == 0x0d and fm3 == 0x10f and fcsr == 0x80 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x382b; op2val:0x38db;
op3val:0x350f; valaddr_reg:x3; val_offset:3702*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:128 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 128, 0, x3, 3702*FLEN/8, x4, x1, x2)

inst_1235:
// fs1 == 0 and fe1 == 0x0c and fm1 == 0x375 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x293 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x221 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3375; op2val:0x3e93;
op3val:0x3621; valaddr_reg:x3; val_offset:3705*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 3705*FLEN/8, x4, x1, x2)

inst_1236:
// fs1 == 0 and fe1 == 0x0c and fm1 == 0x375 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x293 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x221 and fcsr == 0x20 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3375; op2val:0x3e93;
op3val:0x3621; valaddr_reg:x3; val_offset:3708*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:32 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 32, 0, x3, 3708*FLEN/8, x4, x1, x2)

inst_1237:
// fs1 == 0 and fe1 == 0x0c and fm1 == 0x375 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x293 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x221 and fcsr == 0x40 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3375; op2val:0x3e93;
op3val:0x3621; valaddr_reg:x3; val_offset:3711*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:64 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 64, 0, x3, 3711*FLEN/8, x4, x1, x2)

inst_1238:
// fs1 == 0 and fe1 == 0x0c and fm1 == 0x375 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x293 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x221 and fcsr == 0x60 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3375; op2val:0x3e93;
op3val:0x3621; valaddr_reg:x3; val_offset:3714*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 96, 0, x3, 3714*FLEN/8, x4, x1, x2)

inst_1239:
// fs1 == 0 and fe1 == 0x0c and fm1 == 0x375 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x293 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x221 and fcsr == 0x80 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3375; op2val:0x3e93;
op3val:0x3621; valaddr_reg:x3; val_offset:3717*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:128 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 128, 0, x3, 3717*FLEN/8, x4, x1, x2)

inst_1240:
// fs1 == 0 and fe1 == 0x0d and fm1 == 0x1b7 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x12a and fs3 == 0 and fe3 == 0x0e and fm3 == 0x361 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x35b7; op2val:0x412a;
op3val:0x3b61; valaddr_reg:x3; val_offset:3720*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 3720*FLEN/8, x4, x1, x2)

inst_1241:
// fs1 == 0 and fe1 == 0x0d and fm1 == 0x1b7 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x12a and fs3 == 0 and fe3 == 0x0e and fm3 == 0x361 and fcsr == 0x20 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x35b7; op2val:0x412a;
op3val:0x3b61; valaddr_reg:x3; val_offset:3723*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:32 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 32, 0, x3, 3723*FLEN/8, x4, x1, x2)

inst_1242:
// fs1 == 0 and fe1 == 0x0d and fm1 == 0x1b7 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x12a and fs3 == 0 and fe3 == 0x0e and fm3 == 0x361 and fcsr == 0x40 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x35b7; op2val:0x412a;
op3val:0x3b61; valaddr_reg:x3; val_offset:3726*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:64 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 64, 0, x3, 3726*FLEN/8, x4, x1, x2)

inst_1243:
// fs1 == 0 and fe1 == 0x0d and fm1 == 0x1b7 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x12a and fs3 == 0 and fe3 == 0x0e and fm3 == 0x361 and fcsr == 0x60 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x35b7; op2val:0x412a;
op3val:0x3b61; valaddr_reg:x3; val_offset:3729*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 96, 0, x3, 3729*FLEN/8, x4, x1, x2)

inst_1244:
// fs1 == 0 and fe1 == 0x0d and fm1 == 0x1b7 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x12a and fs3 == 0 and fe3 == 0x0e and fm3 == 0x361 and fcsr == 0x80 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x35b7; op2val:0x412a;
op3val:0x3b61; valaddr_reg:x3; val_offset:3732*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:128 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 128, 0, x3, 3732*FLEN/8, x4, x1, x2)

inst_1245:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x2d2 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x300 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x1f7 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3ad2; op2val:0x3b00;
op3val:0x39f7; valaddr_reg:x3; val_offset:3735*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 3735*FLEN/8, x4, x1, x2)

inst_1246:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x2d2 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x300 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x1f7 and fcsr == 0x20 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3ad2; op2val:0x3b00;
op3val:0x39f7; valaddr_reg:x3; val_offset:3738*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:32 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 32, 0, x3, 3738*FLEN/8, x4, x1, x2)

inst_1247:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x2d2 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x300 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x1f7 and fcsr == 0x40 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3ad2; op2val:0x3b00;
op3val:0x39f7; valaddr_reg:x3; val_offset:3741*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:64 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 64, 0, x3, 3741*FLEN/8, x4, x1, x2)

inst_1248:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x2d2 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x300 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x1f7 and fcsr == 0x60 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3ad2; op2val:0x3b00;
op3val:0x39f7; valaddr_reg:x3; val_offset:3744*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 96, 0, x3, 3744*FLEN/8, x4, x1, x2)

inst_1249:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x2d2 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x300 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x1f7 and fcsr == 0x80 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3ad2; op2val:0x3b00;
op3val:0x39f7; valaddr_reg:x3; val_offset:3747*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:128 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 128, 0, x3, 3747*FLEN/8, x4, x1, x2)

inst_1250:
// fs1 == 0 and fe1 == 0x0d and fm1 == 0x01b and fs2 == 0 and fe2 == 0x10 and fm2 == 0x16a and fs3 == 0 and fe3 == 0x0e and fm3 == 0x190 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x341b; op2val:0x416a;
op3val:0x3990; valaddr_reg:x3; val_offset:3750*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 3750*FLEN/8, x4, x1, x2)

inst_1251:
// fs1 == 0 and fe1 == 0x0d and fm1 == 0x01b and fs2 == 0 and fe2 == 0x10 and fm2 == 0x16a and fs3 == 0 and fe3 == 0x0e and fm3 == 0x190 and fcsr == 0x20 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x341b; op2val:0x416a;
op3val:0x3990; valaddr_reg:x3; val_offset:3753*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:32 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 32, 0, x3, 3753*FLEN/8, x4, x1, x2)

inst_1252:
// fs1 == 0 and fe1 == 0x0d and fm1 == 0x01b and fs2 == 0 and fe2 == 0x10 and fm2 == 0x16a and fs3 == 0 and fe3 == 0x0e and fm3 == 0x190 and fcsr == 0x40 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x341b; op2val:0x416a;
op3val:0x3990; valaddr_reg:x3; val_offset:3756*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:64 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 64, 0, x3, 3756*FLEN/8, x4, x1, x2)

inst_1253:
// fs1 == 0 and fe1 == 0x0d and fm1 == 0x01b and fs2 == 0 and fe2 == 0x10 and fm2 == 0x16a and fs3 == 0 and fe3 == 0x0e and fm3 == 0x190 and fcsr == 0x60 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x341b; op2val:0x416a;
op3val:0x3990; valaddr_reg:x3; val_offset:3759*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 96, 0, x3, 3759*FLEN/8, x4, x1, x2)

inst_1254:
// fs1 == 0 and fe1 == 0x0d and fm1 == 0x01b and fs2 == 0 and fe2 == 0x10 and fm2 == 0x16a and fs3 == 0 and fe3 == 0x0e and fm3 == 0x190 and fcsr == 0x80 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x341b; op2val:0x416a;
op3val:0x3990; valaddr_reg:x3; val_offset:3762*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:128 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 128, 0, x3, 3762*FLEN/8, x4, x1, x2)

inst_1255:
// fs1 == 0 and fe1 == 0x0d and fm1 == 0x2ea and fs2 == 0 and fe2 == 0x10 and fm2 == 0x091 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x3e6 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x36ea; op2val:0x4091;
op3val:0x3be6; valaddr_reg:x3; val_offset:3765*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 3765*FLEN/8, x4, x1, x2)

inst_1256:
// fs1 == 0 and fe1 == 0x0d and fm1 == 0x2ea and fs2 == 0 and fe2 == 0x10 and fm2 == 0x091 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x3e6 and fcsr == 0x20 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x36ea; op2val:0x4091;
op3val:0x3be6; valaddr_reg:x3; val_offset:3768*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:32 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 32, 0, x3, 3768*FLEN/8, x4, x1, x2)

inst_1257:
// fs1 == 0 and fe1 == 0x0d and fm1 == 0x2ea and fs2 == 0 and fe2 == 0x10 and fm2 == 0x091 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x3e6 and fcsr == 0x40 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x36ea; op2val:0x4091;
op3val:0x3be6; valaddr_reg:x3; val_offset:3771*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:64 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 64, 0, x3, 3771*FLEN/8, x4, x1, x2)

inst_1258:
// fs1 == 0 and fe1 == 0x0d and fm1 == 0x2ea and fs2 == 0 and fe2 == 0x10 and fm2 == 0x091 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x3e6 and fcsr == 0x60 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x36ea; op2val:0x4091;
op3val:0x3be6; valaddr_reg:x3; val_offset:3774*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 96, 0, x3, 3774*FLEN/8, x4, x1, x2)

inst_1259:
// fs1 == 0 and fe1 == 0x0d and fm1 == 0x2ea and fs2 == 0 and fe2 == 0x10 and fm2 == 0x091 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x3e6 and fcsr == 0x80 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x36ea; op2val:0x4091;
op3val:0x3be6; valaddr_reg:x3; val_offset:3777*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:128 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 128, 0, x3, 3777*FLEN/8, x4, x1, x2)

inst_1260:
// fs1 == 0 and fe1 == 0x11 and fm1 == 0x0d2 and fs2 == 0 and fe2 == 0x13 and fm2 == 0x03f and fs3 == 0 and fe3 == 0x13 and fm3 == 0x07b and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x44d2; op2val:0x4c3f;
op3val:0x4c7b; valaddr_reg:x3; val_offset:3780*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 3780*FLEN/8, x4, x1, x2)

inst_1261:
// fs1 == 0 and fe1 == 0x11 and fm1 == 0x0d2 and fs2 == 0 and fe2 == 0x13 and fm2 == 0x03f and fs3 == 0 and fe3 == 0x13 and fm3 == 0x07b and fcsr == 0x20 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x44d2; op2val:0x4c3f;
op3val:0x4c7b; valaddr_reg:x3; val_offset:3783*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:32 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 32, 0, x3, 3783*FLEN/8, x4, x1, x2)

inst_1262:
// fs1 == 0 and fe1 == 0x11 and fm1 == 0x0d2 and fs2 == 0 and fe2 == 0x13 and fm2 == 0x03f and fs3 == 0 and fe3 == 0x13 and fm3 == 0x07b and fcsr == 0x40 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x44d2; op2val:0x4c3f;
op3val:0x4c7b; valaddr_reg:x3; val_offset:3786*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:64 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 64, 0, x3, 3786*FLEN/8, x4, x1, x2)

inst_1263:
// fs1 == 0 and fe1 == 0x11 and fm1 == 0x0d2 and fs2 == 0 and fe2 == 0x13 and fm2 == 0x03f and fs3 == 0 and fe3 == 0x13 and fm3 == 0x07b and fcsr == 0x60 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x44d2; op2val:0x4c3f;
op3val:0x4c7b; valaddr_reg:x3; val_offset:3789*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 96, 0, x3, 3789*FLEN/8, x4, x1, x2)

inst_1264:
// fs1 == 0 and fe1 == 0x11 and fm1 == 0x0d2 and fs2 == 0 and fe2 == 0x13 and fm2 == 0x03f and fs3 == 0 and fe3 == 0x13 and fm3 == 0x07b and fcsr == 0x80 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x44d2; op2val:0x4c3f;
op3val:0x4c7b; valaddr_reg:x3; val_offset:3792*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:128 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 128, 0, x3, 3792*FLEN/8, x4, x1, x2)

inst_1265:
// fs1 == 0 and fe1 == 0x14 and fm1 == 0x16a and fs2 == 0 and fe2 == 0x10 and fm2 == 0x103 and fs3 == 0 and fe3 == 0x14 and fm3 == 0x193 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x516a; op2val:0x4103;
op3val:0x5193; valaddr_reg:x3; val_offset:3795*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 3795*FLEN/8, x4, x1, x2)

inst_1266:
// fs1 == 0 and fe1 == 0x14 and fm1 == 0x16a and fs2 == 0 and fe2 == 0x10 and fm2 == 0x103 and fs3 == 0 and fe3 == 0x14 and fm3 == 0x193 and fcsr == 0x20 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x516a; op2val:0x4103;
op3val:0x5193; valaddr_reg:x3; val_offset:3798*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:32 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 32, 0, x3, 3798*FLEN/8, x4, x1, x2)

inst_1267:
// fs1 == 0 and fe1 == 0x14 and fm1 == 0x16a and fs2 == 0 and fe2 == 0x10 and fm2 == 0x103 and fs3 == 0 and fe3 == 0x14 and fm3 == 0x193 and fcsr == 0x40 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x516a; op2val:0x4103;
op3val:0x5193; valaddr_reg:x3; val_offset:3801*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:64 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 64, 0, x3, 3801*FLEN/8, x4, x1, x2)

inst_1268:
// fs1 == 0 and fe1 == 0x14 and fm1 == 0x16a and fs2 == 0 and fe2 == 0x10 and fm2 == 0x103 and fs3 == 0 and fe3 == 0x14 and fm3 == 0x193 and fcsr == 0x60 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x516a; op2val:0x4103;
op3val:0x5193; valaddr_reg:x3; val_offset:3804*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 96, 0, x3, 3804*FLEN/8, x4, x1, x2)

inst_1269:
// fs1 == 0 and fe1 == 0x14 and fm1 == 0x16a and fs2 == 0 and fe2 == 0x10 and fm2 == 0x103 and fs3 == 0 and fe3 == 0x14 and fm3 == 0x193 and fcsr == 0x80 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x516a; op2val:0x4103;
op3val:0x5193; valaddr_reg:x3; val_offset:3807*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:128 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 128, 0, x3, 3807*FLEN/8, x4, x1, x2)

inst_1270:
// fs1 == 0 and fe1 == 0x14 and fm1 == 0x172 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x3a6 and fs3 == 0 and fe3 == 0x13 and fm3 == 0x0d4 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x5172; op2val:0x3fa6;
op3val:0x4cd4; valaddr_reg:x3; val_offset:3810*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 3810*FLEN/8, x4, x1, x2)

inst_1271:
// fs1 == 0 and fe1 == 0x14 and fm1 == 0x172 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x3a6 and fs3 == 0 and fe3 == 0x13 and fm3 == 0x0d4 and fcsr == 0x20 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x5172; op2val:0x3fa6;
op3val:0x4cd4; valaddr_reg:x3; val_offset:3813*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:32 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 32, 0, x3, 3813*FLEN/8, x4, x1, x2)

inst_1272:
// fs1 == 0 and fe1 == 0x14 and fm1 == 0x172 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x3a6 and fs3 == 0 and fe3 == 0x13 and fm3 == 0x0d4 and fcsr == 0x40 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x5172; op2val:0x3fa6;
op3val:0x4cd4; valaddr_reg:x3; val_offset:3816*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:64 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 64, 0, x3, 3816*FLEN/8, x4, x1, x2)

inst_1273:
// fs1 == 0 and fe1 == 0x14 and fm1 == 0x172 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x3a6 and fs3 == 0 and fe3 == 0x13 and fm3 == 0x0d4 and fcsr == 0x60 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x5172; op2val:0x3fa6;
op3val:0x4cd4; valaddr_reg:x3; val_offset:3819*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 96, 0, x3, 3819*FLEN/8, x4, x1, x2)

inst_1274:
// fs1 == 0 and fe1 == 0x14 and fm1 == 0x172 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x3a6 and fs3 == 0 and fe3 == 0x13 and fm3 == 0x0d4 and fcsr == 0x80 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x5172; op2val:0x3fa6;
op3val:0x4cd4; valaddr_reg:x3; val_offset:3822*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:128 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 128, 0, x3, 3822*FLEN/8, x4, x1, x2)

inst_1275:
// fs1 == 0 and fe1 == 0x14 and fm1 == 0x031 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x19f and fs3 == 0 and fe3 == 0x13 and fm3 == 0x391 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x5031; op2val:0x419f;
op3val:0x4f91; valaddr_reg:x3; val_offset:3825*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 3825*FLEN/8, x4, x1, x2)

inst_1276:
// fs1 == 0 and fe1 == 0x14 and fm1 == 0x031 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x19f and fs3 == 0 and fe3 == 0x13 and fm3 == 0x391 and fcsr == 0x20 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x5031; op2val:0x419f;
op3val:0x4f91; valaddr_reg:x3; val_offset:3828*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:32 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 32, 0, x3, 3828*FLEN/8, x4, x1, x2)

inst_1277:
// fs1 == 0 and fe1 == 0x14 and fm1 == 0x031 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x19f and fs3 == 0 and fe3 == 0x13 and fm3 == 0x391 and fcsr == 0x40 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x5031; op2val:0x419f;
op3val:0x4f91; valaddr_reg:x3; val_offset:3831*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:64 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 64, 0, x3, 3831*FLEN/8, x4, x1, x2)

inst_1278:
// fs1 == 0 and fe1 == 0x14 and fm1 == 0x031 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x19f and fs3 == 0 and fe3 == 0x13 and fm3 == 0x391 and fcsr == 0x60 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x5031; op2val:0x419f;
op3val:0x4f91; valaddr_reg:x3; val_offset:3834*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 96, 0, x3, 3834*FLEN/8, x4, x1, x2)

inst_1279:
// fs1 == 0 and fe1 == 0x14 and fm1 == 0x031 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x19f and fs3 == 0 and fe3 == 0x13 and fm3 == 0x391 and fcsr == 0x80 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x5031; op2val:0x419f;
op3val:0x4f91; valaddr_reg:x3; val_offset:3837*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:128 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 128, 0, x3, 3837*FLEN/8, x4, x1, x2)
RVTEST_SIGBASE(x1,signature_x1_11)

inst_1280:
// fs1 == 0 and fe1 == 0x13 and fm1 == 0x398 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x0c5 and fs3 == 0 and fe3 == 0x12 and fm3 == 0x03b and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x4f98; op2val:0x40c5;
op3val:0x483b; valaddr_reg:x3; val_offset:3840*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 3840*FLEN/8, x4, x1, x2)

inst_1281:
// fs1 == 0 and fe1 == 0x13 and fm1 == 0x398 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x0c5 and fs3 == 0 and fe3 == 0x12 and fm3 == 0x03b and fcsr == 0x20 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x4f98; op2val:0x40c5;
op3val:0x483b; valaddr_reg:x3; val_offset:3843*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:32 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 32, 0, x3, 3843*FLEN/8, x4, x1, x2)

inst_1282:
// fs1 == 0 and fe1 == 0x13 and fm1 == 0x398 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x0c5 and fs3 == 0 and fe3 == 0x12 and fm3 == 0x03b and fcsr == 0x40 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x4f98; op2val:0x40c5;
op3val:0x483b; valaddr_reg:x3; val_offset:3846*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:64 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 64, 0, x3, 3846*FLEN/8, x4, x1, x2)

inst_1283:
// fs1 == 0 and fe1 == 0x13 and fm1 == 0x398 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x0c5 and fs3 == 0 and fe3 == 0x12 and fm3 == 0x03b and fcsr == 0x60 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x4f98; op2val:0x40c5;
op3val:0x483b; valaddr_reg:x3; val_offset:3849*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 96, 0, x3, 3849*FLEN/8, x4, x1, x2)

inst_1284:
// fs1 == 0 and fe1 == 0x13 and fm1 == 0x398 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x0c5 and fs3 == 0 and fe3 == 0x12 and fm3 == 0x03b and fcsr == 0x80 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x4f98; op2val:0x40c5;
op3val:0x483b; valaddr_reg:x3; val_offset:3852*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:128 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 128, 0, x3, 3852*FLEN/8, x4, x1, x2)

inst_1285:
// fs1 == 0 and fe1 == 0x14 and fm1 == 0x329 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x169 and fs3 == 0 and fe3 == 0x12 and fm3 == 0x2c6 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x5329; op2val:0x3d69;
op3val:0x4ac6; valaddr_reg:x3; val_offset:3855*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 3855*FLEN/8, x4, x1, x2)

inst_1286:
// fs1 == 0 and fe1 == 0x14 and fm1 == 0x329 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x169 and fs3 == 0 and fe3 == 0x12 and fm3 == 0x2c6 and fcsr == 0x20 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x5329; op2val:0x3d69;
op3val:0x4ac6; valaddr_reg:x3; val_offset:3858*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:32 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 32, 0, x3, 3858*FLEN/8, x4, x1, x2)

inst_1287:
// fs1 == 0 and fe1 == 0x14 and fm1 == 0x329 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x169 and fs3 == 0 and fe3 == 0x12 and fm3 == 0x2c6 and fcsr == 0x40 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x5329; op2val:0x3d69;
op3val:0x4ac6; valaddr_reg:x3; val_offset:3861*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:64 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 64, 0, x3, 3861*FLEN/8, x4, x1, x2)

inst_1288:
// fs1 == 0 and fe1 == 0x14 and fm1 == 0x329 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x169 and fs3 == 0 and fe3 == 0x12 and fm3 == 0x2c6 and fcsr == 0x60 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x5329; op2val:0x3d69;
op3val:0x4ac6; valaddr_reg:x3; val_offset:3864*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 96, 0, x3, 3864*FLEN/8, x4, x1, x2)

inst_1289:
// fs1 == 0 and fe1 == 0x14 and fm1 == 0x329 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x169 and fs3 == 0 and fe3 == 0x12 and fm3 == 0x2c6 and fcsr == 0x80 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x5329; op2val:0x3d69;
op3val:0x4ac6; valaddr_reg:x3; val_offset:3867*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:128 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 128, 0, x3, 3867*FLEN/8, x4, x1, x2)

inst_1290:
// fs1 == 0 and fe1 == 0x14 and fm1 == 0x3d4 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x3eb and fs3 == 0 and fe3 == 0x14 and fm3 == 0x37f and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x53d4; op2val:0x3feb;
op3val:0x537f; valaddr_reg:x3; val_offset:3870*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 3870*FLEN/8, x4, x1, x2)

inst_1291:
// fs1 == 0 and fe1 == 0x14 and fm1 == 0x3d4 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x3eb and fs3 == 0 and fe3 == 0x14 and fm3 == 0x37f and fcsr == 0x20 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x53d4; op2val:0x3feb;
op3val:0x537f; valaddr_reg:x3; val_offset:3873*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:32 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 32, 0, x3, 3873*FLEN/8, x4, x1, x2)

inst_1292:
// fs1 == 0 and fe1 == 0x14 and fm1 == 0x3d4 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x3eb and fs3 == 0 and fe3 == 0x14 and fm3 == 0x37f and fcsr == 0x40 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x53d4; op2val:0x3feb;
op3val:0x537f; valaddr_reg:x3; val_offset:3876*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:64 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 64, 0, x3, 3876*FLEN/8, x4, x1, x2)

inst_1293:
// fs1 == 0 and fe1 == 0x14 and fm1 == 0x3d4 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x3eb and fs3 == 0 and fe3 == 0x14 and fm3 == 0x37f and fcsr == 0x60 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x53d4; op2val:0x3feb;
op3val:0x537f; valaddr_reg:x3; val_offset:3879*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 96, 0, x3, 3879*FLEN/8, x4, x1, x2)

inst_1294:
// fs1 == 0 and fe1 == 0x14 and fm1 == 0x3d4 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x3eb and fs3 == 0 and fe3 == 0x14 and fm3 == 0x37f and fcsr == 0x80 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x53d4; op2val:0x3feb;
op3val:0x537f; valaddr_reg:x3; val_offset:3882*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:128 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 128, 0, x3, 3882*FLEN/8, x4, x1, x2)

inst_1295:
// fs1 == 0 and fe1 == 0x10 and fm1 == 0x034 and fs2 == 0 and fe2 == 0x14 and fm2 == 0x195 and fs3 == 0 and fe3 == 0x13 and fm3 == 0x37a and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x4034; op2val:0x5195;
op3val:0x4f7a; valaddr_reg:x3; val_offset:3885*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 3885*FLEN/8, x4, x1, x2)

inst_1296:
// fs1 == 0 and fe1 == 0x10 and fm1 == 0x034 and fs2 == 0 and fe2 == 0x14 and fm2 == 0x195 and fs3 == 0 and fe3 == 0x13 and fm3 == 0x37a and fcsr == 0x20 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x4034; op2val:0x5195;
op3val:0x4f7a; valaddr_reg:x3; val_offset:3888*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:32 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 32, 0, x3, 3888*FLEN/8, x4, x1, x2)

inst_1297:
// fs1 == 0 and fe1 == 0x10 and fm1 == 0x034 and fs2 == 0 and fe2 == 0x14 and fm2 == 0x195 and fs3 == 0 and fe3 == 0x13 and fm3 == 0x37a and fcsr == 0x40 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x4034; op2val:0x5195;
op3val:0x4f7a; valaddr_reg:x3; val_offset:3891*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:64 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 64, 0, x3, 3891*FLEN/8, x4, x1, x2)

inst_1298:
// fs1 == 0 and fe1 == 0x10 and fm1 == 0x034 and fs2 == 0 and fe2 == 0x14 and fm2 == 0x195 and fs3 == 0 and fe3 == 0x13 and fm3 == 0x37a and fcsr == 0x60 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x4034; op2val:0x5195;
op3val:0x4f7a; valaddr_reg:x3; val_offset:3894*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 96, 0, x3, 3894*FLEN/8, x4, x1, x2)

inst_1299:
// fs1 == 0 and fe1 == 0x10 and fm1 == 0x034 and fs2 == 0 and fe2 == 0x14 and fm2 == 0x195 and fs3 == 0 and fe3 == 0x13 and fm3 == 0x37a and fcsr == 0x80 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x4034; op2val:0x5195;
op3val:0x4f7a; valaddr_reg:x3; val_offset:3897*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:128 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 128, 0, x3, 3897*FLEN/8, x4, x1, x2)

inst_1300:
// fs1 == 0 and fe1 == 0x14 and fm1 == 0x295 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x0c9 and fs3 == 0 and fe3 == 0x14 and fm3 == 0x3c0 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x5295; op2val:0x40c9;
op3val:0x53c0; valaddr_reg:x3; val_offset:3900*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 3900*FLEN/8, x4, x1, x2)

inst_1301:
// fs1 == 0 and fe1 == 0x14 and fm1 == 0x295 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x0c9 and fs3 == 0 and fe3 == 0x14 and fm3 == 0x3c0 and fcsr == 0x20 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x5295; op2val:0x40c9;
op3val:0x53c0; valaddr_reg:x3; val_offset:3903*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:32 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 32, 0, x3, 3903*FLEN/8, x4, x1, x2)

inst_1302:
// fs1 == 0 and fe1 == 0x14 and fm1 == 0x295 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x0c9 and fs3 == 0 and fe3 == 0x14 and fm3 == 0x3c0 and fcsr == 0x40 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x5295; op2val:0x40c9;
op3val:0x53c0; valaddr_reg:x3; val_offset:3906*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:64 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 64, 0, x3, 3906*FLEN/8, x4, x1, x2)

inst_1303:
// fs1 == 0 and fe1 == 0x14 and fm1 == 0x295 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x0c9 and fs3 == 0 and fe3 == 0x14 and fm3 == 0x3c0 and fcsr == 0x60 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x5295; op2val:0x40c9;
op3val:0x53c0; valaddr_reg:x3; val_offset:3909*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 96, 0, x3, 3909*FLEN/8, x4, x1, x2)

inst_1304:
// fs1 == 0 and fe1 == 0x14 and fm1 == 0x295 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x0c9 and fs3 == 0 and fe3 == 0x14 and fm3 == 0x3c0 and fcsr == 0x80 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x5295; op2val:0x40c9;
op3val:0x53c0; valaddr_reg:x3; val_offset:3912*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:128 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 128, 0, x3, 3912*FLEN/8, x4, x1, x2)

inst_1305:
// fs1 == 0 and fe1 == 0x13 and fm1 == 0x354 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x196 and fs3 == 0 and fe3 == 0x13 and fm3 == 0x07b and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x4f54; op2val:0x4196;
op3val:0x4c7b; valaddr_reg:x3; val_offset:3915*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 3915*FLEN/8, x4, x1, x2)

inst_1306:
// fs1 == 0 and fe1 == 0x13 and fm1 == 0x354 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x196 and fs3 == 0 and fe3 == 0x13 and fm3 == 0x07b and fcsr == 0x20 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x4f54; op2val:0x4196;
op3val:0x4c7b; valaddr_reg:x3; val_offset:3918*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:32 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 32, 0, x3, 3918*FLEN/8, x4, x1, x2)

inst_1307:
// fs1 == 0 and fe1 == 0x13 and fm1 == 0x354 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x196 and fs3 == 0 and fe3 == 0x13 and fm3 == 0x07b and fcsr == 0x40 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x4f54; op2val:0x4196;
op3val:0x4c7b; valaddr_reg:x3; val_offset:3921*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:64 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 64, 0, x3, 3921*FLEN/8, x4, x1, x2)

inst_1308:
// fs1 == 0 and fe1 == 0x13 and fm1 == 0x354 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x196 and fs3 == 0 and fe3 == 0x13 and fm3 == 0x07b and fcsr == 0x60 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x4f54; op2val:0x4196;
op3val:0x4c7b; valaddr_reg:x3; val_offset:3924*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 96, 0, x3, 3924*FLEN/8, x4, x1, x2)

inst_1309:
// fs1 == 0 and fe1 == 0x13 and fm1 == 0x354 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x196 and fs3 == 0 and fe3 == 0x13 and fm3 == 0x07b and fcsr == 0x80 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x4f54; op2val:0x4196;
op3val:0x4c7b; valaddr_reg:x3; val_offset:3927*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:128 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 128, 0, x3, 3927*FLEN/8, x4, x1, x2)

inst_1310:
// fs1 == 0 and fe1 == 0x12 and fm1 == 0x31c and fs2 == 0 and fe2 == 0x12 and fm2 == 0x061 and fs3 == 0 and fe3 == 0x14 and fm3 == 0x392 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x4b1c; op2val:0x4861;
op3val:0x5392; valaddr_reg:x3; val_offset:3930*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 3930*FLEN/8, x4, x1, x2)

inst_1311:
// fs1 == 0 and fe1 == 0x12 and fm1 == 0x31c and fs2 == 0 and fe2 == 0x12 and fm2 == 0x061 and fs3 == 0 and fe3 == 0x14 and fm3 == 0x392 and fcsr == 0x20 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x4b1c; op2val:0x4861;
op3val:0x5392; valaddr_reg:x3; val_offset:3933*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:32 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 32, 0, x3, 3933*FLEN/8, x4, x1, x2)

inst_1312:
// fs1 == 0 and fe1 == 0x12 and fm1 == 0x31c and fs2 == 0 and fe2 == 0x12 and fm2 == 0x061 and fs3 == 0 and fe3 == 0x14 and fm3 == 0x392 and fcsr == 0x40 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x4b1c; op2val:0x4861;
op3val:0x5392; valaddr_reg:x3; val_offset:3936*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:64 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 64, 0, x3, 3936*FLEN/8, x4, x1, x2)

inst_1313:
// fs1 == 0 and fe1 == 0x12 and fm1 == 0x31c and fs2 == 0 and fe2 == 0x12 and fm2 == 0x061 and fs3 == 0 and fe3 == 0x14 and fm3 == 0x392 and fcsr == 0x60 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x4b1c; op2val:0x4861;
op3val:0x5392; valaddr_reg:x3; val_offset:3939*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 96, 0, x3, 3939*FLEN/8, x4, x1, x2)

inst_1314:
// fs1 == 0 and fe1 == 0x12 and fm1 == 0x31c and fs2 == 0 and fe2 == 0x12 and fm2 == 0x061 and fs3 == 0 and fe3 == 0x14 and fm3 == 0x392 and fcsr == 0x80 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x4b1c; op2val:0x4861;
op3val:0x5392; valaddr_reg:x3; val_offset:3942*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:128 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 128, 0, x3, 3942*FLEN/8, x4, x1, x2)

inst_1315:
// fs1 == 0 and fe1 == 0x12 and fm1 == 0x323 and fs2 == 0 and fe2 == 0x11 and fm2 == 0x31e and fs3 == 0 and fe3 == 0x14 and fm3 == 0x0b4 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x4b23; op2val:0x471e;
op3val:0x50b4; valaddr_reg:x3; val_offset:3945*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 3945*FLEN/8, x4, x1, x2)

inst_1316:
// fs1 == 0 and fe1 == 0x12 and fm1 == 0x323 and fs2 == 0 and fe2 == 0x11 and fm2 == 0x31e and fs3 == 0 and fe3 == 0x14 and fm3 == 0x0b4 and fcsr == 0x20 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x4b23; op2val:0x471e;
op3val:0x50b4; valaddr_reg:x3; val_offset:3948*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:32 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 32, 0, x3, 3948*FLEN/8, x4, x1, x2)

inst_1317:
// fs1 == 0 and fe1 == 0x12 and fm1 == 0x323 and fs2 == 0 and fe2 == 0x11 and fm2 == 0x31e and fs3 == 0 and fe3 == 0x14 and fm3 == 0x0b4 and fcsr == 0x40 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x4b23; op2val:0x471e;
op3val:0x50b4; valaddr_reg:x3; val_offset:3951*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:64 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 64, 0, x3, 3951*FLEN/8, x4, x1, x2)

inst_1318:
// fs1 == 0 and fe1 == 0x12 and fm1 == 0x323 and fs2 == 0 and fe2 == 0x11 and fm2 == 0x31e and fs3 == 0 and fe3 == 0x14 and fm3 == 0x0b4 and fcsr == 0x60 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x4b23; op2val:0x471e;
op3val:0x50b4; valaddr_reg:x3; val_offset:3954*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 96, 0, x3, 3954*FLEN/8, x4, x1, x2)

inst_1319:
// fs1 == 0 and fe1 == 0x12 and fm1 == 0x323 and fs2 == 0 and fe2 == 0x11 and fm2 == 0x31e and fs3 == 0 and fe3 == 0x14 and fm3 == 0x0b4 and fcsr == 0x80 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x4b23; op2val:0x471e;
op3val:0x50b4; valaddr_reg:x3; val_offset:3957*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:128 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 128, 0, x3, 3957*FLEN/8, x4, x1, x2)

inst_1320:
// fs1 == 0 and fe1 == 0x12 and fm1 == 0x0f7 and fs2 == 0 and fe2 == 0x12 and fm2 == 0x0ef and fs3 == 0 and fe3 == 0x14 and fm3 == 0x040 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x48f7; op2val:0x48ef;
op3val:0x5040; valaddr_reg:x3; val_offset:3960*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 3960*FLEN/8, x4, x1, x2)

inst_1321:
// fs1 == 0 and fe1 == 0x12 and fm1 == 0x0f7 and fs2 == 0 and fe2 == 0x12 and fm2 == 0x0ef and fs3 == 0 and fe3 == 0x14 and fm3 == 0x040 and fcsr == 0x20 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x48f7; op2val:0x48ef;
op3val:0x5040; valaddr_reg:x3; val_offset:3963*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:32 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 32, 0, x3, 3963*FLEN/8, x4, x1, x2)

inst_1322:
// fs1 == 0 and fe1 == 0x12 and fm1 == 0x0f7 and fs2 == 0 and fe2 == 0x12 and fm2 == 0x0ef and fs3 == 0 and fe3 == 0x14 and fm3 == 0x040 and fcsr == 0x40 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x48f7; op2val:0x48ef;
op3val:0x5040; valaddr_reg:x3; val_offset:3966*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:64 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 64, 0, x3, 3966*FLEN/8, x4, x1, x2)

inst_1323:
// fs1 == 0 and fe1 == 0x12 and fm1 == 0x0f7 and fs2 == 0 and fe2 == 0x12 and fm2 == 0x0ef and fs3 == 0 and fe3 == 0x14 and fm3 == 0x040 and fcsr == 0x60 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x48f7; op2val:0x48ef;
op3val:0x5040; valaddr_reg:x3; val_offset:3969*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 96, 0, x3, 3969*FLEN/8, x4, x1, x2)

inst_1324:
// fs1 == 0 and fe1 == 0x12 and fm1 == 0x0f7 and fs2 == 0 and fe2 == 0x12 and fm2 == 0x0ef and fs3 == 0 and fe3 == 0x14 and fm3 == 0x040 and fcsr == 0x80 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x48f7; op2val:0x48ef;
op3val:0x5040; valaddr_reg:x3; val_offset:3972*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:128 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 128, 0, x3, 3972*FLEN/8, x4, x1, x2)

inst_1325:
// fs1 == 0 and fe1 == 0x14 and fm1 == 0x3a1 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x0ce and fs3 == 0 and fe3 == 0x12 and fm3 == 0x0ad and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x53a1; op2val:0x3cce;
op3val:0x48ad; valaddr_reg:x3; val_offset:3975*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 3975*FLEN/8, x4, x1, x2)

inst_1326:
// fs1 == 0 and fe1 == 0x14 and fm1 == 0x3a1 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x0ce and fs3 == 0 and fe3 == 0x12 and fm3 == 0x0ad and fcsr == 0x20 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x53a1; op2val:0x3cce;
op3val:0x48ad; valaddr_reg:x3; val_offset:3978*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:32 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 32, 0, x3, 3978*FLEN/8, x4, x1, x2)

inst_1327:
// fs1 == 0 and fe1 == 0x14 and fm1 == 0x3a1 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x0ce and fs3 == 0 and fe3 == 0x12 and fm3 == 0x0ad and fcsr == 0x40 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x53a1; op2val:0x3cce;
op3val:0x48ad; valaddr_reg:x3; val_offset:3981*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:64 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 64, 0, x3, 3981*FLEN/8, x4, x1, x2)

inst_1328:
// fs1 == 0 and fe1 == 0x14 and fm1 == 0x3a1 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x0ce and fs3 == 0 and fe3 == 0x12 and fm3 == 0x0ad and fcsr == 0x60 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x53a1; op2val:0x3cce;
op3val:0x48ad; valaddr_reg:x3; val_offset:3984*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 96, 0, x3, 3984*FLEN/8, x4, x1, x2)

inst_1329:
// fs1 == 0 and fe1 == 0x14 and fm1 == 0x3a1 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x0ce and fs3 == 0 and fe3 == 0x12 and fm3 == 0x0ad and fcsr == 0x80 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x53a1; op2val:0x3cce;
op3val:0x48ad; valaddr_reg:x3; val_offset:3987*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:128 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 128, 0, x3, 3987*FLEN/8, x4, x1, x2)

inst_1330:
// fs1 == 0 and fe1 == 0x14 and fm1 == 0x295 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x35e and fs3 == 0 and fe3 == 0x14 and fm3 == 0x021 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x5295; op2val:0x3f5e;
op3val:0x5021; valaddr_reg:x3; val_offset:3990*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 3990*FLEN/8, x4, x1, x2)

inst_1331:
// fs1 == 0 and fe1 == 0x14 and fm1 == 0x295 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x35e and fs3 == 0 and fe3 == 0x14 and fm3 == 0x021 and fcsr == 0x20 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x5295; op2val:0x3f5e;
op3val:0x5021; valaddr_reg:x3; val_offset:3993*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:32 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 32, 0, x3, 3993*FLEN/8, x4, x1, x2)

inst_1332:
// fs1 == 0 and fe1 == 0x14 and fm1 == 0x295 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x35e and fs3 == 0 and fe3 == 0x14 and fm3 == 0x021 and fcsr == 0x40 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x5295; op2val:0x3f5e;
op3val:0x5021; valaddr_reg:x3; val_offset:3996*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:64 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 64, 0, x3, 3996*FLEN/8, x4, x1, x2)

inst_1333:
// fs1 == 0 and fe1 == 0x14 and fm1 == 0x295 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x35e and fs3 == 0 and fe3 == 0x14 and fm3 == 0x021 and fcsr == 0x60 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x5295; op2val:0x3f5e;
op3val:0x5021; valaddr_reg:x3; val_offset:3999*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 96, 0, x3, 3999*FLEN/8, x4, x1, x2)

inst_1334:
// fs1 == 0 and fe1 == 0x14 and fm1 == 0x295 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x35e and fs3 == 0 and fe3 == 0x14 and fm3 == 0x021 and fcsr == 0x80 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x5295; op2val:0x3f5e;
op3val:0x5021; valaddr_reg:x3; val_offset:4002*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:128 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 128, 0, x3, 4002*FLEN/8, x4, x1, x2)

inst_1335:
// fs1 == 0 and fe1 == 0x14 and fm1 == 0x31c and fs2 == 0 and fe2 == 0x0f and fm2 == 0x3b0 and fs3 == 0 and fe3 == 0x14 and fm3 == 0x1aa and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x531c; op2val:0x3fb0;
op3val:0x51aa; valaddr_reg:x3; val_offset:4005*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 4005*FLEN/8, x4, x1, x2)

inst_1336:
// fs1 == 0 and fe1 == 0x14 and fm1 == 0x31c and fs2 == 0 and fe2 == 0x0f and fm2 == 0x3b0 and fs3 == 0 and fe3 == 0x14 and fm3 == 0x1aa and fcsr == 0x20 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x531c; op2val:0x3fb0;
op3val:0x51aa; valaddr_reg:x3; val_offset:4008*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:32 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 32, 0, x3, 4008*FLEN/8, x4, x1, x2)

inst_1337:
// fs1 == 0 and fe1 == 0x14 and fm1 == 0x31c and fs2 == 0 and fe2 == 0x0f and fm2 == 0x3b0 and fs3 == 0 and fe3 == 0x14 and fm3 == 0x1aa and fcsr == 0x40 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x531c; op2val:0x3fb0;
op3val:0x51aa; valaddr_reg:x3; val_offset:4011*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:64 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 64, 0, x3, 4011*FLEN/8, x4, x1, x2)

inst_1338:
// fs1 == 0 and fe1 == 0x14 and fm1 == 0x31c and fs2 == 0 and fe2 == 0x0f and fm2 == 0x3b0 and fs3 == 0 and fe3 == 0x14 and fm3 == 0x1aa and fcsr == 0x60 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x531c; op2val:0x3fb0;
op3val:0x51aa; valaddr_reg:x3; val_offset:4014*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 96, 0, x3, 4014*FLEN/8, x4, x1, x2)

inst_1339:
// fs1 == 0 and fe1 == 0x14 and fm1 == 0x31c and fs2 == 0 and fe2 == 0x0f and fm2 == 0x3b0 and fs3 == 0 and fe3 == 0x14 and fm3 == 0x1aa and fcsr == 0x80 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x531c; op2val:0x3fb0;
op3val:0x51aa; valaddr_reg:x3; val_offset:4017*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:128 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 128, 0, x3, 4017*FLEN/8, x4, x1, x2)

inst_1340:
// fs1 == 0 and fe1 == 0x12 and fm1 == 0x3c9 and fs2 == 0 and fe2 == 0x11 and fm2 == 0x3cd and fs3 == 0 and fe3 == 0x14 and fm3 == 0x331 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x4bc9; op2val:0x47cd;
op3val:0x5331; valaddr_reg:x3; val_offset:4020*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 4020*FLEN/8, x4, x1, x2)

inst_1341:
// fs1 == 0 and fe1 == 0x12 and fm1 == 0x3c9 and fs2 == 0 and fe2 == 0x11 and fm2 == 0x3cd and fs3 == 0 and fe3 == 0x14 and fm3 == 0x331 and fcsr == 0x20 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x4bc9; op2val:0x47cd;
op3val:0x5331; valaddr_reg:x3; val_offset:4023*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:32 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 32, 0, x3, 4023*FLEN/8, x4, x1, x2)

inst_1342:
// fs1 == 0 and fe1 == 0x12 and fm1 == 0x3c9 and fs2 == 0 and fe2 == 0x11 and fm2 == 0x3cd and fs3 == 0 and fe3 == 0x14 and fm3 == 0x331 and fcsr == 0x40 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x4bc9; op2val:0x47cd;
op3val:0x5331; valaddr_reg:x3; val_offset:4026*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:64 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 64, 0, x3, 4026*FLEN/8, x4, x1, x2)

inst_1343:
// fs1 == 0 and fe1 == 0x12 and fm1 == 0x3c9 and fs2 == 0 and fe2 == 0x11 and fm2 == 0x3cd and fs3 == 0 and fe3 == 0x14 and fm3 == 0x331 and fcsr == 0x60 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x4bc9; op2val:0x47cd;
op3val:0x5331; valaddr_reg:x3; val_offset:4029*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 96, 0, x3, 4029*FLEN/8, x4, x1, x2)

inst_1344:
// fs1 == 0 and fe1 == 0x12 and fm1 == 0x3c9 and fs2 == 0 and fe2 == 0x11 and fm2 == 0x3cd and fs3 == 0 and fe3 == 0x14 and fm3 == 0x331 and fcsr == 0x80 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x4bc9; op2val:0x47cd;
op3val:0x5331; valaddr_reg:x3; val_offset:4032*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:128 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 128, 0, x3, 4032*FLEN/8, x4, x1, x2)

inst_1345:
// fs1 == 0 and fe1 == 0x13 and fm1 == 0x3e8 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x035 and fs3 == 0 and fe3 == 0x10 and fm3 == 0x121 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x4fe8; op2val:0x4035;
op3val:0x4121; valaddr_reg:x3; val_offset:4035*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 4035*FLEN/8, x4, x1, x2)

inst_1346:
// fs1 == 0 and fe1 == 0x13 and fm1 == 0x3e8 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x035 and fs3 == 0 and fe3 == 0x10 and fm3 == 0x121 and fcsr == 0x20 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x4fe8; op2val:0x4035;
op3val:0x4121; valaddr_reg:x3; val_offset:4038*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:32 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 32, 0, x3, 4038*FLEN/8, x4, x1, x2)

inst_1347:
// fs1 == 0 and fe1 == 0x13 and fm1 == 0x3e8 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x035 and fs3 == 0 and fe3 == 0x10 and fm3 == 0x121 and fcsr == 0x40 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x4fe8; op2val:0x4035;
op3val:0x4121; valaddr_reg:x3; val_offset:4041*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:64 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 64, 0, x3, 4041*FLEN/8, x4, x1, x2)

inst_1348:
// fs1 == 0 and fe1 == 0x13 and fm1 == 0x3e8 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x035 and fs3 == 0 and fe3 == 0x10 and fm3 == 0x121 and fcsr == 0x60 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x4fe8; op2val:0x4035;
op3val:0x4121; valaddr_reg:x3; val_offset:4044*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 96, 0, x3, 4044*FLEN/8, x4, x1, x2)

inst_1349:
// fs1 == 0 and fe1 == 0x13 and fm1 == 0x3e8 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x035 and fs3 == 0 and fe3 == 0x10 and fm3 == 0x121 and fcsr == 0x80 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x4fe8; op2val:0x4035;
op3val:0x4121; valaddr_reg:x3; val_offset:4047*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:128 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 128, 0, x3, 4047*FLEN/8, x4, x1, x2)

inst_1350:
// fs1 == 0 and fe1 == 0x0f and fm1 == 0x0e7 and fs2 == 0 and fe2 == 0x15 and fm2 == 0x0e4 and fs3 == 0 and fe3 == 0x13 and fm3 == 0x3fe and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3ce7; op2val:0x54e4;
op3val:0x4ffe; valaddr_reg:x3; val_offset:4050*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 4050*FLEN/8, x4, x1, x2)

inst_1351:
// fs1 == 0 and fe1 == 0x0f and fm1 == 0x0e7 and fs2 == 0 and fe2 == 0x15 and fm2 == 0x0e4 and fs3 == 0 and fe3 == 0x13 and fm3 == 0x3fe and fcsr == 0x20 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3ce7; op2val:0x54e4;
op3val:0x4ffe; valaddr_reg:x3; val_offset:4053*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:32 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 32, 0, x3, 4053*FLEN/8, x4, x1, x2)

inst_1352:
// fs1 == 0 and fe1 == 0x0f and fm1 == 0x0e7 and fs2 == 0 and fe2 == 0x15 and fm2 == 0x0e4 and fs3 == 0 and fe3 == 0x13 and fm3 == 0x3fe and fcsr == 0x40 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3ce7; op2val:0x54e4;
op3val:0x4ffe; valaddr_reg:x3; val_offset:4056*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:64 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 64, 0, x3, 4056*FLEN/8, x4, x1, x2)

inst_1353:
// fs1 == 0 and fe1 == 0x0f and fm1 == 0x0e7 and fs2 == 0 and fe2 == 0x15 and fm2 == 0x0e4 and fs3 == 0 and fe3 == 0x13 and fm3 == 0x3fe and fcsr == 0x60 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3ce7; op2val:0x54e4;
op3val:0x4ffe; valaddr_reg:x3; val_offset:4059*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 96, 0, x3, 4059*FLEN/8, x4, x1, x2)

inst_1354:
// fs1 == 0 and fe1 == 0x0f and fm1 == 0x0e7 and fs2 == 0 and fe2 == 0x15 and fm2 == 0x0e4 and fs3 == 0 and fe3 == 0x13 and fm3 == 0x3fe and fcsr == 0x80 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3ce7; op2val:0x54e4;
op3val:0x4ffe; valaddr_reg:x3; val_offset:4062*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:128 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 128, 0, x3, 4062*FLEN/8, x4, x1, x2)

inst_1355:
// fs1 == 0 and fe1 == 0x13 and fm1 == 0x359 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x1b7 and fs3 == 0 and fe3 == 0x13 and fm3 == 0x101 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x4f59; op2val:0x41b7;
op3val:0x4d01; valaddr_reg:x3; val_offset:4065*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 4065*FLEN/8, x4, x1, x2)

inst_1356:
// fs1 == 0 and fe1 == 0x13 and fm1 == 0x359 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x1b7 and fs3 == 0 and fe3 == 0x13 and fm3 == 0x101 and fcsr == 0x20 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x4f59; op2val:0x41b7;
op3val:0x4d01; valaddr_reg:x3; val_offset:4068*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:32 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 32, 0, x3, 4068*FLEN/8, x4, x1, x2)

inst_1357:
// fs1 == 0 and fe1 == 0x13 and fm1 == 0x359 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x1b7 and fs3 == 0 and fe3 == 0x13 and fm3 == 0x101 and fcsr == 0x40 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x4f59; op2val:0x41b7;
op3val:0x4d01; valaddr_reg:x3; val_offset:4071*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:64 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 64, 0, x3, 4071*FLEN/8, x4, x1, x2)

inst_1358:
// fs1 == 0 and fe1 == 0x13 and fm1 == 0x359 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x1b7 and fs3 == 0 and fe3 == 0x13 and fm3 == 0x101 and fcsr == 0x60 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x4f59; op2val:0x41b7;
op3val:0x4d01; valaddr_reg:x3; val_offset:4074*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 96, 0, x3, 4074*FLEN/8, x4, x1, x2)

inst_1359:
// fs1 == 0 and fe1 == 0x13 and fm1 == 0x359 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x1b7 and fs3 == 0 and fe3 == 0x13 and fm3 == 0x101 and fcsr == 0x80 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x4f59; op2val:0x41b7;
op3val:0x4d01; valaddr_reg:x3; val_offset:4077*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:128 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 128, 0, x3, 4077*FLEN/8, x4, x1, x2)

inst_1360:
// fs1 == 0 and fe1 == 0x12 and fm1 == 0x0ee and fs2 == 0 and fe2 == 0x12 and fm2 == 0x064 and fs3 == 0 and fe3 == 0x13 and fm3 == 0x1ab and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x48ee; op2val:0x4864;
op3val:0x4dab; valaddr_reg:x3; val_offset:4080*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 4080*FLEN/8, x4, x1, x2)

inst_1361:
// fs1 == 0 and fe1 == 0x12 and fm1 == 0x0ee and fs2 == 0 and fe2 == 0x12 and fm2 == 0x064 and fs3 == 0 and fe3 == 0x13 and fm3 == 0x1ab and fcsr == 0x20 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x48ee; op2val:0x4864;
op3val:0x4dab; valaddr_reg:x3; val_offset:4083*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:32 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 32, 0, x3, 4083*FLEN/8, x4, x1, x2)

inst_1362:
// fs1 == 0 and fe1 == 0x12 and fm1 == 0x0ee and fs2 == 0 and fe2 == 0x12 and fm2 == 0x064 and fs3 == 0 and fe3 == 0x13 and fm3 == 0x1ab and fcsr == 0x40 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x48ee; op2val:0x4864;
op3val:0x4dab; valaddr_reg:x3; val_offset:4086*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:64 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 64, 0, x3, 4086*FLEN/8, x4, x1, x2)

inst_1363:
// fs1 == 0 and fe1 == 0x12 and fm1 == 0x0ee and fs2 == 0 and fe2 == 0x12 and fm2 == 0x064 and fs3 == 0 and fe3 == 0x13 and fm3 == 0x1ab and fcsr == 0x60 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x48ee; op2val:0x4864;
op3val:0x4dab; valaddr_reg:x3; val_offset:4089*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 96, 0, x3, 4089*FLEN/8, x4, x1, x2)

inst_1364:
// fs1 == 0 and fe1 == 0x12 and fm1 == 0x0ee and fs2 == 0 and fe2 == 0x12 and fm2 == 0x064 and fs3 == 0 and fe3 == 0x13 and fm3 == 0x1ab and fcsr == 0x80 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x48ee; op2val:0x4864;
op3val:0x4dab; valaddr_reg:x3; val_offset:4092*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:128 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 128, 0, x3, 4092*FLEN/8, x4, x1, x2)

inst_1365:
// fs1 == 0 and fe1 == 0x13 and fm1 == 0x13a and fs2 == 0 and fe2 == 0x11 and fm2 == 0x1a3 and fs3 == 0 and fe3 == 0x14 and fm3 == 0x2be and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x4d3a; op2val:0x45a3;
op3val:0x52be; valaddr_reg:x3; val_offset:4095*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 4095*FLEN/8, x4, x1, x2)

inst_1366:
// fs1 == 0 and fe1 == 0x13 and fm1 == 0x13a and fs2 == 0 and fe2 == 0x11 and fm2 == 0x1a3 and fs3 == 0 and fe3 == 0x14 and fm3 == 0x2be and fcsr == 0x20 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x4d3a; op2val:0x45a3;
op3val:0x52be; valaddr_reg:x3; val_offset:4098*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:32 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 32, 0, x3, 4098*FLEN/8, x4, x1, x2)

inst_1367:
// fs1 == 0 and fe1 == 0x13 and fm1 == 0x13a and fs2 == 0 and fe2 == 0x11 and fm2 == 0x1a3 and fs3 == 0 and fe3 == 0x14 and fm3 == 0x2be and fcsr == 0x40 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x4d3a; op2val:0x45a3;
op3val:0x52be; valaddr_reg:x3; val_offset:4101*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:64 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 64, 0, x3, 4101*FLEN/8, x4, x1, x2)

inst_1368:
// fs1 == 0 and fe1 == 0x13 and fm1 == 0x13a and fs2 == 0 and fe2 == 0x11 and fm2 == 0x1a3 and fs3 == 0 and fe3 == 0x14 and fm3 == 0x2be and fcsr == 0x60 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x4d3a; op2val:0x45a3;
op3val:0x52be; valaddr_reg:x3; val_offset:4104*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 96, 0, x3, 4104*FLEN/8, x4, x1, x2)

inst_1369:
// fs1 == 0 and fe1 == 0x13 and fm1 == 0x13a and fs2 == 0 and fe2 == 0x11 and fm2 == 0x1a3 and fs3 == 0 and fe3 == 0x14 and fm3 == 0x2be and fcsr == 0x80 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x4d3a; op2val:0x45a3;
op3val:0x52be; valaddr_reg:x3; val_offset:4107*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:128 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 128, 0, x3, 4107*FLEN/8, x4, x1, x2)

inst_1370:
// fs1 == 0 and fe1 == 0x0f and fm1 == 0x070 and fs2 == 0 and fe2 == 0x15 and fm2 == 0x253 and fs3 == 0 and fe3 == 0x14 and fm3 == 0x209 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3c70; op2val:0x5653;
op3val:0x5209; valaddr_reg:x3; val_offset:4110*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 4110*FLEN/8, x4, x1, x2)

inst_1371:
// fs1 == 0 and fe1 == 0x0f and fm1 == 0x070 and fs2 == 0 and fe2 == 0x15 and fm2 == 0x253 and fs3 == 0 and fe3 == 0x14 and fm3 == 0x209 and fcsr == 0x20 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3c70; op2val:0x5653;
op3val:0x5209; valaddr_reg:x3; val_offset:4113*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:32 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 32, 0, x3, 4113*FLEN/8, x4, x1, x2)

inst_1372:
// fs1 == 0 and fe1 == 0x0f and fm1 == 0x070 and fs2 == 0 and fe2 == 0x15 and fm2 == 0x253 and fs3 == 0 and fe3 == 0x14 and fm3 == 0x209 and fcsr == 0x40 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3c70; op2val:0x5653;
op3val:0x5209; valaddr_reg:x3; val_offset:4116*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:64 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 64, 0, x3, 4116*FLEN/8, x4, x1, x2)

inst_1373:
// fs1 == 0 and fe1 == 0x0f and fm1 == 0x070 and fs2 == 0 and fe2 == 0x15 and fm2 == 0x253 and fs3 == 0 and fe3 == 0x14 and fm3 == 0x209 and fcsr == 0x60 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3c70; op2val:0x5653;
op3val:0x5209; valaddr_reg:x3; val_offset:4119*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 96, 0, x3, 4119*FLEN/8, x4, x1, x2)

inst_1374:
// fs1 == 0 and fe1 == 0x0f and fm1 == 0x070 and fs2 == 0 and fe2 == 0x15 and fm2 == 0x253 and fs3 == 0 and fe3 == 0x14 and fm3 == 0x209 and fcsr == 0x80 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3c70; op2val:0x5653;
op3val:0x5209; valaddr_reg:x3; val_offset:4122*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:128 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 128, 0, x3, 4122*FLEN/8, x4, x1, x2)

inst_1375:
// fs1 == 0 and fe1 == 0x14 and fm1 == 0x2bb and fs2 == 0 and fe2 == 0x0f and fm2 == 0x163 and fs3 == 0 and fe3 == 0x12 and fm3 == 0x048 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x52bb; op2val:0x3d63;
op3val:0x4848; valaddr_reg:x3; val_offset:4125*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 4125*FLEN/8, x4, x1, x2)

inst_1376:
// fs1 == 0 and fe1 == 0x14 and fm1 == 0x2bb and fs2 == 0 and fe2 == 0x0f and fm2 == 0x163 and fs3 == 0 and fe3 == 0x12 and fm3 == 0x048 and fcsr == 0x20 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x52bb; op2val:0x3d63;
op3val:0x4848; valaddr_reg:x3; val_offset:4128*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:32 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 32, 0, x3, 4128*FLEN/8, x4, x1, x2)

inst_1377:
// fs1 == 0 and fe1 == 0x14 and fm1 == 0x2bb and fs2 == 0 and fe2 == 0x0f and fm2 == 0x163 and fs3 == 0 and fe3 == 0x12 and fm3 == 0x048 and fcsr == 0x40 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x52bb; op2val:0x3d63;
op3val:0x4848; valaddr_reg:x3; val_offset:4131*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:64 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 64, 0, x3, 4131*FLEN/8, x4, x1, x2)

inst_1378:
// fs1 == 0 and fe1 == 0x14 and fm1 == 0x2bb and fs2 == 0 and fe2 == 0x0f and fm2 == 0x163 and fs3 == 0 and fe3 == 0x12 and fm3 == 0x048 and fcsr == 0x60 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x52bb; op2val:0x3d63;
op3val:0x4848; valaddr_reg:x3; val_offset:4134*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 96, 0, x3, 4134*FLEN/8, x4, x1, x2)

inst_1379:
// fs1 == 0 and fe1 == 0x14 and fm1 == 0x2bb and fs2 == 0 and fe2 == 0x0f and fm2 == 0x163 and fs3 == 0 and fe3 == 0x12 and fm3 == 0x048 and fcsr == 0x80 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x52bb; op2val:0x3d63;
op3val:0x4848; valaddr_reg:x3; val_offset:4137*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:128 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 128, 0, x3, 4137*FLEN/8, x4, x1, x2)

inst_1380:
// fs1 == 0 and fe1 == 0x14 and fm1 == 0x36b and fs2 == 0 and fe2 == 0x0f and fm2 == 0x368 and fs3 == 0 and fe3 == 0x14 and fm3 == 0x1bd and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x536b; op2val:0x3f68;
op3val:0x51bd; valaddr_reg:x3; val_offset:4140*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 4140*FLEN/8, x4, x1, x2)

inst_1381:
// fs1 == 0 and fe1 == 0x14 and fm1 == 0x36b and fs2 == 0 and fe2 == 0x0f and fm2 == 0x368 and fs3 == 0 and fe3 == 0x14 and fm3 == 0x1bd and fcsr == 0x20 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x536b; op2val:0x3f68;
op3val:0x51bd; valaddr_reg:x3; val_offset:4143*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:32 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 32, 0, x3, 4143*FLEN/8, x4, x1, x2)

inst_1382:
// fs1 == 0 and fe1 == 0x14 and fm1 == 0x36b and fs2 == 0 and fe2 == 0x0f and fm2 == 0x368 and fs3 == 0 and fe3 == 0x14 and fm3 == 0x1bd and fcsr == 0x40 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x536b; op2val:0x3f68;
op3val:0x51bd; valaddr_reg:x3; val_offset:4146*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:64 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 64, 0, x3, 4146*FLEN/8, x4, x1, x2)

inst_1383:
// fs1 == 0 and fe1 == 0x14 and fm1 == 0x36b and fs2 == 0 and fe2 == 0x0f and fm2 == 0x368 and fs3 == 0 and fe3 == 0x14 and fm3 == 0x1bd and fcsr == 0x60 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x536b; op2val:0x3f68;
op3val:0x51bd; valaddr_reg:x3; val_offset:4149*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 96, 0, x3, 4149*FLEN/8, x4, x1, x2)

inst_1384:
// fs1 == 0 and fe1 == 0x14 and fm1 == 0x36b and fs2 == 0 and fe2 == 0x0f and fm2 == 0x368 and fs3 == 0 and fe3 == 0x14 and fm3 == 0x1bd and fcsr == 0x80 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x536b; op2val:0x3f68;
op3val:0x51bd; valaddr_reg:x3; val_offset:4152*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:128 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 128, 0, x3, 4152*FLEN/8, x4, x1, x2)

inst_1385:
// fs1 == 0 and fe1 == 0x14 and fm1 == 0x339 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x1c3 and fs3 == 0 and fe3 == 0x13 and fm3 == 0x0d0 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x5339; op2val:0x3dc3;
op3val:0x4cd0; valaddr_reg:x3; val_offset:4155*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 4155*FLEN/8, x4, x1, x2)

inst_1386:
// fs1 == 0 and fe1 == 0x14 and fm1 == 0x339 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x1c3 and fs3 == 0 and fe3 == 0x13 and fm3 == 0x0d0 and fcsr == 0x20 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x5339; op2val:0x3dc3;
op3val:0x4cd0; valaddr_reg:x3; val_offset:4158*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:32 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 32, 0, x3, 4158*FLEN/8, x4, x1, x2)

inst_1387:
// fs1 == 0 and fe1 == 0x14 and fm1 == 0x339 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x1c3 and fs3 == 0 and fe3 == 0x13 and fm3 == 0x0d0 and fcsr == 0x40 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x5339; op2val:0x3dc3;
op3val:0x4cd0; valaddr_reg:x3; val_offset:4161*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:64 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 64, 0, x3, 4161*FLEN/8, x4, x1, x2)

inst_1388:
// fs1 == 0 and fe1 == 0x14 and fm1 == 0x339 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x1c3 and fs3 == 0 and fe3 == 0x13 and fm3 == 0x0d0 and fcsr == 0x60 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x5339; op2val:0x3dc3;
op3val:0x4cd0; valaddr_reg:x3; val_offset:4164*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 96, 0, x3, 4164*FLEN/8, x4, x1, x2)

inst_1389:
// fs1 == 0 and fe1 == 0x14 and fm1 == 0x339 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x1c3 and fs3 == 0 and fe3 == 0x13 and fm3 == 0x0d0 and fcsr == 0x80 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x5339; op2val:0x3dc3;
op3val:0x4cd0; valaddr_reg:x3; val_offset:4167*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:128 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 128, 0, x3, 4167*FLEN/8, x4, x1, x2)

inst_1390:
// fs1 == 0 and fe1 == 0x13 and fm1 == 0x21d and fs2 == 0 and fe2 == 0x10 and fm2 == 0x357 and fs3 == 0 and fe3 == 0x13 and fm3 == 0x270 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x4e1d; op2val:0x4357;
op3val:0x4e70; valaddr_reg:x3; val_offset:4170*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 4170*FLEN/8, x4, x1, x2)

inst_1391:
// fs1 == 0 and fe1 == 0x13 and fm1 == 0x21d and fs2 == 0 and fe2 == 0x10 and fm2 == 0x357 and fs3 == 0 and fe3 == 0x13 and fm3 == 0x270 and fcsr == 0x20 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x4e1d; op2val:0x4357;
op3val:0x4e70; valaddr_reg:x3; val_offset:4173*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:32 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 32, 0, x3, 4173*FLEN/8, x4, x1, x2)

inst_1392:
// fs1 == 0 and fe1 == 0x13 and fm1 == 0x21d and fs2 == 0 and fe2 == 0x10 and fm2 == 0x357 and fs3 == 0 and fe3 == 0x13 and fm3 == 0x270 and fcsr == 0x40 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x4e1d; op2val:0x4357;
op3val:0x4e70; valaddr_reg:x3; val_offset:4176*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:64 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 64, 0, x3, 4176*FLEN/8, x4, x1, x2)

inst_1393:
// fs1 == 0 and fe1 == 0x13 and fm1 == 0x21d and fs2 == 0 and fe2 == 0x10 and fm2 == 0x357 and fs3 == 0 and fe3 == 0x13 and fm3 == 0x270 and fcsr == 0x60 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x4e1d; op2val:0x4357;
op3val:0x4e70; valaddr_reg:x3; val_offset:4179*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 96, 0, x3, 4179*FLEN/8, x4, x1, x2)

inst_1394:
// fs1 == 0 and fe1 == 0x13 and fm1 == 0x21d and fs2 == 0 and fe2 == 0x10 and fm2 == 0x357 and fs3 == 0 and fe3 == 0x13 and fm3 == 0x270 and fcsr == 0x80 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x4e1d; op2val:0x4357;
op3val:0x4e70; valaddr_reg:x3; val_offset:4182*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:128 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 128, 0, x3, 4182*FLEN/8, x4, x1, x2)

inst_1395:
// fs1 == 0 and fe1 == 0x14 and fm1 == 0x3fe and fs2 == 0 and fe2 == 0x0f and fm2 == 0x263 and fs3 == 0 and fe3 == 0x14 and fm3 == 0x0c4 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x53fe; op2val:0x3e63;
op3val:0x50c4; valaddr_reg:x3; val_offset:4185*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 4185*FLEN/8, x4, x1, x2)

inst_1396:
// fs1 == 0 and fe1 == 0x14 and fm1 == 0x3fe and fs2 == 0 and fe2 == 0x0f and fm2 == 0x263 and fs3 == 0 and fe3 == 0x14 and fm3 == 0x0c4 and fcsr == 0x20 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x53fe; op2val:0x3e63;
op3val:0x50c4; valaddr_reg:x3; val_offset:4188*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:32 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 32, 0, x3, 4188*FLEN/8, x4, x1, x2)

inst_1397:
// fs1 == 0 and fe1 == 0x14 and fm1 == 0x3fe and fs2 == 0 and fe2 == 0x0f and fm2 == 0x263 and fs3 == 0 and fe3 == 0x14 and fm3 == 0x0c4 and fcsr == 0x40 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x53fe; op2val:0x3e63;
op3val:0x50c4; valaddr_reg:x3; val_offset:4191*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:64 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 64, 0, x3, 4191*FLEN/8, x4, x1, x2)

inst_1398:
// fs1 == 0 and fe1 == 0x14 and fm1 == 0x3fe and fs2 == 0 and fe2 == 0x0f and fm2 == 0x263 and fs3 == 0 and fe3 == 0x14 and fm3 == 0x0c4 and fcsr == 0x60 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x53fe; op2val:0x3e63;
op3val:0x50c4; valaddr_reg:x3; val_offset:4194*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 96, 0, x3, 4194*FLEN/8, x4, x1, x2)

inst_1399:
// fs1 == 0 and fe1 == 0x14 and fm1 == 0x3fe and fs2 == 0 and fe2 == 0x0f and fm2 == 0x263 and fs3 == 0 and fe3 == 0x14 and fm3 == 0x0c4 and fcsr == 0x80 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x53fe; op2val:0x3e63;
op3val:0x50c4; valaddr_reg:x3; val_offset:4197*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:128 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 128, 0, x3, 4197*FLEN/8, x4, x1, x2)

inst_1400:
// fs1 == 0 and fe1 == 0x13 and fm1 == 0x1ee and fs2 == 0 and fe2 == 0x10 and fm2 == 0x3c0 and fs3 == 0 and fe3 == 0x13 and fm3 == 0x2fd and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x4dee; op2val:0x43c0;
op3val:0x4efd; valaddr_reg:x3; val_offset:4200*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 4200*FLEN/8, x4, x1, x2)

inst_1401:
// fs1 == 0 and fe1 == 0x13 and fm1 == 0x1ee and fs2 == 0 and fe2 == 0x10 and fm2 == 0x3c0 and fs3 == 0 and fe3 == 0x13 and fm3 == 0x2fd and fcsr == 0x20 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x4dee; op2val:0x43c0;
op3val:0x4efd; valaddr_reg:x3; val_offset:4203*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:32 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 32, 0, x3, 4203*FLEN/8, x4, x1, x2)

inst_1402:
// fs1 == 0 and fe1 == 0x13 and fm1 == 0x1ee and fs2 == 0 and fe2 == 0x10 and fm2 == 0x3c0 and fs3 == 0 and fe3 == 0x13 and fm3 == 0x2fd and fcsr == 0x40 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x4dee; op2val:0x43c0;
op3val:0x4efd; valaddr_reg:x3; val_offset:4206*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:64 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 64, 0, x3, 4206*FLEN/8, x4, x1, x2)

inst_1403:
// fs1 == 0 and fe1 == 0x13 and fm1 == 0x1ee and fs2 == 0 and fe2 == 0x10 and fm2 == 0x3c0 and fs3 == 0 and fe3 == 0x13 and fm3 == 0x2fd and fcsr == 0x60 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x4dee; op2val:0x43c0;
op3val:0x4efd; valaddr_reg:x3; val_offset:4209*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 96, 0, x3, 4209*FLEN/8, x4, x1, x2)

inst_1404:
// fs1 == 0 and fe1 == 0x13 and fm1 == 0x1ee and fs2 == 0 and fe2 == 0x10 and fm2 == 0x3c0 and fs3 == 0 and fe3 == 0x13 and fm3 == 0x2fd and fcsr == 0x80 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x4dee; op2val:0x43c0;
op3val:0x4efd; valaddr_reg:x3; val_offset:4212*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:128 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 128, 0, x3, 4212*FLEN/8, x4, x1, x2)

inst_1405:
// fs1 == 0 and fe1 == 0x13 and fm1 == 0x095 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x36c and fs3 == 0 and fe3 == 0x11 and fm3 == 0x00a and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x4c95; op2val:0x436c;
op3val:0x440a; valaddr_reg:x3; val_offset:4215*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 4215*FLEN/8, x4, x1, x2)

inst_1406:
// fs1 == 0 and fe1 == 0x13 and fm1 == 0x095 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x36c and fs3 == 0 and fe3 == 0x11 and fm3 == 0x00a and fcsr == 0x20 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x4c95; op2val:0x436c;
op3val:0x440a; valaddr_reg:x3; val_offset:4218*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:32 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 32, 0, x3, 4218*FLEN/8, x4, x1, x2)

inst_1407:
// fs1 == 0 and fe1 == 0x13 and fm1 == 0x095 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x36c and fs3 == 0 and fe3 == 0x11 and fm3 == 0x00a and fcsr == 0x40 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x4c95; op2val:0x436c;
op3val:0x440a; valaddr_reg:x3; val_offset:4221*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:64 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 64, 0, x3, 4221*FLEN/8, x4, x1, x2)
RVTEST_SIGBASE(x1,signature_x1_12)

inst_1408:
// fs1 == 0 and fe1 == 0x13 and fm1 == 0x095 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x36c and fs3 == 0 and fe3 == 0x11 and fm3 == 0x00a and fcsr == 0x60 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x4c95; op2val:0x436c;
op3val:0x440a; valaddr_reg:x3; val_offset:4224*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 96, 0, x3, 4224*FLEN/8, x4, x1, x2)

inst_1409:
// fs1 == 0 and fe1 == 0x13 and fm1 == 0x095 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x36c and fs3 == 0 and fe3 == 0x11 and fm3 == 0x00a and fcsr == 0x80 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x4c95; op2val:0x436c;
op3val:0x440a; valaddr_reg:x3; val_offset:4227*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:128 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 128, 0, x3, 4227*FLEN/8, x4, x1, x2)

inst_1410:
// fs1 == 0 and fe1 == 0x11 and fm1 == 0x368 and fs2 == 0 and fe2 == 0x12 and fm2 == 0x3ef and fs3 == 0 and fe3 == 0x14 and fm3 == 0x2b2 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x4768; op2val:0x4bef;
op3val:0x52b2; valaddr_reg:x3; val_offset:4230*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 4230*FLEN/8, x4, x1, x2)

inst_1411:
// fs1 == 0 and fe1 == 0x11 and fm1 == 0x368 and fs2 == 0 and fe2 == 0x12 and fm2 == 0x3ef and fs3 == 0 and fe3 == 0x14 and fm3 == 0x2b2 and fcsr == 0x20 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x4768; op2val:0x4bef;
op3val:0x52b2; valaddr_reg:x3; val_offset:4233*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:32 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 32, 0, x3, 4233*FLEN/8, x4, x1, x2)

inst_1412:
// fs1 == 0 and fe1 == 0x11 and fm1 == 0x368 and fs2 == 0 and fe2 == 0x12 and fm2 == 0x3ef and fs3 == 0 and fe3 == 0x14 and fm3 == 0x2b2 and fcsr == 0x40 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x4768; op2val:0x4bef;
op3val:0x52b2; valaddr_reg:x3; val_offset:4236*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:64 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 64, 0, x3, 4236*FLEN/8, x4, x1, x2)

inst_1413:
// fs1 == 0 and fe1 == 0x11 and fm1 == 0x368 and fs2 == 0 and fe2 == 0x12 and fm2 == 0x3ef and fs3 == 0 and fe3 == 0x14 and fm3 == 0x2b2 and fcsr == 0x60 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x4768; op2val:0x4bef;
op3val:0x52b2; valaddr_reg:x3; val_offset:4239*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 96, 0, x3, 4239*FLEN/8, x4, x1, x2)

inst_1414:
// fs1 == 0 and fe1 == 0x11 and fm1 == 0x368 and fs2 == 0 and fe2 == 0x12 and fm2 == 0x3ef and fs3 == 0 and fe3 == 0x14 and fm3 == 0x2b2 and fcsr == 0x80 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x4768; op2val:0x4bef;
op3val:0x52b2; valaddr_reg:x3; val_offset:4242*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:128 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 128, 0, x3, 4242*FLEN/8, x4, x1, x2)

inst_1415:
// fs1 == 0 and fe1 == 0x13 and fm1 == 0x0bf and fs2 == 0 and fe2 == 0x11 and fm2 == 0x286 and fs3 == 0 and fe3 == 0x14 and fm3 == 0x37e and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x4cbf; op2val:0x4686;
op3val:0x537e; valaddr_reg:x3; val_offset:4245*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 4245*FLEN/8, x4, x1, x2)

inst_1416:
// fs1 == 0 and fe1 == 0x13 and fm1 == 0x0bf and fs2 == 0 and fe2 == 0x11 and fm2 == 0x286 and fs3 == 0 and fe3 == 0x14 and fm3 == 0x37e and fcsr == 0x20 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x4cbf; op2val:0x4686;
op3val:0x537e; valaddr_reg:x3; val_offset:4248*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:32 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 32, 0, x3, 4248*FLEN/8, x4, x1, x2)

inst_1417:
// fs1 == 0 and fe1 == 0x13 and fm1 == 0x0bf and fs2 == 0 and fe2 == 0x11 and fm2 == 0x286 and fs3 == 0 and fe3 == 0x14 and fm3 == 0x37e and fcsr == 0x40 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x4cbf; op2val:0x4686;
op3val:0x537e; valaddr_reg:x3; val_offset:4251*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:64 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 64, 0, x3, 4251*FLEN/8, x4, x1, x2)

inst_1418:
// fs1 == 0 and fe1 == 0x13 and fm1 == 0x0bf and fs2 == 0 and fe2 == 0x11 and fm2 == 0x286 and fs3 == 0 and fe3 == 0x14 and fm3 == 0x37e and fcsr == 0x60 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x4cbf; op2val:0x4686;
op3val:0x537e; valaddr_reg:x3; val_offset:4254*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 96, 0, x3, 4254*FLEN/8, x4, x1, x2)

inst_1419:
// fs1 == 0 and fe1 == 0x13 and fm1 == 0x0bf and fs2 == 0 and fe2 == 0x11 and fm2 == 0x286 and fs3 == 0 and fe3 == 0x14 and fm3 == 0x37e and fcsr == 0x80 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x4cbf; op2val:0x4686;
op3val:0x537e; valaddr_reg:x3; val_offset:4257*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:128 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 128, 0, x3, 4257*FLEN/8, x4, x1, x2)

inst_1420:
// fs1 == 0 and fe1 == 0x13 and fm1 == 0x02d and fs2 == 0 and fe2 == 0x11 and fm2 == 0x0e4 and fs3 == 0 and fe3 == 0x13 and fm3 == 0x06f and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x4c2d; op2val:0x44e4;
op3val:0x4c6f; valaddr_reg:x3; val_offset:4260*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 4260*FLEN/8, x4, x1, x2)

inst_1421:
// fs1 == 0 and fe1 == 0x13 and fm1 == 0x02d and fs2 == 0 and fe2 == 0x11 and fm2 == 0x0e4 and fs3 == 0 and fe3 == 0x13 and fm3 == 0x06f and fcsr == 0x20 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x4c2d; op2val:0x44e4;
op3val:0x4c6f; valaddr_reg:x3; val_offset:4263*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:32 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 32, 0, x3, 4263*FLEN/8, x4, x1, x2)

inst_1422:
// fs1 == 0 and fe1 == 0x13 and fm1 == 0x02d and fs2 == 0 and fe2 == 0x11 and fm2 == 0x0e4 and fs3 == 0 and fe3 == 0x13 and fm3 == 0x06f and fcsr == 0x40 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x4c2d; op2val:0x44e4;
op3val:0x4c6f; valaddr_reg:x3; val_offset:4266*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:64 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 64, 0, x3, 4266*FLEN/8, x4, x1, x2)

inst_1423:
// fs1 == 0 and fe1 == 0x13 and fm1 == 0x02d and fs2 == 0 and fe2 == 0x11 and fm2 == 0x0e4 and fs3 == 0 and fe3 == 0x13 and fm3 == 0x06f and fcsr == 0x60 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x4c2d; op2val:0x44e4;
op3val:0x4c6f; valaddr_reg:x3; val_offset:4269*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 96, 0, x3, 4269*FLEN/8, x4, x1, x2)

inst_1424:
// fs1 == 0 and fe1 == 0x13 and fm1 == 0x02d and fs2 == 0 and fe2 == 0x11 and fm2 == 0x0e4 and fs3 == 0 and fe3 == 0x13 and fm3 == 0x06f and fcsr == 0x80 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x4c2d; op2val:0x44e4;
op3val:0x4c6f; valaddr_reg:x3; val_offset:4272*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:128 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 128, 0, x3, 4272*FLEN/8, x4, x1, x2)

inst_1425:
// fs1 == 0 and fe1 == 0x14 and fm1 == 0x026 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x0a3 and fs3 == 0 and fe3 == 0x12 and fm3 == 0x27b and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x5026; op2val:0x40a3;
op3val:0x4a7b; valaddr_reg:x3; val_offset:4275*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 4275*FLEN/8, x4, x1, x2)

inst_1426:
// fs1 == 0 and fe1 == 0x14 and fm1 == 0x026 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x0a3 and fs3 == 0 and fe3 == 0x12 and fm3 == 0x27b and fcsr == 0x20 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x5026; op2val:0x40a3;
op3val:0x4a7b; valaddr_reg:x3; val_offset:4278*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:32 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 32, 0, x3, 4278*FLEN/8, x4, x1, x2)

inst_1427:
// fs1 == 0 and fe1 == 0x14 and fm1 == 0x026 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x0a3 and fs3 == 0 and fe3 == 0x12 and fm3 == 0x27b and fcsr == 0x40 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x5026; op2val:0x40a3;
op3val:0x4a7b; valaddr_reg:x3; val_offset:4281*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:64 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 64, 0, x3, 4281*FLEN/8, x4, x1, x2)

inst_1428:
// fs1 == 0 and fe1 == 0x14 and fm1 == 0x026 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x0a3 and fs3 == 0 and fe3 == 0x12 and fm3 == 0x27b and fcsr == 0x60 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x5026; op2val:0x40a3;
op3val:0x4a7b; valaddr_reg:x3; val_offset:4284*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 96, 0, x3, 4284*FLEN/8, x4, x1, x2)

inst_1429:
// fs1 == 0 and fe1 == 0x14 and fm1 == 0x026 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x0a3 and fs3 == 0 and fe3 == 0x12 and fm3 == 0x27b and fcsr == 0x80 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x5026; op2val:0x40a3;
op3val:0x4a7b; valaddr_reg:x3; val_offset:4287*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:128 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 128, 0, x3, 4287*FLEN/8, x4, x1, x2)

inst_1430:
// fs1 == 0 and fe1 == 0x13 and fm1 == 0x221 and fs2 == 0 and fe2 == 0x11 and fm2 == 0x11b and fs3 == 0 and fe3 == 0x14 and fm3 == 0x3a7 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x4e21; op2val:0x451b;
op3val:0x53a7; valaddr_reg:x3; val_offset:4290*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 4290*FLEN/8, x4, x1, x2)

inst_1431:
// fs1 == 0 and fe1 == 0x13 and fm1 == 0x221 and fs2 == 0 and fe2 == 0x11 and fm2 == 0x11b and fs3 == 0 and fe3 == 0x14 and fm3 == 0x3a7 and fcsr == 0x20 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x4e21; op2val:0x451b;
op3val:0x53a7; valaddr_reg:x3; val_offset:4293*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:32 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 32, 0, x3, 4293*FLEN/8, x4, x1, x2)

inst_1432:
// fs1 == 0 and fe1 == 0x13 and fm1 == 0x221 and fs2 == 0 and fe2 == 0x11 and fm2 == 0x11b and fs3 == 0 and fe3 == 0x14 and fm3 == 0x3a7 and fcsr == 0x40 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x4e21; op2val:0x451b;
op3val:0x53a7; valaddr_reg:x3; val_offset:4296*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:64 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 64, 0, x3, 4296*FLEN/8, x4, x1, x2)

inst_1433:
// fs1 == 0 and fe1 == 0x13 and fm1 == 0x221 and fs2 == 0 and fe2 == 0x11 and fm2 == 0x11b and fs3 == 0 and fe3 == 0x14 and fm3 == 0x3a7 and fcsr == 0x60 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x4e21; op2val:0x451b;
op3val:0x53a7; valaddr_reg:x3; val_offset:4299*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 96, 0, x3, 4299*FLEN/8, x4, x1, x2)

inst_1434:
// fs1 == 0 and fe1 == 0x13 and fm1 == 0x221 and fs2 == 0 and fe2 == 0x11 and fm2 == 0x11b and fs3 == 0 and fe3 == 0x14 and fm3 == 0x3a7 and fcsr == 0x80 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x4e21; op2val:0x451b;
op3val:0x53a7; valaddr_reg:x3; val_offset:4302*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:128 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 128, 0, x3, 4302*FLEN/8, x4, x1, x2)

inst_1435:
// fs1 == 0 and fe1 == 0x14 and fm1 == 0x316 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x018 and fs3 == 0 and fe3 == 0x14 and fm3 == 0x285 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x5316; op2val:0x4018;
op3val:0x5285; valaddr_reg:x3; val_offset:4305*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 4305*FLEN/8, x4, x1, x2)

inst_1436:
// fs1 == 0 and fe1 == 0x14 and fm1 == 0x316 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x018 and fs3 == 0 and fe3 == 0x14 and fm3 == 0x285 and fcsr == 0x20 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x5316; op2val:0x4018;
op3val:0x5285; valaddr_reg:x3; val_offset:4308*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:32 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 32, 0, x3, 4308*FLEN/8, x4, x1, x2)

inst_1437:
// fs1 == 0 and fe1 == 0x14 and fm1 == 0x316 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x018 and fs3 == 0 and fe3 == 0x14 and fm3 == 0x285 and fcsr == 0x40 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x5316; op2val:0x4018;
op3val:0x5285; valaddr_reg:x3; val_offset:4311*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:64 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 64, 0, x3, 4311*FLEN/8, x4, x1, x2)

inst_1438:
// fs1 == 0 and fe1 == 0x14 and fm1 == 0x316 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x018 and fs3 == 0 and fe3 == 0x14 and fm3 == 0x285 and fcsr == 0x60 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x5316; op2val:0x4018;
op3val:0x5285; valaddr_reg:x3; val_offset:4314*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 96, 0, x3, 4314*FLEN/8, x4, x1, x2)

inst_1439:
// fs1 == 0 and fe1 == 0x14 and fm1 == 0x316 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x018 and fs3 == 0 and fe3 == 0x14 and fm3 == 0x285 and fcsr == 0x80 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x5316; op2val:0x4018;
op3val:0x5285; valaddr_reg:x3; val_offset:4317*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:128 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 128, 0, x3, 4317*FLEN/8, x4, x1, x2)

inst_1440:
// fs1 == 0 and fe1 == 0x14 and fm1 == 0x118 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x203 and fs3 == 0 and fe3 == 0x14 and fm3 == 0x351 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x5118; op2val:0x4203;
op3val:0x5351; valaddr_reg:x3; val_offset:4320*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 4320*FLEN/8, x4, x1, x2)

inst_1441:
// fs1 == 0 and fe1 == 0x14 and fm1 == 0x118 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x203 and fs3 == 0 and fe3 == 0x14 and fm3 == 0x351 and fcsr == 0x20 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x5118; op2val:0x4203;
op3val:0x5351; valaddr_reg:x3; val_offset:4323*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:32 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 32, 0, x3, 4323*FLEN/8, x4, x1, x2)

inst_1442:
// fs1 == 0 and fe1 == 0x14 and fm1 == 0x118 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x203 and fs3 == 0 and fe3 == 0x14 and fm3 == 0x351 and fcsr == 0x40 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x5118; op2val:0x4203;
op3val:0x5351; valaddr_reg:x3; val_offset:4326*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:64 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 64, 0, x3, 4326*FLEN/8, x4, x1, x2)

inst_1443:
// fs1 == 0 and fe1 == 0x14 and fm1 == 0x118 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x203 and fs3 == 0 and fe3 == 0x14 and fm3 == 0x351 and fcsr == 0x60 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x5118; op2val:0x4203;
op3val:0x5351; valaddr_reg:x3; val_offset:4329*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 96, 0, x3, 4329*FLEN/8, x4, x1, x2)

inst_1444:
// fs1 == 0 and fe1 == 0x14 and fm1 == 0x118 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x203 and fs3 == 0 and fe3 == 0x14 and fm3 == 0x351 and fcsr == 0x80 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x5118; op2val:0x4203;
op3val:0x5351; valaddr_reg:x3; val_offset:4332*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:128 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 128, 0, x3, 4332*FLEN/8, x4, x1, x2)

inst_1445:
// fs1 == 0 and fe1 == 0x14 and fm1 == 0x388 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x29c and fs3 == 0 and fe3 == 0x14 and fm3 == 0x073 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x5388; op2val:0x3e9c;
op3val:0x5073; valaddr_reg:x3; val_offset:4335*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 4335*FLEN/8, x4, x1, x2)

inst_1446:
// fs1 == 0 and fe1 == 0x14 and fm1 == 0x388 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x29c and fs3 == 0 and fe3 == 0x14 and fm3 == 0x073 and fcsr == 0x20 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x5388; op2val:0x3e9c;
op3val:0x5073; valaddr_reg:x3; val_offset:4338*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:32 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 32, 0, x3, 4338*FLEN/8, x4, x1, x2)

inst_1447:
// fs1 == 0 and fe1 == 0x14 and fm1 == 0x388 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x29c and fs3 == 0 and fe3 == 0x14 and fm3 == 0x073 and fcsr == 0x40 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x5388; op2val:0x3e9c;
op3val:0x5073; valaddr_reg:x3; val_offset:4341*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:64 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 64, 0, x3, 4341*FLEN/8, x4, x1, x2)

inst_1448:
// fs1 == 0 and fe1 == 0x14 and fm1 == 0x388 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x29c and fs3 == 0 and fe3 == 0x14 and fm3 == 0x073 and fcsr == 0x60 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x5388; op2val:0x3e9c;
op3val:0x5073; valaddr_reg:x3; val_offset:4344*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 96, 0, x3, 4344*FLEN/8, x4, x1, x2)

inst_1449:
// fs1 == 0 and fe1 == 0x14 and fm1 == 0x388 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x29c and fs3 == 0 and fe3 == 0x14 and fm3 == 0x073 and fcsr == 0x80 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x5388; op2val:0x3e9c;
op3val:0x5073; valaddr_reg:x3; val_offset:4347*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:128 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 128, 0, x3, 4347*FLEN/8, x4, x1, x2)

inst_1450:
// fs1 == 0 and fe1 == 0x14 and fm1 == 0x1ca and fs2 == 0 and fe2 == 0x0f and fm2 == 0x1e1 and fs3 == 0 and fe3 == 0x11 and fm3 == 0x01e and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x51ca; op2val:0x3de1;
op3val:0x441e; valaddr_reg:x3; val_offset:4350*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 4350*FLEN/8, x4, x1, x2)

inst_1451:
// fs1 == 0 and fe1 == 0x14 and fm1 == 0x1ca and fs2 == 0 and fe2 == 0x0f and fm2 == 0x1e1 and fs3 == 0 and fe3 == 0x11 and fm3 == 0x01e and fcsr == 0x20 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x51ca; op2val:0x3de1;
op3val:0x441e; valaddr_reg:x3; val_offset:4353*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:32 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 32, 0, x3, 4353*FLEN/8, x4, x1, x2)

inst_1452:
// fs1 == 0 and fe1 == 0x14 and fm1 == 0x1ca and fs2 == 0 and fe2 == 0x0f and fm2 == 0x1e1 and fs3 == 0 and fe3 == 0x11 and fm3 == 0x01e and fcsr == 0x40 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x51ca; op2val:0x3de1;
op3val:0x441e; valaddr_reg:x3; val_offset:4356*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:64 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 64, 0, x3, 4356*FLEN/8, x4, x1, x2)

inst_1453:
// fs1 == 0 and fe1 == 0x14 and fm1 == 0x1ca and fs2 == 0 and fe2 == 0x0f and fm2 == 0x1e1 and fs3 == 0 and fe3 == 0x11 and fm3 == 0x01e and fcsr == 0x60 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x51ca; op2val:0x3de1;
op3val:0x441e; valaddr_reg:x3; val_offset:4359*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 96, 0, x3, 4359*FLEN/8, x4, x1, x2)

inst_1454:
// fs1 == 0 and fe1 == 0x14 and fm1 == 0x1ca and fs2 == 0 and fe2 == 0x0f and fm2 == 0x1e1 and fs3 == 0 and fe3 == 0x11 and fm3 == 0x01e and fcsr == 0x80 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x51ca; op2val:0x3de1;
op3val:0x441e; valaddr_reg:x3; val_offset:4362*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:128 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 128, 0, x3, 4362*FLEN/8, x4, x1, x2)

inst_1455:
// fs1 == 0 and fe1 == 0x14 and fm1 == 0x1e4 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x3ed and fs3 == 0 and fe3 == 0x13 and fm3 == 0x35a and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x51e4; op2val:0x3fed;
op3val:0x4f5a; valaddr_reg:x3; val_offset:4365*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 4365*FLEN/8, x4, x1, x2)

inst_1456:
// fs1 == 0 and fe1 == 0x14 and fm1 == 0x1e4 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x3ed and fs3 == 0 and fe3 == 0x13 and fm3 == 0x35a and fcsr == 0x20 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x51e4; op2val:0x3fed;
op3val:0x4f5a; valaddr_reg:x3; val_offset:4368*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:32 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 32, 0, x3, 4368*FLEN/8, x4, x1, x2)

inst_1457:
// fs1 == 0 and fe1 == 0x14 and fm1 == 0x1e4 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x3ed and fs3 == 0 and fe3 == 0x13 and fm3 == 0x35a and fcsr == 0x40 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x51e4; op2val:0x3fed;
op3val:0x4f5a; valaddr_reg:x3; val_offset:4371*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:64 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 64, 0, x3, 4371*FLEN/8, x4, x1, x2)

inst_1458:
// fs1 == 0 and fe1 == 0x14 and fm1 == 0x1e4 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x3ed and fs3 == 0 and fe3 == 0x13 and fm3 == 0x35a and fcsr == 0x60 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x51e4; op2val:0x3fed;
op3val:0x4f5a; valaddr_reg:x3; val_offset:4374*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 96, 0, x3, 4374*FLEN/8, x4, x1, x2)

inst_1459:
// fs1 == 0 and fe1 == 0x14 and fm1 == 0x1e4 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x3ed and fs3 == 0 and fe3 == 0x13 and fm3 == 0x35a and fcsr == 0x80 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x51e4; op2val:0x3fed;
op3val:0x4f5a; valaddr_reg:x3; val_offset:4377*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:128 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 128, 0, x3, 4377*FLEN/8, x4, x1, x2)

inst_1460:
// fs1 == 0 and fe1 == 0x14 and fm1 == 0x20d and fs2 == 0 and fe2 == 0x10 and fm2 == 0x05c and fs3 == 0 and fe3 == 0x14 and fm3 == 0x133 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x520d; op2val:0x405c;
op3val:0x5133; valaddr_reg:x3; val_offset:4380*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 4380*FLEN/8, x4, x1, x2)

inst_1461:
// fs1 == 0 and fe1 == 0x14 and fm1 == 0x20d and fs2 == 0 and fe2 == 0x10 and fm2 == 0x05c and fs3 == 0 and fe3 == 0x14 and fm3 == 0x133 and fcsr == 0x20 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x520d; op2val:0x405c;
op3val:0x5133; valaddr_reg:x3; val_offset:4383*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:32 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 32, 0, x3, 4383*FLEN/8, x4, x1, x2)

inst_1462:
// fs1 == 0 and fe1 == 0x14 and fm1 == 0x20d and fs2 == 0 and fe2 == 0x10 and fm2 == 0x05c and fs3 == 0 and fe3 == 0x14 and fm3 == 0x133 and fcsr == 0x40 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x520d; op2val:0x405c;
op3val:0x5133; valaddr_reg:x3; val_offset:4386*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:64 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 64, 0, x3, 4386*FLEN/8, x4, x1, x2)

inst_1463:
// fs1 == 0 and fe1 == 0x14 and fm1 == 0x20d and fs2 == 0 and fe2 == 0x10 and fm2 == 0x05c and fs3 == 0 and fe3 == 0x14 and fm3 == 0x133 and fcsr == 0x60 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x520d; op2val:0x405c;
op3val:0x5133; valaddr_reg:x3; val_offset:4389*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 96, 0, x3, 4389*FLEN/8, x4, x1, x2)

inst_1464:
// fs1 == 0 and fe1 == 0x14 and fm1 == 0x20d and fs2 == 0 and fe2 == 0x10 and fm2 == 0x05c and fs3 == 0 and fe3 == 0x14 and fm3 == 0x133 and fcsr == 0x80 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x520d; op2val:0x405c;
op3val:0x5133; valaddr_reg:x3; val_offset:4392*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:128 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 128, 0, x3, 4392*FLEN/8, x4, x1, x2)

inst_1465:
// fs1 == 0 and fe1 == 0x13 and fm1 == 0x0c2 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x327 and fs3 == 0 and fe3 == 0x11 and fm3 == 0x016 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x4cc2; op2val:0x4327;
op3val:0x4416; valaddr_reg:x3; val_offset:4395*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 4395*FLEN/8, x4, x1, x2)

inst_1466:
// fs1 == 0 and fe1 == 0x13 and fm1 == 0x0c2 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x327 and fs3 == 0 and fe3 == 0x11 and fm3 == 0x016 and fcsr == 0x20 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x4cc2; op2val:0x4327;
op3val:0x4416; valaddr_reg:x3; val_offset:4398*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:32 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 32, 0, x3, 4398*FLEN/8, x4, x1, x2)

inst_1467:
// fs1 == 0 and fe1 == 0x13 and fm1 == 0x0c2 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x327 and fs3 == 0 and fe3 == 0x11 and fm3 == 0x016 and fcsr == 0x40 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x4cc2; op2val:0x4327;
op3val:0x4416; valaddr_reg:x3; val_offset:4401*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:64 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 64, 0, x3, 4401*FLEN/8, x4, x1, x2)

inst_1468:
// fs1 == 0 and fe1 == 0x13 and fm1 == 0x0c2 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x327 and fs3 == 0 and fe3 == 0x11 and fm3 == 0x016 and fcsr == 0x60 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x4cc2; op2val:0x4327;
op3val:0x4416; valaddr_reg:x3; val_offset:4404*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 96, 0, x3, 4404*FLEN/8, x4, x1, x2)

inst_1469:
// fs1 == 0 and fe1 == 0x13 and fm1 == 0x0c2 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x327 and fs3 == 0 and fe3 == 0x11 and fm3 == 0x016 and fcsr == 0x80 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x4cc2; op2val:0x4327;
op3val:0x4416; valaddr_reg:x3; val_offset:4407*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:128 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 128, 0, x3, 4407*FLEN/8, x4, x1, x2)

inst_1470:
// fs1 == 0 and fe1 == 0x0b and fm1 == 0x28a and fs2 == 0 and fe2 == 0x12 and fm2 == 0x071 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x303 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x2e8a; op2val:0x4871;
op3val:0x3b03; valaddr_reg:x3; val_offset:4410*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 4410*FLEN/8, x4, x1, x2)

inst_1471:
// fs1 == 0 and fe1 == 0x0b and fm1 == 0x28a and fs2 == 0 and fe2 == 0x12 and fm2 == 0x071 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x303 and fcsr == 0x20 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x2e8a; op2val:0x4871;
op3val:0x3b03; valaddr_reg:x3; val_offset:4413*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:32 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 32, 0, x3, 4413*FLEN/8, x4, x1, x2)

inst_1472:
// fs1 == 0 and fe1 == 0x0b and fm1 == 0x28a and fs2 == 0 and fe2 == 0x12 and fm2 == 0x071 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x303 and fcsr == 0x40 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x2e8a; op2val:0x4871;
op3val:0x3b03; valaddr_reg:x3; val_offset:4416*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:64 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 64, 0, x3, 4416*FLEN/8, x4, x1, x2)

inst_1473:
// fs1 == 0 and fe1 == 0x0b and fm1 == 0x28a and fs2 == 0 and fe2 == 0x12 and fm2 == 0x071 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x303 and fcsr == 0x60 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x2e8a; op2val:0x4871;
op3val:0x3b03; valaddr_reg:x3; val_offset:4419*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 96, 0, x3, 4419*FLEN/8, x4, x1, x2)

inst_1474:
// fs1 == 0 and fe1 == 0x0b and fm1 == 0x28a and fs2 == 0 and fe2 == 0x12 and fm2 == 0x071 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x303 and fcsr == 0x80 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x2e8a; op2val:0x4871;
op3val:0x3b03; valaddr_reg:x3; val_offset:4422*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:128 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 128, 0, x3, 4422*FLEN/8, x4, x1, x2)

inst_1475:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x057 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x125 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x156 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3857; op2val:0x3d25;
op3val:0x3956; valaddr_reg:x3; val_offset:4425*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 4425*FLEN/8, x4, x1, x2)

inst_1476:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x057 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x125 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x156 and fcsr == 0x20 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3857; op2val:0x3d25;
op3val:0x3956; valaddr_reg:x3; val_offset:4428*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:32 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 32, 0, x3, 4428*FLEN/8, x4, x1, x2)

inst_1477:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x057 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x125 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x156 and fcsr == 0x40 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3857; op2val:0x3d25;
op3val:0x3956; valaddr_reg:x3; val_offset:4431*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:64 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 64, 0, x3, 4431*FLEN/8, x4, x1, x2)

inst_1478:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x057 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x125 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x156 and fcsr == 0x60 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3857; op2val:0x3d25;
op3val:0x3956; valaddr_reg:x3; val_offset:4434*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 96, 0, x3, 4434*FLEN/8, x4, x1, x2)

inst_1479:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x057 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x125 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x156 and fcsr == 0x80 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3857; op2val:0x3d25;
op3val:0x3956; valaddr_reg:x3; val_offset:4437*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:128 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 128, 0, x3, 4437*FLEN/8, x4, x1, x2)

inst_1480:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x1b1 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x317 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x08b and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x39b1; op2val:0x3717;
op3val:0x348b; valaddr_reg:x3; val_offset:4440*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 4440*FLEN/8, x4, x1, x2)

inst_1481:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x1b1 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x317 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x08b and fcsr == 0x20 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x39b1; op2val:0x3717;
op3val:0x348b; valaddr_reg:x3; val_offset:4443*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:32 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 32, 0, x3, 4443*FLEN/8, x4, x1, x2)

inst_1482:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x1b1 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x317 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x08b and fcsr == 0x40 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x39b1; op2val:0x3717;
op3val:0x348b; valaddr_reg:x3; val_offset:4446*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:64 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 64, 0, x3, 4446*FLEN/8, x4, x1, x2)

inst_1483:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x1b1 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x317 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x08b and fcsr == 0x60 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x39b1; op2val:0x3717;
op3val:0x348b; valaddr_reg:x3; val_offset:4449*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 96, 0, x3, 4449*FLEN/8, x4, x1, x2)

inst_1484:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x1b1 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x317 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x08b and fcsr == 0x80 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x39b1; op2val:0x3717;
op3val:0x348b; valaddr_reg:x3; val_offset:4452*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:128 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 128, 0, x3, 4452*FLEN/8, x4, x1, x2)

inst_1485:
// fs1 == 0 and fe1 == 0x0a and fm1 == 0x2f0 and fs2 == 0 and fe2 == 0x12 and fm2 == 0x32f and fs3 == 0 and fe3 == 0x0e and fm3 == 0x1fb and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x2af0; op2val:0x4b2f;
op3val:0x39fb; valaddr_reg:x3; val_offset:4455*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 4455*FLEN/8, x4, x1, x2)

inst_1486:
// fs1 == 0 and fe1 == 0x0a and fm1 == 0x2f0 and fs2 == 0 and fe2 == 0x12 and fm2 == 0x32f and fs3 == 0 and fe3 == 0x0e and fm3 == 0x1fb and fcsr == 0x20 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x2af0; op2val:0x4b2f;
op3val:0x39fb; valaddr_reg:x3; val_offset:4458*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:32 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 32, 0, x3, 4458*FLEN/8, x4, x1, x2)

inst_1487:
// fs1 == 0 and fe1 == 0x0a and fm1 == 0x2f0 and fs2 == 0 and fe2 == 0x12 and fm2 == 0x32f and fs3 == 0 and fe3 == 0x0e and fm3 == 0x1fb and fcsr == 0x40 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x2af0; op2val:0x4b2f;
op3val:0x39fb; valaddr_reg:x3; val_offset:4461*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:64 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 64, 0, x3, 4461*FLEN/8, x4, x1, x2)

inst_1488:
// fs1 == 0 and fe1 == 0x0a and fm1 == 0x2f0 and fs2 == 0 and fe2 == 0x12 and fm2 == 0x32f and fs3 == 0 and fe3 == 0x0e and fm3 == 0x1fb and fcsr == 0x60 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x2af0; op2val:0x4b2f;
op3val:0x39fb; valaddr_reg:x3; val_offset:4464*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 96, 0, x3, 4464*FLEN/8, x4, x1, x2)

inst_1489:
// fs1 == 0 and fe1 == 0x0a and fm1 == 0x2f0 and fs2 == 0 and fe2 == 0x12 and fm2 == 0x32f and fs3 == 0 and fe3 == 0x0e and fm3 == 0x1fb and fcsr == 0x80 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x2af0; op2val:0x4b2f;
op3val:0x39fb; valaddr_reg:x3; val_offset:4467*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:128 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 128, 0, x3, 4467*FLEN/8, x4, x1, x2)

inst_1490:
// fs1 == 0 and fe1 == 0x0d and fm1 == 0x1d5 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x00f and fs3 == 0 and fe3 == 0x0e and fm3 == 0x1ab and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x35d5; op2val:0x400f;
op3val:0x39ab; valaddr_reg:x3; val_offset:4470*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 4470*FLEN/8, x4, x1, x2)

inst_1491:
// fs1 == 0 and fe1 == 0x0d and fm1 == 0x1d5 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x00f and fs3 == 0 and fe3 == 0x0e and fm3 == 0x1ab and fcsr == 0x20 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x35d5; op2val:0x400f;
op3val:0x39ab; valaddr_reg:x3; val_offset:4473*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:32 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 32, 0, x3, 4473*FLEN/8, x4, x1, x2)

inst_1492:
// fs1 == 0 and fe1 == 0x0d and fm1 == 0x1d5 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x00f and fs3 == 0 and fe3 == 0x0e and fm3 == 0x1ab and fcsr == 0x40 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x35d5; op2val:0x400f;
op3val:0x39ab; valaddr_reg:x3; val_offset:4476*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:64 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 64, 0, x3, 4476*FLEN/8, x4, x1, x2)

inst_1493:
// fs1 == 0 and fe1 == 0x0d and fm1 == 0x1d5 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x00f and fs3 == 0 and fe3 == 0x0e and fm3 == 0x1ab and fcsr == 0x60 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x35d5; op2val:0x400f;
op3val:0x39ab; valaddr_reg:x3; val_offset:4479*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 96, 0, x3, 4479*FLEN/8, x4, x1, x2)

inst_1494:
// fs1 == 0 and fe1 == 0x0d and fm1 == 0x1d5 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x00f and fs3 == 0 and fe3 == 0x0e and fm3 == 0x1ab and fcsr == 0x80 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x35d5; op2val:0x400f;
op3val:0x39ab; valaddr_reg:x3; val_offset:4482*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:128 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 128, 0, x3, 4482*FLEN/8, x4, x1, x2)

inst_1495:
// fs1 == 0 and fe1 == 0x0d and fm1 == 0x35c and fs2 == 0 and fe2 == 0x0f and fm2 == 0x1a4 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x0f1 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x375c; op2val:0x3da4;
op3val:0x38f1; valaddr_reg:x3; val_offset:4485*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 4485*FLEN/8, x4, x1, x2)

inst_1496:
// fs1 == 0 and fe1 == 0x0d and fm1 == 0x35c and fs2 == 0 and fe2 == 0x0f and fm2 == 0x1a4 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x0f1 and fcsr == 0x20 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x375c; op2val:0x3da4;
op3val:0x38f1; valaddr_reg:x3; val_offset:4488*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:32 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 32, 0, x3, 4488*FLEN/8, x4, x1, x2)

inst_1497:
// fs1 == 0 and fe1 == 0x0d and fm1 == 0x35c and fs2 == 0 and fe2 == 0x0f and fm2 == 0x1a4 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x0f1 and fcsr == 0x40 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x375c; op2val:0x3da4;
op3val:0x38f1; valaddr_reg:x3; val_offset:4491*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:64 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 64, 0, x3, 4491*FLEN/8, x4, x1, x2)

inst_1498:
// fs1 == 0 and fe1 == 0x0d and fm1 == 0x35c and fs2 == 0 and fe2 == 0x0f and fm2 == 0x1a4 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x0f1 and fcsr == 0x60 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x375c; op2val:0x3da4;
op3val:0x38f1; valaddr_reg:x3; val_offset:4494*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 96, 0, x3, 4494*FLEN/8, x4, x1, x2)

inst_1499:
// fs1 == 0 and fe1 == 0x0d and fm1 == 0x35c and fs2 == 0 and fe2 == 0x0f and fm2 == 0x1a4 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x0f1 and fcsr == 0x80 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x375c; op2val:0x3da4;
op3val:0x38f1; valaddr_reg:x3; val_offset:4497*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:128 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 128, 0, x3, 4497*FLEN/8, x4, x1, x2)

inst_1500:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x2b4 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x02c and fs3 == 0 and fe3 == 0x0e and fm3 == 0x2bf and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3ab4; op2val:0x3c2c;
op3val:0x3abf; valaddr_reg:x3; val_offset:4500*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 4500*FLEN/8, x4, x1, x2)

inst_1501:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x2b4 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x02c and fs3 == 0 and fe3 == 0x0e and fm3 == 0x2bf and fcsr == 0x20 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3ab4; op2val:0x3c2c;
op3val:0x3abf; valaddr_reg:x3; val_offset:4503*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:32 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 32, 0, x3, 4503*FLEN/8, x4, x1, x2)

inst_1502:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x2b4 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x02c and fs3 == 0 and fe3 == 0x0e and fm3 == 0x2bf and fcsr == 0x40 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3ab4; op2val:0x3c2c;
op3val:0x3abf; valaddr_reg:x3; val_offset:4506*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:64 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 64, 0, x3, 4506*FLEN/8, x4, x1, x2)

inst_1503:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x2b4 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x02c and fs3 == 0 and fe3 == 0x0e and fm3 == 0x2bf and fcsr == 0x60 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3ab4; op2val:0x3c2c;
op3val:0x3abf; valaddr_reg:x3; val_offset:4509*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 96, 0, x3, 4509*FLEN/8, x4, x1, x2)

inst_1504:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x2b4 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x02c and fs3 == 0 and fe3 == 0x0e and fm3 == 0x2bf and fcsr == 0x80 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3ab4; op2val:0x3c2c;
op3val:0x3abf; valaddr_reg:x3; val_offset:4512*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:128 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 128, 0, x3, 4512*FLEN/8, x4, x1, x2)

inst_1505:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x263 and fs2 == 0 and fe2 == 0x0c and fm2 == 0x227 and fs3 == 0 and fe3 == 0x0b and fm3 == 0x3d4 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3a63; op2val:0x3227;
op3val:0x2fd4; valaddr_reg:x3; val_offset:4515*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 4515*FLEN/8, x4, x1, x2)

inst_1506:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x263 and fs2 == 0 and fe2 == 0x0c and fm2 == 0x227 and fs3 == 0 and fe3 == 0x0b and fm3 == 0x3d4 and fcsr == 0x20 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3a63; op2val:0x3227;
op3val:0x2fd4; valaddr_reg:x3; val_offset:4518*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:32 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 32, 0, x3, 4518*FLEN/8, x4, x1, x2)

inst_1507:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x263 and fs2 == 0 and fe2 == 0x0c and fm2 == 0x227 and fs3 == 0 and fe3 == 0x0b and fm3 == 0x3d4 and fcsr == 0x40 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3a63; op2val:0x3227;
op3val:0x2fd4; valaddr_reg:x3; val_offset:4521*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:64 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 64, 0, x3, 4521*FLEN/8, x4, x1, x2)

inst_1508:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x263 and fs2 == 0 and fe2 == 0x0c and fm2 == 0x227 and fs3 == 0 and fe3 == 0x0b and fm3 == 0x3d4 and fcsr == 0x60 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3a63; op2val:0x3227;
op3val:0x2fd4; valaddr_reg:x3; val_offset:4524*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 96, 0, x3, 4524*FLEN/8, x4, x1, x2)

inst_1509:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x263 and fs2 == 0 and fe2 == 0x0c and fm2 == 0x227 and fs3 == 0 and fe3 == 0x0b and fm3 == 0x3d4 and fcsr == 0x80 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3a63; op2val:0x3227;
op3val:0x2fd4; valaddr_reg:x3; val_offset:4527*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:128 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 128, 0, x3, 4527*FLEN/8, x4, x1, x2)

inst_1510:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x025 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x24f and fs3 == 0 and fe3 == 0x0e and fm3 == 0x24b and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3825; op2val:0x3e4f;
op3val:0x3a4b; valaddr_reg:x3; val_offset:4530*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 4530*FLEN/8, x4, x1, x2)

inst_1511:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x025 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x24f and fs3 == 0 and fe3 == 0x0e and fm3 == 0x24b and fcsr == 0x20 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3825; op2val:0x3e4f;
op3val:0x3a4b; valaddr_reg:x3; val_offset:4533*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:32 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 32, 0, x3, 4533*FLEN/8, x4, x1, x2)

inst_1512:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x025 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x24f and fs3 == 0 and fe3 == 0x0e and fm3 == 0x24b and fcsr == 0x40 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3825; op2val:0x3e4f;
op3val:0x3a4b; valaddr_reg:x3; val_offset:4536*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:64 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 64, 0, x3, 4536*FLEN/8, x4, x1, x2)

inst_1513:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x025 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x24f and fs3 == 0 and fe3 == 0x0e and fm3 == 0x24b and fcsr == 0x60 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3825; op2val:0x3e4f;
op3val:0x3a4b; valaddr_reg:x3; val_offset:4539*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 96, 0, x3, 4539*FLEN/8, x4, x1, x2)

inst_1514:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x025 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x24f and fs3 == 0 and fe3 == 0x0e and fm3 == 0x24b and fcsr == 0x80 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3825; op2val:0x3e4f;
op3val:0x3a4b; valaddr_reg:x3; val_offset:4542*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:128 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 128, 0, x3, 4542*FLEN/8, x4, x1, x2)

inst_1515:
// fs1 == 0 and fe1 == 0x0b and fm1 == 0x3cf and fs2 == 0 and fe2 == 0x0e and fm2 == 0x052 and fs3 == 0 and fe3 == 0x0a and fm3 == 0x070 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x2fcf; op2val:0x3852;
op3val:0x2870; valaddr_reg:x3; val_offset:4545*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 4545*FLEN/8, x4, x1, x2)

inst_1516:
// fs1 == 0 and fe1 == 0x0b and fm1 == 0x3cf and fs2 == 0 and fe2 == 0x0e and fm2 == 0x052 and fs3 == 0 and fe3 == 0x0a and fm3 == 0x070 and fcsr == 0x20 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x2fcf; op2val:0x3852;
op3val:0x2870; valaddr_reg:x3; val_offset:4548*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:32 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 32, 0, x3, 4548*FLEN/8, x4, x1, x2)

inst_1517:
// fs1 == 0 and fe1 == 0x0b and fm1 == 0x3cf and fs2 == 0 and fe2 == 0x0e and fm2 == 0x052 and fs3 == 0 and fe3 == 0x0a and fm3 == 0x070 and fcsr == 0x40 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x2fcf; op2val:0x3852;
op3val:0x2870; valaddr_reg:x3; val_offset:4551*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:64 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 64, 0, x3, 4551*FLEN/8, x4, x1, x2)

inst_1518:
// fs1 == 0 and fe1 == 0x0b and fm1 == 0x3cf and fs2 == 0 and fe2 == 0x0e and fm2 == 0x052 and fs3 == 0 and fe3 == 0x0a and fm3 == 0x070 and fcsr == 0x60 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x2fcf; op2val:0x3852;
op3val:0x2870; valaddr_reg:x3; val_offset:4554*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 96, 0, x3, 4554*FLEN/8, x4, x1, x2)

inst_1519:
// fs1 == 0 and fe1 == 0x0b and fm1 == 0x3cf and fs2 == 0 and fe2 == 0x0e and fm2 == 0x052 and fs3 == 0 and fe3 == 0x0a and fm3 == 0x070 and fcsr == 0x80 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x2fcf; op2val:0x3852;
op3val:0x2870; valaddr_reg:x3; val_offset:4557*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:128 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 128, 0, x3, 4557*FLEN/8, x4, x1, x2)

inst_1520:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x083 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x25a and fs3 == 0 and fe3 == 0x0e and fm3 == 0x2eb and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3883; op2val:0x3e5a;
op3val:0x3aeb; valaddr_reg:x3; val_offset:4560*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 4560*FLEN/8, x4, x1, x2)

inst_1521:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x083 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x25a and fs3 == 0 and fe3 == 0x0e and fm3 == 0x2eb and fcsr == 0x20 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3883; op2val:0x3e5a;
op3val:0x3aeb; valaddr_reg:x3; val_offset:4563*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:32 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 32, 0, x3, 4563*FLEN/8, x4, x1, x2)

inst_1522:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x083 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x25a and fs3 == 0 and fe3 == 0x0e and fm3 == 0x2eb and fcsr == 0x40 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3883; op2val:0x3e5a;
op3val:0x3aeb; valaddr_reg:x3; val_offset:4566*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:64 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 64, 0, x3, 4566*FLEN/8, x4, x1, x2)

inst_1523:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x083 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x25a and fs3 == 0 and fe3 == 0x0e and fm3 == 0x2eb and fcsr == 0x60 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3883; op2val:0x3e5a;
op3val:0x3aeb; valaddr_reg:x3; val_offset:4569*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 96, 0, x3, 4569*FLEN/8, x4, x1, x2)

inst_1524:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x083 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x25a and fs3 == 0 and fe3 == 0x0e and fm3 == 0x2eb and fcsr == 0x80 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3883; op2val:0x3e5a;
op3val:0x3aeb; valaddr_reg:x3; val_offset:4572*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:128 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 128, 0, x3, 4572*FLEN/8, x4, x1, x2)

inst_1525:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x282 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x0a3 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x34c and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3a82; op2val:0x3ca3;
op3val:0x3b4c; valaddr_reg:x3; val_offset:4575*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 4575*FLEN/8, x4, x1, x2)

inst_1526:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x282 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x0a3 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x34c and fcsr == 0x20 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3a82; op2val:0x3ca3;
op3val:0x3b4c; valaddr_reg:x3; val_offset:4578*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:32 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 32, 0, x3, 4578*FLEN/8, x4, x1, x2)

inst_1527:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x282 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x0a3 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x34c and fcsr == 0x40 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3a82; op2val:0x3ca3;
op3val:0x3b4c; valaddr_reg:x3; val_offset:4581*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:64 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 64, 0, x3, 4581*FLEN/8, x4, x1, x2)

inst_1528:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x282 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x0a3 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x34c and fcsr == 0x60 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3a82; op2val:0x3ca3;
op3val:0x3b4c; valaddr_reg:x3; val_offset:4584*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 96, 0, x3, 4584*FLEN/8, x4, x1, x2)

inst_1529:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x282 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x0a3 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x34c and fcsr == 0x80 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3a82; op2val:0x3ca3;
op3val:0x3b4c; valaddr_reg:x3; val_offset:4587*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:128 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 128, 0, x3, 4587*FLEN/8, x4, x1, x2)

inst_1530:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x159 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x1a3 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x34b and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3959; op2val:0x3da3;
op3val:0x3b4b; valaddr_reg:x3; val_offset:4590*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 4590*FLEN/8, x4, x1, x2)

inst_1531:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x159 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x1a3 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x34b and fcsr == 0x20 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3959; op2val:0x3da3;
op3val:0x3b4b; valaddr_reg:x3; val_offset:4593*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:32 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 32, 0, x3, 4593*FLEN/8, x4, x1, x2)

inst_1532:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x159 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x1a3 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x34b and fcsr == 0x40 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3959; op2val:0x3da3;
op3val:0x3b4b; valaddr_reg:x3; val_offset:4596*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:64 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 64, 0, x3, 4596*FLEN/8, x4, x1, x2)

inst_1533:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x159 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x1a3 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x34b and fcsr == 0x60 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3959; op2val:0x3da3;
op3val:0x3b4b; valaddr_reg:x3; val_offset:4599*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 96, 0, x3, 4599*FLEN/8, x4, x1, x2)

inst_1534:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x159 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x1a3 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x34b and fcsr == 0x80 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3959; op2val:0x3da3;
op3val:0x3b4b; valaddr_reg:x3; val_offset:4602*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:128 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 128, 0, x3, 4602*FLEN/8, x4, x1, x2)

inst_1535:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x225 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x010 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x1ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3a25; op2val:0x3c10;
op3val:0x39ff; valaddr_reg:x3; val_offset:4605*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 4605*FLEN/8, x4, x1, x2)
RVTEST_SIGBASE(x1,signature_x1_13)

inst_1536:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x225 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x010 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x1ff and fcsr == 0x20 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3a25; op2val:0x3c10;
op3val:0x39ff; valaddr_reg:x3; val_offset:4608*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:32 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 32, 0, x3, 4608*FLEN/8, x4, x1, x2)

inst_1537:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x225 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x010 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x1ff and fcsr == 0x40 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3a25; op2val:0x3c10;
op3val:0x39ff; valaddr_reg:x3; val_offset:4611*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:64 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 64, 0, x3, 4611*FLEN/8, x4, x1, x2)

inst_1538:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x225 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x010 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x1ff and fcsr == 0x60 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3a25; op2val:0x3c10;
op3val:0x39ff; valaddr_reg:x3; val_offset:4614*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 96, 0, x3, 4614*FLEN/8, x4, x1, x2)

inst_1539:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x225 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x010 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x1ff and fcsr == 0x80 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3a25; op2val:0x3c10;
op3val:0x39ff; valaddr_reg:x3; val_offset:4617*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:128 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 128, 0, x3, 4617*FLEN/8, x4, x1, x2)

inst_1540:
// fs1 == 0 and fe1 == 0x0d and fm1 == 0x32b and fs2 == 0 and fe2 == 0x0d and fm2 == 0x221 and fs3 == 0 and fe3 == 0x0c and fm3 == 0x07e and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x372b; op2val:0x3621;
op3val:0x307e; valaddr_reg:x3; val_offset:4620*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 4620*FLEN/8, x4, x1, x2)

inst_1541:
// fs1 == 0 and fe1 == 0x0d and fm1 == 0x32b and fs2 == 0 and fe2 == 0x0d and fm2 == 0x221 and fs3 == 0 and fe3 == 0x0c and fm3 == 0x07e and fcsr == 0x20 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x372b; op2val:0x3621;
op3val:0x307e; valaddr_reg:x3; val_offset:4623*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:32 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 32, 0, x3, 4623*FLEN/8, x4, x1, x2)

inst_1542:
// fs1 == 0 and fe1 == 0x0d and fm1 == 0x32b and fs2 == 0 and fe2 == 0x0d and fm2 == 0x221 and fs3 == 0 and fe3 == 0x0c and fm3 == 0x07e and fcsr == 0x40 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x372b; op2val:0x3621;
op3val:0x307e; valaddr_reg:x3; val_offset:4626*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:64 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 64, 0, x3, 4626*FLEN/8, x4, x1, x2)

inst_1543:
// fs1 == 0 and fe1 == 0x0d and fm1 == 0x32b and fs2 == 0 and fe2 == 0x0d and fm2 == 0x221 and fs3 == 0 and fe3 == 0x0c and fm3 == 0x07e and fcsr == 0x60 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x372b; op2val:0x3621;
op3val:0x307e; valaddr_reg:x3; val_offset:4629*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 96, 0, x3, 4629*FLEN/8, x4, x1, x2)

inst_1544:
// fs1 == 0 and fe1 == 0x0d and fm1 == 0x32b and fs2 == 0 and fe2 == 0x0d and fm2 == 0x221 and fs3 == 0 and fe3 == 0x0c and fm3 == 0x07e and fcsr == 0x80 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x372b; op2val:0x3621;
op3val:0x307e; valaddr_reg:x3; val_offset:4632*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:128 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 128, 0, x3, 4632*FLEN/8, x4, x1, x2)

inst_1545:
// fs1 == 0 and fe1 == 0x0d and fm1 == 0x061 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x09c and fs3 == 0 and fe3 == 0x0e and fm3 == 0x0cd and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3461; op2val:0x409c;
op3val:0x38cd; valaddr_reg:x3; val_offset:4635*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 4635*FLEN/8, x4, x1, x2)

inst_1546:
// fs1 == 0 and fe1 == 0x0d and fm1 == 0x061 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x09c and fs3 == 0 and fe3 == 0x0e and fm3 == 0x0cd and fcsr == 0x20 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3461; op2val:0x409c;
op3val:0x38cd; valaddr_reg:x3; val_offset:4638*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:32 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 32, 0, x3, 4638*FLEN/8, x4, x1, x2)

inst_1547:
// fs1 == 0 and fe1 == 0x0d and fm1 == 0x061 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x09c and fs3 == 0 and fe3 == 0x0e and fm3 == 0x0cd and fcsr == 0x40 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3461; op2val:0x409c;
op3val:0x38cd; valaddr_reg:x3; val_offset:4641*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:64 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 64, 0, x3, 4641*FLEN/8, x4, x1, x2)

inst_1548:
// fs1 == 0 and fe1 == 0x0d and fm1 == 0x061 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x09c and fs3 == 0 and fe3 == 0x0e and fm3 == 0x0cd and fcsr == 0x60 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3461; op2val:0x409c;
op3val:0x38cd; valaddr_reg:x3; val_offset:4644*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 96, 0, x3, 4644*FLEN/8, x4, x1, x2)

inst_1549:
// fs1 == 0 and fe1 == 0x0d and fm1 == 0x061 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x09c and fs3 == 0 and fe3 == 0x0e and fm3 == 0x0cd and fcsr == 0x80 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3461; op2val:0x409c;
op3val:0x38cd; valaddr_reg:x3; val_offset:4647*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:128 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 128, 0, x3, 4647*FLEN/8, x4, x1, x2)

inst_1550:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x0ca and fs2 == 0 and fe2 == 0x0e and fm2 == 0x2fd and fs3 == 0 and fe3 == 0x0d and fm3 == 0x3e0 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x38ca; op2val:0x3afd;
op3val:0x37e0; valaddr_reg:x3; val_offset:4650*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 4650*FLEN/8, x4, x1, x2)

inst_1551:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x0ca and fs2 == 0 and fe2 == 0x0e and fm2 == 0x2fd and fs3 == 0 and fe3 == 0x0d and fm3 == 0x3e0 and fcsr == 0x20 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x38ca; op2val:0x3afd;
op3val:0x37e0; valaddr_reg:x3; val_offset:4653*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:32 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 32, 0, x3, 4653*FLEN/8, x4, x1, x2)

inst_1552:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x0ca and fs2 == 0 and fe2 == 0x0e and fm2 == 0x2fd and fs3 == 0 and fe3 == 0x0d and fm3 == 0x3e0 and fcsr == 0x40 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x38ca; op2val:0x3afd;
op3val:0x37e0; valaddr_reg:x3; val_offset:4656*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:64 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 64, 0, x3, 4656*FLEN/8, x4, x1, x2)

inst_1553:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x0ca and fs2 == 0 and fe2 == 0x0e and fm2 == 0x2fd and fs3 == 0 and fe3 == 0x0d and fm3 == 0x3e0 and fcsr == 0x60 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x38ca; op2val:0x3afd;
op3val:0x37e0; valaddr_reg:x3; val_offset:4659*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 96, 0, x3, 4659*FLEN/8, x4, x1, x2)

inst_1554:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x0ca and fs2 == 0 and fe2 == 0x0e and fm2 == 0x2fd and fs3 == 0 and fe3 == 0x0d and fm3 == 0x3e0 and fcsr == 0x80 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x38ca; op2val:0x3afd;
op3val:0x37e0; valaddr_reg:x3; val_offset:4662*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:128 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 128, 0, x3, 4662*FLEN/8, x4, x1, x2)

inst_1555:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x114 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x06e and fs3 == 0 and fe3 == 0x0e and fm3 == 0x161 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3914; op2val:0x3c6e;
op3val:0x3961; valaddr_reg:x3; val_offset:4665*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 4665*FLEN/8, x4, x1, x2)

inst_1556:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x114 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x06e and fs3 == 0 and fe3 == 0x0e and fm3 == 0x161 and fcsr == 0x20 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3914; op2val:0x3c6e;
op3val:0x3961; valaddr_reg:x3; val_offset:4668*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:32 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 32, 0, x3, 4668*FLEN/8, x4, x1, x2)

inst_1557:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x114 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x06e and fs3 == 0 and fe3 == 0x0e and fm3 == 0x161 and fcsr == 0x40 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3914; op2val:0x3c6e;
op3val:0x3961; valaddr_reg:x3; val_offset:4671*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:64 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 64, 0, x3, 4671*FLEN/8, x4, x1, x2)

inst_1558:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x114 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x06e and fs3 == 0 and fe3 == 0x0e and fm3 == 0x161 and fcsr == 0x60 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3914; op2val:0x3c6e;
op3val:0x3961; valaddr_reg:x3; val_offset:4674*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 96, 0, x3, 4674*FLEN/8, x4, x1, x2)

inst_1559:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x114 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x06e and fs3 == 0 and fe3 == 0x0e and fm3 == 0x161 and fcsr == 0x80 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3914; op2val:0x3c6e;
op3val:0x3961; valaddr_reg:x3; val_offset:4677*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:128 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 128, 0, x3, 4677*FLEN/8, x4, x1, x2)

inst_1560:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x384 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x27d and fs3 == 0 and fe3 == 0x0e and fm3 == 0x1d9 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3b84; op2val:0x3a7d;
op3val:0x39d9; valaddr_reg:x3; val_offset:4680*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 4680*FLEN/8, x4, x1, x2)

inst_1561:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x384 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x27d and fs3 == 0 and fe3 == 0x0e and fm3 == 0x1d9 and fcsr == 0x20 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3b84; op2val:0x3a7d;
op3val:0x39d9; valaddr_reg:x3; val_offset:4683*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:32 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 32, 0, x3, 4683*FLEN/8, x4, x1, x2)

inst_1562:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x384 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x27d and fs3 == 0 and fe3 == 0x0e and fm3 == 0x1d9 and fcsr == 0x40 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3b84; op2val:0x3a7d;
op3val:0x39d9; valaddr_reg:x3; val_offset:4686*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:64 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 64, 0, x3, 4686*FLEN/8, x4, x1, x2)

inst_1563:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x384 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x27d and fs3 == 0 and fe3 == 0x0e and fm3 == 0x1d9 and fcsr == 0x60 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3b84; op2val:0x3a7d;
op3val:0x39d9; valaddr_reg:x3; val_offset:4689*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 96, 0, x3, 4689*FLEN/8, x4, x1, x2)

inst_1564:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x384 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x27d and fs3 == 0 and fe3 == 0x0e and fm3 == 0x1d9 and fcsr == 0x80 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3b84; op2val:0x3a7d;
op3val:0x39d9; valaddr_reg:x3; val_offset:4692*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:128 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 128, 0, x3, 4692*FLEN/8, x4, x1, x2)

inst_1565:
// fs1 == 0 and fe1 == 0x0b and fm1 == 0x000 and fs2 == 0 and fe2 == 0x12 and fm2 == 0x344 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x306 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x2c00; op2val:0x4b44;
op3val:0x3b06; valaddr_reg:x3; val_offset:4695*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 4695*FLEN/8, x4, x1, x2)

inst_1566:
// fs1 == 0 and fe1 == 0x0b and fm1 == 0x000 and fs2 == 0 and fe2 == 0x12 and fm2 == 0x344 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x306 and fcsr == 0x20 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x2c00; op2val:0x4b44;
op3val:0x3b06; valaddr_reg:x3; val_offset:4698*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:32 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 32, 0, x3, 4698*FLEN/8, x4, x1, x2)

inst_1567:
// fs1 == 0 and fe1 == 0x0b and fm1 == 0x000 and fs2 == 0 and fe2 == 0x12 and fm2 == 0x344 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x306 and fcsr == 0x40 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x2c00; op2val:0x4b44;
op3val:0x3b06; valaddr_reg:x3; val_offset:4701*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:64 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 64, 0, x3, 4701*FLEN/8, x4, x1, x2)

inst_1568:
// fs1 == 0 and fe1 == 0x0b and fm1 == 0x000 and fs2 == 0 and fe2 == 0x12 and fm2 == 0x344 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x306 and fcsr == 0x60 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x2c00; op2val:0x4b44;
op3val:0x3b06; valaddr_reg:x3; val_offset:4704*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 96, 0, x3, 4704*FLEN/8, x4, x1, x2)

inst_1569:
// fs1 == 0 and fe1 == 0x0b and fm1 == 0x000 and fs2 == 0 and fe2 == 0x12 and fm2 == 0x344 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x306 and fcsr == 0x80 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x2c00; op2val:0x4b44;
op3val:0x3b06; valaddr_reg:x3; val_offset:4707*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:128 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 128, 0, x3, 4707*FLEN/8, x4, x1, x2)

inst_1570:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x019 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x294 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x23d and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3819; op2val:0x3a94;
op3val:0x363d; valaddr_reg:x3; val_offset:4710*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 4710*FLEN/8, x4, x1, x2)

inst_1571:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x019 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x294 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x23d and fcsr == 0x20 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3819; op2val:0x3a94;
op3val:0x363d; valaddr_reg:x3; val_offset:4713*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:32 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 32, 0, x3, 4713*FLEN/8, x4, x1, x2)

inst_1572:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x019 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x294 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x23d and fcsr == 0x40 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3819; op2val:0x3a94;
op3val:0x363d; valaddr_reg:x3; val_offset:4716*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:64 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 64, 0, x3, 4716*FLEN/8, x4, x1, x2)

inst_1573:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x019 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x294 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x23d and fcsr == 0x60 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3819; op2val:0x3a94;
op3val:0x363d; valaddr_reg:x3; val_offset:4719*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 96, 0, x3, 4719*FLEN/8, x4, x1, x2)

inst_1574:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x019 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x294 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x23d and fcsr == 0x80 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3819; op2val:0x3a94;
op3val:0x363d; valaddr_reg:x3; val_offset:4722*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:128 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 128, 0, x3, 4722*FLEN/8, x4, x1, x2)

inst_1575:
// fs1 == 0 and fe1 == 0x0c and fm1 == 0x140 and fs2 == 0 and fe2 == 0x11 and fm2 == 0x102 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x253 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3140; op2val:0x4502;
op3val:0x3a53; valaddr_reg:x3; val_offset:4725*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 4725*FLEN/8, x4, x1, x2)

inst_1576:
// fs1 == 0 and fe1 == 0x0c and fm1 == 0x140 and fs2 == 0 and fe2 == 0x11 and fm2 == 0x102 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x253 and fcsr == 0x20 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3140; op2val:0x4502;
op3val:0x3a53; valaddr_reg:x3; val_offset:4728*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:32 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 32, 0, x3, 4728*FLEN/8, x4, x1, x2)

inst_1577:
// fs1 == 0 and fe1 == 0x0c and fm1 == 0x140 and fs2 == 0 and fe2 == 0x11 and fm2 == 0x102 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x253 and fcsr == 0x40 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3140; op2val:0x4502;
op3val:0x3a53; valaddr_reg:x3; val_offset:4731*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:64 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 64, 0, x3, 4731*FLEN/8, x4, x1, x2)

inst_1578:
// fs1 == 0 and fe1 == 0x0c and fm1 == 0x140 and fs2 == 0 and fe2 == 0x11 and fm2 == 0x102 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x253 and fcsr == 0x60 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3140; op2val:0x4502;
op3val:0x3a53; valaddr_reg:x3; val_offset:4734*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 96, 0, x3, 4734*FLEN/8, x4, x1, x2)

inst_1579:
// fs1 == 0 and fe1 == 0x0c and fm1 == 0x140 and fs2 == 0 and fe2 == 0x11 and fm2 == 0x102 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x253 and fcsr == 0x80 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3140; op2val:0x4502;
op3val:0x3a53; valaddr_reg:x3; val_offset:4737*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:128 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 128, 0, x3, 4737*FLEN/8, x4, x1, x2)

inst_1580:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x1e6 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x049 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x213 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x39e6; op2val:0x3c49;
op3val:0x3a13; valaddr_reg:x3; val_offset:4740*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 4740*FLEN/8, x4, x1, x2)

inst_1581:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x1e6 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x049 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x213 and fcsr == 0x20 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x39e6; op2val:0x3c49;
op3val:0x3a13; valaddr_reg:x3; val_offset:4743*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:32 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 32, 0, x3, 4743*FLEN/8, x4, x1, x2)

inst_1582:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x1e6 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x049 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x213 and fcsr == 0x40 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x39e6; op2val:0x3c49;
op3val:0x3a13; valaddr_reg:x3; val_offset:4746*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:64 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 64, 0, x3, 4746*FLEN/8, x4, x1, x2)

inst_1583:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x1e6 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x049 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x213 and fcsr == 0x60 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x39e6; op2val:0x3c49;
op3val:0x3a13; valaddr_reg:x3; val_offset:4749*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 96, 0, x3, 4749*FLEN/8, x4, x1, x2)

inst_1584:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x1e6 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x049 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x213 and fcsr == 0x80 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x39e6; op2val:0x3c49;
op3val:0x3a13; valaddr_reg:x3; val_offset:4752*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:128 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 128, 0, x3, 4752*FLEN/8, x4, x1, x2)

inst_1585:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x0e6 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x3d3 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x08b and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x38e6; op2val:0x3bd3;
op3val:0x388b; valaddr_reg:x3; val_offset:4755*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 4755*FLEN/8, x4, x1, x2)

inst_1586:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x0e6 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x3d3 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x08b and fcsr == 0x20 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x38e6; op2val:0x3bd3;
op3val:0x388b; valaddr_reg:x3; val_offset:4758*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:32 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 32, 0, x3, 4758*FLEN/8, x4, x1, x2)

inst_1587:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x0e6 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x3d3 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x08b and fcsr == 0x40 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x38e6; op2val:0x3bd3;
op3val:0x388b; valaddr_reg:x3; val_offset:4761*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:64 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 64, 0, x3, 4761*FLEN/8, x4, x1, x2)

inst_1588:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x0e6 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x3d3 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x08b and fcsr == 0x60 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x38e6; op2val:0x3bd3;
op3val:0x388b; valaddr_reg:x3; val_offset:4764*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 96, 0, x3, 4764*FLEN/8, x4, x1, x2)

inst_1589:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x0e6 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x3d3 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x08b and fcsr == 0x80 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x38e6; op2val:0x3bd3;
op3val:0x388b; valaddr_reg:x3; val_offset:4767*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:128 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 128, 0, x3, 4767*FLEN/8, x4, x1, x2)

inst_1590:
// fs1 == 0 and fe1 == 0x0b and fm1 == 0x0db and fs2 == 0 and fe2 == 0x10 and fm2 == 0x183 and fs3 == 0 and fe3 == 0x0c and fm3 == 0x1b0 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x2cdb; op2val:0x4183;
op3val:0x31b0; valaddr_reg:x3; val_offset:4770*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 4770*FLEN/8, x4, x1, x2)

inst_1591:
// fs1 == 0 and fe1 == 0x0b and fm1 == 0x0db and fs2 == 0 and fe2 == 0x10 and fm2 == 0x183 and fs3 == 0 and fe3 == 0x0c and fm3 == 0x1b0 and fcsr == 0x20 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x2cdb; op2val:0x4183;
op3val:0x31b0; valaddr_reg:x3; val_offset:4773*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:32 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 32, 0, x3, 4773*FLEN/8, x4, x1, x2)

inst_1592:
// fs1 == 0 and fe1 == 0x0b and fm1 == 0x0db and fs2 == 0 and fe2 == 0x10 and fm2 == 0x183 and fs3 == 0 and fe3 == 0x0c and fm3 == 0x1b0 and fcsr == 0x40 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x2cdb; op2val:0x4183;
op3val:0x31b0; valaddr_reg:x3; val_offset:4776*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:64 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 64, 0, x3, 4776*FLEN/8, x4, x1, x2)

inst_1593:
// fs1 == 0 and fe1 == 0x0b and fm1 == 0x0db and fs2 == 0 and fe2 == 0x10 and fm2 == 0x183 and fs3 == 0 and fe3 == 0x0c and fm3 == 0x1b0 and fcsr == 0x60 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x2cdb; op2val:0x4183;
op3val:0x31b0; valaddr_reg:x3; val_offset:4779*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 96, 0, x3, 4779*FLEN/8, x4, x1, x2)

inst_1594:
// fs1 == 0 and fe1 == 0x0b and fm1 == 0x0db and fs2 == 0 and fe2 == 0x10 and fm2 == 0x183 and fs3 == 0 and fe3 == 0x0c and fm3 == 0x1b0 and fcsr == 0x80 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x2cdb; op2val:0x4183;
op3val:0x31b0; valaddr_reg:x3; val_offset:4782*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:128 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 128, 0, x3, 4782*FLEN/8, x4, x1, x2)

inst_1595:
// fs1 == 0 and fe1 == 0x0c and fm1 == 0x0f0 and fs2 == 0 and fe2 == 0x11 and fm2 == 0x28a and fs3 == 0 and fe3 == 0x0e and fm3 == 0x3d4 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x30f0; op2val:0x468a;
op3val:0x3bd4; valaddr_reg:x3; val_offset:4785*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 4785*FLEN/8, x4, x1, x2)

inst_1596:
// fs1 == 0 and fe1 == 0x0c and fm1 == 0x0f0 and fs2 == 0 and fe2 == 0x11 and fm2 == 0x28a and fs3 == 0 and fe3 == 0x0e and fm3 == 0x3d4 and fcsr == 0x20 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x30f0; op2val:0x468a;
op3val:0x3bd4; valaddr_reg:x3; val_offset:4788*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:32 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 32, 0, x3, 4788*FLEN/8, x4, x1, x2)

inst_1597:
// fs1 == 0 and fe1 == 0x0c and fm1 == 0x0f0 and fs2 == 0 and fe2 == 0x11 and fm2 == 0x28a and fs3 == 0 and fe3 == 0x0e and fm3 == 0x3d4 and fcsr == 0x40 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x30f0; op2val:0x468a;
op3val:0x3bd4; valaddr_reg:x3; val_offset:4791*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:64 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 64, 0, x3, 4791*FLEN/8, x4, x1, x2)

inst_1598:
// fs1 == 0 and fe1 == 0x0c and fm1 == 0x0f0 and fs2 == 0 and fe2 == 0x11 and fm2 == 0x28a and fs3 == 0 and fe3 == 0x0e and fm3 == 0x3d4 and fcsr == 0x60 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x30f0; op2val:0x468a;
op3val:0x3bd4; valaddr_reg:x3; val_offset:4794*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 96, 0, x3, 4794*FLEN/8, x4, x1, x2)

inst_1599:
// fs1 == 0 and fe1 == 0x0c and fm1 == 0x0f0 and fs2 == 0 and fe2 == 0x11 and fm2 == 0x28a and fs3 == 0 and fe3 == 0x0e and fm3 == 0x3d4 and fcsr == 0x80 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x30f0; op2val:0x468a;
op3val:0x3bd4; valaddr_reg:x3; val_offset:4797*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:128 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 128, 0, x3, 4797*FLEN/8, x4, x1, x2)

inst_1600:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x3c0 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x1ae and fs3 == 0 and fe3 == 0x0d and fm3 == 0x100 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3bc0; op2val:0x35ae;
op3val:0x3500; valaddr_reg:x3; val_offset:4800*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 4800*FLEN/8, x4, x1, x2)

inst_1601:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x3c0 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x1ae and fs3 == 0 and fe3 == 0x0d and fm3 == 0x100 and fcsr == 0x20 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3bc0; op2val:0x35ae;
op3val:0x3500; valaddr_reg:x3; val_offset:4803*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:32 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 32, 0, x3, 4803*FLEN/8, x4, x1, x2)

inst_1602:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x3c0 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x1ae and fs3 == 0 and fe3 == 0x0d and fm3 == 0x100 and fcsr == 0x40 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3bc0; op2val:0x35ae;
op3val:0x3500; valaddr_reg:x3; val_offset:4806*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:64 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 64, 0, x3, 4806*FLEN/8, x4, x1, x2)

inst_1603:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x3c0 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x1ae and fs3 == 0 and fe3 == 0x0d and fm3 == 0x100 and fcsr == 0x60 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3bc0; op2val:0x35ae;
op3val:0x3500; valaddr_reg:x3; val_offset:4809*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 96, 0, x3, 4809*FLEN/8, x4, x1, x2)

inst_1604:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x3c0 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x1ae and fs3 == 0 and fe3 == 0x0d and fm3 == 0x100 and fcsr == 0x80 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3bc0; op2val:0x35ae;
op3val:0x3500; valaddr_reg:x3; val_offset:4812*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:128 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 128, 0, x3, 4812*FLEN/8, x4, x1, x2)

inst_1605:
// fs1 == 0 and fe1 == 0x0c and fm1 == 0x03b and fs2 == 0 and fe2 == 0x11 and fm2 == 0x054 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x055 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x303b; op2val:0x4454;
op3val:0x3855; valaddr_reg:x3; val_offset:4815*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 4815*FLEN/8, x4, x1, x2)

inst_1606:
// fs1 == 0 and fe1 == 0x0c and fm1 == 0x03b and fs2 == 0 and fe2 == 0x11 and fm2 == 0x054 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x055 and fcsr == 0x20 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x303b; op2val:0x4454;
op3val:0x3855; valaddr_reg:x3; val_offset:4818*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:32 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 32, 0, x3, 4818*FLEN/8, x4, x1, x2)

inst_1607:
// fs1 == 0 and fe1 == 0x0c and fm1 == 0x03b and fs2 == 0 and fe2 == 0x11 and fm2 == 0x054 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x055 and fcsr == 0x40 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x303b; op2val:0x4454;
op3val:0x3855; valaddr_reg:x3; val_offset:4821*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:64 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 64, 0, x3, 4821*FLEN/8, x4, x1, x2)

inst_1608:
// fs1 == 0 and fe1 == 0x0c and fm1 == 0x03b and fs2 == 0 and fe2 == 0x11 and fm2 == 0x054 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x055 and fcsr == 0x60 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x303b; op2val:0x4454;
op3val:0x3855; valaddr_reg:x3; val_offset:4824*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 96, 0, x3, 4824*FLEN/8, x4, x1, x2)

inst_1609:
// fs1 == 0 and fe1 == 0x0c and fm1 == 0x03b and fs2 == 0 and fe2 == 0x11 and fm2 == 0x054 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x055 and fcsr == 0x80 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x303b; op2val:0x4454;
op3val:0x3855; valaddr_reg:x3; val_offset:4827*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:128 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 128, 0, x3, 4827*FLEN/8, x4, x1, x2)

inst_1610:
// fs1 == 0 and fe1 == 0x0d and fm1 == 0x2e6 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x0c8 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x36e6; op2val:0x40c8;
op3val:0x3bff; valaddr_reg:x3; val_offset:4830*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 4830*FLEN/8, x4, x1, x2)

inst_1611:
// fs1 == 0 and fe1 == 0x0d and fm1 == 0x2e6 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x0c8 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x3ff and fcsr == 0x20 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x36e6; op2val:0x40c8;
op3val:0x3bff; valaddr_reg:x3; val_offset:4833*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:32 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 32, 0, x3, 4833*FLEN/8, x4, x1, x2)

inst_1612:
// fs1 == 0 and fe1 == 0x0d and fm1 == 0x2e6 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x0c8 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x3ff and fcsr == 0x40 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x36e6; op2val:0x40c8;
op3val:0x3bff; valaddr_reg:x3; val_offset:4836*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:64 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 64, 0, x3, 4836*FLEN/8, x4, x1, x2)

inst_1613:
// fs1 == 0 and fe1 == 0x0d and fm1 == 0x2e6 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x0c8 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x3ff and fcsr == 0x60 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x36e6; op2val:0x40c8;
op3val:0x3bff; valaddr_reg:x3; val_offset:4839*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 96, 0, x3, 4839*FLEN/8, x4, x1, x2)

inst_1614:
// fs1 == 0 and fe1 == 0x0d and fm1 == 0x2e6 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x0c8 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x3ff and fcsr == 0x80 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x36e6; op2val:0x40c8;
op3val:0x3bff; valaddr_reg:x3; val_offset:4842*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:128 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 128, 0, x3, 4842*FLEN/8, x4, x1, x2)

inst_1615:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x0f7 and fs2 == 0 and fe2 == 0x0c and fm2 == 0x2e0 and fs3 == 0 and fe3 == 0x0b and fm3 == 0x289 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x38f7; op2val:0x32e0;
op3val:0x2e89; valaddr_reg:x3; val_offset:4845*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 4845*FLEN/8, x4, x1, x2)

inst_1616:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x0f7 and fs2 == 0 and fe2 == 0x0c and fm2 == 0x2e0 and fs3 == 0 and fe3 == 0x0b and fm3 == 0x289 and fcsr == 0x20 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x38f7; op2val:0x32e0;
op3val:0x2e89; valaddr_reg:x3; val_offset:4848*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:32 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 32, 0, x3, 4848*FLEN/8, x4, x1, x2)

inst_1617:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x0f7 and fs2 == 0 and fe2 == 0x0c and fm2 == 0x2e0 and fs3 == 0 and fe3 == 0x0b and fm3 == 0x289 and fcsr == 0x40 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x38f7; op2val:0x32e0;
op3val:0x2e89; valaddr_reg:x3; val_offset:4851*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:64 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 64, 0, x3, 4851*FLEN/8, x4, x1, x2)

inst_1618:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x0f7 and fs2 == 0 and fe2 == 0x0c and fm2 == 0x2e0 and fs3 == 0 and fe3 == 0x0b and fm3 == 0x289 and fcsr == 0x60 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x38f7; op2val:0x32e0;
op3val:0x2e89; valaddr_reg:x3; val_offset:4854*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 96, 0, x3, 4854*FLEN/8, x4, x1, x2)

inst_1619:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x0f7 and fs2 == 0 and fe2 == 0x0c and fm2 == 0x2e0 and fs3 == 0 and fe3 == 0x0b and fm3 == 0x289 and fcsr == 0x80 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x38f7; op2val:0x32e0;
op3val:0x2e89; valaddr_reg:x3; val_offset:4857*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:128 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 128, 0, x3, 4857*FLEN/8, x4, x1, x2)

inst_1620:
// fs1 == 0 and fe1 == 0x0c and fm1 == 0x268 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x00b and fs3 == 0 and fe3 == 0x0c and fm3 == 0x17b and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3268; op2val:0x3c0b;
op3val:0x317b; valaddr_reg:x3; val_offset:4860*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 4860*FLEN/8, x4, x1, x2)

inst_1621:
// fs1 == 0 and fe1 == 0x0c and fm1 == 0x268 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x00b and fs3 == 0 and fe3 == 0x0c and fm3 == 0x17b and fcsr == 0x20 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3268; op2val:0x3c0b;
op3val:0x317b; valaddr_reg:x3; val_offset:4863*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:32 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 32, 0, x3, 4863*FLEN/8, x4, x1, x2)

inst_1622:
// fs1 == 0 and fe1 == 0x0c and fm1 == 0x268 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x00b and fs3 == 0 and fe3 == 0x0c and fm3 == 0x17b and fcsr == 0x40 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3268; op2val:0x3c0b;
op3val:0x317b; valaddr_reg:x3; val_offset:4866*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:64 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 64, 0, x3, 4866*FLEN/8, x4, x1, x2)

inst_1623:
// fs1 == 0 and fe1 == 0x0c and fm1 == 0x268 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x00b and fs3 == 0 and fe3 == 0x0c and fm3 == 0x17b and fcsr == 0x60 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3268; op2val:0x3c0b;
op3val:0x317b; valaddr_reg:x3; val_offset:4869*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 96, 0, x3, 4869*FLEN/8, x4, x1, x2)

inst_1624:
// fs1 == 0 and fe1 == 0x0c and fm1 == 0x268 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x00b and fs3 == 0 and fe3 == 0x0c and fm3 == 0x17b and fcsr == 0x80 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3268; op2val:0x3c0b;
op3val:0x317b; valaddr_reg:x3; val_offset:4872*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:128 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 128, 0, x3, 4872*FLEN/8, x4, x1, x2)

inst_1625:
// fs1 == 0 and fe1 == 0x0a and fm1 == 0x371 and fs2 == 0 and fe2 == 0x12 and fm2 == 0x2cc and fs3 == 0 and fe3 == 0x0e and fm3 == 0x213 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x2b71; op2val:0x4acc;
op3val:0x3a13; valaddr_reg:x3; val_offset:4875*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 4875*FLEN/8, x4, x1, x2)

inst_1626:
// fs1 == 0 and fe1 == 0x0a and fm1 == 0x371 and fs2 == 0 and fe2 == 0x12 and fm2 == 0x2cc and fs3 == 0 and fe3 == 0x0e and fm3 == 0x213 and fcsr == 0x20 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x2b71; op2val:0x4acc;
op3val:0x3a13; valaddr_reg:x3; val_offset:4878*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:32 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 32, 0, x3, 4878*FLEN/8, x4, x1, x2)

inst_1627:
// fs1 == 0 and fe1 == 0x0a and fm1 == 0x371 and fs2 == 0 and fe2 == 0x12 and fm2 == 0x2cc and fs3 == 0 and fe3 == 0x0e and fm3 == 0x213 and fcsr == 0x40 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x2b71; op2val:0x4acc;
op3val:0x3a13; valaddr_reg:x3; val_offset:4881*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:64 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 64, 0, x3, 4881*FLEN/8, x4, x1, x2)

inst_1628:
// fs1 == 0 and fe1 == 0x0a and fm1 == 0x371 and fs2 == 0 and fe2 == 0x12 and fm2 == 0x2cc and fs3 == 0 and fe3 == 0x0e and fm3 == 0x213 and fcsr == 0x60 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x2b71; op2val:0x4acc;
op3val:0x3a13; valaddr_reg:x3; val_offset:4884*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 96, 0, x3, 4884*FLEN/8, x4, x1, x2)

inst_1629:
// fs1 == 0 and fe1 == 0x0a and fm1 == 0x371 and fs2 == 0 and fe2 == 0x12 and fm2 == 0x2cc and fs3 == 0 and fe3 == 0x0e and fm3 == 0x213 and fcsr == 0x80 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x2b71; op2val:0x4acc;
op3val:0x3a13; valaddr_reg:x3; val_offset:4887*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:128 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 128, 0, x3, 4887*FLEN/8, x4, x1, x2)

inst_1630:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x327 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x3e3 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x2cd and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3b27; op2val:0x3be3;
op3val:0x3acd; valaddr_reg:x3; val_offset:4890*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 4890*FLEN/8, x4, x1, x2)

inst_1631:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x327 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x3e3 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x2cd and fcsr == 0x20 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3b27; op2val:0x3be3;
op3val:0x3acd; valaddr_reg:x3; val_offset:4893*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:32 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 32, 0, x3, 4893*FLEN/8, x4, x1, x2)

inst_1632:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x327 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x3e3 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x2cd and fcsr == 0x40 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3b27; op2val:0x3be3;
op3val:0x3acd; valaddr_reg:x3; val_offset:4896*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:64 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 64, 0, x3, 4896*FLEN/8, x4, x1, x2)

inst_1633:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x327 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x3e3 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x2cd and fcsr == 0x60 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3b27; op2val:0x3be3;
op3val:0x3acd; valaddr_reg:x3; val_offset:4899*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 96, 0, x3, 4899*FLEN/8, x4, x1, x2)

inst_1634:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x327 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x3e3 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x2cd and fcsr == 0x80 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3b27; op2val:0x3be3;
op3val:0x3acd; valaddr_reg:x3; val_offset:4902*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:128 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 128, 0, x3, 4902*FLEN/8, x4, x1, x2)

inst_1635:
// fs1 == 0 and fe1 == 0x0d and fm1 == 0x3e7 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x200 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x16d and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x37e7; op2val:0x3a00;
op3val:0x356d; valaddr_reg:x3; val_offset:4905*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 4905*FLEN/8, x4, x1, x2)

inst_1636:
// fs1 == 0 and fe1 == 0x0d and fm1 == 0x3e7 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x200 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x16d and fcsr == 0x20 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x37e7; op2val:0x3a00;
op3val:0x356d; valaddr_reg:x3; val_offset:4908*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:32 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 32, 0, x3, 4908*FLEN/8, x4, x1, x2)

inst_1637:
// fs1 == 0 and fe1 == 0x0d and fm1 == 0x3e7 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x200 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x16d and fcsr == 0x40 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x37e7; op2val:0x3a00;
op3val:0x356d; valaddr_reg:x3; val_offset:4911*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:64 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 64, 0, x3, 4911*FLEN/8, x4, x1, x2)

inst_1638:
// fs1 == 0 and fe1 == 0x0d and fm1 == 0x3e7 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x200 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x16d and fcsr == 0x60 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x37e7; op2val:0x3a00;
op3val:0x356d; valaddr_reg:x3; val_offset:4914*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 96, 0, x3, 4914*FLEN/8, x4, x1, x2)

inst_1639:
// fs1 == 0 and fe1 == 0x0d and fm1 == 0x3e7 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x200 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x16d and fcsr == 0x80 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x37e7; op2val:0x3a00;
op3val:0x356d; valaddr_reg:x3; val_offset:4917*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:128 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 128, 0, x3, 4917*FLEN/8, x4, x1, x2)

inst_1640:
// fs1 == 0 and fe1 == 0x0b and fm1 == 0x1a0 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x38d and fs3 == 0 and fe3 == 0x0d and fm3 == 0x0d0 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x2da0; op2val:0x438d;
op3val:0x34d0; valaddr_reg:x3; val_offset:4920*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 4920*FLEN/8, x4, x1, x2)

inst_1641:
// fs1 == 0 and fe1 == 0x0b and fm1 == 0x1a0 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x38d and fs3 == 0 and fe3 == 0x0d and fm3 == 0x0d0 and fcsr == 0x20 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x2da0; op2val:0x438d;
op3val:0x34d0; valaddr_reg:x3; val_offset:4923*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:32 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 32, 0, x3, 4923*FLEN/8, x4, x1, x2)

inst_1642:
// fs1 == 0 and fe1 == 0x0b and fm1 == 0x1a0 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x38d and fs3 == 0 and fe3 == 0x0d and fm3 == 0x0d0 and fcsr == 0x40 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x2da0; op2val:0x438d;
op3val:0x34d0; valaddr_reg:x3; val_offset:4926*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:64 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 64, 0, x3, 4926*FLEN/8, x4, x1, x2)

inst_1643:
// fs1 == 0 and fe1 == 0x0b and fm1 == 0x1a0 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x38d and fs3 == 0 and fe3 == 0x0d and fm3 == 0x0d0 and fcsr == 0x60 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x2da0; op2val:0x438d;
op3val:0x34d0; valaddr_reg:x3; val_offset:4929*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 96, 0, x3, 4929*FLEN/8, x4, x1, x2)

inst_1644:
// fs1 == 0 and fe1 == 0x0b and fm1 == 0x1a0 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x38d and fs3 == 0 and fe3 == 0x0d and fm3 == 0x0d0 and fcsr == 0x80 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x2da0; op2val:0x438d;
op3val:0x34d0; valaddr_reg:x3; val_offset:4932*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:128 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 128, 0, x3, 4932*FLEN/8, x4, x1, x2)

inst_1645:
// fs1 == 0 and fe1 == 0x0d and fm1 == 0x1f7 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x23a and fs3 == 0 and fe3 == 0x0d and fm3 == 0x025 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x35f7; op2val:0x3a3a;
op3val:0x3425; valaddr_reg:x3; val_offset:4935*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 4935*FLEN/8, x4, x1, x2)

inst_1646:
// fs1 == 0 and fe1 == 0x0d and fm1 == 0x1f7 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x23a and fs3 == 0 and fe3 == 0x0d and fm3 == 0x025 and fcsr == 0x20 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x35f7; op2val:0x3a3a;
op3val:0x3425; valaddr_reg:x3; val_offset:4938*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:32 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 32, 0, x3, 4938*FLEN/8, x4, x1, x2)

inst_1647:
// fs1 == 0 and fe1 == 0x0d and fm1 == 0x1f7 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x23a and fs3 == 0 and fe3 == 0x0d and fm3 == 0x025 and fcsr == 0x40 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x35f7; op2val:0x3a3a;
op3val:0x3425; valaddr_reg:x3; val_offset:4941*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:64 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 64, 0, x3, 4941*FLEN/8, x4, x1, x2)

inst_1648:
// fs1 == 0 and fe1 == 0x0d and fm1 == 0x1f7 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x23a and fs3 == 0 and fe3 == 0x0d and fm3 == 0x025 and fcsr == 0x60 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x35f7; op2val:0x3a3a;
op3val:0x3425; valaddr_reg:x3; val_offset:4944*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 96, 0, x3, 4944*FLEN/8, x4, x1, x2)

inst_1649:
// fs1 == 0 and fe1 == 0x0d and fm1 == 0x1f7 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x23a and fs3 == 0 and fe3 == 0x0d and fm3 == 0x025 and fcsr == 0x80 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x35f7; op2val:0x3a3a;
op3val:0x3425; valaddr_reg:x3; val_offset:4947*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:128 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 128, 0, x3, 4947*FLEN/8, x4, x1, x2)

inst_1650:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x074 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x323 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x373 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3874; op2val:0x3b23;
op3val:0x3773; valaddr_reg:x3; val_offset:4950*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 4950*FLEN/8, x4, x1, x2)

inst_1651:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x074 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x323 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x373 and fcsr == 0x20 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3874; op2val:0x3b23;
op3val:0x3773; valaddr_reg:x3; val_offset:4953*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:32 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 32, 0, x3, 4953*FLEN/8, x4, x1, x2)

inst_1652:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x074 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x323 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x373 and fcsr == 0x40 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3874; op2val:0x3b23;
op3val:0x3773; valaddr_reg:x3; val_offset:4956*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:64 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 64, 0, x3, 4956*FLEN/8, x4, x1, x2)

inst_1653:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x074 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x323 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x373 and fcsr == 0x60 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3874; op2val:0x3b23;
op3val:0x3773; valaddr_reg:x3; val_offset:4959*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 96, 0, x3, 4959*FLEN/8, x4, x1, x2)

inst_1654:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x074 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x323 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x373 and fcsr == 0x80 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3874; op2val:0x3b23;
op3val:0x3773; valaddr_reg:x3; val_offset:4962*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:128 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 128, 0, x3, 4962*FLEN/8, x4, x1, x2)

inst_1655:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x3b1 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x08c and fs3 == 0 and fe3 == 0x0c and fm3 == 0x3bf and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3bb1; op2val:0x348c;
op3val:0x33bf; valaddr_reg:x3; val_offset:4965*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 4965*FLEN/8, x4, x1, x2)

inst_1656:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x3b1 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x08c and fs3 == 0 and fe3 == 0x0c and fm3 == 0x3bf and fcsr == 0x20 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3bb1; op2val:0x348c;
op3val:0x33bf; valaddr_reg:x3; val_offset:4968*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:32 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 32, 0, x3, 4968*FLEN/8, x4, x1, x2)

inst_1657:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x3b1 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x08c and fs3 == 0 and fe3 == 0x0c and fm3 == 0x3bf and fcsr == 0x40 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3bb1; op2val:0x348c;
op3val:0x33bf; valaddr_reg:x3; val_offset:4971*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:64 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 64, 0, x3, 4971*FLEN/8, x4, x1, x2)

inst_1658:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x3b1 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x08c and fs3 == 0 and fe3 == 0x0c and fm3 == 0x3bf and fcsr == 0x60 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3bb1; op2val:0x348c;
op3val:0x33bf; valaddr_reg:x3; val_offset:4974*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 96, 0, x3, 4974*FLEN/8, x4, x1, x2)

inst_1659:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x3b1 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x08c and fs3 == 0 and fe3 == 0x0c and fm3 == 0x3bf and fcsr == 0x80 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3bb1; op2val:0x348c;
op3val:0x33bf; valaddr_reg:x3; val_offset:4977*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:128 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 128, 0, x3, 4977*FLEN/8, x4, x1, x2)

inst_1660:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x232 and fs2 == 0 and fe2 == 0x0c and fm2 == 0x1c9 and fs3 == 0 and fe3 == 0x0b and fm3 == 0x2f7 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3a32; op2val:0x31c9;
op3val:0x2ef7; valaddr_reg:x3; val_offset:4980*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 4980*FLEN/8, x4, x1, x2)

inst_1661:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x232 and fs2 == 0 and fe2 == 0x0c and fm2 == 0x1c9 and fs3 == 0 and fe3 == 0x0b and fm3 == 0x2f7 and fcsr == 0x20 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3a32; op2val:0x31c9;
op3val:0x2ef7; valaddr_reg:x3; val_offset:4983*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:32 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 32, 0, x3, 4983*FLEN/8, x4, x1, x2)

inst_1662:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x232 and fs2 == 0 and fe2 == 0x0c and fm2 == 0x1c9 and fs3 == 0 and fe3 == 0x0b and fm3 == 0x2f7 and fcsr == 0x40 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3a32; op2val:0x31c9;
op3val:0x2ef7; valaddr_reg:x3; val_offset:4986*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:64 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 64, 0, x3, 4986*FLEN/8, x4, x1, x2)

inst_1663:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x232 and fs2 == 0 and fe2 == 0x0c and fm2 == 0x1c9 and fs3 == 0 and fe3 == 0x0b and fm3 == 0x2f7 and fcsr == 0x60 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3a32; op2val:0x31c9;
op3val:0x2ef7; valaddr_reg:x3; val_offset:4989*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 96, 0, x3, 4989*FLEN/8, x4, x1, x2)
RVTEST_SIGBASE(x1,signature_x1_14)

inst_1664:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x232 and fs2 == 0 and fe2 == 0x0c and fm2 == 0x1c9 and fs3 == 0 and fe3 == 0x0b and fm3 == 0x2f7 and fcsr == 0x80 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3a32; op2val:0x31c9;
op3val:0x2ef7; valaddr_reg:x3; val_offset:4992*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:128 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 128, 0, x3, 4992*FLEN/8, x4, x1, x2)

inst_1665:
// fs1 == 0 and fe1 == 0x0d and fm1 == 0x1fe and fs2 == 0 and fe2 == 0x0f and fm2 == 0x3de and fs3 == 0 and fe3 == 0x0e and fm3 == 0x1a5 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x35fe; op2val:0x3fde;
op3val:0x39a5; valaddr_reg:x3; val_offset:4995*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 4995*FLEN/8, x4, x1, x2)

inst_1666:
// fs1 == 0 and fe1 == 0x0d and fm1 == 0x1fe and fs2 == 0 and fe2 == 0x0f and fm2 == 0x3de and fs3 == 0 and fe3 == 0x0e and fm3 == 0x1a5 and fcsr == 0x20 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x35fe; op2val:0x3fde;
op3val:0x39a5; valaddr_reg:x3; val_offset:4998*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:32 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 32, 0, x3, 4998*FLEN/8, x4, x1, x2)

inst_1667:
// fs1 == 0 and fe1 == 0x0d and fm1 == 0x1fe and fs2 == 0 and fe2 == 0x0f and fm2 == 0x3de and fs3 == 0 and fe3 == 0x0e and fm3 == 0x1a5 and fcsr == 0x40 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x35fe; op2val:0x3fde;
op3val:0x39a5; valaddr_reg:x3; val_offset:5001*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:64 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 64, 0, x3, 5001*FLEN/8, x4, x1, x2)

inst_1668:
// fs1 == 0 and fe1 == 0x0d and fm1 == 0x1fe and fs2 == 0 and fe2 == 0x0f and fm2 == 0x3de and fs3 == 0 and fe3 == 0x0e and fm3 == 0x1a5 and fcsr == 0x60 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x35fe; op2val:0x3fde;
op3val:0x39a5; valaddr_reg:x3; val_offset:5004*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 96, 0, x3, 5004*FLEN/8, x4, x1, x2)

inst_1669:
// fs1 == 0 and fe1 == 0x0d and fm1 == 0x1fe and fs2 == 0 and fe2 == 0x0f and fm2 == 0x3de and fs3 == 0 and fe3 == 0x0e and fm3 == 0x1a5 and fcsr == 0x80 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x35fe; op2val:0x3fde;
op3val:0x39a5; valaddr_reg:x3; val_offset:5007*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:128 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 128, 0, x3, 5007*FLEN/8, x4, x1, x2)

inst_1670:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x302 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x330 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x20c and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3b02; op2val:0x3b30;
op3val:0x3a0c; valaddr_reg:x3; val_offset:5010*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 5010*FLEN/8, x4, x1, x2)

inst_1671:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x302 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x330 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x20c and fcsr == 0x20 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3b02; op2val:0x3b30;
op3val:0x3a0c; valaddr_reg:x3; val_offset:5013*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:32 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 32, 0, x3, 5013*FLEN/8, x4, x1, x2)

inst_1672:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x302 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x330 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x20c and fcsr == 0x40 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3b02; op2val:0x3b30;
op3val:0x3a0c; valaddr_reg:x3; val_offset:5016*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:64 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 64, 0, x3, 5016*FLEN/8, x4, x1, x2)

inst_1673:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x302 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x330 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x20c and fcsr == 0x60 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3b02; op2val:0x3b30;
op3val:0x3a0c; valaddr_reg:x3; val_offset:5019*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 96, 0, x3, 5019*FLEN/8, x4, x1, x2)

inst_1674:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x302 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x330 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x20c and fcsr == 0x80 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3b02; op2val:0x3b30;
op3val:0x3a0c; valaddr_reg:x3; val_offset:5022*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:128 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 128, 0, x3, 5022*FLEN/8, x4, x1, x2)

inst_1675:
// fs1 == 0 and fe1 == 0x0d and fm1 == 0x223 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x364 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x12c and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3623; op2val:0x3b64;
op3val:0x352c; valaddr_reg:x3; val_offset:5025*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 5025*FLEN/8, x4, x1, x2)

inst_1676:
// fs1 == 0 and fe1 == 0x0d and fm1 == 0x223 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x364 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x12c and fcsr == 0x20 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3623; op2val:0x3b64;
op3val:0x352c; valaddr_reg:x3; val_offset:5028*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:32 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 32, 0, x3, 5028*FLEN/8, x4, x1, x2)

inst_1677:
// fs1 == 0 and fe1 == 0x0d and fm1 == 0x223 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x364 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x12c and fcsr == 0x40 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3623; op2val:0x3b64;
op3val:0x352c; valaddr_reg:x3; val_offset:5031*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:64 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 64, 0, x3, 5031*FLEN/8, x4, x1, x2)

inst_1678:
// fs1 == 0 and fe1 == 0x0d and fm1 == 0x223 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x364 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x12c and fcsr == 0x60 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3623; op2val:0x3b64;
op3val:0x352c; valaddr_reg:x3; val_offset:5034*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 96, 0, x3, 5034*FLEN/8, x4, x1, x2)

inst_1679:
// fs1 == 0 and fe1 == 0x0d and fm1 == 0x223 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x364 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x12c and fcsr == 0x80 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3623; op2val:0x3b64;
op3val:0x352c; valaddr_reg:x3; val_offset:5037*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:128 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 128, 0, x3, 5037*FLEN/8, x4, x1, x2)

inst_1680:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x168 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x105 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x2cb and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3968; op2val:0x3d05;
op3val:0x3acb; valaddr_reg:x3; val_offset:5040*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 5040*FLEN/8, x4, x1, x2)

inst_1681:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x168 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x105 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x2cb and fcsr == 0x40 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3968; op2val:0x3d05;
op3val:0x3acb; valaddr_reg:x3; val_offset:5043*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:64 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 64, 0, x3, 5043*FLEN/8, x4, x1, x2)

inst_1682:
// fs1 == 0 and fe1 == 0x0d and fm1 == 0x195 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x150 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x36b and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3595; op2val:0x4150;
op3val:0x3b6b; valaddr_reg:x3; val_offset:5046*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 5046*FLEN/8, x4, x1, x2)

inst_1683:
// fs1 == 0 and fe1 == 0x0d and fm1 == 0x195 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x150 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x36b and fcsr == 0x20 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3595; op2val:0x4150;
op3val:0x3b6b; valaddr_reg:x3; val_offset:5049*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:32 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 32, 0, x3, 5049*FLEN/8, x4, x1, x2)

inst_1684:
// fs1 == 0 and fe1 == 0x0d and fm1 == 0x195 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x150 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x36b and fcsr == 0x40 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3595; op2val:0x4150;
op3val:0x3b6b; valaddr_reg:x3; val_offset:5052*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:64 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 64, 0, x3, 5052*FLEN/8, x4, x1, x2)

inst_1685:
// fs1 == 0 and fe1 == 0x0d and fm1 == 0x195 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x150 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x36b and fcsr == 0x60 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3595; op2val:0x4150;
op3val:0x3b6b; valaddr_reg:x3; val_offset:5055*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 96, 0, x3, 5055*FLEN/8, x4, x1, x2)

inst_1686:
// fs1 == 0 and fe1 == 0x0d and fm1 == 0x195 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x150 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x36b and fcsr == 0x80 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3595; op2val:0x4150;
op3val:0x3b6b; valaddr_reg:x3; val_offset:5058*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:128 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 128, 0, x3, 5058*FLEN/8, x4, x1, x2)

inst_1687:
// fs1 == 0 and fe1 == 0x0d and fm1 == 0x36d and fs2 == 0 and fe2 == 0x0f and fm2 == 0x177 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x113 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x376d; op2val:0x3d77;
op3val:0x3913; valaddr_reg:x3; val_offset:5061*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 5061*FLEN/8, x4, x1, x2)
#endif


RVTEST_CODE_END
RVMODEL_HALT

RVTEST_DATA_BEGIN
.align 4
rvtest_data:
.word 0xbabecafe
.word 0xabecafeb
.word 0xbecafeba
.word 0xecafebab
test_dataset_0:
NAN_BOXED(14696,16,FLEN)
NAN_BOXED(15621,16,FLEN)
NAN_BOXED(14696,16,FLEN)
NAN_BOXED(14696,16,FLEN)
NAN_BOXED(15621,16,FLEN)
NAN_BOXED(15051,16,FLEN)
NAN_BOXED(14696,16,FLEN)
NAN_BOXED(15621,16,FLEN)
NAN_BOXED(15621,16,FLEN)
NAN_BOXED(14696,16,FLEN)
NAN_BOXED(15621,16,FLEN)
NAN_BOXED(15051,16,FLEN)
NAN_BOXED(14696,16,FLEN)
NAN_BOXED(15621,16,FLEN)
NAN_BOXED(15051,16,FLEN)
NAN_BOXED(13717,16,FLEN)
NAN_BOXED(13717,16,FLEN)
NAN_BOXED(13717,16,FLEN)
NAN_BOXED(13717,16,FLEN)
NAN_BOXED(16720,16,FLEN)
NAN_BOXED(16720,16,FLEN)
NAN_BOXED(13717,16,FLEN)
NAN_BOXED(13717,16,FLEN)
NAN_BOXED(15211,16,FLEN)
NAN_BOXED(13717,16,FLEN)
NAN_BOXED(13717,16,FLEN)
NAN_BOXED(13717,16,FLEN)
NAN_BOXED(13717,16,FLEN)
NAN_BOXED(13717,16,FLEN)
NAN_BOXED(15211,16,FLEN)
NAN_BOXED(14189,16,FLEN)
NAN_BOXED(15735,16,FLEN)
NAN_BOXED(14189,16,FLEN)
NAN_BOXED(14189,16,FLEN)
NAN_BOXED(15735,16,FLEN)
NAN_BOXED(14611,16,FLEN)
NAN_BOXED(14189,16,FLEN)
NAN_BOXED(15735,16,FLEN)
NAN_BOXED(14611,16,FLEN)
NAN_BOXED(14189,16,FLEN)
NAN_BOXED(15735,16,FLEN)
NAN_BOXED(14611,16,FLEN)
NAN_BOXED(14189,16,FLEN)
NAN_BOXED(15735,16,FLEN)
NAN_BOXED(14611,16,FLEN)
NAN_BOXED(15241,16,FLEN)
NAN_BOXED(14382,16,FLEN)
NAN_BOXED(14305,16,FLEN)
NAN_BOXED(15241,16,FLEN)
NAN_BOXED(14382,16,FLEN)
NAN_BOXED(14305,16,FLEN)
NAN_BOXED(15241,16,FLEN)
NAN_BOXED(14382,16,FLEN)
NAN_BOXED(14305,16,FLEN)
NAN_BOXED(15241,16,FLEN)
NAN_BOXED(14382,16,FLEN)
NAN_BOXED(14305,16,FLEN)
NAN_BOXED(15241,16,FLEN)
NAN_BOXED(14382,16,FLEN)
NAN_BOXED(14305,16,FLEN)
NAN_BOXED(15283,16,FLEN)
NAN_BOXED(14517,16,FLEN)
NAN_BOXED(14471,16,FLEN)
NAN_BOXED(15283,16,FLEN)
NAN_BOXED(14517,16,FLEN)
NAN_BOXED(14471,16,FLEN)
NAN_BOXED(15283,16,FLEN)
NAN_BOXED(14517,16,FLEN)
NAN_BOXED(14471,16,FLEN)
NAN_BOXED(15283,16,FLEN)
NAN_BOXED(14517,16,FLEN)
NAN_BOXED(14471,16,FLEN)
NAN_BOXED(15283,16,FLEN)
NAN_BOXED(14517,16,FLEN)
NAN_BOXED(14471,16,FLEN)
NAN_BOXED(15216,16,FLEN)
NAN_BOXED(15314,16,FLEN)
NAN_BOXED(15174,16,FLEN)
NAN_BOXED(15216,16,FLEN)
NAN_BOXED(15314,16,FLEN)
NAN_BOXED(15174,16,FLEN)
NAN_BOXED(15216,16,FLEN)
NAN_BOXED(15314,16,FLEN)
NAN_BOXED(15174,16,FLEN)
NAN_BOXED(15216,16,FLEN)
NAN_BOXED(15314,16,FLEN)
NAN_BOXED(15174,16,FLEN)
NAN_BOXED(15216,16,FLEN)
NAN_BOXED(15314,16,FLEN)
NAN_BOXED(15174,16,FLEN)
NAN_BOXED(14490,16,FLEN)
NAN_BOXED(13520,16,FLEN)
NAN_BOXED(12682,16,FLEN)
NAN_BOXED(14490,16,FLEN)
NAN_BOXED(13520,16,FLEN)
NAN_BOXED(12682,16,FLEN)
NAN_BOXED(14490,16,FLEN)
NAN_BOXED(13520,16,FLEN)
NAN_BOXED(12682,16,FLEN)
NAN_BOXED(14490,16,FLEN)
NAN_BOXED(13520,16,FLEN)
NAN_BOXED(12682,16,FLEN)
NAN_BOXED(14490,16,FLEN)
NAN_BOXED(13520,16,FLEN)
NAN_BOXED(12682,16,FLEN)
NAN_BOXED(15106,16,FLEN)
NAN_BOXED(15127,16,FLEN)
NAN_BOXED(14902,16,FLEN)
NAN_BOXED(15106,16,FLEN)
NAN_BOXED(15127,16,FLEN)
NAN_BOXED(14902,16,FLEN)
NAN_BOXED(15106,16,FLEN)
NAN_BOXED(15127,16,FLEN)
NAN_BOXED(14902,16,FLEN)
NAN_BOXED(15106,16,FLEN)
NAN_BOXED(15127,16,FLEN)
NAN_BOXED(14902,16,FLEN)
NAN_BOXED(15106,16,FLEN)
NAN_BOXED(15127,16,FLEN)
NAN_BOXED(14902,16,FLEN)
NAN_BOXED(13814,16,FLEN)
NAN_BOXED(12413,16,FLEN)
NAN_BOXED(10929,16,FLEN)
NAN_BOXED(13814,16,FLEN)
NAN_BOXED(12413,16,FLEN)
NAN_BOXED(10929,16,FLEN)
NAN_BOXED(13814,16,FLEN)
NAN_BOXED(12413,16,FLEN)
NAN_BOXED(10929,16,FLEN)
NAN_BOXED(13814,16,FLEN)
NAN_BOXED(12413,16,FLEN)
NAN_BOXED(10929,16,FLEN)
NAN_BOXED(13814,16,FLEN)
NAN_BOXED(12413,16,FLEN)
NAN_BOXED(10929,16,FLEN)
NAN_BOXED(14020,16,FLEN)
NAN_BOXED(15796,16,FLEN)
NAN_BOXED(14547,16,FLEN)
NAN_BOXED(14020,16,FLEN)
NAN_BOXED(15796,16,FLEN)
NAN_BOXED(14547,16,FLEN)
NAN_BOXED(14020,16,FLEN)
NAN_BOXED(15796,16,FLEN)
NAN_BOXED(14547,16,FLEN)
NAN_BOXED(14020,16,FLEN)
NAN_BOXED(15796,16,FLEN)
NAN_BOXED(14547,16,FLEN)
NAN_BOXED(14020,16,FLEN)
NAN_BOXED(15796,16,FLEN)
NAN_BOXED(14547,16,FLEN)
NAN_BOXED(9748,16,FLEN)
NAN_BOXED(20740,16,FLEN)
NAN_BOXED(15264,16,FLEN)
NAN_BOXED(9748,16,FLEN)
NAN_BOXED(20740,16,FLEN)
NAN_BOXED(15264,16,FLEN)
NAN_BOXED(9748,16,FLEN)
NAN_BOXED(20740,16,FLEN)
NAN_BOXED(15264,16,FLEN)
NAN_BOXED(9748,16,FLEN)
NAN_BOXED(20740,16,FLEN)
NAN_BOXED(15264,16,FLEN)
NAN_BOXED(9748,16,FLEN)
NAN_BOXED(20740,16,FLEN)
NAN_BOXED(15264,16,FLEN)
NAN_BOXED(12423,16,FLEN)
NAN_BOXED(17668,16,FLEN)
NAN_BOXED(14766,16,FLEN)
NAN_BOXED(12423,16,FLEN)
NAN_BOXED(17668,16,FLEN)
NAN_BOXED(14766,16,FLEN)
NAN_BOXED(12423,16,FLEN)
NAN_BOXED(17668,16,FLEN)
NAN_BOXED(14766,16,FLEN)
NAN_BOXED(12423,16,FLEN)
NAN_BOXED(17668,16,FLEN)
NAN_BOXED(14766,16,FLEN)
NAN_BOXED(12423,16,FLEN)
NAN_BOXED(17668,16,FLEN)
NAN_BOXED(14766,16,FLEN)
NAN_BOXED(15064,16,FLEN)
NAN_BOXED(15391,16,FLEN)
NAN_BOXED(15118,16,FLEN)
NAN_BOXED(15064,16,FLEN)
NAN_BOXED(15391,16,FLEN)
NAN_BOXED(15118,16,FLEN)
NAN_BOXED(15064,16,FLEN)
NAN_BOXED(15391,16,FLEN)
NAN_BOXED(15118,16,FLEN)
NAN_BOXED(15064,16,FLEN)
NAN_BOXED(15391,16,FLEN)
NAN_BOXED(15118,16,FLEN)
NAN_BOXED(15064,16,FLEN)
NAN_BOXED(15391,16,FLEN)
NAN_BOXED(15118,16,FLEN)
NAN_BOXED(14728,16,FLEN)
NAN_BOXED(13377,16,FLEN)
NAN_BOXED(12770,16,FLEN)
NAN_BOXED(14728,16,FLEN)
NAN_BOXED(13377,16,FLEN)
NAN_BOXED(12770,16,FLEN)
NAN_BOXED(14728,16,FLEN)
NAN_BOXED(13377,16,FLEN)
NAN_BOXED(12770,16,FLEN)
NAN_BOXED(14728,16,FLEN)
NAN_BOXED(13377,16,FLEN)
NAN_BOXED(12770,16,FLEN)
NAN_BOXED(14728,16,FLEN)
NAN_BOXED(13377,16,FLEN)
NAN_BOXED(12770,16,FLEN)
NAN_BOXED(14989,16,FLEN)
NAN_BOXED(14357,16,FLEN)
NAN_BOXED(14001,16,FLEN)
NAN_BOXED(14989,16,FLEN)
NAN_BOXED(14357,16,FLEN)
NAN_BOXED(14001,16,FLEN)
NAN_BOXED(14989,16,FLEN)
NAN_BOXED(14357,16,FLEN)
NAN_BOXED(14001,16,FLEN)
NAN_BOXED(14989,16,FLEN)
NAN_BOXED(14357,16,FLEN)
NAN_BOXED(14001,16,FLEN)
NAN_BOXED(14989,16,FLEN)
NAN_BOXED(14357,16,FLEN)
NAN_BOXED(14001,16,FLEN)
NAN_BOXED(13767,16,FLEN)
NAN_BOXED(16115,16,FLEN)
NAN_BOXED(14597,16,FLEN)
NAN_BOXED(13767,16,FLEN)
NAN_BOXED(16115,16,FLEN)
NAN_BOXED(14597,16,FLEN)
NAN_BOXED(13767,16,FLEN)
NAN_BOXED(16115,16,FLEN)
NAN_BOXED(14597,16,FLEN)
NAN_BOXED(13767,16,FLEN)
NAN_BOXED(16115,16,FLEN)
NAN_BOXED(14597,16,FLEN)
NAN_BOXED(13767,16,FLEN)
NAN_BOXED(16115,16,FLEN)
NAN_BOXED(14597,16,FLEN)
NAN_BOXED(14140,16,FLEN)
NAN_BOXED(16421,16,FLEN)
NAN_BOXED(15231,16,FLEN)
NAN_BOXED(14140,16,FLEN)
NAN_BOXED(16421,16,FLEN)
NAN_BOXED(15231,16,FLEN)
NAN_BOXED(14140,16,FLEN)
NAN_BOXED(16421,16,FLEN)
NAN_BOXED(15231,16,FLEN)
NAN_BOXED(14140,16,FLEN)
NAN_BOXED(16421,16,FLEN)
NAN_BOXED(15231,16,FLEN)
NAN_BOXED(14140,16,FLEN)
NAN_BOXED(16421,16,FLEN)
NAN_BOXED(15231,16,FLEN)
NAN_BOXED(15237,16,FLEN)
NAN_BOXED(15041,16,FLEN)
NAN_BOXED(14938,16,FLEN)
NAN_BOXED(15237,16,FLEN)
NAN_BOXED(15041,16,FLEN)
NAN_BOXED(14938,16,FLEN)
NAN_BOXED(15237,16,FLEN)
NAN_BOXED(15041,16,FLEN)
NAN_BOXED(14938,16,FLEN)
NAN_BOXED(15237,16,FLEN)
NAN_BOXED(15041,16,FLEN)
NAN_BOXED(14938,16,FLEN)
NAN_BOXED(15237,16,FLEN)
NAN_BOXED(15041,16,FLEN)
NAN_BOXED(14938,16,FLEN)
NAN_BOXED(13597,16,FLEN)
NAN_BOXED(16169,16,FLEN)
NAN_BOXED(14484,16,FLEN)
NAN_BOXED(13597,16,FLEN)
NAN_BOXED(16169,16,FLEN)
NAN_BOXED(14484,16,FLEN)
NAN_BOXED(13597,16,FLEN)
NAN_BOXED(16169,16,FLEN)
NAN_BOXED(14484,16,FLEN)
NAN_BOXED(13597,16,FLEN)
NAN_BOXED(16169,16,FLEN)
NAN_BOXED(14484,16,FLEN)
NAN_BOXED(13597,16,FLEN)
NAN_BOXED(16169,16,FLEN)
NAN_BOXED(14484,16,FLEN)
NAN_BOXED(14716,16,FLEN)
NAN_BOXED(14549,16,FLEN)
NAN_BOXED(13985,16,FLEN)
NAN_BOXED(14716,16,FLEN)
NAN_BOXED(14549,16,FLEN)
NAN_BOXED(13985,16,FLEN)
NAN_BOXED(14716,16,FLEN)
NAN_BOXED(14549,16,FLEN)
NAN_BOXED(13985,16,FLEN)
NAN_BOXED(14716,16,FLEN)
NAN_BOXED(14549,16,FLEN)
NAN_BOXED(13985,16,FLEN)
NAN_BOXED(14716,16,FLEN)
NAN_BOXED(14549,16,FLEN)
NAN_BOXED(13985,16,FLEN)
NAN_BOXED(14431,16,FLEN)
NAN_BOXED(15647,16,FLEN)
NAN_BOXED(14746,16,FLEN)
NAN_BOXED(14431,16,FLEN)
NAN_BOXED(15647,16,FLEN)
NAN_BOXED(14746,16,FLEN)
NAN_BOXED(14431,16,FLEN)
NAN_BOXED(15647,16,FLEN)
NAN_BOXED(14746,16,FLEN)
NAN_BOXED(14431,16,FLEN)
NAN_BOXED(15647,16,FLEN)
NAN_BOXED(14746,16,FLEN)
NAN_BOXED(14431,16,FLEN)
NAN_BOXED(15647,16,FLEN)
NAN_BOXED(14746,16,FLEN)
NAN_BOXED(12948,16,FLEN)
NAN_BOXED(15835,16,FLEN)
NAN_BOXED(13520,16,FLEN)
NAN_BOXED(12948,16,FLEN)
NAN_BOXED(15835,16,FLEN)
NAN_BOXED(13520,16,FLEN)
NAN_BOXED(12948,16,FLEN)
NAN_BOXED(15835,16,FLEN)
NAN_BOXED(13520,16,FLEN)
NAN_BOXED(12948,16,FLEN)
NAN_BOXED(15835,16,FLEN)
NAN_BOXED(13520,16,FLEN)
NAN_BOXED(12948,16,FLEN)
NAN_BOXED(15835,16,FLEN)
NAN_BOXED(13520,16,FLEN)
NAN_BOXED(14860,16,FLEN)
NAN_BOXED(14465,16,FLEN)
NAN_BOXED(14031,16,FLEN)
NAN_BOXED(14860,16,FLEN)
NAN_BOXED(14465,16,FLEN)
NAN_BOXED(14031,16,FLEN)
NAN_BOXED(14860,16,FLEN)
NAN_BOXED(14465,16,FLEN)
NAN_BOXED(14031,16,FLEN)
NAN_BOXED(14860,16,FLEN)
NAN_BOXED(14465,16,FLEN)
NAN_BOXED(14031,16,FLEN)
NAN_BOXED(14860,16,FLEN)
NAN_BOXED(14465,16,FLEN)
NAN_BOXED(14031,16,FLEN)
NAN_BOXED(14232,16,FLEN)
NAN_BOXED(13365,16,FLEN)
NAN_BOXED(12285,16,FLEN)
NAN_BOXED(14232,16,FLEN)
NAN_BOXED(13365,16,FLEN)
NAN_BOXED(12285,16,FLEN)
NAN_BOXED(14232,16,FLEN)
NAN_BOXED(13365,16,FLEN)
NAN_BOXED(12285,16,FLEN)
NAN_BOXED(14232,16,FLEN)
NAN_BOXED(13365,16,FLEN)
NAN_BOXED(12285,16,FLEN)
NAN_BOXED(14232,16,FLEN)
NAN_BOXED(13365,16,FLEN)
NAN_BOXED(12285,16,FLEN)
NAN_BOXED(13396,16,FLEN)
NAN_BOXED(16707,16,FLEN)
NAN_BOXED(14770,16,FLEN)
NAN_BOXED(13396,16,FLEN)
NAN_BOXED(16707,16,FLEN)
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NAN_BOXED(13815,16,FLEN)
NAN_BOXED(14906,16,FLEN)
NAN_BOXED(13349,16,FLEN)
NAN_BOXED(13815,16,FLEN)
NAN_BOXED(14906,16,FLEN)
NAN_BOXED(13349,16,FLEN)
NAN_BOXED(14452,16,FLEN)
NAN_BOXED(15139,16,FLEN)
NAN_BOXED(14195,16,FLEN)
NAN_BOXED(14452,16,FLEN)
NAN_BOXED(15139,16,FLEN)
NAN_BOXED(14195,16,FLEN)
NAN_BOXED(14452,16,FLEN)
NAN_BOXED(15139,16,FLEN)
NAN_BOXED(14195,16,FLEN)
NAN_BOXED(14452,16,FLEN)
NAN_BOXED(15139,16,FLEN)
NAN_BOXED(14195,16,FLEN)
NAN_BOXED(14452,16,FLEN)
NAN_BOXED(15139,16,FLEN)
NAN_BOXED(14195,16,FLEN)
NAN_BOXED(15281,16,FLEN)
NAN_BOXED(13452,16,FLEN)
NAN_BOXED(13247,16,FLEN)
NAN_BOXED(15281,16,FLEN)
NAN_BOXED(13452,16,FLEN)
NAN_BOXED(13247,16,FLEN)
NAN_BOXED(15281,16,FLEN)
NAN_BOXED(13452,16,FLEN)
NAN_BOXED(13247,16,FLEN)
NAN_BOXED(15281,16,FLEN)
NAN_BOXED(13452,16,FLEN)
NAN_BOXED(13247,16,FLEN)
NAN_BOXED(15281,16,FLEN)
NAN_BOXED(13452,16,FLEN)
NAN_BOXED(13247,16,FLEN)
NAN_BOXED(14898,16,FLEN)
NAN_BOXED(12745,16,FLEN)
NAN_BOXED(12023,16,FLEN)
NAN_BOXED(14898,16,FLEN)
NAN_BOXED(12745,16,FLEN)
NAN_BOXED(12023,16,FLEN)
NAN_BOXED(14898,16,FLEN)
NAN_BOXED(12745,16,FLEN)
NAN_BOXED(12023,16,FLEN)
NAN_BOXED(14898,16,FLEN)
NAN_BOXED(12745,16,FLEN)
NAN_BOXED(12023,16,FLEN)
NAN_BOXED(14898,16,FLEN)
NAN_BOXED(12745,16,FLEN)
NAN_BOXED(12023,16,FLEN)
NAN_BOXED(13822,16,FLEN)
NAN_BOXED(16350,16,FLEN)
NAN_BOXED(14757,16,FLEN)
NAN_BOXED(13822,16,FLEN)
NAN_BOXED(16350,16,FLEN)
NAN_BOXED(14757,16,FLEN)
NAN_BOXED(13822,16,FLEN)
NAN_BOXED(16350,16,FLEN)
NAN_BOXED(14757,16,FLEN)
NAN_BOXED(13822,16,FLEN)
NAN_BOXED(16350,16,FLEN)
NAN_BOXED(14757,16,FLEN)
NAN_BOXED(13822,16,FLEN)
NAN_BOXED(16350,16,FLEN)
NAN_BOXED(14757,16,FLEN)
NAN_BOXED(15106,16,FLEN)
NAN_BOXED(15152,16,FLEN)
NAN_BOXED(14860,16,FLEN)
NAN_BOXED(15106,16,FLEN)
NAN_BOXED(15152,16,FLEN)
NAN_BOXED(14860,16,FLEN)
NAN_BOXED(15106,16,FLEN)
NAN_BOXED(15152,16,FLEN)
NAN_BOXED(14860,16,FLEN)
NAN_BOXED(15106,16,FLEN)
NAN_BOXED(15152,16,FLEN)
NAN_BOXED(14860,16,FLEN)
NAN_BOXED(15106,16,FLEN)
NAN_BOXED(15152,16,FLEN)
NAN_BOXED(14860,16,FLEN)
NAN_BOXED(13859,16,FLEN)
NAN_BOXED(15204,16,FLEN)
NAN_BOXED(13612,16,FLEN)
NAN_BOXED(13859,16,FLEN)
NAN_BOXED(15204,16,FLEN)
NAN_BOXED(13612,16,FLEN)
NAN_BOXED(13859,16,FLEN)
NAN_BOXED(15204,16,FLEN)
NAN_BOXED(13612,16,FLEN)
NAN_BOXED(13859,16,FLEN)
NAN_BOXED(15204,16,FLEN)
NAN_BOXED(13612,16,FLEN)
NAN_BOXED(13859,16,FLEN)
NAN_BOXED(15204,16,FLEN)
NAN_BOXED(13612,16,FLEN)
NAN_BOXED(14696,16,FLEN)
NAN_BOXED(15621,16,FLEN)
NAN_BOXED(15051,16,FLEN)
NAN_BOXED(14696,16,FLEN)
NAN_BOXED(15621,16,FLEN)
NAN_BOXED(15051,16,FLEN)
NAN_BOXED(13717,16,FLEN)
NAN_BOXED(16720,16,FLEN)
NAN_BOXED(15211,16,FLEN)
NAN_BOXED(13717,16,FLEN)
NAN_BOXED(16720,16,FLEN)
NAN_BOXED(15211,16,FLEN)
NAN_BOXED(13717,16,FLEN)
NAN_BOXED(16720,16,FLEN)
NAN_BOXED(15211,16,FLEN)
NAN_BOXED(13717,16,FLEN)
NAN_BOXED(16720,16,FLEN)
NAN_BOXED(15211,16,FLEN)
NAN_BOXED(13717,16,FLEN)
NAN_BOXED(16720,16,FLEN)
NAN_BOXED(15211,16,FLEN)
NAN_BOXED(14189,16,FLEN)
NAN_BOXED(15735,16,FLEN)
NAN_BOXED(14611,16,FLEN)
RVTEST_DATA_END

RVMODEL_DATA_BEGIN
rvtest_sig_begin:
sig_begin_canary:
CANARY;



signature_x1_0:
    .fill 0*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_1:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_2:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_3:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_4:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_5:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_6:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_7:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_8:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_9:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_10:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_11:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_12:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_13:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_14:
    .fill 48*((SIGALIGN)/4),4,0xdeadbeef

#ifdef rvtest_mtrap_routine
tsig_begin_canary:
CANARY;

mtrap_sigptr:
    .fill 64*XLEN/32,4,0xdeadbeef

tsig_end_canary:
CANARY;
#endif

#ifdef rvtest_gpr_save

gpr_save:
    .fill 32*XLEN/32,4,0xdeadbeef

#endif


sig_end_canary:
CANARY;
rvtest_sig_end:
RVMODEL_DATA_END
