
// -----------
// This file was generated by riscv_ctg (https://github.com/riscv-software-src/riscv-ctg)
// version   : 0.12.1
// timestamp : Wed Mar  6 21:53:15 2024 GMT
// usage     : riscv_ctg \
//                  -- cgf //                  --cgf /home/cm/src/riscv-ctg/zfa/sample_cgfs/dataset.cgf \
//                  --cgf /home/cm/src/riscv-ctg/zfa/sample_cgfs/zfa/fleq.s.cgf \
 \
//                  -- xlen 32  \
// -----------
//
// -----------
// Copyright (c) 2020. RISC-V International. All rights reserved.
// SPDX-License-Identifier: BSD-3-Clause
// -----------
//
// This assembly file tests the fleq.s instruction of the RISC-V RV32F_Zicsr_Zfa,RV32FD_Zicsr_Zfa,RV64F_Zicsr_Zfa,RV64FD_Zicsr_Zfa extension for the fleq_b1 covergroup.
// 
#include "model_test.h"
#include "arch_test.h"
RVTEST_ISA("RV32IF_Zicsr_Zfa,RV32IFD_Zicsr_Zfa,RV64IF_Zicsr_Zfa,RV64IFD_Zicsr_Zfa")

.section .text.init
.globl rvtest_entry_point
rvtest_entry_point:
RVMODEL_BOOT
RVTEST_CODE_BEGIN

#ifdef TEST_CASE_1

RVTEST_CASE(0,"//check ISA:=regex(.*I.*F.*Zfa.*);def TEST_CASE_1=True;",fleq_b1)

RVTEST_FP_ENABLE()
RVTEST_VALBASEUPD(x3,test_dataset_0)
RVTEST_SIGBASE(x1,signature_x1_1)

inst_0:// rs1 == rs2, rs1==f31, rs2==f31, rd==x31,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and  fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff  
/* opcode: fleq.s ; op1:f31; op2:f31; dest:x31; op1val:0x0; op2val:0x0;
valaddr_reg:x3; val_offset:0*FLEN/8; correctval:??; testreg:x2;
fcsr_val: 0*/
TEST_FCMP_OP(fleq.s, x31, f31, f31, 0, 0, x3, 0*FLEN/8, x4, x1, x2)

inst_1:// rs1 != rs2, rs1==f30, rs2==f29, rd==x30,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and  fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff  
/* opcode: fleq.s ; op1:f30; op2:f29; dest:x30; op1val:0x0; op2val:0x80000000;
valaddr_reg:x3; val_offset:2*FLEN/8; correctval:??; testreg:x2;
fcsr_val: 0*/
TEST_FCMP_OP(fleq.s, x30, f30, f29, 0, 0, x3, 2*FLEN/8, x4, x1, x2)

inst_2:// rs1==f29, rs2==f30, rd==x29,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000001 and  fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff  
/* opcode: fleq.s ; op1:f29; op2:f30; dest:x29; op1val:0x0; op2val:0x1;
valaddr_reg:x3; val_offset:4*FLEN/8; correctval:??; testreg:x2;
fcsr_val: 0*/
TEST_FCMP_OP(fleq.s, x29, f29, f30, 0, 0, x3, 4*FLEN/8, x4, x1, x2)

inst_3:// rs1==f28, rs2==f27, rd==x28,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000001 and  fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff  
/* opcode: fleq.s ; op1:f28; op2:f27; dest:x28; op1val:0x0; op2val:0x80000001;
valaddr_reg:x3; val_offset:6*FLEN/8; correctval:??; testreg:x2;
fcsr_val: 0*/
TEST_FCMP_OP(fleq.s, x28, f28, f27, 0, 0, x3, 6*FLEN/8, x4, x1, x2)

inst_4:// rs1==f27, rs2==f28, rd==x27,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000002 and  fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff  
/* opcode: fleq.s ; op1:f27; op2:f28; dest:x27; op1val:0x0; op2val:0x2;
valaddr_reg:x3; val_offset:8*FLEN/8; correctval:??; testreg:x2;
fcsr_val: 0*/
TEST_FCMP_OP(fleq.s, x27, f27, f28, 0, 0, x3, 8*FLEN/8, x4, x1, x2)

inst_5:// rs1==f26, rs2==f25, rd==x26,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7ffffe and  fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff  
/* opcode: fleq.s ; op1:f26; op2:f25; dest:x26; op1val:0x0; op2val:0x807ffffe;
valaddr_reg:x3; val_offset:10*FLEN/8; correctval:??; testreg:x2;
fcsr_val: 0*/
TEST_FCMP_OP(fleq.s, x26, f26, f25, 0, 0, x3, 10*FLEN/8, x4, x1, x2)

inst_6:// rs1==f25, rs2==f26, rd==x25,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x7fffff and  fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff  
/* opcode: fleq.s ; op1:f25; op2:f26; dest:x25; op1val:0x0; op2val:0x7fffff;
valaddr_reg:x3; val_offset:12*FLEN/8; correctval:??; testreg:x2;
fcsr_val: 0*/
TEST_FCMP_OP(fleq.s, x25, f25, f26, 0, 0, x3, 12*FLEN/8, x4, x1, x2)

inst_7:// rs1==f24, rs2==f23, rd==x24,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7fffff and  fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff  
/* opcode: fleq.s ; op1:f24; op2:f23; dest:x24; op1val:0x0; op2val:0x807fffff;
valaddr_reg:x3; val_offset:14*FLEN/8; correctval:??; testreg:x2;
fcsr_val: 0*/
TEST_FCMP_OP(fleq.s, x24, f24, f23, 0, 0, x3, 14*FLEN/8, x4, x1, x2)

inst_8:// rs1==f23, rs2==f24, rd==x23,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000000 and  fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff  
/* opcode: fleq.s ; op1:f23; op2:f24; dest:x23; op1val:0x0; op2val:0x800000;
valaddr_reg:x3; val_offset:16*FLEN/8; correctval:??; testreg:x2;
fcsr_val: 0*/
TEST_FCMP_OP(fleq.s, x23, f23, f24, 0, 0, x3, 16*FLEN/8, x4, x1, x2)

inst_9:// rs1==f22, rs2==f21, rd==x22,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000000 and  fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff  
/* opcode: fleq.s ; op1:f22; op2:f21; dest:x22; op1val:0x0; op2val:0x80800000;
valaddr_reg:x3; val_offset:18*FLEN/8; correctval:??; testreg:x2;
fcsr_val: 0*/
TEST_FCMP_OP(fleq.s, x22, f22, f21, 0, 0, x3, 18*FLEN/8, x4, x1, x2)

inst_10:// rs1==f21, rs2==f22, rd==x21,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000001 and  fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff  
/* opcode: fleq.s ; op1:f21; op2:f22; dest:x21; op1val:0x0; op2val:0x800001;
valaddr_reg:x3; val_offset:20*FLEN/8; correctval:??; testreg:x2;
fcsr_val: 0*/
TEST_FCMP_OP(fleq.s, x21, f21, f22, 0, 0, x3, 20*FLEN/8, x4, x1, x2)

inst_11:// rs1==f20, rs2==f19, rd==x20,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055555 and  fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff  
/* opcode: fleq.s ; op1:f20; op2:f19; dest:x20; op1val:0x0; op2val:0x80855555;
valaddr_reg:x3; val_offset:22*FLEN/8; correctval:??; testreg:x2;
fcsr_val: 0*/
TEST_FCMP_OP(fleq.s, x20, f20, f19, 0, 0, x3, 22*FLEN/8, x4, x1, x2)

inst_12:// rs1==f19, rs2==f20, rd==x19,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and  fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff  
/* opcode: fleq.s ; op1:f19; op2:f20; dest:x19; op1val:0x0; op2val:0x7f7fffff;
valaddr_reg:x3; val_offset:24*FLEN/8; correctval:??; testreg:x2;
fcsr_val: 0*/
TEST_FCMP_OP(fleq.s, x19, f19, f20, 0, 0, x3, 24*FLEN/8, x4, x1, x2)

inst_13:// rs1==f18, rs2==f17, rd==x18,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and  fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff  
/* opcode: fleq.s ; op1:f18; op2:f17; dest:x18; op1val:0x0; op2val:0xff7fffff;
valaddr_reg:x3; val_offset:26*FLEN/8; correctval:??; testreg:x2;
fcsr_val: 0*/
TEST_FCMP_OP(fleq.s, x18, f18, f17, 0, 0, x3, 26*FLEN/8, x4, x1, x2)

inst_14:// rs1==f17, rs2==f18, rd==x17,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000000 and  fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff  
/* opcode: fleq.s ; op1:f17; op2:f18; dest:x17; op1val:0x0; op2val:0x7f800000;
valaddr_reg:x3; val_offset:28*FLEN/8; correctval:??; testreg:x2;
fcsr_val: 0*/
TEST_FCMP_OP(fleq.s, x17, f17, f18, 0, 0, x3, 28*FLEN/8, x4, x1, x2)

inst_15:// rs1==f16, rs2==f15, rd==x16,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x000000 and  fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff  
/* opcode: fleq.s ; op1:f16; op2:f15; dest:x16; op1val:0x0; op2val:0xff800000;
valaddr_reg:x3; val_offset:30*FLEN/8; correctval:??; testreg:x2;
fcsr_val: 0*/
TEST_FCMP_OP(fleq.s, x16, f16, f15, 0, 0, x3, 30*FLEN/8, x4, x1, x2)

inst_16:// rs1==f15, rs2==f16, rd==x15,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400000 and  fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff  
/* opcode: fleq.s ; op1:f15; op2:f16; dest:x15; op1val:0x0; op2val:0x7fc00000;
valaddr_reg:x3; val_offset:32*FLEN/8; correctval:??; testreg:x2;
fcsr_val: 0*/
TEST_FCMP_OP(fleq.s, x15, f15, f16, 0, 0, x3, 32*FLEN/8, x4, x1, x2)

inst_17:// rs1==f14, rs2==f13, rd==x14,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x400000 and  fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff  
/* opcode: fleq.s ; op1:f14; op2:f13; dest:x14; op1val:0x0; op2val:0xffc00000;
valaddr_reg:x3; val_offset:34*FLEN/8; correctval:??; testreg:x2;
fcsr_val: 0*/
TEST_FCMP_OP(fleq.s, x14, f14, f13, 0, 0, x3, 34*FLEN/8, x4, x1, x2)

inst_18:// rs1==f13, rs2==f14, rd==x13,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400001 and  fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff  
/* opcode: fleq.s ; op1:f13; op2:f14; dest:x13; op1val:0x0; op2val:0x7fc00001;
valaddr_reg:x3; val_offset:36*FLEN/8; correctval:??; testreg:x2;
fcsr_val: 0*/
TEST_FCMP_OP(fleq.s, x13, f13, f14, 0, 0, x3, 36*FLEN/8, x4, x1, x2)

inst_19:// rs1==f12, rs2==f11, rd==x12,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x455555 and  fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff  
/* opcode: fleq.s ; op1:f12; op2:f11; dest:x12; op1val:0x0; op2val:0xffc55555;
valaddr_reg:x3; val_offset:38*FLEN/8; correctval:??; testreg:x2;
fcsr_val: 0*/
TEST_FCMP_OP(fleq.s, x12, f12, f11, 0, 0, x3, 38*FLEN/8, x4, x1, x2)

inst_20:// rs1==f11, rs2==f12, rd==x11,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000001 and  fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff  
/* opcode: fleq.s ; op1:f11; op2:f12; dest:x11; op1val:0x0; op2val:0x7f800001;
valaddr_reg:x3; val_offset:40*FLEN/8; correctval:??; testreg:x2;
fcsr_val: 0*/
TEST_FCMP_OP(fleq.s, x11, f11, f12, 0, 0, x3, 40*FLEN/8, x4, x1, x2)

inst_21:// rs1==f10, rs2==f9, rd==x10,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x2aaaaa and  fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff  
/* opcode: fleq.s ; op1:f10; op2:f9; dest:x10; op1val:0x0; op2val:0xffaaaaaa;
valaddr_reg:x3; val_offset:42*FLEN/8; correctval:??; testreg:x2;
fcsr_val: 0*/
TEST_FCMP_OP(fleq.s, x10, f10, f9, 0, 0, x3, 42*FLEN/8, x4, x1, x2)

inst_22:// rs1==f9, rs2==f10, rd==x9,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x000000 and  fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff  
/* opcode: fleq.s ; op1:f9; op2:f10; dest:x9; op1val:0x0; op2val:0x3f800000;
valaddr_reg:x3; val_offset:44*FLEN/8; correctval:??; testreg:x2;
fcsr_val: 0*/
TEST_FCMP_OP(fleq.s, x9, f9, f10, 0, 0, x3, 44*FLEN/8, x4, x1, x2)
RVTEST_VALBASEUPD(x9,test_dataset_1)

inst_23:// rs1==f8, rs2==f7, rd==x8,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x7f and fm2 == 0x000000 and  fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff  
/* opcode: fleq.s ; op1:f8; op2:f7; dest:x8; op1val:0x0; op2val:0xbf800000;
valaddr_reg:x9; val_offset:0*FLEN/8; correctval:??; testreg:x2;
fcsr_val: 0*/
TEST_FCMP_OP(fleq.s, x8, f8, f7, 0, 0, x9, 0*FLEN/8, x10, x1, x2)

inst_24:// rs1==f7, rs2==f8, rd==x7,fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and  fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff  
/* opcode: fleq.s ; op1:f7; op2:f8; dest:x7; op1val:0x80000000; op2val:0x0;
valaddr_reg:x9; val_offset:2*FLEN/8; correctval:??; testreg:x2;
fcsr_val: 0*/
TEST_FCMP_OP(fleq.s, x7, f7, f8, 0, 0, x9, 2*FLEN/8, x10, x1, x2)

inst_25:// rs1==f6, rs2==f5, rd==x6,fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and  fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff  
/* opcode: fleq.s ; op1:f6; op2:f5; dest:x6; op1val:0x80000000; op2val:0x80000000;
valaddr_reg:x9; val_offset:4*FLEN/8; correctval:??; testreg:x7;
fcsr_val: 0*/
TEST_FCMP_OP(fleq.s, x6, f6, f5, 0, 0, x9, 4*FLEN/8, x10, x1, x7)
RVTEST_SIGBASE(x6,signature_x6_0)

inst_26:// rs1==f5, rs2==f6, rd==x5,fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000001 and  fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff  
/* opcode: fleq.s ; op1:f5; op2:f6; dest:x5; op1val:0x80000000; op2val:0x1;
valaddr_reg:x9; val_offset:6*FLEN/8; correctval:??; testreg:x7;
fcsr_val: 0*/
TEST_FCMP_OP(fleq.s, x5, f5, f6, 0, 0, x9, 6*FLEN/8, x10, x6, x7)

inst_27:// rs1==f4, rs2==f3, rd==x4,fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000001 and  fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff  
/* opcode: fleq.s ; op1:f4; op2:f3; dest:x4; op1val:0x80000000; op2val:0x80000001;
valaddr_reg:x9; val_offset:8*FLEN/8; correctval:??; testreg:x7;
fcsr_val: 0*/
TEST_FCMP_OP(fleq.s, x4, f4, f3, 0, 0, x9, 8*FLEN/8, x10, x6, x7)

inst_28:// rs1==f3, rs2==f4, rd==x3,fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000002 and  fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff  
/* opcode: fleq.s ; op1:f3; op2:f4; dest:x3; op1val:0x80000000; op2val:0x2;
valaddr_reg:x9; val_offset:10*FLEN/8; correctval:??; testreg:x7;
fcsr_val: 0*/
TEST_FCMP_OP(fleq.s, x3, f3, f4, 0, 0, x9, 10*FLEN/8, x10, x6, x7)

inst_29:// rs1==f2, rs2==f1, rd==x2,fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7ffffe and  fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff  
/* opcode: fleq.s ; op1:f2; op2:f1; dest:x2; op1val:0x80000000; op2val:0x807ffffe;
valaddr_reg:x9; val_offset:12*FLEN/8; correctval:??; testreg:x7;
fcsr_val: 0*/
TEST_FCMP_OP(fleq.s, x2, f2, f1, 0, 0, x9, 12*FLEN/8, x10, x6, x7)

inst_30:// rs1==f1, rs2==f2, rd==x1,fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x7fffff and  fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff  
/* opcode: fleq.s ; op1:f1; op2:f2; dest:x1; op1val:0x80000000; op2val:0x7fffff;
valaddr_reg:x9; val_offset:14*FLEN/8; correctval:??; testreg:x7;
fcsr_val: 0*/
TEST_FCMP_OP(fleq.s, x1, f1, f2, 0, 0, x9, 14*FLEN/8, x10, x6, x7)

inst_31:// rs1==f0,fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7fffff and  fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff  
/* opcode: fleq.s ; op1:f0; op2:f31; dest:x31; op1val:0x80000000; op2val:0x807fffff;
valaddr_reg:x9; val_offset:16*FLEN/8; correctval:??; testreg:x7;
fcsr_val: 0*/
TEST_FCMP_OP(fleq.s, x31, f0, f31, 0, 0, x9, 16*FLEN/8, x10, x6, x7)

inst_32:// rs2==f0,fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000000 and  fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff  
/* opcode: fleq.s ; op1:f31; op2:f0; dest:x31; op1val:0x80000000; op2val:0x800000;
valaddr_reg:x9; val_offset:18*FLEN/8; correctval:??; testreg:x7;
fcsr_val: 0*/
TEST_FCMP_OP(fleq.s, x31, f31, f0, 0, 0, x9, 18*FLEN/8, x10, x6, x7)

inst_33:// rd==x0,fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000000 and  fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff  
/* opcode: fleq.s ; op1:f31; op2:f30; dest:x0; op1val:0x80000000; op2val:0x80800000;
valaddr_reg:x9; val_offset:20*FLEN/8; correctval:??; testreg:x7;
fcsr_val: 0*/
TEST_FCMP_OP(fleq.s, x0, f31, f30, 0, 0, x9, 20*FLEN/8, x10, x6, x7)
#endif


RVTEST_CODE_END
RVMODEL_HALT

RVTEST_DATA_BEGIN
.align 4
rvtest_data:
.word 0xbabecafe
.word 0xabecafeb
.word 0xbecafeba
.word 0xecafebab
test_dataset_0:
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x80000000147483648,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x1,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x80000001147483649,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x2,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x807ffffe155872254,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x7fffff388607,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x807fffff155872255,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x800000388608,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x80800000155872256,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x800001388609,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x80855555156221781,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x7f7fffff139095039,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xff7fffff286578687,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x7f800000139095040,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xff800000286578688,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x7fc00000143289344,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xffc00000290772992,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x7fc00001143289345,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xffc55555291122517,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x7f800001139095041,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xffaaaaaa289374890,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x3f800000065353216,32,FLEN)
test_dataset_1:
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xbf800000212836864,32,FLEN)
NAN_BOXED(0x80000000147483648,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x80000000147483648,32,FLEN)
NAN_BOXED(0x80000000147483648,32,FLEN)
NAN_BOXED(0x80000000147483648,32,FLEN)
NAN_BOXED(0x1,32,FLEN)
NAN_BOXED(0x80000000147483648,32,FLEN)
NAN_BOXED(0x80000001147483649,32,FLEN)
NAN_BOXED(0x80000000147483648,32,FLEN)
NAN_BOXED(0x2,32,FLEN)
NAN_BOXED(0x80000000147483648,32,FLEN)
NAN_BOXED(0x807ffffe155872254,32,FLEN)
NAN_BOXED(0x80000000147483648,32,FLEN)
NAN_BOXED(0x7fffff388607,32,FLEN)
NAN_BOXED(0x80000000147483648,32,FLEN)
NAN_BOXED(0x807fffff155872255,32,FLEN)
NAN_BOXED(0x80000000147483648,32,FLEN)
NAN_BOXED(0x800000388608,32,FLEN)
NAN_BOXED(0x80000000147483648,32,FLEN)
NAN_BOXED(0x80800000155872256,32,FLEN)
RVTEST_DATA_END

RVMODEL_DATA_BEGIN
rvtest_sig_begin:
sig_begin_canary:
CANARY;



signature_x1_0:
    .fill 0*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_1:
    .fill 52*((SIGALIGN)/4),4,0xdeadbeef


signature_x6_0:
    .fill 16*((SIGALIGN)/4),4,0xdeadbeef

#ifdef rvtest_mtrap_routine
tsig_begin_canary:
CANARY;

mtrap_sigptr:
    .fill 64*XLEN/32,4,0xdeadbeef

tsig_end_canary:
CANARY;
#endif

#ifdef rvtest_gpr_save

gpr_save:
    .fill 32*XLEN/32,4,0xdeadbeef

#endif


sig_end_canary:
CANARY;
rvtest_sig_end:
RVMODEL_DATA_END
