
// -----------
// This file was generated by riscv_ctg (https://github.com/riscv-software-src/riscv-ctg)
// version   : 0.7.1
// timestamp : Fri Jun 17 14:18:07 2022 GMT
// usage     : riscv_ctg \
//                  -- cgf //                  --cgf /scratch/pawan/work/normalised/RV32F/fmsub.s.cgf \
 \
//                  -- xlen 32  \
//                  --randomize \
// -----------
//
// -----------
// Copyright (c) 2020. RISC-V International. All rights reserved.
// SPDX-License-Identifier: BSD-3-Clause
// -----------
//
// This assembly file tests the fmsub.s instruction of the RISC-V RV32F_Zicsr,RV32FD_Zicsr,RV64F_Zicsr,RV64FD_Zicsr extension for the fmsub_b15 covergroup.
// 
#include "model_test.h"
#include "arch_test.h"
RVTEST_ISA("RV32IF_Zicsr,RV32IFD_Zicsr,RV64IF_Zicsr,RV64IFD_Zicsr,RV32EF_Zicsr,RV32EFD_Zicsr,RV64EF_Zicsr,RV64EFD_Zicsr")

.section .text.init
.globl rvtest_entry_point
rvtest_entry_point:
RVMODEL_BOOT
RVTEST_CODE_BEGIN

#ifdef TEST_CASE_1

RVTEST_CASE(0,"//check ISA:=regex(.*I.*F.*);def TEST_CASE_1=True;",fmsub_b15)
RVTEST_CASE(1,"//check ISA:=regex(.*E.*F.*);def TEST_CASE_1=True;",fmsub_b15)
RVTEST_FP_ENABLE()
RVTEST_VALBASEUPD(x3,test_dataset_0)
RVTEST_SIGBASE(x1,signature_x1_1)

inst_9984:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x4c2a81 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x207f2f and fs3 == 0 and fe3 == 0x52 and fm3 == 0x007fff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e4c2a81; op2val:0xa07f2f;
op3val:0x29007fff; valaddr_reg:x3; val_offset:29952*0 + 3*-1*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 29952*0 + 3*0*FLEN/8, x4, x1, x2)

inst_9985:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x4c2a81 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x207f2f and fs3 == 0 and fe3 == 0x52 and fm3 == 0x00ffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e4c2a81; op2val:0xa07f2f;
op3val:0x2900ffff; valaddr_reg:x3; val_offset:29955*0 + 3*0*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 29955*0 + 3*1*FLEN/8, x4, x1, x2)

inst_9986:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x4c2a81 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x207f2f and fs3 == 0 and fe3 == 0x52 and fm3 == 0x01ffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e4c2a81; op2val:0xa07f2f;
op3val:0x2901ffff; valaddr_reg:x3; val_offset:29958*0 + 3*1*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 29958*0 + 3*2*FLEN/8, x4, x1, x2)

inst_9987:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x4c2a81 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x207f2f and fs3 == 0 and fe3 == 0x52 and fm3 == 0x03ffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e4c2a81; op2val:0xa07f2f;
op3val:0x2903ffff; valaddr_reg:x3; val_offset:29961*0 + 3*2*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 29961*0 + 3*3*FLEN/8, x4, x1, x2)

inst_9988:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x4c2a81 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x207f2f and fs3 == 0 and fe3 == 0x52 and fm3 == 0x07ffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e4c2a81; op2val:0xa07f2f;
op3val:0x2907ffff; valaddr_reg:x3; val_offset:29964*0 + 3*3*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 29964*0 + 3*4*FLEN/8, x4, x1, x2)

inst_9989:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x4c2a81 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x207f2f and fs3 == 0 and fe3 == 0x52 and fm3 == 0x0fffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e4c2a81; op2val:0xa07f2f;
op3val:0x290fffff; valaddr_reg:x3; val_offset:29967*0 + 3*4*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 29967*0 + 3*5*FLEN/8, x4, x1, x2)

inst_9990:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x4c2a81 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x207f2f and fs3 == 0 and fe3 == 0x52 and fm3 == 0x1fffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e4c2a81; op2val:0xa07f2f;
op3val:0x291fffff; valaddr_reg:x3; val_offset:29970*0 + 3*5*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 29970*0 + 3*6*FLEN/8, x4, x1, x2)

inst_9991:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x4c2a81 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x207f2f and fs3 == 0 and fe3 == 0x52 and fm3 == 0x3fffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e4c2a81; op2val:0xa07f2f;
op3val:0x293fffff; valaddr_reg:x3; val_offset:29973*0 + 3*6*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 29973*0 + 3*7*FLEN/8, x4, x1, x2)

inst_9992:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x4c2a81 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x207f2f and fs3 == 0 and fe3 == 0x52 and fm3 == 0x400000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e4c2a81; op2val:0xa07f2f;
op3val:0x29400000; valaddr_reg:x3; val_offset:29976*0 + 3*7*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 29976*0 + 3*8*FLEN/8, x4, x1, x2)

inst_9993:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x4c2a81 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x207f2f and fs3 == 0 and fe3 == 0x52 and fm3 == 0x600000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e4c2a81; op2val:0xa07f2f;
op3val:0x29600000; valaddr_reg:x3; val_offset:29979*0 + 3*8*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 29979*0 + 3*9*FLEN/8, x4, x1, x2)

inst_9994:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x4c2a81 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x207f2f and fs3 == 0 and fe3 == 0x52 and fm3 == 0x700000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e4c2a81; op2val:0xa07f2f;
op3val:0x29700000; valaddr_reg:x3; val_offset:29982*0 + 3*9*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 29982*0 + 3*10*FLEN/8, x4, x1, x2)

inst_9995:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x4c2a81 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x207f2f and fs3 == 0 and fe3 == 0x52 and fm3 == 0x780000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e4c2a81; op2val:0xa07f2f;
op3val:0x29780000; valaddr_reg:x3; val_offset:29985*0 + 3*10*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 29985*0 + 3*11*FLEN/8, x4, x1, x2)

inst_9996:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x4c2a81 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x207f2f and fs3 == 0 and fe3 == 0x52 and fm3 == 0x7c0000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e4c2a81; op2val:0xa07f2f;
op3val:0x297c0000; valaddr_reg:x3; val_offset:29988*0 + 3*11*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 29988*0 + 3*12*FLEN/8, x4, x1, x2)

inst_9997:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x4c2a81 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x207f2f and fs3 == 0 and fe3 == 0x52 and fm3 == 0x7e0000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e4c2a81; op2val:0xa07f2f;
op3val:0x297e0000; valaddr_reg:x3; val_offset:29991*0 + 3*12*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 29991*0 + 3*13*FLEN/8, x4, x1, x2)

inst_9998:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x4c2a81 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x207f2f and fs3 == 0 and fe3 == 0x52 and fm3 == 0x7f0000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e4c2a81; op2val:0xa07f2f;
op3val:0x297f0000; valaddr_reg:x3; val_offset:29994*0 + 3*13*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 29994*0 + 3*14*FLEN/8, x4, x1, x2)

inst_9999:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x4c2a81 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x207f2f and fs3 == 0 and fe3 == 0x52 and fm3 == 0x7f8000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e4c2a81; op2val:0xa07f2f;
op3val:0x297f8000; valaddr_reg:x3; val_offset:29997*0 + 3*14*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 29997*0 + 3*15*FLEN/8, x4, x1, x2)

inst_10000:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x4c2a81 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x207f2f and fs3 == 0 and fe3 == 0x52 and fm3 == 0x7fc000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e4c2a81; op2val:0xa07f2f;
op3val:0x297fc000; valaddr_reg:x3; val_offset:30000*0 + 3*15*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 30000*0 + 3*16*FLEN/8, x4, x1, x2)

inst_10001:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x4c2a81 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x207f2f and fs3 == 0 and fe3 == 0x52 and fm3 == 0x7fe000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e4c2a81; op2val:0xa07f2f;
op3val:0x297fe000; valaddr_reg:x3; val_offset:30003*0 + 3*16*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 30003*0 + 3*17*FLEN/8, x4, x1, x2)

inst_10002:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x4c2a81 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x207f2f and fs3 == 0 and fe3 == 0x52 and fm3 == 0x7ff000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e4c2a81; op2val:0xa07f2f;
op3val:0x297ff000; valaddr_reg:x3; val_offset:30006*0 + 3*17*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 30006*0 + 3*18*FLEN/8, x4, x1, x2)

inst_10003:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x4c2a81 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x207f2f and fs3 == 0 and fe3 == 0x52 and fm3 == 0x7ff800 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e4c2a81; op2val:0xa07f2f;
op3val:0x297ff800; valaddr_reg:x3; val_offset:30009*0 + 3*18*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 30009*0 + 3*19*FLEN/8, x4, x1, x2)

inst_10004:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x4c2a81 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x207f2f and fs3 == 0 and fe3 == 0x52 and fm3 == 0x7ffc00 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e4c2a81; op2val:0xa07f2f;
op3val:0x297ffc00; valaddr_reg:x3; val_offset:30012*0 + 3*19*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 30012*0 + 3*20*FLEN/8, x4, x1, x2)

inst_10005:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x4c2a81 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x207f2f and fs3 == 0 and fe3 == 0x52 and fm3 == 0x7ffe00 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e4c2a81; op2val:0xa07f2f;
op3val:0x297ffe00; valaddr_reg:x3; val_offset:30015*0 + 3*20*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 30015*0 + 3*21*FLEN/8, x4, x1, x2)

inst_10006:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x4c2a81 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x207f2f and fs3 == 0 and fe3 == 0x52 and fm3 == 0x7fff00 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e4c2a81; op2val:0xa07f2f;
op3val:0x297fff00; valaddr_reg:x3; val_offset:30018*0 + 3*21*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 30018*0 + 3*22*FLEN/8, x4, x1, x2)

inst_10007:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x4c2a81 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x207f2f and fs3 == 0 and fe3 == 0x52 and fm3 == 0x7fff80 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e4c2a81; op2val:0xa07f2f;
op3val:0x297fff80; valaddr_reg:x3; val_offset:30021*0 + 3*22*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 30021*0 + 3*23*FLEN/8, x4, x1, x2)

inst_10008:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x4c2a81 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x207f2f and fs3 == 0 and fe3 == 0x52 and fm3 == 0x7fffc0 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e4c2a81; op2val:0xa07f2f;
op3val:0x297fffc0; valaddr_reg:x3; val_offset:30024*0 + 3*23*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 30024*0 + 3*24*FLEN/8, x4, x1, x2)

inst_10009:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x4c2a81 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x207f2f and fs3 == 0 and fe3 == 0x52 and fm3 == 0x7fffe0 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e4c2a81; op2val:0xa07f2f;
op3val:0x297fffe0; valaddr_reg:x3; val_offset:30027*0 + 3*24*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 30027*0 + 3*25*FLEN/8, x4, x1, x2)

inst_10010:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x4c2a81 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x207f2f and fs3 == 0 and fe3 == 0x52 and fm3 == 0x7ffff0 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e4c2a81; op2val:0xa07f2f;
op3val:0x297ffff0; valaddr_reg:x3; val_offset:30030*0 + 3*25*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 30030*0 + 3*26*FLEN/8, x4, x1, x2)

inst_10011:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x4c2a81 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x207f2f and fs3 == 0 and fe3 == 0x52 and fm3 == 0x7ffff8 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e4c2a81; op2val:0xa07f2f;
op3val:0x297ffff8; valaddr_reg:x3; val_offset:30033*0 + 3*26*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 30033*0 + 3*27*FLEN/8, x4, x1, x2)

inst_10012:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x4c2a81 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x207f2f and fs3 == 0 and fe3 == 0x52 and fm3 == 0x7ffffc and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e4c2a81; op2val:0xa07f2f;
op3val:0x297ffffc; valaddr_reg:x3; val_offset:30036*0 + 3*27*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 30036*0 + 3*28*FLEN/8, x4, x1, x2)

inst_10013:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x4c2a81 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x207f2f and fs3 == 0 and fe3 == 0x52 and fm3 == 0x7ffffe and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e4c2a81; op2val:0xa07f2f;
op3val:0x297ffffe; valaddr_reg:x3; val_offset:30039*0 + 3*28*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 30039*0 + 3*29*FLEN/8, x4, x1, x2)

inst_10014:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x4c2a81 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x207f2f and fs3 == 0 and fe3 == 0x52 and fm3 == 0x7fffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e4c2a81; op2val:0xa07f2f;
op3val:0x297fffff; valaddr_reg:x3; val_offset:30042*0 + 3*29*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 30042*0 + 3*30*FLEN/8, x4, x1, x2)

inst_10015:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x4c2a81 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x207f2f and fs3 == 0 and fe3 == 0x7f and fm3 == 0x000001 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e4c2a81; op2val:0xa07f2f;
op3val:0x3f800001; valaddr_reg:x3; val_offset:30045*0 + 3*30*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 30045*0 + 3*31*FLEN/8, x4, x1, x2)

inst_10016:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x4c2a81 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x207f2f and fs3 == 0 and fe3 == 0x7f and fm3 == 0x000003 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e4c2a81; op2val:0xa07f2f;
op3val:0x3f800003; valaddr_reg:x3; val_offset:30048*0 + 3*31*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 30048*0 + 3*32*FLEN/8, x4, x1, x2)

inst_10017:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x4c2a81 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x207f2f and fs3 == 0 and fe3 == 0x7f and fm3 == 0x000007 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e4c2a81; op2val:0xa07f2f;
op3val:0x3f800007; valaddr_reg:x3; val_offset:30051*0 + 3*32*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 30051*0 + 3*33*FLEN/8, x4, x1, x2)

inst_10018:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x4c2a81 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x207f2f and fs3 == 0 and fe3 == 0x7f and fm3 == 0x199999 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e4c2a81; op2val:0xa07f2f;
op3val:0x3f999999; valaddr_reg:x3; val_offset:30054*0 + 3*33*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 30054*0 + 3*34*FLEN/8, x4, x1, x2)

inst_10019:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x4c2a81 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x207f2f and fs3 == 0 and fe3 == 0x7f and fm3 == 0x249249 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e4c2a81; op2val:0xa07f2f;
op3val:0x3fa49249; valaddr_reg:x3; val_offset:30057*0 + 3*34*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 30057*0 + 3*35*FLEN/8, x4, x1, x2)

inst_10020:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x4c2a81 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x207f2f and fs3 == 0 and fe3 == 0x7f and fm3 == 0x333333 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e4c2a81; op2val:0xa07f2f;
op3val:0x3fb33333; valaddr_reg:x3; val_offset:30060*0 + 3*35*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 30060*0 + 3*36*FLEN/8, x4, x1, x2)

inst_10021:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x4c2a81 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x207f2f and fs3 == 0 and fe3 == 0x7f and fm3 == 0x36db6d and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e4c2a81; op2val:0xa07f2f;
op3val:0x3fb6db6d; valaddr_reg:x3; val_offset:30063*0 + 3*36*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 30063*0 + 3*37*FLEN/8, x4, x1, x2)

inst_10022:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x4c2a81 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x207f2f and fs3 == 0 and fe3 == 0x7f and fm3 == 0x3bbbbb and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e4c2a81; op2val:0xa07f2f;
op3val:0x3fbbbbbb; valaddr_reg:x3; val_offset:30066*0 + 3*37*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 30066*0 + 3*38*FLEN/8, x4, x1, x2)

inst_10023:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x4c2a81 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x207f2f and fs3 == 0 and fe3 == 0x7f and fm3 == 0x444444 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e4c2a81; op2val:0xa07f2f;
op3val:0x3fc44444; valaddr_reg:x3; val_offset:30069*0 + 3*38*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 30069*0 + 3*39*FLEN/8, x4, x1, x2)

inst_10024:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x4c2a81 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x207f2f and fs3 == 0 and fe3 == 0x7f and fm3 == 0x4ccccc and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e4c2a81; op2val:0xa07f2f;
op3val:0x3fcccccc; valaddr_reg:x3; val_offset:30072*0 + 3*39*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 30072*0 + 3*40*FLEN/8, x4, x1, x2)

inst_10025:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x4c2a81 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x207f2f and fs3 == 0 and fe3 == 0x7f and fm3 == 0x5b6db6 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e4c2a81; op2val:0xa07f2f;
op3val:0x3fdb6db6; valaddr_reg:x3; val_offset:30075*0 + 3*40*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 30075*0 + 3*41*FLEN/8, x4, x1, x2)

inst_10026:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x4c2a81 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x207f2f and fs3 == 0 and fe3 == 0x7f and fm3 == 0x666666 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e4c2a81; op2val:0xa07f2f;
op3val:0x3fe66666; valaddr_reg:x3; val_offset:30078*0 + 3*41*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 30078*0 + 3*42*FLEN/8, x4, x1, x2)

inst_10027:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x4c2a81 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x207f2f and fs3 == 0 and fe3 == 0x7f and fm3 == 0x6db6db and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e4c2a81; op2val:0xa07f2f;
op3val:0x3fedb6db; valaddr_reg:x3; val_offset:30081*0 + 3*42*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 30081*0 + 3*43*FLEN/8, x4, x1, x2)

inst_10028:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x4c2a81 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x207f2f and fs3 == 0 and fe3 == 0x7f and fm3 == 0x7ffff8 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e4c2a81; op2val:0xa07f2f;
op3val:0x3ffffff8; valaddr_reg:x3; val_offset:30084*0 + 3*43*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 30084*0 + 3*44*FLEN/8, x4, x1, x2)

inst_10029:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x4c2a81 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x207f2f and fs3 == 0 and fe3 == 0x7f and fm3 == 0x7ffffc and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e4c2a81; op2val:0xa07f2f;
op3val:0x3ffffffc; valaddr_reg:x3; val_offset:30087*0 + 3*44*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 30087*0 + 3*45*FLEN/8, x4, x1, x2)

inst_10030:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x4c2a81 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x207f2f and fs3 == 0 and fe3 == 0x7f and fm3 == 0x7ffffe and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e4c2a81; op2val:0xa07f2f;
op3val:0x3ffffffe; valaddr_reg:x3; val_offset:30090*0 + 3*45*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 30090*0 + 3*46*FLEN/8, x4, x1, x2)

inst_10031:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x4e0246 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000001 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e4e0246; op2val:0x0;
op3val:0x1; valaddr_reg:x3; val_offset:30093*0 + 3*46*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 30093*0 + 3*47*FLEN/8, x4, x1, x2)

inst_10032:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x4e0246 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000003 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e4e0246; op2val:0x0;
op3val:0x3; valaddr_reg:x3; val_offset:30096*0 + 3*47*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 30096*0 + 3*48*FLEN/8, x4, x1, x2)

inst_10033:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x4e0246 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000007 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e4e0246; op2val:0x0;
op3val:0x7; valaddr_reg:x3; val_offset:30099*0 + 3*48*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 30099*0 + 3*49*FLEN/8, x4, x1, x2)

inst_10034:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x4e0246 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x199999 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e4e0246; op2val:0x0;
op3val:0x199999; valaddr_reg:x3; val_offset:30102*0 + 3*49*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 30102*0 + 3*50*FLEN/8, x4, x1, x2)

inst_10035:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x4e0246 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x249249 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e4e0246; op2val:0x0;
op3val:0x249249; valaddr_reg:x3; val_offset:30105*0 + 3*50*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 30105*0 + 3*51*FLEN/8, x4, x1, x2)

inst_10036:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x4e0246 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x333333 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e4e0246; op2val:0x0;
op3val:0x333333; valaddr_reg:x3; val_offset:30108*0 + 3*51*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 30108*0 + 3*52*FLEN/8, x4, x1, x2)

inst_10037:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x4e0246 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x36db6d and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e4e0246; op2val:0x0;
op3val:0x36db6d; valaddr_reg:x3; val_offset:30111*0 + 3*52*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 30111*0 + 3*53*FLEN/8, x4, x1, x2)

inst_10038:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x4e0246 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x3bbbbb and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e4e0246; op2val:0x0;
op3val:0x3bbbbb; valaddr_reg:x3; val_offset:30114*0 + 3*53*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 30114*0 + 3*54*FLEN/8, x4, x1, x2)

inst_10039:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x4e0246 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x444444 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e4e0246; op2val:0x0;
op3val:0x444444; valaddr_reg:x3; val_offset:30117*0 + 3*54*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 30117*0 + 3*55*FLEN/8, x4, x1, x2)

inst_10040:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x4e0246 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x4ccccc and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e4e0246; op2val:0x0;
op3val:0x4ccccc; valaddr_reg:x3; val_offset:30120*0 + 3*55*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 30120*0 + 3*56*FLEN/8, x4, x1, x2)

inst_10041:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x4e0246 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x5b6db6 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e4e0246; op2val:0x0;
op3val:0x5b6db6; valaddr_reg:x3; val_offset:30123*0 + 3*56*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 30123*0 + 3*57*FLEN/8, x4, x1, x2)

inst_10042:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x4e0246 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x666666 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e4e0246; op2val:0x0;
op3val:0x666666; valaddr_reg:x3; val_offset:30126*0 + 3*57*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 30126*0 + 3*58*FLEN/8, x4, x1, x2)

inst_10043:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x4e0246 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x6db6db and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e4e0246; op2val:0x0;
op3val:0x6db6db; valaddr_reg:x3; val_offset:30129*0 + 3*58*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 30129*0 + 3*59*FLEN/8, x4, x1, x2)

inst_10044:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x4e0246 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x7ffff8 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e4e0246; op2val:0x0;
op3val:0x7ffff8; valaddr_reg:x3; val_offset:30132*0 + 3*59*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 30132*0 + 3*60*FLEN/8, x4, x1, x2)

inst_10045:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x4e0246 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x7ffffc and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e4e0246; op2val:0x0;
op3val:0x7ffffc; valaddr_reg:x3; val_offset:30135*0 + 3*60*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 30135*0 + 3*61*FLEN/8, x4, x1, x2)

inst_10046:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x4e0246 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x7ffffe and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e4e0246; op2val:0x0;
op3val:0x7ffffe; valaddr_reg:x3; val_offset:30138*0 + 3*61*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 30138*0 + 3*62*FLEN/8, x4, x1, x2)

inst_10047:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x4e0246 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x10 and fm3 == 0x000000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e4e0246; op2val:0x0;
op3val:0x8000000; valaddr_reg:x3; val_offset:30141*0 + 3*62*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 30141*0 + 3*63*FLEN/8, x4, x1, x2)

inst_10048:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x4e0246 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x10 and fm3 == 0x000001 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e4e0246; op2val:0x0;
op3val:0x8000001; valaddr_reg:x3; val_offset:30144*0 + 3*63*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 30144*0 + 3*64*FLEN/8, x4, x1, x2)

inst_10049:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x4e0246 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x10 and fm3 == 0x000003 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e4e0246; op2val:0x0;
op3val:0x8000003; valaddr_reg:x3; val_offset:30147*0 + 3*64*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 30147*0 + 3*65*FLEN/8, x4, x1, x2)

inst_10050:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x4e0246 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x10 and fm3 == 0x000007 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e4e0246; op2val:0x0;
op3val:0x8000007; valaddr_reg:x3; val_offset:30150*0 + 3*65*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 30150*0 + 3*66*FLEN/8, x4, x1, x2)

inst_10051:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x4e0246 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x10 and fm3 == 0x00000f and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e4e0246; op2val:0x0;
op3val:0x800000f; valaddr_reg:x3; val_offset:30153*0 + 3*66*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 30153*0 + 3*67*FLEN/8, x4, x1, x2)

inst_10052:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x4e0246 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x10 and fm3 == 0x00001f and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e4e0246; op2val:0x0;
op3val:0x800001f; valaddr_reg:x3; val_offset:30156*0 + 3*67*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 30156*0 + 3*68*FLEN/8, x4, x1, x2)

inst_10053:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x4e0246 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x10 and fm3 == 0x00003f and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e4e0246; op2val:0x0;
op3val:0x800003f; valaddr_reg:x3; val_offset:30159*0 + 3*68*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 30159*0 + 3*69*FLEN/8, x4, x1, x2)

inst_10054:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x4e0246 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x10 and fm3 == 0x00007f and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e4e0246; op2val:0x0;
op3val:0x800007f; valaddr_reg:x3; val_offset:30162*0 + 3*69*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 30162*0 + 3*70*FLEN/8, x4, x1, x2)

inst_10055:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x4e0246 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x10 and fm3 == 0x0000ff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e4e0246; op2val:0x0;
op3val:0x80000ff; valaddr_reg:x3; val_offset:30165*0 + 3*70*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 30165*0 + 3*71*FLEN/8, x4, x1, x2)

inst_10056:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x4e0246 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x10 and fm3 == 0x0001ff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e4e0246; op2val:0x0;
op3val:0x80001ff; valaddr_reg:x3; val_offset:30168*0 + 3*71*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 30168*0 + 3*72*FLEN/8, x4, x1, x2)

inst_10057:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x4e0246 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x10 and fm3 == 0x0003ff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e4e0246; op2val:0x0;
op3val:0x80003ff; valaddr_reg:x3; val_offset:30171*0 + 3*72*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 30171*0 + 3*73*FLEN/8, x4, x1, x2)

inst_10058:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x4e0246 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x10 and fm3 == 0x0007ff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e4e0246; op2val:0x0;
op3val:0x80007ff; valaddr_reg:x3; val_offset:30174*0 + 3*73*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 30174*0 + 3*74*FLEN/8, x4, x1, x2)

inst_10059:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x4e0246 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x10 and fm3 == 0x000fff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e4e0246; op2val:0x0;
op3val:0x8000fff; valaddr_reg:x3; val_offset:30177*0 + 3*74*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 30177*0 + 3*75*FLEN/8, x4, x1, x2)

inst_10060:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x4e0246 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x10 and fm3 == 0x001fff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e4e0246; op2val:0x0;
op3val:0x8001fff; valaddr_reg:x3; val_offset:30180*0 + 3*75*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 30180*0 + 3*76*FLEN/8, x4, x1, x2)

inst_10061:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x4e0246 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x10 and fm3 == 0x003fff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e4e0246; op2val:0x0;
op3val:0x8003fff; valaddr_reg:x3; val_offset:30183*0 + 3*76*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 30183*0 + 3*77*FLEN/8, x4, x1, x2)

inst_10062:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x4e0246 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x10 and fm3 == 0x007fff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e4e0246; op2val:0x0;
op3val:0x8007fff; valaddr_reg:x3; val_offset:30186*0 + 3*77*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 30186*0 + 3*78*FLEN/8, x4, x1, x2)

inst_10063:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x4e0246 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x10 and fm3 == 0x00ffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e4e0246; op2val:0x0;
op3val:0x800ffff; valaddr_reg:x3; val_offset:30189*0 + 3*78*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 30189*0 + 3*79*FLEN/8, x4, x1, x2)

inst_10064:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x4e0246 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x10 and fm3 == 0x01ffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e4e0246; op2val:0x0;
op3val:0x801ffff; valaddr_reg:x3; val_offset:30192*0 + 3*79*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 30192*0 + 3*80*FLEN/8, x4, x1, x2)

inst_10065:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x4e0246 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x10 and fm3 == 0x03ffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e4e0246; op2val:0x0;
op3val:0x803ffff; valaddr_reg:x3; val_offset:30195*0 + 3*80*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 30195*0 + 3*81*FLEN/8, x4, x1, x2)

inst_10066:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x4e0246 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x10 and fm3 == 0x07ffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e4e0246; op2val:0x0;
op3val:0x807ffff; valaddr_reg:x3; val_offset:30198*0 + 3*81*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 30198*0 + 3*82*FLEN/8, x4, x1, x2)

inst_10067:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x4e0246 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x10 and fm3 == 0x0fffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e4e0246; op2val:0x0;
op3val:0x80fffff; valaddr_reg:x3; val_offset:30201*0 + 3*82*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 30201*0 + 3*83*FLEN/8, x4, x1, x2)

inst_10068:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x4e0246 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x10 and fm3 == 0x1fffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e4e0246; op2val:0x0;
op3val:0x81fffff; valaddr_reg:x3; val_offset:30204*0 + 3*83*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 30204*0 + 3*84*FLEN/8, x4, x1, x2)

inst_10069:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x4e0246 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x10 and fm3 == 0x3fffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e4e0246; op2val:0x0;
op3val:0x83fffff; valaddr_reg:x3; val_offset:30207*0 + 3*84*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 30207*0 + 3*85*FLEN/8, x4, x1, x2)

inst_10070:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x4e0246 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x10 and fm3 == 0x400000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e4e0246; op2val:0x0;
op3val:0x8400000; valaddr_reg:x3; val_offset:30210*0 + 3*85*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 30210*0 + 3*86*FLEN/8, x4, x1, x2)

inst_10071:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x4e0246 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x10 and fm3 == 0x600000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e4e0246; op2val:0x0;
op3val:0x8600000; valaddr_reg:x3; val_offset:30213*0 + 3*86*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 30213*0 + 3*87*FLEN/8, x4, x1, x2)

inst_10072:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x4e0246 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x10 and fm3 == 0x700000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e4e0246; op2val:0x0;
op3val:0x8700000; valaddr_reg:x3; val_offset:30216*0 + 3*87*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 30216*0 + 3*88*FLEN/8, x4, x1, x2)

inst_10073:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x4e0246 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x10 and fm3 == 0x780000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e4e0246; op2val:0x0;
op3val:0x8780000; valaddr_reg:x3; val_offset:30219*0 + 3*88*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 30219*0 + 3*89*FLEN/8, x4, x1, x2)

inst_10074:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x4e0246 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x10 and fm3 == 0x7c0000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e4e0246; op2val:0x0;
op3val:0x87c0000; valaddr_reg:x3; val_offset:30222*0 + 3*89*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 30222*0 + 3*90*FLEN/8, x4, x1, x2)

inst_10075:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x4e0246 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x10 and fm3 == 0x7e0000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e4e0246; op2val:0x0;
op3val:0x87e0000; valaddr_reg:x3; val_offset:30225*0 + 3*90*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 30225*0 + 3*91*FLEN/8, x4, x1, x2)

inst_10076:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x4e0246 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x10 and fm3 == 0x7f0000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e4e0246; op2val:0x0;
op3val:0x87f0000; valaddr_reg:x3; val_offset:30228*0 + 3*91*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 30228*0 + 3*92*FLEN/8, x4, x1, x2)

inst_10077:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x4e0246 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x10 and fm3 == 0x7f8000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e4e0246; op2val:0x0;
op3val:0x87f8000; valaddr_reg:x3; val_offset:30231*0 + 3*92*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 30231*0 + 3*93*FLEN/8, x4, x1, x2)

inst_10078:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x4e0246 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x10 and fm3 == 0x7fc000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e4e0246; op2val:0x0;
op3val:0x87fc000; valaddr_reg:x3; val_offset:30234*0 + 3*93*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 30234*0 + 3*94*FLEN/8, x4, x1, x2)

inst_10079:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x4e0246 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x10 and fm3 == 0x7fe000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e4e0246; op2val:0x0;
op3val:0x87fe000; valaddr_reg:x3; val_offset:30237*0 + 3*94*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 30237*0 + 3*95*FLEN/8, x4, x1, x2)

inst_10080:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x4e0246 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x10 and fm3 == 0x7ff000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e4e0246; op2val:0x0;
op3val:0x87ff000; valaddr_reg:x3; val_offset:30240*0 + 3*95*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 30240*0 + 3*96*FLEN/8, x4, x1, x2)

inst_10081:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x4e0246 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x10 and fm3 == 0x7ff800 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e4e0246; op2val:0x0;
op3val:0x87ff800; valaddr_reg:x3; val_offset:30243*0 + 3*96*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 30243*0 + 3*97*FLEN/8, x4, x1, x2)

inst_10082:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x4e0246 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x10 and fm3 == 0x7ffc00 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e4e0246; op2val:0x0;
op3val:0x87ffc00; valaddr_reg:x3; val_offset:30246*0 + 3*97*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 30246*0 + 3*98*FLEN/8, x4, x1, x2)

inst_10083:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x4e0246 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x10 and fm3 == 0x7ffe00 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e4e0246; op2val:0x0;
op3val:0x87ffe00; valaddr_reg:x3; val_offset:30249*0 + 3*98*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 30249*0 + 3*99*FLEN/8, x4, x1, x2)

inst_10084:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x4e0246 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x10 and fm3 == 0x7fff00 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e4e0246; op2val:0x0;
op3val:0x87fff00; valaddr_reg:x3; val_offset:30252*0 + 3*99*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 30252*0 + 3*100*FLEN/8, x4, x1, x2)

inst_10085:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x4e0246 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x10 and fm3 == 0x7fff80 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e4e0246; op2val:0x0;
op3val:0x87fff80; valaddr_reg:x3; val_offset:30255*0 + 3*100*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 30255*0 + 3*101*FLEN/8, x4, x1, x2)

inst_10086:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x4e0246 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x10 and fm3 == 0x7fffc0 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e4e0246; op2val:0x0;
op3val:0x87fffc0; valaddr_reg:x3; val_offset:30258*0 + 3*101*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 30258*0 + 3*102*FLEN/8, x4, x1, x2)

inst_10087:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x4e0246 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x10 and fm3 == 0x7fffe0 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e4e0246; op2val:0x0;
op3val:0x87fffe0; valaddr_reg:x3; val_offset:30261*0 + 3*102*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 30261*0 + 3*103*FLEN/8, x4, x1, x2)

inst_10088:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x4e0246 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x10 and fm3 == 0x7ffff0 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e4e0246; op2val:0x0;
op3val:0x87ffff0; valaddr_reg:x3; val_offset:30264*0 + 3*103*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 30264*0 + 3*104*FLEN/8, x4, x1, x2)

inst_10089:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x4e0246 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x10 and fm3 == 0x7ffff8 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e4e0246; op2val:0x0;
op3val:0x87ffff8; valaddr_reg:x3; val_offset:30267*0 + 3*104*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 30267*0 + 3*105*FLEN/8, x4, x1, x2)

inst_10090:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x4e0246 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x10 and fm3 == 0x7ffffc and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e4e0246; op2val:0x0;
op3val:0x87ffffc; valaddr_reg:x3; val_offset:30270*0 + 3*105*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 30270*0 + 3*106*FLEN/8, x4, x1, x2)

inst_10091:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x4e0246 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x10 and fm3 == 0x7ffffe and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e4e0246; op2val:0x0;
op3val:0x87ffffe; valaddr_reg:x3; val_offset:30273*0 + 3*106*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 30273*0 + 3*107*FLEN/8, x4, x1, x2)

inst_10092:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x4e0246 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x10 and fm3 == 0x7fffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e4e0246; op2val:0x0;
op3val:0x87fffff; valaddr_reg:x3; val_offset:30276*0 + 3*107*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 30276*0 + 3*108*FLEN/8, x4, x1, x2)

inst_10093:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x4e4fe8 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000001 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e4e4fe8; op2val:0x0;
op3val:0x800001; valaddr_reg:x3; val_offset:30279*0 + 3*108*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 30279*0 + 3*109*FLEN/8, x4, x1, x2)

inst_10094:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x4e4fe8 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000003 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e4e4fe8; op2val:0x0;
op3val:0x800003; valaddr_reg:x3; val_offset:30282*0 + 3*109*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 30282*0 + 3*110*FLEN/8, x4, x1, x2)

inst_10095:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x4e4fe8 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000007 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e4e4fe8; op2val:0x0;
op3val:0x800007; valaddr_reg:x3; val_offset:30285*0 + 3*110*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 30285*0 + 3*111*FLEN/8, x4, x1, x2)

inst_10096:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x4e4fe8 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x199999 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e4e4fe8; op2val:0x0;
op3val:0x999999; valaddr_reg:x3; val_offset:30288*0 + 3*111*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 30288*0 + 3*112*FLEN/8, x4, x1, x2)

inst_10097:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x4e4fe8 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x249249 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e4e4fe8; op2val:0x0;
op3val:0xa49249; valaddr_reg:x3; val_offset:30291*0 + 3*112*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 30291*0 + 3*113*FLEN/8, x4, x1, x2)

inst_10098:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x4e4fe8 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x333333 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e4e4fe8; op2val:0x0;
op3val:0xb33333; valaddr_reg:x3; val_offset:30294*0 + 3*113*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 30294*0 + 3*114*FLEN/8, x4, x1, x2)

inst_10099:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x4e4fe8 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x36db6d and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e4e4fe8; op2val:0x0;
op3val:0xb6db6d; valaddr_reg:x3; val_offset:30297*0 + 3*114*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 30297*0 + 3*115*FLEN/8, x4, x1, x2)

inst_10100:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x4e4fe8 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x3bbbbb and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e4e4fe8; op2val:0x0;
op3val:0xbbbbbb; valaddr_reg:x3; val_offset:30300*0 + 3*115*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 30300*0 + 3*116*FLEN/8, x4, x1, x2)

inst_10101:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x4e4fe8 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x444444 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e4e4fe8; op2val:0x0;
op3val:0xc44444; valaddr_reg:x3; val_offset:30303*0 + 3*116*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 30303*0 + 3*117*FLEN/8, x4, x1, x2)

inst_10102:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x4e4fe8 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x4ccccc and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e4e4fe8; op2val:0x0;
op3val:0xcccccc; valaddr_reg:x3; val_offset:30306*0 + 3*117*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 30306*0 + 3*118*FLEN/8, x4, x1, x2)

inst_10103:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x4e4fe8 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x5b6db6 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e4e4fe8; op2val:0x0;
op3val:0xdb6db6; valaddr_reg:x3; val_offset:30309*0 + 3*118*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 30309*0 + 3*119*FLEN/8, x4, x1, x2)

inst_10104:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x4e4fe8 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x666666 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e4e4fe8; op2val:0x0;
op3val:0xe66666; valaddr_reg:x3; val_offset:30312*0 + 3*119*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 30312*0 + 3*120*FLEN/8, x4, x1, x2)

inst_10105:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x4e4fe8 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x6db6db and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e4e4fe8; op2val:0x0;
op3val:0xedb6db; valaddr_reg:x3; val_offset:30315*0 + 3*120*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 30315*0 + 3*121*FLEN/8, x4, x1, x2)

inst_10106:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x4e4fe8 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x7ffff8 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e4e4fe8; op2val:0x0;
op3val:0xfffff8; valaddr_reg:x3; val_offset:30318*0 + 3*121*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 30318*0 + 3*122*FLEN/8, x4, x1, x2)

inst_10107:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x4e4fe8 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x7ffffc and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e4e4fe8; op2val:0x0;
op3val:0xfffffc; valaddr_reg:x3; val_offset:30321*0 + 3*122*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 30321*0 + 3*123*FLEN/8, x4, x1, x2)

inst_10108:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x4e4fe8 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x7ffffe and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e4e4fe8; op2val:0x0;
op3val:0xfffffe; valaddr_reg:x3; val_offset:30324*0 + 3*123*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 30324*0 + 3*124*FLEN/8, x4, x1, x2)

inst_10109:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x4e4fe8 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x09 and fm3 == 0x000000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e4e4fe8; op2val:0x0;
op3val:0x4800000; valaddr_reg:x3; val_offset:30327*0 + 3*124*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 30327*0 + 3*125*FLEN/8, x4, x1, x2)

inst_10110:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x4e4fe8 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x09 and fm3 == 0x000001 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e4e4fe8; op2val:0x0;
op3val:0x4800001; valaddr_reg:x3; val_offset:30330*0 + 3*125*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 30330*0 + 3*126*FLEN/8, x4, x1, x2)

inst_10111:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x4e4fe8 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x09 and fm3 == 0x000003 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e4e4fe8; op2val:0x0;
op3val:0x4800003; valaddr_reg:x3; val_offset:30333*0 + 3*126*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 30333*0 + 3*127*FLEN/8, x4, x1, x2)
RVTEST_SIGBASE(x1,signature_x1_2)

inst_10112:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x4e4fe8 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x09 and fm3 == 0x000007 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e4e4fe8; op2val:0x0;
op3val:0x4800007; valaddr_reg:x3; val_offset:30336*0 + 3*127*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 30336*0 + 3*128*FLEN/8, x4, x1, x2)

inst_10113:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x4e4fe8 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x09 and fm3 == 0x00000f and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e4e4fe8; op2val:0x0;
op3val:0x480000f; valaddr_reg:x3; val_offset:30339*0 + 3*128*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 30339*0 + 3*129*FLEN/8, x4, x1, x2)

inst_10114:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x4e4fe8 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x09 and fm3 == 0x00001f and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e4e4fe8; op2val:0x0;
op3val:0x480001f; valaddr_reg:x3; val_offset:30342*0 + 3*129*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 30342*0 + 3*130*FLEN/8, x4, x1, x2)

inst_10115:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x4e4fe8 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x09 and fm3 == 0x00003f and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e4e4fe8; op2val:0x0;
op3val:0x480003f; valaddr_reg:x3; val_offset:30345*0 + 3*130*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 30345*0 + 3*131*FLEN/8, x4, x1, x2)

inst_10116:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x4e4fe8 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x09 and fm3 == 0x00007f and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e4e4fe8; op2val:0x0;
op3val:0x480007f; valaddr_reg:x3; val_offset:30348*0 + 3*131*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 30348*0 + 3*132*FLEN/8, x4, x1, x2)

inst_10117:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x4e4fe8 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x09 and fm3 == 0x0000ff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e4e4fe8; op2val:0x0;
op3val:0x48000ff; valaddr_reg:x3; val_offset:30351*0 + 3*132*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 30351*0 + 3*133*FLEN/8, x4, x1, x2)

inst_10118:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x4e4fe8 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x09 and fm3 == 0x0001ff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e4e4fe8; op2val:0x0;
op3val:0x48001ff; valaddr_reg:x3; val_offset:30354*0 + 3*133*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 30354*0 + 3*134*FLEN/8, x4, x1, x2)

inst_10119:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x4e4fe8 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x09 and fm3 == 0x0003ff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e4e4fe8; op2val:0x0;
op3val:0x48003ff; valaddr_reg:x3; val_offset:30357*0 + 3*134*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 30357*0 + 3*135*FLEN/8, x4, x1, x2)

inst_10120:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x4e4fe8 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x09 and fm3 == 0x0007ff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e4e4fe8; op2val:0x0;
op3val:0x48007ff; valaddr_reg:x3; val_offset:30360*0 + 3*135*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 30360*0 + 3*136*FLEN/8, x4, x1, x2)

inst_10121:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x4e4fe8 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x09 and fm3 == 0x000fff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e4e4fe8; op2val:0x0;
op3val:0x4800fff; valaddr_reg:x3; val_offset:30363*0 + 3*136*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 30363*0 + 3*137*FLEN/8, x4, x1, x2)

inst_10122:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x4e4fe8 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x09 and fm3 == 0x001fff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e4e4fe8; op2val:0x0;
op3val:0x4801fff; valaddr_reg:x3; val_offset:30366*0 + 3*137*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 30366*0 + 3*138*FLEN/8, x4, x1, x2)

inst_10123:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x4e4fe8 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x09 and fm3 == 0x003fff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e4e4fe8; op2val:0x0;
op3val:0x4803fff; valaddr_reg:x3; val_offset:30369*0 + 3*138*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 30369*0 + 3*139*FLEN/8, x4, x1, x2)

inst_10124:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x4e4fe8 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x09 and fm3 == 0x007fff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e4e4fe8; op2val:0x0;
op3val:0x4807fff; valaddr_reg:x3; val_offset:30372*0 + 3*139*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 30372*0 + 3*140*FLEN/8, x4, x1, x2)

inst_10125:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x4e4fe8 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x09 and fm3 == 0x00ffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e4e4fe8; op2val:0x0;
op3val:0x480ffff; valaddr_reg:x3; val_offset:30375*0 + 3*140*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 30375*0 + 3*141*FLEN/8, x4, x1, x2)

inst_10126:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x4e4fe8 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x09 and fm3 == 0x01ffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e4e4fe8; op2val:0x0;
op3val:0x481ffff; valaddr_reg:x3; val_offset:30378*0 + 3*141*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 30378*0 + 3*142*FLEN/8, x4, x1, x2)

inst_10127:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x4e4fe8 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x09 and fm3 == 0x03ffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e4e4fe8; op2val:0x0;
op3val:0x483ffff; valaddr_reg:x3; val_offset:30381*0 + 3*142*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 30381*0 + 3*143*FLEN/8, x4, x1, x2)

inst_10128:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x4e4fe8 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x09 and fm3 == 0x07ffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e4e4fe8; op2val:0x0;
op3val:0x487ffff; valaddr_reg:x3; val_offset:30384*0 + 3*143*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 30384*0 + 3*144*FLEN/8, x4, x1, x2)

inst_10129:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x4e4fe8 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x09 and fm3 == 0x0fffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e4e4fe8; op2val:0x0;
op3val:0x48fffff; valaddr_reg:x3; val_offset:30387*0 + 3*144*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 30387*0 + 3*145*FLEN/8, x4, x1, x2)

inst_10130:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x4e4fe8 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x09 and fm3 == 0x1fffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e4e4fe8; op2val:0x0;
op3val:0x49fffff; valaddr_reg:x3; val_offset:30390*0 + 3*145*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 30390*0 + 3*146*FLEN/8, x4, x1, x2)

inst_10131:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x4e4fe8 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x09 and fm3 == 0x3fffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e4e4fe8; op2val:0x0;
op3val:0x4bfffff; valaddr_reg:x3; val_offset:30393*0 + 3*146*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 30393*0 + 3*147*FLEN/8, x4, x1, x2)

inst_10132:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x4e4fe8 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x09 and fm3 == 0x400000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e4e4fe8; op2val:0x0;
op3val:0x4c00000; valaddr_reg:x3; val_offset:30396*0 + 3*147*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 30396*0 + 3*148*FLEN/8, x4, x1, x2)

inst_10133:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x4e4fe8 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x09 and fm3 == 0x600000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e4e4fe8; op2val:0x0;
op3val:0x4e00000; valaddr_reg:x3; val_offset:30399*0 + 3*148*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 30399*0 + 3*149*FLEN/8, x4, x1, x2)

inst_10134:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x4e4fe8 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x09 and fm3 == 0x700000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e4e4fe8; op2val:0x0;
op3val:0x4f00000; valaddr_reg:x3; val_offset:30402*0 + 3*149*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 30402*0 + 3*150*FLEN/8, x4, x1, x2)

inst_10135:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x4e4fe8 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x09 and fm3 == 0x780000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e4e4fe8; op2val:0x0;
op3val:0x4f80000; valaddr_reg:x3; val_offset:30405*0 + 3*150*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 30405*0 + 3*151*FLEN/8, x4, x1, x2)

inst_10136:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x4e4fe8 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x09 and fm3 == 0x7c0000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e4e4fe8; op2val:0x0;
op3val:0x4fc0000; valaddr_reg:x3; val_offset:30408*0 + 3*151*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 30408*0 + 3*152*FLEN/8, x4, x1, x2)

inst_10137:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x4e4fe8 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x09 and fm3 == 0x7e0000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e4e4fe8; op2val:0x0;
op3val:0x4fe0000; valaddr_reg:x3; val_offset:30411*0 + 3*152*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 30411*0 + 3*153*FLEN/8, x4, x1, x2)

inst_10138:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x4e4fe8 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x09 and fm3 == 0x7f0000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e4e4fe8; op2val:0x0;
op3val:0x4ff0000; valaddr_reg:x3; val_offset:30414*0 + 3*153*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 30414*0 + 3*154*FLEN/8, x4, x1, x2)

inst_10139:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x4e4fe8 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x09 and fm3 == 0x7f8000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e4e4fe8; op2val:0x0;
op3val:0x4ff8000; valaddr_reg:x3; val_offset:30417*0 + 3*154*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 30417*0 + 3*155*FLEN/8, x4, x1, x2)

inst_10140:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x4e4fe8 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x09 and fm3 == 0x7fc000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e4e4fe8; op2val:0x0;
op3val:0x4ffc000; valaddr_reg:x3; val_offset:30420*0 + 3*155*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 30420*0 + 3*156*FLEN/8, x4, x1, x2)

inst_10141:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x4e4fe8 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x09 and fm3 == 0x7fe000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e4e4fe8; op2val:0x0;
op3val:0x4ffe000; valaddr_reg:x3; val_offset:30423*0 + 3*156*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 30423*0 + 3*157*FLEN/8, x4, x1, x2)

inst_10142:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x4e4fe8 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x09 and fm3 == 0x7ff000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e4e4fe8; op2val:0x0;
op3val:0x4fff000; valaddr_reg:x3; val_offset:30426*0 + 3*157*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 30426*0 + 3*158*FLEN/8, x4, x1, x2)

inst_10143:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x4e4fe8 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x09 and fm3 == 0x7ff800 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e4e4fe8; op2val:0x0;
op3val:0x4fff800; valaddr_reg:x3; val_offset:30429*0 + 3*158*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 30429*0 + 3*159*FLEN/8, x4, x1, x2)

inst_10144:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x4e4fe8 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x09 and fm3 == 0x7ffc00 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e4e4fe8; op2val:0x0;
op3val:0x4fffc00; valaddr_reg:x3; val_offset:30432*0 + 3*159*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 30432*0 + 3*160*FLEN/8, x4, x1, x2)

inst_10145:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x4e4fe8 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x09 and fm3 == 0x7ffe00 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e4e4fe8; op2val:0x0;
op3val:0x4fffe00; valaddr_reg:x3; val_offset:30435*0 + 3*160*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 30435*0 + 3*161*FLEN/8, x4, x1, x2)

inst_10146:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x4e4fe8 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x09 and fm3 == 0x7fff00 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e4e4fe8; op2val:0x0;
op3val:0x4ffff00; valaddr_reg:x3; val_offset:30438*0 + 3*161*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 30438*0 + 3*162*FLEN/8, x4, x1, x2)

inst_10147:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x4e4fe8 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x09 and fm3 == 0x7fff80 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e4e4fe8; op2val:0x0;
op3val:0x4ffff80; valaddr_reg:x3; val_offset:30441*0 + 3*162*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 30441*0 + 3*163*FLEN/8, x4, x1, x2)

inst_10148:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x4e4fe8 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x09 and fm3 == 0x7fffc0 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e4e4fe8; op2val:0x0;
op3val:0x4ffffc0; valaddr_reg:x3; val_offset:30444*0 + 3*163*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 30444*0 + 3*164*FLEN/8, x4, x1, x2)

inst_10149:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x4e4fe8 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x09 and fm3 == 0x7fffe0 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e4e4fe8; op2val:0x0;
op3val:0x4ffffe0; valaddr_reg:x3; val_offset:30447*0 + 3*164*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 30447*0 + 3*165*FLEN/8, x4, x1, x2)

inst_10150:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x4e4fe8 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x09 and fm3 == 0x7ffff0 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e4e4fe8; op2val:0x0;
op3val:0x4fffff0; valaddr_reg:x3; val_offset:30450*0 + 3*165*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 30450*0 + 3*166*FLEN/8, x4, x1, x2)

inst_10151:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x4e4fe8 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x09 and fm3 == 0x7ffff8 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e4e4fe8; op2val:0x0;
op3val:0x4fffff8; valaddr_reg:x3; val_offset:30453*0 + 3*166*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 30453*0 + 3*167*FLEN/8, x4, x1, x2)

inst_10152:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x4e4fe8 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x09 and fm3 == 0x7ffffc and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e4e4fe8; op2val:0x0;
op3val:0x4fffffc; valaddr_reg:x3; val_offset:30456*0 + 3*167*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 30456*0 + 3*168*FLEN/8, x4, x1, x2)

inst_10153:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x4e4fe8 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x09 and fm3 == 0x7ffffe and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e4e4fe8; op2val:0x0;
op3val:0x4fffffe; valaddr_reg:x3; val_offset:30459*0 + 3*168*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 30459*0 + 3*169*FLEN/8, x4, x1, x2)

inst_10154:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x4e4fe8 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x09 and fm3 == 0x7fffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e4e4fe8; op2val:0x0;
op3val:0x4ffffff; valaddr_reg:x3; val_offset:30462*0 + 3*169*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 30462*0 + 3*170*FLEN/8, x4, x1, x2)

inst_10155:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x512e72 and fs2 == 1 and fe2 == 0x81 and fm2 == 0x1ca610 and fs3 == 1 and fe3 == 0xcb and fm3 == 0x000000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e512e72; op2val:0xc09ca610;
op3val:0xe5800000; valaddr_reg:x3; val_offset:30465*0 + 3*170*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 30465*0 + 3*171*FLEN/8, x4, x1, x2)

inst_10156:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x512e72 and fs2 == 1 and fe2 == 0x81 and fm2 == 0x1ca610 and fs3 == 1 and fe3 == 0xcb and fm3 == 0x000001 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e512e72; op2val:0xc09ca610;
op3val:0xe5800001; valaddr_reg:x3; val_offset:30468*0 + 3*171*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 30468*0 + 3*172*FLEN/8, x4, x1, x2)

inst_10157:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x512e72 and fs2 == 1 and fe2 == 0x81 and fm2 == 0x1ca610 and fs3 == 1 and fe3 == 0xcb and fm3 == 0x000003 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e512e72; op2val:0xc09ca610;
op3val:0xe5800003; valaddr_reg:x3; val_offset:30471*0 + 3*172*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 30471*0 + 3*173*FLEN/8, x4, x1, x2)

inst_10158:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x512e72 and fs2 == 1 and fe2 == 0x81 and fm2 == 0x1ca610 and fs3 == 1 and fe3 == 0xcb and fm3 == 0x000007 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e512e72; op2val:0xc09ca610;
op3val:0xe5800007; valaddr_reg:x3; val_offset:30474*0 + 3*173*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 30474*0 + 3*174*FLEN/8, x4, x1, x2)

inst_10159:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x512e72 and fs2 == 1 and fe2 == 0x81 and fm2 == 0x1ca610 and fs3 == 1 and fe3 == 0xcb and fm3 == 0x00000f and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e512e72; op2val:0xc09ca610;
op3val:0xe580000f; valaddr_reg:x3; val_offset:30477*0 + 3*174*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 30477*0 + 3*175*FLEN/8, x4, x1, x2)

inst_10160:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x512e72 and fs2 == 1 and fe2 == 0x81 and fm2 == 0x1ca610 and fs3 == 1 and fe3 == 0xcb and fm3 == 0x00001f and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e512e72; op2val:0xc09ca610;
op3val:0xe580001f; valaddr_reg:x3; val_offset:30480*0 + 3*175*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 30480*0 + 3*176*FLEN/8, x4, x1, x2)

inst_10161:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x512e72 and fs2 == 1 and fe2 == 0x81 and fm2 == 0x1ca610 and fs3 == 1 and fe3 == 0xcb and fm3 == 0x00003f and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e512e72; op2val:0xc09ca610;
op3val:0xe580003f; valaddr_reg:x3; val_offset:30483*0 + 3*176*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 30483*0 + 3*177*FLEN/8, x4, x1, x2)

inst_10162:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x512e72 and fs2 == 1 and fe2 == 0x81 and fm2 == 0x1ca610 and fs3 == 1 and fe3 == 0xcb and fm3 == 0x00007f and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e512e72; op2val:0xc09ca610;
op3val:0xe580007f; valaddr_reg:x3; val_offset:30486*0 + 3*177*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 30486*0 + 3*178*FLEN/8, x4, x1, x2)

inst_10163:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x512e72 and fs2 == 1 and fe2 == 0x81 and fm2 == 0x1ca610 and fs3 == 1 and fe3 == 0xcb and fm3 == 0x0000ff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e512e72; op2val:0xc09ca610;
op3val:0xe58000ff; valaddr_reg:x3; val_offset:30489*0 + 3*178*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 30489*0 + 3*179*FLEN/8, x4, x1, x2)

inst_10164:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x512e72 and fs2 == 1 and fe2 == 0x81 and fm2 == 0x1ca610 and fs3 == 1 and fe3 == 0xcb and fm3 == 0x0001ff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e512e72; op2val:0xc09ca610;
op3val:0xe58001ff; valaddr_reg:x3; val_offset:30492*0 + 3*179*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 30492*0 + 3*180*FLEN/8, x4, x1, x2)

inst_10165:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x512e72 and fs2 == 1 and fe2 == 0x81 and fm2 == 0x1ca610 and fs3 == 1 and fe3 == 0xcb and fm3 == 0x0003ff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e512e72; op2val:0xc09ca610;
op3val:0xe58003ff; valaddr_reg:x3; val_offset:30495*0 + 3*180*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 30495*0 + 3*181*FLEN/8, x4, x1, x2)

inst_10166:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x512e72 and fs2 == 1 and fe2 == 0x81 and fm2 == 0x1ca610 and fs3 == 1 and fe3 == 0xcb and fm3 == 0x0007ff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e512e72; op2val:0xc09ca610;
op3val:0xe58007ff; valaddr_reg:x3; val_offset:30498*0 + 3*181*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 30498*0 + 3*182*FLEN/8, x4, x1, x2)

inst_10167:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x512e72 and fs2 == 1 and fe2 == 0x81 and fm2 == 0x1ca610 and fs3 == 1 and fe3 == 0xcb and fm3 == 0x000fff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e512e72; op2val:0xc09ca610;
op3val:0xe5800fff; valaddr_reg:x3; val_offset:30501*0 + 3*182*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 30501*0 + 3*183*FLEN/8, x4, x1, x2)

inst_10168:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x512e72 and fs2 == 1 and fe2 == 0x81 and fm2 == 0x1ca610 and fs3 == 1 and fe3 == 0xcb and fm3 == 0x001fff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e512e72; op2val:0xc09ca610;
op3val:0xe5801fff; valaddr_reg:x3; val_offset:30504*0 + 3*183*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 30504*0 + 3*184*FLEN/8, x4, x1, x2)

inst_10169:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x512e72 and fs2 == 1 and fe2 == 0x81 and fm2 == 0x1ca610 and fs3 == 1 and fe3 == 0xcb and fm3 == 0x003fff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e512e72; op2val:0xc09ca610;
op3val:0xe5803fff; valaddr_reg:x3; val_offset:30507*0 + 3*184*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 30507*0 + 3*185*FLEN/8, x4, x1, x2)

inst_10170:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x512e72 and fs2 == 1 and fe2 == 0x81 and fm2 == 0x1ca610 and fs3 == 1 and fe3 == 0xcb and fm3 == 0x007fff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e512e72; op2val:0xc09ca610;
op3val:0xe5807fff; valaddr_reg:x3; val_offset:30510*0 + 3*185*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 30510*0 + 3*186*FLEN/8, x4, x1, x2)

inst_10171:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x512e72 and fs2 == 1 and fe2 == 0x81 and fm2 == 0x1ca610 and fs3 == 1 and fe3 == 0xcb and fm3 == 0x00ffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e512e72; op2val:0xc09ca610;
op3val:0xe580ffff; valaddr_reg:x3; val_offset:30513*0 + 3*186*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 30513*0 + 3*187*FLEN/8, x4, x1, x2)

inst_10172:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x512e72 and fs2 == 1 and fe2 == 0x81 and fm2 == 0x1ca610 and fs3 == 1 and fe3 == 0xcb and fm3 == 0x01ffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e512e72; op2val:0xc09ca610;
op3val:0xe581ffff; valaddr_reg:x3; val_offset:30516*0 + 3*187*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 30516*0 + 3*188*FLEN/8, x4, x1, x2)

inst_10173:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x512e72 and fs2 == 1 and fe2 == 0x81 and fm2 == 0x1ca610 and fs3 == 1 and fe3 == 0xcb and fm3 == 0x03ffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e512e72; op2val:0xc09ca610;
op3val:0xe583ffff; valaddr_reg:x3; val_offset:30519*0 + 3*188*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 30519*0 + 3*189*FLEN/8, x4, x1, x2)

inst_10174:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x512e72 and fs2 == 1 and fe2 == 0x81 and fm2 == 0x1ca610 and fs3 == 1 and fe3 == 0xcb and fm3 == 0x07ffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e512e72; op2val:0xc09ca610;
op3val:0xe587ffff; valaddr_reg:x3; val_offset:30522*0 + 3*189*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 30522*0 + 3*190*FLEN/8, x4, x1, x2)

inst_10175:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x512e72 and fs2 == 1 and fe2 == 0x81 and fm2 == 0x1ca610 and fs3 == 1 and fe3 == 0xcb and fm3 == 0x0fffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e512e72; op2val:0xc09ca610;
op3val:0xe58fffff; valaddr_reg:x3; val_offset:30525*0 + 3*190*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 30525*0 + 3*191*FLEN/8, x4, x1, x2)

inst_10176:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x512e72 and fs2 == 1 and fe2 == 0x81 and fm2 == 0x1ca610 and fs3 == 1 and fe3 == 0xcb and fm3 == 0x1fffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e512e72; op2val:0xc09ca610;
op3val:0xe59fffff; valaddr_reg:x3; val_offset:30528*0 + 3*191*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 30528*0 + 3*192*FLEN/8, x4, x1, x2)

inst_10177:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x512e72 and fs2 == 1 and fe2 == 0x81 and fm2 == 0x1ca610 and fs3 == 1 and fe3 == 0xcb and fm3 == 0x3fffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e512e72; op2val:0xc09ca610;
op3val:0xe5bfffff; valaddr_reg:x3; val_offset:30531*0 + 3*192*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 30531*0 + 3*193*FLEN/8, x4, x1, x2)

inst_10178:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x512e72 and fs2 == 1 and fe2 == 0x81 and fm2 == 0x1ca610 and fs3 == 1 and fe3 == 0xcb and fm3 == 0x400000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e512e72; op2val:0xc09ca610;
op3val:0xe5c00000; valaddr_reg:x3; val_offset:30534*0 + 3*193*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 30534*0 + 3*194*FLEN/8, x4, x1, x2)

inst_10179:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x512e72 and fs2 == 1 and fe2 == 0x81 and fm2 == 0x1ca610 and fs3 == 1 and fe3 == 0xcb and fm3 == 0x600000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e512e72; op2val:0xc09ca610;
op3val:0xe5e00000; valaddr_reg:x3; val_offset:30537*0 + 3*194*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 30537*0 + 3*195*FLEN/8, x4, x1, x2)

inst_10180:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x512e72 and fs2 == 1 and fe2 == 0x81 and fm2 == 0x1ca610 and fs3 == 1 and fe3 == 0xcb and fm3 == 0x700000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e512e72; op2val:0xc09ca610;
op3val:0xe5f00000; valaddr_reg:x3; val_offset:30540*0 + 3*195*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 30540*0 + 3*196*FLEN/8, x4, x1, x2)

inst_10181:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x512e72 and fs2 == 1 and fe2 == 0x81 and fm2 == 0x1ca610 and fs3 == 1 and fe3 == 0xcb and fm3 == 0x780000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e512e72; op2val:0xc09ca610;
op3val:0xe5f80000; valaddr_reg:x3; val_offset:30543*0 + 3*196*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 30543*0 + 3*197*FLEN/8, x4, x1, x2)

inst_10182:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x512e72 and fs2 == 1 and fe2 == 0x81 and fm2 == 0x1ca610 and fs3 == 1 and fe3 == 0xcb and fm3 == 0x7c0000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e512e72; op2val:0xc09ca610;
op3val:0xe5fc0000; valaddr_reg:x3; val_offset:30546*0 + 3*197*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 30546*0 + 3*198*FLEN/8, x4, x1, x2)

inst_10183:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x512e72 and fs2 == 1 and fe2 == 0x81 and fm2 == 0x1ca610 and fs3 == 1 and fe3 == 0xcb and fm3 == 0x7e0000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e512e72; op2val:0xc09ca610;
op3val:0xe5fe0000; valaddr_reg:x3; val_offset:30549*0 + 3*198*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 30549*0 + 3*199*FLEN/8, x4, x1, x2)

inst_10184:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x512e72 and fs2 == 1 and fe2 == 0x81 and fm2 == 0x1ca610 and fs3 == 1 and fe3 == 0xcb and fm3 == 0x7f0000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e512e72; op2val:0xc09ca610;
op3val:0xe5ff0000; valaddr_reg:x3; val_offset:30552*0 + 3*199*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 30552*0 + 3*200*FLEN/8, x4, x1, x2)

inst_10185:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x512e72 and fs2 == 1 and fe2 == 0x81 and fm2 == 0x1ca610 and fs3 == 1 and fe3 == 0xcb and fm3 == 0x7f8000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e512e72; op2val:0xc09ca610;
op3val:0xe5ff8000; valaddr_reg:x3; val_offset:30555*0 + 3*200*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 30555*0 + 3*201*FLEN/8, x4, x1, x2)

inst_10186:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x512e72 and fs2 == 1 and fe2 == 0x81 and fm2 == 0x1ca610 and fs3 == 1 and fe3 == 0xcb and fm3 == 0x7fc000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e512e72; op2val:0xc09ca610;
op3val:0xe5ffc000; valaddr_reg:x3; val_offset:30558*0 + 3*201*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 30558*0 + 3*202*FLEN/8, x4, x1, x2)

inst_10187:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x512e72 and fs2 == 1 and fe2 == 0x81 and fm2 == 0x1ca610 and fs3 == 1 and fe3 == 0xcb and fm3 == 0x7fe000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e512e72; op2val:0xc09ca610;
op3val:0xe5ffe000; valaddr_reg:x3; val_offset:30561*0 + 3*202*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 30561*0 + 3*203*FLEN/8, x4, x1, x2)

inst_10188:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x512e72 and fs2 == 1 and fe2 == 0x81 and fm2 == 0x1ca610 and fs3 == 1 and fe3 == 0xcb and fm3 == 0x7ff000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e512e72; op2val:0xc09ca610;
op3val:0xe5fff000; valaddr_reg:x3; val_offset:30564*0 + 3*203*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 30564*0 + 3*204*FLEN/8, x4, x1, x2)

inst_10189:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x512e72 and fs2 == 1 and fe2 == 0x81 and fm2 == 0x1ca610 and fs3 == 1 and fe3 == 0xcb and fm3 == 0x7ff800 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e512e72; op2val:0xc09ca610;
op3val:0xe5fff800; valaddr_reg:x3; val_offset:30567*0 + 3*204*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 30567*0 + 3*205*FLEN/8, x4, x1, x2)

inst_10190:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x512e72 and fs2 == 1 and fe2 == 0x81 and fm2 == 0x1ca610 and fs3 == 1 and fe3 == 0xcb and fm3 == 0x7ffc00 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e512e72; op2val:0xc09ca610;
op3val:0xe5fffc00; valaddr_reg:x3; val_offset:30570*0 + 3*205*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 30570*0 + 3*206*FLEN/8, x4, x1, x2)

inst_10191:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x512e72 and fs2 == 1 and fe2 == 0x81 and fm2 == 0x1ca610 and fs3 == 1 and fe3 == 0xcb and fm3 == 0x7ffe00 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e512e72; op2val:0xc09ca610;
op3val:0xe5fffe00; valaddr_reg:x3; val_offset:30573*0 + 3*206*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 30573*0 + 3*207*FLEN/8, x4, x1, x2)

inst_10192:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x512e72 and fs2 == 1 and fe2 == 0x81 and fm2 == 0x1ca610 and fs3 == 1 and fe3 == 0xcb and fm3 == 0x7fff00 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e512e72; op2val:0xc09ca610;
op3val:0xe5ffff00; valaddr_reg:x3; val_offset:30576*0 + 3*207*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 30576*0 + 3*208*FLEN/8, x4, x1, x2)

inst_10193:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x512e72 and fs2 == 1 and fe2 == 0x81 and fm2 == 0x1ca610 and fs3 == 1 and fe3 == 0xcb and fm3 == 0x7fff80 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e512e72; op2val:0xc09ca610;
op3val:0xe5ffff80; valaddr_reg:x3; val_offset:30579*0 + 3*208*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 30579*0 + 3*209*FLEN/8, x4, x1, x2)

inst_10194:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x512e72 and fs2 == 1 and fe2 == 0x81 and fm2 == 0x1ca610 and fs3 == 1 and fe3 == 0xcb and fm3 == 0x7fffc0 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e512e72; op2val:0xc09ca610;
op3val:0xe5ffffc0; valaddr_reg:x3; val_offset:30582*0 + 3*209*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 30582*0 + 3*210*FLEN/8, x4, x1, x2)

inst_10195:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x512e72 and fs2 == 1 and fe2 == 0x81 and fm2 == 0x1ca610 and fs3 == 1 and fe3 == 0xcb and fm3 == 0x7fffe0 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e512e72; op2val:0xc09ca610;
op3val:0xe5ffffe0; valaddr_reg:x3; val_offset:30585*0 + 3*210*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 30585*0 + 3*211*FLEN/8, x4, x1, x2)

inst_10196:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x512e72 and fs2 == 1 and fe2 == 0x81 and fm2 == 0x1ca610 and fs3 == 1 and fe3 == 0xcb and fm3 == 0x7ffff0 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e512e72; op2val:0xc09ca610;
op3val:0xe5fffff0; valaddr_reg:x3; val_offset:30588*0 + 3*211*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 30588*0 + 3*212*FLEN/8, x4, x1, x2)

inst_10197:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x512e72 and fs2 == 1 and fe2 == 0x81 and fm2 == 0x1ca610 and fs3 == 1 and fe3 == 0xcb and fm3 == 0x7ffff8 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e512e72; op2val:0xc09ca610;
op3val:0xe5fffff8; valaddr_reg:x3; val_offset:30591*0 + 3*212*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 30591*0 + 3*213*FLEN/8, x4, x1, x2)

inst_10198:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x512e72 and fs2 == 1 and fe2 == 0x81 and fm2 == 0x1ca610 and fs3 == 1 and fe3 == 0xcb and fm3 == 0x7ffffc and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e512e72; op2val:0xc09ca610;
op3val:0xe5fffffc; valaddr_reg:x3; val_offset:30594*0 + 3*213*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 30594*0 + 3*214*FLEN/8, x4, x1, x2)

inst_10199:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x512e72 and fs2 == 1 and fe2 == 0x81 and fm2 == 0x1ca610 and fs3 == 1 and fe3 == 0xcb and fm3 == 0x7ffffe and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e512e72; op2val:0xc09ca610;
op3val:0xe5fffffe; valaddr_reg:x3; val_offset:30597*0 + 3*214*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 30597*0 + 3*215*FLEN/8, x4, x1, x2)

inst_10200:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x512e72 and fs2 == 1 and fe2 == 0x81 and fm2 == 0x1ca610 and fs3 == 1 and fe3 == 0xcb and fm3 == 0x7fffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e512e72; op2val:0xc09ca610;
op3val:0xe5ffffff; valaddr_reg:x3; val_offset:30600*0 + 3*215*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 30600*0 + 3*216*FLEN/8, x4, x1, x2)

inst_10201:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x512e72 and fs2 == 1 and fe2 == 0x81 and fm2 == 0x1ca610 and fs3 == 1 and fe3 == 0xfe and fm3 == 0x000001 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e512e72; op2val:0xc09ca610;
op3val:0xff000001; valaddr_reg:x3; val_offset:30603*0 + 3*216*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 30603*0 + 3*217*FLEN/8, x4, x1, x2)

inst_10202:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x512e72 and fs2 == 1 and fe2 == 0x81 and fm2 == 0x1ca610 and fs3 == 1 and fe3 == 0xfe and fm3 == 0x000003 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e512e72; op2val:0xc09ca610;
op3val:0xff000003; valaddr_reg:x3; val_offset:30606*0 + 3*217*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 30606*0 + 3*218*FLEN/8, x4, x1, x2)

inst_10203:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x512e72 and fs2 == 1 and fe2 == 0x81 and fm2 == 0x1ca610 and fs3 == 1 and fe3 == 0xfe and fm3 == 0x000007 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e512e72; op2val:0xc09ca610;
op3val:0xff000007; valaddr_reg:x3; val_offset:30609*0 + 3*218*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 30609*0 + 3*219*FLEN/8, x4, x1, x2)

inst_10204:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x512e72 and fs2 == 1 and fe2 == 0x81 and fm2 == 0x1ca610 and fs3 == 1 and fe3 == 0xfe and fm3 == 0x199999 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e512e72; op2val:0xc09ca610;
op3val:0xff199999; valaddr_reg:x3; val_offset:30612*0 + 3*219*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 30612*0 + 3*220*FLEN/8, x4, x1, x2)

inst_10205:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x512e72 and fs2 == 1 and fe2 == 0x81 and fm2 == 0x1ca610 and fs3 == 1 and fe3 == 0xfe and fm3 == 0x249249 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e512e72; op2val:0xc09ca610;
op3val:0xff249249; valaddr_reg:x3; val_offset:30615*0 + 3*220*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 30615*0 + 3*221*FLEN/8, x4, x1, x2)

inst_10206:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x512e72 and fs2 == 1 and fe2 == 0x81 and fm2 == 0x1ca610 and fs3 == 1 and fe3 == 0xfe and fm3 == 0x333333 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e512e72; op2val:0xc09ca610;
op3val:0xff333333; valaddr_reg:x3; val_offset:30618*0 + 3*221*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 30618*0 + 3*222*FLEN/8, x4, x1, x2)

inst_10207:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x512e72 and fs2 == 1 and fe2 == 0x81 and fm2 == 0x1ca610 and fs3 == 1 and fe3 == 0xfe and fm3 == 0x36db6d and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e512e72; op2val:0xc09ca610;
op3val:0xff36db6d; valaddr_reg:x3; val_offset:30621*0 + 3*222*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 30621*0 + 3*223*FLEN/8, x4, x1, x2)

inst_10208:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x512e72 and fs2 == 1 and fe2 == 0x81 and fm2 == 0x1ca610 and fs3 == 1 and fe3 == 0xfe and fm3 == 0x3bbbbb and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e512e72; op2val:0xc09ca610;
op3val:0xff3bbbbb; valaddr_reg:x3; val_offset:30624*0 + 3*223*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 30624*0 + 3*224*FLEN/8, x4, x1, x2)

inst_10209:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x512e72 and fs2 == 1 and fe2 == 0x81 and fm2 == 0x1ca610 and fs3 == 1 and fe3 == 0xfe and fm3 == 0x444444 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e512e72; op2val:0xc09ca610;
op3val:0xff444444; valaddr_reg:x3; val_offset:30627*0 + 3*224*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 30627*0 + 3*225*FLEN/8, x4, x1, x2)

inst_10210:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x512e72 and fs2 == 1 and fe2 == 0x81 and fm2 == 0x1ca610 and fs3 == 1 and fe3 == 0xfe and fm3 == 0x4ccccc and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e512e72; op2val:0xc09ca610;
op3val:0xff4ccccc; valaddr_reg:x3; val_offset:30630*0 + 3*225*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 30630*0 + 3*226*FLEN/8, x4, x1, x2)

inst_10211:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x512e72 and fs2 == 1 and fe2 == 0x81 and fm2 == 0x1ca610 and fs3 == 1 and fe3 == 0xfe and fm3 == 0x5b6db6 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e512e72; op2val:0xc09ca610;
op3val:0xff5b6db6; valaddr_reg:x3; val_offset:30633*0 + 3*226*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 30633*0 + 3*227*FLEN/8, x4, x1, x2)

inst_10212:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x512e72 and fs2 == 1 and fe2 == 0x81 and fm2 == 0x1ca610 and fs3 == 1 and fe3 == 0xfe and fm3 == 0x666666 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e512e72; op2val:0xc09ca610;
op3val:0xff666666; valaddr_reg:x3; val_offset:30636*0 + 3*227*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 30636*0 + 3*228*FLEN/8, x4, x1, x2)

inst_10213:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x512e72 and fs2 == 1 and fe2 == 0x81 and fm2 == 0x1ca610 and fs3 == 1 and fe3 == 0xfe and fm3 == 0x6db6db and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e512e72; op2val:0xc09ca610;
op3val:0xff6db6db; valaddr_reg:x3; val_offset:30639*0 + 3*228*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 30639*0 + 3*229*FLEN/8, x4, x1, x2)

inst_10214:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x512e72 and fs2 == 1 and fe2 == 0x81 and fm2 == 0x1ca610 and fs3 == 1 and fe3 == 0xfe and fm3 == 0x7ffff8 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e512e72; op2val:0xc09ca610;
op3val:0xff7ffff8; valaddr_reg:x3; val_offset:30642*0 + 3*229*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 30642*0 + 3*230*FLEN/8, x4, x1, x2)

inst_10215:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x512e72 and fs2 == 1 and fe2 == 0x81 and fm2 == 0x1ca610 and fs3 == 1 and fe3 == 0xfe and fm3 == 0x7ffffc and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e512e72; op2val:0xc09ca610;
op3val:0xff7ffffc; valaddr_reg:x3; val_offset:30645*0 + 3*230*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 30645*0 + 3*231*FLEN/8, x4, x1, x2)

inst_10216:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x512e72 and fs2 == 1 and fe2 == 0x81 and fm2 == 0x1ca610 and fs3 == 1 and fe3 == 0xfe and fm3 == 0x7ffffe and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e512e72; op2val:0xc09ca610;
op3val:0xff7ffffe; valaddr_reg:x3; val_offset:30648*0 + 3*231*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 30648*0 + 3*232*FLEN/8, x4, x1, x2)

inst_10217:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x51b0b6 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e51b0b6; op2val:0x0;
op3val:0x0; valaddr_reg:x3; val_offset:30651*0 + 3*232*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 30651*0 + 3*233*FLEN/8, x4, x1, x2)

inst_10218:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x51b0b6 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000001 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e51b0b6; op2val:0x0;
op3val:0x1; valaddr_reg:x3; val_offset:30654*0 + 3*233*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 30654*0 + 3*234*FLEN/8, x4, x1, x2)

inst_10219:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x51b0b6 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000003 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e51b0b6; op2val:0x0;
op3val:0x3; valaddr_reg:x3; val_offset:30657*0 + 3*234*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 30657*0 + 3*235*FLEN/8, x4, x1, x2)

inst_10220:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x51b0b6 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000007 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e51b0b6; op2val:0x0;
op3val:0x7; valaddr_reg:x3; val_offset:30660*0 + 3*235*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 30660*0 + 3*236*FLEN/8, x4, x1, x2)

inst_10221:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x51b0b6 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x00000f and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e51b0b6; op2val:0x0;
op3val:0xf; valaddr_reg:x3; val_offset:30663*0 + 3*236*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 30663*0 + 3*237*FLEN/8, x4, x1, x2)

inst_10222:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x51b0b6 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x00001f and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e51b0b6; op2val:0x0;
op3val:0x1f; valaddr_reg:x3; val_offset:30666*0 + 3*237*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 30666*0 + 3*238*FLEN/8, x4, x1, x2)

inst_10223:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x51b0b6 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x00003f and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e51b0b6; op2val:0x0;
op3val:0x3f; valaddr_reg:x3; val_offset:30669*0 + 3*238*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 30669*0 + 3*239*FLEN/8, x4, x1, x2)

inst_10224:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x51b0b6 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x00007f and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e51b0b6; op2val:0x0;
op3val:0x7f; valaddr_reg:x3; val_offset:30672*0 + 3*239*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 30672*0 + 3*240*FLEN/8, x4, x1, x2)

inst_10225:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x51b0b6 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x0000ff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e51b0b6; op2val:0x0;
op3val:0xff; valaddr_reg:x3; val_offset:30675*0 + 3*240*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 30675*0 + 3*241*FLEN/8, x4, x1, x2)

inst_10226:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x51b0b6 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x0001ff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e51b0b6; op2val:0x0;
op3val:0x1ff; valaddr_reg:x3; val_offset:30678*0 + 3*241*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 30678*0 + 3*242*FLEN/8, x4, x1, x2)

inst_10227:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x51b0b6 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x0003ff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e51b0b6; op2val:0x0;
op3val:0x3ff; valaddr_reg:x3; val_offset:30681*0 + 3*242*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 30681*0 + 3*243*FLEN/8, x4, x1, x2)

inst_10228:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x51b0b6 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x0007ff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e51b0b6; op2val:0x0;
op3val:0x7ff; valaddr_reg:x3; val_offset:30684*0 + 3*243*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 30684*0 + 3*244*FLEN/8, x4, x1, x2)

inst_10229:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x51b0b6 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000fff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e51b0b6; op2val:0x0;
op3val:0xfff; valaddr_reg:x3; val_offset:30687*0 + 3*244*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 30687*0 + 3*245*FLEN/8, x4, x1, x2)

inst_10230:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x51b0b6 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x001fff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e51b0b6; op2val:0x0;
op3val:0x1fff; valaddr_reg:x3; val_offset:30690*0 + 3*245*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 30690*0 + 3*246*FLEN/8, x4, x1, x2)

inst_10231:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x51b0b6 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x003fff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e51b0b6; op2val:0x0;
op3val:0x3fff; valaddr_reg:x3; val_offset:30693*0 + 3*246*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 30693*0 + 3*247*FLEN/8, x4, x1, x2)

inst_10232:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x51b0b6 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x007fff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e51b0b6; op2val:0x0;
op3val:0x7fff; valaddr_reg:x3; val_offset:30696*0 + 3*247*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 30696*0 + 3*248*FLEN/8, x4, x1, x2)

inst_10233:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x51b0b6 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x00ffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e51b0b6; op2val:0x0;
op3val:0xffff; valaddr_reg:x3; val_offset:30699*0 + 3*248*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 30699*0 + 3*249*FLEN/8, x4, x1, x2)

inst_10234:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x51b0b6 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x01ffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e51b0b6; op2val:0x0;
op3val:0x1ffff; valaddr_reg:x3; val_offset:30702*0 + 3*249*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 30702*0 + 3*250*FLEN/8, x4, x1, x2)

inst_10235:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x51b0b6 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x03ffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e51b0b6; op2val:0x0;
op3val:0x3ffff; valaddr_reg:x3; val_offset:30705*0 + 3*250*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 30705*0 + 3*251*FLEN/8, x4, x1, x2)

inst_10236:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x51b0b6 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x07ffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e51b0b6; op2val:0x0;
op3val:0x7ffff; valaddr_reg:x3; val_offset:30708*0 + 3*251*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 30708*0 + 3*252*FLEN/8, x4, x1, x2)

inst_10237:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x51b0b6 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x0fffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e51b0b6; op2val:0x0;
op3val:0xfffff; valaddr_reg:x3; val_offset:30711*0 + 3*252*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 30711*0 + 3*253*FLEN/8, x4, x1, x2)

inst_10238:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x51b0b6 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x1fffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e51b0b6; op2val:0x0;
op3val:0x1fffff; valaddr_reg:x3; val_offset:30714*0 + 3*253*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 30714*0 + 3*254*FLEN/8, x4, x1, x2)

inst_10239:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x51b0b6 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x3fffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e51b0b6; op2val:0x0;
op3val:0x3fffff; valaddr_reg:x3; val_offset:30717*0 + 3*254*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 30717*0 + 3*255*FLEN/8, x4, x1, x2)
RVTEST_SIGBASE(x1,signature_x1_3)

inst_10240:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x51b0b6 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x400000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e51b0b6; op2val:0x0;
op3val:0x400000; valaddr_reg:x3; val_offset:30720*0 + 3*256*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 30720*0 + 3*256*FLEN/8, x4, x1, x2)

inst_10241:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x51b0b6 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x600000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e51b0b6; op2val:0x0;
op3val:0x600000; valaddr_reg:x3; val_offset:30723*0 + 3*257*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 30723*0 + 3*257*FLEN/8, x4, x1, x2)

inst_10242:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x51b0b6 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x700000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e51b0b6; op2val:0x0;
op3val:0x700000; valaddr_reg:x3; val_offset:30726*0 + 3*258*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 30726*0 + 3*258*FLEN/8, x4, x1, x2)

inst_10243:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x51b0b6 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x780000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e51b0b6; op2val:0x0;
op3val:0x780000; valaddr_reg:x3; val_offset:30729*0 + 3*259*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 30729*0 + 3*259*FLEN/8, x4, x1, x2)

inst_10244:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x51b0b6 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x7c0000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e51b0b6; op2val:0x0;
op3val:0x7c0000; valaddr_reg:x3; val_offset:30732*0 + 3*260*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 30732*0 + 3*260*FLEN/8, x4, x1, x2)

inst_10245:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x51b0b6 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x7e0000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e51b0b6; op2val:0x0;
op3val:0x7e0000; valaddr_reg:x3; val_offset:30735*0 + 3*261*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 30735*0 + 3*261*FLEN/8, x4, x1, x2)

inst_10246:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x51b0b6 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x7f0000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e51b0b6; op2val:0x0;
op3val:0x7f0000; valaddr_reg:x3; val_offset:30738*0 + 3*262*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 30738*0 + 3*262*FLEN/8, x4, x1, x2)

inst_10247:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x51b0b6 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x7f8000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e51b0b6; op2val:0x0;
op3val:0x7f8000; valaddr_reg:x3; val_offset:30741*0 + 3*263*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 30741*0 + 3*263*FLEN/8, x4, x1, x2)

inst_10248:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x51b0b6 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x7fc000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e51b0b6; op2val:0x0;
op3val:0x7fc000; valaddr_reg:x3; val_offset:30744*0 + 3*264*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 30744*0 + 3*264*FLEN/8, x4, x1, x2)

inst_10249:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x51b0b6 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x7fe000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e51b0b6; op2val:0x0;
op3val:0x7fe000; valaddr_reg:x3; val_offset:30747*0 + 3*265*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 30747*0 + 3*265*FLEN/8, x4, x1, x2)

inst_10250:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x51b0b6 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x7ff000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e51b0b6; op2val:0x0;
op3val:0x7ff000; valaddr_reg:x3; val_offset:30750*0 + 3*266*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 30750*0 + 3*266*FLEN/8, x4, x1, x2)

inst_10251:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x51b0b6 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x7ff800 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e51b0b6; op2val:0x0;
op3val:0x7ff800; valaddr_reg:x3; val_offset:30753*0 + 3*267*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 30753*0 + 3*267*FLEN/8, x4, x1, x2)

inst_10252:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x51b0b6 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x7ffc00 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e51b0b6; op2val:0x0;
op3val:0x7ffc00; valaddr_reg:x3; val_offset:30756*0 + 3*268*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 30756*0 + 3*268*FLEN/8, x4, x1, x2)

inst_10253:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x51b0b6 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x7ffe00 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e51b0b6; op2val:0x0;
op3val:0x7ffe00; valaddr_reg:x3; val_offset:30759*0 + 3*269*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 30759*0 + 3*269*FLEN/8, x4, x1, x2)

inst_10254:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x51b0b6 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x7fff00 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e51b0b6; op2val:0x0;
op3val:0x7fff00; valaddr_reg:x3; val_offset:30762*0 + 3*270*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 30762*0 + 3*270*FLEN/8, x4, x1, x2)

inst_10255:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x51b0b6 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x7fff80 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e51b0b6; op2val:0x0;
op3val:0x7fff80; valaddr_reg:x3; val_offset:30765*0 + 3*271*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 30765*0 + 3*271*FLEN/8, x4, x1, x2)

inst_10256:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x51b0b6 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x7fffc0 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e51b0b6; op2val:0x0;
op3val:0x7fffc0; valaddr_reg:x3; val_offset:30768*0 + 3*272*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 30768*0 + 3*272*FLEN/8, x4, x1, x2)

inst_10257:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x51b0b6 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x7fffe0 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e51b0b6; op2val:0x0;
op3val:0x7fffe0; valaddr_reg:x3; val_offset:30771*0 + 3*273*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 30771*0 + 3*273*FLEN/8, x4, x1, x2)

inst_10258:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x51b0b6 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x7ffff0 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e51b0b6; op2val:0x0;
op3val:0x7ffff0; valaddr_reg:x3; val_offset:30774*0 + 3*274*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 30774*0 + 3*274*FLEN/8, x4, x1, x2)

inst_10259:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x51b0b6 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x7ffff8 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e51b0b6; op2val:0x0;
op3val:0x7ffff8; valaddr_reg:x3; val_offset:30777*0 + 3*275*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 30777*0 + 3*275*FLEN/8, x4, x1, x2)

inst_10260:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x51b0b6 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x7ffffc and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e51b0b6; op2val:0x0;
op3val:0x7ffffc; valaddr_reg:x3; val_offset:30780*0 + 3*276*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 30780*0 + 3*276*FLEN/8, x4, x1, x2)

inst_10261:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x51b0b6 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x7ffffe and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e51b0b6; op2val:0x0;
op3val:0x7ffffe; valaddr_reg:x3; val_offset:30783*0 + 3*277*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 30783*0 + 3*277*FLEN/8, x4, x1, x2)

inst_10262:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x51b0b6 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x7fffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e51b0b6; op2val:0x0;
op3val:0x7fffff; valaddr_reg:x3; val_offset:30786*0 + 3*278*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 30786*0 + 3*278*FLEN/8, x4, x1, x2)

inst_10263:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x51b0b6 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000001 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e51b0b6; op2val:0x0;
op3val:0x800001; valaddr_reg:x3; val_offset:30789*0 + 3*279*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 30789*0 + 3*279*FLEN/8, x4, x1, x2)

inst_10264:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x51b0b6 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000003 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e51b0b6; op2val:0x0;
op3val:0x800003; valaddr_reg:x3; val_offset:30792*0 + 3*280*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 30792*0 + 3*280*FLEN/8, x4, x1, x2)

inst_10265:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x51b0b6 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000007 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e51b0b6; op2val:0x0;
op3val:0x800007; valaddr_reg:x3; val_offset:30795*0 + 3*281*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 30795*0 + 3*281*FLEN/8, x4, x1, x2)

inst_10266:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x51b0b6 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x199999 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e51b0b6; op2val:0x0;
op3val:0x999999; valaddr_reg:x3; val_offset:30798*0 + 3*282*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 30798*0 + 3*282*FLEN/8, x4, x1, x2)

inst_10267:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x51b0b6 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x249249 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e51b0b6; op2val:0x0;
op3val:0xa49249; valaddr_reg:x3; val_offset:30801*0 + 3*283*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 30801*0 + 3*283*FLEN/8, x4, x1, x2)

inst_10268:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x51b0b6 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x333333 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e51b0b6; op2val:0x0;
op3val:0xb33333; valaddr_reg:x3; val_offset:30804*0 + 3*284*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 30804*0 + 3*284*FLEN/8, x4, x1, x2)

inst_10269:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x51b0b6 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x36db6d and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e51b0b6; op2val:0x0;
op3val:0xb6db6d; valaddr_reg:x3; val_offset:30807*0 + 3*285*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 30807*0 + 3*285*FLEN/8, x4, x1, x2)

inst_10270:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x51b0b6 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x3bbbbb and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e51b0b6; op2val:0x0;
op3val:0xbbbbbb; valaddr_reg:x3; val_offset:30810*0 + 3*286*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 30810*0 + 3*286*FLEN/8, x4, x1, x2)

inst_10271:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x51b0b6 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x444444 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e51b0b6; op2val:0x0;
op3val:0xc44444; valaddr_reg:x3; val_offset:30813*0 + 3*287*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 30813*0 + 3*287*FLEN/8, x4, x1, x2)

inst_10272:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x51b0b6 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x4ccccc and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e51b0b6; op2val:0x0;
op3val:0xcccccc; valaddr_reg:x3; val_offset:30816*0 + 3*288*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 30816*0 + 3*288*FLEN/8, x4, x1, x2)

inst_10273:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x51b0b6 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x5b6db6 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e51b0b6; op2val:0x0;
op3val:0xdb6db6; valaddr_reg:x3; val_offset:30819*0 + 3*289*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 30819*0 + 3*289*FLEN/8, x4, x1, x2)

inst_10274:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x51b0b6 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x666666 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e51b0b6; op2val:0x0;
op3val:0xe66666; valaddr_reg:x3; val_offset:30822*0 + 3*290*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 30822*0 + 3*290*FLEN/8, x4, x1, x2)

inst_10275:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x51b0b6 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x6db6db and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e51b0b6; op2val:0x0;
op3val:0xedb6db; valaddr_reg:x3; val_offset:30825*0 + 3*291*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 30825*0 + 3*291*FLEN/8, x4, x1, x2)

inst_10276:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x51b0b6 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x7ffff8 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e51b0b6; op2val:0x0;
op3val:0xfffff8; valaddr_reg:x3; val_offset:30828*0 + 3*292*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 30828*0 + 3*292*FLEN/8, x4, x1, x2)

inst_10277:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x51b0b6 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x7ffffc and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e51b0b6; op2val:0x0;
op3val:0xfffffc; valaddr_reg:x3; val_offset:30831*0 + 3*293*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 30831*0 + 3*293*FLEN/8, x4, x1, x2)

inst_10278:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x51b0b6 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x7ffffe and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e51b0b6; op2val:0x0;
op3val:0xfffffe; valaddr_reg:x3; val_offset:30834*0 + 3*294*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 30834*0 + 3*294*FLEN/8, x4, x1, x2)

inst_10279:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x52bf26 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000001 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e52bf26; op2val:0x80000000;
op3val:0x80000001; valaddr_reg:x3; val_offset:30837*0 + 3*295*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 30837*0 + 3*295*FLEN/8, x4, x1, x2)

inst_10280:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x52bf26 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000003 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e52bf26; op2val:0x80000000;
op3val:0x80000003; valaddr_reg:x3; val_offset:30840*0 + 3*296*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 30840*0 + 3*296*FLEN/8, x4, x1, x2)

inst_10281:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x52bf26 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000007 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e52bf26; op2val:0x80000000;
op3val:0x80000007; valaddr_reg:x3; val_offset:30843*0 + 3*297*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 30843*0 + 3*297*FLEN/8, x4, x1, x2)

inst_10282:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x52bf26 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x199999 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e52bf26; op2val:0x80000000;
op3val:0x80199999; valaddr_reg:x3; val_offset:30846*0 + 3*298*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 30846*0 + 3*298*FLEN/8, x4, x1, x2)

inst_10283:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x52bf26 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x249249 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e52bf26; op2val:0x80000000;
op3val:0x80249249; valaddr_reg:x3; val_offset:30849*0 + 3*299*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 30849*0 + 3*299*FLEN/8, x4, x1, x2)

inst_10284:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x52bf26 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x333333 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e52bf26; op2val:0x80000000;
op3val:0x80333333; valaddr_reg:x3; val_offset:30852*0 + 3*300*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 30852*0 + 3*300*FLEN/8, x4, x1, x2)

inst_10285:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x52bf26 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x36db6d and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e52bf26; op2val:0x80000000;
op3val:0x8036db6d; valaddr_reg:x3; val_offset:30855*0 + 3*301*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 30855*0 + 3*301*FLEN/8, x4, x1, x2)

inst_10286:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x52bf26 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3bbbbb and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e52bf26; op2val:0x80000000;
op3val:0x803bbbbb; valaddr_reg:x3; val_offset:30858*0 + 3*302*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 30858*0 + 3*302*FLEN/8, x4, x1, x2)

inst_10287:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x52bf26 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x444444 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e52bf26; op2val:0x80000000;
op3val:0x80444444; valaddr_reg:x3; val_offset:30861*0 + 3*303*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 30861*0 + 3*303*FLEN/8, x4, x1, x2)

inst_10288:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x52bf26 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x4ccccc and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e52bf26; op2val:0x80000000;
op3val:0x804ccccc; valaddr_reg:x3; val_offset:30864*0 + 3*304*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 30864*0 + 3*304*FLEN/8, x4, x1, x2)

inst_10289:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x52bf26 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x5b6db6 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e52bf26; op2val:0x80000000;
op3val:0x805b6db6; valaddr_reg:x3; val_offset:30867*0 + 3*305*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 30867*0 + 3*305*FLEN/8, x4, x1, x2)

inst_10290:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x52bf26 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x666666 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e52bf26; op2val:0x80000000;
op3val:0x80666666; valaddr_reg:x3; val_offset:30870*0 + 3*306*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 30870*0 + 3*306*FLEN/8, x4, x1, x2)

inst_10291:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x52bf26 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x6db6db and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e52bf26; op2val:0x80000000;
op3val:0x806db6db; valaddr_reg:x3; val_offset:30873*0 + 3*307*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 30873*0 + 3*307*FLEN/8, x4, x1, x2)

inst_10292:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x52bf26 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7ffff8 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e52bf26; op2val:0x80000000;
op3val:0x807ffff8; valaddr_reg:x3; val_offset:30876*0 + 3*308*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 30876*0 + 3*308*FLEN/8, x4, x1, x2)

inst_10293:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x52bf26 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7ffffc and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e52bf26; op2val:0x80000000;
op3val:0x807ffffc; valaddr_reg:x3; val_offset:30879*0 + 3*309*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 30879*0 + 3*309*FLEN/8, x4, x1, x2)

inst_10294:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x52bf26 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7ffffe and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e52bf26; op2val:0x80000000;
op3val:0x807ffffe; valaddr_reg:x3; val_offset:30882*0 + 3*310*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 30882*0 + 3*310*FLEN/8, x4, x1, x2)

inst_10295:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x52bf26 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x14 and fm3 == 0x000000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e52bf26; op2val:0x80000000;
op3val:0x8a000000; valaddr_reg:x3; val_offset:30885*0 + 3*311*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 30885*0 + 3*311*FLEN/8, x4, x1, x2)

inst_10296:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x52bf26 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x14 and fm3 == 0x000001 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e52bf26; op2val:0x80000000;
op3val:0x8a000001; valaddr_reg:x3; val_offset:30888*0 + 3*312*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 30888*0 + 3*312*FLEN/8, x4, x1, x2)

inst_10297:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x52bf26 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x14 and fm3 == 0x000003 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e52bf26; op2val:0x80000000;
op3val:0x8a000003; valaddr_reg:x3; val_offset:30891*0 + 3*313*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 30891*0 + 3*313*FLEN/8, x4, x1, x2)

inst_10298:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x52bf26 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x14 and fm3 == 0x000007 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e52bf26; op2val:0x80000000;
op3val:0x8a000007; valaddr_reg:x3; val_offset:30894*0 + 3*314*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 30894*0 + 3*314*FLEN/8, x4, x1, x2)

inst_10299:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x52bf26 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x14 and fm3 == 0x00000f and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e52bf26; op2val:0x80000000;
op3val:0x8a00000f; valaddr_reg:x3; val_offset:30897*0 + 3*315*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 30897*0 + 3*315*FLEN/8, x4, x1, x2)

inst_10300:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x52bf26 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x14 and fm3 == 0x00001f and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e52bf26; op2val:0x80000000;
op3val:0x8a00001f; valaddr_reg:x3; val_offset:30900*0 + 3*316*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 30900*0 + 3*316*FLEN/8, x4, x1, x2)

inst_10301:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x52bf26 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x14 and fm3 == 0x00003f and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e52bf26; op2val:0x80000000;
op3val:0x8a00003f; valaddr_reg:x3; val_offset:30903*0 + 3*317*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 30903*0 + 3*317*FLEN/8, x4, x1, x2)

inst_10302:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x52bf26 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x14 and fm3 == 0x00007f and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e52bf26; op2val:0x80000000;
op3val:0x8a00007f; valaddr_reg:x3; val_offset:30906*0 + 3*318*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 30906*0 + 3*318*FLEN/8, x4, x1, x2)

inst_10303:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x52bf26 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x14 and fm3 == 0x0000ff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e52bf26; op2val:0x80000000;
op3val:0x8a0000ff; valaddr_reg:x3; val_offset:30909*0 + 3*319*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 30909*0 + 3*319*FLEN/8, x4, x1, x2)

inst_10304:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x52bf26 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x14 and fm3 == 0x0001ff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e52bf26; op2val:0x80000000;
op3val:0x8a0001ff; valaddr_reg:x3; val_offset:30912*0 + 3*320*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 30912*0 + 3*320*FLEN/8, x4, x1, x2)

inst_10305:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x52bf26 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x14 and fm3 == 0x0003ff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e52bf26; op2val:0x80000000;
op3val:0x8a0003ff; valaddr_reg:x3; val_offset:30915*0 + 3*321*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 30915*0 + 3*321*FLEN/8, x4, x1, x2)

inst_10306:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x52bf26 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x14 and fm3 == 0x0007ff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e52bf26; op2val:0x80000000;
op3val:0x8a0007ff; valaddr_reg:x3; val_offset:30918*0 + 3*322*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 30918*0 + 3*322*FLEN/8, x4, x1, x2)

inst_10307:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x52bf26 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x14 and fm3 == 0x000fff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e52bf26; op2val:0x80000000;
op3val:0x8a000fff; valaddr_reg:x3; val_offset:30921*0 + 3*323*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 30921*0 + 3*323*FLEN/8, x4, x1, x2)

inst_10308:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x52bf26 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x14 and fm3 == 0x001fff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e52bf26; op2val:0x80000000;
op3val:0x8a001fff; valaddr_reg:x3; val_offset:30924*0 + 3*324*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 30924*0 + 3*324*FLEN/8, x4, x1, x2)

inst_10309:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x52bf26 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x14 and fm3 == 0x003fff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e52bf26; op2val:0x80000000;
op3val:0x8a003fff; valaddr_reg:x3; val_offset:30927*0 + 3*325*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 30927*0 + 3*325*FLEN/8, x4, x1, x2)

inst_10310:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x52bf26 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x14 and fm3 == 0x007fff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e52bf26; op2val:0x80000000;
op3val:0x8a007fff; valaddr_reg:x3; val_offset:30930*0 + 3*326*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 30930*0 + 3*326*FLEN/8, x4, x1, x2)

inst_10311:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x52bf26 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x14 and fm3 == 0x00ffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e52bf26; op2val:0x80000000;
op3val:0x8a00ffff; valaddr_reg:x3; val_offset:30933*0 + 3*327*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 30933*0 + 3*327*FLEN/8, x4, x1, x2)

inst_10312:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x52bf26 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x14 and fm3 == 0x01ffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e52bf26; op2val:0x80000000;
op3val:0x8a01ffff; valaddr_reg:x3; val_offset:30936*0 + 3*328*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 30936*0 + 3*328*FLEN/8, x4, x1, x2)

inst_10313:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x52bf26 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x14 and fm3 == 0x03ffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e52bf26; op2val:0x80000000;
op3val:0x8a03ffff; valaddr_reg:x3; val_offset:30939*0 + 3*329*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 30939*0 + 3*329*FLEN/8, x4, x1, x2)

inst_10314:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x52bf26 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x14 and fm3 == 0x07ffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e52bf26; op2val:0x80000000;
op3val:0x8a07ffff; valaddr_reg:x3; val_offset:30942*0 + 3*330*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 30942*0 + 3*330*FLEN/8, x4, x1, x2)

inst_10315:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x52bf26 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x14 and fm3 == 0x0fffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e52bf26; op2val:0x80000000;
op3val:0x8a0fffff; valaddr_reg:x3; val_offset:30945*0 + 3*331*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 30945*0 + 3*331*FLEN/8, x4, x1, x2)

inst_10316:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x52bf26 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x14 and fm3 == 0x1fffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e52bf26; op2val:0x80000000;
op3val:0x8a1fffff; valaddr_reg:x3; val_offset:30948*0 + 3*332*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 30948*0 + 3*332*FLEN/8, x4, x1, x2)

inst_10317:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x52bf26 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x14 and fm3 == 0x3fffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e52bf26; op2val:0x80000000;
op3val:0x8a3fffff; valaddr_reg:x3; val_offset:30951*0 + 3*333*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 30951*0 + 3*333*FLEN/8, x4, x1, x2)

inst_10318:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x52bf26 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x14 and fm3 == 0x400000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e52bf26; op2val:0x80000000;
op3val:0x8a400000; valaddr_reg:x3; val_offset:30954*0 + 3*334*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 30954*0 + 3*334*FLEN/8, x4, x1, x2)

inst_10319:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x52bf26 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x14 and fm3 == 0x600000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e52bf26; op2val:0x80000000;
op3val:0x8a600000; valaddr_reg:x3; val_offset:30957*0 + 3*335*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 30957*0 + 3*335*FLEN/8, x4, x1, x2)

inst_10320:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x52bf26 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x14 and fm3 == 0x700000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e52bf26; op2val:0x80000000;
op3val:0x8a700000; valaddr_reg:x3; val_offset:30960*0 + 3*336*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 30960*0 + 3*336*FLEN/8, x4, x1, x2)

inst_10321:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x52bf26 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x14 and fm3 == 0x780000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e52bf26; op2val:0x80000000;
op3val:0x8a780000; valaddr_reg:x3; val_offset:30963*0 + 3*337*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 30963*0 + 3*337*FLEN/8, x4, x1, x2)

inst_10322:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x52bf26 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x14 and fm3 == 0x7c0000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e52bf26; op2val:0x80000000;
op3val:0x8a7c0000; valaddr_reg:x3; val_offset:30966*0 + 3*338*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 30966*0 + 3*338*FLEN/8, x4, x1, x2)

inst_10323:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x52bf26 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x14 and fm3 == 0x7e0000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e52bf26; op2val:0x80000000;
op3val:0x8a7e0000; valaddr_reg:x3; val_offset:30969*0 + 3*339*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 30969*0 + 3*339*FLEN/8, x4, x1, x2)

inst_10324:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x52bf26 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x14 and fm3 == 0x7f0000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e52bf26; op2val:0x80000000;
op3val:0x8a7f0000; valaddr_reg:x3; val_offset:30972*0 + 3*340*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 30972*0 + 3*340*FLEN/8, x4, x1, x2)

inst_10325:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x52bf26 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x14 and fm3 == 0x7f8000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e52bf26; op2val:0x80000000;
op3val:0x8a7f8000; valaddr_reg:x3; val_offset:30975*0 + 3*341*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 30975*0 + 3*341*FLEN/8, x4, x1, x2)

inst_10326:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x52bf26 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x14 and fm3 == 0x7fc000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e52bf26; op2val:0x80000000;
op3val:0x8a7fc000; valaddr_reg:x3; val_offset:30978*0 + 3*342*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 30978*0 + 3*342*FLEN/8, x4, x1, x2)

inst_10327:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x52bf26 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x14 and fm3 == 0x7fe000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e52bf26; op2val:0x80000000;
op3val:0x8a7fe000; valaddr_reg:x3; val_offset:30981*0 + 3*343*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 30981*0 + 3*343*FLEN/8, x4, x1, x2)

inst_10328:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x52bf26 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x14 and fm3 == 0x7ff000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e52bf26; op2val:0x80000000;
op3val:0x8a7ff000; valaddr_reg:x3; val_offset:30984*0 + 3*344*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 30984*0 + 3*344*FLEN/8, x4, x1, x2)

inst_10329:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x52bf26 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x14 and fm3 == 0x7ff800 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e52bf26; op2val:0x80000000;
op3val:0x8a7ff800; valaddr_reg:x3; val_offset:30987*0 + 3*345*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 30987*0 + 3*345*FLEN/8, x4, x1, x2)

inst_10330:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x52bf26 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x14 and fm3 == 0x7ffc00 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e52bf26; op2val:0x80000000;
op3val:0x8a7ffc00; valaddr_reg:x3; val_offset:30990*0 + 3*346*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 30990*0 + 3*346*FLEN/8, x4, x1, x2)

inst_10331:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x52bf26 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x14 and fm3 == 0x7ffe00 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e52bf26; op2val:0x80000000;
op3val:0x8a7ffe00; valaddr_reg:x3; val_offset:30993*0 + 3*347*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 30993*0 + 3*347*FLEN/8, x4, x1, x2)

inst_10332:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x52bf26 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x14 and fm3 == 0x7fff00 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e52bf26; op2val:0x80000000;
op3val:0x8a7fff00; valaddr_reg:x3; val_offset:30996*0 + 3*348*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 30996*0 + 3*348*FLEN/8, x4, x1, x2)

inst_10333:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x52bf26 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x14 and fm3 == 0x7fff80 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e52bf26; op2val:0x80000000;
op3val:0x8a7fff80; valaddr_reg:x3; val_offset:30999*0 + 3*349*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 30999*0 + 3*349*FLEN/8, x4, x1, x2)

inst_10334:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x52bf26 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x14 and fm3 == 0x7fffc0 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e52bf26; op2val:0x80000000;
op3val:0x8a7fffc0; valaddr_reg:x3; val_offset:31002*0 + 3*350*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 31002*0 + 3*350*FLEN/8, x4, x1, x2)

inst_10335:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x52bf26 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x14 and fm3 == 0x7fffe0 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e52bf26; op2val:0x80000000;
op3val:0x8a7fffe0; valaddr_reg:x3; val_offset:31005*0 + 3*351*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 31005*0 + 3*351*FLEN/8, x4, x1, x2)

inst_10336:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x52bf26 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x14 and fm3 == 0x7ffff0 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e52bf26; op2val:0x80000000;
op3val:0x8a7ffff0; valaddr_reg:x3; val_offset:31008*0 + 3*352*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 31008*0 + 3*352*FLEN/8, x4, x1, x2)

inst_10337:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x52bf26 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x14 and fm3 == 0x7ffff8 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e52bf26; op2val:0x80000000;
op3val:0x8a7ffff8; valaddr_reg:x3; val_offset:31011*0 + 3*353*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 31011*0 + 3*353*FLEN/8, x4, x1, x2)

inst_10338:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x52bf26 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x14 and fm3 == 0x7ffffc and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e52bf26; op2val:0x80000000;
op3val:0x8a7ffffc; valaddr_reg:x3; val_offset:31014*0 + 3*354*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 31014*0 + 3*354*FLEN/8, x4, x1, x2)

inst_10339:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x52bf26 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x14 and fm3 == 0x7ffffe and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e52bf26; op2val:0x80000000;
op3val:0x8a7ffffe; valaddr_reg:x3; val_offset:31017*0 + 3*355*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 31017*0 + 3*355*FLEN/8, x4, x1, x2)

inst_10340:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x52bf26 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x14 and fm3 == 0x7fffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e52bf26; op2val:0x80000000;
op3val:0x8a7fffff; valaddr_reg:x3; val_offset:31020*0 + 3*356*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 31020*0 + 3*356*FLEN/8, x4, x1, x2)

inst_10341:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x551c11 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000001 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e551c11; op2val:0x80000000;
op3val:0x80000001; valaddr_reg:x3; val_offset:31023*0 + 3*357*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 31023*0 + 3*357*FLEN/8, x4, x1, x2)

inst_10342:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x551c11 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000003 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e551c11; op2val:0x80000000;
op3val:0x80000003; valaddr_reg:x3; val_offset:31026*0 + 3*358*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 31026*0 + 3*358*FLEN/8, x4, x1, x2)

inst_10343:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x551c11 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000007 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e551c11; op2val:0x80000000;
op3val:0x80000007; valaddr_reg:x3; val_offset:31029*0 + 3*359*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 31029*0 + 3*359*FLEN/8, x4, x1, x2)

inst_10344:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x551c11 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x199999 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e551c11; op2val:0x80000000;
op3val:0x80199999; valaddr_reg:x3; val_offset:31032*0 + 3*360*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 31032*0 + 3*360*FLEN/8, x4, x1, x2)

inst_10345:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x551c11 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x249249 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e551c11; op2val:0x80000000;
op3val:0x80249249; valaddr_reg:x3; val_offset:31035*0 + 3*361*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 31035*0 + 3*361*FLEN/8, x4, x1, x2)

inst_10346:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x551c11 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x333333 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e551c11; op2val:0x80000000;
op3val:0x80333333; valaddr_reg:x3; val_offset:31038*0 + 3*362*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 31038*0 + 3*362*FLEN/8, x4, x1, x2)

inst_10347:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x551c11 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x36db6d and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e551c11; op2val:0x80000000;
op3val:0x8036db6d; valaddr_reg:x3; val_offset:31041*0 + 3*363*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 31041*0 + 3*363*FLEN/8, x4, x1, x2)

inst_10348:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x551c11 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3bbbbb and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e551c11; op2val:0x80000000;
op3val:0x803bbbbb; valaddr_reg:x3; val_offset:31044*0 + 3*364*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 31044*0 + 3*364*FLEN/8, x4, x1, x2)

inst_10349:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x551c11 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x444444 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e551c11; op2val:0x80000000;
op3val:0x80444444; valaddr_reg:x3; val_offset:31047*0 + 3*365*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 31047*0 + 3*365*FLEN/8, x4, x1, x2)

inst_10350:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x551c11 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x4ccccc and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e551c11; op2val:0x80000000;
op3val:0x804ccccc; valaddr_reg:x3; val_offset:31050*0 + 3*366*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 31050*0 + 3*366*FLEN/8, x4, x1, x2)

inst_10351:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x551c11 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x5b6db6 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e551c11; op2val:0x80000000;
op3val:0x805b6db6; valaddr_reg:x3; val_offset:31053*0 + 3*367*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 31053*0 + 3*367*FLEN/8, x4, x1, x2)

inst_10352:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x551c11 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x666666 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e551c11; op2val:0x80000000;
op3val:0x80666666; valaddr_reg:x3; val_offset:31056*0 + 3*368*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 31056*0 + 3*368*FLEN/8, x4, x1, x2)

inst_10353:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x551c11 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x6db6db and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e551c11; op2val:0x80000000;
op3val:0x806db6db; valaddr_reg:x3; val_offset:31059*0 + 3*369*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 31059*0 + 3*369*FLEN/8, x4, x1, x2)

inst_10354:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x551c11 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7ffff8 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e551c11; op2val:0x80000000;
op3val:0x807ffff8; valaddr_reg:x3; val_offset:31062*0 + 3*370*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 31062*0 + 3*370*FLEN/8, x4, x1, x2)

inst_10355:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x551c11 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7ffffc and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e551c11; op2val:0x80000000;
op3val:0x807ffffc; valaddr_reg:x3; val_offset:31065*0 + 3*371*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 31065*0 + 3*371*FLEN/8, x4, x1, x2)

inst_10356:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x551c11 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7ffffe and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e551c11; op2val:0x80000000;
op3val:0x807ffffe; valaddr_reg:x3; val_offset:31068*0 + 3*372*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 31068*0 + 3*372*FLEN/8, x4, x1, x2)

inst_10357:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x551c11 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x13 and fm3 == 0x000000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e551c11; op2val:0x80000000;
op3val:0x89800000; valaddr_reg:x3; val_offset:31071*0 + 3*373*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 31071*0 + 3*373*FLEN/8, x4, x1, x2)

inst_10358:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x551c11 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x13 and fm3 == 0x000001 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e551c11; op2val:0x80000000;
op3val:0x89800001; valaddr_reg:x3; val_offset:31074*0 + 3*374*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 31074*0 + 3*374*FLEN/8, x4, x1, x2)

inst_10359:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x551c11 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x13 and fm3 == 0x000003 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e551c11; op2val:0x80000000;
op3val:0x89800003; valaddr_reg:x3; val_offset:31077*0 + 3*375*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 31077*0 + 3*375*FLEN/8, x4, x1, x2)

inst_10360:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x551c11 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x13 and fm3 == 0x000007 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e551c11; op2val:0x80000000;
op3val:0x89800007; valaddr_reg:x3; val_offset:31080*0 + 3*376*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 31080*0 + 3*376*FLEN/8, x4, x1, x2)

inst_10361:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x551c11 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x13 and fm3 == 0x00000f and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e551c11; op2val:0x80000000;
op3val:0x8980000f; valaddr_reg:x3; val_offset:31083*0 + 3*377*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 31083*0 + 3*377*FLEN/8, x4, x1, x2)

inst_10362:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x551c11 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x13 and fm3 == 0x00001f and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e551c11; op2val:0x80000000;
op3val:0x8980001f; valaddr_reg:x3; val_offset:31086*0 + 3*378*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 31086*0 + 3*378*FLEN/8, x4, x1, x2)

inst_10363:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x551c11 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x13 and fm3 == 0x00003f and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e551c11; op2val:0x80000000;
op3val:0x8980003f; valaddr_reg:x3; val_offset:31089*0 + 3*379*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 31089*0 + 3*379*FLEN/8, x4, x1, x2)

inst_10364:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x551c11 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x13 and fm3 == 0x00007f and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e551c11; op2val:0x80000000;
op3val:0x8980007f; valaddr_reg:x3; val_offset:31092*0 + 3*380*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 31092*0 + 3*380*FLEN/8, x4, x1, x2)

inst_10365:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x551c11 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x13 and fm3 == 0x0000ff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e551c11; op2val:0x80000000;
op3val:0x898000ff; valaddr_reg:x3; val_offset:31095*0 + 3*381*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 31095*0 + 3*381*FLEN/8, x4, x1, x2)

inst_10366:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x551c11 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x13 and fm3 == 0x0001ff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e551c11; op2val:0x80000000;
op3val:0x898001ff; valaddr_reg:x3; val_offset:31098*0 + 3*382*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 31098*0 + 3*382*FLEN/8, x4, x1, x2)

inst_10367:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x551c11 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x13 and fm3 == 0x0003ff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e551c11; op2val:0x80000000;
op3val:0x898003ff; valaddr_reg:x3; val_offset:31101*0 + 3*383*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 31101*0 + 3*383*FLEN/8, x4, x1, x2)
RVTEST_SIGBASE(x1,signature_x1_4)

inst_10368:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x551c11 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x13 and fm3 == 0x0007ff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e551c11; op2val:0x80000000;
op3val:0x898007ff; valaddr_reg:x3; val_offset:31104*0 + 3*384*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 31104*0 + 3*384*FLEN/8, x4, x1, x2)

inst_10369:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x551c11 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x13 and fm3 == 0x000fff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e551c11; op2val:0x80000000;
op3val:0x89800fff; valaddr_reg:x3; val_offset:31107*0 + 3*385*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 31107*0 + 3*385*FLEN/8, x4, x1, x2)

inst_10370:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x551c11 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x13 and fm3 == 0x001fff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e551c11; op2val:0x80000000;
op3val:0x89801fff; valaddr_reg:x3; val_offset:31110*0 + 3*386*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 31110*0 + 3*386*FLEN/8, x4, x1, x2)

inst_10371:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x551c11 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x13 and fm3 == 0x003fff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e551c11; op2val:0x80000000;
op3val:0x89803fff; valaddr_reg:x3; val_offset:31113*0 + 3*387*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 31113*0 + 3*387*FLEN/8, x4, x1, x2)

inst_10372:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x551c11 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x13 and fm3 == 0x007fff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e551c11; op2val:0x80000000;
op3val:0x89807fff; valaddr_reg:x3; val_offset:31116*0 + 3*388*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 31116*0 + 3*388*FLEN/8, x4, x1, x2)

inst_10373:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x551c11 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x13 and fm3 == 0x00ffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e551c11; op2val:0x80000000;
op3val:0x8980ffff; valaddr_reg:x3; val_offset:31119*0 + 3*389*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 31119*0 + 3*389*FLEN/8, x4, x1, x2)

inst_10374:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x551c11 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x13 and fm3 == 0x01ffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e551c11; op2val:0x80000000;
op3val:0x8981ffff; valaddr_reg:x3; val_offset:31122*0 + 3*390*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 31122*0 + 3*390*FLEN/8, x4, x1, x2)

inst_10375:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x551c11 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x13 and fm3 == 0x03ffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e551c11; op2val:0x80000000;
op3val:0x8983ffff; valaddr_reg:x3; val_offset:31125*0 + 3*391*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 31125*0 + 3*391*FLEN/8, x4, x1, x2)

inst_10376:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x551c11 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x13 and fm3 == 0x07ffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e551c11; op2val:0x80000000;
op3val:0x8987ffff; valaddr_reg:x3; val_offset:31128*0 + 3*392*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 31128*0 + 3*392*FLEN/8, x4, x1, x2)

inst_10377:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x551c11 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x13 and fm3 == 0x0fffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e551c11; op2val:0x80000000;
op3val:0x898fffff; valaddr_reg:x3; val_offset:31131*0 + 3*393*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 31131*0 + 3*393*FLEN/8, x4, x1, x2)

inst_10378:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x551c11 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x13 and fm3 == 0x1fffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e551c11; op2val:0x80000000;
op3val:0x899fffff; valaddr_reg:x3; val_offset:31134*0 + 3*394*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 31134*0 + 3*394*FLEN/8, x4, x1, x2)

inst_10379:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x551c11 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x13 and fm3 == 0x3fffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e551c11; op2val:0x80000000;
op3val:0x89bfffff; valaddr_reg:x3; val_offset:31137*0 + 3*395*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 31137*0 + 3*395*FLEN/8, x4, x1, x2)

inst_10380:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x551c11 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x13 and fm3 == 0x400000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e551c11; op2val:0x80000000;
op3val:0x89c00000; valaddr_reg:x3; val_offset:31140*0 + 3*396*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 31140*0 + 3*396*FLEN/8, x4, x1, x2)

inst_10381:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x551c11 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x13 and fm3 == 0x600000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e551c11; op2val:0x80000000;
op3val:0x89e00000; valaddr_reg:x3; val_offset:31143*0 + 3*397*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 31143*0 + 3*397*FLEN/8, x4, x1, x2)

inst_10382:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x551c11 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x13 and fm3 == 0x700000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e551c11; op2val:0x80000000;
op3val:0x89f00000; valaddr_reg:x3; val_offset:31146*0 + 3*398*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 31146*0 + 3*398*FLEN/8, x4, x1, x2)

inst_10383:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x551c11 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x13 and fm3 == 0x780000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e551c11; op2val:0x80000000;
op3val:0x89f80000; valaddr_reg:x3; val_offset:31149*0 + 3*399*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 31149*0 + 3*399*FLEN/8, x4, x1, x2)

inst_10384:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x551c11 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x13 and fm3 == 0x7c0000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e551c11; op2val:0x80000000;
op3val:0x89fc0000; valaddr_reg:x3; val_offset:31152*0 + 3*400*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 31152*0 + 3*400*FLEN/8, x4, x1, x2)

inst_10385:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x551c11 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x13 and fm3 == 0x7e0000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e551c11; op2val:0x80000000;
op3val:0x89fe0000; valaddr_reg:x3; val_offset:31155*0 + 3*401*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 31155*0 + 3*401*FLEN/8, x4, x1, x2)

inst_10386:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x551c11 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x13 and fm3 == 0x7f0000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e551c11; op2val:0x80000000;
op3val:0x89ff0000; valaddr_reg:x3; val_offset:31158*0 + 3*402*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 31158*0 + 3*402*FLEN/8, x4, x1, x2)

inst_10387:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x551c11 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x13 and fm3 == 0x7f8000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e551c11; op2val:0x80000000;
op3val:0x89ff8000; valaddr_reg:x3; val_offset:31161*0 + 3*403*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 31161*0 + 3*403*FLEN/8, x4, x1, x2)

inst_10388:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x551c11 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x13 and fm3 == 0x7fc000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e551c11; op2val:0x80000000;
op3val:0x89ffc000; valaddr_reg:x3; val_offset:31164*0 + 3*404*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 31164*0 + 3*404*FLEN/8, x4, x1, x2)

inst_10389:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x551c11 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x13 and fm3 == 0x7fe000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e551c11; op2val:0x80000000;
op3val:0x89ffe000; valaddr_reg:x3; val_offset:31167*0 + 3*405*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 31167*0 + 3*405*FLEN/8, x4, x1, x2)

inst_10390:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x551c11 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x13 and fm3 == 0x7ff000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e551c11; op2val:0x80000000;
op3val:0x89fff000; valaddr_reg:x3; val_offset:31170*0 + 3*406*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 31170*0 + 3*406*FLEN/8, x4, x1, x2)

inst_10391:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x551c11 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x13 and fm3 == 0x7ff800 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e551c11; op2val:0x80000000;
op3val:0x89fff800; valaddr_reg:x3; val_offset:31173*0 + 3*407*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 31173*0 + 3*407*FLEN/8, x4, x1, x2)

inst_10392:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x551c11 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x13 and fm3 == 0x7ffc00 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e551c11; op2val:0x80000000;
op3val:0x89fffc00; valaddr_reg:x3; val_offset:31176*0 + 3*408*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 31176*0 + 3*408*FLEN/8, x4, x1, x2)

inst_10393:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x551c11 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x13 and fm3 == 0x7ffe00 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e551c11; op2val:0x80000000;
op3val:0x89fffe00; valaddr_reg:x3; val_offset:31179*0 + 3*409*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 31179*0 + 3*409*FLEN/8, x4, x1, x2)

inst_10394:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x551c11 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x13 and fm3 == 0x7fff00 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e551c11; op2val:0x80000000;
op3val:0x89ffff00; valaddr_reg:x3; val_offset:31182*0 + 3*410*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 31182*0 + 3*410*FLEN/8, x4, x1, x2)

inst_10395:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x551c11 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x13 and fm3 == 0x7fff80 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e551c11; op2val:0x80000000;
op3val:0x89ffff80; valaddr_reg:x3; val_offset:31185*0 + 3*411*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 31185*0 + 3*411*FLEN/8, x4, x1, x2)

inst_10396:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x551c11 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x13 and fm3 == 0x7fffc0 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e551c11; op2val:0x80000000;
op3val:0x89ffffc0; valaddr_reg:x3; val_offset:31188*0 + 3*412*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 31188*0 + 3*412*FLEN/8, x4, x1, x2)

inst_10397:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x551c11 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x13 and fm3 == 0x7fffe0 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e551c11; op2val:0x80000000;
op3val:0x89ffffe0; valaddr_reg:x3; val_offset:31191*0 + 3*413*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 31191*0 + 3*413*FLEN/8, x4, x1, x2)

inst_10398:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x551c11 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x13 and fm3 == 0x7ffff0 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e551c11; op2val:0x80000000;
op3val:0x89fffff0; valaddr_reg:x3; val_offset:31194*0 + 3*414*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 31194*0 + 3*414*FLEN/8, x4, x1, x2)

inst_10399:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x551c11 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x13 and fm3 == 0x7ffff8 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e551c11; op2val:0x80000000;
op3val:0x89fffff8; valaddr_reg:x3; val_offset:31197*0 + 3*415*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 31197*0 + 3*415*FLEN/8, x4, x1, x2)

inst_10400:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x551c11 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x13 and fm3 == 0x7ffffc and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e551c11; op2val:0x80000000;
op3val:0x89fffffc; valaddr_reg:x3; val_offset:31200*0 + 3*416*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 31200*0 + 3*416*FLEN/8, x4, x1, x2)

inst_10401:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x551c11 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x13 and fm3 == 0x7ffffe and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e551c11; op2val:0x80000000;
op3val:0x89fffffe; valaddr_reg:x3; val_offset:31203*0 + 3*417*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 31203*0 + 3*417*FLEN/8, x4, x1, x2)

inst_10402:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x551c11 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x13 and fm3 == 0x7fffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e551c11; op2val:0x80000000;
op3val:0x89ffffff; valaddr_reg:x3; val_offset:31206*0 + 3*418*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 31206*0 + 3*418*FLEN/8, x4, x1, x2)

inst_10403:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x5611f2 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x191243 and fs3 == 0 and fe3 == 0x7f and fm3 == 0x000001 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e5611f2; op2val:0x991243;
op3val:0x3f800001; valaddr_reg:x3; val_offset:31209*0 + 3*419*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 31209*0 + 3*419*FLEN/8, x4, x1, x2)

inst_10404:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x5611f2 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x191243 and fs3 == 0 and fe3 == 0x7f and fm3 == 0x000003 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e5611f2; op2val:0x991243;
op3val:0x3f800003; valaddr_reg:x3; val_offset:31212*0 + 3*420*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 31212*0 + 3*420*FLEN/8, x4, x1, x2)

inst_10405:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x5611f2 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x191243 and fs3 == 0 and fe3 == 0x7f and fm3 == 0x000007 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e5611f2; op2val:0x991243;
op3val:0x3f800007; valaddr_reg:x3; val_offset:31215*0 + 3*421*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 31215*0 + 3*421*FLEN/8, x4, x1, x2)

inst_10406:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x5611f2 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x191243 and fs3 == 0 and fe3 == 0x7f and fm3 == 0x199999 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e5611f2; op2val:0x991243;
op3val:0x3f999999; valaddr_reg:x3; val_offset:31218*0 + 3*422*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 31218*0 + 3*422*FLEN/8, x4, x1, x2)

inst_10407:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x5611f2 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x191243 and fs3 == 0 and fe3 == 0x7f and fm3 == 0x249249 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e5611f2; op2val:0x991243;
op3val:0x3fa49249; valaddr_reg:x3; val_offset:31221*0 + 3*423*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 31221*0 + 3*423*FLEN/8, x4, x1, x2)

inst_10408:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x5611f2 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x191243 and fs3 == 0 and fe3 == 0x7f and fm3 == 0x333333 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e5611f2; op2val:0x991243;
op3val:0x3fb33333; valaddr_reg:x3; val_offset:31224*0 + 3*424*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 31224*0 + 3*424*FLEN/8, x4, x1, x2)

inst_10409:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x5611f2 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x191243 and fs3 == 0 and fe3 == 0x7f and fm3 == 0x36db6d and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e5611f2; op2val:0x991243;
op3val:0x3fb6db6d; valaddr_reg:x3; val_offset:31227*0 + 3*425*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 31227*0 + 3*425*FLEN/8, x4, x1, x2)

inst_10410:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x5611f2 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x191243 and fs3 == 0 and fe3 == 0x7f and fm3 == 0x3bbbbb and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e5611f2; op2val:0x991243;
op3val:0x3fbbbbbb; valaddr_reg:x3; val_offset:31230*0 + 3*426*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 31230*0 + 3*426*FLEN/8, x4, x1, x2)

inst_10411:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x5611f2 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x191243 and fs3 == 0 and fe3 == 0x7f and fm3 == 0x444444 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e5611f2; op2val:0x991243;
op3val:0x3fc44444; valaddr_reg:x3; val_offset:31233*0 + 3*427*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 31233*0 + 3*427*FLEN/8, x4, x1, x2)

inst_10412:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x5611f2 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x191243 and fs3 == 0 and fe3 == 0x7f and fm3 == 0x4ccccc and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e5611f2; op2val:0x991243;
op3val:0x3fcccccc; valaddr_reg:x3; val_offset:31236*0 + 3*428*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 31236*0 + 3*428*FLEN/8, x4, x1, x2)

inst_10413:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x5611f2 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x191243 and fs3 == 0 and fe3 == 0x7f and fm3 == 0x5b6db6 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e5611f2; op2val:0x991243;
op3val:0x3fdb6db6; valaddr_reg:x3; val_offset:31239*0 + 3*429*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 31239*0 + 3*429*FLEN/8, x4, x1, x2)

inst_10414:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x5611f2 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x191243 and fs3 == 0 and fe3 == 0x7f and fm3 == 0x666666 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e5611f2; op2val:0x991243;
op3val:0x3fe66666; valaddr_reg:x3; val_offset:31242*0 + 3*430*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 31242*0 + 3*430*FLEN/8, x4, x1, x2)

inst_10415:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x5611f2 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x191243 and fs3 == 0 and fe3 == 0x7f and fm3 == 0x6db6db and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e5611f2; op2val:0x991243;
op3val:0x3fedb6db; valaddr_reg:x3; val_offset:31245*0 + 3*431*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 31245*0 + 3*431*FLEN/8, x4, x1, x2)

inst_10416:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x5611f2 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x191243 and fs3 == 0 and fe3 == 0x7f and fm3 == 0x7ffff8 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e5611f2; op2val:0x991243;
op3val:0x3ffffff8; valaddr_reg:x3; val_offset:31248*0 + 3*432*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 31248*0 + 3*432*FLEN/8, x4, x1, x2)

inst_10417:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x5611f2 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x191243 and fs3 == 0 and fe3 == 0x7f and fm3 == 0x7ffffc and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e5611f2; op2val:0x991243;
op3val:0x3ffffffc; valaddr_reg:x3; val_offset:31251*0 + 3*433*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 31251*0 + 3*433*FLEN/8, x4, x1, x2)

inst_10418:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x5611f2 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x191243 and fs3 == 0 and fe3 == 0x7f and fm3 == 0x7ffffe and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e5611f2; op2val:0x991243;
op3val:0x3ffffffe; valaddr_reg:x3; val_offset:31254*0 + 3*434*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 31254*0 + 3*434*FLEN/8, x4, x1, x2)

inst_10419:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x5611f2 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x191243 and fs3 == 0 and fe3 == 0x9c and fm3 == 0x000000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e5611f2; op2val:0x991243;
op3val:0x4e000000; valaddr_reg:x3; val_offset:31257*0 + 3*435*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 31257*0 + 3*435*FLEN/8, x4, x1, x2)

inst_10420:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x5611f2 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x191243 and fs3 == 0 and fe3 == 0x9c and fm3 == 0x000001 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e5611f2; op2val:0x991243;
op3val:0x4e000001; valaddr_reg:x3; val_offset:31260*0 + 3*436*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 31260*0 + 3*436*FLEN/8, x4, x1, x2)

inst_10421:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x5611f2 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x191243 and fs3 == 0 and fe3 == 0x9c and fm3 == 0x000003 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e5611f2; op2val:0x991243;
op3val:0x4e000003; valaddr_reg:x3; val_offset:31263*0 + 3*437*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 31263*0 + 3*437*FLEN/8, x4, x1, x2)

inst_10422:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x5611f2 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x191243 and fs3 == 0 and fe3 == 0x9c and fm3 == 0x000007 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e5611f2; op2val:0x991243;
op3val:0x4e000007; valaddr_reg:x3; val_offset:31266*0 + 3*438*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 31266*0 + 3*438*FLEN/8, x4, x1, x2)

inst_10423:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x5611f2 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x191243 and fs3 == 0 and fe3 == 0x9c and fm3 == 0x00000f and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e5611f2; op2val:0x991243;
op3val:0x4e00000f; valaddr_reg:x3; val_offset:31269*0 + 3*439*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 31269*0 + 3*439*FLEN/8, x4, x1, x2)

inst_10424:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x5611f2 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x191243 and fs3 == 0 and fe3 == 0x9c and fm3 == 0x00001f and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e5611f2; op2val:0x991243;
op3val:0x4e00001f; valaddr_reg:x3; val_offset:31272*0 + 3*440*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 31272*0 + 3*440*FLEN/8, x4, x1, x2)

inst_10425:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x5611f2 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x191243 and fs3 == 0 and fe3 == 0x9c and fm3 == 0x00003f and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e5611f2; op2val:0x991243;
op3val:0x4e00003f; valaddr_reg:x3; val_offset:31275*0 + 3*441*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 31275*0 + 3*441*FLEN/8, x4, x1, x2)

inst_10426:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x5611f2 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x191243 and fs3 == 0 and fe3 == 0x9c and fm3 == 0x00007f and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e5611f2; op2val:0x991243;
op3val:0x4e00007f; valaddr_reg:x3; val_offset:31278*0 + 3*442*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 31278*0 + 3*442*FLEN/8, x4, x1, x2)

inst_10427:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x5611f2 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x191243 and fs3 == 0 and fe3 == 0x9c and fm3 == 0x0000ff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e5611f2; op2val:0x991243;
op3val:0x4e0000ff; valaddr_reg:x3; val_offset:31281*0 + 3*443*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 31281*0 + 3*443*FLEN/8, x4, x1, x2)

inst_10428:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x5611f2 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x191243 and fs3 == 0 and fe3 == 0x9c and fm3 == 0x0001ff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e5611f2; op2val:0x991243;
op3val:0x4e0001ff; valaddr_reg:x3; val_offset:31284*0 + 3*444*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 31284*0 + 3*444*FLEN/8, x4, x1, x2)

inst_10429:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x5611f2 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x191243 and fs3 == 0 and fe3 == 0x9c and fm3 == 0x0003ff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e5611f2; op2val:0x991243;
op3val:0x4e0003ff; valaddr_reg:x3; val_offset:31287*0 + 3*445*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 31287*0 + 3*445*FLEN/8, x4, x1, x2)

inst_10430:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x5611f2 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x191243 and fs3 == 0 and fe3 == 0x9c and fm3 == 0x0007ff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e5611f2; op2val:0x991243;
op3val:0x4e0007ff; valaddr_reg:x3; val_offset:31290*0 + 3*446*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 31290*0 + 3*446*FLEN/8, x4, x1, x2)

inst_10431:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x5611f2 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x191243 and fs3 == 0 and fe3 == 0x9c and fm3 == 0x000fff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e5611f2; op2val:0x991243;
op3val:0x4e000fff; valaddr_reg:x3; val_offset:31293*0 + 3*447*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 31293*0 + 3*447*FLEN/8, x4, x1, x2)

inst_10432:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x5611f2 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x191243 and fs3 == 0 and fe3 == 0x9c and fm3 == 0x001fff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e5611f2; op2val:0x991243;
op3val:0x4e001fff; valaddr_reg:x3; val_offset:31296*0 + 3*448*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 31296*0 + 3*448*FLEN/8, x4, x1, x2)

inst_10433:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x5611f2 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x191243 and fs3 == 0 and fe3 == 0x9c and fm3 == 0x003fff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e5611f2; op2val:0x991243;
op3val:0x4e003fff; valaddr_reg:x3; val_offset:31299*0 + 3*449*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 31299*0 + 3*449*FLEN/8, x4, x1, x2)

inst_10434:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x5611f2 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x191243 and fs3 == 0 and fe3 == 0x9c and fm3 == 0x007fff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e5611f2; op2val:0x991243;
op3val:0x4e007fff; valaddr_reg:x3; val_offset:31302*0 + 3*450*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 31302*0 + 3*450*FLEN/8, x4, x1, x2)

inst_10435:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x5611f2 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x191243 and fs3 == 0 and fe3 == 0x9c and fm3 == 0x00ffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e5611f2; op2val:0x991243;
op3val:0x4e00ffff; valaddr_reg:x3; val_offset:31305*0 + 3*451*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 31305*0 + 3*451*FLEN/8, x4, x1, x2)

inst_10436:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x5611f2 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x191243 and fs3 == 0 and fe3 == 0x9c and fm3 == 0x01ffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e5611f2; op2val:0x991243;
op3val:0x4e01ffff; valaddr_reg:x3; val_offset:31308*0 + 3*452*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 31308*0 + 3*452*FLEN/8, x4, x1, x2)

inst_10437:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x5611f2 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x191243 and fs3 == 0 and fe3 == 0x9c and fm3 == 0x03ffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e5611f2; op2val:0x991243;
op3val:0x4e03ffff; valaddr_reg:x3; val_offset:31311*0 + 3*453*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 31311*0 + 3*453*FLEN/8, x4, x1, x2)

inst_10438:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x5611f2 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x191243 and fs3 == 0 and fe3 == 0x9c and fm3 == 0x07ffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e5611f2; op2val:0x991243;
op3val:0x4e07ffff; valaddr_reg:x3; val_offset:31314*0 + 3*454*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 31314*0 + 3*454*FLEN/8, x4, x1, x2)

inst_10439:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x5611f2 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x191243 and fs3 == 0 and fe3 == 0x9c and fm3 == 0x0fffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e5611f2; op2val:0x991243;
op3val:0x4e0fffff; valaddr_reg:x3; val_offset:31317*0 + 3*455*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 31317*0 + 3*455*FLEN/8, x4, x1, x2)

inst_10440:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x5611f2 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x191243 and fs3 == 0 and fe3 == 0x9c and fm3 == 0x1fffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e5611f2; op2val:0x991243;
op3val:0x4e1fffff; valaddr_reg:x3; val_offset:31320*0 + 3*456*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 31320*0 + 3*456*FLEN/8, x4, x1, x2)

inst_10441:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x5611f2 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x191243 and fs3 == 0 and fe3 == 0x9c and fm3 == 0x3fffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e5611f2; op2val:0x991243;
op3val:0x4e3fffff; valaddr_reg:x3; val_offset:31323*0 + 3*457*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 31323*0 + 3*457*FLEN/8, x4, x1, x2)

inst_10442:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x5611f2 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x191243 and fs3 == 0 and fe3 == 0x9c and fm3 == 0x400000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e5611f2; op2val:0x991243;
op3val:0x4e400000; valaddr_reg:x3; val_offset:31326*0 + 3*458*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 31326*0 + 3*458*FLEN/8, x4, x1, x2)

inst_10443:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x5611f2 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x191243 and fs3 == 0 and fe3 == 0x9c and fm3 == 0x600000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e5611f2; op2val:0x991243;
op3val:0x4e600000; valaddr_reg:x3; val_offset:31329*0 + 3*459*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 31329*0 + 3*459*FLEN/8, x4, x1, x2)

inst_10444:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x5611f2 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x191243 and fs3 == 0 and fe3 == 0x9c and fm3 == 0x700000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e5611f2; op2val:0x991243;
op3val:0x4e700000; valaddr_reg:x3; val_offset:31332*0 + 3*460*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 31332*0 + 3*460*FLEN/8, x4, x1, x2)

inst_10445:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x5611f2 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x191243 and fs3 == 0 and fe3 == 0x9c and fm3 == 0x780000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e5611f2; op2val:0x991243;
op3val:0x4e780000; valaddr_reg:x3; val_offset:31335*0 + 3*461*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 31335*0 + 3*461*FLEN/8, x4, x1, x2)

inst_10446:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x5611f2 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x191243 and fs3 == 0 and fe3 == 0x9c and fm3 == 0x7c0000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e5611f2; op2val:0x991243;
op3val:0x4e7c0000; valaddr_reg:x3; val_offset:31338*0 + 3*462*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 31338*0 + 3*462*FLEN/8, x4, x1, x2)

inst_10447:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x5611f2 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x191243 and fs3 == 0 and fe3 == 0x9c and fm3 == 0x7e0000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e5611f2; op2val:0x991243;
op3val:0x4e7e0000; valaddr_reg:x3; val_offset:31341*0 + 3*463*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 31341*0 + 3*463*FLEN/8, x4, x1, x2)

inst_10448:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x5611f2 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x191243 and fs3 == 0 and fe3 == 0x9c and fm3 == 0x7f0000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e5611f2; op2val:0x991243;
op3val:0x4e7f0000; valaddr_reg:x3; val_offset:31344*0 + 3*464*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 31344*0 + 3*464*FLEN/8, x4, x1, x2)

inst_10449:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x5611f2 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x191243 and fs3 == 0 and fe3 == 0x9c and fm3 == 0x7f8000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e5611f2; op2val:0x991243;
op3val:0x4e7f8000; valaddr_reg:x3; val_offset:31347*0 + 3*465*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 31347*0 + 3*465*FLEN/8, x4, x1, x2)

inst_10450:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x5611f2 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x191243 and fs3 == 0 and fe3 == 0x9c and fm3 == 0x7fc000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e5611f2; op2val:0x991243;
op3val:0x4e7fc000; valaddr_reg:x3; val_offset:31350*0 + 3*466*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 31350*0 + 3*466*FLEN/8, x4, x1, x2)

inst_10451:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x5611f2 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x191243 and fs3 == 0 and fe3 == 0x9c and fm3 == 0x7fe000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e5611f2; op2val:0x991243;
op3val:0x4e7fe000; valaddr_reg:x3; val_offset:31353*0 + 3*467*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 31353*0 + 3*467*FLEN/8, x4, x1, x2)

inst_10452:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x5611f2 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x191243 and fs3 == 0 and fe3 == 0x9c and fm3 == 0x7ff000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e5611f2; op2val:0x991243;
op3val:0x4e7ff000; valaddr_reg:x3; val_offset:31356*0 + 3*468*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 31356*0 + 3*468*FLEN/8, x4, x1, x2)

inst_10453:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x5611f2 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x191243 and fs3 == 0 and fe3 == 0x9c and fm3 == 0x7ff800 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e5611f2; op2val:0x991243;
op3val:0x4e7ff800; valaddr_reg:x3; val_offset:31359*0 + 3*469*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 31359*0 + 3*469*FLEN/8, x4, x1, x2)

inst_10454:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x5611f2 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x191243 and fs3 == 0 and fe3 == 0x9c and fm3 == 0x7ffc00 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e5611f2; op2val:0x991243;
op3val:0x4e7ffc00; valaddr_reg:x3; val_offset:31362*0 + 3*470*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 31362*0 + 3*470*FLEN/8, x4, x1, x2)

inst_10455:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x5611f2 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x191243 and fs3 == 0 and fe3 == 0x9c and fm3 == 0x7ffe00 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e5611f2; op2val:0x991243;
op3val:0x4e7ffe00; valaddr_reg:x3; val_offset:31365*0 + 3*471*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 31365*0 + 3*471*FLEN/8, x4, x1, x2)

inst_10456:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x5611f2 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x191243 and fs3 == 0 and fe3 == 0x9c and fm3 == 0x7fff00 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e5611f2; op2val:0x991243;
op3val:0x4e7fff00; valaddr_reg:x3; val_offset:31368*0 + 3*472*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 31368*0 + 3*472*FLEN/8, x4, x1, x2)

inst_10457:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x5611f2 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x191243 and fs3 == 0 and fe3 == 0x9c and fm3 == 0x7fff80 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e5611f2; op2val:0x991243;
op3val:0x4e7fff80; valaddr_reg:x3; val_offset:31371*0 + 3*473*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 31371*0 + 3*473*FLEN/8, x4, x1, x2)

inst_10458:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x5611f2 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x191243 and fs3 == 0 and fe3 == 0x9c and fm3 == 0x7fffc0 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e5611f2; op2val:0x991243;
op3val:0x4e7fffc0; valaddr_reg:x3; val_offset:31374*0 + 3*474*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 31374*0 + 3*474*FLEN/8, x4, x1, x2)

inst_10459:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x5611f2 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x191243 and fs3 == 0 and fe3 == 0x9c and fm3 == 0x7fffe0 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e5611f2; op2val:0x991243;
op3val:0x4e7fffe0; valaddr_reg:x3; val_offset:31377*0 + 3*475*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 31377*0 + 3*475*FLEN/8, x4, x1, x2)

inst_10460:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x5611f2 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x191243 and fs3 == 0 and fe3 == 0x9c and fm3 == 0x7ffff0 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e5611f2; op2val:0x991243;
op3val:0x4e7ffff0; valaddr_reg:x3; val_offset:31380*0 + 3*476*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 31380*0 + 3*476*FLEN/8, x4, x1, x2)

inst_10461:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x5611f2 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x191243 and fs3 == 0 and fe3 == 0x9c and fm3 == 0x7ffff8 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e5611f2; op2val:0x991243;
op3val:0x4e7ffff8; valaddr_reg:x3; val_offset:31383*0 + 3*477*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 31383*0 + 3*477*FLEN/8, x4, x1, x2)

inst_10462:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x5611f2 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x191243 and fs3 == 0 and fe3 == 0x9c and fm3 == 0x7ffffc and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e5611f2; op2val:0x991243;
op3val:0x4e7ffffc; valaddr_reg:x3; val_offset:31386*0 + 3*478*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 31386*0 + 3*478*FLEN/8, x4, x1, x2)

inst_10463:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x5611f2 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x191243 and fs3 == 0 and fe3 == 0x9c and fm3 == 0x7ffffe and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e5611f2; op2val:0x991243;
op3val:0x4e7ffffe; valaddr_reg:x3; val_offset:31389*0 + 3*479*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 31389*0 + 3*479*FLEN/8, x4, x1, x2)

inst_10464:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x5611f2 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x191243 and fs3 == 0 and fe3 == 0x9c and fm3 == 0x7fffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e5611f2; op2val:0x991243;
op3val:0x4e7fffff; valaddr_reg:x3; val_offset:31392*0 + 3*480*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 31392*0 + 3*480*FLEN/8, x4, x1, x2)

inst_10465:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x5659bb and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000001 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e5659bb; op2val:0x80000000;
op3val:0x80000001; valaddr_reg:x3; val_offset:31395*0 + 3*481*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 31395*0 + 3*481*FLEN/8, x4, x1, x2)

inst_10466:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x5659bb and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000003 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e5659bb; op2val:0x80000000;
op3val:0x80000003; valaddr_reg:x3; val_offset:31398*0 + 3*482*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 31398*0 + 3*482*FLEN/8, x4, x1, x2)

inst_10467:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x5659bb and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000007 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e5659bb; op2val:0x80000000;
op3val:0x80000007; valaddr_reg:x3; val_offset:31401*0 + 3*483*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 31401*0 + 3*483*FLEN/8, x4, x1, x2)

inst_10468:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x5659bb and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x199999 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e5659bb; op2val:0x80000000;
op3val:0x80199999; valaddr_reg:x3; val_offset:31404*0 + 3*484*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 31404*0 + 3*484*FLEN/8, x4, x1, x2)

inst_10469:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x5659bb and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x249249 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e5659bb; op2val:0x80000000;
op3val:0x80249249; valaddr_reg:x3; val_offset:31407*0 + 3*485*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 31407*0 + 3*485*FLEN/8, x4, x1, x2)

inst_10470:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x5659bb and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x333333 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e5659bb; op2val:0x80000000;
op3val:0x80333333; valaddr_reg:x3; val_offset:31410*0 + 3*486*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 31410*0 + 3*486*FLEN/8, x4, x1, x2)

inst_10471:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x5659bb and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x36db6d and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e5659bb; op2val:0x80000000;
op3val:0x8036db6d; valaddr_reg:x3; val_offset:31413*0 + 3*487*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 31413*0 + 3*487*FLEN/8, x4, x1, x2)

inst_10472:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x5659bb and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3bbbbb and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e5659bb; op2val:0x80000000;
op3val:0x803bbbbb; valaddr_reg:x3; val_offset:31416*0 + 3*488*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 31416*0 + 3*488*FLEN/8, x4, x1, x2)

inst_10473:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x5659bb and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x444444 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e5659bb; op2val:0x80000000;
op3val:0x80444444; valaddr_reg:x3; val_offset:31419*0 + 3*489*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 31419*0 + 3*489*FLEN/8, x4, x1, x2)

inst_10474:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x5659bb and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x4ccccc and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e5659bb; op2val:0x80000000;
op3val:0x804ccccc; valaddr_reg:x3; val_offset:31422*0 + 3*490*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 31422*0 + 3*490*FLEN/8, x4, x1, x2)

inst_10475:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x5659bb and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x5b6db6 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e5659bb; op2val:0x80000000;
op3val:0x805b6db6; valaddr_reg:x3; val_offset:31425*0 + 3*491*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 31425*0 + 3*491*FLEN/8, x4, x1, x2)

inst_10476:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x5659bb and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x666666 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e5659bb; op2val:0x80000000;
op3val:0x80666666; valaddr_reg:x3; val_offset:31428*0 + 3*492*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 31428*0 + 3*492*FLEN/8, x4, x1, x2)

inst_10477:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x5659bb and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x6db6db and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e5659bb; op2val:0x80000000;
op3val:0x806db6db; valaddr_reg:x3; val_offset:31431*0 + 3*493*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 31431*0 + 3*493*FLEN/8, x4, x1, x2)

inst_10478:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x5659bb and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7ffff8 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e5659bb; op2val:0x80000000;
op3val:0x807ffff8; valaddr_reg:x3; val_offset:31434*0 + 3*494*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 31434*0 + 3*494*FLEN/8, x4, x1, x2)

inst_10479:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x5659bb and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7ffffc and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e5659bb; op2val:0x80000000;
op3val:0x807ffffc; valaddr_reg:x3; val_offset:31437*0 + 3*495*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 31437*0 + 3*495*FLEN/8, x4, x1, x2)

inst_10480:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x5659bb and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7ffffe and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e5659bb; op2val:0x80000000;
op3val:0x807ffffe; valaddr_reg:x3; val_offset:31440*0 + 3*496*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 31440*0 + 3*496*FLEN/8, x4, x1, x2)

inst_10481:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x5659bb and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x0c and fm3 == 0x000000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e5659bb; op2val:0x80000000;
op3val:0x86000000; valaddr_reg:x3; val_offset:31443*0 + 3*497*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 31443*0 + 3*497*FLEN/8, x4, x1, x2)

inst_10482:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x5659bb and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x0c and fm3 == 0x000001 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e5659bb; op2val:0x80000000;
op3val:0x86000001; valaddr_reg:x3; val_offset:31446*0 + 3*498*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 31446*0 + 3*498*FLEN/8, x4, x1, x2)

inst_10483:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x5659bb and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x0c and fm3 == 0x000003 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e5659bb; op2val:0x80000000;
op3val:0x86000003; valaddr_reg:x3; val_offset:31449*0 + 3*499*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 31449*0 + 3*499*FLEN/8, x4, x1, x2)

inst_10484:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x5659bb and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x0c and fm3 == 0x000007 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e5659bb; op2val:0x80000000;
op3val:0x86000007; valaddr_reg:x3; val_offset:31452*0 + 3*500*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 31452*0 + 3*500*FLEN/8, x4, x1, x2)

inst_10485:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x5659bb and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x0c and fm3 == 0x00000f and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e5659bb; op2val:0x80000000;
op3val:0x8600000f; valaddr_reg:x3; val_offset:31455*0 + 3*501*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 31455*0 + 3*501*FLEN/8, x4, x1, x2)

inst_10486:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x5659bb and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x0c and fm3 == 0x00001f and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e5659bb; op2val:0x80000000;
op3val:0x8600001f; valaddr_reg:x3; val_offset:31458*0 + 3*502*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 31458*0 + 3*502*FLEN/8, x4, x1, x2)

inst_10487:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x5659bb and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x0c and fm3 == 0x00003f and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e5659bb; op2val:0x80000000;
op3val:0x8600003f; valaddr_reg:x3; val_offset:31461*0 + 3*503*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 31461*0 + 3*503*FLEN/8, x4, x1, x2)

inst_10488:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x5659bb and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x0c and fm3 == 0x00007f and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e5659bb; op2val:0x80000000;
op3val:0x8600007f; valaddr_reg:x3; val_offset:31464*0 + 3*504*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 31464*0 + 3*504*FLEN/8, x4, x1, x2)

inst_10489:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x5659bb and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x0c and fm3 == 0x0000ff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e5659bb; op2val:0x80000000;
op3val:0x860000ff; valaddr_reg:x3; val_offset:31467*0 + 3*505*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 31467*0 + 3*505*FLEN/8, x4, x1, x2)

inst_10490:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x5659bb and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x0c and fm3 == 0x0001ff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e5659bb; op2val:0x80000000;
op3val:0x860001ff; valaddr_reg:x3; val_offset:31470*0 + 3*506*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 31470*0 + 3*506*FLEN/8, x4, x1, x2)

inst_10491:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x5659bb and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x0c and fm3 == 0x0003ff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e5659bb; op2val:0x80000000;
op3val:0x860003ff; valaddr_reg:x3; val_offset:31473*0 + 3*507*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 31473*0 + 3*507*FLEN/8, x4, x1, x2)

inst_10492:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x5659bb and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x0c and fm3 == 0x0007ff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e5659bb; op2val:0x80000000;
op3val:0x860007ff; valaddr_reg:x3; val_offset:31476*0 + 3*508*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 31476*0 + 3*508*FLEN/8, x4, x1, x2)

inst_10493:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x5659bb and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x0c and fm3 == 0x000fff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e5659bb; op2val:0x80000000;
op3val:0x86000fff; valaddr_reg:x3; val_offset:31479*0 + 3*509*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 31479*0 + 3*509*FLEN/8, x4, x1, x2)

inst_10494:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x5659bb and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x0c and fm3 == 0x001fff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e5659bb; op2val:0x80000000;
op3val:0x86001fff; valaddr_reg:x3; val_offset:31482*0 + 3*510*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 31482*0 + 3*510*FLEN/8, x4, x1, x2)

inst_10495:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x5659bb and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x0c and fm3 == 0x003fff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e5659bb; op2val:0x80000000;
op3val:0x86003fff; valaddr_reg:x3; val_offset:31485*0 + 3*511*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 31485*0 + 3*511*FLEN/8, x4, x1, x2)
RVTEST_SIGBASE(x1,signature_x1_5)

inst_10496:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x5659bb and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x0c and fm3 == 0x007fff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e5659bb; op2val:0x80000000;
op3val:0x86007fff; valaddr_reg:x3; val_offset:31488*0 + 3*512*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 31488*0 + 3*512*FLEN/8, x4, x1, x2)

inst_10497:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x5659bb and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x0c and fm3 == 0x00ffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e5659bb; op2val:0x80000000;
op3val:0x8600ffff; valaddr_reg:x3; val_offset:31491*0 + 3*513*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 31491*0 + 3*513*FLEN/8, x4, x1, x2)

inst_10498:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x5659bb and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x0c and fm3 == 0x01ffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e5659bb; op2val:0x80000000;
op3val:0x8601ffff; valaddr_reg:x3; val_offset:31494*0 + 3*514*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 31494*0 + 3*514*FLEN/8, x4, x1, x2)

inst_10499:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x5659bb and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x0c and fm3 == 0x03ffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e5659bb; op2val:0x80000000;
op3val:0x8603ffff; valaddr_reg:x3; val_offset:31497*0 + 3*515*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 31497*0 + 3*515*FLEN/8, x4, x1, x2)

inst_10500:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x5659bb and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x0c and fm3 == 0x07ffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e5659bb; op2val:0x80000000;
op3val:0x8607ffff; valaddr_reg:x3; val_offset:31500*0 + 3*516*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 31500*0 + 3*516*FLEN/8, x4, x1, x2)

inst_10501:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x5659bb and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x0c and fm3 == 0x0fffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e5659bb; op2val:0x80000000;
op3val:0x860fffff; valaddr_reg:x3; val_offset:31503*0 + 3*517*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 31503*0 + 3*517*FLEN/8, x4, x1, x2)

inst_10502:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x5659bb and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x0c and fm3 == 0x1fffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e5659bb; op2val:0x80000000;
op3val:0x861fffff; valaddr_reg:x3; val_offset:31506*0 + 3*518*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 31506*0 + 3*518*FLEN/8, x4, x1, x2)

inst_10503:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x5659bb and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x0c and fm3 == 0x3fffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e5659bb; op2val:0x80000000;
op3val:0x863fffff; valaddr_reg:x3; val_offset:31509*0 + 3*519*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 31509*0 + 3*519*FLEN/8, x4, x1, x2)

inst_10504:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x5659bb and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x0c and fm3 == 0x400000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e5659bb; op2val:0x80000000;
op3val:0x86400000; valaddr_reg:x3; val_offset:31512*0 + 3*520*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 31512*0 + 3*520*FLEN/8, x4, x1, x2)

inst_10505:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x5659bb and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x0c and fm3 == 0x600000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e5659bb; op2val:0x80000000;
op3val:0x86600000; valaddr_reg:x3; val_offset:31515*0 + 3*521*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 31515*0 + 3*521*FLEN/8, x4, x1, x2)

inst_10506:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x5659bb and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x0c and fm3 == 0x700000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e5659bb; op2val:0x80000000;
op3val:0x86700000; valaddr_reg:x3; val_offset:31518*0 + 3*522*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 31518*0 + 3*522*FLEN/8, x4, x1, x2)

inst_10507:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x5659bb and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x0c and fm3 == 0x780000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e5659bb; op2val:0x80000000;
op3val:0x86780000; valaddr_reg:x3; val_offset:31521*0 + 3*523*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 31521*0 + 3*523*FLEN/8, x4, x1, x2)

inst_10508:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x5659bb and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x0c and fm3 == 0x7c0000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e5659bb; op2val:0x80000000;
op3val:0x867c0000; valaddr_reg:x3; val_offset:31524*0 + 3*524*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 31524*0 + 3*524*FLEN/8, x4, x1, x2)

inst_10509:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x5659bb and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x0c and fm3 == 0x7e0000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e5659bb; op2val:0x80000000;
op3val:0x867e0000; valaddr_reg:x3; val_offset:31527*0 + 3*525*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 31527*0 + 3*525*FLEN/8, x4, x1, x2)

inst_10510:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x5659bb and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x0c and fm3 == 0x7f0000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e5659bb; op2val:0x80000000;
op3val:0x867f0000; valaddr_reg:x3; val_offset:31530*0 + 3*526*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 31530*0 + 3*526*FLEN/8, x4, x1, x2)

inst_10511:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x5659bb and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x0c and fm3 == 0x7f8000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e5659bb; op2val:0x80000000;
op3val:0x867f8000; valaddr_reg:x3; val_offset:31533*0 + 3*527*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 31533*0 + 3*527*FLEN/8, x4, x1, x2)

inst_10512:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x5659bb and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x0c and fm3 == 0x7fc000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e5659bb; op2val:0x80000000;
op3val:0x867fc000; valaddr_reg:x3; val_offset:31536*0 + 3*528*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 31536*0 + 3*528*FLEN/8, x4, x1, x2)

inst_10513:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x5659bb and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x0c and fm3 == 0x7fe000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e5659bb; op2val:0x80000000;
op3val:0x867fe000; valaddr_reg:x3; val_offset:31539*0 + 3*529*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 31539*0 + 3*529*FLEN/8, x4, x1, x2)

inst_10514:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x5659bb and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x0c and fm3 == 0x7ff000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e5659bb; op2val:0x80000000;
op3val:0x867ff000; valaddr_reg:x3; val_offset:31542*0 + 3*530*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 31542*0 + 3*530*FLEN/8, x4, x1, x2)

inst_10515:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x5659bb and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x0c and fm3 == 0x7ff800 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e5659bb; op2val:0x80000000;
op3val:0x867ff800; valaddr_reg:x3; val_offset:31545*0 + 3*531*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 31545*0 + 3*531*FLEN/8, x4, x1, x2)

inst_10516:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x5659bb and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x0c and fm3 == 0x7ffc00 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e5659bb; op2val:0x80000000;
op3val:0x867ffc00; valaddr_reg:x3; val_offset:31548*0 + 3*532*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 31548*0 + 3*532*FLEN/8, x4, x1, x2)

inst_10517:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x5659bb and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x0c and fm3 == 0x7ffe00 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e5659bb; op2val:0x80000000;
op3val:0x867ffe00; valaddr_reg:x3; val_offset:31551*0 + 3*533*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 31551*0 + 3*533*FLEN/8, x4, x1, x2)

inst_10518:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x5659bb and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x0c and fm3 == 0x7fff00 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e5659bb; op2val:0x80000000;
op3val:0x867fff00; valaddr_reg:x3; val_offset:31554*0 + 3*534*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 31554*0 + 3*534*FLEN/8, x4, x1, x2)

inst_10519:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x5659bb and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x0c and fm3 == 0x7fff80 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e5659bb; op2val:0x80000000;
op3val:0x867fff80; valaddr_reg:x3; val_offset:31557*0 + 3*535*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 31557*0 + 3*535*FLEN/8, x4, x1, x2)

inst_10520:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x5659bb and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x0c and fm3 == 0x7fffc0 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e5659bb; op2val:0x80000000;
op3val:0x867fffc0; valaddr_reg:x3; val_offset:31560*0 + 3*536*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 31560*0 + 3*536*FLEN/8, x4, x1, x2)

inst_10521:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x5659bb and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x0c and fm3 == 0x7fffe0 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e5659bb; op2val:0x80000000;
op3val:0x867fffe0; valaddr_reg:x3; val_offset:31563*0 + 3*537*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 31563*0 + 3*537*FLEN/8, x4, x1, x2)

inst_10522:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x5659bb and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x0c and fm3 == 0x7ffff0 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e5659bb; op2val:0x80000000;
op3val:0x867ffff0; valaddr_reg:x3; val_offset:31566*0 + 3*538*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 31566*0 + 3*538*FLEN/8, x4, x1, x2)

inst_10523:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x5659bb and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x0c and fm3 == 0x7ffff8 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e5659bb; op2val:0x80000000;
op3val:0x867ffff8; valaddr_reg:x3; val_offset:31569*0 + 3*539*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 31569*0 + 3*539*FLEN/8, x4, x1, x2)

inst_10524:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x5659bb and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x0c and fm3 == 0x7ffffc and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e5659bb; op2val:0x80000000;
op3val:0x867ffffc; valaddr_reg:x3; val_offset:31572*0 + 3*540*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 31572*0 + 3*540*FLEN/8, x4, x1, x2)

inst_10525:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x5659bb and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x0c and fm3 == 0x7ffffe and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e5659bb; op2val:0x80000000;
op3val:0x867ffffe; valaddr_reg:x3; val_offset:31575*0 + 3*541*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 31575*0 + 3*541*FLEN/8, x4, x1, x2)

inst_10526:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x5659bb and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x0c and fm3 == 0x7fffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e5659bb; op2val:0x80000000;
op3val:0x867fffff; valaddr_reg:x3; val_offset:31578*0 + 3*542*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 31578*0 + 3*542*FLEN/8, x4, x1, x2)

inst_10527:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x56eede and fs2 == 1 and fe2 == 0x81 and fm2 == 0x1874ed and fs3 == 1 and fe3 == 0xce and fm3 == 0x000000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e56eede; op2val:0xc09874ed;
op3val:0xe7000000; valaddr_reg:x3; val_offset:31581*0 + 3*543*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 31581*0 + 3*543*FLEN/8, x4, x1, x2)

inst_10528:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x56eede and fs2 == 1 and fe2 == 0x81 and fm2 == 0x1874ed and fs3 == 1 and fe3 == 0xce and fm3 == 0x000001 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e56eede; op2val:0xc09874ed;
op3val:0xe7000001; valaddr_reg:x3; val_offset:31584*0 + 3*544*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 31584*0 + 3*544*FLEN/8, x4, x1, x2)

inst_10529:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x56eede and fs2 == 1 and fe2 == 0x81 and fm2 == 0x1874ed and fs3 == 1 and fe3 == 0xce and fm3 == 0x000003 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e56eede; op2val:0xc09874ed;
op3val:0xe7000003; valaddr_reg:x3; val_offset:31587*0 + 3*545*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 31587*0 + 3*545*FLEN/8, x4, x1, x2)

inst_10530:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x56eede and fs2 == 1 and fe2 == 0x81 and fm2 == 0x1874ed and fs3 == 1 and fe3 == 0xce and fm3 == 0x000007 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e56eede; op2val:0xc09874ed;
op3val:0xe7000007; valaddr_reg:x3; val_offset:31590*0 + 3*546*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 31590*0 + 3*546*FLEN/8, x4, x1, x2)

inst_10531:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x56eede and fs2 == 1 and fe2 == 0x81 and fm2 == 0x1874ed and fs3 == 1 and fe3 == 0xce and fm3 == 0x00000f and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e56eede; op2val:0xc09874ed;
op3val:0xe700000f; valaddr_reg:x3; val_offset:31593*0 + 3*547*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 31593*0 + 3*547*FLEN/8, x4, x1, x2)

inst_10532:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x56eede and fs2 == 1 and fe2 == 0x81 and fm2 == 0x1874ed and fs3 == 1 and fe3 == 0xce and fm3 == 0x00001f and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e56eede; op2val:0xc09874ed;
op3val:0xe700001f; valaddr_reg:x3; val_offset:31596*0 + 3*548*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 31596*0 + 3*548*FLEN/8, x4, x1, x2)

inst_10533:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x56eede and fs2 == 1 and fe2 == 0x81 and fm2 == 0x1874ed and fs3 == 1 and fe3 == 0xce and fm3 == 0x00003f and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e56eede; op2val:0xc09874ed;
op3val:0xe700003f; valaddr_reg:x3; val_offset:31599*0 + 3*549*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 31599*0 + 3*549*FLEN/8, x4, x1, x2)

inst_10534:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x56eede and fs2 == 1 and fe2 == 0x81 and fm2 == 0x1874ed and fs3 == 1 and fe3 == 0xce and fm3 == 0x00007f and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e56eede; op2val:0xc09874ed;
op3val:0xe700007f; valaddr_reg:x3; val_offset:31602*0 + 3*550*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 31602*0 + 3*550*FLEN/8, x4, x1, x2)

inst_10535:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x56eede and fs2 == 1 and fe2 == 0x81 and fm2 == 0x1874ed and fs3 == 1 and fe3 == 0xce and fm3 == 0x0000ff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e56eede; op2val:0xc09874ed;
op3val:0xe70000ff; valaddr_reg:x3; val_offset:31605*0 + 3*551*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 31605*0 + 3*551*FLEN/8, x4, x1, x2)

inst_10536:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x56eede and fs2 == 1 and fe2 == 0x81 and fm2 == 0x1874ed and fs3 == 1 and fe3 == 0xce and fm3 == 0x0001ff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e56eede; op2val:0xc09874ed;
op3val:0xe70001ff; valaddr_reg:x3; val_offset:31608*0 + 3*552*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 31608*0 + 3*552*FLEN/8, x4, x1, x2)

inst_10537:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x56eede and fs2 == 1 and fe2 == 0x81 and fm2 == 0x1874ed and fs3 == 1 and fe3 == 0xce and fm3 == 0x0003ff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e56eede; op2val:0xc09874ed;
op3val:0xe70003ff; valaddr_reg:x3; val_offset:31611*0 + 3*553*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 31611*0 + 3*553*FLEN/8, x4, x1, x2)

inst_10538:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x56eede and fs2 == 1 and fe2 == 0x81 and fm2 == 0x1874ed and fs3 == 1 and fe3 == 0xce and fm3 == 0x0007ff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e56eede; op2val:0xc09874ed;
op3val:0xe70007ff; valaddr_reg:x3; val_offset:31614*0 + 3*554*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 31614*0 + 3*554*FLEN/8, x4, x1, x2)

inst_10539:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x56eede and fs2 == 1 and fe2 == 0x81 and fm2 == 0x1874ed and fs3 == 1 and fe3 == 0xce and fm3 == 0x000fff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e56eede; op2val:0xc09874ed;
op3val:0xe7000fff; valaddr_reg:x3; val_offset:31617*0 + 3*555*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 31617*0 + 3*555*FLEN/8, x4, x1, x2)

inst_10540:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x56eede and fs2 == 1 and fe2 == 0x81 and fm2 == 0x1874ed and fs3 == 1 and fe3 == 0xce and fm3 == 0x001fff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e56eede; op2val:0xc09874ed;
op3val:0xe7001fff; valaddr_reg:x3; val_offset:31620*0 + 3*556*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 31620*0 + 3*556*FLEN/8, x4, x1, x2)

inst_10541:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x56eede and fs2 == 1 and fe2 == 0x81 and fm2 == 0x1874ed and fs3 == 1 and fe3 == 0xce and fm3 == 0x003fff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e56eede; op2val:0xc09874ed;
op3val:0xe7003fff; valaddr_reg:x3; val_offset:31623*0 + 3*557*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 31623*0 + 3*557*FLEN/8, x4, x1, x2)

inst_10542:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x56eede and fs2 == 1 and fe2 == 0x81 and fm2 == 0x1874ed and fs3 == 1 and fe3 == 0xce and fm3 == 0x007fff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e56eede; op2val:0xc09874ed;
op3val:0xe7007fff; valaddr_reg:x3; val_offset:31626*0 + 3*558*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 31626*0 + 3*558*FLEN/8, x4, x1, x2)

inst_10543:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x56eede and fs2 == 1 and fe2 == 0x81 and fm2 == 0x1874ed and fs3 == 1 and fe3 == 0xce and fm3 == 0x00ffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e56eede; op2val:0xc09874ed;
op3val:0xe700ffff; valaddr_reg:x3; val_offset:31629*0 + 3*559*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 31629*0 + 3*559*FLEN/8, x4, x1, x2)

inst_10544:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x56eede and fs2 == 1 and fe2 == 0x81 and fm2 == 0x1874ed and fs3 == 1 and fe3 == 0xce and fm3 == 0x01ffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e56eede; op2val:0xc09874ed;
op3val:0xe701ffff; valaddr_reg:x3; val_offset:31632*0 + 3*560*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 31632*0 + 3*560*FLEN/8, x4, x1, x2)

inst_10545:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x56eede and fs2 == 1 and fe2 == 0x81 and fm2 == 0x1874ed and fs3 == 1 and fe3 == 0xce and fm3 == 0x03ffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e56eede; op2val:0xc09874ed;
op3val:0xe703ffff; valaddr_reg:x3; val_offset:31635*0 + 3*561*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 31635*0 + 3*561*FLEN/8, x4, x1, x2)

inst_10546:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x56eede and fs2 == 1 and fe2 == 0x81 and fm2 == 0x1874ed and fs3 == 1 and fe3 == 0xce and fm3 == 0x07ffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e56eede; op2val:0xc09874ed;
op3val:0xe707ffff; valaddr_reg:x3; val_offset:31638*0 + 3*562*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 31638*0 + 3*562*FLEN/8, x4, x1, x2)

inst_10547:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x56eede and fs2 == 1 and fe2 == 0x81 and fm2 == 0x1874ed and fs3 == 1 and fe3 == 0xce and fm3 == 0x0fffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e56eede; op2val:0xc09874ed;
op3val:0xe70fffff; valaddr_reg:x3; val_offset:31641*0 + 3*563*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 31641*0 + 3*563*FLEN/8, x4, x1, x2)

inst_10548:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x56eede and fs2 == 1 and fe2 == 0x81 and fm2 == 0x1874ed and fs3 == 1 and fe3 == 0xce and fm3 == 0x1fffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e56eede; op2val:0xc09874ed;
op3val:0xe71fffff; valaddr_reg:x3; val_offset:31644*0 + 3*564*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 31644*0 + 3*564*FLEN/8, x4, x1, x2)

inst_10549:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x56eede and fs2 == 1 and fe2 == 0x81 and fm2 == 0x1874ed and fs3 == 1 and fe3 == 0xce and fm3 == 0x3fffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e56eede; op2val:0xc09874ed;
op3val:0xe73fffff; valaddr_reg:x3; val_offset:31647*0 + 3*565*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 31647*0 + 3*565*FLEN/8, x4, x1, x2)

inst_10550:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x56eede and fs2 == 1 and fe2 == 0x81 and fm2 == 0x1874ed and fs3 == 1 and fe3 == 0xce and fm3 == 0x400000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e56eede; op2val:0xc09874ed;
op3val:0xe7400000; valaddr_reg:x3; val_offset:31650*0 + 3*566*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 31650*0 + 3*566*FLEN/8, x4, x1, x2)

inst_10551:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x56eede and fs2 == 1 and fe2 == 0x81 and fm2 == 0x1874ed and fs3 == 1 and fe3 == 0xce and fm3 == 0x600000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e56eede; op2val:0xc09874ed;
op3val:0xe7600000; valaddr_reg:x3; val_offset:31653*0 + 3*567*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 31653*0 + 3*567*FLEN/8, x4, x1, x2)

inst_10552:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x56eede and fs2 == 1 and fe2 == 0x81 and fm2 == 0x1874ed and fs3 == 1 and fe3 == 0xce and fm3 == 0x700000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e56eede; op2val:0xc09874ed;
op3val:0xe7700000; valaddr_reg:x3; val_offset:31656*0 + 3*568*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 31656*0 + 3*568*FLEN/8, x4, x1, x2)

inst_10553:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x56eede and fs2 == 1 and fe2 == 0x81 and fm2 == 0x1874ed and fs3 == 1 and fe3 == 0xce and fm3 == 0x780000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e56eede; op2val:0xc09874ed;
op3val:0xe7780000; valaddr_reg:x3; val_offset:31659*0 + 3*569*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 31659*0 + 3*569*FLEN/8, x4, x1, x2)

inst_10554:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x56eede and fs2 == 1 and fe2 == 0x81 and fm2 == 0x1874ed and fs3 == 1 and fe3 == 0xce and fm3 == 0x7c0000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e56eede; op2val:0xc09874ed;
op3val:0xe77c0000; valaddr_reg:x3; val_offset:31662*0 + 3*570*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 31662*0 + 3*570*FLEN/8, x4, x1, x2)

inst_10555:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x56eede and fs2 == 1 and fe2 == 0x81 and fm2 == 0x1874ed and fs3 == 1 and fe3 == 0xce and fm3 == 0x7e0000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e56eede; op2val:0xc09874ed;
op3val:0xe77e0000; valaddr_reg:x3; val_offset:31665*0 + 3*571*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 31665*0 + 3*571*FLEN/8, x4, x1, x2)

inst_10556:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x56eede and fs2 == 1 and fe2 == 0x81 and fm2 == 0x1874ed and fs3 == 1 and fe3 == 0xce and fm3 == 0x7f0000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e56eede; op2val:0xc09874ed;
op3val:0xe77f0000; valaddr_reg:x3; val_offset:31668*0 + 3*572*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 31668*0 + 3*572*FLEN/8, x4, x1, x2)

inst_10557:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x56eede and fs2 == 1 and fe2 == 0x81 and fm2 == 0x1874ed and fs3 == 1 and fe3 == 0xce and fm3 == 0x7f8000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e56eede; op2val:0xc09874ed;
op3val:0xe77f8000; valaddr_reg:x3; val_offset:31671*0 + 3*573*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 31671*0 + 3*573*FLEN/8, x4, x1, x2)

inst_10558:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x56eede and fs2 == 1 and fe2 == 0x81 and fm2 == 0x1874ed and fs3 == 1 and fe3 == 0xce and fm3 == 0x7fc000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e56eede; op2val:0xc09874ed;
op3val:0xe77fc000; valaddr_reg:x3; val_offset:31674*0 + 3*574*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 31674*0 + 3*574*FLEN/8, x4, x1, x2)

inst_10559:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x56eede and fs2 == 1 and fe2 == 0x81 and fm2 == 0x1874ed and fs3 == 1 and fe3 == 0xce and fm3 == 0x7fe000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e56eede; op2val:0xc09874ed;
op3val:0xe77fe000; valaddr_reg:x3; val_offset:31677*0 + 3*575*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 31677*0 + 3*575*FLEN/8, x4, x1, x2)

inst_10560:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x56eede and fs2 == 1 and fe2 == 0x81 and fm2 == 0x1874ed and fs3 == 1 and fe3 == 0xce and fm3 == 0x7ff000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e56eede; op2val:0xc09874ed;
op3val:0xe77ff000; valaddr_reg:x3; val_offset:31680*0 + 3*576*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 31680*0 + 3*576*FLEN/8, x4, x1, x2)

inst_10561:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x56eede and fs2 == 1 and fe2 == 0x81 and fm2 == 0x1874ed and fs3 == 1 and fe3 == 0xce and fm3 == 0x7ff800 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e56eede; op2val:0xc09874ed;
op3val:0xe77ff800; valaddr_reg:x3; val_offset:31683*0 + 3*577*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 31683*0 + 3*577*FLEN/8, x4, x1, x2)

inst_10562:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x56eede and fs2 == 1 and fe2 == 0x81 and fm2 == 0x1874ed and fs3 == 1 and fe3 == 0xce and fm3 == 0x7ffc00 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e56eede; op2val:0xc09874ed;
op3val:0xe77ffc00; valaddr_reg:x3; val_offset:31686*0 + 3*578*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 31686*0 + 3*578*FLEN/8, x4, x1, x2)

inst_10563:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x56eede and fs2 == 1 and fe2 == 0x81 and fm2 == 0x1874ed and fs3 == 1 and fe3 == 0xce and fm3 == 0x7ffe00 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e56eede; op2val:0xc09874ed;
op3val:0xe77ffe00; valaddr_reg:x3; val_offset:31689*0 + 3*579*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 31689*0 + 3*579*FLEN/8, x4, x1, x2)

inst_10564:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x56eede and fs2 == 1 and fe2 == 0x81 and fm2 == 0x1874ed and fs3 == 1 and fe3 == 0xce and fm3 == 0x7fff00 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e56eede; op2val:0xc09874ed;
op3val:0xe77fff00; valaddr_reg:x3; val_offset:31692*0 + 3*580*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 31692*0 + 3*580*FLEN/8, x4, x1, x2)

inst_10565:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x56eede and fs2 == 1 and fe2 == 0x81 and fm2 == 0x1874ed and fs3 == 1 and fe3 == 0xce and fm3 == 0x7fff80 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e56eede; op2val:0xc09874ed;
op3val:0xe77fff80; valaddr_reg:x3; val_offset:31695*0 + 3*581*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 31695*0 + 3*581*FLEN/8, x4, x1, x2)

inst_10566:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x56eede and fs2 == 1 and fe2 == 0x81 and fm2 == 0x1874ed and fs3 == 1 and fe3 == 0xce and fm3 == 0x7fffc0 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e56eede; op2val:0xc09874ed;
op3val:0xe77fffc0; valaddr_reg:x3; val_offset:31698*0 + 3*582*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 31698*0 + 3*582*FLEN/8, x4, x1, x2)

inst_10567:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x56eede and fs2 == 1 and fe2 == 0x81 and fm2 == 0x1874ed and fs3 == 1 and fe3 == 0xce and fm3 == 0x7fffe0 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e56eede; op2val:0xc09874ed;
op3val:0xe77fffe0; valaddr_reg:x3; val_offset:31701*0 + 3*583*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 31701*0 + 3*583*FLEN/8, x4, x1, x2)

inst_10568:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x56eede and fs2 == 1 and fe2 == 0x81 and fm2 == 0x1874ed and fs3 == 1 and fe3 == 0xce and fm3 == 0x7ffff0 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e56eede; op2val:0xc09874ed;
op3val:0xe77ffff0; valaddr_reg:x3; val_offset:31704*0 + 3*584*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 31704*0 + 3*584*FLEN/8, x4, x1, x2)

inst_10569:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x56eede and fs2 == 1 and fe2 == 0x81 and fm2 == 0x1874ed and fs3 == 1 and fe3 == 0xce and fm3 == 0x7ffff8 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e56eede; op2val:0xc09874ed;
op3val:0xe77ffff8; valaddr_reg:x3; val_offset:31707*0 + 3*585*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 31707*0 + 3*585*FLEN/8, x4, x1, x2)

inst_10570:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x56eede and fs2 == 1 and fe2 == 0x81 and fm2 == 0x1874ed and fs3 == 1 and fe3 == 0xce and fm3 == 0x7ffffc and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e56eede; op2val:0xc09874ed;
op3val:0xe77ffffc; valaddr_reg:x3; val_offset:31710*0 + 3*586*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 31710*0 + 3*586*FLEN/8, x4, x1, x2)

inst_10571:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x56eede and fs2 == 1 and fe2 == 0x81 and fm2 == 0x1874ed and fs3 == 1 and fe3 == 0xce and fm3 == 0x7ffffe and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e56eede; op2val:0xc09874ed;
op3val:0xe77ffffe; valaddr_reg:x3; val_offset:31713*0 + 3*587*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 31713*0 + 3*587*FLEN/8, x4, x1, x2)

inst_10572:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x56eede and fs2 == 1 and fe2 == 0x81 and fm2 == 0x1874ed and fs3 == 1 and fe3 == 0xce and fm3 == 0x7fffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e56eede; op2val:0xc09874ed;
op3val:0xe77fffff; valaddr_reg:x3; val_offset:31716*0 + 3*588*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 31716*0 + 3*588*FLEN/8, x4, x1, x2)

inst_10573:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x56eede and fs2 == 1 and fe2 == 0x81 and fm2 == 0x1874ed and fs3 == 1 and fe3 == 0xfe and fm3 == 0x000001 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e56eede; op2val:0xc09874ed;
op3val:0xff000001; valaddr_reg:x3; val_offset:31719*0 + 3*589*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 31719*0 + 3*589*FLEN/8, x4, x1, x2)

inst_10574:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x56eede and fs2 == 1 and fe2 == 0x81 and fm2 == 0x1874ed and fs3 == 1 and fe3 == 0xfe and fm3 == 0x000003 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e56eede; op2val:0xc09874ed;
op3val:0xff000003; valaddr_reg:x3; val_offset:31722*0 + 3*590*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 31722*0 + 3*590*FLEN/8, x4, x1, x2)

inst_10575:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x56eede and fs2 == 1 and fe2 == 0x81 and fm2 == 0x1874ed and fs3 == 1 and fe3 == 0xfe and fm3 == 0x000007 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e56eede; op2val:0xc09874ed;
op3val:0xff000007; valaddr_reg:x3; val_offset:31725*0 + 3*591*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 31725*0 + 3*591*FLEN/8, x4, x1, x2)

inst_10576:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x56eede and fs2 == 1 and fe2 == 0x81 and fm2 == 0x1874ed and fs3 == 1 and fe3 == 0xfe and fm3 == 0x199999 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e56eede; op2val:0xc09874ed;
op3val:0xff199999; valaddr_reg:x3; val_offset:31728*0 + 3*592*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 31728*0 + 3*592*FLEN/8, x4, x1, x2)

inst_10577:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x56eede and fs2 == 1 and fe2 == 0x81 and fm2 == 0x1874ed and fs3 == 1 and fe3 == 0xfe and fm3 == 0x249249 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e56eede; op2val:0xc09874ed;
op3val:0xff249249; valaddr_reg:x3; val_offset:31731*0 + 3*593*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 31731*0 + 3*593*FLEN/8, x4, x1, x2)

inst_10578:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x56eede and fs2 == 1 and fe2 == 0x81 and fm2 == 0x1874ed and fs3 == 1 and fe3 == 0xfe and fm3 == 0x333333 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e56eede; op2val:0xc09874ed;
op3val:0xff333333; valaddr_reg:x3; val_offset:31734*0 + 3*594*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 31734*0 + 3*594*FLEN/8, x4, x1, x2)

inst_10579:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x56eede and fs2 == 1 and fe2 == 0x81 and fm2 == 0x1874ed and fs3 == 1 and fe3 == 0xfe and fm3 == 0x36db6d and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e56eede; op2val:0xc09874ed;
op3val:0xff36db6d; valaddr_reg:x3; val_offset:31737*0 + 3*595*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 31737*0 + 3*595*FLEN/8, x4, x1, x2)

inst_10580:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x56eede and fs2 == 1 and fe2 == 0x81 and fm2 == 0x1874ed and fs3 == 1 and fe3 == 0xfe and fm3 == 0x3bbbbb and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e56eede; op2val:0xc09874ed;
op3val:0xff3bbbbb; valaddr_reg:x3; val_offset:31740*0 + 3*596*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 31740*0 + 3*596*FLEN/8, x4, x1, x2)

inst_10581:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x56eede and fs2 == 1 and fe2 == 0x81 and fm2 == 0x1874ed and fs3 == 1 and fe3 == 0xfe and fm3 == 0x444444 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e56eede; op2val:0xc09874ed;
op3val:0xff444444; valaddr_reg:x3; val_offset:31743*0 + 3*597*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 31743*0 + 3*597*FLEN/8, x4, x1, x2)

inst_10582:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x56eede and fs2 == 1 and fe2 == 0x81 and fm2 == 0x1874ed and fs3 == 1 and fe3 == 0xfe and fm3 == 0x4ccccc and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e56eede; op2val:0xc09874ed;
op3val:0xff4ccccc; valaddr_reg:x3; val_offset:31746*0 + 3*598*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 31746*0 + 3*598*FLEN/8, x4, x1, x2)

inst_10583:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x56eede and fs2 == 1 and fe2 == 0x81 and fm2 == 0x1874ed and fs3 == 1 and fe3 == 0xfe and fm3 == 0x5b6db6 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e56eede; op2val:0xc09874ed;
op3val:0xff5b6db6; valaddr_reg:x3; val_offset:31749*0 + 3*599*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 31749*0 + 3*599*FLEN/8, x4, x1, x2)

inst_10584:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x56eede and fs2 == 1 and fe2 == 0x81 and fm2 == 0x1874ed and fs3 == 1 and fe3 == 0xfe and fm3 == 0x666666 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e56eede; op2val:0xc09874ed;
op3val:0xff666666; valaddr_reg:x3; val_offset:31752*0 + 3*600*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 31752*0 + 3*600*FLEN/8, x4, x1, x2)

inst_10585:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x56eede and fs2 == 1 and fe2 == 0x81 and fm2 == 0x1874ed and fs3 == 1 and fe3 == 0xfe and fm3 == 0x6db6db and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e56eede; op2val:0xc09874ed;
op3val:0xff6db6db; valaddr_reg:x3; val_offset:31755*0 + 3*601*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 31755*0 + 3*601*FLEN/8, x4, x1, x2)

inst_10586:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x56eede and fs2 == 1 and fe2 == 0x81 and fm2 == 0x1874ed and fs3 == 1 and fe3 == 0xfe and fm3 == 0x7ffff8 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e56eede; op2val:0xc09874ed;
op3val:0xff7ffff8; valaddr_reg:x3; val_offset:31758*0 + 3*602*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 31758*0 + 3*602*FLEN/8, x4, x1, x2)

inst_10587:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x56eede and fs2 == 1 and fe2 == 0x81 and fm2 == 0x1874ed and fs3 == 1 and fe3 == 0xfe and fm3 == 0x7ffffc and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e56eede; op2val:0xc09874ed;
op3val:0xff7ffffc; valaddr_reg:x3; val_offset:31761*0 + 3*603*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 31761*0 + 3*603*FLEN/8, x4, x1, x2)

inst_10588:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x56eede and fs2 == 1 and fe2 == 0x81 and fm2 == 0x1874ed and fs3 == 1 and fe3 == 0xfe and fm3 == 0x7ffffe and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e56eede; op2val:0xc09874ed;
op3val:0xff7ffffe; valaddr_reg:x3; val_offset:31764*0 + 3*604*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 31764*0 + 3*604*FLEN/8, x4, x1, x2)

inst_10589:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x579c96 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000001 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e579c96; op2val:0x0;
op3val:0x800001; valaddr_reg:x3; val_offset:31767*0 + 3*605*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 31767*0 + 3*605*FLEN/8, x4, x1, x2)

inst_10590:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x579c96 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000003 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e579c96; op2val:0x0;
op3val:0x800003; valaddr_reg:x3; val_offset:31770*0 + 3*606*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 31770*0 + 3*606*FLEN/8, x4, x1, x2)

inst_10591:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x579c96 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000007 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e579c96; op2val:0x0;
op3val:0x800007; valaddr_reg:x3; val_offset:31773*0 + 3*607*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 31773*0 + 3*607*FLEN/8, x4, x1, x2)

inst_10592:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x579c96 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x199999 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e579c96; op2val:0x0;
op3val:0x999999; valaddr_reg:x3; val_offset:31776*0 + 3*608*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 31776*0 + 3*608*FLEN/8, x4, x1, x2)

inst_10593:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x579c96 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x249249 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e579c96; op2val:0x0;
op3val:0xa49249; valaddr_reg:x3; val_offset:31779*0 + 3*609*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 31779*0 + 3*609*FLEN/8, x4, x1, x2)

inst_10594:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x579c96 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x333333 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e579c96; op2val:0x0;
op3val:0xb33333; valaddr_reg:x3; val_offset:31782*0 + 3*610*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 31782*0 + 3*610*FLEN/8, x4, x1, x2)

inst_10595:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x579c96 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x36db6d and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e579c96; op2val:0x0;
op3val:0xb6db6d; valaddr_reg:x3; val_offset:31785*0 + 3*611*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 31785*0 + 3*611*FLEN/8, x4, x1, x2)

inst_10596:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x579c96 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x3bbbbb and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e579c96; op2val:0x0;
op3val:0xbbbbbb; valaddr_reg:x3; val_offset:31788*0 + 3*612*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 31788*0 + 3*612*FLEN/8, x4, x1, x2)

inst_10597:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x579c96 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x444444 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e579c96; op2val:0x0;
op3val:0xc44444; valaddr_reg:x3; val_offset:31791*0 + 3*613*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 31791*0 + 3*613*FLEN/8, x4, x1, x2)

inst_10598:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x579c96 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x4ccccc and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e579c96; op2val:0x0;
op3val:0xcccccc; valaddr_reg:x3; val_offset:31794*0 + 3*614*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 31794*0 + 3*614*FLEN/8, x4, x1, x2)

inst_10599:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x579c96 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x5b6db6 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e579c96; op2val:0x0;
op3val:0xdb6db6; valaddr_reg:x3; val_offset:31797*0 + 3*615*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 31797*0 + 3*615*FLEN/8, x4, x1, x2)

inst_10600:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x579c96 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x666666 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e579c96; op2val:0x0;
op3val:0xe66666; valaddr_reg:x3; val_offset:31800*0 + 3*616*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 31800*0 + 3*616*FLEN/8, x4, x1, x2)

inst_10601:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x579c96 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x6db6db and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e579c96; op2val:0x0;
op3val:0xedb6db; valaddr_reg:x3; val_offset:31803*0 + 3*617*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 31803*0 + 3*617*FLEN/8, x4, x1, x2)

inst_10602:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x579c96 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x7ffff8 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e579c96; op2val:0x0;
op3val:0xfffff8; valaddr_reg:x3; val_offset:31806*0 + 3*618*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 31806*0 + 3*618*FLEN/8, x4, x1, x2)

inst_10603:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x579c96 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x7ffffc and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e579c96; op2val:0x0;
op3val:0xfffffc; valaddr_reg:x3; val_offset:31809*0 + 3*619*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 31809*0 + 3*619*FLEN/8, x4, x1, x2)

inst_10604:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x579c96 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x7ffffe and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e579c96; op2val:0x0;
op3val:0xfffffe; valaddr_reg:x3; val_offset:31812*0 + 3*620*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 31812*0 + 3*620*FLEN/8, x4, x1, x2)

inst_10605:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x579c96 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x000000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e579c96; op2val:0x0;
op3val:0x7000000; valaddr_reg:x3; val_offset:31815*0 + 3*621*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 31815*0 + 3*621*FLEN/8, x4, x1, x2)

inst_10606:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x579c96 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x000001 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e579c96; op2val:0x0;
op3val:0x7000001; valaddr_reg:x3; val_offset:31818*0 + 3*622*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 31818*0 + 3*622*FLEN/8, x4, x1, x2)

inst_10607:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x579c96 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x000003 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e579c96; op2val:0x0;
op3val:0x7000003; valaddr_reg:x3; val_offset:31821*0 + 3*623*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 31821*0 + 3*623*FLEN/8, x4, x1, x2)

inst_10608:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x579c96 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x000007 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e579c96; op2val:0x0;
op3val:0x7000007; valaddr_reg:x3; val_offset:31824*0 + 3*624*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 31824*0 + 3*624*FLEN/8, x4, x1, x2)

inst_10609:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x579c96 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x00000f and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e579c96; op2val:0x0;
op3val:0x700000f; valaddr_reg:x3; val_offset:31827*0 + 3*625*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 31827*0 + 3*625*FLEN/8, x4, x1, x2)

inst_10610:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x579c96 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x00001f and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e579c96; op2val:0x0;
op3val:0x700001f; valaddr_reg:x3; val_offset:31830*0 + 3*626*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 31830*0 + 3*626*FLEN/8, x4, x1, x2)

inst_10611:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x579c96 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x00003f and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e579c96; op2val:0x0;
op3val:0x700003f; valaddr_reg:x3; val_offset:31833*0 + 3*627*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 31833*0 + 3*627*FLEN/8, x4, x1, x2)

inst_10612:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x579c96 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x00007f and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e579c96; op2val:0x0;
op3val:0x700007f; valaddr_reg:x3; val_offset:31836*0 + 3*628*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 31836*0 + 3*628*FLEN/8, x4, x1, x2)

inst_10613:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x579c96 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x0000ff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e579c96; op2val:0x0;
op3val:0x70000ff; valaddr_reg:x3; val_offset:31839*0 + 3*629*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 31839*0 + 3*629*FLEN/8, x4, x1, x2)

inst_10614:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x579c96 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x0001ff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e579c96; op2val:0x0;
op3val:0x70001ff; valaddr_reg:x3; val_offset:31842*0 + 3*630*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 31842*0 + 3*630*FLEN/8, x4, x1, x2)

inst_10615:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x579c96 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x0003ff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e579c96; op2val:0x0;
op3val:0x70003ff; valaddr_reg:x3; val_offset:31845*0 + 3*631*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 31845*0 + 3*631*FLEN/8, x4, x1, x2)

inst_10616:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x579c96 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x0007ff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e579c96; op2val:0x0;
op3val:0x70007ff; valaddr_reg:x3; val_offset:31848*0 + 3*632*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 31848*0 + 3*632*FLEN/8, x4, x1, x2)

inst_10617:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x579c96 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x000fff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e579c96; op2val:0x0;
op3val:0x7000fff; valaddr_reg:x3; val_offset:31851*0 + 3*633*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 31851*0 + 3*633*FLEN/8, x4, x1, x2)

inst_10618:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x579c96 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x001fff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e579c96; op2val:0x0;
op3val:0x7001fff; valaddr_reg:x3; val_offset:31854*0 + 3*634*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 31854*0 + 3*634*FLEN/8, x4, x1, x2)

inst_10619:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x579c96 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x003fff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e579c96; op2val:0x0;
op3val:0x7003fff; valaddr_reg:x3; val_offset:31857*0 + 3*635*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 31857*0 + 3*635*FLEN/8, x4, x1, x2)

inst_10620:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x579c96 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x007fff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e579c96; op2val:0x0;
op3val:0x7007fff; valaddr_reg:x3; val_offset:31860*0 + 3*636*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 31860*0 + 3*636*FLEN/8, x4, x1, x2)

inst_10621:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x579c96 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x00ffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e579c96; op2val:0x0;
op3val:0x700ffff; valaddr_reg:x3; val_offset:31863*0 + 3*637*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 31863*0 + 3*637*FLEN/8, x4, x1, x2)

inst_10622:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x579c96 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x01ffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e579c96; op2val:0x0;
op3val:0x701ffff; valaddr_reg:x3; val_offset:31866*0 + 3*638*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 31866*0 + 3*638*FLEN/8, x4, x1, x2)

inst_10623:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x579c96 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x03ffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e579c96; op2val:0x0;
op3val:0x703ffff; valaddr_reg:x3; val_offset:31869*0 + 3*639*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 31869*0 + 3*639*FLEN/8, x4, x1, x2)
RVTEST_SIGBASE(x1,signature_x1_6)

inst_10624:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x579c96 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x07ffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e579c96; op2val:0x0;
op3val:0x707ffff; valaddr_reg:x3; val_offset:31872*0 + 3*640*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 31872*0 + 3*640*FLEN/8, x4, x1, x2)

inst_10625:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x579c96 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x0fffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e579c96; op2val:0x0;
op3val:0x70fffff; valaddr_reg:x3; val_offset:31875*0 + 3*641*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 31875*0 + 3*641*FLEN/8, x4, x1, x2)

inst_10626:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x579c96 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x1fffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e579c96; op2val:0x0;
op3val:0x71fffff; valaddr_reg:x3; val_offset:31878*0 + 3*642*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 31878*0 + 3*642*FLEN/8, x4, x1, x2)

inst_10627:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x579c96 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x3fffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e579c96; op2val:0x0;
op3val:0x73fffff; valaddr_reg:x3; val_offset:31881*0 + 3*643*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 31881*0 + 3*643*FLEN/8, x4, x1, x2)

inst_10628:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x579c96 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x400000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e579c96; op2val:0x0;
op3val:0x7400000; valaddr_reg:x3; val_offset:31884*0 + 3*644*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 31884*0 + 3*644*FLEN/8, x4, x1, x2)

inst_10629:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x579c96 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x600000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e579c96; op2val:0x0;
op3val:0x7600000; valaddr_reg:x3; val_offset:31887*0 + 3*645*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 31887*0 + 3*645*FLEN/8, x4, x1, x2)

inst_10630:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x579c96 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x700000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e579c96; op2val:0x0;
op3val:0x7700000; valaddr_reg:x3; val_offset:31890*0 + 3*646*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 31890*0 + 3*646*FLEN/8, x4, x1, x2)

inst_10631:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x579c96 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x780000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e579c96; op2val:0x0;
op3val:0x7780000; valaddr_reg:x3; val_offset:31893*0 + 3*647*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 31893*0 + 3*647*FLEN/8, x4, x1, x2)

inst_10632:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x579c96 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x7c0000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e579c96; op2val:0x0;
op3val:0x77c0000; valaddr_reg:x3; val_offset:31896*0 + 3*648*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 31896*0 + 3*648*FLEN/8, x4, x1, x2)

inst_10633:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x579c96 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x7e0000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e579c96; op2val:0x0;
op3val:0x77e0000; valaddr_reg:x3; val_offset:31899*0 + 3*649*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 31899*0 + 3*649*FLEN/8, x4, x1, x2)

inst_10634:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x579c96 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x7f0000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e579c96; op2val:0x0;
op3val:0x77f0000; valaddr_reg:x3; val_offset:31902*0 + 3*650*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 31902*0 + 3*650*FLEN/8, x4, x1, x2)

inst_10635:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x579c96 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x7f8000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e579c96; op2val:0x0;
op3val:0x77f8000; valaddr_reg:x3; val_offset:31905*0 + 3*651*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 31905*0 + 3*651*FLEN/8, x4, x1, x2)

inst_10636:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x579c96 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x7fc000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e579c96; op2val:0x0;
op3val:0x77fc000; valaddr_reg:x3; val_offset:31908*0 + 3*652*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 31908*0 + 3*652*FLEN/8, x4, x1, x2)

inst_10637:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x579c96 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x7fe000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e579c96; op2val:0x0;
op3val:0x77fe000; valaddr_reg:x3; val_offset:31911*0 + 3*653*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 31911*0 + 3*653*FLEN/8, x4, x1, x2)

inst_10638:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x579c96 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x7ff000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e579c96; op2val:0x0;
op3val:0x77ff000; valaddr_reg:x3; val_offset:31914*0 + 3*654*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 31914*0 + 3*654*FLEN/8, x4, x1, x2)

inst_10639:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x579c96 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x7ff800 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e579c96; op2val:0x0;
op3val:0x77ff800; valaddr_reg:x3; val_offset:31917*0 + 3*655*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 31917*0 + 3*655*FLEN/8, x4, x1, x2)

inst_10640:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x579c96 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x7ffc00 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e579c96; op2val:0x0;
op3val:0x77ffc00; valaddr_reg:x3; val_offset:31920*0 + 3*656*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 31920*0 + 3*656*FLEN/8, x4, x1, x2)

inst_10641:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x579c96 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x7ffe00 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e579c96; op2val:0x0;
op3val:0x77ffe00; valaddr_reg:x3; val_offset:31923*0 + 3*657*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 31923*0 + 3*657*FLEN/8, x4, x1, x2)

inst_10642:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x579c96 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x7fff00 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e579c96; op2val:0x0;
op3val:0x77fff00; valaddr_reg:x3; val_offset:31926*0 + 3*658*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 31926*0 + 3*658*FLEN/8, x4, x1, x2)

inst_10643:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x579c96 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x7fff80 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e579c96; op2val:0x0;
op3val:0x77fff80; valaddr_reg:x3; val_offset:31929*0 + 3*659*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 31929*0 + 3*659*FLEN/8, x4, x1, x2)

inst_10644:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x579c96 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x7fffc0 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e579c96; op2val:0x0;
op3val:0x77fffc0; valaddr_reg:x3; val_offset:31932*0 + 3*660*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 31932*0 + 3*660*FLEN/8, x4, x1, x2)

inst_10645:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x579c96 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x7fffe0 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e579c96; op2val:0x0;
op3val:0x77fffe0; valaddr_reg:x3; val_offset:31935*0 + 3*661*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 31935*0 + 3*661*FLEN/8, x4, x1, x2)

inst_10646:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x579c96 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x7ffff0 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e579c96; op2val:0x0;
op3val:0x77ffff0; valaddr_reg:x3; val_offset:31938*0 + 3*662*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 31938*0 + 3*662*FLEN/8, x4, x1, x2)

inst_10647:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x579c96 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x7ffff8 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e579c96; op2val:0x0;
op3val:0x77ffff8; valaddr_reg:x3; val_offset:31941*0 + 3*663*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 31941*0 + 3*663*FLEN/8, x4, x1, x2)

inst_10648:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x579c96 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x7ffffc and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e579c96; op2val:0x0;
op3val:0x77ffffc; valaddr_reg:x3; val_offset:31944*0 + 3*664*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 31944*0 + 3*664*FLEN/8, x4, x1, x2)

inst_10649:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x579c96 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x7ffffe and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e579c96; op2val:0x0;
op3val:0x77ffffe; valaddr_reg:x3; val_offset:31947*0 + 3*665*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 31947*0 + 3*665*FLEN/8, x4, x1, x2)

inst_10650:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x579c96 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x7fffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e579c96; op2val:0x0;
op3val:0x77fffff; valaddr_reg:x3; val_offset:31950*0 + 3*666*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 31950*0 + 3*666*FLEN/8, x4, x1, x2)

inst_10651:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x591432 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000001 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e591432; op2val:0x0;
op3val:0x1; valaddr_reg:x3; val_offset:31953*0 + 3*667*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 31953*0 + 3*667*FLEN/8, x4, x1, x2)

inst_10652:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x591432 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000003 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e591432; op2val:0x0;
op3val:0x3; valaddr_reg:x3; val_offset:31956*0 + 3*668*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 31956*0 + 3*668*FLEN/8, x4, x1, x2)

inst_10653:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x591432 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000007 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e591432; op2val:0x0;
op3val:0x7; valaddr_reg:x3; val_offset:31959*0 + 3*669*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 31959*0 + 3*669*FLEN/8, x4, x1, x2)

inst_10654:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x591432 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x199999 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e591432; op2val:0x0;
op3val:0x199999; valaddr_reg:x3; val_offset:31962*0 + 3*670*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 31962*0 + 3*670*FLEN/8, x4, x1, x2)

inst_10655:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x591432 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x249249 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e591432; op2val:0x0;
op3val:0x249249; valaddr_reg:x3; val_offset:31965*0 + 3*671*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 31965*0 + 3*671*FLEN/8, x4, x1, x2)

inst_10656:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x591432 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x333333 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e591432; op2val:0x0;
op3val:0x333333; valaddr_reg:x3; val_offset:31968*0 + 3*672*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 31968*0 + 3*672*FLEN/8, x4, x1, x2)

inst_10657:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x591432 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x36db6d and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e591432; op2val:0x0;
op3val:0x36db6d; valaddr_reg:x3; val_offset:31971*0 + 3*673*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 31971*0 + 3*673*FLEN/8, x4, x1, x2)

inst_10658:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x591432 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x3bbbbb and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e591432; op2val:0x0;
op3val:0x3bbbbb; valaddr_reg:x3; val_offset:31974*0 + 3*674*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 31974*0 + 3*674*FLEN/8, x4, x1, x2)

inst_10659:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x591432 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x444444 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e591432; op2val:0x0;
op3val:0x444444; valaddr_reg:x3; val_offset:31977*0 + 3*675*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 31977*0 + 3*675*FLEN/8, x4, x1, x2)

inst_10660:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x591432 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x4ccccc and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e591432; op2val:0x0;
op3val:0x4ccccc; valaddr_reg:x3; val_offset:31980*0 + 3*676*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 31980*0 + 3*676*FLEN/8, x4, x1, x2)

inst_10661:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x591432 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x5b6db6 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e591432; op2val:0x0;
op3val:0x5b6db6; valaddr_reg:x3; val_offset:31983*0 + 3*677*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 31983*0 + 3*677*FLEN/8, x4, x1, x2)

inst_10662:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x591432 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x666666 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e591432; op2val:0x0;
op3val:0x666666; valaddr_reg:x3; val_offset:31986*0 + 3*678*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 31986*0 + 3*678*FLEN/8, x4, x1, x2)

inst_10663:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x591432 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x6db6db and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e591432; op2val:0x0;
op3val:0x6db6db; valaddr_reg:x3; val_offset:31989*0 + 3*679*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 31989*0 + 3*679*FLEN/8, x4, x1, x2)

inst_10664:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x591432 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x7ffff8 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e591432; op2val:0x0;
op3val:0x7ffff8; valaddr_reg:x3; val_offset:31992*0 + 3*680*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 31992*0 + 3*680*FLEN/8, x4, x1, x2)

inst_10665:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x591432 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x7ffffc and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e591432; op2val:0x0;
op3val:0x7ffffc; valaddr_reg:x3; val_offset:31995*0 + 3*681*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 31995*0 + 3*681*FLEN/8, x4, x1, x2)

inst_10666:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x591432 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x7ffffe and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e591432; op2val:0x0;
op3val:0x7ffffe; valaddr_reg:x3; val_offset:31998*0 + 3*682*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 31998*0 + 3*682*FLEN/8, x4, x1, x2)

inst_10667:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x591432 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x17 and fm3 == 0x000000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e591432; op2val:0x0;
op3val:0xb800000; valaddr_reg:x3; val_offset:32001*0 + 3*683*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 32001*0 + 3*683*FLEN/8, x4, x1, x2)

inst_10668:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x591432 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x17 and fm3 == 0x000001 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e591432; op2val:0x0;
op3val:0xb800001; valaddr_reg:x3; val_offset:32004*0 + 3*684*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 32004*0 + 3*684*FLEN/8, x4, x1, x2)

inst_10669:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x591432 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x17 and fm3 == 0x000003 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e591432; op2val:0x0;
op3val:0xb800003; valaddr_reg:x3; val_offset:32007*0 + 3*685*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 32007*0 + 3*685*FLEN/8, x4, x1, x2)

inst_10670:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x591432 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x17 and fm3 == 0x000007 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e591432; op2val:0x0;
op3val:0xb800007; valaddr_reg:x3; val_offset:32010*0 + 3*686*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 32010*0 + 3*686*FLEN/8, x4, x1, x2)

inst_10671:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x591432 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x17 and fm3 == 0x00000f and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e591432; op2val:0x0;
op3val:0xb80000f; valaddr_reg:x3; val_offset:32013*0 + 3*687*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 32013*0 + 3*687*FLEN/8, x4, x1, x2)

inst_10672:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x591432 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x17 and fm3 == 0x00001f and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e591432; op2val:0x0;
op3val:0xb80001f; valaddr_reg:x3; val_offset:32016*0 + 3*688*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 32016*0 + 3*688*FLEN/8, x4, x1, x2)

inst_10673:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x591432 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x17 and fm3 == 0x00003f and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e591432; op2val:0x0;
op3val:0xb80003f; valaddr_reg:x3; val_offset:32019*0 + 3*689*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 32019*0 + 3*689*FLEN/8, x4, x1, x2)

inst_10674:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x591432 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x17 and fm3 == 0x00007f and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e591432; op2val:0x0;
op3val:0xb80007f; valaddr_reg:x3; val_offset:32022*0 + 3*690*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 32022*0 + 3*690*FLEN/8, x4, x1, x2)

inst_10675:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x591432 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x17 and fm3 == 0x0000ff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e591432; op2val:0x0;
op3val:0xb8000ff; valaddr_reg:x3; val_offset:32025*0 + 3*691*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 32025*0 + 3*691*FLEN/8, x4, x1, x2)

inst_10676:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x591432 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x17 and fm3 == 0x0001ff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e591432; op2val:0x0;
op3val:0xb8001ff; valaddr_reg:x3; val_offset:32028*0 + 3*692*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 32028*0 + 3*692*FLEN/8, x4, x1, x2)

inst_10677:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x591432 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x17 and fm3 == 0x0003ff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e591432; op2val:0x0;
op3val:0xb8003ff; valaddr_reg:x3; val_offset:32031*0 + 3*693*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 32031*0 + 3*693*FLEN/8, x4, x1, x2)

inst_10678:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x591432 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x17 and fm3 == 0x0007ff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e591432; op2val:0x0;
op3val:0xb8007ff; valaddr_reg:x3; val_offset:32034*0 + 3*694*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 32034*0 + 3*694*FLEN/8, x4, x1, x2)

inst_10679:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x591432 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x17 and fm3 == 0x000fff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e591432; op2val:0x0;
op3val:0xb800fff; valaddr_reg:x3; val_offset:32037*0 + 3*695*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 32037*0 + 3*695*FLEN/8, x4, x1, x2)

inst_10680:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x591432 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x17 and fm3 == 0x001fff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e591432; op2val:0x0;
op3val:0xb801fff; valaddr_reg:x3; val_offset:32040*0 + 3*696*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 32040*0 + 3*696*FLEN/8, x4, x1, x2)

inst_10681:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x591432 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x17 and fm3 == 0x003fff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e591432; op2val:0x0;
op3val:0xb803fff; valaddr_reg:x3; val_offset:32043*0 + 3*697*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 32043*0 + 3*697*FLEN/8, x4, x1, x2)

inst_10682:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x591432 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x17 and fm3 == 0x007fff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e591432; op2val:0x0;
op3val:0xb807fff; valaddr_reg:x3; val_offset:32046*0 + 3*698*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 32046*0 + 3*698*FLEN/8, x4, x1, x2)

inst_10683:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x591432 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x17 and fm3 == 0x00ffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e591432; op2val:0x0;
op3val:0xb80ffff; valaddr_reg:x3; val_offset:32049*0 + 3*699*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 32049*0 + 3*699*FLEN/8, x4, x1, x2)

inst_10684:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x591432 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x17 and fm3 == 0x01ffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e591432; op2val:0x0;
op3val:0xb81ffff; valaddr_reg:x3; val_offset:32052*0 + 3*700*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 32052*0 + 3*700*FLEN/8, x4, x1, x2)

inst_10685:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x591432 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x17 and fm3 == 0x03ffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e591432; op2val:0x0;
op3val:0xb83ffff; valaddr_reg:x3; val_offset:32055*0 + 3*701*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 32055*0 + 3*701*FLEN/8, x4, x1, x2)

inst_10686:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x591432 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x17 and fm3 == 0x07ffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e591432; op2val:0x0;
op3val:0xb87ffff; valaddr_reg:x3; val_offset:32058*0 + 3*702*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 32058*0 + 3*702*FLEN/8, x4, x1, x2)

inst_10687:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x591432 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x17 and fm3 == 0x0fffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e591432; op2val:0x0;
op3val:0xb8fffff; valaddr_reg:x3; val_offset:32061*0 + 3*703*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 32061*0 + 3*703*FLEN/8, x4, x1, x2)

inst_10688:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x591432 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x17 and fm3 == 0x1fffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e591432; op2val:0x0;
op3val:0xb9fffff; valaddr_reg:x3; val_offset:32064*0 + 3*704*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 32064*0 + 3*704*FLEN/8, x4, x1, x2)

inst_10689:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x591432 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x17 and fm3 == 0x3fffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e591432; op2val:0x0;
op3val:0xbbfffff; valaddr_reg:x3; val_offset:32067*0 + 3*705*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 32067*0 + 3*705*FLEN/8, x4, x1, x2)

inst_10690:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x591432 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x17 and fm3 == 0x400000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e591432; op2val:0x0;
op3val:0xbc00000; valaddr_reg:x3; val_offset:32070*0 + 3*706*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 32070*0 + 3*706*FLEN/8, x4, x1, x2)

inst_10691:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x591432 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x17 and fm3 == 0x600000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e591432; op2val:0x0;
op3val:0xbe00000; valaddr_reg:x3; val_offset:32073*0 + 3*707*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 32073*0 + 3*707*FLEN/8, x4, x1, x2)

inst_10692:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x591432 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x17 and fm3 == 0x700000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e591432; op2val:0x0;
op3val:0xbf00000; valaddr_reg:x3; val_offset:32076*0 + 3*708*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 32076*0 + 3*708*FLEN/8, x4, x1, x2)

inst_10693:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x591432 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x17 and fm3 == 0x780000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e591432; op2val:0x0;
op3val:0xbf80000; valaddr_reg:x3; val_offset:32079*0 + 3*709*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 32079*0 + 3*709*FLEN/8, x4, x1, x2)

inst_10694:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x591432 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x17 and fm3 == 0x7c0000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e591432; op2val:0x0;
op3val:0xbfc0000; valaddr_reg:x3; val_offset:32082*0 + 3*710*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 32082*0 + 3*710*FLEN/8, x4, x1, x2)

inst_10695:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x591432 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x17 and fm3 == 0x7e0000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e591432; op2val:0x0;
op3val:0xbfe0000; valaddr_reg:x3; val_offset:32085*0 + 3*711*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 32085*0 + 3*711*FLEN/8, x4, x1, x2)

inst_10696:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x591432 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x17 and fm3 == 0x7f0000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e591432; op2val:0x0;
op3val:0xbff0000; valaddr_reg:x3; val_offset:32088*0 + 3*712*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 32088*0 + 3*712*FLEN/8, x4, x1, x2)

inst_10697:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x591432 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x17 and fm3 == 0x7f8000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e591432; op2val:0x0;
op3val:0xbff8000; valaddr_reg:x3; val_offset:32091*0 + 3*713*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 32091*0 + 3*713*FLEN/8, x4, x1, x2)

inst_10698:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x591432 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x17 and fm3 == 0x7fc000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e591432; op2val:0x0;
op3val:0xbffc000; valaddr_reg:x3; val_offset:32094*0 + 3*714*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 32094*0 + 3*714*FLEN/8, x4, x1, x2)

inst_10699:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x591432 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x17 and fm3 == 0x7fe000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e591432; op2val:0x0;
op3val:0xbffe000; valaddr_reg:x3; val_offset:32097*0 + 3*715*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 32097*0 + 3*715*FLEN/8, x4, x1, x2)

inst_10700:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x591432 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x17 and fm3 == 0x7ff000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e591432; op2val:0x0;
op3val:0xbfff000; valaddr_reg:x3; val_offset:32100*0 + 3*716*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 32100*0 + 3*716*FLEN/8, x4, x1, x2)

inst_10701:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x591432 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x17 and fm3 == 0x7ff800 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e591432; op2val:0x0;
op3val:0xbfff800; valaddr_reg:x3; val_offset:32103*0 + 3*717*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 32103*0 + 3*717*FLEN/8, x4, x1, x2)

inst_10702:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x591432 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x17 and fm3 == 0x7ffc00 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e591432; op2val:0x0;
op3val:0xbfffc00; valaddr_reg:x3; val_offset:32106*0 + 3*718*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 32106*0 + 3*718*FLEN/8, x4, x1, x2)

inst_10703:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x591432 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x17 and fm3 == 0x7ffe00 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e591432; op2val:0x0;
op3val:0xbfffe00; valaddr_reg:x3; val_offset:32109*0 + 3*719*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 32109*0 + 3*719*FLEN/8, x4, x1, x2)

inst_10704:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x591432 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x17 and fm3 == 0x7fff00 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e591432; op2val:0x0;
op3val:0xbffff00; valaddr_reg:x3; val_offset:32112*0 + 3*720*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 32112*0 + 3*720*FLEN/8, x4, x1, x2)

inst_10705:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x591432 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x17 and fm3 == 0x7fff80 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e591432; op2val:0x0;
op3val:0xbffff80; valaddr_reg:x3; val_offset:32115*0 + 3*721*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 32115*0 + 3*721*FLEN/8, x4, x1, x2)

inst_10706:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x591432 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x17 and fm3 == 0x7fffc0 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e591432; op2val:0x0;
op3val:0xbffffc0; valaddr_reg:x3; val_offset:32118*0 + 3*722*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 32118*0 + 3*722*FLEN/8, x4, x1, x2)

inst_10707:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x591432 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x17 and fm3 == 0x7fffe0 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e591432; op2val:0x0;
op3val:0xbffffe0; valaddr_reg:x3; val_offset:32121*0 + 3*723*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 32121*0 + 3*723*FLEN/8, x4, x1, x2)

inst_10708:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x591432 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x17 and fm3 == 0x7ffff0 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e591432; op2val:0x0;
op3val:0xbfffff0; valaddr_reg:x3; val_offset:32124*0 + 3*724*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 32124*0 + 3*724*FLEN/8, x4, x1, x2)

inst_10709:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x591432 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x17 and fm3 == 0x7ffff8 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e591432; op2val:0x0;
op3val:0xbfffff8; valaddr_reg:x3; val_offset:32127*0 + 3*725*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 32127*0 + 3*725*FLEN/8, x4, x1, x2)

inst_10710:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x591432 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x17 and fm3 == 0x7ffffc and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e591432; op2val:0x0;
op3val:0xbfffffc; valaddr_reg:x3; val_offset:32130*0 + 3*726*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 32130*0 + 3*726*FLEN/8, x4, x1, x2)

inst_10711:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x591432 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x17 and fm3 == 0x7ffffe and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e591432; op2val:0x0;
op3val:0xbfffffe; valaddr_reg:x3; val_offset:32133*0 + 3*727*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 32133*0 + 3*727*FLEN/8, x4, x1, x2)

inst_10712:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x591432 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x17 and fm3 == 0x7fffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e591432; op2val:0x0;
op3val:0xbffffff; valaddr_reg:x3; val_offset:32136*0 + 3*728*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 32136*0 + 3*728*FLEN/8, x4, x1, x2)

inst_10713:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x5bab1f and fs2 == 0 and fe2 == 0x01 and fm2 == 0x152b96 and fs3 == 0 and fe3 == 0x6e and fm3 == 0x000000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e5bab1f; op2val:0x952b96;
op3val:0x37000000; valaddr_reg:x3; val_offset:32139*0 + 3*729*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 32139*0 + 3*729*FLEN/8, x4, x1, x2)

inst_10714:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x5bab1f and fs2 == 0 and fe2 == 0x01 and fm2 == 0x152b96 and fs3 == 0 and fe3 == 0x6e and fm3 == 0x000001 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e5bab1f; op2val:0x952b96;
op3val:0x37000001; valaddr_reg:x3; val_offset:32142*0 + 3*730*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 32142*0 + 3*730*FLEN/8, x4, x1, x2)

inst_10715:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x5bab1f and fs2 == 0 and fe2 == 0x01 and fm2 == 0x152b96 and fs3 == 0 and fe3 == 0x6e and fm3 == 0x000003 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e5bab1f; op2val:0x952b96;
op3val:0x37000003; valaddr_reg:x3; val_offset:32145*0 + 3*731*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 32145*0 + 3*731*FLEN/8, x4, x1, x2)

inst_10716:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x5bab1f and fs2 == 0 and fe2 == 0x01 and fm2 == 0x152b96 and fs3 == 0 and fe3 == 0x6e and fm3 == 0x000007 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e5bab1f; op2val:0x952b96;
op3val:0x37000007; valaddr_reg:x3; val_offset:32148*0 + 3*732*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 32148*0 + 3*732*FLEN/8, x4, x1, x2)

inst_10717:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x5bab1f and fs2 == 0 and fe2 == 0x01 and fm2 == 0x152b96 and fs3 == 0 and fe3 == 0x6e and fm3 == 0x00000f and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e5bab1f; op2val:0x952b96;
op3val:0x3700000f; valaddr_reg:x3; val_offset:32151*0 + 3*733*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 32151*0 + 3*733*FLEN/8, x4, x1, x2)

inst_10718:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x5bab1f and fs2 == 0 and fe2 == 0x01 and fm2 == 0x152b96 and fs3 == 0 and fe3 == 0x6e and fm3 == 0x00001f and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e5bab1f; op2val:0x952b96;
op3val:0x3700001f; valaddr_reg:x3; val_offset:32154*0 + 3*734*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 32154*0 + 3*734*FLEN/8, x4, x1, x2)

inst_10719:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x5bab1f and fs2 == 0 and fe2 == 0x01 and fm2 == 0x152b96 and fs3 == 0 and fe3 == 0x6e and fm3 == 0x00003f and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e5bab1f; op2val:0x952b96;
op3val:0x3700003f; valaddr_reg:x3; val_offset:32157*0 + 3*735*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 32157*0 + 3*735*FLEN/8, x4, x1, x2)

inst_10720:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x5bab1f and fs2 == 0 and fe2 == 0x01 and fm2 == 0x152b96 and fs3 == 0 and fe3 == 0x6e and fm3 == 0x00007f and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e5bab1f; op2val:0x952b96;
op3val:0x3700007f; valaddr_reg:x3; val_offset:32160*0 + 3*736*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 32160*0 + 3*736*FLEN/8, x4, x1, x2)

inst_10721:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x5bab1f and fs2 == 0 and fe2 == 0x01 and fm2 == 0x152b96 and fs3 == 0 and fe3 == 0x6e and fm3 == 0x0000ff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e5bab1f; op2val:0x952b96;
op3val:0x370000ff; valaddr_reg:x3; val_offset:32163*0 + 3*737*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 32163*0 + 3*737*FLEN/8, x4, x1, x2)

inst_10722:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x5bab1f and fs2 == 0 and fe2 == 0x01 and fm2 == 0x152b96 and fs3 == 0 and fe3 == 0x6e and fm3 == 0x0001ff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e5bab1f; op2val:0x952b96;
op3val:0x370001ff; valaddr_reg:x3; val_offset:32166*0 + 3*738*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 32166*0 + 3*738*FLEN/8, x4, x1, x2)

inst_10723:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x5bab1f and fs2 == 0 and fe2 == 0x01 and fm2 == 0x152b96 and fs3 == 0 and fe3 == 0x6e and fm3 == 0x0003ff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e5bab1f; op2val:0x952b96;
op3val:0x370003ff; valaddr_reg:x3; val_offset:32169*0 + 3*739*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 32169*0 + 3*739*FLEN/8, x4, x1, x2)

inst_10724:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x5bab1f and fs2 == 0 and fe2 == 0x01 and fm2 == 0x152b96 and fs3 == 0 and fe3 == 0x6e and fm3 == 0x0007ff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e5bab1f; op2val:0x952b96;
op3val:0x370007ff; valaddr_reg:x3; val_offset:32172*0 + 3*740*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 32172*0 + 3*740*FLEN/8, x4, x1, x2)

inst_10725:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x5bab1f and fs2 == 0 and fe2 == 0x01 and fm2 == 0x152b96 and fs3 == 0 and fe3 == 0x6e and fm3 == 0x000fff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e5bab1f; op2val:0x952b96;
op3val:0x37000fff; valaddr_reg:x3; val_offset:32175*0 + 3*741*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 32175*0 + 3*741*FLEN/8, x4, x1, x2)

inst_10726:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x5bab1f and fs2 == 0 and fe2 == 0x01 and fm2 == 0x152b96 and fs3 == 0 and fe3 == 0x6e and fm3 == 0x001fff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e5bab1f; op2val:0x952b96;
op3val:0x37001fff; valaddr_reg:x3; val_offset:32178*0 + 3*742*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 32178*0 + 3*742*FLEN/8, x4, x1, x2)

inst_10727:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x5bab1f and fs2 == 0 and fe2 == 0x01 and fm2 == 0x152b96 and fs3 == 0 and fe3 == 0x6e and fm3 == 0x003fff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e5bab1f; op2val:0x952b96;
op3val:0x37003fff; valaddr_reg:x3; val_offset:32181*0 + 3*743*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 32181*0 + 3*743*FLEN/8, x4, x1, x2)

inst_10728:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x5bab1f and fs2 == 0 and fe2 == 0x01 and fm2 == 0x152b96 and fs3 == 0 and fe3 == 0x6e and fm3 == 0x007fff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e5bab1f; op2val:0x952b96;
op3val:0x37007fff; valaddr_reg:x3; val_offset:32184*0 + 3*744*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 32184*0 + 3*744*FLEN/8, x4, x1, x2)

inst_10729:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x5bab1f and fs2 == 0 and fe2 == 0x01 and fm2 == 0x152b96 and fs3 == 0 and fe3 == 0x6e and fm3 == 0x00ffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e5bab1f; op2val:0x952b96;
op3val:0x3700ffff; valaddr_reg:x3; val_offset:32187*0 + 3*745*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 32187*0 + 3*745*FLEN/8, x4, x1, x2)

inst_10730:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x5bab1f and fs2 == 0 and fe2 == 0x01 and fm2 == 0x152b96 and fs3 == 0 and fe3 == 0x6e and fm3 == 0x01ffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e5bab1f; op2val:0x952b96;
op3val:0x3701ffff; valaddr_reg:x3; val_offset:32190*0 + 3*746*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 32190*0 + 3*746*FLEN/8, x4, x1, x2)

inst_10731:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x5bab1f and fs2 == 0 and fe2 == 0x01 and fm2 == 0x152b96 and fs3 == 0 and fe3 == 0x6e and fm3 == 0x03ffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e5bab1f; op2val:0x952b96;
op3val:0x3703ffff; valaddr_reg:x3; val_offset:32193*0 + 3*747*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 32193*0 + 3*747*FLEN/8, x4, x1, x2)

inst_10732:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x5bab1f and fs2 == 0 and fe2 == 0x01 and fm2 == 0x152b96 and fs3 == 0 and fe3 == 0x6e and fm3 == 0x07ffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e5bab1f; op2val:0x952b96;
op3val:0x3707ffff; valaddr_reg:x3; val_offset:32196*0 + 3*748*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 32196*0 + 3*748*FLEN/8, x4, x1, x2)

inst_10733:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x5bab1f and fs2 == 0 and fe2 == 0x01 and fm2 == 0x152b96 and fs3 == 0 and fe3 == 0x6e and fm3 == 0x0fffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e5bab1f; op2val:0x952b96;
op3val:0x370fffff; valaddr_reg:x3; val_offset:32199*0 + 3*749*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 32199*0 + 3*749*FLEN/8, x4, x1, x2)

inst_10734:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x5bab1f and fs2 == 0 and fe2 == 0x01 and fm2 == 0x152b96 and fs3 == 0 and fe3 == 0x6e and fm3 == 0x1fffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e5bab1f; op2val:0x952b96;
op3val:0x371fffff; valaddr_reg:x3; val_offset:32202*0 + 3*750*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 32202*0 + 3*750*FLEN/8, x4, x1, x2)

inst_10735:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x5bab1f and fs2 == 0 and fe2 == 0x01 and fm2 == 0x152b96 and fs3 == 0 and fe3 == 0x6e and fm3 == 0x3fffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e5bab1f; op2val:0x952b96;
op3val:0x373fffff; valaddr_reg:x3; val_offset:32205*0 + 3*751*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 32205*0 + 3*751*FLEN/8, x4, x1, x2)

inst_10736:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x5bab1f and fs2 == 0 and fe2 == 0x01 and fm2 == 0x152b96 and fs3 == 0 and fe3 == 0x6e and fm3 == 0x400000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e5bab1f; op2val:0x952b96;
op3val:0x37400000; valaddr_reg:x3; val_offset:32208*0 + 3*752*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 32208*0 + 3*752*FLEN/8, x4, x1, x2)

inst_10737:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x5bab1f and fs2 == 0 and fe2 == 0x01 and fm2 == 0x152b96 and fs3 == 0 and fe3 == 0x6e and fm3 == 0x600000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e5bab1f; op2val:0x952b96;
op3val:0x37600000; valaddr_reg:x3; val_offset:32211*0 + 3*753*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 32211*0 + 3*753*FLEN/8, x4, x1, x2)

inst_10738:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x5bab1f and fs2 == 0 and fe2 == 0x01 and fm2 == 0x152b96 and fs3 == 0 and fe3 == 0x6e and fm3 == 0x700000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e5bab1f; op2val:0x952b96;
op3val:0x37700000; valaddr_reg:x3; val_offset:32214*0 + 3*754*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 32214*0 + 3*754*FLEN/8, x4, x1, x2)

inst_10739:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x5bab1f and fs2 == 0 and fe2 == 0x01 and fm2 == 0x152b96 and fs3 == 0 and fe3 == 0x6e and fm3 == 0x780000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e5bab1f; op2val:0x952b96;
op3val:0x37780000; valaddr_reg:x3; val_offset:32217*0 + 3*755*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 32217*0 + 3*755*FLEN/8, x4, x1, x2)

inst_10740:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x5bab1f and fs2 == 0 and fe2 == 0x01 and fm2 == 0x152b96 and fs3 == 0 and fe3 == 0x6e and fm3 == 0x7c0000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e5bab1f; op2val:0x952b96;
op3val:0x377c0000; valaddr_reg:x3; val_offset:32220*0 + 3*756*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 32220*0 + 3*756*FLEN/8, x4, x1, x2)

inst_10741:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x5bab1f and fs2 == 0 and fe2 == 0x01 and fm2 == 0x152b96 and fs3 == 0 and fe3 == 0x6e and fm3 == 0x7e0000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e5bab1f; op2val:0x952b96;
op3val:0x377e0000; valaddr_reg:x3; val_offset:32223*0 + 3*757*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 32223*0 + 3*757*FLEN/8, x4, x1, x2)

inst_10742:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x5bab1f and fs2 == 0 and fe2 == 0x01 and fm2 == 0x152b96 and fs3 == 0 and fe3 == 0x6e and fm3 == 0x7f0000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e5bab1f; op2val:0x952b96;
op3val:0x377f0000; valaddr_reg:x3; val_offset:32226*0 + 3*758*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 32226*0 + 3*758*FLEN/8, x4, x1, x2)

inst_10743:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x5bab1f and fs2 == 0 and fe2 == 0x01 and fm2 == 0x152b96 and fs3 == 0 and fe3 == 0x6e and fm3 == 0x7f8000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e5bab1f; op2val:0x952b96;
op3val:0x377f8000; valaddr_reg:x3; val_offset:32229*0 + 3*759*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 32229*0 + 3*759*FLEN/8, x4, x1, x2)

inst_10744:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x5bab1f and fs2 == 0 and fe2 == 0x01 and fm2 == 0x152b96 and fs3 == 0 and fe3 == 0x6e and fm3 == 0x7fc000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e5bab1f; op2val:0x952b96;
op3val:0x377fc000; valaddr_reg:x3; val_offset:32232*0 + 3*760*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 32232*0 + 3*760*FLEN/8, x4, x1, x2)

inst_10745:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x5bab1f and fs2 == 0 and fe2 == 0x01 and fm2 == 0x152b96 and fs3 == 0 and fe3 == 0x6e and fm3 == 0x7fe000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e5bab1f; op2val:0x952b96;
op3val:0x377fe000; valaddr_reg:x3; val_offset:32235*0 + 3*761*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 32235*0 + 3*761*FLEN/8, x4, x1, x2)

inst_10746:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x5bab1f and fs2 == 0 and fe2 == 0x01 and fm2 == 0x152b96 and fs3 == 0 and fe3 == 0x6e and fm3 == 0x7ff000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e5bab1f; op2val:0x952b96;
op3val:0x377ff000; valaddr_reg:x3; val_offset:32238*0 + 3*762*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 32238*0 + 3*762*FLEN/8, x4, x1, x2)

inst_10747:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x5bab1f and fs2 == 0 and fe2 == 0x01 and fm2 == 0x152b96 and fs3 == 0 and fe3 == 0x6e and fm3 == 0x7ff800 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e5bab1f; op2val:0x952b96;
op3val:0x377ff800; valaddr_reg:x3; val_offset:32241*0 + 3*763*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 32241*0 + 3*763*FLEN/8, x4, x1, x2)

inst_10748:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x5bab1f and fs2 == 0 and fe2 == 0x01 and fm2 == 0x152b96 and fs3 == 0 and fe3 == 0x6e and fm3 == 0x7ffc00 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e5bab1f; op2val:0x952b96;
op3val:0x377ffc00; valaddr_reg:x3; val_offset:32244*0 + 3*764*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 32244*0 + 3*764*FLEN/8, x4, x1, x2)

inst_10749:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x5bab1f and fs2 == 0 and fe2 == 0x01 and fm2 == 0x152b96 and fs3 == 0 and fe3 == 0x6e and fm3 == 0x7ffe00 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e5bab1f; op2val:0x952b96;
op3val:0x377ffe00; valaddr_reg:x3; val_offset:32247*0 + 3*765*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 32247*0 + 3*765*FLEN/8, x4, x1, x2)

inst_10750:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x5bab1f and fs2 == 0 and fe2 == 0x01 and fm2 == 0x152b96 and fs3 == 0 and fe3 == 0x6e and fm3 == 0x7fff00 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e5bab1f; op2val:0x952b96;
op3val:0x377fff00; valaddr_reg:x3; val_offset:32250*0 + 3*766*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 32250*0 + 3*766*FLEN/8, x4, x1, x2)

inst_10751:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x5bab1f and fs2 == 0 and fe2 == 0x01 and fm2 == 0x152b96 and fs3 == 0 and fe3 == 0x6e and fm3 == 0x7fff80 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e5bab1f; op2val:0x952b96;
op3val:0x377fff80; valaddr_reg:x3; val_offset:32253*0 + 3*767*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 32253*0 + 3*767*FLEN/8, x4, x1, x2)
#endif


RVTEST_CODE_END
RVMODEL_HALT

RVTEST_DATA_BEGIN
.align 4
rvtest_data:
.word 0xbabecafe
.word 0xabecafeb
.word 0xbecafeba
.word 0xecafebab
test_dataset_0:
NAN_BOXED(0x7e4c2a81,32,FLEN)
NAN_BOXED(0xa07f2f,32,FLEN)
NAN_BOXED(0x29007fff,32,FLEN)
NAN_BOXED(0x7e4c2a81,32,FLEN)
NAN_BOXED(0xa07f2f,32,FLEN)
NAN_BOXED(0x2900ffff,32,FLEN)
NAN_BOXED(0x7e4c2a81,32,FLEN)
NAN_BOXED(0xa07f2f,32,FLEN)
NAN_BOXED(0x2901ffff,32,FLEN)
NAN_BOXED(0x7e4c2a81,32,FLEN)
NAN_BOXED(0xa07f2f,32,FLEN)
NAN_BOXED(0x2903ffff,32,FLEN)
NAN_BOXED(0x7e4c2a81,32,FLEN)
NAN_BOXED(0xa07f2f,32,FLEN)
NAN_BOXED(0x2907ffff,32,FLEN)
NAN_BOXED(0x7e4c2a81,32,FLEN)
NAN_BOXED(0xa07f2f,32,FLEN)
NAN_BOXED(0x290fffff,32,FLEN)
NAN_BOXED(0x7e4c2a81,32,FLEN)
NAN_BOXED(0xa07f2f,32,FLEN)
NAN_BOXED(0x291fffff,32,FLEN)
NAN_BOXED(0x7e4c2a81,32,FLEN)
NAN_BOXED(0xa07f2f,32,FLEN)
NAN_BOXED(0x293fffff,32,FLEN)
NAN_BOXED(0x7e4c2a81,32,FLEN)
NAN_BOXED(0xa07f2f,32,FLEN)
NAN_BOXED(0x29400000,32,FLEN)
NAN_BOXED(0x7e4c2a81,32,FLEN)
NAN_BOXED(0xa07f2f,32,FLEN)
NAN_BOXED(0x29600000,32,FLEN)
NAN_BOXED(0x7e4c2a81,32,FLEN)
NAN_BOXED(0xa07f2f,32,FLEN)
NAN_BOXED(0x29700000,32,FLEN)
NAN_BOXED(0x7e4c2a81,32,FLEN)
NAN_BOXED(0xa07f2f,32,FLEN)
NAN_BOXED(0x29780000,32,FLEN)
NAN_BOXED(0x7e4c2a81,32,FLEN)
NAN_BOXED(0xa07f2f,32,FLEN)
NAN_BOXED(0x297c0000,32,FLEN)
NAN_BOXED(0x7e4c2a81,32,FLEN)
NAN_BOXED(0xa07f2f,32,FLEN)
NAN_BOXED(0x297e0000,32,FLEN)
NAN_BOXED(0x7e4c2a81,32,FLEN)
NAN_BOXED(0xa07f2f,32,FLEN)
NAN_BOXED(0x297f0000,32,FLEN)
NAN_BOXED(0x7e4c2a81,32,FLEN)
NAN_BOXED(0xa07f2f,32,FLEN)
NAN_BOXED(0x297f8000,32,FLEN)
NAN_BOXED(0x7e4c2a81,32,FLEN)
NAN_BOXED(0xa07f2f,32,FLEN)
NAN_BOXED(0x297fc000,32,FLEN)
NAN_BOXED(0x7e4c2a81,32,FLEN)
NAN_BOXED(0xa07f2f,32,FLEN)
NAN_BOXED(0x297fe000,32,FLEN)
NAN_BOXED(0x7e4c2a81,32,FLEN)
NAN_BOXED(0xa07f2f,32,FLEN)
NAN_BOXED(0x297ff000,32,FLEN)
NAN_BOXED(0x7e4c2a81,32,FLEN)
NAN_BOXED(0xa07f2f,32,FLEN)
NAN_BOXED(0x297ff800,32,FLEN)
NAN_BOXED(0x7e4c2a81,32,FLEN)
NAN_BOXED(0xa07f2f,32,FLEN)
NAN_BOXED(0x297ffc00,32,FLEN)
NAN_BOXED(0x7e4c2a81,32,FLEN)
NAN_BOXED(0xa07f2f,32,FLEN)
NAN_BOXED(0x297ffe00,32,FLEN)
NAN_BOXED(0x7e4c2a81,32,FLEN)
NAN_BOXED(0xa07f2f,32,FLEN)
NAN_BOXED(0x297fff00,32,FLEN)
NAN_BOXED(0x7e4c2a81,32,FLEN)
NAN_BOXED(0xa07f2f,32,FLEN)
NAN_BOXED(0x297fff80,32,FLEN)
NAN_BOXED(0x7e4c2a81,32,FLEN)
NAN_BOXED(0xa07f2f,32,FLEN)
NAN_BOXED(0x297fffc0,32,FLEN)
NAN_BOXED(0x7e4c2a81,32,FLEN)
NAN_BOXED(0xa07f2f,32,FLEN)
NAN_BOXED(0x297fffe0,32,FLEN)
NAN_BOXED(0x7e4c2a81,32,FLEN)
NAN_BOXED(0xa07f2f,32,FLEN)
NAN_BOXED(0x297ffff0,32,FLEN)
NAN_BOXED(0x7e4c2a81,32,FLEN)
NAN_BOXED(0xa07f2f,32,FLEN)
NAN_BOXED(0x297ffff8,32,FLEN)
NAN_BOXED(0x7e4c2a81,32,FLEN)
NAN_BOXED(0xa07f2f,32,FLEN)
NAN_BOXED(0x297ffffc,32,FLEN)
NAN_BOXED(0x7e4c2a81,32,FLEN)
NAN_BOXED(0xa07f2f,32,FLEN)
NAN_BOXED(0x297ffffe,32,FLEN)
NAN_BOXED(0x7e4c2a81,32,FLEN)
NAN_BOXED(0xa07f2f,32,FLEN)
NAN_BOXED(0x297fffff,32,FLEN)
NAN_BOXED(0x7e4c2a81,32,FLEN)
NAN_BOXED(0xa07f2f,32,FLEN)
NAN_BOXED(0x3f800001,32,FLEN)
NAN_BOXED(0x7e4c2a81,32,FLEN)
NAN_BOXED(0xa07f2f,32,FLEN)
NAN_BOXED(0x3f800003,32,FLEN)
NAN_BOXED(0x7e4c2a81,32,FLEN)
NAN_BOXED(0xa07f2f,32,FLEN)
NAN_BOXED(0x3f800007,32,FLEN)
NAN_BOXED(0x7e4c2a81,32,FLEN)
NAN_BOXED(0xa07f2f,32,FLEN)
NAN_BOXED(0x3f999999,32,FLEN)
NAN_BOXED(0x7e4c2a81,32,FLEN)
NAN_BOXED(0xa07f2f,32,FLEN)
NAN_BOXED(0x3fa49249,32,FLEN)
NAN_BOXED(0x7e4c2a81,32,FLEN)
NAN_BOXED(0xa07f2f,32,FLEN)
NAN_BOXED(0x3fb33333,32,FLEN)
NAN_BOXED(0x7e4c2a81,32,FLEN)
NAN_BOXED(0xa07f2f,32,FLEN)
NAN_BOXED(0x3fb6db6d,32,FLEN)
NAN_BOXED(0x7e4c2a81,32,FLEN)
NAN_BOXED(0xa07f2f,32,FLEN)
NAN_BOXED(0x3fbbbbbb,32,FLEN)
NAN_BOXED(0x7e4c2a81,32,FLEN)
NAN_BOXED(0xa07f2f,32,FLEN)
NAN_BOXED(0x3fc44444,32,FLEN)
NAN_BOXED(0x7e4c2a81,32,FLEN)
NAN_BOXED(0xa07f2f,32,FLEN)
NAN_BOXED(0x3fcccccc,32,FLEN)
NAN_BOXED(0x7e4c2a81,32,FLEN)
NAN_BOXED(0xa07f2f,32,FLEN)
NAN_BOXED(0x3fdb6db6,32,FLEN)
NAN_BOXED(0x7e4c2a81,32,FLEN)
NAN_BOXED(0xa07f2f,32,FLEN)
NAN_BOXED(0x3fe66666,32,FLEN)
NAN_BOXED(0x7e4c2a81,32,FLEN)
NAN_BOXED(0xa07f2f,32,FLEN)
NAN_BOXED(0x3fedb6db,32,FLEN)
NAN_BOXED(0x7e4c2a81,32,FLEN)
NAN_BOXED(0xa07f2f,32,FLEN)
NAN_BOXED(0x3ffffff8,32,FLEN)
NAN_BOXED(0x7e4c2a81,32,FLEN)
NAN_BOXED(0xa07f2f,32,FLEN)
NAN_BOXED(0x3ffffffc,32,FLEN)
NAN_BOXED(0x7e4c2a81,32,FLEN)
NAN_BOXED(0xa07f2f,32,FLEN)
NAN_BOXED(0x3ffffffe,32,FLEN)
NAN_BOXED(0x7e4e0246,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x1,32,FLEN)
NAN_BOXED(0x7e4e0246,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x3,32,FLEN)
NAN_BOXED(0x7e4e0246,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x7,32,FLEN)
NAN_BOXED(0x7e4e0246,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x199999,32,FLEN)
NAN_BOXED(0x7e4e0246,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x249249,32,FLEN)
NAN_BOXED(0x7e4e0246,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x333333,32,FLEN)
NAN_BOXED(0x7e4e0246,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x36db6d,32,FLEN)
NAN_BOXED(0x7e4e0246,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x3bbbbb,32,FLEN)
NAN_BOXED(0x7e4e0246,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x444444,32,FLEN)
NAN_BOXED(0x7e4e0246,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x4ccccc,32,FLEN)
NAN_BOXED(0x7e4e0246,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x5b6db6,32,FLEN)
NAN_BOXED(0x7e4e0246,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x666666,32,FLEN)
NAN_BOXED(0x7e4e0246,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x6db6db,32,FLEN)
NAN_BOXED(0x7e4e0246,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x7ffff8,32,FLEN)
NAN_BOXED(0x7e4e0246,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x7ffffc,32,FLEN)
NAN_BOXED(0x7e4e0246,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x7ffffe,32,FLEN)
NAN_BOXED(0x7e4e0246,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x8000000,32,FLEN)
NAN_BOXED(0x7e4e0246,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x8000001,32,FLEN)
NAN_BOXED(0x7e4e0246,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x8000003,32,FLEN)
NAN_BOXED(0x7e4e0246,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x8000007,32,FLEN)
NAN_BOXED(0x7e4e0246,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x800000f,32,FLEN)
NAN_BOXED(0x7e4e0246,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x800001f,32,FLEN)
NAN_BOXED(0x7e4e0246,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x800003f,32,FLEN)
NAN_BOXED(0x7e4e0246,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x800007f,32,FLEN)
NAN_BOXED(0x7e4e0246,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x80000ff,32,FLEN)
NAN_BOXED(0x7e4e0246,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x80001ff,32,FLEN)
NAN_BOXED(0x7e4e0246,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x80003ff,32,FLEN)
NAN_BOXED(0x7e4e0246,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x80007ff,32,FLEN)
NAN_BOXED(0x7e4e0246,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x8000fff,32,FLEN)
NAN_BOXED(0x7e4e0246,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x8001fff,32,FLEN)
NAN_BOXED(0x7e4e0246,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x8003fff,32,FLEN)
NAN_BOXED(0x7e4e0246,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x8007fff,32,FLEN)
NAN_BOXED(0x7e4e0246,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x800ffff,32,FLEN)
NAN_BOXED(0x7e4e0246,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x801ffff,32,FLEN)
NAN_BOXED(0x7e4e0246,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x803ffff,32,FLEN)
NAN_BOXED(0x7e4e0246,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x807ffff,32,FLEN)
NAN_BOXED(0x7e4e0246,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x80fffff,32,FLEN)
NAN_BOXED(0x7e4e0246,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x81fffff,32,FLEN)
NAN_BOXED(0x7e4e0246,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x83fffff,32,FLEN)
NAN_BOXED(0x7e4e0246,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x8400000,32,FLEN)
NAN_BOXED(0x7e4e0246,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x8600000,32,FLEN)
NAN_BOXED(0x7e4e0246,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x8700000,32,FLEN)
NAN_BOXED(0x7e4e0246,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x8780000,32,FLEN)
NAN_BOXED(0x7e4e0246,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x87c0000,32,FLEN)
NAN_BOXED(0x7e4e0246,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x87e0000,32,FLEN)
NAN_BOXED(0x7e4e0246,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x87f0000,32,FLEN)
NAN_BOXED(0x7e4e0246,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x87f8000,32,FLEN)
NAN_BOXED(0x7e4e0246,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x87fc000,32,FLEN)
NAN_BOXED(0x7e4e0246,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x87fe000,32,FLEN)
NAN_BOXED(0x7e4e0246,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x87ff000,32,FLEN)
NAN_BOXED(0x7e4e0246,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x87ff800,32,FLEN)
NAN_BOXED(0x7e4e0246,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x87ffc00,32,FLEN)
NAN_BOXED(0x7e4e0246,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x87ffe00,32,FLEN)
NAN_BOXED(0x7e4e0246,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x87fff00,32,FLEN)
NAN_BOXED(0x7e4e0246,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x87fff80,32,FLEN)
NAN_BOXED(0x7e4e0246,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x87fffc0,32,FLEN)
NAN_BOXED(0x7e4e0246,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x87fffe0,32,FLEN)
NAN_BOXED(0x7e4e0246,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x87ffff0,32,FLEN)
NAN_BOXED(0x7e4e0246,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x87ffff8,32,FLEN)
NAN_BOXED(0x7e4e0246,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x87ffffc,32,FLEN)
NAN_BOXED(0x7e4e0246,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x87ffffe,32,FLEN)
NAN_BOXED(0x7e4e0246,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x87fffff,32,FLEN)
NAN_BOXED(0x7e4e4fe8,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x800001,32,FLEN)
NAN_BOXED(0x7e4e4fe8,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x800003,32,FLEN)
NAN_BOXED(0x7e4e4fe8,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x800007,32,FLEN)
NAN_BOXED(0x7e4e4fe8,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x999999,32,FLEN)
NAN_BOXED(0x7e4e4fe8,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xa49249,32,FLEN)
NAN_BOXED(0x7e4e4fe8,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xb33333,32,FLEN)
NAN_BOXED(0x7e4e4fe8,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xb6db6d,32,FLEN)
NAN_BOXED(0x7e4e4fe8,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xbbbbbb,32,FLEN)
NAN_BOXED(0x7e4e4fe8,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xc44444,32,FLEN)
NAN_BOXED(0x7e4e4fe8,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xcccccc,32,FLEN)
NAN_BOXED(0x7e4e4fe8,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xdb6db6,32,FLEN)
NAN_BOXED(0x7e4e4fe8,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xe66666,32,FLEN)
NAN_BOXED(0x7e4e4fe8,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xedb6db,32,FLEN)
NAN_BOXED(0x7e4e4fe8,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xfffff8,32,FLEN)
NAN_BOXED(0x7e4e4fe8,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xfffffc,32,FLEN)
NAN_BOXED(0x7e4e4fe8,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xfffffe,32,FLEN)
NAN_BOXED(0x7e4e4fe8,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x4800000,32,FLEN)
NAN_BOXED(0x7e4e4fe8,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x4800001,32,FLEN)
NAN_BOXED(0x7e4e4fe8,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x4800003,32,FLEN)
NAN_BOXED(0x7e4e4fe8,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x4800007,32,FLEN)
NAN_BOXED(0x7e4e4fe8,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x480000f,32,FLEN)
NAN_BOXED(0x7e4e4fe8,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x480001f,32,FLEN)
NAN_BOXED(0x7e4e4fe8,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x480003f,32,FLEN)
NAN_BOXED(0x7e4e4fe8,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x480007f,32,FLEN)
NAN_BOXED(0x7e4e4fe8,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x48000ff,32,FLEN)
NAN_BOXED(0x7e4e4fe8,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x48001ff,32,FLEN)
NAN_BOXED(0x7e4e4fe8,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x48003ff,32,FLEN)
NAN_BOXED(0x7e4e4fe8,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x48007ff,32,FLEN)
NAN_BOXED(0x7e4e4fe8,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x4800fff,32,FLEN)
NAN_BOXED(0x7e4e4fe8,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x4801fff,32,FLEN)
NAN_BOXED(0x7e4e4fe8,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x4803fff,32,FLEN)
NAN_BOXED(0x7e4e4fe8,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x4807fff,32,FLEN)
NAN_BOXED(0x7e4e4fe8,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x480ffff,32,FLEN)
NAN_BOXED(0x7e4e4fe8,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x481ffff,32,FLEN)
NAN_BOXED(0x7e4e4fe8,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x483ffff,32,FLEN)
NAN_BOXED(0x7e4e4fe8,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x487ffff,32,FLEN)
NAN_BOXED(0x7e4e4fe8,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x48fffff,32,FLEN)
NAN_BOXED(0x7e4e4fe8,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x49fffff,32,FLEN)
NAN_BOXED(0x7e4e4fe8,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x4bfffff,32,FLEN)
NAN_BOXED(0x7e4e4fe8,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x4c00000,32,FLEN)
NAN_BOXED(0x7e4e4fe8,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x4e00000,32,FLEN)
NAN_BOXED(0x7e4e4fe8,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x4f00000,32,FLEN)
NAN_BOXED(0x7e4e4fe8,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x4f80000,32,FLEN)
NAN_BOXED(0x7e4e4fe8,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x4fc0000,32,FLEN)
NAN_BOXED(0x7e4e4fe8,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x4fe0000,32,FLEN)
NAN_BOXED(0x7e4e4fe8,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x4ff0000,32,FLEN)
NAN_BOXED(0x7e4e4fe8,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x4ff8000,32,FLEN)
NAN_BOXED(0x7e4e4fe8,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x4ffc000,32,FLEN)
NAN_BOXED(0x7e4e4fe8,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x4ffe000,32,FLEN)
NAN_BOXED(0x7e4e4fe8,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x4fff000,32,FLEN)
NAN_BOXED(0x7e4e4fe8,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x4fff800,32,FLEN)
NAN_BOXED(0x7e4e4fe8,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x4fffc00,32,FLEN)
NAN_BOXED(0x7e4e4fe8,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x4fffe00,32,FLEN)
NAN_BOXED(0x7e4e4fe8,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x4ffff00,32,FLEN)
NAN_BOXED(0x7e4e4fe8,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x4ffff80,32,FLEN)
NAN_BOXED(0x7e4e4fe8,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x4ffffc0,32,FLEN)
NAN_BOXED(0x7e4e4fe8,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x4ffffe0,32,FLEN)
NAN_BOXED(0x7e4e4fe8,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x4fffff0,32,FLEN)
NAN_BOXED(0x7e4e4fe8,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x4fffff8,32,FLEN)
NAN_BOXED(0x7e4e4fe8,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x4fffffc,32,FLEN)
NAN_BOXED(0x7e4e4fe8,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x4fffffe,32,FLEN)
NAN_BOXED(0x7e4e4fe8,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x4ffffff,32,FLEN)
NAN_BOXED(0x7e512e72,32,FLEN)
NAN_BOXED(0xc09ca610,32,FLEN)
NAN_BOXED(0xe5800000,32,FLEN)
NAN_BOXED(0x7e512e72,32,FLEN)
NAN_BOXED(0xc09ca610,32,FLEN)
NAN_BOXED(0xe5800001,32,FLEN)
NAN_BOXED(0x7e512e72,32,FLEN)
NAN_BOXED(0xc09ca610,32,FLEN)
NAN_BOXED(0xe5800003,32,FLEN)
NAN_BOXED(0x7e512e72,32,FLEN)
NAN_BOXED(0xc09ca610,32,FLEN)
NAN_BOXED(0xe5800007,32,FLEN)
NAN_BOXED(0x7e512e72,32,FLEN)
NAN_BOXED(0xc09ca610,32,FLEN)
NAN_BOXED(0xe580000f,32,FLEN)
NAN_BOXED(0x7e512e72,32,FLEN)
NAN_BOXED(0xc09ca610,32,FLEN)
NAN_BOXED(0xe580001f,32,FLEN)
NAN_BOXED(0x7e512e72,32,FLEN)
NAN_BOXED(0xc09ca610,32,FLEN)
NAN_BOXED(0xe580003f,32,FLEN)
NAN_BOXED(0x7e512e72,32,FLEN)
NAN_BOXED(0xc09ca610,32,FLEN)
NAN_BOXED(0xe580007f,32,FLEN)
NAN_BOXED(0x7e512e72,32,FLEN)
NAN_BOXED(0xc09ca610,32,FLEN)
NAN_BOXED(0xe58000ff,32,FLEN)
NAN_BOXED(0x7e512e72,32,FLEN)
NAN_BOXED(0xc09ca610,32,FLEN)
NAN_BOXED(0xe58001ff,32,FLEN)
NAN_BOXED(0x7e512e72,32,FLEN)
NAN_BOXED(0xc09ca610,32,FLEN)
NAN_BOXED(0xe58003ff,32,FLEN)
NAN_BOXED(0x7e512e72,32,FLEN)
NAN_BOXED(0xc09ca610,32,FLEN)
NAN_BOXED(0xe58007ff,32,FLEN)
NAN_BOXED(0x7e512e72,32,FLEN)
NAN_BOXED(0xc09ca610,32,FLEN)
NAN_BOXED(0xe5800fff,32,FLEN)
NAN_BOXED(0x7e512e72,32,FLEN)
NAN_BOXED(0xc09ca610,32,FLEN)
NAN_BOXED(0xe5801fff,32,FLEN)
NAN_BOXED(0x7e512e72,32,FLEN)
NAN_BOXED(0xc09ca610,32,FLEN)
NAN_BOXED(0xe5803fff,32,FLEN)
NAN_BOXED(0x7e512e72,32,FLEN)
NAN_BOXED(0xc09ca610,32,FLEN)
NAN_BOXED(0xe5807fff,32,FLEN)
NAN_BOXED(0x7e512e72,32,FLEN)
NAN_BOXED(0xc09ca610,32,FLEN)
NAN_BOXED(0xe580ffff,32,FLEN)
NAN_BOXED(0x7e512e72,32,FLEN)
NAN_BOXED(0xc09ca610,32,FLEN)
NAN_BOXED(0xe581ffff,32,FLEN)
NAN_BOXED(0x7e512e72,32,FLEN)
NAN_BOXED(0xc09ca610,32,FLEN)
NAN_BOXED(0xe583ffff,32,FLEN)
NAN_BOXED(0x7e512e72,32,FLEN)
NAN_BOXED(0xc09ca610,32,FLEN)
NAN_BOXED(0xe587ffff,32,FLEN)
NAN_BOXED(0x7e512e72,32,FLEN)
NAN_BOXED(0xc09ca610,32,FLEN)
NAN_BOXED(0xe58fffff,32,FLEN)
NAN_BOXED(0x7e512e72,32,FLEN)
NAN_BOXED(0xc09ca610,32,FLEN)
NAN_BOXED(0xe59fffff,32,FLEN)
NAN_BOXED(0x7e512e72,32,FLEN)
NAN_BOXED(0xc09ca610,32,FLEN)
NAN_BOXED(0xe5bfffff,32,FLEN)
NAN_BOXED(0x7e512e72,32,FLEN)
NAN_BOXED(0xc09ca610,32,FLEN)
NAN_BOXED(0xe5c00000,32,FLEN)
NAN_BOXED(0x7e512e72,32,FLEN)
NAN_BOXED(0xc09ca610,32,FLEN)
NAN_BOXED(0xe5e00000,32,FLEN)
NAN_BOXED(0x7e512e72,32,FLEN)
NAN_BOXED(0xc09ca610,32,FLEN)
NAN_BOXED(0xe5f00000,32,FLEN)
NAN_BOXED(0x7e512e72,32,FLEN)
NAN_BOXED(0xc09ca610,32,FLEN)
NAN_BOXED(0xe5f80000,32,FLEN)
NAN_BOXED(0x7e512e72,32,FLEN)
NAN_BOXED(0xc09ca610,32,FLEN)
NAN_BOXED(0xe5fc0000,32,FLEN)
NAN_BOXED(0x7e512e72,32,FLEN)
NAN_BOXED(0xc09ca610,32,FLEN)
NAN_BOXED(0xe5fe0000,32,FLEN)
NAN_BOXED(0x7e512e72,32,FLEN)
NAN_BOXED(0xc09ca610,32,FLEN)
NAN_BOXED(0xe5ff0000,32,FLEN)
NAN_BOXED(0x7e512e72,32,FLEN)
NAN_BOXED(0xc09ca610,32,FLEN)
NAN_BOXED(0xe5ff8000,32,FLEN)
NAN_BOXED(0x7e512e72,32,FLEN)
NAN_BOXED(0xc09ca610,32,FLEN)
NAN_BOXED(0xe5ffc000,32,FLEN)
NAN_BOXED(0x7e512e72,32,FLEN)
NAN_BOXED(0xc09ca610,32,FLEN)
NAN_BOXED(0xe5ffe000,32,FLEN)
NAN_BOXED(0x7e512e72,32,FLEN)
NAN_BOXED(0xc09ca610,32,FLEN)
NAN_BOXED(0xe5fff000,32,FLEN)
NAN_BOXED(0x7e512e72,32,FLEN)
NAN_BOXED(0xc09ca610,32,FLEN)
NAN_BOXED(0xe5fff800,32,FLEN)
NAN_BOXED(0x7e512e72,32,FLEN)
NAN_BOXED(0xc09ca610,32,FLEN)
NAN_BOXED(0xe5fffc00,32,FLEN)
NAN_BOXED(0x7e512e72,32,FLEN)
NAN_BOXED(0xc09ca610,32,FLEN)
NAN_BOXED(0xe5fffe00,32,FLEN)
NAN_BOXED(0x7e512e72,32,FLEN)
NAN_BOXED(0xc09ca610,32,FLEN)
NAN_BOXED(0xe5ffff00,32,FLEN)
NAN_BOXED(0x7e512e72,32,FLEN)
NAN_BOXED(0xc09ca610,32,FLEN)
NAN_BOXED(0xe5ffff80,32,FLEN)
NAN_BOXED(0x7e512e72,32,FLEN)
NAN_BOXED(0xc09ca610,32,FLEN)
NAN_BOXED(0xe5ffffc0,32,FLEN)
NAN_BOXED(0x7e512e72,32,FLEN)
NAN_BOXED(0xc09ca610,32,FLEN)
NAN_BOXED(0xe5ffffe0,32,FLEN)
NAN_BOXED(0x7e512e72,32,FLEN)
NAN_BOXED(0xc09ca610,32,FLEN)
NAN_BOXED(0xe5fffff0,32,FLEN)
NAN_BOXED(0x7e512e72,32,FLEN)
NAN_BOXED(0xc09ca610,32,FLEN)
NAN_BOXED(0xe5fffff8,32,FLEN)
NAN_BOXED(0x7e512e72,32,FLEN)
NAN_BOXED(0xc09ca610,32,FLEN)
NAN_BOXED(0xe5fffffc,32,FLEN)
NAN_BOXED(0x7e512e72,32,FLEN)
NAN_BOXED(0xc09ca610,32,FLEN)
NAN_BOXED(0xe5fffffe,32,FLEN)
NAN_BOXED(0x7e512e72,32,FLEN)
NAN_BOXED(0xc09ca610,32,FLEN)
NAN_BOXED(0xe5ffffff,32,FLEN)
NAN_BOXED(0x7e512e72,32,FLEN)
NAN_BOXED(0xc09ca610,32,FLEN)
NAN_BOXED(0xff000001,32,FLEN)
NAN_BOXED(0x7e512e72,32,FLEN)
NAN_BOXED(0xc09ca610,32,FLEN)
NAN_BOXED(0xff000003,32,FLEN)
NAN_BOXED(0x7e512e72,32,FLEN)
NAN_BOXED(0xc09ca610,32,FLEN)
NAN_BOXED(0xff000007,32,FLEN)
NAN_BOXED(0x7e512e72,32,FLEN)
NAN_BOXED(0xc09ca610,32,FLEN)
NAN_BOXED(0xff199999,32,FLEN)
NAN_BOXED(0x7e512e72,32,FLEN)
NAN_BOXED(0xc09ca610,32,FLEN)
NAN_BOXED(0xff249249,32,FLEN)
NAN_BOXED(0x7e512e72,32,FLEN)
NAN_BOXED(0xc09ca610,32,FLEN)
NAN_BOXED(0xff333333,32,FLEN)
NAN_BOXED(0x7e512e72,32,FLEN)
NAN_BOXED(0xc09ca610,32,FLEN)
NAN_BOXED(0xff36db6d,32,FLEN)
NAN_BOXED(0x7e512e72,32,FLEN)
NAN_BOXED(0xc09ca610,32,FLEN)
NAN_BOXED(0xff3bbbbb,32,FLEN)
NAN_BOXED(0x7e512e72,32,FLEN)
NAN_BOXED(0xc09ca610,32,FLEN)
NAN_BOXED(0xff444444,32,FLEN)
NAN_BOXED(0x7e512e72,32,FLEN)
NAN_BOXED(0xc09ca610,32,FLEN)
NAN_BOXED(0xff4ccccc,32,FLEN)
NAN_BOXED(0x7e512e72,32,FLEN)
NAN_BOXED(0xc09ca610,32,FLEN)
NAN_BOXED(0xff5b6db6,32,FLEN)
NAN_BOXED(0x7e512e72,32,FLEN)
NAN_BOXED(0xc09ca610,32,FLEN)
NAN_BOXED(0xff666666,32,FLEN)
NAN_BOXED(0x7e512e72,32,FLEN)
NAN_BOXED(0xc09ca610,32,FLEN)
NAN_BOXED(0xff6db6db,32,FLEN)
NAN_BOXED(0x7e512e72,32,FLEN)
NAN_BOXED(0xc09ca610,32,FLEN)
NAN_BOXED(0xff7ffff8,32,FLEN)
NAN_BOXED(0x7e512e72,32,FLEN)
NAN_BOXED(0xc09ca610,32,FLEN)
NAN_BOXED(0xff7ffffc,32,FLEN)
NAN_BOXED(0x7e512e72,32,FLEN)
NAN_BOXED(0xc09ca610,32,FLEN)
NAN_BOXED(0xff7ffffe,32,FLEN)
NAN_BOXED(0x7e51b0b6,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x7e51b0b6,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x1,32,FLEN)
NAN_BOXED(0x7e51b0b6,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x3,32,FLEN)
NAN_BOXED(0x7e51b0b6,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x7,32,FLEN)
NAN_BOXED(0x7e51b0b6,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xf,32,FLEN)
NAN_BOXED(0x7e51b0b6,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x1f,32,FLEN)
NAN_BOXED(0x7e51b0b6,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x3f,32,FLEN)
NAN_BOXED(0x7e51b0b6,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x7f,32,FLEN)
NAN_BOXED(0x7e51b0b6,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xff,32,FLEN)
NAN_BOXED(0x7e51b0b6,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x1ff,32,FLEN)
NAN_BOXED(0x7e51b0b6,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x3ff,32,FLEN)
NAN_BOXED(0x7e51b0b6,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x7ff,32,FLEN)
NAN_BOXED(0x7e51b0b6,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xfff,32,FLEN)
NAN_BOXED(0x7e51b0b6,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x1fff,32,FLEN)
NAN_BOXED(0x7e51b0b6,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x3fff,32,FLEN)
NAN_BOXED(0x7e51b0b6,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x7fff,32,FLEN)
NAN_BOXED(0x7e51b0b6,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xffff,32,FLEN)
NAN_BOXED(0x7e51b0b6,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x1ffff,32,FLEN)
NAN_BOXED(0x7e51b0b6,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x3ffff,32,FLEN)
NAN_BOXED(0x7e51b0b6,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x7ffff,32,FLEN)
NAN_BOXED(0x7e51b0b6,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xfffff,32,FLEN)
NAN_BOXED(0x7e51b0b6,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x1fffff,32,FLEN)
NAN_BOXED(0x7e51b0b6,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x3fffff,32,FLEN)
NAN_BOXED(0x7e51b0b6,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x400000,32,FLEN)
NAN_BOXED(0x7e51b0b6,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x600000,32,FLEN)
NAN_BOXED(0x7e51b0b6,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x700000,32,FLEN)
NAN_BOXED(0x7e51b0b6,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x780000,32,FLEN)
NAN_BOXED(0x7e51b0b6,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x7c0000,32,FLEN)
NAN_BOXED(0x7e51b0b6,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x7e0000,32,FLEN)
NAN_BOXED(0x7e51b0b6,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x7f0000,32,FLEN)
NAN_BOXED(0x7e51b0b6,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x7f8000,32,FLEN)
NAN_BOXED(0x7e51b0b6,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x7fc000,32,FLEN)
NAN_BOXED(0x7e51b0b6,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x7fe000,32,FLEN)
NAN_BOXED(0x7e51b0b6,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x7ff000,32,FLEN)
NAN_BOXED(0x7e51b0b6,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x7ff800,32,FLEN)
NAN_BOXED(0x7e51b0b6,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x7ffc00,32,FLEN)
NAN_BOXED(0x7e51b0b6,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x7ffe00,32,FLEN)
NAN_BOXED(0x7e51b0b6,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x7fff00,32,FLEN)
NAN_BOXED(0x7e51b0b6,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x7fff80,32,FLEN)
NAN_BOXED(0x7e51b0b6,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x7fffc0,32,FLEN)
NAN_BOXED(0x7e51b0b6,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x7fffe0,32,FLEN)
NAN_BOXED(0x7e51b0b6,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x7ffff0,32,FLEN)
NAN_BOXED(0x7e51b0b6,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x7ffff8,32,FLEN)
NAN_BOXED(0x7e51b0b6,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x7ffffc,32,FLEN)
NAN_BOXED(0x7e51b0b6,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x7ffffe,32,FLEN)
NAN_BOXED(0x7e51b0b6,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x7fffff,32,FLEN)
NAN_BOXED(0x7e51b0b6,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x800001,32,FLEN)
NAN_BOXED(0x7e51b0b6,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x800003,32,FLEN)
NAN_BOXED(0x7e51b0b6,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x800007,32,FLEN)
NAN_BOXED(0x7e51b0b6,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x999999,32,FLEN)
NAN_BOXED(0x7e51b0b6,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xa49249,32,FLEN)
NAN_BOXED(0x7e51b0b6,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xb33333,32,FLEN)
NAN_BOXED(0x7e51b0b6,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xb6db6d,32,FLEN)
NAN_BOXED(0x7e51b0b6,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xbbbbbb,32,FLEN)
NAN_BOXED(0x7e51b0b6,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xc44444,32,FLEN)
NAN_BOXED(0x7e51b0b6,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xcccccc,32,FLEN)
NAN_BOXED(0x7e51b0b6,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xdb6db6,32,FLEN)
NAN_BOXED(0x7e51b0b6,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xe66666,32,FLEN)
NAN_BOXED(0x7e51b0b6,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xedb6db,32,FLEN)
NAN_BOXED(0x7e51b0b6,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xfffff8,32,FLEN)
NAN_BOXED(0x7e51b0b6,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xfffffc,32,FLEN)
NAN_BOXED(0x7e51b0b6,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xfffffe,32,FLEN)
NAN_BOXED(0x7e52bf26,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x80000001,32,FLEN)
NAN_BOXED(0x7e52bf26,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x80000003,32,FLEN)
NAN_BOXED(0x7e52bf26,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x80000007,32,FLEN)
NAN_BOXED(0x7e52bf26,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x80199999,32,FLEN)
NAN_BOXED(0x7e52bf26,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x80249249,32,FLEN)
NAN_BOXED(0x7e52bf26,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x80333333,32,FLEN)
NAN_BOXED(0x7e52bf26,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x8036db6d,32,FLEN)
NAN_BOXED(0x7e52bf26,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x803bbbbb,32,FLEN)
NAN_BOXED(0x7e52bf26,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x80444444,32,FLEN)
NAN_BOXED(0x7e52bf26,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x804ccccc,32,FLEN)
NAN_BOXED(0x7e52bf26,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x805b6db6,32,FLEN)
NAN_BOXED(0x7e52bf26,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x80666666,32,FLEN)
NAN_BOXED(0x7e52bf26,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x806db6db,32,FLEN)
NAN_BOXED(0x7e52bf26,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x807ffff8,32,FLEN)
NAN_BOXED(0x7e52bf26,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x807ffffc,32,FLEN)
NAN_BOXED(0x7e52bf26,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x807ffffe,32,FLEN)
NAN_BOXED(0x7e52bf26,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x8a000000,32,FLEN)
NAN_BOXED(0x7e52bf26,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x8a000001,32,FLEN)
NAN_BOXED(0x7e52bf26,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x8a000003,32,FLEN)
NAN_BOXED(0x7e52bf26,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x8a000007,32,FLEN)
NAN_BOXED(0x7e52bf26,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x8a00000f,32,FLEN)
NAN_BOXED(0x7e52bf26,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x8a00001f,32,FLEN)
NAN_BOXED(0x7e52bf26,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x8a00003f,32,FLEN)
NAN_BOXED(0x7e52bf26,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x8a00007f,32,FLEN)
NAN_BOXED(0x7e52bf26,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x8a0000ff,32,FLEN)
NAN_BOXED(0x7e52bf26,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x8a0001ff,32,FLEN)
NAN_BOXED(0x7e52bf26,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x8a0003ff,32,FLEN)
NAN_BOXED(0x7e52bf26,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x8a0007ff,32,FLEN)
NAN_BOXED(0x7e52bf26,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x8a000fff,32,FLEN)
NAN_BOXED(0x7e52bf26,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x8a001fff,32,FLEN)
NAN_BOXED(0x7e52bf26,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x8a003fff,32,FLEN)
NAN_BOXED(0x7e52bf26,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x8a007fff,32,FLEN)
NAN_BOXED(0x7e52bf26,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x8a00ffff,32,FLEN)
NAN_BOXED(0x7e52bf26,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x8a01ffff,32,FLEN)
NAN_BOXED(0x7e52bf26,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x8a03ffff,32,FLEN)
NAN_BOXED(0x7e52bf26,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x8a07ffff,32,FLEN)
NAN_BOXED(0x7e52bf26,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x8a0fffff,32,FLEN)
NAN_BOXED(0x7e52bf26,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x8a1fffff,32,FLEN)
NAN_BOXED(0x7e52bf26,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x8a3fffff,32,FLEN)
NAN_BOXED(0x7e52bf26,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x8a400000,32,FLEN)
NAN_BOXED(0x7e52bf26,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x8a600000,32,FLEN)
NAN_BOXED(0x7e52bf26,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x8a700000,32,FLEN)
NAN_BOXED(0x7e52bf26,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x8a780000,32,FLEN)
NAN_BOXED(0x7e52bf26,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x8a7c0000,32,FLEN)
NAN_BOXED(0x7e52bf26,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x8a7e0000,32,FLEN)
NAN_BOXED(0x7e52bf26,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x8a7f0000,32,FLEN)
NAN_BOXED(0x7e52bf26,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x8a7f8000,32,FLEN)
NAN_BOXED(0x7e52bf26,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x8a7fc000,32,FLEN)
NAN_BOXED(0x7e52bf26,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x8a7fe000,32,FLEN)
NAN_BOXED(0x7e52bf26,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x8a7ff000,32,FLEN)
NAN_BOXED(0x7e52bf26,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x8a7ff800,32,FLEN)
NAN_BOXED(0x7e52bf26,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x8a7ffc00,32,FLEN)
NAN_BOXED(0x7e52bf26,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x8a7ffe00,32,FLEN)
NAN_BOXED(0x7e52bf26,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x8a7fff00,32,FLEN)
NAN_BOXED(0x7e52bf26,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x8a7fff80,32,FLEN)
NAN_BOXED(0x7e52bf26,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x8a7fffc0,32,FLEN)
NAN_BOXED(0x7e52bf26,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x8a7fffe0,32,FLEN)
NAN_BOXED(0x7e52bf26,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x8a7ffff0,32,FLEN)
NAN_BOXED(0x7e52bf26,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x8a7ffff8,32,FLEN)
NAN_BOXED(0x7e52bf26,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x8a7ffffc,32,FLEN)
NAN_BOXED(0x7e52bf26,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x8a7ffffe,32,FLEN)
NAN_BOXED(0x7e52bf26,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x8a7fffff,32,FLEN)
NAN_BOXED(0x7e551c11,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x80000001,32,FLEN)
NAN_BOXED(0x7e551c11,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x80000003,32,FLEN)
NAN_BOXED(0x7e551c11,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x80000007,32,FLEN)
NAN_BOXED(0x7e551c11,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x80199999,32,FLEN)
NAN_BOXED(0x7e551c11,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x80249249,32,FLEN)
NAN_BOXED(0x7e551c11,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x80333333,32,FLEN)
NAN_BOXED(0x7e551c11,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x8036db6d,32,FLEN)
NAN_BOXED(0x7e551c11,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x803bbbbb,32,FLEN)
NAN_BOXED(0x7e551c11,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x80444444,32,FLEN)
NAN_BOXED(0x7e551c11,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x804ccccc,32,FLEN)
NAN_BOXED(0x7e551c11,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x805b6db6,32,FLEN)
NAN_BOXED(0x7e551c11,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x80666666,32,FLEN)
NAN_BOXED(0x7e551c11,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x806db6db,32,FLEN)
NAN_BOXED(0x7e551c11,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x807ffff8,32,FLEN)
NAN_BOXED(0x7e551c11,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x807ffffc,32,FLEN)
NAN_BOXED(0x7e551c11,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x807ffffe,32,FLEN)
NAN_BOXED(0x7e551c11,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x89800000,32,FLEN)
NAN_BOXED(0x7e551c11,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x89800001,32,FLEN)
NAN_BOXED(0x7e551c11,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x89800003,32,FLEN)
NAN_BOXED(0x7e551c11,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x89800007,32,FLEN)
NAN_BOXED(0x7e551c11,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x8980000f,32,FLEN)
NAN_BOXED(0x7e551c11,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x8980001f,32,FLEN)
NAN_BOXED(0x7e551c11,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x8980003f,32,FLEN)
NAN_BOXED(0x7e551c11,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x8980007f,32,FLEN)
NAN_BOXED(0x7e551c11,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x898000ff,32,FLEN)
NAN_BOXED(0x7e551c11,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x898001ff,32,FLEN)
NAN_BOXED(0x7e551c11,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x898003ff,32,FLEN)
NAN_BOXED(0x7e551c11,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x898007ff,32,FLEN)
NAN_BOXED(0x7e551c11,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x89800fff,32,FLEN)
NAN_BOXED(0x7e551c11,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x89801fff,32,FLEN)
NAN_BOXED(0x7e551c11,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x89803fff,32,FLEN)
NAN_BOXED(0x7e551c11,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x89807fff,32,FLEN)
NAN_BOXED(0x7e551c11,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x8980ffff,32,FLEN)
NAN_BOXED(0x7e551c11,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x8981ffff,32,FLEN)
NAN_BOXED(0x7e551c11,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x8983ffff,32,FLEN)
NAN_BOXED(0x7e551c11,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x8987ffff,32,FLEN)
NAN_BOXED(0x7e551c11,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x898fffff,32,FLEN)
NAN_BOXED(0x7e551c11,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x899fffff,32,FLEN)
NAN_BOXED(0x7e551c11,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x89bfffff,32,FLEN)
NAN_BOXED(0x7e551c11,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x89c00000,32,FLEN)
NAN_BOXED(0x7e551c11,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x89e00000,32,FLEN)
NAN_BOXED(0x7e551c11,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x89f00000,32,FLEN)
NAN_BOXED(0x7e551c11,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x89f80000,32,FLEN)
NAN_BOXED(0x7e551c11,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x89fc0000,32,FLEN)
NAN_BOXED(0x7e551c11,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x89fe0000,32,FLEN)
NAN_BOXED(0x7e551c11,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x89ff0000,32,FLEN)
NAN_BOXED(0x7e551c11,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x89ff8000,32,FLEN)
NAN_BOXED(0x7e551c11,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x89ffc000,32,FLEN)
NAN_BOXED(0x7e551c11,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x89ffe000,32,FLEN)
NAN_BOXED(0x7e551c11,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x89fff000,32,FLEN)
NAN_BOXED(0x7e551c11,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x89fff800,32,FLEN)
NAN_BOXED(0x7e551c11,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x89fffc00,32,FLEN)
NAN_BOXED(0x7e551c11,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x89fffe00,32,FLEN)
NAN_BOXED(0x7e551c11,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x89ffff00,32,FLEN)
NAN_BOXED(0x7e551c11,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x89ffff80,32,FLEN)
NAN_BOXED(0x7e551c11,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x89ffffc0,32,FLEN)
NAN_BOXED(0x7e551c11,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x89ffffe0,32,FLEN)
NAN_BOXED(0x7e551c11,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x89fffff0,32,FLEN)
NAN_BOXED(0x7e551c11,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x89fffff8,32,FLEN)
NAN_BOXED(0x7e551c11,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x89fffffc,32,FLEN)
NAN_BOXED(0x7e551c11,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x89fffffe,32,FLEN)
NAN_BOXED(0x7e551c11,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x89ffffff,32,FLEN)
NAN_BOXED(0x7e5611f2,32,FLEN)
NAN_BOXED(0x991243,32,FLEN)
NAN_BOXED(0x3f800001,32,FLEN)
NAN_BOXED(0x7e5611f2,32,FLEN)
NAN_BOXED(0x991243,32,FLEN)
NAN_BOXED(0x3f800003,32,FLEN)
NAN_BOXED(0x7e5611f2,32,FLEN)
NAN_BOXED(0x991243,32,FLEN)
NAN_BOXED(0x3f800007,32,FLEN)
NAN_BOXED(0x7e5611f2,32,FLEN)
NAN_BOXED(0x991243,32,FLEN)
NAN_BOXED(0x3f999999,32,FLEN)
NAN_BOXED(0x7e5611f2,32,FLEN)
NAN_BOXED(0x991243,32,FLEN)
NAN_BOXED(0x3fa49249,32,FLEN)
NAN_BOXED(0x7e5611f2,32,FLEN)
NAN_BOXED(0x991243,32,FLEN)
NAN_BOXED(0x3fb33333,32,FLEN)
NAN_BOXED(0x7e5611f2,32,FLEN)
NAN_BOXED(0x991243,32,FLEN)
NAN_BOXED(0x3fb6db6d,32,FLEN)
NAN_BOXED(0x7e5611f2,32,FLEN)
NAN_BOXED(0x991243,32,FLEN)
NAN_BOXED(0x3fbbbbbb,32,FLEN)
NAN_BOXED(0x7e5611f2,32,FLEN)
NAN_BOXED(0x991243,32,FLEN)
NAN_BOXED(0x3fc44444,32,FLEN)
NAN_BOXED(0x7e5611f2,32,FLEN)
NAN_BOXED(0x991243,32,FLEN)
NAN_BOXED(0x3fcccccc,32,FLEN)
NAN_BOXED(0x7e5611f2,32,FLEN)
NAN_BOXED(0x991243,32,FLEN)
NAN_BOXED(0x3fdb6db6,32,FLEN)
NAN_BOXED(0x7e5611f2,32,FLEN)
NAN_BOXED(0x991243,32,FLEN)
NAN_BOXED(0x3fe66666,32,FLEN)
NAN_BOXED(0x7e5611f2,32,FLEN)
NAN_BOXED(0x991243,32,FLEN)
NAN_BOXED(0x3fedb6db,32,FLEN)
NAN_BOXED(0x7e5611f2,32,FLEN)
NAN_BOXED(0x991243,32,FLEN)
NAN_BOXED(0x3ffffff8,32,FLEN)
NAN_BOXED(0x7e5611f2,32,FLEN)
NAN_BOXED(0x991243,32,FLEN)
NAN_BOXED(0x3ffffffc,32,FLEN)
NAN_BOXED(0x7e5611f2,32,FLEN)
NAN_BOXED(0x991243,32,FLEN)
NAN_BOXED(0x3ffffffe,32,FLEN)
NAN_BOXED(0x7e5611f2,32,FLEN)
NAN_BOXED(0x991243,32,FLEN)
NAN_BOXED(0x4e000000,32,FLEN)
NAN_BOXED(0x7e5611f2,32,FLEN)
NAN_BOXED(0x991243,32,FLEN)
NAN_BOXED(0x4e000001,32,FLEN)
NAN_BOXED(0x7e5611f2,32,FLEN)
NAN_BOXED(0x991243,32,FLEN)
NAN_BOXED(0x4e000003,32,FLEN)
NAN_BOXED(0x7e5611f2,32,FLEN)
NAN_BOXED(0x991243,32,FLEN)
NAN_BOXED(0x4e000007,32,FLEN)
NAN_BOXED(0x7e5611f2,32,FLEN)
NAN_BOXED(0x991243,32,FLEN)
NAN_BOXED(0x4e00000f,32,FLEN)
NAN_BOXED(0x7e5611f2,32,FLEN)
NAN_BOXED(0x991243,32,FLEN)
NAN_BOXED(0x4e00001f,32,FLEN)
NAN_BOXED(0x7e5611f2,32,FLEN)
NAN_BOXED(0x991243,32,FLEN)
NAN_BOXED(0x4e00003f,32,FLEN)
NAN_BOXED(0x7e5611f2,32,FLEN)
NAN_BOXED(0x991243,32,FLEN)
NAN_BOXED(0x4e00007f,32,FLEN)
NAN_BOXED(0x7e5611f2,32,FLEN)
NAN_BOXED(0x991243,32,FLEN)
NAN_BOXED(0x4e0000ff,32,FLEN)
NAN_BOXED(0x7e5611f2,32,FLEN)
NAN_BOXED(0x991243,32,FLEN)
NAN_BOXED(0x4e0001ff,32,FLEN)
NAN_BOXED(0x7e5611f2,32,FLEN)
NAN_BOXED(0x991243,32,FLEN)
NAN_BOXED(0x4e0003ff,32,FLEN)
NAN_BOXED(0x7e5611f2,32,FLEN)
NAN_BOXED(0x991243,32,FLEN)
NAN_BOXED(0x4e0007ff,32,FLEN)
NAN_BOXED(0x7e5611f2,32,FLEN)
NAN_BOXED(0x991243,32,FLEN)
NAN_BOXED(0x4e000fff,32,FLEN)
NAN_BOXED(0x7e5611f2,32,FLEN)
NAN_BOXED(0x991243,32,FLEN)
NAN_BOXED(0x4e001fff,32,FLEN)
NAN_BOXED(0x7e5611f2,32,FLEN)
NAN_BOXED(0x991243,32,FLEN)
NAN_BOXED(0x4e003fff,32,FLEN)
NAN_BOXED(0x7e5611f2,32,FLEN)
NAN_BOXED(0x991243,32,FLEN)
NAN_BOXED(0x4e007fff,32,FLEN)
NAN_BOXED(0x7e5611f2,32,FLEN)
NAN_BOXED(0x991243,32,FLEN)
NAN_BOXED(0x4e00ffff,32,FLEN)
NAN_BOXED(0x7e5611f2,32,FLEN)
NAN_BOXED(0x991243,32,FLEN)
NAN_BOXED(0x4e01ffff,32,FLEN)
NAN_BOXED(0x7e5611f2,32,FLEN)
NAN_BOXED(0x991243,32,FLEN)
NAN_BOXED(0x4e03ffff,32,FLEN)
NAN_BOXED(0x7e5611f2,32,FLEN)
NAN_BOXED(0x991243,32,FLEN)
NAN_BOXED(0x4e07ffff,32,FLEN)
NAN_BOXED(0x7e5611f2,32,FLEN)
NAN_BOXED(0x991243,32,FLEN)
NAN_BOXED(0x4e0fffff,32,FLEN)
NAN_BOXED(0x7e5611f2,32,FLEN)
NAN_BOXED(0x991243,32,FLEN)
NAN_BOXED(0x4e1fffff,32,FLEN)
NAN_BOXED(0x7e5611f2,32,FLEN)
NAN_BOXED(0x991243,32,FLEN)
NAN_BOXED(0x4e3fffff,32,FLEN)
NAN_BOXED(0x7e5611f2,32,FLEN)
NAN_BOXED(0x991243,32,FLEN)
NAN_BOXED(0x4e400000,32,FLEN)
NAN_BOXED(0x7e5611f2,32,FLEN)
NAN_BOXED(0x991243,32,FLEN)
NAN_BOXED(0x4e600000,32,FLEN)
NAN_BOXED(0x7e5611f2,32,FLEN)
NAN_BOXED(0x991243,32,FLEN)
NAN_BOXED(0x4e700000,32,FLEN)
NAN_BOXED(0x7e5611f2,32,FLEN)
NAN_BOXED(0x991243,32,FLEN)
NAN_BOXED(0x4e780000,32,FLEN)
NAN_BOXED(0x7e5611f2,32,FLEN)
NAN_BOXED(0x991243,32,FLEN)
NAN_BOXED(0x4e7c0000,32,FLEN)
NAN_BOXED(0x7e5611f2,32,FLEN)
NAN_BOXED(0x991243,32,FLEN)
NAN_BOXED(0x4e7e0000,32,FLEN)
NAN_BOXED(0x7e5611f2,32,FLEN)
NAN_BOXED(0x991243,32,FLEN)
NAN_BOXED(0x4e7f0000,32,FLEN)
NAN_BOXED(0x7e5611f2,32,FLEN)
NAN_BOXED(0x991243,32,FLEN)
NAN_BOXED(0x4e7f8000,32,FLEN)
NAN_BOXED(0x7e5611f2,32,FLEN)
NAN_BOXED(0x991243,32,FLEN)
NAN_BOXED(0x4e7fc000,32,FLEN)
NAN_BOXED(0x7e5611f2,32,FLEN)
NAN_BOXED(0x991243,32,FLEN)
NAN_BOXED(0x4e7fe000,32,FLEN)
NAN_BOXED(0x7e5611f2,32,FLEN)
NAN_BOXED(0x991243,32,FLEN)
NAN_BOXED(0x4e7ff000,32,FLEN)
NAN_BOXED(0x7e5611f2,32,FLEN)
NAN_BOXED(0x991243,32,FLEN)
NAN_BOXED(0x4e7ff800,32,FLEN)
NAN_BOXED(0x7e5611f2,32,FLEN)
NAN_BOXED(0x991243,32,FLEN)
NAN_BOXED(0x4e7ffc00,32,FLEN)
NAN_BOXED(0x7e5611f2,32,FLEN)
NAN_BOXED(0x991243,32,FLEN)
NAN_BOXED(0x4e7ffe00,32,FLEN)
NAN_BOXED(0x7e5611f2,32,FLEN)
NAN_BOXED(0x991243,32,FLEN)
NAN_BOXED(0x4e7fff00,32,FLEN)
NAN_BOXED(0x7e5611f2,32,FLEN)
NAN_BOXED(0x991243,32,FLEN)
NAN_BOXED(0x4e7fff80,32,FLEN)
NAN_BOXED(0x7e5611f2,32,FLEN)
NAN_BOXED(0x991243,32,FLEN)
NAN_BOXED(0x4e7fffc0,32,FLEN)
NAN_BOXED(0x7e5611f2,32,FLEN)
NAN_BOXED(0x991243,32,FLEN)
NAN_BOXED(0x4e7fffe0,32,FLEN)
NAN_BOXED(0x7e5611f2,32,FLEN)
NAN_BOXED(0x991243,32,FLEN)
NAN_BOXED(0x4e7ffff0,32,FLEN)
NAN_BOXED(0x7e5611f2,32,FLEN)
NAN_BOXED(0x991243,32,FLEN)
NAN_BOXED(0x4e7ffff8,32,FLEN)
NAN_BOXED(0x7e5611f2,32,FLEN)
NAN_BOXED(0x991243,32,FLEN)
NAN_BOXED(0x4e7ffffc,32,FLEN)
NAN_BOXED(0x7e5611f2,32,FLEN)
NAN_BOXED(0x991243,32,FLEN)
NAN_BOXED(0x4e7ffffe,32,FLEN)
NAN_BOXED(0x7e5611f2,32,FLEN)
NAN_BOXED(0x991243,32,FLEN)
NAN_BOXED(0x4e7fffff,32,FLEN)
NAN_BOXED(0x7e5659bb,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x80000001,32,FLEN)
NAN_BOXED(0x7e5659bb,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x80000003,32,FLEN)
NAN_BOXED(0x7e5659bb,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x80000007,32,FLEN)
NAN_BOXED(0x7e5659bb,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x80199999,32,FLEN)
NAN_BOXED(0x7e5659bb,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x80249249,32,FLEN)
NAN_BOXED(0x7e5659bb,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x80333333,32,FLEN)
NAN_BOXED(0x7e5659bb,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x8036db6d,32,FLEN)
NAN_BOXED(0x7e5659bb,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x803bbbbb,32,FLEN)
NAN_BOXED(0x7e5659bb,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x80444444,32,FLEN)
NAN_BOXED(0x7e5659bb,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x804ccccc,32,FLEN)
NAN_BOXED(0x7e5659bb,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x805b6db6,32,FLEN)
NAN_BOXED(0x7e5659bb,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x80666666,32,FLEN)
NAN_BOXED(0x7e5659bb,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x806db6db,32,FLEN)
NAN_BOXED(0x7e5659bb,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x807ffff8,32,FLEN)
NAN_BOXED(0x7e5659bb,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x807ffffc,32,FLEN)
NAN_BOXED(0x7e5659bb,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x807ffffe,32,FLEN)
NAN_BOXED(0x7e5659bb,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x86000000,32,FLEN)
NAN_BOXED(0x7e5659bb,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x86000001,32,FLEN)
NAN_BOXED(0x7e5659bb,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x86000003,32,FLEN)
NAN_BOXED(0x7e5659bb,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x86000007,32,FLEN)
NAN_BOXED(0x7e5659bb,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x8600000f,32,FLEN)
NAN_BOXED(0x7e5659bb,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x8600001f,32,FLEN)
NAN_BOXED(0x7e5659bb,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x8600003f,32,FLEN)
NAN_BOXED(0x7e5659bb,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x8600007f,32,FLEN)
NAN_BOXED(0x7e5659bb,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x860000ff,32,FLEN)
NAN_BOXED(0x7e5659bb,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x860001ff,32,FLEN)
NAN_BOXED(0x7e5659bb,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x860003ff,32,FLEN)
NAN_BOXED(0x7e5659bb,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x860007ff,32,FLEN)
NAN_BOXED(0x7e5659bb,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x86000fff,32,FLEN)
NAN_BOXED(0x7e5659bb,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x86001fff,32,FLEN)
NAN_BOXED(0x7e5659bb,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x86003fff,32,FLEN)
NAN_BOXED(0x7e5659bb,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x86007fff,32,FLEN)
NAN_BOXED(0x7e5659bb,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x8600ffff,32,FLEN)
NAN_BOXED(0x7e5659bb,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x8601ffff,32,FLEN)
NAN_BOXED(0x7e5659bb,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x8603ffff,32,FLEN)
NAN_BOXED(0x7e5659bb,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x8607ffff,32,FLEN)
NAN_BOXED(0x7e5659bb,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x860fffff,32,FLEN)
NAN_BOXED(0x7e5659bb,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x861fffff,32,FLEN)
NAN_BOXED(0x7e5659bb,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x863fffff,32,FLEN)
NAN_BOXED(0x7e5659bb,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x86400000,32,FLEN)
NAN_BOXED(0x7e5659bb,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x86600000,32,FLEN)
NAN_BOXED(0x7e5659bb,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x86700000,32,FLEN)
NAN_BOXED(0x7e5659bb,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x86780000,32,FLEN)
NAN_BOXED(0x7e5659bb,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x867c0000,32,FLEN)
NAN_BOXED(0x7e5659bb,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x867e0000,32,FLEN)
NAN_BOXED(0x7e5659bb,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x867f0000,32,FLEN)
NAN_BOXED(0x7e5659bb,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x867f8000,32,FLEN)
NAN_BOXED(0x7e5659bb,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x867fc000,32,FLEN)
NAN_BOXED(0x7e5659bb,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x867fe000,32,FLEN)
NAN_BOXED(0x7e5659bb,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x867ff000,32,FLEN)
NAN_BOXED(0x7e5659bb,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x867ff800,32,FLEN)
NAN_BOXED(0x7e5659bb,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x867ffc00,32,FLEN)
NAN_BOXED(0x7e5659bb,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x867ffe00,32,FLEN)
NAN_BOXED(0x7e5659bb,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x867fff00,32,FLEN)
NAN_BOXED(0x7e5659bb,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x867fff80,32,FLEN)
NAN_BOXED(0x7e5659bb,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x867fffc0,32,FLEN)
NAN_BOXED(0x7e5659bb,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x867fffe0,32,FLEN)
NAN_BOXED(0x7e5659bb,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x867ffff0,32,FLEN)
NAN_BOXED(0x7e5659bb,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x867ffff8,32,FLEN)
NAN_BOXED(0x7e5659bb,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x867ffffc,32,FLEN)
NAN_BOXED(0x7e5659bb,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x867ffffe,32,FLEN)
NAN_BOXED(0x7e5659bb,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x867fffff,32,FLEN)
NAN_BOXED(0x7e56eede,32,FLEN)
NAN_BOXED(0xc09874ed,32,FLEN)
NAN_BOXED(0xe7000000,32,FLEN)
NAN_BOXED(0x7e56eede,32,FLEN)
NAN_BOXED(0xc09874ed,32,FLEN)
NAN_BOXED(0xe7000001,32,FLEN)
NAN_BOXED(0x7e56eede,32,FLEN)
NAN_BOXED(0xc09874ed,32,FLEN)
NAN_BOXED(0xe7000003,32,FLEN)
NAN_BOXED(0x7e56eede,32,FLEN)
NAN_BOXED(0xc09874ed,32,FLEN)
NAN_BOXED(0xe7000007,32,FLEN)
NAN_BOXED(0x7e56eede,32,FLEN)
NAN_BOXED(0xc09874ed,32,FLEN)
NAN_BOXED(0xe700000f,32,FLEN)
NAN_BOXED(0x7e56eede,32,FLEN)
NAN_BOXED(0xc09874ed,32,FLEN)
NAN_BOXED(0xe700001f,32,FLEN)
NAN_BOXED(0x7e56eede,32,FLEN)
NAN_BOXED(0xc09874ed,32,FLEN)
NAN_BOXED(0xe700003f,32,FLEN)
NAN_BOXED(0x7e56eede,32,FLEN)
NAN_BOXED(0xc09874ed,32,FLEN)
NAN_BOXED(0xe700007f,32,FLEN)
NAN_BOXED(0x7e56eede,32,FLEN)
NAN_BOXED(0xc09874ed,32,FLEN)
NAN_BOXED(0xe70000ff,32,FLEN)
NAN_BOXED(0x7e56eede,32,FLEN)
NAN_BOXED(0xc09874ed,32,FLEN)
NAN_BOXED(0xe70001ff,32,FLEN)
NAN_BOXED(0x7e56eede,32,FLEN)
NAN_BOXED(0xc09874ed,32,FLEN)
NAN_BOXED(0xe70003ff,32,FLEN)
NAN_BOXED(0x7e56eede,32,FLEN)
NAN_BOXED(0xc09874ed,32,FLEN)
NAN_BOXED(0xe70007ff,32,FLEN)
NAN_BOXED(0x7e56eede,32,FLEN)
NAN_BOXED(0xc09874ed,32,FLEN)
NAN_BOXED(0xe7000fff,32,FLEN)
NAN_BOXED(0x7e56eede,32,FLEN)
NAN_BOXED(0xc09874ed,32,FLEN)
NAN_BOXED(0xe7001fff,32,FLEN)
NAN_BOXED(0x7e56eede,32,FLEN)
NAN_BOXED(0xc09874ed,32,FLEN)
NAN_BOXED(0xe7003fff,32,FLEN)
NAN_BOXED(0x7e56eede,32,FLEN)
NAN_BOXED(0xc09874ed,32,FLEN)
NAN_BOXED(0xe7007fff,32,FLEN)
NAN_BOXED(0x7e56eede,32,FLEN)
NAN_BOXED(0xc09874ed,32,FLEN)
NAN_BOXED(0xe700ffff,32,FLEN)
NAN_BOXED(0x7e56eede,32,FLEN)
NAN_BOXED(0xc09874ed,32,FLEN)
NAN_BOXED(0xe701ffff,32,FLEN)
NAN_BOXED(0x7e56eede,32,FLEN)
NAN_BOXED(0xc09874ed,32,FLEN)
NAN_BOXED(0xe703ffff,32,FLEN)
NAN_BOXED(0x7e56eede,32,FLEN)
NAN_BOXED(0xc09874ed,32,FLEN)
NAN_BOXED(0xe707ffff,32,FLEN)
NAN_BOXED(0x7e56eede,32,FLEN)
NAN_BOXED(0xc09874ed,32,FLEN)
NAN_BOXED(0xe70fffff,32,FLEN)
NAN_BOXED(0x7e56eede,32,FLEN)
NAN_BOXED(0xc09874ed,32,FLEN)
NAN_BOXED(0xe71fffff,32,FLEN)
NAN_BOXED(0x7e56eede,32,FLEN)
NAN_BOXED(0xc09874ed,32,FLEN)
NAN_BOXED(0xe73fffff,32,FLEN)
NAN_BOXED(0x7e56eede,32,FLEN)
NAN_BOXED(0xc09874ed,32,FLEN)
NAN_BOXED(0xe7400000,32,FLEN)
NAN_BOXED(0x7e56eede,32,FLEN)
NAN_BOXED(0xc09874ed,32,FLEN)
NAN_BOXED(0xe7600000,32,FLEN)
NAN_BOXED(0x7e56eede,32,FLEN)
NAN_BOXED(0xc09874ed,32,FLEN)
NAN_BOXED(0xe7700000,32,FLEN)
NAN_BOXED(0x7e56eede,32,FLEN)
NAN_BOXED(0xc09874ed,32,FLEN)
NAN_BOXED(0xe7780000,32,FLEN)
NAN_BOXED(0x7e56eede,32,FLEN)
NAN_BOXED(0xc09874ed,32,FLEN)
NAN_BOXED(0xe77c0000,32,FLEN)
NAN_BOXED(0x7e56eede,32,FLEN)
NAN_BOXED(0xc09874ed,32,FLEN)
NAN_BOXED(0xe77e0000,32,FLEN)
NAN_BOXED(0x7e56eede,32,FLEN)
NAN_BOXED(0xc09874ed,32,FLEN)
NAN_BOXED(0xe77f0000,32,FLEN)
NAN_BOXED(0x7e56eede,32,FLEN)
NAN_BOXED(0xc09874ed,32,FLEN)
NAN_BOXED(0xe77f8000,32,FLEN)
NAN_BOXED(0x7e56eede,32,FLEN)
NAN_BOXED(0xc09874ed,32,FLEN)
NAN_BOXED(0xe77fc000,32,FLEN)
NAN_BOXED(0x7e56eede,32,FLEN)
NAN_BOXED(0xc09874ed,32,FLEN)
NAN_BOXED(0xe77fe000,32,FLEN)
NAN_BOXED(0x7e56eede,32,FLEN)
NAN_BOXED(0xc09874ed,32,FLEN)
NAN_BOXED(0xe77ff000,32,FLEN)
NAN_BOXED(0x7e56eede,32,FLEN)
NAN_BOXED(0xc09874ed,32,FLEN)
NAN_BOXED(0xe77ff800,32,FLEN)
NAN_BOXED(0x7e56eede,32,FLEN)
NAN_BOXED(0xc09874ed,32,FLEN)
NAN_BOXED(0xe77ffc00,32,FLEN)
NAN_BOXED(0x7e56eede,32,FLEN)
NAN_BOXED(0xc09874ed,32,FLEN)
NAN_BOXED(0xe77ffe00,32,FLEN)
NAN_BOXED(0x7e56eede,32,FLEN)
NAN_BOXED(0xc09874ed,32,FLEN)
NAN_BOXED(0xe77fff00,32,FLEN)
NAN_BOXED(0x7e56eede,32,FLEN)
NAN_BOXED(0xc09874ed,32,FLEN)
NAN_BOXED(0xe77fff80,32,FLEN)
NAN_BOXED(0x7e56eede,32,FLEN)
NAN_BOXED(0xc09874ed,32,FLEN)
NAN_BOXED(0xe77fffc0,32,FLEN)
NAN_BOXED(0x7e56eede,32,FLEN)
NAN_BOXED(0xc09874ed,32,FLEN)
NAN_BOXED(0xe77fffe0,32,FLEN)
NAN_BOXED(0x7e56eede,32,FLEN)
NAN_BOXED(0xc09874ed,32,FLEN)
NAN_BOXED(0xe77ffff0,32,FLEN)
NAN_BOXED(0x7e56eede,32,FLEN)
NAN_BOXED(0xc09874ed,32,FLEN)
NAN_BOXED(0xe77ffff8,32,FLEN)
NAN_BOXED(0x7e56eede,32,FLEN)
NAN_BOXED(0xc09874ed,32,FLEN)
NAN_BOXED(0xe77ffffc,32,FLEN)
NAN_BOXED(0x7e56eede,32,FLEN)
NAN_BOXED(0xc09874ed,32,FLEN)
NAN_BOXED(0xe77ffffe,32,FLEN)
NAN_BOXED(0x7e56eede,32,FLEN)
NAN_BOXED(0xc09874ed,32,FLEN)
NAN_BOXED(0xe77fffff,32,FLEN)
NAN_BOXED(0x7e56eede,32,FLEN)
NAN_BOXED(0xc09874ed,32,FLEN)
NAN_BOXED(0xff000001,32,FLEN)
NAN_BOXED(0x7e56eede,32,FLEN)
NAN_BOXED(0xc09874ed,32,FLEN)
NAN_BOXED(0xff000003,32,FLEN)
NAN_BOXED(0x7e56eede,32,FLEN)
NAN_BOXED(0xc09874ed,32,FLEN)
NAN_BOXED(0xff000007,32,FLEN)
NAN_BOXED(0x7e56eede,32,FLEN)
NAN_BOXED(0xc09874ed,32,FLEN)
NAN_BOXED(0xff199999,32,FLEN)
NAN_BOXED(0x7e56eede,32,FLEN)
NAN_BOXED(0xc09874ed,32,FLEN)
NAN_BOXED(0xff249249,32,FLEN)
NAN_BOXED(0x7e56eede,32,FLEN)
NAN_BOXED(0xc09874ed,32,FLEN)
NAN_BOXED(0xff333333,32,FLEN)
NAN_BOXED(0x7e56eede,32,FLEN)
NAN_BOXED(0xc09874ed,32,FLEN)
NAN_BOXED(0xff36db6d,32,FLEN)
NAN_BOXED(0x7e56eede,32,FLEN)
NAN_BOXED(0xc09874ed,32,FLEN)
NAN_BOXED(0xff3bbbbb,32,FLEN)
NAN_BOXED(0x7e56eede,32,FLEN)
NAN_BOXED(0xc09874ed,32,FLEN)
NAN_BOXED(0xff444444,32,FLEN)
NAN_BOXED(0x7e56eede,32,FLEN)
NAN_BOXED(0xc09874ed,32,FLEN)
NAN_BOXED(0xff4ccccc,32,FLEN)
NAN_BOXED(0x7e56eede,32,FLEN)
NAN_BOXED(0xc09874ed,32,FLEN)
NAN_BOXED(0xff5b6db6,32,FLEN)
NAN_BOXED(0x7e56eede,32,FLEN)
NAN_BOXED(0xc09874ed,32,FLEN)
NAN_BOXED(0xff666666,32,FLEN)
NAN_BOXED(0x7e56eede,32,FLEN)
NAN_BOXED(0xc09874ed,32,FLEN)
NAN_BOXED(0xff6db6db,32,FLEN)
NAN_BOXED(0x7e56eede,32,FLEN)
NAN_BOXED(0xc09874ed,32,FLEN)
NAN_BOXED(0xff7ffff8,32,FLEN)
NAN_BOXED(0x7e56eede,32,FLEN)
NAN_BOXED(0xc09874ed,32,FLEN)
NAN_BOXED(0xff7ffffc,32,FLEN)
NAN_BOXED(0x7e56eede,32,FLEN)
NAN_BOXED(0xc09874ed,32,FLEN)
NAN_BOXED(0xff7ffffe,32,FLEN)
NAN_BOXED(0x7e579c96,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x800001,32,FLEN)
NAN_BOXED(0x7e579c96,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x800003,32,FLEN)
NAN_BOXED(0x7e579c96,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x800007,32,FLEN)
NAN_BOXED(0x7e579c96,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x999999,32,FLEN)
NAN_BOXED(0x7e579c96,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xa49249,32,FLEN)
NAN_BOXED(0x7e579c96,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xb33333,32,FLEN)
NAN_BOXED(0x7e579c96,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xb6db6d,32,FLEN)
NAN_BOXED(0x7e579c96,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xbbbbbb,32,FLEN)
NAN_BOXED(0x7e579c96,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xc44444,32,FLEN)
NAN_BOXED(0x7e579c96,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xcccccc,32,FLEN)
NAN_BOXED(0x7e579c96,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xdb6db6,32,FLEN)
NAN_BOXED(0x7e579c96,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xe66666,32,FLEN)
NAN_BOXED(0x7e579c96,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xedb6db,32,FLEN)
NAN_BOXED(0x7e579c96,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xfffff8,32,FLEN)
NAN_BOXED(0x7e579c96,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xfffffc,32,FLEN)
NAN_BOXED(0x7e579c96,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xfffffe,32,FLEN)
NAN_BOXED(0x7e579c96,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x7000000,32,FLEN)
NAN_BOXED(0x7e579c96,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x7000001,32,FLEN)
NAN_BOXED(0x7e579c96,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x7000003,32,FLEN)
NAN_BOXED(0x7e579c96,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x7000007,32,FLEN)
NAN_BOXED(0x7e579c96,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x700000f,32,FLEN)
NAN_BOXED(0x7e579c96,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x700001f,32,FLEN)
NAN_BOXED(0x7e579c96,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x700003f,32,FLEN)
NAN_BOXED(0x7e579c96,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x700007f,32,FLEN)
NAN_BOXED(0x7e579c96,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x70000ff,32,FLEN)
NAN_BOXED(0x7e579c96,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x70001ff,32,FLEN)
NAN_BOXED(0x7e579c96,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x70003ff,32,FLEN)
NAN_BOXED(0x7e579c96,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x70007ff,32,FLEN)
NAN_BOXED(0x7e579c96,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x7000fff,32,FLEN)
NAN_BOXED(0x7e579c96,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x7001fff,32,FLEN)
NAN_BOXED(0x7e579c96,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x7003fff,32,FLEN)
NAN_BOXED(0x7e579c96,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x7007fff,32,FLEN)
NAN_BOXED(0x7e579c96,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x700ffff,32,FLEN)
NAN_BOXED(0x7e579c96,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x701ffff,32,FLEN)
NAN_BOXED(0x7e579c96,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x703ffff,32,FLEN)
NAN_BOXED(0x7e579c96,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x707ffff,32,FLEN)
NAN_BOXED(0x7e579c96,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x70fffff,32,FLEN)
NAN_BOXED(0x7e579c96,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x71fffff,32,FLEN)
NAN_BOXED(0x7e579c96,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x73fffff,32,FLEN)
NAN_BOXED(0x7e579c96,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x7400000,32,FLEN)
NAN_BOXED(0x7e579c96,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x7600000,32,FLEN)
NAN_BOXED(0x7e579c96,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x7700000,32,FLEN)
NAN_BOXED(0x7e579c96,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x7780000,32,FLEN)
NAN_BOXED(0x7e579c96,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x77c0000,32,FLEN)
NAN_BOXED(0x7e579c96,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x77e0000,32,FLEN)
NAN_BOXED(0x7e579c96,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x77f0000,32,FLEN)
NAN_BOXED(0x7e579c96,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x77f8000,32,FLEN)
NAN_BOXED(0x7e579c96,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x77fc000,32,FLEN)
NAN_BOXED(0x7e579c96,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x77fe000,32,FLEN)
NAN_BOXED(0x7e579c96,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x77ff000,32,FLEN)
NAN_BOXED(0x7e579c96,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x77ff800,32,FLEN)
NAN_BOXED(0x7e579c96,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x77ffc00,32,FLEN)
NAN_BOXED(0x7e579c96,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x77ffe00,32,FLEN)
NAN_BOXED(0x7e579c96,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x77fff00,32,FLEN)
NAN_BOXED(0x7e579c96,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x77fff80,32,FLEN)
NAN_BOXED(0x7e579c96,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x77fffc0,32,FLEN)
NAN_BOXED(0x7e579c96,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x77fffe0,32,FLEN)
NAN_BOXED(0x7e579c96,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x77ffff0,32,FLEN)
NAN_BOXED(0x7e579c96,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x77ffff8,32,FLEN)
NAN_BOXED(0x7e579c96,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x77ffffc,32,FLEN)
NAN_BOXED(0x7e579c96,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x77ffffe,32,FLEN)
NAN_BOXED(0x7e579c96,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x77fffff,32,FLEN)
NAN_BOXED(0x7e591432,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x1,32,FLEN)
NAN_BOXED(0x7e591432,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x3,32,FLEN)
NAN_BOXED(0x7e591432,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x7,32,FLEN)
NAN_BOXED(0x7e591432,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x199999,32,FLEN)
NAN_BOXED(0x7e591432,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x249249,32,FLEN)
NAN_BOXED(0x7e591432,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x333333,32,FLEN)
NAN_BOXED(0x7e591432,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x36db6d,32,FLEN)
NAN_BOXED(0x7e591432,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x3bbbbb,32,FLEN)
NAN_BOXED(0x7e591432,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x444444,32,FLEN)
NAN_BOXED(0x7e591432,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x4ccccc,32,FLEN)
NAN_BOXED(0x7e591432,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x5b6db6,32,FLEN)
NAN_BOXED(0x7e591432,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x666666,32,FLEN)
NAN_BOXED(0x7e591432,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x6db6db,32,FLEN)
NAN_BOXED(0x7e591432,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x7ffff8,32,FLEN)
NAN_BOXED(0x7e591432,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x7ffffc,32,FLEN)
NAN_BOXED(0x7e591432,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x7ffffe,32,FLEN)
NAN_BOXED(0x7e591432,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xb800000,32,FLEN)
NAN_BOXED(0x7e591432,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xb800001,32,FLEN)
NAN_BOXED(0x7e591432,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xb800003,32,FLEN)
NAN_BOXED(0x7e591432,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xb800007,32,FLEN)
NAN_BOXED(0x7e591432,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xb80000f,32,FLEN)
NAN_BOXED(0x7e591432,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xb80001f,32,FLEN)
NAN_BOXED(0x7e591432,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xb80003f,32,FLEN)
NAN_BOXED(0x7e591432,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xb80007f,32,FLEN)
NAN_BOXED(0x7e591432,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xb8000ff,32,FLEN)
NAN_BOXED(0x7e591432,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xb8001ff,32,FLEN)
NAN_BOXED(0x7e591432,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xb8003ff,32,FLEN)
NAN_BOXED(0x7e591432,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xb8007ff,32,FLEN)
NAN_BOXED(0x7e591432,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xb800fff,32,FLEN)
NAN_BOXED(0x7e591432,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xb801fff,32,FLEN)
NAN_BOXED(0x7e591432,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xb803fff,32,FLEN)
NAN_BOXED(0x7e591432,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xb807fff,32,FLEN)
NAN_BOXED(0x7e591432,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xb80ffff,32,FLEN)
NAN_BOXED(0x7e591432,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xb81ffff,32,FLEN)
NAN_BOXED(0x7e591432,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xb83ffff,32,FLEN)
NAN_BOXED(0x7e591432,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xb87ffff,32,FLEN)
NAN_BOXED(0x7e591432,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xb8fffff,32,FLEN)
NAN_BOXED(0x7e591432,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xb9fffff,32,FLEN)
NAN_BOXED(0x7e591432,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xbbfffff,32,FLEN)
NAN_BOXED(0x7e591432,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xbc00000,32,FLEN)
NAN_BOXED(0x7e591432,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xbe00000,32,FLEN)
NAN_BOXED(0x7e591432,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xbf00000,32,FLEN)
NAN_BOXED(0x7e591432,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xbf80000,32,FLEN)
NAN_BOXED(0x7e591432,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xbfc0000,32,FLEN)
NAN_BOXED(0x7e591432,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xbfe0000,32,FLEN)
NAN_BOXED(0x7e591432,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xbff0000,32,FLEN)
NAN_BOXED(0x7e591432,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xbff8000,32,FLEN)
NAN_BOXED(0x7e591432,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xbffc000,32,FLEN)
NAN_BOXED(0x7e591432,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xbffe000,32,FLEN)
NAN_BOXED(0x7e591432,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xbfff000,32,FLEN)
NAN_BOXED(0x7e591432,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xbfff800,32,FLEN)
NAN_BOXED(0x7e591432,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xbfffc00,32,FLEN)
NAN_BOXED(0x7e591432,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xbfffe00,32,FLEN)
NAN_BOXED(0x7e591432,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xbffff00,32,FLEN)
NAN_BOXED(0x7e591432,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xbffff80,32,FLEN)
NAN_BOXED(0x7e591432,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xbffffc0,32,FLEN)
NAN_BOXED(0x7e591432,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xbffffe0,32,FLEN)
NAN_BOXED(0x7e591432,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xbfffff0,32,FLEN)
NAN_BOXED(0x7e591432,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xbfffff8,32,FLEN)
NAN_BOXED(0x7e591432,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xbfffffc,32,FLEN)
NAN_BOXED(0x7e591432,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xbfffffe,32,FLEN)
NAN_BOXED(0x7e591432,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xbffffff,32,FLEN)
NAN_BOXED(0x7e5bab1f,32,FLEN)
NAN_BOXED(0x952b96,32,FLEN)
NAN_BOXED(0x37000000,32,FLEN)
NAN_BOXED(0x7e5bab1f,32,FLEN)
NAN_BOXED(0x952b96,32,FLEN)
NAN_BOXED(0x37000001,32,FLEN)
NAN_BOXED(0x7e5bab1f,32,FLEN)
NAN_BOXED(0x952b96,32,FLEN)
NAN_BOXED(0x37000003,32,FLEN)
NAN_BOXED(0x7e5bab1f,32,FLEN)
NAN_BOXED(0x952b96,32,FLEN)
NAN_BOXED(0x37000007,32,FLEN)
NAN_BOXED(0x7e5bab1f,32,FLEN)
NAN_BOXED(0x952b96,32,FLEN)
NAN_BOXED(0x3700000f,32,FLEN)
NAN_BOXED(0x7e5bab1f,32,FLEN)
NAN_BOXED(0x952b96,32,FLEN)
NAN_BOXED(0x3700001f,32,FLEN)
NAN_BOXED(0x7e5bab1f,32,FLEN)
NAN_BOXED(0x952b96,32,FLEN)
NAN_BOXED(0x3700003f,32,FLEN)
NAN_BOXED(0x7e5bab1f,32,FLEN)
NAN_BOXED(0x952b96,32,FLEN)
NAN_BOXED(0x3700007f,32,FLEN)
NAN_BOXED(0x7e5bab1f,32,FLEN)
NAN_BOXED(0x952b96,32,FLEN)
NAN_BOXED(0x370000ff,32,FLEN)
NAN_BOXED(0x7e5bab1f,32,FLEN)
NAN_BOXED(0x952b96,32,FLEN)
NAN_BOXED(0x370001ff,32,FLEN)
NAN_BOXED(0x7e5bab1f,32,FLEN)
NAN_BOXED(0x952b96,32,FLEN)
NAN_BOXED(0x370003ff,32,FLEN)
NAN_BOXED(0x7e5bab1f,32,FLEN)
NAN_BOXED(0x952b96,32,FLEN)
NAN_BOXED(0x370007ff,32,FLEN)
NAN_BOXED(0x7e5bab1f,32,FLEN)
NAN_BOXED(0x952b96,32,FLEN)
NAN_BOXED(0x37000fff,32,FLEN)
NAN_BOXED(0x7e5bab1f,32,FLEN)
NAN_BOXED(0x952b96,32,FLEN)
NAN_BOXED(0x37001fff,32,FLEN)
NAN_BOXED(0x7e5bab1f,32,FLEN)
NAN_BOXED(0x952b96,32,FLEN)
NAN_BOXED(0x37003fff,32,FLEN)
NAN_BOXED(0x7e5bab1f,32,FLEN)
NAN_BOXED(0x952b96,32,FLEN)
NAN_BOXED(0x37007fff,32,FLEN)
NAN_BOXED(0x7e5bab1f,32,FLEN)
NAN_BOXED(0x952b96,32,FLEN)
NAN_BOXED(0x3700ffff,32,FLEN)
NAN_BOXED(0x7e5bab1f,32,FLEN)
NAN_BOXED(0x952b96,32,FLEN)
NAN_BOXED(0x3701ffff,32,FLEN)
NAN_BOXED(0x7e5bab1f,32,FLEN)
NAN_BOXED(0x952b96,32,FLEN)
NAN_BOXED(0x3703ffff,32,FLEN)
NAN_BOXED(0x7e5bab1f,32,FLEN)
NAN_BOXED(0x952b96,32,FLEN)
NAN_BOXED(0x3707ffff,32,FLEN)
NAN_BOXED(0x7e5bab1f,32,FLEN)
NAN_BOXED(0x952b96,32,FLEN)
NAN_BOXED(0x370fffff,32,FLEN)
NAN_BOXED(0x7e5bab1f,32,FLEN)
NAN_BOXED(0x952b96,32,FLEN)
NAN_BOXED(0x371fffff,32,FLEN)
NAN_BOXED(0x7e5bab1f,32,FLEN)
NAN_BOXED(0x952b96,32,FLEN)
NAN_BOXED(0x373fffff,32,FLEN)
NAN_BOXED(0x7e5bab1f,32,FLEN)
NAN_BOXED(0x952b96,32,FLEN)
NAN_BOXED(0x37400000,32,FLEN)
NAN_BOXED(0x7e5bab1f,32,FLEN)
NAN_BOXED(0x952b96,32,FLEN)
NAN_BOXED(0x37600000,32,FLEN)
NAN_BOXED(0x7e5bab1f,32,FLEN)
NAN_BOXED(0x952b96,32,FLEN)
NAN_BOXED(0x37700000,32,FLEN)
NAN_BOXED(0x7e5bab1f,32,FLEN)
NAN_BOXED(0x952b96,32,FLEN)
NAN_BOXED(0x37780000,32,FLEN)
NAN_BOXED(0x7e5bab1f,32,FLEN)
NAN_BOXED(0x952b96,32,FLEN)
NAN_BOXED(0x377c0000,32,FLEN)
NAN_BOXED(0x7e5bab1f,32,FLEN)
NAN_BOXED(0x952b96,32,FLEN)
NAN_BOXED(0x377e0000,32,FLEN)
NAN_BOXED(0x7e5bab1f,32,FLEN)
NAN_BOXED(0x952b96,32,FLEN)
NAN_BOXED(0x377f0000,32,FLEN)
NAN_BOXED(0x7e5bab1f,32,FLEN)
NAN_BOXED(0x952b96,32,FLEN)
NAN_BOXED(0x377f8000,32,FLEN)
NAN_BOXED(0x7e5bab1f,32,FLEN)
NAN_BOXED(0x952b96,32,FLEN)
NAN_BOXED(0x377fc000,32,FLEN)
NAN_BOXED(0x7e5bab1f,32,FLEN)
NAN_BOXED(0x952b96,32,FLEN)
NAN_BOXED(0x377fe000,32,FLEN)
NAN_BOXED(0x7e5bab1f,32,FLEN)
NAN_BOXED(0x952b96,32,FLEN)
NAN_BOXED(0x377ff000,32,FLEN)
NAN_BOXED(0x7e5bab1f,32,FLEN)
NAN_BOXED(0x952b96,32,FLEN)
NAN_BOXED(0x377ff800,32,FLEN)
NAN_BOXED(0x7e5bab1f,32,FLEN)
NAN_BOXED(0x952b96,32,FLEN)
NAN_BOXED(0x377ffc00,32,FLEN)
NAN_BOXED(0x7e5bab1f,32,FLEN)
NAN_BOXED(0x952b96,32,FLEN)
NAN_BOXED(0x377ffe00,32,FLEN)
NAN_BOXED(0x7e5bab1f,32,FLEN)
NAN_BOXED(0x952b96,32,FLEN)
NAN_BOXED(0x377fff00,32,FLEN)
NAN_BOXED(0x7e5bab1f,32,FLEN)
NAN_BOXED(0x952b96,32,FLEN)
NAN_BOXED(0x377fff80,32,FLEN)
RVTEST_DATA_END

RVMODEL_DATA_BEGIN
rvtest_sig_begin:
sig_begin_canary:
CANARY;


signature_x1_0:
    .fill 0*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_1:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_2:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_3:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_4:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_5:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_6:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef

#ifdef rvtest_mtrap_routine

tsig_begin_canary:
CANARY;
tsig_begin_canary:
CANARY;
mtrap_sigptr:
    .fill 64*(XLEN/32),4,0xdeadbeef
tsig_end_canary:
CANARY;
tsig_end_canary:
CANARY;

#endif

#ifdef rvtest_gpr_save

gpr_save:
    .fill 32*XLEN/32,4,0xdeadbeef

#endif

sig_end_canary:
CANARY;
rvtest_sig_end:
RVMODEL_DATA_END
