
// -----------
// This file was generated by riscv_ctg (https://github.com/riscv-software-src/riscv-ctg)
// version   : 0.11.0
// timestamp : Tue Jan 30 08:43:45 2024 GMT
// usage     : riscv_ctg \
//                  -- cgf //                  --cgf /home/riscv/riscv-ctg/sample_cgfs/dataset.cgf \
//                  --cgf /home/riscv/riscv-ctg/sample_cgfs/sample_cgfs_fext/RV32H/rv32h_fmsub.cgf \
 \
//                  -- xlen 32  \
// -----------
//
// -----------
// Copyright (c) 2020. RISC-V International. All rights reserved.
// SPDX-License-Identifier: BSD-3-Clause
// -----------
//
// This assembly file tests the fmsub.h instruction of the RISC-V RV32F_Zicsr_Zfh,RV64F_Zicsr_Zfh extension for the fmsub_b1 covergroup.
// 
#include "model_test.h"
#include "arch_test.h"
RVTEST_ISA("RV32IF_Zicsr_Zfh,RV64IF_Zicsr_Zfh")

.section .text.init
.globl rvtest_entry_point
rvtest_entry_point:
RVMODEL_BOOT
RVTEST_CODE_BEGIN

#ifdef TEST_CASE_1

RVTEST_CASE(0,"//check ISA:=regex(.*I.*F.*Zfh.*);def TEST_CASE_1=True;",fmsub_b1)

RVTEST_FP_ENABLE()
RVTEST_VALBASEUPD(x3,test_dataset_0)
RVTEST_SIGBASE(x1,signature_x1_1)

inst_9971:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfe00; op2val:0x83ff;
op3val:0x8455; valaddr_reg:x3; val_offset:29913*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 29913*FLEN/8, x4, x1, x2)

inst_9972:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfe00; op2val:0x83ff;
op3val:0x7bff; valaddr_reg:x3; val_offset:29916*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 29916*FLEN/8, x4, x1, x2)

inst_9973:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfe00; op2val:0x83ff;
op3val:0xfbff; valaddr_reg:x3; val_offset:29919*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 29919*FLEN/8, x4, x1, x2)

inst_9974:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfe00; op2val:0x83ff;
op3val:0x7c00; valaddr_reg:x3; val_offset:29922*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 29922*FLEN/8, x4, x1, x2)

inst_9975:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfe00; op2val:0x83ff;
op3val:0xfc00; valaddr_reg:x3; val_offset:29925*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 29925*FLEN/8, x4, x1, x2)

inst_9976:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfe00; op2val:0x83ff;
op3val:0x7e00; valaddr_reg:x3; val_offset:29928*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 29928*FLEN/8, x4, x1, x2)

inst_9977:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfe00; op2val:0x83ff;
op3val:0xfe00; valaddr_reg:x3; val_offset:29931*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 29931*FLEN/8, x4, x1, x2)

inst_9978:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x1f and fm3 == 0x201 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfe00; op2val:0x83ff;
op3val:0x7e01; valaddr_reg:x3; val_offset:29934*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 29934*FLEN/8, x4, x1, x2)

inst_9979:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x1f and fm3 == 0x255 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfe00; op2val:0x83ff;
op3val:0xfe55; valaddr_reg:x3; val_offset:29937*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 29937*FLEN/8, x4, x1, x2)

inst_9980:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x1f and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfe00; op2val:0x83ff;
op3val:0x7c01; valaddr_reg:x3; val_offset:29940*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 29940*FLEN/8, x4, x1, x2)

inst_9981:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x1f and fm3 == 0x155 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfe00; op2val:0x83ff;
op3val:0xfd55; valaddr_reg:x3; val_offset:29943*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 29943*FLEN/8, x4, x1, x2)

inst_9982:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfe00; op2val:0x83ff;
op3val:0x3c00; valaddr_reg:x3; val_offset:29946*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 29946*FLEN/8, x4, x1, x2)

inst_9983:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfe00; op2val:0x83ff;
op3val:0xbc00; valaddr_reg:x3; val_offset:29949*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 29949*FLEN/8, x4, x1, x2)

RVTEST_SIGBASE(x1,signature_x1_79)
inst_9984:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfe00; op2val:0x400;
op3val:0x0; valaddr_reg:x3; val_offset:29952*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 29952*FLEN/8, x4, x1, x2)

inst_9985:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfe00; op2val:0x400;
op3val:0x8000; valaddr_reg:x3; val_offset:29955*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 29955*FLEN/8, x4, x1, x2)

inst_9986:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfe00; op2val:0x400;
op3val:0x1; valaddr_reg:x3; val_offset:29958*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 29958*FLEN/8, x4, x1, x2)

inst_9987:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfe00; op2val:0x400;
op3val:0x8001; valaddr_reg:x3; val_offset:29961*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 29961*FLEN/8, x4, x1, x2)

inst_9988:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x002 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfe00; op2val:0x400;
op3val:0x2; valaddr_reg:x3; val_offset:29964*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 29964*FLEN/8, x4, x1, x2)

inst_9989:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3fe and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfe00; op2val:0x400;
op3val:0x83fe; valaddr_reg:x3; val_offset:29967*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 29967*FLEN/8, x4, x1, x2)

inst_9990:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfe00; op2val:0x400;
op3val:0x3ff; valaddr_reg:x3; val_offset:29970*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 29970*FLEN/8, x4, x1, x2)

inst_9991:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfe00; op2val:0x400;
op3val:0x83ff; valaddr_reg:x3; val_offset:29973*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 29973*FLEN/8, x4, x1, x2)

inst_9992:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfe00; op2val:0x400;
op3val:0x400; valaddr_reg:x3; val_offset:29976*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 29976*FLEN/8, x4, x1, x2)

inst_9993:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfe00; op2val:0x400;
op3val:0x8400; valaddr_reg:x3; val_offset:29979*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 29979*FLEN/8, x4, x1, x2)

inst_9994:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfe00; op2val:0x400;
op3val:0x401; valaddr_reg:x3; val_offset:29982*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 29982*FLEN/8, x4, x1, x2)

inst_9995:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfe00; op2val:0x400;
op3val:0x8455; valaddr_reg:x3; val_offset:29985*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 29985*FLEN/8, x4, x1, x2)

inst_9996:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfe00; op2val:0x400;
op3val:0x7bff; valaddr_reg:x3; val_offset:29988*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 29988*FLEN/8, x4, x1, x2)

inst_9997:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfe00; op2val:0x400;
op3val:0xfbff; valaddr_reg:x3; val_offset:29991*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 29991*FLEN/8, x4, x1, x2)

inst_9998:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfe00; op2val:0x400;
op3val:0x7c00; valaddr_reg:x3; val_offset:29994*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 29994*FLEN/8, x4, x1, x2)

inst_9999:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfe00; op2val:0x400;
op3val:0xfc00; valaddr_reg:x3; val_offset:29997*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 29997*FLEN/8, x4, x1, x2)

inst_10000:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfe00; op2val:0x400;
op3val:0x7e00; valaddr_reg:x3; val_offset:30000*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 30000*FLEN/8, x4, x1, x2)

inst_10001:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfe00; op2val:0x400;
op3val:0xfe00; valaddr_reg:x3; val_offset:30003*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 30003*FLEN/8, x4, x1, x2)

inst_10002:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x201 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfe00; op2val:0x400;
op3val:0x7e01; valaddr_reg:x3; val_offset:30006*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 30006*FLEN/8, x4, x1, x2)

inst_10003:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x255 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfe00; op2val:0x400;
op3val:0xfe55; valaddr_reg:x3; val_offset:30009*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 30009*FLEN/8, x4, x1, x2)

inst_10004:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfe00; op2val:0x400;
op3val:0x7c01; valaddr_reg:x3; val_offset:30012*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 30012*FLEN/8, x4, x1, x2)

inst_10005:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x155 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfe00; op2val:0x400;
op3val:0xfd55; valaddr_reg:x3; val_offset:30015*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 30015*FLEN/8, x4, x1, x2)

inst_10006:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfe00; op2val:0x400;
op3val:0x3c00; valaddr_reg:x3; val_offset:30018*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 30018*FLEN/8, x4, x1, x2)

inst_10007:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfe00; op2val:0x400;
op3val:0xbc00; valaddr_reg:x3; val_offset:30021*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 30021*FLEN/8, x4, x1, x2)

inst_10008:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfe00; op2val:0x8400;
op3val:0x0; valaddr_reg:x3; val_offset:30024*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 30024*FLEN/8, x4, x1, x2)

inst_10009:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfe00; op2val:0x8400;
op3val:0x8000; valaddr_reg:x3; val_offset:30027*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 30027*FLEN/8, x4, x1, x2)

inst_10010:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfe00; op2val:0x8400;
op3val:0x1; valaddr_reg:x3; val_offset:30030*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 30030*FLEN/8, x4, x1, x2)

inst_10011:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfe00; op2val:0x8400;
op3val:0x8001; valaddr_reg:x3; val_offset:30033*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 30033*FLEN/8, x4, x1, x2)

inst_10012:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x002 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfe00; op2val:0x8400;
op3val:0x2; valaddr_reg:x3; val_offset:30036*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 30036*FLEN/8, x4, x1, x2)

inst_10013:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3fe and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfe00; op2val:0x8400;
op3val:0x83fe; valaddr_reg:x3; val_offset:30039*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 30039*FLEN/8, x4, x1, x2)

inst_10014:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfe00; op2val:0x8400;
op3val:0x3ff; valaddr_reg:x3; val_offset:30042*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 30042*FLEN/8, x4, x1, x2)

inst_10015:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfe00; op2val:0x8400;
op3val:0x83ff; valaddr_reg:x3; val_offset:30045*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 30045*FLEN/8, x4, x1, x2)

inst_10016:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfe00; op2val:0x8400;
op3val:0x400; valaddr_reg:x3; val_offset:30048*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 30048*FLEN/8, x4, x1, x2)

inst_10017:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfe00; op2val:0x8400;
op3val:0x8400; valaddr_reg:x3; val_offset:30051*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 30051*FLEN/8, x4, x1, x2)

inst_10018:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfe00; op2val:0x8400;
op3val:0x401; valaddr_reg:x3; val_offset:30054*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 30054*FLEN/8, x4, x1, x2)

inst_10019:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfe00; op2val:0x8400;
op3val:0x8455; valaddr_reg:x3; val_offset:30057*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 30057*FLEN/8, x4, x1, x2)

inst_10020:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfe00; op2val:0x8400;
op3val:0x7bff; valaddr_reg:x3; val_offset:30060*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 30060*FLEN/8, x4, x1, x2)

inst_10021:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfe00; op2val:0x8400;
op3val:0xfbff; valaddr_reg:x3; val_offset:30063*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 30063*FLEN/8, x4, x1, x2)

inst_10022:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfe00; op2val:0x8400;
op3val:0x7c00; valaddr_reg:x3; val_offset:30066*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 30066*FLEN/8, x4, x1, x2)

inst_10023:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfe00; op2val:0x8400;
op3val:0xfc00; valaddr_reg:x3; val_offset:30069*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 30069*FLEN/8, x4, x1, x2)

inst_10024:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfe00; op2val:0x8400;
op3val:0x7e00; valaddr_reg:x3; val_offset:30072*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 30072*FLEN/8, x4, x1, x2)

inst_10025:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfe00; op2val:0x8400;
op3val:0xfe00; valaddr_reg:x3; val_offset:30075*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 30075*FLEN/8, x4, x1, x2)

inst_10026:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x201 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfe00; op2val:0x8400;
op3val:0x7e01; valaddr_reg:x3; val_offset:30078*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 30078*FLEN/8, x4, x1, x2)

inst_10027:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x255 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfe00; op2val:0x8400;
op3val:0xfe55; valaddr_reg:x3; val_offset:30081*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 30081*FLEN/8, x4, x1, x2)

inst_10028:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfe00; op2val:0x8400;
op3val:0x7c01; valaddr_reg:x3; val_offset:30084*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 30084*FLEN/8, x4, x1, x2)

inst_10029:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x155 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfe00; op2val:0x8400;
op3val:0xfd55; valaddr_reg:x3; val_offset:30087*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 30087*FLEN/8, x4, x1, x2)

inst_10030:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfe00; op2val:0x8400;
op3val:0x3c00; valaddr_reg:x3; val_offset:30090*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 30090*FLEN/8, x4, x1, x2)

inst_10031:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfe00; op2val:0x8400;
op3val:0xbc00; valaddr_reg:x3; val_offset:30093*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 30093*FLEN/8, x4, x1, x2)

inst_10032:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfe00; op2val:0x401;
op3val:0x0; valaddr_reg:x3; val_offset:30096*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 30096*FLEN/8, x4, x1, x2)

inst_10033:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfe00; op2val:0x401;
op3val:0x8000; valaddr_reg:x3; val_offset:30099*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 30099*FLEN/8, x4, x1, x2)

inst_10034:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfe00; op2val:0x401;
op3val:0x1; valaddr_reg:x3; val_offset:30102*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 30102*FLEN/8, x4, x1, x2)

inst_10035:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfe00; op2val:0x401;
op3val:0x8001; valaddr_reg:x3; val_offset:30105*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 30105*FLEN/8, x4, x1, x2)

inst_10036:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x002 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfe00; op2val:0x401;
op3val:0x2; valaddr_reg:x3; val_offset:30108*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 30108*FLEN/8, x4, x1, x2)

inst_10037:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3fe and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfe00; op2val:0x401;
op3val:0x83fe; valaddr_reg:x3; val_offset:30111*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 30111*FLEN/8, x4, x1, x2)

inst_10038:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfe00; op2val:0x401;
op3val:0x3ff; valaddr_reg:x3; val_offset:30114*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 30114*FLEN/8, x4, x1, x2)

inst_10039:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfe00; op2val:0x401;
op3val:0x83ff; valaddr_reg:x3; val_offset:30117*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 30117*FLEN/8, x4, x1, x2)

inst_10040:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfe00; op2val:0x401;
op3val:0x400; valaddr_reg:x3; val_offset:30120*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 30120*FLEN/8, x4, x1, x2)

inst_10041:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfe00; op2val:0x401;
op3val:0x8400; valaddr_reg:x3; val_offset:30123*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 30123*FLEN/8, x4, x1, x2)

inst_10042:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfe00; op2val:0x401;
op3val:0x401; valaddr_reg:x3; val_offset:30126*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 30126*FLEN/8, x4, x1, x2)

inst_10043:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfe00; op2val:0x401;
op3val:0x8455; valaddr_reg:x3; val_offset:30129*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 30129*FLEN/8, x4, x1, x2)

inst_10044:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfe00; op2val:0x401;
op3val:0x7bff; valaddr_reg:x3; val_offset:30132*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 30132*FLEN/8, x4, x1, x2)

inst_10045:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfe00; op2val:0x401;
op3val:0xfbff; valaddr_reg:x3; val_offset:30135*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 30135*FLEN/8, x4, x1, x2)

inst_10046:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfe00; op2val:0x401;
op3val:0x7c00; valaddr_reg:x3; val_offset:30138*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 30138*FLEN/8, x4, x1, x2)

inst_10047:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfe00; op2val:0x401;
op3val:0xfc00; valaddr_reg:x3; val_offset:30141*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 30141*FLEN/8, x4, x1, x2)

inst_10048:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfe00; op2val:0x401;
op3val:0x7e00; valaddr_reg:x3; val_offset:30144*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 30144*FLEN/8, x4, x1, x2)

inst_10049:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfe00; op2val:0x401;
op3val:0xfe00; valaddr_reg:x3; val_offset:30147*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 30147*FLEN/8, x4, x1, x2)

inst_10050:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x201 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfe00; op2val:0x401;
op3val:0x7e01; valaddr_reg:x3; val_offset:30150*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 30150*FLEN/8, x4, x1, x2)

inst_10051:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x255 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfe00; op2val:0x401;
op3val:0xfe55; valaddr_reg:x3; val_offset:30153*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 30153*FLEN/8, x4, x1, x2)

inst_10052:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfe00; op2val:0x401;
op3val:0x7c01; valaddr_reg:x3; val_offset:30156*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 30156*FLEN/8, x4, x1, x2)

inst_10053:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x155 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfe00; op2val:0x401;
op3val:0xfd55; valaddr_reg:x3; val_offset:30159*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 30159*FLEN/8, x4, x1, x2)

inst_10054:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfe00; op2val:0x401;
op3val:0x3c00; valaddr_reg:x3; val_offset:30162*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 30162*FLEN/8, x4, x1, x2)

inst_10055:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfe00; op2val:0x401;
op3val:0xbc00; valaddr_reg:x3; val_offset:30165*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 30165*FLEN/8, x4, x1, x2)

inst_10056:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfe00; op2val:0x8455;
op3val:0x0; valaddr_reg:x3; val_offset:30168*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 30168*FLEN/8, x4, x1, x2)

inst_10057:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfe00; op2val:0x8455;
op3val:0x8000; valaddr_reg:x3; val_offset:30171*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 30171*FLEN/8, x4, x1, x2)

inst_10058:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfe00; op2val:0x8455;
op3val:0x1; valaddr_reg:x3; val_offset:30174*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 30174*FLEN/8, x4, x1, x2)

inst_10059:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfe00; op2val:0x8455;
op3val:0x8001; valaddr_reg:x3; val_offset:30177*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 30177*FLEN/8, x4, x1, x2)

inst_10060:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x002 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfe00; op2val:0x8455;
op3val:0x2; valaddr_reg:x3; val_offset:30180*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 30180*FLEN/8, x4, x1, x2)

inst_10061:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3fe and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfe00; op2val:0x8455;
op3val:0x83fe; valaddr_reg:x3; val_offset:30183*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 30183*FLEN/8, x4, x1, x2)

inst_10062:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfe00; op2val:0x8455;
op3val:0x3ff; valaddr_reg:x3; val_offset:30186*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 30186*FLEN/8, x4, x1, x2)

inst_10063:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfe00; op2val:0x8455;
op3val:0x83ff; valaddr_reg:x3; val_offset:30189*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 30189*FLEN/8, x4, x1, x2)

inst_10064:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfe00; op2val:0x8455;
op3val:0x400; valaddr_reg:x3; val_offset:30192*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 30192*FLEN/8, x4, x1, x2)

inst_10065:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfe00; op2val:0x8455;
op3val:0x8400; valaddr_reg:x3; val_offset:30195*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 30195*FLEN/8, x4, x1, x2)

inst_10066:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfe00; op2val:0x8455;
op3val:0x401; valaddr_reg:x3; val_offset:30198*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 30198*FLEN/8, x4, x1, x2)

inst_10067:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfe00; op2val:0x8455;
op3val:0x8455; valaddr_reg:x3; val_offset:30201*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 30201*FLEN/8, x4, x1, x2)

inst_10068:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfe00; op2val:0x8455;
op3val:0x7bff; valaddr_reg:x3; val_offset:30204*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 30204*FLEN/8, x4, x1, x2)

inst_10069:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfe00; op2val:0x8455;
op3val:0xfbff; valaddr_reg:x3; val_offset:30207*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 30207*FLEN/8, x4, x1, x2)

inst_10070:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfe00; op2val:0x8455;
op3val:0x7c00; valaddr_reg:x3; val_offset:30210*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 30210*FLEN/8, x4, x1, x2)

inst_10071:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfe00; op2val:0x8455;
op3val:0xfc00; valaddr_reg:x3; val_offset:30213*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 30213*FLEN/8, x4, x1, x2)

inst_10072:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfe00; op2val:0x8455;
op3val:0x7e00; valaddr_reg:x3; val_offset:30216*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 30216*FLEN/8, x4, x1, x2)

inst_10073:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfe00; op2val:0x8455;
op3val:0xfe00; valaddr_reg:x3; val_offset:30219*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 30219*FLEN/8, x4, x1, x2)

inst_10074:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x201 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfe00; op2val:0x8455;
op3val:0x7e01; valaddr_reg:x3; val_offset:30222*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 30222*FLEN/8, x4, x1, x2)

inst_10075:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x255 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfe00; op2val:0x8455;
op3val:0xfe55; valaddr_reg:x3; val_offset:30225*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 30225*FLEN/8, x4, x1, x2)

inst_10076:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfe00; op2val:0x8455;
op3val:0x7c01; valaddr_reg:x3; val_offset:30228*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 30228*FLEN/8, x4, x1, x2)

inst_10077:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x155 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfe00; op2val:0x8455;
op3val:0xfd55; valaddr_reg:x3; val_offset:30231*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 30231*FLEN/8, x4, x1, x2)

inst_10078:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fs3 == 0 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfe00; op2val:0x8455;
op3val:0x3c00; valaddr_reg:x3; val_offset:30234*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 30234*FLEN/8, x4, x1, x2)

inst_10079:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fs3 == 1 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfe00; op2val:0x8455;
op3val:0xbc00; valaddr_reg:x3; val_offset:30237*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 30237*FLEN/8, x4, x1, x2)

inst_10080:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfe00; op2val:0x7bff;
op3val:0x0; valaddr_reg:x3; val_offset:30240*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 30240*FLEN/8, x4, x1, x2)

inst_10081:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfe00; op2val:0x7bff;
op3val:0x8000; valaddr_reg:x3; val_offset:30243*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 30243*FLEN/8, x4, x1, x2)

inst_10082:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfe00; op2val:0x7bff;
op3val:0x1; valaddr_reg:x3; val_offset:30246*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 30246*FLEN/8, x4, x1, x2)

inst_10083:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfe00; op2val:0x7bff;
op3val:0x8001; valaddr_reg:x3; val_offset:30249*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 30249*FLEN/8, x4, x1, x2)

inst_10084:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x002 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfe00; op2val:0x7bff;
op3val:0x2; valaddr_reg:x3; val_offset:30252*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 30252*FLEN/8, x4, x1, x2)

inst_10085:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3fe and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfe00; op2val:0x7bff;
op3val:0x83fe; valaddr_reg:x3; val_offset:30255*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 30255*FLEN/8, x4, x1, x2)

inst_10086:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfe00; op2val:0x7bff;
op3val:0x3ff; valaddr_reg:x3; val_offset:30258*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 30258*FLEN/8, x4, x1, x2)

inst_10087:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfe00; op2val:0x7bff;
op3val:0x83ff; valaddr_reg:x3; val_offset:30261*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 30261*FLEN/8, x4, x1, x2)

inst_10088:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfe00; op2val:0x7bff;
op3val:0x400; valaddr_reg:x3; val_offset:30264*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 30264*FLEN/8, x4, x1, x2)

inst_10089:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfe00; op2val:0x7bff;
op3val:0x8400; valaddr_reg:x3; val_offset:30267*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 30267*FLEN/8, x4, x1, x2)

inst_10090:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x01 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfe00; op2val:0x7bff;
op3val:0x401; valaddr_reg:x3; val_offset:30270*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 30270*FLEN/8, x4, x1, x2)

inst_10091:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfe00; op2val:0x7bff;
op3val:0x8455; valaddr_reg:x3; val_offset:30273*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 30273*FLEN/8, x4, x1, x2)

inst_10092:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfe00; op2val:0x7bff;
op3val:0x7bff; valaddr_reg:x3; val_offset:30276*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 30276*FLEN/8, x4, x1, x2)

inst_10093:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfe00; op2val:0x7bff;
op3val:0xfbff; valaddr_reg:x3; val_offset:30279*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 30279*FLEN/8, x4, x1, x2)

inst_10094:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfe00; op2val:0x7bff;
op3val:0x7c00; valaddr_reg:x3; val_offset:30282*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 30282*FLEN/8, x4, x1, x2)

inst_10095:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfe00; op2val:0x7bff;
op3val:0xfc00; valaddr_reg:x3; val_offset:30285*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 30285*FLEN/8, x4, x1, x2)

inst_10096:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfe00; op2val:0x7bff;
op3val:0x7e00; valaddr_reg:x3; val_offset:30288*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 30288*FLEN/8, x4, x1, x2)

inst_10097:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfe00; op2val:0x7bff;
op3val:0xfe00; valaddr_reg:x3; val_offset:30291*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 30291*FLEN/8, x4, x1, x2)

inst_10098:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x1f and fm3 == 0x201 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfe00; op2val:0x7bff;
op3val:0x7e01; valaddr_reg:x3; val_offset:30294*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 30294*FLEN/8, x4, x1, x2)

inst_10099:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x1f and fm3 == 0x255 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfe00; op2val:0x7bff;
op3val:0xfe55; valaddr_reg:x3; val_offset:30297*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 30297*FLEN/8, x4, x1, x2)

inst_10100:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x1f and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfe00; op2val:0x7bff;
op3val:0x7c01; valaddr_reg:x3; val_offset:30300*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 30300*FLEN/8, x4, x1, x2)

inst_10101:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x1f and fm3 == 0x155 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfe00; op2val:0x7bff;
op3val:0xfd55; valaddr_reg:x3; val_offset:30303*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 30303*FLEN/8, x4, x1, x2)

inst_10102:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfe00; op2val:0x7bff;
op3val:0x3c00; valaddr_reg:x3; val_offset:30306*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 30306*FLEN/8, x4, x1, x2)

inst_10103:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfe00; op2val:0x7bff;
op3val:0xbc00; valaddr_reg:x3; val_offset:30309*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 30309*FLEN/8, x4, x1, x2)

inst_10104:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfe00; op2val:0xfbff;
op3val:0x0; valaddr_reg:x3; val_offset:30312*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 30312*FLEN/8, x4, x1, x2)

inst_10105:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfe00; op2val:0xfbff;
op3val:0x8000; valaddr_reg:x3; val_offset:30315*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 30315*FLEN/8, x4, x1, x2)

inst_10106:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfe00; op2val:0xfbff;
op3val:0x1; valaddr_reg:x3; val_offset:30318*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 30318*FLEN/8, x4, x1, x2)

inst_10107:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfe00; op2val:0xfbff;
op3val:0x8001; valaddr_reg:x3; val_offset:30321*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 30321*FLEN/8, x4, x1, x2)

inst_10108:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x002 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfe00; op2val:0xfbff;
op3val:0x2; valaddr_reg:x3; val_offset:30324*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 30324*FLEN/8, x4, x1, x2)

inst_10109:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3fe and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfe00; op2val:0xfbff;
op3val:0x83fe; valaddr_reg:x3; val_offset:30327*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 30327*FLEN/8, x4, x1, x2)

inst_10110:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfe00; op2val:0xfbff;
op3val:0x3ff; valaddr_reg:x3; val_offset:30330*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 30330*FLEN/8, x4, x1, x2)

inst_10111:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfe00; op2val:0xfbff;
op3val:0x83ff; valaddr_reg:x3; val_offset:30333*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 30333*FLEN/8, x4, x1, x2)

RVTEST_SIGBASE(x1,signature_x1_80)
inst_10112:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfe00; op2val:0xfbff;
op3val:0x400; valaddr_reg:x3; val_offset:30336*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 30336*FLEN/8, x4, x1, x2)

inst_10113:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfe00; op2val:0xfbff;
op3val:0x8400; valaddr_reg:x3; val_offset:30339*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 30339*FLEN/8, x4, x1, x2)

inst_10114:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x01 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfe00; op2val:0xfbff;
op3val:0x401; valaddr_reg:x3; val_offset:30342*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 30342*FLEN/8, x4, x1, x2)

inst_10115:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfe00; op2val:0xfbff;
op3val:0x8455; valaddr_reg:x3; val_offset:30345*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 30345*FLEN/8, x4, x1, x2)

inst_10116:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfe00; op2val:0xfbff;
op3val:0x7bff; valaddr_reg:x3; val_offset:30348*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 30348*FLEN/8, x4, x1, x2)

inst_10117:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfe00; op2val:0xfbff;
op3val:0xfbff; valaddr_reg:x3; val_offset:30351*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 30351*FLEN/8, x4, x1, x2)

inst_10118:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfe00; op2val:0xfbff;
op3val:0x7c00; valaddr_reg:x3; val_offset:30354*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 30354*FLEN/8, x4, x1, x2)

inst_10119:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfe00; op2val:0xfbff;
op3val:0xfc00; valaddr_reg:x3; val_offset:30357*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 30357*FLEN/8, x4, x1, x2)

inst_10120:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfe00; op2val:0xfbff;
op3val:0x7e00; valaddr_reg:x3; val_offset:30360*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 30360*FLEN/8, x4, x1, x2)

inst_10121:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfe00; op2val:0xfbff;
op3val:0xfe00; valaddr_reg:x3; val_offset:30363*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 30363*FLEN/8, x4, x1, x2)

inst_10122:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x1f and fm3 == 0x201 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfe00; op2val:0xfbff;
op3val:0x7e01; valaddr_reg:x3; val_offset:30366*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 30366*FLEN/8, x4, x1, x2)

inst_10123:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x1f and fm3 == 0x255 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfe00; op2val:0xfbff;
op3val:0xfe55; valaddr_reg:x3; val_offset:30369*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 30369*FLEN/8, x4, x1, x2)

inst_10124:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x1f and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfe00; op2val:0xfbff;
op3val:0x7c01; valaddr_reg:x3; val_offset:30372*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 30372*FLEN/8, x4, x1, x2)

inst_10125:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x1f and fm3 == 0x155 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfe00; op2val:0xfbff;
op3val:0xfd55; valaddr_reg:x3; val_offset:30375*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 30375*FLEN/8, x4, x1, x2)

inst_10126:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfe00; op2val:0xfbff;
op3val:0x3c00; valaddr_reg:x3; val_offset:30378*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 30378*FLEN/8, x4, x1, x2)

inst_10127:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfe00; op2val:0xfbff;
op3val:0xbc00; valaddr_reg:x3; val_offset:30381*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 30381*FLEN/8, x4, x1, x2)

inst_10128:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfe00; op2val:0x7c00;
op3val:0x0; valaddr_reg:x3; val_offset:30384*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 30384*FLEN/8, x4, x1, x2)

inst_10129:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfe00; op2val:0x7c00;
op3val:0x8000; valaddr_reg:x3; val_offset:30387*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 30387*FLEN/8, x4, x1, x2)

inst_10130:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfe00; op2val:0x7c00;
op3val:0x1; valaddr_reg:x3; val_offset:30390*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 30390*FLEN/8, x4, x1, x2)

inst_10131:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfe00; op2val:0x7c00;
op3val:0x8001; valaddr_reg:x3; val_offset:30393*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 30393*FLEN/8, x4, x1, x2)

inst_10132:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x002 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfe00; op2val:0x7c00;
op3val:0x2; valaddr_reg:x3; val_offset:30396*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 30396*FLEN/8, x4, x1, x2)

inst_10133:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3fe and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfe00; op2val:0x7c00;
op3val:0x83fe; valaddr_reg:x3; val_offset:30399*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 30399*FLEN/8, x4, x1, x2)

inst_10134:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfe00; op2val:0x7c00;
op3val:0x3ff; valaddr_reg:x3; val_offset:30402*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 30402*FLEN/8, x4, x1, x2)

inst_10135:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfe00; op2val:0x7c00;
op3val:0x83ff; valaddr_reg:x3; val_offset:30405*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 30405*FLEN/8, x4, x1, x2)

inst_10136:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfe00; op2val:0x7c00;
op3val:0x400; valaddr_reg:x3; val_offset:30408*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 30408*FLEN/8, x4, x1, x2)

inst_10137:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfe00; op2val:0x7c00;
op3val:0x8400; valaddr_reg:x3; val_offset:30411*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 30411*FLEN/8, x4, x1, x2)

inst_10138:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfe00; op2val:0x7c00;
op3val:0x401; valaddr_reg:x3; val_offset:30414*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 30414*FLEN/8, x4, x1, x2)

inst_10139:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfe00; op2val:0x7c00;
op3val:0x8455; valaddr_reg:x3; val_offset:30417*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 30417*FLEN/8, x4, x1, x2)

inst_10140:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfe00; op2val:0x7c00;
op3val:0x7bff; valaddr_reg:x3; val_offset:30420*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 30420*FLEN/8, x4, x1, x2)

inst_10141:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfe00; op2val:0x7c00;
op3val:0xfbff; valaddr_reg:x3; val_offset:30423*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 30423*FLEN/8, x4, x1, x2)

inst_10142:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfe00; op2val:0x7c00;
op3val:0x7c00; valaddr_reg:x3; val_offset:30426*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 30426*FLEN/8, x4, x1, x2)

inst_10143:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfe00; op2val:0x7c00;
op3val:0xfc00; valaddr_reg:x3; val_offset:30429*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 30429*FLEN/8, x4, x1, x2)

inst_10144:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfe00; op2val:0x7c00;
op3val:0x7e00; valaddr_reg:x3; val_offset:30432*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 30432*FLEN/8, x4, x1, x2)

inst_10145:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfe00; op2val:0x7c00;
op3val:0xfe00; valaddr_reg:x3; val_offset:30435*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 30435*FLEN/8, x4, x1, x2)

inst_10146:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x201 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfe00; op2val:0x7c00;
op3val:0x7e01; valaddr_reg:x3; val_offset:30438*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 30438*FLEN/8, x4, x1, x2)

inst_10147:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x255 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfe00; op2val:0x7c00;
op3val:0xfe55; valaddr_reg:x3; val_offset:30441*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 30441*FLEN/8, x4, x1, x2)

inst_10148:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfe00; op2val:0x7c00;
op3val:0x7c01; valaddr_reg:x3; val_offset:30444*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 30444*FLEN/8, x4, x1, x2)

inst_10149:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x155 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfe00; op2val:0x7c00;
op3val:0xfd55; valaddr_reg:x3; val_offset:30447*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 30447*FLEN/8, x4, x1, x2)

inst_10150:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfe00; op2val:0x7c00;
op3val:0x3c00; valaddr_reg:x3; val_offset:30450*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 30450*FLEN/8, x4, x1, x2)

inst_10151:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfe00; op2val:0x7c00;
op3val:0xbc00; valaddr_reg:x3; val_offset:30453*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 30453*FLEN/8, x4, x1, x2)

inst_10152:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfe00; op2val:0xfc00;
op3val:0x0; valaddr_reg:x3; val_offset:30456*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 30456*FLEN/8, x4, x1, x2)

inst_10153:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfe00; op2val:0xfc00;
op3val:0x8000; valaddr_reg:x3; val_offset:30459*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 30459*FLEN/8, x4, x1, x2)

inst_10154:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfe00; op2val:0xfc00;
op3val:0x1; valaddr_reg:x3; val_offset:30462*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 30462*FLEN/8, x4, x1, x2)

inst_10155:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfe00; op2val:0xfc00;
op3val:0x8001; valaddr_reg:x3; val_offset:30465*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 30465*FLEN/8, x4, x1, x2)

inst_10156:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x002 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfe00; op2val:0xfc00;
op3val:0x2; valaddr_reg:x3; val_offset:30468*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 30468*FLEN/8, x4, x1, x2)

inst_10157:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3fe and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfe00; op2val:0xfc00;
op3val:0x83fe; valaddr_reg:x3; val_offset:30471*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 30471*FLEN/8, x4, x1, x2)

inst_10158:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfe00; op2val:0xfc00;
op3val:0x3ff; valaddr_reg:x3; val_offset:30474*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 30474*FLEN/8, x4, x1, x2)

inst_10159:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfe00; op2val:0xfc00;
op3val:0x83ff; valaddr_reg:x3; val_offset:30477*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 30477*FLEN/8, x4, x1, x2)

inst_10160:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfe00; op2val:0xfc00;
op3val:0x400; valaddr_reg:x3; val_offset:30480*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 30480*FLEN/8, x4, x1, x2)

inst_10161:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfe00; op2val:0xfc00;
op3val:0x8400; valaddr_reg:x3; val_offset:30483*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 30483*FLEN/8, x4, x1, x2)

inst_10162:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfe00; op2val:0xfc00;
op3val:0x401; valaddr_reg:x3; val_offset:30486*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 30486*FLEN/8, x4, x1, x2)

inst_10163:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfe00; op2val:0xfc00;
op3val:0x8455; valaddr_reg:x3; val_offset:30489*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 30489*FLEN/8, x4, x1, x2)

inst_10164:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfe00; op2val:0xfc00;
op3val:0x7bff; valaddr_reg:x3; val_offset:30492*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 30492*FLEN/8, x4, x1, x2)

inst_10165:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfe00; op2val:0xfc00;
op3val:0xfbff; valaddr_reg:x3; val_offset:30495*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 30495*FLEN/8, x4, x1, x2)

inst_10166:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfe00; op2val:0xfc00;
op3val:0x7c00; valaddr_reg:x3; val_offset:30498*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 30498*FLEN/8, x4, x1, x2)

inst_10167:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfe00; op2val:0xfc00;
op3val:0xfc00; valaddr_reg:x3; val_offset:30501*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 30501*FLEN/8, x4, x1, x2)

inst_10168:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfe00; op2val:0xfc00;
op3val:0x7e00; valaddr_reg:x3; val_offset:30504*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 30504*FLEN/8, x4, x1, x2)

inst_10169:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfe00; op2val:0xfc00;
op3val:0xfe00; valaddr_reg:x3; val_offset:30507*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 30507*FLEN/8, x4, x1, x2)

inst_10170:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x201 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfe00; op2val:0xfc00;
op3val:0x7e01; valaddr_reg:x3; val_offset:30510*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 30510*FLEN/8, x4, x1, x2)

inst_10171:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x255 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfe00; op2val:0xfc00;
op3val:0xfe55; valaddr_reg:x3; val_offset:30513*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 30513*FLEN/8, x4, x1, x2)

inst_10172:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfe00; op2val:0xfc00;
op3val:0x7c01; valaddr_reg:x3; val_offset:30516*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 30516*FLEN/8, x4, x1, x2)

inst_10173:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x155 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfe00; op2val:0xfc00;
op3val:0xfd55; valaddr_reg:x3; val_offset:30519*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 30519*FLEN/8, x4, x1, x2)

inst_10174:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfe00; op2val:0xfc00;
op3val:0x3c00; valaddr_reg:x3; val_offset:30522*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 30522*FLEN/8, x4, x1, x2)

inst_10175:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfe00; op2val:0xfc00;
op3val:0xbc00; valaddr_reg:x3; val_offset:30525*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 30525*FLEN/8, x4, x1, x2)

inst_10176:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfe00; op2val:0x7e00;
op3val:0x0; valaddr_reg:x3; val_offset:30528*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 30528*FLEN/8, x4, x1, x2)

inst_10177:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfe00; op2val:0x7e00;
op3val:0x8000; valaddr_reg:x3; val_offset:30531*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 30531*FLEN/8, x4, x1, x2)

inst_10178:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfe00; op2val:0x7e00;
op3val:0x1; valaddr_reg:x3; val_offset:30534*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 30534*FLEN/8, x4, x1, x2)

inst_10179:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfe00; op2val:0x7e00;
op3val:0x8001; valaddr_reg:x3; val_offset:30537*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 30537*FLEN/8, x4, x1, x2)

inst_10180:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x002 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfe00; op2val:0x7e00;
op3val:0x2; valaddr_reg:x3; val_offset:30540*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 30540*FLEN/8, x4, x1, x2)

inst_10181:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3fe and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfe00; op2val:0x7e00;
op3val:0x83fe; valaddr_reg:x3; val_offset:30543*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 30543*FLEN/8, x4, x1, x2)

inst_10182:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfe00; op2val:0x7e00;
op3val:0x3ff; valaddr_reg:x3; val_offset:30546*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 30546*FLEN/8, x4, x1, x2)

inst_10183:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfe00; op2val:0x7e00;
op3val:0x83ff; valaddr_reg:x3; val_offset:30549*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 30549*FLEN/8, x4, x1, x2)

inst_10184:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfe00; op2val:0x7e00;
op3val:0x400; valaddr_reg:x3; val_offset:30552*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 30552*FLEN/8, x4, x1, x2)

inst_10185:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfe00; op2val:0x7e00;
op3val:0x8400; valaddr_reg:x3; val_offset:30555*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 30555*FLEN/8, x4, x1, x2)

inst_10186:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfe00; op2val:0x7e00;
op3val:0x401; valaddr_reg:x3; val_offset:30558*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 30558*FLEN/8, x4, x1, x2)

inst_10187:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfe00; op2val:0x7e00;
op3val:0x8455; valaddr_reg:x3; val_offset:30561*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 30561*FLEN/8, x4, x1, x2)

inst_10188:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfe00; op2val:0x7e00;
op3val:0x7bff; valaddr_reg:x3; val_offset:30564*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 30564*FLEN/8, x4, x1, x2)

inst_10189:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfe00; op2val:0x7e00;
op3val:0xfbff; valaddr_reg:x3; val_offset:30567*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 30567*FLEN/8, x4, x1, x2)

inst_10190:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfe00; op2val:0x7e00;
op3val:0x7c00; valaddr_reg:x3; val_offset:30570*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 30570*FLEN/8, x4, x1, x2)

inst_10191:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfe00; op2val:0x7e00;
op3val:0xfc00; valaddr_reg:x3; val_offset:30573*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 30573*FLEN/8, x4, x1, x2)

inst_10192:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfe00; op2val:0x7e00;
op3val:0x7e00; valaddr_reg:x3; val_offset:30576*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 30576*FLEN/8, x4, x1, x2)

inst_10193:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfe00; op2val:0x7e00;
op3val:0xfe00; valaddr_reg:x3; val_offset:30579*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 30579*FLEN/8, x4, x1, x2)

inst_10194:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x201 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfe00; op2val:0x7e00;
op3val:0x7e01; valaddr_reg:x3; val_offset:30582*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 30582*FLEN/8, x4, x1, x2)

inst_10195:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x255 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfe00; op2val:0x7e00;
op3val:0xfe55; valaddr_reg:x3; val_offset:30585*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 30585*FLEN/8, x4, x1, x2)

inst_10196:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfe00; op2val:0x7e00;
op3val:0x7c01; valaddr_reg:x3; val_offset:30588*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 30588*FLEN/8, x4, x1, x2)

inst_10197:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x155 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfe00; op2val:0x7e00;
op3val:0xfd55; valaddr_reg:x3; val_offset:30591*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 30591*FLEN/8, x4, x1, x2)

inst_10198:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 0 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfe00; op2val:0x7e00;
op3val:0x3c00; valaddr_reg:x3; val_offset:30594*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 30594*FLEN/8, x4, x1, x2)

inst_10199:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 1 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfe00; op2val:0x7e00;
op3val:0xbc00; valaddr_reg:x3; val_offset:30597*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 30597*FLEN/8, x4, x1, x2)

inst_10200:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfe00; op2val:0xfe00;
op3val:0x0; valaddr_reg:x3; val_offset:30600*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 30600*FLEN/8, x4, x1, x2)

inst_10201:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfe00; op2val:0xfe00;
op3val:0x8000; valaddr_reg:x3; val_offset:30603*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 30603*FLEN/8, x4, x1, x2)

inst_10202:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfe00; op2val:0xfe00;
op3val:0x1; valaddr_reg:x3; val_offset:30606*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 30606*FLEN/8, x4, x1, x2)

inst_10203:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfe00; op2val:0xfe00;
op3val:0x8001; valaddr_reg:x3; val_offset:30609*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 30609*FLEN/8, x4, x1, x2)

inst_10204:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x002 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfe00; op2val:0xfe00;
op3val:0x2; valaddr_reg:x3; val_offset:30612*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 30612*FLEN/8, x4, x1, x2)

inst_10205:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3fe and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfe00; op2val:0xfe00;
op3val:0x83fe; valaddr_reg:x3; val_offset:30615*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 30615*FLEN/8, x4, x1, x2)

inst_10206:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfe00; op2val:0xfe00;
op3val:0x3ff; valaddr_reg:x3; val_offset:30618*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 30618*FLEN/8, x4, x1, x2)

inst_10207:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfe00; op2val:0xfe00;
op3val:0x83ff; valaddr_reg:x3; val_offset:30621*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 30621*FLEN/8, x4, x1, x2)

inst_10208:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfe00; op2val:0xfe00;
op3val:0x400; valaddr_reg:x3; val_offset:30624*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 30624*FLEN/8, x4, x1, x2)

inst_10209:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfe00; op2val:0xfe00;
op3val:0x8400; valaddr_reg:x3; val_offset:30627*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 30627*FLEN/8, x4, x1, x2)

inst_10210:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfe00; op2val:0xfe00;
op3val:0x401; valaddr_reg:x3; val_offset:30630*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 30630*FLEN/8, x4, x1, x2)

inst_10211:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfe00; op2val:0xfe00;
op3val:0x8455; valaddr_reg:x3; val_offset:30633*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 30633*FLEN/8, x4, x1, x2)

inst_10212:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfe00; op2val:0xfe00;
op3val:0x7bff; valaddr_reg:x3; val_offset:30636*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 30636*FLEN/8, x4, x1, x2)

inst_10213:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfe00; op2val:0xfe00;
op3val:0xfbff; valaddr_reg:x3; val_offset:30639*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 30639*FLEN/8, x4, x1, x2)

inst_10214:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfe00; op2val:0xfe00;
op3val:0x7c00; valaddr_reg:x3; val_offset:30642*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 30642*FLEN/8, x4, x1, x2)

inst_10215:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfe00; op2val:0xfe00;
op3val:0xfc00; valaddr_reg:x3; val_offset:30645*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 30645*FLEN/8, x4, x1, x2)

inst_10216:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfe00; op2val:0xfe00;
op3val:0x7e00; valaddr_reg:x3; val_offset:30648*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 30648*FLEN/8, x4, x1, x2)

inst_10217:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfe00; op2val:0xfe00;
op3val:0xfe00; valaddr_reg:x3; val_offset:30651*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 30651*FLEN/8, x4, x1, x2)

inst_10218:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x201 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfe00; op2val:0xfe00;
op3val:0x7e01; valaddr_reg:x3; val_offset:30654*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 30654*FLEN/8, x4, x1, x2)

inst_10219:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x255 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfe00; op2val:0xfe00;
op3val:0xfe55; valaddr_reg:x3; val_offset:30657*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 30657*FLEN/8, x4, x1, x2)

inst_10220:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfe00; op2val:0xfe00;
op3val:0x7c01; valaddr_reg:x3; val_offset:30660*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 30660*FLEN/8, x4, x1, x2)

inst_10221:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x155 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfe00; op2val:0xfe00;
op3val:0xfd55; valaddr_reg:x3; val_offset:30663*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 30663*FLEN/8, x4, x1, x2)

inst_10222:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 0 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfe00; op2val:0xfe00;
op3val:0x3c00; valaddr_reg:x3; val_offset:30666*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 30666*FLEN/8, x4, x1, x2)

inst_10223:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 1 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfe00; op2val:0xfe00;
op3val:0xbc00; valaddr_reg:x3; val_offset:30669*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 30669*FLEN/8, x4, x1, x2)

inst_10224:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfe00; op2val:0x7e01;
op3val:0x0; valaddr_reg:x3; val_offset:30672*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 30672*FLEN/8, x4, x1, x2)

inst_10225:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfe00; op2val:0x7e01;
op3val:0x8000; valaddr_reg:x3; val_offset:30675*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 30675*FLEN/8, x4, x1, x2)

inst_10226:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfe00; op2val:0x7e01;
op3val:0x1; valaddr_reg:x3; val_offset:30678*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 30678*FLEN/8, x4, x1, x2)

inst_10227:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfe00; op2val:0x7e01;
op3val:0x8001; valaddr_reg:x3; val_offset:30681*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 30681*FLEN/8, x4, x1, x2)

inst_10228:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x002 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfe00; op2val:0x7e01;
op3val:0x2; valaddr_reg:x3; val_offset:30684*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 30684*FLEN/8, x4, x1, x2)

inst_10229:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3fe and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfe00; op2val:0x7e01;
op3val:0x83fe; valaddr_reg:x3; val_offset:30687*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 30687*FLEN/8, x4, x1, x2)

inst_10230:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfe00; op2val:0x7e01;
op3val:0x3ff; valaddr_reg:x3; val_offset:30690*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 30690*FLEN/8, x4, x1, x2)

inst_10231:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfe00; op2val:0x7e01;
op3val:0x83ff; valaddr_reg:x3; val_offset:30693*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 30693*FLEN/8, x4, x1, x2)

inst_10232:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfe00; op2val:0x7e01;
op3val:0x400; valaddr_reg:x3; val_offset:30696*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 30696*FLEN/8, x4, x1, x2)

inst_10233:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfe00; op2val:0x7e01;
op3val:0x8400; valaddr_reg:x3; val_offset:30699*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 30699*FLEN/8, x4, x1, x2)

inst_10234:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfe00; op2val:0x7e01;
op3val:0x401; valaddr_reg:x3; val_offset:30702*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 30702*FLEN/8, x4, x1, x2)

inst_10235:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfe00; op2val:0x7e01;
op3val:0x8455; valaddr_reg:x3; val_offset:30705*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 30705*FLEN/8, x4, x1, x2)

inst_10236:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfe00; op2val:0x7e01;
op3val:0x7bff; valaddr_reg:x3; val_offset:30708*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 30708*FLEN/8, x4, x1, x2)

inst_10237:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfe00; op2val:0x7e01;
op3val:0xfbff; valaddr_reg:x3; val_offset:30711*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 30711*FLEN/8, x4, x1, x2)

inst_10238:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfe00; op2val:0x7e01;
op3val:0x7c00; valaddr_reg:x3; val_offset:30714*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 30714*FLEN/8, x4, x1, x2)

inst_10239:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfe00; op2val:0x7e01;
op3val:0xfc00; valaddr_reg:x3; val_offset:30717*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 30717*FLEN/8, x4, x1, x2)

RVTEST_SIGBASE(x1,signature_x1_81)
inst_10240:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfe00; op2val:0x7e01;
op3val:0x7e00; valaddr_reg:x3; val_offset:30720*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 30720*FLEN/8, x4, x1, x2)

inst_10241:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfe00; op2val:0x7e01;
op3val:0xfe00; valaddr_reg:x3; val_offset:30723*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 30723*FLEN/8, x4, x1, x2)

inst_10242:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x201 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfe00; op2val:0x7e01;
op3val:0x7e01; valaddr_reg:x3; val_offset:30726*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 30726*FLEN/8, x4, x1, x2)

inst_10243:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x255 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfe00; op2val:0x7e01;
op3val:0xfe55; valaddr_reg:x3; val_offset:30729*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 30729*FLEN/8, x4, x1, x2)

inst_10244:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfe00; op2val:0x7e01;
op3val:0x7c01; valaddr_reg:x3; val_offset:30732*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 30732*FLEN/8, x4, x1, x2)

inst_10245:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x155 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfe00; op2val:0x7e01;
op3val:0xfd55; valaddr_reg:x3; val_offset:30735*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 30735*FLEN/8, x4, x1, x2)

inst_10246:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fs3 == 0 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfe00; op2val:0x7e01;
op3val:0x3c00; valaddr_reg:x3; val_offset:30738*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 30738*FLEN/8, x4, x1, x2)

inst_10247:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fs3 == 1 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfe00; op2val:0x7e01;
op3val:0xbc00; valaddr_reg:x3; val_offset:30741*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 30741*FLEN/8, x4, x1, x2)

inst_10248:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfe00; op2val:0xfe55;
op3val:0x0; valaddr_reg:x3; val_offset:30744*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 30744*FLEN/8, x4, x1, x2)

inst_10249:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfe00; op2val:0xfe55;
op3val:0x8000; valaddr_reg:x3; val_offset:30747*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 30747*FLEN/8, x4, x1, x2)

inst_10250:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfe00; op2val:0xfe55;
op3val:0x1; valaddr_reg:x3; val_offset:30750*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 30750*FLEN/8, x4, x1, x2)

inst_10251:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfe00; op2val:0xfe55;
op3val:0x8001; valaddr_reg:x3; val_offset:30753*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 30753*FLEN/8, x4, x1, x2)

inst_10252:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x002 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfe00; op2val:0xfe55;
op3val:0x2; valaddr_reg:x3; val_offset:30756*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 30756*FLEN/8, x4, x1, x2)

inst_10253:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3fe and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfe00; op2val:0xfe55;
op3val:0x83fe; valaddr_reg:x3; val_offset:30759*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 30759*FLEN/8, x4, x1, x2)

inst_10254:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfe00; op2val:0xfe55;
op3val:0x3ff; valaddr_reg:x3; val_offset:30762*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 30762*FLEN/8, x4, x1, x2)

inst_10255:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfe00; op2val:0xfe55;
op3val:0x83ff; valaddr_reg:x3; val_offset:30765*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 30765*FLEN/8, x4, x1, x2)

inst_10256:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfe00; op2val:0xfe55;
op3val:0x400; valaddr_reg:x3; val_offset:30768*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 30768*FLEN/8, x4, x1, x2)

inst_10257:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfe00; op2val:0xfe55;
op3val:0x8400; valaddr_reg:x3; val_offset:30771*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 30771*FLEN/8, x4, x1, x2)

inst_10258:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfe00; op2val:0xfe55;
op3val:0x401; valaddr_reg:x3; val_offset:30774*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 30774*FLEN/8, x4, x1, x2)

inst_10259:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfe00; op2val:0xfe55;
op3val:0x8455; valaddr_reg:x3; val_offset:30777*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 30777*FLEN/8, x4, x1, x2)

inst_10260:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfe00; op2val:0xfe55;
op3val:0x7bff; valaddr_reg:x3; val_offset:30780*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 30780*FLEN/8, x4, x1, x2)

inst_10261:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfe00; op2val:0xfe55;
op3val:0xfbff; valaddr_reg:x3; val_offset:30783*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 30783*FLEN/8, x4, x1, x2)

inst_10262:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfe00; op2val:0xfe55;
op3val:0x7c00; valaddr_reg:x3; val_offset:30786*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 30786*FLEN/8, x4, x1, x2)

inst_10263:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfe00; op2val:0xfe55;
op3val:0xfc00; valaddr_reg:x3; val_offset:30789*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 30789*FLEN/8, x4, x1, x2)

inst_10264:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfe00; op2val:0xfe55;
op3val:0x7e00; valaddr_reg:x3; val_offset:30792*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 30792*FLEN/8, x4, x1, x2)

inst_10265:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfe00; op2val:0xfe55;
op3val:0xfe00; valaddr_reg:x3; val_offset:30795*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 30795*FLEN/8, x4, x1, x2)

inst_10266:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x201 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfe00; op2val:0xfe55;
op3val:0x7e01; valaddr_reg:x3; val_offset:30798*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 30798*FLEN/8, x4, x1, x2)

inst_10267:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x255 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfe00; op2val:0xfe55;
op3val:0xfe55; valaddr_reg:x3; val_offset:30801*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 30801*FLEN/8, x4, x1, x2)

inst_10268:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfe00; op2val:0xfe55;
op3val:0x7c01; valaddr_reg:x3; val_offset:30804*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 30804*FLEN/8, x4, x1, x2)

inst_10269:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x155 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfe00; op2val:0xfe55;
op3val:0xfd55; valaddr_reg:x3; val_offset:30807*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 30807*FLEN/8, x4, x1, x2)

inst_10270:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fs3 == 0 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfe00; op2val:0xfe55;
op3val:0x3c00; valaddr_reg:x3; val_offset:30810*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 30810*FLEN/8, x4, x1, x2)

inst_10271:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fs3 == 1 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfe00; op2val:0xfe55;
op3val:0xbc00; valaddr_reg:x3; val_offset:30813*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 30813*FLEN/8, x4, x1, x2)

inst_10272:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfe00; op2val:0x7c01;
op3val:0x0; valaddr_reg:x3; val_offset:30816*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 30816*FLEN/8, x4, x1, x2)

inst_10273:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfe00; op2val:0x7c01;
op3val:0x8000; valaddr_reg:x3; val_offset:30819*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 30819*FLEN/8, x4, x1, x2)

inst_10274:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfe00; op2val:0x7c01;
op3val:0x1; valaddr_reg:x3; val_offset:30822*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 30822*FLEN/8, x4, x1, x2)

inst_10275:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfe00; op2val:0x7c01;
op3val:0x8001; valaddr_reg:x3; val_offset:30825*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 30825*FLEN/8, x4, x1, x2)

inst_10276:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x002 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfe00; op2val:0x7c01;
op3val:0x2; valaddr_reg:x3; val_offset:30828*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 30828*FLEN/8, x4, x1, x2)

inst_10277:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3fe and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfe00; op2val:0x7c01;
op3val:0x83fe; valaddr_reg:x3; val_offset:30831*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 30831*FLEN/8, x4, x1, x2)

inst_10278:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfe00; op2val:0x7c01;
op3val:0x3ff; valaddr_reg:x3; val_offset:30834*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 30834*FLEN/8, x4, x1, x2)

inst_10279:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfe00; op2val:0x7c01;
op3val:0x83ff; valaddr_reg:x3; val_offset:30837*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 30837*FLEN/8, x4, x1, x2)

inst_10280:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfe00; op2val:0x7c01;
op3val:0x400; valaddr_reg:x3; val_offset:30840*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 30840*FLEN/8, x4, x1, x2)

inst_10281:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfe00; op2val:0x7c01;
op3val:0x8400; valaddr_reg:x3; val_offset:30843*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 30843*FLEN/8, x4, x1, x2)

inst_10282:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfe00; op2val:0x7c01;
op3val:0x401; valaddr_reg:x3; val_offset:30846*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 30846*FLEN/8, x4, x1, x2)

inst_10283:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfe00; op2val:0x7c01;
op3val:0x8455; valaddr_reg:x3; val_offset:30849*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 30849*FLEN/8, x4, x1, x2)

inst_10284:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfe00; op2val:0x7c01;
op3val:0x7bff; valaddr_reg:x3; val_offset:30852*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 30852*FLEN/8, x4, x1, x2)

inst_10285:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfe00; op2val:0x7c01;
op3val:0xfbff; valaddr_reg:x3; val_offset:30855*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 30855*FLEN/8, x4, x1, x2)

inst_10286:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfe00; op2val:0x7c01;
op3val:0x7c00; valaddr_reg:x3; val_offset:30858*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 30858*FLEN/8, x4, x1, x2)

inst_10287:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfe00; op2val:0x7c01;
op3val:0xfc00; valaddr_reg:x3; val_offset:30861*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 30861*FLEN/8, x4, x1, x2)

inst_10288:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfe00; op2val:0x7c01;
op3val:0x7e00; valaddr_reg:x3; val_offset:30864*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 30864*FLEN/8, x4, x1, x2)

inst_10289:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfe00; op2val:0x7c01;
op3val:0xfe00; valaddr_reg:x3; val_offset:30867*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 30867*FLEN/8, x4, x1, x2)

inst_10290:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x201 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfe00; op2val:0x7c01;
op3val:0x7e01; valaddr_reg:x3; val_offset:30870*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 30870*FLEN/8, x4, x1, x2)

inst_10291:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x255 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfe00; op2val:0x7c01;
op3val:0xfe55; valaddr_reg:x3; val_offset:30873*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 30873*FLEN/8, x4, x1, x2)

inst_10292:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfe00; op2val:0x7c01;
op3val:0x7c01; valaddr_reg:x3; val_offset:30876*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 30876*FLEN/8, x4, x1, x2)

inst_10293:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x155 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfe00; op2val:0x7c01;
op3val:0xfd55; valaddr_reg:x3; val_offset:30879*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 30879*FLEN/8, x4, x1, x2)

inst_10294:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fs3 == 0 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfe00; op2val:0x7c01;
op3val:0x3c00; valaddr_reg:x3; val_offset:30882*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 30882*FLEN/8, x4, x1, x2)

inst_10295:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fs3 == 1 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfe00; op2val:0x7c01;
op3val:0xbc00; valaddr_reg:x3; val_offset:30885*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 30885*FLEN/8, x4, x1, x2)

inst_10296:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfe00; op2val:0xfd55;
op3val:0x0; valaddr_reg:x3; val_offset:30888*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 30888*FLEN/8, x4, x1, x2)

inst_10297:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfe00; op2val:0xfd55;
op3val:0x8000; valaddr_reg:x3; val_offset:30891*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 30891*FLEN/8, x4, x1, x2)

inst_10298:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfe00; op2val:0xfd55;
op3val:0x1; valaddr_reg:x3; val_offset:30894*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 30894*FLEN/8, x4, x1, x2)

inst_10299:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfe00; op2val:0xfd55;
op3val:0x8001; valaddr_reg:x3; val_offset:30897*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 30897*FLEN/8, x4, x1, x2)

inst_10300:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x002 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfe00; op2val:0xfd55;
op3val:0x2; valaddr_reg:x3; val_offset:30900*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 30900*FLEN/8, x4, x1, x2)

inst_10301:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3fe and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfe00; op2val:0xfd55;
op3val:0x83fe; valaddr_reg:x3; val_offset:30903*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 30903*FLEN/8, x4, x1, x2)

inst_10302:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfe00; op2val:0xfd55;
op3val:0x3ff; valaddr_reg:x3; val_offset:30906*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 30906*FLEN/8, x4, x1, x2)

inst_10303:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfe00; op2val:0xfd55;
op3val:0x83ff; valaddr_reg:x3; val_offset:30909*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 30909*FLEN/8, x4, x1, x2)

inst_10304:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfe00; op2val:0xfd55;
op3val:0x400; valaddr_reg:x3; val_offset:30912*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 30912*FLEN/8, x4, x1, x2)

inst_10305:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfe00; op2val:0xfd55;
op3val:0x8400; valaddr_reg:x3; val_offset:30915*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 30915*FLEN/8, x4, x1, x2)

inst_10306:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfe00; op2val:0xfd55;
op3val:0x401; valaddr_reg:x3; val_offset:30918*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 30918*FLEN/8, x4, x1, x2)

inst_10307:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfe00; op2val:0xfd55;
op3val:0x8455; valaddr_reg:x3; val_offset:30921*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 30921*FLEN/8, x4, x1, x2)

inst_10308:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfe00; op2val:0xfd55;
op3val:0x7bff; valaddr_reg:x3; val_offset:30924*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 30924*FLEN/8, x4, x1, x2)

inst_10309:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfe00; op2val:0xfd55;
op3val:0xfbff; valaddr_reg:x3; val_offset:30927*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 30927*FLEN/8, x4, x1, x2)

inst_10310:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfe00; op2val:0xfd55;
op3val:0x7c00; valaddr_reg:x3; val_offset:30930*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 30930*FLEN/8, x4, x1, x2)

inst_10311:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfe00; op2val:0xfd55;
op3val:0xfc00; valaddr_reg:x3; val_offset:30933*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 30933*FLEN/8, x4, x1, x2)

inst_10312:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfe00; op2val:0xfd55;
op3val:0x7e00; valaddr_reg:x3; val_offset:30936*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 30936*FLEN/8, x4, x1, x2)

inst_10313:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfe00; op2val:0xfd55;
op3val:0xfe00; valaddr_reg:x3; val_offset:30939*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 30939*FLEN/8, x4, x1, x2)

inst_10314:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x201 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfe00; op2val:0xfd55;
op3val:0x7e01; valaddr_reg:x3; val_offset:30942*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 30942*FLEN/8, x4, x1, x2)

inst_10315:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x255 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfe00; op2val:0xfd55;
op3val:0xfe55; valaddr_reg:x3; val_offset:30945*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 30945*FLEN/8, x4, x1, x2)

inst_10316:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfe00; op2val:0xfd55;
op3val:0x7c01; valaddr_reg:x3; val_offset:30948*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 30948*FLEN/8, x4, x1, x2)

inst_10317:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x155 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfe00; op2val:0xfd55;
op3val:0xfd55; valaddr_reg:x3; val_offset:30951*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 30951*FLEN/8, x4, x1, x2)

inst_10318:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fs3 == 0 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfe00; op2val:0xfd55;
op3val:0x3c00; valaddr_reg:x3; val_offset:30954*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 30954*FLEN/8, x4, x1, x2)

inst_10319:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fs3 == 1 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfe00; op2val:0xfd55;
op3val:0xbc00; valaddr_reg:x3; val_offset:30957*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 30957*FLEN/8, x4, x1, x2)

inst_10320:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfe00; op2val:0x3c00;
op3val:0x0; valaddr_reg:x3; val_offset:30960*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 30960*FLEN/8, x4, x1, x2)

inst_10321:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfe00; op2val:0x3c00;
op3val:0x8000; valaddr_reg:x3; val_offset:30963*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 30963*FLEN/8, x4, x1, x2)

inst_10322:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfe00; op2val:0x3c00;
op3val:0x1; valaddr_reg:x3; val_offset:30966*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 30966*FLEN/8, x4, x1, x2)

inst_10323:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfe00; op2val:0x3c00;
op3val:0x8001; valaddr_reg:x3; val_offset:30969*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 30969*FLEN/8, x4, x1, x2)

inst_10324:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x002 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfe00; op2val:0x3c00;
op3val:0x2; valaddr_reg:x3; val_offset:30972*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 30972*FLEN/8, x4, x1, x2)

inst_10325:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3fe and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfe00; op2val:0x3c00;
op3val:0x83fe; valaddr_reg:x3; val_offset:30975*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 30975*FLEN/8, x4, x1, x2)

inst_10326:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfe00; op2val:0x3c00;
op3val:0x3ff; valaddr_reg:x3; val_offset:30978*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 30978*FLEN/8, x4, x1, x2)

inst_10327:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfe00; op2val:0x3c00;
op3val:0x83ff; valaddr_reg:x3; val_offset:30981*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 30981*FLEN/8, x4, x1, x2)

inst_10328:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfe00; op2val:0x3c00;
op3val:0x400; valaddr_reg:x3; val_offset:30984*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 30984*FLEN/8, x4, x1, x2)

inst_10329:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfe00; op2val:0x3c00;
op3val:0x8400; valaddr_reg:x3; val_offset:30987*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 30987*FLEN/8, x4, x1, x2)

inst_10330:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfe00; op2val:0x3c00;
op3val:0x401; valaddr_reg:x3; val_offset:30990*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 30990*FLEN/8, x4, x1, x2)

inst_10331:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfe00; op2val:0x3c00;
op3val:0x8455; valaddr_reg:x3; val_offset:30993*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 30993*FLEN/8, x4, x1, x2)

inst_10332:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfe00; op2val:0x3c00;
op3val:0x7bff; valaddr_reg:x3; val_offset:30996*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 30996*FLEN/8, x4, x1, x2)

inst_10333:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfe00; op2val:0x3c00;
op3val:0xfbff; valaddr_reg:x3; val_offset:30999*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 30999*FLEN/8, x4, x1, x2)

inst_10334:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfe00; op2val:0x3c00;
op3val:0x7c00; valaddr_reg:x3; val_offset:31002*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 31002*FLEN/8, x4, x1, x2)

inst_10335:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfe00; op2val:0x3c00;
op3val:0xfc00; valaddr_reg:x3; val_offset:31005*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 31005*FLEN/8, x4, x1, x2)

inst_10336:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfe00; op2val:0x3c00;
op3val:0x7e00; valaddr_reg:x3; val_offset:31008*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 31008*FLEN/8, x4, x1, x2)

inst_10337:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfe00; op2val:0x3c00;
op3val:0xfe00; valaddr_reg:x3; val_offset:31011*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 31011*FLEN/8, x4, x1, x2)

inst_10338:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x201 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfe00; op2val:0x3c00;
op3val:0x7e01; valaddr_reg:x3; val_offset:31014*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 31014*FLEN/8, x4, x1, x2)

inst_10339:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x255 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfe00; op2val:0x3c00;
op3val:0xfe55; valaddr_reg:x3; val_offset:31017*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 31017*FLEN/8, x4, x1, x2)

inst_10340:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfe00; op2val:0x3c00;
op3val:0x7c01; valaddr_reg:x3; val_offset:31020*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 31020*FLEN/8, x4, x1, x2)

inst_10341:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x155 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfe00; op2val:0x3c00;
op3val:0xfd55; valaddr_reg:x3; val_offset:31023*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 31023*FLEN/8, x4, x1, x2)

inst_10342:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfe00; op2val:0x3c00;
op3val:0x3c00; valaddr_reg:x3; val_offset:31026*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 31026*FLEN/8, x4, x1, x2)

inst_10343:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfe00; op2val:0x3c00;
op3val:0xbc00; valaddr_reg:x3; val_offset:31029*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 31029*FLEN/8, x4, x1, x2)

inst_10344:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfe00; op2val:0xbc00;
op3val:0x0; valaddr_reg:x3; val_offset:31032*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 31032*FLEN/8, x4, x1, x2)

inst_10345:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfe00; op2val:0xbc00;
op3val:0x8000; valaddr_reg:x3; val_offset:31035*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 31035*FLEN/8, x4, x1, x2)

inst_10346:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfe00; op2val:0xbc00;
op3val:0x1; valaddr_reg:x3; val_offset:31038*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 31038*FLEN/8, x4, x1, x2)

inst_10347:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfe00; op2val:0xbc00;
op3val:0x8001; valaddr_reg:x3; val_offset:31041*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 31041*FLEN/8, x4, x1, x2)

inst_10348:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x002 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfe00; op2val:0xbc00;
op3val:0x2; valaddr_reg:x3; val_offset:31044*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 31044*FLEN/8, x4, x1, x2)

inst_10349:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3fe and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfe00; op2val:0xbc00;
op3val:0x83fe; valaddr_reg:x3; val_offset:31047*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 31047*FLEN/8, x4, x1, x2)

inst_10350:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfe00; op2val:0xbc00;
op3val:0x3ff; valaddr_reg:x3; val_offset:31050*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 31050*FLEN/8, x4, x1, x2)

inst_10351:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfe00; op2val:0xbc00;
op3val:0x83ff; valaddr_reg:x3; val_offset:31053*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 31053*FLEN/8, x4, x1, x2)

inst_10352:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfe00; op2val:0xbc00;
op3val:0x400; valaddr_reg:x3; val_offset:31056*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 31056*FLEN/8, x4, x1, x2)

inst_10353:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfe00; op2val:0xbc00;
op3val:0x8400; valaddr_reg:x3; val_offset:31059*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 31059*FLEN/8, x4, x1, x2)

inst_10354:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfe00; op2val:0xbc00;
op3val:0x401; valaddr_reg:x3; val_offset:31062*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 31062*FLEN/8, x4, x1, x2)

inst_10355:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfe00; op2val:0xbc00;
op3val:0x8455; valaddr_reg:x3; val_offset:31065*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 31065*FLEN/8, x4, x1, x2)

inst_10356:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfe00; op2val:0xbc00;
op3val:0x7bff; valaddr_reg:x3; val_offset:31068*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 31068*FLEN/8, x4, x1, x2)

inst_10357:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfe00; op2val:0xbc00;
op3val:0xfbff; valaddr_reg:x3; val_offset:31071*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 31071*FLEN/8, x4, x1, x2)

inst_10358:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfe00; op2val:0xbc00;
op3val:0x7c00; valaddr_reg:x3; val_offset:31074*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 31074*FLEN/8, x4, x1, x2)

inst_10359:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfe00; op2val:0xbc00;
op3val:0xfc00; valaddr_reg:x3; val_offset:31077*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 31077*FLEN/8, x4, x1, x2)

inst_10360:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfe00; op2val:0xbc00;
op3val:0x7e00; valaddr_reg:x3; val_offset:31080*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 31080*FLEN/8, x4, x1, x2)

inst_10361:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfe00; op2val:0xbc00;
op3val:0xfe00; valaddr_reg:x3; val_offset:31083*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 31083*FLEN/8, x4, x1, x2)

inst_10362:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x201 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfe00; op2val:0xbc00;
op3val:0x7e01; valaddr_reg:x3; val_offset:31086*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 31086*FLEN/8, x4, x1, x2)

inst_10363:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x255 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfe00; op2val:0xbc00;
op3val:0xfe55; valaddr_reg:x3; val_offset:31089*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 31089*FLEN/8, x4, x1, x2)

inst_10364:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfe00; op2val:0xbc00;
op3val:0x7c01; valaddr_reg:x3; val_offset:31092*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 31092*FLEN/8, x4, x1, x2)

inst_10365:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x155 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfe00; op2val:0xbc00;
op3val:0xfd55; valaddr_reg:x3; val_offset:31095*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 31095*FLEN/8, x4, x1, x2)

inst_10366:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfe00; op2val:0xbc00;
op3val:0x3c00; valaddr_reg:x3; val_offset:31098*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 31098*FLEN/8, x4, x1, x2)

inst_10367:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfe00; op2val:0xbc00;
op3val:0xbc00; valaddr_reg:x3; val_offset:31101*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 31101*FLEN/8, x4, x1, x2)

RVTEST_SIGBASE(x1,signature_x1_82)
inst_10368:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e01; op2val:0x0;
op3val:0x0; valaddr_reg:x3; val_offset:31104*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 31104*FLEN/8, x4, x1, x2)

inst_10369:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e01; op2val:0x0;
op3val:0x8000; valaddr_reg:x3; val_offset:31107*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 31107*FLEN/8, x4, x1, x2)

inst_10370:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e01; op2val:0x0;
op3val:0x1; valaddr_reg:x3; val_offset:31110*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 31110*FLEN/8, x4, x1, x2)

inst_10371:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e01; op2val:0x0;
op3val:0x8001; valaddr_reg:x3; val_offset:31113*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 31113*FLEN/8, x4, x1, x2)

inst_10372:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x002 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e01; op2val:0x0;
op3val:0x2; valaddr_reg:x3; val_offset:31116*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 31116*FLEN/8, x4, x1, x2)

inst_10373:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3fe and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e01; op2val:0x0;
op3val:0x83fe; valaddr_reg:x3; val_offset:31119*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 31119*FLEN/8, x4, x1, x2)

inst_10374:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e01; op2val:0x0;
op3val:0x3ff; valaddr_reg:x3; val_offset:31122*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 31122*FLEN/8, x4, x1, x2)

inst_10375:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e01; op2val:0x0;
op3val:0x83ff; valaddr_reg:x3; val_offset:31125*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 31125*FLEN/8, x4, x1, x2)

inst_10376:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e01; op2val:0x0;
op3val:0x400; valaddr_reg:x3; val_offset:31128*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 31128*FLEN/8, x4, x1, x2)

inst_10377:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e01; op2val:0x0;
op3val:0x8400; valaddr_reg:x3; val_offset:31131*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 31131*FLEN/8, x4, x1, x2)

inst_10378:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e01; op2val:0x0;
op3val:0x401; valaddr_reg:x3; val_offset:31134*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 31134*FLEN/8, x4, x1, x2)

inst_10379:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e01; op2val:0x0;
op3val:0x8455; valaddr_reg:x3; val_offset:31137*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 31137*FLEN/8, x4, x1, x2)

inst_10380:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e01; op2val:0x0;
op3val:0x7bff; valaddr_reg:x3; val_offset:31140*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 31140*FLEN/8, x4, x1, x2)

inst_10381:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e01; op2val:0x0;
op3val:0xfbff; valaddr_reg:x3; val_offset:31143*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 31143*FLEN/8, x4, x1, x2)

inst_10382:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e01; op2val:0x0;
op3val:0x7c00; valaddr_reg:x3; val_offset:31146*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 31146*FLEN/8, x4, x1, x2)

inst_10383:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e01; op2val:0x0;
op3val:0xfc00; valaddr_reg:x3; val_offset:31149*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 31149*FLEN/8, x4, x1, x2)

inst_10384:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e01; op2val:0x0;
op3val:0x7e00; valaddr_reg:x3; val_offset:31152*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 31152*FLEN/8, x4, x1, x2)

inst_10385:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e01; op2val:0x0;
op3val:0xfe00; valaddr_reg:x3; val_offset:31155*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 31155*FLEN/8, x4, x1, x2)

inst_10386:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x201 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e01; op2val:0x0;
op3val:0x7e01; valaddr_reg:x3; val_offset:31158*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 31158*FLEN/8, x4, x1, x2)

inst_10387:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x255 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e01; op2val:0x0;
op3val:0xfe55; valaddr_reg:x3; val_offset:31161*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 31161*FLEN/8, x4, x1, x2)

inst_10388:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e01; op2val:0x0;
op3val:0x7c01; valaddr_reg:x3; val_offset:31164*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 31164*FLEN/8, x4, x1, x2)

inst_10389:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x155 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e01; op2val:0x0;
op3val:0xfd55; valaddr_reg:x3; val_offset:31167*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 31167*FLEN/8, x4, x1, x2)

inst_10390:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e01; op2val:0x0;
op3val:0x3c00; valaddr_reg:x3; val_offset:31170*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 31170*FLEN/8, x4, x1, x2)

inst_10391:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e01; op2val:0x0;
op3val:0xbc00; valaddr_reg:x3; val_offset:31173*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 31173*FLEN/8, x4, x1, x2)

inst_10392:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e01; op2val:0x8000;
op3val:0x0; valaddr_reg:x3; val_offset:31176*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 31176*FLEN/8, x4, x1, x2)

inst_10393:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e01; op2val:0x8000;
op3val:0x8000; valaddr_reg:x3; val_offset:31179*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 31179*FLEN/8, x4, x1, x2)

inst_10394:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e01; op2val:0x8000;
op3val:0x1; valaddr_reg:x3; val_offset:31182*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 31182*FLEN/8, x4, x1, x2)

inst_10395:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e01; op2val:0x8000;
op3val:0x8001; valaddr_reg:x3; val_offset:31185*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 31185*FLEN/8, x4, x1, x2)

inst_10396:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x002 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e01; op2val:0x8000;
op3val:0x2; valaddr_reg:x3; val_offset:31188*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 31188*FLEN/8, x4, x1, x2)

inst_10397:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3fe and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e01; op2val:0x8000;
op3val:0x83fe; valaddr_reg:x3; val_offset:31191*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 31191*FLEN/8, x4, x1, x2)

inst_10398:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e01; op2val:0x8000;
op3val:0x3ff; valaddr_reg:x3; val_offset:31194*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 31194*FLEN/8, x4, x1, x2)

inst_10399:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e01; op2val:0x8000;
op3val:0x83ff; valaddr_reg:x3; val_offset:31197*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 31197*FLEN/8, x4, x1, x2)

inst_10400:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e01; op2val:0x8000;
op3val:0x400; valaddr_reg:x3; val_offset:31200*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 31200*FLEN/8, x4, x1, x2)

inst_10401:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e01; op2val:0x8000;
op3val:0x8400; valaddr_reg:x3; val_offset:31203*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 31203*FLEN/8, x4, x1, x2)

inst_10402:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e01; op2val:0x8000;
op3val:0x401; valaddr_reg:x3; val_offset:31206*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 31206*FLEN/8, x4, x1, x2)

inst_10403:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e01; op2val:0x8000;
op3val:0x8455; valaddr_reg:x3; val_offset:31209*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 31209*FLEN/8, x4, x1, x2)

inst_10404:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e01; op2val:0x8000;
op3val:0x7bff; valaddr_reg:x3; val_offset:31212*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 31212*FLEN/8, x4, x1, x2)

inst_10405:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e01; op2val:0x8000;
op3val:0xfbff; valaddr_reg:x3; val_offset:31215*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 31215*FLEN/8, x4, x1, x2)

inst_10406:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e01; op2val:0x8000;
op3val:0x7c00; valaddr_reg:x3; val_offset:31218*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 31218*FLEN/8, x4, x1, x2)

inst_10407:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e01; op2val:0x8000;
op3val:0xfc00; valaddr_reg:x3; val_offset:31221*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 31221*FLEN/8, x4, x1, x2)

inst_10408:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e01; op2val:0x8000;
op3val:0x7e00; valaddr_reg:x3; val_offset:31224*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 31224*FLEN/8, x4, x1, x2)

inst_10409:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e01; op2val:0x8000;
op3val:0xfe00; valaddr_reg:x3; val_offset:31227*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 31227*FLEN/8, x4, x1, x2)

inst_10410:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x201 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e01; op2val:0x8000;
op3val:0x7e01; valaddr_reg:x3; val_offset:31230*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 31230*FLEN/8, x4, x1, x2)

inst_10411:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x255 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e01; op2val:0x8000;
op3val:0xfe55; valaddr_reg:x3; val_offset:31233*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 31233*FLEN/8, x4, x1, x2)

inst_10412:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e01; op2val:0x8000;
op3val:0x7c01; valaddr_reg:x3; val_offset:31236*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 31236*FLEN/8, x4, x1, x2)

inst_10413:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x155 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e01; op2val:0x8000;
op3val:0xfd55; valaddr_reg:x3; val_offset:31239*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 31239*FLEN/8, x4, x1, x2)

inst_10414:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e01; op2val:0x8000;
op3val:0x3c00; valaddr_reg:x3; val_offset:31242*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 31242*FLEN/8, x4, x1, x2)

inst_10415:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e01; op2val:0x8000;
op3val:0xbc00; valaddr_reg:x3; val_offset:31245*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 31245*FLEN/8, x4, x1, x2)

inst_10416:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e01; op2val:0x1;
op3val:0x0; valaddr_reg:x3; val_offset:31248*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 31248*FLEN/8, x4, x1, x2)

inst_10417:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e01; op2val:0x1;
op3val:0x8000; valaddr_reg:x3; val_offset:31251*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 31251*FLEN/8, x4, x1, x2)

inst_10418:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e01; op2val:0x1;
op3val:0x1; valaddr_reg:x3; val_offset:31254*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 31254*FLEN/8, x4, x1, x2)

inst_10419:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e01; op2val:0x1;
op3val:0x8001; valaddr_reg:x3; val_offset:31257*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 31257*FLEN/8, x4, x1, x2)

inst_10420:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x002 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e01; op2val:0x1;
op3val:0x2; valaddr_reg:x3; val_offset:31260*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 31260*FLEN/8, x4, x1, x2)

inst_10421:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3fe and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e01; op2val:0x1;
op3val:0x83fe; valaddr_reg:x3; val_offset:31263*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 31263*FLEN/8, x4, x1, x2)

inst_10422:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e01; op2val:0x1;
op3val:0x3ff; valaddr_reg:x3; val_offset:31266*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 31266*FLEN/8, x4, x1, x2)

inst_10423:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e01; op2val:0x1;
op3val:0x83ff; valaddr_reg:x3; val_offset:31269*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 31269*FLEN/8, x4, x1, x2)

inst_10424:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e01; op2val:0x1;
op3val:0x400; valaddr_reg:x3; val_offset:31272*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 31272*FLEN/8, x4, x1, x2)

inst_10425:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e01; op2val:0x1;
op3val:0x8400; valaddr_reg:x3; val_offset:31275*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 31275*FLEN/8, x4, x1, x2)

inst_10426:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e01; op2val:0x1;
op3val:0x401; valaddr_reg:x3; val_offset:31278*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 31278*FLEN/8, x4, x1, x2)

inst_10427:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e01; op2val:0x1;
op3val:0x8455; valaddr_reg:x3; val_offset:31281*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 31281*FLEN/8, x4, x1, x2)

inst_10428:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e01; op2val:0x1;
op3val:0x7bff; valaddr_reg:x3; val_offset:31284*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 31284*FLEN/8, x4, x1, x2)

inst_10429:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e01; op2val:0x1;
op3val:0xfbff; valaddr_reg:x3; val_offset:31287*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 31287*FLEN/8, x4, x1, x2)

inst_10430:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e01; op2val:0x1;
op3val:0x7c00; valaddr_reg:x3; val_offset:31290*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 31290*FLEN/8, x4, x1, x2)

inst_10431:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e01; op2val:0x1;
op3val:0xfc00; valaddr_reg:x3; val_offset:31293*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 31293*FLEN/8, x4, x1, x2)

inst_10432:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e01; op2val:0x1;
op3val:0x7e00; valaddr_reg:x3; val_offset:31296*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 31296*FLEN/8, x4, x1, x2)

inst_10433:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e01; op2val:0x1;
op3val:0xfe00; valaddr_reg:x3; val_offset:31299*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 31299*FLEN/8, x4, x1, x2)

inst_10434:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x201 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e01; op2val:0x1;
op3val:0x7e01; valaddr_reg:x3; val_offset:31302*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 31302*FLEN/8, x4, x1, x2)

inst_10435:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x255 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e01; op2val:0x1;
op3val:0xfe55; valaddr_reg:x3; val_offset:31305*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 31305*FLEN/8, x4, x1, x2)

inst_10436:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e01; op2val:0x1;
op3val:0x7c01; valaddr_reg:x3; val_offset:31308*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 31308*FLEN/8, x4, x1, x2)

inst_10437:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x155 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e01; op2val:0x1;
op3val:0xfd55; valaddr_reg:x3; val_offset:31311*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 31311*FLEN/8, x4, x1, x2)

inst_10438:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e01; op2val:0x1;
op3val:0x3c00; valaddr_reg:x3; val_offset:31314*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 31314*FLEN/8, x4, x1, x2)

inst_10439:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e01; op2val:0x1;
op3val:0xbc00; valaddr_reg:x3; val_offset:31317*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 31317*FLEN/8, x4, x1, x2)

inst_10440:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e01; op2val:0x8001;
op3val:0x0; valaddr_reg:x3; val_offset:31320*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 31320*FLEN/8, x4, x1, x2)

inst_10441:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e01; op2val:0x8001;
op3val:0x8000; valaddr_reg:x3; val_offset:31323*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 31323*FLEN/8, x4, x1, x2)

inst_10442:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e01; op2val:0x8001;
op3val:0x1; valaddr_reg:x3; val_offset:31326*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 31326*FLEN/8, x4, x1, x2)

inst_10443:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e01; op2val:0x8001;
op3val:0x8001; valaddr_reg:x3; val_offset:31329*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 31329*FLEN/8, x4, x1, x2)

inst_10444:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x002 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e01; op2val:0x8001;
op3val:0x2; valaddr_reg:x3; val_offset:31332*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 31332*FLEN/8, x4, x1, x2)

inst_10445:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3fe and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e01; op2val:0x8001;
op3val:0x83fe; valaddr_reg:x3; val_offset:31335*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 31335*FLEN/8, x4, x1, x2)

inst_10446:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e01; op2val:0x8001;
op3val:0x3ff; valaddr_reg:x3; val_offset:31338*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 31338*FLEN/8, x4, x1, x2)

inst_10447:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e01; op2val:0x8001;
op3val:0x83ff; valaddr_reg:x3; val_offset:31341*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 31341*FLEN/8, x4, x1, x2)

inst_10448:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e01; op2val:0x8001;
op3val:0x400; valaddr_reg:x3; val_offset:31344*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 31344*FLEN/8, x4, x1, x2)

inst_10449:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e01; op2val:0x8001;
op3val:0x8400; valaddr_reg:x3; val_offset:31347*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 31347*FLEN/8, x4, x1, x2)

inst_10450:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e01; op2val:0x8001;
op3val:0x401; valaddr_reg:x3; val_offset:31350*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 31350*FLEN/8, x4, x1, x2)

inst_10451:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e01; op2val:0x8001;
op3val:0x8455; valaddr_reg:x3; val_offset:31353*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 31353*FLEN/8, x4, x1, x2)

inst_10452:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e01; op2val:0x8001;
op3val:0x7bff; valaddr_reg:x3; val_offset:31356*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 31356*FLEN/8, x4, x1, x2)

inst_10453:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e01; op2val:0x8001;
op3val:0xfbff; valaddr_reg:x3; val_offset:31359*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 31359*FLEN/8, x4, x1, x2)

inst_10454:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e01; op2val:0x8001;
op3val:0x7c00; valaddr_reg:x3; val_offset:31362*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 31362*FLEN/8, x4, x1, x2)

inst_10455:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e01; op2val:0x8001;
op3val:0xfc00; valaddr_reg:x3; val_offset:31365*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 31365*FLEN/8, x4, x1, x2)

inst_10456:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e01; op2val:0x8001;
op3val:0x7e00; valaddr_reg:x3; val_offset:31368*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 31368*FLEN/8, x4, x1, x2)

inst_10457:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e01; op2val:0x8001;
op3val:0xfe00; valaddr_reg:x3; val_offset:31371*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 31371*FLEN/8, x4, x1, x2)

inst_10458:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x201 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e01; op2val:0x8001;
op3val:0x7e01; valaddr_reg:x3; val_offset:31374*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 31374*FLEN/8, x4, x1, x2)

inst_10459:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x255 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e01; op2val:0x8001;
op3val:0xfe55; valaddr_reg:x3; val_offset:31377*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 31377*FLEN/8, x4, x1, x2)

inst_10460:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e01; op2val:0x8001;
op3val:0x7c01; valaddr_reg:x3; val_offset:31380*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 31380*FLEN/8, x4, x1, x2)

inst_10461:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x155 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e01; op2val:0x8001;
op3val:0xfd55; valaddr_reg:x3; val_offset:31383*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 31383*FLEN/8, x4, x1, x2)

inst_10462:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e01; op2val:0x8001;
op3val:0x3c00; valaddr_reg:x3; val_offset:31386*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 31386*FLEN/8, x4, x1, x2)

inst_10463:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e01; op2val:0x8001;
op3val:0xbc00; valaddr_reg:x3; val_offset:31389*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 31389*FLEN/8, x4, x1, x2)

inst_10464:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e01; op2val:0x2;
op3val:0x0; valaddr_reg:x3; val_offset:31392*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 31392*FLEN/8, x4, x1, x2)

inst_10465:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e01; op2val:0x2;
op3val:0x8000; valaddr_reg:x3; val_offset:31395*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 31395*FLEN/8, x4, x1, x2)

inst_10466:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e01; op2val:0x2;
op3val:0x1; valaddr_reg:x3; val_offset:31398*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 31398*FLEN/8, x4, x1, x2)

inst_10467:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e01; op2val:0x2;
op3val:0x8001; valaddr_reg:x3; val_offset:31401*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 31401*FLEN/8, x4, x1, x2)

inst_10468:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x002 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e01; op2val:0x2;
op3val:0x2; valaddr_reg:x3; val_offset:31404*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 31404*FLEN/8, x4, x1, x2)

inst_10469:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3fe and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e01; op2val:0x2;
op3val:0x83fe; valaddr_reg:x3; val_offset:31407*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 31407*FLEN/8, x4, x1, x2)

inst_10470:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e01; op2val:0x2;
op3val:0x3ff; valaddr_reg:x3; val_offset:31410*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 31410*FLEN/8, x4, x1, x2)

inst_10471:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e01; op2val:0x2;
op3val:0x83ff; valaddr_reg:x3; val_offset:31413*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 31413*FLEN/8, x4, x1, x2)

inst_10472:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e01; op2val:0x2;
op3val:0x400; valaddr_reg:x3; val_offset:31416*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 31416*FLEN/8, x4, x1, x2)

inst_10473:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e01; op2val:0x2;
op3val:0x8400; valaddr_reg:x3; val_offset:31419*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 31419*FLEN/8, x4, x1, x2)

inst_10474:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e01; op2val:0x2;
op3val:0x401; valaddr_reg:x3; val_offset:31422*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 31422*FLEN/8, x4, x1, x2)

inst_10475:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e01; op2val:0x2;
op3val:0x8455; valaddr_reg:x3; val_offset:31425*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 31425*FLEN/8, x4, x1, x2)

inst_10476:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e01; op2val:0x2;
op3val:0x7bff; valaddr_reg:x3; val_offset:31428*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 31428*FLEN/8, x4, x1, x2)

inst_10477:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e01; op2val:0x2;
op3val:0xfbff; valaddr_reg:x3; val_offset:31431*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 31431*FLEN/8, x4, x1, x2)

inst_10478:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e01; op2val:0x2;
op3val:0x7c00; valaddr_reg:x3; val_offset:31434*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 31434*FLEN/8, x4, x1, x2)

inst_10479:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e01; op2val:0x2;
op3val:0xfc00; valaddr_reg:x3; val_offset:31437*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 31437*FLEN/8, x4, x1, x2)

inst_10480:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e01; op2val:0x2;
op3val:0x7e00; valaddr_reg:x3; val_offset:31440*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 31440*FLEN/8, x4, x1, x2)

inst_10481:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e01; op2val:0x2;
op3val:0xfe00; valaddr_reg:x3; val_offset:31443*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 31443*FLEN/8, x4, x1, x2)

inst_10482:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x201 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e01; op2val:0x2;
op3val:0x7e01; valaddr_reg:x3; val_offset:31446*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 31446*FLEN/8, x4, x1, x2)

inst_10483:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x255 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e01; op2val:0x2;
op3val:0xfe55; valaddr_reg:x3; val_offset:31449*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 31449*FLEN/8, x4, x1, x2)

inst_10484:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e01; op2val:0x2;
op3val:0x7c01; valaddr_reg:x3; val_offset:31452*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 31452*FLEN/8, x4, x1, x2)

inst_10485:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x155 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e01; op2val:0x2;
op3val:0xfd55; valaddr_reg:x3; val_offset:31455*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 31455*FLEN/8, x4, x1, x2)

inst_10486:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fs3 == 0 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e01; op2val:0x2;
op3val:0x3c00; valaddr_reg:x3; val_offset:31458*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 31458*FLEN/8, x4, x1, x2)

inst_10487:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fs3 == 1 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e01; op2val:0x2;
op3val:0xbc00; valaddr_reg:x3; val_offset:31461*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 31461*FLEN/8, x4, x1, x2)

inst_10488:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e01; op2val:0x83fe;
op3val:0x0; valaddr_reg:x3; val_offset:31464*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 31464*FLEN/8, x4, x1, x2)

inst_10489:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e01; op2val:0x83fe;
op3val:0x8000; valaddr_reg:x3; val_offset:31467*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 31467*FLEN/8, x4, x1, x2)

inst_10490:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fs3 == 0 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e01; op2val:0x83fe;
op3val:0x1; valaddr_reg:x3; val_offset:31470*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 31470*FLEN/8, x4, x1, x2)

inst_10491:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fs3 == 1 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e01; op2val:0x83fe;
op3val:0x8001; valaddr_reg:x3; val_offset:31473*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 31473*FLEN/8, x4, x1, x2)

inst_10492:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fs3 == 0 and fe3 == 0x00 and fm3 == 0x002 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e01; op2val:0x83fe;
op3val:0x2; valaddr_reg:x3; val_offset:31476*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 31476*FLEN/8, x4, x1, x2)

inst_10493:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3fe and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e01; op2val:0x83fe;
op3val:0x83fe; valaddr_reg:x3; val_offset:31479*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 31479*FLEN/8, x4, x1, x2)

inst_10494:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fs3 == 0 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e01; op2val:0x83fe;
op3val:0x3ff; valaddr_reg:x3; val_offset:31482*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 31482*FLEN/8, x4, x1, x2)

inst_10495:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e01; op2val:0x83fe;
op3val:0x83ff; valaddr_reg:x3; val_offset:31485*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 31485*FLEN/8, x4, x1, x2)

RVTEST_SIGBASE(x1,signature_x1_83)
inst_10496:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e01; op2val:0x83fe;
op3val:0x400; valaddr_reg:x3; val_offset:31488*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 31488*FLEN/8, x4, x1, x2)

inst_10497:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e01; op2val:0x83fe;
op3val:0x8400; valaddr_reg:x3; val_offset:31491*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 31491*FLEN/8, x4, x1, x2)

inst_10498:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fs3 == 0 and fe3 == 0x01 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e01; op2val:0x83fe;
op3val:0x401; valaddr_reg:x3; val_offset:31494*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 31494*FLEN/8, x4, x1, x2)

inst_10499:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e01; op2val:0x83fe;
op3val:0x8455; valaddr_reg:x3; val_offset:31497*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 31497*FLEN/8, x4, x1, x2)

inst_10500:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e01; op2val:0x83fe;
op3val:0x7bff; valaddr_reg:x3; val_offset:31500*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 31500*FLEN/8, x4, x1, x2)

inst_10501:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e01; op2val:0x83fe;
op3val:0xfbff; valaddr_reg:x3; val_offset:31503*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 31503*FLEN/8, x4, x1, x2)

inst_10502:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fs3 == 0 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e01; op2val:0x83fe;
op3val:0x7c00; valaddr_reg:x3; val_offset:31506*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 31506*FLEN/8, x4, x1, x2)

inst_10503:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fs3 == 1 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e01; op2val:0x83fe;
op3val:0xfc00; valaddr_reg:x3; val_offset:31509*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 31509*FLEN/8, x4, x1, x2)

inst_10504:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fs3 == 0 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e01; op2val:0x83fe;
op3val:0x7e00; valaddr_reg:x3; val_offset:31512*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 31512*FLEN/8, x4, x1, x2)

inst_10505:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fs3 == 1 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e01; op2val:0x83fe;
op3val:0xfe00; valaddr_reg:x3; val_offset:31515*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 31515*FLEN/8, x4, x1, x2)

inst_10506:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fs3 == 0 and fe3 == 0x1f and fm3 == 0x201 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e01; op2val:0x83fe;
op3val:0x7e01; valaddr_reg:x3; val_offset:31518*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 31518*FLEN/8, x4, x1, x2)

inst_10507:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fs3 == 1 and fe3 == 0x1f and fm3 == 0x255 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e01; op2val:0x83fe;
op3val:0xfe55; valaddr_reg:x3; val_offset:31521*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 31521*FLEN/8, x4, x1, x2)

inst_10508:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fs3 == 0 and fe3 == 0x1f and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e01; op2val:0x83fe;
op3val:0x7c01; valaddr_reg:x3; val_offset:31524*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 31524*FLEN/8, x4, x1, x2)

inst_10509:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fs3 == 1 and fe3 == 0x1f and fm3 == 0x155 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e01; op2val:0x83fe;
op3val:0xfd55; valaddr_reg:x3; val_offset:31527*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 31527*FLEN/8, x4, x1, x2)

inst_10510:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fs3 == 0 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e01; op2val:0x83fe;
op3val:0x3c00; valaddr_reg:x3; val_offset:31530*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 31530*FLEN/8, x4, x1, x2)

inst_10511:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fs3 == 1 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e01; op2val:0x83fe;
op3val:0xbc00; valaddr_reg:x3; val_offset:31533*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 31533*FLEN/8, x4, x1, x2)

inst_10512:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e01; op2val:0x3ff;
op3val:0x0; valaddr_reg:x3; val_offset:31536*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 31536*FLEN/8, x4, x1, x2)

inst_10513:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e01; op2val:0x3ff;
op3val:0x8000; valaddr_reg:x3; val_offset:31539*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 31539*FLEN/8, x4, x1, x2)

inst_10514:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e01; op2val:0x3ff;
op3val:0x1; valaddr_reg:x3; val_offset:31542*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 31542*FLEN/8, x4, x1, x2)

inst_10515:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e01; op2val:0x3ff;
op3val:0x8001; valaddr_reg:x3; val_offset:31545*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 31545*FLEN/8, x4, x1, x2)

inst_10516:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x002 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e01; op2val:0x3ff;
op3val:0x2; valaddr_reg:x3; val_offset:31548*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 31548*FLEN/8, x4, x1, x2)

inst_10517:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3fe and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e01; op2val:0x3ff;
op3val:0x83fe; valaddr_reg:x3; val_offset:31551*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 31551*FLEN/8, x4, x1, x2)

inst_10518:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e01; op2val:0x3ff;
op3val:0x3ff; valaddr_reg:x3; val_offset:31554*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 31554*FLEN/8, x4, x1, x2)

inst_10519:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e01; op2val:0x3ff;
op3val:0x83ff; valaddr_reg:x3; val_offset:31557*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 31557*FLEN/8, x4, x1, x2)

inst_10520:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e01; op2val:0x3ff;
op3val:0x400; valaddr_reg:x3; val_offset:31560*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 31560*FLEN/8, x4, x1, x2)

inst_10521:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e01; op2val:0x3ff;
op3val:0x8400; valaddr_reg:x3; val_offset:31563*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 31563*FLEN/8, x4, x1, x2)

inst_10522:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x01 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e01; op2val:0x3ff;
op3val:0x401; valaddr_reg:x3; val_offset:31566*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 31566*FLEN/8, x4, x1, x2)

inst_10523:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e01; op2val:0x3ff;
op3val:0x8455; valaddr_reg:x3; val_offset:31569*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 31569*FLEN/8, x4, x1, x2)

inst_10524:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e01; op2val:0x3ff;
op3val:0x7bff; valaddr_reg:x3; val_offset:31572*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 31572*FLEN/8, x4, x1, x2)

inst_10525:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e01; op2val:0x3ff;
op3val:0xfbff; valaddr_reg:x3; val_offset:31575*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 31575*FLEN/8, x4, x1, x2)

inst_10526:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e01; op2val:0x3ff;
op3val:0x7c00; valaddr_reg:x3; val_offset:31578*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 31578*FLEN/8, x4, x1, x2)

inst_10527:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e01; op2val:0x3ff;
op3val:0xfc00; valaddr_reg:x3; val_offset:31581*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 31581*FLEN/8, x4, x1, x2)

inst_10528:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e01; op2val:0x3ff;
op3val:0x7e00; valaddr_reg:x3; val_offset:31584*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 31584*FLEN/8, x4, x1, x2)

inst_10529:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e01; op2val:0x3ff;
op3val:0xfe00; valaddr_reg:x3; val_offset:31587*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 31587*FLEN/8, x4, x1, x2)

inst_10530:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x1f and fm3 == 0x201 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e01; op2val:0x3ff;
op3val:0x7e01; valaddr_reg:x3; val_offset:31590*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 31590*FLEN/8, x4, x1, x2)

inst_10531:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x1f and fm3 == 0x255 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e01; op2val:0x3ff;
op3val:0xfe55; valaddr_reg:x3; val_offset:31593*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 31593*FLEN/8, x4, x1, x2)

inst_10532:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x1f and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e01; op2val:0x3ff;
op3val:0x7c01; valaddr_reg:x3; val_offset:31596*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 31596*FLEN/8, x4, x1, x2)

inst_10533:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x1f and fm3 == 0x155 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e01; op2val:0x3ff;
op3val:0xfd55; valaddr_reg:x3; val_offset:31599*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 31599*FLEN/8, x4, x1, x2)

inst_10534:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e01; op2val:0x3ff;
op3val:0x3c00; valaddr_reg:x3; val_offset:31602*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 31602*FLEN/8, x4, x1, x2)

inst_10535:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e01; op2val:0x3ff;
op3val:0xbc00; valaddr_reg:x3; val_offset:31605*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 31605*FLEN/8, x4, x1, x2)

inst_10536:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e01; op2val:0x83ff;
op3val:0x0; valaddr_reg:x3; val_offset:31608*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 31608*FLEN/8, x4, x1, x2)

inst_10537:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e01; op2val:0x83ff;
op3val:0x8000; valaddr_reg:x3; val_offset:31611*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 31611*FLEN/8, x4, x1, x2)

inst_10538:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e01; op2val:0x83ff;
op3val:0x1; valaddr_reg:x3; val_offset:31614*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 31614*FLEN/8, x4, x1, x2)

inst_10539:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e01; op2val:0x83ff;
op3val:0x8001; valaddr_reg:x3; val_offset:31617*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 31617*FLEN/8, x4, x1, x2)

inst_10540:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x002 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e01; op2val:0x83ff;
op3val:0x2; valaddr_reg:x3; val_offset:31620*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 31620*FLEN/8, x4, x1, x2)

inst_10541:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3fe and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e01; op2val:0x83ff;
op3val:0x83fe; valaddr_reg:x3; val_offset:31623*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 31623*FLEN/8, x4, x1, x2)

inst_10542:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e01; op2val:0x83ff;
op3val:0x3ff; valaddr_reg:x3; val_offset:31626*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 31626*FLEN/8, x4, x1, x2)

inst_10543:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e01; op2val:0x83ff;
op3val:0x83ff; valaddr_reg:x3; val_offset:31629*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 31629*FLEN/8, x4, x1, x2)

inst_10544:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e01; op2val:0x83ff;
op3val:0x400; valaddr_reg:x3; val_offset:31632*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 31632*FLEN/8, x4, x1, x2)

inst_10545:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e01; op2val:0x83ff;
op3val:0x8400; valaddr_reg:x3; val_offset:31635*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 31635*FLEN/8, x4, x1, x2)

inst_10546:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x01 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e01; op2val:0x83ff;
op3val:0x401; valaddr_reg:x3; val_offset:31638*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 31638*FLEN/8, x4, x1, x2)

inst_10547:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e01; op2val:0x83ff;
op3val:0x8455; valaddr_reg:x3; val_offset:31641*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 31641*FLEN/8, x4, x1, x2)

inst_10548:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e01; op2val:0x83ff;
op3val:0x7bff; valaddr_reg:x3; val_offset:31644*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 31644*FLEN/8, x4, x1, x2)

inst_10549:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e01; op2val:0x83ff;
op3val:0xfbff; valaddr_reg:x3; val_offset:31647*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 31647*FLEN/8, x4, x1, x2)

inst_10550:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e01; op2val:0x83ff;
op3val:0x7c00; valaddr_reg:x3; val_offset:31650*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 31650*FLEN/8, x4, x1, x2)

inst_10551:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e01; op2val:0x83ff;
op3val:0xfc00; valaddr_reg:x3; val_offset:31653*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 31653*FLEN/8, x4, x1, x2)

inst_10552:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e01; op2val:0x83ff;
op3val:0x7e00; valaddr_reg:x3; val_offset:31656*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 31656*FLEN/8, x4, x1, x2)

inst_10553:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e01; op2val:0x83ff;
op3val:0xfe00; valaddr_reg:x3; val_offset:31659*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 31659*FLEN/8, x4, x1, x2)

inst_10554:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x1f and fm3 == 0x201 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e01; op2val:0x83ff;
op3val:0x7e01; valaddr_reg:x3; val_offset:31662*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 31662*FLEN/8, x4, x1, x2)

inst_10555:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x1f and fm3 == 0x255 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e01; op2val:0x83ff;
op3val:0xfe55; valaddr_reg:x3; val_offset:31665*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 31665*FLEN/8, x4, x1, x2)

inst_10556:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x1f and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e01; op2val:0x83ff;
op3val:0x7c01; valaddr_reg:x3; val_offset:31668*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 31668*FLEN/8, x4, x1, x2)

inst_10557:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x1f and fm3 == 0x155 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e01; op2val:0x83ff;
op3val:0xfd55; valaddr_reg:x3; val_offset:31671*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 31671*FLEN/8, x4, x1, x2)

inst_10558:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e01; op2val:0x83ff;
op3val:0x3c00; valaddr_reg:x3; val_offset:31674*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 31674*FLEN/8, x4, x1, x2)

inst_10559:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e01; op2val:0x83ff;
op3val:0xbc00; valaddr_reg:x3; val_offset:31677*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 31677*FLEN/8, x4, x1, x2)

inst_10560:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e01; op2val:0x400;
op3val:0x0; valaddr_reg:x3; val_offset:31680*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 31680*FLEN/8, x4, x1, x2)

inst_10561:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e01; op2val:0x400;
op3val:0x8000; valaddr_reg:x3; val_offset:31683*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 31683*FLEN/8, x4, x1, x2)

inst_10562:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e01; op2val:0x400;
op3val:0x1; valaddr_reg:x3; val_offset:31686*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 31686*FLEN/8, x4, x1, x2)

inst_10563:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e01; op2val:0x400;
op3val:0x8001; valaddr_reg:x3; val_offset:31689*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 31689*FLEN/8, x4, x1, x2)

inst_10564:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x002 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e01; op2val:0x400;
op3val:0x2; valaddr_reg:x3; val_offset:31692*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 31692*FLEN/8, x4, x1, x2)

inst_10565:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3fe and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e01; op2val:0x400;
op3val:0x83fe; valaddr_reg:x3; val_offset:31695*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 31695*FLEN/8, x4, x1, x2)

inst_10566:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e01; op2val:0x400;
op3val:0x3ff; valaddr_reg:x3; val_offset:31698*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 31698*FLEN/8, x4, x1, x2)

inst_10567:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e01; op2val:0x400;
op3val:0x83ff; valaddr_reg:x3; val_offset:31701*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 31701*FLEN/8, x4, x1, x2)

inst_10568:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e01; op2val:0x400;
op3val:0x400; valaddr_reg:x3; val_offset:31704*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 31704*FLEN/8, x4, x1, x2)

inst_10569:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e01; op2val:0x400;
op3val:0x8400; valaddr_reg:x3; val_offset:31707*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 31707*FLEN/8, x4, x1, x2)

inst_10570:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e01; op2val:0x400;
op3val:0x401; valaddr_reg:x3; val_offset:31710*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 31710*FLEN/8, x4, x1, x2)

inst_10571:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e01; op2val:0x400;
op3val:0x8455; valaddr_reg:x3; val_offset:31713*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 31713*FLEN/8, x4, x1, x2)

inst_10572:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e01; op2val:0x400;
op3val:0x7bff; valaddr_reg:x3; val_offset:31716*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 31716*FLEN/8, x4, x1, x2)

inst_10573:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e01; op2val:0x400;
op3val:0xfbff; valaddr_reg:x3; val_offset:31719*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 31719*FLEN/8, x4, x1, x2)

inst_10574:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e01; op2val:0x400;
op3val:0x7c00; valaddr_reg:x3; val_offset:31722*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 31722*FLEN/8, x4, x1, x2)

inst_10575:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e01; op2val:0x400;
op3val:0xfc00; valaddr_reg:x3; val_offset:31725*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 31725*FLEN/8, x4, x1, x2)

inst_10576:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e01; op2val:0x400;
op3val:0x7e00; valaddr_reg:x3; val_offset:31728*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 31728*FLEN/8, x4, x1, x2)

inst_10577:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e01; op2val:0x400;
op3val:0xfe00; valaddr_reg:x3; val_offset:31731*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 31731*FLEN/8, x4, x1, x2)

inst_10578:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x201 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e01; op2val:0x400;
op3val:0x7e01; valaddr_reg:x3; val_offset:31734*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 31734*FLEN/8, x4, x1, x2)

inst_10579:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x255 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e01; op2val:0x400;
op3val:0xfe55; valaddr_reg:x3; val_offset:31737*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 31737*FLEN/8, x4, x1, x2)

inst_10580:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e01; op2val:0x400;
op3val:0x7c01; valaddr_reg:x3; val_offset:31740*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 31740*FLEN/8, x4, x1, x2)

inst_10581:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x155 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e01; op2val:0x400;
op3val:0xfd55; valaddr_reg:x3; val_offset:31743*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 31743*FLEN/8, x4, x1, x2)

inst_10582:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e01; op2val:0x400;
op3val:0x3c00; valaddr_reg:x3; val_offset:31746*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 31746*FLEN/8, x4, x1, x2)

inst_10583:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e01; op2val:0x400;
op3val:0xbc00; valaddr_reg:x3; val_offset:31749*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 31749*FLEN/8, x4, x1, x2)

inst_10584:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e01; op2val:0x8400;
op3val:0x0; valaddr_reg:x3; val_offset:31752*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 31752*FLEN/8, x4, x1, x2)

inst_10585:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e01; op2val:0x8400;
op3val:0x8000; valaddr_reg:x3; val_offset:31755*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 31755*FLEN/8, x4, x1, x2)

inst_10586:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e01; op2val:0x8400;
op3val:0x1; valaddr_reg:x3; val_offset:31758*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 31758*FLEN/8, x4, x1, x2)

inst_10587:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e01; op2val:0x8400;
op3val:0x8001; valaddr_reg:x3; val_offset:31761*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 31761*FLEN/8, x4, x1, x2)

inst_10588:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x002 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e01; op2val:0x8400;
op3val:0x2; valaddr_reg:x3; val_offset:31764*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 31764*FLEN/8, x4, x1, x2)

inst_10589:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3fe and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e01; op2val:0x8400;
op3val:0x83fe; valaddr_reg:x3; val_offset:31767*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 31767*FLEN/8, x4, x1, x2)

inst_10590:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e01; op2val:0x8400;
op3val:0x3ff; valaddr_reg:x3; val_offset:31770*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 31770*FLEN/8, x4, x1, x2)

inst_10591:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e01; op2val:0x8400;
op3val:0x83ff; valaddr_reg:x3; val_offset:31773*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 31773*FLEN/8, x4, x1, x2)

inst_10592:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e01; op2val:0x8400;
op3val:0x400; valaddr_reg:x3; val_offset:31776*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 31776*FLEN/8, x4, x1, x2)

inst_10593:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e01; op2val:0x8400;
op3val:0x8400; valaddr_reg:x3; val_offset:31779*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 31779*FLEN/8, x4, x1, x2)

inst_10594:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e01; op2val:0x8400;
op3val:0x401; valaddr_reg:x3; val_offset:31782*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 31782*FLEN/8, x4, x1, x2)

inst_10595:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e01; op2val:0x8400;
op3val:0x8455; valaddr_reg:x3; val_offset:31785*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 31785*FLEN/8, x4, x1, x2)

inst_10596:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e01; op2val:0x8400;
op3val:0x7bff; valaddr_reg:x3; val_offset:31788*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 31788*FLEN/8, x4, x1, x2)

inst_10597:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e01; op2val:0x8400;
op3val:0xfbff; valaddr_reg:x3; val_offset:31791*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 31791*FLEN/8, x4, x1, x2)

inst_10598:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e01; op2val:0x8400;
op3val:0x7c00; valaddr_reg:x3; val_offset:31794*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 31794*FLEN/8, x4, x1, x2)

inst_10599:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e01; op2val:0x8400;
op3val:0xfc00; valaddr_reg:x3; val_offset:31797*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 31797*FLEN/8, x4, x1, x2)

inst_10600:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e01; op2val:0x8400;
op3val:0x7e00; valaddr_reg:x3; val_offset:31800*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 31800*FLEN/8, x4, x1, x2)

inst_10601:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e01; op2val:0x8400;
op3val:0xfe00; valaddr_reg:x3; val_offset:31803*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 31803*FLEN/8, x4, x1, x2)

inst_10602:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x201 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e01; op2val:0x8400;
op3val:0x7e01; valaddr_reg:x3; val_offset:31806*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 31806*FLEN/8, x4, x1, x2)

inst_10603:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x255 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e01; op2val:0x8400;
op3val:0xfe55; valaddr_reg:x3; val_offset:31809*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 31809*FLEN/8, x4, x1, x2)

inst_10604:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e01; op2val:0x8400;
op3val:0x7c01; valaddr_reg:x3; val_offset:31812*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 31812*FLEN/8, x4, x1, x2)

inst_10605:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x155 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e01; op2val:0x8400;
op3val:0xfd55; valaddr_reg:x3; val_offset:31815*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 31815*FLEN/8, x4, x1, x2)

inst_10606:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e01; op2val:0x8400;
op3val:0x3c00; valaddr_reg:x3; val_offset:31818*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 31818*FLEN/8, x4, x1, x2)

inst_10607:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e01; op2val:0x8400;
op3val:0xbc00; valaddr_reg:x3; val_offset:31821*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 31821*FLEN/8, x4, x1, x2)

inst_10608:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e01; op2val:0x401;
op3val:0x0; valaddr_reg:x3; val_offset:31824*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 31824*FLEN/8, x4, x1, x2)

inst_10609:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e01; op2val:0x401;
op3val:0x8000; valaddr_reg:x3; val_offset:31827*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 31827*FLEN/8, x4, x1, x2)

inst_10610:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e01; op2val:0x401;
op3val:0x1; valaddr_reg:x3; val_offset:31830*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 31830*FLEN/8, x4, x1, x2)

inst_10611:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e01; op2val:0x401;
op3val:0x8001; valaddr_reg:x3; val_offset:31833*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 31833*FLEN/8, x4, x1, x2)

inst_10612:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x002 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e01; op2val:0x401;
op3val:0x2; valaddr_reg:x3; val_offset:31836*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 31836*FLEN/8, x4, x1, x2)

inst_10613:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3fe and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e01; op2val:0x401;
op3val:0x83fe; valaddr_reg:x3; val_offset:31839*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 31839*FLEN/8, x4, x1, x2)

inst_10614:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e01; op2val:0x401;
op3val:0x3ff; valaddr_reg:x3; val_offset:31842*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 31842*FLEN/8, x4, x1, x2)

inst_10615:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e01; op2val:0x401;
op3val:0x83ff; valaddr_reg:x3; val_offset:31845*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 31845*FLEN/8, x4, x1, x2)

inst_10616:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e01; op2val:0x401;
op3val:0x400; valaddr_reg:x3; val_offset:31848*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 31848*FLEN/8, x4, x1, x2)

inst_10617:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e01; op2val:0x401;
op3val:0x8400; valaddr_reg:x3; val_offset:31851*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 31851*FLEN/8, x4, x1, x2)

inst_10618:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e01; op2val:0x401;
op3val:0x401; valaddr_reg:x3; val_offset:31854*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 31854*FLEN/8, x4, x1, x2)

inst_10619:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e01; op2val:0x401;
op3val:0x8455; valaddr_reg:x3; val_offset:31857*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 31857*FLEN/8, x4, x1, x2)

inst_10620:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e01; op2val:0x401;
op3val:0x7bff; valaddr_reg:x3; val_offset:31860*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 31860*FLEN/8, x4, x1, x2)

inst_10621:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e01; op2val:0x401;
op3val:0xfbff; valaddr_reg:x3; val_offset:31863*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 31863*FLEN/8, x4, x1, x2)

inst_10622:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e01; op2val:0x401;
op3val:0x7c00; valaddr_reg:x3; val_offset:31866*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 31866*FLEN/8, x4, x1, x2)

inst_10623:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e01; op2val:0x401;
op3val:0xfc00; valaddr_reg:x3; val_offset:31869*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 31869*FLEN/8, x4, x1, x2)

RVTEST_SIGBASE(x1,signature_x1_84)
inst_10624:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e01; op2val:0x401;
op3val:0x7e00; valaddr_reg:x3; val_offset:31872*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 31872*FLEN/8, x4, x1, x2)

inst_10625:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e01; op2val:0x401;
op3val:0xfe00; valaddr_reg:x3; val_offset:31875*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 31875*FLEN/8, x4, x1, x2)

inst_10626:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x201 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e01; op2val:0x401;
op3val:0x7e01; valaddr_reg:x3; val_offset:31878*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 31878*FLEN/8, x4, x1, x2)

inst_10627:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x255 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e01; op2val:0x401;
op3val:0xfe55; valaddr_reg:x3; val_offset:31881*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 31881*FLEN/8, x4, x1, x2)

inst_10628:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e01; op2val:0x401;
op3val:0x7c01; valaddr_reg:x3; val_offset:31884*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 31884*FLEN/8, x4, x1, x2)

inst_10629:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x155 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e01; op2val:0x401;
op3val:0xfd55; valaddr_reg:x3; val_offset:31887*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 31887*FLEN/8, x4, x1, x2)

inst_10630:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e01; op2val:0x401;
op3val:0x3c00; valaddr_reg:x3; val_offset:31890*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 31890*FLEN/8, x4, x1, x2)

inst_10631:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e01; op2val:0x401;
op3val:0xbc00; valaddr_reg:x3; val_offset:31893*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 31893*FLEN/8, x4, x1, x2)

inst_10632:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e01; op2val:0x8455;
op3val:0x0; valaddr_reg:x3; val_offset:31896*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 31896*FLEN/8, x4, x1, x2)

inst_10633:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e01; op2val:0x8455;
op3val:0x8000; valaddr_reg:x3; val_offset:31899*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 31899*FLEN/8, x4, x1, x2)

inst_10634:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e01; op2val:0x8455;
op3val:0x1; valaddr_reg:x3; val_offset:31902*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 31902*FLEN/8, x4, x1, x2)

inst_10635:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e01; op2val:0x8455;
op3val:0x8001; valaddr_reg:x3; val_offset:31905*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 31905*FLEN/8, x4, x1, x2)

inst_10636:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x002 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e01; op2val:0x8455;
op3val:0x2; valaddr_reg:x3; val_offset:31908*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 31908*FLEN/8, x4, x1, x2)

inst_10637:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3fe and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e01; op2val:0x8455;
op3val:0x83fe; valaddr_reg:x3; val_offset:31911*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 31911*FLEN/8, x4, x1, x2)

inst_10638:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e01; op2val:0x8455;
op3val:0x3ff; valaddr_reg:x3; val_offset:31914*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 31914*FLEN/8, x4, x1, x2)

inst_10639:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e01; op2val:0x8455;
op3val:0x83ff; valaddr_reg:x3; val_offset:31917*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 31917*FLEN/8, x4, x1, x2)

inst_10640:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e01; op2val:0x8455;
op3val:0x400; valaddr_reg:x3; val_offset:31920*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 31920*FLEN/8, x4, x1, x2)

inst_10641:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e01; op2val:0x8455;
op3val:0x8400; valaddr_reg:x3; val_offset:31923*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 31923*FLEN/8, x4, x1, x2)

inst_10642:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e01; op2val:0x8455;
op3val:0x401; valaddr_reg:x3; val_offset:31926*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 31926*FLEN/8, x4, x1, x2)

inst_10643:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e01; op2val:0x8455;
op3val:0x8455; valaddr_reg:x3; val_offset:31929*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 31929*FLEN/8, x4, x1, x2)

inst_10644:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e01; op2val:0x8455;
op3val:0x7bff; valaddr_reg:x3; val_offset:31932*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 31932*FLEN/8, x4, x1, x2)

inst_10645:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e01; op2val:0x8455;
op3val:0xfbff; valaddr_reg:x3; val_offset:31935*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 31935*FLEN/8, x4, x1, x2)

inst_10646:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e01; op2val:0x8455;
op3val:0x7c00; valaddr_reg:x3; val_offset:31938*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 31938*FLEN/8, x4, x1, x2)

inst_10647:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e01; op2val:0x8455;
op3val:0xfc00; valaddr_reg:x3; val_offset:31941*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 31941*FLEN/8, x4, x1, x2)

inst_10648:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e01; op2val:0x8455;
op3val:0x7e00; valaddr_reg:x3; val_offset:31944*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 31944*FLEN/8, x4, x1, x2)

inst_10649:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e01; op2val:0x8455;
op3val:0xfe00; valaddr_reg:x3; val_offset:31947*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 31947*FLEN/8, x4, x1, x2)

inst_10650:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x201 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e01; op2val:0x8455;
op3val:0x7e01; valaddr_reg:x3; val_offset:31950*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 31950*FLEN/8, x4, x1, x2)

inst_10651:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x255 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e01; op2val:0x8455;
op3val:0xfe55; valaddr_reg:x3; val_offset:31953*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 31953*FLEN/8, x4, x1, x2)

inst_10652:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e01; op2val:0x8455;
op3val:0x7c01; valaddr_reg:x3; val_offset:31956*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 31956*FLEN/8, x4, x1, x2)

inst_10653:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x155 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e01; op2val:0x8455;
op3val:0xfd55; valaddr_reg:x3; val_offset:31959*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 31959*FLEN/8, x4, x1, x2)

inst_10654:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fs3 == 0 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e01; op2val:0x8455;
op3val:0x3c00; valaddr_reg:x3; val_offset:31962*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 31962*FLEN/8, x4, x1, x2)

inst_10655:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fs3 == 1 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e01; op2val:0x8455;
op3val:0xbc00; valaddr_reg:x3; val_offset:31965*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 31965*FLEN/8, x4, x1, x2)

inst_10656:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e01; op2val:0x7bff;
op3val:0x0; valaddr_reg:x3; val_offset:31968*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 31968*FLEN/8, x4, x1, x2)

inst_10657:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e01; op2val:0x7bff;
op3val:0x8000; valaddr_reg:x3; val_offset:31971*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 31971*FLEN/8, x4, x1, x2)

inst_10658:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e01; op2val:0x7bff;
op3val:0x1; valaddr_reg:x3; val_offset:31974*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 31974*FLEN/8, x4, x1, x2)

inst_10659:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e01; op2val:0x7bff;
op3val:0x8001; valaddr_reg:x3; val_offset:31977*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 31977*FLEN/8, x4, x1, x2)

inst_10660:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x002 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e01; op2val:0x7bff;
op3val:0x2; valaddr_reg:x3; val_offset:31980*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 31980*FLEN/8, x4, x1, x2)

inst_10661:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3fe and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e01; op2val:0x7bff;
op3val:0x83fe; valaddr_reg:x3; val_offset:31983*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 31983*FLEN/8, x4, x1, x2)

inst_10662:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e01; op2val:0x7bff;
op3val:0x3ff; valaddr_reg:x3; val_offset:31986*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 31986*FLEN/8, x4, x1, x2)

inst_10663:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e01; op2val:0x7bff;
op3val:0x83ff; valaddr_reg:x3; val_offset:31989*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 31989*FLEN/8, x4, x1, x2)

inst_10664:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e01; op2val:0x7bff;
op3val:0x400; valaddr_reg:x3; val_offset:31992*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 31992*FLEN/8, x4, x1, x2)

inst_10665:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e01; op2val:0x7bff;
op3val:0x8400; valaddr_reg:x3; val_offset:31995*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 31995*FLEN/8, x4, x1, x2)

inst_10666:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x01 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e01; op2val:0x7bff;
op3val:0x401; valaddr_reg:x3; val_offset:31998*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 31998*FLEN/8, x4, x1, x2)

inst_10667:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e01; op2val:0x7bff;
op3val:0x8455; valaddr_reg:x3; val_offset:32001*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 32001*FLEN/8, x4, x1, x2)

inst_10668:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e01; op2val:0x7bff;
op3val:0x7bff; valaddr_reg:x3; val_offset:32004*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 32004*FLEN/8, x4, x1, x2)

inst_10669:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e01; op2val:0x7bff;
op3val:0xfbff; valaddr_reg:x3; val_offset:32007*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 32007*FLEN/8, x4, x1, x2)

inst_10670:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e01; op2val:0x7bff;
op3val:0x7c00; valaddr_reg:x3; val_offset:32010*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 32010*FLEN/8, x4, x1, x2)

inst_10671:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e01; op2val:0x7bff;
op3val:0xfc00; valaddr_reg:x3; val_offset:32013*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 32013*FLEN/8, x4, x1, x2)

inst_10672:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e01; op2val:0x7bff;
op3val:0x7e00; valaddr_reg:x3; val_offset:32016*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 32016*FLEN/8, x4, x1, x2)

inst_10673:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e01; op2val:0x7bff;
op3val:0xfe00; valaddr_reg:x3; val_offset:32019*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 32019*FLEN/8, x4, x1, x2)

inst_10674:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x1f and fm3 == 0x201 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e01; op2val:0x7bff;
op3val:0x7e01; valaddr_reg:x3; val_offset:32022*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 32022*FLEN/8, x4, x1, x2)

inst_10675:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x1f and fm3 == 0x255 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e01; op2val:0x7bff;
op3val:0xfe55; valaddr_reg:x3; val_offset:32025*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 32025*FLEN/8, x4, x1, x2)

inst_10676:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x1f and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e01; op2val:0x7bff;
op3val:0x7c01; valaddr_reg:x3; val_offset:32028*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 32028*FLEN/8, x4, x1, x2)

inst_10677:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x1f and fm3 == 0x155 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e01; op2val:0x7bff;
op3val:0xfd55; valaddr_reg:x3; val_offset:32031*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 32031*FLEN/8, x4, x1, x2)

inst_10678:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e01; op2val:0x7bff;
op3val:0x3c00; valaddr_reg:x3; val_offset:32034*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 32034*FLEN/8, x4, x1, x2)

inst_10679:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e01; op2val:0x7bff;
op3val:0xbc00; valaddr_reg:x3; val_offset:32037*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 32037*FLEN/8, x4, x1, x2)

inst_10680:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e01; op2val:0xfbff;
op3val:0x0; valaddr_reg:x3; val_offset:32040*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 32040*FLEN/8, x4, x1, x2)

inst_10681:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e01; op2val:0xfbff;
op3val:0x8000; valaddr_reg:x3; val_offset:32043*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 32043*FLEN/8, x4, x1, x2)

inst_10682:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e01; op2val:0xfbff;
op3val:0x1; valaddr_reg:x3; val_offset:32046*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 32046*FLEN/8, x4, x1, x2)

inst_10683:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e01; op2val:0xfbff;
op3val:0x8001; valaddr_reg:x3; val_offset:32049*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 32049*FLEN/8, x4, x1, x2)

inst_10684:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x002 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e01; op2val:0xfbff;
op3val:0x2; valaddr_reg:x3; val_offset:32052*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 32052*FLEN/8, x4, x1, x2)

inst_10685:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3fe and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e01; op2val:0xfbff;
op3val:0x83fe; valaddr_reg:x3; val_offset:32055*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 32055*FLEN/8, x4, x1, x2)

inst_10686:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e01; op2val:0xfbff;
op3val:0x3ff; valaddr_reg:x3; val_offset:32058*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 32058*FLEN/8, x4, x1, x2)

inst_10687:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e01; op2val:0xfbff;
op3val:0x83ff; valaddr_reg:x3; val_offset:32061*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 32061*FLEN/8, x4, x1, x2)

inst_10688:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e01; op2val:0xfbff;
op3val:0x400; valaddr_reg:x3; val_offset:32064*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 32064*FLEN/8, x4, x1, x2)

inst_10689:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e01; op2val:0xfbff;
op3val:0x8400; valaddr_reg:x3; val_offset:32067*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 32067*FLEN/8, x4, x1, x2)

inst_10690:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x01 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e01; op2val:0xfbff;
op3val:0x401; valaddr_reg:x3; val_offset:32070*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 32070*FLEN/8, x4, x1, x2)

inst_10691:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e01; op2val:0xfbff;
op3val:0x8455; valaddr_reg:x3; val_offset:32073*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 32073*FLEN/8, x4, x1, x2)

inst_10692:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e01; op2val:0xfbff;
op3val:0x7bff; valaddr_reg:x3; val_offset:32076*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 32076*FLEN/8, x4, x1, x2)

inst_10693:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e01; op2val:0xfbff;
op3val:0xfbff; valaddr_reg:x3; val_offset:32079*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 32079*FLEN/8, x4, x1, x2)

inst_10694:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e01; op2val:0xfbff;
op3val:0x7c00; valaddr_reg:x3; val_offset:32082*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 32082*FLEN/8, x4, x1, x2)

inst_10695:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e01; op2val:0xfbff;
op3val:0xfc00; valaddr_reg:x3; val_offset:32085*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 32085*FLEN/8, x4, x1, x2)

inst_10696:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e01; op2val:0xfbff;
op3val:0x7e00; valaddr_reg:x3; val_offset:32088*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 32088*FLEN/8, x4, x1, x2)

#endif
RVTEST_CODE_END
RVMODEL_HALT
RVTEST_DATA_BEGIN
.align 4
rvtest_data:
.word 0xbabecafe
.word 0xabecafeb
.word 0xbecafeba
.word 0xecafebab
test_dataset_0:
NAN_BOXED(65109,16,FLEN)
NAN_BOXED(65024,16,FLEN)
NAN_BOXED(33791,16,FLEN)
NAN_BOXED(31745,16,FLEN)
NAN_BOXED(65024,16,FLEN)
NAN_BOXED(33791,16,FLEN)
NAN_BOXED(64853,16,FLEN)
NAN_BOXED(65024,16,FLEN)
NAN_BOXED(33791,16,FLEN)
NAN_BOXED(15360,16,FLEN)
NAN_BOXED(65024,16,FLEN)
NAN_BOXED(33791,16,FLEN)
NAN_BOXED(48128,16,FLEN)
NAN_BOXED(65024,16,FLEN)
NAN_BOXED(1024,16,FLEN)
NAN_BOXED(0,16,FLEN)
NAN_BOXED(65024,16,FLEN)
NAN_BOXED(1024,16,FLEN)
NAN_BOXED(32768,16,FLEN)
NAN_BOXED(65024,16,FLEN)
NAN_BOXED(1024,16,FLEN)
NAN_BOXED(1,16,FLEN)
NAN_BOXED(65024,16,FLEN)
NAN_BOXED(1024,16,FLEN)
NAN_BOXED(32769,16,FLEN)
NAN_BOXED(65024,16,FLEN)
NAN_BOXED(1024,16,FLEN)
NAN_BOXED(2,16,FLEN)
NAN_BOXED(65024,16,FLEN)
NAN_BOXED(1024,16,FLEN)
NAN_BOXED(33790,16,FLEN)
NAN_BOXED(65024,16,FLEN)
NAN_BOXED(1024,16,FLEN)
NAN_BOXED(1023,16,FLEN)
NAN_BOXED(65024,16,FLEN)
NAN_BOXED(1024,16,FLEN)
NAN_BOXED(33791,16,FLEN)
NAN_BOXED(65024,16,FLEN)
NAN_BOXED(1024,16,FLEN)
NAN_BOXED(1024,16,FLEN)
NAN_BOXED(65024,16,FLEN)
NAN_BOXED(1024,16,FLEN)
NAN_BOXED(33792,16,FLEN)
NAN_BOXED(65024,16,FLEN)
NAN_BOXED(1024,16,FLEN)
NAN_BOXED(1025,16,FLEN)
NAN_BOXED(65024,16,FLEN)
NAN_BOXED(1024,16,FLEN)
NAN_BOXED(33877,16,FLEN)
NAN_BOXED(65024,16,FLEN)
NAN_BOXED(1024,16,FLEN)
NAN_BOXED(31743,16,FLEN)
NAN_BOXED(65024,16,FLEN)
NAN_BOXED(1024,16,FLEN)
NAN_BOXED(64511,16,FLEN)
NAN_BOXED(65024,16,FLEN)
NAN_BOXED(1024,16,FLEN)
NAN_BOXED(31744,16,FLEN)
NAN_BOXED(65024,16,FLEN)
NAN_BOXED(1024,16,FLEN)
NAN_BOXED(64512,16,FLEN)
NAN_BOXED(65024,16,FLEN)
NAN_BOXED(1024,16,FLEN)
NAN_BOXED(32256,16,FLEN)
NAN_BOXED(65024,16,FLEN)
NAN_BOXED(1024,16,FLEN)
NAN_BOXED(65024,16,FLEN)
NAN_BOXED(65024,16,FLEN)
NAN_BOXED(1024,16,FLEN)
NAN_BOXED(32257,16,FLEN)
NAN_BOXED(65024,16,FLEN)
NAN_BOXED(1024,16,FLEN)
NAN_BOXED(65109,16,FLEN)
NAN_BOXED(65024,16,FLEN)
NAN_BOXED(1024,16,FLEN)
NAN_BOXED(31745,16,FLEN)
NAN_BOXED(65024,16,FLEN)
NAN_BOXED(1024,16,FLEN)
NAN_BOXED(64853,16,FLEN)
NAN_BOXED(65024,16,FLEN)
NAN_BOXED(1024,16,FLEN)
NAN_BOXED(15360,16,FLEN)
NAN_BOXED(65024,16,FLEN)
NAN_BOXED(1024,16,FLEN)
NAN_BOXED(48128,16,FLEN)
NAN_BOXED(65024,16,FLEN)
NAN_BOXED(33792,16,FLEN)
NAN_BOXED(0,16,FLEN)
NAN_BOXED(65024,16,FLEN)
NAN_BOXED(33792,16,FLEN)
NAN_BOXED(32768,16,FLEN)
NAN_BOXED(65024,16,FLEN)
NAN_BOXED(33792,16,FLEN)
NAN_BOXED(1,16,FLEN)
NAN_BOXED(65024,16,FLEN)
NAN_BOXED(33792,16,FLEN)
NAN_BOXED(32769,16,FLEN)
NAN_BOXED(65024,16,FLEN)
NAN_BOXED(33792,16,FLEN)
NAN_BOXED(2,16,FLEN)
NAN_BOXED(65024,16,FLEN)
NAN_BOXED(33792,16,FLEN)
NAN_BOXED(33790,16,FLEN)
NAN_BOXED(65024,16,FLEN)
NAN_BOXED(33792,16,FLEN)
NAN_BOXED(1023,16,FLEN)
NAN_BOXED(65024,16,FLEN)
NAN_BOXED(33792,16,FLEN)
NAN_BOXED(33791,16,FLEN)
NAN_BOXED(65024,16,FLEN)
NAN_BOXED(33792,16,FLEN)
NAN_BOXED(1024,16,FLEN)
NAN_BOXED(65024,16,FLEN)
NAN_BOXED(33792,16,FLEN)
NAN_BOXED(33792,16,FLEN)
NAN_BOXED(65024,16,FLEN)
NAN_BOXED(33792,16,FLEN)
NAN_BOXED(1025,16,FLEN)
NAN_BOXED(65024,16,FLEN)
NAN_BOXED(33792,16,FLEN)
NAN_BOXED(33877,16,FLEN)
NAN_BOXED(65024,16,FLEN)
NAN_BOXED(33792,16,FLEN)
NAN_BOXED(31743,16,FLEN)
NAN_BOXED(65024,16,FLEN)
NAN_BOXED(33792,16,FLEN)
NAN_BOXED(64511,16,FLEN)
NAN_BOXED(65024,16,FLEN)
NAN_BOXED(33792,16,FLEN)
NAN_BOXED(31744,16,FLEN)
NAN_BOXED(65024,16,FLEN)
NAN_BOXED(33792,16,FLEN)
NAN_BOXED(64512,16,FLEN)
NAN_BOXED(65024,16,FLEN)
NAN_BOXED(33792,16,FLEN)
NAN_BOXED(32256,16,FLEN)
NAN_BOXED(65024,16,FLEN)
NAN_BOXED(33792,16,FLEN)
NAN_BOXED(65024,16,FLEN)
NAN_BOXED(65024,16,FLEN)
NAN_BOXED(33792,16,FLEN)
NAN_BOXED(32257,16,FLEN)
NAN_BOXED(65024,16,FLEN)
NAN_BOXED(33792,16,FLEN)
NAN_BOXED(65109,16,FLEN)
NAN_BOXED(65024,16,FLEN)
NAN_BOXED(33792,16,FLEN)
NAN_BOXED(31745,16,FLEN)
NAN_BOXED(65024,16,FLEN)
NAN_BOXED(33792,16,FLEN)
NAN_BOXED(64853,16,FLEN)
NAN_BOXED(65024,16,FLEN)
NAN_BOXED(33792,16,FLEN)
NAN_BOXED(15360,16,FLEN)
NAN_BOXED(65024,16,FLEN)
NAN_BOXED(33792,16,FLEN)
NAN_BOXED(48128,16,FLEN)
NAN_BOXED(65024,16,FLEN)
NAN_BOXED(1025,16,FLEN)
NAN_BOXED(0,16,FLEN)
NAN_BOXED(65024,16,FLEN)
NAN_BOXED(1025,16,FLEN)
NAN_BOXED(32768,16,FLEN)
NAN_BOXED(65024,16,FLEN)
NAN_BOXED(1025,16,FLEN)
NAN_BOXED(1,16,FLEN)
NAN_BOXED(65024,16,FLEN)
NAN_BOXED(1025,16,FLEN)
NAN_BOXED(32769,16,FLEN)
NAN_BOXED(65024,16,FLEN)
NAN_BOXED(1025,16,FLEN)
NAN_BOXED(2,16,FLEN)
NAN_BOXED(65024,16,FLEN)
NAN_BOXED(1025,16,FLEN)
NAN_BOXED(33790,16,FLEN)
NAN_BOXED(65024,16,FLEN)
NAN_BOXED(1025,16,FLEN)
NAN_BOXED(1023,16,FLEN)
NAN_BOXED(65024,16,FLEN)
NAN_BOXED(1025,16,FLEN)
NAN_BOXED(33791,16,FLEN)
NAN_BOXED(65024,16,FLEN)
NAN_BOXED(1025,16,FLEN)
NAN_BOXED(1024,16,FLEN)
NAN_BOXED(65024,16,FLEN)
NAN_BOXED(1025,16,FLEN)
NAN_BOXED(33792,16,FLEN)
NAN_BOXED(65024,16,FLEN)
NAN_BOXED(1025,16,FLEN)
NAN_BOXED(1025,16,FLEN)
NAN_BOXED(65024,16,FLEN)
NAN_BOXED(1025,16,FLEN)
NAN_BOXED(33877,16,FLEN)
NAN_BOXED(65024,16,FLEN)
NAN_BOXED(1025,16,FLEN)
NAN_BOXED(31743,16,FLEN)
NAN_BOXED(65024,16,FLEN)
NAN_BOXED(1025,16,FLEN)
NAN_BOXED(64511,16,FLEN)
NAN_BOXED(65024,16,FLEN)
NAN_BOXED(1025,16,FLEN)
NAN_BOXED(31744,16,FLEN)
NAN_BOXED(65024,16,FLEN)
NAN_BOXED(1025,16,FLEN)
NAN_BOXED(64512,16,FLEN)
NAN_BOXED(65024,16,FLEN)
NAN_BOXED(1025,16,FLEN)
NAN_BOXED(32256,16,FLEN)
NAN_BOXED(65024,16,FLEN)
NAN_BOXED(1025,16,FLEN)
NAN_BOXED(65024,16,FLEN)
NAN_BOXED(65024,16,FLEN)
NAN_BOXED(1025,16,FLEN)
NAN_BOXED(32257,16,FLEN)
NAN_BOXED(65024,16,FLEN)
NAN_BOXED(1025,16,FLEN)
NAN_BOXED(65109,16,FLEN)
NAN_BOXED(65024,16,FLEN)
NAN_BOXED(1025,16,FLEN)
NAN_BOXED(31745,16,FLEN)
NAN_BOXED(65024,16,FLEN)
NAN_BOXED(1025,16,FLEN)
NAN_BOXED(64853,16,FLEN)
NAN_BOXED(65024,16,FLEN)
NAN_BOXED(1025,16,FLEN)
NAN_BOXED(15360,16,FLEN)
NAN_BOXED(65024,16,FLEN)
NAN_BOXED(1025,16,FLEN)
NAN_BOXED(48128,16,FLEN)
NAN_BOXED(65024,16,FLEN)
NAN_BOXED(33877,16,FLEN)
NAN_BOXED(0,16,FLEN)
NAN_BOXED(65024,16,FLEN)
NAN_BOXED(33877,16,FLEN)
NAN_BOXED(32768,16,FLEN)
NAN_BOXED(65024,16,FLEN)
NAN_BOXED(33877,16,FLEN)
NAN_BOXED(1,16,FLEN)
NAN_BOXED(65024,16,FLEN)
NAN_BOXED(33877,16,FLEN)
NAN_BOXED(32769,16,FLEN)
NAN_BOXED(65024,16,FLEN)
NAN_BOXED(33877,16,FLEN)
NAN_BOXED(2,16,FLEN)
NAN_BOXED(65024,16,FLEN)
NAN_BOXED(33877,16,FLEN)
NAN_BOXED(33790,16,FLEN)
NAN_BOXED(65024,16,FLEN)
NAN_BOXED(33877,16,FLEN)
NAN_BOXED(1023,16,FLEN)
NAN_BOXED(65024,16,FLEN)
NAN_BOXED(33877,16,FLEN)
NAN_BOXED(33791,16,FLEN)
NAN_BOXED(65024,16,FLEN)
NAN_BOXED(33877,16,FLEN)
NAN_BOXED(1024,16,FLEN)
NAN_BOXED(65024,16,FLEN)
NAN_BOXED(33877,16,FLEN)
NAN_BOXED(33792,16,FLEN)
NAN_BOXED(65024,16,FLEN)
NAN_BOXED(33877,16,FLEN)
NAN_BOXED(1025,16,FLEN)
NAN_BOXED(65024,16,FLEN)
NAN_BOXED(33877,16,FLEN)
NAN_BOXED(33877,16,FLEN)
NAN_BOXED(65024,16,FLEN)
NAN_BOXED(33877,16,FLEN)
NAN_BOXED(31743,16,FLEN)
NAN_BOXED(65024,16,FLEN)
NAN_BOXED(33877,16,FLEN)
NAN_BOXED(64511,16,FLEN)
NAN_BOXED(65024,16,FLEN)
NAN_BOXED(33877,16,FLEN)
NAN_BOXED(31744,16,FLEN)
NAN_BOXED(65024,16,FLEN)
NAN_BOXED(33877,16,FLEN)
NAN_BOXED(64512,16,FLEN)
NAN_BOXED(65024,16,FLEN)
NAN_BOXED(33877,16,FLEN)
NAN_BOXED(32256,16,FLEN)
NAN_BOXED(65024,16,FLEN)
NAN_BOXED(33877,16,FLEN)
NAN_BOXED(65024,16,FLEN)
NAN_BOXED(65024,16,FLEN)
NAN_BOXED(33877,16,FLEN)
NAN_BOXED(32257,16,FLEN)
NAN_BOXED(65024,16,FLEN)
NAN_BOXED(33877,16,FLEN)
NAN_BOXED(65109,16,FLEN)
NAN_BOXED(65024,16,FLEN)
NAN_BOXED(33877,16,FLEN)
NAN_BOXED(31745,16,FLEN)
NAN_BOXED(65024,16,FLEN)
NAN_BOXED(33877,16,FLEN)
NAN_BOXED(64853,16,FLEN)
NAN_BOXED(65024,16,FLEN)
NAN_BOXED(33877,16,FLEN)
NAN_BOXED(15360,16,FLEN)
NAN_BOXED(65024,16,FLEN)
NAN_BOXED(33877,16,FLEN)
NAN_BOXED(48128,16,FLEN)
NAN_BOXED(65024,16,FLEN)
NAN_BOXED(31743,16,FLEN)
NAN_BOXED(0,16,FLEN)
NAN_BOXED(65024,16,FLEN)
NAN_BOXED(31743,16,FLEN)
NAN_BOXED(32768,16,FLEN)
NAN_BOXED(65024,16,FLEN)
NAN_BOXED(31743,16,FLEN)
NAN_BOXED(1,16,FLEN)
NAN_BOXED(65024,16,FLEN)
NAN_BOXED(31743,16,FLEN)
NAN_BOXED(32769,16,FLEN)
NAN_BOXED(65024,16,FLEN)
NAN_BOXED(31743,16,FLEN)
NAN_BOXED(2,16,FLEN)
NAN_BOXED(65024,16,FLEN)
NAN_BOXED(31743,16,FLEN)
NAN_BOXED(33790,16,FLEN)
NAN_BOXED(65024,16,FLEN)
NAN_BOXED(31743,16,FLEN)
NAN_BOXED(1023,16,FLEN)
NAN_BOXED(65024,16,FLEN)
NAN_BOXED(31743,16,FLEN)
NAN_BOXED(33791,16,FLEN)
NAN_BOXED(65024,16,FLEN)
NAN_BOXED(31743,16,FLEN)
NAN_BOXED(1024,16,FLEN)
NAN_BOXED(65024,16,FLEN)
NAN_BOXED(31743,16,FLEN)
NAN_BOXED(33792,16,FLEN)
NAN_BOXED(65024,16,FLEN)
NAN_BOXED(31743,16,FLEN)
NAN_BOXED(1025,16,FLEN)
NAN_BOXED(65024,16,FLEN)
NAN_BOXED(31743,16,FLEN)
NAN_BOXED(33877,16,FLEN)
NAN_BOXED(65024,16,FLEN)
NAN_BOXED(31743,16,FLEN)
NAN_BOXED(31743,16,FLEN)
NAN_BOXED(65024,16,FLEN)
NAN_BOXED(31743,16,FLEN)
NAN_BOXED(64511,16,FLEN)
NAN_BOXED(65024,16,FLEN)
NAN_BOXED(31743,16,FLEN)
NAN_BOXED(31744,16,FLEN)
NAN_BOXED(65024,16,FLEN)
NAN_BOXED(31743,16,FLEN)
NAN_BOXED(64512,16,FLEN)
NAN_BOXED(65024,16,FLEN)
NAN_BOXED(31743,16,FLEN)
NAN_BOXED(32256,16,FLEN)
NAN_BOXED(65024,16,FLEN)
NAN_BOXED(31743,16,FLEN)
NAN_BOXED(65024,16,FLEN)
NAN_BOXED(65024,16,FLEN)
NAN_BOXED(31743,16,FLEN)
NAN_BOXED(32257,16,FLEN)
NAN_BOXED(65024,16,FLEN)
NAN_BOXED(31743,16,FLEN)
NAN_BOXED(65109,16,FLEN)
NAN_BOXED(65024,16,FLEN)
NAN_BOXED(31743,16,FLEN)
NAN_BOXED(31745,16,FLEN)
NAN_BOXED(65024,16,FLEN)
NAN_BOXED(31743,16,FLEN)
NAN_BOXED(64853,16,FLEN)
NAN_BOXED(65024,16,FLEN)
NAN_BOXED(31743,16,FLEN)
NAN_BOXED(15360,16,FLEN)
NAN_BOXED(65024,16,FLEN)
NAN_BOXED(31743,16,FLEN)
NAN_BOXED(48128,16,FLEN)
NAN_BOXED(65024,16,FLEN)
NAN_BOXED(64511,16,FLEN)
NAN_BOXED(0,16,FLEN)
NAN_BOXED(65024,16,FLEN)
NAN_BOXED(64511,16,FLEN)
NAN_BOXED(32768,16,FLEN)
NAN_BOXED(65024,16,FLEN)
NAN_BOXED(64511,16,FLEN)
NAN_BOXED(1,16,FLEN)
NAN_BOXED(65024,16,FLEN)
NAN_BOXED(64511,16,FLEN)
NAN_BOXED(32769,16,FLEN)
NAN_BOXED(65024,16,FLEN)
NAN_BOXED(64511,16,FLEN)
NAN_BOXED(2,16,FLEN)
NAN_BOXED(65024,16,FLEN)
NAN_BOXED(64511,16,FLEN)
NAN_BOXED(33790,16,FLEN)
NAN_BOXED(65024,16,FLEN)
NAN_BOXED(64511,16,FLEN)
NAN_BOXED(1023,16,FLEN)
NAN_BOXED(65024,16,FLEN)
NAN_BOXED(64511,16,FLEN)
NAN_BOXED(33791,16,FLEN)
NAN_BOXED(65024,16,FLEN)
NAN_BOXED(64511,16,FLEN)
NAN_BOXED(1024,16,FLEN)
NAN_BOXED(65024,16,FLEN)
NAN_BOXED(64511,16,FLEN)
NAN_BOXED(33792,16,FLEN)
NAN_BOXED(65024,16,FLEN)
NAN_BOXED(64511,16,FLEN)
NAN_BOXED(1025,16,FLEN)
NAN_BOXED(65024,16,FLEN)
NAN_BOXED(64511,16,FLEN)
NAN_BOXED(33877,16,FLEN)
NAN_BOXED(65024,16,FLEN)
NAN_BOXED(64511,16,FLEN)
NAN_BOXED(31743,16,FLEN)
NAN_BOXED(65024,16,FLEN)
NAN_BOXED(64511,16,FLEN)
NAN_BOXED(64511,16,FLEN)
NAN_BOXED(65024,16,FLEN)
NAN_BOXED(64511,16,FLEN)
NAN_BOXED(31744,16,FLEN)
NAN_BOXED(65024,16,FLEN)
NAN_BOXED(64511,16,FLEN)
NAN_BOXED(64512,16,FLEN)
NAN_BOXED(65024,16,FLEN)
NAN_BOXED(64511,16,FLEN)
NAN_BOXED(32256,16,FLEN)
NAN_BOXED(65024,16,FLEN)
NAN_BOXED(64511,16,FLEN)
NAN_BOXED(65024,16,FLEN)
NAN_BOXED(65024,16,FLEN)
NAN_BOXED(64511,16,FLEN)
NAN_BOXED(32257,16,FLEN)
NAN_BOXED(65024,16,FLEN)
NAN_BOXED(64511,16,FLEN)
NAN_BOXED(65109,16,FLEN)
NAN_BOXED(65024,16,FLEN)
NAN_BOXED(64511,16,FLEN)
NAN_BOXED(31745,16,FLEN)
NAN_BOXED(65024,16,FLEN)
NAN_BOXED(64511,16,FLEN)
NAN_BOXED(64853,16,FLEN)
NAN_BOXED(65024,16,FLEN)
NAN_BOXED(64511,16,FLEN)
NAN_BOXED(15360,16,FLEN)
NAN_BOXED(65024,16,FLEN)
NAN_BOXED(64511,16,FLEN)
NAN_BOXED(48128,16,FLEN)
NAN_BOXED(65024,16,FLEN)
NAN_BOXED(31744,16,FLEN)
NAN_BOXED(0,16,FLEN)
NAN_BOXED(65024,16,FLEN)
NAN_BOXED(31744,16,FLEN)
NAN_BOXED(32768,16,FLEN)
NAN_BOXED(65024,16,FLEN)
NAN_BOXED(31744,16,FLEN)
NAN_BOXED(1,16,FLEN)
NAN_BOXED(65024,16,FLEN)
NAN_BOXED(31744,16,FLEN)
NAN_BOXED(32769,16,FLEN)
NAN_BOXED(65024,16,FLEN)
NAN_BOXED(31744,16,FLEN)
NAN_BOXED(2,16,FLEN)
NAN_BOXED(65024,16,FLEN)
NAN_BOXED(31744,16,FLEN)
NAN_BOXED(33790,16,FLEN)
NAN_BOXED(65024,16,FLEN)
NAN_BOXED(31744,16,FLEN)
NAN_BOXED(1023,16,FLEN)
NAN_BOXED(65024,16,FLEN)
NAN_BOXED(31744,16,FLEN)
NAN_BOXED(33791,16,FLEN)
NAN_BOXED(65024,16,FLEN)
NAN_BOXED(31744,16,FLEN)
NAN_BOXED(1024,16,FLEN)
NAN_BOXED(65024,16,FLEN)
NAN_BOXED(31744,16,FLEN)
NAN_BOXED(33792,16,FLEN)
NAN_BOXED(65024,16,FLEN)
NAN_BOXED(31744,16,FLEN)
NAN_BOXED(1025,16,FLEN)
NAN_BOXED(65024,16,FLEN)
NAN_BOXED(31744,16,FLEN)
NAN_BOXED(33877,16,FLEN)
NAN_BOXED(65024,16,FLEN)
NAN_BOXED(31744,16,FLEN)
NAN_BOXED(31743,16,FLEN)
NAN_BOXED(65024,16,FLEN)
NAN_BOXED(31744,16,FLEN)
NAN_BOXED(64511,16,FLEN)
NAN_BOXED(65024,16,FLEN)
NAN_BOXED(31744,16,FLEN)
NAN_BOXED(31744,16,FLEN)
NAN_BOXED(65024,16,FLEN)
NAN_BOXED(31744,16,FLEN)
NAN_BOXED(64512,16,FLEN)
NAN_BOXED(65024,16,FLEN)
NAN_BOXED(31744,16,FLEN)
NAN_BOXED(32256,16,FLEN)
NAN_BOXED(65024,16,FLEN)
NAN_BOXED(31744,16,FLEN)
NAN_BOXED(65024,16,FLEN)
NAN_BOXED(65024,16,FLEN)
NAN_BOXED(31744,16,FLEN)
NAN_BOXED(32257,16,FLEN)
NAN_BOXED(65024,16,FLEN)
NAN_BOXED(31744,16,FLEN)
NAN_BOXED(65109,16,FLEN)
NAN_BOXED(65024,16,FLEN)
NAN_BOXED(31744,16,FLEN)
NAN_BOXED(31745,16,FLEN)
NAN_BOXED(65024,16,FLEN)
NAN_BOXED(31744,16,FLEN)
NAN_BOXED(64853,16,FLEN)
NAN_BOXED(65024,16,FLEN)
NAN_BOXED(31744,16,FLEN)
NAN_BOXED(15360,16,FLEN)
NAN_BOXED(65024,16,FLEN)
NAN_BOXED(31744,16,FLEN)
NAN_BOXED(48128,16,FLEN)
NAN_BOXED(65024,16,FLEN)
NAN_BOXED(64512,16,FLEN)
NAN_BOXED(0,16,FLEN)
NAN_BOXED(65024,16,FLEN)
NAN_BOXED(64512,16,FLEN)
NAN_BOXED(32768,16,FLEN)
NAN_BOXED(65024,16,FLEN)
NAN_BOXED(64512,16,FLEN)
NAN_BOXED(1,16,FLEN)
NAN_BOXED(65024,16,FLEN)
NAN_BOXED(64512,16,FLEN)
NAN_BOXED(32769,16,FLEN)
NAN_BOXED(65024,16,FLEN)
NAN_BOXED(64512,16,FLEN)
NAN_BOXED(2,16,FLEN)
NAN_BOXED(65024,16,FLEN)
NAN_BOXED(64512,16,FLEN)
NAN_BOXED(33790,16,FLEN)
NAN_BOXED(65024,16,FLEN)
NAN_BOXED(64512,16,FLEN)
NAN_BOXED(1023,16,FLEN)
NAN_BOXED(65024,16,FLEN)
NAN_BOXED(64512,16,FLEN)
NAN_BOXED(33791,16,FLEN)
NAN_BOXED(65024,16,FLEN)
NAN_BOXED(64512,16,FLEN)
NAN_BOXED(1024,16,FLEN)
NAN_BOXED(65024,16,FLEN)
NAN_BOXED(64512,16,FLEN)
NAN_BOXED(33792,16,FLEN)
NAN_BOXED(65024,16,FLEN)
NAN_BOXED(64512,16,FLEN)
NAN_BOXED(1025,16,FLEN)
NAN_BOXED(65024,16,FLEN)
NAN_BOXED(64512,16,FLEN)
NAN_BOXED(33877,16,FLEN)
NAN_BOXED(65024,16,FLEN)
NAN_BOXED(64512,16,FLEN)
NAN_BOXED(31743,16,FLEN)
NAN_BOXED(65024,16,FLEN)
NAN_BOXED(64512,16,FLEN)
NAN_BOXED(64511,16,FLEN)
NAN_BOXED(65024,16,FLEN)
NAN_BOXED(64512,16,FLEN)
NAN_BOXED(31744,16,FLEN)
NAN_BOXED(65024,16,FLEN)
NAN_BOXED(64512,16,FLEN)
NAN_BOXED(64512,16,FLEN)
NAN_BOXED(65024,16,FLEN)
NAN_BOXED(64512,16,FLEN)
NAN_BOXED(32256,16,FLEN)
NAN_BOXED(65024,16,FLEN)
NAN_BOXED(64512,16,FLEN)
NAN_BOXED(65024,16,FLEN)
NAN_BOXED(65024,16,FLEN)
NAN_BOXED(64512,16,FLEN)
NAN_BOXED(32257,16,FLEN)
NAN_BOXED(65024,16,FLEN)
NAN_BOXED(64512,16,FLEN)
NAN_BOXED(65109,16,FLEN)
NAN_BOXED(65024,16,FLEN)
NAN_BOXED(64512,16,FLEN)
NAN_BOXED(31745,16,FLEN)
NAN_BOXED(65024,16,FLEN)
NAN_BOXED(64512,16,FLEN)
NAN_BOXED(64853,16,FLEN)
NAN_BOXED(65024,16,FLEN)
NAN_BOXED(64512,16,FLEN)
NAN_BOXED(15360,16,FLEN)
NAN_BOXED(65024,16,FLEN)
NAN_BOXED(64512,16,FLEN)
NAN_BOXED(48128,16,FLEN)
NAN_BOXED(65024,16,FLEN)
NAN_BOXED(32256,16,FLEN)
NAN_BOXED(0,16,FLEN)
NAN_BOXED(65024,16,FLEN)
NAN_BOXED(32256,16,FLEN)
NAN_BOXED(32768,16,FLEN)
NAN_BOXED(65024,16,FLEN)
NAN_BOXED(32256,16,FLEN)
NAN_BOXED(1,16,FLEN)
NAN_BOXED(65024,16,FLEN)
NAN_BOXED(32256,16,FLEN)
NAN_BOXED(32769,16,FLEN)
NAN_BOXED(65024,16,FLEN)
NAN_BOXED(32256,16,FLEN)
NAN_BOXED(2,16,FLEN)
NAN_BOXED(65024,16,FLEN)
NAN_BOXED(32256,16,FLEN)
NAN_BOXED(33790,16,FLEN)
NAN_BOXED(65024,16,FLEN)
NAN_BOXED(32256,16,FLEN)
NAN_BOXED(1023,16,FLEN)
NAN_BOXED(65024,16,FLEN)
NAN_BOXED(32256,16,FLEN)
NAN_BOXED(33791,16,FLEN)
NAN_BOXED(65024,16,FLEN)
NAN_BOXED(32256,16,FLEN)
NAN_BOXED(1024,16,FLEN)
NAN_BOXED(65024,16,FLEN)
NAN_BOXED(32256,16,FLEN)
NAN_BOXED(33792,16,FLEN)
NAN_BOXED(65024,16,FLEN)
NAN_BOXED(32256,16,FLEN)
NAN_BOXED(1025,16,FLEN)
NAN_BOXED(65024,16,FLEN)
NAN_BOXED(32256,16,FLEN)
NAN_BOXED(33877,16,FLEN)
NAN_BOXED(65024,16,FLEN)
NAN_BOXED(32256,16,FLEN)
NAN_BOXED(31743,16,FLEN)
NAN_BOXED(65024,16,FLEN)
NAN_BOXED(32256,16,FLEN)
NAN_BOXED(64511,16,FLEN)
NAN_BOXED(65024,16,FLEN)
NAN_BOXED(32256,16,FLEN)
NAN_BOXED(31744,16,FLEN)
NAN_BOXED(65024,16,FLEN)
NAN_BOXED(32256,16,FLEN)
NAN_BOXED(64512,16,FLEN)
NAN_BOXED(65024,16,FLEN)
NAN_BOXED(32256,16,FLEN)
NAN_BOXED(32256,16,FLEN)
NAN_BOXED(65024,16,FLEN)
NAN_BOXED(32256,16,FLEN)
NAN_BOXED(65024,16,FLEN)
NAN_BOXED(65024,16,FLEN)
NAN_BOXED(32256,16,FLEN)
NAN_BOXED(32257,16,FLEN)
NAN_BOXED(65024,16,FLEN)
NAN_BOXED(32256,16,FLEN)
NAN_BOXED(65109,16,FLEN)
NAN_BOXED(65024,16,FLEN)
NAN_BOXED(32256,16,FLEN)
NAN_BOXED(31745,16,FLEN)
NAN_BOXED(65024,16,FLEN)
NAN_BOXED(32256,16,FLEN)
NAN_BOXED(64853,16,FLEN)
NAN_BOXED(65024,16,FLEN)
NAN_BOXED(32256,16,FLEN)
NAN_BOXED(15360,16,FLEN)
NAN_BOXED(65024,16,FLEN)
NAN_BOXED(32256,16,FLEN)
NAN_BOXED(48128,16,FLEN)
NAN_BOXED(65024,16,FLEN)
NAN_BOXED(65024,16,FLEN)
NAN_BOXED(0,16,FLEN)
NAN_BOXED(65024,16,FLEN)
NAN_BOXED(65024,16,FLEN)
NAN_BOXED(32768,16,FLEN)
NAN_BOXED(65024,16,FLEN)
NAN_BOXED(65024,16,FLEN)
NAN_BOXED(1,16,FLEN)
NAN_BOXED(65024,16,FLEN)
NAN_BOXED(65024,16,FLEN)
NAN_BOXED(32769,16,FLEN)
NAN_BOXED(65024,16,FLEN)
NAN_BOXED(65024,16,FLEN)
NAN_BOXED(2,16,FLEN)
NAN_BOXED(65024,16,FLEN)
NAN_BOXED(65024,16,FLEN)
NAN_BOXED(33790,16,FLEN)
NAN_BOXED(65024,16,FLEN)
NAN_BOXED(65024,16,FLEN)
NAN_BOXED(1023,16,FLEN)
NAN_BOXED(65024,16,FLEN)
NAN_BOXED(65024,16,FLEN)
NAN_BOXED(33791,16,FLEN)
NAN_BOXED(65024,16,FLEN)
NAN_BOXED(65024,16,FLEN)
NAN_BOXED(1024,16,FLEN)
NAN_BOXED(65024,16,FLEN)
NAN_BOXED(65024,16,FLEN)
NAN_BOXED(33792,16,FLEN)
NAN_BOXED(65024,16,FLEN)
NAN_BOXED(65024,16,FLEN)
NAN_BOXED(1025,16,FLEN)
NAN_BOXED(65024,16,FLEN)
NAN_BOXED(65024,16,FLEN)
NAN_BOXED(33877,16,FLEN)
NAN_BOXED(65024,16,FLEN)
NAN_BOXED(65024,16,FLEN)
NAN_BOXED(31743,16,FLEN)
NAN_BOXED(65024,16,FLEN)
NAN_BOXED(65024,16,FLEN)
NAN_BOXED(64511,16,FLEN)
NAN_BOXED(65024,16,FLEN)
NAN_BOXED(65024,16,FLEN)
NAN_BOXED(31744,16,FLEN)
NAN_BOXED(65024,16,FLEN)
NAN_BOXED(65024,16,FLEN)
NAN_BOXED(64512,16,FLEN)
NAN_BOXED(65024,16,FLEN)
NAN_BOXED(65024,16,FLEN)
NAN_BOXED(32256,16,FLEN)
NAN_BOXED(65024,16,FLEN)
NAN_BOXED(65024,16,FLEN)
NAN_BOXED(65024,16,FLEN)
NAN_BOXED(65024,16,FLEN)
NAN_BOXED(65024,16,FLEN)
NAN_BOXED(32257,16,FLEN)
NAN_BOXED(65024,16,FLEN)
NAN_BOXED(65024,16,FLEN)
NAN_BOXED(65109,16,FLEN)
NAN_BOXED(65024,16,FLEN)
NAN_BOXED(65024,16,FLEN)
NAN_BOXED(31745,16,FLEN)
NAN_BOXED(65024,16,FLEN)
NAN_BOXED(65024,16,FLEN)
NAN_BOXED(64853,16,FLEN)
NAN_BOXED(65024,16,FLEN)
NAN_BOXED(65024,16,FLEN)
NAN_BOXED(15360,16,FLEN)
NAN_BOXED(65024,16,FLEN)
NAN_BOXED(65024,16,FLEN)
NAN_BOXED(48128,16,FLEN)
NAN_BOXED(65024,16,FLEN)
NAN_BOXED(32257,16,FLEN)
NAN_BOXED(0,16,FLEN)
NAN_BOXED(65024,16,FLEN)
NAN_BOXED(32257,16,FLEN)
NAN_BOXED(32768,16,FLEN)
NAN_BOXED(65024,16,FLEN)
NAN_BOXED(32257,16,FLEN)
NAN_BOXED(1,16,FLEN)
NAN_BOXED(65024,16,FLEN)
NAN_BOXED(32257,16,FLEN)
NAN_BOXED(32769,16,FLEN)
NAN_BOXED(65024,16,FLEN)
NAN_BOXED(32257,16,FLEN)
NAN_BOXED(2,16,FLEN)
NAN_BOXED(65024,16,FLEN)
NAN_BOXED(32257,16,FLEN)
NAN_BOXED(33790,16,FLEN)
NAN_BOXED(65024,16,FLEN)
NAN_BOXED(32257,16,FLEN)
NAN_BOXED(1023,16,FLEN)
NAN_BOXED(65024,16,FLEN)
NAN_BOXED(32257,16,FLEN)
NAN_BOXED(33791,16,FLEN)
NAN_BOXED(65024,16,FLEN)
NAN_BOXED(32257,16,FLEN)
NAN_BOXED(1024,16,FLEN)
NAN_BOXED(65024,16,FLEN)
NAN_BOXED(32257,16,FLEN)
NAN_BOXED(33792,16,FLEN)
NAN_BOXED(65024,16,FLEN)
NAN_BOXED(32257,16,FLEN)
NAN_BOXED(1025,16,FLEN)
NAN_BOXED(65024,16,FLEN)
NAN_BOXED(32257,16,FLEN)
NAN_BOXED(33877,16,FLEN)
NAN_BOXED(65024,16,FLEN)
NAN_BOXED(32257,16,FLEN)
NAN_BOXED(31743,16,FLEN)
NAN_BOXED(65024,16,FLEN)
NAN_BOXED(32257,16,FLEN)
NAN_BOXED(64511,16,FLEN)
NAN_BOXED(65024,16,FLEN)
NAN_BOXED(32257,16,FLEN)
NAN_BOXED(31744,16,FLEN)
NAN_BOXED(65024,16,FLEN)
NAN_BOXED(32257,16,FLEN)
NAN_BOXED(64512,16,FLEN)
NAN_BOXED(65024,16,FLEN)
NAN_BOXED(32257,16,FLEN)
NAN_BOXED(32256,16,FLEN)
NAN_BOXED(65024,16,FLEN)
NAN_BOXED(32257,16,FLEN)
NAN_BOXED(65024,16,FLEN)
NAN_BOXED(65024,16,FLEN)
NAN_BOXED(32257,16,FLEN)
NAN_BOXED(32257,16,FLEN)
NAN_BOXED(65024,16,FLEN)
NAN_BOXED(32257,16,FLEN)
NAN_BOXED(65109,16,FLEN)
NAN_BOXED(65024,16,FLEN)
NAN_BOXED(32257,16,FLEN)
NAN_BOXED(31745,16,FLEN)
NAN_BOXED(65024,16,FLEN)
NAN_BOXED(32257,16,FLEN)
NAN_BOXED(64853,16,FLEN)
NAN_BOXED(65024,16,FLEN)
NAN_BOXED(32257,16,FLEN)
NAN_BOXED(15360,16,FLEN)
NAN_BOXED(65024,16,FLEN)
NAN_BOXED(32257,16,FLEN)
NAN_BOXED(48128,16,FLEN)
NAN_BOXED(65024,16,FLEN)
NAN_BOXED(65109,16,FLEN)
NAN_BOXED(0,16,FLEN)
NAN_BOXED(65024,16,FLEN)
NAN_BOXED(65109,16,FLEN)
NAN_BOXED(32768,16,FLEN)
NAN_BOXED(65024,16,FLEN)
NAN_BOXED(65109,16,FLEN)
NAN_BOXED(1,16,FLEN)
NAN_BOXED(65024,16,FLEN)
NAN_BOXED(65109,16,FLEN)
NAN_BOXED(32769,16,FLEN)
NAN_BOXED(65024,16,FLEN)
NAN_BOXED(65109,16,FLEN)
NAN_BOXED(2,16,FLEN)
NAN_BOXED(65024,16,FLEN)
NAN_BOXED(65109,16,FLEN)
NAN_BOXED(33790,16,FLEN)
NAN_BOXED(65024,16,FLEN)
NAN_BOXED(65109,16,FLEN)
NAN_BOXED(1023,16,FLEN)
NAN_BOXED(65024,16,FLEN)
NAN_BOXED(65109,16,FLEN)
NAN_BOXED(33791,16,FLEN)
NAN_BOXED(65024,16,FLEN)
NAN_BOXED(65109,16,FLEN)
NAN_BOXED(1024,16,FLEN)
NAN_BOXED(65024,16,FLEN)
NAN_BOXED(65109,16,FLEN)
NAN_BOXED(33792,16,FLEN)
NAN_BOXED(65024,16,FLEN)
NAN_BOXED(65109,16,FLEN)
NAN_BOXED(1025,16,FLEN)
NAN_BOXED(65024,16,FLEN)
NAN_BOXED(65109,16,FLEN)
NAN_BOXED(33877,16,FLEN)
NAN_BOXED(65024,16,FLEN)
NAN_BOXED(65109,16,FLEN)
NAN_BOXED(31743,16,FLEN)
NAN_BOXED(65024,16,FLEN)
NAN_BOXED(65109,16,FLEN)
NAN_BOXED(64511,16,FLEN)
NAN_BOXED(65024,16,FLEN)
NAN_BOXED(65109,16,FLEN)
NAN_BOXED(31744,16,FLEN)
NAN_BOXED(65024,16,FLEN)
NAN_BOXED(65109,16,FLEN)
NAN_BOXED(64512,16,FLEN)
NAN_BOXED(65024,16,FLEN)
NAN_BOXED(65109,16,FLEN)
NAN_BOXED(32256,16,FLEN)
NAN_BOXED(65024,16,FLEN)
NAN_BOXED(65109,16,FLEN)
NAN_BOXED(65024,16,FLEN)
NAN_BOXED(65024,16,FLEN)
NAN_BOXED(65109,16,FLEN)
NAN_BOXED(32257,16,FLEN)
NAN_BOXED(65024,16,FLEN)
NAN_BOXED(65109,16,FLEN)
NAN_BOXED(65109,16,FLEN)
NAN_BOXED(65024,16,FLEN)
NAN_BOXED(65109,16,FLEN)
NAN_BOXED(31745,16,FLEN)
NAN_BOXED(65024,16,FLEN)
NAN_BOXED(65109,16,FLEN)
NAN_BOXED(64853,16,FLEN)
NAN_BOXED(65024,16,FLEN)
NAN_BOXED(65109,16,FLEN)
NAN_BOXED(15360,16,FLEN)
NAN_BOXED(65024,16,FLEN)
NAN_BOXED(65109,16,FLEN)
NAN_BOXED(48128,16,FLEN)
NAN_BOXED(65024,16,FLEN)
NAN_BOXED(31745,16,FLEN)
NAN_BOXED(0,16,FLEN)
NAN_BOXED(65024,16,FLEN)
NAN_BOXED(31745,16,FLEN)
NAN_BOXED(32768,16,FLEN)
NAN_BOXED(65024,16,FLEN)
NAN_BOXED(31745,16,FLEN)
NAN_BOXED(1,16,FLEN)
NAN_BOXED(65024,16,FLEN)
NAN_BOXED(31745,16,FLEN)
NAN_BOXED(32769,16,FLEN)
NAN_BOXED(65024,16,FLEN)
NAN_BOXED(31745,16,FLEN)
NAN_BOXED(2,16,FLEN)
NAN_BOXED(65024,16,FLEN)
NAN_BOXED(31745,16,FLEN)
NAN_BOXED(33790,16,FLEN)
NAN_BOXED(65024,16,FLEN)
NAN_BOXED(31745,16,FLEN)
NAN_BOXED(1023,16,FLEN)
NAN_BOXED(65024,16,FLEN)
NAN_BOXED(31745,16,FLEN)
NAN_BOXED(33791,16,FLEN)
NAN_BOXED(65024,16,FLEN)
NAN_BOXED(31745,16,FLEN)
NAN_BOXED(1024,16,FLEN)
NAN_BOXED(65024,16,FLEN)
NAN_BOXED(31745,16,FLEN)
NAN_BOXED(33792,16,FLEN)
NAN_BOXED(65024,16,FLEN)
NAN_BOXED(31745,16,FLEN)
NAN_BOXED(1025,16,FLEN)
NAN_BOXED(65024,16,FLEN)
NAN_BOXED(31745,16,FLEN)
NAN_BOXED(33877,16,FLEN)
NAN_BOXED(65024,16,FLEN)
NAN_BOXED(31745,16,FLEN)
NAN_BOXED(31743,16,FLEN)
NAN_BOXED(65024,16,FLEN)
NAN_BOXED(31745,16,FLEN)
NAN_BOXED(64511,16,FLEN)
NAN_BOXED(65024,16,FLEN)
NAN_BOXED(31745,16,FLEN)
NAN_BOXED(31744,16,FLEN)
NAN_BOXED(65024,16,FLEN)
NAN_BOXED(31745,16,FLEN)
NAN_BOXED(64512,16,FLEN)
NAN_BOXED(65024,16,FLEN)
NAN_BOXED(31745,16,FLEN)
NAN_BOXED(32256,16,FLEN)
NAN_BOXED(65024,16,FLEN)
NAN_BOXED(31745,16,FLEN)
NAN_BOXED(65024,16,FLEN)
NAN_BOXED(65024,16,FLEN)
NAN_BOXED(31745,16,FLEN)
NAN_BOXED(32257,16,FLEN)
NAN_BOXED(65024,16,FLEN)
NAN_BOXED(31745,16,FLEN)
NAN_BOXED(65109,16,FLEN)
NAN_BOXED(65024,16,FLEN)
NAN_BOXED(31745,16,FLEN)
NAN_BOXED(31745,16,FLEN)
NAN_BOXED(65024,16,FLEN)
NAN_BOXED(31745,16,FLEN)
NAN_BOXED(64853,16,FLEN)
NAN_BOXED(65024,16,FLEN)
NAN_BOXED(31745,16,FLEN)
NAN_BOXED(15360,16,FLEN)
NAN_BOXED(65024,16,FLEN)
NAN_BOXED(31745,16,FLEN)
NAN_BOXED(48128,16,FLEN)
NAN_BOXED(65024,16,FLEN)
NAN_BOXED(64853,16,FLEN)
NAN_BOXED(0,16,FLEN)
NAN_BOXED(65024,16,FLEN)
NAN_BOXED(64853,16,FLEN)
NAN_BOXED(32768,16,FLEN)
NAN_BOXED(65024,16,FLEN)
NAN_BOXED(64853,16,FLEN)
NAN_BOXED(1,16,FLEN)
NAN_BOXED(65024,16,FLEN)
NAN_BOXED(64853,16,FLEN)
NAN_BOXED(32769,16,FLEN)
NAN_BOXED(65024,16,FLEN)
NAN_BOXED(64853,16,FLEN)
NAN_BOXED(2,16,FLEN)
NAN_BOXED(65024,16,FLEN)
NAN_BOXED(64853,16,FLEN)
NAN_BOXED(33790,16,FLEN)
NAN_BOXED(65024,16,FLEN)
NAN_BOXED(64853,16,FLEN)
NAN_BOXED(1023,16,FLEN)
NAN_BOXED(65024,16,FLEN)
NAN_BOXED(64853,16,FLEN)
NAN_BOXED(33791,16,FLEN)
NAN_BOXED(65024,16,FLEN)
NAN_BOXED(64853,16,FLEN)
NAN_BOXED(1024,16,FLEN)
NAN_BOXED(65024,16,FLEN)
NAN_BOXED(64853,16,FLEN)
NAN_BOXED(33792,16,FLEN)
NAN_BOXED(65024,16,FLEN)
NAN_BOXED(64853,16,FLEN)
NAN_BOXED(1025,16,FLEN)
NAN_BOXED(65024,16,FLEN)
NAN_BOXED(64853,16,FLEN)
NAN_BOXED(33877,16,FLEN)
NAN_BOXED(65024,16,FLEN)
NAN_BOXED(64853,16,FLEN)
NAN_BOXED(31743,16,FLEN)
NAN_BOXED(65024,16,FLEN)
NAN_BOXED(64853,16,FLEN)
NAN_BOXED(64511,16,FLEN)
NAN_BOXED(65024,16,FLEN)
NAN_BOXED(64853,16,FLEN)
NAN_BOXED(31744,16,FLEN)
NAN_BOXED(65024,16,FLEN)
NAN_BOXED(64853,16,FLEN)
NAN_BOXED(64512,16,FLEN)
NAN_BOXED(65024,16,FLEN)
NAN_BOXED(64853,16,FLEN)
NAN_BOXED(32256,16,FLEN)
NAN_BOXED(65024,16,FLEN)
NAN_BOXED(64853,16,FLEN)
NAN_BOXED(65024,16,FLEN)
NAN_BOXED(65024,16,FLEN)
NAN_BOXED(64853,16,FLEN)
NAN_BOXED(32257,16,FLEN)
NAN_BOXED(65024,16,FLEN)
NAN_BOXED(64853,16,FLEN)
NAN_BOXED(65109,16,FLEN)
NAN_BOXED(65024,16,FLEN)
NAN_BOXED(64853,16,FLEN)
NAN_BOXED(31745,16,FLEN)
NAN_BOXED(65024,16,FLEN)
NAN_BOXED(64853,16,FLEN)
NAN_BOXED(64853,16,FLEN)
NAN_BOXED(65024,16,FLEN)
NAN_BOXED(64853,16,FLEN)
NAN_BOXED(15360,16,FLEN)
NAN_BOXED(65024,16,FLEN)
NAN_BOXED(64853,16,FLEN)
NAN_BOXED(48128,16,FLEN)
NAN_BOXED(65024,16,FLEN)
NAN_BOXED(15360,16,FLEN)
NAN_BOXED(0,16,FLEN)
NAN_BOXED(65024,16,FLEN)
NAN_BOXED(15360,16,FLEN)
NAN_BOXED(32768,16,FLEN)
NAN_BOXED(65024,16,FLEN)
NAN_BOXED(15360,16,FLEN)
NAN_BOXED(1,16,FLEN)
NAN_BOXED(65024,16,FLEN)
NAN_BOXED(15360,16,FLEN)
NAN_BOXED(32769,16,FLEN)
NAN_BOXED(65024,16,FLEN)
NAN_BOXED(15360,16,FLEN)
NAN_BOXED(2,16,FLEN)
NAN_BOXED(65024,16,FLEN)
NAN_BOXED(15360,16,FLEN)
NAN_BOXED(33790,16,FLEN)
NAN_BOXED(65024,16,FLEN)
NAN_BOXED(15360,16,FLEN)
NAN_BOXED(1023,16,FLEN)
NAN_BOXED(65024,16,FLEN)
NAN_BOXED(15360,16,FLEN)
NAN_BOXED(33791,16,FLEN)
NAN_BOXED(65024,16,FLEN)
NAN_BOXED(15360,16,FLEN)
NAN_BOXED(1024,16,FLEN)
NAN_BOXED(65024,16,FLEN)
NAN_BOXED(15360,16,FLEN)
NAN_BOXED(33792,16,FLEN)
NAN_BOXED(65024,16,FLEN)
NAN_BOXED(15360,16,FLEN)
NAN_BOXED(1025,16,FLEN)
NAN_BOXED(65024,16,FLEN)
NAN_BOXED(15360,16,FLEN)
NAN_BOXED(33877,16,FLEN)
NAN_BOXED(65024,16,FLEN)
NAN_BOXED(15360,16,FLEN)
NAN_BOXED(31743,16,FLEN)
NAN_BOXED(65024,16,FLEN)
NAN_BOXED(15360,16,FLEN)
NAN_BOXED(64511,16,FLEN)
NAN_BOXED(65024,16,FLEN)
NAN_BOXED(15360,16,FLEN)
NAN_BOXED(31744,16,FLEN)
NAN_BOXED(65024,16,FLEN)
NAN_BOXED(15360,16,FLEN)
NAN_BOXED(64512,16,FLEN)
NAN_BOXED(65024,16,FLEN)
NAN_BOXED(15360,16,FLEN)
NAN_BOXED(32256,16,FLEN)
NAN_BOXED(65024,16,FLEN)
NAN_BOXED(15360,16,FLEN)
NAN_BOXED(65024,16,FLEN)
NAN_BOXED(65024,16,FLEN)
NAN_BOXED(15360,16,FLEN)
NAN_BOXED(32257,16,FLEN)
NAN_BOXED(65024,16,FLEN)
NAN_BOXED(15360,16,FLEN)
NAN_BOXED(65109,16,FLEN)
NAN_BOXED(65024,16,FLEN)
NAN_BOXED(15360,16,FLEN)
NAN_BOXED(31745,16,FLEN)
NAN_BOXED(65024,16,FLEN)
NAN_BOXED(15360,16,FLEN)
NAN_BOXED(64853,16,FLEN)
NAN_BOXED(65024,16,FLEN)
NAN_BOXED(15360,16,FLEN)
NAN_BOXED(15360,16,FLEN)
NAN_BOXED(65024,16,FLEN)
NAN_BOXED(15360,16,FLEN)
NAN_BOXED(48128,16,FLEN)
NAN_BOXED(65024,16,FLEN)
NAN_BOXED(48128,16,FLEN)
NAN_BOXED(0,16,FLEN)
NAN_BOXED(65024,16,FLEN)
NAN_BOXED(48128,16,FLEN)
NAN_BOXED(32768,16,FLEN)
NAN_BOXED(65024,16,FLEN)
NAN_BOXED(48128,16,FLEN)
NAN_BOXED(1,16,FLEN)
NAN_BOXED(65024,16,FLEN)
NAN_BOXED(48128,16,FLEN)
NAN_BOXED(32769,16,FLEN)
NAN_BOXED(65024,16,FLEN)
NAN_BOXED(48128,16,FLEN)
NAN_BOXED(2,16,FLEN)
NAN_BOXED(65024,16,FLEN)
NAN_BOXED(48128,16,FLEN)
NAN_BOXED(33790,16,FLEN)
NAN_BOXED(65024,16,FLEN)
NAN_BOXED(48128,16,FLEN)
NAN_BOXED(1023,16,FLEN)
NAN_BOXED(65024,16,FLEN)
NAN_BOXED(48128,16,FLEN)
NAN_BOXED(33791,16,FLEN)
NAN_BOXED(65024,16,FLEN)
NAN_BOXED(48128,16,FLEN)
NAN_BOXED(1024,16,FLEN)
NAN_BOXED(65024,16,FLEN)
NAN_BOXED(48128,16,FLEN)
NAN_BOXED(33792,16,FLEN)
NAN_BOXED(65024,16,FLEN)
NAN_BOXED(48128,16,FLEN)
NAN_BOXED(1025,16,FLEN)
NAN_BOXED(65024,16,FLEN)
NAN_BOXED(48128,16,FLEN)
NAN_BOXED(33877,16,FLEN)
NAN_BOXED(65024,16,FLEN)
NAN_BOXED(48128,16,FLEN)
NAN_BOXED(31743,16,FLEN)
NAN_BOXED(65024,16,FLEN)
NAN_BOXED(48128,16,FLEN)
NAN_BOXED(64511,16,FLEN)
NAN_BOXED(65024,16,FLEN)
NAN_BOXED(48128,16,FLEN)
NAN_BOXED(31744,16,FLEN)
NAN_BOXED(65024,16,FLEN)
NAN_BOXED(48128,16,FLEN)
NAN_BOXED(64512,16,FLEN)
NAN_BOXED(65024,16,FLEN)
NAN_BOXED(48128,16,FLEN)
NAN_BOXED(32256,16,FLEN)
NAN_BOXED(65024,16,FLEN)
NAN_BOXED(48128,16,FLEN)
NAN_BOXED(65024,16,FLEN)
NAN_BOXED(65024,16,FLEN)
NAN_BOXED(48128,16,FLEN)
NAN_BOXED(32257,16,FLEN)
NAN_BOXED(65024,16,FLEN)
NAN_BOXED(48128,16,FLEN)
NAN_BOXED(65109,16,FLEN)
NAN_BOXED(65024,16,FLEN)
NAN_BOXED(48128,16,FLEN)
NAN_BOXED(31745,16,FLEN)
NAN_BOXED(65024,16,FLEN)
NAN_BOXED(48128,16,FLEN)
NAN_BOXED(64853,16,FLEN)
NAN_BOXED(65024,16,FLEN)
NAN_BOXED(48128,16,FLEN)
NAN_BOXED(15360,16,FLEN)
NAN_BOXED(65024,16,FLEN)
NAN_BOXED(48128,16,FLEN)
NAN_BOXED(48128,16,FLEN)
NAN_BOXED(32257,16,FLEN)
NAN_BOXED(0,16,FLEN)
NAN_BOXED(0,16,FLEN)
NAN_BOXED(32257,16,FLEN)
NAN_BOXED(0,16,FLEN)
NAN_BOXED(32768,16,FLEN)
NAN_BOXED(32257,16,FLEN)
NAN_BOXED(0,16,FLEN)
NAN_BOXED(1,16,FLEN)
NAN_BOXED(32257,16,FLEN)
NAN_BOXED(0,16,FLEN)
NAN_BOXED(32769,16,FLEN)
NAN_BOXED(32257,16,FLEN)
NAN_BOXED(0,16,FLEN)
NAN_BOXED(2,16,FLEN)
NAN_BOXED(32257,16,FLEN)
NAN_BOXED(0,16,FLEN)
NAN_BOXED(33790,16,FLEN)
NAN_BOXED(32257,16,FLEN)
NAN_BOXED(0,16,FLEN)
NAN_BOXED(1023,16,FLEN)
NAN_BOXED(32257,16,FLEN)
NAN_BOXED(0,16,FLEN)
NAN_BOXED(33791,16,FLEN)
NAN_BOXED(32257,16,FLEN)
NAN_BOXED(0,16,FLEN)
NAN_BOXED(1024,16,FLEN)
NAN_BOXED(32257,16,FLEN)
NAN_BOXED(0,16,FLEN)
NAN_BOXED(33792,16,FLEN)
NAN_BOXED(32257,16,FLEN)
NAN_BOXED(0,16,FLEN)
NAN_BOXED(1025,16,FLEN)
NAN_BOXED(32257,16,FLEN)
NAN_BOXED(0,16,FLEN)
NAN_BOXED(33877,16,FLEN)
NAN_BOXED(32257,16,FLEN)
NAN_BOXED(0,16,FLEN)
NAN_BOXED(31743,16,FLEN)
NAN_BOXED(32257,16,FLEN)
NAN_BOXED(0,16,FLEN)
NAN_BOXED(64511,16,FLEN)
NAN_BOXED(32257,16,FLEN)
NAN_BOXED(0,16,FLEN)
NAN_BOXED(31744,16,FLEN)
NAN_BOXED(32257,16,FLEN)
NAN_BOXED(0,16,FLEN)
NAN_BOXED(64512,16,FLEN)
NAN_BOXED(32257,16,FLEN)
NAN_BOXED(0,16,FLEN)
NAN_BOXED(32256,16,FLEN)
NAN_BOXED(32257,16,FLEN)
NAN_BOXED(0,16,FLEN)
NAN_BOXED(65024,16,FLEN)
NAN_BOXED(32257,16,FLEN)
NAN_BOXED(0,16,FLEN)
NAN_BOXED(32257,16,FLEN)
NAN_BOXED(32257,16,FLEN)
NAN_BOXED(0,16,FLEN)
NAN_BOXED(65109,16,FLEN)
NAN_BOXED(32257,16,FLEN)
NAN_BOXED(0,16,FLEN)
NAN_BOXED(31745,16,FLEN)
NAN_BOXED(32257,16,FLEN)
NAN_BOXED(0,16,FLEN)
NAN_BOXED(64853,16,FLEN)
NAN_BOXED(32257,16,FLEN)
NAN_BOXED(0,16,FLEN)
NAN_BOXED(15360,16,FLEN)
NAN_BOXED(32257,16,FLEN)
NAN_BOXED(0,16,FLEN)
NAN_BOXED(48128,16,FLEN)
NAN_BOXED(32257,16,FLEN)
NAN_BOXED(32768,16,FLEN)
NAN_BOXED(0,16,FLEN)
NAN_BOXED(32257,16,FLEN)
NAN_BOXED(32768,16,FLEN)
NAN_BOXED(32768,16,FLEN)
NAN_BOXED(32257,16,FLEN)
NAN_BOXED(32768,16,FLEN)
NAN_BOXED(1,16,FLEN)
NAN_BOXED(32257,16,FLEN)
NAN_BOXED(32768,16,FLEN)
NAN_BOXED(32769,16,FLEN)
NAN_BOXED(32257,16,FLEN)
NAN_BOXED(32768,16,FLEN)
NAN_BOXED(2,16,FLEN)
NAN_BOXED(32257,16,FLEN)
NAN_BOXED(32768,16,FLEN)
NAN_BOXED(33790,16,FLEN)
NAN_BOXED(32257,16,FLEN)
NAN_BOXED(32768,16,FLEN)
NAN_BOXED(1023,16,FLEN)
NAN_BOXED(32257,16,FLEN)
NAN_BOXED(32768,16,FLEN)
NAN_BOXED(33791,16,FLEN)
NAN_BOXED(32257,16,FLEN)
NAN_BOXED(32768,16,FLEN)
NAN_BOXED(1024,16,FLEN)
NAN_BOXED(32257,16,FLEN)
NAN_BOXED(32768,16,FLEN)
NAN_BOXED(33792,16,FLEN)
NAN_BOXED(32257,16,FLEN)
NAN_BOXED(32768,16,FLEN)
NAN_BOXED(1025,16,FLEN)
NAN_BOXED(32257,16,FLEN)
NAN_BOXED(32768,16,FLEN)
NAN_BOXED(33877,16,FLEN)
NAN_BOXED(32257,16,FLEN)
NAN_BOXED(32768,16,FLEN)
NAN_BOXED(31743,16,FLEN)
NAN_BOXED(32257,16,FLEN)
NAN_BOXED(32768,16,FLEN)
NAN_BOXED(64511,16,FLEN)
NAN_BOXED(32257,16,FLEN)
NAN_BOXED(32768,16,FLEN)
NAN_BOXED(31744,16,FLEN)
NAN_BOXED(32257,16,FLEN)
NAN_BOXED(32768,16,FLEN)
NAN_BOXED(64512,16,FLEN)
NAN_BOXED(32257,16,FLEN)
NAN_BOXED(32768,16,FLEN)
NAN_BOXED(32256,16,FLEN)
NAN_BOXED(32257,16,FLEN)
NAN_BOXED(32768,16,FLEN)
NAN_BOXED(65024,16,FLEN)
NAN_BOXED(32257,16,FLEN)
NAN_BOXED(32768,16,FLEN)
NAN_BOXED(32257,16,FLEN)
NAN_BOXED(32257,16,FLEN)
NAN_BOXED(32768,16,FLEN)
NAN_BOXED(65109,16,FLEN)
NAN_BOXED(32257,16,FLEN)
NAN_BOXED(32768,16,FLEN)
NAN_BOXED(31745,16,FLEN)
NAN_BOXED(32257,16,FLEN)
NAN_BOXED(32768,16,FLEN)
NAN_BOXED(64853,16,FLEN)
NAN_BOXED(32257,16,FLEN)
NAN_BOXED(32768,16,FLEN)
NAN_BOXED(15360,16,FLEN)
NAN_BOXED(32257,16,FLEN)
NAN_BOXED(32768,16,FLEN)
NAN_BOXED(48128,16,FLEN)
NAN_BOXED(32257,16,FLEN)
NAN_BOXED(1,16,FLEN)
NAN_BOXED(0,16,FLEN)
NAN_BOXED(32257,16,FLEN)
NAN_BOXED(1,16,FLEN)
NAN_BOXED(32768,16,FLEN)
NAN_BOXED(32257,16,FLEN)
NAN_BOXED(1,16,FLEN)
NAN_BOXED(1,16,FLEN)
NAN_BOXED(32257,16,FLEN)
NAN_BOXED(1,16,FLEN)
NAN_BOXED(32769,16,FLEN)
NAN_BOXED(32257,16,FLEN)
NAN_BOXED(1,16,FLEN)
NAN_BOXED(2,16,FLEN)
NAN_BOXED(32257,16,FLEN)
NAN_BOXED(1,16,FLEN)
NAN_BOXED(33790,16,FLEN)
NAN_BOXED(32257,16,FLEN)
NAN_BOXED(1,16,FLEN)
NAN_BOXED(1023,16,FLEN)
NAN_BOXED(32257,16,FLEN)
NAN_BOXED(1,16,FLEN)
NAN_BOXED(33791,16,FLEN)
NAN_BOXED(32257,16,FLEN)
NAN_BOXED(1,16,FLEN)
NAN_BOXED(1024,16,FLEN)
NAN_BOXED(32257,16,FLEN)
NAN_BOXED(1,16,FLEN)
NAN_BOXED(33792,16,FLEN)
NAN_BOXED(32257,16,FLEN)
NAN_BOXED(1,16,FLEN)
NAN_BOXED(1025,16,FLEN)
NAN_BOXED(32257,16,FLEN)
NAN_BOXED(1,16,FLEN)
NAN_BOXED(33877,16,FLEN)
NAN_BOXED(32257,16,FLEN)
NAN_BOXED(1,16,FLEN)
NAN_BOXED(31743,16,FLEN)
NAN_BOXED(32257,16,FLEN)
NAN_BOXED(1,16,FLEN)
NAN_BOXED(64511,16,FLEN)
NAN_BOXED(32257,16,FLEN)
NAN_BOXED(1,16,FLEN)
NAN_BOXED(31744,16,FLEN)
NAN_BOXED(32257,16,FLEN)
NAN_BOXED(1,16,FLEN)
NAN_BOXED(64512,16,FLEN)
NAN_BOXED(32257,16,FLEN)
NAN_BOXED(1,16,FLEN)
NAN_BOXED(32256,16,FLEN)
NAN_BOXED(32257,16,FLEN)
NAN_BOXED(1,16,FLEN)
NAN_BOXED(65024,16,FLEN)
NAN_BOXED(32257,16,FLEN)
NAN_BOXED(1,16,FLEN)
NAN_BOXED(32257,16,FLEN)
NAN_BOXED(32257,16,FLEN)
NAN_BOXED(1,16,FLEN)
NAN_BOXED(65109,16,FLEN)
NAN_BOXED(32257,16,FLEN)
NAN_BOXED(1,16,FLEN)
NAN_BOXED(31745,16,FLEN)
NAN_BOXED(32257,16,FLEN)
NAN_BOXED(1,16,FLEN)
NAN_BOXED(64853,16,FLEN)
NAN_BOXED(32257,16,FLEN)
NAN_BOXED(1,16,FLEN)
NAN_BOXED(15360,16,FLEN)
NAN_BOXED(32257,16,FLEN)
NAN_BOXED(1,16,FLEN)
NAN_BOXED(48128,16,FLEN)
NAN_BOXED(32257,16,FLEN)
NAN_BOXED(32769,16,FLEN)
NAN_BOXED(0,16,FLEN)
NAN_BOXED(32257,16,FLEN)
NAN_BOXED(32769,16,FLEN)
NAN_BOXED(32768,16,FLEN)
NAN_BOXED(32257,16,FLEN)
NAN_BOXED(32769,16,FLEN)
NAN_BOXED(1,16,FLEN)
NAN_BOXED(32257,16,FLEN)
NAN_BOXED(32769,16,FLEN)
NAN_BOXED(32769,16,FLEN)
NAN_BOXED(32257,16,FLEN)
NAN_BOXED(32769,16,FLEN)
NAN_BOXED(2,16,FLEN)
NAN_BOXED(32257,16,FLEN)
NAN_BOXED(32769,16,FLEN)
NAN_BOXED(33790,16,FLEN)
NAN_BOXED(32257,16,FLEN)
NAN_BOXED(32769,16,FLEN)
NAN_BOXED(1023,16,FLEN)
NAN_BOXED(32257,16,FLEN)
NAN_BOXED(32769,16,FLEN)
NAN_BOXED(33791,16,FLEN)
NAN_BOXED(32257,16,FLEN)
NAN_BOXED(32769,16,FLEN)
NAN_BOXED(1024,16,FLEN)
NAN_BOXED(32257,16,FLEN)
NAN_BOXED(32769,16,FLEN)
NAN_BOXED(33792,16,FLEN)
NAN_BOXED(32257,16,FLEN)
NAN_BOXED(32769,16,FLEN)
NAN_BOXED(1025,16,FLEN)
NAN_BOXED(32257,16,FLEN)
NAN_BOXED(32769,16,FLEN)
NAN_BOXED(33877,16,FLEN)
NAN_BOXED(32257,16,FLEN)
NAN_BOXED(32769,16,FLEN)
NAN_BOXED(31743,16,FLEN)
NAN_BOXED(32257,16,FLEN)
NAN_BOXED(32769,16,FLEN)
NAN_BOXED(64511,16,FLEN)
NAN_BOXED(32257,16,FLEN)
NAN_BOXED(32769,16,FLEN)
NAN_BOXED(31744,16,FLEN)
NAN_BOXED(32257,16,FLEN)
NAN_BOXED(32769,16,FLEN)
NAN_BOXED(64512,16,FLEN)
NAN_BOXED(32257,16,FLEN)
NAN_BOXED(32769,16,FLEN)
NAN_BOXED(32256,16,FLEN)
NAN_BOXED(32257,16,FLEN)
NAN_BOXED(32769,16,FLEN)
NAN_BOXED(65024,16,FLEN)
NAN_BOXED(32257,16,FLEN)
NAN_BOXED(32769,16,FLEN)
NAN_BOXED(32257,16,FLEN)
NAN_BOXED(32257,16,FLEN)
NAN_BOXED(32769,16,FLEN)
NAN_BOXED(65109,16,FLEN)
NAN_BOXED(32257,16,FLEN)
NAN_BOXED(32769,16,FLEN)
NAN_BOXED(31745,16,FLEN)
NAN_BOXED(32257,16,FLEN)
NAN_BOXED(32769,16,FLEN)
NAN_BOXED(64853,16,FLEN)
NAN_BOXED(32257,16,FLEN)
NAN_BOXED(32769,16,FLEN)
NAN_BOXED(15360,16,FLEN)
NAN_BOXED(32257,16,FLEN)
NAN_BOXED(32769,16,FLEN)
NAN_BOXED(48128,16,FLEN)
NAN_BOXED(32257,16,FLEN)
NAN_BOXED(2,16,FLEN)
NAN_BOXED(0,16,FLEN)
NAN_BOXED(32257,16,FLEN)
NAN_BOXED(2,16,FLEN)
NAN_BOXED(32768,16,FLEN)
NAN_BOXED(32257,16,FLEN)
NAN_BOXED(2,16,FLEN)
NAN_BOXED(1,16,FLEN)
NAN_BOXED(32257,16,FLEN)
NAN_BOXED(2,16,FLEN)
NAN_BOXED(32769,16,FLEN)
NAN_BOXED(32257,16,FLEN)
NAN_BOXED(2,16,FLEN)
NAN_BOXED(2,16,FLEN)
NAN_BOXED(32257,16,FLEN)
NAN_BOXED(2,16,FLEN)
NAN_BOXED(33790,16,FLEN)
NAN_BOXED(32257,16,FLEN)
NAN_BOXED(2,16,FLEN)
NAN_BOXED(1023,16,FLEN)
NAN_BOXED(32257,16,FLEN)
NAN_BOXED(2,16,FLEN)
NAN_BOXED(33791,16,FLEN)
NAN_BOXED(32257,16,FLEN)
NAN_BOXED(2,16,FLEN)
NAN_BOXED(1024,16,FLEN)
NAN_BOXED(32257,16,FLEN)
NAN_BOXED(2,16,FLEN)
NAN_BOXED(33792,16,FLEN)
NAN_BOXED(32257,16,FLEN)
NAN_BOXED(2,16,FLEN)
NAN_BOXED(1025,16,FLEN)
NAN_BOXED(32257,16,FLEN)
NAN_BOXED(2,16,FLEN)
NAN_BOXED(33877,16,FLEN)
NAN_BOXED(32257,16,FLEN)
NAN_BOXED(2,16,FLEN)
NAN_BOXED(31743,16,FLEN)
NAN_BOXED(32257,16,FLEN)
NAN_BOXED(2,16,FLEN)
NAN_BOXED(64511,16,FLEN)
NAN_BOXED(32257,16,FLEN)
NAN_BOXED(2,16,FLEN)
NAN_BOXED(31744,16,FLEN)
NAN_BOXED(32257,16,FLEN)
NAN_BOXED(2,16,FLEN)
NAN_BOXED(64512,16,FLEN)
NAN_BOXED(32257,16,FLEN)
NAN_BOXED(2,16,FLEN)
NAN_BOXED(32256,16,FLEN)
NAN_BOXED(32257,16,FLEN)
NAN_BOXED(2,16,FLEN)
NAN_BOXED(65024,16,FLEN)
NAN_BOXED(32257,16,FLEN)
NAN_BOXED(2,16,FLEN)
NAN_BOXED(32257,16,FLEN)
NAN_BOXED(32257,16,FLEN)
NAN_BOXED(2,16,FLEN)
NAN_BOXED(65109,16,FLEN)
NAN_BOXED(32257,16,FLEN)
NAN_BOXED(2,16,FLEN)
NAN_BOXED(31745,16,FLEN)
NAN_BOXED(32257,16,FLEN)
NAN_BOXED(2,16,FLEN)
NAN_BOXED(64853,16,FLEN)
NAN_BOXED(32257,16,FLEN)
NAN_BOXED(2,16,FLEN)
NAN_BOXED(15360,16,FLEN)
NAN_BOXED(32257,16,FLEN)
NAN_BOXED(2,16,FLEN)
NAN_BOXED(48128,16,FLEN)
NAN_BOXED(32257,16,FLEN)
NAN_BOXED(33790,16,FLEN)
NAN_BOXED(0,16,FLEN)
NAN_BOXED(32257,16,FLEN)
NAN_BOXED(33790,16,FLEN)
NAN_BOXED(32768,16,FLEN)
NAN_BOXED(32257,16,FLEN)
NAN_BOXED(33790,16,FLEN)
NAN_BOXED(1,16,FLEN)
NAN_BOXED(32257,16,FLEN)
NAN_BOXED(33790,16,FLEN)
NAN_BOXED(32769,16,FLEN)
NAN_BOXED(32257,16,FLEN)
NAN_BOXED(33790,16,FLEN)
NAN_BOXED(2,16,FLEN)
NAN_BOXED(32257,16,FLEN)
NAN_BOXED(33790,16,FLEN)
NAN_BOXED(33790,16,FLEN)
NAN_BOXED(32257,16,FLEN)
NAN_BOXED(33790,16,FLEN)
NAN_BOXED(1023,16,FLEN)
NAN_BOXED(32257,16,FLEN)
NAN_BOXED(33790,16,FLEN)
NAN_BOXED(33791,16,FLEN)
NAN_BOXED(32257,16,FLEN)
NAN_BOXED(33790,16,FLEN)
NAN_BOXED(1024,16,FLEN)
NAN_BOXED(32257,16,FLEN)
NAN_BOXED(33790,16,FLEN)
NAN_BOXED(33792,16,FLEN)
NAN_BOXED(32257,16,FLEN)
NAN_BOXED(33790,16,FLEN)
NAN_BOXED(1025,16,FLEN)
NAN_BOXED(32257,16,FLEN)
NAN_BOXED(33790,16,FLEN)
NAN_BOXED(33877,16,FLEN)
NAN_BOXED(32257,16,FLEN)
NAN_BOXED(33790,16,FLEN)
NAN_BOXED(31743,16,FLEN)
NAN_BOXED(32257,16,FLEN)
NAN_BOXED(33790,16,FLEN)
NAN_BOXED(64511,16,FLEN)
NAN_BOXED(32257,16,FLEN)
NAN_BOXED(33790,16,FLEN)
NAN_BOXED(31744,16,FLEN)
NAN_BOXED(32257,16,FLEN)
NAN_BOXED(33790,16,FLEN)
NAN_BOXED(64512,16,FLEN)
NAN_BOXED(32257,16,FLEN)
NAN_BOXED(33790,16,FLEN)
NAN_BOXED(32256,16,FLEN)
NAN_BOXED(32257,16,FLEN)
NAN_BOXED(33790,16,FLEN)
NAN_BOXED(65024,16,FLEN)
NAN_BOXED(32257,16,FLEN)
NAN_BOXED(33790,16,FLEN)
NAN_BOXED(32257,16,FLEN)
NAN_BOXED(32257,16,FLEN)
NAN_BOXED(33790,16,FLEN)
NAN_BOXED(65109,16,FLEN)
NAN_BOXED(32257,16,FLEN)
NAN_BOXED(33790,16,FLEN)
NAN_BOXED(31745,16,FLEN)
NAN_BOXED(32257,16,FLEN)
NAN_BOXED(33790,16,FLEN)
NAN_BOXED(64853,16,FLEN)
NAN_BOXED(32257,16,FLEN)
NAN_BOXED(33790,16,FLEN)
NAN_BOXED(15360,16,FLEN)
NAN_BOXED(32257,16,FLEN)
NAN_BOXED(33790,16,FLEN)
NAN_BOXED(48128,16,FLEN)
NAN_BOXED(32257,16,FLEN)
NAN_BOXED(1023,16,FLEN)
NAN_BOXED(0,16,FLEN)
NAN_BOXED(32257,16,FLEN)
NAN_BOXED(1023,16,FLEN)
NAN_BOXED(32768,16,FLEN)
NAN_BOXED(32257,16,FLEN)
NAN_BOXED(1023,16,FLEN)
NAN_BOXED(1,16,FLEN)
NAN_BOXED(32257,16,FLEN)
NAN_BOXED(1023,16,FLEN)
NAN_BOXED(32769,16,FLEN)
NAN_BOXED(32257,16,FLEN)
NAN_BOXED(1023,16,FLEN)
NAN_BOXED(2,16,FLEN)
NAN_BOXED(32257,16,FLEN)
NAN_BOXED(1023,16,FLEN)
NAN_BOXED(33790,16,FLEN)
NAN_BOXED(32257,16,FLEN)
NAN_BOXED(1023,16,FLEN)
NAN_BOXED(1023,16,FLEN)
NAN_BOXED(32257,16,FLEN)
NAN_BOXED(1023,16,FLEN)
NAN_BOXED(33791,16,FLEN)
NAN_BOXED(32257,16,FLEN)
NAN_BOXED(1023,16,FLEN)
NAN_BOXED(1024,16,FLEN)
NAN_BOXED(32257,16,FLEN)
NAN_BOXED(1023,16,FLEN)
NAN_BOXED(33792,16,FLEN)
NAN_BOXED(32257,16,FLEN)
NAN_BOXED(1023,16,FLEN)
NAN_BOXED(1025,16,FLEN)
NAN_BOXED(32257,16,FLEN)
NAN_BOXED(1023,16,FLEN)
NAN_BOXED(33877,16,FLEN)
NAN_BOXED(32257,16,FLEN)
NAN_BOXED(1023,16,FLEN)
NAN_BOXED(31743,16,FLEN)
NAN_BOXED(32257,16,FLEN)
NAN_BOXED(1023,16,FLEN)
NAN_BOXED(64511,16,FLEN)
NAN_BOXED(32257,16,FLEN)
NAN_BOXED(1023,16,FLEN)
NAN_BOXED(31744,16,FLEN)
NAN_BOXED(32257,16,FLEN)
NAN_BOXED(1023,16,FLEN)
NAN_BOXED(64512,16,FLEN)
NAN_BOXED(32257,16,FLEN)
NAN_BOXED(1023,16,FLEN)
NAN_BOXED(32256,16,FLEN)
NAN_BOXED(32257,16,FLEN)
NAN_BOXED(1023,16,FLEN)
NAN_BOXED(65024,16,FLEN)
NAN_BOXED(32257,16,FLEN)
NAN_BOXED(1023,16,FLEN)
NAN_BOXED(32257,16,FLEN)
NAN_BOXED(32257,16,FLEN)
NAN_BOXED(1023,16,FLEN)
NAN_BOXED(65109,16,FLEN)
NAN_BOXED(32257,16,FLEN)
NAN_BOXED(1023,16,FLEN)
NAN_BOXED(31745,16,FLEN)
NAN_BOXED(32257,16,FLEN)
NAN_BOXED(1023,16,FLEN)
NAN_BOXED(64853,16,FLEN)
NAN_BOXED(32257,16,FLEN)
NAN_BOXED(1023,16,FLEN)
NAN_BOXED(15360,16,FLEN)
NAN_BOXED(32257,16,FLEN)
NAN_BOXED(1023,16,FLEN)
NAN_BOXED(48128,16,FLEN)
NAN_BOXED(32257,16,FLEN)
NAN_BOXED(33791,16,FLEN)
NAN_BOXED(0,16,FLEN)
NAN_BOXED(32257,16,FLEN)
NAN_BOXED(33791,16,FLEN)
NAN_BOXED(32768,16,FLEN)
NAN_BOXED(32257,16,FLEN)
NAN_BOXED(33791,16,FLEN)
NAN_BOXED(1,16,FLEN)
NAN_BOXED(32257,16,FLEN)
NAN_BOXED(33791,16,FLEN)
NAN_BOXED(32769,16,FLEN)
NAN_BOXED(32257,16,FLEN)
NAN_BOXED(33791,16,FLEN)
NAN_BOXED(2,16,FLEN)
NAN_BOXED(32257,16,FLEN)
NAN_BOXED(33791,16,FLEN)
NAN_BOXED(33790,16,FLEN)
NAN_BOXED(32257,16,FLEN)
NAN_BOXED(33791,16,FLEN)
NAN_BOXED(1023,16,FLEN)
NAN_BOXED(32257,16,FLEN)
NAN_BOXED(33791,16,FLEN)
NAN_BOXED(33791,16,FLEN)
NAN_BOXED(32257,16,FLEN)
NAN_BOXED(33791,16,FLEN)
NAN_BOXED(1024,16,FLEN)
NAN_BOXED(32257,16,FLEN)
NAN_BOXED(33791,16,FLEN)
NAN_BOXED(33792,16,FLEN)
NAN_BOXED(32257,16,FLEN)
NAN_BOXED(33791,16,FLEN)
NAN_BOXED(1025,16,FLEN)
NAN_BOXED(32257,16,FLEN)
NAN_BOXED(33791,16,FLEN)
NAN_BOXED(33877,16,FLEN)
NAN_BOXED(32257,16,FLEN)
NAN_BOXED(33791,16,FLEN)
NAN_BOXED(31743,16,FLEN)
NAN_BOXED(32257,16,FLEN)
NAN_BOXED(33791,16,FLEN)
NAN_BOXED(64511,16,FLEN)
NAN_BOXED(32257,16,FLEN)
NAN_BOXED(33791,16,FLEN)
NAN_BOXED(31744,16,FLEN)
NAN_BOXED(32257,16,FLEN)
NAN_BOXED(33791,16,FLEN)
NAN_BOXED(64512,16,FLEN)
NAN_BOXED(32257,16,FLEN)
NAN_BOXED(33791,16,FLEN)
NAN_BOXED(32256,16,FLEN)
NAN_BOXED(32257,16,FLEN)
NAN_BOXED(33791,16,FLEN)
NAN_BOXED(65024,16,FLEN)
NAN_BOXED(32257,16,FLEN)
NAN_BOXED(33791,16,FLEN)
NAN_BOXED(32257,16,FLEN)
NAN_BOXED(32257,16,FLEN)
NAN_BOXED(33791,16,FLEN)
NAN_BOXED(65109,16,FLEN)
NAN_BOXED(32257,16,FLEN)
NAN_BOXED(33791,16,FLEN)
NAN_BOXED(31745,16,FLEN)
NAN_BOXED(32257,16,FLEN)
NAN_BOXED(33791,16,FLEN)
NAN_BOXED(64853,16,FLEN)
NAN_BOXED(32257,16,FLEN)
NAN_BOXED(33791,16,FLEN)
NAN_BOXED(15360,16,FLEN)
NAN_BOXED(32257,16,FLEN)
NAN_BOXED(33791,16,FLEN)
NAN_BOXED(48128,16,FLEN)
NAN_BOXED(32257,16,FLEN)
NAN_BOXED(1024,16,FLEN)
NAN_BOXED(0,16,FLEN)
NAN_BOXED(32257,16,FLEN)
NAN_BOXED(1024,16,FLEN)
NAN_BOXED(32768,16,FLEN)
NAN_BOXED(32257,16,FLEN)
NAN_BOXED(1024,16,FLEN)
NAN_BOXED(1,16,FLEN)
NAN_BOXED(32257,16,FLEN)
NAN_BOXED(1024,16,FLEN)
NAN_BOXED(32769,16,FLEN)
NAN_BOXED(32257,16,FLEN)
NAN_BOXED(1024,16,FLEN)
NAN_BOXED(2,16,FLEN)
NAN_BOXED(32257,16,FLEN)
NAN_BOXED(1024,16,FLEN)
NAN_BOXED(33790,16,FLEN)
NAN_BOXED(32257,16,FLEN)
NAN_BOXED(1024,16,FLEN)
NAN_BOXED(1023,16,FLEN)
NAN_BOXED(32257,16,FLEN)
NAN_BOXED(1024,16,FLEN)
NAN_BOXED(33791,16,FLEN)
NAN_BOXED(32257,16,FLEN)
NAN_BOXED(1024,16,FLEN)
NAN_BOXED(1024,16,FLEN)
NAN_BOXED(32257,16,FLEN)
NAN_BOXED(1024,16,FLEN)
NAN_BOXED(33792,16,FLEN)
NAN_BOXED(32257,16,FLEN)
NAN_BOXED(1024,16,FLEN)
NAN_BOXED(1025,16,FLEN)
NAN_BOXED(32257,16,FLEN)
NAN_BOXED(1024,16,FLEN)
NAN_BOXED(33877,16,FLEN)
NAN_BOXED(32257,16,FLEN)
NAN_BOXED(1024,16,FLEN)
NAN_BOXED(31743,16,FLEN)
NAN_BOXED(32257,16,FLEN)
NAN_BOXED(1024,16,FLEN)
NAN_BOXED(64511,16,FLEN)
NAN_BOXED(32257,16,FLEN)
NAN_BOXED(1024,16,FLEN)
NAN_BOXED(31744,16,FLEN)
NAN_BOXED(32257,16,FLEN)
NAN_BOXED(1024,16,FLEN)
NAN_BOXED(64512,16,FLEN)
NAN_BOXED(32257,16,FLEN)
NAN_BOXED(1024,16,FLEN)
NAN_BOXED(32256,16,FLEN)
NAN_BOXED(32257,16,FLEN)
NAN_BOXED(1024,16,FLEN)
NAN_BOXED(65024,16,FLEN)
NAN_BOXED(32257,16,FLEN)
NAN_BOXED(1024,16,FLEN)
NAN_BOXED(32257,16,FLEN)
NAN_BOXED(32257,16,FLEN)
NAN_BOXED(1024,16,FLEN)
NAN_BOXED(65109,16,FLEN)
NAN_BOXED(32257,16,FLEN)
NAN_BOXED(1024,16,FLEN)
NAN_BOXED(31745,16,FLEN)
NAN_BOXED(32257,16,FLEN)
NAN_BOXED(1024,16,FLEN)
NAN_BOXED(64853,16,FLEN)
NAN_BOXED(32257,16,FLEN)
NAN_BOXED(1024,16,FLEN)
NAN_BOXED(15360,16,FLEN)
NAN_BOXED(32257,16,FLEN)
NAN_BOXED(1024,16,FLEN)
NAN_BOXED(48128,16,FLEN)
NAN_BOXED(32257,16,FLEN)
NAN_BOXED(33792,16,FLEN)
NAN_BOXED(0,16,FLEN)
NAN_BOXED(32257,16,FLEN)
NAN_BOXED(33792,16,FLEN)
NAN_BOXED(32768,16,FLEN)
NAN_BOXED(32257,16,FLEN)
NAN_BOXED(33792,16,FLEN)
NAN_BOXED(1,16,FLEN)
NAN_BOXED(32257,16,FLEN)
NAN_BOXED(33792,16,FLEN)
NAN_BOXED(32769,16,FLEN)
NAN_BOXED(32257,16,FLEN)
NAN_BOXED(33792,16,FLEN)
NAN_BOXED(2,16,FLEN)
NAN_BOXED(32257,16,FLEN)
NAN_BOXED(33792,16,FLEN)
NAN_BOXED(33790,16,FLEN)
NAN_BOXED(32257,16,FLEN)
NAN_BOXED(33792,16,FLEN)
NAN_BOXED(1023,16,FLEN)
NAN_BOXED(32257,16,FLEN)
NAN_BOXED(33792,16,FLEN)
NAN_BOXED(33791,16,FLEN)
NAN_BOXED(32257,16,FLEN)
NAN_BOXED(33792,16,FLEN)
NAN_BOXED(1024,16,FLEN)
NAN_BOXED(32257,16,FLEN)
NAN_BOXED(33792,16,FLEN)
NAN_BOXED(33792,16,FLEN)
NAN_BOXED(32257,16,FLEN)
NAN_BOXED(33792,16,FLEN)
NAN_BOXED(1025,16,FLEN)
NAN_BOXED(32257,16,FLEN)
NAN_BOXED(33792,16,FLEN)
NAN_BOXED(33877,16,FLEN)
NAN_BOXED(32257,16,FLEN)
NAN_BOXED(33792,16,FLEN)
NAN_BOXED(31743,16,FLEN)
NAN_BOXED(32257,16,FLEN)
NAN_BOXED(33792,16,FLEN)
NAN_BOXED(64511,16,FLEN)
NAN_BOXED(32257,16,FLEN)
NAN_BOXED(33792,16,FLEN)
NAN_BOXED(31744,16,FLEN)
NAN_BOXED(32257,16,FLEN)
NAN_BOXED(33792,16,FLEN)
NAN_BOXED(64512,16,FLEN)
NAN_BOXED(32257,16,FLEN)
NAN_BOXED(33792,16,FLEN)
NAN_BOXED(32256,16,FLEN)
NAN_BOXED(32257,16,FLEN)
NAN_BOXED(33792,16,FLEN)
NAN_BOXED(65024,16,FLEN)
NAN_BOXED(32257,16,FLEN)
NAN_BOXED(33792,16,FLEN)
NAN_BOXED(32257,16,FLEN)
NAN_BOXED(32257,16,FLEN)
NAN_BOXED(33792,16,FLEN)
NAN_BOXED(65109,16,FLEN)
NAN_BOXED(32257,16,FLEN)
NAN_BOXED(33792,16,FLEN)
NAN_BOXED(31745,16,FLEN)
NAN_BOXED(32257,16,FLEN)
NAN_BOXED(33792,16,FLEN)
NAN_BOXED(64853,16,FLEN)
NAN_BOXED(32257,16,FLEN)
NAN_BOXED(33792,16,FLEN)
NAN_BOXED(15360,16,FLEN)
NAN_BOXED(32257,16,FLEN)
NAN_BOXED(33792,16,FLEN)
NAN_BOXED(48128,16,FLEN)
NAN_BOXED(32257,16,FLEN)
NAN_BOXED(1025,16,FLEN)
NAN_BOXED(0,16,FLEN)
NAN_BOXED(32257,16,FLEN)
NAN_BOXED(1025,16,FLEN)
NAN_BOXED(32768,16,FLEN)
NAN_BOXED(32257,16,FLEN)
NAN_BOXED(1025,16,FLEN)
NAN_BOXED(1,16,FLEN)
NAN_BOXED(32257,16,FLEN)
NAN_BOXED(1025,16,FLEN)
NAN_BOXED(32769,16,FLEN)
NAN_BOXED(32257,16,FLEN)
NAN_BOXED(1025,16,FLEN)
NAN_BOXED(2,16,FLEN)
NAN_BOXED(32257,16,FLEN)
NAN_BOXED(1025,16,FLEN)
NAN_BOXED(33790,16,FLEN)
NAN_BOXED(32257,16,FLEN)
NAN_BOXED(1025,16,FLEN)
NAN_BOXED(1023,16,FLEN)
NAN_BOXED(32257,16,FLEN)
NAN_BOXED(1025,16,FLEN)
NAN_BOXED(33791,16,FLEN)
NAN_BOXED(32257,16,FLEN)
NAN_BOXED(1025,16,FLEN)
NAN_BOXED(1024,16,FLEN)
NAN_BOXED(32257,16,FLEN)
NAN_BOXED(1025,16,FLEN)
NAN_BOXED(33792,16,FLEN)
NAN_BOXED(32257,16,FLEN)
NAN_BOXED(1025,16,FLEN)
NAN_BOXED(1025,16,FLEN)
NAN_BOXED(32257,16,FLEN)
NAN_BOXED(1025,16,FLEN)
NAN_BOXED(33877,16,FLEN)
NAN_BOXED(32257,16,FLEN)
NAN_BOXED(1025,16,FLEN)
NAN_BOXED(31743,16,FLEN)
NAN_BOXED(32257,16,FLEN)
NAN_BOXED(1025,16,FLEN)
NAN_BOXED(64511,16,FLEN)
NAN_BOXED(32257,16,FLEN)
NAN_BOXED(1025,16,FLEN)
NAN_BOXED(31744,16,FLEN)
NAN_BOXED(32257,16,FLEN)
NAN_BOXED(1025,16,FLEN)
NAN_BOXED(64512,16,FLEN)
NAN_BOXED(32257,16,FLEN)
NAN_BOXED(1025,16,FLEN)
NAN_BOXED(32256,16,FLEN)
NAN_BOXED(32257,16,FLEN)
NAN_BOXED(1025,16,FLEN)
NAN_BOXED(65024,16,FLEN)
NAN_BOXED(32257,16,FLEN)
NAN_BOXED(1025,16,FLEN)
NAN_BOXED(32257,16,FLEN)
NAN_BOXED(32257,16,FLEN)
NAN_BOXED(1025,16,FLEN)
NAN_BOXED(65109,16,FLEN)
NAN_BOXED(32257,16,FLEN)
NAN_BOXED(1025,16,FLEN)
NAN_BOXED(31745,16,FLEN)
NAN_BOXED(32257,16,FLEN)
NAN_BOXED(1025,16,FLEN)
NAN_BOXED(64853,16,FLEN)
NAN_BOXED(32257,16,FLEN)
NAN_BOXED(1025,16,FLEN)
NAN_BOXED(15360,16,FLEN)
NAN_BOXED(32257,16,FLEN)
NAN_BOXED(1025,16,FLEN)
NAN_BOXED(48128,16,FLEN)
NAN_BOXED(32257,16,FLEN)
NAN_BOXED(33877,16,FLEN)
NAN_BOXED(0,16,FLEN)
NAN_BOXED(32257,16,FLEN)
NAN_BOXED(33877,16,FLEN)
NAN_BOXED(32768,16,FLEN)
NAN_BOXED(32257,16,FLEN)
NAN_BOXED(33877,16,FLEN)
NAN_BOXED(1,16,FLEN)
NAN_BOXED(32257,16,FLEN)
NAN_BOXED(33877,16,FLEN)
NAN_BOXED(32769,16,FLEN)
NAN_BOXED(32257,16,FLEN)
NAN_BOXED(33877,16,FLEN)
NAN_BOXED(2,16,FLEN)
NAN_BOXED(32257,16,FLEN)
NAN_BOXED(33877,16,FLEN)
NAN_BOXED(33790,16,FLEN)
NAN_BOXED(32257,16,FLEN)
NAN_BOXED(33877,16,FLEN)
NAN_BOXED(1023,16,FLEN)
NAN_BOXED(32257,16,FLEN)
NAN_BOXED(33877,16,FLEN)
NAN_BOXED(33791,16,FLEN)
NAN_BOXED(32257,16,FLEN)
NAN_BOXED(33877,16,FLEN)
NAN_BOXED(1024,16,FLEN)
NAN_BOXED(32257,16,FLEN)
NAN_BOXED(33877,16,FLEN)
NAN_BOXED(33792,16,FLEN)
NAN_BOXED(32257,16,FLEN)
NAN_BOXED(33877,16,FLEN)
NAN_BOXED(1025,16,FLEN)
NAN_BOXED(32257,16,FLEN)
NAN_BOXED(33877,16,FLEN)
NAN_BOXED(33877,16,FLEN)
NAN_BOXED(32257,16,FLEN)
NAN_BOXED(33877,16,FLEN)
NAN_BOXED(31743,16,FLEN)
NAN_BOXED(32257,16,FLEN)
NAN_BOXED(33877,16,FLEN)
NAN_BOXED(64511,16,FLEN)
NAN_BOXED(32257,16,FLEN)
NAN_BOXED(33877,16,FLEN)
NAN_BOXED(31744,16,FLEN)
NAN_BOXED(32257,16,FLEN)
NAN_BOXED(33877,16,FLEN)
NAN_BOXED(64512,16,FLEN)
NAN_BOXED(32257,16,FLEN)
NAN_BOXED(33877,16,FLEN)
NAN_BOXED(32256,16,FLEN)
NAN_BOXED(32257,16,FLEN)
NAN_BOXED(33877,16,FLEN)
NAN_BOXED(65024,16,FLEN)
NAN_BOXED(32257,16,FLEN)
NAN_BOXED(33877,16,FLEN)
NAN_BOXED(32257,16,FLEN)
NAN_BOXED(32257,16,FLEN)
NAN_BOXED(33877,16,FLEN)
NAN_BOXED(65109,16,FLEN)
NAN_BOXED(32257,16,FLEN)
NAN_BOXED(33877,16,FLEN)
NAN_BOXED(31745,16,FLEN)
NAN_BOXED(32257,16,FLEN)
NAN_BOXED(33877,16,FLEN)
NAN_BOXED(64853,16,FLEN)
NAN_BOXED(32257,16,FLEN)
NAN_BOXED(33877,16,FLEN)
NAN_BOXED(15360,16,FLEN)
NAN_BOXED(32257,16,FLEN)
NAN_BOXED(33877,16,FLEN)
NAN_BOXED(48128,16,FLEN)
NAN_BOXED(32257,16,FLEN)
NAN_BOXED(31743,16,FLEN)
NAN_BOXED(0,16,FLEN)
NAN_BOXED(32257,16,FLEN)
NAN_BOXED(31743,16,FLEN)
NAN_BOXED(32768,16,FLEN)
NAN_BOXED(32257,16,FLEN)
NAN_BOXED(31743,16,FLEN)
NAN_BOXED(1,16,FLEN)
NAN_BOXED(32257,16,FLEN)
NAN_BOXED(31743,16,FLEN)
NAN_BOXED(32769,16,FLEN)
NAN_BOXED(32257,16,FLEN)
NAN_BOXED(31743,16,FLEN)
NAN_BOXED(2,16,FLEN)
NAN_BOXED(32257,16,FLEN)
NAN_BOXED(31743,16,FLEN)
NAN_BOXED(33790,16,FLEN)
NAN_BOXED(32257,16,FLEN)
NAN_BOXED(31743,16,FLEN)
NAN_BOXED(1023,16,FLEN)
NAN_BOXED(32257,16,FLEN)
NAN_BOXED(31743,16,FLEN)
NAN_BOXED(33791,16,FLEN)
NAN_BOXED(32257,16,FLEN)
NAN_BOXED(31743,16,FLEN)
NAN_BOXED(1024,16,FLEN)
NAN_BOXED(32257,16,FLEN)
NAN_BOXED(31743,16,FLEN)
NAN_BOXED(33792,16,FLEN)
NAN_BOXED(32257,16,FLEN)
NAN_BOXED(31743,16,FLEN)
NAN_BOXED(1025,16,FLEN)
NAN_BOXED(32257,16,FLEN)
NAN_BOXED(31743,16,FLEN)
NAN_BOXED(33877,16,FLEN)
NAN_BOXED(32257,16,FLEN)
NAN_BOXED(31743,16,FLEN)
NAN_BOXED(31743,16,FLEN)
NAN_BOXED(32257,16,FLEN)
NAN_BOXED(31743,16,FLEN)
NAN_BOXED(64511,16,FLEN)
NAN_BOXED(32257,16,FLEN)
NAN_BOXED(31743,16,FLEN)
NAN_BOXED(31744,16,FLEN)
NAN_BOXED(32257,16,FLEN)
NAN_BOXED(31743,16,FLEN)
NAN_BOXED(64512,16,FLEN)
NAN_BOXED(32257,16,FLEN)
NAN_BOXED(31743,16,FLEN)
NAN_BOXED(32256,16,FLEN)
NAN_BOXED(32257,16,FLEN)
NAN_BOXED(31743,16,FLEN)
NAN_BOXED(65024,16,FLEN)
NAN_BOXED(32257,16,FLEN)
NAN_BOXED(31743,16,FLEN)
NAN_BOXED(32257,16,FLEN)
NAN_BOXED(32257,16,FLEN)
NAN_BOXED(31743,16,FLEN)
NAN_BOXED(65109,16,FLEN)
NAN_BOXED(32257,16,FLEN)
NAN_BOXED(31743,16,FLEN)
NAN_BOXED(31745,16,FLEN)
NAN_BOXED(32257,16,FLEN)
NAN_BOXED(31743,16,FLEN)
NAN_BOXED(64853,16,FLEN)
NAN_BOXED(32257,16,FLEN)
NAN_BOXED(31743,16,FLEN)
NAN_BOXED(15360,16,FLEN)
NAN_BOXED(32257,16,FLEN)
NAN_BOXED(31743,16,FLEN)
NAN_BOXED(48128,16,FLEN)
NAN_BOXED(32257,16,FLEN)
NAN_BOXED(64511,16,FLEN)
NAN_BOXED(0,16,FLEN)
NAN_BOXED(32257,16,FLEN)
NAN_BOXED(64511,16,FLEN)
NAN_BOXED(32768,16,FLEN)
NAN_BOXED(32257,16,FLEN)
NAN_BOXED(64511,16,FLEN)
NAN_BOXED(1,16,FLEN)
NAN_BOXED(32257,16,FLEN)
NAN_BOXED(64511,16,FLEN)
NAN_BOXED(32769,16,FLEN)
NAN_BOXED(32257,16,FLEN)
NAN_BOXED(64511,16,FLEN)
NAN_BOXED(2,16,FLEN)
NAN_BOXED(32257,16,FLEN)
NAN_BOXED(64511,16,FLEN)
NAN_BOXED(33790,16,FLEN)
NAN_BOXED(32257,16,FLEN)
NAN_BOXED(64511,16,FLEN)
NAN_BOXED(1023,16,FLEN)
NAN_BOXED(32257,16,FLEN)
NAN_BOXED(64511,16,FLEN)
NAN_BOXED(33791,16,FLEN)
NAN_BOXED(32257,16,FLEN)
NAN_BOXED(64511,16,FLEN)
NAN_BOXED(1024,16,FLEN)
NAN_BOXED(32257,16,FLEN)
NAN_BOXED(64511,16,FLEN)
NAN_BOXED(33792,16,FLEN)
NAN_BOXED(32257,16,FLEN)
NAN_BOXED(64511,16,FLEN)
NAN_BOXED(1025,16,FLEN)
NAN_BOXED(32257,16,FLEN)
NAN_BOXED(64511,16,FLEN)
NAN_BOXED(33877,16,FLEN)
NAN_BOXED(32257,16,FLEN)
NAN_BOXED(64511,16,FLEN)
NAN_BOXED(31743,16,FLEN)
NAN_BOXED(32257,16,FLEN)
NAN_BOXED(64511,16,FLEN)
NAN_BOXED(64511,16,FLEN)
NAN_BOXED(32257,16,FLEN)
NAN_BOXED(64511,16,FLEN)
NAN_BOXED(31744,16,FLEN)
NAN_BOXED(32257,16,FLEN)
NAN_BOXED(64511,16,FLEN)
NAN_BOXED(64512,16,FLEN)
NAN_BOXED(32257,16,FLEN)
NAN_BOXED(64511,16,FLEN)
NAN_BOXED(32256,16,FLEN)
NAN_BOXED(32257,16,FLEN)
NAN_BOXED(64511,16,FLEN)
NAN_BOXED(65024,16,FLEN)
NAN_BOXED(32257,16,FLEN)
NAN_BOXED(64511,16,FLEN)
NAN_BOXED(32257,16,FLEN)
NAN_BOXED(32257,16,FLEN)
NAN_BOXED(64511,16,FLEN)
NAN_BOXED(65109,16,FLEN)
NAN_BOXED(32257,16,FLEN)
NAN_BOXED(64511,16,FLEN)
NAN_BOXED(31745,16,FLEN)
NAN_BOXED(32257,16,FLEN)
NAN_BOXED(64511,16,FLEN)
NAN_BOXED(64853,16,FLEN)
NAN_BOXED(32257,16,FLEN)
NAN_BOXED(64511,16,FLEN)
NAN_BOXED(15360,16,FLEN)
NAN_BOXED(32257,16,FLEN)
NAN_BOXED(64511,16,FLEN)
NAN_BOXED(48128,16,FLEN)
NAN_BOXED(32257,16,FLEN)
NAN_BOXED(31744,16,FLEN)
NAN_BOXED(0,16,FLEN)
NAN_BOXED(32257,16,FLEN)
NAN_BOXED(31744,16,FLEN)
NAN_BOXED(32768,16,FLEN)
NAN_BOXED(32257,16,FLEN)
NAN_BOXED(31744,16,FLEN)
NAN_BOXED(1,16,FLEN)
NAN_BOXED(32257,16,FLEN)
NAN_BOXED(31744,16,FLEN)
NAN_BOXED(32769,16,FLEN)
NAN_BOXED(32257,16,FLEN)
NAN_BOXED(31744,16,FLEN)
NAN_BOXED(2,16,FLEN)
NAN_BOXED(32257,16,FLEN)
NAN_BOXED(31744,16,FLEN)
NAN_BOXED(33790,16,FLEN)
NAN_BOXED(32257,16,FLEN)
NAN_BOXED(31744,16,FLEN)
NAN_BOXED(1023,16,FLEN)
NAN_BOXED(32257,16,FLEN)
NAN_BOXED(31744,16,FLEN)
NAN_BOXED(33791,16,FLEN)
NAN_BOXED(32257,16,FLEN)
NAN_BOXED(31744,16,FLEN)
NAN_BOXED(1024,16,FLEN)
NAN_BOXED(32257,16,FLEN)
NAN_BOXED(31744,16,FLEN)
NAN_BOXED(33792,16,FLEN)
NAN_BOXED(32257,16,FLEN)
NAN_BOXED(31744,16,FLEN)
NAN_BOXED(1025,16,FLEN)
NAN_BOXED(32257,16,FLEN)
NAN_BOXED(31744,16,FLEN)
NAN_BOXED(33877,16,FLEN)
NAN_BOXED(32257,16,FLEN)
NAN_BOXED(31744,16,FLEN)
NAN_BOXED(31743,16,FLEN)
NAN_BOXED(32257,16,FLEN)
NAN_BOXED(31744,16,FLEN)
NAN_BOXED(64511,16,FLEN)
NAN_BOXED(32257,16,FLEN)
NAN_BOXED(31744,16,FLEN)
NAN_BOXED(31744,16,FLEN)
NAN_BOXED(32257,16,FLEN)
NAN_BOXED(31744,16,FLEN)
NAN_BOXED(64512,16,FLEN)
NAN_BOXED(32257,16,FLEN)
NAN_BOXED(31744,16,FLEN)
NAN_BOXED(32256,16,FLEN)
NAN_BOXED(32257,16,FLEN)
NAN_BOXED(31744,16,FLEN)
NAN_BOXED(65024,16,FLEN)
NAN_BOXED(32257,16,FLEN)
NAN_BOXED(31744,16,FLEN)
NAN_BOXED(32257,16,FLEN)
NAN_BOXED(32257,16,FLEN)
NAN_BOXED(31744,16,FLEN)
NAN_BOXED(65109,16,FLEN)
NAN_BOXED(32257,16,FLEN)
NAN_BOXED(31744,16,FLEN)
NAN_BOXED(31745,16,FLEN)
NAN_BOXED(32257,16,FLEN)
NAN_BOXED(31744,16,FLEN)
NAN_BOXED(64853,16,FLEN)
NAN_BOXED(32257,16,FLEN)
NAN_BOXED(31744,16,FLEN)
NAN_BOXED(15360,16,FLEN)
NAN_BOXED(32257,16,FLEN)
NAN_BOXED(31744,16,FLEN)
NAN_BOXED(48128,16,FLEN)
NAN_BOXED(32257,16,FLEN)
NAN_BOXED(64512,16,FLEN)
NAN_BOXED(0,16,FLEN)
NAN_BOXED(32257,16,FLEN)
NAN_BOXED(64512,16,FLEN)
NAN_BOXED(32768,16,FLEN)
NAN_BOXED(32257,16,FLEN)
NAN_BOXED(64512,16,FLEN)
NAN_BOXED(1,16,FLEN)
NAN_BOXED(32257,16,FLEN)
NAN_BOXED(64512,16,FLEN)
NAN_BOXED(32769,16,FLEN)
NAN_BOXED(32257,16,FLEN)
NAN_BOXED(64512,16,FLEN)
NAN_BOXED(2,16,FLEN)
NAN_BOXED(32257,16,FLEN)
NAN_BOXED(64512,16,FLEN)
NAN_BOXED(33790,16,FLEN)
NAN_BOXED(32257,16,FLEN)
NAN_BOXED(64512,16,FLEN)
NAN_BOXED(1023,16,FLEN)
NAN_BOXED(32257,16,FLEN)
NAN_BOXED(64512,16,FLEN)
NAN_BOXED(33791,16,FLEN)
NAN_BOXED(32257,16,FLEN)
NAN_BOXED(64512,16,FLEN)
NAN_BOXED(1024,16,FLEN)
NAN_BOXED(32257,16,FLEN)
NAN_BOXED(64512,16,FLEN)
NAN_BOXED(33792,16,FLEN)
NAN_BOXED(32257,16,FLEN)
NAN_BOXED(64512,16,FLEN)
NAN_BOXED(1025,16,FLEN)
NAN_BOXED(32257,16,FLEN)
NAN_BOXED(64512,16,FLEN)
NAN_BOXED(33877,16,FLEN)
NAN_BOXED(32257,16,FLEN)
NAN_BOXED(64512,16,FLEN)
NAN_BOXED(31743,16,FLEN)
NAN_BOXED(32257,16,FLEN)
NAN_BOXED(64512,16,FLEN)
NAN_BOXED(64511,16,FLEN)
NAN_BOXED(32257,16,FLEN)
NAN_BOXED(64512,16,FLEN)
NAN_BOXED(31744,16,FLEN)
NAN_BOXED(32257,16,FLEN)
NAN_BOXED(64512,16,FLEN)
NAN_BOXED(64512,16,FLEN)
NAN_BOXED(32257,16,FLEN)
NAN_BOXED(64512,16,FLEN)
NAN_BOXED(32256,16,FLEN)
NAN_BOXED(32257,16,FLEN)
NAN_BOXED(64512,16,FLEN)
NAN_BOXED(65024,16,FLEN)
NAN_BOXED(32257,16,FLEN)
NAN_BOXED(64512,16,FLEN)
NAN_BOXED(32257,16,FLEN)
NAN_BOXED(32257,16,FLEN)
NAN_BOXED(64512,16,FLEN)
RVTEST_DATA_END

RVMODEL_DATA_BEGIN
rvtest_sig_begin:
sig_begin_canary:
CANARY;



signature_x1_0:
    .fill 0*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_1:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_2:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_3:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_4:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_5:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_6:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_7:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_8:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_9:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_10:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_11:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_12:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_13:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_14:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_15:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_16:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_17:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_18:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_19:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_20:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_21:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_22:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_23:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_24:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_25:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_26:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_27:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_28:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_29:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_30:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_31:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_32:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_33:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_34:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_35:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_36:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_37:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_38:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_39:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_40:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_41:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_42:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_43:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_44:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_45:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_46:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_47:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_48:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_49:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_50:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_51:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_52:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_53:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_54:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_55:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_56:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_57:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_58:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_59:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_60:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_61:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_62:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_63:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_64:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_65:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_66:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_67:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_68:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_69:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_70:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_71:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_72:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_73:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_74:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_75:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_76:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_77:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_78:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_79:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_80:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_81:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_82:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_83:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_84:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_85:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_86:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_87:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_88:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_89:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_90:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_91:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_92:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_93:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_94:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_95:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_96:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_97:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_98:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_99:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_100:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_101:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_102:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_103:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_104:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_105:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_106:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_107:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_108:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_109:
    .fill 14*((SIGALIGN)/4),4,0xdeadbeef

#ifdef rvtest_mtrap_routine
tsig_begin_canary:
CANARY;

mtrap_sigptr:
    .fill 64*XLEN/32,4,0xdeadbeef

tsig_end_canary:
CANARY;
#endif

#ifdef rvtest_gpr_save

gpr_save:
    .fill 32*XLEN/32,4,0xdeadbeef

#endif


sig_end_canary:
CANARY;
rvtest_sig_end:
RVMODEL_DATA_END
