
// -----------
// This file was generated by riscv_ctg (https://github.com/riscv-software-src/riscv-ctg)
// version   : 0.7.1
// timestamp : Fri Jun 17 14:18:09 2022 GMT
// usage     : riscv_ctg \
//                  -- cgf //                  --cgf /scratch/pawan/work/normalised/RV32F/fnmadd.s.cgf \
 \
//                  -- xlen 32  \
//                  --randomize \
// -----------
//
// -----------
// Copyright (c) 2020. RISC-V International. All rights reserved.
// SPDX-License-Identifier: BSD-3-Clause
// -----------
//
// This assembly file tests the fnmadd.s instruction of the RISC-V RV32F_Zicsr,RV32FD_Zicsr,RV64F_Zicsr,RV64FD_Zicsr extension for the fnmadd_b2 covergroup.
// 
#include "model_test.h"
#include "arch_test.h"
RVTEST_ISA("RV32IF_Zicsr,RV32IFD_Zicsr,RV64IF_Zicsr,RV64IFD_Zicsr")

.section .text.init
.globl rvtest_entry_point
rvtest_entry_point:
RVMODEL_BOOT
RVTEST_CODE_BEGIN

#ifdef TEST_CASE_1

RVTEST_CASE(0,"//check ISA:=regex(.*I.*F.*);def TEST_CASE_1=True;",fnmadd_b2)

RVTEST_FP_ENABLE()
RVTEST_VALBASEUPD(x3,test_dataset_0)
RVTEST_SIGBASE(x1,signature_x1_1)

inst_0:
// rd == rs2 == rs3 != rs1, rs1==f0, rs2==f24, rs3==f24, rd==f24,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x82 and fm2 == 0x300000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000013 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f0; op2:f24; op3:f24; dest:f24; op1val:0x1; op2val:0x41300000;
op3val:0x41300000; valaddr_reg:x3; val_offset:0*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f24, f0, f24, f24, dyn, 0, 0, x3, 0*FLEN/8, x4, x1, x2)

inst_1:
// rs1 == rs2 != rs3 and rs1 == rs2 != rd and rd != rs3, rs1==f25, rs2==f25, rs3==f20, rd==f10,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000002 and fs2 == 0 and fe2 == 0x94 and fm2 == 0x780064 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000033 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f25; op2:f25; op3:f20; dest:f10; op1val:0x2; op2val:0x2;
op3val:0x33; valaddr_reg:x3; val_offset:3*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f10, f25, f25, f20, dyn, 0, 0, x3, 3*FLEN/8, x4, x1, x2)

inst_2:
// rs3 == rd != rs1 and rs3 == rd != rs2 and rs2 != rs1, rs1==f6, rs2==f20, rs3==f12, rd==f12,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000003 and fs2 == 1 and fe2 == 0x85 and fm2 == 0x135555 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000023 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f6; op2:f20; op3:f12; dest:f12; op1val:0x3; op2val:0xc2935555;
op3val:0x23; valaddr_reg:x3; val_offset:6*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f12, f6, f20, f12, dyn, 0, 0, x3, 6*FLEN/8, x4, x1, x2)

inst_3:
// rs2 == rs3 != rs1 and rs2 == rs3 != rd and rd != rs1, rs1==f20, rs2==f0, rs3==f0, rd==f26,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000004 and fs2 == 0 and fe2 == 0x80 and fm2 == 0x600000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x00004f and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f20; op2:f0; op3:f0; dest:f26; op1val:0x4; op2val:0x40600000;
op3val:0x40600000; valaddr_reg:x3; val_offset:9*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f26, f20, f0, f0, dyn, 0, 0, x3, 9*FLEN/8, x4, x1, x2)

inst_4:
// rs1 == rd != rs2 and rs1 == rd != rs3 and rs3 != rs2, rs1==f5, rs2==f17, rs3==f23, rd==f5,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000005 and fs2 == 1 and fe2 == 0x92 and fm2 == 0x4ccbcd and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000051 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f5; op2:f17; op3:f23; dest:f5; op1val:0x5; op2val:0xc94ccbcd;
op3val:0x51; valaddr_reg:x3; val_offset:12*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f5, f5, f17, f23, dyn, 0, 0, x3, 12*FLEN/8, x4, x1, x2)

inst_5:
// rs1 != rs2 and rs1 != rd and rs1 != rs3 and rs2 != rs3 and rs2 != rd and rs3 != rd, rs1==f16, rs2==f11, rs3==f2, rd==f8,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000005 and fs2 == 1 and fe2 == 0x93 and fm2 == 0x4cca9a and fs3 == 0 and fe3 == 0x00 and fm3 == 0x00005f and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f16; op2:f11; op3:f2; dest:f8; op1val:0x5; op2val:0xc9ccca9a;
op3val:0x5f; valaddr_reg:x3; val_offset:15*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f8, f16, f11, f2, dyn, 0, 0, x3, 15*FLEN/8, x4, x1, x2)

inst_6:
// rs2 == rd != rs1 and rs2 == rd != rs3 and rs3 != rs1, rs1==f7, rs2==f4, rs3==f15, rd==f4,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000006 and fs2 == 0 and fe2 == 0x82 and fm2 == 0x6aaaab and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000053 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f7; op2:f4; op3:f15; dest:f4; op1val:0x6; op2val:0x416aaaab;
op3val:0x53; valaddr_reg:x3; val_offset:18*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f4, f7, f4, f15, dyn, 0, 0, x3, 18*FLEN/8, x4, x1, x2)

inst_7:
// rs1 == rs2 == rd != rs3, rs1==f18, rs2==f18, rs3==f6, rd==f18,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000007 and fs2 == 1 and fe2 == 0x93 and fm2 == 0x123f92 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x00005f and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f18; op2:f18; op3:f6; dest:f18; op1val:0x7; op2val:0x7;
op3val:0x5f; valaddr_reg:x3; val_offset:21*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f18, f18, f18, f6, dyn, 0, 0, x3, 21*FLEN/8, x4, x1, x2)

inst_8:
// rs1 == rs3 != rs2 and rs1 == rs3 != rd and rd != rs2, rs1==f3, rs2==f26, rs3==f3, rd==f13,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000008 and fs2 == 1 and fe2 == 0x7f and fm2 == 0x100000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000018 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f3; op2:f26; op3:f3; dest:f13; op1val:0x8; op2val:0xbf900000;
op3val:0x8; valaddr_reg:x3; val_offset:24*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f13, f3, f26, f3, dyn, 0, 0, x3, 24*FLEN/8, x4, x1, x2)

inst_9:
// rs1 == rd == rs3 != rs2, rs1==f9, rs2==f19, rs3==f9, rd==f9,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000008 and fs2 == 1 and fe2 == 0x86 and fm2 == 0x7d0000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000019 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f9; op2:f19; op3:f9; dest:f9; op1val:0x8; op2val:0xc37d0000;
op3val:0x8; valaddr_reg:x3; val_offset:27*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f9, f9, f19, f9, dyn, 0, 0, x3, 27*FLEN/8, x4, x1, x2)

inst_10:
// rs1 == rs2 == rs3 != rd, rs1==f29, rs2==f29, rs3==f29, rd==f2,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000009 and fs2 == 0 and fe2 == 0x8e and fm2 == 0x63928e and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000026 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f29; op2:f29; op3:f29; dest:f2; op1val:0x9; op2val:0x9;
op3val:0x9; valaddr_reg:x3; val_offset:30*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f2, f29, f29, f29, dyn, 0, 0, x3, 30*FLEN/8, x4, x1, x2)

inst_11:
// rs1 == rs2 == rs3 == rd, rs1==f30, rs2==f30, rs3==f30, rd==f30,fs1 == 0 and fe1 == 0x00 and fm1 == 0x00000a and fs2 == 1 and fe2 == 0x91 and fm2 == 0x4ccc3a and fs3 == 0 and fe3 == 0x00 and fm3 == 0x00002d and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f30; op3:f30; dest:f30; op1val:0xa; op2val:0xa;
op3val:0xa; valaddr_reg:x3; val_offset:33*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f30, f30, f30, f30, dyn, 0, 0, x3, 33*FLEN/8, x4, x1, x2)

inst_12:
// rs1==f2, rs2==f27, rs3==f14, rd==f16,fs1 == 0 and fe1 == 0x00 and fm1 == 0x00000a and fs2 == 1 and fe2 == 0x92 and fm2 == 0x19997d and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000011 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f2; op2:f27; op3:f14; dest:f16; op1val:0xa; op2val:0xc919997d;
op3val:0x11; valaddr_reg:x3; val_offset:36*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f16, f2, f27, f14, dyn, 0, 0, x3, 36*FLEN/8, x4, x1, x2)

inst_13:
// rs1==f17, rs2==f2, rs3==f25, rd==f7,fs1 == 0 and fe1 == 0x00 and fm1 == 0x00000a and fs2 == 1 and fe2 == 0x92 and fm2 == 0x4bffdd and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000015 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f17; op2:f2; op3:f25; dest:f7; op1val:0xa; op2val:0xc94bffdd;
op3val:0x15; valaddr_reg:x3; val_offset:39*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f7, f17, f2, f25, dyn, 0, 0, x3, 39*FLEN/8, x4, x1, x2)

inst_14:
// rs1==f13, rs2==f8, rs3==f18, rd==f21,fs1 == 0 and fe1 == 0x00 and fm1 == 0x00000b and fs2 == 0 and fe2 == 0x83 and fm2 == 0x4a2e8c and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000015 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f13; op2:f8; op3:f18; dest:f21; op1val:0xb; op2val:0x41ca2e8c;
op3val:0x15; valaddr_reg:x3; val_offset:42*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f21, f13, f8, f18, dyn, 0, 0, x3, 42*FLEN/8, x4, x1, x2)

inst_15:
// rs1==f28, rs2==f9, rs3==f22, rd==f27,fs1 == 0 and fe1 == 0x00 and fm1 == 0x00000b and fs2 == 0 and fe2 == 0x91 and fm2 == 0x3a2f4c and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000041 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f28; op2:f9; op3:f22; dest:f27; op1val:0xb; op2val:0x48ba2f4c;
op3val:0x41; valaddr_reg:x3; val_offset:45*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f27, f28, f9, f22, dyn, 0, 0, x3, 45*FLEN/8, x4, x1, x2)

inst_16:
// rs1==f24, rs2==f5, rs3==f16, rd==f22,fs1 == 0 and fe1 == 0x00 and fm1 == 0x00000c and fs2 == 1 and fe2 == 0x8e and fm2 == 0x2aa6c0 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x00002f and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f24; op2:f5; op3:f16; dest:f22; op1val:0xc; op2val:0xc72aa6c0;
op3val:0x2f; valaddr_reg:x3; val_offset:48*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f22, f24, f5, f16, dyn, 0, 0, x3, 48*FLEN/8, x4, x1, x2)

inst_17:
// rs1==f12, rs2==f28, rs3==f13, rd==f0,fs1 == 0 and fe1 == 0x00 and fm1 == 0x00000d and fs2 == 0 and fe2 == 0x7e and fm2 == 0x44ec4f and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000006 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f12; op2:f28; op3:f13; dest:f0; op1val:0xd; op2val:0x3f44ec4f;
op3val:0x6; valaddr_reg:x3; val_offset:51*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f0, f12, f28, f13, dyn, 0, 0, x3, 51*FLEN/8, x4, x1, x2)

inst_18:
// rs1==f22, rs2==f15, rs3==f5, rd==f23,fs1 == 0 and fe1 == 0x00 and fm1 == 0x00000d and fs2 == 1 and fe2 == 0x8c and fm2 == 0x1d7b62 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000030 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f22; op2:f15; op3:f5; dest:f23; op1val:0xd; op2val:0xc61d7b62;
op3val:0x30; valaddr_reg:x3; val_offset:54*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f23, f22, f15, f5, dyn, 0, 0, x3, 54*FLEN/8, x4, x1, x2)

inst_19:
// rs1==f8, rs2==f7, rs3==f17, rd==f19,fs1 == 0 and fe1 == 0x00 and fm1 == 0x00000d and fs2 == 1 and fe2 == 0x91 and fm2 == 0x1d88ea and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000061 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f8; op2:f7; op3:f17; dest:f19; op1val:0xd; op2val:0xc89d88ea;
op3val:0x61; valaddr_reg:x3; val_offset:57*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f19, f8, f7, f17, dyn, 0, 0, x3, 57*FLEN/8, x4, x1, x2)

inst_20:
// rs1==f21, rs2==f14, rs3==f19, rd==f3,fs1 == 0 and fe1 == 0x00 and fm1 == 0x00000f and fs2 == 0 and fe2 == 0x8b and fm2 == 0x08b222 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x00004e and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f21; op2:f14; op3:f19; dest:f3; op1val:0xf; op2val:0x4588b222;
op3val:0x4e; valaddr_reg:x3; val_offset:60*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f3, f21, f14, f19, dyn, 0, 0, x3, 60*FLEN/8, x4, x1, x2)

inst_21:
// rs1==f27, rs2==f22, rs3==f7, rd==f25,fs1 == 0 and fe1 == 0x00 and fm1 == 0x00000f and fs2 == 1 and fe2 == 0x92 and fm2 == 0x06662e and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000034 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f27; op2:f22; op3:f7; dest:f25; op1val:0xf; op2val:0xc906662e;
op3val:0x34; valaddr_reg:x3; val_offset:63*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f25, f27, f22, f7, dyn, 0, 0, x3, 63*FLEN/8, x4, x1, x2)

inst_22:
// rs1==f31, rs2==f23, rs3==f10, rd==f14,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000010 and fs2 == 0 and fe2 == 0x88 and fm2 == 0x003000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x00000c and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f31; op2:f23; op3:f10; dest:f14; op1val:0x10; op2val:0x44003000;
op3val:0xc; valaddr_reg:x3; val_offset:66*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f14, f31, f23, f10, dyn, 0, 0, x3, 66*FLEN/8, x4, x1, x2)

inst_23:
// rs1==f11, rs2==f10, rs3==f27, rd==f15,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000011 and fs2 == 0 and fe2 == 0x82 and fm2 == 0x43c3c4 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x00004f and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f11; op2:f10; op3:f27; dest:f15; op1val:0x11; op2val:0x4143c3c4;
op3val:0x4f; valaddr_reg:x3; val_offset:69*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f15, f11, f10, f27, dyn, 0, 0, x3, 69*FLEN/8, x4, x1, x2)

inst_24:
// rs1==f14, rs2==f12, rs3==f31, rd==f6,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000011 and fs2 == 0 and fe2 == 0x91 and fm2 == 0x70ed91 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000036 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f14; op2:f12; op3:f31; dest:f6; op1val:0x11; op2val:0x48f0ed91;
op3val:0x36; valaddr_reg:x3; val_offset:72*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f6, f14, f12, f31, dyn, 0, 0, x3, 72*FLEN/8, x4, x1, x2)

inst_25:
// rs1==f23, rs2==f6, rs3==f1, rd==f29,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000012 and fs2 == 0 and fe2 == 0x8f and fm2 == 0x63905c and fs3 == 0 and fe3 == 0x00 and fm3 == 0x00004d and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f23; op2:f6; op3:f1; dest:f29; op1val:0x12; op2val:0x47e3905c;
op3val:0x4d; valaddr_reg:x3; val_offset:75*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f29, f23, f6, f1, dyn, 0, 0, x3, 75*FLEN/8, x4, x1, x2)

inst_26:
// rs1==f4, rs2==f3, rs3==f8, rd==f11,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000014 and fs2 == 1 and fe2 == 0x86 and fm2 == 0x4b199a and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000023 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f4; op2:f3; op3:f8; dest:f11; op1val:0x14; op2val:0xc34b199a;
op3val:0x23; valaddr_reg:x3; val_offset:78*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f11, f4, f3, f8, dyn, 0, 0, x3, 78*FLEN/8, x4, x1, x2)

inst_27:
// rs1==f26, rs2==f1, rs3==f4, rd==f17,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000015 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x492492 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000026 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f26; op2:f1; op3:f4; dest:f17; op1val:0x15; op2val:0x3fc92492;
op3val:0x26; valaddr_reg:x3; val_offset:81*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f17, f26, f1, f4, dyn, 0, 0, x3, 81*FLEN/8, x4, x1, x2)

inst_28:
// rs1==f1, rs2==f16, rs3==f11, rd==f31,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000017 and fs2 == 1 and fe2 == 0x91 and fm2 == 0x32133c and fs3 == 0 and fe3 == 0x00 and fm3 == 0x00002c and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f1; op2:f16; op3:f11; dest:f31; op1val:0x17; op2val:0xc8b2133c;
op3val:0x2c; valaddr_reg:x3; val_offset:84*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f1, f16, f11, dyn, 0, 0, x3, 84*FLEN/8, x4, x1, x2)

inst_29:
// rs1==f10, rs2==f21, rs3==f28, rd==f1,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000018 and fs2 == 0 and fe2 == 0x91 and fm2 == 0x2aaad0 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000025 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f10; op2:f21; op3:f28; dest:f1; op1val:0x18; op2val:0x48aaaad0;
op3val:0x25; valaddr_reg:x3; val_offset:87*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f1, f10, f21, f28, dyn, 0, 0, x3, 87*FLEN/8, x4, x1, x2)

inst_30:
// rs1==f15, rs2==f31, rs3==f26, rd==f28,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000018 and fs2 == 0 and fe2 == 0x91 and fm2 == 0x2aab01 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000044 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f15; op2:f31; op3:f26; dest:f28; op1val:0x18; op2val:0x48aaab01;
op3val:0x44; valaddr_reg:x3; val_offset:90*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f28, f15, f31, f26, dyn, 0, 0, x3, 90*FLEN/8, x4, x1, x2)

inst_31:
// rs1==f19, rs2==f13, rs3==f21, rd==f20,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000019 and fs2 == 0 and fe2 == 0x88 and fm2 == 0x246b85 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000039 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f19; op2:f13; op3:f21; dest:f20; op1val:0x19; op2val:0x44246b85;
op3val:0x39; valaddr_reg:x3; val_offset:93*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f20, f19, f13, f21, dyn, 0, 0, x3, 93*FLEN/8, x4, x1, x2)

inst_32:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000019 and fs2 == 0 and fe2 == 0x91 and fm2 == 0x2333af and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000062 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x19; op2val:0x48a333af;
op3val:0x62; valaddr_reg:x3; val_offset:96*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 96*FLEN/8, x4, x1, x2)

inst_33:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000019 and fs2 == 1 and fe2 == 0x87 and fm2 == 0x226148 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000049 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x19; op2val:0xc3a26148;
op3val:0x49; valaddr_reg:x3; val_offset:99*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 99*FLEN/8, x4, x1, x2)

inst_34:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x00001a and fs2 == 0 and fe2 == 0x80 and fm2 == 0x600000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x00005a and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x1a; op2val:0x40600000;
op3val:0x5a; valaddr_reg:x3; val_offset:102*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 102*FLEN/8, x4, x1, x2)

inst_35:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x00001a and fs2 == 0 and fe2 == 0x8d and fm2 == 0x1d8d9e and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000031 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x1a; op2val:0x469d8d9e;
op3val:0x31; valaddr_reg:x3; val_offset:105*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 105*FLEN/8, x4, x1, x2)

inst_36:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x00001b and fs2 == 0 and fe2 == 0x90 and fm2 == 0x17b4fb and fs3 == 0 and fe3 == 0x00 and fm3 == 0x00005a and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x1b; op2val:0x4817b4fb;
op3val:0x5a; valaddr_reg:x3; val_offset:108*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 108*FLEN/8, x4, x1, x2)

inst_37:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x00001b and fs2 == 1 and fe2 == 0x91 and fm2 == 0x178dcd and fs3 == 0 and fe3 == 0x00 and fm3 == 0x00005a and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x1b; op2val:0xc8978dcd;
op3val:0x5a; valaddr_reg:x3; val_offset:111*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 111*FLEN/8, x4, x1, x2)

inst_38:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x00001d and fs2 == 0 and fe2 == 0x91 and fm2 == 0x0d3da0 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x00005a and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x1d; op2val:0x488d3da0;
op3val:0x5a; valaddr_reg:x3; val_offset:114*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 114*FLEN/8, x4, x1, x2)

inst_39:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x00001f and fs2 == 0 and fe2 == 0x91 and fm2 == 0x0410cd and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000048 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x1f; op2val:0x488410cd;
op3val:0x48; valaddr_reg:x3; val_offset:117*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 117*FLEN/8, x4, x1, x2)

inst_40:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000020 and fs2 == 0 and fe2 == 0x84 and fm2 == 0x09c000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x00004e and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x20; op2val:0x4209c000;
op3val:0x4e; valaddr_reg:x3; val_offset:120*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 120*FLEN/8, x4, x1, x2)

inst_41:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000020 and fs2 == 1 and fe2 == 0x8d and fm2 == 0x7ffb30 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x00004e and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x20; op2val:0xc6fffb30;
op3val:0x4e; valaddr_reg:x3; val_offset:123*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 123*FLEN/8, x4, x1, x2)

inst_42:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000020 and fs2 == 1 and fe2 == 0x90 and fm2 == 0x7fff22 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x00004e and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x20; op2val:0xc87fff22;
op3val:0x4e; valaddr_reg:x3; val_offset:126*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 126*FLEN/8, x4, x1, x2)

inst_43:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000022 and fs2 == 0 and fe2 == 0x79 and fm2 == 0x70f0f1 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000005 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x22; op2val:0x3cf0f0f1;
op3val:0x5; valaddr_reg:x3; val_offset:129*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 129*FLEN/8, x4, x1, x2)

inst_44:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000022 and fs2 == 0 and fe2 == 0x84 and fm2 == 0x027878 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000054 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x22; op2val:0x42027878;
op3val:0x54; valaddr_reg:x3; val_offset:132*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 132*FLEN/8, x4, x1, x2)

inst_45:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000024 and fs2 == 0 and fe2 == 0x8a and fm2 == 0x63aa39 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x00003e and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x24; op2val:0x4563aa39;
op3val:0x3e; valaddr_reg:x3; val_offset:135*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 135*FLEN/8, x4, x1, x2)

inst_46:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000024 and fs2 == 1 and fe2 == 0x90 and fm2 == 0x638dc7 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x00003d and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x24; op2val:0xc8638dc7;
op3val:0x3d; valaddr_reg:x3; val_offset:138*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 138*FLEN/8, x4, x1, x2)

inst_47:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000024 and fs2 == 1 and fe2 == 0x90 and fm2 == 0x638df5 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000024 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x24; op2val:0xc8638df5;
op3val:0x24; valaddr_reg:x3; val_offset:141*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 141*FLEN/8, x4, x1, x2)

inst_48:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000028 and fs2 == 0 and fe2 == 0x8b and fm2 == 0x4cdf66 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x00005d and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x28; op2val:0x45ccdf66;
op3val:0x5d; valaddr_reg:x3; val_offset:144*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 144*FLEN/8, x4, x1, x2)

inst_49:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000029 and fs2 == 1 and fe2 == 0x7e and fm2 == 0x3512bb and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000063 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x29; op2val:0xbf3512bb;
op3val:0x63; valaddr_reg:x3; val_offset:147*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 147*FLEN/8, x4, x1, x2)

inst_50:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000029 and fs2 == 1 and fe2 == 0x8e and fm2 == 0x47cd9c and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000013 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x29; op2val:0xc747cd9c;
op3val:0x13; valaddr_reg:x3; val_offset:150*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 150*FLEN/8, x4, x1, x2)

inst_51:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x00002a and fs2 == 0 and fe2 == 0x90 and fm2 == 0x418662 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000031 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x2a; op2val:0x48418662;
op3val:0x31; valaddr_reg:x3; val_offset:153*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 153*FLEN/8, x4, x1, x2)

inst_52:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x00002e and fs2 == 0 and fe2 == 0x85 and fm2 == 0x35642d and fs3 == 0 and fe3 == 0x00 and fm3 == 0x00004c and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x2e; op2val:0x42b5642d;
op3val:0x4c; valaddr_reg:x3; val_offset:156*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 156*FLEN/8, x4, x1, x2)

inst_53:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x00002f and fs2 == 0 and fe2 == 0x8d and fm2 == 0x2e4ddf and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000025 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x2f; op2val:0x46ae4ddf;
op3val:0x25; valaddr_reg:x3; val_offset:159*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 159*FLEN/8, x4, x1, x2)

inst_54:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x00002f and fs2 == 0 and fe2 == 0x8e and fm2 == 0x2e4c62 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000005 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x2f; op2val:0x472e4c62;
op3val:0x5; valaddr_reg:x3; val_offset:162*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 162*FLEN/8, x4, x1, x2)

inst_55:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x00002f and fs2 == 1 and fe2 == 0x8b and fm2 == 0x2e4931 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000013 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x2f; op2val:0xc5ae4931;
op3val:0x13; valaddr_reg:x3; val_offset:165*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 165*FLEN/8, x4, x1, x2)

inst_56:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000030 and fs2 == 1 and fe2 == 0x82 and fm2 == 0x1b5555 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x00002f and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x30; op2val:0xc11b5555;
op3val:0x2f; valaddr_reg:x3; val_offset:168*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 168*FLEN/8, x4, x1, x2)

inst_57:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000030 and fs2 == 1 and fe2 == 0x90 and fm2 == 0x2aa54d and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000005 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x30; op2val:0xc82aa54d;
op3val:0x5; valaddr_reg:x3; val_offset:171*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 171*FLEN/8, x4, x1, x2)

inst_58:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000030 and fs2 == 1 and fe2 == 0x90 and fm2 == 0x2aaa98 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000005 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x30; op2val:0xc82aaa98;
op3val:0x5; valaddr_reg:x3; val_offset:174*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 174*FLEN/8, x4, x1, x2)

inst_59:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000032 and fs2 == 0 and fe2 == 0x90 and fm2 == 0x23d6dc and fs3 == 0 and fe3 == 0x00 and fm3 == 0x00001d and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x32; op2val:0x4823d6dc;
op3val:0x1d; valaddr_reg:x3; val_offset:177*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 177*FLEN/8, x4, x1, x2)

inst_60:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000035 and fs2 == 1 and fe2 == 0x8d and fm2 == 0x1a8fa9 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000021 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x35; op2val:0xc69a8fa9;
op3val:0x21; valaddr_reg:x3; val_offset:180*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 180*FLEN/8, x4, x1, x2)

inst_61:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000037 and fs2 == 1 and fe2 == 0x87 and fm2 == 0x14561c and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000044 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x37; op2val:0xc394561c;
op3val:0x44; valaddr_reg:x3; val_offset:183*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 183*FLEN/8, x4, x1, x2)

inst_62:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000037 and fs2 == 1 and fe2 == 0x8b and fm2 == 0x14ebc8 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x00002b and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x37; op2val:0xc594ebc8;
op3val:0x2b; valaddr_reg:x3; val_offset:186*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 186*FLEN/8, x4, x1, x2)

inst_63:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000038 and fs2 == 0 and fe2 == 0x84 and fm2 == 0x151249 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000027 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x38; op2val:0x42151249;
op3val:0x27; valaddr_reg:x3; val_offset:189*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 189*FLEN/8, x4, x1, x2)

inst_64:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000038 and fs2 == 1 and fe2 == 0x90 and fm2 == 0x11ffcd and fs3 == 0 and fe3 == 0x00 and fm3 == 0x00002c and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x38; op2val:0xc811ffcd;
op3val:0x2c; valaddr_reg:x3; val_offset:192*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 192*FLEN/8, x4, x1, x2)

inst_65:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000038 and fs2 == 1 and fe2 == 0x90 and fm2 == 0x1248de and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000039 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x38; op2val:0xc81248de;
op3val:0x39; valaddr_reg:x3; val_offset:195*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 195*FLEN/8, x4, x1, x2)

inst_66:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000039 and fs2 == 1 and fe2 == 0x8e and fm2 == 0x0fb690 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x00005a and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x39; op2val:0xc70fb690;
op3val:0x5a; valaddr_reg:x3; val_offset:198*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 198*FLEN/8, x4, x1, x2)

inst_67:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x00003a and fs2 == 0 and fe2 == 0x84 and fm2 == 0x11b961 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000040 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3a; op2val:0x4211b961;
op3val:0x40; valaddr_reg:x3; val_offset:201*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 201*FLEN/8, x4, x1, x2)

inst_68:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x00003a and fs2 == 0 and fe2 == 0x89 and fm2 == 0x0d6612 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000048 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3a; op2val:0x448d6612;
op3val:0x48; valaddr_reg:x3; val_offset:204*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 204*FLEN/8, x4, x1, x2)

inst_69:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x00003c and fs2 == 1 and fe2 == 0x8f and fm2 == 0x7fff31 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000060 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3c; op2val:0xc7ffff31;
op3val:0x60; valaddr_reg:x3; val_offset:207*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 207*FLEN/8, x4, x1, x2)

inst_70:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x00003d and fs2 == 0 and fe2 == 0x7f and fm2 == 0x0a7de7 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000062 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3d; op2val:0x3f8a7de7;
op3val:0x62; valaddr_reg:x3; val_offset:210*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 210*FLEN/8, x4, x1, x2)

inst_71:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x00003d and fs2 == 1 and fe2 == 0x89 and fm2 == 0x063c54 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x00001e and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3d; op2val:0xc4863c54;
op3val:0x1e; valaddr_reg:x3; val_offset:213*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 213*FLEN/8, x4, x1, x2)

inst_72:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x00003e and fs2 == 0 and fe2 == 0x7f and fm2 == 0x0e739d and fs3 == 0 and fe3 == 0x00 and fm3 == 0x00003c and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3e; op2val:0x3f8e739d;
op3val:0x3c; valaddr_reg:x3; val_offset:216*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 216*FLEN/8, x4, x1, x2)

inst_73:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x00003e and fs2 == 0 and fe2 == 0x88 and fm2 == 0x045ce7 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000039 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3e; op2val:0x44045ce7;
op3val:0x39; valaddr_reg:x3; val_offset:219*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 219*FLEN/8, x4, x1, x2)

inst_74:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x00003e and fs2 == 0 and fe2 == 0x8d and fm2 == 0x0421f8 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x00001d and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3e; op2val:0x468421f8;
op3val:0x1d; valaddr_reg:x3; val_offset:222*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 222*FLEN/8, x4, x1, x2)

inst_75:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x00003f and fs2 == 0 and fe2 == 0x7e and fm2 == 0x679e7a and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000019 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3f; op2val:0x3f679e7a;
op3val:0x19; valaddr_reg:x3; val_offset:225*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 225*FLEN/8, x4, x1, x2)

inst_76:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x00003f and fs2 == 0 and fe2 == 0x7f and fm2 == 0x38e38e and fs3 == 0 and fe3 == 0x00 and fm3 == 0x00005e and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3f; op2val:0x3fb8e38e;
op3val:0x5e; valaddr_reg:x3; val_offset:228*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 228*FLEN/8, x4, x1, x2)

inst_77:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x00003f and fs2 == 0 and fe2 == 0x7f and fm2 == 0x430c31 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000062 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3f; op2val:0x3fc30c31;
op3val:0x62; valaddr_reg:x3; val_offset:231*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 231*FLEN/8, x4, x1, x2)

inst_78:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x00003f and fs2 == 1 and fe2 == 0x81 and fm2 == 0x76db6e and fs3 == 0 and fe3 == 0x00 and fm3 == 0x00001a and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3f; op2val:0xc0f6db6e;
op3val:0x1a; valaddr_reg:x3; val_offset:234*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 234*FLEN/8, x4, x1, x2)

inst_79:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x00003f and fs2 == 1 and fe2 == 0x88 and fm2 == 0x01fefc and fs3 == 0 and fe3 == 0x00 and fm3 == 0x00000a and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3f; op2val:0xc401fefc;
op3val:0xa; valaddr_reg:x3; val_offset:237*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 237*FLEN/8, x4, x1, x2)

inst_80:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000040 and fs2 == 1 and fe2 == 0x82 and fm2 == 0x6d4000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x00004c and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x40; op2val:0xc16d4000;
op3val:0x4c; valaddr_reg:x3; val_offset:240*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 240*FLEN/8, x4, x1, x2)

inst_81:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000040 and fs2 == 1 and fe2 == 0x8f and fm2 == 0x5fff5a and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000052 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x40; op2val:0xc7dfff5a;
op3val:0x52; valaddr_reg:x3; val_offset:243*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 243*FLEN/8, x4, x1, x2)

inst_82:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000041 and fs2 == 0 and fe2 == 0x81 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000004 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x41; op2val:0x40800000;
op3val:0x4; valaddr_reg:x3; val_offset:246*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 246*FLEN/8, x4, x1, x2)

inst_83:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000041 and fs2 == 0 and fe2 == 0x86 and fm2 == 0x7d6666 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000057 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x41; op2val:0x437d6666;
op3val:0x57; valaddr_reg:x3; val_offset:249*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 249*FLEN/8, x4, x1, x2)

inst_84:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000041 and fs2 == 0 and fe2 == 0x8f and fm2 == 0x7c1010 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000049 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x41; op2val:0x47fc1010;
op3val:0x49; valaddr_reg:x3; val_offset:252*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 252*FLEN/8, x4, x1, x2)

inst_85:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000042 and fs2 == 0 and fe2 == 0x80 and fm2 == 0x05d174 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x00004a and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x42; op2val:0x4005d174;
op3val:0x4a; valaddr_reg:x3; val_offset:255*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 255*FLEN/8, x4, x1, x2)

inst_86:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000043 and fs2 == 0 and fe2 == 0x8f and fm2 == 0x748991 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000004 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x43; op2val:0x47f48991;
op3val:0x4; valaddr_reg:x3; val_offset:258*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 258*FLEN/8, x4, x1, x2)

inst_87:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000044 and fs2 == 0 and fe2 == 0x87 and fm2 == 0x7121e2 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x00001a and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x44; op2val:0x43f121e2;
op3val:0x1a; valaddr_reg:x3; val_offset:261*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 261*FLEN/8, x4, x1, x2)

inst_88:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000044 and fs2 == 0 and fe2 == 0x8f and fm2 == 0x61e266 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000047 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x44; op2val:0x47e1e266;
op3val:0x47; valaddr_reg:x3; val_offset:264*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 264*FLEN/8, x4, x1, x2)

inst_89:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000044 and fs2 == 0 and fe2 == 0x8f and fm2 == 0x6d2d97 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000039 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x44; op2val:0x47ed2d97;
op3val:0x39; valaddr_reg:x3; val_offset:267*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 267*FLEN/8, x4, x1, x2)

inst_90:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000045 and fs2 == 1 and fe2 == 0x83 and fm2 == 0x655555 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000046 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x45; op2val:0xc1e55555;
op3val:0x46; valaddr_reg:x3; val_offset:270*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 270*FLEN/8, x4, x1, x2)

inst_91:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000045 and fs2 == 1 and fe2 == 0x8f and fm2 == 0x6d7162 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000060 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x45; op2val:0xc7ed7162;
op3val:0x60; valaddr_reg:x3; val_offset:273*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 273*FLEN/8, x4, x1, x2)

inst_92:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000047 and fs2 == 1 and fe2 == 0x86 and fm2 == 0x657e32 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x00005a and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x47; op2val:0xc3657e32;
op3val:0x5a; valaddr_reg:x3; val_offset:276*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 276*FLEN/8, x4, x1, x2)

inst_93:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000047 and fs2 == 1 and fe2 == 0x8f and fm2 == 0x5f8c7c and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000012 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x47; op2val:0xc7df8c7c;
op3val:0x12; valaddr_reg:x3; val_offset:279*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 279*FLEN/8, x4, x1, x2)

inst_94:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000048 and fs2 == 1 and fe2 == 0x7b and fm2 == 0x638e39 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000001 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x48; op2val:0xbde38e39;
op3val:0x1; valaddr_reg:x3; val_offset:282*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 282*FLEN/8, x4, x1, x2)

inst_95:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000049 and fs2 == 0 and fe2 == 0x8f and fm2 == 0x600056 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000032 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x49; op2val:0x47e00056;
op3val:0x32; valaddr_reg:x3; val_offset:285*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 285*FLEN/8, x4, x1, x2)

inst_96:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000049 and fs2 == 0 and fe2 == 0x8f and fm2 == 0x606f17 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x00005c and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x49; op2val:0x47e06f17;
op3val:0x5c; valaddr_reg:x3; val_offset:288*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 288*FLEN/8, x4, x1, x2)

inst_97:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000049 and fs2 == 1 and fe2 == 0x7f and fm2 == 0x47e3f2 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x00000f and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x49; op2val:0xbfc7e3f2;
op3val:0xf; valaddr_reg:x3; val_offset:291*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 291*FLEN/8, x4, x1, x2)

inst_98:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x00004a and fs2 == 0 and fe2 == 0x7c and fm2 == 0x0a60dd and fs3 == 0 and fe3 == 0x00 and fm3 == 0x00000b and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x4a; op2val:0x3e0a60dd;
op3val:0xb; valaddr_reg:x3; val_offset:294*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 294*FLEN/8, x4, x1, x2)

inst_99:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x00004a and fs2 == 0 and fe2 == 0x8f and fm2 == 0x5d306f and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000001 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x4a; op2val:0x47dd306f;
op3val:0x1; valaddr_reg:x3; val_offset:297*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 297*FLEN/8, x4, x1, x2)

inst_100:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x00004c and fs2 == 0 and fe2 == 0x7d and fm2 == 0x650d79 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x00001a and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x4c; op2val:0x3ee50d79;
op3val:0x1a; valaddr_reg:x3; val_offset:300*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 300*FLEN/8, x4, x1, x2)

inst_101:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x00004f and fs2 == 1 and fe2 == 0x85 and fm2 == 0x4f5dfa and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000002 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x4f; op2val:0xc2cf5dfa;
op3val:0x2; valaddr_reg:x3; val_offset:303*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 303*FLEN/8, x4, x1, x2)

inst_102:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000050 and fs2 == 0 and fe2 == 0x7e and fm2 == 0x033333 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x00003a and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x50; op2val:0x3f033333;
op3val:0x3a; valaddr_reg:x3; val_offset:306*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 306*FLEN/8, x4, x1, x2)

inst_103:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000050 and fs2 == 0 and fe2 == 0x81 and fm2 == 0x6d999a and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000051 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x50; op2val:0x40ed999a;
op3val:0x51; valaddr_reg:x3; val_offset:309*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 309*FLEN/8, x4, x1, x2)

inst_104:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000051 and fs2 == 0 and fe2 == 0x7d and fm2 == 0x69e065 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000004 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x51; op2val:0x3ee9e065;
op3val:0x4; valaddr_reg:x3; val_offset:312*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 312*FLEN/8, x4, x1, x2)

inst_105:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000052 and fs2 == 0 and fe2 == 0x7d and fm2 == 0x79c190 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000026 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x52; op2val:0x3ef9c190;
op3val:0x26; valaddr_reg:x3; val_offset:315*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 315*FLEN/8, x4, x1, x2)

inst_106:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000052 and fs2 == 0 and fe2 == 0x81 and fm2 == 0x5a2577 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x00002f and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x52; op2val:0x40da2577;
op3val:0x2f; valaddr_reg:x3; val_offset:318*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 318*FLEN/8, x4, x1, x2)

inst_107:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000052 and fs2 == 0 and fe2 == 0x85 and fm2 == 0x4844af and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000012 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x52; op2val:0x42c844af;
op3val:0x12; valaddr_reg:x3; val_offset:321*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 321*FLEN/8, x4, x1, x2)

inst_108:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000052 and fs2 == 1 and fe2 == 0x8f and fm2 == 0x47cd77 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x00001f and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x52; op2val:0xc7c7cd77;
op3val:0x1f; valaddr_reg:x3; val_offset:324*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 324*FLEN/8, x4, x1, x2)

inst_109:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000053 and fs2 == 0 and fe2 == 0x7e and fm2 == 0x1b19a3 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000033 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x53; op2val:0x3f1b19a3;
op3val:0x33; valaddr_reg:x3; val_offset:327*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 327*FLEN/8, x4, x1, x2)

inst_110:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000053 and fs2 == 0 and fe2 == 0x80 and fm2 == 0x2818ad and fs3 == 0 and fe3 == 0x00 and fm3 == 0x00005a and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x53; op2val:0x402818ad;
op3val:0x5a; valaddr_reg:x3; val_offset:330*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 330*FLEN/8, x4, x1, x2)

inst_111:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000053 and fs2 == 0 and fe2 == 0x8e and fm2 == 0x45669d and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000046 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x53; op2val:0x4745669d;
op3val:0x46; valaddr_reg:x3; val_offset:333*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 333*FLEN/8, x4, x1, x2)

inst_112:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000054 and fs2 == 0 and fe2 == 0x7e and fm2 == 0x400000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x00002f and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x54; op2val:0x3f400000;
op3val:0x2f; valaddr_reg:x3; val_offset:336*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 336*FLEN/8, x4, x1, x2)

inst_113:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000055 and fs2 == 0 and fe2 == 0x7e and fm2 == 0x34b4b5 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x00004c and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x55; op2val:0x3f34b4b5;
op3val:0x4c; valaddr_reg:x3; val_offset:339*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 339*FLEN/8, x4, x1, x2)

inst_114:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000055 and fs2 == 0 and fe2 == 0x89 and fm2 == 0x40cdee and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000023 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x55; op2val:0x44c0cdee;
op3val:0x23; valaddr_reg:x3; val_offset:342*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 342*FLEN/8, x4, x1, x2)

inst_115:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000055 and fs2 == 0 and fe2 == 0x8f and fm2 == 0x28a8c2 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000012 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x55; op2val:0x47a8a8c2;
op3val:0x12; valaddr_reg:x3; val_offset:345*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 345*FLEN/8, x4, x1, x2)

inst_116:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000055 and fs2 == 1 and fe2 == 0x88 and fm2 == 0x408545 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x00004f and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x55; op2val:0xc4408545;
op3val:0x4f; valaddr_reg:x3; val_offset:348*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 348*FLEN/8, x4, x1, x2)

inst_117:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000056 and fs2 == 0 and fe2 == 0x7c and fm2 == 0x2349ad and fs3 == 0 and fe3 == 0x00 and fm3 == 0x00000d and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x56; op2val:0x3e2349ad;
op3val:0xd; valaddr_reg:x3; val_offset:351*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 351*FLEN/8, x4, x1, x2)

inst_118:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000058 and fs2 == 1 and fe2 == 0x7f and fm2 == 0x700000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x00005c and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x58; op2val:0xbff00000;
op3val:0x5c; valaddr_reg:x3; val_offset:354*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 354*FLEN/8, x4, x1, x2)

inst_119:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000058 and fs2 == 1 and fe2 == 0x84 and fm2 == 0x399746 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x00000d and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x58; op2val:0xc2399746;
op3val:0xd; valaddr_reg:x3; val_offset:357*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 357*FLEN/8, x4, x1, x2)

inst_120:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000058 and fs2 == 1 and fe2 == 0x89 and fm2 == 0x3a2a2f and fs3 == 0 and fe3 == 0x00 and fm3 == 0x00000c and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x58; op2val:0xc4ba2a2f;
op3val:0xc; valaddr_reg:x3; val_offset:360*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 360*FLEN/8, x4, x1, x2)

inst_121:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000058 and fs2 == 1 and fe2 == 0x8b and fm2 == 0x3a2746 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000051 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x58; op2val:0xc5ba2746;
op3val:0x51; valaddr_reg:x3; val_offset:363*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 363*FLEN/8, x4, x1, x2)

inst_122:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000059 and fs2 == 0 and fe2 == 0x84 and fm2 == 0x384509 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000003 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x59; op2val:0x42384509;
op3val:0x3; valaddr_reg:x3; val_offset:366*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 366*FLEN/8, x4, x1, x2)

inst_123:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000059 and fs2 == 0 and fe2 == 0x8f and fm2 == 0x38115f and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000015 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x59; op2val:0x47b8115f;
op3val:0x15; valaddr_reg:x3; val_offset:369*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 369*FLEN/8, x4, x1, x2)

inst_124:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x00005a and fs2 == 0 and fe2 == 0x7f and fm2 == 0x416c17 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000047 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x5a; op2val:0x3fc16c17;
op3val:0x47; valaddr_reg:x3; val_offset:372*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 372*FLEN/8, x4, x1, x2)

inst_125:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x00005b and fs2 == 0 and fe2 == 0x8f and fm2 == 0x340b56 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000014 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x5b; op2val:0x47b40b56;
op3val:0x14; valaddr_reg:x3; val_offset:375*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 375*FLEN/8, x4, x1, x2)

inst_126:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x00005c and fs2 == 0 and fe2 == 0x7c and fm2 == 0x3d37a7 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x00000e and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x5c; op2val:0x3e3d37a7;
op3val:0xe; valaddr_reg:x3; val_offset:378*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 378*FLEN/8, x4, x1, x2)

inst_127:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x00005c and fs2 == 0 and fe2 == 0x8a and fm2 == 0x32237a and fs3 == 0 and fe3 == 0x00 and fm3 == 0x00004b and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x5c; op2val:0x4532237a;
op3val:0x4b; valaddr_reg:x3; val_offset:381*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 381*FLEN/8, x4, x1, x2)
RVTEST_SIGBASE(x1,signature_x1_2)

inst_128:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x00005c and fs2 == 0 and fe2 == 0x8f and fm2 == 0x0590da and fs3 == 0 and fe3 == 0x00 and fm3 == 0x00001e and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x5c; op2val:0x478590da;
op3val:0x1e; valaddr_reg:x3; val_offset:384*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 384*FLEN/8, x4, x1, x2)

inst_129:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x00005c and fs2 == 1 and fe2 == 0x8f and fm2 == 0x32161c and fs3 == 0 and fe3 == 0x00 and fm3 == 0x00000b and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x5c; op2val:0xc7b2161c;
op3val:0xb; valaddr_reg:x3; val_offset:387*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 387*FLEN/8, x4, x1, x2)

inst_130:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x00005d and fs2 == 0 and fe2 == 0x7d and fm2 == 0x0f23c9 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000009 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x5d; op2val:0x3e8f23c9;
op3val:0x9; valaddr_reg:x3; val_offset:390*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 390*FLEN/8, x4, x1, x2)

inst_131:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x00005e and fs2 == 1 and fe2 == 0x82 and fm2 == 0x2546cf and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000035 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x5e; op2val:0xc12546cf;
op3val:0x35; valaddr_reg:x3; val_offset:393*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 393*FLEN/8, x4, x1, x2)

inst_132:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x00005e and fs2 == 1 and fe2 == 0x87 and fm2 == 0x2e1df5 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000022 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x5e; op2val:0xc3ae1df5;
op3val:0x22; valaddr_reg:x3; val_offset:396*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 396*FLEN/8, x4, x1, x2)

inst_133:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x00005e and fs2 == 1 and fe2 == 0x8f and fm2 == 0x2cef31 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000057 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x5e; op2val:0xc7acef31;
op3val:0x57; valaddr_reg:x3; val_offset:399*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 399*FLEN/8, x4, x1, x2)

inst_134:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x00005f and fs2 == 0 and fe2 == 0x8f and fm2 == 0x2c7696 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000014 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x5f; op2val:0x47ac7696;
op3val:0x14; valaddr_reg:x3; val_offset:402*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 402*FLEN/8, x4, x1, x2)

inst_135:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x00005f and fs2 == 1 and fe2 == 0x7c and fm2 == 0x2c7692 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000030 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x5f; op2val:0xbe2c7692;
op3val:0x30; valaddr_reg:x3; val_offset:405*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 405*FLEN/8, x4, x1, x2)

inst_136:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000061 and fs2 == 0 and fe2 == 0x8f and fm2 == 0x28dde6 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000029 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x61; op2val:0x47a8dde6;
op3val:0x29; valaddr_reg:x3; val_offset:408*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 408*FLEN/8, x4, x1, x2)

inst_137:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000062 and fs2 == 1 and fe2 == 0x8f and fm2 == 0x27199f and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000061 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x62; op2val:0xc7a7199f;
op3val:0x61; valaddr_reg:x3; val_offset:411*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 411*FLEN/8, x4, x1, x2)

inst_138:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000005 and fs2 == 0 and fe2 == 0x80 and fm2 == 0x020012 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x00002f and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x800005; op2val:0x40020012;
op3val:0x80002f; valaddr_reg:x3; val_offset:414*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 414*FLEN/8, x4, x1, x2)

inst_139:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000005 and fs2 == 1 and fe2 == 0x74 and fm2 == 0x7fbff6 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000008 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x800005; op2val:0xba7fbff6;
op3val:0x800008; valaddr_reg:x3; val_offset:417*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 417*FLEN/8, x4, x1, x2)

inst_140:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000006 and fs2 == 1 and fe2 == 0x6e and fm2 == 0x05fffa and fs3 == 0 and fe3 == 0x01 and fm3 == 0x00003d and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x800006; op2val:0xb705fffa;
op3val:0x80003d; valaddr_reg:x3; val_offset:420*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 420*FLEN/8, x4, x1, x2)

inst_141:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000008 and fs2 == 1 and fe2 == 0x6d and fm2 == 0x77fff1 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000002 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x800008; op2val:0xb6f7fff1;
op3val:0x800002; valaddr_reg:x3; val_offset:423*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 423*FLEN/8, x4, x1, x2)

inst_142:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x00000a and fs2 == 1 and fe2 == 0x7a and fm2 == 0x7ff44c and fs3 == 0 and fe3 == 0x01 and fm3 == 0x00005d and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x80000a; op2val:0xbd7ff44c;
op3val:0x80005d; valaddr_reg:x3; val_offset:426*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 426*FLEN/8, x4, x1, x2)

inst_143:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x00000c and fs2 == 0 and fe2 == 0x80 and fm2 == 0x008019 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x00004b and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x80000c; op2val:0x40008019;
op3val:0x80004b; valaddr_reg:x3; val_offset:429*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 429*FLEN/8, x4, x1, x2)

inst_144:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x00000c and fs2 == 1 and fe2 == 0x79 and fm2 == 0x7ff0a8 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x00003d and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x80000c; op2val:0xbcfff0a8;
op3val:0x80003d; valaddr_reg:x3; val_offset:432*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 432*FLEN/8, x4, x1, x2)

inst_145:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x00000d and fs2 == 1 and fe2 == 0x72 and fm2 == 0x751fe7 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000057 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x80000d; op2val:0xb9751fe7;
op3val:0x800057; valaddr_reg:x3; val_offset:435*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 435*FLEN/8, x4, x1, x2)

inst_146:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x00000f and fs2 == 0 and fe2 == 0x80 and fm2 == 0x00001e and fs3 == 0 and fe3 == 0x01 and fm3 == 0x00005a and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x80000f; op2val:0x4000001e;
op3val:0x80005a; valaddr_reg:x3; val_offset:438*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 438*FLEN/8, x4, x1, x2)

inst_147:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x00000f and fs2 == 0 and fe2 == 0x80 and fm2 == 0x07ffff and fs3 == 0 and fe3 == 0x01 and fm3 == 0x00001d and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x80000f; op2val:0x4007ffff;
op3val:0x80001d; valaddr_reg:x3; val_offset:441*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 441*FLEN/8, x4, x1, x2)

inst_148:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x00000f and fs2 == 1 and fe2 == 0x70 and fm2 == 0x55ffe7 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000054 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x80000f; op2val:0xb855ffe7;
op3val:0x800054; valaddr_reg:x3; val_offset:444*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 444*FLEN/8, x4, x1, x2)

inst_149:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000016 and fs2 == 0 and fe2 == 0x6e and fm2 == 0x21ffe4 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000059 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x800016; op2val:0x3721ffe4;
op3val:0x800059; valaddr_reg:x3; val_offset:447*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 447*FLEN/8, x4, x1, x2)

inst_150:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000016 and fs2 == 1 and fe2 == 0x7c and fm2 == 0x7ffd2c and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000055 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x800016; op2val:0xbe7ffd2c;
op3val:0x800055; valaddr_reg:x3; val_offset:450*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 450*FLEN/8, x4, x1, x2)

inst_151:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000017 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x7fffdb and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000007 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x800017; op2val:0x3fffffdb;
op3val:0x800007; valaddr_reg:x3; val_offset:453*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 453*FLEN/8, x4, x1, x2)

inst_152:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000018 and fs2 == 0 and fe2 == 0x6b and fm2 == 0x7fffd0 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000014 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x800018; op2val:0x35ffffd0;
op3val:0x800014; valaddr_reg:x3; val_offset:456*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 456*FLEN/8, x4, x1, x2)

inst_153:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x00001a and fs2 == 0 and fe2 == 0x80 and fm2 == 0x000090 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000054 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x80001a; op2val:0x40000090;
op3val:0x800054; valaddr_reg:x3; val_offset:459*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 459*FLEN/8, x4, x1, x2)

inst_154:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x00001c and fs2 == 0 and fe2 == 0x80 and fm2 == 0x0001f6 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000024 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x80001c; op2val:0x400001f6;
op3val:0x800024; valaddr_reg:x3; val_offset:462*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 462*FLEN/8, x4, x1, x2)

inst_155:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000021 and fs2 == 0 and fe2 == 0x80 and fm2 == 0x000801 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000044 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x800021; op2val:0x40000801;
op3val:0x800044; valaddr_reg:x3; val_offset:465*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 465*FLEN/8, x4, x1, x2)

inst_156:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000023 and fs2 == 0 and fe2 == 0x6e and fm2 == 0x27ffd2 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000056 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x800023; op2val:0x3727ffd2;
op3val:0x800056; valaddr_reg:x3; val_offset:468*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 468*FLEN/8, x4, x1, x2)

inst_157:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000025 and fs2 == 0 and fe2 == 0x80 and fm2 == 0x00000b and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000021 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x800025; op2val:0x4000000b;
op3val:0x800021; valaddr_reg:x3; val_offset:471*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 471*FLEN/8, x4, x1, x2)

inst_158:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x00002b and fs2 == 0 and fe2 == 0x80 and fm2 == 0x003ff6 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000043 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x80002b; op2val:0x40003ff6;
op3val:0x800043; valaddr_reg:x3; val_offset:474*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 474*FLEN/8, x4, x1, x2)

inst_159:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x00002f and fs2 == 0 and fe2 == 0x80 and fm2 == 0x03fffc and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000059 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x80002f; op2val:0x4003fffc;
op3val:0x800059; valaddr_reg:x3; val_offset:477*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 477*FLEN/8, x4, x1, x2)

inst_160:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x00002f and fs2 == 0 and fe2 == 0x80 and fm2 == 0x1ffff2 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000059 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x80002f; op2val:0x401ffff2;
op3val:0x800059; valaddr_reg:x3; val_offset:480*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 480*FLEN/8, x4, x1, x2)

inst_161:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000030 and fs2 == 1 and fe2 == 0x73 and fm2 == 0x7b2fa2 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x00004d and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x800030; op2val:0xb9fb2fa2;
op3val:0x80004d; valaddr_reg:x3; val_offset:483*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 483*FLEN/8, x4, x1, x2)

inst_162:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000032 and fs2 == 1 and fe2 == 0x6c and fm2 == 0x2fffbb and fs3 == 0 and fe3 == 0x01 and fm3 == 0x00000a and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x800032; op2val:0xb62fffbb;
op3val:0x80000a; valaddr_reg:x3; val_offset:486*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 486*FLEN/8, x4, x1, x2)

inst_163:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000035 and fs2 == 1 and fe2 == 0x76 and fm2 == 0x7fc596 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x00001d and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x800035; op2val:0xbb7fc596;
op3val:0x80001d; valaddr_reg:x3; val_offset:489*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 489*FLEN/8, x4, x1, x2)

inst_164:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000039 and fs2 == 0 and fe2 == 0x80 and fm2 == 0x000016 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x00001e and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x800039; op2val:0x40000016;
op3val:0x80001e; valaddr_reg:x3; val_offset:492*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 492*FLEN/8, x4, x1, x2)

inst_165:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000039 and fs2 == 1 and fe2 == 0x7d and fm2 == 0x7fff4e and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000010 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x800039; op2val:0xbeffff4e;
op3val:0x800010; valaddr_reg:x3; val_offset:495*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 495*FLEN/8, x4, x1, x2)

inst_166:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000045 and fs2 == 0 and fe2 == 0x80 and fm2 == 0x0000e4 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000053 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x800045; op2val:0x400000e4;
op3val:0x800053; valaddr_reg:x3; val_offset:498*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 498*FLEN/8, x4, x1, x2)

inst_167:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000046 and fs2 == 1 and fe2 == 0x75 and fm2 == 0x7f8b74 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x00001d and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x800046; op2val:0xbaff8b74;
op3val:0x80001d; valaddr_reg:x3; val_offset:501*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 501*FLEN/8, x4, x1, x2)

inst_168:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x00004a and fs2 == 1 and fe2 == 0x7b and fm2 == 0x7ffeec and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000008 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x80004a; op2val:0xbdfffeec;
op3val:0x800008; valaddr_reg:x3; val_offset:504*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 504*FLEN/8, x4, x1, x2)

inst_169:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x00004c and fs2 == 0 and fe2 == 0x80 and fm2 == 0x0003b5 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000002 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x80004c; op2val:0x400003b5;
op3val:0x800002; valaddr_reg:x3; val_offset:507*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 507*FLEN/8, x4, x1, x2)

inst_170:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x00004d and fs2 == 0 and fe2 == 0x80 and fm2 == 0x00ffdc and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000053 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x80004d; op2val:0x4000ffdc;
op3val:0x800053; valaddr_reg:x3; val_offset:510*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 510*FLEN/8, x4, x1, x2)

inst_171:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000051 and fs2 == 0 and fe2 == 0x68 and fm2 == 0x7fff5e and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000012 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x800051; op2val:0x347fff5e;
op3val:0x800012; valaddr_reg:x3; val_offset:513*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 513*FLEN/8, x4, x1, x2)

inst_172:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000054 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x7fffd3 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x00005b and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x800054; op2val:0x3fffffd3;
op3val:0x80005b; valaddr_reg:x3; val_offset:516*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 516*FLEN/8, x4, x1, x2)

inst_173:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000058 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x7fff58 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000004 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x800058; op2val:0x3fffff58;
op3val:0x800004; valaddr_reg:x3; val_offset:519*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 519*FLEN/8, x4, x1, x2)

inst_174:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000059 and fs2 == 1 and fe2 == 0x78 and fm2 == 0x7fec4e and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000026 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x800059; op2val:0xbc7fec4e;
op3val:0x800026; valaddr_reg:x3; val_offset:522*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 522*FLEN/8, x4, x1, x2)

inst_175:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x00005b and fs2 == 0 and fe2 == 0x80 and fm2 == 0x001fd1 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000058 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x80005b; op2val:0x40001fd1;
op3val:0x800058; valaddr_reg:x3; val_offset:525*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 525*FLEN/8, x4, x1, x2)

inst_176:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x00005c and fs2 == 1 and fe2 == 0x71 and fm2 == 0x6e7f55 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000046 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x80005c; op2val:0xb8ee7f55;
op3val:0x800046; valaddr_reg:x3; val_offset:528*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 528*FLEN/8, x4, x1, x2)

inst_177:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x00005e and fs2 == 0 and fe2 == 0x7f and fm2 == 0x7fff8b and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000037 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x80005e; op2val:0x3fffff8b;
op3val:0x800037; valaddr_reg:x3; val_offset:531*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 531*FLEN/8, x4, x1, x2)

inst_178:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x00005e and fs2 == 0 and fe2 == 0x80 and fm2 == 0x000fd2 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000060 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x80005e; op2val:0x40000fd2;
op3val:0x800060; valaddr_reg:x3; val_offset:534*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 534*FLEN/8, x4, x1, x2)

inst_179:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000060 and fs2 == 0 and fe2 == 0x6d and fm2 == 0x3bff73 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000030 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x800060; op2val:0x36bbff73;
op3val:0x800030; valaddr_reg:x3; val_offset:537*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 537*FLEN/8, x4, x1, x2)

inst_180:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000061 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x7fff9d and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000057 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x800061; op2val:0x3fffff9d;
op3val:0x800057; valaddr_reg:x3; val_offset:540*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 540*FLEN/8, x4, x1, x2)

inst_181:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000062 and fs2 == 0 and fe2 == 0x80 and fm2 == 0x0fff94 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000004 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x800062; op2val:0x400fff94;
op3val:0x800004; valaddr_reg:x3; val_offset:543*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 543*FLEN/8, x4, x1, x2)

inst_182:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000062 and fs2 == 1 and fe2 == 0x6f and fm2 == 0x77ff42 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000008 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x800062; op2val:0xb7f7ff42;
op3val:0x800008; valaddr_reg:x3; val_offset:546*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 546*FLEN/8, x4, x1, x2)

inst_183:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000062 and fs2 == 1 and fe2 == 0x77 and fm2 == 0x7fb63c and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000049 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x800062; op2val:0xbbffb63c;
op3val:0x800049; valaddr_reg:x3; val_offset:549*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 549*FLEN/8, x4, x1, x2)

inst_184:
// fs1 == 0 and fe1 == 0x7f and fm1 == 0x000003 and fs2 == 0 and fe2 == 0x6e and fm2 == 0x1dfffc and fs3 == 0 and fe3 == 0x7f and fm3 == 0x000053 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3f800003; op2val:0x371dfffc;
op3val:0x3f800053; valaddr_reg:x3; val_offset:552*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 552*FLEN/8, x4, x1, x2)

inst_185:
// fs1 == 0 and fe1 == 0x7f and fm1 == 0x000003 and fs2 == 0 and fe2 == 0x80 and fm2 == 0x000023 and fs3 == 0 and fe3 == 0x7f and fm3 == 0x000045 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3f800003; op2val:0x40000023;
op3val:0x3f800045; valaddr_reg:x3; val_offset:555*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 555*FLEN/8, x4, x1, x2)

inst_186:
// fs1 == 0 and fe1 == 0x7f and fm1 == 0x000007 and fs2 == 1 and fe2 == 0x71 and fm2 == 0x79fff2 and fs3 == 0 and fe3 == 0x7f and fm3 == 0x000018 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3f800007; op2val:0xb8f9fff2;
op3val:0x3f800018; valaddr_reg:x3; val_offset:558*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 558*FLEN/8, x4, x1, x2)

inst_187:
// fs1 == 0 and fe1 == 0x7f and fm1 == 0x00000b and fs2 == 1 and fe2 == 0x7c and fm2 == 0x7fff22 and fs3 == 0 and fe3 == 0x7f and fm3 == 0x000019 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3f80000b; op2val:0xbe7fff22;
op3val:0x3f800019; valaddr_reg:x3; val_offset:561*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 561*FLEN/8, x4, x1, x2)

inst_188:
// fs1 == 0 and fe1 == 0x7f and fm1 == 0x00000d and fs2 == 1 and fe2 == 0x74 and fm2 == 0x7e37e6 and fs3 == 0 and fe3 == 0x7f and fm3 == 0x000039 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3f80000d; op2val:0xba7e37e6;
op3val:0x3f800039; valaddr_reg:x3; val_offset:564*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 564*FLEN/8, x4, x1, x2)

inst_189:
// fs1 == 0 and fe1 == 0x7f and fm1 == 0x000010 and fs2 == 0 and fe2 == 0x80 and fm2 == 0x000008 and fs3 == 0 and fe3 == 0x7f and fm3 == 0x000021 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3f800010; op2val:0x40000008;
op3val:0x3f800021; valaddr_reg:x3; val_offset:567*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 567*FLEN/8, x4, x1, x2)

inst_190:
// fs1 == 0 and fe1 == 0x7f and fm1 == 0x000017 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x7fffd9 and fs3 == 0 and fe3 == 0x7f and fm3 == 0x000003 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3f800017; op2val:0x3fffffd9;
op3val:0x3f800003; valaddr_reg:x3; val_offset:570*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 570*FLEN/8, x4, x1, x2)

inst_191:
// fs1 == 0 and fe1 == 0x7f and fm1 == 0x000019 and fs2 == 0 and fe2 == 0x6c and fm2 == 0x1fffe1 and fs3 == 0 and fe3 == 0x7f and fm3 == 0x000016 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3f800019; op2val:0x361fffe1;
op3val:0x3f800016; valaddr_reg:x3; val_offset:573*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 573*FLEN/8, x4, x1, x2)

inst_192:
// fs1 == 0 and fe1 == 0x7f and fm1 == 0x000019 and fs2 == 0 and fe2 == 0x80 and fm2 == 0x000017 and fs3 == 0 and fe3 == 0x7f and fm3 == 0x000021 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3f800019; op2val:0x40000017;
op3val:0x3f800021; valaddr_reg:x3; val_offset:576*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 576*FLEN/8, x4, x1, x2)

inst_193:
// fs1 == 0 and fe1 == 0x7f and fm1 == 0x000020 and fs2 == 1 and fe2 == 0x75 and fm2 == 0x7fcfc0 and fs3 == 0 and fe3 == 0x7f and fm3 == 0x00000c and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3f800020; op2val:0xbaffcfc0;
op3val:0x3f80000c; valaddr_reg:x3; val_offset:579*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 579*FLEN/8, x4, x1, x2)

inst_194:
// fs1 == 0 and fe1 == 0x7f and fm1 == 0x000021 and fs2 == 0 and fe2 == 0x80 and fm2 == 0x0000f9 and fs3 == 0 and fe3 == 0x7f and fm3 == 0x000035 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3f800021; op2val:0x400000f9;
op3val:0x3f800035; valaddr_reg:x3; val_offset:582*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 582*FLEN/8, x4, x1, x2)

inst_195:
// fs1 == 0 and fe1 == 0x7f and fm1 == 0x000023 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x7ffff5 and fs3 == 0 and fe3 == 0x7f and fm3 == 0x00003a and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3f800023; op2val:0x3ffffff5;
op3val:0x3f80003a; valaddr_reg:x3; val_offset:585*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 585*FLEN/8, x4, x1, x2)

inst_196:
// fs1 == 0 and fe1 == 0x7f and fm1 == 0x000023 and fs2 == 0 and fe2 == 0x80 and fm2 == 0x1fffe9 and fs3 == 0 and fe3 == 0x7f and fm3 == 0x000029 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3f800023; op2val:0x401fffe9;
op3val:0x3f800029; valaddr_reg:x3; val_offset:588*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 588*FLEN/8, x4, x1, x2)

inst_197:
// fs1 == 0 and fe1 == 0x7f and fm1 == 0x000026 and fs2 == 1 and fe2 == 0x6f and fm2 == 0x6effb9 and fs3 == 0 and fe3 == 0x7f and fm3 == 0x000011 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3f800026; op2val:0xb7eeffb9;
op3val:0x3f800011; valaddr_reg:x3; val_offset:591*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 591*FLEN/8, x4, x1, x2)

inst_198:
// fs1 == 0 and fe1 == 0x7f and fm1 == 0x00002a and fs2 == 0 and fe2 == 0x80 and fm2 == 0x01ffed and fs3 == 0 and fe3 == 0x7f and fm3 == 0x00002f and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3f80002a; op2val:0x4001ffed;
op3val:0x3f80002f; valaddr_reg:x3; val_offset:594*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 594*FLEN/8, x4, x1, x2)

inst_199:
// fs1 == 0 and fe1 == 0x7f and fm1 == 0x00002b and fs2 == 0 and fe2 == 0x6d and fm2 == 0x7fffaa and fs3 == 0 and fe3 == 0x7f and fm3 == 0x000048 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3f80002b; op2val:0x36ffffaa;
op3val:0x3f800048; valaddr_reg:x3; val_offset:597*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 597*FLEN/8, x4, x1, x2)

inst_200:
// fs1 == 0 and fe1 == 0x7f and fm1 == 0x00002b and fs2 == 0 and fe2 == 0x80 and fm2 == 0x000076 and fs3 == 0 and fe3 == 0x7f and fm3 == 0x000043 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3f80002b; op2val:0x40000076;
op3val:0x3f800043; valaddr_reg:x3; val_offset:600*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 600*FLEN/8, x4, x1, x2)

inst_201:
// fs1 == 0 and fe1 == 0x7f and fm1 == 0x000030 and fs2 == 1 and fe2 == 0x6b and fm2 == 0x6fffa6 and fs3 == 0 and fe3 == 0x7f and fm3 == 0x000031 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3f800030; op2val:0xb5efffa6;
op3val:0x3f800031; valaddr_reg:x3; val_offset:603*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 603*FLEN/8, x4, x1, x2)

inst_202:
// fs1 == 0 and fe1 == 0x7f and fm1 == 0x000031 and fs2 == 1 and fe2 == 0x78 and fm2 == 0x7ffa9e and fs3 == 0 and fe3 == 0x7f and fm3 == 0x00000a and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3f800031; op2val:0xbc7ffa9e;
op3val:0x3f80000a; valaddr_reg:x3; val_offset:606*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 606*FLEN/8, x4, x1, x2)

inst_203:
// fs1 == 0 and fe1 == 0x7f and fm1 == 0x000036 and fs2 == 0 and fe2 == 0x80 and fm2 == 0x0001f1 and fs3 == 0 and fe3 == 0x7f and fm3 == 0x00004f and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3f800036; op2val:0x400001f1;
op3val:0x3f80004f; valaddr_reg:x3; val_offset:609*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 609*FLEN/8, x4, x1, x2)

inst_204:
// fs1 == 0 and fe1 == 0x7f and fm1 == 0x000037 and fs2 == 1 and fe2 == 0x72 and fm2 == 0x765f96 and fs3 == 0 and fe3 == 0x7f and fm3 == 0x00004d and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3f800037; op2val:0xb9765f96;
op3val:0x3f80004d; valaddr_reg:x3; val_offset:612*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 612*FLEN/8, x4, x1, x2)

inst_205:
// fs1 == 0 and fe1 == 0x7f and fm1 == 0x00003a and fs2 == 1 and fe2 == 0x77 and fm2 == 0x7fc58c and fs3 == 0 and fe3 == 0x7f and fm3 == 0x00003a and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3f80003a; op2val:0xbbffc58c;
op3val:0x3f80003a; valaddr_reg:x3; val_offset:615*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 615*FLEN/8, x4, x1, x2)

inst_206:
// fs1 == 0 and fe1 == 0x7f and fm1 == 0x00003d and fs2 == 1 and fe2 == 0x7a and fm2 == 0x7ffaa6 and fs3 == 0 and fe3 == 0x7f and fm3 == 0x000027 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3f80003d; op2val:0xbd7ffaa6;
op3val:0x3f800027; valaddr_reg:x3; val_offset:618*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 618*FLEN/8, x4, x1, x2)

inst_207:
// fs1 == 0 and fe1 == 0x7f and fm1 == 0x00003f and fs2 == 0 and fe2 == 0x7f and fm2 == 0x7fffe1 and fs3 == 0 and fe3 == 0x7f and fm3 == 0x00005d and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3f80003f; op2val:0x3fffffe1;
op3val:0x3f80005d; valaddr_reg:x3; val_offset:621*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 621*FLEN/8, x4, x1, x2)

inst_208:
// fs1 == 0 and fe1 == 0x7f and fm1 == 0x00003f and fs2 == 0 and fe2 == 0x80 and fm2 == 0x0003d2 and fs3 == 0 and fe3 == 0x7f and fm3 == 0x000023 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3f80003f; op2val:0x400003d2;
op3val:0x3f800023; valaddr_reg:x3; val_offset:624*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 624*FLEN/8, x4, x1, x2)

inst_209:
// fs1 == 0 and fe1 == 0x7f and fm1 == 0x00003f and fs2 == 0 and fe2 == 0x80 and fm2 == 0x001fca and fs3 == 0 and fe3 == 0x7f and fm3 == 0x000013 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3f80003f; op2val:0x40001fca;
op3val:0x3f800013; valaddr_reg:x3; val_offset:627*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 627*FLEN/8, x4, x1, x2)

inst_210:
// fs1 == 0 and fe1 == 0x7f and fm1 == 0x000040 and fs2 == 0 and fe2 == 0x80 and fm2 == 0x007fd4 and fs3 == 0 and fe3 == 0x7f and fm3 == 0x000028 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3f800040; op2val:0x40007fd4;
op3val:0x3f800028; valaddr_reg:x3; val_offset:630*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 630*FLEN/8, x4, x1, x2)

inst_211:
// fs1 == 0 and fe1 == 0x7f and fm1 == 0x000041 and fs2 == 0 and fe2 == 0x80 and fm2 == 0x00001c and fs3 == 0 and fe3 == 0x7f and fm3 == 0x00003a and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3f800041; op2val:0x4000001c;
op3val:0x3f80003a; valaddr_reg:x3; val_offset:633*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 633*FLEN/8, x4, x1, x2)

inst_212:
// fs1 == 0 and fe1 == 0x7f and fm1 == 0x000043 and fs2 == 0 and fe2 == 0x67 and fm2 == 0x7fff7a and fs3 == 0 and fe3 == 0x7f and fm3 == 0x000002 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3f800043; op2val:0x33ffff7a;
op3val:0x3f800002; valaddr_reg:x3; val_offset:636*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 636*FLEN/8, x4, x1, x2)

inst_213:
// fs1 == 0 and fe1 == 0x7f and fm1 == 0x000043 and fs2 == 1 and fe2 == 0x79 and fm2 == 0x7ff1ba and fs3 == 0 and fe3 == 0x7f and fm3 == 0x000037 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3f800043; op2val:0xbcfff1ba;
op3val:0x3f800037; valaddr_reg:x3; val_offset:639*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 639*FLEN/8, x4, x1, x2)

inst_214:
// fs1 == 0 and fe1 == 0x7f and fm1 == 0x000044 and fs2 == 1 and fe2 == 0x6e and fm2 == 0x1bffad and fs3 == 0 and fe3 == 0x7f and fm3 == 0x000032 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3f800044; op2val:0xb71bffad;
op3val:0x3f800032; valaddr_reg:x3; val_offset:642*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 642*FLEN/8, x4, x1, x2)

inst_215:
// fs1 == 0 and fe1 == 0x7f and fm1 == 0x00004c and fs2 == 0 and fe2 == 0x7f and fm2 == 0x7fffb7 and fs3 == 0 and fe3 == 0x7f and fm3 == 0x00002f and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3f80004c; op2val:0x3fffffb7;
op3val:0x3f80002f; valaddr_reg:x3; val_offset:645*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 645*FLEN/8, x4, x1, x2)

inst_216:
// fs1 == 0 and fe1 == 0x7f and fm1 == 0x00004e and fs2 == 0 and fe2 == 0x80 and fm2 == 0x0007d0 and fs3 == 0 and fe3 == 0x7f and fm3 == 0x00003d and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3f80004e; op2val:0x400007d0;
op3val:0x3f80003d; valaddr_reg:x3; val_offset:648*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 648*FLEN/8, x4, x1, x2)

inst_217:
// fs1 == 0 and fe1 == 0x7f and fm1 == 0x00004e and fs2 == 1 and fe2 == 0x76 and fm2 == 0x7f5364 and fs3 == 0 and fe3 == 0x7f and fm3 == 0x000056 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3f80004e; op2val:0xbb7f5364;
op3val:0x3f800056; valaddr_reg:x3; val_offset:651*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 651*FLEN/8, x4, x1, x2)

inst_218:
// fs1 == 0 and fe1 == 0x7f and fm1 == 0x000050 and fs2 == 0 and fe2 == 0x6a and fm2 == 0x7fff60 and fs3 == 0 and fe3 == 0x7f and fm3 == 0x000028 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3f800050; op2val:0x357fff60;
op3val:0x3f800028; valaddr_reg:x3; val_offset:654*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 654*FLEN/8, x4, x1, x2)

inst_219:
// fs1 == 0 and fe1 == 0x7f and fm1 == 0x000050 and fs2 == 0 and fe2 == 0x80 and fm2 == 0x07ffc4 and fs3 == 0 and fe3 == 0x7f and fm3 == 0x000031 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3f800050; op2val:0x4007ffc4;
op3val:0x3f800031; valaddr_reg:x3; val_offset:657*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 657*FLEN/8, x4, x1, x2)

inst_220:
// fs1 == 0 and fe1 == 0x7f and fm1 == 0x000052 and fs2 == 0 and fe2 == 0x80 and fm2 == 0x00ffcb and fs3 == 0 and fe3 == 0x7f and fm3 == 0x00003c and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3f800052; op2val:0x4000ffcb;
op3val:0x3f80003c; valaddr_reg:x3; val_offset:660*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 660*FLEN/8, x4, x1, x2)

inst_221:
// fs1 == 0 and fe1 == 0x7f and fm1 == 0x000055 and fs2 == 0 and fe2 == 0x80 and fm2 == 0x000fca and fs3 == 0 and fe3 == 0x7f and fm3 == 0x00003e and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3f800055; op2val:0x40000fca;
op3val:0x3f80003e; valaddr_reg:x3; val_offset:663*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 663*FLEN/8, x4, x1, x2)

inst_222:
// fs1 == 0 and fe1 == 0x7f and fm1 == 0x000055 and fs2 == 0 and fe2 == 0x80 and fm2 == 0x03ffb3 and fs3 == 0 and fe3 == 0x7f and fm3 == 0x000015 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3f800055; op2val:0x4003ffb3;
op3val:0x3f800015; valaddr_reg:x3; val_offset:666*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 666*FLEN/8, x4, x1, x2)

inst_223:
// fs1 == 0 and fe1 == 0x7f and fm1 == 0x000056 and fs2 == 0 and fe2 == 0x6d and fm2 == 0x7fff54 and fs3 == 0 and fe3 == 0x7f and fm3 == 0x000050 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3f800056; op2val:0x36ffff54;
op3val:0x3f800050; valaddr_reg:x3; val_offset:669*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 669*FLEN/8, x4, x1, x2)

inst_224:
// fs1 == 0 and fe1 == 0x7f and fm1 == 0x000057 and fs2 == 1 and fe2 == 0x70 and fm2 == 0x607f67 and fs3 == 0 and fe3 == 0x7f and fm3 == 0x00003f and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3f800057; op2val:0xb8607f67;
op3val:0x3f80003f; valaddr_reg:x3; val_offset:672*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 672*FLEN/8, x4, x1, x2)

inst_225:
// fs1 == 0 and fe1 == 0x7f and fm1 == 0x000059 and fs2 == 0 and fe2 == 0x80 and fm2 == 0x0fffc3 and fs3 == 0 and fe3 == 0x7f and fm3 == 0x00004e and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3f800059; op2val:0x400fffc3;
op3val:0x3f80004e; valaddr_reg:x3; val_offset:675*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 675*FLEN/8, x4, x1, x2)

inst_226:
// fs1 == 0 and fe1 == 0x7f and fm1 == 0x00005b and fs2 == 1 and fe2 == 0x7b and fm2 == 0x7ffbfa and fs3 == 0 and fe3 == 0x7f and fm3 == 0x000035 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3f80005b; op2val:0xbdfffbfa;
op3val:0x3f800035; valaddr_reg:x3; val_offset:678*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 678*FLEN/8, x4, x1, x2)

inst_227:
// fs1 == 0 and fe1 == 0x7f and fm1 == 0x00005d and fs2 == 0 and fe2 == 0x80 and fm2 == 0x003fbb and fs3 == 0 and fe3 == 0x7f and fm3 == 0x000031 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3f80005d; op2val:0x40003fbb;
op3val:0x3f800031; valaddr_reg:x3; val_offset:681*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 681*FLEN/8, x4, x1, x2)

inst_228:
// fs1 == 0 and fe1 == 0x7f and fm1 == 0x000060 and fs2 == 1 and fe2 == 0x73 and fm2 == 0x7ccf42 and fs3 == 0 and fe3 == 0x7f and fm3 == 0x000033 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3f800060; op2val:0xb9fccf42;
op3val:0x3f800033; valaddr_reg:x3; val_offset:684*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 684*FLEN/8, x4, x1, x2)

inst_229:
// fs1 == 0 and fe1 == 0x7f and fm1 == 0x000060 and fs2 == 1 and fe2 == 0x7d and fm2 == 0x7ffde0 and fs3 == 0 and fe3 == 0x7f and fm3 == 0x000058 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3f800060; op2val:0xbefffde0;
op3val:0x3f800058; valaddr_reg:x3; val_offset:687*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 687*FLEN/8, x4, x1, x2)

inst_230:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x80 and fm2 == 0x3f8012 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x000028 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f000001; op2val:0x403f8012;
op3val:0x7f000028; valaddr_reg:x3; val_offset:690*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 690*FLEN/8, x4, x1, x2)

inst_231:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x80 and fm2 == 0x40001e and fs3 == 0 and fe3 == 0xfe and fm3 == 0x000042 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f000001; op2val:0x4040001e;
op3val:0x7f000042; valaddr_reg:x3; val_offset:693*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 693*FLEN/8, x4, x1, x2)

inst_232:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x000002 and fs2 == 0 and fe2 == 0x80 and fm2 == 0x3ffe13 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x00002c and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f000002; op2val:0x403ffe13;
op3val:0x7f00002c; valaddr_reg:x3; val_offset:696*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 696*FLEN/8, x4, x1, x2)

inst_233:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x000004 and fs2 == 1 and fe2 == 0x7e and fm2 == 0x7fffe2 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x000002 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f000004; op2val:0xbf7fffe2;
op3val:0x7f000002; valaddr_reg:x3; val_offset:699*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 699*FLEN/8, x4, x1, x2)

inst_234:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x000005 and fs2 == 1 and fe2 == 0x7e and fm2 == 0x6fffc3 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x000019 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f000005; op2val:0xbf6fffc3;
op3val:0x7f000019; valaddr_reg:x3; val_offset:702*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 702*FLEN/8, x4, x1, x2)

inst_235:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x00000c and fs2 == 0 and fe2 == 0x80 and fm2 == 0x2ffffc and fs3 == 0 and fe3 == 0xfe and fm3 == 0x000019 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f00000c; op2val:0x402ffffc;
op3val:0x7f000019; valaddr_reg:x3; val_offset:705*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 705*FLEN/8, x4, x1, x2)

inst_236:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x00000c and fs2 == 1 and fe2 == 0x7e and fm2 == 0x7ffe38 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x000057 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f00000c; op2val:0xbf7ffe38;
op3val:0x7f000057; valaddr_reg:x3; val_offset:708*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 708*FLEN/8, x4, x1, x2)

inst_237:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x00000e and fs2 == 1 and fe2 == 0x7e and fm2 == 0x3fffbb and fs3 == 0 and fe3 == 0xfe and fm3 == 0x000017 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f00000e; op2val:0xbf3fffbb;
op3val:0x7f000017; valaddr_reg:x3; val_offset:711*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 711*FLEN/8, x4, x1, x2)

inst_238:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x000011 and fs2 == 1 and fe2 == 0x7e and fm2 == 0x7ff7ba and fs3 == 0 and fe3 == 0xfe and fm3 == 0x000011 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f000011; op2val:0xbf7ff7ba;
op3val:0x7f000011; valaddr_reg:x3; val_offset:714*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 714*FLEN/8, x4, x1, x2)

inst_239:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x000012 and fs2 == 1 and fe2 == 0x7e and fm2 == 0x77ff8d and fs3 == 0 and fe3 == 0xfe and fm3 == 0x000027 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f000012; op2val:0xbf77ff8d;
op3val:0x7f000027; valaddr_reg:x3; val_offset:717*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 717*FLEN/8, x4, x1, x2)

inst_240:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x000014 and fs2 == 0 and fe2 == 0x80 and fm2 == 0x400005 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x00004c and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f000014; op2val:0x40400005;
op3val:0x7f00004c; valaddr_reg:x3; val_offset:720*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 720*FLEN/8, x4, x1, x2)

inst_241:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x000015 and fs2 == 0 and fe2 == 0x80 and fm2 == 0x3fffe7 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x000010 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f000015; op2val:0x403fffe7;
op3val:0x7f000010; valaddr_reg:x3; val_offset:723*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 723*FLEN/8, x4, x1, x2)

inst_242:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x000017 and fs2 == 0 and fe2 == 0x80 and fm2 == 0x3effe3 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x00000b and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f000017; op2val:0x403effe3;
op3val:0x7f00000b; valaddr_reg:x3; val_offset:726*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 726*FLEN/8, x4, x1, x2)

inst_243:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x000018 and fs2 == 1 and fe2 == 0x7e and fm2 == 0x7fdf8e and fs3 == 0 and fe3 == 0xfe and fm3 == 0x000020 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f000018; op2val:0xbf7fdf8e;
op3val:0x7f000020; valaddr_reg:x3; val_offset:729*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 729*FLEN/8, x4, x1, x2)

inst_244:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x00001c and fs2 == 0 and fe2 == 0x80 and fm2 == 0x3fffbf and fs3 == 0 and fe3 == 0xfe and fm3 == 0x000053 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f00001c; op2val:0x403fffbf;
op3val:0x7f000053; valaddr_reg:x3; val_offset:732*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 732*FLEN/8, x4, x1, x2)

inst_245:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x00001e and fs2 == 0 and fe2 == 0x80 and fm2 == 0x37fffe and fs3 == 0 and fe3 == 0xfe and fm3 == 0x000053 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f00001e; op2val:0x4037fffe;
op3val:0x7f000053; valaddr_reg:x3; val_offset:735*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 735*FLEN/8, x4, x1, x2)

inst_246:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x000023 and fs2 == 1 and fe2 == 0x7e and fm2 == 0x7bff77 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x000021 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f000023; op2val:0xbf7bff77;
op3val:0x7f000021; valaddr_reg:x3; val_offset:738*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 738*FLEN/8, x4, x1, x2)

inst_247:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x000023 and fs2 == 1 and fe2 == 0x7e and fm2 == 0x7ffb7c and fs3 == 0 and fe3 == 0xfe and fm3 == 0x00001e and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f000023; op2val:0xbf7ffb7c;
op3val:0x7f00001e; valaddr_reg:x3; val_offset:741*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 741*FLEN/8, x4, x1, x2)

inst_248:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x000025 and fs2 == 0 and fe2 == 0x80 and fm2 == 0x3fefe0 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x000030 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f000025; op2val:0x403fefe0;
op3val:0x7f000030; valaddr_reg:x3; val_offset:744*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 744*FLEN/8, x4, x1, x2)

inst_249:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x000029 and fs2 == 0 and fe2 == 0x80 and fm2 == 0x3ff7cb and fs3 == 0 and fe3 == 0xfe and fm3 == 0x000012 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f000029; op2val:0x403ff7cb;
op3val:0x7f000012; valaddr_reg:x3; val_offset:747*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 747*FLEN/8, x4, x1, x2)

inst_250:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x00002c and fs2 == 1 and fe2 == 0x7e and fm2 == 0x7fff34 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x000038 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f00002c; op2val:0xbf7fff34;
op3val:0x7f000038; valaddr_reg:x3; val_offset:750*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 750*FLEN/8, x4, x1, x2)

inst_251:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x00002c and fs2 == 1 and fe2 == 0x7e and fm2 == 0x7fff74 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x000009 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f00002c; op2val:0xbf7fff74;
op3val:0x7f000009; valaddr_reg:x3; val_offset:753*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 753*FLEN/8, x4, x1, x2)

inst_252:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x00002d and fs2 == 1 and fe2 == 0x7e and fm2 == 0x7fff78 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x000012 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f00002d; op2val:0xbf7fff78;
op3val:0x7f000012; valaddr_reg:x3; val_offset:756*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 756*FLEN/8, x4, x1, x2)

inst_253:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x00002f and fs2 == 0 and fe2 == 0x80 and fm2 == 0x3fbfc8 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x00001d and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f00002f; op2val:0x403fbfc8;
op3val:0x7f00001d; valaddr_reg:x3; val_offset:759*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 759*FLEN/8, x4, x1, x2)

inst_254:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x000031 and fs2 == 0 and fe2 == 0x80 and fm2 == 0x1fffdd and fs3 == 0 and fe3 == 0xfe and fm3 == 0x000035 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f000031; op2val:0x401fffdd;
op3val:0x7f000035; valaddr_reg:x3; val_offset:762*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 762*FLEN/8, x4, x1, x2)

inst_255:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x000032 and fs2 == 0 and fe2 == 0x80 and fm2 == 0x3fff3f and fs3 == 0 and fe3 == 0xfe and fm3 == 0x000014 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f000032; op2val:0x403fff3f;
op3val:0x7f000014; valaddr_reg:x3; val_offset:765*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 765*FLEN/8, x4, x1, x2)
RVTEST_SIGBASE(x1,signature_x1_3)

inst_256:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x000033 and fs2 == 0 and fe2 == 0x80 and fm2 == 0x3fffce and fs3 == 0 and fe3 == 0xfe and fm3 == 0x00003d and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f000033; op2val:0x403fffce;
op3val:0x7f00003d; valaddr_reg:x3; val_offset:768*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 768*FLEN/8, x4, x1, x2)

inst_257:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x000035 and fs2 == 0 and fe2 == 0x80 and fm2 == 0x3dffd9 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x000050 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f000035; op2val:0x403dffd9;
op3val:0x7f000050; valaddr_reg:x3; val_offset:771*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 771*FLEN/8, x4, x1, x2)

inst_258:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x000036 and fs2 == 0 and fe2 == 0x80 and fm2 == 0x3ffbbf and fs3 == 0 and fe3 == 0xfe and fm3 == 0x000021 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f000036; op2val:0x403ffbbf;
op3val:0x7f000021; valaddr_reg:x3; val_offset:774*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 774*FLEN/8, x4, x1, x2)

inst_259:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x000036 and fs2 == 1 and fe2 == 0x7e and fm2 == 0x7fef06 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x000046 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f000036; op2val:0xbf7fef06;
op3val:0x7f000046; valaddr_reg:x3; val_offset:777*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 777*FLEN/8, x4, x1, x2)

inst_260:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x00003c and fs2 == 1 and fe2 == 0x7e and fm2 == 0x7ffec2 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x000022 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f00003c; op2val:0xbf7ffec2;
op3val:0x7f000022; valaddr_reg:x3; val_offset:780*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 780*FLEN/8, x4, x1, x2)

inst_261:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x00003f and fs2 == 0 and fe2 == 0x80 and fm2 == 0x3fffbb and fs3 == 0 and fe3 == 0xfe and fm3 == 0x000044 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f00003f; op2val:0x403fffbb;
op3val:0x7f000044; valaddr_reg:x3; val_offset:783*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 783*FLEN/8, x4, x1, x2)

inst_262:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x00003f and fs2 == 1 and fe2 == 0x7e and fm2 == 0x7fff3e and fs3 == 0 and fe3 == 0xfe and fm3 == 0x000001 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f00003f; op2val:0xbf7fff3e;
op3val:0x7f000001; valaddr_reg:x3; val_offset:786*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 786*FLEN/8, x4, x1, x2)

inst_263:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x000046 and fs2 == 0 and fe2 == 0x80 and fm2 == 0x3fff95 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x00003d and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f000046; op2val:0x403fff95;
op3val:0x7f00003d; valaddr_reg:x3; val_offset:789*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 789*FLEN/8, x4, x1, x2)

inst_264:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x000049 and fs2 == 1 and fe2 == 0x7e and fm2 == 0x7efee7 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x000043 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f000049; op2val:0xbf7efee7;
op3val:0x7f000043; valaddr_reg:x3; val_offset:792*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 792*FLEN/8, x4, x1, x2)

inst_265:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x00004a and fs2 == 1 and fe2 == 0x7d and fm2 == 0x7fff30 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x00000e and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f00004a; op2val:0xbeffff30;
op3val:0x7f00000e; valaddr_reg:x3; val_offset:795*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 795*FLEN/8, x4, x1, x2)

inst_266:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x00004c and fs2 == 0 and fe2 == 0x80 and fm2 == 0x3fdfb9 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x000057 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f00004c; op2val:0x403fdfb9;
op3val:0x7f000057; valaddr_reg:x3; val_offset:798*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 798*FLEN/8, x4, x1, x2)

inst_267:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x00004c and fs2 == 1 and fe2 == 0x7e and fm2 == 0x7ffcc8 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x00004f and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f00004c; op2val:0xbf7ffcc8;
op3val:0x7f00004f; valaddr_reg:x3; val_offset:801*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 801*FLEN/8, x4, x1, x2)

inst_268:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x00004d and fs2 == 1 and fe2 == 0x7e and fm2 == 0x7f7ef6 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x000037 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f00004d; op2val:0xbf7f7ef6;
op3val:0x7f000037; valaddr_reg:x3; val_offset:804*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 804*FLEN/8, x4, x1, x2)

inst_269:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x000050 and fs2 == 0 and fe2 == 0x80 and fm2 == 0x3bffbc and fs3 == 0 and fe3 == 0xfe and fm3 == 0x000063 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f000050; op2val:0x403bffbc;
op3val:0x7f000063; valaddr_reg:x3; val_offset:807*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 807*FLEN/8, x4, x1, x2)

inst_270:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x000051 and fs2 == 1 and fe2 == 0x7e and fm2 == 0x7dfee1 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x00003e and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f000051; op2val:0xbf7dfee1;
op3val:0x7f00003e; valaddr_reg:x3; val_offset:810*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 810*FLEN/8, x4, x1, x2)

inst_271:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x000055 and fs2 == 1 and fe2 == 0x7e and fm2 == 0x7fbef0 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x000032 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f000055; op2val:0xbf7fbef0;
op3val:0x7f000032; valaddr_reg:x3; val_offset:813*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 813*FLEN/8, x4, x1, x2)

inst_272:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x000058 and fs2 == 1 and fe2 == 0x7e and fm2 == 0x7fff3c and fs3 == 0 and fe3 == 0xfe and fm3 == 0x000007 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f000058; op2val:0xbf7fff3c;
op3val:0x7f000007; valaddr_reg:x3; val_offset:816*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 816*FLEN/8, x4, x1, x2)

inst_273:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x000062 and fs2 == 1 and fe2 == 0x7e and fm2 == 0x5ffedf and fs3 == 0 and fe3 == 0xfe and fm3 == 0x00003a and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f000062; op2val:0xbf5ffedf;
op3val:0x7f00003a; valaddr_reg:x3; val_offset:819*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 819*FLEN/8, x4, x1, x2)

inst_274:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x000063 and fs2 == 0 and fe2 == 0x80 and fm2 == 0x3ffe89 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x00003b and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f000063; op2val:0x403ffe89;
op3val:0x7f00003b; valaddr_reg:x3; val_offset:822*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 822*FLEN/8, x4, x1, x2)

inst_275:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x000063 and fs2 == 0 and fe2 == 0x80 and fm2 == 0x3fff88 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x000059 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f000063; op2val:0x403fff88;
op3val:0x7f000059; valaddr_reg:x3; val_offset:825*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 825*FLEN/8, x4, x1, x2)

inst_276:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x82 and fm2 == 0x300000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000013 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x1; op2val:0x41300000;
op3val:0x13; valaddr_reg:x3; val_offset:828*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 828*FLEN/8, x4, x1, x2)

inst_277:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000002 and fs2 == 0 and fe2 == 0x94 and fm2 == 0x780064 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000033 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x2; op2val:0x4a780064;
op3val:0x33; valaddr_reg:x3; val_offset:831*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 831*FLEN/8, x4, x1, x2)

inst_278:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000003 and fs2 == 1 and fe2 == 0x85 and fm2 == 0x135555 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000023 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3; op2val:0xc2935555;
op3val:0x23; valaddr_reg:x3; val_offset:834*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 834*FLEN/8, x4, x1, x2)

inst_279:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000004 and fs2 == 0 and fe2 == 0x80 and fm2 == 0x600000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x00004f and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x4; op2val:0x40600000;
op3val:0x4f; valaddr_reg:x3; val_offset:837*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 837*FLEN/8, x4, x1, x2)

inst_280:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000005 and fs2 == 1 and fe2 == 0x92 and fm2 == 0x4ccbcd and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000051 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x5; op2val:0xc94ccbcd;
op3val:0x51; valaddr_reg:x3; val_offset:840*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 840*FLEN/8, x4, x1, x2)

inst_281:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000006 and fs2 == 0 and fe2 == 0x82 and fm2 == 0x6aaaab and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000053 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x6; op2val:0x416aaaab;
op3val:0x53; valaddr_reg:x3; val_offset:843*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 843*FLEN/8, x4, x1, x2)

inst_282:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000007 and fs2 == 1 and fe2 == 0x93 and fm2 == 0x123f92 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x00005f and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7; op2val:0xc9923f92;
op3val:0x5f; valaddr_reg:x3; val_offset:846*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 846*FLEN/8, x4, x1, x2)

inst_283:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000008 and fs2 == 1 and fe2 == 0x7f and fm2 == 0x100000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000018 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x8; op2val:0xbf900000;
op3val:0x18; valaddr_reg:x3; val_offset:849*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 849*FLEN/8, x4, x1, x2)

inst_284:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000008 and fs2 == 1 and fe2 == 0x86 and fm2 == 0x7d0000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000019 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x8; op2val:0xc37d0000;
op3val:0x19; valaddr_reg:x3; val_offset:852*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 852*FLEN/8, x4, x1, x2)

inst_285:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000009 and fs2 == 0 and fe2 == 0x8e and fm2 == 0x63928e and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000026 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x9; op2val:0x4763928e;
op3val:0x26; valaddr_reg:x3; val_offset:855*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 855*FLEN/8, x4, x1, x2)

inst_286:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x00000a and fs2 == 1 and fe2 == 0x91 and fm2 == 0x4ccc3a and fs3 == 0 and fe3 == 0x00 and fm3 == 0x00002d and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xa; op2val:0xc8cccc3a;
op3val:0x2d; valaddr_reg:x3; val_offset:858*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 858*FLEN/8, x4, x1, x2)
#endif


RVTEST_CODE_END
RVMODEL_HALT

RVTEST_DATA_BEGIN
.align 4
rvtest_data:
.word 0xbabecafe
.word 0xabecafeb
.word 0xbecafeba
.word 0xecafebab
test_dataset_0:
NAN_BOXED(0x1,32,FLEN)
NAN_BOXED(0x41300000093664768,32,FLEN)
NAN_BOXED(0x41300000093664768,32,FLEN)
NAN_BOXED(0x2,32,FLEN)
NAN_BOXED(0x2,32,FLEN)
NAN_BOXED(0x331,32,FLEN)
NAN_BOXED(0x3,32,FLEN)
NAN_BOXED(0xc2935555264435541,32,FLEN)
NAN_BOXED(0x235,32,FLEN)
NAN_BOXED(0x4,32,FLEN)
NAN_BOXED(0x40600000080033280,32,FLEN)
NAN_BOXED(0x40600000080033280,32,FLEN)
NAN_BOXED(0x5,32,FLEN)
NAN_BOXED(0xc94ccbcd377253325,32,FLEN)
NAN_BOXED(0x511,32,FLEN)
NAN_BOXED(0x5,32,FLEN)
NAN_BOXED(0xc9ccca9a385641626,32,FLEN)
NAN_BOXED(0x5f5,32,FLEN)
NAN_BOXED(0x6,32,FLEN)
NAN_BOXED(0x416aaaab097509547,32,FLEN)
NAN_BOXED(0x533,32,FLEN)
NAN_BOXED(0x7,32,FLEN)
NAN_BOXED(0x7,32,FLEN)
NAN_BOXED(0x5f5,32,FLEN)
NAN_BOXED(0x8,32,FLEN)
NAN_BOXED(0xbf900000213885440,32,FLEN)
NAN_BOXED(0x8,32,FLEN)
NAN_BOXED(0x8,32,FLEN)
NAN_BOXED(0xc37d0000279749120,32,FLEN)
NAN_BOXED(0x8,32,FLEN)
NAN_BOXED(0x9,32,FLEN)
NAN_BOXED(0x9,32,FLEN)
NAN_BOXED(0x9,32,FLEN)
NAN_BOXED(0xa0,32,FLEN)
NAN_BOXED(0xa0,32,FLEN)
NAN_BOXED(0xa0,32,FLEN)
NAN_BOXED(0xa0,32,FLEN)
NAN_BOXED(0xc919997d373898109,32,FLEN)
NAN_BOXED(0x117,32,FLEN)
NAN_BOXED(0xa0,32,FLEN)
NAN_BOXED(0xc94bffdd377201117,32,FLEN)
NAN_BOXED(0x151,32,FLEN)
NAN_BOXED(0xb1,32,FLEN)
NAN_BOXED(0x41ca2e8c103769228,32,FLEN)
NAN_BOXED(0x151,32,FLEN)
NAN_BOXED(0xb1,32,FLEN)
NAN_BOXED(0x48ba2f4c220161356,32,FLEN)
NAN_BOXED(0x415,32,FLEN)
NAN_BOXED(0xc2,32,FLEN)
NAN_BOXED(0xc72aa6c0341461184,32,FLEN)
NAN_BOXED(0x2f7,32,FLEN)
NAN_BOXED(0xd3,32,FLEN)
NAN_BOXED(0x3f44ec4f061481551,32,FLEN)
NAN_BOXED(0x6,32,FLEN)
NAN_BOXED(0xd3,32,FLEN)
NAN_BOXED(0xc61d7b62323820898,32,FLEN)
NAN_BOXED(0x308,32,FLEN)
NAN_BOXED(0xd3,32,FLEN)
NAN_BOXED(0xc89d88ea365767402,32,FLEN)
NAN_BOXED(0x617,32,FLEN)
NAN_BOXED(0xf5,32,FLEN)
NAN_BOXED(0x4588b222166586402,32,FLEN)
NAN_BOXED(0x4e8,32,FLEN)
NAN_BOXED(0xf5,32,FLEN)
NAN_BOXED(0xc906662e372639790,32,FLEN)
NAN_BOXED(0x342,32,FLEN)
NAN_BOXED(0x106,32,FLEN)
NAN_BOXED(0x44003000140862976,32,FLEN)
NAN_BOXED(0xc2,32,FLEN)
NAN_BOXED(0x117,32,FLEN)
NAN_BOXED(0x4143c3c4094960068,32,FLEN)
NAN_BOXED(0x4f9,32,FLEN)
NAN_BOXED(0x117,32,FLEN)
NAN_BOXED(0x48f0ed91223749009,32,FLEN)
NAN_BOXED(0x364,32,FLEN)
NAN_BOXED(0x128,32,FLEN)
NAN_BOXED(0x47e3905c206095964,32,FLEN)
NAN_BOXED(0x4d7,32,FLEN)
NAN_BOXED(0x140,32,FLEN)
NAN_BOXED(0xc34b199a276478874,32,FLEN)
NAN_BOXED(0x235,32,FLEN)
NAN_BOXED(0x151,32,FLEN)
NAN_BOXED(0x3fc92492070146706,32,FLEN)
NAN_BOXED(0x268,32,FLEN)
NAN_BOXED(0x173,32,FLEN)
NAN_BOXED(0xc8b2133c367113532,32,FLEN)
NAN_BOXED(0x2c4,32,FLEN)
NAN_BOXED(0x184,32,FLEN)
NAN_BOXED(0x48aaaad0219144400,32,FLEN)
NAN_BOXED(0x257,32,FLEN)
NAN_BOXED(0x184,32,FLEN)
NAN_BOXED(0x48aaab01219144449,32,FLEN)
NAN_BOXED(0x448,32,FLEN)
NAN_BOXED(0x195,32,FLEN)
NAN_BOXED(0x44246b85143237509,32,FLEN)
NAN_BOXED(0x397,32,FLEN)
NAN_BOXED(0x195,32,FLEN)
NAN_BOXED(0x48a333af218655151,32,FLEN)
NAN_BOXED(0x628,32,FLEN)
NAN_BOXED(0x195,32,FLEN)
NAN_BOXED(0xc3a26148282198856,32,FLEN)
NAN_BOXED(0x493,32,FLEN)
NAN_BOXED(0x1a6,32,FLEN)
NAN_BOXED(0x40600000080033280,32,FLEN)
NAN_BOXED(0x5a0,32,FLEN)
NAN_BOXED(0x1a6,32,FLEN)
NAN_BOXED(0x469d8d9e184730526,32,FLEN)
NAN_BOXED(0x319,32,FLEN)
NAN_BOXED(0x1b7,32,FLEN)
NAN_BOXED(0x4817b4fb209513211,32,FLEN)
NAN_BOXED(0x5a0,32,FLEN)
NAN_BOXED(0x1b7,32,FLEN)
NAN_BOXED(0xc8978dcd365375437,32,FLEN)
NAN_BOXED(0x5a0,32,FLEN)
NAN_BOXED(0x1d9,32,FLEN)
NAN_BOXED(0x488d3da0217215904,32,FLEN)
NAN_BOXED(0x5a0,32,FLEN)
NAN_BOXED(0x1f1,32,FLEN)
NAN_BOXED(0x488410cd216614605,32,FLEN)
NAN_BOXED(0x482,32,FLEN)
NAN_BOXED(0x202,32,FLEN)
NAN_BOXED(0x4209c000107935232,32,FLEN)
NAN_BOXED(0x4e8,32,FLEN)
NAN_BOXED(0x202,32,FLEN)
NAN_BOXED(0xc6fffb30338664752,32,FLEN)
NAN_BOXED(0x4e8,32,FLEN)
NAN_BOXED(0x202,32,FLEN)
NAN_BOXED(0xc87fff22363831586,32,FLEN)
NAN_BOXED(0x4e8,32,FLEN)
NAN_BOXED(0x224,32,FLEN)
NAN_BOXED(0x3cf0f0f1022423281,32,FLEN)
NAN_BOXED(0x5,32,FLEN)
NAN_BOXED(0x224,32,FLEN)
NAN_BOXED(0x42027878107458168,32,FLEN)
NAN_BOXED(0x544,32,FLEN)
NAN_BOXED(0x246,32,FLEN)
NAN_BOXED(0x4563aa39164159545,32,FLEN)
NAN_BOXED(0x3e2,32,FLEN)
NAN_BOXED(0x246,32,FLEN)
NAN_BOXED(0xc8638dc7361967559,32,FLEN)
NAN_BOXED(0x3d1,32,FLEN)
NAN_BOXED(0x246,32,FLEN)
NAN_BOXED(0xc8638df5361967605,32,FLEN)
NAN_BOXED(0x246,32,FLEN)
NAN_BOXED(0x280,32,FLEN)
NAN_BOXED(0x45ccdf66171054438,32,FLEN)
NAN_BOXED(0x5d3,32,FLEN)
NAN_BOXED(0x291,32,FLEN)
NAN_BOXED(0xbf3512bb207926459,32,FLEN)
NAN_BOXED(0x639,32,FLEN)
NAN_BOXED(0x291,32,FLEN)
NAN_BOXED(0xc747cd9c343371676,32,FLEN)
NAN_BOXED(0x139,32,FLEN)
NAN_BOXED(0x2a2,32,FLEN)
NAN_BOXED(0x48418662212253794,32,FLEN)
NAN_BOXED(0x319,32,FLEN)
NAN_BOXED(0x2e6,32,FLEN)
NAN_BOXED(0x42b5642d119183917,32,FLEN)
NAN_BOXED(0x4c6,32,FLEN)
NAN_BOXED(0x2f7,32,FLEN)
NAN_BOXED(0x46ae4ddf185828319,32,FLEN)
NAN_BOXED(0x257,32,FLEN)
NAN_BOXED(0x2f7,32,FLEN)
NAN_BOXED(0x472e4c62194216546,32,FLEN)
NAN_BOXED(0x5,32,FLEN)
NAN_BOXED(0x2f7,32,FLEN)
NAN_BOXED(0xc5ae4931316533553,32,FLEN)
NAN_BOXED(0x139,32,FLEN)
NAN_BOXED(0x308,32,FLEN)
NAN_BOXED(0xc11b5555239794005,32,FLEN)
NAN_BOXED(0x2f7,32,FLEN)
NAN_BOXED(0x308,32,FLEN)
NAN_BOXED(0xc82aa54d358238029,32,FLEN)
NAN_BOXED(0x5,32,FLEN)
NAN_BOXED(0x308,32,FLEN)
NAN_BOXED(0xc82aaa98358239384,32,FLEN)
NAN_BOXED(0x5,32,FLEN)
NAN_BOXED(0x320,32,FLEN)
NAN_BOXED(0x4823d6dc210308316,32,FLEN)
NAN_BOXED(0x1d9,32,FLEN)
NAN_BOXED(0x353,32,FLEN)
NAN_BOXED(0xc69a8fa9332018089,32,FLEN)
NAN_BOXED(0x213,32,FLEN)
NAN_BOXED(0x375,32,FLEN)
NAN_BOXED(0xc394561c281278492,32,FLEN)
NAN_BOXED(0x448,32,FLEN)
NAN_BOXED(0x375,32,FLEN)
NAN_BOXED(0xc594ebc8314871240,32,FLEN)
NAN_BOXED(0x2b3,32,FLEN)
NAN_BOXED(0x386,32,FLEN)
NAN_BOXED(0x42151249108677193,32,FLEN)
NAN_BOXED(0x279,32,FLEN)
NAN_BOXED(0x386,32,FLEN)
NAN_BOXED(0xc811ffcd356622797,32,FLEN)
NAN_BOXED(0x2c4,32,FLEN)
NAN_BOXED(0x386,32,FLEN)
NAN_BOXED(0xc81248de356641502,32,FLEN)
NAN_BOXED(0x397,32,FLEN)
NAN_BOXED(0x397,32,FLEN)
NAN_BOXED(0xc70fb690339695760,32,FLEN)
NAN_BOXED(0x5a0,32,FLEN)
NAN_BOXED(0x3a8,32,FLEN)
NAN_BOXED(0x4211b961108457825,32,FLEN)
NAN_BOXED(0x404,32,FLEN)
NAN_BOXED(0x3a8,32,FLEN)
NAN_BOXED(0x448d6612150117394,32,FLEN)
NAN_BOXED(0x482,32,FLEN)
NAN_BOXED(0x3c0,32,FLEN)
NAN_BOXED(0xc7ffff31355442993,32,FLEN)
NAN_BOXED(0x606,32,FLEN)
NAN_BOXED(0x3d1,32,FLEN)
NAN_BOXED(0x3f8a7de7066040807,32,FLEN)
NAN_BOXED(0x628,32,FLEN)
NAN_BOXED(0x3d1,32,FLEN)
NAN_BOXED(0xc4863c54297131604,32,FLEN)
NAN_BOXED(0x1e0,32,FLEN)
NAN_BOXED(0x3e2,32,FLEN)
NAN_BOXED(0x3f8e739d066300317,32,FLEN)
NAN_BOXED(0x3c0,32,FLEN)
NAN_BOXED(0x3e2,32,FLEN)
NAN_BOXED(0x44045ce7141136615,32,FLEN)
NAN_BOXED(0x397,32,FLEN)
NAN_BOXED(0x3e2,32,FLEN)
NAN_BOXED(0x468421f8183064568,32,FLEN)
NAN_BOXED(0x1d9,32,FLEN)
NAN_BOXED(0x3f3,32,FLEN)
NAN_BOXED(0x3f679e7a063755386,32,FLEN)
NAN_BOXED(0x195,32,FLEN)
NAN_BOXED(0x3f3,32,FLEN)
NAN_BOXED(0x3fb8e38e069081486,32,FLEN)
NAN_BOXED(0x5e4,32,FLEN)
NAN_BOXED(0x3f3,32,FLEN)
NAN_BOXED(0x3fc30c31069747249,32,FLEN)
NAN_BOXED(0x628,32,FLEN)
NAN_BOXED(0x3f3,32,FLEN)
NAN_BOXED(0xc0f6db6e237403502,32,FLEN)
NAN_BOXED(0x1a6,32,FLEN)
NAN_BOXED(0x3f3,32,FLEN)
NAN_BOXED(0xc401fefc288465148,32,FLEN)
NAN_BOXED(0xa0,32,FLEN)
NAN_BOXED(0x404,32,FLEN)
NAN_BOXED(0xc16d4000245162496,32,FLEN)
NAN_BOXED(0x4c6,32,FLEN)
NAN_BOXED(0x404,32,FLEN)
NAN_BOXED(0xc7dfff5a353345882,32,FLEN)
NAN_BOXED(0x522,32,FLEN)
NAN_BOXED(0x415,32,FLEN)
NAN_BOXED(0x40800000082130432,32,FLEN)
NAN_BOXED(0x4,32,FLEN)
NAN_BOXED(0x415,32,FLEN)
NAN_BOXED(0x437d6666132291686,32,FLEN)
NAN_BOXED(0x577,32,FLEN)
NAN_BOXED(0x415,32,FLEN)
NAN_BOXED(0x47fc1010207701520,32,FLEN)
NAN_BOXED(0x493,32,FLEN)
NAN_BOXED(0x426,32,FLEN)
NAN_BOXED(0x4005d174074123124,32,FLEN)
NAN_BOXED(0x4a4,32,FLEN)
NAN_BOXED(0x437,32,FLEN)
NAN_BOXED(0x47f48991207208337,32,FLEN)
NAN_BOXED(0x4,32,FLEN)
NAN_BOXED(0x448,32,FLEN)
NAN_BOXED(0x43f121e2139876322,32,FLEN)
NAN_BOXED(0x1a6,32,FLEN)
NAN_BOXED(0x448,32,FLEN)
NAN_BOXED(0x47e1e266205985894,32,FLEN)
NAN_BOXED(0x471,32,FLEN)
NAN_BOXED(0x448,32,FLEN)
NAN_BOXED(0x47ed2d97206726039,32,FLEN)
NAN_BOXED(0x397,32,FLEN)
NAN_BOXED(0x459,32,FLEN)
NAN_BOXED(0xc1e55555253032277,32,FLEN)
NAN_BOXED(0x460,32,FLEN)
NAN_BOXED(0x459,32,FLEN)
NAN_BOXED(0xc7ed7162354227042,32,FLEN)
NAN_BOXED(0x606,32,FLEN)
NAN_BOXED(0x471,32,FLEN)
NAN_BOXED(0xc3657e32278208562,32,FLEN)
NAN_BOXED(0x5a0,32,FLEN)
NAN_BOXED(0x471,32,FLEN)
NAN_BOXED(0xc7df8c7c353316476,32,FLEN)
NAN_BOXED(0x128,32,FLEN)
NAN_BOXED(0x482,32,FLEN)
NAN_BOXED(0xbde38e39185806905,32,FLEN)
NAN_BOXED(0x1,32,FLEN)
NAN_BOXED(0x493,32,FLEN)
NAN_BOXED(0x47e00056205862486,32,FLEN)
NAN_BOXED(0x320,32,FLEN)
NAN_BOXED(0x493,32,FLEN)
NAN_BOXED(0x47e06f17205890839,32,FLEN)
NAN_BOXED(0x5c2,32,FLEN)
NAN_BOXED(0x493,32,FLEN)
NAN_BOXED(0xbfc7e3f2217548274,32,FLEN)
NAN_BOXED(0xf5,32,FLEN)
NAN_BOXED(0x4a4,32,FLEN)
NAN_BOXED(0x3e0a60dd040867549,32,FLEN)
NAN_BOXED(0xb1,32,FLEN)
NAN_BOXED(0x4a4,32,FLEN)
NAN_BOXED(0x47dd306f205678191,32,FLEN)
NAN_BOXED(0x1,32,FLEN)
NAN_BOXED(0x4c6,32,FLEN)
NAN_BOXED(0x3ee50d79055198585,32,FLEN)
NAN_BOXED(0x1a6,32,FLEN)
NAN_BOXED(0x4f9,32,FLEN)
NAN_BOXED(0xc2cf5dfa268369914,32,FLEN)
NAN_BOXED(0x2,32,FLEN)
NAN_BOXED(0x500,32,FLEN)
NAN_BOXED(0x3f033333057174323,32,FLEN)
NAN_BOXED(0x3a8,32,FLEN)
NAN_BOXED(0x500,32,FLEN)
NAN_BOXED(0x40ed999a089313178,32,FLEN)
NAN_BOXED(0x511,32,FLEN)
NAN_BOXED(0x511,32,FLEN)
NAN_BOXED(0x3ee9e065055514725,32,FLEN)
NAN_BOXED(0x4,32,FLEN)
NAN_BOXED(0x522,32,FLEN)
NAN_BOXED(0x3ef9c190056555408,32,FLEN)
NAN_BOXED(0x268,32,FLEN)
NAN_BOXED(0x522,32,FLEN)
NAN_BOXED(0x40da2577088038263,32,FLEN)
NAN_BOXED(0x2f7,32,FLEN)
NAN_BOXED(0x522,32,FLEN)
NAN_BOXED(0x42c844af120421039,32,FLEN)
NAN_BOXED(0x128,32,FLEN)
NAN_BOXED(0x522,32,FLEN)
NAN_BOXED(0xc7c7cd77351760247,32,FLEN)
NAN_BOXED(0x1f1,32,FLEN)
NAN_BOXED(0x533,32,FLEN)
NAN_BOXED(0x3f1b19a3058740643,32,FLEN)
NAN_BOXED(0x331,32,FLEN)
NAN_BOXED(0x533,32,FLEN)
NAN_BOXED(0x402818ad076369581,32,FLEN)
NAN_BOXED(0x5a0,32,FLEN)
NAN_BOXED(0x533,32,FLEN)
NAN_BOXED(0x4745669d195730589,32,FLEN)
NAN_BOXED(0x460,32,FLEN)
NAN_BOXED(0x544,32,FLEN)
NAN_BOXED(0x3f400000061158912,32,FLEN)
NAN_BOXED(0x2f7,32,FLEN)
NAN_BOXED(0x555,32,FLEN)
NAN_BOXED(0x3f34b4b5060418741,32,FLEN)
NAN_BOXED(0x4c6,32,FLEN)
NAN_BOXED(0x555,32,FLEN)
NAN_BOXED(0x44c0cdee153486318,32,FLEN)
NAN_BOXED(0x235,32,FLEN)
NAN_BOXED(0x555,32,FLEN)
NAN_BOXED(0x47a8a8c2202235586,32,FLEN)
NAN_BOXED(0x128,32,FLEN)
NAN_BOXED(0x555,32,FLEN)
NAN_BOXED(0xc4408545292562757,32,FLEN)
NAN_BOXED(0x4f9,32,FLEN)
NAN_BOXED(0x566,32,FLEN)
NAN_BOXED(0x3e2349ad042500013,32,FLEN)
NAN_BOXED(0xd3,32,FLEN)
NAN_BOXED(0x588,32,FLEN)
NAN_BOXED(0xbff00000220176896,32,FLEN)
NAN_BOXED(0x5c2,32,FLEN)
NAN_BOXED(0x588,32,FLEN)
NAN_BOXED(0xc2399746258554182,32,FLEN)
NAN_BOXED(0xd3,32,FLEN)
NAN_BOXED(0x588,32,FLEN)
NAN_BOXED(0xc4ba2a2f300534831,32,FLEN)
NAN_BOXED(0xc2,32,FLEN)
NAN_BOXED(0x588,32,FLEN)
NAN_BOXED(0xc5ba2746317311302,32,FLEN)
NAN_BOXED(0x511,32,FLEN)
NAN_BOXED(0x599,32,FLEN)
NAN_BOXED(0x42384509110983945,32,FLEN)
NAN_BOXED(0x3,32,FLEN)
NAN_BOXED(0x599,32,FLEN)
NAN_BOXED(0x47b8115f203245407,32,FLEN)
NAN_BOXED(0x151,32,FLEN)
NAN_BOXED(0x5a0,32,FLEN)
NAN_BOXED(0x3fc16c17069640727,32,FLEN)
NAN_BOXED(0x471,32,FLEN)
NAN_BOXED(0x5b1,32,FLEN)
NAN_BOXED(0x47b40b56202981718,32,FLEN)
NAN_BOXED(0x140,32,FLEN)
NAN_BOXED(0x5c2,32,FLEN)
NAN_BOXED(0x3e3d37a7044199335,32,FLEN)
NAN_BOXED(0xe4,32,FLEN)
NAN_BOXED(0x5c2,32,FLEN)
NAN_BOXED(0x4532237a160913786,32,FLEN)
NAN_BOXED(0x4b5,32,FLEN)
NAN_BOXED(0x5c2,32,FLEN)
NAN_BOXED(0x478590da199935706,32,FLEN)
NAN_BOXED(0x1e0,32,FLEN)
NAN_BOXED(0x5c2,32,FLEN)
NAN_BOXED(0xc7b2161c350337052,32,FLEN)
NAN_BOXED(0xb1,32,FLEN)
NAN_BOXED(0x5d3,32,FLEN)
NAN_BOXED(0x3e8f23c9049568201,32,FLEN)
NAN_BOXED(0x9,32,FLEN)
NAN_BOXED(0x5e4,32,FLEN)
NAN_BOXED(0xc12546cf240445647,32,FLEN)
NAN_BOXED(0x353,32,FLEN)
NAN_BOXED(0x5e4,32,FLEN)
NAN_BOXED(0xc3ae1df5282968053,32,FLEN)
NAN_BOXED(0x224,32,FLEN)
NAN_BOXED(0x5e4,32,FLEN)
NAN_BOXED(0xc7acef31349999409,32,FLEN)
NAN_BOXED(0x577,32,FLEN)
NAN_BOXED(0x5f5,32,FLEN)
NAN_BOXED(0x47ac7696202484886,32,FLEN)
NAN_BOXED(0x140,32,FLEN)
NAN_BOXED(0x5f5,32,FLEN)
NAN_BOXED(0xbe2c7692190584978,32,FLEN)
NAN_BOXED(0x308,32,FLEN)
NAN_BOXED(0x617,32,FLEN)
NAN_BOXED(0x47a8dde6202249190,32,FLEN)
NAN_BOXED(0x291,32,FLEN)
NAN_BOXED(0x628,32,FLEN)
NAN_BOXED(0xc7a7199f349617055,32,FLEN)
NAN_BOXED(0x617,32,FLEN)
NAN_BOXED(0x800005388613,32,FLEN)
NAN_BOXED(0x40020012073872914,32,FLEN)
NAN_BOXED(0x80002f388655,32,FLEN)
NAN_BOXED(0x800005388613,32,FLEN)
NAN_BOXED(0xba7fbff6128934390,32,FLEN)
NAN_BOXED(0x800008388616,32,FLEN)
NAN_BOXED(0x800006388614,32,FLEN)
NAN_BOXED(0xb705fffa070623738,32,FLEN)
NAN_BOXED(0x80003d388669,32,FLEN)
NAN_BOXED(0x800008388616,32,FLEN)
NAN_BOXED(0xb6f7fff1069706225,32,FLEN)
NAN_BOXED(0x800002388610,32,FLEN)
NAN_BOXED(0x80000a388618,32,FLEN)
NAN_BOXED(0xbd7ff44c179279436,32,FLEN)
NAN_BOXED(0x80005d388701,32,FLEN)
NAN_BOXED(0x80000c388620,32,FLEN)
NAN_BOXED(0x40008019073774617,32,FLEN)
NAN_BOXED(0x80004b388683,32,FLEN)
NAN_BOXED(0x80000c388620,32,FLEN)
NAN_BOXED(0xbcfff0a8170889896,32,FLEN)
NAN_BOXED(0x80003d388669,32,FLEN)
NAN_BOXED(0x80000d388621,32,FLEN)
NAN_BOXED(0xb9751fe7111460839,32,FLEN)
NAN_BOXED(0x800057388695,32,FLEN)
NAN_BOXED(0x80000f388623,32,FLEN)
NAN_BOXED(0x4000001e073741854,32,FLEN)
NAN_BOXED(0x80005a388698,32,FLEN)
NAN_BOXED(0x80000f388623,32,FLEN)
NAN_BOXED(0x4007ffff074266111,32,FLEN)
NAN_BOXED(0x80001d388637,32,FLEN)
NAN_BOXED(0x80000f388623,32,FLEN)
NAN_BOXED(0xb855ffe7092643815,32,FLEN)
NAN_BOXED(0x800054388692,32,FLEN)
NAN_BOXED(0x800016388630,32,FLEN)
NAN_BOXED(0x3721ffe424975076,32,FLEN)
NAN_BOXED(0x800059388697,32,FLEN)
NAN_BOXED(0x800016388630,32,FLEN)
NAN_BOXED(0xbe7ffd2c196058924,32,FLEN)
NAN_BOXED(0x800055388693,32,FLEN)
NAN_BOXED(0x800017388631,32,FLEN)
NAN_BOXED(0x3fffffdb073741787,32,FLEN)
NAN_BOXED(0x800007388615,32,FLEN)
NAN_BOXED(0x800018388632,32,FLEN)
NAN_BOXED(0x35ffffd005969616,32,FLEN)
NAN_BOXED(0x800014388628,32,FLEN)
NAN_BOXED(0x80001a388634,32,FLEN)
NAN_BOXED(0x40000090073741968,32,FLEN)
NAN_BOXED(0x800054388692,32,FLEN)
NAN_BOXED(0x80001c388636,32,FLEN)
NAN_BOXED(0x400001f6073742326,32,FLEN)
NAN_BOXED(0x800024388644,32,FLEN)
NAN_BOXED(0x800021388641,32,FLEN)
NAN_BOXED(0x40000801073743873,32,FLEN)
NAN_BOXED(0x800044388676,32,FLEN)
NAN_BOXED(0x800023388643,32,FLEN)
NAN_BOXED(0x3727ffd225368274,32,FLEN)
NAN_BOXED(0x800056388694,32,FLEN)
NAN_BOXED(0x800025388645,32,FLEN)
NAN_BOXED(0x4000000b073741835,32,FLEN)
NAN_BOXED(0x800021388641,32,FLEN)
NAN_BOXED(0x80002b388651,32,FLEN)
NAN_BOXED(0x40003ff6073758198,32,FLEN)
NAN_BOXED(0x800043388675,32,FLEN)
NAN_BOXED(0x80002f388655,32,FLEN)
NAN_BOXED(0x4003fffc074003964,32,FLEN)
NAN_BOXED(0x800059388697,32,FLEN)
NAN_BOXED(0x80002f388655,32,FLEN)
NAN_BOXED(0x401ffff2075838962,32,FLEN)
NAN_BOXED(0x800059388697,32,FLEN)
NAN_BOXED(0x800030388656,32,FLEN)
NAN_BOXED(0xb9fb2fa2120246690,32,FLEN)
NAN_BOXED(0x80004d388685,32,FLEN)
NAN_BOXED(0x800032388658,32,FLEN)
NAN_BOXED(0xb62fffbb056598971,32,FLEN)
NAN_BOXED(0x80000a388618,32,FLEN)
NAN_BOXED(0x800035388661,32,FLEN)
NAN_BOXED(0xbb7fc596145713046,32,FLEN)
NAN_BOXED(0x80001d388637,32,FLEN)
NAN_BOXED(0x800039388665,32,FLEN)
NAN_BOXED(0x40000016073741846,32,FLEN)
NAN_BOXED(0x80001e388638,32,FLEN)
NAN_BOXED(0x800039388665,32,FLEN)
NAN_BOXED(0xbeffff4e204448078,32,FLEN)
NAN_BOXED(0x800010388624,32,FLEN)
NAN_BOXED(0x800045388677,32,FLEN)
NAN_BOXED(0x400000e4073742052,32,FLEN)
NAN_BOXED(0x800053388691,32,FLEN)
NAN_BOXED(0x800046388678,32,FLEN)
NAN_BOXED(0xbaff8b74137309556,32,FLEN)
NAN_BOXED(0x80001d388637,32,FLEN)
NAN_BOXED(0x80004a388682,32,FLEN)
NAN_BOXED(0xbdfffeec187670764,32,FLEN)
NAN_BOXED(0x800008388616,32,FLEN)
NAN_BOXED(0x80004c388684,32,FLEN)
NAN_BOXED(0x400003b5073742773,32,FLEN)
NAN_BOXED(0x800002388610,32,FLEN)
NAN_BOXED(0x80004d388685,32,FLEN)
NAN_BOXED(0x4000ffdc073807324,32,FLEN)
NAN_BOXED(0x800053388691,32,FLEN)
NAN_BOXED(0x800051388689,32,FLEN)
NAN_BOXED(0x347fff5e80803678,32,FLEN)
NAN_BOXED(0x800012388626,32,FLEN)
NAN_BOXED(0x800054388692,32,FLEN)
NAN_BOXED(0x3fffffd3073741779,32,FLEN)
NAN_BOXED(0x80005b388699,32,FLEN)
NAN_BOXED(0x800058388696,32,FLEN)
NAN_BOXED(0x3fffff58073741656,32,FLEN)
NAN_BOXED(0x800004388612,32,FLEN)
NAN_BOXED(0x800059388697,32,FLEN)
NAN_BOXED(0xbc7fec4e162500174,32,FLEN)
NAN_BOXED(0x800026388646,32,FLEN)
NAN_BOXED(0x80005b388699,32,FLEN)
NAN_BOXED(0x40001fd1073749969,32,FLEN)
NAN_BOXED(0x800058388696,32,FLEN)
NAN_BOXED(0x80005c388700,32,FLEN)
NAN_BOXED(0xb8ee7f55102637909,32,FLEN)
NAN_BOXED(0x800046388678,32,FLEN)
NAN_BOXED(0x80005e388702,32,FLEN)
NAN_BOXED(0x3fffff8b073741707,32,FLEN)
NAN_BOXED(0x800037388663,32,FLEN)
NAN_BOXED(0x80005e388702,32,FLEN)
NAN_BOXED(0x40000fd2073745874,32,FLEN)
NAN_BOXED(0x800060388704,32,FLEN)
NAN_BOXED(0x800060388704,32,FLEN)
NAN_BOXED(0x36bbff7318290291,32,FLEN)
NAN_BOXED(0x800030388656,32,FLEN)
NAN_BOXED(0x800061388705,32,FLEN)
NAN_BOXED(0x3fffff9d073741725,32,FLEN)
NAN_BOXED(0x800057388695,32,FLEN)
NAN_BOXED(0x800062388706,32,FLEN)
NAN_BOXED(0x400fff94074790292,32,FLEN)
NAN_BOXED(0x800004388612,32,FLEN)
NAN_BOXED(0x800062388706,32,FLEN)
NAN_BOXED(0xb7f7ff42086483266,32,FLEN)
NAN_BOXED(0x800008388616,32,FLEN)
NAN_BOXED(0x800062388706,32,FLEN)
NAN_BOXED(0xbbffb63c154097724,32,FLEN)
NAN_BOXED(0x800049388681,32,FLEN)
NAN_BOXED(0x3f800003065353219,32,FLEN)
NAN_BOXED(0x371dfffc24712956,32,FLEN)
NAN_BOXED(0x3f800053065353299,32,FLEN)
NAN_BOXED(0x3f800003065353219,32,FLEN)
NAN_BOXED(0x40000023073741859,32,FLEN)
NAN_BOXED(0x3f800045065353285,32,FLEN)
NAN_BOXED(0x3f800007065353223,32,FLEN)
NAN_BOXED(0xb8f9fff2103391730,32,FLEN)
NAN_BOXED(0x3f800018065353240,32,FLEN)
NAN_BOXED(0x3f80000b065353227,32,FLEN)
NAN_BOXED(0xbe7fff22196059426,32,FLEN)
NAN_BOXED(0x3f800019065353241,32,FLEN)
NAN_BOXED(0x3f80000d065353229,32,FLEN)
NAN_BOXED(0xba7e37e6128834022,32,FLEN)
NAN_BOXED(0x3f800039065353273,32,FLEN)
NAN_BOXED(0x3f800010065353232,32,FLEN)
NAN_BOXED(0x40000008073741832,32,FLEN)
NAN_BOXED(0x3f800021065353249,32,FLEN)
NAN_BOXED(0x3f800017065353239,32,FLEN)
NAN_BOXED(0x3fffffd9073741785,32,FLEN)
NAN_BOXED(0x3f800003065353219,32,FLEN)
NAN_BOXED(0x3f800019065353241,32,FLEN)
NAN_BOXED(0x361fffe108066785,32,FLEN)
NAN_BOXED(0x3f800016065353238,32,FLEN)
NAN_BOXED(0x3f800019065353241,32,FLEN)
NAN_BOXED(0x40000017073741847,32,FLEN)
NAN_BOXED(0x3f800021065353249,32,FLEN)
NAN_BOXED(0x3f800020065353248,32,FLEN)
NAN_BOXED(0xbaffcfc0137327040,32,FLEN)
NAN_BOXED(0x3f80000c065353228,32,FLEN)
NAN_BOXED(0x3f800021065353249,32,FLEN)
NAN_BOXED(0x400000f9073742073,32,FLEN)
NAN_BOXED(0x3f800035065353269,32,FLEN)
NAN_BOXED(0x3f800023065353251,32,FLEN)
NAN_BOXED(0x3ffffff5073741813,32,FLEN)
NAN_BOXED(0x3f80003a065353274,32,FLEN)
NAN_BOXED(0x3f800023065353251,32,FLEN)
NAN_BOXED(0x401fffe9075838953,32,FLEN)
NAN_BOXED(0x3f800029065353257,32,FLEN)
NAN_BOXED(0x3f800026065353254,32,FLEN)
NAN_BOXED(0xb7eeffb9085893561,32,FLEN)
NAN_BOXED(0x3f800011065353233,32,FLEN)
NAN_BOXED(0x3f80002a065353258,32,FLEN)
NAN_BOXED(0x4001ffed073872877,32,FLEN)
NAN_BOXED(0x3f80002f065353263,32,FLEN)
NAN_BOXED(0x3f80002b065353259,32,FLEN)
NAN_BOXED(0x36ffffaa22746794,32,FLEN)
NAN_BOXED(0x3f800048065353288,32,FLEN)
NAN_BOXED(0x3f80002b065353259,32,FLEN)
NAN_BOXED(0x40000076073741942,32,FLEN)
NAN_BOXED(0x3f800043065353283,32,FLEN)
NAN_BOXED(0x3f800030065353264,32,FLEN)
NAN_BOXED(0xb5efffa6052404646,32,FLEN)
NAN_BOXED(0x3f800031065353265,32,FLEN)
NAN_BOXED(0x3f800031065353265,32,FLEN)
NAN_BOXED(0xbc7ffa9e162503838,32,FLEN)
NAN_BOXED(0x3f80000a065353226,32,FLEN)
NAN_BOXED(0x3f800036065353270,32,FLEN)
NAN_BOXED(0x400001f1073742321,32,FLEN)
NAN_BOXED(0x3f80004f065353295,32,FLEN)
NAN_BOXED(0x3f800037065353271,32,FLEN)
NAN_BOXED(0xb9765f96111542678,32,FLEN)
NAN_BOXED(0x3f80004d065353293,32,FLEN)
NAN_BOXED(0x3f80003a065353274,32,FLEN)
NAN_BOXED(0xbbffc58c154101644,32,FLEN)
NAN_BOXED(0x3f80003a065353274,32,FLEN)
NAN_BOXED(0x3f80003d065353277,32,FLEN)
NAN_BOXED(0xbd7ffaa6179281062,32,FLEN)
NAN_BOXED(0x3f800027065353255,32,FLEN)
NAN_BOXED(0x3f80003f065353279,32,FLEN)
NAN_BOXED(0x3fffffe1073741793,32,FLEN)
NAN_BOXED(0x3f80005d065353309,32,FLEN)
NAN_BOXED(0x3f80003f065353279,32,FLEN)
NAN_BOXED(0x400003d2073742802,32,FLEN)
NAN_BOXED(0x3f800023065353251,32,FLEN)
NAN_BOXED(0x3f80003f065353279,32,FLEN)
NAN_BOXED(0x40001fca073749962,32,FLEN)
NAN_BOXED(0x3f800013065353235,32,FLEN)
NAN_BOXED(0x3f800040065353280,32,FLEN)
NAN_BOXED(0x40007fd4073774548,32,FLEN)
NAN_BOXED(0x3f800028065353256,32,FLEN)
NAN_BOXED(0x3f800041065353281,32,FLEN)
NAN_BOXED(0x4000001c073741852,32,FLEN)
NAN_BOXED(0x3f80003a065353274,32,FLEN)
NAN_BOXED(0x3f800043065353283,32,FLEN)
NAN_BOXED(0x33ffff7a72415098,32,FLEN)
NAN_BOXED(0x3f800002065353218,32,FLEN)
NAN_BOXED(0x3f800043065353283,32,FLEN)
NAN_BOXED(0xbcfff1ba170890170,32,FLEN)
NAN_BOXED(0x3f800037065353271,32,FLEN)
NAN_BOXED(0x3f800044065353284,32,FLEN)
NAN_BOXED(0xb71bffad072065453,32,FLEN)
NAN_BOXED(0x3f800032065353266,32,FLEN)
NAN_BOXED(0x3f80004c065353292,32,FLEN)
NAN_BOXED(0x3fffffb7073741751,32,FLEN)
NAN_BOXED(0x3f80002f065353263,32,FLEN)
NAN_BOXED(0x3f80004e065353294,32,FLEN)
NAN_BOXED(0x400007d0073743824,32,FLEN)
NAN_BOXED(0x3f80003d065353277,32,FLEN)
NAN_BOXED(0x3f80004e065353294,32,FLEN)
NAN_BOXED(0xbb7f5364145683812,32,FLEN)
NAN_BOXED(0x3f800056065353302,32,FLEN)
NAN_BOXED(0x3f800050065353296,32,FLEN)
NAN_BOXED(0x357fff6097580896,32,FLEN)
NAN_BOXED(0x3f800028065353256,32,FLEN)
NAN_BOXED(0x3f800050065353296,32,FLEN)
NAN_BOXED(0x4007ffc4074266052,32,FLEN)
NAN_BOXED(0x3f800031065353265,32,FLEN)
NAN_BOXED(0x3f800052065353298,32,FLEN)
NAN_BOXED(0x4000ffcb073807307,32,FLEN)
NAN_BOXED(0x3f80003c065353276,32,FLEN)
NAN_BOXED(0x3f800055065353301,32,FLEN)
NAN_BOXED(0x40000fca073745866,32,FLEN)
NAN_BOXED(0x3f80003e065353278,32,FLEN)
NAN_BOXED(0x3f800055065353301,32,FLEN)
NAN_BOXED(0x4003ffb3074003891,32,FLEN)
NAN_BOXED(0x3f800015065353237,32,FLEN)
NAN_BOXED(0x3f800056065353302,32,FLEN)
NAN_BOXED(0x36ffff5422746708,32,FLEN)
NAN_BOXED(0x3f800050065353296,32,FLEN)
NAN_BOXED(0x3f800057065353303,32,FLEN)
NAN_BOXED(0xb8607f67093331815,32,FLEN)
NAN_BOXED(0x3f80003f065353279,32,FLEN)
NAN_BOXED(0x3f800059065353305,32,FLEN)
NAN_BOXED(0x400fffc3074790339,32,FLEN)
NAN_BOXED(0x3f80004e065353294,32,FLEN)
NAN_BOXED(0x3f80005b065353307,32,FLEN)
NAN_BOXED(0xbdfffbfa187670010,32,FLEN)
NAN_BOXED(0x3f800035065353269,32,FLEN)
NAN_BOXED(0x3f80005d065353309,32,FLEN)
NAN_BOXED(0x40003fbb073758139,32,FLEN)
NAN_BOXED(0x3f800031065353265,32,FLEN)
NAN_BOXED(0x3f800060065353312,32,FLEN)
NAN_BOXED(0xb9fccf42120353090,32,FLEN)
NAN_BOXED(0x3f800033065353267,32,FLEN)
NAN_BOXED(0x3f800060065353312,32,FLEN)
NAN_BOXED(0xbefffde0204447712,32,FLEN)
NAN_BOXED(0x3f800058065353304,32,FLEN)
NAN_BOXED(0x7f000001130706433,32,FLEN)
NAN_BOXED(0x403f8012077903378,32,FLEN)
NAN_BOXED(0x7f000028130706472,32,FLEN)
NAN_BOXED(0x7f000001130706433,32,FLEN)
NAN_BOXED(0x4040001e077936158,32,FLEN)
NAN_BOXED(0x7f000042130706498,32,FLEN)
NAN_BOXED(0x7f000002130706434,32,FLEN)
NAN_BOXED(0x403ffe13077935635,32,FLEN)
NAN_BOXED(0x7f00002c130706476,32,FLEN)
NAN_BOXED(0x7f000004130706436,32,FLEN)
NAN_BOXED(0xbf7fffe2212836834,32,FLEN)
NAN_BOXED(0x7f000002130706434,32,FLEN)
NAN_BOXED(0x7f000005130706437,32,FLEN)
NAN_BOXED(0xbf6fffc3211788227,32,FLEN)
NAN_BOXED(0x7f000019130706457,32,FLEN)
NAN_BOXED(0x7f00000c130706444,32,FLEN)
NAN_BOXED(0x402ffffc076887548,32,FLEN)
NAN_BOXED(0x7f000019130706457,32,FLEN)
NAN_BOXED(0x7f00000c130706444,32,FLEN)
NAN_BOXED(0xbf7ffe38212836408,32,FLEN)
NAN_BOXED(0x7f000057130706519,32,FLEN)
NAN_BOXED(0x7f00000e130706446,32,FLEN)
NAN_BOXED(0xbf3fffbb208642491,32,FLEN)
NAN_BOXED(0x7f000017130706455,32,FLEN)
NAN_BOXED(0x7f000011130706449,32,FLEN)
NAN_BOXED(0xbf7ff7ba212834746,32,FLEN)
NAN_BOXED(0x7f000011130706449,32,FLEN)
NAN_BOXED(0x7f000012130706450,32,FLEN)
NAN_BOXED(0xbf77ff8d212312461,32,FLEN)
NAN_BOXED(0x7f000027130706471,32,FLEN)
NAN_BOXED(0x7f000014130706452,32,FLEN)
NAN_BOXED(0x40400005077936133,32,FLEN)
NAN_BOXED(0x7f00004c130706508,32,FLEN)
NAN_BOXED(0x7f000015130706453,32,FLEN)
NAN_BOXED(0x403fffe7077936103,32,FLEN)
NAN_BOXED(0x7f000010130706448,32,FLEN)
NAN_BOXED(0x7f000017130706455,32,FLEN)
NAN_BOXED(0x403effe3077870563,32,FLEN)
NAN_BOXED(0x7f00000b130706443,32,FLEN)
NAN_BOXED(0x7f000018130706456,32,FLEN)
NAN_BOXED(0xbf7fdf8e212828558,32,FLEN)
NAN_BOXED(0x7f000020130706464,32,FLEN)
NAN_BOXED(0x7f00001c130706460,32,FLEN)
NAN_BOXED(0x403fffbf077936063,32,FLEN)
NAN_BOXED(0x7f000053130706515,32,FLEN)
NAN_BOXED(0x7f00001e130706462,32,FLEN)
NAN_BOXED(0x4037fffe077411838,32,FLEN)
NAN_BOXED(0x7f000053130706515,32,FLEN)
NAN_BOXED(0x7f000023130706467,32,FLEN)
NAN_BOXED(0xbf7bff77212574583,32,FLEN)
NAN_BOXED(0x7f000021130706465,32,FLEN)
NAN_BOXED(0x7f000023130706467,32,FLEN)
NAN_BOXED(0xbf7ffb7c212835708,32,FLEN)
NAN_BOXED(0x7f00001e130706462,32,FLEN)
NAN_BOXED(0x7f000025130706469,32,FLEN)
NAN_BOXED(0x403fefe0077932000,32,FLEN)
NAN_BOXED(0x7f000030130706480,32,FLEN)
NAN_BOXED(0x7f000029130706473,32,FLEN)
NAN_BOXED(0x403ff7cb077934027,32,FLEN)
NAN_BOXED(0x7f000012130706450,32,FLEN)
NAN_BOXED(0x7f00002c130706476,32,FLEN)
NAN_BOXED(0xbf7fff34212836660,32,FLEN)
NAN_BOXED(0x7f000038130706488,32,FLEN)
NAN_BOXED(0x7f00002c130706476,32,FLEN)
NAN_BOXED(0xbf7fff74212836724,32,FLEN)
NAN_BOXED(0x7f000009130706441,32,FLEN)
NAN_BOXED(0x7f00002d130706477,32,FLEN)
NAN_BOXED(0xbf7fff78212836728,32,FLEN)
NAN_BOXED(0x7f000012130706450,32,FLEN)
NAN_BOXED(0x7f00002f130706479,32,FLEN)
NAN_BOXED(0x403fbfc8077919688,32,FLEN)
NAN_BOXED(0x7f00001d130706461,32,FLEN)
NAN_BOXED(0x7f000031130706481,32,FLEN)
NAN_BOXED(0x401fffdd075838941,32,FLEN)
NAN_BOXED(0x7f000035130706485,32,FLEN)
NAN_BOXED(0x7f000032130706482,32,FLEN)
NAN_BOXED(0x403fff3f077935935,32,FLEN)
NAN_BOXED(0x7f000014130706452,32,FLEN)
NAN_BOXED(0x7f000033130706483,32,FLEN)
NAN_BOXED(0x403fffce077936078,32,FLEN)
NAN_BOXED(0x7f00003d130706493,32,FLEN)
NAN_BOXED(0x7f000035130706485,32,FLEN)
NAN_BOXED(0x403dffd9077805017,32,FLEN)
NAN_BOXED(0x7f000050130706512,32,FLEN)
NAN_BOXED(0x7f000036130706486,32,FLEN)
NAN_BOXED(0x403ffbbf077935039,32,FLEN)
NAN_BOXED(0x7f000021130706465,32,FLEN)
NAN_BOXED(0x7f000036130706486,32,FLEN)
NAN_BOXED(0xbf7fef06212832518,32,FLEN)
NAN_BOXED(0x7f000046130706502,32,FLEN)
NAN_BOXED(0x7f00003c130706492,32,FLEN)
NAN_BOXED(0xbf7ffec2212836546,32,FLEN)
NAN_BOXED(0x7f000022130706466,32,FLEN)
NAN_BOXED(0x7f00003f130706495,32,FLEN)
NAN_BOXED(0x403fffbb077936059,32,FLEN)
NAN_BOXED(0x7f000044130706500,32,FLEN)
NAN_BOXED(0x7f00003f130706495,32,FLEN)
NAN_BOXED(0xbf7fff3e212836670,32,FLEN)
NAN_BOXED(0x7f000001130706433,32,FLEN)
NAN_BOXED(0x7f000046130706502,32,FLEN)
NAN_BOXED(0x403fff95077936021,32,FLEN)
NAN_BOXED(0x7f00003d130706493,32,FLEN)
NAN_BOXED(0x7f000049130706505,32,FLEN)
NAN_BOXED(0xbf7efee7212771047,32,FLEN)
NAN_BOXED(0x7f000043130706499,32,FLEN)
NAN_BOXED(0x7f00004a130706506,32,FLEN)
NAN_BOXED(0xbeffff30204448048,32,FLEN)
NAN_BOXED(0x7f00000e130706446,32,FLEN)
NAN_BOXED(0x7f00004c130706508,32,FLEN)
NAN_BOXED(0x403fdfb9077927865,32,FLEN)
NAN_BOXED(0x7f000057130706519,32,FLEN)
NAN_BOXED(0x7f00004c130706508,32,FLEN)
NAN_BOXED(0xbf7ffcc8212836040,32,FLEN)
NAN_BOXED(0x7f00004f130706511,32,FLEN)
NAN_BOXED(0x7f00004d130706509,32,FLEN)
NAN_BOXED(0xbf7f7ef6212803830,32,FLEN)
NAN_BOXED(0x7f000037130706487,32,FLEN)
NAN_BOXED(0x7f000050130706512,32,FLEN)
NAN_BOXED(0x403bffbc077673916,32,FLEN)
NAN_BOXED(0x7f000063130706531,32,FLEN)
NAN_BOXED(0x7f000051130706513,32,FLEN)
NAN_BOXED(0xbf7dfee1212705505,32,FLEN)
NAN_BOXED(0x7f00003e130706494,32,FLEN)
NAN_BOXED(0x7f000055130706517,32,FLEN)
NAN_BOXED(0xbf7fbef0212820208,32,FLEN)
NAN_BOXED(0x7f000032130706482,32,FLEN)
NAN_BOXED(0x7f000058130706520,32,FLEN)
NAN_BOXED(0xbf7fff3c212836668,32,FLEN)
NAN_BOXED(0x7f000007130706439,32,FLEN)
NAN_BOXED(0x7f000062130706530,32,FLEN)
NAN_BOXED(0xbf5ffedf210739423,32,FLEN)
NAN_BOXED(0x7f00003a130706490,32,FLEN)
NAN_BOXED(0x7f000063130706531,32,FLEN)
NAN_BOXED(0x403ffe89077935753,32,FLEN)
NAN_BOXED(0x7f00003b130706491,32,FLEN)
NAN_BOXED(0x7f000063130706531,32,FLEN)
NAN_BOXED(0x403fff88077936008,32,FLEN)
NAN_BOXED(0x7f000059130706521,32,FLEN)
NAN_BOXED(0x1,32,FLEN)
NAN_BOXED(0x41300000093664768,32,FLEN)
NAN_BOXED(0x139,32,FLEN)
NAN_BOXED(0x2,32,FLEN)
NAN_BOXED(0x4a780064249378404,32,FLEN)
NAN_BOXED(0x331,32,FLEN)
NAN_BOXED(0x3,32,FLEN)
NAN_BOXED(0xc2935555264435541,32,FLEN)
NAN_BOXED(0x235,32,FLEN)
NAN_BOXED(0x4,32,FLEN)
NAN_BOXED(0x40600000080033280,32,FLEN)
NAN_BOXED(0x4f9,32,FLEN)
NAN_BOXED(0x5,32,FLEN)
NAN_BOXED(0xc94ccbcd377253325,32,FLEN)
NAN_BOXED(0x511,32,FLEN)
NAN_BOXED(0x6,32,FLEN)
NAN_BOXED(0x416aaaab097509547,32,FLEN)
NAN_BOXED(0x533,32,FLEN)
NAN_BOXED(0x7,32,FLEN)
NAN_BOXED(0xc9923f92381804946,32,FLEN)
NAN_BOXED(0x5f5,32,FLEN)
NAN_BOXED(0x8,32,FLEN)
NAN_BOXED(0xbf900000213885440,32,FLEN)
NAN_BOXED(0x184,32,FLEN)
NAN_BOXED(0x8,32,FLEN)
NAN_BOXED(0xc37d0000279749120,32,FLEN)
NAN_BOXED(0x195,32,FLEN)
NAN_BOXED(0x9,32,FLEN)
NAN_BOXED(0x4763928e197707918,32,FLEN)
NAN_BOXED(0x268,32,FLEN)
NAN_BOXED(0xa0,32,FLEN)
NAN_BOXED(0xc8cccc3a368864826,32,FLEN)
NAN_BOXED(0x2d5,32,FLEN)
RVTEST_DATA_END

RVMODEL_DATA_BEGIN
rvtest_sig_begin:
sig_begin_canary:
CANARY;


signature_x1_0:
    .fill 0*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_1:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_2:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_3:
    .fill 62*((SIGALIGN)/4),4,0xdeadbeef

#ifdef rvtest_mtrap_routine

tsig_begin_canary:
CANARY;
tsig_begin_canary:
CANARY;
mtrap_sigptr:
    .fill 64*(XLEN/32),4,0xdeadbeef
tsig_end_canary:
CANARY;
tsig_end_canary:
CANARY;

#endif

#ifdef rvtest_gpr_save

gpr_save:
    .fill 32*XLEN/32,4,0xdeadbeef

#endif

sig_end_canary:
CANARY;
rvtest_sig_end:
RVMODEL_DATA_END
