
// -----------
// This file was generated by riscv_ctg (https://github.com/riscv-software-src/riscv-ctg)
// version   : 0.11.0
// timestamp : Tue Jan 30 08:43:50 2024 GMT
// usage     : riscv_ctg \
//                  -- cgf //                  --cgf /home/riscv/riscv-ctg/sample_cgfs/dataset.cgf \
//                  --cgf /home/riscv/riscv-ctg/sample_cgfs/sample_cgfs_fext/RV32H/rv32h_fnmadd.cgf \
 \
//                  -- xlen 32  \
// -----------
//
// -----------
// Copyright (c) 2020. RISC-V International. All rights reserved.
// SPDX-License-Identifier: BSD-3-Clause
// -----------
//
// This assembly file tests the fnmadd.h instruction of the RISC-V RV32F_Zicsr_Zfh,RV32FD_Zicsr,RV64F_Zicsr_Zfh,RV64FD_Zicsr extension for the fnmadd_b1 covergroup.
// 
#include "model_test.h"
#include "arch_test.h"
RVTEST_ISA("RV32IF_Zicsr_Zfh,RV32IFD_Zicsr,RV64IF_Zicsr_Zfh,RV64IFD_Zicsr")

.section .text.init
.globl rvtest_entry_point
rvtest_entry_point:
RVMODEL_BOOT
RVTEST_CODE_BEGIN

#ifdef TEST_CASE_1

RVTEST_CASE(0,"//check ISA:=regex(.*I.*F.*Zfh.*);def TEST_CASE_1=True;",fnmadd_b1)

RVTEST_FP_ENABLE()
RVTEST_VALBASEUPD(x3,test_dataset_0)
RVTEST_SIGBASE(x1,signature_x1_1)

inst_1534:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x1; op2val:0xfc00;
op3val:0x3c00; valaddr_reg:x3; val_offset:4602*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 4602*FLEN/8, x4, x1, x2)

inst_1535:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x1; op2val:0xfc00;
op3val:0xbc00; valaddr_reg:x3; val_offset:4605*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 4605*FLEN/8, x4, x1, x2)

RVTEST_SIGBASE(x1,signature_x1_13)
inst_1536:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x1; op2val:0x7e00;
op3val:0x0; valaddr_reg:x3; val_offset:4608*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 4608*FLEN/8, x4, x1, x2)

inst_1537:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x1; op2val:0x7e00;
op3val:0x8000; valaddr_reg:x3; val_offset:4611*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 4611*FLEN/8, x4, x1, x2)

inst_1538:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x1; op2val:0x7e00;
op3val:0x1; valaddr_reg:x3; val_offset:4614*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 4614*FLEN/8, x4, x1, x2)

inst_1539:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x1; op2val:0x7e00;
op3val:0x8001; valaddr_reg:x3; val_offset:4617*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 4617*FLEN/8, x4, x1, x2)

inst_1540:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x002 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x1; op2val:0x7e00;
op3val:0x2; valaddr_reg:x3; val_offset:4620*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 4620*FLEN/8, x4, x1, x2)

inst_1541:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3fe and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x1; op2val:0x7e00;
op3val:0x83fe; valaddr_reg:x3; val_offset:4623*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 4623*FLEN/8, x4, x1, x2)

inst_1542:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x1; op2val:0x7e00;
op3val:0x3ff; valaddr_reg:x3; val_offset:4626*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 4626*FLEN/8, x4, x1, x2)

inst_1543:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x1; op2val:0x7e00;
op3val:0x83ff; valaddr_reg:x3; val_offset:4629*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 4629*FLEN/8, x4, x1, x2)

inst_1544:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x1; op2val:0x7e00;
op3val:0x400; valaddr_reg:x3; val_offset:4632*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 4632*FLEN/8, x4, x1, x2)

inst_1545:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x1; op2val:0x7e00;
op3val:0x8400; valaddr_reg:x3; val_offset:4635*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 4635*FLEN/8, x4, x1, x2)

inst_1546:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x1; op2val:0x7e00;
op3val:0x401; valaddr_reg:x3; val_offset:4638*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 4638*FLEN/8, x4, x1, x2)

inst_1547:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x1; op2val:0x7e00;
op3val:0x8455; valaddr_reg:x3; val_offset:4641*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 4641*FLEN/8, x4, x1, x2)

inst_1548:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x1; op2val:0x7e00;
op3val:0x7bff; valaddr_reg:x3; val_offset:4644*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 4644*FLEN/8, x4, x1, x2)

inst_1549:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x1; op2val:0x7e00;
op3val:0xfbff; valaddr_reg:x3; val_offset:4647*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 4647*FLEN/8, x4, x1, x2)

inst_1550:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x1; op2val:0x7e00;
op3val:0x7c00; valaddr_reg:x3; val_offset:4650*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 4650*FLEN/8, x4, x1, x2)

inst_1551:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x1; op2val:0x7e00;
op3val:0xfc00; valaddr_reg:x3; val_offset:4653*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 4653*FLEN/8, x4, x1, x2)

inst_1552:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x1; op2val:0x7e00;
op3val:0x7e00; valaddr_reg:x3; val_offset:4656*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 4656*FLEN/8, x4, x1, x2)

inst_1553:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x1; op2val:0x7e00;
op3val:0xfe00; valaddr_reg:x3; val_offset:4659*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 4659*FLEN/8, x4, x1, x2)

inst_1554:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x201 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x1; op2val:0x7e00;
op3val:0x7e01; valaddr_reg:x3; val_offset:4662*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 4662*FLEN/8, x4, x1, x2)

inst_1555:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x255 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x1; op2val:0x7e00;
op3val:0xfe55; valaddr_reg:x3; val_offset:4665*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 4665*FLEN/8, x4, x1, x2)

inst_1556:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x1; op2val:0x7e00;
op3val:0x7c01; valaddr_reg:x3; val_offset:4668*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 4668*FLEN/8, x4, x1, x2)

inst_1557:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x155 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x1; op2val:0x7e00;
op3val:0xfd55; valaddr_reg:x3; val_offset:4671*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 4671*FLEN/8, x4, x1, x2)

inst_1558:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 0 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x1; op2val:0x7e00;
op3val:0x3c00; valaddr_reg:x3; val_offset:4674*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 4674*FLEN/8, x4, x1, x2)

inst_1559:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 1 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x1; op2val:0x7e00;
op3val:0xbc00; valaddr_reg:x3; val_offset:4677*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 4677*FLEN/8, x4, x1, x2)

inst_1560:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x1; op2val:0xfe00;
op3val:0x0; valaddr_reg:x3; val_offset:4680*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 4680*FLEN/8, x4, x1, x2)

inst_1561:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x1; op2val:0xfe00;
op3val:0x8000; valaddr_reg:x3; val_offset:4683*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 4683*FLEN/8, x4, x1, x2)

inst_1562:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x1; op2val:0xfe00;
op3val:0x1; valaddr_reg:x3; val_offset:4686*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 4686*FLEN/8, x4, x1, x2)

inst_1563:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x1; op2val:0xfe00;
op3val:0x8001; valaddr_reg:x3; val_offset:4689*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 4689*FLEN/8, x4, x1, x2)

inst_1564:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x002 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x1; op2val:0xfe00;
op3val:0x2; valaddr_reg:x3; val_offset:4692*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 4692*FLEN/8, x4, x1, x2)

inst_1565:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3fe and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x1; op2val:0xfe00;
op3val:0x83fe; valaddr_reg:x3; val_offset:4695*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 4695*FLEN/8, x4, x1, x2)

inst_1566:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x1; op2val:0xfe00;
op3val:0x3ff; valaddr_reg:x3; val_offset:4698*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 4698*FLEN/8, x4, x1, x2)

inst_1567:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x1; op2val:0xfe00;
op3val:0x83ff; valaddr_reg:x3; val_offset:4701*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 4701*FLEN/8, x4, x1, x2)

inst_1568:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x1; op2val:0xfe00;
op3val:0x400; valaddr_reg:x3; val_offset:4704*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 4704*FLEN/8, x4, x1, x2)

inst_1569:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x1; op2val:0xfe00;
op3val:0x8400; valaddr_reg:x3; val_offset:4707*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 4707*FLEN/8, x4, x1, x2)

inst_1570:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x1; op2val:0xfe00;
op3val:0x401; valaddr_reg:x3; val_offset:4710*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 4710*FLEN/8, x4, x1, x2)

inst_1571:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x1; op2val:0xfe00;
op3val:0x8455; valaddr_reg:x3; val_offset:4713*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 4713*FLEN/8, x4, x1, x2)

inst_1572:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x1; op2val:0xfe00;
op3val:0x7bff; valaddr_reg:x3; val_offset:4716*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 4716*FLEN/8, x4, x1, x2)

inst_1573:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x1; op2val:0xfe00;
op3val:0xfbff; valaddr_reg:x3; val_offset:4719*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 4719*FLEN/8, x4, x1, x2)

inst_1574:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x1; op2val:0xfe00;
op3val:0x7c00; valaddr_reg:x3; val_offset:4722*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 4722*FLEN/8, x4, x1, x2)

inst_1575:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x1; op2val:0xfe00;
op3val:0xfc00; valaddr_reg:x3; val_offset:4725*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 4725*FLEN/8, x4, x1, x2)

inst_1576:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x1; op2val:0xfe00;
op3val:0x7e00; valaddr_reg:x3; val_offset:4728*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 4728*FLEN/8, x4, x1, x2)

inst_1577:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x1; op2val:0xfe00;
op3val:0xfe00; valaddr_reg:x3; val_offset:4731*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 4731*FLEN/8, x4, x1, x2)

inst_1578:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x201 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x1; op2val:0xfe00;
op3val:0x7e01; valaddr_reg:x3; val_offset:4734*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 4734*FLEN/8, x4, x1, x2)

inst_1579:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x255 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x1; op2val:0xfe00;
op3val:0xfe55; valaddr_reg:x3; val_offset:4737*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 4737*FLEN/8, x4, x1, x2)

inst_1580:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x1; op2val:0xfe00;
op3val:0x7c01; valaddr_reg:x3; val_offset:4740*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 4740*FLEN/8, x4, x1, x2)

inst_1581:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x155 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x1; op2val:0xfe00;
op3val:0xfd55; valaddr_reg:x3; val_offset:4743*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 4743*FLEN/8, x4, x1, x2)

inst_1582:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 0 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x1; op2val:0xfe00;
op3val:0x3c00; valaddr_reg:x3; val_offset:4746*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 4746*FLEN/8, x4, x1, x2)

inst_1583:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 1 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x1; op2val:0xfe00;
op3val:0xbc00; valaddr_reg:x3; val_offset:4749*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 4749*FLEN/8, x4, x1, x2)

inst_1584:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x1; op2val:0x7e01;
op3val:0x0; valaddr_reg:x3; val_offset:4752*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 4752*FLEN/8, x4, x1, x2)

inst_1585:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x1; op2val:0x7e01;
op3val:0x8000; valaddr_reg:x3; val_offset:4755*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 4755*FLEN/8, x4, x1, x2)

inst_1586:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x1; op2val:0x7e01;
op3val:0x1; valaddr_reg:x3; val_offset:4758*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 4758*FLEN/8, x4, x1, x2)

inst_1587:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x1; op2val:0x7e01;
op3val:0x8001; valaddr_reg:x3; val_offset:4761*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 4761*FLEN/8, x4, x1, x2)

inst_1588:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x002 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x1; op2val:0x7e01;
op3val:0x2; valaddr_reg:x3; val_offset:4764*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 4764*FLEN/8, x4, x1, x2)

inst_1589:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3fe and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x1; op2val:0x7e01;
op3val:0x83fe; valaddr_reg:x3; val_offset:4767*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 4767*FLEN/8, x4, x1, x2)

inst_1590:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x1; op2val:0x7e01;
op3val:0x3ff; valaddr_reg:x3; val_offset:4770*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 4770*FLEN/8, x4, x1, x2)

inst_1591:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x1; op2val:0x7e01;
op3val:0x83ff; valaddr_reg:x3; val_offset:4773*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 4773*FLEN/8, x4, x1, x2)

inst_1592:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x1; op2val:0x7e01;
op3val:0x400; valaddr_reg:x3; val_offset:4776*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 4776*FLEN/8, x4, x1, x2)

inst_1593:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x1; op2val:0x7e01;
op3val:0x8400; valaddr_reg:x3; val_offset:4779*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 4779*FLEN/8, x4, x1, x2)

inst_1594:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x1; op2val:0x7e01;
op3val:0x401; valaddr_reg:x3; val_offset:4782*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 4782*FLEN/8, x4, x1, x2)

inst_1595:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x1; op2val:0x7e01;
op3val:0x8455; valaddr_reg:x3; val_offset:4785*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 4785*FLEN/8, x4, x1, x2)

inst_1596:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x1; op2val:0x7e01;
op3val:0x7bff; valaddr_reg:x3; val_offset:4788*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 4788*FLEN/8, x4, x1, x2)

inst_1597:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x1; op2val:0x7e01;
op3val:0xfbff; valaddr_reg:x3; val_offset:4791*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 4791*FLEN/8, x4, x1, x2)

inst_1598:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x1; op2val:0x7e01;
op3val:0x7c00; valaddr_reg:x3; val_offset:4794*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 4794*FLEN/8, x4, x1, x2)

inst_1599:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x1; op2val:0x7e01;
op3val:0xfc00; valaddr_reg:x3; val_offset:4797*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 4797*FLEN/8, x4, x1, x2)

inst_1600:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x1; op2val:0x7e01;
op3val:0x7e00; valaddr_reg:x3; val_offset:4800*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 4800*FLEN/8, x4, x1, x2)

inst_1601:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x1; op2val:0x7e01;
op3val:0xfe00; valaddr_reg:x3; val_offset:4803*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 4803*FLEN/8, x4, x1, x2)

inst_1602:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x201 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x1; op2val:0x7e01;
op3val:0x7e01; valaddr_reg:x3; val_offset:4806*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 4806*FLEN/8, x4, x1, x2)

inst_1603:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x255 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x1; op2val:0x7e01;
op3val:0xfe55; valaddr_reg:x3; val_offset:4809*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 4809*FLEN/8, x4, x1, x2)

inst_1604:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x1; op2val:0x7e01;
op3val:0x7c01; valaddr_reg:x3; val_offset:4812*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 4812*FLEN/8, x4, x1, x2)

inst_1605:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x155 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x1; op2val:0x7e01;
op3val:0xfd55; valaddr_reg:x3; val_offset:4815*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 4815*FLEN/8, x4, x1, x2)

inst_1606:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fs3 == 0 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x1; op2val:0x7e01;
op3val:0x3c00; valaddr_reg:x3; val_offset:4818*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 4818*FLEN/8, x4, x1, x2)

inst_1607:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fs3 == 1 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x1; op2val:0x7e01;
op3val:0xbc00; valaddr_reg:x3; val_offset:4821*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 4821*FLEN/8, x4, x1, x2)

inst_1608:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x1; op2val:0xfe55;
op3val:0x0; valaddr_reg:x3; val_offset:4824*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 4824*FLEN/8, x4, x1, x2)

inst_1609:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x1; op2val:0xfe55;
op3val:0x8000; valaddr_reg:x3; val_offset:4827*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 4827*FLEN/8, x4, x1, x2)

inst_1610:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x1; op2val:0xfe55;
op3val:0x1; valaddr_reg:x3; val_offset:4830*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 4830*FLEN/8, x4, x1, x2)

inst_1611:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x1; op2val:0xfe55;
op3val:0x8001; valaddr_reg:x3; val_offset:4833*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 4833*FLEN/8, x4, x1, x2)

inst_1612:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x002 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x1; op2val:0xfe55;
op3val:0x2; valaddr_reg:x3; val_offset:4836*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 4836*FLEN/8, x4, x1, x2)

inst_1613:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3fe and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x1; op2val:0xfe55;
op3val:0x83fe; valaddr_reg:x3; val_offset:4839*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 4839*FLEN/8, x4, x1, x2)

inst_1614:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x1; op2val:0xfe55;
op3val:0x3ff; valaddr_reg:x3; val_offset:4842*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 4842*FLEN/8, x4, x1, x2)

inst_1615:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x1; op2val:0xfe55;
op3val:0x83ff; valaddr_reg:x3; val_offset:4845*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 4845*FLEN/8, x4, x1, x2)

inst_1616:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x1; op2val:0xfe55;
op3val:0x400; valaddr_reg:x3; val_offset:4848*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 4848*FLEN/8, x4, x1, x2)

inst_1617:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x1; op2val:0xfe55;
op3val:0x8400; valaddr_reg:x3; val_offset:4851*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 4851*FLEN/8, x4, x1, x2)

inst_1618:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x1; op2val:0xfe55;
op3val:0x401; valaddr_reg:x3; val_offset:4854*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 4854*FLEN/8, x4, x1, x2)

inst_1619:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x1; op2val:0xfe55;
op3val:0x8455; valaddr_reg:x3; val_offset:4857*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 4857*FLEN/8, x4, x1, x2)

inst_1620:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x1; op2val:0xfe55;
op3val:0x7bff; valaddr_reg:x3; val_offset:4860*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 4860*FLEN/8, x4, x1, x2)

inst_1621:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x1; op2val:0xfe55;
op3val:0xfbff; valaddr_reg:x3; val_offset:4863*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 4863*FLEN/8, x4, x1, x2)

inst_1622:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x1; op2val:0xfe55;
op3val:0x7c00; valaddr_reg:x3; val_offset:4866*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 4866*FLEN/8, x4, x1, x2)

inst_1623:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x1; op2val:0xfe55;
op3val:0xfc00; valaddr_reg:x3; val_offset:4869*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 4869*FLEN/8, x4, x1, x2)

inst_1624:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x1; op2val:0xfe55;
op3val:0x7e00; valaddr_reg:x3; val_offset:4872*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 4872*FLEN/8, x4, x1, x2)

inst_1625:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x1; op2val:0xfe55;
op3val:0xfe00; valaddr_reg:x3; val_offset:4875*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 4875*FLEN/8, x4, x1, x2)

inst_1626:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x201 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x1; op2val:0xfe55;
op3val:0x7e01; valaddr_reg:x3; val_offset:4878*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 4878*FLEN/8, x4, x1, x2)

inst_1627:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x255 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x1; op2val:0xfe55;
op3val:0xfe55; valaddr_reg:x3; val_offset:4881*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 4881*FLEN/8, x4, x1, x2)

inst_1628:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x1; op2val:0xfe55;
op3val:0x7c01; valaddr_reg:x3; val_offset:4884*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 4884*FLEN/8, x4, x1, x2)

inst_1629:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x155 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x1; op2val:0xfe55;
op3val:0xfd55; valaddr_reg:x3; val_offset:4887*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 4887*FLEN/8, x4, x1, x2)

inst_1630:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fs3 == 0 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x1; op2val:0xfe55;
op3val:0x3c00; valaddr_reg:x3; val_offset:4890*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 4890*FLEN/8, x4, x1, x2)

inst_1631:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fs3 == 1 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x1; op2val:0xfe55;
op3val:0xbc00; valaddr_reg:x3; val_offset:4893*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 4893*FLEN/8, x4, x1, x2)

inst_1632:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x1; op2val:0x7c01;
op3val:0x0; valaddr_reg:x3; val_offset:4896*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 4896*FLEN/8, x4, x1, x2)

inst_1633:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x1; op2val:0x7c01;
op3val:0x8000; valaddr_reg:x3; val_offset:4899*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 4899*FLEN/8, x4, x1, x2)

inst_1634:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x1; op2val:0x7c01;
op3val:0x1; valaddr_reg:x3; val_offset:4902*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 4902*FLEN/8, x4, x1, x2)

inst_1635:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x1; op2val:0x7c01;
op3val:0x8001; valaddr_reg:x3; val_offset:4905*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 4905*FLEN/8, x4, x1, x2)

inst_1636:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x002 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x1; op2val:0x7c01;
op3val:0x2; valaddr_reg:x3; val_offset:4908*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 4908*FLEN/8, x4, x1, x2)

inst_1637:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3fe and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x1; op2val:0x7c01;
op3val:0x83fe; valaddr_reg:x3; val_offset:4911*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 4911*FLEN/8, x4, x1, x2)

inst_1638:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x1; op2val:0x7c01;
op3val:0x3ff; valaddr_reg:x3; val_offset:4914*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 4914*FLEN/8, x4, x1, x2)

inst_1639:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x1; op2val:0x7c01;
op3val:0x83ff; valaddr_reg:x3; val_offset:4917*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 4917*FLEN/8, x4, x1, x2)

inst_1640:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x1; op2val:0x7c01;
op3val:0x400; valaddr_reg:x3; val_offset:4920*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 4920*FLEN/8, x4, x1, x2)

inst_1641:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x1; op2val:0x7c01;
op3val:0x8400; valaddr_reg:x3; val_offset:4923*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 4923*FLEN/8, x4, x1, x2)

inst_1642:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x1; op2val:0x7c01;
op3val:0x401; valaddr_reg:x3; val_offset:4926*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 4926*FLEN/8, x4, x1, x2)

inst_1643:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x1; op2val:0x7c01;
op3val:0x8455; valaddr_reg:x3; val_offset:4929*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 4929*FLEN/8, x4, x1, x2)

inst_1644:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x1; op2val:0x7c01;
op3val:0x7bff; valaddr_reg:x3; val_offset:4932*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 4932*FLEN/8, x4, x1, x2)

inst_1645:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x1; op2val:0x7c01;
op3val:0xfbff; valaddr_reg:x3; val_offset:4935*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 4935*FLEN/8, x4, x1, x2)

inst_1646:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x1; op2val:0x7c01;
op3val:0x7c00; valaddr_reg:x3; val_offset:4938*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 4938*FLEN/8, x4, x1, x2)

inst_1647:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x1; op2val:0x7c01;
op3val:0xfc00; valaddr_reg:x3; val_offset:4941*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 4941*FLEN/8, x4, x1, x2)

inst_1648:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x1; op2val:0x7c01;
op3val:0x7e00; valaddr_reg:x3; val_offset:4944*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 4944*FLEN/8, x4, x1, x2)

inst_1649:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x1; op2val:0x7c01;
op3val:0xfe00; valaddr_reg:x3; val_offset:4947*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 4947*FLEN/8, x4, x1, x2)

inst_1650:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x201 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x1; op2val:0x7c01;
op3val:0x7e01; valaddr_reg:x3; val_offset:4950*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 4950*FLEN/8, x4, x1, x2)

inst_1651:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x255 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x1; op2val:0x7c01;
op3val:0xfe55; valaddr_reg:x3; val_offset:4953*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 4953*FLEN/8, x4, x1, x2)

inst_1652:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x1; op2val:0x7c01;
op3val:0x7c01; valaddr_reg:x3; val_offset:4956*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 4956*FLEN/8, x4, x1, x2)

inst_1653:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x155 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x1; op2val:0x7c01;
op3val:0xfd55; valaddr_reg:x3; val_offset:4959*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 4959*FLEN/8, x4, x1, x2)

inst_1654:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fs3 == 0 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x1; op2val:0x7c01;
op3val:0x3c00; valaddr_reg:x3; val_offset:4962*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 4962*FLEN/8, x4, x1, x2)

inst_1655:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fs3 == 1 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x1; op2val:0x7c01;
op3val:0xbc00; valaddr_reg:x3; val_offset:4965*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 4965*FLEN/8, x4, x1, x2)

inst_1656:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x1; op2val:0xfd55;
op3val:0x0; valaddr_reg:x3; val_offset:4968*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 4968*FLEN/8, x4, x1, x2)

inst_1657:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x1; op2val:0xfd55;
op3val:0x8000; valaddr_reg:x3; val_offset:4971*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 4971*FLEN/8, x4, x1, x2)

inst_1658:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x1; op2val:0xfd55;
op3val:0x1; valaddr_reg:x3; val_offset:4974*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 4974*FLEN/8, x4, x1, x2)

inst_1659:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x1; op2val:0xfd55;
op3val:0x8001; valaddr_reg:x3; val_offset:4977*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 4977*FLEN/8, x4, x1, x2)

inst_1660:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x002 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x1; op2val:0xfd55;
op3val:0x2; valaddr_reg:x3; val_offset:4980*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 4980*FLEN/8, x4, x1, x2)

inst_1661:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3fe and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x1; op2val:0xfd55;
op3val:0x83fe; valaddr_reg:x3; val_offset:4983*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 4983*FLEN/8, x4, x1, x2)

inst_1662:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x1; op2val:0xfd55;
op3val:0x3ff; valaddr_reg:x3; val_offset:4986*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 4986*FLEN/8, x4, x1, x2)

inst_1663:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x1; op2val:0xfd55;
op3val:0x83ff; valaddr_reg:x3; val_offset:4989*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 4989*FLEN/8, x4, x1, x2)

RVTEST_SIGBASE(x1,signature_x1_14)
inst_1664:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x1; op2val:0xfd55;
op3val:0x400; valaddr_reg:x3; val_offset:4992*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 4992*FLEN/8, x4, x1, x2)

inst_1665:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x1; op2val:0xfd55;
op3val:0x8400; valaddr_reg:x3; val_offset:4995*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 4995*FLEN/8, x4, x1, x2)

inst_1666:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x1; op2val:0xfd55;
op3val:0x401; valaddr_reg:x3; val_offset:4998*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 4998*FLEN/8, x4, x1, x2)

inst_1667:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x1; op2val:0xfd55;
op3val:0x8455; valaddr_reg:x3; val_offset:5001*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 5001*FLEN/8, x4, x1, x2)

inst_1668:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x1; op2val:0xfd55;
op3val:0x7bff; valaddr_reg:x3; val_offset:5004*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 5004*FLEN/8, x4, x1, x2)

inst_1669:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x1; op2val:0xfd55;
op3val:0xfbff; valaddr_reg:x3; val_offset:5007*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 5007*FLEN/8, x4, x1, x2)

inst_1670:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x1; op2val:0xfd55;
op3val:0x7c00; valaddr_reg:x3; val_offset:5010*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 5010*FLEN/8, x4, x1, x2)

inst_1671:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x1; op2val:0xfd55;
op3val:0xfc00; valaddr_reg:x3; val_offset:5013*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 5013*FLEN/8, x4, x1, x2)

inst_1672:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x1; op2val:0xfd55;
op3val:0x7e00; valaddr_reg:x3; val_offset:5016*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 5016*FLEN/8, x4, x1, x2)

inst_1673:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x1; op2val:0xfd55;
op3val:0xfe00; valaddr_reg:x3; val_offset:5019*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 5019*FLEN/8, x4, x1, x2)

inst_1674:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x201 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x1; op2val:0xfd55;
op3val:0x7e01; valaddr_reg:x3; val_offset:5022*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 5022*FLEN/8, x4, x1, x2)

inst_1675:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x255 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x1; op2val:0xfd55;
op3val:0xfe55; valaddr_reg:x3; val_offset:5025*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 5025*FLEN/8, x4, x1, x2)

inst_1676:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x1; op2val:0xfd55;
op3val:0x7c01; valaddr_reg:x3; val_offset:5028*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 5028*FLEN/8, x4, x1, x2)

inst_1677:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x155 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x1; op2val:0xfd55;
op3val:0xfd55; valaddr_reg:x3; val_offset:5031*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 5031*FLEN/8, x4, x1, x2)

inst_1678:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fs3 == 0 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x1; op2val:0xfd55;
op3val:0x3c00; valaddr_reg:x3; val_offset:5034*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 5034*FLEN/8, x4, x1, x2)

inst_1679:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fs3 == 1 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x1; op2val:0xfd55;
op3val:0xbc00; valaddr_reg:x3; val_offset:5037*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 5037*FLEN/8, x4, x1, x2)

inst_1680:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x1; op2val:0x3c00;
op3val:0x0; valaddr_reg:x3; val_offset:5040*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 5040*FLEN/8, x4, x1, x2)

inst_1681:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x1; op2val:0x3c00;
op3val:0x8000; valaddr_reg:x3; val_offset:5043*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 5043*FLEN/8, x4, x1, x2)

inst_1682:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x1; op2val:0x3c00;
op3val:0x1; valaddr_reg:x3; val_offset:5046*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 5046*FLEN/8, x4, x1, x2)

inst_1683:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x1; op2val:0x3c00;
op3val:0x8001; valaddr_reg:x3; val_offset:5049*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 5049*FLEN/8, x4, x1, x2)

inst_1684:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x002 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x1; op2val:0x3c00;
op3val:0x2; valaddr_reg:x3; val_offset:5052*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 5052*FLEN/8, x4, x1, x2)

inst_1685:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3fe and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x1; op2val:0x3c00;
op3val:0x83fe; valaddr_reg:x3; val_offset:5055*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 5055*FLEN/8, x4, x1, x2)

inst_1686:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x1; op2val:0x3c00;
op3val:0x3ff; valaddr_reg:x3; val_offset:5058*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 5058*FLEN/8, x4, x1, x2)

inst_1687:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x1; op2val:0x3c00;
op3val:0x83ff; valaddr_reg:x3; val_offset:5061*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 5061*FLEN/8, x4, x1, x2)

inst_1688:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x1; op2val:0x3c00;
op3val:0x400; valaddr_reg:x3; val_offset:5064*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 5064*FLEN/8, x4, x1, x2)

inst_1689:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x1; op2val:0x3c00;
op3val:0x8400; valaddr_reg:x3; val_offset:5067*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 5067*FLEN/8, x4, x1, x2)

inst_1690:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x1; op2val:0x3c00;
op3val:0x401; valaddr_reg:x3; val_offset:5070*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 5070*FLEN/8, x4, x1, x2)

inst_1691:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x1; op2val:0x3c00;
op3val:0x8455; valaddr_reg:x3; val_offset:5073*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 5073*FLEN/8, x4, x1, x2)

inst_1692:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x1; op2val:0x3c00;
op3val:0x7bff; valaddr_reg:x3; val_offset:5076*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 5076*FLEN/8, x4, x1, x2)

inst_1693:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x1; op2val:0x3c00;
op3val:0xfbff; valaddr_reg:x3; val_offset:5079*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 5079*FLEN/8, x4, x1, x2)

inst_1694:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x1; op2val:0x3c00;
op3val:0x7c00; valaddr_reg:x3; val_offset:5082*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 5082*FLEN/8, x4, x1, x2)

inst_1695:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x1; op2val:0x3c00;
op3val:0xfc00; valaddr_reg:x3; val_offset:5085*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 5085*FLEN/8, x4, x1, x2)

inst_1696:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x1; op2val:0x3c00;
op3val:0x7e00; valaddr_reg:x3; val_offset:5088*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 5088*FLEN/8, x4, x1, x2)

inst_1697:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x1; op2val:0x3c00;
op3val:0xfe00; valaddr_reg:x3; val_offset:5091*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 5091*FLEN/8, x4, x1, x2)

inst_1698:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x201 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x1; op2val:0x3c00;
op3val:0x7e01; valaddr_reg:x3; val_offset:5094*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 5094*FLEN/8, x4, x1, x2)

inst_1699:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x255 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x1; op2val:0x3c00;
op3val:0xfe55; valaddr_reg:x3; val_offset:5097*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 5097*FLEN/8, x4, x1, x2)

inst_1700:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x1; op2val:0x3c00;
op3val:0x7c01; valaddr_reg:x3; val_offset:5100*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 5100*FLEN/8, x4, x1, x2)

inst_1701:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x155 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x1; op2val:0x3c00;
op3val:0xfd55; valaddr_reg:x3; val_offset:5103*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 5103*FLEN/8, x4, x1, x2)

inst_1702:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x1; op2val:0x3c00;
op3val:0x3c00; valaddr_reg:x3; val_offset:5106*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 5106*FLEN/8, x4, x1, x2)

inst_1703:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x1; op2val:0x3c00;
op3val:0xbc00; valaddr_reg:x3; val_offset:5109*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 5109*FLEN/8, x4, x1, x2)

inst_1704:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x1; op2val:0xbc00;
op3val:0x0; valaddr_reg:x3; val_offset:5112*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 5112*FLEN/8, x4, x1, x2)

inst_1705:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x1; op2val:0xbc00;
op3val:0x8000; valaddr_reg:x3; val_offset:5115*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 5115*FLEN/8, x4, x1, x2)

inst_1706:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x1; op2val:0xbc00;
op3val:0x1; valaddr_reg:x3; val_offset:5118*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 5118*FLEN/8, x4, x1, x2)

inst_1707:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x1; op2val:0xbc00;
op3val:0x8001; valaddr_reg:x3; val_offset:5121*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 5121*FLEN/8, x4, x1, x2)

inst_1708:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x002 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x1; op2val:0xbc00;
op3val:0x2; valaddr_reg:x3; val_offset:5124*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 5124*FLEN/8, x4, x1, x2)

inst_1709:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3fe and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x1; op2val:0xbc00;
op3val:0x83fe; valaddr_reg:x3; val_offset:5127*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 5127*FLEN/8, x4, x1, x2)

inst_1710:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x1; op2val:0xbc00;
op3val:0x3ff; valaddr_reg:x3; val_offset:5130*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 5130*FLEN/8, x4, x1, x2)

inst_1711:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x1; op2val:0xbc00;
op3val:0x83ff; valaddr_reg:x3; val_offset:5133*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 5133*FLEN/8, x4, x1, x2)

inst_1712:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x1; op2val:0xbc00;
op3val:0x400; valaddr_reg:x3; val_offset:5136*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 5136*FLEN/8, x4, x1, x2)

inst_1713:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x1; op2val:0xbc00;
op3val:0x8400; valaddr_reg:x3; val_offset:5139*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 5139*FLEN/8, x4, x1, x2)

inst_1714:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x1; op2val:0xbc00;
op3val:0x401; valaddr_reg:x3; val_offset:5142*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 5142*FLEN/8, x4, x1, x2)

inst_1715:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x1; op2val:0xbc00;
op3val:0x8455; valaddr_reg:x3; val_offset:5145*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 5145*FLEN/8, x4, x1, x2)

inst_1716:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x1; op2val:0xbc00;
op3val:0x7bff; valaddr_reg:x3; val_offset:5148*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 5148*FLEN/8, x4, x1, x2)

inst_1717:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x1; op2val:0xbc00;
op3val:0xfbff; valaddr_reg:x3; val_offset:5151*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 5151*FLEN/8, x4, x1, x2)

inst_1718:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x1; op2val:0xbc00;
op3val:0x7c00; valaddr_reg:x3; val_offset:5154*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 5154*FLEN/8, x4, x1, x2)

inst_1719:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x1; op2val:0xbc00;
op3val:0xfc00; valaddr_reg:x3; val_offset:5157*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 5157*FLEN/8, x4, x1, x2)

inst_1720:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x1; op2val:0xbc00;
op3val:0x7e00; valaddr_reg:x3; val_offset:5160*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 5160*FLEN/8, x4, x1, x2)

inst_1721:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x1; op2val:0xbc00;
op3val:0xfe00; valaddr_reg:x3; val_offset:5163*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 5163*FLEN/8, x4, x1, x2)

inst_1722:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x201 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x1; op2val:0xbc00;
op3val:0x7e01; valaddr_reg:x3; val_offset:5166*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 5166*FLEN/8, x4, x1, x2)

inst_1723:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x255 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x1; op2val:0xbc00;
op3val:0xfe55; valaddr_reg:x3; val_offset:5169*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 5169*FLEN/8, x4, x1, x2)

inst_1724:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x1; op2val:0xbc00;
op3val:0x7c01; valaddr_reg:x3; val_offset:5172*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 5172*FLEN/8, x4, x1, x2)

inst_1725:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x155 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x1; op2val:0xbc00;
op3val:0xfd55; valaddr_reg:x3; val_offset:5175*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 5175*FLEN/8, x4, x1, x2)

inst_1726:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x1; op2val:0xbc00;
op3val:0x3c00; valaddr_reg:x3; val_offset:5178*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 5178*FLEN/8, x4, x1, x2)

inst_1727:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x1; op2val:0xbc00;
op3val:0xbc00; valaddr_reg:x3; val_offset:5181*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 5181*FLEN/8, x4, x1, x2)

inst_1728:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x8001; op2val:0x0;
op3val:0x0; valaddr_reg:x3; val_offset:5184*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 5184*FLEN/8, x4, x1, x2)

inst_1729:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x8001; op2val:0x0;
op3val:0x8000; valaddr_reg:x3; val_offset:5187*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 5187*FLEN/8, x4, x1, x2)

inst_1730:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x8001; op2val:0x0;
op3val:0x1; valaddr_reg:x3; val_offset:5190*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 5190*FLEN/8, x4, x1, x2)

inst_1731:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x8001; op2val:0x0;
op3val:0x8001; valaddr_reg:x3; val_offset:5193*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 5193*FLEN/8, x4, x1, x2)

inst_1732:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x002 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x8001; op2val:0x0;
op3val:0x2; valaddr_reg:x3; val_offset:5196*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 5196*FLEN/8, x4, x1, x2)

inst_1733:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3fe and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x8001; op2val:0x0;
op3val:0x83fe; valaddr_reg:x3; val_offset:5199*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 5199*FLEN/8, x4, x1, x2)

inst_1734:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x8001; op2val:0x0;
op3val:0x3ff; valaddr_reg:x3; val_offset:5202*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 5202*FLEN/8, x4, x1, x2)

inst_1735:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x8001; op2val:0x0;
op3val:0x83ff; valaddr_reg:x3; val_offset:5205*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 5205*FLEN/8, x4, x1, x2)

inst_1736:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x8001; op2val:0x0;
op3val:0x400; valaddr_reg:x3; val_offset:5208*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 5208*FLEN/8, x4, x1, x2)

inst_1737:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x8001; op2val:0x0;
op3val:0x8400; valaddr_reg:x3; val_offset:5211*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 5211*FLEN/8, x4, x1, x2)

inst_1738:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x8001; op2val:0x0;
op3val:0x401; valaddr_reg:x3; val_offset:5214*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 5214*FLEN/8, x4, x1, x2)

inst_1739:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x8001; op2val:0x0;
op3val:0x8455; valaddr_reg:x3; val_offset:5217*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 5217*FLEN/8, x4, x1, x2)

inst_1740:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x8001; op2val:0x0;
op3val:0x7bff; valaddr_reg:x3; val_offset:5220*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 5220*FLEN/8, x4, x1, x2)

inst_1741:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x8001; op2val:0x0;
op3val:0xfbff; valaddr_reg:x3; val_offset:5223*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 5223*FLEN/8, x4, x1, x2)

inst_1742:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x8001; op2val:0x0;
op3val:0x7c00; valaddr_reg:x3; val_offset:5226*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 5226*FLEN/8, x4, x1, x2)

inst_1743:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x8001; op2val:0x0;
op3val:0xfc00; valaddr_reg:x3; val_offset:5229*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 5229*FLEN/8, x4, x1, x2)

inst_1744:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x8001; op2val:0x0;
op3val:0x7e00; valaddr_reg:x3; val_offset:5232*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 5232*FLEN/8, x4, x1, x2)

inst_1745:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x8001; op2val:0x0;
op3val:0xfe00; valaddr_reg:x3; val_offset:5235*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 5235*FLEN/8, x4, x1, x2)

inst_1746:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x201 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x8001; op2val:0x0;
op3val:0x7e01; valaddr_reg:x3; val_offset:5238*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 5238*FLEN/8, x4, x1, x2)

inst_1747:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x255 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x8001; op2val:0x0;
op3val:0xfe55; valaddr_reg:x3; val_offset:5241*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 5241*FLEN/8, x4, x1, x2)

inst_1748:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x8001; op2val:0x0;
op3val:0x7c01; valaddr_reg:x3; val_offset:5244*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 5244*FLEN/8, x4, x1, x2)

inst_1749:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x155 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x8001; op2val:0x0;
op3val:0xfd55; valaddr_reg:x3; val_offset:5247*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 5247*FLEN/8, x4, x1, x2)

inst_1750:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x8001; op2val:0x0;
op3val:0x3c00; valaddr_reg:x3; val_offset:5250*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 5250*FLEN/8, x4, x1, x2)

inst_1751:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x8001; op2val:0x0;
op3val:0xbc00; valaddr_reg:x3; val_offset:5253*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 5253*FLEN/8, x4, x1, x2)

inst_1752:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x8001; op2val:0x8000;
op3val:0x0; valaddr_reg:x3; val_offset:5256*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 5256*FLEN/8, x4, x1, x2)

inst_1753:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x8001; op2val:0x8000;
op3val:0x8000; valaddr_reg:x3; val_offset:5259*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 5259*FLEN/8, x4, x1, x2)

inst_1754:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x8001; op2val:0x8000;
op3val:0x1; valaddr_reg:x3; val_offset:5262*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 5262*FLEN/8, x4, x1, x2)

inst_1755:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x8001; op2val:0x8000;
op3val:0x8001; valaddr_reg:x3; val_offset:5265*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 5265*FLEN/8, x4, x1, x2)

inst_1756:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x002 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x8001; op2val:0x8000;
op3val:0x2; valaddr_reg:x3; val_offset:5268*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 5268*FLEN/8, x4, x1, x2)

inst_1757:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3fe and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x8001; op2val:0x8000;
op3val:0x83fe; valaddr_reg:x3; val_offset:5271*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 5271*FLEN/8, x4, x1, x2)

inst_1758:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x8001; op2val:0x8000;
op3val:0x3ff; valaddr_reg:x3; val_offset:5274*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 5274*FLEN/8, x4, x1, x2)

inst_1759:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x8001; op2val:0x8000;
op3val:0x83ff; valaddr_reg:x3; val_offset:5277*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 5277*FLEN/8, x4, x1, x2)

inst_1760:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x8001; op2val:0x8000;
op3val:0x400; valaddr_reg:x3; val_offset:5280*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 5280*FLEN/8, x4, x1, x2)

inst_1761:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x8001; op2val:0x8000;
op3val:0x8400; valaddr_reg:x3; val_offset:5283*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 5283*FLEN/8, x4, x1, x2)

inst_1762:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x8001; op2val:0x8000;
op3val:0x401; valaddr_reg:x3; val_offset:5286*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 5286*FLEN/8, x4, x1, x2)

inst_1763:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x8001; op2val:0x8000;
op3val:0x8455; valaddr_reg:x3; val_offset:5289*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 5289*FLEN/8, x4, x1, x2)

inst_1764:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x8001; op2val:0x8000;
op3val:0x7bff; valaddr_reg:x3; val_offset:5292*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 5292*FLEN/8, x4, x1, x2)

inst_1765:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x8001; op2val:0x8000;
op3val:0xfbff; valaddr_reg:x3; val_offset:5295*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 5295*FLEN/8, x4, x1, x2)

inst_1766:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x8001; op2val:0x8000;
op3val:0x7c00; valaddr_reg:x3; val_offset:5298*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 5298*FLEN/8, x4, x1, x2)

inst_1767:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x8001; op2val:0x8000;
op3val:0xfc00; valaddr_reg:x3; val_offset:5301*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 5301*FLEN/8, x4, x1, x2)

inst_1768:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x8001; op2val:0x8000;
op3val:0x7e00; valaddr_reg:x3; val_offset:5304*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 5304*FLEN/8, x4, x1, x2)

inst_1769:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x8001; op2val:0x8000;
op3val:0xfe00; valaddr_reg:x3; val_offset:5307*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 5307*FLEN/8, x4, x1, x2)

inst_1770:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x201 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x8001; op2val:0x8000;
op3val:0x7e01; valaddr_reg:x3; val_offset:5310*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 5310*FLEN/8, x4, x1, x2)

inst_1771:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x255 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x8001; op2val:0x8000;
op3val:0xfe55; valaddr_reg:x3; val_offset:5313*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 5313*FLEN/8, x4, x1, x2)

inst_1772:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x8001; op2val:0x8000;
op3val:0x7c01; valaddr_reg:x3; val_offset:5316*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 5316*FLEN/8, x4, x1, x2)

inst_1773:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x155 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x8001; op2val:0x8000;
op3val:0xfd55; valaddr_reg:x3; val_offset:5319*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 5319*FLEN/8, x4, x1, x2)

inst_1774:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x8001; op2val:0x8000;
op3val:0x3c00; valaddr_reg:x3; val_offset:5322*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 5322*FLEN/8, x4, x1, x2)

inst_1775:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x8001; op2val:0x8000;
op3val:0xbc00; valaddr_reg:x3; val_offset:5325*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 5325*FLEN/8, x4, x1, x2)

inst_1776:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x8001; op2val:0x1;
op3val:0x0; valaddr_reg:x3; val_offset:5328*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 5328*FLEN/8, x4, x1, x2)

inst_1777:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x8001; op2val:0x1;
op3val:0x8000; valaddr_reg:x3; val_offset:5331*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 5331*FLEN/8, x4, x1, x2)

inst_1778:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x8001; op2val:0x1;
op3val:0x1; valaddr_reg:x3; val_offset:5334*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 5334*FLEN/8, x4, x1, x2)

inst_1779:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x8001; op2val:0x1;
op3val:0x8001; valaddr_reg:x3; val_offset:5337*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 5337*FLEN/8, x4, x1, x2)

inst_1780:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x002 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x8001; op2val:0x1;
op3val:0x2; valaddr_reg:x3; val_offset:5340*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 5340*FLEN/8, x4, x1, x2)

inst_1781:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3fe and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x8001; op2val:0x1;
op3val:0x83fe; valaddr_reg:x3; val_offset:5343*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 5343*FLEN/8, x4, x1, x2)

inst_1782:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x8001; op2val:0x1;
op3val:0x3ff; valaddr_reg:x3; val_offset:5346*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 5346*FLEN/8, x4, x1, x2)

inst_1783:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x8001; op2val:0x1;
op3val:0x83ff; valaddr_reg:x3; val_offset:5349*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 5349*FLEN/8, x4, x1, x2)

inst_1784:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x8001; op2val:0x1;
op3val:0x400; valaddr_reg:x3; val_offset:5352*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 5352*FLEN/8, x4, x1, x2)

inst_1785:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x8001; op2val:0x1;
op3val:0x8400; valaddr_reg:x3; val_offset:5355*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 5355*FLEN/8, x4, x1, x2)

inst_1786:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x8001; op2val:0x1;
op3val:0x401; valaddr_reg:x3; val_offset:5358*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 5358*FLEN/8, x4, x1, x2)

inst_1787:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x8001; op2val:0x1;
op3val:0x8455; valaddr_reg:x3; val_offset:5361*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 5361*FLEN/8, x4, x1, x2)

inst_1788:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x8001; op2val:0x1;
op3val:0x7bff; valaddr_reg:x3; val_offset:5364*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 5364*FLEN/8, x4, x1, x2)

inst_1789:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x8001; op2val:0x1;
op3val:0xfbff; valaddr_reg:x3; val_offset:5367*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 5367*FLEN/8, x4, x1, x2)

inst_1790:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x8001; op2val:0x1;
op3val:0x7c00; valaddr_reg:x3; val_offset:5370*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 5370*FLEN/8, x4, x1, x2)

inst_1791:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x8001; op2val:0x1;
op3val:0xfc00; valaddr_reg:x3; val_offset:5373*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 5373*FLEN/8, x4, x1, x2)

RVTEST_SIGBASE(x1,signature_x1_15)
inst_1792:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x8001; op2val:0x1;
op3val:0x7e00; valaddr_reg:x3; val_offset:5376*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 5376*FLEN/8, x4, x1, x2)

inst_1793:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x8001; op2val:0x1;
op3val:0xfe00; valaddr_reg:x3; val_offset:5379*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 5379*FLEN/8, x4, x1, x2)

inst_1794:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x201 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x8001; op2val:0x1;
op3val:0x7e01; valaddr_reg:x3; val_offset:5382*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 5382*FLEN/8, x4, x1, x2)

inst_1795:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x255 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x8001; op2val:0x1;
op3val:0xfe55; valaddr_reg:x3; val_offset:5385*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 5385*FLEN/8, x4, x1, x2)

inst_1796:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x8001; op2val:0x1;
op3val:0x7c01; valaddr_reg:x3; val_offset:5388*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 5388*FLEN/8, x4, x1, x2)

inst_1797:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x155 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x8001; op2val:0x1;
op3val:0xfd55; valaddr_reg:x3; val_offset:5391*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 5391*FLEN/8, x4, x1, x2)

inst_1798:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x8001; op2val:0x1;
op3val:0x3c00; valaddr_reg:x3; val_offset:5394*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 5394*FLEN/8, x4, x1, x2)

inst_1799:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x8001; op2val:0x1;
op3val:0xbc00; valaddr_reg:x3; val_offset:5397*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 5397*FLEN/8, x4, x1, x2)

inst_1800:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x8001; op2val:0x8001;
op3val:0x0; valaddr_reg:x3; val_offset:5400*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 5400*FLEN/8, x4, x1, x2)

inst_1801:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x8001; op2val:0x8001;
op3val:0x8000; valaddr_reg:x3; val_offset:5403*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 5403*FLEN/8, x4, x1, x2)

inst_1802:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x8001; op2val:0x8001;
op3val:0x1; valaddr_reg:x3; val_offset:5406*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 5406*FLEN/8, x4, x1, x2)

inst_1803:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x8001; op2val:0x8001;
op3val:0x8001; valaddr_reg:x3; val_offset:5409*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 5409*FLEN/8, x4, x1, x2)

inst_1804:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x002 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x8001; op2val:0x8001;
op3val:0x2; valaddr_reg:x3; val_offset:5412*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 5412*FLEN/8, x4, x1, x2)

inst_1805:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3fe and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x8001; op2val:0x8001;
op3val:0x83fe; valaddr_reg:x3; val_offset:5415*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 5415*FLEN/8, x4, x1, x2)

inst_1806:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x8001; op2val:0x8001;
op3val:0x3ff; valaddr_reg:x3; val_offset:5418*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 5418*FLEN/8, x4, x1, x2)

inst_1807:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x8001; op2val:0x8001;
op3val:0x83ff; valaddr_reg:x3; val_offset:5421*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 5421*FLEN/8, x4, x1, x2)

inst_1808:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x8001; op2val:0x8001;
op3val:0x400; valaddr_reg:x3; val_offset:5424*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 5424*FLEN/8, x4, x1, x2)

inst_1809:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x8001; op2val:0x8001;
op3val:0x8400; valaddr_reg:x3; val_offset:5427*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 5427*FLEN/8, x4, x1, x2)

inst_1810:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x8001; op2val:0x8001;
op3val:0x401; valaddr_reg:x3; val_offset:5430*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 5430*FLEN/8, x4, x1, x2)

inst_1811:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x8001; op2val:0x8001;
op3val:0x8455; valaddr_reg:x3; val_offset:5433*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 5433*FLEN/8, x4, x1, x2)

inst_1812:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x8001; op2val:0x8001;
op3val:0x7bff; valaddr_reg:x3; val_offset:5436*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 5436*FLEN/8, x4, x1, x2)

inst_1813:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x8001; op2val:0x8001;
op3val:0xfbff; valaddr_reg:x3; val_offset:5439*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 5439*FLEN/8, x4, x1, x2)

inst_1814:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x8001; op2val:0x8001;
op3val:0x7c00; valaddr_reg:x3; val_offset:5442*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 5442*FLEN/8, x4, x1, x2)

inst_1815:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x8001; op2val:0x8001;
op3val:0xfc00; valaddr_reg:x3; val_offset:5445*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 5445*FLEN/8, x4, x1, x2)

inst_1816:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x8001; op2val:0x8001;
op3val:0x7e00; valaddr_reg:x3; val_offset:5448*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 5448*FLEN/8, x4, x1, x2)

inst_1817:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x8001; op2val:0x8001;
op3val:0xfe00; valaddr_reg:x3; val_offset:5451*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 5451*FLEN/8, x4, x1, x2)

inst_1818:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x201 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x8001; op2val:0x8001;
op3val:0x7e01; valaddr_reg:x3; val_offset:5454*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 5454*FLEN/8, x4, x1, x2)

inst_1819:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x255 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x8001; op2val:0x8001;
op3val:0xfe55; valaddr_reg:x3; val_offset:5457*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 5457*FLEN/8, x4, x1, x2)

inst_1820:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x8001; op2val:0x8001;
op3val:0x7c01; valaddr_reg:x3; val_offset:5460*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 5460*FLEN/8, x4, x1, x2)

inst_1821:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x155 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x8001; op2val:0x8001;
op3val:0xfd55; valaddr_reg:x3; val_offset:5463*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 5463*FLEN/8, x4, x1, x2)

inst_1822:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x8001; op2val:0x8001;
op3val:0x3c00; valaddr_reg:x3; val_offset:5466*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 5466*FLEN/8, x4, x1, x2)

inst_1823:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x8001; op2val:0x8001;
op3val:0xbc00; valaddr_reg:x3; val_offset:5469*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 5469*FLEN/8, x4, x1, x2)

inst_1824:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x8001; op2val:0x2;
op3val:0x0; valaddr_reg:x3; val_offset:5472*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 5472*FLEN/8, x4, x1, x2)

inst_1825:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x8001; op2val:0x2;
op3val:0x8000; valaddr_reg:x3; val_offset:5475*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 5475*FLEN/8, x4, x1, x2)

inst_1826:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x8001; op2val:0x2;
op3val:0x1; valaddr_reg:x3; val_offset:5478*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 5478*FLEN/8, x4, x1, x2)

inst_1827:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x8001; op2val:0x2;
op3val:0x8001; valaddr_reg:x3; val_offset:5481*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 5481*FLEN/8, x4, x1, x2)

inst_1828:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x002 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x8001; op2val:0x2;
op3val:0x2; valaddr_reg:x3; val_offset:5484*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 5484*FLEN/8, x4, x1, x2)

inst_1829:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3fe and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x8001; op2val:0x2;
op3val:0x83fe; valaddr_reg:x3; val_offset:5487*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 5487*FLEN/8, x4, x1, x2)

inst_1830:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x8001; op2val:0x2;
op3val:0x3ff; valaddr_reg:x3; val_offset:5490*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 5490*FLEN/8, x4, x1, x2)

inst_1831:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x8001; op2val:0x2;
op3val:0x83ff; valaddr_reg:x3; val_offset:5493*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 5493*FLEN/8, x4, x1, x2)

inst_1832:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x8001; op2val:0x2;
op3val:0x400; valaddr_reg:x3; val_offset:5496*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 5496*FLEN/8, x4, x1, x2)

inst_1833:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x8001; op2val:0x2;
op3val:0x8400; valaddr_reg:x3; val_offset:5499*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 5499*FLEN/8, x4, x1, x2)

inst_1834:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x8001; op2val:0x2;
op3val:0x401; valaddr_reg:x3; val_offset:5502*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 5502*FLEN/8, x4, x1, x2)

inst_1835:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x8001; op2val:0x2;
op3val:0x8455; valaddr_reg:x3; val_offset:5505*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 5505*FLEN/8, x4, x1, x2)

inst_1836:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x8001; op2val:0x2;
op3val:0x7bff; valaddr_reg:x3; val_offset:5508*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 5508*FLEN/8, x4, x1, x2)

inst_1837:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x8001; op2val:0x2;
op3val:0xfbff; valaddr_reg:x3; val_offset:5511*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 5511*FLEN/8, x4, x1, x2)

inst_1838:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x8001; op2val:0x2;
op3val:0x7c00; valaddr_reg:x3; val_offset:5514*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 5514*FLEN/8, x4, x1, x2)

inst_1839:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x8001; op2val:0x2;
op3val:0xfc00; valaddr_reg:x3; val_offset:5517*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 5517*FLEN/8, x4, x1, x2)

inst_1840:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x8001; op2val:0x2;
op3val:0x7e00; valaddr_reg:x3; val_offset:5520*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 5520*FLEN/8, x4, x1, x2)

inst_1841:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x8001; op2val:0x2;
op3val:0xfe00; valaddr_reg:x3; val_offset:5523*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 5523*FLEN/8, x4, x1, x2)

inst_1842:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x201 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x8001; op2val:0x2;
op3val:0x7e01; valaddr_reg:x3; val_offset:5526*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 5526*FLEN/8, x4, x1, x2)

inst_1843:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x255 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x8001; op2val:0x2;
op3val:0xfe55; valaddr_reg:x3; val_offset:5529*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 5529*FLEN/8, x4, x1, x2)

inst_1844:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x8001; op2val:0x2;
op3val:0x7c01; valaddr_reg:x3; val_offset:5532*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 5532*FLEN/8, x4, x1, x2)

inst_1845:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x155 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x8001; op2val:0x2;
op3val:0xfd55; valaddr_reg:x3; val_offset:5535*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 5535*FLEN/8, x4, x1, x2)

inst_1846:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fs3 == 0 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x8001; op2val:0x2;
op3val:0x3c00; valaddr_reg:x3; val_offset:5538*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 5538*FLEN/8, x4, x1, x2)

inst_1847:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fs3 == 1 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x8001; op2val:0x2;
op3val:0xbc00; valaddr_reg:x3; val_offset:5541*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 5541*FLEN/8, x4, x1, x2)

inst_1848:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x8001; op2val:0x83fe;
op3val:0x0; valaddr_reg:x3; val_offset:5544*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 5544*FLEN/8, x4, x1, x2)

inst_1849:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x8001; op2val:0x83fe;
op3val:0x8000; valaddr_reg:x3; val_offset:5547*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 5547*FLEN/8, x4, x1, x2)

inst_1850:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fs3 == 0 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x8001; op2val:0x83fe;
op3val:0x1; valaddr_reg:x3; val_offset:5550*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 5550*FLEN/8, x4, x1, x2)

inst_1851:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fs3 == 1 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x8001; op2val:0x83fe;
op3val:0x8001; valaddr_reg:x3; val_offset:5553*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 5553*FLEN/8, x4, x1, x2)

inst_1852:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fs3 == 0 and fe3 == 0x00 and fm3 == 0x002 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x8001; op2val:0x83fe;
op3val:0x2; valaddr_reg:x3; val_offset:5556*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 5556*FLEN/8, x4, x1, x2)

inst_1853:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3fe and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x8001; op2val:0x83fe;
op3val:0x83fe; valaddr_reg:x3; val_offset:5559*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 5559*FLEN/8, x4, x1, x2)

inst_1854:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fs3 == 0 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x8001; op2val:0x83fe;
op3val:0x3ff; valaddr_reg:x3; val_offset:5562*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 5562*FLEN/8, x4, x1, x2)

inst_1855:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x8001; op2val:0x83fe;
op3val:0x83ff; valaddr_reg:x3; val_offset:5565*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 5565*FLEN/8, x4, x1, x2)

inst_1856:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x8001; op2val:0x83fe;
op3val:0x400; valaddr_reg:x3; val_offset:5568*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 5568*FLEN/8, x4, x1, x2)

inst_1857:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x8001; op2val:0x83fe;
op3val:0x8400; valaddr_reg:x3; val_offset:5571*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 5571*FLEN/8, x4, x1, x2)

inst_1858:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fs3 == 0 and fe3 == 0x01 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x8001; op2val:0x83fe;
op3val:0x401; valaddr_reg:x3; val_offset:5574*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 5574*FLEN/8, x4, x1, x2)

inst_1859:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x8001; op2val:0x83fe;
op3val:0x8455; valaddr_reg:x3; val_offset:5577*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 5577*FLEN/8, x4, x1, x2)

inst_1860:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x8001; op2val:0x83fe;
op3val:0x7bff; valaddr_reg:x3; val_offset:5580*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 5580*FLEN/8, x4, x1, x2)

inst_1861:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x8001; op2val:0x83fe;
op3val:0xfbff; valaddr_reg:x3; val_offset:5583*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 5583*FLEN/8, x4, x1, x2)

inst_1862:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fs3 == 0 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x8001; op2val:0x83fe;
op3val:0x7c00; valaddr_reg:x3; val_offset:5586*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 5586*FLEN/8, x4, x1, x2)

inst_1863:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fs3 == 1 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x8001; op2val:0x83fe;
op3val:0xfc00; valaddr_reg:x3; val_offset:5589*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 5589*FLEN/8, x4, x1, x2)

inst_1864:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fs3 == 0 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x8001; op2val:0x83fe;
op3val:0x7e00; valaddr_reg:x3; val_offset:5592*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 5592*FLEN/8, x4, x1, x2)

inst_1865:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fs3 == 1 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x8001; op2val:0x83fe;
op3val:0xfe00; valaddr_reg:x3; val_offset:5595*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 5595*FLEN/8, x4, x1, x2)

inst_1866:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fs3 == 0 and fe3 == 0x1f and fm3 == 0x201 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x8001; op2val:0x83fe;
op3val:0x7e01; valaddr_reg:x3; val_offset:5598*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 5598*FLEN/8, x4, x1, x2)

inst_1867:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fs3 == 1 and fe3 == 0x1f and fm3 == 0x255 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x8001; op2val:0x83fe;
op3val:0xfe55; valaddr_reg:x3; val_offset:5601*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 5601*FLEN/8, x4, x1, x2)

inst_1868:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fs3 == 0 and fe3 == 0x1f and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x8001; op2val:0x83fe;
op3val:0x7c01; valaddr_reg:x3; val_offset:5604*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 5604*FLEN/8, x4, x1, x2)

inst_1869:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fs3 == 1 and fe3 == 0x1f and fm3 == 0x155 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x8001; op2val:0x83fe;
op3val:0xfd55; valaddr_reg:x3; val_offset:5607*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 5607*FLEN/8, x4, x1, x2)

inst_1870:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fs3 == 0 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x8001; op2val:0x83fe;
op3val:0x3c00; valaddr_reg:x3; val_offset:5610*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 5610*FLEN/8, x4, x1, x2)

inst_1871:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fs3 == 1 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x8001; op2val:0x83fe;
op3val:0xbc00; valaddr_reg:x3; val_offset:5613*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 5613*FLEN/8, x4, x1, x2)

inst_1872:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x8001; op2val:0x3ff;
op3val:0x0; valaddr_reg:x3; val_offset:5616*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 5616*FLEN/8, x4, x1, x2)

inst_1873:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x8001; op2val:0x3ff;
op3val:0x8000; valaddr_reg:x3; val_offset:5619*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 5619*FLEN/8, x4, x1, x2)

inst_1874:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x8001; op2val:0x3ff;
op3val:0x1; valaddr_reg:x3; val_offset:5622*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 5622*FLEN/8, x4, x1, x2)

inst_1875:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x8001; op2val:0x3ff;
op3val:0x8001; valaddr_reg:x3; val_offset:5625*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 5625*FLEN/8, x4, x1, x2)

inst_1876:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x002 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x8001; op2val:0x3ff;
op3val:0x2; valaddr_reg:x3; val_offset:5628*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 5628*FLEN/8, x4, x1, x2)

inst_1877:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3fe and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x8001; op2val:0x3ff;
op3val:0x83fe; valaddr_reg:x3; val_offset:5631*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 5631*FLEN/8, x4, x1, x2)

inst_1878:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x8001; op2val:0x3ff;
op3val:0x3ff; valaddr_reg:x3; val_offset:5634*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 5634*FLEN/8, x4, x1, x2)

inst_1879:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x8001; op2val:0x3ff;
op3val:0x83ff; valaddr_reg:x3; val_offset:5637*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 5637*FLEN/8, x4, x1, x2)

inst_1880:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x8001; op2val:0x3ff;
op3val:0x400; valaddr_reg:x3; val_offset:5640*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 5640*FLEN/8, x4, x1, x2)

inst_1881:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x8001; op2val:0x3ff;
op3val:0x8400; valaddr_reg:x3; val_offset:5643*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 5643*FLEN/8, x4, x1, x2)

inst_1882:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x01 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x8001; op2val:0x3ff;
op3val:0x401; valaddr_reg:x3; val_offset:5646*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 5646*FLEN/8, x4, x1, x2)

inst_1883:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x8001; op2val:0x3ff;
op3val:0x8455; valaddr_reg:x3; val_offset:5649*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 5649*FLEN/8, x4, x1, x2)

inst_1884:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x8001; op2val:0x3ff;
op3val:0x7bff; valaddr_reg:x3; val_offset:5652*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 5652*FLEN/8, x4, x1, x2)

inst_1885:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x8001; op2val:0x3ff;
op3val:0xfbff; valaddr_reg:x3; val_offset:5655*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 5655*FLEN/8, x4, x1, x2)

inst_1886:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x8001; op2val:0x3ff;
op3val:0x7c00; valaddr_reg:x3; val_offset:5658*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 5658*FLEN/8, x4, x1, x2)

inst_1887:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x8001; op2val:0x3ff;
op3val:0xfc00; valaddr_reg:x3; val_offset:5661*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 5661*FLEN/8, x4, x1, x2)

inst_1888:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x8001; op2val:0x3ff;
op3val:0x7e00; valaddr_reg:x3; val_offset:5664*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 5664*FLEN/8, x4, x1, x2)

inst_1889:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x8001; op2val:0x3ff;
op3val:0xfe00; valaddr_reg:x3; val_offset:5667*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 5667*FLEN/8, x4, x1, x2)

inst_1890:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x1f and fm3 == 0x201 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x8001; op2val:0x3ff;
op3val:0x7e01; valaddr_reg:x3; val_offset:5670*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 5670*FLEN/8, x4, x1, x2)

inst_1891:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x1f and fm3 == 0x255 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x8001; op2val:0x3ff;
op3val:0xfe55; valaddr_reg:x3; val_offset:5673*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 5673*FLEN/8, x4, x1, x2)

inst_1892:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x1f and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x8001; op2val:0x3ff;
op3val:0x7c01; valaddr_reg:x3; val_offset:5676*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 5676*FLEN/8, x4, x1, x2)

inst_1893:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x1f and fm3 == 0x155 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x8001; op2val:0x3ff;
op3val:0xfd55; valaddr_reg:x3; val_offset:5679*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 5679*FLEN/8, x4, x1, x2)

inst_1894:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x8001; op2val:0x3ff;
op3val:0x3c00; valaddr_reg:x3; val_offset:5682*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 5682*FLEN/8, x4, x1, x2)

inst_1895:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x8001; op2val:0x3ff;
op3val:0xbc00; valaddr_reg:x3; val_offset:5685*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 5685*FLEN/8, x4, x1, x2)

inst_1896:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x8001; op2val:0x83ff;
op3val:0x0; valaddr_reg:x3; val_offset:5688*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 5688*FLEN/8, x4, x1, x2)

inst_1897:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x8001; op2val:0x83ff;
op3val:0x8000; valaddr_reg:x3; val_offset:5691*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 5691*FLEN/8, x4, x1, x2)

inst_1898:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x8001; op2val:0x83ff;
op3val:0x1; valaddr_reg:x3; val_offset:5694*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 5694*FLEN/8, x4, x1, x2)

inst_1899:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x8001; op2val:0x83ff;
op3val:0x8001; valaddr_reg:x3; val_offset:5697*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 5697*FLEN/8, x4, x1, x2)

inst_1900:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x002 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x8001; op2val:0x83ff;
op3val:0x2; valaddr_reg:x3; val_offset:5700*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 5700*FLEN/8, x4, x1, x2)

inst_1901:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3fe and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x8001; op2val:0x83ff;
op3val:0x83fe; valaddr_reg:x3; val_offset:5703*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 5703*FLEN/8, x4, x1, x2)

inst_1902:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x8001; op2val:0x83ff;
op3val:0x3ff; valaddr_reg:x3; val_offset:5706*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 5706*FLEN/8, x4, x1, x2)

inst_1903:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x8001; op2val:0x83ff;
op3val:0x83ff; valaddr_reg:x3; val_offset:5709*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 5709*FLEN/8, x4, x1, x2)

inst_1904:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x8001; op2val:0x83ff;
op3val:0x400; valaddr_reg:x3; val_offset:5712*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 5712*FLEN/8, x4, x1, x2)

inst_1905:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x8001; op2val:0x83ff;
op3val:0x8400; valaddr_reg:x3; val_offset:5715*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 5715*FLEN/8, x4, x1, x2)

inst_1906:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x01 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x8001; op2val:0x83ff;
op3val:0x401; valaddr_reg:x3; val_offset:5718*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 5718*FLEN/8, x4, x1, x2)

inst_1907:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x8001; op2val:0x83ff;
op3val:0x8455; valaddr_reg:x3; val_offset:5721*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 5721*FLEN/8, x4, x1, x2)

inst_1908:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x8001; op2val:0x83ff;
op3val:0x7bff; valaddr_reg:x3; val_offset:5724*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 5724*FLEN/8, x4, x1, x2)

inst_1909:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x8001; op2val:0x83ff;
op3val:0xfbff; valaddr_reg:x3; val_offset:5727*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 5727*FLEN/8, x4, x1, x2)

inst_1910:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x8001; op2val:0x83ff;
op3val:0x7c00; valaddr_reg:x3; val_offset:5730*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 5730*FLEN/8, x4, x1, x2)

inst_1911:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x8001; op2val:0x83ff;
op3val:0xfc00; valaddr_reg:x3; val_offset:5733*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 5733*FLEN/8, x4, x1, x2)

inst_1912:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x8001; op2val:0x83ff;
op3val:0x7e00; valaddr_reg:x3; val_offset:5736*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 5736*FLEN/8, x4, x1, x2)

inst_1913:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x8001; op2val:0x83ff;
op3val:0xfe00; valaddr_reg:x3; val_offset:5739*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 5739*FLEN/8, x4, x1, x2)

inst_1914:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x1f and fm3 == 0x201 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x8001; op2val:0x83ff;
op3val:0x7e01; valaddr_reg:x3; val_offset:5742*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 5742*FLEN/8, x4, x1, x2)

inst_1915:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x1f and fm3 == 0x255 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x8001; op2val:0x83ff;
op3val:0xfe55; valaddr_reg:x3; val_offset:5745*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 5745*FLEN/8, x4, x1, x2)

inst_1916:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x1f and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x8001; op2val:0x83ff;
op3val:0x7c01; valaddr_reg:x3; val_offset:5748*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 5748*FLEN/8, x4, x1, x2)

inst_1917:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x1f and fm3 == 0x155 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x8001; op2val:0x83ff;
op3val:0xfd55; valaddr_reg:x3; val_offset:5751*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 5751*FLEN/8, x4, x1, x2)

inst_1918:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x8001; op2val:0x83ff;
op3val:0x3c00; valaddr_reg:x3; val_offset:5754*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 5754*FLEN/8, x4, x1, x2)

inst_1919:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x8001; op2val:0x83ff;
op3val:0xbc00; valaddr_reg:x3; val_offset:5757*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 5757*FLEN/8, x4, x1, x2)

RVTEST_SIGBASE(x1,signature_x1_16)
inst_1920:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x8001; op2val:0x400;
op3val:0x0; valaddr_reg:x3; val_offset:5760*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 5760*FLEN/8, x4, x1, x2)

inst_1921:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x8001; op2val:0x400;
op3val:0x8000; valaddr_reg:x3; val_offset:5763*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 5763*FLEN/8, x4, x1, x2)

inst_1922:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x8001; op2val:0x400;
op3val:0x1; valaddr_reg:x3; val_offset:5766*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 5766*FLEN/8, x4, x1, x2)

inst_1923:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x8001; op2val:0x400;
op3val:0x8001; valaddr_reg:x3; val_offset:5769*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 5769*FLEN/8, x4, x1, x2)

inst_1924:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x002 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x8001; op2val:0x400;
op3val:0x2; valaddr_reg:x3; val_offset:5772*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 5772*FLEN/8, x4, x1, x2)

inst_1925:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3fe and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x8001; op2val:0x400;
op3val:0x83fe; valaddr_reg:x3; val_offset:5775*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 5775*FLEN/8, x4, x1, x2)

inst_1926:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x8001; op2val:0x400;
op3val:0x3ff; valaddr_reg:x3; val_offset:5778*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 5778*FLEN/8, x4, x1, x2)

inst_1927:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x8001; op2val:0x400;
op3val:0x83ff; valaddr_reg:x3; val_offset:5781*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 5781*FLEN/8, x4, x1, x2)

inst_1928:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x8001; op2val:0x400;
op3val:0x400; valaddr_reg:x3; val_offset:5784*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 5784*FLEN/8, x4, x1, x2)

inst_1929:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x8001; op2val:0x400;
op3val:0x8400; valaddr_reg:x3; val_offset:5787*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 5787*FLEN/8, x4, x1, x2)

inst_1930:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x8001; op2val:0x400;
op3val:0x401; valaddr_reg:x3; val_offset:5790*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 5790*FLEN/8, x4, x1, x2)

inst_1931:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x8001; op2val:0x400;
op3val:0x8455; valaddr_reg:x3; val_offset:5793*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 5793*FLEN/8, x4, x1, x2)

inst_1932:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x8001; op2val:0x400;
op3val:0x7bff; valaddr_reg:x3; val_offset:5796*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 5796*FLEN/8, x4, x1, x2)

inst_1933:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x8001; op2val:0x400;
op3val:0xfbff; valaddr_reg:x3; val_offset:5799*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 5799*FLEN/8, x4, x1, x2)

inst_1934:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x8001; op2val:0x400;
op3val:0x7c00; valaddr_reg:x3; val_offset:5802*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 5802*FLEN/8, x4, x1, x2)

inst_1935:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x8001; op2val:0x400;
op3val:0xfc00; valaddr_reg:x3; val_offset:5805*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 5805*FLEN/8, x4, x1, x2)

inst_1936:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x8001; op2val:0x400;
op3val:0x7e00; valaddr_reg:x3; val_offset:5808*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 5808*FLEN/8, x4, x1, x2)

inst_1937:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x8001; op2val:0x400;
op3val:0xfe00; valaddr_reg:x3; val_offset:5811*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 5811*FLEN/8, x4, x1, x2)

inst_1938:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x201 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x8001; op2val:0x400;
op3val:0x7e01; valaddr_reg:x3; val_offset:5814*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 5814*FLEN/8, x4, x1, x2)

inst_1939:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x255 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x8001; op2val:0x400;
op3val:0xfe55; valaddr_reg:x3; val_offset:5817*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 5817*FLEN/8, x4, x1, x2)

inst_1940:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x8001; op2val:0x400;
op3val:0x7c01; valaddr_reg:x3; val_offset:5820*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 5820*FLEN/8, x4, x1, x2)

inst_1941:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x155 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x8001; op2val:0x400;
op3val:0xfd55; valaddr_reg:x3; val_offset:5823*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 5823*FLEN/8, x4, x1, x2)

inst_1942:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x8001; op2val:0x400;
op3val:0x3c00; valaddr_reg:x3; val_offset:5826*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 5826*FLEN/8, x4, x1, x2)

inst_1943:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x8001; op2val:0x400;
op3val:0xbc00; valaddr_reg:x3; val_offset:5829*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 5829*FLEN/8, x4, x1, x2)

inst_1944:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x8001; op2val:0x8400;
op3val:0x0; valaddr_reg:x3; val_offset:5832*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 5832*FLEN/8, x4, x1, x2)

inst_1945:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x8001; op2val:0x8400;
op3val:0x8000; valaddr_reg:x3; val_offset:5835*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 5835*FLEN/8, x4, x1, x2)

inst_1946:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x8001; op2val:0x8400;
op3val:0x1; valaddr_reg:x3; val_offset:5838*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 5838*FLEN/8, x4, x1, x2)

inst_1947:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x8001; op2val:0x8400;
op3val:0x8001; valaddr_reg:x3; val_offset:5841*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 5841*FLEN/8, x4, x1, x2)

inst_1948:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x002 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x8001; op2val:0x8400;
op3val:0x2; valaddr_reg:x3; val_offset:5844*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 5844*FLEN/8, x4, x1, x2)

inst_1949:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3fe and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x8001; op2val:0x8400;
op3val:0x83fe; valaddr_reg:x3; val_offset:5847*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 5847*FLEN/8, x4, x1, x2)

inst_1950:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x8001; op2val:0x8400;
op3val:0x3ff; valaddr_reg:x3; val_offset:5850*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 5850*FLEN/8, x4, x1, x2)

inst_1951:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x8001; op2val:0x8400;
op3val:0x83ff; valaddr_reg:x3; val_offset:5853*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 5853*FLEN/8, x4, x1, x2)

inst_1952:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x8001; op2val:0x8400;
op3val:0x400; valaddr_reg:x3; val_offset:5856*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 5856*FLEN/8, x4, x1, x2)

inst_1953:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x8001; op2val:0x8400;
op3val:0x8400; valaddr_reg:x3; val_offset:5859*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 5859*FLEN/8, x4, x1, x2)

inst_1954:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x8001; op2val:0x8400;
op3val:0x401; valaddr_reg:x3; val_offset:5862*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 5862*FLEN/8, x4, x1, x2)

inst_1955:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x8001; op2val:0x8400;
op3val:0x8455; valaddr_reg:x3; val_offset:5865*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 5865*FLEN/8, x4, x1, x2)

inst_1956:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x8001; op2val:0x8400;
op3val:0x7bff; valaddr_reg:x3; val_offset:5868*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 5868*FLEN/8, x4, x1, x2)

inst_1957:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x8001; op2val:0x8400;
op3val:0xfbff; valaddr_reg:x3; val_offset:5871*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 5871*FLEN/8, x4, x1, x2)

inst_1958:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x8001; op2val:0x8400;
op3val:0x7c00; valaddr_reg:x3; val_offset:5874*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 5874*FLEN/8, x4, x1, x2)

inst_1959:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x8001; op2val:0x8400;
op3val:0xfc00; valaddr_reg:x3; val_offset:5877*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 5877*FLEN/8, x4, x1, x2)

inst_1960:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x8001; op2val:0x8400;
op3val:0x7e00; valaddr_reg:x3; val_offset:5880*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 5880*FLEN/8, x4, x1, x2)

inst_1961:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x8001; op2val:0x8400;
op3val:0xfe00; valaddr_reg:x3; val_offset:5883*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 5883*FLEN/8, x4, x1, x2)

inst_1962:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x201 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x8001; op2val:0x8400;
op3val:0x7e01; valaddr_reg:x3; val_offset:5886*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 5886*FLEN/8, x4, x1, x2)

inst_1963:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x255 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x8001; op2val:0x8400;
op3val:0xfe55; valaddr_reg:x3; val_offset:5889*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 5889*FLEN/8, x4, x1, x2)

inst_1964:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x8001; op2val:0x8400;
op3val:0x7c01; valaddr_reg:x3; val_offset:5892*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 5892*FLEN/8, x4, x1, x2)

inst_1965:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x155 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x8001; op2val:0x8400;
op3val:0xfd55; valaddr_reg:x3; val_offset:5895*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 5895*FLEN/8, x4, x1, x2)

inst_1966:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x8001; op2val:0x8400;
op3val:0x3c00; valaddr_reg:x3; val_offset:5898*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 5898*FLEN/8, x4, x1, x2)

inst_1967:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x8001; op2val:0x8400;
op3val:0xbc00; valaddr_reg:x3; val_offset:5901*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 5901*FLEN/8, x4, x1, x2)

inst_1968:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x8001; op2val:0x401;
op3val:0x0; valaddr_reg:x3; val_offset:5904*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 5904*FLEN/8, x4, x1, x2)

inst_1969:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x8001; op2val:0x401;
op3val:0x8000; valaddr_reg:x3; val_offset:5907*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 5907*FLEN/8, x4, x1, x2)

inst_1970:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x8001; op2val:0x401;
op3val:0x1; valaddr_reg:x3; val_offset:5910*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 5910*FLEN/8, x4, x1, x2)

inst_1971:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x8001; op2val:0x401;
op3val:0x8001; valaddr_reg:x3; val_offset:5913*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 5913*FLEN/8, x4, x1, x2)

inst_1972:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x002 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x8001; op2val:0x401;
op3val:0x2; valaddr_reg:x3; val_offset:5916*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 5916*FLEN/8, x4, x1, x2)

inst_1973:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3fe and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x8001; op2val:0x401;
op3val:0x83fe; valaddr_reg:x3; val_offset:5919*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 5919*FLEN/8, x4, x1, x2)

inst_1974:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x8001; op2val:0x401;
op3val:0x3ff; valaddr_reg:x3; val_offset:5922*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 5922*FLEN/8, x4, x1, x2)

inst_1975:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x8001; op2val:0x401;
op3val:0x83ff; valaddr_reg:x3; val_offset:5925*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 5925*FLEN/8, x4, x1, x2)

inst_1976:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x8001; op2val:0x401;
op3val:0x400; valaddr_reg:x3; val_offset:5928*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 5928*FLEN/8, x4, x1, x2)

inst_1977:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x8001; op2val:0x401;
op3val:0x8400; valaddr_reg:x3; val_offset:5931*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 5931*FLEN/8, x4, x1, x2)

inst_1978:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x8001; op2val:0x401;
op3val:0x401; valaddr_reg:x3; val_offset:5934*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 5934*FLEN/8, x4, x1, x2)

inst_1979:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x8001; op2val:0x401;
op3val:0x8455; valaddr_reg:x3; val_offset:5937*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 5937*FLEN/8, x4, x1, x2)

inst_1980:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x8001; op2val:0x401;
op3val:0x7bff; valaddr_reg:x3; val_offset:5940*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 5940*FLEN/8, x4, x1, x2)

inst_1981:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x8001; op2val:0x401;
op3val:0xfbff; valaddr_reg:x3; val_offset:5943*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 5943*FLEN/8, x4, x1, x2)

inst_1982:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x8001; op2val:0x401;
op3val:0x7c00; valaddr_reg:x3; val_offset:5946*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 5946*FLEN/8, x4, x1, x2)

inst_1983:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x8001; op2val:0x401;
op3val:0xfc00; valaddr_reg:x3; val_offset:5949*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 5949*FLEN/8, x4, x1, x2)

inst_1984:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x8001; op2val:0x401;
op3val:0x7e00; valaddr_reg:x3; val_offset:5952*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 5952*FLEN/8, x4, x1, x2)

inst_1985:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x8001; op2val:0x401;
op3val:0xfe00; valaddr_reg:x3; val_offset:5955*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 5955*FLEN/8, x4, x1, x2)

inst_1986:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x201 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x8001; op2val:0x401;
op3val:0x7e01; valaddr_reg:x3; val_offset:5958*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 5958*FLEN/8, x4, x1, x2)

inst_1987:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x255 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x8001; op2val:0x401;
op3val:0xfe55; valaddr_reg:x3; val_offset:5961*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 5961*FLEN/8, x4, x1, x2)

inst_1988:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x8001; op2val:0x401;
op3val:0x7c01; valaddr_reg:x3; val_offset:5964*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 5964*FLEN/8, x4, x1, x2)

inst_1989:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x155 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x8001; op2val:0x401;
op3val:0xfd55; valaddr_reg:x3; val_offset:5967*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 5967*FLEN/8, x4, x1, x2)

inst_1990:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x8001; op2val:0x401;
op3val:0x3c00; valaddr_reg:x3; val_offset:5970*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 5970*FLEN/8, x4, x1, x2)

inst_1991:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x8001; op2val:0x401;
op3val:0xbc00; valaddr_reg:x3; val_offset:5973*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 5973*FLEN/8, x4, x1, x2)

inst_1992:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x8001; op2val:0x8455;
op3val:0x0; valaddr_reg:x3; val_offset:5976*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 5976*FLEN/8, x4, x1, x2)

inst_1993:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x8001; op2val:0x8455;
op3val:0x8000; valaddr_reg:x3; val_offset:5979*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 5979*FLEN/8, x4, x1, x2)

inst_1994:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x8001; op2val:0x8455;
op3val:0x1; valaddr_reg:x3; val_offset:5982*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 5982*FLEN/8, x4, x1, x2)

inst_1995:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x8001; op2val:0x8455;
op3val:0x8001; valaddr_reg:x3; val_offset:5985*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 5985*FLEN/8, x4, x1, x2)

inst_1996:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x002 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x8001; op2val:0x8455;
op3val:0x2; valaddr_reg:x3; val_offset:5988*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 5988*FLEN/8, x4, x1, x2)

inst_1997:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3fe and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x8001; op2val:0x8455;
op3val:0x83fe; valaddr_reg:x3; val_offset:5991*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 5991*FLEN/8, x4, x1, x2)

inst_1998:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x8001; op2val:0x8455;
op3val:0x3ff; valaddr_reg:x3; val_offset:5994*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 5994*FLEN/8, x4, x1, x2)

inst_1999:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x8001; op2val:0x8455;
op3val:0x83ff; valaddr_reg:x3; val_offset:5997*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 5997*FLEN/8, x4, x1, x2)

inst_2000:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x8001; op2val:0x8455;
op3val:0x400; valaddr_reg:x3; val_offset:6000*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 6000*FLEN/8, x4, x1, x2)

inst_2001:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x8001; op2val:0x8455;
op3val:0x8400; valaddr_reg:x3; val_offset:6003*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 6003*FLEN/8, x4, x1, x2)

inst_2002:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x8001; op2val:0x8455;
op3val:0x401; valaddr_reg:x3; val_offset:6006*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 6006*FLEN/8, x4, x1, x2)

inst_2003:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x8001; op2val:0x8455;
op3val:0x8455; valaddr_reg:x3; val_offset:6009*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 6009*FLEN/8, x4, x1, x2)

inst_2004:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x8001; op2val:0x8455;
op3val:0x7bff; valaddr_reg:x3; val_offset:6012*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 6012*FLEN/8, x4, x1, x2)

inst_2005:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x8001; op2val:0x8455;
op3val:0xfbff; valaddr_reg:x3; val_offset:6015*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 6015*FLEN/8, x4, x1, x2)

inst_2006:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x8001; op2val:0x8455;
op3val:0x7c00; valaddr_reg:x3; val_offset:6018*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 6018*FLEN/8, x4, x1, x2)

inst_2007:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x8001; op2val:0x8455;
op3val:0xfc00; valaddr_reg:x3; val_offset:6021*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 6021*FLEN/8, x4, x1, x2)

inst_2008:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x8001; op2val:0x8455;
op3val:0x7e00; valaddr_reg:x3; val_offset:6024*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 6024*FLEN/8, x4, x1, x2)

inst_2009:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x8001; op2val:0x8455;
op3val:0xfe00; valaddr_reg:x3; val_offset:6027*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 6027*FLEN/8, x4, x1, x2)

inst_2010:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x201 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x8001; op2val:0x8455;
op3val:0x7e01; valaddr_reg:x3; val_offset:6030*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 6030*FLEN/8, x4, x1, x2)

inst_2011:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x255 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x8001; op2val:0x8455;
op3val:0xfe55; valaddr_reg:x3; val_offset:6033*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 6033*FLEN/8, x4, x1, x2)

inst_2012:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x8001; op2val:0x8455;
op3val:0x7c01; valaddr_reg:x3; val_offset:6036*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 6036*FLEN/8, x4, x1, x2)

inst_2013:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x155 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x8001; op2val:0x8455;
op3val:0xfd55; valaddr_reg:x3; val_offset:6039*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 6039*FLEN/8, x4, x1, x2)

inst_2014:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fs3 == 0 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x8001; op2val:0x8455;
op3val:0x3c00; valaddr_reg:x3; val_offset:6042*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 6042*FLEN/8, x4, x1, x2)

inst_2015:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fs3 == 1 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x8001; op2val:0x8455;
op3val:0xbc00; valaddr_reg:x3; val_offset:6045*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 6045*FLEN/8, x4, x1, x2)

inst_2016:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x8001; op2val:0x7bff;
op3val:0x0; valaddr_reg:x3; val_offset:6048*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 6048*FLEN/8, x4, x1, x2)

inst_2017:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x8001; op2val:0x7bff;
op3val:0x8000; valaddr_reg:x3; val_offset:6051*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 6051*FLEN/8, x4, x1, x2)

inst_2018:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x8001; op2val:0x7bff;
op3val:0x1; valaddr_reg:x3; val_offset:6054*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 6054*FLEN/8, x4, x1, x2)

inst_2019:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x8001; op2val:0x7bff;
op3val:0x8001; valaddr_reg:x3; val_offset:6057*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 6057*FLEN/8, x4, x1, x2)

inst_2020:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x002 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x8001; op2val:0x7bff;
op3val:0x2; valaddr_reg:x3; val_offset:6060*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 6060*FLEN/8, x4, x1, x2)

inst_2021:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3fe and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x8001; op2val:0x7bff;
op3val:0x83fe; valaddr_reg:x3; val_offset:6063*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 6063*FLEN/8, x4, x1, x2)

inst_2022:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x8001; op2val:0x7bff;
op3val:0x3ff; valaddr_reg:x3; val_offset:6066*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 6066*FLEN/8, x4, x1, x2)

inst_2023:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x8001; op2val:0x7bff;
op3val:0x83ff; valaddr_reg:x3; val_offset:6069*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 6069*FLEN/8, x4, x1, x2)

inst_2024:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x8001; op2val:0x7bff;
op3val:0x400; valaddr_reg:x3; val_offset:6072*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 6072*FLEN/8, x4, x1, x2)

inst_2025:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x8001; op2val:0x7bff;
op3val:0x8400; valaddr_reg:x3; val_offset:6075*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 6075*FLEN/8, x4, x1, x2)

inst_2026:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x01 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x8001; op2val:0x7bff;
op3val:0x401; valaddr_reg:x3; val_offset:6078*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 6078*FLEN/8, x4, x1, x2)

inst_2027:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x8001; op2val:0x7bff;
op3val:0x8455; valaddr_reg:x3; val_offset:6081*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 6081*FLEN/8, x4, x1, x2)

inst_2028:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x8001; op2val:0x7bff;
op3val:0x7bff; valaddr_reg:x3; val_offset:6084*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 6084*FLEN/8, x4, x1, x2)

inst_2029:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x8001; op2val:0x7bff;
op3val:0xfbff; valaddr_reg:x3; val_offset:6087*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 6087*FLEN/8, x4, x1, x2)

inst_2030:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x8001; op2val:0x7bff;
op3val:0x7c00; valaddr_reg:x3; val_offset:6090*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 6090*FLEN/8, x4, x1, x2)

inst_2031:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x8001; op2val:0x7bff;
op3val:0xfc00; valaddr_reg:x3; val_offset:6093*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 6093*FLEN/8, x4, x1, x2)

inst_2032:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x8001; op2val:0x7bff;
op3val:0x7e00; valaddr_reg:x3; val_offset:6096*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 6096*FLEN/8, x4, x1, x2)

inst_2033:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x8001; op2val:0x7bff;
op3val:0xfe00; valaddr_reg:x3; val_offset:6099*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 6099*FLEN/8, x4, x1, x2)

inst_2034:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x1f and fm3 == 0x201 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x8001; op2val:0x7bff;
op3val:0x7e01; valaddr_reg:x3; val_offset:6102*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 6102*FLEN/8, x4, x1, x2)

inst_2035:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x1f and fm3 == 0x255 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x8001; op2val:0x7bff;
op3val:0xfe55; valaddr_reg:x3; val_offset:6105*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 6105*FLEN/8, x4, x1, x2)

inst_2036:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x1f and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x8001; op2val:0x7bff;
op3val:0x7c01; valaddr_reg:x3; val_offset:6108*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 6108*FLEN/8, x4, x1, x2)

inst_2037:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x1f and fm3 == 0x155 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x8001; op2val:0x7bff;
op3val:0xfd55; valaddr_reg:x3; val_offset:6111*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 6111*FLEN/8, x4, x1, x2)

inst_2038:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x8001; op2val:0x7bff;
op3val:0x3c00; valaddr_reg:x3; val_offset:6114*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 6114*FLEN/8, x4, x1, x2)

inst_2039:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x8001; op2val:0x7bff;
op3val:0xbc00; valaddr_reg:x3; val_offset:6117*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 6117*FLEN/8, x4, x1, x2)

inst_2040:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x8001; op2val:0xfbff;
op3val:0x0; valaddr_reg:x3; val_offset:6120*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 6120*FLEN/8, x4, x1, x2)

inst_2041:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x8001; op2val:0xfbff;
op3val:0x8000; valaddr_reg:x3; val_offset:6123*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 6123*FLEN/8, x4, x1, x2)

inst_2042:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x8001; op2val:0xfbff;
op3val:0x1; valaddr_reg:x3; val_offset:6126*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 6126*FLEN/8, x4, x1, x2)

inst_2043:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x8001; op2val:0xfbff;
op3val:0x8001; valaddr_reg:x3; val_offset:6129*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 6129*FLEN/8, x4, x1, x2)

inst_2044:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x002 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x8001; op2val:0xfbff;
op3val:0x2; valaddr_reg:x3; val_offset:6132*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 6132*FLEN/8, x4, x1, x2)

inst_2045:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3fe and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x8001; op2val:0xfbff;
op3val:0x83fe; valaddr_reg:x3; val_offset:6135*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 6135*FLEN/8, x4, x1, x2)

inst_2046:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x8001; op2val:0xfbff;
op3val:0x3ff; valaddr_reg:x3; val_offset:6138*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 6138*FLEN/8, x4, x1, x2)

inst_2047:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x8001; op2val:0xfbff;
op3val:0x83ff; valaddr_reg:x3; val_offset:6141*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 6141*FLEN/8, x4, x1, x2)

RVTEST_SIGBASE(x1,signature_x1_17)
inst_2048:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x8001; op2val:0xfbff;
op3val:0x400; valaddr_reg:x3; val_offset:6144*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 6144*FLEN/8, x4, x1, x2)

inst_2049:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x8001; op2val:0xfbff;
op3val:0x8400; valaddr_reg:x3; val_offset:6147*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 6147*FLEN/8, x4, x1, x2)

inst_2050:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x01 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x8001; op2val:0xfbff;
op3val:0x401; valaddr_reg:x3; val_offset:6150*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 6150*FLEN/8, x4, x1, x2)

inst_2051:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x8001; op2val:0xfbff;
op3val:0x8455; valaddr_reg:x3; val_offset:6153*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 6153*FLEN/8, x4, x1, x2)

inst_2052:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x8001; op2val:0xfbff;
op3val:0x7bff; valaddr_reg:x3; val_offset:6156*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 6156*FLEN/8, x4, x1, x2)

inst_2053:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x8001; op2val:0xfbff;
op3val:0xfbff; valaddr_reg:x3; val_offset:6159*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 6159*FLEN/8, x4, x1, x2)

inst_2054:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x8001; op2val:0xfbff;
op3val:0x7c00; valaddr_reg:x3; val_offset:6162*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 6162*FLEN/8, x4, x1, x2)

inst_2055:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x8001; op2val:0xfbff;
op3val:0xfc00; valaddr_reg:x3; val_offset:6165*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 6165*FLEN/8, x4, x1, x2)

inst_2056:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x8001; op2val:0xfbff;
op3val:0x7e00; valaddr_reg:x3; val_offset:6168*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 6168*FLEN/8, x4, x1, x2)

inst_2057:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x8001; op2val:0xfbff;
op3val:0xfe00; valaddr_reg:x3; val_offset:6171*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 6171*FLEN/8, x4, x1, x2)

inst_2058:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x1f and fm3 == 0x201 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x8001; op2val:0xfbff;
op3val:0x7e01; valaddr_reg:x3; val_offset:6174*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 6174*FLEN/8, x4, x1, x2)

inst_2059:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x1f and fm3 == 0x255 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x8001; op2val:0xfbff;
op3val:0xfe55; valaddr_reg:x3; val_offset:6177*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 6177*FLEN/8, x4, x1, x2)

inst_2060:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x1f and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x8001; op2val:0xfbff;
op3val:0x7c01; valaddr_reg:x3; val_offset:6180*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 6180*FLEN/8, x4, x1, x2)

inst_2061:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x1f and fm3 == 0x155 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x8001; op2val:0xfbff;
op3val:0xfd55; valaddr_reg:x3; val_offset:6183*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 6183*FLEN/8, x4, x1, x2)

inst_2062:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x8001; op2val:0xfbff;
op3val:0x3c00; valaddr_reg:x3; val_offset:6186*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 6186*FLEN/8, x4, x1, x2)

inst_2063:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x8001; op2val:0xfbff;
op3val:0xbc00; valaddr_reg:x3; val_offset:6189*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 6189*FLEN/8, x4, x1, x2)

inst_2064:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x8001; op2val:0x7c00;
op3val:0x0; valaddr_reg:x3; val_offset:6192*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 6192*FLEN/8, x4, x1, x2)

inst_2065:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x8001; op2val:0x7c00;
op3val:0x8000; valaddr_reg:x3; val_offset:6195*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 6195*FLEN/8, x4, x1, x2)

inst_2066:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x8001; op2val:0x7c00;
op3val:0x1; valaddr_reg:x3; val_offset:6198*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 6198*FLEN/8, x4, x1, x2)

inst_2067:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x8001; op2val:0x7c00;
op3val:0x8001; valaddr_reg:x3; val_offset:6201*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 6201*FLEN/8, x4, x1, x2)

inst_2068:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x002 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x8001; op2val:0x7c00;
op3val:0x2; valaddr_reg:x3; val_offset:6204*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 6204*FLEN/8, x4, x1, x2)

inst_2069:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3fe and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x8001; op2val:0x7c00;
op3val:0x83fe; valaddr_reg:x3; val_offset:6207*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 6207*FLEN/8, x4, x1, x2)

inst_2070:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x8001; op2val:0x7c00;
op3val:0x3ff; valaddr_reg:x3; val_offset:6210*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 6210*FLEN/8, x4, x1, x2)

inst_2071:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x8001; op2val:0x7c00;
op3val:0x83ff; valaddr_reg:x3; val_offset:6213*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 6213*FLEN/8, x4, x1, x2)

inst_2072:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x8001; op2val:0x7c00;
op3val:0x400; valaddr_reg:x3; val_offset:6216*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 6216*FLEN/8, x4, x1, x2)

inst_2073:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x8001; op2val:0x7c00;
op3val:0x8400; valaddr_reg:x3; val_offset:6219*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 6219*FLEN/8, x4, x1, x2)

inst_2074:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x8001; op2val:0x7c00;
op3val:0x401; valaddr_reg:x3; val_offset:6222*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 6222*FLEN/8, x4, x1, x2)

inst_2075:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x8001; op2val:0x7c00;
op3val:0x8455; valaddr_reg:x3; val_offset:6225*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 6225*FLEN/8, x4, x1, x2)

inst_2076:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x8001; op2val:0x7c00;
op3val:0x7bff; valaddr_reg:x3; val_offset:6228*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 6228*FLEN/8, x4, x1, x2)

inst_2077:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x8001; op2val:0x7c00;
op3val:0xfbff; valaddr_reg:x3; val_offset:6231*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 6231*FLEN/8, x4, x1, x2)

inst_2078:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x8001; op2val:0x7c00;
op3val:0x7c00; valaddr_reg:x3; val_offset:6234*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 6234*FLEN/8, x4, x1, x2)

inst_2079:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x8001; op2val:0x7c00;
op3val:0xfc00; valaddr_reg:x3; val_offset:6237*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 6237*FLEN/8, x4, x1, x2)

inst_2080:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x8001; op2val:0x7c00;
op3val:0x7e00; valaddr_reg:x3; val_offset:6240*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 6240*FLEN/8, x4, x1, x2)

inst_2081:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x8001; op2val:0x7c00;
op3val:0xfe00; valaddr_reg:x3; val_offset:6243*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 6243*FLEN/8, x4, x1, x2)

inst_2082:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x201 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x8001; op2val:0x7c00;
op3val:0x7e01; valaddr_reg:x3; val_offset:6246*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 6246*FLEN/8, x4, x1, x2)

inst_2083:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x255 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x8001; op2val:0x7c00;
op3val:0xfe55; valaddr_reg:x3; val_offset:6249*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 6249*FLEN/8, x4, x1, x2)

inst_2084:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x8001; op2val:0x7c00;
op3val:0x7c01; valaddr_reg:x3; val_offset:6252*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 6252*FLEN/8, x4, x1, x2)

inst_2085:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x155 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x8001; op2val:0x7c00;
op3val:0xfd55; valaddr_reg:x3; val_offset:6255*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 6255*FLEN/8, x4, x1, x2)

inst_2086:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x8001; op2val:0x7c00;
op3val:0x3c00; valaddr_reg:x3; val_offset:6258*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 6258*FLEN/8, x4, x1, x2)

inst_2087:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x8001; op2val:0x7c00;
op3val:0xbc00; valaddr_reg:x3; val_offset:6261*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 6261*FLEN/8, x4, x1, x2)

inst_2088:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x8001; op2val:0xfc00;
op3val:0x0; valaddr_reg:x3; val_offset:6264*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 6264*FLEN/8, x4, x1, x2)

inst_2089:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x8001; op2val:0xfc00;
op3val:0x8000; valaddr_reg:x3; val_offset:6267*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 6267*FLEN/8, x4, x1, x2)

inst_2090:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x8001; op2val:0xfc00;
op3val:0x1; valaddr_reg:x3; val_offset:6270*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 6270*FLEN/8, x4, x1, x2)

inst_2091:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x8001; op2val:0xfc00;
op3val:0x8001; valaddr_reg:x3; val_offset:6273*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 6273*FLEN/8, x4, x1, x2)

inst_2092:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x002 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x8001; op2val:0xfc00;
op3val:0x2; valaddr_reg:x3; val_offset:6276*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 6276*FLEN/8, x4, x1, x2)

inst_2093:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3fe and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x8001; op2val:0xfc00;
op3val:0x83fe; valaddr_reg:x3; val_offset:6279*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 6279*FLEN/8, x4, x1, x2)

inst_2094:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x8001; op2val:0xfc00;
op3val:0x3ff; valaddr_reg:x3; val_offset:6282*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 6282*FLEN/8, x4, x1, x2)

inst_2095:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x8001; op2val:0xfc00;
op3val:0x83ff; valaddr_reg:x3; val_offset:6285*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 6285*FLEN/8, x4, x1, x2)

inst_2096:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x8001; op2val:0xfc00;
op3val:0x400; valaddr_reg:x3; val_offset:6288*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 6288*FLEN/8, x4, x1, x2)

inst_2097:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x8001; op2val:0xfc00;
op3val:0x8400; valaddr_reg:x3; val_offset:6291*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 6291*FLEN/8, x4, x1, x2)

inst_2098:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x8001; op2val:0xfc00;
op3val:0x401; valaddr_reg:x3; val_offset:6294*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 6294*FLEN/8, x4, x1, x2)

inst_2099:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x8001; op2val:0xfc00;
op3val:0x8455; valaddr_reg:x3; val_offset:6297*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 6297*FLEN/8, x4, x1, x2)

inst_2100:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x8001; op2val:0xfc00;
op3val:0x7bff; valaddr_reg:x3; val_offset:6300*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 6300*FLEN/8, x4, x1, x2)

inst_2101:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x8001; op2val:0xfc00;
op3val:0xfbff; valaddr_reg:x3; val_offset:6303*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 6303*FLEN/8, x4, x1, x2)

inst_2102:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x8001; op2val:0xfc00;
op3val:0x7c00; valaddr_reg:x3; val_offset:6306*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 6306*FLEN/8, x4, x1, x2)

inst_2103:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x8001; op2val:0xfc00;
op3val:0xfc00; valaddr_reg:x3; val_offset:6309*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 6309*FLEN/8, x4, x1, x2)

inst_2104:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x8001; op2val:0xfc00;
op3val:0x7e00; valaddr_reg:x3; val_offset:6312*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 6312*FLEN/8, x4, x1, x2)

inst_2105:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x8001; op2val:0xfc00;
op3val:0xfe00; valaddr_reg:x3; val_offset:6315*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 6315*FLEN/8, x4, x1, x2)

inst_2106:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x201 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x8001; op2val:0xfc00;
op3val:0x7e01; valaddr_reg:x3; val_offset:6318*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 6318*FLEN/8, x4, x1, x2)

inst_2107:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x255 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x8001; op2val:0xfc00;
op3val:0xfe55; valaddr_reg:x3; val_offset:6321*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 6321*FLEN/8, x4, x1, x2)

inst_2108:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x8001; op2val:0xfc00;
op3val:0x7c01; valaddr_reg:x3; val_offset:6324*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 6324*FLEN/8, x4, x1, x2)

inst_2109:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x155 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x8001; op2val:0xfc00;
op3val:0xfd55; valaddr_reg:x3; val_offset:6327*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 6327*FLEN/8, x4, x1, x2)

inst_2110:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x8001; op2val:0xfc00;
op3val:0x3c00; valaddr_reg:x3; val_offset:6330*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 6330*FLEN/8, x4, x1, x2)

inst_2111:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x8001; op2val:0xfc00;
op3val:0xbc00; valaddr_reg:x3; val_offset:6333*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 6333*FLEN/8, x4, x1, x2)

inst_2112:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x8001; op2val:0x7e00;
op3val:0x0; valaddr_reg:x3; val_offset:6336*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 6336*FLEN/8, x4, x1, x2)

inst_2113:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x8001; op2val:0x7e00;
op3val:0x8000; valaddr_reg:x3; val_offset:6339*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 6339*FLEN/8, x4, x1, x2)

inst_2114:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x8001; op2val:0x7e00;
op3val:0x1; valaddr_reg:x3; val_offset:6342*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 6342*FLEN/8, x4, x1, x2)

inst_2115:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x8001; op2val:0x7e00;
op3val:0x8001; valaddr_reg:x3; val_offset:6345*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 6345*FLEN/8, x4, x1, x2)

inst_2116:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x002 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x8001; op2val:0x7e00;
op3val:0x2; valaddr_reg:x3; val_offset:6348*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 6348*FLEN/8, x4, x1, x2)

inst_2117:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3fe and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x8001; op2val:0x7e00;
op3val:0x83fe; valaddr_reg:x3; val_offset:6351*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 6351*FLEN/8, x4, x1, x2)

inst_2118:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x8001; op2val:0x7e00;
op3val:0x3ff; valaddr_reg:x3; val_offset:6354*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 6354*FLEN/8, x4, x1, x2)

inst_2119:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x8001; op2val:0x7e00;
op3val:0x83ff; valaddr_reg:x3; val_offset:6357*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 6357*FLEN/8, x4, x1, x2)

inst_2120:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x8001; op2val:0x7e00;
op3val:0x400; valaddr_reg:x3; val_offset:6360*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 6360*FLEN/8, x4, x1, x2)

inst_2121:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x8001; op2val:0x7e00;
op3val:0x8400; valaddr_reg:x3; val_offset:6363*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 6363*FLEN/8, x4, x1, x2)

inst_2122:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x8001; op2val:0x7e00;
op3val:0x401; valaddr_reg:x3; val_offset:6366*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 6366*FLEN/8, x4, x1, x2)

inst_2123:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x8001; op2val:0x7e00;
op3val:0x8455; valaddr_reg:x3; val_offset:6369*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 6369*FLEN/8, x4, x1, x2)

inst_2124:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x8001; op2val:0x7e00;
op3val:0x7bff; valaddr_reg:x3; val_offset:6372*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 6372*FLEN/8, x4, x1, x2)

inst_2125:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x8001; op2val:0x7e00;
op3val:0xfbff; valaddr_reg:x3; val_offset:6375*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 6375*FLEN/8, x4, x1, x2)

inst_2126:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x8001; op2val:0x7e00;
op3val:0x7c00; valaddr_reg:x3; val_offset:6378*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 6378*FLEN/8, x4, x1, x2)

inst_2127:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x8001; op2val:0x7e00;
op3val:0xfc00; valaddr_reg:x3; val_offset:6381*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 6381*FLEN/8, x4, x1, x2)

inst_2128:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x8001; op2val:0x7e00;
op3val:0x7e00; valaddr_reg:x3; val_offset:6384*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 6384*FLEN/8, x4, x1, x2)

inst_2129:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x8001; op2val:0x7e00;
op3val:0xfe00; valaddr_reg:x3; val_offset:6387*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 6387*FLEN/8, x4, x1, x2)

inst_2130:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x201 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x8001; op2val:0x7e00;
op3val:0x7e01; valaddr_reg:x3; val_offset:6390*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 6390*FLEN/8, x4, x1, x2)

inst_2131:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x255 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x8001; op2val:0x7e00;
op3val:0xfe55; valaddr_reg:x3; val_offset:6393*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 6393*FLEN/8, x4, x1, x2)

inst_2132:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x8001; op2val:0x7e00;
op3val:0x7c01; valaddr_reg:x3; val_offset:6396*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 6396*FLEN/8, x4, x1, x2)

inst_2133:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x155 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x8001; op2val:0x7e00;
op3val:0xfd55; valaddr_reg:x3; val_offset:6399*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 6399*FLEN/8, x4, x1, x2)

inst_2134:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 0 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x8001; op2val:0x7e00;
op3val:0x3c00; valaddr_reg:x3; val_offset:6402*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 6402*FLEN/8, x4, x1, x2)

inst_2135:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 1 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x8001; op2val:0x7e00;
op3val:0xbc00; valaddr_reg:x3; val_offset:6405*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 6405*FLEN/8, x4, x1, x2)

inst_2136:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x8001; op2val:0xfe00;
op3val:0x0; valaddr_reg:x3; val_offset:6408*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 6408*FLEN/8, x4, x1, x2)

inst_2137:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x8001; op2val:0xfe00;
op3val:0x8000; valaddr_reg:x3; val_offset:6411*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 6411*FLEN/8, x4, x1, x2)

inst_2138:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x8001; op2val:0xfe00;
op3val:0x1; valaddr_reg:x3; val_offset:6414*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 6414*FLEN/8, x4, x1, x2)

inst_2139:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x8001; op2val:0xfe00;
op3val:0x8001; valaddr_reg:x3; val_offset:6417*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 6417*FLEN/8, x4, x1, x2)

inst_2140:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x002 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x8001; op2val:0xfe00;
op3val:0x2; valaddr_reg:x3; val_offset:6420*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 6420*FLEN/8, x4, x1, x2)

inst_2141:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3fe and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x8001; op2val:0xfe00;
op3val:0x83fe; valaddr_reg:x3; val_offset:6423*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 6423*FLEN/8, x4, x1, x2)

inst_2142:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x8001; op2val:0xfe00;
op3val:0x3ff; valaddr_reg:x3; val_offset:6426*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 6426*FLEN/8, x4, x1, x2)

inst_2143:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x8001; op2val:0xfe00;
op3val:0x83ff; valaddr_reg:x3; val_offset:6429*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 6429*FLEN/8, x4, x1, x2)

inst_2144:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x8001; op2val:0xfe00;
op3val:0x400; valaddr_reg:x3; val_offset:6432*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 6432*FLEN/8, x4, x1, x2)

inst_2145:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x8001; op2val:0xfe00;
op3val:0x8400; valaddr_reg:x3; val_offset:6435*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 6435*FLEN/8, x4, x1, x2)

inst_2146:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x8001; op2val:0xfe00;
op3val:0x401; valaddr_reg:x3; val_offset:6438*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 6438*FLEN/8, x4, x1, x2)

inst_2147:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x8001; op2val:0xfe00;
op3val:0x8455; valaddr_reg:x3; val_offset:6441*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 6441*FLEN/8, x4, x1, x2)

inst_2148:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x8001; op2val:0xfe00;
op3val:0x7bff; valaddr_reg:x3; val_offset:6444*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 6444*FLEN/8, x4, x1, x2)

inst_2149:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x8001; op2val:0xfe00;
op3val:0xfbff; valaddr_reg:x3; val_offset:6447*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 6447*FLEN/8, x4, x1, x2)

inst_2150:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x8001; op2val:0xfe00;
op3val:0x7c00; valaddr_reg:x3; val_offset:6450*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 6450*FLEN/8, x4, x1, x2)

inst_2151:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x8001; op2val:0xfe00;
op3val:0xfc00; valaddr_reg:x3; val_offset:6453*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 6453*FLEN/8, x4, x1, x2)

inst_2152:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x8001; op2val:0xfe00;
op3val:0x7e00; valaddr_reg:x3; val_offset:6456*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 6456*FLEN/8, x4, x1, x2)

inst_2153:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x8001; op2val:0xfe00;
op3val:0xfe00; valaddr_reg:x3; val_offset:6459*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 6459*FLEN/8, x4, x1, x2)

inst_2154:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x201 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x8001; op2val:0xfe00;
op3val:0x7e01; valaddr_reg:x3; val_offset:6462*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 6462*FLEN/8, x4, x1, x2)

inst_2155:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x255 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x8001; op2val:0xfe00;
op3val:0xfe55; valaddr_reg:x3; val_offset:6465*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 6465*FLEN/8, x4, x1, x2)

inst_2156:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x8001; op2val:0xfe00;
op3val:0x7c01; valaddr_reg:x3; val_offset:6468*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 6468*FLEN/8, x4, x1, x2)

inst_2157:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x155 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x8001; op2val:0xfe00;
op3val:0xfd55; valaddr_reg:x3; val_offset:6471*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 6471*FLEN/8, x4, x1, x2)

inst_2158:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 0 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x8001; op2val:0xfe00;
op3val:0x3c00; valaddr_reg:x3; val_offset:6474*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 6474*FLEN/8, x4, x1, x2)

inst_2159:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 1 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x8001; op2val:0xfe00;
op3val:0xbc00; valaddr_reg:x3; val_offset:6477*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 6477*FLEN/8, x4, x1, x2)

inst_2160:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x8001; op2val:0x7e01;
op3val:0x0; valaddr_reg:x3; val_offset:6480*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 6480*FLEN/8, x4, x1, x2)

inst_2161:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x8001; op2val:0x7e01;
op3val:0x8000; valaddr_reg:x3; val_offset:6483*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 6483*FLEN/8, x4, x1, x2)

inst_2162:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x8001; op2val:0x7e01;
op3val:0x1; valaddr_reg:x3; val_offset:6486*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 6486*FLEN/8, x4, x1, x2)

inst_2163:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x8001; op2val:0x7e01;
op3val:0x8001; valaddr_reg:x3; val_offset:6489*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 6489*FLEN/8, x4, x1, x2)

inst_2164:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x002 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x8001; op2val:0x7e01;
op3val:0x2; valaddr_reg:x3; val_offset:6492*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 6492*FLEN/8, x4, x1, x2)

inst_2165:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3fe and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x8001; op2val:0x7e01;
op3val:0x83fe; valaddr_reg:x3; val_offset:6495*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 6495*FLEN/8, x4, x1, x2)

inst_2166:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x8001; op2val:0x7e01;
op3val:0x3ff; valaddr_reg:x3; val_offset:6498*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 6498*FLEN/8, x4, x1, x2)

inst_2167:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x8001; op2val:0x7e01;
op3val:0x83ff; valaddr_reg:x3; val_offset:6501*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 6501*FLEN/8, x4, x1, x2)

inst_2168:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x8001; op2val:0x7e01;
op3val:0x400; valaddr_reg:x3; val_offset:6504*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 6504*FLEN/8, x4, x1, x2)

inst_2169:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x8001; op2val:0x7e01;
op3val:0x8400; valaddr_reg:x3; val_offset:6507*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 6507*FLEN/8, x4, x1, x2)

inst_2170:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x8001; op2val:0x7e01;
op3val:0x401; valaddr_reg:x3; val_offset:6510*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 6510*FLEN/8, x4, x1, x2)

inst_2171:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x8001; op2val:0x7e01;
op3val:0x8455; valaddr_reg:x3; val_offset:6513*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 6513*FLEN/8, x4, x1, x2)

inst_2172:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x8001; op2val:0x7e01;
op3val:0x7bff; valaddr_reg:x3; val_offset:6516*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 6516*FLEN/8, x4, x1, x2)

inst_2173:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x8001; op2val:0x7e01;
op3val:0xfbff; valaddr_reg:x3; val_offset:6519*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 6519*FLEN/8, x4, x1, x2)

inst_2174:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x8001; op2val:0x7e01;
op3val:0x7c00; valaddr_reg:x3; val_offset:6522*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 6522*FLEN/8, x4, x1, x2)

inst_2175:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x8001; op2val:0x7e01;
op3val:0xfc00; valaddr_reg:x3; val_offset:6525*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 6525*FLEN/8, x4, x1, x2)

RVTEST_SIGBASE(x1,signature_x1_18)
inst_2176:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x8001; op2val:0x7e01;
op3val:0x7e00; valaddr_reg:x3; val_offset:6528*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 6528*FLEN/8, x4, x1, x2)

inst_2177:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x8001; op2val:0x7e01;
op3val:0xfe00; valaddr_reg:x3; val_offset:6531*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 6531*FLEN/8, x4, x1, x2)

inst_2178:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x201 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x8001; op2val:0x7e01;
op3val:0x7e01; valaddr_reg:x3; val_offset:6534*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 6534*FLEN/8, x4, x1, x2)

inst_2179:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x255 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x8001; op2val:0x7e01;
op3val:0xfe55; valaddr_reg:x3; val_offset:6537*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 6537*FLEN/8, x4, x1, x2)

inst_2180:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x8001; op2val:0x7e01;
op3val:0x7c01; valaddr_reg:x3; val_offset:6540*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 6540*FLEN/8, x4, x1, x2)

inst_2181:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x155 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x8001; op2val:0x7e01;
op3val:0xfd55; valaddr_reg:x3; val_offset:6543*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 6543*FLEN/8, x4, x1, x2)

inst_2182:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fs3 == 0 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x8001; op2val:0x7e01;
op3val:0x3c00; valaddr_reg:x3; val_offset:6546*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 6546*FLEN/8, x4, x1, x2)

inst_2183:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fs3 == 1 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x8001; op2val:0x7e01;
op3val:0xbc00; valaddr_reg:x3; val_offset:6549*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 6549*FLEN/8, x4, x1, x2)

inst_2184:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x8001; op2val:0xfe55;
op3val:0x0; valaddr_reg:x3; val_offset:6552*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 6552*FLEN/8, x4, x1, x2)

inst_2185:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x8001; op2val:0xfe55;
op3val:0x8000; valaddr_reg:x3; val_offset:6555*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 6555*FLEN/8, x4, x1, x2)

inst_2186:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x8001; op2val:0xfe55;
op3val:0x1; valaddr_reg:x3; val_offset:6558*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 6558*FLEN/8, x4, x1, x2)

inst_2187:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x8001; op2val:0xfe55;
op3val:0x8001; valaddr_reg:x3; val_offset:6561*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 6561*FLEN/8, x4, x1, x2)

inst_2188:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x002 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x8001; op2val:0xfe55;
op3val:0x2; valaddr_reg:x3; val_offset:6564*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 6564*FLEN/8, x4, x1, x2)

inst_2189:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3fe and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x8001; op2val:0xfe55;
op3val:0x83fe; valaddr_reg:x3; val_offset:6567*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 6567*FLEN/8, x4, x1, x2)

inst_2190:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x8001; op2val:0xfe55;
op3val:0x3ff; valaddr_reg:x3; val_offset:6570*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 6570*FLEN/8, x4, x1, x2)

inst_2191:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x8001; op2val:0xfe55;
op3val:0x83ff; valaddr_reg:x3; val_offset:6573*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 6573*FLEN/8, x4, x1, x2)

inst_2192:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x8001; op2val:0xfe55;
op3val:0x400; valaddr_reg:x3; val_offset:6576*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 6576*FLEN/8, x4, x1, x2)

inst_2193:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x8001; op2val:0xfe55;
op3val:0x8400; valaddr_reg:x3; val_offset:6579*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 6579*FLEN/8, x4, x1, x2)

inst_2194:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x8001; op2val:0xfe55;
op3val:0x401; valaddr_reg:x3; val_offset:6582*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 6582*FLEN/8, x4, x1, x2)

inst_2195:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x8001; op2val:0xfe55;
op3val:0x8455; valaddr_reg:x3; val_offset:6585*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 6585*FLEN/8, x4, x1, x2)

inst_2196:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x8001; op2val:0xfe55;
op3val:0x7bff; valaddr_reg:x3; val_offset:6588*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 6588*FLEN/8, x4, x1, x2)

inst_2197:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x8001; op2val:0xfe55;
op3val:0xfbff; valaddr_reg:x3; val_offset:6591*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 6591*FLEN/8, x4, x1, x2)

inst_2198:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x8001; op2val:0xfe55;
op3val:0x7c00; valaddr_reg:x3; val_offset:6594*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 6594*FLEN/8, x4, x1, x2)

inst_2199:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x8001; op2val:0xfe55;
op3val:0xfc00; valaddr_reg:x3; val_offset:6597*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 6597*FLEN/8, x4, x1, x2)

inst_2200:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x8001; op2val:0xfe55;
op3val:0x7e00; valaddr_reg:x3; val_offset:6600*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 6600*FLEN/8, x4, x1, x2)

inst_2201:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x8001; op2val:0xfe55;
op3val:0xfe00; valaddr_reg:x3; val_offset:6603*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 6603*FLEN/8, x4, x1, x2)

inst_2202:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x201 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x8001; op2val:0xfe55;
op3val:0x7e01; valaddr_reg:x3; val_offset:6606*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 6606*FLEN/8, x4, x1, x2)

inst_2203:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x255 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x8001; op2val:0xfe55;
op3val:0xfe55; valaddr_reg:x3; val_offset:6609*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 6609*FLEN/8, x4, x1, x2)

inst_2204:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x8001; op2val:0xfe55;
op3val:0x7c01; valaddr_reg:x3; val_offset:6612*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 6612*FLEN/8, x4, x1, x2)

inst_2205:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x155 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x8001; op2val:0xfe55;
op3val:0xfd55; valaddr_reg:x3; val_offset:6615*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 6615*FLEN/8, x4, x1, x2)

inst_2206:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fs3 == 0 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x8001; op2val:0xfe55;
op3val:0x3c00; valaddr_reg:x3; val_offset:6618*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 6618*FLEN/8, x4, x1, x2)

inst_2207:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fs3 == 1 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x8001; op2val:0xfe55;
op3val:0xbc00; valaddr_reg:x3; val_offset:6621*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 6621*FLEN/8, x4, x1, x2)

inst_2208:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x8001; op2val:0x7c01;
op3val:0x0; valaddr_reg:x3; val_offset:6624*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 6624*FLEN/8, x4, x1, x2)

inst_2209:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x8001; op2val:0x7c01;
op3val:0x8000; valaddr_reg:x3; val_offset:6627*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 6627*FLEN/8, x4, x1, x2)

inst_2210:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x8001; op2val:0x7c01;
op3val:0x1; valaddr_reg:x3; val_offset:6630*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 6630*FLEN/8, x4, x1, x2)

inst_2211:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x8001; op2val:0x7c01;
op3val:0x8001; valaddr_reg:x3; val_offset:6633*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 6633*FLEN/8, x4, x1, x2)

inst_2212:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x002 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x8001; op2val:0x7c01;
op3val:0x2; valaddr_reg:x3; val_offset:6636*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 6636*FLEN/8, x4, x1, x2)

inst_2213:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3fe and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x8001; op2val:0x7c01;
op3val:0x83fe; valaddr_reg:x3; val_offset:6639*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 6639*FLEN/8, x4, x1, x2)

inst_2214:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x8001; op2val:0x7c01;
op3val:0x3ff; valaddr_reg:x3; val_offset:6642*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 6642*FLEN/8, x4, x1, x2)

inst_2215:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x8001; op2val:0x7c01;
op3val:0x83ff; valaddr_reg:x3; val_offset:6645*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 6645*FLEN/8, x4, x1, x2)

inst_2216:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x8001; op2val:0x7c01;
op3val:0x400; valaddr_reg:x3; val_offset:6648*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 6648*FLEN/8, x4, x1, x2)

inst_2217:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x8001; op2val:0x7c01;
op3val:0x8400; valaddr_reg:x3; val_offset:6651*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 6651*FLEN/8, x4, x1, x2)

inst_2218:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x8001; op2val:0x7c01;
op3val:0x401; valaddr_reg:x3; val_offset:6654*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 6654*FLEN/8, x4, x1, x2)

inst_2219:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x8001; op2val:0x7c01;
op3val:0x8455; valaddr_reg:x3; val_offset:6657*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 6657*FLEN/8, x4, x1, x2)

inst_2220:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x8001; op2val:0x7c01;
op3val:0x7bff; valaddr_reg:x3; val_offset:6660*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 6660*FLEN/8, x4, x1, x2)

inst_2221:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x8001; op2val:0x7c01;
op3val:0xfbff; valaddr_reg:x3; val_offset:6663*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 6663*FLEN/8, x4, x1, x2)

inst_2222:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x8001; op2val:0x7c01;
op3val:0x7c00; valaddr_reg:x3; val_offset:6666*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 6666*FLEN/8, x4, x1, x2)

inst_2223:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x8001; op2val:0x7c01;
op3val:0xfc00; valaddr_reg:x3; val_offset:6669*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 6669*FLEN/8, x4, x1, x2)

inst_2224:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x8001; op2val:0x7c01;
op3val:0x7e00; valaddr_reg:x3; val_offset:6672*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 6672*FLEN/8, x4, x1, x2)

inst_2225:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x8001; op2val:0x7c01;
op3val:0xfe00; valaddr_reg:x3; val_offset:6675*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 6675*FLEN/8, x4, x1, x2)

inst_2226:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x201 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x8001; op2val:0x7c01;
op3val:0x7e01; valaddr_reg:x3; val_offset:6678*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 6678*FLEN/8, x4, x1, x2)

inst_2227:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x255 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x8001; op2val:0x7c01;
op3val:0xfe55; valaddr_reg:x3; val_offset:6681*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 6681*FLEN/8, x4, x1, x2)

inst_2228:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x8001; op2val:0x7c01;
op3val:0x7c01; valaddr_reg:x3; val_offset:6684*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 6684*FLEN/8, x4, x1, x2)

inst_2229:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x155 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x8001; op2val:0x7c01;
op3val:0xfd55; valaddr_reg:x3; val_offset:6687*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 6687*FLEN/8, x4, x1, x2)

inst_2230:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fs3 == 0 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x8001; op2val:0x7c01;
op3val:0x3c00; valaddr_reg:x3; val_offset:6690*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 6690*FLEN/8, x4, x1, x2)

inst_2231:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fs3 == 1 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x8001; op2val:0x7c01;
op3val:0xbc00; valaddr_reg:x3; val_offset:6693*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 6693*FLEN/8, x4, x1, x2)

inst_2232:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x8001; op2val:0xfd55;
op3val:0x0; valaddr_reg:x3; val_offset:6696*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 6696*FLEN/8, x4, x1, x2)

inst_2233:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x8001; op2val:0xfd55;
op3val:0x8000; valaddr_reg:x3; val_offset:6699*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 6699*FLEN/8, x4, x1, x2)

inst_2234:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x8001; op2val:0xfd55;
op3val:0x1; valaddr_reg:x3; val_offset:6702*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 6702*FLEN/8, x4, x1, x2)

inst_2235:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x8001; op2val:0xfd55;
op3val:0x8001; valaddr_reg:x3; val_offset:6705*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 6705*FLEN/8, x4, x1, x2)

inst_2236:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x002 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x8001; op2val:0xfd55;
op3val:0x2; valaddr_reg:x3; val_offset:6708*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 6708*FLEN/8, x4, x1, x2)

inst_2237:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3fe and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x8001; op2val:0xfd55;
op3val:0x83fe; valaddr_reg:x3; val_offset:6711*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 6711*FLEN/8, x4, x1, x2)

inst_2238:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x8001; op2val:0xfd55;
op3val:0x3ff; valaddr_reg:x3; val_offset:6714*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 6714*FLEN/8, x4, x1, x2)

inst_2239:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x8001; op2val:0xfd55;
op3val:0x83ff; valaddr_reg:x3; val_offset:6717*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 6717*FLEN/8, x4, x1, x2)

inst_2240:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x8001; op2val:0xfd55;
op3val:0x400; valaddr_reg:x3; val_offset:6720*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 6720*FLEN/8, x4, x1, x2)

inst_2241:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x8001; op2val:0xfd55;
op3val:0x8400; valaddr_reg:x3; val_offset:6723*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 6723*FLEN/8, x4, x1, x2)

inst_2242:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x8001; op2val:0xfd55;
op3val:0x401; valaddr_reg:x3; val_offset:6726*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 6726*FLEN/8, x4, x1, x2)

inst_2243:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x8001; op2val:0xfd55;
op3val:0x8455; valaddr_reg:x3; val_offset:6729*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 6729*FLEN/8, x4, x1, x2)

inst_2244:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x8001; op2val:0xfd55;
op3val:0x7bff; valaddr_reg:x3; val_offset:6732*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 6732*FLEN/8, x4, x1, x2)

inst_2245:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x8001; op2val:0xfd55;
op3val:0xfbff; valaddr_reg:x3; val_offset:6735*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 6735*FLEN/8, x4, x1, x2)

inst_2246:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x8001; op2val:0xfd55;
op3val:0x7c00; valaddr_reg:x3; val_offset:6738*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 6738*FLEN/8, x4, x1, x2)

inst_2247:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x8001; op2val:0xfd55;
op3val:0xfc00; valaddr_reg:x3; val_offset:6741*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 6741*FLEN/8, x4, x1, x2)

inst_2248:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x8001; op2val:0xfd55;
op3val:0x7e00; valaddr_reg:x3; val_offset:6744*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 6744*FLEN/8, x4, x1, x2)

inst_2249:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x8001; op2val:0xfd55;
op3val:0xfe00; valaddr_reg:x3; val_offset:6747*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 6747*FLEN/8, x4, x1, x2)

inst_2250:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x201 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x8001; op2val:0xfd55;
op3val:0x7e01; valaddr_reg:x3; val_offset:6750*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 6750*FLEN/8, x4, x1, x2)

inst_2251:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x255 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x8001; op2val:0xfd55;
op3val:0xfe55; valaddr_reg:x3; val_offset:6753*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 6753*FLEN/8, x4, x1, x2)

inst_2252:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x8001; op2val:0xfd55;
op3val:0x7c01; valaddr_reg:x3; val_offset:6756*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 6756*FLEN/8, x4, x1, x2)

inst_2253:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x155 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x8001; op2val:0xfd55;
op3val:0xfd55; valaddr_reg:x3; val_offset:6759*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 6759*FLEN/8, x4, x1, x2)

inst_2254:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fs3 == 0 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x8001; op2val:0xfd55;
op3val:0x3c00; valaddr_reg:x3; val_offset:6762*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 6762*FLEN/8, x4, x1, x2)

inst_2255:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fs3 == 1 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x8001; op2val:0xfd55;
op3val:0xbc00; valaddr_reg:x3; val_offset:6765*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 6765*FLEN/8, x4, x1, x2)

inst_2256:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x8001; op2val:0x3c00;
op3val:0x0; valaddr_reg:x3; val_offset:6768*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 6768*FLEN/8, x4, x1, x2)

inst_2257:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x8001; op2val:0x3c00;
op3val:0x8000; valaddr_reg:x3; val_offset:6771*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 6771*FLEN/8, x4, x1, x2)

inst_2258:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x8001; op2val:0x3c00;
op3val:0x1; valaddr_reg:x3; val_offset:6774*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 6774*FLEN/8, x4, x1, x2)

inst_2259:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x8001; op2val:0x3c00;
op3val:0x8001; valaddr_reg:x3; val_offset:6777*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 6777*FLEN/8, x4, x1, x2)

#endif
RVTEST_CODE_END
RVMODEL_HALT
RVTEST_DATA_BEGIN
.align 4
rvtest_data:
.word 0xbabecafe
.word 0xabecafeb
.word 0xbecafeba
.word 0xecafebab
test_dataset_0:
NAN_BOXED(64512,16,FLEN)
NAN_BOXED(48128,16,FLEN)
NAN_BOXED(1,16,FLEN)
NAN_BOXED(32256,16,FLEN)
NAN_BOXED(0,16,FLEN)
NAN_BOXED(1,16,FLEN)
NAN_BOXED(32256,16,FLEN)
NAN_BOXED(32768,16,FLEN)
NAN_BOXED(1,16,FLEN)
NAN_BOXED(32256,16,FLEN)
NAN_BOXED(1,16,FLEN)
NAN_BOXED(1,16,FLEN)
NAN_BOXED(32256,16,FLEN)
NAN_BOXED(32769,16,FLEN)
NAN_BOXED(1,16,FLEN)
NAN_BOXED(32256,16,FLEN)
NAN_BOXED(2,16,FLEN)
NAN_BOXED(1,16,FLEN)
NAN_BOXED(32256,16,FLEN)
NAN_BOXED(33790,16,FLEN)
NAN_BOXED(1,16,FLEN)
NAN_BOXED(32256,16,FLEN)
NAN_BOXED(1023,16,FLEN)
NAN_BOXED(1,16,FLEN)
NAN_BOXED(32256,16,FLEN)
NAN_BOXED(33791,16,FLEN)
NAN_BOXED(1,16,FLEN)
NAN_BOXED(32256,16,FLEN)
NAN_BOXED(1024,16,FLEN)
NAN_BOXED(1,16,FLEN)
NAN_BOXED(32256,16,FLEN)
NAN_BOXED(33792,16,FLEN)
NAN_BOXED(1,16,FLEN)
NAN_BOXED(32256,16,FLEN)
NAN_BOXED(1025,16,FLEN)
NAN_BOXED(1,16,FLEN)
NAN_BOXED(32256,16,FLEN)
NAN_BOXED(33877,16,FLEN)
NAN_BOXED(1,16,FLEN)
NAN_BOXED(32256,16,FLEN)
NAN_BOXED(31743,16,FLEN)
NAN_BOXED(1,16,FLEN)
NAN_BOXED(32256,16,FLEN)
NAN_BOXED(64511,16,FLEN)
NAN_BOXED(1,16,FLEN)
NAN_BOXED(32256,16,FLEN)
NAN_BOXED(31744,16,FLEN)
NAN_BOXED(1,16,FLEN)
NAN_BOXED(32256,16,FLEN)
NAN_BOXED(64512,16,FLEN)
NAN_BOXED(1,16,FLEN)
NAN_BOXED(32256,16,FLEN)
NAN_BOXED(32256,16,FLEN)
NAN_BOXED(1,16,FLEN)
NAN_BOXED(32256,16,FLEN)
NAN_BOXED(65024,16,FLEN)
NAN_BOXED(1,16,FLEN)
NAN_BOXED(32256,16,FLEN)
NAN_BOXED(32257,16,FLEN)
NAN_BOXED(1,16,FLEN)
NAN_BOXED(32256,16,FLEN)
NAN_BOXED(65109,16,FLEN)
NAN_BOXED(1,16,FLEN)
NAN_BOXED(32256,16,FLEN)
NAN_BOXED(31745,16,FLEN)
NAN_BOXED(1,16,FLEN)
NAN_BOXED(32256,16,FLEN)
NAN_BOXED(64853,16,FLEN)
NAN_BOXED(1,16,FLEN)
NAN_BOXED(32256,16,FLEN)
NAN_BOXED(15360,16,FLEN)
NAN_BOXED(1,16,FLEN)
NAN_BOXED(32256,16,FLEN)
NAN_BOXED(48128,16,FLEN)
NAN_BOXED(1,16,FLEN)
NAN_BOXED(65024,16,FLEN)
NAN_BOXED(0,16,FLEN)
NAN_BOXED(1,16,FLEN)
NAN_BOXED(65024,16,FLEN)
NAN_BOXED(32768,16,FLEN)
NAN_BOXED(1,16,FLEN)
NAN_BOXED(65024,16,FLEN)
NAN_BOXED(1,16,FLEN)
NAN_BOXED(1,16,FLEN)
NAN_BOXED(65024,16,FLEN)
NAN_BOXED(32769,16,FLEN)
NAN_BOXED(1,16,FLEN)
NAN_BOXED(65024,16,FLEN)
NAN_BOXED(2,16,FLEN)
NAN_BOXED(1,16,FLEN)
NAN_BOXED(65024,16,FLEN)
NAN_BOXED(33790,16,FLEN)
NAN_BOXED(1,16,FLEN)
NAN_BOXED(65024,16,FLEN)
NAN_BOXED(1023,16,FLEN)
NAN_BOXED(1,16,FLEN)
NAN_BOXED(65024,16,FLEN)
NAN_BOXED(33791,16,FLEN)
NAN_BOXED(1,16,FLEN)
NAN_BOXED(65024,16,FLEN)
NAN_BOXED(1024,16,FLEN)
NAN_BOXED(1,16,FLEN)
NAN_BOXED(65024,16,FLEN)
NAN_BOXED(33792,16,FLEN)
NAN_BOXED(1,16,FLEN)
NAN_BOXED(65024,16,FLEN)
NAN_BOXED(1025,16,FLEN)
NAN_BOXED(1,16,FLEN)
NAN_BOXED(65024,16,FLEN)
NAN_BOXED(33877,16,FLEN)
NAN_BOXED(1,16,FLEN)
NAN_BOXED(65024,16,FLEN)
NAN_BOXED(31743,16,FLEN)
NAN_BOXED(1,16,FLEN)
NAN_BOXED(65024,16,FLEN)
NAN_BOXED(64511,16,FLEN)
NAN_BOXED(1,16,FLEN)
NAN_BOXED(65024,16,FLEN)
NAN_BOXED(31744,16,FLEN)
NAN_BOXED(1,16,FLEN)
NAN_BOXED(65024,16,FLEN)
NAN_BOXED(64512,16,FLEN)
NAN_BOXED(1,16,FLEN)
NAN_BOXED(65024,16,FLEN)
NAN_BOXED(32256,16,FLEN)
NAN_BOXED(1,16,FLEN)
NAN_BOXED(65024,16,FLEN)
NAN_BOXED(65024,16,FLEN)
NAN_BOXED(1,16,FLEN)
NAN_BOXED(65024,16,FLEN)
NAN_BOXED(32257,16,FLEN)
NAN_BOXED(1,16,FLEN)
NAN_BOXED(65024,16,FLEN)
NAN_BOXED(65109,16,FLEN)
NAN_BOXED(1,16,FLEN)
NAN_BOXED(65024,16,FLEN)
NAN_BOXED(31745,16,FLEN)
NAN_BOXED(1,16,FLEN)
NAN_BOXED(65024,16,FLEN)
NAN_BOXED(64853,16,FLEN)
NAN_BOXED(1,16,FLEN)
NAN_BOXED(65024,16,FLEN)
NAN_BOXED(15360,16,FLEN)
NAN_BOXED(1,16,FLEN)
NAN_BOXED(65024,16,FLEN)
NAN_BOXED(48128,16,FLEN)
NAN_BOXED(1,16,FLEN)
NAN_BOXED(32257,16,FLEN)
NAN_BOXED(0,16,FLEN)
NAN_BOXED(1,16,FLEN)
NAN_BOXED(32257,16,FLEN)
NAN_BOXED(32768,16,FLEN)
NAN_BOXED(1,16,FLEN)
NAN_BOXED(32257,16,FLEN)
NAN_BOXED(1,16,FLEN)
NAN_BOXED(1,16,FLEN)
NAN_BOXED(32257,16,FLEN)
NAN_BOXED(32769,16,FLEN)
NAN_BOXED(1,16,FLEN)
NAN_BOXED(32257,16,FLEN)
NAN_BOXED(2,16,FLEN)
NAN_BOXED(1,16,FLEN)
NAN_BOXED(32257,16,FLEN)
NAN_BOXED(33790,16,FLEN)
NAN_BOXED(1,16,FLEN)
NAN_BOXED(32257,16,FLEN)
NAN_BOXED(1023,16,FLEN)
NAN_BOXED(1,16,FLEN)
NAN_BOXED(32257,16,FLEN)
NAN_BOXED(33791,16,FLEN)
NAN_BOXED(1,16,FLEN)
NAN_BOXED(32257,16,FLEN)
NAN_BOXED(1024,16,FLEN)
NAN_BOXED(1,16,FLEN)
NAN_BOXED(32257,16,FLEN)
NAN_BOXED(33792,16,FLEN)
NAN_BOXED(1,16,FLEN)
NAN_BOXED(32257,16,FLEN)
NAN_BOXED(1025,16,FLEN)
NAN_BOXED(1,16,FLEN)
NAN_BOXED(32257,16,FLEN)
NAN_BOXED(33877,16,FLEN)
NAN_BOXED(1,16,FLEN)
NAN_BOXED(32257,16,FLEN)
NAN_BOXED(31743,16,FLEN)
NAN_BOXED(1,16,FLEN)
NAN_BOXED(32257,16,FLEN)
NAN_BOXED(64511,16,FLEN)
NAN_BOXED(1,16,FLEN)
NAN_BOXED(32257,16,FLEN)
NAN_BOXED(31744,16,FLEN)
NAN_BOXED(1,16,FLEN)
NAN_BOXED(32257,16,FLEN)
NAN_BOXED(64512,16,FLEN)
NAN_BOXED(1,16,FLEN)
NAN_BOXED(32257,16,FLEN)
NAN_BOXED(32256,16,FLEN)
NAN_BOXED(1,16,FLEN)
NAN_BOXED(32257,16,FLEN)
NAN_BOXED(65024,16,FLEN)
NAN_BOXED(1,16,FLEN)
NAN_BOXED(32257,16,FLEN)
NAN_BOXED(32257,16,FLEN)
NAN_BOXED(1,16,FLEN)
NAN_BOXED(32257,16,FLEN)
NAN_BOXED(65109,16,FLEN)
NAN_BOXED(1,16,FLEN)
NAN_BOXED(32257,16,FLEN)
NAN_BOXED(31745,16,FLEN)
NAN_BOXED(1,16,FLEN)
NAN_BOXED(32257,16,FLEN)
NAN_BOXED(64853,16,FLEN)
NAN_BOXED(1,16,FLEN)
NAN_BOXED(32257,16,FLEN)
NAN_BOXED(15360,16,FLEN)
NAN_BOXED(1,16,FLEN)
NAN_BOXED(32257,16,FLEN)
NAN_BOXED(48128,16,FLEN)
NAN_BOXED(1,16,FLEN)
NAN_BOXED(65109,16,FLEN)
NAN_BOXED(0,16,FLEN)
NAN_BOXED(1,16,FLEN)
NAN_BOXED(65109,16,FLEN)
NAN_BOXED(32768,16,FLEN)
NAN_BOXED(1,16,FLEN)
NAN_BOXED(65109,16,FLEN)
NAN_BOXED(1,16,FLEN)
NAN_BOXED(1,16,FLEN)
NAN_BOXED(65109,16,FLEN)
NAN_BOXED(32769,16,FLEN)
NAN_BOXED(1,16,FLEN)
NAN_BOXED(65109,16,FLEN)
NAN_BOXED(2,16,FLEN)
NAN_BOXED(1,16,FLEN)
NAN_BOXED(65109,16,FLEN)
NAN_BOXED(33790,16,FLEN)
NAN_BOXED(1,16,FLEN)
NAN_BOXED(65109,16,FLEN)
NAN_BOXED(1023,16,FLEN)
NAN_BOXED(1,16,FLEN)
NAN_BOXED(65109,16,FLEN)
NAN_BOXED(33791,16,FLEN)
NAN_BOXED(1,16,FLEN)
NAN_BOXED(65109,16,FLEN)
NAN_BOXED(1024,16,FLEN)
NAN_BOXED(1,16,FLEN)
NAN_BOXED(65109,16,FLEN)
NAN_BOXED(33792,16,FLEN)
NAN_BOXED(1,16,FLEN)
NAN_BOXED(65109,16,FLEN)
NAN_BOXED(1025,16,FLEN)
NAN_BOXED(1,16,FLEN)
NAN_BOXED(65109,16,FLEN)
NAN_BOXED(33877,16,FLEN)
NAN_BOXED(1,16,FLEN)
NAN_BOXED(65109,16,FLEN)
NAN_BOXED(31743,16,FLEN)
NAN_BOXED(1,16,FLEN)
NAN_BOXED(65109,16,FLEN)
NAN_BOXED(64511,16,FLEN)
NAN_BOXED(1,16,FLEN)
NAN_BOXED(65109,16,FLEN)
NAN_BOXED(31744,16,FLEN)
NAN_BOXED(1,16,FLEN)
NAN_BOXED(65109,16,FLEN)
NAN_BOXED(64512,16,FLEN)
NAN_BOXED(1,16,FLEN)
NAN_BOXED(65109,16,FLEN)
NAN_BOXED(32256,16,FLEN)
NAN_BOXED(1,16,FLEN)
NAN_BOXED(65109,16,FLEN)
NAN_BOXED(65024,16,FLEN)
NAN_BOXED(1,16,FLEN)
NAN_BOXED(65109,16,FLEN)
NAN_BOXED(32257,16,FLEN)
NAN_BOXED(1,16,FLEN)
NAN_BOXED(65109,16,FLEN)
NAN_BOXED(65109,16,FLEN)
NAN_BOXED(1,16,FLEN)
NAN_BOXED(65109,16,FLEN)
NAN_BOXED(31745,16,FLEN)
NAN_BOXED(1,16,FLEN)
NAN_BOXED(65109,16,FLEN)
NAN_BOXED(64853,16,FLEN)
NAN_BOXED(1,16,FLEN)
NAN_BOXED(65109,16,FLEN)
NAN_BOXED(15360,16,FLEN)
NAN_BOXED(1,16,FLEN)
NAN_BOXED(65109,16,FLEN)
NAN_BOXED(48128,16,FLEN)
NAN_BOXED(1,16,FLEN)
NAN_BOXED(31745,16,FLEN)
NAN_BOXED(0,16,FLEN)
NAN_BOXED(1,16,FLEN)
NAN_BOXED(31745,16,FLEN)
NAN_BOXED(32768,16,FLEN)
NAN_BOXED(1,16,FLEN)
NAN_BOXED(31745,16,FLEN)
NAN_BOXED(1,16,FLEN)
NAN_BOXED(1,16,FLEN)
NAN_BOXED(31745,16,FLEN)
NAN_BOXED(32769,16,FLEN)
NAN_BOXED(1,16,FLEN)
NAN_BOXED(31745,16,FLEN)
NAN_BOXED(2,16,FLEN)
NAN_BOXED(1,16,FLEN)
NAN_BOXED(31745,16,FLEN)
NAN_BOXED(33790,16,FLEN)
NAN_BOXED(1,16,FLEN)
NAN_BOXED(31745,16,FLEN)
NAN_BOXED(1023,16,FLEN)
NAN_BOXED(1,16,FLEN)
NAN_BOXED(31745,16,FLEN)
NAN_BOXED(33791,16,FLEN)
NAN_BOXED(1,16,FLEN)
NAN_BOXED(31745,16,FLEN)
NAN_BOXED(1024,16,FLEN)
NAN_BOXED(1,16,FLEN)
NAN_BOXED(31745,16,FLEN)
NAN_BOXED(33792,16,FLEN)
NAN_BOXED(1,16,FLEN)
NAN_BOXED(31745,16,FLEN)
NAN_BOXED(1025,16,FLEN)
NAN_BOXED(1,16,FLEN)
NAN_BOXED(31745,16,FLEN)
NAN_BOXED(33877,16,FLEN)
NAN_BOXED(1,16,FLEN)
NAN_BOXED(31745,16,FLEN)
NAN_BOXED(31743,16,FLEN)
NAN_BOXED(1,16,FLEN)
NAN_BOXED(31745,16,FLEN)
NAN_BOXED(64511,16,FLEN)
NAN_BOXED(1,16,FLEN)
NAN_BOXED(31745,16,FLEN)
NAN_BOXED(31744,16,FLEN)
NAN_BOXED(1,16,FLEN)
NAN_BOXED(31745,16,FLEN)
NAN_BOXED(64512,16,FLEN)
NAN_BOXED(1,16,FLEN)
NAN_BOXED(31745,16,FLEN)
NAN_BOXED(32256,16,FLEN)
NAN_BOXED(1,16,FLEN)
NAN_BOXED(31745,16,FLEN)
NAN_BOXED(65024,16,FLEN)
NAN_BOXED(1,16,FLEN)
NAN_BOXED(31745,16,FLEN)
NAN_BOXED(32257,16,FLEN)
NAN_BOXED(1,16,FLEN)
NAN_BOXED(31745,16,FLEN)
NAN_BOXED(65109,16,FLEN)
NAN_BOXED(1,16,FLEN)
NAN_BOXED(31745,16,FLEN)
NAN_BOXED(31745,16,FLEN)
NAN_BOXED(1,16,FLEN)
NAN_BOXED(31745,16,FLEN)
NAN_BOXED(64853,16,FLEN)
NAN_BOXED(1,16,FLEN)
NAN_BOXED(31745,16,FLEN)
NAN_BOXED(15360,16,FLEN)
NAN_BOXED(1,16,FLEN)
NAN_BOXED(31745,16,FLEN)
NAN_BOXED(48128,16,FLEN)
NAN_BOXED(1,16,FLEN)
NAN_BOXED(64853,16,FLEN)
NAN_BOXED(0,16,FLEN)
NAN_BOXED(1,16,FLEN)
NAN_BOXED(64853,16,FLEN)
NAN_BOXED(32768,16,FLEN)
NAN_BOXED(1,16,FLEN)
NAN_BOXED(64853,16,FLEN)
NAN_BOXED(1,16,FLEN)
NAN_BOXED(1,16,FLEN)
NAN_BOXED(64853,16,FLEN)
NAN_BOXED(32769,16,FLEN)
NAN_BOXED(1,16,FLEN)
NAN_BOXED(64853,16,FLEN)
NAN_BOXED(2,16,FLEN)
NAN_BOXED(1,16,FLEN)
NAN_BOXED(64853,16,FLEN)
NAN_BOXED(33790,16,FLEN)
NAN_BOXED(1,16,FLEN)
NAN_BOXED(64853,16,FLEN)
NAN_BOXED(1023,16,FLEN)
NAN_BOXED(1,16,FLEN)
NAN_BOXED(64853,16,FLEN)
NAN_BOXED(33791,16,FLEN)
NAN_BOXED(1,16,FLEN)
NAN_BOXED(64853,16,FLEN)
NAN_BOXED(1024,16,FLEN)
NAN_BOXED(1,16,FLEN)
NAN_BOXED(64853,16,FLEN)
NAN_BOXED(33792,16,FLEN)
NAN_BOXED(1,16,FLEN)
NAN_BOXED(64853,16,FLEN)
NAN_BOXED(1025,16,FLEN)
NAN_BOXED(1,16,FLEN)
NAN_BOXED(64853,16,FLEN)
NAN_BOXED(33877,16,FLEN)
NAN_BOXED(1,16,FLEN)
NAN_BOXED(64853,16,FLEN)
NAN_BOXED(31743,16,FLEN)
NAN_BOXED(1,16,FLEN)
NAN_BOXED(64853,16,FLEN)
NAN_BOXED(64511,16,FLEN)
NAN_BOXED(1,16,FLEN)
NAN_BOXED(64853,16,FLEN)
NAN_BOXED(31744,16,FLEN)
NAN_BOXED(1,16,FLEN)
NAN_BOXED(64853,16,FLEN)
NAN_BOXED(64512,16,FLEN)
NAN_BOXED(1,16,FLEN)
NAN_BOXED(64853,16,FLEN)
NAN_BOXED(32256,16,FLEN)
NAN_BOXED(1,16,FLEN)
NAN_BOXED(64853,16,FLEN)
NAN_BOXED(65024,16,FLEN)
NAN_BOXED(1,16,FLEN)
NAN_BOXED(64853,16,FLEN)
NAN_BOXED(32257,16,FLEN)
NAN_BOXED(1,16,FLEN)
NAN_BOXED(64853,16,FLEN)
NAN_BOXED(65109,16,FLEN)
NAN_BOXED(1,16,FLEN)
NAN_BOXED(64853,16,FLEN)
NAN_BOXED(31745,16,FLEN)
NAN_BOXED(1,16,FLEN)
NAN_BOXED(64853,16,FLEN)
NAN_BOXED(64853,16,FLEN)
NAN_BOXED(1,16,FLEN)
NAN_BOXED(64853,16,FLEN)
NAN_BOXED(15360,16,FLEN)
NAN_BOXED(1,16,FLEN)
NAN_BOXED(64853,16,FLEN)
NAN_BOXED(48128,16,FLEN)
NAN_BOXED(1,16,FLEN)
NAN_BOXED(15360,16,FLEN)
NAN_BOXED(0,16,FLEN)
NAN_BOXED(1,16,FLEN)
NAN_BOXED(15360,16,FLEN)
NAN_BOXED(32768,16,FLEN)
NAN_BOXED(1,16,FLEN)
NAN_BOXED(15360,16,FLEN)
NAN_BOXED(1,16,FLEN)
NAN_BOXED(1,16,FLEN)
NAN_BOXED(15360,16,FLEN)
NAN_BOXED(32769,16,FLEN)
NAN_BOXED(1,16,FLEN)
NAN_BOXED(15360,16,FLEN)
NAN_BOXED(2,16,FLEN)
NAN_BOXED(1,16,FLEN)
NAN_BOXED(15360,16,FLEN)
NAN_BOXED(33790,16,FLEN)
NAN_BOXED(1,16,FLEN)
NAN_BOXED(15360,16,FLEN)
NAN_BOXED(1023,16,FLEN)
NAN_BOXED(1,16,FLEN)
NAN_BOXED(15360,16,FLEN)
NAN_BOXED(33791,16,FLEN)
NAN_BOXED(1,16,FLEN)
NAN_BOXED(15360,16,FLEN)
NAN_BOXED(1024,16,FLEN)
NAN_BOXED(1,16,FLEN)
NAN_BOXED(15360,16,FLEN)
NAN_BOXED(33792,16,FLEN)
NAN_BOXED(1,16,FLEN)
NAN_BOXED(15360,16,FLEN)
NAN_BOXED(1025,16,FLEN)
NAN_BOXED(1,16,FLEN)
NAN_BOXED(15360,16,FLEN)
NAN_BOXED(33877,16,FLEN)
NAN_BOXED(1,16,FLEN)
NAN_BOXED(15360,16,FLEN)
NAN_BOXED(31743,16,FLEN)
NAN_BOXED(1,16,FLEN)
NAN_BOXED(15360,16,FLEN)
NAN_BOXED(64511,16,FLEN)
NAN_BOXED(1,16,FLEN)
NAN_BOXED(15360,16,FLEN)
NAN_BOXED(31744,16,FLEN)
NAN_BOXED(1,16,FLEN)
NAN_BOXED(15360,16,FLEN)
NAN_BOXED(64512,16,FLEN)
NAN_BOXED(1,16,FLEN)
NAN_BOXED(15360,16,FLEN)
NAN_BOXED(32256,16,FLEN)
NAN_BOXED(1,16,FLEN)
NAN_BOXED(15360,16,FLEN)
NAN_BOXED(65024,16,FLEN)
NAN_BOXED(1,16,FLEN)
NAN_BOXED(15360,16,FLEN)
NAN_BOXED(32257,16,FLEN)
NAN_BOXED(1,16,FLEN)
NAN_BOXED(15360,16,FLEN)
NAN_BOXED(65109,16,FLEN)
NAN_BOXED(1,16,FLEN)
NAN_BOXED(15360,16,FLEN)
NAN_BOXED(31745,16,FLEN)
NAN_BOXED(1,16,FLEN)
NAN_BOXED(15360,16,FLEN)
NAN_BOXED(64853,16,FLEN)
NAN_BOXED(1,16,FLEN)
NAN_BOXED(15360,16,FLEN)
NAN_BOXED(15360,16,FLEN)
NAN_BOXED(1,16,FLEN)
NAN_BOXED(15360,16,FLEN)
NAN_BOXED(48128,16,FLEN)
NAN_BOXED(1,16,FLEN)
NAN_BOXED(48128,16,FLEN)
NAN_BOXED(0,16,FLEN)
NAN_BOXED(1,16,FLEN)
NAN_BOXED(48128,16,FLEN)
NAN_BOXED(32768,16,FLEN)
NAN_BOXED(1,16,FLEN)
NAN_BOXED(48128,16,FLEN)
NAN_BOXED(1,16,FLEN)
NAN_BOXED(1,16,FLEN)
NAN_BOXED(48128,16,FLEN)
NAN_BOXED(32769,16,FLEN)
NAN_BOXED(1,16,FLEN)
NAN_BOXED(48128,16,FLEN)
NAN_BOXED(2,16,FLEN)
NAN_BOXED(1,16,FLEN)
NAN_BOXED(48128,16,FLEN)
NAN_BOXED(33790,16,FLEN)
NAN_BOXED(1,16,FLEN)
NAN_BOXED(48128,16,FLEN)
NAN_BOXED(1023,16,FLEN)
NAN_BOXED(1,16,FLEN)
NAN_BOXED(48128,16,FLEN)
NAN_BOXED(33791,16,FLEN)
NAN_BOXED(1,16,FLEN)
NAN_BOXED(48128,16,FLEN)
NAN_BOXED(1024,16,FLEN)
NAN_BOXED(1,16,FLEN)
NAN_BOXED(48128,16,FLEN)
NAN_BOXED(33792,16,FLEN)
NAN_BOXED(1,16,FLEN)
NAN_BOXED(48128,16,FLEN)
NAN_BOXED(1025,16,FLEN)
NAN_BOXED(1,16,FLEN)
NAN_BOXED(48128,16,FLEN)
NAN_BOXED(33877,16,FLEN)
NAN_BOXED(1,16,FLEN)
NAN_BOXED(48128,16,FLEN)
NAN_BOXED(31743,16,FLEN)
NAN_BOXED(1,16,FLEN)
NAN_BOXED(48128,16,FLEN)
NAN_BOXED(64511,16,FLEN)
NAN_BOXED(1,16,FLEN)
NAN_BOXED(48128,16,FLEN)
NAN_BOXED(31744,16,FLEN)
NAN_BOXED(1,16,FLEN)
NAN_BOXED(48128,16,FLEN)
NAN_BOXED(64512,16,FLEN)
NAN_BOXED(1,16,FLEN)
NAN_BOXED(48128,16,FLEN)
NAN_BOXED(32256,16,FLEN)
NAN_BOXED(1,16,FLEN)
NAN_BOXED(48128,16,FLEN)
NAN_BOXED(65024,16,FLEN)
NAN_BOXED(1,16,FLEN)
NAN_BOXED(48128,16,FLEN)
NAN_BOXED(32257,16,FLEN)
NAN_BOXED(1,16,FLEN)
NAN_BOXED(48128,16,FLEN)
NAN_BOXED(65109,16,FLEN)
NAN_BOXED(1,16,FLEN)
NAN_BOXED(48128,16,FLEN)
NAN_BOXED(31745,16,FLEN)
NAN_BOXED(1,16,FLEN)
NAN_BOXED(48128,16,FLEN)
NAN_BOXED(64853,16,FLEN)
NAN_BOXED(1,16,FLEN)
NAN_BOXED(48128,16,FLEN)
NAN_BOXED(15360,16,FLEN)
NAN_BOXED(1,16,FLEN)
NAN_BOXED(48128,16,FLEN)
NAN_BOXED(48128,16,FLEN)
NAN_BOXED(32769,16,FLEN)
NAN_BOXED(0,16,FLEN)
NAN_BOXED(0,16,FLEN)
NAN_BOXED(32769,16,FLEN)
NAN_BOXED(0,16,FLEN)
NAN_BOXED(32768,16,FLEN)
NAN_BOXED(32769,16,FLEN)
NAN_BOXED(0,16,FLEN)
NAN_BOXED(1,16,FLEN)
NAN_BOXED(32769,16,FLEN)
NAN_BOXED(0,16,FLEN)
NAN_BOXED(32769,16,FLEN)
NAN_BOXED(32769,16,FLEN)
NAN_BOXED(0,16,FLEN)
NAN_BOXED(2,16,FLEN)
NAN_BOXED(32769,16,FLEN)
NAN_BOXED(0,16,FLEN)
NAN_BOXED(33790,16,FLEN)
NAN_BOXED(32769,16,FLEN)
NAN_BOXED(0,16,FLEN)
NAN_BOXED(1023,16,FLEN)
NAN_BOXED(32769,16,FLEN)
NAN_BOXED(0,16,FLEN)
NAN_BOXED(33791,16,FLEN)
NAN_BOXED(32769,16,FLEN)
NAN_BOXED(0,16,FLEN)
NAN_BOXED(1024,16,FLEN)
NAN_BOXED(32769,16,FLEN)
NAN_BOXED(0,16,FLEN)
NAN_BOXED(33792,16,FLEN)
NAN_BOXED(32769,16,FLEN)
NAN_BOXED(0,16,FLEN)
NAN_BOXED(1025,16,FLEN)
NAN_BOXED(32769,16,FLEN)
NAN_BOXED(0,16,FLEN)
NAN_BOXED(33877,16,FLEN)
NAN_BOXED(32769,16,FLEN)
NAN_BOXED(0,16,FLEN)
NAN_BOXED(31743,16,FLEN)
NAN_BOXED(32769,16,FLEN)
NAN_BOXED(0,16,FLEN)
NAN_BOXED(64511,16,FLEN)
NAN_BOXED(32769,16,FLEN)
NAN_BOXED(0,16,FLEN)
NAN_BOXED(31744,16,FLEN)
NAN_BOXED(32769,16,FLEN)
NAN_BOXED(0,16,FLEN)
NAN_BOXED(64512,16,FLEN)
NAN_BOXED(32769,16,FLEN)
NAN_BOXED(0,16,FLEN)
NAN_BOXED(32256,16,FLEN)
NAN_BOXED(32769,16,FLEN)
NAN_BOXED(0,16,FLEN)
NAN_BOXED(65024,16,FLEN)
NAN_BOXED(32769,16,FLEN)
NAN_BOXED(0,16,FLEN)
NAN_BOXED(32257,16,FLEN)
NAN_BOXED(32769,16,FLEN)
NAN_BOXED(0,16,FLEN)
NAN_BOXED(65109,16,FLEN)
NAN_BOXED(32769,16,FLEN)
NAN_BOXED(0,16,FLEN)
NAN_BOXED(31745,16,FLEN)
NAN_BOXED(32769,16,FLEN)
NAN_BOXED(0,16,FLEN)
NAN_BOXED(64853,16,FLEN)
NAN_BOXED(32769,16,FLEN)
NAN_BOXED(0,16,FLEN)
NAN_BOXED(15360,16,FLEN)
NAN_BOXED(32769,16,FLEN)
NAN_BOXED(0,16,FLEN)
NAN_BOXED(48128,16,FLEN)
NAN_BOXED(32769,16,FLEN)
NAN_BOXED(32768,16,FLEN)
NAN_BOXED(0,16,FLEN)
NAN_BOXED(32769,16,FLEN)
NAN_BOXED(32768,16,FLEN)
NAN_BOXED(32768,16,FLEN)
NAN_BOXED(32769,16,FLEN)
NAN_BOXED(32768,16,FLEN)
NAN_BOXED(1,16,FLEN)
NAN_BOXED(32769,16,FLEN)
NAN_BOXED(32768,16,FLEN)
NAN_BOXED(32769,16,FLEN)
NAN_BOXED(32769,16,FLEN)
NAN_BOXED(32768,16,FLEN)
NAN_BOXED(2,16,FLEN)
NAN_BOXED(32769,16,FLEN)
NAN_BOXED(32768,16,FLEN)
NAN_BOXED(33790,16,FLEN)
NAN_BOXED(32769,16,FLEN)
NAN_BOXED(32768,16,FLEN)
NAN_BOXED(1023,16,FLEN)
NAN_BOXED(32769,16,FLEN)
NAN_BOXED(32768,16,FLEN)
NAN_BOXED(33791,16,FLEN)
NAN_BOXED(32769,16,FLEN)
NAN_BOXED(32768,16,FLEN)
NAN_BOXED(1024,16,FLEN)
NAN_BOXED(32769,16,FLEN)
NAN_BOXED(32768,16,FLEN)
NAN_BOXED(33792,16,FLEN)
NAN_BOXED(32769,16,FLEN)
NAN_BOXED(32768,16,FLEN)
NAN_BOXED(1025,16,FLEN)
NAN_BOXED(32769,16,FLEN)
NAN_BOXED(32768,16,FLEN)
NAN_BOXED(33877,16,FLEN)
NAN_BOXED(32769,16,FLEN)
NAN_BOXED(32768,16,FLEN)
NAN_BOXED(31743,16,FLEN)
NAN_BOXED(32769,16,FLEN)
NAN_BOXED(32768,16,FLEN)
NAN_BOXED(64511,16,FLEN)
NAN_BOXED(32769,16,FLEN)
NAN_BOXED(32768,16,FLEN)
NAN_BOXED(31744,16,FLEN)
NAN_BOXED(32769,16,FLEN)
NAN_BOXED(32768,16,FLEN)
NAN_BOXED(64512,16,FLEN)
NAN_BOXED(32769,16,FLEN)
NAN_BOXED(32768,16,FLEN)
NAN_BOXED(32256,16,FLEN)
NAN_BOXED(32769,16,FLEN)
NAN_BOXED(32768,16,FLEN)
NAN_BOXED(65024,16,FLEN)
NAN_BOXED(32769,16,FLEN)
NAN_BOXED(32768,16,FLEN)
NAN_BOXED(32257,16,FLEN)
NAN_BOXED(32769,16,FLEN)
NAN_BOXED(32768,16,FLEN)
NAN_BOXED(65109,16,FLEN)
NAN_BOXED(32769,16,FLEN)
NAN_BOXED(32768,16,FLEN)
NAN_BOXED(31745,16,FLEN)
NAN_BOXED(32769,16,FLEN)
NAN_BOXED(32768,16,FLEN)
NAN_BOXED(64853,16,FLEN)
NAN_BOXED(32769,16,FLEN)
NAN_BOXED(32768,16,FLEN)
NAN_BOXED(15360,16,FLEN)
NAN_BOXED(32769,16,FLEN)
NAN_BOXED(32768,16,FLEN)
NAN_BOXED(48128,16,FLEN)
NAN_BOXED(32769,16,FLEN)
NAN_BOXED(1,16,FLEN)
NAN_BOXED(0,16,FLEN)
NAN_BOXED(32769,16,FLEN)
NAN_BOXED(1,16,FLEN)
NAN_BOXED(32768,16,FLEN)
NAN_BOXED(32769,16,FLEN)
NAN_BOXED(1,16,FLEN)
NAN_BOXED(1,16,FLEN)
NAN_BOXED(32769,16,FLEN)
NAN_BOXED(1,16,FLEN)
NAN_BOXED(32769,16,FLEN)
NAN_BOXED(32769,16,FLEN)
NAN_BOXED(1,16,FLEN)
NAN_BOXED(2,16,FLEN)
NAN_BOXED(32769,16,FLEN)
NAN_BOXED(1,16,FLEN)
NAN_BOXED(33790,16,FLEN)
NAN_BOXED(32769,16,FLEN)
NAN_BOXED(1,16,FLEN)
NAN_BOXED(1023,16,FLEN)
NAN_BOXED(32769,16,FLEN)
NAN_BOXED(1,16,FLEN)
NAN_BOXED(33791,16,FLEN)
NAN_BOXED(32769,16,FLEN)
NAN_BOXED(1,16,FLEN)
NAN_BOXED(1024,16,FLEN)
NAN_BOXED(32769,16,FLEN)
NAN_BOXED(1,16,FLEN)
NAN_BOXED(33792,16,FLEN)
NAN_BOXED(32769,16,FLEN)
NAN_BOXED(1,16,FLEN)
NAN_BOXED(1025,16,FLEN)
NAN_BOXED(32769,16,FLEN)
NAN_BOXED(1,16,FLEN)
NAN_BOXED(33877,16,FLEN)
NAN_BOXED(32769,16,FLEN)
NAN_BOXED(1,16,FLEN)
NAN_BOXED(31743,16,FLEN)
NAN_BOXED(32769,16,FLEN)
NAN_BOXED(1,16,FLEN)
NAN_BOXED(64511,16,FLEN)
NAN_BOXED(32769,16,FLEN)
NAN_BOXED(1,16,FLEN)
NAN_BOXED(31744,16,FLEN)
NAN_BOXED(32769,16,FLEN)
NAN_BOXED(1,16,FLEN)
NAN_BOXED(64512,16,FLEN)
NAN_BOXED(32769,16,FLEN)
NAN_BOXED(1,16,FLEN)
NAN_BOXED(32256,16,FLEN)
NAN_BOXED(32769,16,FLEN)
NAN_BOXED(1,16,FLEN)
NAN_BOXED(65024,16,FLEN)
NAN_BOXED(32769,16,FLEN)
NAN_BOXED(1,16,FLEN)
NAN_BOXED(32257,16,FLEN)
NAN_BOXED(32769,16,FLEN)
NAN_BOXED(1,16,FLEN)
NAN_BOXED(65109,16,FLEN)
NAN_BOXED(32769,16,FLEN)
NAN_BOXED(1,16,FLEN)
NAN_BOXED(31745,16,FLEN)
NAN_BOXED(32769,16,FLEN)
NAN_BOXED(1,16,FLEN)
NAN_BOXED(64853,16,FLEN)
NAN_BOXED(32769,16,FLEN)
NAN_BOXED(1,16,FLEN)
NAN_BOXED(15360,16,FLEN)
NAN_BOXED(32769,16,FLEN)
NAN_BOXED(1,16,FLEN)
NAN_BOXED(48128,16,FLEN)
NAN_BOXED(32769,16,FLEN)
NAN_BOXED(32769,16,FLEN)
NAN_BOXED(0,16,FLEN)
NAN_BOXED(32769,16,FLEN)
NAN_BOXED(32769,16,FLEN)
NAN_BOXED(32768,16,FLEN)
NAN_BOXED(32769,16,FLEN)
NAN_BOXED(32769,16,FLEN)
NAN_BOXED(1,16,FLEN)
NAN_BOXED(32769,16,FLEN)
NAN_BOXED(32769,16,FLEN)
NAN_BOXED(32769,16,FLEN)
NAN_BOXED(32769,16,FLEN)
NAN_BOXED(32769,16,FLEN)
NAN_BOXED(2,16,FLEN)
NAN_BOXED(32769,16,FLEN)
NAN_BOXED(32769,16,FLEN)
NAN_BOXED(33790,16,FLEN)
NAN_BOXED(32769,16,FLEN)
NAN_BOXED(32769,16,FLEN)
NAN_BOXED(1023,16,FLEN)
NAN_BOXED(32769,16,FLEN)
NAN_BOXED(32769,16,FLEN)
NAN_BOXED(33791,16,FLEN)
NAN_BOXED(32769,16,FLEN)
NAN_BOXED(32769,16,FLEN)
NAN_BOXED(1024,16,FLEN)
NAN_BOXED(32769,16,FLEN)
NAN_BOXED(32769,16,FLEN)
NAN_BOXED(33792,16,FLEN)
NAN_BOXED(32769,16,FLEN)
NAN_BOXED(32769,16,FLEN)
NAN_BOXED(1025,16,FLEN)
NAN_BOXED(32769,16,FLEN)
NAN_BOXED(32769,16,FLEN)
NAN_BOXED(33877,16,FLEN)
NAN_BOXED(32769,16,FLEN)
NAN_BOXED(32769,16,FLEN)
NAN_BOXED(31743,16,FLEN)
NAN_BOXED(32769,16,FLEN)
NAN_BOXED(32769,16,FLEN)
NAN_BOXED(64511,16,FLEN)
NAN_BOXED(32769,16,FLEN)
NAN_BOXED(32769,16,FLEN)
NAN_BOXED(31744,16,FLEN)
NAN_BOXED(32769,16,FLEN)
NAN_BOXED(32769,16,FLEN)
NAN_BOXED(64512,16,FLEN)
NAN_BOXED(32769,16,FLEN)
NAN_BOXED(32769,16,FLEN)
NAN_BOXED(32256,16,FLEN)
NAN_BOXED(32769,16,FLEN)
NAN_BOXED(32769,16,FLEN)
NAN_BOXED(65024,16,FLEN)
NAN_BOXED(32769,16,FLEN)
NAN_BOXED(32769,16,FLEN)
NAN_BOXED(32257,16,FLEN)
NAN_BOXED(32769,16,FLEN)
NAN_BOXED(32769,16,FLEN)
NAN_BOXED(65109,16,FLEN)
NAN_BOXED(32769,16,FLEN)
NAN_BOXED(32769,16,FLEN)
NAN_BOXED(31745,16,FLEN)
NAN_BOXED(32769,16,FLEN)
NAN_BOXED(32769,16,FLEN)
NAN_BOXED(64853,16,FLEN)
NAN_BOXED(32769,16,FLEN)
NAN_BOXED(32769,16,FLEN)
NAN_BOXED(15360,16,FLEN)
NAN_BOXED(32769,16,FLEN)
NAN_BOXED(32769,16,FLEN)
NAN_BOXED(48128,16,FLEN)
NAN_BOXED(32769,16,FLEN)
NAN_BOXED(2,16,FLEN)
NAN_BOXED(0,16,FLEN)
NAN_BOXED(32769,16,FLEN)
NAN_BOXED(2,16,FLEN)
NAN_BOXED(32768,16,FLEN)
NAN_BOXED(32769,16,FLEN)
NAN_BOXED(2,16,FLEN)
NAN_BOXED(1,16,FLEN)
NAN_BOXED(32769,16,FLEN)
NAN_BOXED(2,16,FLEN)
NAN_BOXED(32769,16,FLEN)
NAN_BOXED(32769,16,FLEN)
NAN_BOXED(2,16,FLEN)
NAN_BOXED(2,16,FLEN)
NAN_BOXED(32769,16,FLEN)
NAN_BOXED(2,16,FLEN)
NAN_BOXED(33790,16,FLEN)
NAN_BOXED(32769,16,FLEN)
NAN_BOXED(2,16,FLEN)
NAN_BOXED(1023,16,FLEN)
NAN_BOXED(32769,16,FLEN)
NAN_BOXED(2,16,FLEN)
NAN_BOXED(33791,16,FLEN)
NAN_BOXED(32769,16,FLEN)
NAN_BOXED(2,16,FLEN)
NAN_BOXED(1024,16,FLEN)
NAN_BOXED(32769,16,FLEN)
NAN_BOXED(2,16,FLEN)
NAN_BOXED(33792,16,FLEN)
NAN_BOXED(32769,16,FLEN)
NAN_BOXED(2,16,FLEN)
NAN_BOXED(1025,16,FLEN)
NAN_BOXED(32769,16,FLEN)
NAN_BOXED(2,16,FLEN)
NAN_BOXED(33877,16,FLEN)
NAN_BOXED(32769,16,FLEN)
NAN_BOXED(2,16,FLEN)
NAN_BOXED(31743,16,FLEN)
NAN_BOXED(32769,16,FLEN)
NAN_BOXED(2,16,FLEN)
NAN_BOXED(64511,16,FLEN)
NAN_BOXED(32769,16,FLEN)
NAN_BOXED(2,16,FLEN)
NAN_BOXED(31744,16,FLEN)
NAN_BOXED(32769,16,FLEN)
NAN_BOXED(2,16,FLEN)
NAN_BOXED(64512,16,FLEN)
NAN_BOXED(32769,16,FLEN)
NAN_BOXED(2,16,FLEN)
NAN_BOXED(32256,16,FLEN)
NAN_BOXED(32769,16,FLEN)
NAN_BOXED(2,16,FLEN)
NAN_BOXED(65024,16,FLEN)
NAN_BOXED(32769,16,FLEN)
NAN_BOXED(2,16,FLEN)
NAN_BOXED(32257,16,FLEN)
NAN_BOXED(32769,16,FLEN)
NAN_BOXED(2,16,FLEN)
NAN_BOXED(65109,16,FLEN)
NAN_BOXED(32769,16,FLEN)
NAN_BOXED(2,16,FLEN)
NAN_BOXED(31745,16,FLEN)
NAN_BOXED(32769,16,FLEN)
NAN_BOXED(2,16,FLEN)
NAN_BOXED(64853,16,FLEN)
NAN_BOXED(32769,16,FLEN)
NAN_BOXED(2,16,FLEN)
NAN_BOXED(15360,16,FLEN)
NAN_BOXED(32769,16,FLEN)
NAN_BOXED(2,16,FLEN)
NAN_BOXED(48128,16,FLEN)
NAN_BOXED(32769,16,FLEN)
NAN_BOXED(33790,16,FLEN)
NAN_BOXED(0,16,FLEN)
NAN_BOXED(32769,16,FLEN)
NAN_BOXED(33790,16,FLEN)
NAN_BOXED(32768,16,FLEN)
NAN_BOXED(32769,16,FLEN)
NAN_BOXED(33790,16,FLEN)
NAN_BOXED(1,16,FLEN)
NAN_BOXED(32769,16,FLEN)
NAN_BOXED(33790,16,FLEN)
NAN_BOXED(32769,16,FLEN)
NAN_BOXED(32769,16,FLEN)
NAN_BOXED(33790,16,FLEN)
NAN_BOXED(2,16,FLEN)
NAN_BOXED(32769,16,FLEN)
NAN_BOXED(33790,16,FLEN)
NAN_BOXED(33790,16,FLEN)
NAN_BOXED(32769,16,FLEN)
NAN_BOXED(33790,16,FLEN)
NAN_BOXED(1023,16,FLEN)
NAN_BOXED(32769,16,FLEN)
NAN_BOXED(33790,16,FLEN)
NAN_BOXED(33791,16,FLEN)
NAN_BOXED(32769,16,FLEN)
NAN_BOXED(33790,16,FLEN)
NAN_BOXED(1024,16,FLEN)
NAN_BOXED(32769,16,FLEN)
NAN_BOXED(33790,16,FLEN)
NAN_BOXED(33792,16,FLEN)
NAN_BOXED(32769,16,FLEN)
NAN_BOXED(33790,16,FLEN)
NAN_BOXED(1025,16,FLEN)
NAN_BOXED(32769,16,FLEN)
NAN_BOXED(33790,16,FLEN)
NAN_BOXED(33877,16,FLEN)
NAN_BOXED(32769,16,FLEN)
NAN_BOXED(33790,16,FLEN)
NAN_BOXED(31743,16,FLEN)
NAN_BOXED(32769,16,FLEN)
NAN_BOXED(33790,16,FLEN)
NAN_BOXED(64511,16,FLEN)
NAN_BOXED(32769,16,FLEN)
NAN_BOXED(33790,16,FLEN)
NAN_BOXED(31744,16,FLEN)
NAN_BOXED(32769,16,FLEN)
NAN_BOXED(33790,16,FLEN)
NAN_BOXED(64512,16,FLEN)
NAN_BOXED(32769,16,FLEN)
NAN_BOXED(33790,16,FLEN)
NAN_BOXED(32256,16,FLEN)
NAN_BOXED(32769,16,FLEN)
NAN_BOXED(33790,16,FLEN)
NAN_BOXED(65024,16,FLEN)
NAN_BOXED(32769,16,FLEN)
NAN_BOXED(33790,16,FLEN)
NAN_BOXED(32257,16,FLEN)
NAN_BOXED(32769,16,FLEN)
NAN_BOXED(33790,16,FLEN)
NAN_BOXED(65109,16,FLEN)
NAN_BOXED(32769,16,FLEN)
NAN_BOXED(33790,16,FLEN)
NAN_BOXED(31745,16,FLEN)
NAN_BOXED(32769,16,FLEN)
NAN_BOXED(33790,16,FLEN)
NAN_BOXED(64853,16,FLEN)
NAN_BOXED(32769,16,FLEN)
NAN_BOXED(33790,16,FLEN)
NAN_BOXED(15360,16,FLEN)
NAN_BOXED(32769,16,FLEN)
NAN_BOXED(33790,16,FLEN)
NAN_BOXED(48128,16,FLEN)
NAN_BOXED(32769,16,FLEN)
NAN_BOXED(1023,16,FLEN)
NAN_BOXED(0,16,FLEN)
NAN_BOXED(32769,16,FLEN)
NAN_BOXED(1023,16,FLEN)
NAN_BOXED(32768,16,FLEN)
NAN_BOXED(32769,16,FLEN)
NAN_BOXED(1023,16,FLEN)
NAN_BOXED(1,16,FLEN)
NAN_BOXED(32769,16,FLEN)
NAN_BOXED(1023,16,FLEN)
NAN_BOXED(32769,16,FLEN)
NAN_BOXED(32769,16,FLEN)
NAN_BOXED(1023,16,FLEN)
NAN_BOXED(2,16,FLEN)
NAN_BOXED(32769,16,FLEN)
NAN_BOXED(1023,16,FLEN)
NAN_BOXED(33790,16,FLEN)
NAN_BOXED(32769,16,FLEN)
NAN_BOXED(1023,16,FLEN)
NAN_BOXED(1023,16,FLEN)
NAN_BOXED(32769,16,FLEN)
NAN_BOXED(1023,16,FLEN)
NAN_BOXED(33791,16,FLEN)
NAN_BOXED(32769,16,FLEN)
NAN_BOXED(1023,16,FLEN)
NAN_BOXED(1024,16,FLEN)
NAN_BOXED(32769,16,FLEN)
NAN_BOXED(1023,16,FLEN)
NAN_BOXED(33792,16,FLEN)
NAN_BOXED(32769,16,FLEN)
NAN_BOXED(1023,16,FLEN)
NAN_BOXED(1025,16,FLEN)
NAN_BOXED(32769,16,FLEN)
NAN_BOXED(1023,16,FLEN)
NAN_BOXED(33877,16,FLEN)
NAN_BOXED(32769,16,FLEN)
NAN_BOXED(1023,16,FLEN)
NAN_BOXED(31743,16,FLEN)
NAN_BOXED(32769,16,FLEN)
NAN_BOXED(1023,16,FLEN)
NAN_BOXED(64511,16,FLEN)
NAN_BOXED(32769,16,FLEN)
NAN_BOXED(1023,16,FLEN)
NAN_BOXED(31744,16,FLEN)
NAN_BOXED(32769,16,FLEN)
NAN_BOXED(1023,16,FLEN)
NAN_BOXED(64512,16,FLEN)
NAN_BOXED(32769,16,FLEN)
NAN_BOXED(1023,16,FLEN)
NAN_BOXED(32256,16,FLEN)
NAN_BOXED(32769,16,FLEN)
NAN_BOXED(1023,16,FLEN)
NAN_BOXED(65024,16,FLEN)
NAN_BOXED(32769,16,FLEN)
NAN_BOXED(1023,16,FLEN)
NAN_BOXED(32257,16,FLEN)
NAN_BOXED(32769,16,FLEN)
NAN_BOXED(1023,16,FLEN)
NAN_BOXED(65109,16,FLEN)
NAN_BOXED(32769,16,FLEN)
NAN_BOXED(1023,16,FLEN)
NAN_BOXED(31745,16,FLEN)
NAN_BOXED(32769,16,FLEN)
NAN_BOXED(1023,16,FLEN)
NAN_BOXED(64853,16,FLEN)
NAN_BOXED(32769,16,FLEN)
NAN_BOXED(1023,16,FLEN)
NAN_BOXED(15360,16,FLEN)
NAN_BOXED(32769,16,FLEN)
NAN_BOXED(1023,16,FLEN)
NAN_BOXED(48128,16,FLEN)
NAN_BOXED(32769,16,FLEN)
NAN_BOXED(33791,16,FLEN)
NAN_BOXED(0,16,FLEN)
NAN_BOXED(32769,16,FLEN)
NAN_BOXED(33791,16,FLEN)
NAN_BOXED(32768,16,FLEN)
NAN_BOXED(32769,16,FLEN)
NAN_BOXED(33791,16,FLEN)
NAN_BOXED(1,16,FLEN)
NAN_BOXED(32769,16,FLEN)
NAN_BOXED(33791,16,FLEN)
NAN_BOXED(32769,16,FLEN)
NAN_BOXED(32769,16,FLEN)
NAN_BOXED(33791,16,FLEN)
NAN_BOXED(2,16,FLEN)
NAN_BOXED(32769,16,FLEN)
NAN_BOXED(33791,16,FLEN)
NAN_BOXED(33790,16,FLEN)
NAN_BOXED(32769,16,FLEN)
NAN_BOXED(33791,16,FLEN)
NAN_BOXED(1023,16,FLEN)
NAN_BOXED(32769,16,FLEN)
NAN_BOXED(33791,16,FLEN)
NAN_BOXED(33791,16,FLEN)
NAN_BOXED(32769,16,FLEN)
NAN_BOXED(33791,16,FLEN)
NAN_BOXED(1024,16,FLEN)
NAN_BOXED(32769,16,FLEN)
NAN_BOXED(33791,16,FLEN)
NAN_BOXED(33792,16,FLEN)
NAN_BOXED(32769,16,FLEN)
NAN_BOXED(33791,16,FLEN)
NAN_BOXED(1025,16,FLEN)
NAN_BOXED(32769,16,FLEN)
NAN_BOXED(33791,16,FLEN)
NAN_BOXED(33877,16,FLEN)
NAN_BOXED(32769,16,FLEN)
NAN_BOXED(33791,16,FLEN)
NAN_BOXED(31743,16,FLEN)
NAN_BOXED(32769,16,FLEN)
NAN_BOXED(33791,16,FLEN)
NAN_BOXED(64511,16,FLEN)
NAN_BOXED(32769,16,FLEN)
NAN_BOXED(33791,16,FLEN)
NAN_BOXED(31744,16,FLEN)
NAN_BOXED(32769,16,FLEN)
NAN_BOXED(33791,16,FLEN)
NAN_BOXED(64512,16,FLEN)
NAN_BOXED(32769,16,FLEN)
NAN_BOXED(33791,16,FLEN)
NAN_BOXED(32256,16,FLEN)
NAN_BOXED(32769,16,FLEN)
NAN_BOXED(33791,16,FLEN)
NAN_BOXED(65024,16,FLEN)
NAN_BOXED(32769,16,FLEN)
NAN_BOXED(33791,16,FLEN)
NAN_BOXED(32257,16,FLEN)
NAN_BOXED(32769,16,FLEN)
NAN_BOXED(33791,16,FLEN)
NAN_BOXED(65109,16,FLEN)
NAN_BOXED(32769,16,FLEN)
NAN_BOXED(33791,16,FLEN)
NAN_BOXED(31745,16,FLEN)
NAN_BOXED(32769,16,FLEN)
NAN_BOXED(33791,16,FLEN)
NAN_BOXED(64853,16,FLEN)
NAN_BOXED(32769,16,FLEN)
NAN_BOXED(33791,16,FLEN)
NAN_BOXED(15360,16,FLEN)
NAN_BOXED(32769,16,FLEN)
NAN_BOXED(33791,16,FLEN)
NAN_BOXED(48128,16,FLEN)
NAN_BOXED(32769,16,FLEN)
NAN_BOXED(1024,16,FLEN)
NAN_BOXED(0,16,FLEN)
NAN_BOXED(32769,16,FLEN)
NAN_BOXED(1024,16,FLEN)
NAN_BOXED(32768,16,FLEN)
NAN_BOXED(32769,16,FLEN)
NAN_BOXED(1024,16,FLEN)
NAN_BOXED(1,16,FLEN)
NAN_BOXED(32769,16,FLEN)
NAN_BOXED(1024,16,FLEN)
NAN_BOXED(32769,16,FLEN)
NAN_BOXED(32769,16,FLEN)
NAN_BOXED(1024,16,FLEN)
NAN_BOXED(2,16,FLEN)
NAN_BOXED(32769,16,FLEN)
NAN_BOXED(1024,16,FLEN)
NAN_BOXED(33790,16,FLEN)
NAN_BOXED(32769,16,FLEN)
NAN_BOXED(1024,16,FLEN)
NAN_BOXED(1023,16,FLEN)
NAN_BOXED(32769,16,FLEN)
NAN_BOXED(1024,16,FLEN)
NAN_BOXED(33791,16,FLEN)
NAN_BOXED(32769,16,FLEN)
NAN_BOXED(1024,16,FLEN)
NAN_BOXED(1024,16,FLEN)
NAN_BOXED(32769,16,FLEN)
NAN_BOXED(1024,16,FLEN)
NAN_BOXED(33792,16,FLEN)
NAN_BOXED(32769,16,FLEN)
NAN_BOXED(1024,16,FLEN)
NAN_BOXED(1025,16,FLEN)
NAN_BOXED(32769,16,FLEN)
NAN_BOXED(1024,16,FLEN)
NAN_BOXED(33877,16,FLEN)
NAN_BOXED(32769,16,FLEN)
NAN_BOXED(1024,16,FLEN)
NAN_BOXED(31743,16,FLEN)
NAN_BOXED(32769,16,FLEN)
NAN_BOXED(1024,16,FLEN)
NAN_BOXED(64511,16,FLEN)
NAN_BOXED(32769,16,FLEN)
NAN_BOXED(1024,16,FLEN)
NAN_BOXED(31744,16,FLEN)
NAN_BOXED(32769,16,FLEN)
NAN_BOXED(1024,16,FLEN)
NAN_BOXED(64512,16,FLEN)
NAN_BOXED(32769,16,FLEN)
NAN_BOXED(1024,16,FLEN)
NAN_BOXED(32256,16,FLEN)
NAN_BOXED(32769,16,FLEN)
NAN_BOXED(1024,16,FLEN)
NAN_BOXED(65024,16,FLEN)
NAN_BOXED(32769,16,FLEN)
NAN_BOXED(1024,16,FLEN)
NAN_BOXED(32257,16,FLEN)
NAN_BOXED(32769,16,FLEN)
NAN_BOXED(1024,16,FLEN)
NAN_BOXED(65109,16,FLEN)
NAN_BOXED(32769,16,FLEN)
NAN_BOXED(1024,16,FLEN)
NAN_BOXED(31745,16,FLEN)
NAN_BOXED(32769,16,FLEN)
NAN_BOXED(1024,16,FLEN)
NAN_BOXED(64853,16,FLEN)
NAN_BOXED(32769,16,FLEN)
NAN_BOXED(1024,16,FLEN)
NAN_BOXED(15360,16,FLEN)
NAN_BOXED(32769,16,FLEN)
NAN_BOXED(1024,16,FLEN)
NAN_BOXED(48128,16,FLEN)
NAN_BOXED(32769,16,FLEN)
NAN_BOXED(33792,16,FLEN)
NAN_BOXED(0,16,FLEN)
NAN_BOXED(32769,16,FLEN)
NAN_BOXED(33792,16,FLEN)
NAN_BOXED(32768,16,FLEN)
NAN_BOXED(32769,16,FLEN)
NAN_BOXED(33792,16,FLEN)
NAN_BOXED(1,16,FLEN)
NAN_BOXED(32769,16,FLEN)
NAN_BOXED(33792,16,FLEN)
NAN_BOXED(32769,16,FLEN)
NAN_BOXED(32769,16,FLEN)
NAN_BOXED(33792,16,FLEN)
NAN_BOXED(2,16,FLEN)
NAN_BOXED(32769,16,FLEN)
NAN_BOXED(33792,16,FLEN)
NAN_BOXED(33790,16,FLEN)
NAN_BOXED(32769,16,FLEN)
NAN_BOXED(33792,16,FLEN)
NAN_BOXED(1023,16,FLEN)
NAN_BOXED(32769,16,FLEN)
NAN_BOXED(33792,16,FLEN)
NAN_BOXED(33791,16,FLEN)
NAN_BOXED(32769,16,FLEN)
NAN_BOXED(33792,16,FLEN)
NAN_BOXED(1024,16,FLEN)
NAN_BOXED(32769,16,FLEN)
NAN_BOXED(33792,16,FLEN)
NAN_BOXED(33792,16,FLEN)
NAN_BOXED(32769,16,FLEN)
NAN_BOXED(33792,16,FLEN)
NAN_BOXED(1025,16,FLEN)
NAN_BOXED(32769,16,FLEN)
NAN_BOXED(33792,16,FLEN)
NAN_BOXED(33877,16,FLEN)
NAN_BOXED(32769,16,FLEN)
NAN_BOXED(33792,16,FLEN)
NAN_BOXED(31743,16,FLEN)
NAN_BOXED(32769,16,FLEN)
NAN_BOXED(33792,16,FLEN)
NAN_BOXED(64511,16,FLEN)
NAN_BOXED(32769,16,FLEN)
NAN_BOXED(33792,16,FLEN)
NAN_BOXED(31744,16,FLEN)
NAN_BOXED(32769,16,FLEN)
NAN_BOXED(33792,16,FLEN)
NAN_BOXED(64512,16,FLEN)
NAN_BOXED(32769,16,FLEN)
NAN_BOXED(33792,16,FLEN)
NAN_BOXED(32256,16,FLEN)
NAN_BOXED(32769,16,FLEN)
NAN_BOXED(33792,16,FLEN)
NAN_BOXED(65024,16,FLEN)
NAN_BOXED(32769,16,FLEN)
NAN_BOXED(33792,16,FLEN)
NAN_BOXED(32257,16,FLEN)
NAN_BOXED(32769,16,FLEN)
NAN_BOXED(33792,16,FLEN)
NAN_BOXED(65109,16,FLEN)
NAN_BOXED(32769,16,FLEN)
NAN_BOXED(33792,16,FLEN)
NAN_BOXED(31745,16,FLEN)
NAN_BOXED(32769,16,FLEN)
NAN_BOXED(33792,16,FLEN)
NAN_BOXED(64853,16,FLEN)
NAN_BOXED(32769,16,FLEN)
NAN_BOXED(33792,16,FLEN)
NAN_BOXED(15360,16,FLEN)
NAN_BOXED(32769,16,FLEN)
NAN_BOXED(33792,16,FLEN)
NAN_BOXED(48128,16,FLEN)
NAN_BOXED(32769,16,FLEN)
NAN_BOXED(1025,16,FLEN)
NAN_BOXED(0,16,FLEN)
NAN_BOXED(32769,16,FLEN)
NAN_BOXED(1025,16,FLEN)
NAN_BOXED(32768,16,FLEN)
NAN_BOXED(32769,16,FLEN)
NAN_BOXED(1025,16,FLEN)
NAN_BOXED(1,16,FLEN)
NAN_BOXED(32769,16,FLEN)
NAN_BOXED(1025,16,FLEN)
NAN_BOXED(32769,16,FLEN)
NAN_BOXED(32769,16,FLEN)
NAN_BOXED(1025,16,FLEN)
NAN_BOXED(2,16,FLEN)
NAN_BOXED(32769,16,FLEN)
NAN_BOXED(1025,16,FLEN)
NAN_BOXED(33790,16,FLEN)
NAN_BOXED(32769,16,FLEN)
NAN_BOXED(1025,16,FLEN)
NAN_BOXED(1023,16,FLEN)
NAN_BOXED(32769,16,FLEN)
NAN_BOXED(1025,16,FLEN)
NAN_BOXED(33791,16,FLEN)
NAN_BOXED(32769,16,FLEN)
NAN_BOXED(1025,16,FLEN)
NAN_BOXED(1024,16,FLEN)
NAN_BOXED(32769,16,FLEN)
NAN_BOXED(1025,16,FLEN)
NAN_BOXED(33792,16,FLEN)
NAN_BOXED(32769,16,FLEN)
NAN_BOXED(1025,16,FLEN)
NAN_BOXED(1025,16,FLEN)
NAN_BOXED(32769,16,FLEN)
NAN_BOXED(1025,16,FLEN)
NAN_BOXED(33877,16,FLEN)
NAN_BOXED(32769,16,FLEN)
NAN_BOXED(1025,16,FLEN)
NAN_BOXED(31743,16,FLEN)
NAN_BOXED(32769,16,FLEN)
NAN_BOXED(1025,16,FLEN)
NAN_BOXED(64511,16,FLEN)
NAN_BOXED(32769,16,FLEN)
NAN_BOXED(1025,16,FLEN)
NAN_BOXED(31744,16,FLEN)
NAN_BOXED(32769,16,FLEN)
NAN_BOXED(1025,16,FLEN)
NAN_BOXED(64512,16,FLEN)
NAN_BOXED(32769,16,FLEN)
NAN_BOXED(1025,16,FLEN)
NAN_BOXED(32256,16,FLEN)
NAN_BOXED(32769,16,FLEN)
NAN_BOXED(1025,16,FLEN)
NAN_BOXED(65024,16,FLEN)
NAN_BOXED(32769,16,FLEN)
NAN_BOXED(1025,16,FLEN)
NAN_BOXED(32257,16,FLEN)
NAN_BOXED(32769,16,FLEN)
NAN_BOXED(1025,16,FLEN)
NAN_BOXED(65109,16,FLEN)
NAN_BOXED(32769,16,FLEN)
NAN_BOXED(1025,16,FLEN)
NAN_BOXED(31745,16,FLEN)
NAN_BOXED(32769,16,FLEN)
NAN_BOXED(1025,16,FLEN)
NAN_BOXED(64853,16,FLEN)
NAN_BOXED(32769,16,FLEN)
NAN_BOXED(1025,16,FLEN)
NAN_BOXED(15360,16,FLEN)
NAN_BOXED(32769,16,FLEN)
NAN_BOXED(1025,16,FLEN)
NAN_BOXED(48128,16,FLEN)
NAN_BOXED(32769,16,FLEN)
NAN_BOXED(33877,16,FLEN)
NAN_BOXED(0,16,FLEN)
NAN_BOXED(32769,16,FLEN)
NAN_BOXED(33877,16,FLEN)
NAN_BOXED(32768,16,FLEN)
NAN_BOXED(32769,16,FLEN)
NAN_BOXED(33877,16,FLEN)
NAN_BOXED(1,16,FLEN)
NAN_BOXED(32769,16,FLEN)
NAN_BOXED(33877,16,FLEN)
NAN_BOXED(32769,16,FLEN)
NAN_BOXED(32769,16,FLEN)
NAN_BOXED(33877,16,FLEN)
NAN_BOXED(2,16,FLEN)
NAN_BOXED(32769,16,FLEN)
NAN_BOXED(33877,16,FLEN)
NAN_BOXED(33790,16,FLEN)
NAN_BOXED(32769,16,FLEN)
NAN_BOXED(33877,16,FLEN)
NAN_BOXED(1023,16,FLEN)
NAN_BOXED(32769,16,FLEN)
NAN_BOXED(33877,16,FLEN)
NAN_BOXED(33791,16,FLEN)
NAN_BOXED(32769,16,FLEN)
NAN_BOXED(33877,16,FLEN)
NAN_BOXED(1024,16,FLEN)
NAN_BOXED(32769,16,FLEN)
NAN_BOXED(33877,16,FLEN)
NAN_BOXED(33792,16,FLEN)
NAN_BOXED(32769,16,FLEN)
NAN_BOXED(33877,16,FLEN)
NAN_BOXED(1025,16,FLEN)
NAN_BOXED(32769,16,FLEN)
NAN_BOXED(33877,16,FLEN)
NAN_BOXED(33877,16,FLEN)
NAN_BOXED(32769,16,FLEN)
NAN_BOXED(33877,16,FLEN)
NAN_BOXED(31743,16,FLEN)
NAN_BOXED(32769,16,FLEN)
NAN_BOXED(33877,16,FLEN)
NAN_BOXED(64511,16,FLEN)
NAN_BOXED(32769,16,FLEN)
NAN_BOXED(33877,16,FLEN)
NAN_BOXED(31744,16,FLEN)
NAN_BOXED(32769,16,FLEN)
NAN_BOXED(33877,16,FLEN)
NAN_BOXED(64512,16,FLEN)
NAN_BOXED(32769,16,FLEN)
NAN_BOXED(33877,16,FLEN)
NAN_BOXED(32256,16,FLEN)
NAN_BOXED(32769,16,FLEN)
NAN_BOXED(33877,16,FLEN)
NAN_BOXED(65024,16,FLEN)
NAN_BOXED(32769,16,FLEN)
NAN_BOXED(33877,16,FLEN)
NAN_BOXED(32257,16,FLEN)
NAN_BOXED(32769,16,FLEN)
NAN_BOXED(33877,16,FLEN)
NAN_BOXED(65109,16,FLEN)
NAN_BOXED(32769,16,FLEN)
NAN_BOXED(33877,16,FLEN)
NAN_BOXED(31745,16,FLEN)
NAN_BOXED(32769,16,FLEN)
NAN_BOXED(33877,16,FLEN)
NAN_BOXED(64853,16,FLEN)
NAN_BOXED(32769,16,FLEN)
NAN_BOXED(33877,16,FLEN)
NAN_BOXED(15360,16,FLEN)
NAN_BOXED(32769,16,FLEN)
NAN_BOXED(33877,16,FLEN)
NAN_BOXED(48128,16,FLEN)
NAN_BOXED(32769,16,FLEN)
NAN_BOXED(31743,16,FLEN)
NAN_BOXED(0,16,FLEN)
NAN_BOXED(32769,16,FLEN)
NAN_BOXED(31743,16,FLEN)
NAN_BOXED(32768,16,FLEN)
NAN_BOXED(32769,16,FLEN)
NAN_BOXED(31743,16,FLEN)
NAN_BOXED(1,16,FLEN)
NAN_BOXED(32769,16,FLEN)
NAN_BOXED(31743,16,FLEN)
NAN_BOXED(32769,16,FLEN)
NAN_BOXED(32769,16,FLEN)
NAN_BOXED(31743,16,FLEN)
NAN_BOXED(2,16,FLEN)
NAN_BOXED(32769,16,FLEN)
NAN_BOXED(31743,16,FLEN)
NAN_BOXED(33790,16,FLEN)
NAN_BOXED(32769,16,FLEN)
NAN_BOXED(31743,16,FLEN)
NAN_BOXED(1023,16,FLEN)
NAN_BOXED(32769,16,FLEN)
NAN_BOXED(31743,16,FLEN)
NAN_BOXED(33791,16,FLEN)
NAN_BOXED(32769,16,FLEN)
NAN_BOXED(31743,16,FLEN)
NAN_BOXED(1024,16,FLEN)
NAN_BOXED(32769,16,FLEN)
NAN_BOXED(31743,16,FLEN)
NAN_BOXED(33792,16,FLEN)
NAN_BOXED(32769,16,FLEN)
NAN_BOXED(31743,16,FLEN)
NAN_BOXED(1025,16,FLEN)
NAN_BOXED(32769,16,FLEN)
NAN_BOXED(31743,16,FLEN)
NAN_BOXED(33877,16,FLEN)
NAN_BOXED(32769,16,FLEN)
NAN_BOXED(31743,16,FLEN)
NAN_BOXED(31743,16,FLEN)
NAN_BOXED(32769,16,FLEN)
NAN_BOXED(31743,16,FLEN)
NAN_BOXED(64511,16,FLEN)
NAN_BOXED(32769,16,FLEN)
NAN_BOXED(31743,16,FLEN)
NAN_BOXED(31744,16,FLEN)
NAN_BOXED(32769,16,FLEN)
NAN_BOXED(31743,16,FLEN)
NAN_BOXED(64512,16,FLEN)
NAN_BOXED(32769,16,FLEN)
NAN_BOXED(31743,16,FLEN)
NAN_BOXED(32256,16,FLEN)
NAN_BOXED(32769,16,FLEN)
NAN_BOXED(31743,16,FLEN)
NAN_BOXED(65024,16,FLEN)
NAN_BOXED(32769,16,FLEN)
NAN_BOXED(31743,16,FLEN)
NAN_BOXED(32257,16,FLEN)
NAN_BOXED(32769,16,FLEN)
NAN_BOXED(31743,16,FLEN)
NAN_BOXED(65109,16,FLEN)
NAN_BOXED(32769,16,FLEN)
NAN_BOXED(31743,16,FLEN)
NAN_BOXED(31745,16,FLEN)
NAN_BOXED(32769,16,FLEN)
NAN_BOXED(31743,16,FLEN)
NAN_BOXED(64853,16,FLEN)
NAN_BOXED(32769,16,FLEN)
NAN_BOXED(31743,16,FLEN)
NAN_BOXED(15360,16,FLEN)
NAN_BOXED(32769,16,FLEN)
NAN_BOXED(31743,16,FLEN)
NAN_BOXED(48128,16,FLEN)
NAN_BOXED(32769,16,FLEN)
NAN_BOXED(64511,16,FLEN)
NAN_BOXED(0,16,FLEN)
NAN_BOXED(32769,16,FLEN)
NAN_BOXED(64511,16,FLEN)
NAN_BOXED(32768,16,FLEN)
NAN_BOXED(32769,16,FLEN)
NAN_BOXED(64511,16,FLEN)
NAN_BOXED(1,16,FLEN)
NAN_BOXED(32769,16,FLEN)
NAN_BOXED(64511,16,FLEN)
NAN_BOXED(32769,16,FLEN)
NAN_BOXED(32769,16,FLEN)
NAN_BOXED(64511,16,FLEN)
NAN_BOXED(2,16,FLEN)
NAN_BOXED(32769,16,FLEN)
NAN_BOXED(64511,16,FLEN)
NAN_BOXED(33790,16,FLEN)
NAN_BOXED(32769,16,FLEN)
NAN_BOXED(64511,16,FLEN)
NAN_BOXED(1023,16,FLEN)
NAN_BOXED(32769,16,FLEN)
NAN_BOXED(64511,16,FLEN)
NAN_BOXED(33791,16,FLEN)
NAN_BOXED(32769,16,FLEN)
NAN_BOXED(64511,16,FLEN)
NAN_BOXED(1024,16,FLEN)
NAN_BOXED(32769,16,FLEN)
NAN_BOXED(64511,16,FLEN)
NAN_BOXED(33792,16,FLEN)
NAN_BOXED(32769,16,FLEN)
NAN_BOXED(64511,16,FLEN)
NAN_BOXED(1025,16,FLEN)
NAN_BOXED(32769,16,FLEN)
NAN_BOXED(64511,16,FLEN)
NAN_BOXED(33877,16,FLEN)
NAN_BOXED(32769,16,FLEN)
NAN_BOXED(64511,16,FLEN)
NAN_BOXED(31743,16,FLEN)
NAN_BOXED(32769,16,FLEN)
NAN_BOXED(64511,16,FLEN)
NAN_BOXED(64511,16,FLEN)
NAN_BOXED(32769,16,FLEN)
NAN_BOXED(64511,16,FLEN)
NAN_BOXED(31744,16,FLEN)
NAN_BOXED(32769,16,FLEN)
NAN_BOXED(64511,16,FLEN)
NAN_BOXED(64512,16,FLEN)
NAN_BOXED(32769,16,FLEN)
NAN_BOXED(64511,16,FLEN)
NAN_BOXED(32256,16,FLEN)
NAN_BOXED(32769,16,FLEN)
NAN_BOXED(64511,16,FLEN)
NAN_BOXED(65024,16,FLEN)
NAN_BOXED(32769,16,FLEN)
NAN_BOXED(64511,16,FLEN)
NAN_BOXED(32257,16,FLEN)
NAN_BOXED(32769,16,FLEN)
NAN_BOXED(64511,16,FLEN)
NAN_BOXED(65109,16,FLEN)
NAN_BOXED(32769,16,FLEN)
NAN_BOXED(64511,16,FLEN)
NAN_BOXED(31745,16,FLEN)
NAN_BOXED(32769,16,FLEN)
NAN_BOXED(64511,16,FLEN)
NAN_BOXED(64853,16,FLEN)
NAN_BOXED(32769,16,FLEN)
NAN_BOXED(64511,16,FLEN)
NAN_BOXED(15360,16,FLEN)
NAN_BOXED(32769,16,FLEN)
NAN_BOXED(64511,16,FLEN)
NAN_BOXED(48128,16,FLEN)
NAN_BOXED(32769,16,FLEN)
NAN_BOXED(31744,16,FLEN)
NAN_BOXED(0,16,FLEN)
NAN_BOXED(32769,16,FLEN)
NAN_BOXED(31744,16,FLEN)
NAN_BOXED(32768,16,FLEN)
NAN_BOXED(32769,16,FLEN)
NAN_BOXED(31744,16,FLEN)
NAN_BOXED(1,16,FLEN)
NAN_BOXED(32769,16,FLEN)
NAN_BOXED(31744,16,FLEN)
NAN_BOXED(32769,16,FLEN)
NAN_BOXED(32769,16,FLEN)
NAN_BOXED(31744,16,FLEN)
NAN_BOXED(2,16,FLEN)
NAN_BOXED(32769,16,FLEN)
NAN_BOXED(31744,16,FLEN)
NAN_BOXED(33790,16,FLEN)
NAN_BOXED(32769,16,FLEN)
NAN_BOXED(31744,16,FLEN)
NAN_BOXED(1023,16,FLEN)
NAN_BOXED(32769,16,FLEN)
NAN_BOXED(31744,16,FLEN)
NAN_BOXED(33791,16,FLEN)
NAN_BOXED(32769,16,FLEN)
NAN_BOXED(31744,16,FLEN)
NAN_BOXED(1024,16,FLEN)
NAN_BOXED(32769,16,FLEN)
NAN_BOXED(31744,16,FLEN)
NAN_BOXED(33792,16,FLEN)
NAN_BOXED(32769,16,FLEN)
NAN_BOXED(31744,16,FLEN)
NAN_BOXED(1025,16,FLEN)
NAN_BOXED(32769,16,FLEN)
NAN_BOXED(31744,16,FLEN)
NAN_BOXED(33877,16,FLEN)
NAN_BOXED(32769,16,FLEN)
NAN_BOXED(31744,16,FLEN)
NAN_BOXED(31743,16,FLEN)
NAN_BOXED(32769,16,FLEN)
NAN_BOXED(31744,16,FLEN)
NAN_BOXED(64511,16,FLEN)
NAN_BOXED(32769,16,FLEN)
NAN_BOXED(31744,16,FLEN)
NAN_BOXED(31744,16,FLEN)
NAN_BOXED(32769,16,FLEN)
NAN_BOXED(31744,16,FLEN)
NAN_BOXED(64512,16,FLEN)
NAN_BOXED(32769,16,FLEN)
NAN_BOXED(31744,16,FLEN)
NAN_BOXED(32256,16,FLEN)
NAN_BOXED(32769,16,FLEN)
NAN_BOXED(31744,16,FLEN)
NAN_BOXED(65024,16,FLEN)
NAN_BOXED(32769,16,FLEN)
NAN_BOXED(31744,16,FLEN)
NAN_BOXED(32257,16,FLEN)
NAN_BOXED(32769,16,FLEN)
NAN_BOXED(31744,16,FLEN)
NAN_BOXED(65109,16,FLEN)
NAN_BOXED(32769,16,FLEN)
NAN_BOXED(31744,16,FLEN)
NAN_BOXED(31745,16,FLEN)
NAN_BOXED(32769,16,FLEN)
NAN_BOXED(31744,16,FLEN)
NAN_BOXED(64853,16,FLEN)
NAN_BOXED(32769,16,FLEN)
NAN_BOXED(31744,16,FLEN)
NAN_BOXED(15360,16,FLEN)
NAN_BOXED(32769,16,FLEN)
NAN_BOXED(31744,16,FLEN)
NAN_BOXED(48128,16,FLEN)
NAN_BOXED(32769,16,FLEN)
NAN_BOXED(64512,16,FLEN)
NAN_BOXED(0,16,FLEN)
NAN_BOXED(32769,16,FLEN)
NAN_BOXED(64512,16,FLEN)
NAN_BOXED(32768,16,FLEN)
NAN_BOXED(32769,16,FLEN)
NAN_BOXED(64512,16,FLEN)
NAN_BOXED(1,16,FLEN)
NAN_BOXED(32769,16,FLEN)
NAN_BOXED(64512,16,FLEN)
NAN_BOXED(32769,16,FLEN)
NAN_BOXED(32769,16,FLEN)
NAN_BOXED(64512,16,FLEN)
NAN_BOXED(2,16,FLEN)
NAN_BOXED(32769,16,FLEN)
NAN_BOXED(64512,16,FLEN)
NAN_BOXED(33790,16,FLEN)
NAN_BOXED(32769,16,FLEN)
NAN_BOXED(64512,16,FLEN)
NAN_BOXED(1023,16,FLEN)
NAN_BOXED(32769,16,FLEN)
NAN_BOXED(64512,16,FLEN)
NAN_BOXED(33791,16,FLEN)
NAN_BOXED(32769,16,FLEN)
NAN_BOXED(64512,16,FLEN)
NAN_BOXED(1024,16,FLEN)
NAN_BOXED(32769,16,FLEN)
NAN_BOXED(64512,16,FLEN)
NAN_BOXED(33792,16,FLEN)
NAN_BOXED(32769,16,FLEN)
NAN_BOXED(64512,16,FLEN)
NAN_BOXED(1025,16,FLEN)
NAN_BOXED(32769,16,FLEN)
NAN_BOXED(64512,16,FLEN)
NAN_BOXED(33877,16,FLEN)
NAN_BOXED(32769,16,FLEN)
NAN_BOXED(64512,16,FLEN)
NAN_BOXED(31743,16,FLEN)
NAN_BOXED(32769,16,FLEN)
NAN_BOXED(64512,16,FLEN)
NAN_BOXED(64511,16,FLEN)
NAN_BOXED(32769,16,FLEN)
NAN_BOXED(64512,16,FLEN)
NAN_BOXED(31744,16,FLEN)
NAN_BOXED(32769,16,FLEN)
NAN_BOXED(64512,16,FLEN)
NAN_BOXED(64512,16,FLEN)
NAN_BOXED(32769,16,FLEN)
NAN_BOXED(64512,16,FLEN)
NAN_BOXED(32256,16,FLEN)
NAN_BOXED(32769,16,FLEN)
NAN_BOXED(64512,16,FLEN)
NAN_BOXED(65024,16,FLEN)
NAN_BOXED(32769,16,FLEN)
NAN_BOXED(64512,16,FLEN)
NAN_BOXED(32257,16,FLEN)
NAN_BOXED(32769,16,FLEN)
NAN_BOXED(64512,16,FLEN)
NAN_BOXED(65109,16,FLEN)
NAN_BOXED(32769,16,FLEN)
NAN_BOXED(64512,16,FLEN)
NAN_BOXED(31745,16,FLEN)
NAN_BOXED(32769,16,FLEN)
NAN_BOXED(64512,16,FLEN)
NAN_BOXED(64853,16,FLEN)
NAN_BOXED(32769,16,FLEN)
NAN_BOXED(64512,16,FLEN)
NAN_BOXED(15360,16,FLEN)
NAN_BOXED(32769,16,FLEN)
NAN_BOXED(64512,16,FLEN)
NAN_BOXED(48128,16,FLEN)
NAN_BOXED(32769,16,FLEN)
NAN_BOXED(32256,16,FLEN)
NAN_BOXED(0,16,FLEN)
NAN_BOXED(32769,16,FLEN)
NAN_BOXED(32256,16,FLEN)
NAN_BOXED(32768,16,FLEN)
NAN_BOXED(32769,16,FLEN)
NAN_BOXED(32256,16,FLEN)
NAN_BOXED(1,16,FLEN)
NAN_BOXED(32769,16,FLEN)
NAN_BOXED(32256,16,FLEN)
NAN_BOXED(32769,16,FLEN)
NAN_BOXED(32769,16,FLEN)
NAN_BOXED(32256,16,FLEN)
NAN_BOXED(2,16,FLEN)
NAN_BOXED(32769,16,FLEN)
NAN_BOXED(32256,16,FLEN)
NAN_BOXED(33790,16,FLEN)
NAN_BOXED(32769,16,FLEN)
NAN_BOXED(32256,16,FLEN)
NAN_BOXED(1023,16,FLEN)
NAN_BOXED(32769,16,FLEN)
NAN_BOXED(32256,16,FLEN)
NAN_BOXED(33791,16,FLEN)
NAN_BOXED(32769,16,FLEN)
NAN_BOXED(32256,16,FLEN)
NAN_BOXED(1024,16,FLEN)
NAN_BOXED(32769,16,FLEN)
NAN_BOXED(32256,16,FLEN)
NAN_BOXED(33792,16,FLEN)
NAN_BOXED(32769,16,FLEN)
NAN_BOXED(32256,16,FLEN)
NAN_BOXED(1025,16,FLEN)
NAN_BOXED(32769,16,FLEN)
NAN_BOXED(32256,16,FLEN)
NAN_BOXED(33877,16,FLEN)
NAN_BOXED(32769,16,FLEN)
NAN_BOXED(32256,16,FLEN)
NAN_BOXED(31743,16,FLEN)
NAN_BOXED(32769,16,FLEN)
NAN_BOXED(32256,16,FLEN)
NAN_BOXED(64511,16,FLEN)
NAN_BOXED(32769,16,FLEN)
NAN_BOXED(32256,16,FLEN)
NAN_BOXED(31744,16,FLEN)
NAN_BOXED(32769,16,FLEN)
NAN_BOXED(32256,16,FLEN)
NAN_BOXED(64512,16,FLEN)
NAN_BOXED(32769,16,FLEN)
NAN_BOXED(32256,16,FLEN)
NAN_BOXED(32256,16,FLEN)
NAN_BOXED(32769,16,FLEN)
NAN_BOXED(32256,16,FLEN)
NAN_BOXED(65024,16,FLEN)
NAN_BOXED(32769,16,FLEN)
NAN_BOXED(32256,16,FLEN)
NAN_BOXED(32257,16,FLEN)
NAN_BOXED(32769,16,FLEN)
NAN_BOXED(32256,16,FLEN)
NAN_BOXED(65109,16,FLEN)
NAN_BOXED(32769,16,FLEN)
NAN_BOXED(32256,16,FLEN)
NAN_BOXED(31745,16,FLEN)
NAN_BOXED(32769,16,FLEN)
NAN_BOXED(32256,16,FLEN)
NAN_BOXED(64853,16,FLEN)
NAN_BOXED(32769,16,FLEN)
NAN_BOXED(32256,16,FLEN)
NAN_BOXED(15360,16,FLEN)
NAN_BOXED(32769,16,FLEN)
NAN_BOXED(32256,16,FLEN)
NAN_BOXED(48128,16,FLEN)
NAN_BOXED(32769,16,FLEN)
NAN_BOXED(65024,16,FLEN)
NAN_BOXED(0,16,FLEN)
NAN_BOXED(32769,16,FLEN)
NAN_BOXED(65024,16,FLEN)
NAN_BOXED(32768,16,FLEN)
NAN_BOXED(32769,16,FLEN)
NAN_BOXED(65024,16,FLEN)
NAN_BOXED(1,16,FLEN)
NAN_BOXED(32769,16,FLEN)
NAN_BOXED(65024,16,FLEN)
NAN_BOXED(32769,16,FLEN)
NAN_BOXED(32769,16,FLEN)
NAN_BOXED(65024,16,FLEN)
NAN_BOXED(2,16,FLEN)
NAN_BOXED(32769,16,FLEN)
NAN_BOXED(65024,16,FLEN)
NAN_BOXED(33790,16,FLEN)
NAN_BOXED(32769,16,FLEN)
NAN_BOXED(65024,16,FLEN)
NAN_BOXED(1023,16,FLEN)
NAN_BOXED(32769,16,FLEN)
NAN_BOXED(65024,16,FLEN)
NAN_BOXED(33791,16,FLEN)
NAN_BOXED(32769,16,FLEN)
NAN_BOXED(65024,16,FLEN)
NAN_BOXED(1024,16,FLEN)
NAN_BOXED(32769,16,FLEN)
NAN_BOXED(65024,16,FLEN)
NAN_BOXED(33792,16,FLEN)
NAN_BOXED(32769,16,FLEN)
NAN_BOXED(65024,16,FLEN)
NAN_BOXED(1025,16,FLEN)
NAN_BOXED(32769,16,FLEN)
NAN_BOXED(65024,16,FLEN)
NAN_BOXED(33877,16,FLEN)
NAN_BOXED(32769,16,FLEN)
NAN_BOXED(65024,16,FLEN)
NAN_BOXED(31743,16,FLEN)
NAN_BOXED(32769,16,FLEN)
NAN_BOXED(65024,16,FLEN)
NAN_BOXED(64511,16,FLEN)
NAN_BOXED(32769,16,FLEN)
NAN_BOXED(65024,16,FLEN)
NAN_BOXED(31744,16,FLEN)
NAN_BOXED(32769,16,FLEN)
NAN_BOXED(65024,16,FLEN)
NAN_BOXED(64512,16,FLEN)
NAN_BOXED(32769,16,FLEN)
NAN_BOXED(65024,16,FLEN)
NAN_BOXED(32256,16,FLEN)
NAN_BOXED(32769,16,FLEN)
NAN_BOXED(65024,16,FLEN)
NAN_BOXED(65024,16,FLEN)
NAN_BOXED(32769,16,FLEN)
NAN_BOXED(65024,16,FLEN)
NAN_BOXED(32257,16,FLEN)
NAN_BOXED(32769,16,FLEN)
NAN_BOXED(65024,16,FLEN)
NAN_BOXED(65109,16,FLEN)
NAN_BOXED(32769,16,FLEN)
NAN_BOXED(65024,16,FLEN)
NAN_BOXED(31745,16,FLEN)
NAN_BOXED(32769,16,FLEN)
NAN_BOXED(65024,16,FLEN)
NAN_BOXED(64853,16,FLEN)
NAN_BOXED(32769,16,FLEN)
NAN_BOXED(65024,16,FLEN)
NAN_BOXED(15360,16,FLEN)
NAN_BOXED(32769,16,FLEN)
NAN_BOXED(65024,16,FLEN)
NAN_BOXED(48128,16,FLEN)
NAN_BOXED(32769,16,FLEN)
NAN_BOXED(32257,16,FLEN)
NAN_BOXED(0,16,FLEN)
NAN_BOXED(32769,16,FLEN)
NAN_BOXED(32257,16,FLEN)
NAN_BOXED(32768,16,FLEN)
NAN_BOXED(32769,16,FLEN)
NAN_BOXED(32257,16,FLEN)
NAN_BOXED(1,16,FLEN)
NAN_BOXED(32769,16,FLEN)
NAN_BOXED(32257,16,FLEN)
NAN_BOXED(32769,16,FLEN)
NAN_BOXED(32769,16,FLEN)
NAN_BOXED(32257,16,FLEN)
NAN_BOXED(2,16,FLEN)
NAN_BOXED(32769,16,FLEN)
NAN_BOXED(32257,16,FLEN)
NAN_BOXED(33790,16,FLEN)
NAN_BOXED(32769,16,FLEN)
NAN_BOXED(32257,16,FLEN)
NAN_BOXED(1023,16,FLEN)
NAN_BOXED(32769,16,FLEN)
NAN_BOXED(32257,16,FLEN)
NAN_BOXED(33791,16,FLEN)
NAN_BOXED(32769,16,FLEN)
NAN_BOXED(32257,16,FLEN)
NAN_BOXED(1024,16,FLEN)
NAN_BOXED(32769,16,FLEN)
NAN_BOXED(32257,16,FLEN)
NAN_BOXED(33792,16,FLEN)
NAN_BOXED(32769,16,FLEN)
NAN_BOXED(32257,16,FLEN)
NAN_BOXED(1025,16,FLEN)
NAN_BOXED(32769,16,FLEN)
NAN_BOXED(32257,16,FLEN)
NAN_BOXED(33877,16,FLEN)
NAN_BOXED(32769,16,FLEN)
NAN_BOXED(32257,16,FLEN)
NAN_BOXED(31743,16,FLEN)
NAN_BOXED(32769,16,FLEN)
NAN_BOXED(32257,16,FLEN)
NAN_BOXED(64511,16,FLEN)
NAN_BOXED(32769,16,FLEN)
NAN_BOXED(32257,16,FLEN)
NAN_BOXED(31744,16,FLEN)
NAN_BOXED(32769,16,FLEN)
NAN_BOXED(32257,16,FLEN)
NAN_BOXED(64512,16,FLEN)
NAN_BOXED(32769,16,FLEN)
NAN_BOXED(32257,16,FLEN)
NAN_BOXED(32256,16,FLEN)
NAN_BOXED(32769,16,FLEN)
NAN_BOXED(32257,16,FLEN)
NAN_BOXED(65024,16,FLEN)
NAN_BOXED(32769,16,FLEN)
NAN_BOXED(32257,16,FLEN)
NAN_BOXED(32257,16,FLEN)
NAN_BOXED(32769,16,FLEN)
NAN_BOXED(32257,16,FLEN)
NAN_BOXED(65109,16,FLEN)
NAN_BOXED(32769,16,FLEN)
NAN_BOXED(32257,16,FLEN)
NAN_BOXED(31745,16,FLEN)
NAN_BOXED(32769,16,FLEN)
NAN_BOXED(32257,16,FLEN)
NAN_BOXED(64853,16,FLEN)
NAN_BOXED(32769,16,FLEN)
NAN_BOXED(32257,16,FLEN)
NAN_BOXED(15360,16,FLEN)
NAN_BOXED(32769,16,FLEN)
NAN_BOXED(32257,16,FLEN)
NAN_BOXED(48128,16,FLEN)
NAN_BOXED(32769,16,FLEN)
NAN_BOXED(65109,16,FLEN)
NAN_BOXED(0,16,FLEN)
NAN_BOXED(32769,16,FLEN)
NAN_BOXED(65109,16,FLEN)
NAN_BOXED(32768,16,FLEN)
NAN_BOXED(32769,16,FLEN)
NAN_BOXED(65109,16,FLEN)
NAN_BOXED(1,16,FLEN)
NAN_BOXED(32769,16,FLEN)
NAN_BOXED(65109,16,FLEN)
NAN_BOXED(32769,16,FLEN)
NAN_BOXED(32769,16,FLEN)
NAN_BOXED(65109,16,FLEN)
NAN_BOXED(2,16,FLEN)
NAN_BOXED(32769,16,FLEN)
NAN_BOXED(65109,16,FLEN)
NAN_BOXED(33790,16,FLEN)
NAN_BOXED(32769,16,FLEN)
NAN_BOXED(65109,16,FLEN)
NAN_BOXED(1023,16,FLEN)
NAN_BOXED(32769,16,FLEN)
NAN_BOXED(65109,16,FLEN)
NAN_BOXED(33791,16,FLEN)
NAN_BOXED(32769,16,FLEN)
NAN_BOXED(65109,16,FLEN)
NAN_BOXED(1024,16,FLEN)
NAN_BOXED(32769,16,FLEN)
NAN_BOXED(65109,16,FLEN)
NAN_BOXED(33792,16,FLEN)
NAN_BOXED(32769,16,FLEN)
NAN_BOXED(65109,16,FLEN)
NAN_BOXED(1025,16,FLEN)
NAN_BOXED(32769,16,FLEN)
NAN_BOXED(65109,16,FLEN)
NAN_BOXED(33877,16,FLEN)
NAN_BOXED(32769,16,FLEN)
NAN_BOXED(65109,16,FLEN)
NAN_BOXED(31743,16,FLEN)
NAN_BOXED(32769,16,FLEN)
NAN_BOXED(65109,16,FLEN)
NAN_BOXED(64511,16,FLEN)
NAN_BOXED(32769,16,FLEN)
NAN_BOXED(65109,16,FLEN)
NAN_BOXED(31744,16,FLEN)
NAN_BOXED(32769,16,FLEN)
NAN_BOXED(65109,16,FLEN)
NAN_BOXED(64512,16,FLEN)
NAN_BOXED(32769,16,FLEN)
NAN_BOXED(65109,16,FLEN)
NAN_BOXED(32256,16,FLEN)
NAN_BOXED(32769,16,FLEN)
NAN_BOXED(65109,16,FLEN)
NAN_BOXED(65024,16,FLEN)
NAN_BOXED(32769,16,FLEN)
NAN_BOXED(65109,16,FLEN)
NAN_BOXED(32257,16,FLEN)
NAN_BOXED(32769,16,FLEN)
NAN_BOXED(65109,16,FLEN)
NAN_BOXED(65109,16,FLEN)
NAN_BOXED(32769,16,FLEN)
NAN_BOXED(65109,16,FLEN)
NAN_BOXED(31745,16,FLEN)
NAN_BOXED(32769,16,FLEN)
NAN_BOXED(65109,16,FLEN)
NAN_BOXED(64853,16,FLEN)
NAN_BOXED(32769,16,FLEN)
NAN_BOXED(65109,16,FLEN)
NAN_BOXED(15360,16,FLEN)
NAN_BOXED(32769,16,FLEN)
NAN_BOXED(65109,16,FLEN)
NAN_BOXED(48128,16,FLEN)
NAN_BOXED(32769,16,FLEN)
NAN_BOXED(31745,16,FLEN)
NAN_BOXED(0,16,FLEN)
NAN_BOXED(32769,16,FLEN)
NAN_BOXED(31745,16,FLEN)
NAN_BOXED(32768,16,FLEN)
NAN_BOXED(32769,16,FLEN)
NAN_BOXED(31745,16,FLEN)
NAN_BOXED(1,16,FLEN)
NAN_BOXED(32769,16,FLEN)
NAN_BOXED(31745,16,FLEN)
NAN_BOXED(32769,16,FLEN)
NAN_BOXED(32769,16,FLEN)
NAN_BOXED(31745,16,FLEN)
NAN_BOXED(2,16,FLEN)
NAN_BOXED(32769,16,FLEN)
NAN_BOXED(31745,16,FLEN)
NAN_BOXED(33790,16,FLEN)
NAN_BOXED(32769,16,FLEN)
NAN_BOXED(31745,16,FLEN)
NAN_BOXED(1023,16,FLEN)
NAN_BOXED(32769,16,FLEN)
NAN_BOXED(31745,16,FLEN)
NAN_BOXED(33791,16,FLEN)
NAN_BOXED(32769,16,FLEN)
NAN_BOXED(31745,16,FLEN)
NAN_BOXED(1024,16,FLEN)
NAN_BOXED(32769,16,FLEN)
NAN_BOXED(31745,16,FLEN)
NAN_BOXED(33792,16,FLEN)
NAN_BOXED(32769,16,FLEN)
NAN_BOXED(31745,16,FLEN)
NAN_BOXED(1025,16,FLEN)
NAN_BOXED(32769,16,FLEN)
NAN_BOXED(31745,16,FLEN)
NAN_BOXED(33877,16,FLEN)
NAN_BOXED(32769,16,FLEN)
NAN_BOXED(31745,16,FLEN)
NAN_BOXED(31743,16,FLEN)
NAN_BOXED(32769,16,FLEN)
NAN_BOXED(31745,16,FLEN)
NAN_BOXED(64511,16,FLEN)
NAN_BOXED(32769,16,FLEN)
NAN_BOXED(31745,16,FLEN)
NAN_BOXED(31744,16,FLEN)
NAN_BOXED(32769,16,FLEN)
NAN_BOXED(31745,16,FLEN)
NAN_BOXED(64512,16,FLEN)
NAN_BOXED(32769,16,FLEN)
NAN_BOXED(31745,16,FLEN)
NAN_BOXED(32256,16,FLEN)
NAN_BOXED(32769,16,FLEN)
NAN_BOXED(31745,16,FLEN)
NAN_BOXED(65024,16,FLEN)
NAN_BOXED(32769,16,FLEN)
NAN_BOXED(31745,16,FLEN)
NAN_BOXED(32257,16,FLEN)
NAN_BOXED(32769,16,FLEN)
NAN_BOXED(31745,16,FLEN)
NAN_BOXED(65109,16,FLEN)
NAN_BOXED(32769,16,FLEN)
NAN_BOXED(31745,16,FLEN)
NAN_BOXED(31745,16,FLEN)
NAN_BOXED(32769,16,FLEN)
NAN_BOXED(31745,16,FLEN)
NAN_BOXED(64853,16,FLEN)
NAN_BOXED(32769,16,FLEN)
NAN_BOXED(31745,16,FLEN)
NAN_BOXED(15360,16,FLEN)
NAN_BOXED(32769,16,FLEN)
NAN_BOXED(31745,16,FLEN)
NAN_BOXED(48128,16,FLEN)
NAN_BOXED(32769,16,FLEN)
NAN_BOXED(64853,16,FLEN)
NAN_BOXED(0,16,FLEN)
NAN_BOXED(32769,16,FLEN)
NAN_BOXED(64853,16,FLEN)
NAN_BOXED(32768,16,FLEN)
NAN_BOXED(32769,16,FLEN)
NAN_BOXED(64853,16,FLEN)
NAN_BOXED(1,16,FLEN)
NAN_BOXED(32769,16,FLEN)
NAN_BOXED(64853,16,FLEN)
NAN_BOXED(32769,16,FLEN)
NAN_BOXED(32769,16,FLEN)
NAN_BOXED(64853,16,FLEN)
NAN_BOXED(2,16,FLEN)
NAN_BOXED(32769,16,FLEN)
NAN_BOXED(64853,16,FLEN)
NAN_BOXED(33790,16,FLEN)
NAN_BOXED(32769,16,FLEN)
NAN_BOXED(64853,16,FLEN)
NAN_BOXED(1023,16,FLEN)
NAN_BOXED(32769,16,FLEN)
NAN_BOXED(64853,16,FLEN)
NAN_BOXED(33791,16,FLEN)
NAN_BOXED(32769,16,FLEN)
NAN_BOXED(64853,16,FLEN)
NAN_BOXED(1024,16,FLEN)
NAN_BOXED(32769,16,FLEN)
NAN_BOXED(64853,16,FLEN)
NAN_BOXED(33792,16,FLEN)
NAN_BOXED(32769,16,FLEN)
NAN_BOXED(64853,16,FLEN)
NAN_BOXED(1025,16,FLEN)
NAN_BOXED(32769,16,FLEN)
NAN_BOXED(64853,16,FLEN)
NAN_BOXED(33877,16,FLEN)
NAN_BOXED(32769,16,FLEN)
NAN_BOXED(64853,16,FLEN)
NAN_BOXED(31743,16,FLEN)
NAN_BOXED(32769,16,FLEN)
NAN_BOXED(64853,16,FLEN)
NAN_BOXED(64511,16,FLEN)
NAN_BOXED(32769,16,FLEN)
NAN_BOXED(64853,16,FLEN)
NAN_BOXED(31744,16,FLEN)
NAN_BOXED(32769,16,FLEN)
NAN_BOXED(64853,16,FLEN)
NAN_BOXED(64512,16,FLEN)
NAN_BOXED(32769,16,FLEN)
NAN_BOXED(64853,16,FLEN)
NAN_BOXED(32256,16,FLEN)
NAN_BOXED(32769,16,FLEN)
NAN_BOXED(64853,16,FLEN)
NAN_BOXED(65024,16,FLEN)
NAN_BOXED(32769,16,FLEN)
NAN_BOXED(64853,16,FLEN)
NAN_BOXED(32257,16,FLEN)
NAN_BOXED(32769,16,FLEN)
NAN_BOXED(64853,16,FLEN)
NAN_BOXED(65109,16,FLEN)
NAN_BOXED(32769,16,FLEN)
NAN_BOXED(64853,16,FLEN)
NAN_BOXED(31745,16,FLEN)
NAN_BOXED(32769,16,FLEN)
NAN_BOXED(64853,16,FLEN)
NAN_BOXED(64853,16,FLEN)
NAN_BOXED(32769,16,FLEN)
NAN_BOXED(64853,16,FLEN)
NAN_BOXED(15360,16,FLEN)
NAN_BOXED(32769,16,FLEN)
NAN_BOXED(64853,16,FLEN)
NAN_BOXED(48128,16,FLEN)
NAN_BOXED(32769,16,FLEN)
NAN_BOXED(15360,16,FLEN)
NAN_BOXED(0,16,FLEN)
NAN_BOXED(32769,16,FLEN)
NAN_BOXED(15360,16,FLEN)
NAN_BOXED(32768,16,FLEN)
NAN_BOXED(32769,16,FLEN)
NAN_BOXED(15360,16,FLEN)
NAN_BOXED(1,16,FLEN)
NAN_BOXED(32769,16,FLEN)
NAN_BOXED(15360,16,FLEN)
NAN_BOXED(32769,16,FLEN)
NAN_BOXED(32769,16,FLEN)
NAN_BOXED(15360,16,FLEN)
NAN_BOXED(2,16,FLEN)
NAN_BOXED(32769,16,FLEN)
NAN_BOXED(15360,16,FLEN)
NAN_BOXED(33790,16,FLEN)
NAN_BOXED(32769,16,FLEN)
NAN_BOXED(15360,16,FLEN)
NAN_BOXED(1023,16,FLEN)
NAN_BOXED(32769,16,FLEN)
NAN_BOXED(15360,16,FLEN)
NAN_BOXED(33791,16,FLEN)
NAN_BOXED(32769,16,FLEN)
NAN_BOXED(15360,16,FLEN)
NAN_BOXED(1024,16,FLEN)
NAN_BOXED(32769,16,FLEN)
NAN_BOXED(15360,16,FLEN)
NAN_BOXED(33792,16,FLEN)
NAN_BOXED(32769,16,FLEN)
NAN_BOXED(15360,16,FLEN)
NAN_BOXED(1025,16,FLEN)
NAN_BOXED(32769,16,FLEN)
NAN_BOXED(15360,16,FLEN)
NAN_BOXED(33877,16,FLEN)
NAN_BOXED(32769,16,FLEN)
NAN_BOXED(15360,16,FLEN)
NAN_BOXED(31743,16,FLEN)
NAN_BOXED(32769,16,FLEN)
NAN_BOXED(15360,16,FLEN)
NAN_BOXED(64511,16,FLEN)
NAN_BOXED(32769,16,FLEN)
NAN_BOXED(15360,16,FLEN)
NAN_BOXED(31744,16,FLEN)
NAN_BOXED(32769,16,FLEN)
NAN_BOXED(15360,16,FLEN)
NAN_BOXED(64512,16,FLEN)
NAN_BOXED(32769,16,FLEN)
NAN_BOXED(15360,16,FLEN)
NAN_BOXED(32256,16,FLEN)
NAN_BOXED(32769,16,FLEN)
NAN_BOXED(15360,16,FLEN)
NAN_BOXED(65024,16,FLEN)
NAN_BOXED(32769,16,FLEN)
NAN_BOXED(15360,16,FLEN)
NAN_BOXED(32257,16,FLEN)
NAN_BOXED(32769,16,FLEN)
NAN_BOXED(15360,16,FLEN)
NAN_BOXED(65109,16,FLEN)
NAN_BOXED(32769,16,FLEN)
NAN_BOXED(15360,16,FLEN)
NAN_BOXED(31745,16,FLEN)
NAN_BOXED(32769,16,FLEN)
NAN_BOXED(15360,16,FLEN)
NAN_BOXED(64853,16,FLEN)
NAN_BOXED(32769,16,FLEN)
NAN_BOXED(15360,16,FLEN)
NAN_BOXED(15360,16,FLEN)
NAN_BOXED(32769,16,FLEN)
NAN_BOXED(15360,16,FLEN)
NAN_BOXED(48128,16,FLEN)
NAN_BOXED(32769,16,FLEN)
NAN_BOXED(48128,16,FLEN)
NAN_BOXED(0,16,FLEN)
NAN_BOXED(32769,16,FLEN)
NAN_BOXED(48128,16,FLEN)
NAN_BOXED(32768,16,FLEN)
NAN_BOXED(32769,16,FLEN)
NAN_BOXED(48128,16,FLEN)
NAN_BOXED(1,16,FLEN)
NAN_BOXED(32769,16,FLEN)
NAN_BOXED(48128,16,FLEN)
NAN_BOXED(32769,16,FLEN)
NAN_BOXED(32769,16,FLEN)
NAN_BOXED(48128,16,FLEN)
NAN_BOXED(2,16,FLEN)
NAN_BOXED(32769,16,FLEN)
NAN_BOXED(48128,16,FLEN)
NAN_BOXED(33790,16,FLEN)
NAN_BOXED(32769,16,FLEN)
NAN_BOXED(48128,16,FLEN)
NAN_BOXED(1023,16,FLEN)
NAN_BOXED(32769,16,FLEN)
NAN_BOXED(48128,16,FLEN)
NAN_BOXED(33791,16,FLEN)
NAN_BOXED(32769,16,FLEN)
NAN_BOXED(48128,16,FLEN)
NAN_BOXED(1024,16,FLEN)
NAN_BOXED(32769,16,FLEN)
NAN_BOXED(48128,16,FLEN)
NAN_BOXED(33792,16,FLEN)
NAN_BOXED(32769,16,FLEN)
NAN_BOXED(48128,16,FLEN)
NAN_BOXED(1025,16,FLEN)
NAN_BOXED(32769,16,FLEN)
NAN_BOXED(48128,16,FLEN)
NAN_BOXED(33877,16,FLEN)
NAN_BOXED(32769,16,FLEN)
NAN_BOXED(48128,16,FLEN)
NAN_BOXED(31743,16,FLEN)
NAN_BOXED(32769,16,FLEN)
NAN_BOXED(48128,16,FLEN)
NAN_BOXED(64511,16,FLEN)
NAN_BOXED(32769,16,FLEN)
NAN_BOXED(48128,16,FLEN)
NAN_BOXED(31744,16,FLEN)
NAN_BOXED(32769,16,FLEN)
NAN_BOXED(48128,16,FLEN)
NAN_BOXED(64512,16,FLEN)
NAN_BOXED(32769,16,FLEN)
NAN_BOXED(48128,16,FLEN)
NAN_BOXED(32256,16,FLEN)
NAN_BOXED(32769,16,FLEN)
NAN_BOXED(48128,16,FLEN)
NAN_BOXED(65024,16,FLEN)
NAN_BOXED(32769,16,FLEN)
NAN_BOXED(48128,16,FLEN)
NAN_BOXED(32257,16,FLEN)
NAN_BOXED(32769,16,FLEN)
NAN_BOXED(48128,16,FLEN)
NAN_BOXED(65109,16,FLEN)
NAN_BOXED(32769,16,FLEN)
NAN_BOXED(48128,16,FLEN)
NAN_BOXED(31745,16,FLEN)
NAN_BOXED(32769,16,FLEN)
NAN_BOXED(48128,16,FLEN)
NAN_BOXED(64853,16,FLEN)
NAN_BOXED(32769,16,FLEN)
NAN_BOXED(48128,16,FLEN)
NAN_BOXED(15360,16,FLEN)
NAN_BOXED(32769,16,FLEN)
RVTEST_DATA_END

RVMODEL_DATA_BEGIN
rvtest_sig_begin:
sig_begin_canary:
CANARY;



signature_x1_0:
    .fill 0*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_1:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_2:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_3:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_4:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_5:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_6:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_7:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_8:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_9:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_10:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_11:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_12:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_13:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_14:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_15:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_16:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_17:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_18:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_19:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_20:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_21:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_22:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_23:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_24:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_25:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_26:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_27:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_28:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_29:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_30:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_31:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_32:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_33:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_34:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_35:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_36:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_37:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_38:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_39:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_40:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_41:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_42:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_43:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_44:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_45:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_46:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_47:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_48:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_49:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_50:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_51:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_52:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_53:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_54:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_55:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_56:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_57:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_58:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_59:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_60:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_61:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_62:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_63:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_64:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_65:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_66:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_67:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_68:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_69:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_70:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_71:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_72:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_73:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_74:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_75:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_76:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_77:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_78:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_79:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_80:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_81:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_82:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_83:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_84:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_85:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_86:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_87:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_88:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_89:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_90:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_91:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_92:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_93:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_94:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_95:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_96:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_97:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_98:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_99:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_100:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_101:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_102:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_103:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_104:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_105:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_106:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_107:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_108:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_109:
    .fill 14*((SIGALIGN)/4),4,0xdeadbeef

#ifdef rvtest_mtrap_routine
tsig_begin_canary:
CANARY;

mtrap_sigptr:
    .fill 64*XLEN/32,4,0xdeadbeef

tsig_end_canary:
CANARY;
#endif

#ifdef rvtest_gpr_save

gpr_save:
    .fill 32*XLEN/32,4,0xdeadbeef

#endif


sig_end_canary:
CANARY;
rvtest_sig_end:
RVMODEL_DATA_END
