// DO NOT EDIT -- auto-generated from riscv-formal/insns/generate.py

module rvfi_isa_rv64ib (
  input                                 rvfi_valid,
  input  [`RISCV_FORMAL_ILEN   - 1 : 0] rvfi_insn,
  input  [`RISCV_FORMAL_XLEN   - 1 : 0] rvfi_pc_rdata,
  input  [`RISCV_FORMAL_XLEN   - 1 : 0] rvfi_rs1_rdata,
  input  [`RISCV_FORMAL_XLEN   - 1 : 0] rvfi_rs2_rdata,
  input  [`RISCV_FORMAL_XLEN   - 1 : 0] rvfi_mem_rdata,
`ifdef RISCV_FORMAL_CSR_MISA
  input  [`RISCV_FORMAL_XLEN   - 1 : 0] rvfi_csr_misa_rdata,
  output [`RISCV_FORMAL_XLEN   - 1 : 0] spec_csr_misa_rmask,
`endif

  output                                spec_valid,
  output                                spec_trap,
  output [                       4 : 0] spec_rs1_addr,
  output [                       4 : 0] spec_rs2_addr,
  output [                       4 : 0] spec_rd_addr,
  output [`RISCV_FORMAL_XLEN   - 1 : 0] spec_rd_wdata,
  output [`RISCV_FORMAL_XLEN   - 1 : 0] spec_pc_wdata,
  output [`RISCV_FORMAL_XLEN   - 1 : 0] spec_mem_addr,
  output [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_mem_rmask,
  output [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_mem_wmask,
  output [`RISCV_FORMAL_XLEN   - 1 : 0] spec_mem_wdata
);
  wire                                spec_insn_add_valid;
  wire                                spec_insn_add_trap;
  wire [                       4 : 0] spec_insn_add_rs1_addr;
  wire [                       4 : 0] spec_insn_add_rs2_addr;
  wire [                       4 : 0] spec_insn_add_rd_addr;
  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_add_rd_wdata;
  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_add_pc_wdata;
  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_add_mem_addr;
  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_add_mem_rmask;
  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_add_mem_wmask;
  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_add_mem_wdata;
`ifdef RISCV_FORMAL_CSR_MISA
  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_add_csr_misa_rmask;
`endif

  rvfi_insn_add insn_add (
    .rvfi_valid(rvfi_valid),
    .rvfi_insn(rvfi_insn),
    .rvfi_pc_rdata(rvfi_pc_rdata),
    .rvfi_rs1_rdata(rvfi_rs1_rdata),
    .rvfi_rs2_rdata(rvfi_rs2_rdata),
    .rvfi_mem_rdata(rvfi_mem_rdata),
`ifdef RISCV_FORMAL_CSR_MISA
    .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata),
    .spec_csr_misa_rmask(spec_insn_add_csr_misa_rmask),
`endif
    .spec_valid(spec_insn_add_valid),
    .spec_trap(spec_insn_add_trap),
    .spec_rs1_addr(spec_insn_add_rs1_addr),
    .spec_rs2_addr(spec_insn_add_rs2_addr),
    .spec_rd_addr(spec_insn_add_rd_addr),
    .spec_rd_wdata(spec_insn_add_rd_wdata),
    .spec_pc_wdata(spec_insn_add_pc_wdata),
    .spec_mem_addr(spec_insn_add_mem_addr),
    .spec_mem_rmask(spec_insn_add_mem_rmask),
    .spec_mem_wmask(spec_insn_add_mem_wmask),
    .spec_mem_wdata(spec_insn_add_mem_wdata)
  );

  wire                                spec_insn_add_uw_valid;
  wire                                spec_insn_add_uw_trap;
  wire [                       4 : 0] spec_insn_add_uw_rs1_addr;
  wire [                       4 : 0] spec_insn_add_uw_rs2_addr;
  wire [                       4 : 0] spec_insn_add_uw_rd_addr;
  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_add_uw_rd_wdata;
  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_add_uw_pc_wdata;
  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_add_uw_mem_addr;
  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_add_uw_mem_rmask;
  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_add_uw_mem_wmask;
  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_add_uw_mem_wdata;
`ifdef RISCV_FORMAL_CSR_MISA
  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_add_uw_csr_misa_rmask;
`endif

  rvfi_insn_add_uw insn_add_uw (
    .rvfi_valid(rvfi_valid),
    .rvfi_insn(rvfi_insn),
    .rvfi_pc_rdata(rvfi_pc_rdata),
    .rvfi_rs1_rdata(rvfi_rs1_rdata),
    .rvfi_rs2_rdata(rvfi_rs2_rdata),
    .rvfi_mem_rdata(rvfi_mem_rdata),
`ifdef RISCV_FORMAL_CSR_MISA
    .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata),
    .spec_csr_misa_rmask(spec_insn_add_uw_csr_misa_rmask),
`endif
    .spec_valid(spec_insn_add_uw_valid),
    .spec_trap(spec_insn_add_uw_trap),
    .spec_rs1_addr(spec_insn_add_uw_rs1_addr),
    .spec_rs2_addr(spec_insn_add_uw_rs2_addr),
    .spec_rd_addr(spec_insn_add_uw_rd_addr),
    .spec_rd_wdata(spec_insn_add_uw_rd_wdata),
    .spec_pc_wdata(spec_insn_add_uw_pc_wdata),
    .spec_mem_addr(spec_insn_add_uw_mem_addr),
    .spec_mem_rmask(spec_insn_add_uw_mem_rmask),
    .spec_mem_wmask(spec_insn_add_uw_mem_wmask),
    .spec_mem_wdata(spec_insn_add_uw_mem_wdata)
  );

  wire                                spec_insn_addi_valid;
  wire                                spec_insn_addi_trap;
  wire [                       4 : 0] spec_insn_addi_rs1_addr;
  wire [                       4 : 0] spec_insn_addi_rs2_addr;
  wire [                       4 : 0] spec_insn_addi_rd_addr;
  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_addi_rd_wdata;
  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_addi_pc_wdata;
  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_addi_mem_addr;
  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_addi_mem_rmask;
  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_addi_mem_wmask;
  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_addi_mem_wdata;
`ifdef RISCV_FORMAL_CSR_MISA
  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_addi_csr_misa_rmask;
`endif

  rvfi_insn_addi insn_addi (
    .rvfi_valid(rvfi_valid),
    .rvfi_insn(rvfi_insn),
    .rvfi_pc_rdata(rvfi_pc_rdata),
    .rvfi_rs1_rdata(rvfi_rs1_rdata),
    .rvfi_rs2_rdata(rvfi_rs2_rdata),
    .rvfi_mem_rdata(rvfi_mem_rdata),
`ifdef RISCV_FORMAL_CSR_MISA
    .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata),
    .spec_csr_misa_rmask(spec_insn_addi_csr_misa_rmask),
`endif
    .spec_valid(spec_insn_addi_valid),
    .spec_trap(spec_insn_addi_trap),
    .spec_rs1_addr(spec_insn_addi_rs1_addr),
    .spec_rs2_addr(spec_insn_addi_rs2_addr),
    .spec_rd_addr(spec_insn_addi_rd_addr),
    .spec_rd_wdata(spec_insn_addi_rd_wdata),
    .spec_pc_wdata(spec_insn_addi_pc_wdata),
    .spec_mem_addr(spec_insn_addi_mem_addr),
    .spec_mem_rmask(spec_insn_addi_mem_rmask),
    .spec_mem_wmask(spec_insn_addi_mem_wmask),
    .spec_mem_wdata(spec_insn_addi_mem_wdata)
  );

  wire                                spec_insn_addiw_valid;
  wire                                spec_insn_addiw_trap;
  wire [                       4 : 0] spec_insn_addiw_rs1_addr;
  wire [                       4 : 0] spec_insn_addiw_rs2_addr;
  wire [                       4 : 0] spec_insn_addiw_rd_addr;
  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_addiw_rd_wdata;
  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_addiw_pc_wdata;
  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_addiw_mem_addr;
  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_addiw_mem_rmask;
  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_addiw_mem_wmask;
  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_addiw_mem_wdata;
`ifdef RISCV_FORMAL_CSR_MISA
  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_addiw_csr_misa_rmask;
`endif

  rvfi_insn_addiw insn_addiw (
    .rvfi_valid(rvfi_valid),
    .rvfi_insn(rvfi_insn),
    .rvfi_pc_rdata(rvfi_pc_rdata),
    .rvfi_rs1_rdata(rvfi_rs1_rdata),
    .rvfi_rs2_rdata(rvfi_rs2_rdata),
    .rvfi_mem_rdata(rvfi_mem_rdata),
`ifdef RISCV_FORMAL_CSR_MISA
    .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata),
    .spec_csr_misa_rmask(spec_insn_addiw_csr_misa_rmask),
`endif
    .spec_valid(spec_insn_addiw_valid),
    .spec_trap(spec_insn_addiw_trap),
    .spec_rs1_addr(spec_insn_addiw_rs1_addr),
    .spec_rs2_addr(spec_insn_addiw_rs2_addr),
    .spec_rd_addr(spec_insn_addiw_rd_addr),
    .spec_rd_wdata(spec_insn_addiw_rd_wdata),
    .spec_pc_wdata(spec_insn_addiw_pc_wdata),
    .spec_mem_addr(spec_insn_addiw_mem_addr),
    .spec_mem_rmask(spec_insn_addiw_mem_rmask),
    .spec_mem_wmask(spec_insn_addiw_mem_wmask),
    .spec_mem_wdata(spec_insn_addiw_mem_wdata)
  );

  wire                                spec_insn_addw_valid;
  wire                                spec_insn_addw_trap;
  wire [                       4 : 0] spec_insn_addw_rs1_addr;
  wire [                       4 : 0] spec_insn_addw_rs2_addr;
  wire [                       4 : 0] spec_insn_addw_rd_addr;
  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_addw_rd_wdata;
  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_addw_pc_wdata;
  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_addw_mem_addr;
  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_addw_mem_rmask;
  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_addw_mem_wmask;
  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_addw_mem_wdata;
`ifdef RISCV_FORMAL_CSR_MISA
  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_addw_csr_misa_rmask;
`endif

  rvfi_insn_addw insn_addw (
    .rvfi_valid(rvfi_valid),
    .rvfi_insn(rvfi_insn),
    .rvfi_pc_rdata(rvfi_pc_rdata),
    .rvfi_rs1_rdata(rvfi_rs1_rdata),
    .rvfi_rs2_rdata(rvfi_rs2_rdata),
    .rvfi_mem_rdata(rvfi_mem_rdata),
`ifdef RISCV_FORMAL_CSR_MISA
    .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata),
    .spec_csr_misa_rmask(spec_insn_addw_csr_misa_rmask),
`endif
    .spec_valid(spec_insn_addw_valid),
    .spec_trap(spec_insn_addw_trap),
    .spec_rs1_addr(spec_insn_addw_rs1_addr),
    .spec_rs2_addr(spec_insn_addw_rs2_addr),
    .spec_rd_addr(spec_insn_addw_rd_addr),
    .spec_rd_wdata(spec_insn_addw_rd_wdata),
    .spec_pc_wdata(spec_insn_addw_pc_wdata),
    .spec_mem_addr(spec_insn_addw_mem_addr),
    .spec_mem_rmask(spec_insn_addw_mem_rmask),
    .spec_mem_wmask(spec_insn_addw_mem_wmask),
    .spec_mem_wdata(spec_insn_addw_mem_wdata)
  );

  wire                                spec_insn_and_valid;
  wire                                spec_insn_and_trap;
  wire [                       4 : 0] spec_insn_and_rs1_addr;
  wire [                       4 : 0] spec_insn_and_rs2_addr;
  wire [                       4 : 0] spec_insn_and_rd_addr;
  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_and_rd_wdata;
  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_and_pc_wdata;
  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_and_mem_addr;
  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_and_mem_rmask;
  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_and_mem_wmask;
  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_and_mem_wdata;
`ifdef RISCV_FORMAL_CSR_MISA
  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_and_csr_misa_rmask;
`endif

  rvfi_insn_and insn_and (
    .rvfi_valid(rvfi_valid),
    .rvfi_insn(rvfi_insn),
    .rvfi_pc_rdata(rvfi_pc_rdata),
    .rvfi_rs1_rdata(rvfi_rs1_rdata),
    .rvfi_rs2_rdata(rvfi_rs2_rdata),
    .rvfi_mem_rdata(rvfi_mem_rdata),
`ifdef RISCV_FORMAL_CSR_MISA
    .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata),
    .spec_csr_misa_rmask(spec_insn_and_csr_misa_rmask),
`endif
    .spec_valid(spec_insn_and_valid),
    .spec_trap(spec_insn_and_trap),
    .spec_rs1_addr(spec_insn_and_rs1_addr),
    .spec_rs2_addr(spec_insn_and_rs2_addr),
    .spec_rd_addr(spec_insn_and_rd_addr),
    .spec_rd_wdata(spec_insn_and_rd_wdata),
    .spec_pc_wdata(spec_insn_and_pc_wdata),
    .spec_mem_addr(spec_insn_and_mem_addr),
    .spec_mem_rmask(spec_insn_and_mem_rmask),
    .spec_mem_wmask(spec_insn_and_mem_wmask),
    .spec_mem_wdata(spec_insn_and_mem_wdata)
  );

  wire                                spec_insn_andi_valid;
  wire                                spec_insn_andi_trap;
  wire [                       4 : 0] spec_insn_andi_rs1_addr;
  wire [                       4 : 0] spec_insn_andi_rs2_addr;
  wire [                       4 : 0] spec_insn_andi_rd_addr;
  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_andi_rd_wdata;
  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_andi_pc_wdata;
  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_andi_mem_addr;
  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_andi_mem_rmask;
  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_andi_mem_wmask;
  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_andi_mem_wdata;
`ifdef RISCV_FORMAL_CSR_MISA
  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_andi_csr_misa_rmask;
`endif

  rvfi_insn_andi insn_andi (
    .rvfi_valid(rvfi_valid),
    .rvfi_insn(rvfi_insn),
    .rvfi_pc_rdata(rvfi_pc_rdata),
    .rvfi_rs1_rdata(rvfi_rs1_rdata),
    .rvfi_rs2_rdata(rvfi_rs2_rdata),
    .rvfi_mem_rdata(rvfi_mem_rdata),
`ifdef RISCV_FORMAL_CSR_MISA
    .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata),
    .spec_csr_misa_rmask(spec_insn_andi_csr_misa_rmask),
`endif
    .spec_valid(spec_insn_andi_valid),
    .spec_trap(spec_insn_andi_trap),
    .spec_rs1_addr(spec_insn_andi_rs1_addr),
    .spec_rs2_addr(spec_insn_andi_rs2_addr),
    .spec_rd_addr(spec_insn_andi_rd_addr),
    .spec_rd_wdata(spec_insn_andi_rd_wdata),
    .spec_pc_wdata(spec_insn_andi_pc_wdata),
    .spec_mem_addr(spec_insn_andi_mem_addr),
    .spec_mem_rmask(spec_insn_andi_mem_rmask),
    .spec_mem_wmask(spec_insn_andi_mem_wmask),
    .spec_mem_wdata(spec_insn_andi_mem_wdata)
  );

  wire                                spec_insn_andn_valid;
  wire                                spec_insn_andn_trap;
  wire [                       4 : 0] spec_insn_andn_rs1_addr;
  wire [                       4 : 0] spec_insn_andn_rs2_addr;
  wire [                       4 : 0] spec_insn_andn_rd_addr;
  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_andn_rd_wdata;
  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_andn_pc_wdata;
  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_andn_mem_addr;
  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_andn_mem_rmask;
  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_andn_mem_wmask;
  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_andn_mem_wdata;
`ifdef RISCV_FORMAL_CSR_MISA
  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_andn_csr_misa_rmask;
`endif

  rvfi_insn_andn insn_andn (
    .rvfi_valid(rvfi_valid),
    .rvfi_insn(rvfi_insn),
    .rvfi_pc_rdata(rvfi_pc_rdata),
    .rvfi_rs1_rdata(rvfi_rs1_rdata),
    .rvfi_rs2_rdata(rvfi_rs2_rdata),
    .rvfi_mem_rdata(rvfi_mem_rdata),
`ifdef RISCV_FORMAL_CSR_MISA
    .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata),
    .spec_csr_misa_rmask(spec_insn_andn_csr_misa_rmask),
`endif
    .spec_valid(spec_insn_andn_valid),
    .spec_trap(spec_insn_andn_trap),
    .spec_rs1_addr(spec_insn_andn_rs1_addr),
    .spec_rs2_addr(spec_insn_andn_rs2_addr),
    .spec_rd_addr(spec_insn_andn_rd_addr),
    .spec_rd_wdata(spec_insn_andn_rd_wdata),
    .spec_pc_wdata(spec_insn_andn_pc_wdata),
    .spec_mem_addr(spec_insn_andn_mem_addr),
    .spec_mem_rmask(spec_insn_andn_mem_rmask),
    .spec_mem_wmask(spec_insn_andn_mem_wmask),
    .spec_mem_wdata(spec_insn_andn_mem_wdata)
  );

  wire                                spec_insn_auipc_valid;
  wire                                spec_insn_auipc_trap;
  wire [                       4 : 0] spec_insn_auipc_rs1_addr;
  wire [                       4 : 0] spec_insn_auipc_rs2_addr;
  wire [                       4 : 0] spec_insn_auipc_rd_addr;
  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_auipc_rd_wdata;
  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_auipc_pc_wdata;
  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_auipc_mem_addr;
  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_auipc_mem_rmask;
  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_auipc_mem_wmask;
  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_auipc_mem_wdata;
`ifdef RISCV_FORMAL_CSR_MISA
  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_auipc_csr_misa_rmask;
`endif

  rvfi_insn_auipc insn_auipc (
    .rvfi_valid(rvfi_valid),
    .rvfi_insn(rvfi_insn),
    .rvfi_pc_rdata(rvfi_pc_rdata),
    .rvfi_rs1_rdata(rvfi_rs1_rdata),
    .rvfi_rs2_rdata(rvfi_rs2_rdata),
    .rvfi_mem_rdata(rvfi_mem_rdata),
`ifdef RISCV_FORMAL_CSR_MISA
    .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata),
    .spec_csr_misa_rmask(spec_insn_auipc_csr_misa_rmask),
`endif
    .spec_valid(spec_insn_auipc_valid),
    .spec_trap(spec_insn_auipc_trap),
    .spec_rs1_addr(spec_insn_auipc_rs1_addr),
    .spec_rs2_addr(spec_insn_auipc_rs2_addr),
    .spec_rd_addr(spec_insn_auipc_rd_addr),
    .spec_rd_wdata(spec_insn_auipc_rd_wdata),
    .spec_pc_wdata(spec_insn_auipc_pc_wdata),
    .spec_mem_addr(spec_insn_auipc_mem_addr),
    .spec_mem_rmask(spec_insn_auipc_mem_rmask),
    .spec_mem_wmask(spec_insn_auipc_mem_wmask),
    .spec_mem_wdata(spec_insn_auipc_mem_wdata)
  );

  wire                                spec_insn_bclr_valid;
  wire                                spec_insn_bclr_trap;
  wire [                       4 : 0] spec_insn_bclr_rs1_addr;
  wire [                       4 : 0] spec_insn_bclr_rs2_addr;
  wire [                       4 : 0] spec_insn_bclr_rd_addr;
  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_bclr_rd_wdata;
  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_bclr_pc_wdata;
  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_bclr_mem_addr;
  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_bclr_mem_rmask;
  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_bclr_mem_wmask;
  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_bclr_mem_wdata;
`ifdef RISCV_FORMAL_CSR_MISA
  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_bclr_csr_misa_rmask;
`endif

  rvfi_insn_bclr insn_bclr (
    .rvfi_valid(rvfi_valid),
    .rvfi_insn(rvfi_insn),
    .rvfi_pc_rdata(rvfi_pc_rdata),
    .rvfi_rs1_rdata(rvfi_rs1_rdata),
    .rvfi_rs2_rdata(rvfi_rs2_rdata),
    .rvfi_mem_rdata(rvfi_mem_rdata),
`ifdef RISCV_FORMAL_CSR_MISA
    .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata),
    .spec_csr_misa_rmask(spec_insn_bclr_csr_misa_rmask),
`endif
    .spec_valid(spec_insn_bclr_valid),
    .spec_trap(spec_insn_bclr_trap),
    .spec_rs1_addr(spec_insn_bclr_rs1_addr),
    .spec_rs2_addr(spec_insn_bclr_rs2_addr),
    .spec_rd_addr(spec_insn_bclr_rd_addr),
    .spec_rd_wdata(spec_insn_bclr_rd_wdata),
    .spec_pc_wdata(spec_insn_bclr_pc_wdata),
    .spec_mem_addr(spec_insn_bclr_mem_addr),
    .spec_mem_rmask(spec_insn_bclr_mem_rmask),
    .spec_mem_wmask(spec_insn_bclr_mem_wmask),
    .spec_mem_wdata(spec_insn_bclr_mem_wdata)
  );

  wire                                spec_insn_bclri_valid;
  wire                                spec_insn_bclri_trap;
  wire [                       4 : 0] spec_insn_bclri_rs1_addr;
  wire [                       4 : 0] spec_insn_bclri_rs2_addr;
  wire [                       4 : 0] spec_insn_bclri_rd_addr;
  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_bclri_rd_wdata;
  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_bclri_pc_wdata;
  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_bclri_mem_addr;
  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_bclri_mem_rmask;
  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_bclri_mem_wmask;
  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_bclri_mem_wdata;
`ifdef RISCV_FORMAL_CSR_MISA
  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_bclri_csr_misa_rmask;
`endif

  rvfi_insn_bclri insn_bclri (
    .rvfi_valid(rvfi_valid),
    .rvfi_insn(rvfi_insn),
    .rvfi_pc_rdata(rvfi_pc_rdata),
    .rvfi_rs1_rdata(rvfi_rs1_rdata),
    .rvfi_rs2_rdata(rvfi_rs2_rdata),
    .rvfi_mem_rdata(rvfi_mem_rdata),
`ifdef RISCV_FORMAL_CSR_MISA
    .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata),
    .spec_csr_misa_rmask(spec_insn_bclri_csr_misa_rmask),
`endif
    .spec_valid(spec_insn_bclri_valid),
    .spec_trap(spec_insn_bclri_trap),
    .spec_rs1_addr(spec_insn_bclri_rs1_addr),
    .spec_rs2_addr(spec_insn_bclri_rs2_addr),
    .spec_rd_addr(spec_insn_bclri_rd_addr),
    .spec_rd_wdata(spec_insn_bclri_rd_wdata),
    .spec_pc_wdata(spec_insn_bclri_pc_wdata),
    .spec_mem_addr(spec_insn_bclri_mem_addr),
    .spec_mem_rmask(spec_insn_bclri_mem_rmask),
    .spec_mem_wmask(spec_insn_bclri_mem_wmask),
    .spec_mem_wdata(spec_insn_bclri_mem_wdata)
  );

  wire                                spec_insn_beq_valid;
  wire                                spec_insn_beq_trap;
  wire [                       4 : 0] spec_insn_beq_rs1_addr;
  wire [                       4 : 0] spec_insn_beq_rs2_addr;
  wire [                       4 : 0] spec_insn_beq_rd_addr;
  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_beq_rd_wdata;
  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_beq_pc_wdata;
  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_beq_mem_addr;
  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_beq_mem_rmask;
  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_beq_mem_wmask;
  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_beq_mem_wdata;
`ifdef RISCV_FORMAL_CSR_MISA
  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_beq_csr_misa_rmask;
`endif

  rvfi_insn_beq insn_beq (
    .rvfi_valid(rvfi_valid),
    .rvfi_insn(rvfi_insn),
    .rvfi_pc_rdata(rvfi_pc_rdata),
    .rvfi_rs1_rdata(rvfi_rs1_rdata),
    .rvfi_rs2_rdata(rvfi_rs2_rdata),
    .rvfi_mem_rdata(rvfi_mem_rdata),
`ifdef RISCV_FORMAL_CSR_MISA
    .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata),
    .spec_csr_misa_rmask(spec_insn_beq_csr_misa_rmask),
`endif
    .spec_valid(spec_insn_beq_valid),
    .spec_trap(spec_insn_beq_trap),
    .spec_rs1_addr(spec_insn_beq_rs1_addr),
    .spec_rs2_addr(spec_insn_beq_rs2_addr),
    .spec_rd_addr(spec_insn_beq_rd_addr),
    .spec_rd_wdata(spec_insn_beq_rd_wdata),
    .spec_pc_wdata(spec_insn_beq_pc_wdata),
    .spec_mem_addr(spec_insn_beq_mem_addr),
    .spec_mem_rmask(spec_insn_beq_mem_rmask),
    .spec_mem_wmask(spec_insn_beq_mem_wmask),
    .spec_mem_wdata(spec_insn_beq_mem_wdata)
  );

  wire                                spec_insn_bext_valid;
  wire                                spec_insn_bext_trap;
  wire [                       4 : 0] spec_insn_bext_rs1_addr;
  wire [                       4 : 0] spec_insn_bext_rs2_addr;
  wire [                       4 : 0] spec_insn_bext_rd_addr;
  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_bext_rd_wdata;
  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_bext_pc_wdata;
  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_bext_mem_addr;
  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_bext_mem_rmask;
  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_bext_mem_wmask;
  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_bext_mem_wdata;
`ifdef RISCV_FORMAL_CSR_MISA
  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_bext_csr_misa_rmask;
`endif

  rvfi_insn_bext insn_bext (
    .rvfi_valid(rvfi_valid),
    .rvfi_insn(rvfi_insn),
    .rvfi_pc_rdata(rvfi_pc_rdata),
    .rvfi_rs1_rdata(rvfi_rs1_rdata),
    .rvfi_rs2_rdata(rvfi_rs2_rdata),
    .rvfi_mem_rdata(rvfi_mem_rdata),
`ifdef RISCV_FORMAL_CSR_MISA
    .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata),
    .spec_csr_misa_rmask(spec_insn_bext_csr_misa_rmask),
`endif
    .spec_valid(spec_insn_bext_valid),
    .spec_trap(spec_insn_bext_trap),
    .spec_rs1_addr(spec_insn_bext_rs1_addr),
    .spec_rs2_addr(spec_insn_bext_rs2_addr),
    .spec_rd_addr(spec_insn_bext_rd_addr),
    .spec_rd_wdata(spec_insn_bext_rd_wdata),
    .spec_pc_wdata(spec_insn_bext_pc_wdata),
    .spec_mem_addr(spec_insn_bext_mem_addr),
    .spec_mem_rmask(spec_insn_bext_mem_rmask),
    .spec_mem_wmask(spec_insn_bext_mem_wmask),
    .spec_mem_wdata(spec_insn_bext_mem_wdata)
  );

  wire                                spec_insn_bexti_valid;
  wire                                spec_insn_bexti_trap;
  wire [                       4 : 0] spec_insn_bexti_rs1_addr;
  wire [                       4 : 0] spec_insn_bexti_rs2_addr;
  wire [                       4 : 0] spec_insn_bexti_rd_addr;
  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_bexti_rd_wdata;
  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_bexti_pc_wdata;
  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_bexti_mem_addr;
  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_bexti_mem_rmask;
  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_bexti_mem_wmask;
  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_bexti_mem_wdata;
`ifdef RISCV_FORMAL_CSR_MISA
  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_bexti_csr_misa_rmask;
`endif

  rvfi_insn_bexti insn_bexti (
    .rvfi_valid(rvfi_valid),
    .rvfi_insn(rvfi_insn),
    .rvfi_pc_rdata(rvfi_pc_rdata),
    .rvfi_rs1_rdata(rvfi_rs1_rdata),
    .rvfi_rs2_rdata(rvfi_rs2_rdata),
    .rvfi_mem_rdata(rvfi_mem_rdata),
`ifdef RISCV_FORMAL_CSR_MISA
    .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata),
    .spec_csr_misa_rmask(spec_insn_bexti_csr_misa_rmask),
`endif
    .spec_valid(spec_insn_bexti_valid),
    .spec_trap(spec_insn_bexti_trap),
    .spec_rs1_addr(spec_insn_bexti_rs1_addr),
    .spec_rs2_addr(spec_insn_bexti_rs2_addr),
    .spec_rd_addr(spec_insn_bexti_rd_addr),
    .spec_rd_wdata(spec_insn_bexti_rd_wdata),
    .spec_pc_wdata(spec_insn_bexti_pc_wdata),
    .spec_mem_addr(spec_insn_bexti_mem_addr),
    .spec_mem_rmask(spec_insn_bexti_mem_rmask),
    .spec_mem_wmask(spec_insn_bexti_mem_wmask),
    .spec_mem_wdata(spec_insn_bexti_mem_wdata)
  );

  wire                                spec_insn_bge_valid;
  wire                                spec_insn_bge_trap;
  wire [                       4 : 0] spec_insn_bge_rs1_addr;
  wire [                       4 : 0] spec_insn_bge_rs2_addr;
  wire [                       4 : 0] spec_insn_bge_rd_addr;
  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_bge_rd_wdata;
  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_bge_pc_wdata;
  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_bge_mem_addr;
  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_bge_mem_rmask;
  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_bge_mem_wmask;
  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_bge_mem_wdata;
`ifdef RISCV_FORMAL_CSR_MISA
  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_bge_csr_misa_rmask;
`endif

  rvfi_insn_bge insn_bge (
    .rvfi_valid(rvfi_valid),
    .rvfi_insn(rvfi_insn),
    .rvfi_pc_rdata(rvfi_pc_rdata),
    .rvfi_rs1_rdata(rvfi_rs1_rdata),
    .rvfi_rs2_rdata(rvfi_rs2_rdata),
    .rvfi_mem_rdata(rvfi_mem_rdata),
`ifdef RISCV_FORMAL_CSR_MISA
    .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata),
    .spec_csr_misa_rmask(spec_insn_bge_csr_misa_rmask),
`endif
    .spec_valid(spec_insn_bge_valid),
    .spec_trap(spec_insn_bge_trap),
    .spec_rs1_addr(spec_insn_bge_rs1_addr),
    .spec_rs2_addr(spec_insn_bge_rs2_addr),
    .spec_rd_addr(spec_insn_bge_rd_addr),
    .spec_rd_wdata(spec_insn_bge_rd_wdata),
    .spec_pc_wdata(spec_insn_bge_pc_wdata),
    .spec_mem_addr(spec_insn_bge_mem_addr),
    .spec_mem_rmask(spec_insn_bge_mem_rmask),
    .spec_mem_wmask(spec_insn_bge_mem_wmask),
    .spec_mem_wdata(spec_insn_bge_mem_wdata)
  );

  wire                                spec_insn_bgeu_valid;
  wire                                spec_insn_bgeu_trap;
  wire [                       4 : 0] spec_insn_bgeu_rs1_addr;
  wire [                       4 : 0] spec_insn_bgeu_rs2_addr;
  wire [                       4 : 0] spec_insn_bgeu_rd_addr;
  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_bgeu_rd_wdata;
  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_bgeu_pc_wdata;
  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_bgeu_mem_addr;
  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_bgeu_mem_rmask;
  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_bgeu_mem_wmask;
  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_bgeu_mem_wdata;
`ifdef RISCV_FORMAL_CSR_MISA
  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_bgeu_csr_misa_rmask;
`endif

  rvfi_insn_bgeu insn_bgeu (
    .rvfi_valid(rvfi_valid),
    .rvfi_insn(rvfi_insn),
    .rvfi_pc_rdata(rvfi_pc_rdata),
    .rvfi_rs1_rdata(rvfi_rs1_rdata),
    .rvfi_rs2_rdata(rvfi_rs2_rdata),
    .rvfi_mem_rdata(rvfi_mem_rdata),
`ifdef RISCV_FORMAL_CSR_MISA
    .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata),
    .spec_csr_misa_rmask(spec_insn_bgeu_csr_misa_rmask),
`endif
    .spec_valid(spec_insn_bgeu_valid),
    .spec_trap(spec_insn_bgeu_trap),
    .spec_rs1_addr(spec_insn_bgeu_rs1_addr),
    .spec_rs2_addr(spec_insn_bgeu_rs2_addr),
    .spec_rd_addr(spec_insn_bgeu_rd_addr),
    .spec_rd_wdata(spec_insn_bgeu_rd_wdata),
    .spec_pc_wdata(spec_insn_bgeu_pc_wdata),
    .spec_mem_addr(spec_insn_bgeu_mem_addr),
    .spec_mem_rmask(spec_insn_bgeu_mem_rmask),
    .spec_mem_wmask(spec_insn_bgeu_mem_wmask),
    .spec_mem_wdata(spec_insn_bgeu_mem_wdata)
  );

  wire                                spec_insn_binv_valid;
  wire                                spec_insn_binv_trap;
  wire [                       4 : 0] spec_insn_binv_rs1_addr;
  wire [                       4 : 0] spec_insn_binv_rs2_addr;
  wire [                       4 : 0] spec_insn_binv_rd_addr;
  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_binv_rd_wdata;
  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_binv_pc_wdata;
  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_binv_mem_addr;
  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_binv_mem_rmask;
  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_binv_mem_wmask;
  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_binv_mem_wdata;
`ifdef RISCV_FORMAL_CSR_MISA
  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_binv_csr_misa_rmask;
`endif

  rvfi_insn_binv insn_binv (
    .rvfi_valid(rvfi_valid),
    .rvfi_insn(rvfi_insn),
    .rvfi_pc_rdata(rvfi_pc_rdata),
    .rvfi_rs1_rdata(rvfi_rs1_rdata),
    .rvfi_rs2_rdata(rvfi_rs2_rdata),
    .rvfi_mem_rdata(rvfi_mem_rdata),
`ifdef RISCV_FORMAL_CSR_MISA
    .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata),
    .spec_csr_misa_rmask(spec_insn_binv_csr_misa_rmask),
`endif
    .spec_valid(spec_insn_binv_valid),
    .spec_trap(spec_insn_binv_trap),
    .spec_rs1_addr(spec_insn_binv_rs1_addr),
    .spec_rs2_addr(spec_insn_binv_rs2_addr),
    .spec_rd_addr(spec_insn_binv_rd_addr),
    .spec_rd_wdata(spec_insn_binv_rd_wdata),
    .spec_pc_wdata(spec_insn_binv_pc_wdata),
    .spec_mem_addr(spec_insn_binv_mem_addr),
    .spec_mem_rmask(spec_insn_binv_mem_rmask),
    .spec_mem_wmask(spec_insn_binv_mem_wmask),
    .spec_mem_wdata(spec_insn_binv_mem_wdata)
  );

  wire                                spec_insn_binvi_valid;
  wire                                spec_insn_binvi_trap;
  wire [                       4 : 0] spec_insn_binvi_rs1_addr;
  wire [                       4 : 0] spec_insn_binvi_rs2_addr;
  wire [                       4 : 0] spec_insn_binvi_rd_addr;
  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_binvi_rd_wdata;
  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_binvi_pc_wdata;
  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_binvi_mem_addr;
  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_binvi_mem_rmask;
  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_binvi_mem_wmask;
  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_binvi_mem_wdata;
`ifdef RISCV_FORMAL_CSR_MISA
  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_binvi_csr_misa_rmask;
`endif

  rvfi_insn_binvi insn_binvi (
    .rvfi_valid(rvfi_valid),
    .rvfi_insn(rvfi_insn),
    .rvfi_pc_rdata(rvfi_pc_rdata),
    .rvfi_rs1_rdata(rvfi_rs1_rdata),
    .rvfi_rs2_rdata(rvfi_rs2_rdata),
    .rvfi_mem_rdata(rvfi_mem_rdata),
`ifdef RISCV_FORMAL_CSR_MISA
    .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata),
    .spec_csr_misa_rmask(spec_insn_binvi_csr_misa_rmask),
`endif
    .spec_valid(spec_insn_binvi_valid),
    .spec_trap(spec_insn_binvi_trap),
    .spec_rs1_addr(spec_insn_binvi_rs1_addr),
    .spec_rs2_addr(spec_insn_binvi_rs2_addr),
    .spec_rd_addr(spec_insn_binvi_rd_addr),
    .spec_rd_wdata(spec_insn_binvi_rd_wdata),
    .spec_pc_wdata(spec_insn_binvi_pc_wdata),
    .spec_mem_addr(spec_insn_binvi_mem_addr),
    .spec_mem_rmask(spec_insn_binvi_mem_rmask),
    .spec_mem_wmask(spec_insn_binvi_mem_wmask),
    .spec_mem_wdata(spec_insn_binvi_mem_wdata)
  );

  wire                                spec_insn_blt_valid;
  wire                                spec_insn_blt_trap;
  wire [                       4 : 0] spec_insn_blt_rs1_addr;
  wire [                       4 : 0] spec_insn_blt_rs2_addr;
  wire [                       4 : 0] spec_insn_blt_rd_addr;
  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_blt_rd_wdata;
  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_blt_pc_wdata;
  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_blt_mem_addr;
  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_blt_mem_rmask;
  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_blt_mem_wmask;
  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_blt_mem_wdata;
`ifdef RISCV_FORMAL_CSR_MISA
  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_blt_csr_misa_rmask;
`endif

  rvfi_insn_blt insn_blt (
    .rvfi_valid(rvfi_valid),
    .rvfi_insn(rvfi_insn),
    .rvfi_pc_rdata(rvfi_pc_rdata),
    .rvfi_rs1_rdata(rvfi_rs1_rdata),
    .rvfi_rs2_rdata(rvfi_rs2_rdata),
    .rvfi_mem_rdata(rvfi_mem_rdata),
`ifdef RISCV_FORMAL_CSR_MISA
    .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata),
    .spec_csr_misa_rmask(spec_insn_blt_csr_misa_rmask),
`endif
    .spec_valid(spec_insn_blt_valid),
    .spec_trap(spec_insn_blt_trap),
    .spec_rs1_addr(spec_insn_blt_rs1_addr),
    .spec_rs2_addr(spec_insn_blt_rs2_addr),
    .spec_rd_addr(spec_insn_blt_rd_addr),
    .spec_rd_wdata(spec_insn_blt_rd_wdata),
    .spec_pc_wdata(spec_insn_blt_pc_wdata),
    .spec_mem_addr(spec_insn_blt_mem_addr),
    .spec_mem_rmask(spec_insn_blt_mem_rmask),
    .spec_mem_wmask(spec_insn_blt_mem_wmask),
    .spec_mem_wdata(spec_insn_blt_mem_wdata)
  );

  wire                                spec_insn_bltu_valid;
  wire                                spec_insn_bltu_trap;
  wire [                       4 : 0] spec_insn_bltu_rs1_addr;
  wire [                       4 : 0] spec_insn_bltu_rs2_addr;
  wire [                       4 : 0] spec_insn_bltu_rd_addr;
  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_bltu_rd_wdata;
  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_bltu_pc_wdata;
  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_bltu_mem_addr;
  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_bltu_mem_rmask;
  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_bltu_mem_wmask;
  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_bltu_mem_wdata;
`ifdef RISCV_FORMAL_CSR_MISA
  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_bltu_csr_misa_rmask;
`endif

  rvfi_insn_bltu insn_bltu (
    .rvfi_valid(rvfi_valid),
    .rvfi_insn(rvfi_insn),
    .rvfi_pc_rdata(rvfi_pc_rdata),
    .rvfi_rs1_rdata(rvfi_rs1_rdata),
    .rvfi_rs2_rdata(rvfi_rs2_rdata),
    .rvfi_mem_rdata(rvfi_mem_rdata),
`ifdef RISCV_FORMAL_CSR_MISA
    .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata),
    .spec_csr_misa_rmask(spec_insn_bltu_csr_misa_rmask),
`endif
    .spec_valid(spec_insn_bltu_valid),
    .spec_trap(spec_insn_bltu_trap),
    .spec_rs1_addr(spec_insn_bltu_rs1_addr),
    .spec_rs2_addr(spec_insn_bltu_rs2_addr),
    .spec_rd_addr(spec_insn_bltu_rd_addr),
    .spec_rd_wdata(spec_insn_bltu_rd_wdata),
    .spec_pc_wdata(spec_insn_bltu_pc_wdata),
    .spec_mem_addr(spec_insn_bltu_mem_addr),
    .spec_mem_rmask(spec_insn_bltu_mem_rmask),
    .spec_mem_wmask(spec_insn_bltu_mem_wmask),
    .spec_mem_wdata(spec_insn_bltu_mem_wdata)
  );

  wire                                spec_insn_bne_valid;
  wire                                spec_insn_bne_trap;
  wire [                       4 : 0] spec_insn_bne_rs1_addr;
  wire [                       4 : 0] spec_insn_bne_rs2_addr;
  wire [                       4 : 0] spec_insn_bne_rd_addr;
  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_bne_rd_wdata;
  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_bne_pc_wdata;
  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_bne_mem_addr;
  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_bne_mem_rmask;
  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_bne_mem_wmask;
  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_bne_mem_wdata;
`ifdef RISCV_FORMAL_CSR_MISA
  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_bne_csr_misa_rmask;
`endif

  rvfi_insn_bne insn_bne (
    .rvfi_valid(rvfi_valid),
    .rvfi_insn(rvfi_insn),
    .rvfi_pc_rdata(rvfi_pc_rdata),
    .rvfi_rs1_rdata(rvfi_rs1_rdata),
    .rvfi_rs2_rdata(rvfi_rs2_rdata),
    .rvfi_mem_rdata(rvfi_mem_rdata),
`ifdef RISCV_FORMAL_CSR_MISA
    .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata),
    .spec_csr_misa_rmask(spec_insn_bne_csr_misa_rmask),
`endif
    .spec_valid(spec_insn_bne_valid),
    .spec_trap(spec_insn_bne_trap),
    .spec_rs1_addr(spec_insn_bne_rs1_addr),
    .spec_rs2_addr(spec_insn_bne_rs2_addr),
    .spec_rd_addr(spec_insn_bne_rd_addr),
    .spec_rd_wdata(spec_insn_bne_rd_wdata),
    .spec_pc_wdata(spec_insn_bne_pc_wdata),
    .spec_mem_addr(spec_insn_bne_mem_addr),
    .spec_mem_rmask(spec_insn_bne_mem_rmask),
    .spec_mem_wmask(spec_insn_bne_mem_wmask),
    .spec_mem_wdata(spec_insn_bne_mem_wdata)
  );

  wire                                spec_insn_bset_valid;
  wire                                spec_insn_bset_trap;
  wire [                       4 : 0] spec_insn_bset_rs1_addr;
  wire [                       4 : 0] spec_insn_bset_rs2_addr;
  wire [                       4 : 0] spec_insn_bset_rd_addr;
  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_bset_rd_wdata;
  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_bset_pc_wdata;
  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_bset_mem_addr;
  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_bset_mem_rmask;
  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_bset_mem_wmask;
  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_bset_mem_wdata;
`ifdef RISCV_FORMAL_CSR_MISA
  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_bset_csr_misa_rmask;
`endif

  rvfi_insn_bset insn_bset (
    .rvfi_valid(rvfi_valid),
    .rvfi_insn(rvfi_insn),
    .rvfi_pc_rdata(rvfi_pc_rdata),
    .rvfi_rs1_rdata(rvfi_rs1_rdata),
    .rvfi_rs2_rdata(rvfi_rs2_rdata),
    .rvfi_mem_rdata(rvfi_mem_rdata),
`ifdef RISCV_FORMAL_CSR_MISA
    .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata),
    .spec_csr_misa_rmask(spec_insn_bset_csr_misa_rmask),
`endif
    .spec_valid(spec_insn_bset_valid),
    .spec_trap(spec_insn_bset_trap),
    .spec_rs1_addr(spec_insn_bset_rs1_addr),
    .spec_rs2_addr(spec_insn_bset_rs2_addr),
    .spec_rd_addr(spec_insn_bset_rd_addr),
    .spec_rd_wdata(spec_insn_bset_rd_wdata),
    .spec_pc_wdata(spec_insn_bset_pc_wdata),
    .spec_mem_addr(spec_insn_bset_mem_addr),
    .spec_mem_rmask(spec_insn_bset_mem_rmask),
    .spec_mem_wmask(spec_insn_bset_mem_wmask),
    .spec_mem_wdata(spec_insn_bset_mem_wdata)
  );

  wire                                spec_insn_bseti_valid;
  wire                                spec_insn_bseti_trap;
  wire [                       4 : 0] spec_insn_bseti_rs1_addr;
  wire [                       4 : 0] spec_insn_bseti_rs2_addr;
  wire [                       4 : 0] spec_insn_bseti_rd_addr;
  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_bseti_rd_wdata;
  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_bseti_pc_wdata;
  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_bseti_mem_addr;
  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_bseti_mem_rmask;
  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_bseti_mem_wmask;
  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_bseti_mem_wdata;
`ifdef RISCV_FORMAL_CSR_MISA
  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_bseti_csr_misa_rmask;
`endif

  rvfi_insn_bseti insn_bseti (
    .rvfi_valid(rvfi_valid),
    .rvfi_insn(rvfi_insn),
    .rvfi_pc_rdata(rvfi_pc_rdata),
    .rvfi_rs1_rdata(rvfi_rs1_rdata),
    .rvfi_rs2_rdata(rvfi_rs2_rdata),
    .rvfi_mem_rdata(rvfi_mem_rdata),
`ifdef RISCV_FORMAL_CSR_MISA
    .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata),
    .spec_csr_misa_rmask(spec_insn_bseti_csr_misa_rmask),
`endif
    .spec_valid(spec_insn_bseti_valid),
    .spec_trap(spec_insn_bseti_trap),
    .spec_rs1_addr(spec_insn_bseti_rs1_addr),
    .spec_rs2_addr(spec_insn_bseti_rs2_addr),
    .spec_rd_addr(spec_insn_bseti_rd_addr),
    .spec_rd_wdata(spec_insn_bseti_rd_wdata),
    .spec_pc_wdata(spec_insn_bseti_pc_wdata),
    .spec_mem_addr(spec_insn_bseti_mem_addr),
    .spec_mem_rmask(spec_insn_bseti_mem_rmask),
    .spec_mem_wmask(spec_insn_bseti_mem_wmask),
    .spec_mem_wdata(spec_insn_bseti_mem_wdata)
  );

  wire                                spec_insn_clz_valid;
  wire                                spec_insn_clz_trap;
  wire [                       4 : 0] spec_insn_clz_rs1_addr;
  wire [                       4 : 0] spec_insn_clz_rs2_addr;
  wire [                       4 : 0] spec_insn_clz_rd_addr;
  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_clz_rd_wdata;
  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_clz_pc_wdata;
  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_clz_mem_addr;
  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_clz_mem_rmask;
  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_clz_mem_wmask;
  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_clz_mem_wdata;
`ifdef RISCV_FORMAL_CSR_MISA
  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_clz_csr_misa_rmask;
`endif

  rvfi_insn_clz insn_clz (
    .rvfi_valid(rvfi_valid),
    .rvfi_insn(rvfi_insn),
    .rvfi_pc_rdata(rvfi_pc_rdata),
    .rvfi_rs1_rdata(rvfi_rs1_rdata),
    .rvfi_rs2_rdata(rvfi_rs2_rdata),
    .rvfi_mem_rdata(rvfi_mem_rdata),
`ifdef RISCV_FORMAL_CSR_MISA
    .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata),
    .spec_csr_misa_rmask(spec_insn_clz_csr_misa_rmask),
`endif
    .spec_valid(spec_insn_clz_valid),
    .spec_trap(spec_insn_clz_trap),
    .spec_rs1_addr(spec_insn_clz_rs1_addr),
    .spec_rs2_addr(spec_insn_clz_rs2_addr),
    .spec_rd_addr(spec_insn_clz_rd_addr),
    .spec_rd_wdata(spec_insn_clz_rd_wdata),
    .spec_pc_wdata(spec_insn_clz_pc_wdata),
    .spec_mem_addr(spec_insn_clz_mem_addr),
    .spec_mem_rmask(spec_insn_clz_mem_rmask),
    .spec_mem_wmask(spec_insn_clz_mem_wmask),
    .spec_mem_wdata(spec_insn_clz_mem_wdata)
  );

  wire                                spec_insn_clzw_valid;
  wire                                spec_insn_clzw_trap;
  wire [                       4 : 0] spec_insn_clzw_rs1_addr;
  wire [                       4 : 0] spec_insn_clzw_rs2_addr;
  wire [                       4 : 0] spec_insn_clzw_rd_addr;
  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_clzw_rd_wdata;
  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_clzw_pc_wdata;
  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_clzw_mem_addr;
  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_clzw_mem_rmask;
  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_clzw_mem_wmask;
  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_clzw_mem_wdata;
`ifdef RISCV_FORMAL_CSR_MISA
  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_clzw_csr_misa_rmask;
`endif

  rvfi_insn_clzw insn_clzw (
    .rvfi_valid(rvfi_valid),
    .rvfi_insn(rvfi_insn),
    .rvfi_pc_rdata(rvfi_pc_rdata),
    .rvfi_rs1_rdata(rvfi_rs1_rdata),
    .rvfi_rs2_rdata(rvfi_rs2_rdata),
    .rvfi_mem_rdata(rvfi_mem_rdata),
`ifdef RISCV_FORMAL_CSR_MISA
    .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata),
    .spec_csr_misa_rmask(spec_insn_clzw_csr_misa_rmask),
`endif
    .spec_valid(spec_insn_clzw_valid),
    .spec_trap(spec_insn_clzw_trap),
    .spec_rs1_addr(spec_insn_clzw_rs1_addr),
    .spec_rs2_addr(spec_insn_clzw_rs2_addr),
    .spec_rd_addr(spec_insn_clzw_rd_addr),
    .spec_rd_wdata(spec_insn_clzw_rd_wdata),
    .spec_pc_wdata(spec_insn_clzw_pc_wdata),
    .spec_mem_addr(spec_insn_clzw_mem_addr),
    .spec_mem_rmask(spec_insn_clzw_mem_rmask),
    .spec_mem_wmask(spec_insn_clzw_mem_wmask),
    .spec_mem_wdata(spec_insn_clzw_mem_wdata)
  );

  wire                                spec_insn_cpop_valid;
  wire                                spec_insn_cpop_trap;
  wire [                       4 : 0] spec_insn_cpop_rs1_addr;
  wire [                       4 : 0] spec_insn_cpop_rs2_addr;
  wire [                       4 : 0] spec_insn_cpop_rd_addr;
  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_cpop_rd_wdata;
  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_cpop_pc_wdata;
  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_cpop_mem_addr;
  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_cpop_mem_rmask;
  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_cpop_mem_wmask;
  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_cpop_mem_wdata;
`ifdef RISCV_FORMAL_CSR_MISA
  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_cpop_csr_misa_rmask;
`endif

  rvfi_insn_cpop insn_cpop (
    .rvfi_valid(rvfi_valid),
    .rvfi_insn(rvfi_insn),
    .rvfi_pc_rdata(rvfi_pc_rdata),
    .rvfi_rs1_rdata(rvfi_rs1_rdata),
    .rvfi_rs2_rdata(rvfi_rs2_rdata),
    .rvfi_mem_rdata(rvfi_mem_rdata),
`ifdef RISCV_FORMAL_CSR_MISA
    .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata),
    .spec_csr_misa_rmask(spec_insn_cpop_csr_misa_rmask),
`endif
    .spec_valid(spec_insn_cpop_valid),
    .spec_trap(spec_insn_cpop_trap),
    .spec_rs1_addr(spec_insn_cpop_rs1_addr),
    .spec_rs2_addr(spec_insn_cpop_rs2_addr),
    .spec_rd_addr(spec_insn_cpop_rd_addr),
    .spec_rd_wdata(spec_insn_cpop_rd_wdata),
    .spec_pc_wdata(spec_insn_cpop_pc_wdata),
    .spec_mem_addr(spec_insn_cpop_mem_addr),
    .spec_mem_rmask(spec_insn_cpop_mem_rmask),
    .spec_mem_wmask(spec_insn_cpop_mem_wmask),
    .spec_mem_wdata(spec_insn_cpop_mem_wdata)
  );

  wire                                spec_insn_cpopw_valid;
  wire                                spec_insn_cpopw_trap;
  wire [                       4 : 0] spec_insn_cpopw_rs1_addr;
  wire [                       4 : 0] spec_insn_cpopw_rs2_addr;
  wire [                       4 : 0] spec_insn_cpopw_rd_addr;
  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_cpopw_rd_wdata;
  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_cpopw_pc_wdata;
  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_cpopw_mem_addr;
  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_cpopw_mem_rmask;
  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_cpopw_mem_wmask;
  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_cpopw_mem_wdata;
`ifdef RISCV_FORMAL_CSR_MISA
  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_cpopw_csr_misa_rmask;
`endif

  rvfi_insn_cpopw insn_cpopw (
    .rvfi_valid(rvfi_valid),
    .rvfi_insn(rvfi_insn),
    .rvfi_pc_rdata(rvfi_pc_rdata),
    .rvfi_rs1_rdata(rvfi_rs1_rdata),
    .rvfi_rs2_rdata(rvfi_rs2_rdata),
    .rvfi_mem_rdata(rvfi_mem_rdata),
`ifdef RISCV_FORMAL_CSR_MISA
    .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata),
    .spec_csr_misa_rmask(spec_insn_cpopw_csr_misa_rmask),
`endif
    .spec_valid(spec_insn_cpopw_valid),
    .spec_trap(spec_insn_cpopw_trap),
    .spec_rs1_addr(spec_insn_cpopw_rs1_addr),
    .spec_rs2_addr(spec_insn_cpopw_rs2_addr),
    .spec_rd_addr(spec_insn_cpopw_rd_addr),
    .spec_rd_wdata(spec_insn_cpopw_rd_wdata),
    .spec_pc_wdata(spec_insn_cpopw_pc_wdata),
    .spec_mem_addr(spec_insn_cpopw_mem_addr),
    .spec_mem_rmask(spec_insn_cpopw_mem_rmask),
    .spec_mem_wmask(spec_insn_cpopw_mem_wmask),
    .spec_mem_wdata(spec_insn_cpopw_mem_wdata)
  );

  wire                                spec_insn_ctz_valid;
  wire                                spec_insn_ctz_trap;
  wire [                       4 : 0] spec_insn_ctz_rs1_addr;
  wire [                       4 : 0] spec_insn_ctz_rs2_addr;
  wire [                       4 : 0] spec_insn_ctz_rd_addr;
  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_ctz_rd_wdata;
  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_ctz_pc_wdata;
  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_ctz_mem_addr;
  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_ctz_mem_rmask;
  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_ctz_mem_wmask;
  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_ctz_mem_wdata;
`ifdef RISCV_FORMAL_CSR_MISA
  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_ctz_csr_misa_rmask;
`endif

  rvfi_insn_ctz insn_ctz (
    .rvfi_valid(rvfi_valid),
    .rvfi_insn(rvfi_insn),
    .rvfi_pc_rdata(rvfi_pc_rdata),
    .rvfi_rs1_rdata(rvfi_rs1_rdata),
    .rvfi_rs2_rdata(rvfi_rs2_rdata),
    .rvfi_mem_rdata(rvfi_mem_rdata),
`ifdef RISCV_FORMAL_CSR_MISA
    .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata),
    .spec_csr_misa_rmask(spec_insn_ctz_csr_misa_rmask),
`endif
    .spec_valid(spec_insn_ctz_valid),
    .spec_trap(spec_insn_ctz_trap),
    .spec_rs1_addr(spec_insn_ctz_rs1_addr),
    .spec_rs2_addr(spec_insn_ctz_rs2_addr),
    .spec_rd_addr(spec_insn_ctz_rd_addr),
    .spec_rd_wdata(spec_insn_ctz_rd_wdata),
    .spec_pc_wdata(spec_insn_ctz_pc_wdata),
    .spec_mem_addr(spec_insn_ctz_mem_addr),
    .spec_mem_rmask(spec_insn_ctz_mem_rmask),
    .spec_mem_wmask(spec_insn_ctz_mem_wmask),
    .spec_mem_wdata(spec_insn_ctz_mem_wdata)
  );

  wire                                spec_insn_ctzw_valid;
  wire                                spec_insn_ctzw_trap;
  wire [                       4 : 0] spec_insn_ctzw_rs1_addr;
  wire [                       4 : 0] spec_insn_ctzw_rs2_addr;
  wire [                       4 : 0] spec_insn_ctzw_rd_addr;
  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_ctzw_rd_wdata;
  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_ctzw_pc_wdata;
  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_ctzw_mem_addr;
  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_ctzw_mem_rmask;
  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_ctzw_mem_wmask;
  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_ctzw_mem_wdata;
`ifdef RISCV_FORMAL_CSR_MISA
  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_ctzw_csr_misa_rmask;
`endif

  rvfi_insn_ctzw insn_ctzw (
    .rvfi_valid(rvfi_valid),
    .rvfi_insn(rvfi_insn),
    .rvfi_pc_rdata(rvfi_pc_rdata),
    .rvfi_rs1_rdata(rvfi_rs1_rdata),
    .rvfi_rs2_rdata(rvfi_rs2_rdata),
    .rvfi_mem_rdata(rvfi_mem_rdata),
`ifdef RISCV_FORMAL_CSR_MISA
    .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata),
    .spec_csr_misa_rmask(spec_insn_ctzw_csr_misa_rmask),
`endif
    .spec_valid(spec_insn_ctzw_valid),
    .spec_trap(spec_insn_ctzw_trap),
    .spec_rs1_addr(spec_insn_ctzw_rs1_addr),
    .spec_rs2_addr(spec_insn_ctzw_rs2_addr),
    .spec_rd_addr(spec_insn_ctzw_rd_addr),
    .spec_rd_wdata(spec_insn_ctzw_rd_wdata),
    .spec_pc_wdata(spec_insn_ctzw_pc_wdata),
    .spec_mem_addr(spec_insn_ctzw_mem_addr),
    .spec_mem_rmask(spec_insn_ctzw_mem_rmask),
    .spec_mem_wmask(spec_insn_ctzw_mem_wmask),
    .spec_mem_wdata(spec_insn_ctzw_mem_wdata)
  );

  wire                                spec_insn_jal_valid;
  wire                                spec_insn_jal_trap;
  wire [                       4 : 0] spec_insn_jal_rs1_addr;
  wire [                       4 : 0] spec_insn_jal_rs2_addr;
  wire [                       4 : 0] spec_insn_jal_rd_addr;
  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_jal_rd_wdata;
  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_jal_pc_wdata;
  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_jal_mem_addr;
  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_jal_mem_rmask;
  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_jal_mem_wmask;
  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_jal_mem_wdata;
`ifdef RISCV_FORMAL_CSR_MISA
  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_jal_csr_misa_rmask;
`endif

  rvfi_insn_jal insn_jal (
    .rvfi_valid(rvfi_valid),
    .rvfi_insn(rvfi_insn),
    .rvfi_pc_rdata(rvfi_pc_rdata),
    .rvfi_rs1_rdata(rvfi_rs1_rdata),
    .rvfi_rs2_rdata(rvfi_rs2_rdata),
    .rvfi_mem_rdata(rvfi_mem_rdata),
`ifdef RISCV_FORMAL_CSR_MISA
    .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata),
    .spec_csr_misa_rmask(spec_insn_jal_csr_misa_rmask),
`endif
    .spec_valid(spec_insn_jal_valid),
    .spec_trap(spec_insn_jal_trap),
    .spec_rs1_addr(spec_insn_jal_rs1_addr),
    .spec_rs2_addr(spec_insn_jal_rs2_addr),
    .spec_rd_addr(spec_insn_jal_rd_addr),
    .spec_rd_wdata(spec_insn_jal_rd_wdata),
    .spec_pc_wdata(spec_insn_jal_pc_wdata),
    .spec_mem_addr(spec_insn_jal_mem_addr),
    .spec_mem_rmask(spec_insn_jal_mem_rmask),
    .spec_mem_wmask(spec_insn_jal_mem_wmask),
    .spec_mem_wdata(spec_insn_jal_mem_wdata)
  );

  wire                                spec_insn_jalr_valid;
  wire                                spec_insn_jalr_trap;
  wire [                       4 : 0] spec_insn_jalr_rs1_addr;
  wire [                       4 : 0] spec_insn_jalr_rs2_addr;
  wire [                       4 : 0] spec_insn_jalr_rd_addr;
  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_jalr_rd_wdata;
  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_jalr_pc_wdata;
  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_jalr_mem_addr;
  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_jalr_mem_rmask;
  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_jalr_mem_wmask;
  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_jalr_mem_wdata;
`ifdef RISCV_FORMAL_CSR_MISA
  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_jalr_csr_misa_rmask;
`endif

  rvfi_insn_jalr insn_jalr (
    .rvfi_valid(rvfi_valid),
    .rvfi_insn(rvfi_insn),
    .rvfi_pc_rdata(rvfi_pc_rdata),
    .rvfi_rs1_rdata(rvfi_rs1_rdata),
    .rvfi_rs2_rdata(rvfi_rs2_rdata),
    .rvfi_mem_rdata(rvfi_mem_rdata),
`ifdef RISCV_FORMAL_CSR_MISA
    .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata),
    .spec_csr_misa_rmask(spec_insn_jalr_csr_misa_rmask),
`endif
    .spec_valid(spec_insn_jalr_valid),
    .spec_trap(spec_insn_jalr_trap),
    .spec_rs1_addr(spec_insn_jalr_rs1_addr),
    .spec_rs2_addr(spec_insn_jalr_rs2_addr),
    .spec_rd_addr(spec_insn_jalr_rd_addr),
    .spec_rd_wdata(spec_insn_jalr_rd_wdata),
    .spec_pc_wdata(spec_insn_jalr_pc_wdata),
    .spec_mem_addr(spec_insn_jalr_mem_addr),
    .spec_mem_rmask(spec_insn_jalr_mem_rmask),
    .spec_mem_wmask(spec_insn_jalr_mem_wmask),
    .spec_mem_wdata(spec_insn_jalr_mem_wdata)
  );

  wire                                spec_insn_lb_valid;
  wire                                spec_insn_lb_trap;
  wire [                       4 : 0] spec_insn_lb_rs1_addr;
  wire [                       4 : 0] spec_insn_lb_rs2_addr;
  wire [                       4 : 0] spec_insn_lb_rd_addr;
  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_lb_rd_wdata;
  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_lb_pc_wdata;
  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_lb_mem_addr;
  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_lb_mem_rmask;
  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_lb_mem_wmask;
  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_lb_mem_wdata;
`ifdef RISCV_FORMAL_CSR_MISA
  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_lb_csr_misa_rmask;
`endif

  rvfi_insn_lb insn_lb (
    .rvfi_valid(rvfi_valid),
    .rvfi_insn(rvfi_insn),
    .rvfi_pc_rdata(rvfi_pc_rdata),
    .rvfi_rs1_rdata(rvfi_rs1_rdata),
    .rvfi_rs2_rdata(rvfi_rs2_rdata),
    .rvfi_mem_rdata(rvfi_mem_rdata),
`ifdef RISCV_FORMAL_CSR_MISA
    .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata),
    .spec_csr_misa_rmask(spec_insn_lb_csr_misa_rmask),
`endif
    .spec_valid(spec_insn_lb_valid),
    .spec_trap(spec_insn_lb_trap),
    .spec_rs1_addr(spec_insn_lb_rs1_addr),
    .spec_rs2_addr(spec_insn_lb_rs2_addr),
    .spec_rd_addr(spec_insn_lb_rd_addr),
    .spec_rd_wdata(spec_insn_lb_rd_wdata),
    .spec_pc_wdata(spec_insn_lb_pc_wdata),
    .spec_mem_addr(spec_insn_lb_mem_addr),
    .spec_mem_rmask(spec_insn_lb_mem_rmask),
    .spec_mem_wmask(spec_insn_lb_mem_wmask),
    .spec_mem_wdata(spec_insn_lb_mem_wdata)
  );

  wire                                spec_insn_lbu_valid;
  wire                                spec_insn_lbu_trap;
  wire [                       4 : 0] spec_insn_lbu_rs1_addr;
  wire [                       4 : 0] spec_insn_lbu_rs2_addr;
  wire [                       4 : 0] spec_insn_lbu_rd_addr;
  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_lbu_rd_wdata;
  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_lbu_pc_wdata;
  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_lbu_mem_addr;
  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_lbu_mem_rmask;
  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_lbu_mem_wmask;
  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_lbu_mem_wdata;
`ifdef RISCV_FORMAL_CSR_MISA
  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_lbu_csr_misa_rmask;
`endif

  rvfi_insn_lbu insn_lbu (
    .rvfi_valid(rvfi_valid),
    .rvfi_insn(rvfi_insn),
    .rvfi_pc_rdata(rvfi_pc_rdata),
    .rvfi_rs1_rdata(rvfi_rs1_rdata),
    .rvfi_rs2_rdata(rvfi_rs2_rdata),
    .rvfi_mem_rdata(rvfi_mem_rdata),
`ifdef RISCV_FORMAL_CSR_MISA
    .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata),
    .spec_csr_misa_rmask(spec_insn_lbu_csr_misa_rmask),
`endif
    .spec_valid(spec_insn_lbu_valid),
    .spec_trap(spec_insn_lbu_trap),
    .spec_rs1_addr(spec_insn_lbu_rs1_addr),
    .spec_rs2_addr(spec_insn_lbu_rs2_addr),
    .spec_rd_addr(spec_insn_lbu_rd_addr),
    .spec_rd_wdata(spec_insn_lbu_rd_wdata),
    .spec_pc_wdata(spec_insn_lbu_pc_wdata),
    .spec_mem_addr(spec_insn_lbu_mem_addr),
    .spec_mem_rmask(spec_insn_lbu_mem_rmask),
    .spec_mem_wmask(spec_insn_lbu_mem_wmask),
    .spec_mem_wdata(spec_insn_lbu_mem_wdata)
  );

  wire                                spec_insn_ld_valid;
  wire                                spec_insn_ld_trap;
  wire [                       4 : 0] spec_insn_ld_rs1_addr;
  wire [                       4 : 0] spec_insn_ld_rs2_addr;
  wire [                       4 : 0] spec_insn_ld_rd_addr;
  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_ld_rd_wdata;
  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_ld_pc_wdata;
  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_ld_mem_addr;
  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_ld_mem_rmask;
  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_ld_mem_wmask;
  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_ld_mem_wdata;
`ifdef RISCV_FORMAL_CSR_MISA
  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_ld_csr_misa_rmask;
`endif

  rvfi_insn_ld insn_ld (
    .rvfi_valid(rvfi_valid),
    .rvfi_insn(rvfi_insn),
    .rvfi_pc_rdata(rvfi_pc_rdata),
    .rvfi_rs1_rdata(rvfi_rs1_rdata),
    .rvfi_rs2_rdata(rvfi_rs2_rdata),
    .rvfi_mem_rdata(rvfi_mem_rdata),
`ifdef RISCV_FORMAL_CSR_MISA
    .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata),
    .spec_csr_misa_rmask(spec_insn_ld_csr_misa_rmask),
`endif
    .spec_valid(spec_insn_ld_valid),
    .spec_trap(spec_insn_ld_trap),
    .spec_rs1_addr(spec_insn_ld_rs1_addr),
    .spec_rs2_addr(spec_insn_ld_rs2_addr),
    .spec_rd_addr(spec_insn_ld_rd_addr),
    .spec_rd_wdata(spec_insn_ld_rd_wdata),
    .spec_pc_wdata(spec_insn_ld_pc_wdata),
    .spec_mem_addr(spec_insn_ld_mem_addr),
    .spec_mem_rmask(spec_insn_ld_mem_rmask),
    .spec_mem_wmask(spec_insn_ld_mem_wmask),
    .spec_mem_wdata(spec_insn_ld_mem_wdata)
  );

  wire                                spec_insn_lh_valid;
  wire                                spec_insn_lh_trap;
  wire [                       4 : 0] spec_insn_lh_rs1_addr;
  wire [                       4 : 0] spec_insn_lh_rs2_addr;
  wire [                       4 : 0] spec_insn_lh_rd_addr;
  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_lh_rd_wdata;
  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_lh_pc_wdata;
  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_lh_mem_addr;
  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_lh_mem_rmask;
  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_lh_mem_wmask;
  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_lh_mem_wdata;
`ifdef RISCV_FORMAL_CSR_MISA
  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_lh_csr_misa_rmask;
`endif

  rvfi_insn_lh insn_lh (
    .rvfi_valid(rvfi_valid),
    .rvfi_insn(rvfi_insn),
    .rvfi_pc_rdata(rvfi_pc_rdata),
    .rvfi_rs1_rdata(rvfi_rs1_rdata),
    .rvfi_rs2_rdata(rvfi_rs2_rdata),
    .rvfi_mem_rdata(rvfi_mem_rdata),
`ifdef RISCV_FORMAL_CSR_MISA
    .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata),
    .spec_csr_misa_rmask(spec_insn_lh_csr_misa_rmask),
`endif
    .spec_valid(spec_insn_lh_valid),
    .spec_trap(spec_insn_lh_trap),
    .spec_rs1_addr(spec_insn_lh_rs1_addr),
    .spec_rs2_addr(spec_insn_lh_rs2_addr),
    .spec_rd_addr(spec_insn_lh_rd_addr),
    .spec_rd_wdata(spec_insn_lh_rd_wdata),
    .spec_pc_wdata(spec_insn_lh_pc_wdata),
    .spec_mem_addr(spec_insn_lh_mem_addr),
    .spec_mem_rmask(spec_insn_lh_mem_rmask),
    .spec_mem_wmask(spec_insn_lh_mem_wmask),
    .spec_mem_wdata(spec_insn_lh_mem_wdata)
  );

  wire                                spec_insn_lhu_valid;
  wire                                spec_insn_lhu_trap;
  wire [                       4 : 0] spec_insn_lhu_rs1_addr;
  wire [                       4 : 0] spec_insn_lhu_rs2_addr;
  wire [                       4 : 0] spec_insn_lhu_rd_addr;
  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_lhu_rd_wdata;
  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_lhu_pc_wdata;
  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_lhu_mem_addr;
  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_lhu_mem_rmask;
  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_lhu_mem_wmask;
  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_lhu_mem_wdata;
`ifdef RISCV_FORMAL_CSR_MISA
  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_lhu_csr_misa_rmask;
`endif

  rvfi_insn_lhu insn_lhu (
    .rvfi_valid(rvfi_valid),
    .rvfi_insn(rvfi_insn),
    .rvfi_pc_rdata(rvfi_pc_rdata),
    .rvfi_rs1_rdata(rvfi_rs1_rdata),
    .rvfi_rs2_rdata(rvfi_rs2_rdata),
    .rvfi_mem_rdata(rvfi_mem_rdata),
`ifdef RISCV_FORMAL_CSR_MISA
    .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata),
    .spec_csr_misa_rmask(spec_insn_lhu_csr_misa_rmask),
`endif
    .spec_valid(spec_insn_lhu_valid),
    .spec_trap(spec_insn_lhu_trap),
    .spec_rs1_addr(spec_insn_lhu_rs1_addr),
    .spec_rs2_addr(spec_insn_lhu_rs2_addr),
    .spec_rd_addr(spec_insn_lhu_rd_addr),
    .spec_rd_wdata(spec_insn_lhu_rd_wdata),
    .spec_pc_wdata(spec_insn_lhu_pc_wdata),
    .spec_mem_addr(spec_insn_lhu_mem_addr),
    .spec_mem_rmask(spec_insn_lhu_mem_rmask),
    .spec_mem_wmask(spec_insn_lhu_mem_wmask),
    .spec_mem_wdata(spec_insn_lhu_mem_wdata)
  );

  wire                                spec_insn_lui_valid;
  wire                                spec_insn_lui_trap;
  wire [                       4 : 0] spec_insn_lui_rs1_addr;
  wire [                       4 : 0] spec_insn_lui_rs2_addr;
  wire [                       4 : 0] spec_insn_lui_rd_addr;
  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_lui_rd_wdata;
  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_lui_pc_wdata;
  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_lui_mem_addr;
  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_lui_mem_rmask;
  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_lui_mem_wmask;
  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_lui_mem_wdata;
`ifdef RISCV_FORMAL_CSR_MISA
  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_lui_csr_misa_rmask;
`endif

  rvfi_insn_lui insn_lui (
    .rvfi_valid(rvfi_valid),
    .rvfi_insn(rvfi_insn),
    .rvfi_pc_rdata(rvfi_pc_rdata),
    .rvfi_rs1_rdata(rvfi_rs1_rdata),
    .rvfi_rs2_rdata(rvfi_rs2_rdata),
    .rvfi_mem_rdata(rvfi_mem_rdata),
`ifdef RISCV_FORMAL_CSR_MISA
    .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata),
    .spec_csr_misa_rmask(spec_insn_lui_csr_misa_rmask),
`endif
    .spec_valid(spec_insn_lui_valid),
    .spec_trap(spec_insn_lui_trap),
    .spec_rs1_addr(spec_insn_lui_rs1_addr),
    .spec_rs2_addr(spec_insn_lui_rs2_addr),
    .spec_rd_addr(spec_insn_lui_rd_addr),
    .spec_rd_wdata(spec_insn_lui_rd_wdata),
    .spec_pc_wdata(spec_insn_lui_pc_wdata),
    .spec_mem_addr(spec_insn_lui_mem_addr),
    .spec_mem_rmask(spec_insn_lui_mem_rmask),
    .spec_mem_wmask(spec_insn_lui_mem_wmask),
    .spec_mem_wdata(spec_insn_lui_mem_wdata)
  );

  wire                                spec_insn_lw_valid;
  wire                                spec_insn_lw_trap;
  wire [                       4 : 0] spec_insn_lw_rs1_addr;
  wire [                       4 : 0] spec_insn_lw_rs2_addr;
  wire [                       4 : 0] spec_insn_lw_rd_addr;
  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_lw_rd_wdata;
  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_lw_pc_wdata;
  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_lw_mem_addr;
  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_lw_mem_rmask;
  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_lw_mem_wmask;
  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_lw_mem_wdata;
`ifdef RISCV_FORMAL_CSR_MISA
  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_lw_csr_misa_rmask;
`endif

  rvfi_insn_lw insn_lw (
    .rvfi_valid(rvfi_valid),
    .rvfi_insn(rvfi_insn),
    .rvfi_pc_rdata(rvfi_pc_rdata),
    .rvfi_rs1_rdata(rvfi_rs1_rdata),
    .rvfi_rs2_rdata(rvfi_rs2_rdata),
    .rvfi_mem_rdata(rvfi_mem_rdata),
`ifdef RISCV_FORMAL_CSR_MISA
    .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata),
    .spec_csr_misa_rmask(spec_insn_lw_csr_misa_rmask),
`endif
    .spec_valid(spec_insn_lw_valid),
    .spec_trap(spec_insn_lw_trap),
    .spec_rs1_addr(spec_insn_lw_rs1_addr),
    .spec_rs2_addr(spec_insn_lw_rs2_addr),
    .spec_rd_addr(spec_insn_lw_rd_addr),
    .spec_rd_wdata(spec_insn_lw_rd_wdata),
    .spec_pc_wdata(spec_insn_lw_pc_wdata),
    .spec_mem_addr(spec_insn_lw_mem_addr),
    .spec_mem_rmask(spec_insn_lw_mem_rmask),
    .spec_mem_wmask(spec_insn_lw_mem_wmask),
    .spec_mem_wdata(spec_insn_lw_mem_wdata)
  );

  wire                                spec_insn_lwu_valid;
  wire                                spec_insn_lwu_trap;
  wire [                       4 : 0] spec_insn_lwu_rs1_addr;
  wire [                       4 : 0] spec_insn_lwu_rs2_addr;
  wire [                       4 : 0] spec_insn_lwu_rd_addr;
  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_lwu_rd_wdata;
  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_lwu_pc_wdata;
  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_lwu_mem_addr;
  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_lwu_mem_rmask;
  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_lwu_mem_wmask;
  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_lwu_mem_wdata;
`ifdef RISCV_FORMAL_CSR_MISA
  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_lwu_csr_misa_rmask;
`endif

  rvfi_insn_lwu insn_lwu (
    .rvfi_valid(rvfi_valid),
    .rvfi_insn(rvfi_insn),
    .rvfi_pc_rdata(rvfi_pc_rdata),
    .rvfi_rs1_rdata(rvfi_rs1_rdata),
    .rvfi_rs2_rdata(rvfi_rs2_rdata),
    .rvfi_mem_rdata(rvfi_mem_rdata),
`ifdef RISCV_FORMAL_CSR_MISA
    .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata),
    .spec_csr_misa_rmask(spec_insn_lwu_csr_misa_rmask),
`endif
    .spec_valid(spec_insn_lwu_valid),
    .spec_trap(spec_insn_lwu_trap),
    .spec_rs1_addr(spec_insn_lwu_rs1_addr),
    .spec_rs2_addr(spec_insn_lwu_rs2_addr),
    .spec_rd_addr(spec_insn_lwu_rd_addr),
    .spec_rd_wdata(spec_insn_lwu_rd_wdata),
    .spec_pc_wdata(spec_insn_lwu_pc_wdata),
    .spec_mem_addr(spec_insn_lwu_mem_addr),
    .spec_mem_rmask(spec_insn_lwu_mem_rmask),
    .spec_mem_wmask(spec_insn_lwu_mem_wmask),
    .spec_mem_wdata(spec_insn_lwu_mem_wdata)
  );

  wire                                spec_insn_max_valid;
  wire                                spec_insn_max_trap;
  wire [                       4 : 0] spec_insn_max_rs1_addr;
  wire [                       4 : 0] spec_insn_max_rs2_addr;
  wire [                       4 : 0] spec_insn_max_rd_addr;
  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_max_rd_wdata;
  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_max_pc_wdata;
  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_max_mem_addr;
  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_max_mem_rmask;
  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_max_mem_wmask;
  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_max_mem_wdata;
`ifdef RISCV_FORMAL_CSR_MISA
  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_max_csr_misa_rmask;
`endif

  rvfi_insn_max insn_max (
    .rvfi_valid(rvfi_valid),
    .rvfi_insn(rvfi_insn),
    .rvfi_pc_rdata(rvfi_pc_rdata),
    .rvfi_rs1_rdata(rvfi_rs1_rdata),
    .rvfi_rs2_rdata(rvfi_rs2_rdata),
    .rvfi_mem_rdata(rvfi_mem_rdata),
`ifdef RISCV_FORMAL_CSR_MISA
    .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata),
    .spec_csr_misa_rmask(spec_insn_max_csr_misa_rmask),
`endif
    .spec_valid(spec_insn_max_valid),
    .spec_trap(spec_insn_max_trap),
    .spec_rs1_addr(spec_insn_max_rs1_addr),
    .spec_rs2_addr(spec_insn_max_rs2_addr),
    .spec_rd_addr(spec_insn_max_rd_addr),
    .spec_rd_wdata(spec_insn_max_rd_wdata),
    .spec_pc_wdata(spec_insn_max_pc_wdata),
    .spec_mem_addr(spec_insn_max_mem_addr),
    .spec_mem_rmask(spec_insn_max_mem_rmask),
    .spec_mem_wmask(spec_insn_max_mem_wmask),
    .spec_mem_wdata(spec_insn_max_mem_wdata)
  );

  wire                                spec_insn_maxu_valid;
  wire                                spec_insn_maxu_trap;
  wire [                       4 : 0] spec_insn_maxu_rs1_addr;
  wire [                       4 : 0] spec_insn_maxu_rs2_addr;
  wire [                       4 : 0] spec_insn_maxu_rd_addr;
  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_maxu_rd_wdata;
  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_maxu_pc_wdata;
  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_maxu_mem_addr;
  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_maxu_mem_rmask;
  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_maxu_mem_wmask;
  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_maxu_mem_wdata;
`ifdef RISCV_FORMAL_CSR_MISA
  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_maxu_csr_misa_rmask;
`endif

  rvfi_insn_maxu insn_maxu (
    .rvfi_valid(rvfi_valid),
    .rvfi_insn(rvfi_insn),
    .rvfi_pc_rdata(rvfi_pc_rdata),
    .rvfi_rs1_rdata(rvfi_rs1_rdata),
    .rvfi_rs2_rdata(rvfi_rs2_rdata),
    .rvfi_mem_rdata(rvfi_mem_rdata),
`ifdef RISCV_FORMAL_CSR_MISA
    .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata),
    .spec_csr_misa_rmask(spec_insn_maxu_csr_misa_rmask),
`endif
    .spec_valid(spec_insn_maxu_valid),
    .spec_trap(spec_insn_maxu_trap),
    .spec_rs1_addr(spec_insn_maxu_rs1_addr),
    .spec_rs2_addr(spec_insn_maxu_rs2_addr),
    .spec_rd_addr(spec_insn_maxu_rd_addr),
    .spec_rd_wdata(spec_insn_maxu_rd_wdata),
    .spec_pc_wdata(spec_insn_maxu_pc_wdata),
    .spec_mem_addr(spec_insn_maxu_mem_addr),
    .spec_mem_rmask(spec_insn_maxu_mem_rmask),
    .spec_mem_wmask(spec_insn_maxu_mem_wmask),
    .spec_mem_wdata(spec_insn_maxu_mem_wdata)
  );

  wire                                spec_insn_min_valid;
  wire                                spec_insn_min_trap;
  wire [                       4 : 0] spec_insn_min_rs1_addr;
  wire [                       4 : 0] spec_insn_min_rs2_addr;
  wire [                       4 : 0] spec_insn_min_rd_addr;
  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_min_rd_wdata;
  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_min_pc_wdata;
  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_min_mem_addr;
  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_min_mem_rmask;
  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_min_mem_wmask;
  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_min_mem_wdata;
`ifdef RISCV_FORMAL_CSR_MISA
  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_min_csr_misa_rmask;
`endif

  rvfi_insn_min insn_min (
    .rvfi_valid(rvfi_valid),
    .rvfi_insn(rvfi_insn),
    .rvfi_pc_rdata(rvfi_pc_rdata),
    .rvfi_rs1_rdata(rvfi_rs1_rdata),
    .rvfi_rs2_rdata(rvfi_rs2_rdata),
    .rvfi_mem_rdata(rvfi_mem_rdata),
`ifdef RISCV_FORMAL_CSR_MISA
    .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata),
    .spec_csr_misa_rmask(spec_insn_min_csr_misa_rmask),
`endif
    .spec_valid(spec_insn_min_valid),
    .spec_trap(spec_insn_min_trap),
    .spec_rs1_addr(spec_insn_min_rs1_addr),
    .spec_rs2_addr(spec_insn_min_rs2_addr),
    .spec_rd_addr(spec_insn_min_rd_addr),
    .spec_rd_wdata(spec_insn_min_rd_wdata),
    .spec_pc_wdata(spec_insn_min_pc_wdata),
    .spec_mem_addr(spec_insn_min_mem_addr),
    .spec_mem_rmask(spec_insn_min_mem_rmask),
    .spec_mem_wmask(spec_insn_min_mem_wmask),
    .spec_mem_wdata(spec_insn_min_mem_wdata)
  );

  wire                                spec_insn_minu_valid;
  wire                                spec_insn_minu_trap;
  wire [                       4 : 0] spec_insn_minu_rs1_addr;
  wire [                       4 : 0] spec_insn_minu_rs2_addr;
  wire [                       4 : 0] spec_insn_minu_rd_addr;
  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_minu_rd_wdata;
  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_minu_pc_wdata;
  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_minu_mem_addr;
  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_minu_mem_rmask;
  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_minu_mem_wmask;
  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_minu_mem_wdata;
`ifdef RISCV_FORMAL_CSR_MISA
  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_minu_csr_misa_rmask;
`endif

  rvfi_insn_minu insn_minu (
    .rvfi_valid(rvfi_valid),
    .rvfi_insn(rvfi_insn),
    .rvfi_pc_rdata(rvfi_pc_rdata),
    .rvfi_rs1_rdata(rvfi_rs1_rdata),
    .rvfi_rs2_rdata(rvfi_rs2_rdata),
    .rvfi_mem_rdata(rvfi_mem_rdata),
`ifdef RISCV_FORMAL_CSR_MISA
    .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata),
    .spec_csr_misa_rmask(spec_insn_minu_csr_misa_rmask),
`endif
    .spec_valid(spec_insn_minu_valid),
    .spec_trap(spec_insn_minu_trap),
    .spec_rs1_addr(spec_insn_minu_rs1_addr),
    .spec_rs2_addr(spec_insn_minu_rs2_addr),
    .spec_rd_addr(spec_insn_minu_rd_addr),
    .spec_rd_wdata(spec_insn_minu_rd_wdata),
    .spec_pc_wdata(spec_insn_minu_pc_wdata),
    .spec_mem_addr(spec_insn_minu_mem_addr),
    .spec_mem_rmask(spec_insn_minu_mem_rmask),
    .spec_mem_wmask(spec_insn_minu_mem_wmask),
    .spec_mem_wdata(spec_insn_minu_mem_wdata)
  );

  wire                                spec_insn_or_valid;
  wire                                spec_insn_or_trap;
  wire [                       4 : 0] spec_insn_or_rs1_addr;
  wire [                       4 : 0] spec_insn_or_rs2_addr;
  wire [                       4 : 0] spec_insn_or_rd_addr;
  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_or_rd_wdata;
  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_or_pc_wdata;
  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_or_mem_addr;
  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_or_mem_rmask;
  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_or_mem_wmask;
  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_or_mem_wdata;
`ifdef RISCV_FORMAL_CSR_MISA
  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_or_csr_misa_rmask;
`endif

  rvfi_insn_or insn_or (
    .rvfi_valid(rvfi_valid),
    .rvfi_insn(rvfi_insn),
    .rvfi_pc_rdata(rvfi_pc_rdata),
    .rvfi_rs1_rdata(rvfi_rs1_rdata),
    .rvfi_rs2_rdata(rvfi_rs2_rdata),
    .rvfi_mem_rdata(rvfi_mem_rdata),
`ifdef RISCV_FORMAL_CSR_MISA
    .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata),
    .spec_csr_misa_rmask(spec_insn_or_csr_misa_rmask),
`endif
    .spec_valid(spec_insn_or_valid),
    .spec_trap(spec_insn_or_trap),
    .spec_rs1_addr(spec_insn_or_rs1_addr),
    .spec_rs2_addr(spec_insn_or_rs2_addr),
    .spec_rd_addr(spec_insn_or_rd_addr),
    .spec_rd_wdata(spec_insn_or_rd_wdata),
    .spec_pc_wdata(spec_insn_or_pc_wdata),
    .spec_mem_addr(spec_insn_or_mem_addr),
    .spec_mem_rmask(spec_insn_or_mem_rmask),
    .spec_mem_wmask(spec_insn_or_mem_wmask),
    .spec_mem_wdata(spec_insn_or_mem_wdata)
  );

  wire                                spec_insn_orc_b_valid;
  wire                                spec_insn_orc_b_trap;
  wire [                       4 : 0] spec_insn_orc_b_rs1_addr;
  wire [                       4 : 0] spec_insn_orc_b_rs2_addr;
  wire [                       4 : 0] spec_insn_orc_b_rd_addr;
  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_orc_b_rd_wdata;
  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_orc_b_pc_wdata;
  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_orc_b_mem_addr;
  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_orc_b_mem_rmask;
  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_orc_b_mem_wmask;
  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_orc_b_mem_wdata;
`ifdef RISCV_FORMAL_CSR_MISA
  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_orc_b_csr_misa_rmask;
`endif

  rvfi_insn_orc_b insn_orc_b (
    .rvfi_valid(rvfi_valid),
    .rvfi_insn(rvfi_insn),
    .rvfi_pc_rdata(rvfi_pc_rdata),
    .rvfi_rs1_rdata(rvfi_rs1_rdata),
    .rvfi_rs2_rdata(rvfi_rs2_rdata),
    .rvfi_mem_rdata(rvfi_mem_rdata),
`ifdef RISCV_FORMAL_CSR_MISA
    .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata),
    .spec_csr_misa_rmask(spec_insn_orc_b_csr_misa_rmask),
`endif
    .spec_valid(spec_insn_orc_b_valid),
    .spec_trap(spec_insn_orc_b_trap),
    .spec_rs1_addr(spec_insn_orc_b_rs1_addr),
    .spec_rs2_addr(spec_insn_orc_b_rs2_addr),
    .spec_rd_addr(spec_insn_orc_b_rd_addr),
    .spec_rd_wdata(spec_insn_orc_b_rd_wdata),
    .spec_pc_wdata(spec_insn_orc_b_pc_wdata),
    .spec_mem_addr(spec_insn_orc_b_mem_addr),
    .spec_mem_rmask(spec_insn_orc_b_mem_rmask),
    .spec_mem_wmask(spec_insn_orc_b_mem_wmask),
    .spec_mem_wdata(spec_insn_orc_b_mem_wdata)
  );

  wire                                spec_insn_ori_valid;
  wire                                spec_insn_ori_trap;
  wire [                       4 : 0] spec_insn_ori_rs1_addr;
  wire [                       4 : 0] spec_insn_ori_rs2_addr;
  wire [                       4 : 0] spec_insn_ori_rd_addr;
  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_ori_rd_wdata;
  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_ori_pc_wdata;
  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_ori_mem_addr;
  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_ori_mem_rmask;
  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_ori_mem_wmask;
  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_ori_mem_wdata;
`ifdef RISCV_FORMAL_CSR_MISA
  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_ori_csr_misa_rmask;
`endif

  rvfi_insn_ori insn_ori (
    .rvfi_valid(rvfi_valid),
    .rvfi_insn(rvfi_insn),
    .rvfi_pc_rdata(rvfi_pc_rdata),
    .rvfi_rs1_rdata(rvfi_rs1_rdata),
    .rvfi_rs2_rdata(rvfi_rs2_rdata),
    .rvfi_mem_rdata(rvfi_mem_rdata),
`ifdef RISCV_FORMAL_CSR_MISA
    .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata),
    .spec_csr_misa_rmask(spec_insn_ori_csr_misa_rmask),
`endif
    .spec_valid(spec_insn_ori_valid),
    .spec_trap(spec_insn_ori_trap),
    .spec_rs1_addr(spec_insn_ori_rs1_addr),
    .spec_rs2_addr(spec_insn_ori_rs2_addr),
    .spec_rd_addr(spec_insn_ori_rd_addr),
    .spec_rd_wdata(spec_insn_ori_rd_wdata),
    .spec_pc_wdata(spec_insn_ori_pc_wdata),
    .spec_mem_addr(spec_insn_ori_mem_addr),
    .spec_mem_rmask(spec_insn_ori_mem_rmask),
    .spec_mem_wmask(spec_insn_ori_mem_wmask),
    .spec_mem_wdata(spec_insn_ori_mem_wdata)
  );

  wire                                spec_insn_orn_valid;
  wire                                spec_insn_orn_trap;
  wire [                       4 : 0] spec_insn_orn_rs1_addr;
  wire [                       4 : 0] spec_insn_orn_rs2_addr;
  wire [                       4 : 0] spec_insn_orn_rd_addr;
  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_orn_rd_wdata;
  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_orn_pc_wdata;
  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_orn_mem_addr;
  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_orn_mem_rmask;
  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_orn_mem_wmask;
  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_orn_mem_wdata;
`ifdef RISCV_FORMAL_CSR_MISA
  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_orn_csr_misa_rmask;
`endif

  rvfi_insn_orn insn_orn (
    .rvfi_valid(rvfi_valid),
    .rvfi_insn(rvfi_insn),
    .rvfi_pc_rdata(rvfi_pc_rdata),
    .rvfi_rs1_rdata(rvfi_rs1_rdata),
    .rvfi_rs2_rdata(rvfi_rs2_rdata),
    .rvfi_mem_rdata(rvfi_mem_rdata),
`ifdef RISCV_FORMAL_CSR_MISA
    .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata),
    .spec_csr_misa_rmask(spec_insn_orn_csr_misa_rmask),
`endif
    .spec_valid(spec_insn_orn_valid),
    .spec_trap(spec_insn_orn_trap),
    .spec_rs1_addr(spec_insn_orn_rs1_addr),
    .spec_rs2_addr(spec_insn_orn_rs2_addr),
    .spec_rd_addr(spec_insn_orn_rd_addr),
    .spec_rd_wdata(spec_insn_orn_rd_wdata),
    .spec_pc_wdata(spec_insn_orn_pc_wdata),
    .spec_mem_addr(spec_insn_orn_mem_addr),
    .spec_mem_rmask(spec_insn_orn_mem_rmask),
    .spec_mem_wmask(spec_insn_orn_mem_wmask),
    .spec_mem_wdata(spec_insn_orn_mem_wdata)
  );

  wire                                spec_insn_rev8_valid;
  wire                                spec_insn_rev8_trap;
  wire [                       4 : 0] spec_insn_rev8_rs1_addr;
  wire [                       4 : 0] spec_insn_rev8_rs2_addr;
  wire [                       4 : 0] spec_insn_rev8_rd_addr;
  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_rev8_rd_wdata;
  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_rev8_pc_wdata;
  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_rev8_mem_addr;
  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_rev8_mem_rmask;
  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_rev8_mem_wmask;
  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_rev8_mem_wdata;
`ifdef RISCV_FORMAL_CSR_MISA
  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_rev8_csr_misa_rmask;
`endif

  rvfi_insn_rev8 insn_rev8 (
    .rvfi_valid(rvfi_valid),
    .rvfi_insn(rvfi_insn),
    .rvfi_pc_rdata(rvfi_pc_rdata),
    .rvfi_rs1_rdata(rvfi_rs1_rdata),
    .rvfi_rs2_rdata(rvfi_rs2_rdata),
    .rvfi_mem_rdata(rvfi_mem_rdata),
`ifdef RISCV_FORMAL_CSR_MISA
    .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata),
    .spec_csr_misa_rmask(spec_insn_rev8_csr_misa_rmask),
`endif
    .spec_valid(spec_insn_rev8_valid),
    .spec_trap(spec_insn_rev8_trap),
    .spec_rs1_addr(spec_insn_rev8_rs1_addr),
    .spec_rs2_addr(spec_insn_rev8_rs2_addr),
    .spec_rd_addr(spec_insn_rev8_rd_addr),
    .spec_rd_wdata(spec_insn_rev8_rd_wdata),
    .spec_pc_wdata(spec_insn_rev8_pc_wdata),
    .spec_mem_addr(spec_insn_rev8_mem_addr),
    .spec_mem_rmask(spec_insn_rev8_mem_rmask),
    .spec_mem_wmask(spec_insn_rev8_mem_wmask),
    .spec_mem_wdata(spec_insn_rev8_mem_wdata)
  );

  wire                                spec_insn_rol_valid;
  wire                                spec_insn_rol_trap;
  wire [                       4 : 0] spec_insn_rol_rs1_addr;
  wire [                       4 : 0] spec_insn_rol_rs2_addr;
  wire [                       4 : 0] spec_insn_rol_rd_addr;
  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_rol_rd_wdata;
  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_rol_pc_wdata;
  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_rol_mem_addr;
  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_rol_mem_rmask;
  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_rol_mem_wmask;
  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_rol_mem_wdata;
`ifdef RISCV_FORMAL_CSR_MISA
  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_rol_csr_misa_rmask;
`endif

  rvfi_insn_rol insn_rol (
    .rvfi_valid(rvfi_valid),
    .rvfi_insn(rvfi_insn),
    .rvfi_pc_rdata(rvfi_pc_rdata),
    .rvfi_rs1_rdata(rvfi_rs1_rdata),
    .rvfi_rs2_rdata(rvfi_rs2_rdata),
    .rvfi_mem_rdata(rvfi_mem_rdata),
`ifdef RISCV_FORMAL_CSR_MISA
    .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata),
    .spec_csr_misa_rmask(spec_insn_rol_csr_misa_rmask),
`endif
    .spec_valid(spec_insn_rol_valid),
    .spec_trap(spec_insn_rol_trap),
    .spec_rs1_addr(spec_insn_rol_rs1_addr),
    .spec_rs2_addr(spec_insn_rol_rs2_addr),
    .spec_rd_addr(spec_insn_rol_rd_addr),
    .spec_rd_wdata(spec_insn_rol_rd_wdata),
    .spec_pc_wdata(spec_insn_rol_pc_wdata),
    .spec_mem_addr(spec_insn_rol_mem_addr),
    .spec_mem_rmask(spec_insn_rol_mem_rmask),
    .spec_mem_wmask(spec_insn_rol_mem_wmask),
    .spec_mem_wdata(spec_insn_rol_mem_wdata)
  );

  wire                                spec_insn_rolw_valid;
  wire                                spec_insn_rolw_trap;
  wire [                       4 : 0] spec_insn_rolw_rs1_addr;
  wire [                       4 : 0] spec_insn_rolw_rs2_addr;
  wire [                       4 : 0] spec_insn_rolw_rd_addr;
  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_rolw_rd_wdata;
  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_rolw_pc_wdata;
  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_rolw_mem_addr;
  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_rolw_mem_rmask;
  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_rolw_mem_wmask;
  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_rolw_mem_wdata;
`ifdef RISCV_FORMAL_CSR_MISA
  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_rolw_csr_misa_rmask;
`endif

  rvfi_insn_rolw insn_rolw (
    .rvfi_valid(rvfi_valid),
    .rvfi_insn(rvfi_insn),
    .rvfi_pc_rdata(rvfi_pc_rdata),
    .rvfi_rs1_rdata(rvfi_rs1_rdata),
    .rvfi_rs2_rdata(rvfi_rs2_rdata),
    .rvfi_mem_rdata(rvfi_mem_rdata),
`ifdef RISCV_FORMAL_CSR_MISA
    .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata),
    .spec_csr_misa_rmask(spec_insn_rolw_csr_misa_rmask),
`endif
    .spec_valid(spec_insn_rolw_valid),
    .spec_trap(spec_insn_rolw_trap),
    .spec_rs1_addr(spec_insn_rolw_rs1_addr),
    .spec_rs2_addr(spec_insn_rolw_rs2_addr),
    .spec_rd_addr(spec_insn_rolw_rd_addr),
    .spec_rd_wdata(spec_insn_rolw_rd_wdata),
    .spec_pc_wdata(spec_insn_rolw_pc_wdata),
    .spec_mem_addr(spec_insn_rolw_mem_addr),
    .spec_mem_rmask(spec_insn_rolw_mem_rmask),
    .spec_mem_wmask(spec_insn_rolw_mem_wmask),
    .spec_mem_wdata(spec_insn_rolw_mem_wdata)
  );

  wire                                spec_insn_ror_valid;
  wire                                spec_insn_ror_trap;
  wire [                       4 : 0] spec_insn_ror_rs1_addr;
  wire [                       4 : 0] spec_insn_ror_rs2_addr;
  wire [                       4 : 0] spec_insn_ror_rd_addr;
  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_ror_rd_wdata;
  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_ror_pc_wdata;
  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_ror_mem_addr;
  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_ror_mem_rmask;
  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_ror_mem_wmask;
  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_ror_mem_wdata;
`ifdef RISCV_FORMAL_CSR_MISA
  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_ror_csr_misa_rmask;
`endif

  rvfi_insn_ror insn_ror (
    .rvfi_valid(rvfi_valid),
    .rvfi_insn(rvfi_insn),
    .rvfi_pc_rdata(rvfi_pc_rdata),
    .rvfi_rs1_rdata(rvfi_rs1_rdata),
    .rvfi_rs2_rdata(rvfi_rs2_rdata),
    .rvfi_mem_rdata(rvfi_mem_rdata),
`ifdef RISCV_FORMAL_CSR_MISA
    .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata),
    .spec_csr_misa_rmask(spec_insn_ror_csr_misa_rmask),
`endif
    .spec_valid(spec_insn_ror_valid),
    .spec_trap(spec_insn_ror_trap),
    .spec_rs1_addr(spec_insn_ror_rs1_addr),
    .spec_rs2_addr(spec_insn_ror_rs2_addr),
    .spec_rd_addr(spec_insn_ror_rd_addr),
    .spec_rd_wdata(spec_insn_ror_rd_wdata),
    .spec_pc_wdata(spec_insn_ror_pc_wdata),
    .spec_mem_addr(spec_insn_ror_mem_addr),
    .spec_mem_rmask(spec_insn_ror_mem_rmask),
    .spec_mem_wmask(spec_insn_ror_mem_wmask),
    .spec_mem_wdata(spec_insn_ror_mem_wdata)
  );

  wire                                spec_insn_rori_valid;
  wire                                spec_insn_rori_trap;
  wire [                       4 : 0] spec_insn_rori_rs1_addr;
  wire [                       4 : 0] spec_insn_rori_rs2_addr;
  wire [                       4 : 0] spec_insn_rori_rd_addr;
  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_rori_rd_wdata;
  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_rori_pc_wdata;
  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_rori_mem_addr;
  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_rori_mem_rmask;
  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_rori_mem_wmask;
  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_rori_mem_wdata;
`ifdef RISCV_FORMAL_CSR_MISA
  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_rori_csr_misa_rmask;
`endif

  rvfi_insn_rori insn_rori (
    .rvfi_valid(rvfi_valid),
    .rvfi_insn(rvfi_insn),
    .rvfi_pc_rdata(rvfi_pc_rdata),
    .rvfi_rs1_rdata(rvfi_rs1_rdata),
    .rvfi_rs2_rdata(rvfi_rs2_rdata),
    .rvfi_mem_rdata(rvfi_mem_rdata),
`ifdef RISCV_FORMAL_CSR_MISA
    .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata),
    .spec_csr_misa_rmask(spec_insn_rori_csr_misa_rmask),
`endif
    .spec_valid(spec_insn_rori_valid),
    .spec_trap(spec_insn_rori_trap),
    .spec_rs1_addr(spec_insn_rori_rs1_addr),
    .spec_rs2_addr(spec_insn_rori_rs2_addr),
    .spec_rd_addr(spec_insn_rori_rd_addr),
    .spec_rd_wdata(spec_insn_rori_rd_wdata),
    .spec_pc_wdata(spec_insn_rori_pc_wdata),
    .spec_mem_addr(spec_insn_rori_mem_addr),
    .spec_mem_rmask(spec_insn_rori_mem_rmask),
    .spec_mem_wmask(spec_insn_rori_mem_wmask),
    .spec_mem_wdata(spec_insn_rori_mem_wdata)
  );

  wire                                spec_insn_roriw_valid;
  wire                                spec_insn_roriw_trap;
  wire [                       4 : 0] spec_insn_roriw_rs1_addr;
  wire [                       4 : 0] spec_insn_roriw_rs2_addr;
  wire [                       4 : 0] spec_insn_roriw_rd_addr;
  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_roriw_rd_wdata;
  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_roriw_pc_wdata;
  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_roriw_mem_addr;
  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_roriw_mem_rmask;
  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_roriw_mem_wmask;
  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_roriw_mem_wdata;
`ifdef RISCV_FORMAL_CSR_MISA
  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_roriw_csr_misa_rmask;
`endif

  rvfi_insn_roriw insn_roriw (
    .rvfi_valid(rvfi_valid),
    .rvfi_insn(rvfi_insn),
    .rvfi_pc_rdata(rvfi_pc_rdata),
    .rvfi_rs1_rdata(rvfi_rs1_rdata),
    .rvfi_rs2_rdata(rvfi_rs2_rdata),
    .rvfi_mem_rdata(rvfi_mem_rdata),
`ifdef RISCV_FORMAL_CSR_MISA
    .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata),
    .spec_csr_misa_rmask(spec_insn_roriw_csr_misa_rmask),
`endif
    .spec_valid(spec_insn_roriw_valid),
    .spec_trap(spec_insn_roriw_trap),
    .spec_rs1_addr(spec_insn_roriw_rs1_addr),
    .spec_rs2_addr(spec_insn_roriw_rs2_addr),
    .spec_rd_addr(spec_insn_roriw_rd_addr),
    .spec_rd_wdata(spec_insn_roriw_rd_wdata),
    .spec_pc_wdata(spec_insn_roriw_pc_wdata),
    .spec_mem_addr(spec_insn_roriw_mem_addr),
    .spec_mem_rmask(spec_insn_roriw_mem_rmask),
    .spec_mem_wmask(spec_insn_roriw_mem_wmask),
    .spec_mem_wdata(spec_insn_roriw_mem_wdata)
  );

  wire                                spec_insn_rorw_valid;
  wire                                spec_insn_rorw_trap;
  wire [                       4 : 0] spec_insn_rorw_rs1_addr;
  wire [                       4 : 0] spec_insn_rorw_rs2_addr;
  wire [                       4 : 0] spec_insn_rorw_rd_addr;
  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_rorw_rd_wdata;
  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_rorw_pc_wdata;
  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_rorw_mem_addr;
  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_rorw_mem_rmask;
  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_rorw_mem_wmask;
  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_rorw_mem_wdata;
`ifdef RISCV_FORMAL_CSR_MISA
  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_rorw_csr_misa_rmask;
`endif

  rvfi_insn_rorw insn_rorw (
    .rvfi_valid(rvfi_valid),
    .rvfi_insn(rvfi_insn),
    .rvfi_pc_rdata(rvfi_pc_rdata),
    .rvfi_rs1_rdata(rvfi_rs1_rdata),
    .rvfi_rs2_rdata(rvfi_rs2_rdata),
    .rvfi_mem_rdata(rvfi_mem_rdata),
`ifdef RISCV_FORMAL_CSR_MISA
    .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata),
    .spec_csr_misa_rmask(spec_insn_rorw_csr_misa_rmask),
`endif
    .spec_valid(spec_insn_rorw_valid),
    .spec_trap(spec_insn_rorw_trap),
    .spec_rs1_addr(spec_insn_rorw_rs1_addr),
    .spec_rs2_addr(spec_insn_rorw_rs2_addr),
    .spec_rd_addr(spec_insn_rorw_rd_addr),
    .spec_rd_wdata(spec_insn_rorw_rd_wdata),
    .spec_pc_wdata(spec_insn_rorw_pc_wdata),
    .spec_mem_addr(spec_insn_rorw_mem_addr),
    .spec_mem_rmask(spec_insn_rorw_mem_rmask),
    .spec_mem_wmask(spec_insn_rorw_mem_wmask),
    .spec_mem_wdata(spec_insn_rorw_mem_wdata)
  );

  wire                                spec_insn_sb_valid;
  wire                                spec_insn_sb_trap;
  wire [                       4 : 0] spec_insn_sb_rs1_addr;
  wire [                       4 : 0] spec_insn_sb_rs2_addr;
  wire [                       4 : 0] spec_insn_sb_rd_addr;
  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_sb_rd_wdata;
  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_sb_pc_wdata;
  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_sb_mem_addr;
  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_sb_mem_rmask;
  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_sb_mem_wmask;
  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_sb_mem_wdata;
`ifdef RISCV_FORMAL_CSR_MISA
  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_sb_csr_misa_rmask;
`endif

  rvfi_insn_sb insn_sb (
    .rvfi_valid(rvfi_valid),
    .rvfi_insn(rvfi_insn),
    .rvfi_pc_rdata(rvfi_pc_rdata),
    .rvfi_rs1_rdata(rvfi_rs1_rdata),
    .rvfi_rs2_rdata(rvfi_rs2_rdata),
    .rvfi_mem_rdata(rvfi_mem_rdata),
`ifdef RISCV_FORMAL_CSR_MISA
    .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata),
    .spec_csr_misa_rmask(spec_insn_sb_csr_misa_rmask),
`endif
    .spec_valid(spec_insn_sb_valid),
    .spec_trap(spec_insn_sb_trap),
    .spec_rs1_addr(spec_insn_sb_rs1_addr),
    .spec_rs2_addr(spec_insn_sb_rs2_addr),
    .spec_rd_addr(spec_insn_sb_rd_addr),
    .spec_rd_wdata(spec_insn_sb_rd_wdata),
    .spec_pc_wdata(spec_insn_sb_pc_wdata),
    .spec_mem_addr(spec_insn_sb_mem_addr),
    .spec_mem_rmask(spec_insn_sb_mem_rmask),
    .spec_mem_wmask(spec_insn_sb_mem_wmask),
    .spec_mem_wdata(spec_insn_sb_mem_wdata)
  );

  wire                                spec_insn_sd_valid;
  wire                                spec_insn_sd_trap;
  wire [                       4 : 0] spec_insn_sd_rs1_addr;
  wire [                       4 : 0] spec_insn_sd_rs2_addr;
  wire [                       4 : 0] spec_insn_sd_rd_addr;
  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_sd_rd_wdata;
  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_sd_pc_wdata;
  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_sd_mem_addr;
  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_sd_mem_rmask;
  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_sd_mem_wmask;
  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_sd_mem_wdata;
`ifdef RISCV_FORMAL_CSR_MISA
  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_sd_csr_misa_rmask;
`endif

  rvfi_insn_sd insn_sd (
    .rvfi_valid(rvfi_valid),
    .rvfi_insn(rvfi_insn),
    .rvfi_pc_rdata(rvfi_pc_rdata),
    .rvfi_rs1_rdata(rvfi_rs1_rdata),
    .rvfi_rs2_rdata(rvfi_rs2_rdata),
    .rvfi_mem_rdata(rvfi_mem_rdata),
`ifdef RISCV_FORMAL_CSR_MISA
    .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata),
    .spec_csr_misa_rmask(spec_insn_sd_csr_misa_rmask),
`endif
    .spec_valid(spec_insn_sd_valid),
    .spec_trap(spec_insn_sd_trap),
    .spec_rs1_addr(spec_insn_sd_rs1_addr),
    .spec_rs2_addr(spec_insn_sd_rs2_addr),
    .spec_rd_addr(spec_insn_sd_rd_addr),
    .spec_rd_wdata(spec_insn_sd_rd_wdata),
    .spec_pc_wdata(spec_insn_sd_pc_wdata),
    .spec_mem_addr(spec_insn_sd_mem_addr),
    .spec_mem_rmask(spec_insn_sd_mem_rmask),
    .spec_mem_wmask(spec_insn_sd_mem_wmask),
    .spec_mem_wdata(spec_insn_sd_mem_wdata)
  );

  wire                                spec_insn_sext_b_valid;
  wire                                spec_insn_sext_b_trap;
  wire [                       4 : 0] spec_insn_sext_b_rs1_addr;
  wire [                       4 : 0] spec_insn_sext_b_rs2_addr;
  wire [                       4 : 0] spec_insn_sext_b_rd_addr;
  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_sext_b_rd_wdata;
  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_sext_b_pc_wdata;
  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_sext_b_mem_addr;
  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_sext_b_mem_rmask;
  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_sext_b_mem_wmask;
  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_sext_b_mem_wdata;
`ifdef RISCV_FORMAL_CSR_MISA
  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_sext_b_csr_misa_rmask;
`endif

  rvfi_insn_sext_b insn_sext_b (
    .rvfi_valid(rvfi_valid),
    .rvfi_insn(rvfi_insn),
    .rvfi_pc_rdata(rvfi_pc_rdata),
    .rvfi_rs1_rdata(rvfi_rs1_rdata),
    .rvfi_rs2_rdata(rvfi_rs2_rdata),
    .rvfi_mem_rdata(rvfi_mem_rdata),
`ifdef RISCV_FORMAL_CSR_MISA
    .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata),
    .spec_csr_misa_rmask(spec_insn_sext_b_csr_misa_rmask),
`endif
    .spec_valid(spec_insn_sext_b_valid),
    .spec_trap(spec_insn_sext_b_trap),
    .spec_rs1_addr(spec_insn_sext_b_rs1_addr),
    .spec_rs2_addr(spec_insn_sext_b_rs2_addr),
    .spec_rd_addr(spec_insn_sext_b_rd_addr),
    .spec_rd_wdata(spec_insn_sext_b_rd_wdata),
    .spec_pc_wdata(spec_insn_sext_b_pc_wdata),
    .spec_mem_addr(spec_insn_sext_b_mem_addr),
    .spec_mem_rmask(spec_insn_sext_b_mem_rmask),
    .spec_mem_wmask(spec_insn_sext_b_mem_wmask),
    .spec_mem_wdata(spec_insn_sext_b_mem_wdata)
  );

  wire                                spec_insn_sext_h_valid;
  wire                                spec_insn_sext_h_trap;
  wire [                       4 : 0] spec_insn_sext_h_rs1_addr;
  wire [                       4 : 0] spec_insn_sext_h_rs2_addr;
  wire [                       4 : 0] spec_insn_sext_h_rd_addr;
  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_sext_h_rd_wdata;
  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_sext_h_pc_wdata;
  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_sext_h_mem_addr;
  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_sext_h_mem_rmask;
  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_sext_h_mem_wmask;
  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_sext_h_mem_wdata;
`ifdef RISCV_FORMAL_CSR_MISA
  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_sext_h_csr_misa_rmask;
`endif

  rvfi_insn_sext_h insn_sext_h (
    .rvfi_valid(rvfi_valid),
    .rvfi_insn(rvfi_insn),
    .rvfi_pc_rdata(rvfi_pc_rdata),
    .rvfi_rs1_rdata(rvfi_rs1_rdata),
    .rvfi_rs2_rdata(rvfi_rs2_rdata),
    .rvfi_mem_rdata(rvfi_mem_rdata),
`ifdef RISCV_FORMAL_CSR_MISA
    .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata),
    .spec_csr_misa_rmask(spec_insn_sext_h_csr_misa_rmask),
`endif
    .spec_valid(spec_insn_sext_h_valid),
    .spec_trap(spec_insn_sext_h_trap),
    .spec_rs1_addr(spec_insn_sext_h_rs1_addr),
    .spec_rs2_addr(spec_insn_sext_h_rs2_addr),
    .spec_rd_addr(spec_insn_sext_h_rd_addr),
    .spec_rd_wdata(spec_insn_sext_h_rd_wdata),
    .spec_pc_wdata(spec_insn_sext_h_pc_wdata),
    .spec_mem_addr(spec_insn_sext_h_mem_addr),
    .spec_mem_rmask(spec_insn_sext_h_mem_rmask),
    .spec_mem_wmask(spec_insn_sext_h_mem_wmask),
    .spec_mem_wdata(spec_insn_sext_h_mem_wdata)
  );

  wire                                spec_insn_sh_valid;
  wire                                spec_insn_sh_trap;
  wire [                       4 : 0] spec_insn_sh_rs1_addr;
  wire [                       4 : 0] spec_insn_sh_rs2_addr;
  wire [                       4 : 0] spec_insn_sh_rd_addr;
  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_sh_rd_wdata;
  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_sh_pc_wdata;
  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_sh_mem_addr;
  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_sh_mem_rmask;
  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_sh_mem_wmask;
  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_sh_mem_wdata;
`ifdef RISCV_FORMAL_CSR_MISA
  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_sh_csr_misa_rmask;
`endif

  rvfi_insn_sh insn_sh (
    .rvfi_valid(rvfi_valid),
    .rvfi_insn(rvfi_insn),
    .rvfi_pc_rdata(rvfi_pc_rdata),
    .rvfi_rs1_rdata(rvfi_rs1_rdata),
    .rvfi_rs2_rdata(rvfi_rs2_rdata),
    .rvfi_mem_rdata(rvfi_mem_rdata),
`ifdef RISCV_FORMAL_CSR_MISA
    .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata),
    .spec_csr_misa_rmask(spec_insn_sh_csr_misa_rmask),
`endif
    .spec_valid(spec_insn_sh_valid),
    .spec_trap(spec_insn_sh_trap),
    .spec_rs1_addr(spec_insn_sh_rs1_addr),
    .spec_rs2_addr(spec_insn_sh_rs2_addr),
    .spec_rd_addr(spec_insn_sh_rd_addr),
    .spec_rd_wdata(spec_insn_sh_rd_wdata),
    .spec_pc_wdata(spec_insn_sh_pc_wdata),
    .spec_mem_addr(spec_insn_sh_mem_addr),
    .spec_mem_rmask(spec_insn_sh_mem_rmask),
    .spec_mem_wmask(spec_insn_sh_mem_wmask),
    .spec_mem_wdata(spec_insn_sh_mem_wdata)
  );

  wire                                spec_insn_sh1add_valid;
  wire                                spec_insn_sh1add_trap;
  wire [                       4 : 0] spec_insn_sh1add_rs1_addr;
  wire [                       4 : 0] spec_insn_sh1add_rs2_addr;
  wire [                       4 : 0] spec_insn_sh1add_rd_addr;
  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_sh1add_rd_wdata;
  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_sh1add_pc_wdata;
  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_sh1add_mem_addr;
  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_sh1add_mem_rmask;
  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_sh1add_mem_wmask;
  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_sh1add_mem_wdata;
`ifdef RISCV_FORMAL_CSR_MISA
  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_sh1add_csr_misa_rmask;
`endif

  rvfi_insn_sh1add insn_sh1add (
    .rvfi_valid(rvfi_valid),
    .rvfi_insn(rvfi_insn),
    .rvfi_pc_rdata(rvfi_pc_rdata),
    .rvfi_rs1_rdata(rvfi_rs1_rdata),
    .rvfi_rs2_rdata(rvfi_rs2_rdata),
    .rvfi_mem_rdata(rvfi_mem_rdata),
`ifdef RISCV_FORMAL_CSR_MISA
    .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata),
    .spec_csr_misa_rmask(spec_insn_sh1add_csr_misa_rmask),
`endif
    .spec_valid(spec_insn_sh1add_valid),
    .spec_trap(spec_insn_sh1add_trap),
    .spec_rs1_addr(spec_insn_sh1add_rs1_addr),
    .spec_rs2_addr(spec_insn_sh1add_rs2_addr),
    .spec_rd_addr(spec_insn_sh1add_rd_addr),
    .spec_rd_wdata(spec_insn_sh1add_rd_wdata),
    .spec_pc_wdata(spec_insn_sh1add_pc_wdata),
    .spec_mem_addr(spec_insn_sh1add_mem_addr),
    .spec_mem_rmask(spec_insn_sh1add_mem_rmask),
    .spec_mem_wmask(spec_insn_sh1add_mem_wmask),
    .spec_mem_wdata(spec_insn_sh1add_mem_wdata)
  );

  wire                                spec_insn_sh1add_uw_valid;
  wire                                spec_insn_sh1add_uw_trap;
  wire [                       4 : 0] spec_insn_sh1add_uw_rs1_addr;
  wire [                       4 : 0] spec_insn_sh1add_uw_rs2_addr;
  wire [                       4 : 0] spec_insn_sh1add_uw_rd_addr;
  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_sh1add_uw_rd_wdata;
  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_sh1add_uw_pc_wdata;
  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_sh1add_uw_mem_addr;
  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_sh1add_uw_mem_rmask;
  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_sh1add_uw_mem_wmask;
  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_sh1add_uw_mem_wdata;
`ifdef RISCV_FORMAL_CSR_MISA
  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_sh1add_uw_csr_misa_rmask;
`endif

  rvfi_insn_sh1add_uw insn_sh1add_uw (
    .rvfi_valid(rvfi_valid),
    .rvfi_insn(rvfi_insn),
    .rvfi_pc_rdata(rvfi_pc_rdata),
    .rvfi_rs1_rdata(rvfi_rs1_rdata),
    .rvfi_rs2_rdata(rvfi_rs2_rdata),
    .rvfi_mem_rdata(rvfi_mem_rdata),
`ifdef RISCV_FORMAL_CSR_MISA
    .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata),
    .spec_csr_misa_rmask(spec_insn_sh1add_uw_csr_misa_rmask),
`endif
    .spec_valid(spec_insn_sh1add_uw_valid),
    .spec_trap(spec_insn_sh1add_uw_trap),
    .spec_rs1_addr(spec_insn_sh1add_uw_rs1_addr),
    .spec_rs2_addr(spec_insn_sh1add_uw_rs2_addr),
    .spec_rd_addr(spec_insn_sh1add_uw_rd_addr),
    .spec_rd_wdata(spec_insn_sh1add_uw_rd_wdata),
    .spec_pc_wdata(spec_insn_sh1add_uw_pc_wdata),
    .spec_mem_addr(spec_insn_sh1add_uw_mem_addr),
    .spec_mem_rmask(spec_insn_sh1add_uw_mem_rmask),
    .spec_mem_wmask(spec_insn_sh1add_uw_mem_wmask),
    .spec_mem_wdata(spec_insn_sh1add_uw_mem_wdata)
  );

  wire                                spec_insn_sh2add_valid;
  wire                                spec_insn_sh2add_trap;
  wire [                       4 : 0] spec_insn_sh2add_rs1_addr;
  wire [                       4 : 0] spec_insn_sh2add_rs2_addr;
  wire [                       4 : 0] spec_insn_sh2add_rd_addr;
  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_sh2add_rd_wdata;
  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_sh2add_pc_wdata;
  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_sh2add_mem_addr;
  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_sh2add_mem_rmask;
  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_sh2add_mem_wmask;
  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_sh2add_mem_wdata;
`ifdef RISCV_FORMAL_CSR_MISA
  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_sh2add_csr_misa_rmask;
`endif

  rvfi_insn_sh2add insn_sh2add (
    .rvfi_valid(rvfi_valid),
    .rvfi_insn(rvfi_insn),
    .rvfi_pc_rdata(rvfi_pc_rdata),
    .rvfi_rs1_rdata(rvfi_rs1_rdata),
    .rvfi_rs2_rdata(rvfi_rs2_rdata),
    .rvfi_mem_rdata(rvfi_mem_rdata),
`ifdef RISCV_FORMAL_CSR_MISA
    .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata),
    .spec_csr_misa_rmask(spec_insn_sh2add_csr_misa_rmask),
`endif
    .spec_valid(spec_insn_sh2add_valid),
    .spec_trap(spec_insn_sh2add_trap),
    .spec_rs1_addr(spec_insn_sh2add_rs1_addr),
    .spec_rs2_addr(spec_insn_sh2add_rs2_addr),
    .spec_rd_addr(spec_insn_sh2add_rd_addr),
    .spec_rd_wdata(spec_insn_sh2add_rd_wdata),
    .spec_pc_wdata(spec_insn_sh2add_pc_wdata),
    .spec_mem_addr(spec_insn_sh2add_mem_addr),
    .spec_mem_rmask(spec_insn_sh2add_mem_rmask),
    .spec_mem_wmask(spec_insn_sh2add_mem_wmask),
    .spec_mem_wdata(spec_insn_sh2add_mem_wdata)
  );

  wire                                spec_insn_sh2add_uw_valid;
  wire                                spec_insn_sh2add_uw_trap;
  wire [                       4 : 0] spec_insn_sh2add_uw_rs1_addr;
  wire [                       4 : 0] spec_insn_sh2add_uw_rs2_addr;
  wire [                       4 : 0] spec_insn_sh2add_uw_rd_addr;
  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_sh2add_uw_rd_wdata;
  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_sh2add_uw_pc_wdata;
  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_sh2add_uw_mem_addr;
  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_sh2add_uw_mem_rmask;
  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_sh2add_uw_mem_wmask;
  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_sh2add_uw_mem_wdata;
`ifdef RISCV_FORMAL_CSR_MISA
  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_sh2add_uw_csr_misa_rmask;
`endif

  rvfi_insn_sh2add_uw insn_sh2add_uw (
    .rvfi_valid(rvfi_valid),
    .rvfi_insn(rvfi_insn),
    .rvfi_pc_rdata(rvfi_pc_rdata),
    .rvfi_rs1_rdata(rvfi_rs1_rdata),
    .rvfi_rs2_rdata(rvfi_rs2_rdata),
    .rvfi_mem_rdata(rvfi_mem_rdata),
`ifdef RISCV_FORMAL_CSR_MISA
    .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata),
    .spec_csr_misa_rmask(spec_insn_sh2add_uw_csr_misa_rmask),
`endif
    .spec_valid(spec_insn_sh2add_uw_valid),
    .spec_trap(spec_insn_sh2add_uw_trap),
    .spec_rs1_addr(spec_insn_sh2add_uw_rs1_addr),
    .spec_rs2_addr(spec_insn_sh2add_uw_rs2_addr),
    .spec_rd_addr(spec_insn_sh2add_uw_rd_addr),
    .spec_rd_wdata(spec_insn_sh2add_uw_rd_wdata),
    .spec_pc_wdata(spec_insn_sh2add_uw_pc_wdata),
    .spec_mem_addr(spec_insn_sh2add_uw_mem_addr),
    .spec_mem_rmask(spec_insn_sh2add_uw_mem_rmask),
    .spec_mem_wmask(spec_insn_sh2add_uw_mem_wmask),
    .spec_mem_wdata(spec_insn_sh2add_uw_mem_wdata)
  );

  wire                                spec_insn_sh3add_valid;
  wire                                spec_insn_sh3add_trap;
  wire [                       4 : 0] spec_insn_sh3add_rs1_addr;
  wire [                       4 : 0] spec_insn_sh3add_rs2_addr;
  wire [                       4 : 0] spec_insn_sh3add_rd_addr;
  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_sh3add_rd_wdata;
  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_sh3add_pc_wdata;
  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_sh3add_mem_addr;
  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_sh3add_mem_rmask;
  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_sh3add_mem_wmask;
  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_sh3add_mem_wdata;
`ifdef RISCV_FORMAL_CSR_MISA
  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_sh3add_csr_misa_rmask;
`endif

  rvfi_insn_sh3add insn_sh3add (
    .rvfi_valid(rvfi_valid),
    .rvfi_insn(rvfi_insn),
    .rvfi_pc_rdata(rvfi_pc_rdata),
    .rvfi_rs1_rdata(rvfi_rs1_rdata),
    .rvfi_rs2_rdata(rvfi_rs2_rdata),
    .rvfi_mem_rdata(rvfi_mem_rdata),
`ifdef RISCV_FORMAL_CSR_MISA
    .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata),
    .spec_csr_misa_rmask(spec_insn_sh3add_csr_misa_rmask),
`endif
    .spec_valid(spec_insn_sh3add_valid),
    .spec_trap(spec_insn_sh3add_trap),
    .spec_rs1_addr(spec_insn_sh3add_rs1_addr),
    .spec_rs2_addr(spec_insn_sh3add_rs2_addr),
    .spec_rd_addr(spec_insn_sh3add_rd_addr),
    .spec_rd_wdata(spec_insn_sh3add_rd_wdata),
    .spec_pc_wdata(spec_insn_sh3add_pc_wdata),
    .spec_mem_addr(spec_insn_sh3add_mem_addr),
    .spec_mem_rmask(spec_insn_sh3add_mem_rmask),
    .spec_mem_wmask(spec_insn_sh3add_mem_wmask),
    .spec_mem_wdata(spec_insn_sh3add_mem_wdata)
  );

  wire                                spec_insn_sh3add_uw_valid;
  wire                                spec_insn_sh3add_uw_trap;
  wire [                       4 : 0] spec_insn_sh3add_uw_rs1_addr;
  wire [                       4 : 0] spec_insn_sh3add_uw_rs2_addr;
  wire [                       4 : 0] spec_insn_sh3add_uw_rd_addr;
  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_sh3add_uw_rd_wdata;
  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_sh3add_uw_pc_wdata;
  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_sh3add_uw_mem_addr;
  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_sh3add_uw_mem_rmask;
  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_sh3add_uw_mem_wmask;
  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_sh3add_uw_mem_wdata;
`ifdef RISCV_FORMAL_CSR_MISA
  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_sh3add_uw_csr_misa_rmask;
`endif

  rvfi_insn_sh3add_uw insn_sh3add_uw (
    .rvfi_valid(rvfi_valid),
    .rvfi_insn(rvfi_insn),
    .rvfi_pc_rdata(rvfi_pc_rdata),
    .rvfi_rs1_rdata(rvfi_rs1_rdata),
    .rvfi_rs2_rdata(rvfi_rs2_rdata),
    .rvfi_mem_rdata(rvfi_mem_rdata),
`ifdef RISCV_FORMAL_CSR_MISA
    .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata),
    .spec_csr_misa_rmask(spec_insn_sh3add_uw_csr_misa_rmask),
`endif
    .spec_valid(spec_insn_sh3add_uw_valid),
    .spec_trap(spec_insn_sh3add_uw_trap),
    .spec_rs1_addr(spec_insn_sh3add_uw_rs1_addr),
    .spec_rs2_addr(spec_insn_sh3add_uw_rs2_addr),
    .spec_rd_addr(spec_insn_sh3add_uw_rd_addr),
    .spec_rd_wdata(spec_insn_sh3add_uw_rd_wdata),
    .spec_pc_wdata(spec_insn_sh3add_uw_pc_wdata),
    .spec_mem_addr(spec_insn_sh3add_uw_mem_addr),
    .spec_mem_rmask(spec_insn_sh3add_uw_mem_rmask),
    .spec_mem_wmask(spec_insn_sh3add_uw_mem_wmask),
    .spec_mem_wdata(spec_insn_sh3add_uw_mem_wdata)
  );

  wire                                spec_insn_sll_valid;
  wire                                spec_insn_sll_trap;
  wire [                       4 : 0] spec_insn_sll_rs1_addr;
  wire [                       4 : 0] spec_insn_sll_rs2_addr;
  wire [                       4 : 0] spec_insn_sll_rd_addr;
  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_sll_rd_wdata;
  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_sll_pc_wdata;
  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_sll_mem_addr;
  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_sll_mem_rmask;
  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_sll_mem_wmask;
  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_sll_mem_wdata;
`ifdef RISCV_FORMAL_CSR_MISA
  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_sll_csr_misa_rmask;
`endif

  rvfi_insn_sll insn_sll (
    .rvfi_valid(rvfi_valid),
    .rvfi_insn(rvfi_insn),
    .rvfi_pc_rdata(rvfi_pc_rdata),
    .rvfi_rs1_rdata(rvfi_rs1_rdata),
    .rvfi_rs2_rdata(rvfi_rs2_rdata),
    .rvfi_mem_rdata(rvfi_mem_rdata),
`ifdef RISCV_FORMAL_CSR_MISA
    .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata),
    .spec_csr_misa_rmask(spec_insn_sll_csr_misa_rmask),
`endif
    .spec_valid(spec_insn_sll_valid),
    .spec_trap(spec_insn_sll_trap),
    .spec_rs1_addr(spec_insn_sll_rs1_addr),
    .spec_rs2_addr(spec_insn_sll_rs2_addr),
    .spec_rd_addr(spec_insn_sll_rd_addr),
    .spec_rd_wdata(spec_insn_sll_rd_wdata),
    .spec_pc_wdata(spec_insn_sll_pc_wdata),
    .spec_mem_addr(spec_insn_sll_mem_addr),
    .spec_mem_rmask(spec_insn_sll_mem_rmask),
    .spec_mem_wmask(spec_insn_sll_mem_wmask),
    .spec_mem_wdata(spec_insn_sll_mem_wdata)
  );

  wire                                spec_insn_slli_valid;
  wire                                spec_insn_slli_trap;
  wire [                       4 : 0] spec_insn_slli_rs1_addr;
  wire [                       4 : 0] spec_insn_slli_rs2_addr;
  wire [                       4 : 0] spec_insn_slli_rd_addr;
  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_slli_rd_wdata;
  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_slli_pc_wdata;
  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_slli_mem_addr;
  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_slli_mem_rmask;
  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_slli_mem_wmask;
  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_slli_mem_wdata;
`ifdef RISCV_FORMAL_CSR_MISA
  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_slli_csr_misa_rmask;
`endif

  rvfi_insn_slli insn_slli (
    .rvfi_valid(rvfi_valid),
    .rvfi_insn(rvfi_insn),
    .rvfi_pc_rdata(rvfi_pc_rdata),
    .rvfi_rs1_rdata(rvfi_rs1_rdata),
    .rvfi_rs2_rdata(rvfi_rs2_rdata),
    .rvfi_mem_rdata(rvfi_mem_rdata),
`ifdef RISCV_FORMAL_CSR_MISA
    .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata),
    .spec_csr_misa_rmask(spec_insn_slli_csr_misa_rmask),
`endif
    .spec_valid(spec_insn_slli_valid),
    .spec_trap(spec_insn_slli_trap),
    .spec_rs1_addr(spec_insn_slli_rs1_addr),
    .spec_rs2_addr(spec_insn_slli_rs2_addr),
    .spec_rd_addr(spec_insn_slli_rd_addr),
    .spec_rd_wdata(spec_insn_slli_rd_wdata),
    .spec_pc_wdata(spec_insn_slli_pc_wdata),
    .spec_mem_addr(spec_insn_slli_mem_addr),
    .spec_mem_rmask(spec_insn_slli_mem_rmask),
    .spec_mem_wmask(spec_insn_slli_mem_wmask),
    .spec_mem_wdata(spec_insn_slli_mem_wdata)
  );

  wire                                spec_insn_slli_uw_valid;
  wire                                spec_insn_slli_uw_trap;
  wire [                       4 : 0] spec_insn_slli_uw_rs1_addr;
  wire [                       4 : 0] spec_insn_slli_uw_rs2_addr;
  wire [                       4 : 0] spec_insn_slli_uw_rd_addr;
  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_slli_uw_rd_wdata;
  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_slli_uw_pc_wdata;
  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_slli_uw_mem_addr;
  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_slli_uw_mem_rmask;
  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_slli_uw_mem_wmask;
  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_slli_uw_mem_wdata;
`ifdef RISCV_FORMAL_CSR_MISA
  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_slli_uw_csr_misa_rmask;
`endif

  rvfi_insn_slli_uw insn_slli_uw (
    .rvfi_valid(rvfi_valid),
    .rvfi_insn(rvfi_insn),
    .rvfi_pc_rdata(rvfi_pc_rdata),
    .rvfi_rs1_rdata(rvfi_rs1_rdata),
    .rvfi_rs2_rdata(rvfi_rs2_rdata),
    .rvfi_mem_rdata(rvfi_mem_rdata),
`ifdef RISCV_FORMAL_CSR_MISA
    .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata),
    .spec_csr_misa_rmask(spec_insn_slli_uw_csr_misa_rmask),
`endif
    .spec_valid(spec_insn_slli_uw_valid),
    .spec_trap(spec_insn_slli_uw_trap),
    .spec_rs1_addr(spec_insn_slli_uw_rs1_addr),
    .spec_rs2_addr(spec_insn_slli_uw_rs2_addr),
    .spec_rd_addr(spec_insn_slli_uw_rd_addr),
    .spec_rd_wdata(spec_insn_slli_uw_rd_wdata),
    .spec_pc_wdata(spec_insn_slli_uw_pc_wdata),
    .spec_mem_addr(spec_insn_slli_uw_mem_addr),
    .spec_mem_rmask(spec_insn_slli_uw_mem_rmask),
    .spec_mem_wmask(spec_insn_slli_uw_mem_wmask),
    .spec_mem_wdata(spec_insn_slli_uw_mem_wdata)
  );

  wire                                spec_insn_slliw_valid;
  wire                                spec_insn_slliw_trap;
  wire [                       4 : 0] spec_insn_slliw_rs1_addr;
  wire [                       4 : 0] spec_insn_slliw_rs2_addr;
  wire [                       4 : 0] spec_insn_slliw_rd_addr;
  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_slliw_rd_wdata;
  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_slliw_pc_wdata;
  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_slliw_mem_addr;
  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_slliw_mem_rmask;
  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_slliw_mem_wmask;
  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_slliw_mem_wdata;
`ifdef RISCV_FORMAL_CSR_MISA
  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_slliw_csr_misa_rmask;
`endif

  rvfi_insn_slliw insn_slliw (
    .rvfi_valid(rvfi_valid),
    .rvfi_insn(rvfi_insn),
    .rvfi_pc_rdata(rvfi_pc_rdata),
    .rvfi_rs1_rdata(rvfi_rs1_rdata),
    .rvfi_rs2_rdata(rvfi_rs2_rdata),
    .rvfi_mem_rdata(rvfi_mem_rdata),
`ifdef RISCV_FORMAL_CSR_MISA
    .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata),
    .spec_csr_misa_rmask(spec_insn_slliw_csr_misa_rmask),
`endif
    .spec_valid(spec_insn_slliw_valid),
    .spec_trap(spec_insn_slliw_trap),
    .spec_rs1_addr(spec_insn_slliw_rs1_addr),
    .spec_rs2_addr(spec_insn_slliw_rs2_addr),
    .spec_rd_addr(spec_insn_slliw_rd_addr),
    .spec_rd_wdata(spec_insn_slliw_rd_wdata),
    .spec_pc_wdata(spec_insn_slliw_pc_wdata),
    .spec_mem_addr(spec_insn_slliw_mem_addr),
    .spec_mem_rmask(spec_insn_slliw_mem_rmask),
    .spec_mem_wmask(spec_insn_slliw_mem_wmask),
    .spec_mem_wdata(spec_insn_slliw_mem_wdata)
  );

  wire                                spec_insn_sllw_valid;
  wire                                spec_insn_sllw_trap;
  wire [                       4 : 0] spec_insn_sllw_rs1_addr;
  wire [                       4 : 0] spec_insn_sllw_rs2_addr;
  wire [                       4 : 0] spec_insn_sllw_rd_addr;
  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_sllw_rd_wdata;
  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_sllw_pc_wdata;
  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_sllw_mem_addr;
  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_sllw_mem_rmask;
  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_sllw_mem_wmask;
  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_sllw_mem_wdata;
`ifdef RISCV_FORMAL_CSR_MISA
  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_sllw_csr_misa_rmask;
`endif

  rvfi_insn_sllw insn_sllw (
    .rvfi_valid(rvfi_valid),
    .rvfi_insn(rvfi_insn),
    .rvfi_pc_rdata(rvfi_pc_rdata),
    .rvfi_rs1_rdata(rvfi_rs1_rdata),
    .rvfi_rs2_rdata(rvfi_rs2_rdata),
    .rvfi_mem_rdata(rvfi_mem_rdata),
`ifdef RISCV_FORMAL_CSR_MISA
    .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata),
    .spec_csr_misa_rmask(spec_insn_sllw_csr_misa_rmask),
`endif
    .spec_valid(spec_insn_sllw_valid),
    .spec_trap(spec_insn_sllw_trap),
    .spec_rs1_addr(spec_insn_sllw_rs1_addr),
    .spec_rs2_addr(spec_insn_sllw_rs2_addr),
    .spec_rd_addr(spec_insn_sllw_rd_addr),
    .spec_rd_wdata(spec_insn_sllw_rd_wdata),
    .spec_pc_wdata(spec_insn_sllw_pc_wdata),
    .spec_mem_addr(spec_insn_sllw_mem_addr),
    .spec_mem_rmask(spec_insn_sllw_mem_rmask),
    .spec_mem_wmask(spec_insn_sllw_mem_wmask),
    .spec_mem_wdata(spec_insn_sllw_mem_wdata)
  );

  wire                                spec_insn_slt_valid;
  wire                                spec_insn_slt_trap;
  wire [                       4 : 0] spec_insn_slt_rs1_addr;
  wire [                       4 : 0] spec_insn_slt_rs2_addr;
  wire [                       4 : 0] spec_insn_slt_rd_addr;
  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_slt_rd_wdata;
  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_slt_pc_wdata;
  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_slt_mem_addr;
  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_slt_mem_rmask;
  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_slt_mem_wmask;
  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_slt_mem_wdata;
`ifdef RISCV_FORMAL_CSR_MISA
  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_slt_csr_misa_rmask;
`endif

  rvfi_insn_slt insn_slt (
    .rvfi_valid(rvfi_valid),
    .rvfi_insn(rvfi_insn),
    .rvfi_pc_rdata(rvfi_pc_rdata),
    .rvfi_rs1_rdata(rvfi_rs1_rdata),
    .rvfi_rs2_rdata(rvfi_rs2_rdata),
    .rvfi_mem_rdata(rvfi_mem_rdata),
`ifdef RISCV_FORMAL_CSR_MISA
    .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata),
    .spec_csr_misa_rmask(spec_insn_slt_csr_misa_rmask),
`endif
    .spec_valid(spec_insn_slt_valid),
    .spec_trap(spec_insn_slt_trap),
    .spec_rs1_addr(spec_insn_slt_rs1_addr),
    .spec_rs2_addr(spec_insn_slt_rs2_addr),
    .spec_rd_addr(spec_insn_slt_rd_addr),
    .spec_rd_wdata(spec_insn_slt_rd_wdata),
    .spec_pc_wdata(spec_insn_slt_pc_wdata),
    .spec_mem_addr(spec_insn_slt_mem_addr),
    .spec_mem_rmask(spec_insn_slt_mem_rmask),
    .spec_mem_wmask(spec_insn_slt_mem_wmask),
    .spec_mem_wdata(spec_insn_slt_mem_wdata)
  );

  wire                                spec_insn_slti_valid;
  wire                                spec_insn_slti_trap;
  wire [                       4 : 0] spec_insn_slti_rs1_addr;
  wire [                       4 : 0] spec_insn_slti_rs2_addr;
  wire [                       4 : 0] spec_insn_slti_rd_addr;
  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_slti_rd_wdata;
  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_slti_pc_wdata;
  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_slti_mem_addr;
  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_slti_mem_rmask;
  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_slti_mem_wmask;
  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_slti_mem_wdata;
`ifdef RISCV_FORMAL_CSR_MISA
  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_slti_csr_misa_rmask;
`endif

  rvfi_insn_slti insn_slti (
    .rvfi_valid(rvfi_valid),
    .rvfi_insn(rvfi_insn),
    .rvfi_pc_rdata(rvfi_pc_rdata),
    .rvfi_rs1_rdata(rvfi_rs1_rdata),
    .rvfi_rs2_rdata(rvfi_rs2_rdata),
    .rvfi_mem_rdata(rvfi_mem_rdata),
`ifdef RISCV_FORMAL_CSR_MISA
    .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata),
    .spec_csr_misa_rmask(spec_insn_slti_csr_misa_rmask),
`endif
    .spec_valid(spec_insn_slti_valid),
    .spec_trap(spec_insn_slti_trap),
    .spec_rs1_addr(spec_insn_slti_rs1_addr),
    .spec_rs2_addr(spec_insn_slti_rs2_addr),
    .spec_rd_addr(spec_insn_slti_rd_addr),
    .spec_rd_wdata(spec_insn_slti_rd_wdata),
    .spec_pc_wdata(spec_insn_slti_pc_wdata),
    .spec_mem_addr(spec_insn_slti_mem_addr),
    .spec_mem_rmask(spec_insn_slti_mem_rmask),
    .spec_mem_wmask(spec_insn_slti_mem_wmask),
    .spec_mem_wdata(spec_insn_slti_mem_wdata)
  );

  wire                                spec_insn_sltiu_valid;
  wire                                spec_insn_sltiu_trap;
  wire [                       4 : 0] spec_insn_sltiu_rs1_addr;
  wire [                       4 : 0] spec_insn_sltiu_rs2_addr;
  wire [                       4 : 0] spec_insn_sltiu_rd_addr;
  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_sltiu_rd_wdata;
  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_sltiu_pc_wdata;
  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_sltiu_mem_addr;
  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_sltiu_mem_rmask;
  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_sltiu_mem_wmask;
  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_sltiu_mem_wdata;
`ifdef RISCV_FORMAL_CSR_MISA
  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_sltiu_csr_misa_rmask;
`endif

  rvfi_insn_sltiu insn_sltiu (
    .rvfi_valid(rvfi_valid),
    .rvfi_insn(rvfi_insn),
    .rvfi_pc_rdata(rvfi_pc_rdata),
    .rvfi_rs1_rdata(rvfi_rs1_rdata),
    .rvfi_rs2_rdata(rvfi_rs2_rdata),
    .rvfi_mem_rdata(rvfi_mem_rdata),
`ifdef RISCV_FORMAL_CSR_MISA
    .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata),
    .spec_csr_misa_rmask(spec_insn_sltiu_csr_misa_rmask),
`endif
    .spec_valid(spec_insn_sltiu_valid),
    .spec_trap(spec_insn_sltiu_trap),
    .spec_rs1_addr(spec_insn_sltiu_rs1_addr),
    .spec_rs2_addr(spec_insn_sltiu_rs2_addr),
    .spec_rd_addr(spec_insn_sltiu_rd_addr),
    .spec_rd_wdata(spec_insn_sltiu_rd_wdata),
    .spec_pc_wdata(spec_insn_sltiu_pc_wdata),
    .spec_mem_addr(spec_insn_sltiu_mem_addr),
    .spec_mem_rmask(spec_insn_sltiu_mem_rmask),
    .spec_mem_wmask(spec_insn_sltiu_mem_wmask),
    .spec_mem_wdata(spec_insn_sltiu_mem_wdata)
  );

  wire                                spec_insn_sltu_valid;
  wire                                spec_insn_sltu_trap;
  wire [                       4 : 0] spec_insn_sltu_rs1_addr;
  wire [                       4 : 0] spec_insn_sltu_rs2_addr;
  wire [                       4 : 0] spec_insn_sltu_rd_addr;
  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_sltu_rd_wdata;
  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_sltu_pc_wdata;
  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_sltu_mem_addr;
  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_sltu_mem_rmask;
  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_sltu_mem_wmask;
  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_sltu_mem_wdata;
`ifdef RISCV_FORMAL_CSR_MISA
  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_sltu_csr_misa_rmask;
`endif

  rvfi_insn_sltu insn_sltu (
    .rvfi_valid(rvfi_valid),
    .rvfi_insn(rvfi_insn),
    .rvfi_pc_rdata(rvfi_pc_rdata),
    .rvfi_rs1_rdata(rvfi_rs1_rdata),
    .rvfi_rs2_rdata(rvfi_rs2_rdata),
    .rvfi_mem_rdata(rvfi_mem_rdata),
`ifdef RISCV_FORMAL_CSR_MISA
    .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata),
    .spec_csr_misa_rmask(spec_insn_sltu_csr_misa_rmask),
`endif
    .spec_valid(spec_insn_sltu_valid),
    .spec_trap(spec_insn_sltu_trap),
    .spec_rs1_addr(spec_insn_sltu_rs1_addr),
    .spec_rs2_addr(spec_insn_sltu_rs2_addr),
    .spec_rd_addr(spec_insn_sltu_rd_addr),
    .spec_rd_wdata(spec_insn_sltu_rd_wdata),
    .spec_pc_wdata(spec_insn_sltu_pc_wdata),
    .spec_mem_addr(spec_insn_sltu_mem_addr),
    .spec_mem_rmask(spec_insn_sltu_mem_rmask),
    .spec_mem_wmask(spec_insn_sltu_mem_wmask),
    .spec_mem_wdata(spec_insn_sltu_mem_wdata)
  );

  wire                                spec_insn_sra_valid;
  wire                                spec_insn_sra_trap;
  wire [                       4 : 0] spec_insn_sra_rs1_addr;
  wire [                       4 : 0] spec_insn_sra_rs2_addr;
  wire [                       4 : 0] spec_insn_sra_rd_addr;
  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_sra_rd_wdata;
  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_sra_pc_wdata;
  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_sra_mem_addr;
  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_sra_mem_rmask;
  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_sra_mem_wmask;
  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_sra_mem_wdata;
`ifdef RISCV_FORMAL_CSR_MISA
  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_sra_csr_misa_rmask;
`endif

  rvfi_insn_sra insn_sra (
    .rvfi_valid(rvfi_valid),
    .rvfi_insn(rvfi_insn),
    .rvfi_pc_rdata(rvfi_pc_rdata),
    .rvfi_rs1_rdata(rvfi_rs1_rdata),
    .rvfi_rs2_rdata(rvfi_rs2_rdata),
    .rvfi_mem_rdata(rvfi_mem_rdata),
`ifdef RISCV_FORMAL_CSR_MISA
    .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata),
    .spec_csr_misa_rmask(spec_insn_sra_csr_misa_rmask),
`endif
    .spec_valid(spec_insn_sra_valid),
    .spec_trap(spec_insn_sra_trap),
    .spec_rs1_addr(spec_insn_sra_rs1_addr),
    .spec_rs2_addr(spec_insn_sra_rs2_addr),
    .spec_rd_addr(spec_insn_sra_rd_addr),
    .spec_rd_wdata(spec_insn_sra_rd_wdata),
    .spec_pc_wdata(spec_insn_sra_pc_wdata),
    .spec_mem_addr(spec_insn_sra_mem_addr),
    .spec_mem_rmask(spec_insn_sra_mem_rmask),
    .spec_mem_wmask(spec_insn_sra_mem_wmask),
    .spec_mem_wdata(spec_insn_sra_mem_wdata)
  );

  wire                                spec_insn_srai_valid;
  wire                                spec_insn_srai_trap;
  wire [                       4 : 0] spec_insn_srai_rs1_addr;
  wire [                       4 : 0] spec_insn_srai_rs2_addr;
  wire [                       4 : 0] spec_insn_srai_rd_addr;
  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_srai_rd_wdata;
  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_srai_pc_wdata;
  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_srai_mem_addr;
  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_srai_mem_rmask;
  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_srai_mem_wmask;
  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_srai_mem_wdata;
`ifdef RISCV_FORMAL_CSR_MISA
  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_srai_csr_misa_rmask;
`endif

  rvfi_insn_srai insn_srai (
    .rvfi_valid(rvfi_valid),
    .rvfi_insn(rvfi_insn),
    .rvfi_pc_rdata(rvfi_pc_rdata),
    .rvfi_rs1_rdata(rvfi_rs1_rdata),
    .rvfi_rs2_rdata(rvfi_rs2_rdata),
    .rvfi_mem_rdata(rvfi_mem_rdata),
`ifdef RISCV_FORMAL_CSR_MISA
    .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata),
    .spec_csr_misa_rmask(spec_insn_srai_csr_misa_rmask),
`endif
    .spec_valid(spec_insn_srai_valid),
    .spec_trap(spec_insn_srai_trap),
    .spec_rs1_addr(spec_insn_srai_rs1_addr),
    .spec_rs2_addr(spec_insn_srai_rs2_addr),
    .spec_rd_addr(spec_insn_srai_rd_addr),
    .spec_rd_wdata(spec_insn_srai_rd_wdata),
    .spec_pc_wdata(spec_insn_srai_pc_wdata),
    .spec_mem_addr(spec_insn_srai_mem_addr),
    .spec_mem_rmask(spec_insn_srai_mem_rmask),
    .spec_mem_wmask(spec_insn_srai_mem_wmask),
    .spec_mem_wdata(spec_insn_srai_mem_wdata)
  );

  wire                                spec_insn_sraiw_valid;
  wire                                spec_insn_sraiw_trap;
  wire [                       4 : 0] spec_insn_sraiw_rs1_addr;
  wire [                       4 : 0] spec_insn_sraiw_rs2_addr;
  wire [                       4 : 0] spec_insn_sraiw_rd_addr;
  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_sraiw_rd_wdata;
  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_sraiw_pc_wdata;
  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_sraiw_mem_addr;
  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_sraiw_mem_rmask;
  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_sraiw_mem_wmask;
  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_sraiw_mem_wdata;
`ifdef RISCV_FORMAL_CSR_MISA
  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_sraiw_csr_misa_rmask;
`endif

  rvfi_insn_sraiw insn_sraiw (
    .rvfi_valid(rvfi_valid),
    .rvfi_insn(rvfi_insn),
    .rvfi_pc_rdata(rvfi_pc_rdata),
    .rvfi_rs1_rdata(rvfi_rs1_rdata),
    .rvfi_rs2_rdata(rvfi_rs2_rdata),
    .rvfi_mem_rdata(rvfi_mem_rdata),
`ifdef RISCV_FORMAL_CSR_MISA
    .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata),
    .spec_csr_misa_rmask(spec_insn_sraiw_csr_misa_rmask),
`endif
    .spec_valid(spec_insn_sraiw_valid),
    .spec_trap(spec_insn_sraiw_trap),
    .spec_rs1_addr(spec_insn_sraiw_rs1_addr),
    .spec_rs2_addr(spec_insn_sraiw_rs2_addr),
    .spec_rd_addr(spec_insn_sraiw_rd_addr),
    .spec_rd_wdata(spec_insn_sraiw_rd_wdata),
    .spec_pc_wdata(spec_insn_sraiw_pc_wdata),
    .spec_mem_addr(spec_insn_sraiw_mem_addr),
    .spec_mem_rmask(spec_insn_sraiw_mem_rmask),
    .spec_mem_wmask(spec_insn_sraiw_mem_wmask),
    .spec_mem_wdata(spec_insn_sraiw_mem_wdata)
  );

  wire                                spec_insn_sraw_valid;
  wire                                spec_insn_sraw_trap;
  wire [                       4 : 0] spec_insn_sraw_rs1_addr;
  wire [                       4 : 0] spec_insn_sraw_rs2_addr;
  wire [                       4 : 0] spec_insn_sraw_rd_addr;
  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_sraw_rd_wdata;
  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_sraw_pc_wdata;
  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_sraw_mem_addr;
  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_sraw_mem_rmask;
  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_sraw_mem_wmask;
  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_sraw_mem_wdata;
`ifdef RISCV_FORMAL_CSR_MISA
  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_sraw_csr_misa_rmask;
`endif

  rvfi_insn_sraw insn_sraw (
    .rvfi_valid(rvfi_valid),
    .rvfi_insn(rvfi_insn),
    .rvfi_pc_rdata(rvfi_pc_rdata),
    .rvfi_rs1_rdata(rvfi_rs1_rdata),
    .rvfi_rs2_rdata(rvfi_rs2_rdata),
    .rvfi_mem_rdata(rvfi_mem_rdata),
`ifdef RISCV_FORMAL_CSR_MISA
    .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata),
    .spec_csr_misa_rmask(spec_insn_sraw_csr_misa_rmask),
`endif
    .spec_valid(spec_insn_sraw_valid),
    .spec_trap(spec_insn_sraw_trap),
    .spec_rs1_addr(spec_insn_sraw_rs1_addr),
    .spec_rs2_addr(spec_insn_sraw_rs2_addr),
    .spec_rd_addr(spec_insn_sraw_rd_addr),
    .spec_rd_wdata(spec_insn_sraw_rd_wdata),
    .spec_pc_wdata(spec_insn_sraw_pc_wdata),
    .spec_mem_addr(spec_insn_sraw_mem_addr),
    .spec_mem_rmask(spec_insn_sraw_mem_rmask),
    .spec_mem_wmask(spec_insn_sraw_mem_wmask),
    .spec_mem_wdata(spec_insn_sraw_mem_wdata)
  );

  wire                                spec_insn_srl_valid;
  wire                                spec_insn_srl_trap;
  wire [                       4 : 0] spec_insn_srl_rs1_addr;
  wire [                       4 : 0] spec_insn_srl_rs2_addr;
  wire [                       4 : 0] spec_insn_srl_rd_addr;
  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_srl_rd_wdata;
  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_srl_pc_wdata;
  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_srl_mem_addr;
  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_srl_mem_rmask;
  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_srl_mem_wmask;
  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_srl_mem_wdata;
`ifdef RISCV_FORMAL_CSR_MISA
  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_srl_csr_misa_rmask;
`endif

  rvfi_insn_srl insn_srl (
    .rvfi_valid(rvfi_valid),
    .rvfi_insn(rvfi_insn),
    .rvfi_pc_rdata(rvfi_pc_rdata),
    .rvfi_rs1_rdata(rvfi_rs1_rdata),
    .rvfi_rs2_rdata(rvfi_rs2_rdata),
    .rvfi_mem_rdata(rvfi_mem_rdata),
`ifdef RISCV_FORMAL_CSR_MISA
    .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata),
    .spec_csr_misa_rmask(spec_insn_srl_csr_misa_rmask),
`endif
    .spec_valid(spec_insn_srl_valid),
    .spec_trap(spec_insn_srl_trap),
    .spec_rs1_addr(spec_insn_srl_rs1_addr),
    .spec_rs2_addr(spec_insn_srl_rs2_addr),
    .spec_rd_addr(spec_insn_srl_rd_addr),
    .spec_rd_wdata(spec_insn_srl_rd_wdata),
    .spec_pc_wdata(spec_insn_srl_pc_wdata),
    .spec_mem_addr(spec_insn_srl_mem_addr),
    .spec_mem_rmask(spec_insn_srl_mem_rmask),
    .spec_mem_wmask(spec_insn_srl_mem_wmask),
    .spec_mem_wdata(spec_insn_srl_mem_wdata)
  );

  wire                                spec_insn_srli_valid;
  wire                                spec_insn_srli_trap;
  wire [                       4 : 0] spec_insn_srli_rs1_addr;
  wire [                       4 : 0] spec_insn_srli_rs2_addr;
  wire [                       4 : 0] spec_insn_srli_rd_addr;
  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_srli_rd_wdata;
  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_srli_pc_wdata;
  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_srli_mem_addr;
  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_srli_mem_rmask;
  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_srli_mem_wmask;
  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_srli_mem_wdata;
`ifdef RISCV_FORMAL_CSR_MISA
  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_srli_csr_misa_rmask;
`endif

  rvfi_insn_srli insn_srli (
    .rvfi_valid(rvfi_valid),
    .rvfi_insn(rvfi_insn),
    .rvfi_pc_rdata(rvfi_pc_rdata),
    .rvfi_rs1_rdata(rvfi_rs1_rdata),
    .rvfi_rs2_rdata(rvfi_rs2_rdata),
    .rvfi_mem_rdata(rvfi_mem_rdata),
`ifdef RISCV_FORMAL_CSR_MISA
    .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata),
    .spec_csr_misa_rmask(spec_insn_srli_csr_misa_rmask),
`endif
    .spec_valid(spec_insn_srli_valid),
    .spec_trap(spec_insn_srli_trap),
    .spec_rs1_addr(spec_insn_srli_rs1_addr),
    .spec_rs2_addr(spec_insn_srli_rs2_addr),
    .spec_rd_addr(spec_insn_srli_rd_addr),
    .spec_rd_wdata(spec_insn_srli_rd_wdata),
    .spec_pc_wdata(spec_insn_srli_pc_wdata),
    .spec_mem_addr(spec_insn_srli_mem_addr),
    .spec_mem_rmask(spec_insn_srli_mem_rmask),
    .spec_mem_wmask(spec_insn_srli_mem_wmask),
    .spec_mem_wdata(spec_insn_srli_mem_wdata)
  );

  wire                                spec_insn_srliw_valid;
  wire                                spec_insn_srliw_trap;
  wire [                       4 : 0] spec_insn_srliw_rs1_addr;
  wire [                       4 : 0] spec_insn_srliw_rs2_addr;
  wire [                       4 : 0] spec_insn_srliw_rd_addr;
  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_srliw_rd_wdata;
  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_srliw_pc_wdata;
  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_srliw_mem_addr;
  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_srliw_mem_rmask;
  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_srliw_mem_wmask;
  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_srliw_mem_wdata;
`ifdef RISCV_FORMAL_CSR_MISA
  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_srliw_csr_misa_rmask;
`endif

  rvfi_insn_srliw insn_srliw (
    .rvfi_valid(rvfi_valid),
    .rvfi_insn(rvfi_insn),
    .rvfi_pc_rdata(rvfi_pc_rdata),
    .rvfi_rs1_rdata(rvfi_rs1_rdata),
    .rvfi_rs2_rdata(rvfi_rs2_rdata),
    .rvfi_mem_rdata(rvfi_mem_rdata),
`ifdef RISCV_FORMAL_CSR_MISA
    .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata),
    .spec_csr_misa_rmask(spec_insn_srliw_csr_misa_rmask),
`endif
    .spec_valid(spec_insn_srliw_valid),
    .spec_trap(spec_insn_srliw_trap),
    .spec_rs1_addr(spec_insn_srliw_rs1_addr),
    .spec_rs2_addr(spec_insn_srliw_rs2_addr),
    .spec_rd_addr(spec_insn_srliw_rd_addr),
    .spec_rd_wdata(spec_insn_srliw_rd_wdata),
    .spec_pc_wdata(spec_insn_srliw_pc_wdata),
    .spec_mem_addr(spec_insn_srliw_mem_addr),
    .spec_mem_rmask(spec_insn_srliw_mem_rmask),
    .spec_mem_wmask(spec_insn_srliw_mem_wmask),
    .spec_mem_wdata(spec_insn_srliw_mem_wdata)
  );

  wire                                spec_insn_srlw_valid;
  wire                                spec_insn_srlw_trap;
  wire [                       4 : 0] spec_insn_srlw_rs1_addr;
  wire [                       4 : 0] spec_insn_srlw_rs2_addr;
  wire [                       4 : 0] spec_insn_srlw_rd_addr;
  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_srlw_rd_wdata;
  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_srlw_pc_wdata;
  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_srlw_mem_addr;
  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_srlw_mem_rmask;
  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_srlw_mem_wmask;
  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_srlw_mem_wdata;
`ifdef RISCV_FORMAL_CSR_MISA
  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_srlw_csr_misa_rmask;
`endif

  rvfi_insn_srlw insn_srlw (
    .rvfi_valid(rvfi_valid),
    .rvfi_insn(rvfi_insn),
    .rvfi_pc_rdata(rvfi_pc_rdata),
    .rvfi_rs1_rdata(rvfi_rs1_rdata),
    .rvfi_rs2_rdata(rvfi_rs2_rdata),
    .rvfi_mem_rdata(rvfi_mem_rdata),
`ifdef RISCV_FORMAL_CSR_MISA
    .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata),
    .spec_csr_misa_rmask(spec_insn_srlw_csr_misa_rmask),
`endif
    .spec_valid(spec_insn_srlw_valid),
    .spec_trap(spec_insn_srlw_trap),
    .spec_rs1_addr(spec_insn_srlw_rs1_addr),
    .spec_rs2_addr(spec_insn_srlw_rs2_addr),
    .spec_rd_addr(spec_insn_srlw_rd_addr),
    .spec_rd_wdata(spec_insn_srlw_rd_wdata),
    .spec_pc_wdata(spec_insn_srlw_pc_wdata),
    .spec_mem_addr(spec_insn_srlw_mem_addr),
    .spec_mem_rmask(spec_insn_srlw_mem_rmask),
    .spec_mem_wmask(spec_insn_srlw_mem_wmask),
    .spec_mem_wdata(spec_insn_srlw_mem_wdata)
  );

  wire                                spec_insn_sub_valid;
  wire                                spec_insn_sub_trap;
  wire [                       4 : 0] spec_insn_sub_rs1_addr;
  wire [                       4 : 0] spec_insn_sub_rs2_addr;
  wire [                       4 : 0] spec_insn_sub_rd_addr;
  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_sub_rd_wdata;
  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_sub_pc_wdata;
  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_sub_mem_addr;
  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_sub_mem_rmask;
  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_sub_mem_wmask;
  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_sub_mem_wdata;
`ifdef RISCV_FORMAL_CSR_MISA
  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_sub_csr_misa_rmask;
`endif

  rvfi_insn_sub insn_sub (
    .rvfi_valid(rvfi_valid),
    .rvfi_insn(rvfi_insn),
    .rvfi_pc_rdata(rvfi_pc_rdata),
    .rvfi_rs1_rdata(rvfi_rs1_rdata),
    .rvfi_rs2_rdata(rvfi_rs2_rdata),
    .rvfi_mem_rdata(rvfi_mem_rdata),
`ifdef RISCV_FORMAL_CSR_MISA
    .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata),
    .spec_csr_misa_rmask(spec_insn_sub_csr_misa_rmask),
`endif
    .spec_valid(spec_insn_sub_valid),
    .spec_trap(spec_insn_sub_trap),
    .spec_rs1_addr(spec_insn_sub_rs1_addr),
    .spec_rs2_addr(spec_insn_sub_rs2_addr),
    .spec_rd_addr(spec_insn_sub_rd_addr),
    .spec_rd_wdata(spec_insn_sub_rd_wdata),
    .spec_pc_wdata(spec_insn_sub_pc_wdata),
    .spec_mem_addr(spec_insn_sub_mem_addr),
    .spec_mem_rmask(spec_insn_sub_mem_rmask),
    .spec_mem_wmask(spec_insn_sub_mem_wmask),
    .spec_mem_wdata(spec_insn_sub_mem_wdata)
  );

  wire                                spec_insn_subw_valid;
  wire                                spec_insn_subw_trap;
  wire [                       4 : 0] spec_insn_subw_rs1_addr;
  wire [                       4 : 0] spec_insn_subw_rs2_addr;
  wire [                       4 : 0] spec_insn_subw_rd_addr;
  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_subw_rd_wdata;
  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_subw_pc_wdata;
  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_subw_mem_addr;
  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_subw_mem_rmask;
  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_subw_mem_wmask;
  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_subw_mem_wdata;
`ifdef RISCV_FORMAL_CSR_MISA
  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_subw_csr_misa_rmask;
`endif

  rvfi_insn_subw insn_subw (
    .rvfi_valid(rvfi_valid),
    .rvfi_insn(rvfi_insn),
    .rvfi_pc_rdata(rvfi_pc_rdata),
    .rvfi_rs1_rdata(rvfi_rs1_rdata),
    .rvfi_rs2_rdata(rvfi_rs2_rdata),
    .rvfi_mem_rdata(rvfi_mem_rdata),
`ifdef RISCV_FORMAL_CSR_MISA
    .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata),
    .spec_csr_misa_rmask(spec_insn_subw_csr_misa_rmask),
`endif
    .spec_valid(spec_insn_subw_valid),
    .spec_trap(spec_insn_subw_trap),
    .spec_rs1_addr(spec_insn_subw_rs1_addr),
    .spec_rs2_addr(spec_insn_subw_rs2_addr),
    .spec_rd_addr(spec_insn_subw_rd_addr),
    .spec_rd_wdata(spec_insn_subw_rd_wdata),
    .spec_pc_wdata(spec_insn_subw_pc_wdata),
    .spec_mem_addr(spec_insn_subw_mem_addr),
    .spec_mem_rmask(spec_insn_subw_mem_rmask),
    .spec_mem_wmask(spec_insn_subw_mem_wmask),
    .spec_mem_wdata(spec_insn_subw_mem_wdata)
  );

  wire                                spec_insn_sw_valid;
  wire                                spec_insn_sw_trap;
  wire [                       4 : 0] spec_insn_sw_rs1_addr;
  wire [                       4 : 0] spec_insn_sw_rs2_addr;
  wire [                       4 : 0] spec_insn_sw_rd_addr;
  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_sw_rd_wdata;
  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_sw_pc_wdata;
  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_sw_mem_addr;
  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_sw_mem_rmask;
  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_sw_mem_wmask;
  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_sw_mem_wdata;
`ifdef RISCV_FORMAL_CSR_MISA
  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_sw_csr_misa_rmask;
`endif

  rvfi_insn_sw insn_sw (
    .rvfi_valid(rvfi_valid),
    .rvfi_insn(rvfi_insn),
    .rvfi_pc_rdata(rvfi_pc_rdata),
    .rvfi_rs1_rdata(rvfi_rs1_rdata),
    .rvfi_rs2_rdata(rvfi_rs2_rdata),
    .rvfi_mem_rdata(rvfi_mem_rdata),
`ifdef RISCV_FORMAL_CSR_MISA
    .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata),
    .spec_csr_misa_rmask(spec_insn_sw_csr_misa_rmask),
`endif
    .spec_valid(spec_insn_sw_valid),
    .spec_trap(spec_insn_sw_trap),
    .spec_rs1_addr(spec_insn_sw_rs1_addr),
    .spec_rs2_addr(spec_insn_sw_rs2_addr),
    .spec_rd_addr(spec_insn_sw_rd_addr),
    .spec_rd_wdata(spec_insn_sw_rd_wdata),
    .spec_pc_wdata(spec_insn_sw_pc_wdata),
    .spec_mem_addr(spec_insn_sw_mem_addr),
    .spec_mem_rmask(spec_insn_sw_mem_rmask),
    .spec_mem_wmask(spec_insn_sw_mem_wmask),
    .spec_mem_wdata(spec_insn_sw_mem_wdata)
  );

  wire                                spec_insn_xnor_valid;
  wire                                spec_insn_xnor_trap;
  wire [                       4 : 0] spec_insn_xnor_rs1_addr;
  wire [                       4 : 0] spec_insn_xnor_rs2_addr;
  wire [                       4 : 0] spec_insn_xnor_rd_addr;
  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_xnor_rd_wdata;
  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_xnor_pc_wdata;
  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_xnor_mem_addr;
  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_xnor_mem_rmask;
  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_xnor_mem_wmask;
  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_xnor_mem_wdata;
`ifdef RISCV_FORMAL_CSR_MISA
  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_xnor_csr_misa_rmask;
`endif

  rvfi_insn_xnor insn_xnor (
    .rvfi_valid(rvfi_valid),
    .rvfi_insn(rvfi_insn),
    .rvfi_pc_rdata(rvfi_pc_rdata),
    .rvfi_rs1_rdata(rvfi_rs1_rdata),
    .rvfi_rs2_rdata(rvfi_rs2_rdata),
    .rvfi_mem_rdata(rvfi_mem_rdata),
`ifdef RISCV_FORMAL_CSR_MISA
    .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata),
    .spec_csr_misa_rmask(spec_insn_xnor_csr_misa_rmask),
`endif
    .spec_valid(spec_insn_xnor_valid),
    .spec_trap(spec_insn_xnor_trap),
    .spec_rs1_addr(spec_insn_xnor_rs1_addr),
    .spec_rs2_addr(spec_insn_xnor_rs2_addr),
    .spec_rd_addr(spec_insn_xnor_rd_addr),
    .spec_rd_wdata(spec_insn_xnor_rd_wdata),
    .spec_pc_wdata(spec_insn_xnor_pc_wdata),
    .spec_mem_addr(spec_insn_xnor_mem_addr),
    .spec_mem_rmask(spec_insn_xnor_mem_rmask),
    .spec_mem_wmask(spec_insn_xnor_mem_wmask),
    .spec_mem_wdata(spec_insn_xnor_mem_wdata)
  );

  wire                                spec_insn_xor_valid;
  wire                                spec_insn_xor_trap;
  wire [                       4 : 0] spec_insn_xor_rs1_addr;
  wire [                       4 : 0] spec_insn_xor_rs2_addr;
  wire [                       4 : 0] spec_insn_xor_rd_addr;
  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_xor_rd_wdata;
  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_xor_pc_wdata;
  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_xor_mem_addr;
  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_xor_mem_rmask;
  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_xor_mem_wmask;
  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_xor_mem_wdata;
`ifdef RISCV_FORMAL_CSR_MISA
  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_xor_csr_misa_rmask;
`endif

  rvfi_insn_xor insn_xor (
    .rvfi_valid(rvfi_valid),
    .rvfi_insn(rvfi_insn),
    .rvfi_pc_rdata(rvfi_pc_rdata),
    .rvfi_rs1_rdata(rvfi_rs1_rdata),
    .rvfi_rs2_rdata(rvfi_rs2_rdata),
    .rvfi_mem_rdata(rvfi_mem_rdata),
`ifdef RISCV_FORMAL_CSR_MISA
    .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata),
    .spec_csr_misa_rmask(spec_insn_xor_csr_misa_rmask),
`endif
    .spec_valid(spec_insn_xor_valid),
    .spec_trap(spec_insn_xor_trap),
    .spec_rs1_addr(spec_insn_xor_rs1_addr),
    .spec_rs2_addr(spec_insn_xor_rs2_addr),
    .spec_rd_addr(spec_insn_xor_rd_addr),
    .spec_rd_wdata(spec_insn_xor_rd_wdata),
    .spec_pc_wdata(spec_insn_xor_pc_wdata),
    .spec_mem_addr(spec_insn_xor_mem_addr),
    .spec_mem_rmask(spec_insn_xor_mem_rmask),
    .spec_mem_wmask(spec_insn_xor_mem_wmask),
    .spec_mem_wdata(spec_insn_xor_mem_wdata)
  );

  wire                                spec_insn_xori_valid;
  wire                                spec_insn_xori_trap;
  wire [                       4 : 0] spec_insn_xori_rs1_addr;
  wire [                       4 : 0] spec_insn_xori_rs2_addr;
  wire [                       4 : 0] spec_insn_xori_rd_addr;
  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_xori_rd_wdata;
  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_xori_pc_wdata;
  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_xori_mem_addr;
  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_xori_mem_rmask;
  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_xori_mem_wmask;
  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_xori_mem_wdata;
`ifdef RISCV_FORMAL_CSR_MISA
  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_xori_csr_misa_rmask;
`endif

  rvfi_insn_xori insn_xori (
    .rvfi_valid(rvfi_valid),
    .rvfi_insn(rvfi_insn),
    .rvfi_pc_rdata(rvfi_pc_rdata),
    .rvfi_rs1_rdata(rvfi_rs1_rdata),
    .rvfi_rs2_rdata(rvfi_rs2_rdata),
    .rvfi_mem_rdata(rvfi_mem_rdata),
`ifdef RISCV_FORMAL_CSR_MISA
    .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata),
    .spec_csr_misa_rmask(spec_insn_xori_csr_misa_rmask),
`endif
    .spec_valid(spec_insn_xori_valid),
    .spec_trap(spec_insn_xori_trap),
    .spec_rs1_addr(spec_insn_xori_rs1_addr),
    .spec_rs2_addr(spec_insn_xori_rs2_addr),
    .spec_rd_addr(spec_insn_xori_rd_addr),
    .spec_rd_wdata(spec_insn_xori_rd_wdata),
    .spec_pc_wdata(spec_insn_xori_pc_wdata),
    .spec_mem_addr(spec_insn_xori_mem_addr),
    .spec_mem_rmask(spec_insn_xori_mem_rmask),
    .spec_mem_wmask(spec_insn_xori_mem_wmask),
    .spec_mem_wdata(spec_insn_xori_mem_wdata)
  );

  wire                                spec_insn_zext_h_valid;
  wire                                spec_insn_zext_h_trap;
  wire [                       4 : 0] spec_insn_zext_h_rs1_addr;
  wire [                       4 : 0] spec_insn_zext_h_rs2_addr;
  wire [                       4 : 0] spec_insn_zext_h_rd_addr;
  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_zext_h_rd_wdata;
  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_zext_h_pc_wdata;
  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_zext_h_mem_addr;
  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_zext_h_mem_rmask;
  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_zext_h_mem_wmask;
  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_zext_h_mem_wdata;
`ifdef RISCV_FORMAL_CSR_MISA
  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_zext_h_csr_misa_rmask;
`endif

  rvfi_insn_zext_h insn_zext_h (
    .rvfi_valid(rvfi_valid),
    .rvfi_insn(rvfi_insn),
    .rvfi_pc_rdata(rvfi_pc_rdata),
    .rvfi_rs1_rdata(rvfi_rs1_rdata),
    .rvfi_rs2_rdata(rvfi_rs2_rdata),
    .rvfi_mem_rdata(rvfi_mem_rdata),
`ifdef RISCV_FORMAL_CSR_MISA
    .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata),
    .spec_csr_misa_rmask(spec_insn_zext_h_csr_misa_rmask),
`endif
    .spec_valid(spec_insn_zext_h_valid),
    .spec_trap(spec_insn_zext_h_trap),
    .spec_rs1_addr(spec_insn_zext_h_rs1_addr),
    .spec_rs2_addr(spec_insn_zext_h_rs2_addr),
    .spec_rd_addr(spec_insn_zext_h_rd_addr),
    .spec_rd_wdata(spec_insn_zext_h_rd_wdata),
    .spec_pc_wdata(spec_insn_zext_h_pc_wdata),
    .spec_mem_addr(spec_insn_zext_h_mem_addr),
    .spec_mem_rmask(spec_insn_zext_h_mem_rmask),
    .spec_mem_wmask(spec_insn_zext_h_mem_wmask),
    .spec_mem_wdata(spec_insn_zext_h_mem_wdata)
  );

  assign spec_valid =
		spec_insn_add_valid ? spec_insn_add_valid :
		spec_insn_add_uw_valid ? spec_insn_add_uw_valid :
		spec_insn_addi_valid ? spec_insn_addi_valid :
		spec_insn_addiw_valid ? spec_insn_addiw_valid :
		spec_insn_addw_valid ? spec_insn_addw_valid :
		spec_insn_and_valid ? spec_insn_and_valid :
		spec_insn_andi_valid ? spec_insn_andi_valid :
		spec_insn_andn_valid ? spec_insn_andn_valid :
		spec_insn_auipc_valid ? spec_insn_auipc_valid :
		spec_insn_bclr_valid ? spec_insn_bclr_valid :
		spec_insn_bclri_valid ? spec_insn_bclri_valid :
		spec_insn_beq_valid ? spec_insn_beq_valid :
		spec_insn_bext_valid ? spec_insn_bext_valid :
		spec_insn_bexti_valid ? spec_insn_bexti_valid :
		spec_insn_bge_valid ? spec_insn_bge_valid :
		spec_insn_bgeu_valid ? spec_insn_bgeu_valid :
		spec_insn_binv_valid ? spec_insn_binv_valid :
		spec_insn_binvi_valid ? spec_insn_binvi_valid :
		spec_insn_blt_valid ? spec_insn_blt_valid :
		spec_insn_bltu_valid ? spec_insn_bltu_valid :
		spec_insn_bne_valid ? spec_insn_bne_valid :
		spec_insn_bset_valid ? spec_insn_bset_valid :
		spec_insn_bseti_valid ? spec_insn_bseti_valid :
		spec_insn_clz_valid ? spec_insn_clz_valid :
		spec_insn_clzw_valid ? spec_insn_clzw_valid :
		spec_insn_cpop_valid ? spec_insn_cpop_valid :
		spec_insn_cpopw_valid ? spec_insn_cpopw_valid :
		spec_insn_ctz_valid ? spec_insn_ctz_valid :
		spec_insn_ctzw_valid ? spec_insn_ctzw_valid :
		spec_insn_jal_valid ? spec_insn_jal_valid :
		spec_insn_jalr_valid ? spec_insn_jalr_valid :
		spec_insn_lb_valid ? spec_insn_lb_valid :
		spec_insn_lbu_valid ? spec_insn_lbu_valid :
		spec_insn_ld_valid ? spec_insn_ld_valid :
		spec_insn_lh_valid ? spec_insn_lh_valid :
		spec_insn_lhu_valid ? spec_insn_lhu_valid :
		spec_insn_lui_valid ? spec_insn_lui_valid :
		spec_insn_lw_valid ? spec_insn_lw_valid :
		spec_insn_lwu_valid ? spec_insn_lwu_valid :
		spec_insn_max_valid ? spec_insn_max_valid :
		spec_insn_maxu_valid ? spec_insn_maxu_valid :
		spec_insn_min_valid ? spec_insn_min_valid :
		spec_insn_minu_valid ? spec_insn_minu_valid :
		spec_insn_or_valid ? spec_insn_or_valid :
		spec_insn_orc_b_valid ? spec_insn_orc_b_valid :
		spec_insn_ori_valid ? spec_insn_ori_valid :
		spec_insn_orn_valid ? spec_insn_orn_valid :
		spec_insn_rev8_valid ? spec_insn_rev8_valid :
		spec_insn_rol_valid ? spec_insn_rol_valid :
		spec_insn_rolw_valid ? spec_insn_rolw_valid :
		spec_insn_ror_valid ? spec_insn_ror_valid :
		spec_insn_rori_valid ? spec_insn_rori_valid :
		spec_insn_roriw_valid ? spec_insn_roriw_valid :
		spec_insn_rorw_valid ? spec_insn_rorw_valid :
		spec_insn_sb_valid ? spec_insn_sb_valid :
		spec_insn_sd_valid ? spec_insn_sd_valid :
		spec_insn_sext_b_valid ? spec_insn_sext_b_valid :
		spec_insn_sext_h_valid ? spec_insn_sext_h_valid :
		spec_insn_sh_valid ? spec_insn_sh_valid :
		spec_insn_sh1add_valid ? spec_insn_sh1add_valid :
		spec_insn_sh1add_uw_valid ? spec_insn_sh1add_uw_valid :
		spec_insn_sh2add_valid ? spec_insn_sh2add_valid :
		spec_insn_sh2add_uw_valid ? spec_insn_sh2add_uw_valid :
		spec_insn_sh3add_valid ? spec_insn_sh3add_valid :
		spec_insn_sh3add_uw_valid ? spec_insn_sh3add_uw_valid :
		spec_insn_sll_valid ? spec_insn_sll_valid :
		spec_insn_slli_valid ? spec_insn_slli_valid :
		spec_insn_slli_uw_valid ? spec_insn_slli_uw_valid :
		spec_insn_slliw_valid ? spec_insn_slliw_valid :
		spec_insn_sllw_valid ? spec_insn_sllw_valid :
		spec_insn_slt_valid ? spec_insn_slt_valid :
		spec_insn_slti_valid ? spec_insn_slti_valid :
		spec_insn_sltiu_valid ? spec_insn_sltiu_valid :
		spec_insn_sltu_valid ? spec_insn_sltu_valid :
		spec_insn_sra_valid ? spec_insn_sra_valid :
		spec_insn_srai_valid ? spec_insn_srai_valid :
		spec_insn_sraiw_valid ? spec_insn_sraiw_valid :
		spec_insn_sraw_valid ? spec_insn_sraw_valid :
		spec_insn_srl_valid ? spec_insn_srl_valid :
		spec_insn_srli_valid ? spec_insn_srli_valid :
		spec_insn_srliw_valid ? spec_insn_srliw_valid :
		spec_insn_srlw_valid ? spec_insn_srlw_valid :
		spec_insn_sub_valid ? spec_insn_sub_valid :
		spec_insn_subw_valid ? spec_insn_subw_valid :
		spec_insn_sw_valid ? spec_insn_sw_valid :
		spec_insn_xnor_valid ? spec_insn_xnor_valid :
		spec_insn_xor_valid ? spec_insn_xor_valid :
		spec_insn_xori_valid ? spec_insn_xori_valid :
		spec_insn_zext_h_valid ? spec_insn_zext_h_valid : 0;
  assign spec_trap =
		spec_insn_add_valid ? spec_insn_add_trap :
		spec_insn_add_uw_valid ? spec_insn_add_uw_trap :
		spec_insn_addi_valid ? spec_insn_addi_trap :
		spec_insn_addiw_valid ? spec_insn_addiw_trap :
		spec_insn_addw_valid ? spec_insn_addw_trap :
		spec_insn_and_valid ? spec_insn_and_trap :
		spec_insn_andi_valid ? spec_insn_andi_trap :
		spec_insn_andn_valid ? spec_insn_andn_trap :
		spec_insn_auipc_valid ? spec_insn_auipc_trap :
		spec_insn_bclr_valid ? spec_insn_bclr_trap :
		spec_insn_bclri_valid ? spec_insn_bclri_trap :
		spec_insn_beq_valid ? spec_insn_beq_trap :
		spec_insn_bext_valid ? spec_insn_bext_trap :
		spec_insn_bexti_valid ? spec_insn_bexti_trap :
		spec_insn_bge_valid ? spec_insn_bge_trap :
		spec_insn_bgeu_valid ? spec_insn_bgeu_trap :
		spec_insn_binv_valid ? spec_insn_binv_trap :
		spec_insn_binvi_valid ? spec_insn_binvi_trap :
		spec_insn_blt_valid ? spec_insn_blt_trap :
		spec_insn_bltu_valid ? spec_insn_bltu_trap :
		spec_insn_bne_valid ? spec_insn_bne_trap :
		spec_insn_bset_valid ? spec_insn_bset_trap :
		spec_insn_bseti_valid ? spec_insn_bseti_trap :
		spec_insn_clz_valid ? spec_insn_clz_trap :
		spec_insn_clzw_valid ? spec_insn_clzw_trap :
		spec_insn_cpop_valid ? spec_insn_cpop_trap :
		spec_insn_cpopw_valid ? spec_insn_cpopw_trap :
		spec_insn_ctz_valid ? spec_insn_ctz_trap :
		spec_insn_ctzw_valid ? spec_insn_ctzw_trap :
		spec_insn_jal_valid ? spec_insn_jal_trap :
		spec_insn_jalr_valid ? spec_insn_jalr_trap :
		spec_insn_lb_valid ? spec_insn_lb_trap :
		spec_insn_lbu_valid ? spec_insn_lbu_trap :
		spec_insn_ld_valid ? spec_insn_ld_trap :
		spec_insn_lh_valid ? spec_insn_lh_trap :
		spec_insn_lhu_valid ? spec_insn_lhu_trap :
		spec_insn_lui_valid ? spec_insn_lui_trap :
		spec_insn_lw_valid ? spec_insn_lw_trap :
		spec_insn_lwu_valid ? spec_insn_lwu_trap :
		spec_insn_max_valid ? spec_insn_max_trap :
		spec_insn_maxu_valid ? spec_insn_maxu_trap :
		spec_insn_min_valid ? spec_insn_min_trap :
		spec_insn_minu_valid ? spec_insn_minu_trap :
		spec_insn_or_valid ? spec_insn_or_trap :
		spec_insn_orc_b_valid ? spec_insn_orc_b_trap :
		spec_insn_ori_valid ? spec_insn_ori_trap :
		spec_insn_orn_valid ? spec_insn_orn_trap :
		spec_insn_rev8_valid ? spec_insn_rev8_trap :
		spec_insn_rol_valid ? spec_insn_rol_trap :
		spec_insn_rolw_valid ? spec_insn_rolw_trap :
		spec_insn_ror_valid ? spec_insn_ror_trap :
		spec_insn_rori_valid ? spec_insn_rori_trap :
		spec_insn_roriw_valid ? spec_insn_roriw_trap :
		spec_insn_rorw_valid ? spec_insn_rorw_trap :
		spec_insn_sb_valid ? spec_insn_sb_trap :
		spec_insn_sd_valid ? spec_insn_sd_trap :
		spec_insn_sext_b_valid ? spec_insn_sext_b_trap :
		spec_insn_sext_h_valid ? spec_insn_sext_h_trap :
		spec_insn_sh_valid ? spec_insn_sh_trap :
		spec_insn_sh1add_valid ? spec_insn_sh1add_trap :
		spec_insn_sh1add_uw_valid ? spec_insn_sh1add_uw_trap :
		spec_insn_sh2add_valid ? spec_insn_sh2add_trap :
		spec_insn_sh2add_uw_valid ? spec_insn_sh2add_uw_trap :
		spec_insn_sh3add_valid ? spec_insn_sh3add_trap :
		spec_insn_sh3add_uw_valid ? spec_insn_sh3add_uw_trap :
		spec_insn_sll_valid ? spec_insn_sll_trap :
		spec_insn_slli_valid ? spec_insn_slli_trap :
		spec_insn_slli_uw_valid ? spec_insn_slli_uw_trap :
		spec_insn_slliw_valid ? spec_insn_slliw_trap :
		spec_insn_sllw_valid ? spec_insn_sllw_trap :
		spec_insn_slt_valid ? spec_insn_slt_trap :
		spec_insn_slti_valid ? spec_insn_slti_trap :
		spec_insn_sltiu_valid ? spec_insn_sltiu_trap :
		spec_insn_sltu_valid ? spec_insn_sltu_trap :
		spec_insn_sra_valid ? spec_insn_sra_trap :
		spec_insn_srai_valid ? spec_insn_srai_trap :
		spec_insn_sraiw_valid ? spec_insn_sraiw_trap :
		spec_insn_sraw_valid ? spec_insn_sraw_trap :
		spec_insn_srl_valid ? spec_insn_srl_trap :
		spec_insn_srli_valid ? spec_insn_srli_trap :
		spec_insn_srliw_valid ? spec_insn_srliw_trap :
		spec_insn_srlw_valid ? spec_insn_srlw_trap :
		spec_insn_sub_valid ? spec_insn_sub_trap :
		spec_insn_subw_valid ? spec_insn_subw_trap :
		spec_insn_sw_valid ? spec_insn_sw_trap :
		spec_insn_xnor_valid ? spec_insn_xnor_trap :
		spec_insn_xor_valid ? spec_insn_xor_trap :
		spec_insn_xori_valid ? spec_insn_xori_trap :
		spec_insn_zext_h_valid ? spec_insn_zext_h_trap : 0;
  assign spec_rs1_addr =
		spec_insn_add_valid ? spec_insn_add_rs1_addr :
		spec_insn_add_uw_valid ? spec_insn_add_uw_rs1_addr :
		spec_insn_addi_valid ? spec_insn_addi_rs1_addr :
		spec_insn_addiw_valid ? spec_insn_addiw_rs1_addr :
		spec_insn_addw_valid ? spec_insn_addw_rs1_addr :
		spec_insn_and_valid ? spec_insn_and_rs1_addr :
		spec_insn_andi_valid ? spec_insn_andi_rs1_addr :
		spec_insn_andn_valid ? spec_insn_andn_rs1_addr :
		spec_insn_auipc_valid ? spec_insn_auipc_rs1_addr :
		spec_insn_bclr_valid ? spec_insn_bclr_rs1_addr :
		spec_insn_bclri_valid ? spec_insn_bclri_rs1_addr :
		spec_insn_beq_valid ? spec_insn_beq_rs1_addr :
		spec_insn_bext_valid ? spec_insn_bext_rs1_addr :
		spec_insn_bexti_valid ? spec_insn_bexti_rs1_addr :
		spec_insn_bge_valid ? spec_insn_bge_rs1_addr :
		spec_insn_bgeu_valid ? spec_insn_bgeu_rs1_addr :
		spec_insn_binv_valid ? spec_insn_binv_rs1_addr :
		spec_insn_binvi_valid ? spec_insn_binvi_rs1_addr :
		spec_insn_blt_valid ? spec_insn_blt_rs1_addr :
		spec_insn_bltu_valid ? spec_insn_bltu_rs1_addr :
		spec_insn_bne_valid ? spec_insn_bne_rs1_addr :
		spec_insn_bset_valid ? spec_insn_bset_rs1_addr :
		spec_insn_bseti_valid ? spec_insn_bseti_rs1_addr :
		spec_insn_clz_valid ? spec_insn_clz_rs1_addr :
		spec_insn_clzw_valid ? spec_insn_clzw_rs1_addr :
		spec_insn_cpop_valid ? spec_insn_cpop_rs1_addr :
		spec_insn_cpopw_valid ? spec_insn_cpopw_rs1_addr :
		spec_insn_ctz_valid ? spec_insn_ctz_rs1_addr :
		spec_insn_ctzw_valid ? spec_insn_ctzw_rs1_addr :
		spec_insn_jal_valid ? spec_insn_jal_rs1_addr :
		spec_insn_jalr_valid ? spec_insn_jalr_rs1_addr :
		spec_insn_lb_valid ? spec_insn_lb_rs1_addr :
		spec_insn_lbu_valid ? spec_insn_lbu_rs1_addr :
		spec_insn_ld_valid ? spec_insn_ld_rs1_addr :
		spec_insn_lh_valid ? spec_insn_lh_rs1_addr :
		spec_insn_lhu_valid ? spec_insn_lhu_rs1_addr :
		spec_insn_lui_valid ? spec_insn_lui_rs1_addr :
		spec_insn_lw_valid ? spec_insn_lw_rs1_addr :
		spec_insn_lwu_valid ? spec_insn_lwu_rs1_addr :
		spec_insn_max_valid ? spec_insn_max_rs1_addr :
		spec_insn_maxu_valid ? spec_insn_maxu_rs1_addr :
		spec_insn_min_valid ? spec_insn_min_rs1_addr :
		spec_insn_minu_valid ? spec_insn_minu_rs1_addr :
		spec_insn_or_valid ? spec_insn_or_rs1_addr :
		spec_insn_orc_b_valid ? spec_insn_orc_b_rs1_addr :
		spec_insn_ori_valid ? spec_insn_ori_rs1_addr :
		spec_insn_orn_valid ? spec_insn_orn_rs1_addr :
		spec_insn_rev8_valid ? spec_insn_rev8_rs1_addr :
		spec_insn_rol_valid ? spec_insn_rol_rs1_addr :
		spec_insn_rolw_valid ? spec_insn_rolw_rs1_addr :
		spec_insn_ror_valid ? spec_insn_ror_rs1_addr :
		spec_insn_rori_valid ? spec_insn_rori_rs1_addr :
		spec_insn_roriw_valid ? spec_insn_roriw_rs1_addr :
		spec_insn_rorw_valid ? spec_insn_rorw_rs1_addr :
		spec_insn_sb_valid ? spec_insn_sb_rs1_addr :
		spec_insn_sd_valid ? spec_insn_sd_rs1_addr :
		spec_insn_sext_b_valid ? spec_insn_sext_b_rs1_addr :
		spec_insn_sext_h_valid ? spec_insn_sext_h_rs1_addr :
		spec_insn_sh_valid ? spec_insn_sh_rs1_addr :
		spec_insn_sh1add_valid ? spec_insn_sh1add_rs1_addr :
		spec_insn_sh1add_uw_valid ? spec_insn_sh1add_uw_rs1_addr :
		spec_insn_sh2add_valid ? spec_insn_sh2add_rs1_addr :
		spec_insn_sh2add_uw_valid ? spec_insn_sh2add_uw_rs1_addr :
		spec_insn_sh3add_valid ? spec_insn_sh3add_rs1_addr :
		spec_insn_sh3add_uw_valid ? spec_insn_sh3add_uw_rs1_addr :
		spec_insn_sll_valid ? spec_insn_sll_rs1_addr :
		spec_insn_slli_valid ? spec_insn_slli_rs1_addr :
		spec_insn_slli_uw_valid ? spec_insn_slli_uw_rs1_addr :
		spec_insn_slliw_valid ? spec_insn_slliw_rs1_addr :
		spec_insn_sllw_valid ? spec_insn_sllw_rs1_addr :
		spec_insn_slt_valid ? spec_insn_slt_rs1_addr :
		spec_insn_slti_valid ? spec_insn_slti_rs1_addr :
		spec_insn_sltiu_valid ? spec_insn_sltiu_rs1_addr :
		spec_insn_sltu_valid ? spec_insn_sltu_rs1_addr :
		spec_insn_sra_valid ? spec_insn_sra_rs1_addr :
		spec_insn_srai_valid ? spec_insn_srai_rs1_addr :
		spec_insn_sraiw_valid ? spec_insn_sraiw_rs1_addr :
		spec_insn_sraw_valid ? spec_insn_sraw_rs1_addr :
		spec_insn_srl_valid ? spec_insn_srl_rs1_addr :
		spec_insn_srli_valid ? spec_insn_srli_rs1_addr :
		spec_insn_srliw_valid ? spec_insn_srliw_rs1_addr :
		spec_insn_srlw_valid ? spec_insn_srlw_rs1_addr :
		spec_insn_sub_valid ? spec_insn_sub_rs1_addr :
		spec_insn_subw_valid ? spec_insn_subw_rs1_addr :
		spec_insn_sw_valid ? spec_insn_sw_rs1_addr :
		spec_insn_xnor_valid ? spec_insn_xnor_rs1_addr :
		spec_insn_xor_valid ? spec_insn_xor_rs1_addr :
		spec_insn_xori_valid ? spec_insn_xori_rs1_addr :
		spec_insn_zext_h_valid ? spec_insn_zext_h_rs1_addr : 0;
  assign spec_rs2_addr =
		spec_insn_add_valid ? spec_insn_add_rs2_addr :
		spec_insn_add_uw_valid ? spec_insn_add_uw_rs2_addr :
		spec_insn_addi_valid ? spec_insn_addi_rs2_addr :
		spec_insn_addiw_valid ? spec_insn_addiw_rs2_addr :
		spec_insn_addw_valid ? spec_insn_addw_rs2_addr :
		spec_insn_and_valid ? spec_insn_and_rs2_addr :
		spec_insn_andi_valid ? spec_insn_andi_rs2_addr :
		spec_insn_andn_valid ? spec_insn_andn_rs2_addr :
		spec_insn_auipc_valid ? spec_insn_auipc_rs2_addr :
		spec_insn_bclr_valid ? spec_insn_bclr_rs2_addr :
		spec_insn_bclri_valid ? spec_insn_bclri_rs2_addr :
		spec_insn_beq_valid ? spec_insn_beq_rs2_addr :
		spec_insn_bext_valid ? spec_insn_bext_rs2_addr :
		spec_insn_bexti_valid ? spec_insn_bexti_rs2_addr :
		spec_insn_bge_valid ? spec_insn_bge_rs2_addr :
		spec_insn_bgeu_valid ? spec_insn_bgeu_rs2_addr :
		spec_insn_binv_valid ? spec_insn_binv_rs2_addr :
		spec_insn_binvi_valid ? spec_insn_binvi_rs2_addr :
		spec_insn_blt_valid ? spec_insn_blt_rs2_addr :
		spec_insn_bltu_valid ? spec_insn_bltu_rs2_addr :
		spec_insn_bne_valid ? spec_insn_bne_rs2_addr :
		spec_insn_bset_valid ? spec_insn_bset_rs2_addr :
		spec_insn_bseti_valid ? spec_insn_bseti_rs2_addr :
		spec_insn_clz_valid ? spec_insn_clz_rs2_addr :
		spec_insn_clzw_valid ? spec_insn_clzw_rs2_addr :
		spec_insn_cpop_valid ? spec_insn_cpop_rs2_addr :
		spec_insn_cpopw_valid ? spec_insn_cpopw_rs2_addr :
		spec_insn_ctz_valid ? spec_insn_ctz_rs2_addr :
		spec_insn_ctzw_valid ? spec_insn_ctzw_rs2_addr :
		spec_insn_jal_valid ? spec_insn_jal_rs2_addr :
		spec_insn_jalr_valid ? spec_insn_jalr_rs2_addr :
		spec_insn_lb_valid ? spec_insn_lb_rs2_addr :
		spec_insn_lbu_valid ? spec_insn_lbu_rs2_addr :
		spec_insn_ld_valid ? spec_insn_ld_rs2_addr :
		spec_insn_lh_valid ? spec_insn_lh_rs2_addr :
		spec_insn_lhu_valid ? spec_insn_lhu_rs2_addr :
		spec_insn_lui_valid ? spec_insn_lui_rs2_addr :
		spec_insn_lw_valid ? spec_insn_lw_rs2_addr :
		spec_insn_lwu_valid ? spec_insn_lwu_rs2_addr :
		spec_insn_max_valid ? spec_insn_max_rs2_addr :
		spec_insn_maxu_valid ? spec_insn_maxu_rs2_addr :
		spec_insn_min_valid ? spec_insn_min_rs2_addr :
		spec_insn_minu_valid ? spec_insn_minu_rs2_addr :
		spec_insn_or_valid ? spec_insn_or_rs2_addr :
		spec_insn_orc_b_valid ? spec_insn_orc_b_rs2_addr :
		spec_insn_ori_valid ? spec_insn_ori_rs2_addr :
		spec_insn_orn_valid ? spec_insn_orn_rs2_addr :
		spec_insn_rev8_valid ? spec_insn_rev8_rs2_addr :
		spec_insn_rol_valid ? spec_insn_rol_rs2_addr :
		spec_insn_rolw_valid ? spec_insn_rolw_rs2_addr :
		spec_insn_ror_valid ? spec_insn_ror_rs2_addr :
		spec_insn_rori_valid ? spec_insn_rori_rs2_addr :
		spec_insn_roriw_valid ? spec_insn_roriw_rs2_addr :
		spec_insn_rorw_valid ? spec_insn_rorw_rs2_addr :
		spec_insn_sb_valid ? spec_insn_sb_rs2_addr :
		spec_insn_sd_valid ? spec_insn_sd_rs2_addr :
		spec_insn_sext_b_valid ? spec_insn_sext_b_rs2_addr :
		spec_insn_sext_h_valid ? spec_insn_sext_h_rs2_addr :
		spec_insn_sh_valid ? spec_insn_sh_rs2_addr :
		spec_insn_sh1add_valid ? spec_insn_sh1add_rs2_addr :
		spec_insn_sh1add_uw_valid ? spec_insn_sh1add_uw_rs2_addr :
		spec_insn_sh2add_valid ? spec_insn_sh2add_rs2_addr :
		spec_insn_sh2add_uw_valid ? spec_insn_sh2add_uw_rs2_addr :
		spec_insn_sh3add_valid ? spec_insn_sh3add_rs2_addr :
		spec_insn_sh3add_uw_valid ? spec_insn_sh3add_uw_rs2_addr :
		spec_insn_sll_valid ? spec_insn_sll_rs2_addr :
		spec_insn_slli_valid ? spec_insn_slli_rs2_addr :
		spec_insn_slli_uw_valid ? spec_insn_slli_uw_rs2_addr :
		spec_insn_slliw_valid ? spec_insn_slliw_rs2_addr :
		spec_insn_sllw_valid ? spec_insn_sllw_rs2_addr :
		spec_insn_slt_valid ? spec_insn_slt_rs2_addr :
		spec_insn_slti_valid ? spec_insn_slti_rs2_addr :
		spec_insn_sltiu_valid ? spec_insn_sltiu_rs2_addr :
		spec_insn_sltu_valid ? spec_insn_sltu_rs2_addr :
		spec_insn_sra_valid ? spec_insn_sra_rs2_addr :
		spec_insn_srai_valid ? spec_insn_srai_rs2_addr :
		spec_insn_sraiw_valid ? spec_insn_sraiw_rs2_addr :
		spec_insn_sraw_valid ? spec_insn_sraw_rs2_addr :
		spec_insn_srl_valid ? spec_insn_srl_rs2_addr :
		spec_insn_srli_valid ? spec_insn_srli_rs2_addr :
		spec_insn_srliw_valid ? spec_insn_srliw_rs2_addr :
		spec_insn_srlw_valid ? spec_insn_srlw_rs2_addr :
		spec_insn_sub_valid ? spec_insn_sub_rs2_addr :
		spec_insn_subw_valid ? spec_insn_subw_rs2_addr :
		spec_insn_sw_valid ? spec_insn_sw_rs2_addr :
		spec_insn_xnor_valid ? spec_insn_xnor_rs2_addr :
		spec_insn_xor_valid ? spec_insn_xor_rs2_addr :
		spec_insn_xori_valid ? spec_insn_xori_rs2_addr :
		spec_insn_zext_h_valid ? spec_insn_zext_h_rs2_addr : 0;
  assign spec_rd_addr =
		spec_insn_add_valid ? spec_insn_add_rd_addr :
		spec_insn_add_uw_valid ? spec_insn_add_uw_rd_addr :
		spec_insn_addi_valid ? spec_insn_addi_rd_addr :
		spec_insn_addiw_valid ? spec_insn_addiw_rd_addr :
		spec_insn_addw_valid ? spec_insn_addw_rd_addr :
		spec_insn_and_valid ? spec_insn_and_rd_addr :
		spec_insn_andi_valid ? spec_insn_andi_rd_addr :
		spec_insn_andn_valid ? spec_insn_andn_rd_addr :
		spec_insn_auipc_valid ? spec_insn_auipc_rd_addr :
		spec_insn_bclr_valid ? spec_insn_bclr_rd_addr :
		spec_insn_bclri_valid ? spec_insn_bclri_rd_addr :
		spec_insn_beq_valid ? spec_insn_beq_rd_addr :
		spec_insn_bext_valid ? spec_insn_bext_rd_addr :
		spec_insn_bexti_valid ? spec_insn_bexti_rd_addr :
		spec_insn_bge_valid ? spec_insn_bge_rd_addr :
		spec_insn_bgeu_valid ? spec_insn_bgeu_rd_addr :
		spec_insn_binv_valid ? spec_insn_binv_rd_addr :
		spec_insn_binvi_valid ? spec_insn_binvi_rd_addr :
		spec_insn_blt_valid ? spec_insn_blt_rd_addr :
		spec_insn_bltu_valid ? spec_insn_bltu_rd_addr :
		spec_insn_bne_valid ? spec_insn_bne_rd_addr :
		spec_insn_bset_valid ? spec_insn_bset_rd_addr :
		spec_insn_bseti_valid ? spec_insn_bseti_rd_addr :
		spec_insn_clz_valid ? spec_insn_clz_rd_addr :
		spec_insn_clzw_valid ? spec_insn_clzw_rd_addr :
		spec_insn_cpop_valid ? spec_insn_cpop_rd_addr :
		spec_insn_cpopw_valid ? spec_insn_cpopw_rd_addr :
		spec_insn_ctz_valid ? spec_insn_ctz_rd_addr :
		spec_insn_ctzw_valid ? spec_insn_ctzw_rd_addr :
		spec_insn_jal_valid ? spec_insn_jal_rd_addr :
		spec_insn_jalr_valid ? spec_insn_jalr_rd_addr :
		spec_insn_lb_valid ? spec_insn_lb_rd_addr :
		spec_insn_lbu_valid ? spec_insn_lbu_rd_addr :
		spec_insn_ld_valid ? spec_insn_ld_rd_addr :
		spec_insn_lh_valid ? spec_insn_lh_rd_addr :
		spec_insn_lhu_valid ? spec_insn_lhu_rd_addr :
		spec_insn_lui_valid ? spec_insn_lui_rd_addr :
		spec_insn_lw_valid ? spec_insn_lw_rd_addr :
		spec_insn_lwu_valid ? spec_insn_lwu_rd_addr :
		spec_insn_max_valid ? spec_insn_max_rd_addr :
		spec_insn_maxu_valid ? spec_insn_maxu_rd_addr :
		spec_insn_min_valid ? spec_insn_min_rd_addr :
		spec_insn_minu_valid ? spec_insn_minu_rd_addr :
		spec_insn_or_valid ? spec_insn_or_rd_addr :
		spec_insn_orc_b_valid ? spec_insn_orc_b_rd_addr :
		spec_insn_ori_valid ? spec_insn_ori_rd_addr :
		spec_insn_orn_valid ? spec_insn_orn_rd_addr :
		spec_insn_rev8_valid ? spec_insn_rev8_rd_addr :
		spec_insn_rol_valid ? spec_insn_rol_rd_addr :
		spec_insn_rolw_valid ? spec_insn_rolw_rd_addr :
		spec_insn_ror_valid ? spec_insn_ror_rd_addr :
		spec_insn_rori_valid ? spec_insn_rori_rd_addr :
		spec_insn_roriw_valid ? spec_insn_roriw_rd_addr :
		spec_insn_rorw_valid ? spec_insn_rorw_rd_addr :
		spec_insn_sb_valid ? spec_insn_sb_rd_addr :
		spec_insn_sd_valid ? spec_insn_sd_rd_addr :
		spec_insn_sext_b_valid ? spec_insn_sext_b_rd_addr :
		spec_insn_sext_h_valid ? spec_insn_sext_h_rd_addr :
		spec_insn_sh_valid ? spec_insn_sh_rd_addr :
		spec_insn_sh1add_valid ? spec_insn_sh1add_rd_addr :
		spec_insn_sh1add_uw_valid ? spec_insn_sh1add_uw_rd_addr :
		spec_insn_sh2add_valid ? spec_insn_sh2add_rd_addr :
		spec_insn_sh2add_uw_valid ? spec_insn_sh2add_uw_rd_addr :
		spec_insn_sh3add_valid ? spec_insn_sh3add_rd_addr :
		spec_insn_sh3add_uw_valid ? spec_insn_sh3add_uw_rd_addr :
		spec_insn_sll_valid ? spec_insn_sll_rd_addr :
		spec_insn_slli_valid ? spec_insn_slli_rd_addr :
		spec_insn_slli_uw_valid ? spec_insn_slli_uw_rd_addr :
		spec_insn_slliw_valid ? spec_insn_slliw_rd_addr :
		spec_insn_sllw_valid ? spec_insn_sllw_rd_addr :
		spec_insn_slt_valid ? spec_insn_slt_rd_addr :
		spec_insn_slti_valid ? spec_insn_slti_rd_addr :
		spec_insn_sltiu_valid ? spec_insn_sltiu_rd_addr :
		spec_insn_sltu_valid ? spec_insn_sltu_rd_addr :
		spec_insn_sra_valid ? spec_insn_sra_rd_addr :
		spec_insn_srai_valid ? spec_insn_srai_rd_addr :
		spec_insn_sraiw_valid ? spec_insn_sraiw_rd_addr :
		spec_insn_sraw_valid ? spec_insn_sraw_rd_addr :
		spec_insn_srl_valid ? spec_insn_srl_rd_addr :
		spec_insn_srli_valid ? spec_insn_srli_rd_addr :
		spec_insn_srliw_valid ? spec_insn_srliw_rd_addr :
		spec_insn_srlw_valid ? spec_insn_srlw_rd_addr :
		spec_insn_sub_valid ? spec_insn_sub_rd_addr :
		spec_insn_subw_valid ? spec_insn_subw_rd_addr :
		spec_insn_sw_valid ? spec_insn_sw_rd_addr :
		spec_insn_xnor_valid ? spec_insn_xnor_rd_addr :
		spec_insn_xor_valid ? spec_insn_xor_rd_addr :
		spec_insn_xori_valid ? spec_insn_xori_rd_addr :
		spec_insn_zext_h_valid ? spec_insn_zext_h_rd_addr : 0;
  assign spec_rd_wdata =
		spec_insn_add_valid ? spec_insn_add_rd_wdata :
		spec_insn_add_uw_valid ? spec_insn_add_uw_rd_wdata :
		spec_insn_addi_valid ? spec_insn_addi_rd_wdata :
		spec_insn_addiw_valid ? spec_insn_addiw_rd_wdata :
		spec_insn_addw_valid ? spec_insn_addw_rd_wdata :
		spec_insn_and_valid ? spec_insn_and_rd_wdata :
		spec_insn_andi_valid ? spec_insn_andi_rd_wdata :
		spec_insn_andn_valid ? spec_insn_andn_rd_wdata :
		spec_insn_auipc_valid ? spec_insn_auipc_rd_wdata :
		spec_insn_bclr_valid ? spec_insn_bclr_rd_wdata :
		spec_insn_bclri_valid ? spec_insn_bclri_rd_wdata :
		spec_insn_beq_valid ? spec_insn_beq_rd_wdata :
		spec_insn_bext_valid ? spec_insn_bext_rd_wdata :
		spec_insn_bexti_valid ? spec_insn_bexti_rd_wdata :
		spec_insn_bge_valid ? spec_insn_bge_rd_wdata :
		spec_insn_bgeu_valid ? spec_insn_bgeu_rd_wdata :
		spec_insn_binv_valid ? spec_insn_binv_rd_wdata :
		spec_insn_binvi_valid ? spec_insn_binvi_rd_wdata :
		spec_insn_blt_valid ? spec_insn_blt_rd_wdata :
		spec_insn_bltu_valid ? spec_insn_bltu_rd_wdata :
		spec_insn_bne_valid ? spec_insn_bne_rd_wdata :
		spec_insn_bset_valid ? spec_insn_bset_rd_wdata :
		spec_insn_bseti_valid ? spec_insn_bseti_rd_wdata :
		spec_insn_clz_valid ? spec_insn_clz_rd_wdata :
		spec_insn_clzw_valid ? spec_insn_clzw_rd_wdata :
		spec_insn_cpop_valid ? spec_insn_cpop_rd_wdata :
		spec_insn_cpopw_valid ? spec_insn_cpopw_rd_wdata :
		spec_insn_ctz_valid ? spec_insn_ctz_rd_wdata :
		spec_insn_ctzw_valid ? spec_insn_ctzw_rd_wdata :
		spec_insn_jal_valid ? spec_insn_jal_rd_wdata :
		spec_insn_jalr_valid ? spec_insn_jalr_rd_wdata :
		spec_insn_lb_valid ? spec_insn_lb_rd_wdata :
		spec_insn_lbu_valid ? spec_insn_lbu_rd_wdata :
		spec_insn_ld_valid ? spec_insn_ld_rd_wdata :
		spec_insn_lh_valid ? spec_insn_lh_rd_wdata :
		spec_insn_lhu_valid ? spec_insn_lhu_rd_wdata :
		spec_insn_lui_valid ? spec_insn_lui_rd_wdata :
		spec_insn_lw_valid ? spec_insn_lw_rd_wdata :
		spec_insn_lwu_valid ? spec_insn_lwu_rd_wdata :
		spec_insn_max_valid ? spec_insn_max_rd_wdata :
		spec_insn_maxu_valid ? spec_insn_maxu_rd_wdata :
		spec_insn_min_valid ? spec_insn_min_rd_wdata :
		spec_insn_minu_valid ? spec_insn_minu_rd_wdata :
		spec_insn_or_valid ? spec_insn_or_rd_wdata :
		spec_insn_orc_b_valid ? spec_insn_orc_b_rd_wdata :
		spec_insn_ori_valid ? spec_insn_ori_rd_wdata :
		spec_insn_orn_valid ? spec_insn_orn_rd_wdata :
		spec_insn_rev8_valid ? spec_insn_rev8_rd_wdata :
		spec_insn_rol_valid ? spec_insn_rol_rd_wdata :
		spec_insn_rolw_valid ? spec_insn_rolw_rd_wdata :
		spec_insn_ror_valid ? spec_insn_ror_rd_wdata :
		spec_insn_rori_valid ? spec_insn_rori_rd_wdata :
		spec_insn_roriw_valid ? spec_insn_roriw_rd_wdata :
		spec_insn_rorw_valid ? spec_insn_rorw_rd_wdata :
		spec_insn_sb_valid ? spec_insn_sb_rd_wdata :
		spec_insn_sd_valid ? spec_insn_sd_rd_wdata :
		spec_insn_sext_b_valid ? spec_insn_sext_b_rd_wdata :
		spec_insn_sext_h_valid ? spec_insn_sext_h_rd_wdata :
		spec_insn_sh_valid ? spec_insn_sh_rd_wdata :
		spec_insn_sh1add_valid ? spec_insn_sh1add_rd_wdata :
		spec_insn_sh1add_uw_valid ? spec_insn_sh1add_uw_rd_wdata :
		spec_insn_sh2add_valid ? spec_insn_sh2add_rd_wdata :
		spec_insn_sh2add_uw_valid ? spec_insn_sh2add_uw_rd_wdata :
		spec_insn_sh3add_valid ? spec_insn_sh3add_rd_wdata :
		spec_insn_sh3add_uw_valid ? spec_insn_sh3add_uw_rd_wdata :
		spec_insn_sll_valid ? spec_insn_sll_rd_wdata :
		spec_insn_slli_valid ? spec_insn_slli_rd_wdata :
		spec_insn_slli_uw_valid ? spec_insn_slli_uw_rd_wdata :
		spec_insn_slliw_valid ? spec_insn_slliw_rd_wdata :
		spec_insn_sllw_valid ? spec_insn_sllw_rd_wdata :
		spec_insn_slt_valid ? spec_insn_slt_rd_wdata :
		spec_insn_slti_valid ? spec_insn_slti_rd_wdata :
		spec_insn_sltiu_valid ? spec_insn_sltiu_rd_wdata :
		spec_insn_sltu_valid ? spec_insn_sltu_rd_wdata :
		spec_insn_sra_valid ? spec_insn_sra_rd_wdata :
		spec_insn_srai_valid ? spec_insn_srai_rd_wdata :
		spec_insn_sraiw_valid ? spec_insn_sraiw_rd_wdata :
		spec_insn_sraw_valid ? spec_insn_sraw_rd_wdata :
		spec_insn_srl_valid ? spec_insn_srl_rd_wdata :
		spec_insn_srli_valid ? spec_insn_srli_rd_wdata :
		spec_insn_srliw_valid ? spec_insn_srliw_rd_wdata :
		spec_insn_srlw_valid ? spec_insn_srlw_rd_wdata :
		spec_insn_sub_valid ? spec_insn_sub_rd_wdata :
		spec_insn_subw_valid ? spec_insn_subw_rd_wdata :
		spec_insn_sw_valid ? spec_insn_sw_rd_wdata :
		spec_insn_xnor_valid ? spec_insn_xnor_rd_wdata :
		spec_insn_xor_valid ? spec_insn_xor_rd_wdata :
		spec_insn_xori_valid ? spec_insn_xori_rd_wdata :
		spec_insn_zext_h_valid ? spec_insn_zext_h_rd_wdata : 0;
  assign spec_pc_wdata =
		spec_insn_add_valid ? spec_insn_add_pc_wdata :
		spec_insn_add_uw_valid ? spec_insn_add_uw_pc_wdata :
		spec_insn_addi_valid ? spec_insn_addi_pc_wdata :
		spec_insn_addiw_valid ? spec_insn_addiw_pc_wdata :
		spec_insn_addw_valid ? spec_insn_addw_pc_wdata :
		spec_insn_and_valid ? spec_insn_and_pc_wdata :
		spec_insn_andi_valid ? spec_insn_andi_pc_wdata :
		spec_insn_andn_valid ? spec_insn_andn_pc_wdata :
		spec_insn_auipc_valid ? spec_insn_auipc_pc_wdata :
		spec_insn_bclr_valid ? spec_insn_bclr_pc_wdata :
		spec_insn_bclri_valid ? spec_insn_bclri_pc_wdata :
		spec_insn_beq_valid ? spec_insn_beq_pc_wdata :
		spec_insn_bext_valid ? spec_insn_bext_pc_wdata :
		spec_insn_bexti_valid ? spec_insn_bexti_pc_wdata :
		spec_insn_bge_valid ? spec_insn_bge_pc_wdata :
		spec_insn_bgeu_valid ? spec_insn_bgeu_pc_wdata :
		spec_insn_binv_valid ? spec_insn_binv_pc_wdata :
		spec_insn_binvi_valid ? spec_insn_binvi_pc_wdata :
		spec_insn_blt_valid ? spec_insn_blt_pc_wdata :
		spec_insn_bltu_valid ? spec_insn_bltu_pc_wdata :
		spec_insn_bne_valid ? spec_insn_bne_pc_wdata :
		spec_insn_bset_valid ? spec_insn_bset_pc_wdata :
		spec_insn_bseti_valid ? spec_insn_bseti_pc_wdata :
		spec_insn_clz_valid ? spec_insn_clz_pc_wdata :
		spec_insn_clzw_valid ? spec_insn_clzw_pc_wdata :
		spec_insn_cpop_valid ? spec_insn_cpop_pc_wdata :
		spec_insn_cpopw_valid ? spec_insn_cpopw_pc_wdata :
		spec_insn_ctz_valid ? spec_insn_ctz_pc_wdata :
		spec_insn_ctzw_valid ? spec_insn_ctzw_pc_wdata :
		spec_insn_jal_valid ? spec_insn_jal_pc_wdata :
		spec_insn_jalr_valid ? spec_insn_jalr_pc_wdata :
		spec_insn_lb_valid ? spec_insn_lb_pc_wdata :
		spec_insn_lbu_valid ? spec_insn_lbu_pc_wdata :
		spec_insn_ld_valid ? spec_insn_ld_pc_wdata :
		spec_insn_lh_valid ? spec_insn_lh_pc_wdata :
		spec_insn_lhu_valid ? spec_insn_lhu_pc_wdata :
		spec_insn_lui_valid ? spec_insn_lui_pc_wdata :
		spec_insn_lw_valid ? spec_insn_lw_pc_wdata :
		spec_insn_lwu_valid ? spec_insn_lwu_pc_wdata :
		spec_insn_max_valid ? spec_insn_max_pc_wdata :
		spec_insn_maxu_valid ? spec_insn_maxu_pc_wdata :
		spec_insn_min_valid ? spec_insn_min_pc_wdata :
		spec_insn_minu_valid ? spec_insn_minu_pc_wdata :
		spec_insn_or_valid ? spec_insn_or_pc_wdata :
		spec_insn_orc_b_valid ? spec_insn_orc_b_pc_wdata :
		spec_insn_ori_valid ? spec_insn_ori_pc_wdata :
		spec_insn_orn_valid ? spec_insn_orn_pc_wdata :
		spec_insn_rev8_valid ? spec_insn_rev8_pc_wdata :
		spec_insn_rol_valid ? spec_insn_rol_pc_wdata :
		spec_insn_rolw_valid ? spec_insn_rolw_pc_wdata :
		spec_insn_ror_valid ? spec_insn_ror_pc_wdata :
		spec_insn_rori_valid ? spec_insn_rori_pc_wdata :
		spec_insn_roriw_valid ? spec_insn_roriw_pc_wdata :
		spec_insn_rorw_valid ? spec_insn_rorw_pc_wdata :
		spec_insn_sb_valid ? spec_insn_sb_pc_wdata :
		spec_insn_sd_valid ? spec_insn_sd_pc_wdata :
		spec_insn_sext_b_valid ? spec_insn_sext_b_pc_wdata :
		spec_insn_sext_h_valid ? spec_insn_sext_h_pc_wdata :
		spec_insn_sh_valid ? spec_insn_sh_pc_wdata :
		spec_insn_sh1add_valid ? spec_insn_sh1add_pc_wdata :
		spec_insn_sh1add_uw_valid ? spec_insn_sh1add_uw_pc_wdata :
		spec_insn_sh2add_valid ? spec_insn_sh2add_pc_wdata :
		spec_insn_sh2add_uw_valid ? spec_insn_sh2add_uw_pc_wdata :
		spec_insn_sh3add_valid ? spec_insn_sh3add_pc_wdata :
		spec_insn_sh3add_uw_valid ? spec_insn_sh3add_uw_pc_wdata :
		spec_insn_sll_valid ? spec_insn_sll_pc_wdata :
		spec_insn_slli_valid ? spec_insn_slli_pc_wdata :
		spec_insn_slli_uw_valid ? spec_insn_slli_uw_pc_wdata :
		spec_insn_slliw_valid ? spec_insn_slliw_pc_wdata :
		spec_insn_sllw_valid ? spec_insn_sllw_pc_wdata :
		spec_insn_slt_valid ? spec_insn_slt_pc_wdata :
		spec_insn_slti_valid ? spec_insn_slti_pc_wdata :
		spec_insn_sltiu_valid ? spec_insn_sltiu_pc_wdata :
		spec_insn_sltu_valid ? spec_insn_sltu_pc_wdata :
		spec_insn_sra_valid ? spec_insn_sra_pc_wdata :
		spec_insn_srai_valid ? spec_insn_srai_pc_wdata :
		spec_insn_sraiw_valid ? spec_insn_sraiw_pc_wdata :
		spec_insn_sraw_valid ? spec_insn_sraw_pc_wdata :
		spec_insn_srl_valid ? spec_insn_srl_pc_wdata :
		spec_insn_srli_valid ? spec_insn_srli_pc_wdata :
		spec_insn_srliw_valid ? spec_insn_srliw_pc_wdata :
		spec_insn_srlw_valid ? spec_insn_srlw_pc_wdata :
		spec_insn_sub_valid ? spec_insn_sub_pc_wdata :
		spec_insn_subw_valid ? spec_insn_subw_pc_wdata :
		spec_insn_sw_valid ? spec_insn_sw_pc_wdata :
		spec_insn_xnor_valid ? spec_insn_xnor_pc_wdata :
		spec_insn_xor_valid ? spec_insn_xor_pc_wdata :
		spec_insn_xori_valid ? spec_insn_xori_pc_wdata :
		spec_insn_zext_h_valid ? spec_insn_zext_h_pc_wdata : 0;
  assign spec_mem_addr =
		spec_insn_add_valid ? spec_insn_add_mem_addr :
		spec_insn_add_uw_valid ? spec_insn_add_uw_mem_addr :
		spec_insn_addi_valid ? spec_insn_addi_mem_addr :
		spec_insn_addiw_valid ? spec_insn_addiw_mem_addr :
		spec_insn_addw_valid ? spec_insn_addw_mem_addr :
		spec_insn_and_valid ? spec_insn_and_mem_addr :
		spec_insn_andi_valid ? spec_insn_andi_mem_addr :
		spec_insn_andn_valid ? spec_insn_andn_mem_addr :
		spec_insn_auipc_valid ? spec_insn_auipc_mem_addr :
		spec_insn_bclr_valid ? spec_insn_bclr_mem_addr :
		spec_insn_bclri_valid ? spec_insn_bclri_mem_addr :
		spec_insn_beq_valid ? spec_insn_beq_mem_addr :
		spec_insn_bext_valid ? spec_insn_bext_mem_addr :
		spec_insn_bexti_valid ? spec_insn_bexti_mem_addr :
		spec_insn_bge_valid ? spec_insn_bge_mem_addr :
		spec_insn_bgeu_valid ? spec_insn_bgeu_mem_addr :
		spec_insn_binv_valid ? spec_insn_binv_mem_addr :
		spec_insn_binvi_valid ? spec_insn_binvi_mem_addr :
		spec_insn_blt_valid ? spec_insn_blt_mem_addr :
		spec_insn_bltu_valid ? spec_insn_bltu_mem_addr :
		spec_insn_bne_valid ? spec_insn_bne_mem_addr :
		spec_insn_bset_valid ? spec_insn_bset_mem_addr :
		spec_insn_bseti_valid ? spec_insn_bseti_mem_addr :
		spec_insn_clz_valid ? spec_insn_clz_mem_addr :
		spec_insn_clzw_valid ? spec_insn_clzw_mem_addr :
		spec_insn_cpop_valid ? spec_insn_cpop_mem_addr :
		spec_insn_cpopw_valid ? spec_insn_cpopw_mem_addr :
		spec_insn_ctz_valid ? spec_insn_ctz_mem_addr :
		spec_insn_ctzw_valid ? spec_insn_ctzw_mem_addr :
		spec_insn_jal_valid ? spec_insn_jal_mem_addr :
		spec_insn_jalr_valid ? spec_insn_jalr_mem_addr :
		spec_insn_lb_valid ? spec_insn_lb_mem_addr :
		spec_insn_lbu_valid ? spec_insn_lbu_mem_addr :
		spec_insn_ld_valid ? spec_insn_ld_mem_addr :
		spec_insn_lh_valid ? spec_insn_lh_mem_addr :
		spec_insn_lhu_valid ? spec_insn_lhu_mem_addr :
		spec_insn_lui_valid ? spec_insn_lui_mem_addr :
		spec_insn_lw_valid ? spec_insn_lw_mem_addr :
		spec_insn_lwu_valid ? spec_insn_lwu_mem_addr :
		spec_insn_max_valid ? spec_insn_max_mem_addr :
		spec_insn_maxu_valid ? spec_insn_maxu_mem_addr :
		spec_insn_min_valid ? spec_insn_min_mem_addr :
		spec_insn_minu_valid ? spec_insn_minu_mem_addr :
		spec_insn_or_valid ? spec_insn_or_mem_addr :
		spec_insn_orc_b_valid ? spec_insn_orc_b_mem_addr :
		spec_insn_ori_valid ? spec_insn_ori_mem_addr :
		spec_insn_orn_valid ? spec_insn_orn_mem_addr :
		spec_insn_rev8_valid ? spec_insn_rev8_mem_addr :
		spec_insn_rol_valid ? spec_insn_rol_mem_addr :
		spec_insn_rolw_valid ? spec_insn_rolw_mem_addr :
		spec_insn_ror_valid ? spec_insn_ror_mem_addr :
		spec_insn_rori_valid ? spec_insn_rori_mem_addr :
		spec_insn_roriw_valid ? spec_insn_roriw_mem_addr :
		spec_insn_rorw_valid ? spec_insn_rorw_mem_addr :
		spec_insn_sb_valid ? spec_insn_sb_mem_addr :
		spec_insn_sd_valid ? spec_insn_sd_mem_addr :
		spec_insn_sext_b_valid ? spec_insn_sext_b_mem_addr :
		spec_insn_sext_h_valid ? spec_insn_sext_h_mem_addr :
		spec_insn_sh_valid ? spec_insn_sh_mem_addr :
		spec_insn_sh1add_valid ? spec_insn_sh1add_mem_addr :
		spec_insn_sh1add_uw_valid ? spec_insn_sh1add_uw_mem_addr :
		spec_insn_sh2add_valid ? spec_insn_sh2add_mem_addr :
		spec_insn_sh2add_uw_valid ? spec_insn_sh2add_uw_mem_addr :
		spec_insn_sh3add_valid ? spec_insn_sh3add_mem_addr :
		spec_insn_sh3add_uw_valid ? spec_insn_sh3add_uw_mem_addr :
		spec_insn_sll_valid ? spec_insn_sll_mem_addr :
		spec_insn_slli_valid ? spec_insn_slli_mem_addr :
		spec_insn_slli_uw_valid ? spec_insn_slli_uw_mem_addr :
		spec_insn_slliw_valid ? spec_insn_slliw_mem_addr :
		spec_insn_sllw_valid ? spec_insn_sllw_mem_addr :
		spec_insn_slt_valid ? spec_insn_slt_mem_addr :
		spec_insn_slti_valid ? spec_insn_slti_mem_addr :
		spec_insn_sltiu_valid ? spec_insn_sltiu_mem_addr :
		spec_insn_sltu_valid ? spec_insn_sltu_mem_addr :
		spec_insn_sra_valid ? spec_insn_sra_mem_addr :
		spec_insn_srai_valid ? spec_insn_srai_mem_addr :
		spec_insn_sraiw_valid ? spec_insn_sraiw_mem_addr :
		spec_insn_sraw_valid ? spec_insn_sraw_mem_addr :
		spec_insn_srl_valid ? spec_insn_srl_mem_addr :
		spec_insn_srli_valid ? spec_insn_srli_mem_addr :
		spec_insn_srliw_valid ? spec_insn_srliw_mem_addr :
		spec_insn_srlw_valid ? spec_insn_srlw_mem_addr :
		spec_insn_sub_valid ? spec_insn_sub_mem_addr :
		spec_insn_subw_valid ? spec_insn_subw_mem_addr :
		spec_insn_sw_valid ? spec_insn_sw_mem_addr :
		spec_insn_xnor_valid ? spec_insn_xnor_mem_addr :
		spec_insn_xor_valid ? spec_insn_xor_mem_addr :
		spec_insn_xori_valid ? spec_insn_xori_mem_addr :
		spec_insn_zext_h_valid ? spec_insn_zext_h_mem_addr : 0;
  assign spec_mem_rmask =
		spec_insn_add_valid ? spec_insn_add_mem_rmask :
		spec_insn_add_uw_valid ? spec_insn_add_uw_mem_rmask :
		spec_insn_addi_valid ? spec_insn_addi_mem_rmask :
		spec_insn_addiw_valid ? spec_insn_addiw_mem_rmask :
		spec_insn_addw_valid ? spec_insn_addw_mem_rmask :
		spec_insn_and_valid ? spec_insn_and_mem_rmask :
		spec_insn_andi_valid ? spec_insn_andi_mem_rmask :
		spec_insn_andn_valid ? spec_insn_andn_mem_rmask :
		spec_insn_auipc_valid ? spec_insn_auipc_mem_rmask :
		spec_insn_bclr_valid ? spec_insn_bclr_mem_rmask :
		spec_insn_bclri_valid ? spec_insn_bclri_mem_rmask :
		spec_insn_beq_valid ? spec_insn_beq_mem_rmask :
		spec_insn_bext_valid ? spec_insn_bext_mem_rmask :
		spec_insn_bexti_valid ? spec_insn_bexti_mem_rmask :
		spec_insn_bge_valid ? spec_insn_bge_mem_rmask :
		spec_insn_bgeu_valid ? spec_insn_bgeu_mem_rmask :
		spec_insn_binv_valid ? spec_insn_binv_mem_rmask :
		spec_insn_binvi_valid ? spec_insn_binvi_mem_rmask :
		spec_insn_blt_valid ? spec_insn_blt_mem_rmask :
		spec_insn_bltu_valid ? spec_insn_bltu_mem_rmask :
		spec_insn_bne_valid ? spec_insn_bne_mem_rmask :
		spec_insn_bset_valid ? spec_insn_bset_mem_rmask :
		spec_insn_bseti_valid ? spec_insn_bseti_mem_rmask :
		spec_insn_clz_valid ? spec_insn_clz_mem_rmask :
		spec_insn_clzw_valid ? spec_insn_clzw_mem_rmask :
		spec_insn_cpop_valid ? spec_insn_cpop_mem_rmask :
		spec_insn_cpopw_valid ? spec_insn_cpopw_mem_rmask :
		spec_insn_ctz_valid ? spec_insn_ctz_mem_rmask :
		spec_insn_ctzw_valid ? spec_insn_ctzw_mem_rmask :
		spec_insn_jal_valid ? spec_insn_jal_mem_rmask :
		spec_insn_jalr_valid ? spec_insn_jalr_mem_rmask :
		spec_insn_lb_valid ? spec_insn_lb_mem_rmask :
		spec_insn_lbu_valid ? spec_insn_lbu_mem_rmask :
		spec_insn_ld_valid ? spec_insn_ld_mem_rmask :
		spec_insn_lh_valid ? spec_insn_lh_mem_rmask :
		spec_insn_lhu_valid ? spec_insn_lhu_mem_rmask :
		spec_insn_lui_valid ? spec_insn_lui_mem_rmask :
		spec_insn_lw_valid ? spec_insn_lw_mem_rmask :
		spec_insn_lwu_valid ? spec_insn_lwu_mem_rmask :
		spec_insn_max_valid ? spec_insn_max_mem_rmask :
		spec_insn_maxu_valid ? spec_insn_maxu_mem_rmask :
		spec_insn_min_valid ? spec_insn_min_mem_rmask :
		spec_insn_minu_valid ? spec_insn_minu_mem_rmask :
		spec_insn_or_valid ? spec_insn_or_mem_rmask :
		spec_insn_orc_b_valid ? spec_insn_orc_b_mem_rmask :
		spec_insn_ori_valid ? spec_insn_ori_mem_rmask :
		spec_insn_orn_valid ? spec_insn_orn_mem_rmask :
		spec_insn_rev8_valid ? spec_insn_rev8_mem_rmask :
		spec_insn_rol_valid ? spec_insn_rol_mem_rmask :
		spec_insn_rolw_valid ? spec_insn_rolw_mem_rmask :
		spec_insn_ror_valid ? spec_insn_ror_mem_rmask :
		spec_insn_rori_valid ? spec_insn_rori_mem_rmask :
		spec_insn_roriw_valid ? spec_insn_roriw_mem_rmask :
		spec_insn_rorw_valid ? spec_insn_rorw_mem_rmask :
		spec_insn_sb_valid ? spec_insn_sb_mem_rmask :
		spec_insn_sd_valid ? spec_insn_sd_mem_rmask :
		spec_insn_sext_b_valid ? spec_insn_sext_b_mem_rmask :
		spec_insn_sext_h_valid ? spec_insn_sext_h_mem_rmask :
		spec_insn_sh_valid ? spec_insn_sh_mem_rmask :
		spec_insn_sh1add_valid ? spec_insn_sh1add_mem_rmask :
		spec_insn_sh1add_uw_valid ? spec_insn_sh1add_uw_mem_rmask :
		spec_insn_sh2add_valid ? spec_insn_sh2add_mem_rmask :
		spec_insn_sh2add_uw_valid ? spec_insn_sh2add_uw_mem_rmask :
		spec_insn_sh3add_valid ? spec_insn_sh3add_mem_rmask :
		spec_insn_sh3add_uw_valid ? spec_insn_sh3add_uw_mem_rmask :
		spec_insn_sll_valid ? spec_insn_sll_mem_rmask :
		spec_insn_slli_valid ? spec_insn_slli_mem_rmask :
		spec_insn_slli_uw_valid ? spec_insn_slli_uw_mem_rmask :
		spec_insn_slliw_valid ? spec_insn_slliw_mem_rmask :
		spec_insn_sllw_valid ? spec_insn_sllw_mem_rmask :
		spec_insn_slt_valid ? spec_insn_slt_mem_rmask :
		spec_insn_slti_valid ? spec_insn_slti_mem_rmask :
		spec_insn_sltiu_valid ? spec_insn_sltiu_mem_rmask :
		spec_insn_sltu_valid ? spec_insn_sltu_mem_rmask :
		spec_insn_sra_valid ? spec_insn_sra_mem_rmask :
		spec_insn_srai_valid ? spec_insn_srai_mem_rmask :
		spec_insn_sraiw_valid ? spec_insn_sraiw_mem_rmask :
		spec_insn_sraw_valid ? spec_insn_sraw_mem_rmask :
		spec_insn_srl_valid ? spec_insn_srl_mem_rmask :
		spec_insn_srli_valid ? spec_insn_srli_mem_rmask :
		spec_insn_srliw_valid ? spec_insn_srliw_mem_rmask :
		spec_insn_srlw_valid ? spec_insn_srlw_mem_rmask :
		spec_insn_sub_valid ? spec_insn_sub_mem_rmask :
		spec_insn_subw_valid ? spec_insn_subw_mem_rmask :
		spec_insn_sw_valid ? spec_insn_sw_mem_rmask :
		spec_insn_xnor_valid ? spec_insn_xnor_mem_rmask :
		spec_insn_xor_valid ? spec_insn_xor_mem_rmask :
		spec_insn_xori_valid ? spec_insn_xori_mem_rmask :
		spec_insn_zext_h_valid ? spec_insn_zext_h_mem_rmask : 0;
  assign spec_mem_wmask =
		spec_insn_add_valid ? spec_insn_add_mem_wmask :
		spec_insn_add_uw_valid ? spec_insn_add_uw_mem_wmask :
		spec_insn_addi_valid ? spec_insn_addi_mem_wmask :
		spec_insn_addiw_valid ? spec_insn_addiw_mem_wmask :
		spec_insn_addw_valid ? spec_insn_addw_mem_wmask :
		spec_insn_and_valid ? spec_insn_and_mem_wmask :
		spec_insn_andi_valid ? spec_insn_andi_mem_wmask :
		spec_insn_andn_valid ? spec_insn_andn_mem_wmask :
		spec_insn_auipc_valid ? spec_insn_auipc_mem_wmask :
		spec_insn_bclr_valid ? spec_insn_bclr_mem_wmask :
		spec_insn_bclri_valid ? spec_insn_bclri_mem_wmask :
		spec_insn_beq_valid ? spec_insn_beq_mem_wmask :
		spec_insn_bext_valid ? spec_insn_bext_mem_wmask :
		spec_insn_bexti_valid ? spec_insn_bexti_mem_wmask :
		spec_insn_bge_valid ? spec_insn_bge_mem_wmask :
		spec_insn_bgeu_valid ? spec_insn_bgeu_mem_wmask :
		spec_insn_binv_valid ? spec_insn_binv_mem_wmask :
		spec_insn_binvi_valid ? spec_insn_binvi_mem_wmask :
		spec_insn_blt_valid ? spec_insn_blt_mem_wmask :
		spec_insn_bltu_valid ? spec_insn_bltu_mem_wmask :
		spec_insn_bne_valid ? spec_insn_bne_mem_wmask :
		spec_insn_bset_valid ? spec_insn_bset_mem_wmask :
		spec_insn_bseti_valid ? spec_insn_bseti_mem_wmask :
		spec_insn_clz_valid ? spec_insn_clz_mem_wmask :
		spec_insn_clzw_valid ? spec_insn_clzw_mem_wmask :
		spec_insn_cpop_valid ? spec_insn_cpop_mem_wmask :
		spec_insn_cpopw_valid ? spec_insn_cpopw_mem_wmask :
		spec_insn_ctz_valid ? spec_insn_ctz_mem_wmask :
		spec_insn_ctzw_valid ? spec_insn_ctzw_mem_wmask :
		spec_insn_jal_valid ? spec_insn_jal_mem_wmask :
		spec_insn_jalr_valid ? spec_insn_jalr_mem_wmask :
		spec_insn_lb_valid ? spec_insn_lb_mem_wmask :
		spec_insn_lbu_valid ? spec_insn_lbu_mem_wmask :
		spec_insn_ld_valid ? spec_insn_ld_mem_wmask :
		spec_insn_lh_valid ? spec_insn_lh_mem_wmask :
		spec_insn_lhu_valid ? spec_insn_lhu_mem_wmask :
		spec_insn_lui_valid ? spec_insn_lui_mem_wmask :
		spec_insn_lw_valid ? spec_insn_lw_mem_wmask :
		spec_insn_lwu_valid ? spec_insn_lwu_mem_wmask :
		spec_insn_max_valid ? spec_insn_max_mem_wmask :
		spec_insn_maxu_valid ? spec_insn_maxu_mem_wmask :
		spec_insn_min_valid ? spec_insn_min_mem_wmask :
		spec_insn_minu_valid ? spec_insn_minu_mem_wmask :
		spec_insn_or_valid ? spec_insn_or_mem_wmask :
		spec_insn_orc_b_valid ? spec_insn_orc_b_mem_wmask :
		spec_insn_ori_valid ? spec_insn_ori_mem_wmask :
		spec_insn_orn_valid ? spec_insn_orn_mem_wmask :
		spec_insn_rev8_valid ? spec_insn_rev8_mem_wmask :
		spec_insn_rol_valid ? spec_insn_rol_mem_wmask :
		spec_insn_rolw_valid ? spec_insn_rolw_mem_wmask :
		spec_insn_ror_valid ? spec_insn_ror_mem_wmask :
		spec_insn_rori_valid ? spec_insn_rori_mem_wmask :
		spec_insn_roriw_valid ? spec_insn_roriw_mem_wmask :
		spec_insn_rorw_valid ? spec_insn_rorw_mem_wmask :
		spec_insn_sb_valid ? spec_insn_sb_mem_wmask :
		spec_insn_sd_valid ? spec_insn_sd_mem_wmask :
		spec_insn_sext_b_valid ? spec_insn_sext_b_mem_wmask :
		spec_insn_sext_h_valid ? spec_insn_sext_h_mem_wmask :
		spec_insn_sh_valid ? spec_insn_sh_mem_wmask :
		spec_insn_sh1add_valid ? spec_insn_sh1add_mem_wmask :
		spec_insn_sh1add_uw_valid ? spec_insn_sh1add_uw_mem_wmask :
		spec_insn_sh2add_valid ? spec_insn_sh2add_mem_wmask :
		spec_insn_sh2add_uw_valid ? spec_insn_sh2add_uw_mem_wmask :
		spec_insn_sh3add_valid ? spec_insn_sh3add_mem_wmask :
		spec_insn_sh3add_uw_valid ? spec_insn_sh3add_uw_mem_wmask :
		spec_insn_sll_valid ? spec_insn_sll_mem_wmask :
		spec_insn_slli_valid ? spec_insn_slli_mem_wmask :
		spec_insn_slli_uw_valid ? spec_insn_slli_uw_mem_wmask :
		spec_insn_slliw_valid ? spec_insn_slliw_mem_wmask :
		spec_insn_sllw_valid ? spec_insn_sllw_mem_wmask :
		spec_insn_slt_valid ? spec_insn_slt_mem_wmask :
		spec_insn_slti_valid ? spec_insn_slti_mem_wmask :
		spec_insn_sltiu_valid ? spec_insn_sltiu_mem_wmask :
		spec_insn_sltu_valid ? spec_insn_sltu_mem_wmask :
		spec_insn_sra_valid ? spec_insn_sra_mem_wmask :
		spec_insn_srai_valid ? spec_insn_srai_mem_wmask :
		spec_insn_sraiw_valid ? spec_insn_sraiw_mem_wmask :
		spec_insn_sraw_valid ? spec_insn_sraw_mem_wmask :
		spec_insn_srl_valid ? spec_insn_srl_mem_wmask :
		spec_insn_srli_valid ? spec_insn_srli_mem_wmask :
		spec_insn_srliw_valid ? spec_insn_srliw_mem_wmask :
		spec_insn_srlw_valid ? spec_insn_srlw_mem_wmask :
		spec_insn_sub_valid ? spec_insn_sub_mem_wmask :
		spec_insn_subw_valid ? spec_insn_subw_mem_wmask :
		spec_insn_sw_valid ? spec_insn_sw_mem_wmask :
		spec_insn_xnor_valid ? spec_insn_xnor_mem_wmask :
		spec_insn_xor_valid ? spec_insn_xor_mem_wmask :
		spec_insn_xori_valid ? spec_insn_xori_mem_wmask :
		spec_insn_zext_h_valid ? spec_insn_zext_h_mem_wmask : 0;
  assign spec_mem_wdata =
		spec_insn_add_valid ? spec_insn_add_mem_wdata :
		spec_insn_add_uw_valid ? spec_insn_add_uw_mem_wdata :
		spec_insn_addi_valid ? spec_insn_addi_mem_wdata :
		spec_insn_addiw_valid ? spec_insn_addiw_mem_wdata :
		spec_insn_addw_valid ? spec_insn_addw_mem_wdata :
		spec_insn_and_valid ? spec_insn_and_mem_wdata :
		spec_insn_andi_valid ? spec_insn_andi_mem_wdata :
		spec_insn_andn_valid ? spec_insn_andn_mem_wdata :
		spec_insn_auipc_valid ? spec_insn_auipc_mem_wdata :
		spec_insn_bclr_valid ? spec_insn_bclr_mem_wdata :
		spec_insn_bclri_valid ? spec_insn_bclri_mem_wdata :
		spec_insn_beq_valid ? spec_insn_beq_mem_wdata :
		spec_insn_bext_valid ? spec_insn_bext_mem_wdata :
		spec_insn_bexti_valid ? spec_insn_bexti_mem_wdata :
		spec_insn_bge_valid ? spec_insn_bge_mem_wdata :
		spec_insn_bgeu_valid ? spec_insn_bgeu_mem_wdata :
		spec_insn_binv_valid ? spec_insn_binv_mem_wdata :
		spec_insn_binvi_valid ? spec_insn_binvi_mem_wdata :
		spec_insn_blt_valid ? spec_insn_blt_mem_wdata :
		spec_insn_bltu_valid ? spec_insn_bltu_mem_wdata :
		spec_insn_bne_valid ? spec_insn_bne_mem_wdata :
		spec_insn_bset_valid ? spec_insn_bset_mem_wdata :
		spec_insn_bseti_valid ? spec_insn_bseti_mem_wdata :
		spec_insn_clz_valid ? spec_insn_clz_mem_wdata :
		spec_insn_clzw_valid ? spec_insn_clzw_mem_wdata :
		spec_insn_cpop_valid ? spec_insn_cpop_mem_wdata :
		spec_insn_cpopw_valid ? spec_insn_cpopw_mem_wdata :
		spec_insn_ctz_valid ? spec_insn_ctz_mem_wdata :
		spec_insn_ctzw_valid ? spec_insn_ctzw_mem_wdata :
		spec_insn_jal_valid ? spec_insn_jal_mem_wdata :
		spec_insn_jalr_valid ? spec_insn_jalr_mem_wdata :
		spec_insn_lb_valid ? spec_insn_lb_mem_wdata :
		spec_insn_lbu_valid ? spec_insn_lbu_mem_wdata :
		spec_insn_ld_valid ? spec_insn_ld_mem_wdata :
		spec_insn_lh_valid ? spec_insn_lh_mem_wdata :
		spec_insn_lhu_valid ? spec_insn_lhu_mem_wdata :
		spec_insn_lui_valid ? spec_insn_lui_mem_wdata :
		spec_insn_lw_valid ? spec_insn_lw_mem_wdata :
		spec_insn_lwu_valid ? spec_insn_lwu_mem_wdata :
		spec_insn_max_valid ? spec_insn_max_mem_wdata :
		spec_insn_maxu_valid ? spec_insn_maxu_mem_wdata :
		spec_insn_min_valid ? spec_insn_min_mem_wdata :
		spec_insn_minu_valid ? spec_insn_minu_mem_wdata :
		spec_insn_or_valid ? spec_insn_or_mem_wdata :
		spec_insn_orc_b_valid ? spec_insn_orc_b_mem_wdata :
		spec_insn_ori_valid ? spec_insn_ori_mem_wdata :
		spec_insn_orn_valid ? spec_insn_orn_mem_wdata :
		spec_insn_rev8_valid ? spec_insn_rev8_mem_wdata :
		spec_insn_rol_valid ? spec_insn_rol_mem_wdata :
		spec_insn_rolw_valid ? spec_insn_rolw_mem_wdata :
		spec_insn_ror_valid ? spec_insn_ror_mem_wdata :
		spec_insn_rori_valid ? spec_insn_rori_mem_wdata :
		spec_insn_roriw_valid ? spec_insn_roriw_mem_wdata :
		spec_insn_rorw_valid ? spec_insn_rorw_mem_wdata :
		spec_insn_sb_valid ? spec_insn_sb_mem_wdata :
		spec_insn_sd_valid ? spec_insn_sd_mem_wdata :
		spec_insn_sext_b_valid ? spec_insn_sext_b_mem_wdata :
		spec_insn_sext_h_valid ? spec_insn_sext_h_mem_wdata :
		spec_insn_sh_valid ? spec_insn_sh_mem_wdata :
		spec_insn_sh1add_valid ? spec_insn_sh1add_mem_wdata :
		spec_insn_sh1add_uw_valid ? spec_insn_sh1add_uw_mem_wdata :
		spec_insn_sh2add_valid ? spec_insn_sh2add_mem_wdata :
		spec_insn_sh2add_uw_valid ? spec_insn_sh2add_uw_mem_wdata :
		spec_insn_sh3add_valid ? spec_insn_sh3add_mem_wdata :
		spec_insn_sh3add_uw_valid ? spec_insn_sh3add_uw_mem_wdata :
		spec_insn_sll_valid ? spec_insn_sll_mem_wdata :
		spec_insn_slli_valid ? spec_insn_slli_mem_wdata :
		spec_insn_slli_uw_valid ? spec_insn_slli_uw_mem_wdata :
		spec_insn_slliw_valid ? spec_insn_slliw_mem_wdata :
		spec_insn_sllw_valid ? spec_insn_sllw_mem_wdata :
		spec_insn_slt_valid ? spec_insn_slt_mem_wdata :
		spec_insn_slti_valid ? spec_insn_slti_mem_wdata :
		spec_insn_sltiu_valid ? spec_insn_sltiu_mem_wdata :
		spec_insn_sltu_valid ? spec_insn_sltu_mem_wdata :
		spec_insn_sra_valid ? spec_insn_sra_mem_wdata :
		spec_insn_srai_valid ? spec_insn_srai_mem_wdata :
		spec_insn_sraiw_valid ? spec_insn_sraiw_mem_wdata :
		spec_insn_sraw_valid ? spec_insn_sraw_mem_wdata :
		spec_insn_srl_valid ? spec_insn_srl_mem_wdata :
		spec_insn_srli_valid ? spec_insn_srli_mem_wdata :
		spec_insn_srliw_valid ? spec_insn_srliw_mem_wdata :
		spec_insn_srlw_valid ? spec_insn_srlw_mem_wdata :
		spec_insn_sub_valid ? spec_insn_sub_mem_wdata :
		spec_insn_subw_valid ? spec_insn_subw_mem_wdata :
		spec_insn_sw_valid ? spec_insn_sw_mem_wdata :
		spec_insn_xnor_valid ? spec_insn_xnor_mem_wdata :
		spec_insn_xor_valid ? spec_insn_xor_mem_wdata :
		spec_insn_xori_valid ? spec_insn_xori_mem_wdata :
		spec_insn_zext_h_valid ? spec_insn_zext_h_mem_wdata : 0;
`ifdef RISCV_FORMAL_CSR_MISA
  assign spec_csr_misa_rmask =
		spec_insn_add_valid ? spec_insn_add_csr_misa_rmask :
		spec_insn_add_uw_valid ? spec_insn_add_uw_csr_misa_rmask :
		spec_insn_addi_valid ? spec_insn_addi_csr_misa_rmask :
		spec_insn_addiw_valid ? spec_insn_addiw_csr_misa_rmask :
		spec_insn_addw_valid ? spec_insn_addw_csr_misa_rmask :
		spec_insn_and_valid ? spec_insn_and_csr_misa_rmask :
		spec_insn_andi_valid ? spec_insn_andi_csr_misa_rmask :
		spec_insn_andn_valid ? spec_insn_andn_csr_misa_rmask :
		spec_insn_auipc_valid ? spec_insn_auipc_csr_misa_rmask :
		spec_insn_bclr_valid ? spec_insn_bclr_csr_misa_rmask :
		spec_insn_bclri_valid ? spec_insn_bclri_csr_misa_rmask :
		spec_insn_beq_valid ? spec_insn_beq_csr_misa_rmask :
		spec_insn_bext_valid ? spec_insn_bext_csr_misa_rmask :
		spec_insn_bexti_valid ? spec_insn_bexti_csr_misa_rmask :
		spec_insn_bge_valid ? spec_insn_bge_csr_misa_rmask :
		spec_insn_bgeu_valid ? spec_insn_bgeu_csr_misa_rmask :
		spec_insn_binv_valid ? spec_insn_binv_csr_misa_rmask :
		spec_insn_binvi_valid ? spec_insn_binvi_csr_misa_rmask :
		spec_insn_blt_valid ? spec_insn_blt_csr_misa_rmask :
		spec_insn_bltu_valid ? spec_insn_bltu_csr_misa_rmask :
		spec_insn_bne_valid ? spec_insn_bne_csr_misa_rmask :
		spec_insn_bset_valid ? spec_insn_bset_csr_misa_rmask :
		spec_insn_bseti_valid ? spec_insn_bseti_csr_misa_rmask :
		spec_insn_clz_valid ? spec_insn_clz_csr_misa_rmask :
		spec_insn_clzw_valid ? spec_insn_clzw_csr_misa_rmask :
		spec_insn_cpop_valid ? spec_insn_cpop_csr_misa_rmask :
		spec_insn_cpopw_valid ? spec_insn_cpopw_csr_misa_rmask :
		spec_insn_ctz_valid ? spec_insn_ctz_csr_misa_rmask :
		spec_insn_ctzw_valid ? spec_insn_ctzw_csr_misa_rmask :
		spec_insn_jal_valid ? spec_insn_jal_csr_misa_rmask :
		spec_insn_jalr_valid ? spec_insn_jalr_csr_misa_rmask :
		spec_insn_lb_valid ? spec_insn_lb_csr_misa_rmask :
		spec_insn_lbu_valid ? spec_insn_lbu_csr_misa_rmask :
		spec_insn_ld_valid ? spec_insn_ld_csr_misa_rmask :
		spec_insn_lh_valid ? spec_insn_lh_csr_misa_rmask :
		spec_insn_lhu_valid ? spec_insn_lhu_csr_misa_rmask :
		spec_insn_lui_valid ? spec_insn_lui_csr_misa_rmask :
		spec_insn_lw_valid ? spec_insn_lw_csr_misa_rmask :
		spec_insn_lwu_valid ? spec_insn_lwu_csr_misa_rmask :
		spec_insn_max_valid ? spec_insn_max_csr_misa_rmask :
		spec_insn_maxu_valid ? spec_insn_maxu_csr_misa_rmask :
		spec_insn_min_valid ? spec_insn_min_csr_misa_rmask :
		spec_insn_minu_valid ? spec_insn_minu_csr_misa_rmask :
		spec_insn_or_valid ? spec_insn_or_csr_misa_rmask :
		spec_insn_orc_b_valid ? spec_insn_orc_b_csr_misa_rmask :
		spec_insn_ori_valid ? spec_insn_ori_csr_misa_rmask :
		spec_insn_orn_valid ? spec_insn_orn_csr_misa_rmask :
		spec_insn_rev8_valid ? spec_insn_rev8_csr_misa_rmask :
		spec_insn_rol_valid ? spec_insn_rol_csr_misa_rmask :
		spec_insn_rolw_valid ? spec_insn_rolw_csr_misa_rmask :
		spec_insn_ror_valid ? spec_insn_ror_csr_misa_rmask :
		spec_insn_rori_valid ? spec_insn_rori_csr_misa_rmask :
		spec_insn_roriw_valid ? spec_insn_roriw_csr_misa_rmask :
		spec_insn_rorw_valid ? spec_insn_rorw_csr_misa_rmask :
		spec_insn_sb_valid ? spec_insn_sb_csr_misa_rmask :
		spec_insn_sd_valid ? spec_insn_sd_csr_misa_rmask :
		spec_insn_sext_b_valid ? spec_insn_sext_b_csr_misa_rmask :
		spec_insn_sext_h_valid ? spec_insn_sext_h_csr_misa_rmask :
		spec_insn_sh_valid ? spec_insn_sh_csr_misa_rmask :
		spec_insn_sh1add_valid ? spec_insn_sh1add_csr_misa_rmask :
		spec_insn_sh1add_uw_valid ? spec_insn_sh1add_uw_csr_misa_rmask :
		spec_insn_sh2add_valid ? spec_insn_sh2add_csr_misa_rmask :
		spec_insn_sh2add_uw_valid ? spec_insn_sh2add_uw_csr_misa_rmask :
		spec_insn_sh3add_valid ? spec_insn_sh3add_csr_misa_rmask :
		spec_insn_sh3add_uw_valid ? spec_insn_sh3add_uw_csr_misa_rmask :
		spec_insn_sll_valid ? spec_insn_sll_csr_misa_rmask :
		spec_insn_slli_valid ? spec_insn_slli_csr_misa_rmask :
		spec_insn_slli_uw_valid ? spec_insn_slli_uw_csr_misa_rmask :
		spec_insn_slliw_valid ? spec_insn_slliw_csr_misa_rmask :
		spec_insn_sllw_valid ? spec_insn_sllw_csr_misa_rmask :
		spec_insn_slt_valid ? spec_insn_slt_csr_misa_rmask :
		spec_insn_slti_valid ? spec_insn_slti_csr_misa_rmask :
		spec_insn_sltiu_valid ? spec_insn_sltiu_csr_misa_rmask :
		spec_insn_sltu_valid ? spec_insn_sltu_csr_misa_rmask :
		spec_insn_sra_valid ? spec_insn_sra_csr_misa_rmask :
		spec_insn_srai_valid ? spec_insn_srai_csr_misa_rmask :
		spec_insn_sraiw_valid ? spec_insn_sraiw_csr_misa_rmask :
		spec_insn_sraw_valid ? spec_insn_sraw_csr_misa_rmask :
		spec_insn_srl_valid ? spec_insn_srl_csr_misa_rmask :
		spec_insn_srli_valid ? spec_insn_srli_csr_misa_rmask :
		spec_insn_srliw_valid ? spec_insn_srliw_csr_misa_rmask :
		spec_insn_srlw_valid ? spec_insn_srlw_csr_misa_rmask :
		spec_insn_sub_valid ? spec_insn_sub_csr_misa_rmask :
		spec_insn_subw_valid ? spec_insn_subw_csr_misa_rmask :
		spec_insn_sw_valid ? spec_insn_sw_csr_misa_rmask :
		spec_insn_xnor_valid ? spec_insn_xnor_csr_misa_rmask :
		spec_insn_xor_valid ? spec_insn_xor_csr_misa_rmask :
		spec_insn_xori_valid ? spec_insn_xori_csr_misa_rmask :
		spec_insn_zext_h_valid ? spec_insn_zext_h_csr_misa_rmask : 0;
`endif
endmodule
