
// -----------
// This file was generated by riscv_ctg (https://github.com/riscv-software-src/riscv-ctg)
// version   : 0.11.0
// timestamp : Mon Feb  5 07:30:48 2024 GMT
// usage     : riscv_ctg \
//                  -- cgf //                  --cgf /home/riscv/riscv-ctg/sample_cgfs/dataset.cgf \
//                  --cgf /home/riscv/riscv-ctg/sample_cgfs/sample_cgfs_fext/RV64Zfinx/fnmadd.s.cgf \
 \
//                  -- xlen 64  \
// -----------
//
// -----------
// Copyright (c) 2020. RISC-V International. All rights reserved.
// SPDX-License-Identifier: BSD-3-Clause
// -----------
//
// This assembly file tests the fnmadd.s instruction of the RISC-V RV64_Zfinx,RV64_Zdinx extension for the fnmadd_b15 covergroup.
// 
#include "model_test.h"
#include "arch_test.h"
RVTEST_ISA("RV64I_Zfinx,RV64I_Zdinx")

.section .text.init
.globl rvtest_entry_point
rvtest_entry_point:
RVMODEL_BOOT
RVTEST_CODE_BEGIN

#ifdef TEST_CASE_1

RVTEST_CASE(0,"//check ISA:=regex(.*I.*Zfinx.*);def TEST_CASE_1=True;",fnmadd_b15)

RVTEST_FP_ENABLE()
RVTEST_VALBASEUPD(x3,test_dataset_0)
RVTEST_SIGBASE(x1,signature_x1_1)

inst_1534:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3a0e48 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x249249 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f3a0e48; op2val:0x0;
op3val:0x249249; valaddr_reg:x12; val_offset:4539*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 4539*FLEN/8, x13, x9, x10)

inst_1535:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3a0e48 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x5b6db6 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f3a0e48; op2val:0x0;
op3val:0x5b6db6; valaddr_reg:x12; val_offset:4542*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 4542*FLEN/8, x13, x9, x10)

inst_1536:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3a0e48 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x333333 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f3a0e48; op2val:0x0;
op3val:0x333333; valaddr_reg:x12; val_offset:4545*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 4545*FLEN/8, x13, x9, x10)

inst_1537:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3a0e48 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x4ccccc and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f3a0e48; op2val:0x0;
op3val:0x4ccccc; valaddr_reg:x12; val_offset:4548*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 4548*FLEN/8, x13, x9, x10)

inst_1538:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x0b5d1b and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x17 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f0b5d1b; op2val:0x0;
op3val:0xb800000; valaddr_reg:x12; val_offset:4551*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 4551*FLEN/8, x13, x9, x10)

inst_1539:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x0b5d1b and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x17 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f0b5d1b; op2val:0x0;
op3val:0xbffffff; valaddr_reg:x12; val_offset:4554*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 4554*FLEN/8, x13, x9, x10)

inst_1540:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x0b5d1b and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x17 and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f0b5d1b; op2val:0x0;
op3val:0xbc00000; valaddr_reg:x12; val_offset:4557*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 4557*FLEN/8, x13, x9, x10)

inst_1541:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x0b5d1b and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x17 and fm3 == 0x3fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f0b5d1b; op2val:0x0;
op3val:0xbbfffff; valaddr_reg:x12; val_offset:4560*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 4560*FLEN/8, x13, x9, x10)

inst_1542:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x0b5d1b and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x17 and fm3 == 0x600000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f0b5d1b; op2val:0x0;
op3val:0xbe00000; valaddr_reg:x12; val_offset:4563*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 4563*FLEN/8, x13, x9, x10)

inst_1543:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x0b5d1b and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x17 and fm3 == 0x1fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f0b5d1b; op2val:0x0;
op3val:0xb9fffff; valaddr_reg:x12; val_offset:4566*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 4566*FLEN/8, x13, x9, x10)

inst_1544:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x0b5d1b and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x17 and fm3 == 0x700000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f0b5d1b; op2val:0x0;
op3val:0xbf00000; valaddr_reg:x12; val_offset:4569*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 4569*FLEN/8, x13, x9, x10)

inst_1545:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x0b5d1b and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x17 and fm3 == 0x0fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f0b5d1b; op2val:0x0;
op3val:0xb8fffff; valaddr_reg:x12; val_offset:4572*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 4572*FLEN/8, x13, x9, x10)

inst_1546:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x0b5d1b and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x17 and fm3 == 0x780000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f0b5d1b; op2val:0x0;
op3val:0xbf80000; valaddr_reg:x12; val_offset:4575*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 4575*FLEN/8, x13, x9, x10)

inst_1547:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x0b5d1b and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x17 and fm3 == 0x07ffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f0b5d1b; op2val:0x0;
op3val:0xb87ffff; valaddr_reg:x12; val_offset:4578*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 4578*FLEN/8, x13, x9, x10)

inst_1548:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x0b5d1b and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x17 and fm3 == 0x7c0000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f0b5d1b; op2val:0x0;
op3val:0xbfc0000; valaddr_reg:x12; val_offset:4581*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 4581*FLEN/8, x13, x9, x10)

inst_1549:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x0b5d1b and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x17 and fm3 == 0x03ffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f0b5d1b; op2val:0x0;
op3val:0xb83ffff; valaddr_reg:x12; val_offset:4584*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 4584*FLEN/8, x13, x9, x10)

inst_1550:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x0b5d1b and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x17 and fm3 == 0x7e0000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f0b5d1b; op2val:0x0;
op3val:0xbfe0000; valaddr_reg:x12; val_offset:4587*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 4587*FLEN/8, x13, x9, x10)

inst_1551:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x0b5d1b and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x17 and fm3 == 0x01ffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f0b5d1b; op2val:0x0;
op3val:0xb81ffff; valaddr_reg:x12; val_offset:4590*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 4590*FLEN/8, x13, x9, x10)

inst_1552:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x0b5d1b and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x17 and fm3 == 0x7f0000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f0b5d1b; op2val:0x0;
op3val:0xbff0000; valaddr_reg:x12; val_offset:4593*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 4593*FLEN/8, x13, x9, x10)

inst_1553:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x0b5d1b and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x17 and fm3 == 0x00ffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f0b5d1b; op2val:0x0;
op3val:0xb80ffff; valaddr_reg:x12; val_offset:4596*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 4596*FLEN/8, x13, x9, x10)

inst_1554:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x0b5d1b and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x17 and fm3 == 0x7f8000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f0b5d1b; op2val:0x0;
op3val:0xbff8000; valaddr_reg:x12; val_offset:4599*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 4599*FLEN/8, x13, x9, x10)

inst_1555:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x0b5d1b and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x17 and fm3 == 0x007fff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f0b5d1b; op2val:0x0;
op3val:0xb807fff; valaddr_reg:x12; val_offset:4602*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 4602*FLEN/8, x13, x9, x10)

inst_1556:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x0b5d1b and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x17 and fm3 == 0x7fc000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f0b5d1b; op2val:0x0;
op3val:0xbffc000; valaddr_reg:x12; val_offset:4605*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 4605*FLEN/8, x13, x9, x10)

inst_1557:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x0b5d1b and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x17 and fm3 == 0x003fff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f0b5d1b; op2val:0x0;
op3val:0xb803fff; valaddr_reg:x12; val_offset:4608*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 4608*FLEN/8, x13, x9, x10)

inst_1558:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x0b5d1b and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x17 and fm3 == 0x7fe000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f0b5d1b; op2val:0x0;
op3val:0xbffe000; valaddr_reg:x12; val_offset:4611*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 4611*FLEN/8, x13, x9, x10)

inst_1559:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x0b5d1b and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x17 and fm3 == 0x001fff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f0b5d1b; op2val:0x0;
op3val:0xb801fff; valaddr_reg:x12; val_offset:4614*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 4614*FLEN/8, x13, x9, x10)

RVTEST_SIGBASE(x9,signature_x9_12)
inst_1560:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x0b5d1b and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x17 and fm3 == 0x7ff000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f0b5d1b; op2val:0x0;
op3val:0xbfff000; valaddr_reg:x12; val_offset:4617*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 4617*FLEN/8, x13, x9, x10)

inst_1561:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x0b5d1b and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x17 and fm3 == 0x000fff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f0b5d1b; op2val:0x0;
op3val:0xb800fff; valaddr_reg:x12; val_offset:4620*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 4620*FLEN/8, x13, x9, x10)

inst_1562:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x0b5d1b and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x17 and fm3 == 0x7ff800 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f0b5d1b; op2val:0x0;
op3val:0xbfff800; valaddr_reg:x12; val_offset:4623*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 4623*FLEN/8, x13, x9, x10)

inst_1563:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x0b5d1b and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x17 and fm3 == 0x0007ff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f0b5d1b; op2val:0x0;
op3val:0xb8007ff; valaddr_reg:x12; val_offset:4626*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 4626*FLEN/8, x13, x9, x10)

inst_1564:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x0b5d1b and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x17 and fm3 == 0x7ffc00 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f0b5d1b; op2val:0x0;
op3val:0xbfffc00; valaddr_reg:x12; val_offset:4629*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 4629*FLEN/8, x13, x9, x10)

inst_1565:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x0b5d1b and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x17 and fm3 == 0x0003ff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f0b5d1b; op2val:0x0;
op3val:0xb8003ff; valaddr_reg:x12; val_offset:4632*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 4632*FLEN/8, x13, x9, x10)

inst_1566:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x0b5d1b and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x17 and fm3 == 0x7ffe00 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f0b5d1b; op2val:0x0;
op3val:0xbfffe00; valaddr_reg:x12; val_offset:4635*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 4635*FLEN/8, x13, x9, x10)

inst_1567:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x0b5d1b and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x17 and fm3 == 0x0001ff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f0b5d1b; op2val:0x0;
op3val:0xb8001ff; valaddr_reg:x12; val_offset:4638*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 4638*FLEN/8, x13, x9, x10)

inst_1568:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x0b5d1b and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x17 and fm3 == 0x7fff00 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f0b5d1b; op2val:0x0;
op3val:0xbffff00; valaddr_reg:x12; val_offset:4641*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 4641*FLEN/8, x13, x9, x10)

inst_1569:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x0b5d1b and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x17 and fm3 == 0x0000ff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f0b5d1b; op2val:0x0;
op3val:0xb8000ff; valaddr_reg:x12; val_offset:4644*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 4644*FLEN/8, x13, x9, x10)

inst_1570:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x0b5d1b and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x17 and fm3 == 0x7fff80 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f0b5d1b; op2val:0x0;
op3val:0xbffff80; valaddr_reg:x12; val_offset:4647*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 4647*FLEN/8, x13, x9, x10)

inst_1571:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x0b5d1b and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x17 and fm3 == 0x00007f and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f0b5d1b; op2val:0x0;
op3val:0xb80007f; valaddr_reg:x12; val_offset:4650*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 4650*FLEN/8, x13, x9, x10)

inst_1572:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x0b5d1b and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x17 and fm3 == 0x7fffc0 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f0b5d1b; op2val:0x0;
op3val:0xbffffc0; valaddr_reg:x12; val_offset:4653*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 4653*FLEN/8, x13, x9, x10)

inst_1573:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x0b5d1b and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x17 and fm3 == 0x00003f and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f0b5d1b; op2val:0x0;
op3val:0xb80003f; valaddr_reg:x12; val_offset:4656*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 4656*FLEN/8, x13, x9, x10)

inst_1574:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x0b5d1b and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x17 and fm3 == 0x7fffe0 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f0b5d1b; op2val:0x0;
op3val:0xbffffe0; valaddr_reg:x12; val_offset:4659*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 4659*FLEN/8, x13, x9, x10)

inst_1575:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x0b5d1b and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x17 and fm3 == 0x00001f and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f0b5d1b; op2val:0x0;
op3val:0xb80001f; valaddr_reg:x12; val_offset:4662*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 4662*FLEN/8, x13, x9, x10)

inst_1576:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x0b5d1b and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x17 and fm3 == 0x7ffff0 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f0b5d1b; op2val:0x0;
op3val:0xbfffff0; valaddr_reg:x12; val_offset:4665*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 4665*FLEN/8, x13, x9, x10)

inst_1577:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x0b5d1b and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x17 and fm3 == 0x00000f and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f0b5d1b; op2val:0x0;
op3val:0xb80000f; valaddr_reg:x12; val_offset:4668*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 4668*FLEN/8, x13, x9, x10)

inst_1578:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x0b5d1b and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x17 and fm3 == 0x7ffff8 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f0b5d1b; op2val:0x0;
op3val:0xbfffff8; valaddr_reg:x12; val_offset:4671*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 4671*FLEN/8, x13, x9, x10)

inst_1579:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x0b5d1b and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x17 and fm3 == 0x000007 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f0b5d1b; op2val:0x0;
op3val:0xb800007; valaddr_reg:x12; val_offset:4674*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 4674*FLEN/8, x13, x9, x10)

inst_1580:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x0b5d1b and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x17 and fm3 == 0x7ffffc and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f0b5d1b; op2val:0x0;
op3val:0xbfffffc; valaddr_reg:x12; val_offset:4677*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 4677*FLEN/8, x13, x9, x10)

inst_1581:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x0b5d1b and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x17 and fm3 == 0x000003 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f0b5d1b; op2val:0x0;
op3val:0xb800003; valaddr_reg:x12; val_offset:4680*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 4680*FLEN/8, x13, x9, x10)

inst_1582:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x0b5d1b and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x17 and fm3 == 0x7ffffe and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f0b5d1b; op2val:0x0;
op3val:0xbfffffe; valaddr_reg:x12; val_offset:4683*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 4683*FLEN/8, x13, x9, x10)

inst_1583:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x0b5d1b and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x17 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f0b5d1b; op2val:0x0;
op3val:0xb800001; valaddr_reg:x12; val_offset:4686*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 4686*FLEN/8, x13, x9, x10)

inst_1584:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x0b5d1b and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x7ffff8 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f0b5d1b; op2val:0x0;
op3val:0x7ffff8; valaddr_reg:x12; val_offset:4689*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 4689*FLEN/8, x13, x9, x10)

inst_1585:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x0b5d1b and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000007 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f0b5d1b; op2val:0x0;
op3val:0x7; valaddr_reg:x12; val_offset:4692*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 4692*FLEN/8, x13, x9, x10)

inst_1586:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x0b5d1b and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x7ffffc and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f0b5d1b; op2val:0x0;
op3val:0x7ffffc; valaddr_reg:x12; val_offset:4695*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 4695*FLEN/8, x13, x9, x10)

inst_1587:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x0b5d1b and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000003 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f0b5d1b; op2val:0x0;
op3val:0x3; valaddr_reg:x12; val_offset:4698*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 4698*FLEN/8, x13, x9, x10)

inst_1588:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x0b5d1b and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x7ffffe and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f0b5d1b; op2val:0x0;
op3val:0x7ffffe; valaddr_reg:x12; val_offset:4701*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 4701*FLEN/8, x13, x9, x10)

inst_1589:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x0b5d1b and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f0b5d1b; op2val:0x0;
op3val:0x1; valaddr_reg:x12; val_offset:4704*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 4704*FLEN/8, x13, x9, x10)

inst_1590:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x0b5d1b and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x36db6d and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f0b5d1b; op2val:0x0;
op3val:0x36db6d; valaddr_reg:x12; val_offset:4707*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 4707*FLEN/8, x13, x9, x10)

inst_1591:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x0b5d1b and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x6db6db and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f0b5d1b; op2val:0x0;
op3val:0x6db6db; valaddr_reg:x12; val_offset:4710*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 4710*FLEN/8, x13, x9, x10)

inst_1592:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x0b5d1b and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x199999 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f0b5d1b; op2val:0x0;
op3val:0x199999; valaddr_reg:x12; val_offset:4713*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 4713*FLEN/8, x13, x9, x10)

inst_1593:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x0b5d1b and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x666666 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f0b5d1b; op2val:0x0;
op3val:0x666666; valaddr_reg:x12; val_offset:4716*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 4716*FLEN/8, x13, x9, x10)

inst_1594:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x0b5d1b and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x3bbbbb and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f0b5d1b; op2val:0x0;
op3val:0x3bbbbb; valaddr_reg:x12; val_offset:4719*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 4719*FLEN/8, x13, x9, x10)

inst_1595:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x0b5d1b and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x444444 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f0b5d1b; op2val:0x0;
op3val:0x444444; valaddr_reg:x12; val_offset:4722*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 4722*FLEN/8, x13, x9, x10)

inst_1596:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x0b5d1b and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x249249 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f0b5d1b; op2val:0x0;
op3val:0x249249; valaddr_reg:x12; val_offset:4725*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 4725*FLEN/8, x13, x9, x10)

inst_1597:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x0b5d1b and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x5b6db6 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f0b5d1b; op2val:0x0;
op3val:0x5b6db6; valaddr_reg:x12; val_offset:4728*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 4728*FLEN/8, x13, x9, x10)

inst_1598:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x0b5d1b and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x333333 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f0b5d1b; op2val:0x0;
op3val:0x333333; valaddr_reg:x12; val_offset:4731*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 4731*FLEN/8, x13, x9, x10)

inst_1599:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x0b5d1b and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x4ccccc and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f0b5d1b; op2val:0x0;
op3val:0x4ccccc; valaddr_reg:x12; val_offset:4734*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 4734*FLEN/8, x13, x9, x10)

inst_1600:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x4a9c14 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x18 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7eca9c14; op2val:0x0;
op3val:0xc000000; valaddr_reg:x12; val_offset:4737*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 4737*FLEN/8, x13, x9, x10)

inst_1601:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x4a9c14 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x18 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7eca9c14; op2val:0x0;
op3val:0xc7fffff; valaddr_reg:x12; val_offset:4740*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 4740*FLEN/8, x13, x9, x10)

inst_1602:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x4a9c14 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x18 and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7eca9c14; op2val:0x0;
op3val:0xc400000; valaddr_reg:x12; val_offset:4743*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 4743*FLEN/8, x13, x9, x10)

inst_1603:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x4a9c14 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x18 and fm3 == 0x3fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7eca9c14; op2val:0x0;
op3val:0xc3fffff; valaddr_reg:x12; val_offset:4746*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 4746*FLEN/8, x13, x9, x10)

inst_1604:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x4a9c14 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x18 and fm3 == 0x600000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7eca9c14; op2val:0x0;
op3val:0xc600000; valaddr_reg:x12; val_offset:4749*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 4749*FLEN/8, x13, x9, x10)

inst_1605:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x4a9c14 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x18 and fm3 == 0x1fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7eca9c14; op2val:0x0;
op3val:0xc1fffff; valaddr_reg:x12; val_offset:4752*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 4752*FLEN/8, x13, x9, x10)

inst_1606:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x4a9c14 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x18 and fm3 == 0x700000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7eca9c14; op2val:0x0;
op3val:0xc700000; valaddr_reg:x12; val_offset:4755*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 4755*FLEN/8, x13, x9, x10)

inst_1607:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x4a9c14 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x18 and fm3 == 0x0fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7eca9c14; op2val:0x0;
op3val:0xc0fffff; valaddr_reg:x12; val_offset:4758*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 4758*FLEN/8, x13, x9, x10)

inst_1608:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x4a9c14 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x18 and fm3 == 0x780000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7eca9c14; op2val:0x0;
op3val:0xc780000; valaddr_reg:x12; val_offset:4761*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 4761*FLEN/8, x13, x9, x10)

inst_1609:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x4a9c14 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x18 and fm3 == 0x07ffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7eca9c14; op2val:0x0;
op3val:0xc07ffff; valaddr_reg:x12; val_offset:4764*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 4764*FLEN/8, x13, x9, x10)

inst_1610:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x4a9c14 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x18 and fm3 == 0x7c0000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7eca9c14; op2val:0x0;
op3val:0xc7c0000; valaddr_reg:x12; val_offset:4767*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 4767*FLEN/8, x13, x9, x10)

inst_1611:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x4a9c14 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x18 and fm3 == 0x03ffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7eca9c14; op2val:0x0;
op3val:0xc03ffff; valaddr_reg:x12; val_offset:4770*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 4770*FLEN/8, x13, x9, x10)

inst_1612:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x4a9c14 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x18 and fm3 == 0x7e0000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7eca9c14; op2val:0x0;
op3val:0xc7e0000; valaddr_reg:x12; val_offset:4773*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 4773*FLEN/8, x13, x9, x10)

inst_1613:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x4a9c14 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x18 and fm3 == 0x01ffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7eca9c14; op2val:0x0;
op3val:0xc01ffff; valaddr_reg:x12; val_offset:4776*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 4776*FLEN/8, x13, x9, x10)

inst_1614:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x4a9c14 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x18 and fm3 == 0x7f0000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7eca9c14; op2val:0x0;
op3val:0xc7f0000; valaddr_reg:x12; val_offset:4779*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 4779*FLEN/8, x13, x9, x10)

inst_1615:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x4a9c14 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x18 and fm3 == 0x00ffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7eca9c14; op2val:0x0;
op3val:0xc00ffff; valaddr_reg:x12; val_offset:4782*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 4782*FLEN/8, x13, x9, x10)

inst_1616:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x4a9c14 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x18 and fm3 == 0x7f8000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7eca9c14; op2val:0x0;
op3val:0xc7f8000; valaddr_reg:x12; val_offset:4785*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 4785*FLEN/8, x13, x9, x10)

inst_1617:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x4a9c14 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x18 and fm3 == 0x007fff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7eca9c14; op2val:0x0;
op3val:0xc007fff; valaddr_reg:x12; val_offset:4788*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 4788*FLEN/8, x13, x9, x10)

inst_1618:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x4a9c14 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x18 and fm3 == 0x7fc000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7eca9c14; op2val:0x0;
op3val:0xc7fc000; valaddr_reg:x12; val_offset:4791*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 4791*FLEN/8, x13, x9, x10)

inst_1619:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x4a9c14 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x18 and fm3 == 0x003fff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7eca9c14; op2val:0x0;
op3val:0xc003fff; valaddr_reg:x12; val_offset:4794*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 4794*FLEN/8, x13, x9, x10)

inst_1620:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x4a9c14 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x18 and fm3 == 0x7fe000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7eca9c14; op2val:0x0;
op3val:0xc7fe000; valaddr_reg:x12; val_offset:4797*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 4797*FLEN/8, x13, x9, x10)

inst_1621:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x4a9c14 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x18 and fm3 == 0x001fff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7eca9c14; op2val:0x0;
op3val:0xc001fff; valaddr_reg:x12; val_offset:4800*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 4800*FLEN/8, x13, x9, x10)

inst_1622:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x4a9c14 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x18 and fm3 == 0x7ff000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7eca9c14; op2val:0x0;
op3val:0xc7ff000; valaddr_reg:x12; val_offset:4803*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 4803*FLEN/8, x13, x9, x10)

inst_1623:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x4a9c14 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x18 and fm3 == 0x000fff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7eca9c14; op2val:0x0;
op3val:0xc000fff; valaddr_reg:x12; val_offset:4806*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 4806*FLEN/8, x13, x9, x10)

inst_1624:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x4a9c14 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x18 and fm3 == 0x7ff800 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7eca9c14; op2val:0x0;
op3val:0xc7ff800; valaddr_reg:x12; val_offset:4809*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 4809*FLEN/8, x13, x9, x10)

inst_1625:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x4a9c14 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x18 and fm3 == 0x0007ff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7eca9c14; op2val:0x0;
op3val:0xc0007ff; valaddr_reg:x12; val_offset:4812*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 4812*FLEN/8, x13, x9, x10)

inst_1626:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x4a9c14 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x18 and fm3 == 0x7ffc00 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7eca9c14; op2val:0x0;
op3val:0xc7ffc00; valaddr_reg:x12; val_offset:4815*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 4815*FLEN/8, x13, x9, x10)

inst_1627:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x4a9c14 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x18 and fm3 == 0x0003ff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7eca9c14; op2val:0x0;
op3val:0xc0003ff; valaddr_reg:x12; val_offset:4818*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 4818*FLEN/8, x13, x9, x10)

inst_1628:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x4a9c14 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x18 and fm3 == 0x7ffe00 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7eca9c14; op2val:0x0;
op3val:0xc7ffe00; valaddr_reg:x12; val_offset:4821*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 4821*FLEN/8, x13, x9, x10)

inst_1629:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x4a9c14 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x18 and fm3 == 0x0001ff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7eca9c14; op2val:0x0;
op3val:0xc0001ff; valaddr_reg:x12; val_offset:4824*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 4824*FLEN/8, x13, x9, x10)

inst_1630:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x4a9c14 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x18 and fm3 == 0x7fff00 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7eca9c14; op2val:0x0;
op3val:0xc7fff00; valaddr_reg:x12; val_offset:4827*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 4827*FLEN/8, x13, x9, x10)

inst_1631:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x4a9c14 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x18 and fm3 == 0x0000ff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7eca9c14; op2val:0x0;
op3val:0xc0000ff; valaddr_reg:x12; val_offset:4830*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 4830*FLEN/8, x13, x9, x10)

inst_1632:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x4a9c14 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x18 and fm3 == 0x7fff80 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7eca9c14; op2val:0x0;
op3val:0xc7fff80; valaddr_reg:x12; val_offset:4833*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 4833*FLEN/8, x13, x9, x10)

inst_1633:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x4a9c14 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x18 and fm3 == 0x00007f and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7eca9c14; op2val:0x0;
op3val:0xc00007f; valaddr_reg:x12; val_offset:4836*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 4836*FLEN/8, x13, x9, x10)

inst_1634:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x4a9c14 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x18 and fm3 == 0x7fffc0 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7eca9c14; op2val:0x0;
op3val:0xc7fffc0; valaddr_reg:x12; val_offset:4839*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 4839*FLEN/8, x13, x9, x10)

inst_1635:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x4a9c14 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x18 and fm3 == 0x00003f and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7eca9c14; op2val:0x0;
op3val:0xc00003f; valaddr_reg:x12; val_offset:4842*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 4842*FLEN/8, x13, x9, x10)

inst_1636:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x4a9c14 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x18 and fm3 == 0x7fffe0 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7eca9c14; op2val:0x0;
op3val:0xc7fffe0; valaddr_reg:x12; val_offset:4845*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 4845*FLEN/8, x13, x9, x10)

inst_1637:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x4a9c14 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x18 and fm3 == 0x00001f and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7eca9c14; op2val:0x0;
op3val:0xc00001f; valaddr_reg:x12; val_offset:4848*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 4848*FLEN/8, x13, x9, x10)

inst_1638:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x4a9c14 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x18 and fm3 == 0x7ffff0 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7eca9c14; op2val:0x0;
op3val:0xc7ffff0; valaddr_reg:x12; val_offset:4851*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 4851*FLEN/8, x13, x9, x10)

inst_1639:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x4a9c14 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x18 and fm3 == 0x00000f and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7eca9c14; op2val:0x0;
op3val:0xc00000f; valaddr_reg:x12; val_offset:4854*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 4854*FLEN/8, x13, x9, x10)

inst_1640:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x4a9c14 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x18 and fm3 == 0x7ffff8 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7eca9c14; op2val:0x0;
op3val:0xc7ffff8; valaddr_reg:x12; val_offset:4857*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 4857*FLEN/8, x13, x9, x10)

inst_1641:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x4a9c14 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x18 and fm3 == 0x000007 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7eca9c14; op2val:0x0;
op3val:0xc000007; valaddr_reg:x12; val_offset:4860*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 4860*FLEN/8, x13, x9, x10)

inst_1642:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x4a9c14 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x18 and fm3 == 0x7ffffc and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7eca9c14; op2val:0x0;
op3val:0xc7ffffc; valaddr_reg:x12; val_offset:4863*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 4863*FLEN/8, x13, x9, x10)

inst_1643:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x4a9c14 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x18 and fm3 == 0x000003 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7eca9c14; op2val:0x0;
op3val:0xc000003; valaddr_reg:x12; val_offset:4866*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 4866*FLEN/8, x13, x9, x10)

inst_1644:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x4a9c14 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x18 and fm3 == 0x7ffffe and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7eca9c14; op2val:0x0;
op3val:0xc7ffffe; valaddr_reg:x12; val_offset:4869*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 4869*FLEN/8, x13, x9, x10)

inst_1645:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x4a9c14 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x18 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7eca9c14; op2val:0x0;
op3val:0xc000001; valaddr_reg:x12; val_offset:4872*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 4872*FLEN/8, x13, x9, x10)

inst_1646:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x4a9c14 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x7ffff8 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7eca9c14; op2val:0x0;
op3val:0x7ffff8; valaddr_reg:x12; val_offset:4875*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 4875*FLEN/8, x13, x9, x10)

inst_1647:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x4a9c14 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000007 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7eca9c14; op2val:0x0;
op3val:0x7; valaddr_reg:x12; val_offset:4878*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 4878*FLEN/8, x13, x9, x10)

inst_1648:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x4a9c14 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x7ffffc and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7eca9c14; op2val:0x0;
op3val:0x7ffffc; valaddr_reg:x12; val_offset:4881*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 4881*FLEN/8, x13, x9, x10)

inst_1649:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x4a9c14 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000003 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7eca9c14; op2val:0x0;
op3val:0x3; valaddr_reg:x12; val_offset:4884*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 4884*FLEN/8, x13, x9, x10)

inst_1650:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x4a9c14 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x7ffffe and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7eca9c14; op2val:0x0;
op3val:0x7ffffe; valaddr_reg:x12; val_offset:4887*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 4887*FLEN/8, x13, x9, x10)

inst_1651:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x4a9c14 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7eca9c14; op2val:0x0;
op3val:0x1; valaddr_reg:x12; val_offset:4890*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 4890*FLEN/8, x13, x9, x10)

inst_1652:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x4a9c14 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x36db6d and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7eca9c14; op2val:0x0;
op3val:0x36db6d; valaddr_reg:x12; val_offset:4893*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 4893*FLEN/8, x13, x9, x10)

inst_1653:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x4a9c14 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x6db6db and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7eca9c14; op2val:0x0;
op3val:0x6db6db; valaddr_reg:x12; val_offset:4896*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 4896*FLEN/8, x13, x9, x10)

inst_1654:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x4a9c14 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x199999 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7eca9c14; op2val:0x0;
op3val:0x199999; valaddr_reg:x12; val_offset:4899*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 4899*FLEN/8, x13, x9, x10)

inst_1655:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x4a9c14 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x666666 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7eca9c14; op2val:0x0;
op3val:0x666666; valaddr_reg:x12; val_offset:4902*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 4902*FLEN/8, x13, x9, x10)

inst_1656:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x4a9c14 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x3bbbbb and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7eca9c14; op2val:0x0;
op3val:0x3bbbbb; valaddr_reg:x12; val_offset:4905*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 4905*FLEN/8, x13, x9, x10)

inst_1657:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x4a9c14 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x444444 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7eca9c14; op2val:0x0;
op3val:0x444444; valaddr_reg:x12; val_offset:4908*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 4908*FLEN/8, x13, x9, x10)

inst_1658:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x4a9c14 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x249249 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7eca9c14; op2val:0x0;
op3val:0x249249; valaddr_reg:x12; val_offset:4911*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 4911*FLEN/8, x13, x9, x10)

inst_1659:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x4a9c14 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x5b6db6 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7eca9c14; op2val:0x0;
op3val:0x5b6db6; valaddr_reg:x12; val_offset:4914*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 4914*FLEN/8, x13, x9, x10)

inst_1660:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x4a9c14 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x333333 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7eca9c14; op2val:0x0;
op3val:0x333333; valaddr_reg:x12; val_offset:4917*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 4917*FLEN/8, x13, x9, x10)

inst_1661:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x4a9c14 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x4ccccc and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7eca9c14; op2val:0x0;
op3val:0x4ccccc; valaddr_reg:x12; val_offset:4920*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 4920*FLEN/8, x13, x9, x10)

inst_1662:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x12a16e and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x19 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f12a16e; op2val:0x0;
op3val:0xc800000; valaddr_reg:x12; val_offset:4923*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 4923*FLEN/8, x13, x9, x10)

inst_1663:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x12a16e and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x19 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f12a16e; op2val:0x0;
op3val:0xcffffff; valaddr_reg:x12; val_offset:4926*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 4926*FLEN/8, x13, x9, x10)

inst_1664:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x12a16e and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x19 and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f12a16e; op2val:0x0;
op3val:0xcc00000; valaddr_reg:x12; val_offset:4929*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 4929*FLEN/8, x13, x9, x10)

inst_1665:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x12a16e and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x19 and fm3 == 0x3fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f12a16e; op2val:0x0;
op3val:0xcbfffff; valaddr_reg:x12; val_offset:4932*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 4932*FLEN/8, x13, x9, x10)

inst_1666:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x12a16e and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x19 and fm3 == 0x600000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f12a16e; op2val:0x0;
op3val:0xce00000; valaddr_reg:x12; val_offset:4935*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 4935*FLEN/8, x13, x9, x10)

inst_1667:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x12a16e and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x19 and fm3 == 0x1fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f12a16e; op2val:0x0;
op3val:0xc9fffff; valaddr_reg:x12; val_offset:4938*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 4938*FLEN/8, x13, x9, x10)

inst_1668:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x12a16e and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x19 and fm3 == 0x700000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f12a16e; op2val:0x0;
op3val:0xcf00000; valaddr_reg:x12; val_offset:4941*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 4941*FLEN/8, x13, x9, x10)

inst_1669:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x12a16e and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x19 and fm3 == 0x0fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f12a16e; op2val:0x0;
op3val:0xc8fffff; valaddr_reg:x12; val_offset:4944*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 4944*FLEN/8, x13, x9, x10)

inst_1670:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x12a16e and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x19 and fm3 == 0x780000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f12a16e; op2val:0x0;
op3val:0xcf80000; valaddr_reg:x12; val_offset:4947*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 4947*FLEN/8, x13, x9, x10)

inst_1671:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x12a16e and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x19 and fm3 == 0x07ffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f12a16e; op2val:0x0;
op3val:0xc87ffff; valaddr_reg:x12; val_offset:4950*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 4950*FLEN/8, x13, x9, x10)

inst_1672:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x12a16e and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x19 and fm3 == 0x7c0000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f12a16e; op2val:0x0;
op3val:0xcfc0000; valaddr_reg:x12; val_offset:4953*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 4953*FLEN/8, x13, x9, x10)

inst_1673:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x12a16e and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x19 and fm3 == 0x03ffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f12a16e; op2val:0x0;
op3val:0xc83ffff; valaddr_reg:x12; val_offset:4956*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 4956*FLEN/8, x13, x9, x10)

inst_1674:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x12a16e and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x19 and fm3 == 0x7e0000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f12a16e; op2val:0x0;
op3val:0xcfe0000; valaddr_reg:x12; val_offset:4959*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 4959*FLEN/8, x13, x9, x10)

inst_1675:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x12a16e and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x19 and fm3 == 0x01ffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f12a16e; op2val:0x0;
op3val:0xc81ffff; valaddr_reg:x12; val_offset:4962*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 4962*FLEN/8, x13, x9, x10)

inst_1676:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x12a16e and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x19 and fm3 == 0x7f0000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f12a16e; op2val:0x0;
op3val:0xcff0000; valaddr_reg:x12; val_offset:4965*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 4965*FLEN/8, x13, x9, x10)

inst_1677:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x12a16e and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x19 and fm3 == 0x00ffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f12a16e; op2val:0x0;
op3val:0xc80ffff; valaddr_reg:x12; val_offset:4968*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 4968*FLEN/8, x13, x9, x10)

inst_1678:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x12a16e and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x19 and fm3 == 0x7f8000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f12a16e; op2val:0x0;
op3val:0xcff8000; valaddr_reg:x12; val_offset:4971*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 4971*FLEN/8, x13, x9, x10)

inst_1679:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x12a16e and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x19 and fm3 == 0x007fff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f12a16e; op2val:0x0;
op3val:0xc807fff; valaddr_reg:x12; val_offset:4974*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 4974*FLEN/8, x13, x9, x10)

inst_1680:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x12a16e and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x19 and fm3 == 0x7fc000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f12a16e; op2val:0x0;
op3val:0xcffc000; valaddr_reg:x12; val_offset:4977*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 4977*FLEN/8, x13, x9, x10)

inst_1681:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x12a16e and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x19 and fm3 == 0x003fff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f12a16e; op2val:0x0;
op3val:0xc803fff; valaddr_reg:x12; val_offset:4980*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 4980*FLEN/8, x13, x9, x10)

inst_1682:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x12a16e and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x19 and fm3 == 0x7fe000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f12a16e; op2val:0x0;
op3val:0xcffe000; valaddr_reg:x12; val_offset:4983*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 4983*FLEN/8, x13, x9, x10)

inst_1683:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x12a16e and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x19 and fm3 == 0x001fff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f12a16e; op2val:0x0;
op3val:0xc801fff; valaddr_reg:x12; val_offset:4986*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 4986*FLEN/8, x13, x9, x10)

inst_1684:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x12a16e and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x19 and fm3 == 0x7ff000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f12a16e; op2val:0x0;
op3val:0xcfff000; valaddr_reg:x12; val_offset:4989*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 4989*FLEN/8, x13, x9, x10)

inst_1685:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x12a16e and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x19 and fm3 == 0x000fff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f12a16e; op2val:0x0;
op3val:0xc800fff; valaddr_reg:x12; val_offset:4992*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 4992*FLEN/8, x13, x9, x10)

inst_1686:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x12a16e and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x19 and fm3 == 0x7ff800 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f12a16e; op2val:0x0;
op3val:0xcfff800; valaddr_reg:x12; val_offset:4995*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 4995*FLEN/8, x13, x9, x10)

inst_1687:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x12a16e and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x19 and fm3 == 0x0007ff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f12a16e; op2val:0x0;
op3val:0xc8007ff; valaddr_reg:x12; val_offset:4998*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 4998*FLEN/8, x13, x9, x10)

RVTEST_SIGBASE(x9,signature_x9_13)
inst_1688:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x12a16e and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x19 and fm3 == 0x7ffc00 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f12a16e; op2val:0x0;
op3val:0xcfffc00; valaddr_reg:x12; val_offset:5001*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 5001*FLEN/8, x13, x9, x10)

inst_1689:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x12a16e and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x19 and fm3 == 0x0003ff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f12a16e; op2val:0x0;
op3val:0xc8003ff; valaddr_reg:x12; val_offset:5004*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 5004*FLEN/8, x13, x9, x10)

inst_1690:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x12a16e and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x19 and fm3 == 0x7ffe00 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f12a16e; op2val:0x0;
op3val:0xcfffe00; valaddr_reg:x12; val_offset:5007*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 5007*FLEN/8, x13, x9, x10)

inst_1691:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x12a16e and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x19 and fm3 == 0x0001ff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f12a16e; op2val:0x0;
op3val:0xc8001ff; valaddr_reg:x12; val_offset:5010*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 5010*FLEN/8, x13, x9, x10)

inst_1692:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x12a16e and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x19 and fm3 == 0x7fff00 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f12a16e; op2val:0x0;
op3val:0xcffff00; valaddr_reg:x12; val_offset:5013*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 5013*FLEN/8, x13, x9, x10)

inst_1693:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x12a16e and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x19 and fm3 == 0x0000ff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f12a16e; op2val:0x0;
op3val:0xc8000ff; valaddr_reg:x12; val_offset:5016*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 5016*FLEN/8, x13, x9, x10)

inst_1694:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x12a16e and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x19 and fm3 == 0x7fff80 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f12a16e; op2val:0x0;
op3val:0xcffff80; valaddr_reg:x12; val_offset:5019*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 5019*FLEN/8, x13, x9, x10)

inst_1695:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x12a16e and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x19 and fm3 == 0x00007f and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f12a16e; op2val:0x0;
op3val:0xc80007f; valaddr_reg:x12; val_offset:5022*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 5022*FLEN/8, x13, x9, x10)

inst_1696:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x12a16e and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x19 and fm3 == 0x7fffc0 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f12a16e; op2val:0x0;
op3val:0xcffffc0; valaddr_reg:x12; val_offset:5025*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 5025*FLEN/8, x13, x9, x10)

inst_1697:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x12a16e and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x19 and fm3 == 0x00003f and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f12a16e; op2val:0x0;
op3val:0xc80003f; valaddr_reg:x12; val_offset:5028*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 5028*FLEN/8, x13, x9, x10)

inst_1698:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x12a16e and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x19 and fm3 == 0x7fffe0 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f12a16e; op2val:0x0;
op3val:0xcffffe0; valaddr_reg:x12; val_offset:5031*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 5031*FLEN/8, x13, x9, x10)

inst_1699:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x12a16e and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x19 and fm3 == 0x00001f and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f12a16e; op2val:0x0;
op3val:0xc80001f; valaddr_reg:x12; val_offset:5034*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 5034*FLEN/8, x13, x9, x10)

inst_1700:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x12a16e and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x19 and fm3 == 0x7ffff0 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f12a16e; op2val:0x0;
op3val:0xcfffff0; valaddr_reg:x12; val_offset:5037*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 5037*FLEN/8, x13, x9, x10)

inst_1701:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x12a16e and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x19 and fm3 == 0x00000f and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f12a16e; op2val:0x0;
op3val:0xc80000f; valaddr_reg:x12; val_offset:5040*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 5040*FLEN/8, x13, x9, x10)

inst_1702:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x12a16e and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x19 and fm3 == 0x7ffff8 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f12a16e; op2val:0x0;
op3val:0xcfffff8; valaddr_reg:x12; val_offset:5043*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 5043*FLEN/8, x13, x9, x10)

inst_1703:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x12a16e and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x19 and fm3 == 0x000007 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f12a16e; op2val:0x0;
op3val:0xc800007; valaddr_reg:x12; val_offset:5046*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 5046*FLEN/8, x13, x9, x10)

inst_1704:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x12a16e and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x19 and fm3 == 0x7ffffc and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f12a16e; op2val:0x0;
op3val:0xcfffffc; valaddr_reg:x12; val_offset:5049*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 5049*FLEN/8, x13, x9, x10)

inst_1705:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x12a16e and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x19 and fm3 == 0x000003 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f12a16e; op2val:0x0;
op3val:0xc800003; valaddr_reg:x12; val_offset:5052*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 5052*FLEN/8, x13, x9, x10)

inst_1706:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x12a16e and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x19 and fm3 == 0x7ffffe and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f12a16e; op2val:0x0;
op3val:0xcfffffe; valaddr_reg:x12; val_offset:5055*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 5055*FLEN/8, x13, x9, x10)

inst_1707:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x12a16e and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x19 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f12a16e; op2val:0x0;
op3val:0xc800001; valaddr_reg:x12; val_offset:5058*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 5058*FLEN/8, x13, x9, x10)

inst_1708:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x12a16e and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x7ffff8 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f12a16e; op2val:0x0;
op3val:0x7ffff8; valaddr_reg:x12; val_offset:5061*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 5061*FLEN/8, x13, x9, x10)

inst_1709:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x12a16e and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000007 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f12a16e; op2val:0x0;
op3val:0x7; valaddr_reg:x12; val_offset:5064*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 5064*FLEN/8, x13, x9, x10)

inst_1710:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x12a16e and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x7ffffc and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f12a16e; op2val:0x0;
op3val:0x7ffffc; valaddr_reg:x12; val_offset:5067*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 5067*FLEN/8, x13, x9, x10)

inst_1711:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x12a16e and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000003 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f12a16e; op2val:0x0;
op3val:0x3; valaddr_reg:x12; val_offset:5070*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 5070*FLEN/8, x13, x9, x10)

inst_1712:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x12a16e and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x7ffffe and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f12a16e; op2val:0x0;
op3val:0x7ffffe; valaddr_reg:x12; val_offset:5073*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 5073*FLEN/8, x13, x9, x10)

inst_1713:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x12a16e and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f12a16e; op2val:0x0;
op3val:0x1; valaddr_reg:x12; val_offset:5076*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 5076*FLEN/8, x13, x9, x10)

inst_1714:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x12a16e and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x36db6d and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f12a16e; op2val:0x0;
op3val:0x36db6d; valaddr_reg:x12; val_offset:5079*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 5079*FLEN/8, x13, x9, x10)

inst_1715:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x12a16e and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x6db6db and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f12a16e; op2val:0x0;
op3val:0x6db6db; valaddr_reg:x12; val_offset:5082*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 5082*FLEN/8, x13, x9, x10)

inst_1716:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x12a16e and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x199999 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f12a16e; op2val:0x0;
op3val:0x199999; valaddr_reg:x12; val_offset:5085*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 5085*FLEN/8, x13, x9, x10)

inst_1717:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x12a16e and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x666666 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f12a16e; op2val:0x0;
op3val:0x666666; valaddr_reg:x12; val_offset:5088*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 5088*FLEN/8, x13, x9, x10)

inst_1718:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x12a16e and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x3bbbbb and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f12a16e; op2val:0x0;
op3val:0x3bbbbb; valaddr_reg:x12; val_offset:5091*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 5091*FLEN/8, x13, x9, x10)

inst_1719:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x12a16e and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x444444 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f12a16e; op2val:0x0;
op3val:0x444444; valaddr_reg:x12; val_offset:5094*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 5094*FLEN/8, x13, x9, x10)

inst_1720:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x12a16e and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x249249 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f12a16e; op2val:0x0;
op3val:0x249249; valaddr_reg:x12; val_offset:5097*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 5097*FLEN/8, x13, x9, x10)

inst_1721:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x12a16e and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x5b6db6 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f12a16e; op2val:0x0;
op3val:0x5b6db6; valaddr_reg:x12; val_offset:5100*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 5100*FLEN/8, x13, x9, x10)

inst_1722:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x12a16e and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x333333 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f12a16e; op2val:0x0;
op3val:0x333333; valaddr_reg:x12; val_offset:5103*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 5103*FLEN/8, x13, x9, x10)

inst_1723:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x12a16e and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x4ccccc and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f12a16e; op2val:0x0;
op3val:0x4ccccc; valaddr_reg:x12; val_offset:5106*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 5106*FLEN/8, x13, x9, x10)

inst_1724:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3451ef and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x1a and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f3451ef; op2val:0x0;
op3val:0xd000000; valaddr_reg:x12; val_offset:5109*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 5109*FLEN/8, x13, x9, x10)

inst_1725:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3451ef and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x1a and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f3451ef; op2val:0x0;
op3val:0xd7fffff; valaddr_reg:x12; val_offset:5112*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 5112*FLEN/8, x13, x9, x10)

inst_1726:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3451ef and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x1a and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f3451ef; op2val:0x0;
op3val:0xd400000; valaddr_reg:x12; val_offset:5115*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 5115*FLEN/8, x13, x9, x10)

inst_1727:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3451ef and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x1a and fm3 == 0x3fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f3451ef; op2val:0x0;
op3val:0xd3fffff; valaddr_reg:x12; val_offset:5118*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 5118*FLEN/8, x13, x9, x10)

inst_1728:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3451ef and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x1a and fm3 == 0x600000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f3451ef; op2val:0x0;
op3val:0xd600000; valaddr_reg:x12; val_offset:5121*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 5121*FLEN/8, x13, x9, x10)

inst_1729:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3451ef and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x1a and fm3 == 0x1fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f3451ef; op2val:0x0;
op3val:0xd1fffff; valaddr_reg:x12; val_offset:5124*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 5124*FLEN/8, x13, x9, x10)

inst_1730:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3451ef and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x1a and fm3 == 0x700000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f3451ef; op2val:0x0;
op3val:0xd700000; valaddr_reg:x12; val_offset:5127*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 5127*FLEN/8, x13, x9, x10)

inst_1731:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3451ef and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x1a and fm3 == 0x0fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f3451ef; op2val:0x0;
op3val:0xd0fffff; valaddr_reg:x12; val_offset:5130*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 5130*FLEN/8, x13, x9, x10)

inst_1732:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3451ef and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x1a and fm3 == 0x780000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f3451ef; op2val:0x0;
op3val:0xd780000; valaddr_reg:x12; val_offset:5133*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 5133*FLEN/8, x13, x9, x10)

inst_1733:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3451ef and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x1a and fm3 == 0x07ffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f3451ef; op2val:0x0;
op3val:0xd07ffff; valaddr_reg:x12; val_offset:5136*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 5136*FLEN/8, x13, x9, x10)

inst_1734:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3451ef and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x1a and fm3 == 0x7c0000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f3451ef; op2val:0x0;
op3val:0xd7c0000; valaddr_reg:x12; val_offset:5139*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 5139*FLEN/8, x13, x9, x10)

inst_1735:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3451ef and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x1a and fm3 == 0x03ffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f3451ef; op2val:0x0;
op3val:0xd03ffff; valaddr_reg:x12; val_offset:5142*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 5142*FLEN/8, x13, x9, x10)

inst_1736:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3451ef and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x1a and fm3 == 0x7e0000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f3451ef; op2val:0x0;
op3val:0xd7e0000; valaddr_reg:x12; val_offset:5145*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 5145*FLEN/8, x13, x9, x10)

inst_1737:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3451ef and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x1a and fm3 == 0x01ffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f3451ef; op2val:0x0;
op3val:0xd01ffff; valaddr_reg:x12; val_offset:5148*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 5148*FLEN/8, x13, x9, x10)

inst_1738:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3451ef and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x1a and fm3 == 0x7f0000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f3451ef; op2val:0x0;
op3val:0xd7f0000; valaddr_reg:x12; val_offset:5151*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 5151*FLEN/8, x13, x9, x10)

inst_1739:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3451ef and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x1a and fm3 == 0x00ffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f3451ef; op2val:0x0;
op3val:0xd00ffff; valaddr_reg:x12; val_offset:5154*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 5154*FLEN/8, x13, x9, x10)

inst_1740:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3451ef and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x1a and fm3 == 0x7f8000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f3451ef; op2val:0x0;
op3val:0xd7f8000; valaddr_reg:x12; val_offset:5157*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 5157*FLEN/8, x13, x9, x10)

inst_1741:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3451ef and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x1a and fm3 == 0x007fff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f3451ef; op2val:0x0;
op3val:0xd007fff; valaddr_reg:x12; val_offset:5160*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 5160*FLEN/8, x13, x9, x10)

inst_1742:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3451ef and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x1a and fm3 == 0x7fc000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f3451ef; op2val:0x0;
op3val:0xd7fc000; valaddr_reg:x12; val_offset:5163*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 5163*FLEN/8, x13, x9, x10)

inst_1743:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3451ef and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x1a and fm3 == 0x003fff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f3451ef; op2val:0x0;
op3val:0xd003fff; valaddr_reg:x12; val_offset:5166*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 5166*FLEN/8, x13, x9, x10)

inst_1744:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3451ef and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x1a and fm3 == 0x7fe000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f3451ef; op2val:0x0;
op3val:0xd7fe000; valaddr_reg:x12; val_offset:5169*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 5169*FLEN/8, x13, x9, x10)

inst_1745:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3451ef and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x1a and fm3 == 0x001fff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f3451ef; op2val:0x0;
op3val:0xd001fff; valaddr_reg:x12; val_offset:5172*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 5172*FLEN/8, x13, x9, x10)

inst_1746:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3451ef and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x1a and fm3 == 0x7ff000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f3451ef; op2val:0x0;
op3val:0xd7ff000; valaddr_reg:x12; val_offset:5175*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 5175*FLEN/8, x13, x9, x10)

inst_1747:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3451ef and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x1a and fm3 == 0x000fff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f3451ef; op2val:0x0;
op3val:0xd000fff; valaddr_reg:x12; val_offset:5178*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 5178*FLEN/8, x13, x9, x10)

inst_1748:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3451ef and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x1a and fm3 == 0x7ff800 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f3451ef; op2val:0x0;
op3val:0xd7ff800; valaddr_reg:x12; val_offset:5181*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 5181*FLEN/8, x13, x9, x10)

inst_1749:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3451ef and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x1a and fm3 == 0x0007ff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f3451ef; op2val:0x0;
op3val:0xd0007ff; valaddr_reg:x12; val_offset:5184*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 5184*FLEN/8, x13, x9, x10)

inst_1750:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3451ef and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x1a and fm3 == 0x7ffc00 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f3451ef; op2val:0x0;
op3val:0xd7ffc00; valaddr_reg:x12; val_offset:5187*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 5187*FLEN/8, x13, x9, x10)

inst_1751:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3451ef and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x1a and fm3 == 0x0003ff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f3451ef; op2val:0x0;
op3val:0xd0003ff; valaddr_reg:x12; val_offset:5190*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 5190*FLEN/8, x13, x9, x10)

inst_1752:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3451ef and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x1a and fm3 == 0x7ffe00 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f3451ef; op2val:0x0;
op3val:0xd7ffe00; valaddr_reg:x12; val_offset:5193*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 5193*FLEN/8, x13, x9, x10)

inst_1753:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3451ef and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x1a and fm3 == 0x0001ff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f3451ef; op2val:0x0;
op3val:0xd0001ff; valaddr_reg:x12; val_offset:5196*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 5196*FLEN/8, x13, x9, x10)

inst_1754:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3451ef and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x1a and fm3 == 0x7fff00 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f3451ef; op2val:0x0;
op3val:0xd7fff00; valaddr_reg:x12; val_offset:5199*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 5199*FLEN/8, x13, x9, x10)

inst_1755:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3451ef and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x1a and fm3 == 0x0000ff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f3451ef; op2val:0x0;
op3val:0xd0000ff; valaddr_reg:x12; val_offset:5202*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 5202*FLEN/8, x13, x9, x10)

inst_1756:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3451ef and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x1a and fm3 == 0x7fff80 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f3451ef; op2val:0x0;
op3val:0xd7fff80; valaddr_reg:x12; val_offset:5205*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 5205*FLEN/8, x13, x9, x10)

inst_1757:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3451ef and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x1a and fm3 == 0x00007f and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f3451ef; op2val:0x0;
op3val:0xd00007f; valaddr_reg:x12; val_offset:5208*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 5208*FLEN/8, x13, x9, x10)

inst_1758:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3451ef and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x1a and fm3 == 0x7fffc0 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f3451ef; op2val:0x0;
op3val:0xd7fffc0; valaddr_reg:x12; val_offset:5211*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 5211*FLEN/8, x13, x9, x10)

inst_1759:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3451ef and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x1a and fm3 == 0x00003f and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f3451ef; op2val:0x0;
op3val:0xd00003f; valaddr_reg:x12; val_offset:5214*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 5214*FLEN/8, x13, x9, x10)

inst_1760:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3451ef and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x1a and fm3 == 0x7fffe0 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f3451ef; op2val:0x0;
op3val:0xd7fffe0; valaddr_reg:x12; val_offset:5217*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 5217*FLEN/8, x13, x9, x10)

inst_1761:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3451ef and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x1a and fm3 == 0x00001f and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f3451ef; op2val:0x0;
op3val:0xd00001f; valaddr_reg:x12; val_offset:5220*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 5220*FLEN/8, x13, x9, x10)

inst_1762:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3451ef and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x1a and fm3 == 0x7ffff0 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f3451ef; op2val:0x0;
op3val:0xd7ffff0; valaddr_reg:x12; val_offset:5223*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 5223*FLEN/8, x13, x9, x10)

inst_1763:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3451ef and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x1a and fm3 == 0x00000f and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f3451ef; op2val:0x0;
op3val:0xd00000f; valaddr_reg:x12; val_offset:5226*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 5226*FLEN/8, x13, x9, x10)

inst_1764:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3451ef and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x1a and fm3 == 0x7ffff8 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f3451ef; op2val:0x0;
op3val:0xd7ffff8; valaddr_reg:x12; val_offset:5229*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 5229*FLEN/8, x13, x9, x10)

inst_1765:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3451ef and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x1a and fm3 == 0x000007 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f3451ef; op2val:0x0;
op3val:0xd000007; valaddr_reg:x12; val_offset:5232*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 5232*FLEN/8, x13, x9, x10)

inst_1766:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3451ef and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x1a and fm3 == 0x7ffffc and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f3451ef; op2val:0x0;
op3val:0xd7ffffc; valaddr_reg:x12; val_offset:5235*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 5235*FLEN/8, x13, x9, x10)

inst_1767:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3451ef and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x1a and fm3 == 0x000003 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f3451ef; op2val:0x0;
op3val:0xd000003; valaddr_reg:x12; val_offset:5238*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 5238*FLEN/8, x13, x9, x10)

inst_1768:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3451ef and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x1a and fm3 == 0x7ffffe and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f3451ef; op2val:0x0;
op3val:0xd7ffffe; valaddr_reg:x12; val_offset:5241*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 5241*FLEN/8, x13, x9, x10)

inst_1769:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3451ef and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x1a and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f3451ef; op2val:0x0;
op3val:0xd000001; valaddr_reg:x12; val_offset:5244*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 5244*FLEN/8, x13, x9, x10)

inst_1770:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3451ef and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x7ffff8 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f3451ef; op2val:0x0;
op3val:0x7ffff8; valaddr_reg:x12; val_offset:5247*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 5247*FLEN/8, x13, x9, x10)

inst_1771:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3451ef and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000007 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f3451ef; op2val:0x0;
op3val:0x7; valaddr_reg:x12; val_offset:5250*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 5250*FLEN/8, x13, x9, x10)

inst_1772:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3451ef and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x7ffffc and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f3451ef; op2val:0x0;
op3val:0x7ffffc; valaddr_reg:x12; val_offset:5253*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 5253*FLEN/8, x13, x9, x10)

inst_1773:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3451ef and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000003 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f3451ef; op2val:0x0;
op3val:0x3; valaddr_reg:x12; val_offset:5256*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 5256*FLEN/8, x13, x9, x10)

inst_1774:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3451ef and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x7ffffe and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f3451ef; op2val:0x0;
op3val:0x7ffffe; valaddr_reg:x12; val_offset:5259*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 5259*FLEN/8, x13, x9, x10)

inst_1775:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3451ef and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f3451ef; op2val:0x0;
op3val:0x1; valaddr_reg:x12; val_offset:5262*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 5262*FLEN/8, x13, x9, x10)

inst_1776:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3451ef and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x36db6d and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f3451ef; op2val:0x0;
op3val:0x36db6d; valaddr_reg:x12; val_offset:5265*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 5265*FLEN/8, x13, x9, x10)

inst_1777:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3451ef and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x6db6db and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f3451ef; op2val:0x0;
op3val:0x6db6db; valaddr_reg:x12; val_offset:5268*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 5268*FLEN/8, x13, x9, x10)

inst_1778:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3451ef and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x199999 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f3451ef; op2val:0x0;
op3val:0x199999; valaddr_reg:x12; val_offset:5271*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 5271*FLEN/8, x13, x9, x10)

inst_1779:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3451ef and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x666666 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f3451ef; op2val:0x0;
op3val:0x666666; valaddr_reg:x12; val_offset:5274*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 5274*FLEN/8, x13, x9, x10)

inst_1780:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3451ef and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x3bbbbb and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f3451ef; op2val:0x0;
op3val:0x3bbbbb; valaddr_reg:x12; val_offset:5277*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 5277*FLEN/8, x13, x9, x10)

inst_1781:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3451ef and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x444444 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f3451ef; op2val:0x0;
op3val:0x444444; valaddr_reg:x12; val_offset:5280*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 5280*FLEN/8, x13, x9, x10)

inst_1782:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3451ef and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x249249 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f3451ef; op2val:0x0;
op3val:0x249249; valaddr_reg:x12; val_offset:5283*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 5283*FLEN/8, x13, x9, x10)

inst_1783:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3451ef and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x5b6db6 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f3451ef; op2val:0x0;
op3val:0x5b6db6; valaddr_reg:x12; val_offset:5286*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 5286*FLEN/8, x13, x9, x10)

inst_1784:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3451ef and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x333333 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f3451ef; op2val:0x0;
op3val:0x333333; valaddr_reg:x12; val_offset:5289*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 5289*FLEN/8, x13, x9, x10)

inst_1785:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3451ef and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x4ccccc and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f3451ef; op2val:0x0;
op3val:0x4ccccc; valaddr_reg:x12; val_offset:5292*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 5292*FLEN/8, x13, x9, x10)

inst_1786:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x544c4e and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x1b and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7ed44c4e; op2val:0x0;
op3val:0xd800000; valaddr_reg:x12; val_offset:5295*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 5295*FLEN/8, x13, x9, x10)

inst_1787:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x544c4e and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x1b and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7ed44c4e; op2val:0x0;
op3val:0xdffffff; valaddr_reg:x12; val_offset:5298*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 5298*FLEN/8, x13, x9, x10)

inst_1788:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x544c4e and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x1b and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7ed44c4e; op2val:0x0;
op3val:0xdc00000; valaddr_reg:x12; val_offset:5301*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 5301*FLEN/8, x13, x9, x10)

inst_1789:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x544c4e and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x1b and fm3 == 0x3fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7ed44c4e; op2val:0x0;
op3val:0xdbfffff; valaddr_reg:x12; val_offset:5304*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 5304*FLEN/8, x13, x9, x10)

inst_1790:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x544c4e and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x1b and fm3 == 0x600000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7ed44c4e; op2val:0x0;
op3val:0xde00000; valaddr_reg:x12; val_offset:5307*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 5307*FLEN/8, x13, x9, x10)

inst_1791:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x544c4e and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x1b and fm3 == 0x1fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7ed44c4e; op2val:0x0;
op3val:0xd9fffff; valaddr_reg:x12; val_offset:5310*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 5310*FLEN/8, x13, x9, x10)

inst_1792:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x544c4e and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x1b and fm3 == 0x700000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7ed44c4e; op2val:0x0;
op3val:0xdf00000; valaddr_reg:x12; val_offset:5313*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 5313*FLEN/8, x13, x9, x10)

inst_1793:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x544c4e and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x1b and fm3 == 0x0fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7ed44c4e; op2val:0x0;
op3val:0xd8fffff; valaddr_reg:x12; val_offset:5316*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 5316*FLEN/8, x13, x9, x10)

inst_1794:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x544c4e and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x1b and fm3 == 0x780000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7ed44c4e; op2val:0x0;
op3val:0xdf80000; valaddr_reg:x12; val_offset:5319*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 5319*FLEN/8, x13, x9, x10)

inst_1795:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x544c4e and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x1b and fm3 == 0x07ffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7ed44c4e; op2val:0x0;
op3val:0xd87ffff; valaddr_reg:x12; val_offset:5322*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 5322*FLEN/8, x13, x9, x10)

inst_1796:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x544c4e and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x1b and fm3 == 0x7c0000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7ed44c4e; op2val:0x0;
op3val:0xdfc0000; valaddr_reg:x12; val_offset:5325*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 5325*FLEN/8, x13, x9, x10)

inst_1797:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x544c4e and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x1b and fm3 == 0x03ffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7ed44c4e; op2val:0x0;
op3val:0xd83ffff; valaddr_reg:x12; val_offset:5328*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 5328*FLEN/8, x13, x9, x10)

inst_1798:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x544c4e and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x1b and fm3 == 0x7e0000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7ed44c4e; op2val:0x0;
op3val:0xdfe0000; valaddr_reg:x12; val_offset:5331*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 5331*FLEN/8, x13, x9, x10)

inst_1799:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x544c4e and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x1b and fm3 == 0x01ffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7ed44c4e; op2val:0x0;
op3val:0xd81ffff; valaddr_reg:x12; val_offset:5334*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 5334*FLEN/8, x13, x9, x10)

inst_1800:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x544c4e and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x1b and fm3 == 0x7f0000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7ed44c4e; op2val:0x0;
op3val:0xdff0000; valaddr_reg:x12; val_offset:5337*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 5337*FLEN/8, x13, x9, x10)

inst_1801:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x544c4e and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x1b and fm3 == 0x00ffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7ed44c4e; op2val:0x0;
op3val:0xd80ffff; valaddr_reg:x12; val_offset:5340*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 5340*FLEN/8, x13, x9, x10)

inst_1802:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x544c4e and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x1b and fm3 == 0x7f8000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7ed44c4e; op2val:0x0;
op3val:0xdff8000; valaddr_reg:x12; val_offset:5343*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 5343*FLEN/8, x13, x9, x10)

inst_1803:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x544c4e and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x1b and fm3 == 0x007fff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7ed44c4e; op2val:0x0;
op3val:0xd807fff; valaddr_reg:x12; val_offset:5346*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 5346*FLEN/8, x13, x9, x10)

inst_1804:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x544c4e and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x1b and fm3 == 0x7fc000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7ed44c4e; op2val:0x0;
op3val:0xdffc000; valaddr_reg:x12; val_offset:5349*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 5349*FLEN/8, x13, x9, x10)

inst_1805:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x544c4e and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x1b and fm3 == 0x003fff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7ed44c4e; op2val:0x0;
op3val:0xd803fff; valaddr_reg:x12; val_offset:5352*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 5352*FLEN/8, x13, x9, x10)

inst_1806:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x544c4e and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x1b and fm3 == 0x7fe000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7ed44c4e; op2val:0x0;
op3val:0xdffe000; valaddr_reg:x12; val_offset:5355*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 5355*FLEN/8, x13, x9, x10)

inst_1807:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x544c4e and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x1b and fm3 == 0x001fff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7ed44c4e; op2val:0x0;
op3val:0xd801fff; valaddr_reg:x12; val_offset:5358*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 5358*FLEN/8, x13, x9, x10)

inst_1808:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x544c4e and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x1b and fm3 == 0x7ff000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7ed44c4e; op2val:0x0;
op3val:0xdfff000; valaddr_reg:x12; val_offset:5361*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 5361*FLEN/8, x13, x9, x10)

inst_1809:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x544c4e and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x1b and fm3 == 0x000fff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7ed44c4e; op2val:0x0;
op3val:0xd800fff; valaddr_reg:x12; val_offset:5364*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 5364*FLEN/8, x13, x9, x10)

inst_1810:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x544c4e and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x1b and fm3 == 0x7ff800 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7ed44c4e; op2val:0x0;
op3val:0xdfff800; valaddr_reg:x12; val_offset:5367*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 5367*FLEN/8, x13, x9, x10)

inst_1811:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x544c4e and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x1b and fm3 == 0x0007ff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7ed44c4e; op2val:0x0;
op3val:0xd8007ff; valaddr_reg:x12; val_offset:5370*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 5370*FLEN/8, x13, x9, x10)

inst_1812:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x544c4e and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x1b and fm3 == 0x7ffc00 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7ed44c4e; op2val:0x0;
op3val:0xdfffc00; valaddr_reg:x12; val_offset:5373*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 5373*FLEN/8, x13, x9, x10)

inst_1813:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x544c4e and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x1b and fm3 == 0x0003ff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7ed44c4e; op2val:0x0;
op3val:0xd8003ff; valaddr_reg:x12; val_offset:5376*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 5376*FLEN/8, x13, x9, x10)

inst_1814:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x544c4e and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x1b and fm3 == 0x7ffe00 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7ed44c4e; op2val:0x0;
op3val:0xdfffe00; valaddr_reg:x12; val_offset:5379*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 5379*FLEN/8, x13, x9, x10)

inst_1815:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x544c4e and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x1b and fm3 == 0x0001ff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7ed44c4e; op2val:0x0;
op3val:0xd8001ff; valaddr_reg:x12; val_offset:5382*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 5382*FLEN/8, x13, x9, x10)

RVTEST_SIGBASE(x9,signature_x9_14)
inst_1816:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x544c4e and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x1b and fm3 == 0x7fff00 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7ed44c4e; op2val:0x0;
op3val:0xdffff00; valaddr_reg:x12; val_offset:5385*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 5385*FLEN/8, x13, x9, x10)

inst_1817:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x544c4e and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x1b and fm3 == 0x0000ff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7ed44c4e; op2val:0x0;
op3val:0xd8000ff; valaddr_reg:x12; val_offset:5388*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 5388*FLEN/8, x13, x9, x10)

inst_1818:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x544c4e and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x1b and fm3 == 0x7fff80 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7ed44c4e; op2val:0x0;
op3val:0xdffff80; valaddr_reg:x12; val_offset:5391*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 5391*FLEN/8, x13, x9, x10)

inst_1819:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x544c4e and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x1b and fm3 == 0x00007f and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7ed44c4e; op2val:0x0;
op3val:0xd80007f; valaddr_reg:x12; val_offset:5394*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 5394*FLEN/8, x13, x9, x10)

inst_1820:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x544c4e and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x1b and fm3 == 0x7fffc0 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7ed44c4e; op2val:0x0;
op3val:0xdffffc0; valaddr_reg:x12; val_offset:5397*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 5397*FLEN/8, x13, x9, x10)

inst_1821:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x544c4e and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x1b and fm3 == 0x00003f and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7ed44c4e; op2val:0x0;
op3val:0xd80003f; valaddr_reg:x12; val_offset:5400*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 5400*FLEN/8, x13, x9, x10)

inst_1822:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x544c4e and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x1b and fm3 == 0x7fffe0 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7ed44c4e; op2val:0x0;
op3val:0xdffffe0; valaddr_reg:x12; val_offset:5403*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 5403*FLEN/8, x13, x9, x10)

inst_1823:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x544c4e and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x1b and fm3 == 0x00001f and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7ed44c4e; op2val:0x0;
op3val:0xd80001f; valaddr_reg:x12; val_offset:5406*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 5406*FLEN/8, x13, x9, x10)

inst_1824:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x544c4e and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x1b and fm3 == 0x7ffff0 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7ed44c4e; op2val:0x0;
op3val:0xdfffff0; valaddr_reg:x12; val_offset:5409*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 5409*FLEN/8, x13, x9, x10)

inst_1825:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x544c4e and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x1b and fm3 == 0x00000f and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7ed44c4e; op2val:0x0;
op3val:0xd80000f; valaddr_reg:x12; val_offset:5412*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 5412*FLEN/8, x13, x9, x10)

inst_1826:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x544c4e and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x1b and fm3 == 0x7ffff8 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7ed44c4e; op2val:0x0;
op3val:0xdfffff8; valaddr_reg:x12; val_offset:5415*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 5415*FLEN/8, x13, x9, x10)

inst_1827:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x544c4e and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x1b and fm3 == 0x000007 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7ed44c4e; op2val:0x0;
op3val:0xd800007; valaddr_reg:x12; val_offset:5418*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 5418*FLEN/8, x13, x9, x10)

inst_1828:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x544c4e and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x1b and fm3 == 0x7ffffc and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7ed44c4e; op2val:0x0;
op3val:0xdfffffc; valaddr_reg:x12; val_offset:5421*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 5421*FLEN/8, x13, x9, x10)

inst_1829:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x544c4e and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x1b and fm3 == 0x000003 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7ed44c4e; op2val:0x0;
op3val:0xd800003; valaddr_reg:x12; val_offset:5424*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 5424*FLEN/8, x13, x9, x10)

inst_1830:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x544c4e and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x1b and fm3 == 0x7ffffe and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7ed44c4e; op2val:0x0;
op3val:0xdfffffe; valaddr_reg:x12; val_offset:5427*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 5427*FLEN/8, x13, x9, x10)

inst_1831:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x544c4e and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x1b and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7ed44c4e; op2val:0x0;
op3val:0xd800001; valaddr_reg:x12; val_offset:5430*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 5430*FLEN/8, x13, x9, x10)

inst_1832:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x544c4e and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x7ffff8 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7ed44c4e; op2val:0x0;
op3val:0x7ffff8; valaddr_reg:x12; val_offset:5433*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 5433*FLEN/8, x13, x9, x10)

inst_1833:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x544c4e and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000007 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7ed44c4e; op2val:0x0;
op3val:0x7; valaddr_reg:x12; val_offset:5436*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 5436*FLEN/8, x13, x9, x10)

inst_1834:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x544c4e and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x7ffffc and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7ed44c4e; op2val:0x0;
op3val:0x7ffffc; valaddr_reg:x12; val_offset:5439*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 5439*FLEN/8, x13, x9, x10)

inst_1835:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x544c4e and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000003 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7ed44c4e; op2val:0x0;
op3val:0x3; valaddr_reg:x12; val_offset:5442*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 5442*FLEN/8, x13, x9, x10)

inst_1836:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x544c4e and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x7ffffe and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7ed44c4e; op2val:0x0;
op3val:0x7ffffe; valaddr_reg:x12; val_offset:5445*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 5445*FLEN/8, x13, x9, x10)

inst_1837:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x544c4e and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7ed44c4e; op2val:0x0;
op3val:0x1; valaddr_reg:x12; val_offset:5448*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 5448*FLEN/8, x13, x9, x10)

inst_1838:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x544c4e and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x36db6d and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7ed44c4e; op2val:0x0;
op3val:0x36db6d; valaddr_reg:x12; val_offset:5451*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 5451*FLEN/8, x13, x9, x10)

inst_1839:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x544c4e and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x6db6db and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7ed44c4e; op2val:0x0;
op3val:0x6db6db; valaddr_reg:x12; val_offset:5454*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 5454*FLEN/8, x13, x9, x10)

inst_1840:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x544c4e and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x199999 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7ed44c4e; op2val:0x0;
op3val:0x199999; valaddr_reg:x12; val_offset:5457*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 5457*FLEN/8, x13, x9, x10)

inst_1841:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x544c4e and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x666666 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7ed44c4e; op2val:0x0;
op3val:0x666666; valaddr_reg:x12; val_offset:5460*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 5460*FLEN/8, x13, x9, x10)

inst_1842:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x544c4e and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x3bbbbb and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7ed44c4e; op2val:0x0;
op3val:0x3bbbbb; valaddr_reg:x12; val_offset:5463*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 5463*FLEN/8, x13, x9, x10)

inst_1843:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x544c4e and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x444444 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7ed44c4e; op2val:0x0;
op3val:0x444444; valaddr_reg:x12; val_offset:5466*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 5466*FLEN/8, x13, x9, x10)

inst_1844:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x544c4e and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x249249 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7ed44c4e; op2val:0x0;
op3val:0x249249; valaddr_reg:x12; val_offset:5469*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 5469*FLEN/8, x13, x9, x10)

inst_1845:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x544c4e and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x5b6db6 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7ed44c4e; op2val:0x0;
op3val:0x5b6db6; valaddr_reg:x12; val_offset:5472*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 5472*FLEN/8, x13, x9, x10)

inst_1846:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x544c4e and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x333333 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7ed44c4e; op2val:0x0;
op3val:0x333333; valaddr_reg:x12; val_offset:5475*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 5475*FLEN/8, x13, x9, x10)

inst_1847:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x544c4e and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x4ccccc and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7ed44c4e; op2val:0x0;
op3val:0x4ccccc; valaddr_reg:x12; val_offset:5478*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 5478*FLEN/8, x13, x9, x10)

inst_1848:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x04bfbb and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x1c and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e84bfbb; op2val:0x0;
op3val:0xe000000; valaddr_reg:x12; val_offset:5481*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 5481*FLEN/8, x13, x9, x10)

inst_1849:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x04bfbb and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x1c and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e84bfbb; op2val:0x0;
op3val:0xe7fffff; valaddr_reg:x12; val_offset:5484*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 5484*FLEN/8, x13, x9, x10)

inst_1850:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x04bfbb and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x1c and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e84bfbb; op2val:0x0;
op3val:0xe400000; valaddr_reg:x12; val_offset:5487*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 5487*FLEN/8, x13, x9, x10)

inst_1851:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x04bfbb and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x1c and fm3 == 0x3fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e84bfbb; op2val:0x0;
op3val:0xe3fffff; valaddr_reg:x12; val_offset:5490*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 5490*FLEN/8, x13, x9, x10)

inst_1852:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x04bfbb and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x1c and fm3 == 0x600000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e84bfbb; op2val:0x0;
op3val:0xe600000; valaddr_reg:x12; val_offset:5493*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 5493*FLEN/8, x13, x9, x10)

inst_1853:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x04bfbb and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x1c and fm3 == 0x1fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e84bfbb; op2val:0x0;
op3val:0xe1fffff; valaddr_reg:x12; val_offset:5496*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 5496*FLEN/8, x13, x9, x10)

inst_1854:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x04bfbb and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x1c and fm3 == 0x700000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e84bfbb; op2val:0x0;
op3val:0xe700000; valaddr_reg:x12; val_offset:5499*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 5499*FLEN/8, x13, x9, x10)

inst_1855:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x04bfbb and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x1c and fm3 == 0x0fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e84bfbb; op2val:0x0;
op3val:0xe0fffff; valaddr_reg:x12; val_offset:5502*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 5502*FLEN/8, x13, x9, x10)

inst_1856:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x04bfbb and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x1c and fm3 == 0x780000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e84bfbb; op2val:0x0;
op3val:0xe780000; valaddr_reg:x12; val_offset:5505*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 5505*FLEN/8, x13, x9, x10)

inst_1857:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x04bfbb and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x1c and fm3 == 0x07ffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e84bfbb; op2val:0x0;
op3val:0xe07ffff; valaddr_reg:x12; val_offset:5508*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 5508*FLEN/8, x13, x9, x10)

inst_1858:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x04bfbb and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x1c and fm3 == 0x7c0000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e84bfbb; op2val:0x0;
op3val:0xe7c0000; valaddr_reg:x12; val_offset:5511*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 5511*FLEN/8, x13, x9, x10)

inst_1859:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x04bfbb and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x1c and fm3 == 0x03ffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e84bfbb; op2val:0x0;
op3val:0xe03ffff; valaddr_reg:x12; val_offset:5514*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 5514*FLEN/8, x13, x9, x10)

inst_1860:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x04bfbb and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x1c and fm3 == 0x7e0000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e84bfbb; op2val:0x0;
op3val:0xe7e0000; valaddr_reg:x12; val_offset:5517*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 5517*FLEN/8, x13, x9, x10)

inst_1861:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x04bfbb and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x1c and fm3 == 0x01ffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e84bfbb; op2val:0x0;
op3val:0xe01ffff; valaddr_reg:x12; val_offset:5520*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 5520*FLEN/8, x13, x9, x10)

inst_1862:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x04bfbb and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x1c and fm3 == 0x7f0000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e84bfbb; op2val:0x0;
op3val:0xe7f0000; valaddr_reg:x12; val_offset:5523*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 5523*FLEN/8, x13, x9, x10)

inst_1863:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x04bfbb and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x1c and fm3 == 0x00ffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e84bfbb; op2val:0x0;
op3val:0xe00ffff; valaddr_reg:x12; val_offset:5526*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 5526*FLEN/8, x13, x9, x10)

inst_1864:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x04bfbb and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x1c and fm3 == 0x7f8000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e84bfbb; op2val:0x0;
op3val:0xe7f8000; valaddr_reg:x12; val_offset:5529*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 5529*FLEN/8, x13, x9, x10)

inst_1865:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x04bfbb and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x1c and fm3 == 0x007fff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e84bfbb; op2val:0x0;
op3val:0xe007fff; valaddr_reg:x12; val_offset:5532*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 5532*FLEN/8, x13, x9, x10)

inst_1866:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x04bfbb and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x1c and fm3 == 0x7fc000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e84bfbb; op2val:0x0;
op3val:0xe7fc000; valaddr_reg:x12; val_offset:5535*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 5535*FLEN/8, x13, x9, x10)

inst_1867:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x04bfbb and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x1c and fm3 == 0x003fff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e84bfbb; op2val:0x0;
op3val:0xe003fff; valaddr_reg:x12; val_offset:5538*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 5538*FLEN/8, x13, x9, x10)

inst_1868:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x04bfbb and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x1c and fm3 == 0x7fe000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e84bfbb; op2val:0x0;
op3val:0xe7fe000; valaddr_reg:x12; val_offset:5541*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 5541*FLEN/8, x13, x9, x10)

inst_1869:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x04bfbb and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x1c and fm3 == 0x001fff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e84bfbb; op2val:0x0;
op3val:0xe001fff; valaddr_reg:x12; val_offset:5544*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 5544*FLEN/8, x13, x9, x10)

inst_1870:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x04bfbb and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x1c and fm3 == 0x7ff000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e84bfbb; op2val:0x0;
op3val:0xe7ff000; valaddr_reg:x12; val_offset:5547*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 5547*FLEN/8, x13, x9, x10)

inst_1871:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x04bfbb and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x1c and fm3 == 0x000fff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e84bfbb; op2val:0x0;
op3val:0xe000fff; valaddr_reg:x12; val_offset:5550*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 5550*FLEN/8, x13, x9, x10)

inst_1872:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x04bfbb and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x1c and fm3 == 0x7ff800 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e84bfbb; op2val:0x0;
op3val:0xe7ff800; valaddr_reg:x12; val_offset:5553*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 5553*FLEN/8, x13, x9, x10)

inst_1873:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x04bfbb and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x1c and fm3 == 0x0007ff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e84bfbb; op2val:0x0;
op3val:0xe0007ff; valaddr_reg:x12; val_offset:5556*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 5556*FLEN/8, x13, x9, x10)

inst_1874:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x04bfbb and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x1c and fm3 == 0x7ffc00 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e84bfbb; op2val:0x0;
op3val:0xe7ffc00; valaddr_reg:x12; val_offset:5559*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 5559*FLEN/8, x13, x9, x10)

inst_1875:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x04bfbb and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x1c and fm3 == 0x0003ff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e84bfbb; op2val:0x0;
op3val:0xe0003ff; valaddr_reg:x12; val_offset:5562*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 5562*FLEN/8, x13, x9, x10)

inst_1876:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x04bfbb and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x1c and fm3 == 0x7ffe00 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e84bfbb; op2val:0x0;
op3val:0xe7ffe00; valaddr_reg:x12; val_offset:5565*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 5565*FLEN/8, x13, x9, x10)

inst_1877:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x04bfbb and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x1c and fm3 == 0x0001ff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e84bfbb; op2val:0x0;
op3val:0xe0001ff; valaddr_reg:x12; val_offset:5568*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 5568*FLEN/8, x13, x9, x10)

inst_1878:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x04bfbb and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x1c and fm3 == 0x7fff00 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e84bfbb; op2val:0x0;
op3val:0xe7fff00; valaddr_reg:x12; val_offset:5571*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 5571*FLEN/8, x13, x9, x10)

inst_1879:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x04bfbb and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x1c and fm3 == 0x0000ff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e84bfbb; op2val:0x0;
op3val:0xe0000ff; valaddr_reg:x12; val_offset:5574*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 5574*FLEN/8, x13, x9, x10)

inst_1880:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x04bfbb and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x1c and fm3 == 0x7fff80 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e84bfbb; op2val:0x0;
op3val:0xe7fff80; valaddr_reg:x12; val_offset:5577*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 5577*FLEN/8, x13, x9, x10)

inst_1881:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x04bfbb and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x1c and fm3 == 0x00007f and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e84bfbb; op2val:0x0;
op3val:0xe00007f; valaddr_reg:x12; val_offset:5580*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 5580*FLEN/8, x13, x9, x10)

inst_1882:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x04bfbb and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x1c and fm3 == 0x7fffc0 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e84bfbb; op2val:0x0;
op3val:0xe7fffc0; valaddr_reg:x12; val_offset:5583*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 5583*FLEN/8, x13, x9, x10)

inst_1883:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x04bfbb and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x1c and fm3 == 0x00003f and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e84bfbb; op2val:0x0;
op3val:0xe00003f; valaddr_reg:x12; val_offset:5586*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 5586*FLEN/8, x13, x9, x10)

inst_1884:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x04bfbb and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x1c and fm3 == 0x7fffe0 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e84bfbb; op2val:0x0;
op3val:0xe7fffe0; valaddr_reg:x12; val_offset:5589*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 5589*FLEN/8, x13, x9, x10)

inst_1885:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x04bfbb and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x1c and fm3 == 0x00001f and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e84bfbb; op2val:0x0;
op3val:0xe00001f; valaddr_reg:x12; val_offset:5592*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 5592*FLEN/8, x13, x9, x10)

inst_1886:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x04bfbb and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x1c and fm3 == 0x7ffff0 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e84bfbb; op2val:0x0;
op3val:0xe7ffff0; valaddr_reg:x12; val_offset:5595*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 5595*FLEN/8, x13, x9, x10)

inst_1887:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x04bfbb and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x1c and fm3 == 0x00000f and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e84bfbb; op2val:0x0;
op3val:0xe00000f; valaddr_reg:x12; val_offset:5598*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 5598*FLEN/8, x13, x9, x10)

inst_1888:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x04bfbb and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x1c and fm3 == 0x7ffff8 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e84bfbb; op2val:0x0;
op3val:0xe7ffff8; valaddr_reg:x12; val_offset:5601*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 5601*FLEN/8, x13, x9, x10)

inst_1889:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x04bfbb and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x1c and fm3 == 0x000007 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e84bfbb; op2val:0x0;
op3val:0xe000007; valaddr_reg:x12; val_offset:5604*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 5604*FLEN/8, x13, x9, x10)

inst_1890:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x04bfbb and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x1c and fm3 == 0x7ffffc and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e84bfbb; op2val:0x0;
op3val:0xe7ffffc; valaddr_reg:x12; val_offset:5607*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 5607*FLEN/8, x13, x9, x10)

inst_1891:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x04bfbb and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x1c and fm3 == 0x000003 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e84bfbb; op2val:0x0;
op3val:0xe000003; valaddr_reg:x12; val_offset:5610*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 5610*FLEN/8, x13, x9, x10)

inst_1892:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x04bfbb and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x1c and fm3 == 0x7ffffe and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e84bfbb; op2val:0x0;
op3val:0xe7ffffe; valaddr_reg:x12; val_offset:5613*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 5613*FLEN/8, x13, x9, x10)

inst_1893:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x04bfbb and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x1c and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e84bfbb; op2val:0x0;
op3val:0xe000001; valaddr_reg:x12; val_offset:5616*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 5616*FLEN/8, x13, x9, x10)

inst_1894:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x04bfbb and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x7ffff8 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e84bfbb; op2val:0x0;
op3val:0x7ffff8; valaddr_reg:x12; val_offset:5619*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 5619*FLEN/8, x13, x9, x10)

inst_1895:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x04bfbb and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000007 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e84bfbb; op2val:0x0;
op3val:0x7; valaddr_reg:x12; val_offset:5622*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 5622*FLEN/8, x13, x9, x10)

inst_1896:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x04bfbb and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x7ffffc and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e84bfbb; op2val:0x0;
op3val:0x7ffffc; valaddr_reg:x12; val_offset:5625*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 5625*FLEN/8, x13, x9, x10)

inst_1897:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x04bfbb and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000003 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e84bfbb; op2val:0x0;
op3val:0x3; valaddr_reg:x12; val_offset:5628*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 5628*FLEN/8, x13, x9, x10)

inst_1898:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x04bfbb and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x7ffffe and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e84bfbb; op2val:0x0;
op3val:0x7ffffe; valaddr_reg:x12; val_offset:5631*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 5631*FLEN/8, x13, x9, x10)

inst_1899:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x04bfbb and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e84bfbb; op2val:0x0;
op3val:0x1; valaddr_reg:x12; val_offset:5634*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 5634*FLEN/8, x13, x9, x10)

inst_1900:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x04bfbb and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x36db6d and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e84bfbb; op2val:0x0;
op3val:0x36db6d; valaddr_reg:x12; val_offset:5637*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 5637*FLEN/8, x13, x9, x10)

inst_1901:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x04bfbb and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x6db6db and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e84bfbb; op2val:0x0;
op3val:0x6db6db; valaddr_reg:x12; val_offset:5640*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 5640*FLEN/8, x13, x9, x10)

inst_1902:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x04bfbb and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x199999 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e84bfbb; op2val:0x0;
op3val:0x199999; valaddr_reg:x12; val_offset:5643*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 5643*FLEN/8, x13, x9, x10)

inst_1903:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x04bfbb and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x666666 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e84bfbb; op2val:0x0;
op3val:0x666666; valaddr_reg:x12; val_offset:5646*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 5646*FLEN/8, x13, x9, x10)

inst_1904:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x04bfbb and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x3bbbbb and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e84bfbb; op2val:0x0;
op3val:0x3bbbbb; valaddr_reg:x12; val_offset:5649*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 5649*FLEN/8, x13, x9, x10)

inst_1905:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x04bfbb and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x444444 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e84bfbb; op2val:0x0;
op3val:0x444444; valaddr_reg:x12; val_offset:5652*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 5652*FLEN/8, x13, x9, x10)

inst_1906:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x04bfbb and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x249249 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e84bfbb; op2val:0x0;
op3val:0x249249; valaddr_reg:x12; val_offset:5655*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 5655*FLEN/8, x13, x9, x10)

inst_1907:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x04bfbb and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x5b6db6 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e84bfbb; op2val:0x0;
op3val:0x5b6db6; valaddr_reg:x12; val_offset:5658*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 5658*FLEN/8, x13, x9, x10)

inst_1908:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x04bfbb and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x333333 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e84bfbb; op2val:0x0;
op3val:0x333333; valaddr_reg:x12; val_offset:5661*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 5661*FLEN/8, x13, x9, x10)

inst_1909:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x04bfbb and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x4ccccc and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e84bfbb; op2val:0x0;
op3val:0x4ccccc; valaddr_reg:x12; val_offset:5664*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 5664*FLEN/8, x13, x9, x10)

inst_1910:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x01f475 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f01f475; op2val:0x0;
op3val:0xe800000; valaddr_reg:x12; val_offset:5667*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 5667*FLEN/8, x13, x9, x10)

inst_1911:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x01f475 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f01f475; op2val:0x0;
op3val:0xeffffff; valaddr_reg:x12; val_offset:5670*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 5670*FLEN/8, x13, x9, x10)

inst_1912:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x01f475 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f01f475; op2val:0x0;
op3val:0xec00000; valaddr_reg:x12; val_offset:5673*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 5673*FLEN/8, x13, x9, x10)

inst_1913:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x01f475 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x3fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f01f475; op2val:0x0;
op3val:0xebfffff; valaddr_reg:x12; val_offset:5676*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 5676*FLEN/8, x13, x9, x10)

inst_1914:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x01f475 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x600000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f01f475; op2val:0x0;
op3val:0xee00000; valaddr_reg:x12; val_offset:5679*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 5679*FLEN/8, x13, x9, x10)

inst_1915:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x01f475 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x1fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f01f475; op2val:0x0;
op3val:0xe9fffff; valaddr_reg:x12; val_offset:5682*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 5682*FLEN/8, x13, x9, x10)

inst_1916:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x01f475 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x700000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f01f475; op2val:0x0;
op3val:0xef00000; valaddr_reg:x12; val_offset:5685*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 5685*FLEN/8, x13, x9, x10)

inst_1917:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x01f475 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x0fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f01f475; op2val:0x0;
op3val:0xe8fffff; valaddr_reg:x12; val_offset:5688*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 5688*FLEN/8, x13, x9, x10)

inst_1918:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x01f475 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x780000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f01f475; op2val:0x0;
op3val:0xef80000; valaddr_reg:x12; val_offset:5691*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 5691*FLEN/8, x13, x9, x10)

inst_1919:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x01f475 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x07ffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f01f475; op2val:0x0;
op3val:0xe87ffff; valaddr_reg:x12; val_offset:5694*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 5694*FLEN/8, x13, x9, x10)

inst_1920:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x01f475 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x7c0000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f01f475; op2val:0x0;
op3val:0xefc0000; valaddr_reg:x12; val_offset:5697*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 5697*FLEN/8, x13, x9, x10)

inst_1921:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x01f475 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x03ffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f01f475; op2val:0x0;
op3val:0xe83ffff; valaddr_reg:x12; val_offset:5700*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 5700*FLEN/8, x13, x9, x10)

inst_1922:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x01f475 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x7e0000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f01f475; op2val:0x0;
op3val:0xefe0000; valaddr_reg:x12; val_offset:5703*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 5703*FLEN/8, x13, x9, x10)

inst_1923:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x01f475 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x01ffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f01f475; op2val:0x0;
op3val:0xe81ffff; valaddr_reg:x12; val_offset:5706*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 5706*FLEN/8, x13, x9, x10)

inst_1924:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x01f475 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x7f0000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f01f475; op2val:0x0;
op3val:0xeff0000; valaddr_reg:x12; val_offset:5709*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 5709*FLEN/8, x13, x9, x10)

inst_1925:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x01f475 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x00ffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f01f475; op2val:0x0;
op3val:0xe80ffff; valaddr_reg:x12; val_offset:5712*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 5712*FLEN/8, x13, x9, x10)

inst_1926:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x01f475 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x7f8000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f01f475; op2val:0x0;
op3val:0xeff8000; valaddr_reg:x12; val_offset:5715*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 5715*FLEN/8, x13, x9, x10)

inst_1927:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x01f475 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x007fff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f01f475; op2val:0x0;
op3val:0xe807fff; valaddr_reg:x12; val_offset:5718*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 5718*FLEN/8, x13, x9, x10)

inst_1928:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x01f475 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x7fc000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f01f475; op2val:0x0;
op3val:0xeffc000; valaddr_reg:x12; val_offset:5721*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 5721*FLEN/8, x13, x9, x10)

inst_1929:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x01f475 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x003fff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f01f475; op2val:0x0;
op3val:0xe803fff; valaddr_reg:x12; val_offset:5724*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 5724*FLEN/8, x13, x9, x10)

inst_1930:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x01f475 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x7fe000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f01f475; op2val:0x0;
op3val:0xeffe000; valaddr_reg:x12; val_offset:5727*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 5727*FLEN/8, x13, x9, x10)

inst_1931:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x01f475 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x001fff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f01f475; op2val:0x0;
op3val:0xe801fff; valaddr_reg:x12; val_offset:5730*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 5730*FLEN/8, x13, x9, x10)

inst_1932:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x01f475 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x7ff000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f01f475; op2val:0x0;
op3val:0xefff000; valaddr_reg:x12; val_offset:5733*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 5733*FLEN/8, x13, x9, x10)

inst_1933:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x01f475 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x000fff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f01f475; op2val:0x0;
op3val:0xe800fff; valaddr_reg:x12; val_offset:5736*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 5736*FLEN/8, x13, x9, x10)

inst_1934:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x01f475 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x7ff800 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f01f475; op2val:0x0;
op3val:0xefff800; valaddr_reg:x12; val_offset:5739*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 5739*FLEN/8, x13, x9, x10)

inst_1935:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x01f475 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x0007ff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f01f475; op2val:0x0;
op3val:0xe8007ff; valaddr_reg:x12; val_offset:5742*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 5742*FLEN/8, x13, x9, x10)

inst_1936:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x01f475 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x7ffc00 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f01f475; op2val:0x0;
op3val:0xefffc00; valaddr_reg:x12; val_offset:5745*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 5745*FLEN/8, x13, x9, x10)

inst_1937:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x01f475 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x0003ff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f01f475; op2val:0x0;
op3val:0xe8003ff; valaddr_reg:x12; val_offset:5748*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 5748*FLEN/8, x13, x9, x10)

inst_1938:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x01f475 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x7ffe00 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f01f475; op2val:0x0;
op3val:0xefffe00; valaddr_reg:x12; val_offset:5751*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 5751*FLEN/8, x13, x9, x10)

inst_1939:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x01f475 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x0001ff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f01f475; op2val:0x0;
op3val:0xe8001ff; valaddr_reg:x12; val_offset:5754*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 5754*FLEN/8, x13, x9, x10)

inst_1940:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x01f475 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x7fff00 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f01f475; op2val:0x0;
op3val:0xeffff00; valaddr_reg:x12; val_offset:5757*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 5757*FLEN/8, x13, x9, x10)

inst_1941:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x01f475 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x0000ff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f01f475; op2val:0x0;
op3val:0xe8000ff; valaddr_reg:x12; val_offset:5760*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 5760*FLEN/8, x13, x9, x10)

inst_1942:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x01f475 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x7fff80 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f01f475; op2val:0x0;
op3val:0xeffff80; valaddr_reg:x12; val_offset:5763*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 5763*FLEN/8, x13, x9, x10)

inst_1943:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x01f475 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x00007f and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f01f475; op2val:0x0;
op3val:0xe80007f; valaddr_reg:x12; val_offset:5766*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 5766*FLEN/8, x13, x9, x10)

RVTEST_SIGBASE(x9,signature_x9_15)
inst_1944:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x01f475 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x7fffc0 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f01f475; op2val:0x0;
op3val:0xeffffc0; valaddr_reg:x12; val_offset:5769*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 5769*FLEN/8, x13, x9, x10)

inst_1945:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x01f475 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x00003f and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f01f475; op2val:0x0;
op3val:0xe80003f; valaddr_reg:x12; val_offset:5772*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 5772*FLEN/8, x13, x9, x10)

inst_1946:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x01f475 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x7fffe0 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f01f475; op2val:0x0;
op3val:0xeffffe0; valaddr_reg:x12; val_offset:5775*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 5775*FLEN/8, x13, x9, x10)

inst_1947:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x01f475 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x00001f and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f01f475; op2val:0x0;
op3val:0xe80001f; valaddr_reg:x12; val_offset:5778*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 5778*FLEN/8, x13, x9, x10)

inst_1948:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x01f475 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x7ffff0 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f01f475; op2val:0x0;
op3val:0xefffff0; valaddr_reg:x12; val_offset:5781*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 5781*FLEN/8, x13, x9, x10)

inst_1949:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x01f475 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x00000f and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f01f475; op2val:0x0;
op3val:0xe80000f; valaddr_reg:x12; val_offset:5784*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 5784*FLEN/8, x13, x9, x10)

inst_1950:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x01f475 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x7ffff8 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f01f475; op2val:0x0;
op3val:0xefffff8; valaddr_reg:x12; val_offset:5787*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 5787*FLEN/8, x13, x9, x10)

inst_1951:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x01f475 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x000007 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f01f475; op2val:0x0;
op3val:0xe800007; valaddr_reg:x12; val_offset:5790*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 5790*FLEN/8, x13, x9, x10)

inst_1952:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x01f475 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x7ffffc and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f01f475; op2val:0x0;
op3val:0xefffffc; valaddr_reg:x12; val_offset:5793*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 5793*FLEN/8, x13, x9, x10)

inst_1953:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x01f475 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x000003 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f01f475; op2val:0x0;
op3val:0xe800003; valaddr_reg:x12; val_offset:5796*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 5796*FLEN/8, x13, x9, x10)

inst_1954:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x01f475 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x7ffffe and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f01f475; op2val:0x0;
op3val:0xefffffe; valaddr_reg:x12; val_offset:5799*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 5799*FLEN/8, x13, x9, x10)

inst_1955:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x01f475 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f01f475; op2val:0x0;
op3val:0xe800001; valaddr_reg:x12; val_offset:5802*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 5802*FLEN/8, x13, x9, x10)

inst_1956:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x01f475 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x7ffff8 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f01f475; op2val:0x0;
op3val:0x7ffff8; valaddr_reg:x12; val_offset:5805*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 5805*FLEN/8, x13, x9, x10)

inst_1957:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x01f475 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000007 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f01f475; op2val:0x0;
op3val:0x7; valaddr_reg:x12; val_offset:5808*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 5808*FLEN/8, x13, x9, x10)

inst_1958:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x01f475 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x7ffffc and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f01f475; op2val:0x0;
op3val:0x7ffffc; valaddr_reg:x12; val_offset:5811*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 5811*FLEN/8, x13, x9, x10)

inst_1959:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x01f475 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000003 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f01f475; op2val:0x0;
op3val:0x3; valaddr_reg:x12; val_offset:5814*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 5814*FLEN/8, x13, x9, x10)

inst_1960:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x01f475 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x7ffffe and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f01f475; op2val:0x0;
op3val:0x7ffffe; valaddr_reg:x12; val_offset:5817*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 5817*FLEN/8, x13, x9, x10)

inst_1961:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x01f475 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f01f475; op2val:0x0;
op3val:0x1; valaddr_reg:x12; val_offset:5820*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 5820*FLEN/8, x13, x9, x10)

inst_1962:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x01f475 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x36db6d and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f01f475; op2val:0x0;
op3val:0x36db6d; valaddr_reg:x12; val_offset:5823*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 5823*FLEN/8, x13, x9, x10)

inst_1963:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x01f475 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x6db6db and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f01f475; op2val:0x0;
op3val:0x6db6db; valaddr_reg:x12; val_offset:5826*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 5826*FLEN/8, x13, x9, x10)

inst_1964:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x01f475 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x199999 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f01f475; op2val:0x0;
op3val:0x199999; valaddr_reg:x12; val_offset:5829*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 5829*FLEN/8, x13, x9, x10)

inst_1965:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x01f475 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x666666 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f01f475; op2val:0x0;
op3val:0x666666; valaddr_reg:x12; val_offset:5832*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 5832*FLEN/8, x13, x9, x10)

inst_1966:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x01f475 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x3bbbbb and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f01f475; op2val:0x0;
op3val:0x3bbbbb; valaddr_reg:x12; val_offset:5835*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 5835*FLEN/8, x13, x9, x10)

inst_1967:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x01f475 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x444444 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f01f475; op2val:0x0;
op3val:0x444444; valaddr_reg:x12; val_offset:5838*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 5838*FLEN/8, x13, x9, x10)

inst_1968:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x01f475 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x249249 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f01f475; op2val:0x0;
op3val:0x249249; valaddr_reg:x12; val_offset:5841*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 5841*FLEN/8, x13, x9, x10)

inst_1969:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x01f475 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x5b6db6 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f01f475; op2val:0x0;
op3val:0x5b6db6; valaddr_reg:x12; val_offset:5844*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 5844*FLEN/8, x13, x9, x10)

inst_1970:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x01f475 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x333333 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f01f475; op2val:0x0;
op3val:0x333333; valaddr_reg:x12; val_offset:5847*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 5847*FLEN/8, x13, x9, x10)

inst_1971:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x01f475 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x4ccccc and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f01f475; op2val:0x0;
op3val:0x4ccccc; valaddr_reg:x12; val_offset:5850*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 5850*FLEN/8, x13, x9, x10)

inst_1972:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x121a1a and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f121a1a; op2val:0x0;
op3val:0xf000000; valaddr_reg:x12; val_offset:5853*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 5853*FLEN/8, x13, x9, x10)

inst_1973:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x121a1a and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f121a1a; op2val:0x0;
op3val:0xf7fffff; valaddr_reg:x12; val_offset:5856*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 5856*FLEN/8, x13, x9, x10)

inst_1974:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x121a1a and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f121a1a; op2val:0x0;
op3val:0xf400000; valaddr_reg:x12; val_offset:5859*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 5859*FLEN/8, x13, x9, x10)

inst_1975:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x121a1a and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f121a1a; op2val:0x0;
op3val:0xf3fffff; valaddr_reg:x12; val_offset:5862*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 5862*FLEN/8, x13, x9, x10)

inst_1976:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x121a1a and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x600000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f121a1a; op2val:0x0;
op3val:0xf600000; valaddr_reg:x12; val_offset:5865*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 5865*FLEN/8, x13, x9, x10)

inst_1977:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x121a1a and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x1fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f121a1a; op2val:0x0;
op3val:0xf1fffff; valaddr_reg:x12; val_offset:5868*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 5868*FLEN/8, x13, x9, x10)

inst_1978:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x121a1a and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x700000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f121a1a; op2val:0x0;
op3val:0xf700000; valaddr_reg:x12; val_offset:5871*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 5871*FLEN/8, x13, x9, x10)

inst_1979:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x121a1a and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x0fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f121a1a; op2val:0x0;
op3val:0xf0fffff; valaddr_reg:x12; val_offset:5874*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 5874*FLEN/8, x13, x9, x10)

inst_1980:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x121a1a and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x780000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f121a1a; op2val:0x0;
op3val:0xf780000; valaddr_reg:x12; val_offset:5877*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 5877*FLEN/8, x13, x9, x10)

inst_1981:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x121a1a and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x07ffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f121a1a; op2val:0x0;
op3val:0xf07ffff; valaddr_reg:x12; val_offset:5880*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 5880*FLEN/8, x13, x9, x10)

inst_1982:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x121a1a and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x7c0000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f121a1a; op2val:0x0;
op3val:0xf7c0000; valaddr_reg:x12; val_offset:5883*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 5883*FLEN/8, x13, x9, x10)

inst_1983:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x121a1a and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x03ffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f121a1a; op2val:0x0;
op3val:0xf03ffff; valaddr_reg:x12; val_offset:5886*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 5886*FLEN/8, x13, x9, x10)

inst_1984:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x121a1a and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x7e0000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f121a1a; op2val:0x0;
op3val:0xf7e0000; valaddr_reg:x12; val_offset:5889*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 5889*FLEN/8, x13, x9, x10)

inst_1985:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x121a1a and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x01ffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f121a1a; op2val:0x0;
op3val:0xf01ffff; valaddr_reg:x12; val_offset:5892*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 5892*FLEN/8, x13, x9, x10)

inst_1986:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x121a1a and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x7f0000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f121a1a; op2val:0x0;
op3val:0xf7f0000; valaddr_reg:x12; val_offset:5895*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 5895*FLEN/8, x13, x9, x10)

inst_1987:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x121a1a and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x00ffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f121a1a; op2val:0x0;
op3val:0xf00ffff; valaddr_reg:x12; val_offset:5898*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 5898*FLEN/8, x13, x9, x10)

inst_1988:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x121a1a and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x7f8000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f121a1a; op2val:0x0;
op3val:0xf7f8000; valaddr_reg:x12; val_offset:5901*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 5901*FLEN/8, x13, x9, x10)

inst_1989:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x121a1a and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x007fff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f121a1a; op2val:0x0;
op3val:0xf007fff; valaddr_reg:x12; val_offset:5904*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 5904*FLEN/8, x13, x9, x10)

inst_1990:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x121a1a and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x7fc000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f121a1a; op2val:0x0;
op3val:0xf7fc000; valaddr_reg:x12; val_offset:5907*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 5907*FLEN/8, x13, x9, x10)

inst_1991:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x121a1a and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x003fff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f121a1a; op2val:0x0;
op3val:0xf003fff; valaddr_reg:x12; val_offset:5910*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 5910*FLEN/8, x13, x9, x10)

inst_1992:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x121a1a and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x7fe000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f121a1a; op2val:0x0;
op3val:0xf7fe000; valaddr_reg:x12; val_offset:5913*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 5913*FLEN/8, x13, x9, x10)

inst_1993:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x121a1a and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x001fff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f121a1a; op2val:0x0;
op3val:0xf001fff; valaddr_reg:x12; val_offset:5916*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 5916*FLEN/8, x13, x9, x10)

inst_1994:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x121a1a and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x7ff000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f121a1a; op2val:0x0;
op3val:0xf7ff000; valaddr_reg:x12; val_offset:5919*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 5919*FLEN/8, x13, x9, x10)

inst_1995:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x121a1a and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x000fff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f121a1a; op2val:0x0;
op3val:0xf000fff; valaddr_reg:x12; val_offset:5922*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 5922*FLEN/8, x13, x9, x10)

inst_1996:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x121a1a and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x7ff800 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f121a1a; op2val:0x0;
op3val:0xf7ff800; valaddr_reg:x12; val_offset:5925*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 5925*FLEN/8, x13, x9, x10)

inst_1997:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x121a1a and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x0007ff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f121a1a; op2val:0x0;
op3val:0xf0007ff; valaddr_reg:x12; val_offset:5928*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 5928*FLEN/8, x13, x9, x10)

inst_1998:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x121a1a and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x7ffc00 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f121a1a; op2val:0x0;
op3val:0xf7ffc00; valaddr_reg:x12; val_offset:5931*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 5931*FLEN/8, x13, x9, x10)

inst_1999:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x121a1a and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x0003ff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f121a1a; op2val:0x0;
op3val:0xf0003ff; valaddr_reg:x12; val_offset:5934*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 5934*FLEN/8, x13, x9, x10)

inst_2000:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x121a1a and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x7ffe00 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f121a1a; op2val:0x0;
op3val:0xf7ffe00; valaddr_reg:x12; val_offset:5937*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 5937*FLEN/8, x13, x9, x10)

inst_2001:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x121a1a and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x0001ff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f121a1a; op2val:0x0;
op3val:0xf0001ff; valaddr_reg:x12; val_offset:5940*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 5940*FLEN/8, x13, x9, x10)

inst_2002:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x121a1a and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x7fff00 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f121a1a; op2val:0x0;
op3val:0xf7fff00; valaddr_reg:x12; val_offset:5943*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 5943*FLEN/8, x13, x9, x10)

inst_2003:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x121a1a and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x0000ff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f121a1a; op2val:0x0;
op3val:0xf0000ff; valaddr_reg:x12; val_offset:5946*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 5946*FLEN/8, x13, x9, x10)

inst_2004:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x121a1a and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x7fff80 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f121a1a; op2val:0x0;
op3val:0xf7fff80; valaddr_reg:x12; val_offset:5949*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 5949*FLEN/8, x13, x9, x10)

inst_2005:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x121a1a and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x00007f and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f121a1a; op2val:0x0;
op3val:0xf00007f; valaddr_reg:x12; val_offset:5952*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 5952*FLEN/8, x13, x9, x10)

inst_2006:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x121a1a and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x7fffc0 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f121a1a; op2val:0x0;
op3val:0xf7fffc0; valaddr_reg:x12; val_offset:5955*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 5955*FLEN/8, x13, x9, x10)

inst_2007:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x121a1a and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x00003f and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f121a1a; op2val:0x0;
op3val:0xf00003f; valaddr_reg:x12; val_offset:5958*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 5958*FLEN/8, x13, x9, x10)

inst_2008:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x121a1a and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x7fffe0 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f121a1a; op2val:0x0;
op3val:0xf7fffe0; valaddr_reg:x12; val_offset:5961*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 5961*FLEN/8, x13, x9, x10)

inst_2009:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x121a1a and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x00001f and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f121a1a; op2val:0x0;
op3val:0xf00001f; valaddr_reg:x12; val_offset:5964*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 5964*FLEN/8, x13, x9, x10)

inst_2010:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x121a1a and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x7ffff0 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f121a1a; op2val:0x0;
op3val:0xf7ffff0; valaddr_reg:x12; val_offset:5967*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 5967*FLEN/8, x13, x9, x10)

inst_2011:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x121a1a and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x00000f and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f121a1a; op2val:0x0;
op3val:0xf00000f; valaddr_reg:x12; val_offset:5970*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 5970*FLEN/8, x13, x9, x10)

inst_2012:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x121a1a and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x7ffff8 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f121a1a; op2val:0x0;
op3val:0xf7ffff8; valaddr_reg:x12; val_offset:5973*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 5973*FLEN/8, x13, x9, x10)

inst_2013:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x121a1a and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x000007 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f121a1a; op2val:0x0;
op3val:0xf000007; valaddr_reg:x12; val_offset:5976*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 5976*FLEN/8, x13, x9, x10)

inst_2014:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x121a1a and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x7ffffc and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f121a1a; op2val:0x0;
op3val:0xf7ffffc; valaddr_reg:x12; val_offset:5979*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 5979*FLEN/8, x13, x9, x10)

inst_2015:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x121a1a and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x000003 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f121a1a; op2val:0x0;
op3val:0xf000003; valaddr_reg:x12; val_offset:5982*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 5982*FLEN/8, x13, x9, x10)

inst_2016:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x121a1a and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x7ffffe and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f121a1a; op2val:0x0;
op3val:0xf7ffffe; valaddr_reg:x12; val_offset:5985*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 5985*FLEN/8, x13, x9, x10)

inst_2017:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x121a1a and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f121a1a; op2val:0x0;
op3val:0xf000001; valaddr_reg:x12; val_offset:5988*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 5988*FLEN/8, x13, x9, x10)

inst_2018:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x121a1a and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x7ffff8 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f121a1a; op2val:0x0;
op3val:0x7ffff8; valaddr_reg:x12; val_offset:5991*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 5991*FLEN/8, x13, x9, x10)

inst_2019:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x121a1a and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000007 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f121a1a; op2val:0x0;
op3val:0x7; valaddr_reg:x12; val_offset:5994*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 5994*FLEN/8, x13, x9, x10)

inst_2020:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x121a1a and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x7ffffc and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f121a1a; op2val:0x0;
op3val:0x7ffffc; valaddr_reg:x12; val_offset:5997*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 5997*FLEN/8, x13, x9, x10)

inst_2021:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x121a1a and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000003 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f121a1a; op2val:0x0;
op3val:0x3; valaddr_reg:x12; val_offset:6000*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 6000*FLEN/8, x13, x9, x10)

inst_2022:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x121a1a and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x7ffffe and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f121a1a; op2val:0x0;
op3val:0x7ffffe; valaddr_reg:x12; val_offset:6003*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 6003*FLEN/8, x13, x9, x10)

inst_2023:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x121a1a and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f121a1a; op2val:0x0;
op3val:0x1; valaddr_reg:x12; val_offset:6006*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 6006*FLEN/8, x13, x9, x10)

inst_2024:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x121a1a and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x36db6d and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f121a1a; op2val:0x0;
op3val:0x36db6d; valaddr_reg:x12; val_offset:6009*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 6009*FLEN/8, x13, x9, x10)

inst_2025:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x121a1a and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x6db6db and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f121a1a; op2val:0x0;
op3val:0x6db6db; valaddr_reg:x12; val_offset:6012*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 6012*FLEN/8, x13, x9, x10)

inst_2026:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x121a1a and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x199999 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f121a1a; op2val:0x0;
op3val:0x199999; valaddr_reg:x12; val_offset:6015*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 6015*FLEN/8, x13, x9, x10)

inst_2027:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x121a1a and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x666666 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f121a1a; op2val:0x0;
op3val:0x666666; valaddr_reg:x12; val_offset:6018*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 6018*FLEN/8, x13, x9, x10)

inst_2028:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x121a1a and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x3bbbbb and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f121a1a; op2val:0x0;
op3val:0x3bbbbb; valaddr_reg:x12; val_offset:6021*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 6021*FLEN/8, x13, x9, x10)

inst_2029:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x121a1a and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x444444 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f121a1a; op2val:0x0;
op3val:0x444444; valaddr_reg:x12; val_offset:6024*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 6024*FLEN/8, x13, x9, x10)

inst_2030:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x121a1a and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x249249 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f121a1a; op2val:0x0;
op3val:0x249249; valaddr_reg:x12; val_offset:6027*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 6027*FLEN/8, x13, x9, x10)

inst_2031:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x121a1a and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x5b6db6 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f121a1a; op2val:0x0;
op3val:0x5b6db6; valaddr_reg:x12; val_offset:6030*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 6030*FLEN/8, x13, x9, x10)

inst_2032:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x121a1a and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x333333 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f121a1a; op2val:0x0;
op3val:0x333333; valaddr_reg:x12; val_offset:6033*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 6033*FLEN/8, x13, x9, x10)

inst_2033:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x121a1a and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x4ccccc and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f121a1a; op2val:0x0;
op3val:0x4ccccc; valaddr_reg:x12; val_offset:6036*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 6036*FLEN/8, x13, x9, x10)

inst_2034:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x36d4b7 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f36d4b7; op2val:0x0;
op3val:0xf800000; valaddr_reg:x12; val_offset:6039*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 6039*FLEN/8, x13, x9, x10)

inst_2035:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x36d4b7 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f36d4b7; op2val:0x0;
op3val:0xfffffff; valaddr_reg:x12; val_offset:6042*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 6042*FLEN/8, x13, x9, x10)

inst_2036:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x36d4b7 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f36d4b7; op2val:0x0;
op3val:0xfc00000; valaddr_reg:x12; val_offset:6045*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 6045*FLEN/8, x13, x9, x10)

inst_2037:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x36d4b7 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x3fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f36d4b7; op2val:0x0;
op3val:0xfbfffff; valaddr_reg:x12; val_offset:6048*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 6048*FLEN/8, x13, x9, x10)

inst_2038:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x36d4b7 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x600000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f36d4b7; op2val:0x0;
op3val:0xfe00000; valaddr_reg:x12; val_offset:6051*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 6051*FLEN/8, x13, x9, x10)

inst_2039:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x36d4b7 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x1fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f36d4b7; op2val:0x0;
op3val:0xf9fffff; valaddr_reg:x12; val_offset:6054*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 6054*FLEN/8, x13, x9, x10)

inst_2040:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x36d4b7 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x700000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f36d4b7; op2val:0x0;
op3val:0xff00000; valaddr_reg:x12; val_offset:6057*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 6057*FLEN/8, x13, x9, x10)

inst_2041:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x36d4b7 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x0fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f36d4b7; op2val:0x0;
op3val:0xf8fffff; valaddr_reg:x12; val_offset:6060*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 6060*FLEN/8, x13, x9, x10)

inst_2042:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x36d4b7 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x780000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f36d4b7; op2val:0x0;
op3val:0xff80000; valaddr_reg:x12; val_offset:6063*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 6063*FLEN/8, x13, x9, x10)

inst_2043:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x36d4b7 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x07ffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f36d4b7; op2val:0x0;
op3val:0xf87ffff; valaddr_reg:x12; val_offset:6066*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 6066*FLEN/8, x13, x9, x10)

inst_2044:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x36d4b7 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x7c0000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f36d4b7; op2val:0x0;
op3val:0xffc0000; valaddr_reg:x12; val_offset:6069*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 6069*FLEN/8, x13, x9, x10)

inst_2045:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x36d4b7 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x03ffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f36d4b7; op2val:0x0;
op3val:0xf83ffff; valaddr_reg:x12; val_offset:6072*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 6072*FLEN/8, x13, x9, x10)

inst_2046:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x36d4b7 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x7e0000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f36d4b7; op2val:0x0;
op3val:0xffe0000; valaddr_reg:x12; val_offset:6075*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 6075*FLEN/8, x13, x9, x10)

inst_2047:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x36d4b7 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x01ffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f36d4b7; op2val:0x0;
op3val:0xf81ffff; valaddr_reg:x12; val_offset:6078*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 6078*FLEN/8, x13, x9, x10)

inst_2048:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x36d4b7 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x7f0000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f36d4b7; op2val:0x0;
op3val:0xfff0000; valaddr_reg:x12; val_offset:6081*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 6081*FLEN/8, x13, x9, x10)

inst_2049:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x36d4b7 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x00ffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f36d4b7; op2val:0x0;
op3val:0xf80ffff; valaddr_reg:x12; val_offset:6084*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 6084*FLEN/8, x13, x9, x10)

inst_2050:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x36d4b7 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x7f8000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f36d4b7; op2val:0x0;
op3val:0xfff8000; valaddr_reg:x12; val_offset:6087*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 6087*FLEN/8, x13, x9, x10)

inst_2051:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x36d4b7 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x007fff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f36d4b7; op2val:0x0;
op3val:0xf807fff; valaddr_reg:x12; val_offset:6090*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 6090*FLEN/8, x13, x9, x10)

inst_2052:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x36d4b7 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x7fc000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f36d4b7; op2val:0x0;
op3val:0xfffc000; valaddr_reg:x12; val_offset:6093*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 6093*FLEN/8, x13, x9, x10)

inst_2053:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x36d4b7 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x003fff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f36d4b7; op2val:0x0;
op3val:0xf803fff; valaddr_reg:x12; val_offset:6096*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 6096*FLEN/8, x13, x9, x10)

inst_2054:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x36d4b7 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x7fe000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f36d4b7; op2val:0x0;
op3val:0xfffe000; valaddr_reg:x12; val_offset:6099*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 6099*FLEN/8, x13, x9, x10)

inst_2055:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x36d4b7 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x001fff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f36d4b7; op2val:0x0;
op3val:0xf801fff; valaddr_reg:x12; val_offset:6102*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 6102*FLEN/8, x13, x9, x10)

inst_2056:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x36d4b7 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x7ff000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f36d4b7; op2val:0x0;
op3val:0xffff000; valaddr_reg:x12; val_offset:6105*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 6105*FLEN/8, x13, x9, x10)

inst_2057:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x36d4b7 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x000fff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f36d4b7; op2val:0x0;
op3val:0xf800fff; valaddr_reg:x12; val_offset:6108*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 6108*FLEN/8, x13, x9, x10)

inst_2058:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x36d4b7 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x7ff800 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f36d4b7; op2val:0x0;
op3val:0xffff800; valaddr_reg:x12; val_offset:6111*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 6111*FLEN/8, x13, x9, x10)

inst_2059:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x36d4b7 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x0007ff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f36d4b7; op2val:0x0;
op3val:0xf8007ff; valaddr_reg:x12; val_offset:6114*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 6114*FLEN/8, x13, x9, x10)

inst_2060:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x36d4b7 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x7ffc00 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f36d4b7; op2val:0x0;
op3val:0xffffc00; valaddr_reg:x12; val_offset:6117*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 6117*FLEN/8, x13, x9, x10)

inst_2061:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x36d4b7 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x0003ff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f36d4b7; op2val:0x0;
op3val:0xf8003ff; valaddr_reg:x12; val_offset:6120*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 6120*FLEN/8, x13, x9, x10)

inst_2062:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x36d4b7 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x7ffe00 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f36d4b7; op2val:0x0;
op3val:0xffffe00; valaddr_reg:x12; val_offset:6123*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 6123*FLEN/8, x13, x9, x10)

inst_2063:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x36d4b7 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x0001ff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f36d4b7; op2val:0x0;
op3val:0xf8001ff; valaddr_reg:x12; val_offset:6126*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 6126*FLEN/8, x13, x9, x10)

inst_2064:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x36d4b7 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x7fff00 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f36d4b7; op2val:0x0;
op3val:0xfffff00; valaddr_reg:x12; val_offset:6129*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 6129*FLEN/8, x13, x9, x10)

inst_2065:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x36d4b7 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x0000ff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f36d4b7; op2val:0x0;
op3val:0xf8000ff; valaddr_reg:x12; val_offset:6132*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 6132*FLEN/8, x13, x9, x10)

inst_2066:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x36d4b7 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x7fff80 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f36d4b7; op2val:0x0;
op3val:0xfffff80; valaddr_reg:x12; val_offset:6135*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 6135*FLEN/8, x13, x9, x10)

inst_2067:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x36d4b7 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x00007f and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f36d4b7; op2val:0x0;
op3val:0xf80007f; valaddr_reg:x12; val_offset:6138*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 6138*FLEN/8, x13, x9, x10)

inst_2068:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x36d4b7 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x7fffc0 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f36d4b7; op2val:0x0;
op3val:0xfffffc0; valaddr_reg:x12; val_offset:6141*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 6141*FLEN/8, x13, x9, x10)

inst_2069:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x36d4b7 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x00003f and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f36d4b7; op2val:0x0;
op3val:0xf80003f; valaddr_reg:x12; val_offset:6144*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 6144*FLEN/8, x13, x9, x10)

inst_2070:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x36d4b7 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x7fffe0 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f36d4b7; op2val:0x0;
op3val:0xfffffe0; valaddr_reg:x12; val_offset:6147*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 6147*FLEN/8, x13, x9, x10)

inst_2071:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x36d4b7 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x00001f and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f36d4b7; op2val:0x0;
op3val:0xf80001f; valaddr_reg:x12; val_offset:6150*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 6150*FLEN/8, x13, x9, x10)

RVTEST_SIGBASE(x9,signature_x9_16)
inst_2072:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x36d4b7 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x7ffff0 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f36d4b7; op2val:0x0;
op3val:0xffffff0; valaddr_reg:x12; val_offset:6153*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 6153*FLEN/8, x13, x9, x10)

inst_2073:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x36d4b7 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x00000f and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f36d4b7; op2val:0x0;
op3val:0xf80000f; valaddr_reg:x12; val_offset:6156*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 6156*FLEN/8, x13, x9, x10)

inst_2074:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x36d4b7 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x7ffff8 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f36d4b7; op2val:0x0;
op3val:0xffffff8; valaddr_reg:x12; val_offset:6159*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 6159*FLEN/8, x13, x9, x10)

inst_2075:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x36d4b7 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x000007 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f36d4b7; op2val:0x0;
op3val:0xf800007; valaddr_reg:x12; val_offset:6162*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 6162*FLEN/8, x13, x9, x10)

inst_2076:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x36d4b7 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x7ffffc and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f36d4b7; op2val:0x0;
op3val:0xffffffc; valaddr_reg:x12; val_offset:6165*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 6165*FLEN/8, x13, x9, x10)

inst_2077:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x36d4b7 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x000003 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f36d4b7; op2val:0x0;
op3val:0xf800003; valaddr_reg:x12; val_offset:6168*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 6168*FLEN/8, x13, x9, x10)

inst_2078:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x36d4b7 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x7ffffe and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f36d4b7; op2val:0x0;
op3val:0xffffffe; valaddr_reg:x12; val_offset:6171*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 6171*FLEN/8, x13, x9, x10)

inst_2079:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x36d4b7 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f36d4b7; op2val:0x0;
op3val:0xf800001; valaddr_reg:x12; val_offset:6174*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 6174*FLEN/8, x13, x9, x10)

inst_2080:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x36d4b7 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x7ffff8 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f36d4b7; op2val:0x0;
op3val:0x7ffff8; valaddr_reg:x12; val_offset:6177*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 6177*FLEN/8, x13, x9, x10)

inst_2081:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x36d4b7 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000007 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f36d4b7; op2val:0x0;
op3val:0x7; valaddr_reg:x12; val_offset:6180*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 6180*FLEN/8, x13, x9, x10)

inst_2082:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x36d4b7 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x7ffffc and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f36d4b7; op2val:0x0;
op3val:0x7ffffc; valaddr_reg:x12; val_offset:6183*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 6183*FLEN/8, x13, x9, x10)

inst_2083:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x36d4b7 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000003 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f36d4b7; op2val:0x0;
op3val:0x3; valaddr_reg:x12; val_offset:6186*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 6186*FLEN/8, x13, x9, x10)

inst_2084:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x36d4b7 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x7ffffe and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f36d4b7; op2val:0x0;
op3val:0x7ffffe; valaddr_reg:x12; val_offset:6189*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 6189*FLEN/8, x13, x9, x10)

inst_2085:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x36d4b7 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f36d4b7; op2val:0x0;
op3val:0x1; valaddr_reg:x12; val_offset:6192*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 6192*FLEN/8, x13, x9, x10)

inst_2086:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x36d4b7 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x36db6d and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f36d4b7; op2val:0x0;
op3val:0x36db6d; valaddr_reg:x12; val_offset:6195*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 6195*FLEN/8, x13, x9, x10)

inst_2087:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x36d4b7 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x6db6db and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f36d4b7; op2val:0x0;
op3val:0x6db6db; valaddr_reg:x12; val_offset:6198*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 6198*FLEN/8, x13, x9, x10)

inst_2088:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x36d4b7 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x199999 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f36d4b7; op2val:0x0;
op3val:0x199999; valaddr_reg:x12; val_offset:6201*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 6201*FLEN/8, x13, x9, x10)

inst_2089:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x36d4b7 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x666666 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f36d4b7; op2val:0x0;
op3val:0x666666; valaddr_reg:x12; val_offset:6204*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 6204*FLEN/8, x13, x9, x10)

inst_2090:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x36d4b7 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x3bbbbb and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f36d4b7; op2val:0x0;
op3val:0x3bbbbb; valaddr_reg:x12; val_offset:6207*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 6207*FLEN/8, x13, x9, x10)

inst_2091:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x36d4b7 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x444444 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f36d4b7; op2val:0x0;
op3val:0x444444; valaddr_reg:x12; val_offset:6210*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 6210*FLEN/8, x13, x9, x10)

inst_2092:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x36d4b7 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x249249 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f36d4b7; op2val:0x0;
op3val:0x249249; valaddr_reg:x12; val_offset:6213*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 6213*FLEN/8, x13, x9, x10)

inst_2093:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x36d4b7 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x5b6db6 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f36d4b7; op2val:0x0;
op3val:0x5b6db6; valaddr_reg:x12; val_offset:6216*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 6216*FLEN/8, x13, x9, x10)

inst_2094:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x36d4b7 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x333333 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f36d4b7; op2val:0x0;
op3val:0x333333; valaddr_reg:x12; val_offset:6219*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 6219*FLEN/8, x13, x9, x10)

inst_2095:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x36d4b7 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x4ccccc and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f36d4b7; op2val:0x0;
op3val:0x4ccccc; valaddr_reg:x12; val_offset:6222*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 6222*FLEN/8, x13, x9, x10)

inst_2096:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x31e3a6 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x20 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f31e3a6; op2val:0x0;
op3val:0x10000000; valaddr_reg:x12; val_offset:6225*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 6225*FLEN/8, x13, x9, x10)

inst_2097:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x31e3a6 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x20 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f31e3a6; op2val:0x0;
op3val:0x107fffff; valaddr_reg:x12; val_offset:6228*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 6228*FLEN/8, x13, x9, x10)

inst_2098:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x31e3a6 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x20 and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f31e3a6; op2val:0x0;
op3val:0x10400000; valaddr_reg:x12; val_offset:6231*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 6231*FLEN/8, x13, x9, x10)

inst_2099:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x31e3a6 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x20 and fm3 == 0x3fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f31e3a6; op2val:0x0;
op3val:0x103fffff; valaddr_reg:x12; val_offset:6234*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 6234*FLEN/8, x13, x9, x10)

inst_2100:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x31e3a6 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x20 and fm3 == 0x600000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f31e3a6; op2val:0x0;
op3val:0x10600000; valaddr_reg:x12; val_offset:6237*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 6237*FLEN/8, x13, x9, x10)

inst_2101:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x31e3a6 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x20 and fm3 == 0x1fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f31e3a6; op2val:0x0;
op3val:0x101fffff; valaddr_reg:x12; val_offset:6240*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 6240*FLEN/8, x13, x9, x10)

inst_2102:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x31e3a6 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x20 and fm3 == 0x700000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f31e3a6; op2val:0x0;
op3val:0x10700000; valaddr_reg:x12; val_offset:6243*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 6243*FLEN/8, x13, x9, x10)

inst_2103:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x31e3a6 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x20 and fm3 == 0x0fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f31e3a6; op2val:0x0;
op3val:0x100fffff; valaddr_reg:x12; val_offset:6246*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 6246*FLEN/8, x13, x9, x10)

inst_2104:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x31e3a6 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x20 and fm3 == 0x780000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f31e3a6; op2val:0x0;
op3val:0x10780000; valaddr_reg:x12; val_offset:6249*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 6249*FLEN/8, x13, x9, x10)

inst_2105:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x31e3a6 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x20 and fm3 == 0x07ffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f31e3a6; op2val:0x0;
op3val:0x1007ffff; valaddr_reg:x12; val_offset:6252*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 6252*FLEN/8, x13, x9, x10)

inst_2106:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x31e3a6 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x20 and fm3 == 0x7c0000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f31e3a6; op2val:0x0;
op3val:0x107c0000; valaddr_reg:x12; val_offset:6255*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 6255*FLEN/8, x13, x9, x10)

inst_2107:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x31e3a6 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x20 and fm3 == 0x03ffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f31e3a6; op2val:0x0;
op3val:0x1003ffff; valaddr_reg:x12; val_offset:6258*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 6258*FLEN/8, x13, x9, x10)

inst_2108:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x31e3a6 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x20 and fm3 == 0x7e0000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f31e3a6; op2val:0x0;
op3val:0x107e0000; valaddr_reg:x12; val_offset:6261*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 6261*FLEN/8, x13, x9, x10)

inst_2109:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x31e3a6 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x20 and fm3 == 0x01ffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f31e3a6; op2val:0x0;
op3val:0x1001ffff; valaddr_reg:x12; val_offset:6264*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 6264*FLEN/8, x13, x9, x10)

inst_2110:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x31e3a6 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x20 and fm3 == 0x7f0000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f31e3a6; op2val:0x0;
op3val:0x107f0000; valaddr_reg:x12; val_offset:6267*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 6267*FLEN/8, x13, x9, x10)

inst_2111:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x31e3a6 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x20 and fm3 == 0x00ffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f31e3a6; op2val:0x0;
op3val:0x1000ffff; valaddr_reg:x12; val_offset:6270*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 6270*FLEN/8, x13, x9, x10)

inst_2112:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x31e3a6 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x20 and fm3 == 0x7f8000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f31e3a6; op2val:0x0;
op3val:0x107f8000; valaddr_reg:x12; val_offset:6273*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 6273*FLEN/8, x13, x9, x10)

inst_2113:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x31e3a6 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x20 and fm3 == 0x007fff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f31e3a6; op2val:0x0;
op3val:0x10007fff; valaddr_reg:x12; val_offset:6276*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 6276*FLEN/8, x13, x9, x10)

inst_2114:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x31e3a6 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x20 and fm3 == 0x7fc000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f31e3a6; op2val:0x0;
op3val:0x107fc000; valaddr_reg:x12; val_offset:6279*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 6279*FLEN/8, x13, x9, x10)

inst_2115:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x31e3a6 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x20 and fm3 == 0x003fff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f31e3a6; op2val:0x0;
op3val:0x10003fff; valaddr_reg:x12; val_offset:6282*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 6282*FLEN/8, x13, x9, x10)

inst_2116:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x31e3a6 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x20 and fm3 == 0x7fe000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f31e3a6; op2val:0x0;
op3val:0x107fe000; valaddr_reg:x12; val_offset:6285*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 6285*FLEN/8, x13, x9, x10)

inst_2117:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x31e3a6 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x20 and fm3 == 0x001fff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f31e3a6; op2val:0x0;
op3val:0x10001fff; valaddr_reg:x12; val_offset:6288*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 6288*FLEN/8, x13, x9, x10)

inst_2118:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x31e3a6 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x20 and fm3 == 0x7ff000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f31e3a6; op2val:0x0;
op3val:0x107ff000; valaddr_reg:x12; val_offset:6291*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 6291*FLEN/8, x13, x9, x10)

inst_2119:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x31e3a6 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x20 and fm3 == 0x000fff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f31e3a6; op2val:0x0;
op3val:0x10000fff; valaddr_reg:x12; val_offset:6294*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 6294*FLEN/8, x13, x9, x10)

inst_2120:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x31e3a6 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x20 and fm3 == 0x7ff800 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f31e3a6; op2val:0x0;
op3val:0x107ff800; valaddr_reg:x12; val_offset:6297*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 6297*FLEN/8, x13, x9, x10)

inst_2121:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x31e3a6 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x20 and fm3 == 0x0007ff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f31e3a6; op2val:0x0;
op3val:0x100007ff; valaddr_reg:x12; val_offset:6300*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 6300*FLEN/8, x13, x9, x10)

inst_2122:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x31e3a6 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x20 and fm3 == 0x7ffc00 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f31e3a6; op2val:0x0;
op3val:0x107ffc00; valaddr_reg:x12; val_offset:6303*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 6303*FLEN/8, x13, x9, x10)

inst_2123:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x31e3a6 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x20 and fm3 == 0x0003ff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f31e3a6; op2val:0x0;
op3val:0x100003ff; valaddr_reg:x12; val_offset:6306*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 6306*FLEN/8, x13, x9, x10)

inst_2124:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x31e3a6 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x20 and fm3 == 0x7ffe00 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f31e3a6; op2val:0x0;
op3val:0x107ffe00; valaddr_reg:x12; val_offset:6309*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 6309*FLEN/8, x13, x9, x10)

inst_2125:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x31e3a6 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x20 and fm3 == 0x0001ff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f31e3a6; op2val:0x0;
op3val:0x100001ff; valaddr_reg:x12; val_offset:6312*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 6312*FLEN/8, x13, x9, x10)

inst_2126:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x31e3a6 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x20 and fm3 == 0x7fff00 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f31e3a6; op2val:0x0;
op3val:0x107fff00; valaddr_reg:x12; val_offset:6315*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 6315*FLEN/8, x13, x9, x10)

inst_2127:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x31e3a6 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x20 and fm3 == 0x0000ff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f31e3a6; op2val:0x0;
op3val:0x100000ff; valaddr_reg:x12; val_offset:6318*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 6318*FLEN/8, x13, x9, x10)

inst_2128:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x31e3a6 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x20 and fm3 == 0x7fff80 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f31e3a6; op2val:0x0;
op3val:0x107fff80; valaddr_reg:x12; val_offset:6321*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 6321*FLEN/8, x13, x9, x10)

inst_2129:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x31e3a6 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x20 and fm3 == 0x00007f and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f31e3a6; op2val:0x0;
op3val:0x1000007f; valaddr_reg:x12; val_offset:6324*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 6324*FLEN/8, x13, x9, x10)

inst_2130:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x31e3a6 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x20 and fm3 == 0x7fffc0 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f31e3a6; op2val:0x0;
op3val:0x107fffc0; valaddr_reg:x12; val_offset:6327*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 6327*FLEN/8, x13, x9, x10)

inst_2131:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x31e3a6 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x20 and fm3 == 0x00003f and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f31e3a6; op2val:0x0;
op3val:0x1000003f; valaddr_reg:x12; val_offset:6330*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 6330*FLEN/8, x13, x9, x10)

inst_2132:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x31e3a6 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x20 and fm3 == 0x7fffe0 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f31e3a6; op2val:0x0;
op3val:0x107fffe0; valaddr_reg:x12; val_offset:6333*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 6333*FLEN/8, x13, x9, x10)

inst_2133:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x31e3a6 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x20 and fm3 == 0x00001f and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f31e3a6; op2val:0x0;
op3val:0x1000001f; valaddr_reg:x12; val_offset:6336*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 6336*FLEN/8, x13, x9, x10)

inst_2134:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x31e3a6 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x20 and fm3 == 0x7ffff0 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f31e3a6; op2val:0x0;
op3val:0x107ffff0; valaddr_reg:x12; val_offset:6339*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 6339*FLEN/8, x13, x9, x10)

inst_2135:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x31e3a6 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x20 and fm3 == 0x00000f and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f31e3a6; op2val:0x0;
op3val:0x1000000f; valaddr_reg:x12; val_offset:6342*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 6342*FLEN/8, x13, x9, x10)

inst_2136:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x31e3a6 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x20 and fm3 == 0x7ffff8 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f31e3a6; op2val:0x0;
op3val:0x107ffff8; valaddr_reg:x12; val_offset:6345*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 6345*FLEN/8, x13, x9, x10)

inst_2137:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x31e3a6 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x20 and fm3 == 0x000007 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f31e3a6; op2val:0x0;
op3val:0x10000007; valaddr_reg:x12; val_offset:6348*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 6348*FLEN/8, x13, x9, x10)

inst_2138:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x31e3a6 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x20 and fm3 == 0x7ffffc and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f31e3a6; op2val:0x0;
op3val:0x107ffffc; valaddr_reg:x12; val_offset:6351*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 6351*FLEN/8, x13, x9, x10)

inst_2139:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x31e3a6 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x20 and fm3 == 0x000003 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f31e3a6; op2val:0x0;
op3val:0x10000003; valaddr_reg:x12; val_offset:6354*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 6354*FLEN/8, x13, x9, x10)

inst_2140:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x31e3a6 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x20 and fm3 == 0x7ffffe and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f31e3a6; op2val:0x0;
op3val:0x107ffffe; valaddr_reg:x12; val_offset:6357*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 6357*FLEN/8, x13, x9, x10)

inst_2141:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x31e3a6 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x20 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f31e3a6; op2val:0x0;
op3val:0x10000001; valaddr_reg:x12; val_offset:6360*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 6360*FLEN/8, x13, x9, x10)

inst_2142:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x31e3a6 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x7ffff8 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f31e3a6; op2val:0x0;
op3val:0x7ffff8; valaddr_reg:x12; val_offset:6363*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 6363*FLEN/8, x13, x9, x10)

inst_2143:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x31e3a6 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000007 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f31e3a6; op2val:0x0;
op3val:0x7; valaddr_reg:x12; val_offset:6366*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 6366*FLEN/8, x13, x9, x10)

inst_2144:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x31e3a6 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x7ffffc and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f31e3a6; op2val:0x0;
op3val:0x7ffffc; valaddr_reg:x12; val_offset:6369*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 6369*FLEN/8, x13, x9, x10)

inst_2145:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x31e3a6 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000003 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f31e3a6; op2val:0x0;
op3val:0x3; valaddr_reg:x12; val_offset:6372*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 6372*FLEN/8, x13, x9, x10)

inst_2146:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x31e3a6 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x7ffffe and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f31e3a6; op2val:0x0;
op3val:0x7ffffe; valaddr_reg:x12; val_offset:6375*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 6375*FLEN/8, x13, x9, x10)

inst_2147:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x31e3a6 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f31e3a6; op2val:0x0;
op3val:0x1; valaddr_reg:x12; val_offset:6378*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 6378*FLEN/8, x13, x9, x10)

inst_2148:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x31e3a6 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x36db6d and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f31e3a6; op2val:0x0;
op3val:0x36db6d; valaddr_reg:x12; val_offset:6381*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 6381*FLEN/8, x13, x9, x10)

inst_2149:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x31e3a6 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x6db6db and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f31e3a6; op2val:0x0;
op3val:0x6db6db; valaddr_reg:x12; val_offset:6384*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 6384*FLEN/8, x13, x9, x10)

inst_2150:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x31e3a6 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x199999 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f31e3a6; op2val:0x0;
op3val:0x199999; valaddr_reg:x12; val_offset:6387*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 6387*FLEN/8, x13, x9, x10)

inst_2151:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x31e3a6 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x666666 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f31e3a6; op2val:0x0;
op3val:0x666666; valaddr_reg:x12; val_offset:6390*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 6390*FLEN/8, x13, x9, x10)

inst_2152:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x31e3a6 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x3bbbbb and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f31e3a6; op2val:0x0;
op3val:0x3bbbbb; valaddr_reg:x12; val_offset:6393*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 6393*FLEN/8, x13, x9, x10)

inst_2153:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x31e3a6 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x444444 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f31e3a6; op2val:0x0;
op3val:0x444444; valaddr_reg:x12; val_offset:6396*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 6396*FLEN/8, x13, x9, x10)

inst_2154:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x31e3a6 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x249249 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f31e3a6; op2val:0x0;
op3val:0x249249; valaddr_reg:x12; val_offset:6399*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 6399*FLEN/8, x13, x9, x10)

inst_2155:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x31e3a6 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x5b6db6 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f31e3a6; op2val:0x0;
op3val:0x5b6db6; valaddr_reg:x12; val_offset:6402*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 6402*FLEN/8, x13, x9, x10)

inst_2156:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x31e3a6 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x333333 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f31e3a6; op2val:0x0;
op3val:0x333333; valaddr_reg:x12; val_offset:6405*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 6405*FLEN/8, x13, x9, x10)

inst_2157:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x31e3a6 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x4ccccc and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f31e3a6; op2val:0x0;
op3val:0x4ccccc; valaddr_reg:x12; val_offset:6408*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 6408*FLEN/8, x13, x9, x10)

inst_2158:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x1fd026 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e9fd026; op2val:0x80000000;
op3val:0x80000000; valaddr_reg:x12; val_offset:6411*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 6411*FLEN/8, x13, x9, x10)

inst_2159:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x1fd026 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e9fd026; op2val:0x80000000;
op3val:0x807fffff; valaddr_reg:x12; val_offset:6414*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 6414*FLEN/8, x13, x9, x10)

inst_2160:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x1fd026 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e9fd026; op2val:0x80000000;
op3val:0x80400000; valaddr_reg:x12; val_offset:6417*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 6417*FLEN/8, x13, x9, x10)

inst_2161:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x1fd026 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e9fd026; op2val:0x80000000;
op3val:0x803fffff; valaddr_reg:x12; val_offset:6420*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 6420*FLEN/8, x13, x9, x10)

inst_2162:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x1fd026 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x600000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e9fd026; op2val:0x80000000;
op3val:0x80600000; valaddr_reg:x12; val_offset:6423*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 6423*FLEN/8, x13, x9, x10)

inst_2163:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x1fd026 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x1fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e9fd026; op2val:0x80000000;
op3val:0x801fffff; valaddr_reg:x12; val_offset:6426*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 6426*FLEN/8, x13, x9, x10)

inst_2164:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x1fd026 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x700000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e9fd026; op2val:0x80000000;
op3val:0x80700000; valaddr_reg:x12; val_offset:6429*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 6429*FLEN/8, x13, x9, x10)

inst_2165:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x1fd026 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x0fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e9fd026; op2val:0x80000000;
op3val:0x800fffff; valaddr_reg:x12; val_offset:6432*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 6432*FLEN/8, x13, x9, x10)

inst_2166:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x1fd026 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x780000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e9fd026; op2val:0x80000000;
op3val:0x80780000; valaddr_reg:x12; val_offset:6435*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 6435*FLEN/8, x13, x9, x10)

inst_2167:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x1fd026 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x07ffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e9fd026; op2val:0x80000000;
op3val:0x8007ffff; valaddr_reg:x12; val_offset:6438*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 6438*FLEN/8, x13, x9, x10)

inst_2168:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x1fd026 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7c0000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e9fd026; op2val:0x80000000;
op3val:0x807c0000; valaddr_reg:x12; val_offset:6441*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 6441*FLEN/8, x13, x9, x10)

inst_2169:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x1fd026 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x03ffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e9fd026; op2val:0x80000000;
op3val:0x8003ffff; valaddr_reg:x12; val_offset:6444*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 6444*FLEN/8, x13, x9, x10)

inst_2170:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x1fd026 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7e0000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e9fd026; op2val:0x80000000;
op3val:0x807e0000; valaddr_reg:x12; val_offset:6447*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 6447*FLEN/8, x13, x9, x10)

inst_2171:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x1fd026 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x01ffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e9fd026; op2val:0x80000000;
op3val:0x8001ffff; valaddr_reg:x12; val_offset:6450*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 6450*FLEN/8, x13, x9, x10)

inst_2172:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x1fd026 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7f0000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e9fd026; op2val:0x80000000;
op3val:0x807f0000; valaddr_reg:x12; val_offset:6453*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 6453*FLEN/8, x13, x9, x10)

inst_2173:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x1fd026 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x00ffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e9fd026; op2val:0x80000000;
op3val:0x8000ffff; valaddr_reg:x12; val_offset:6456*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 6456*FLEN/8, x13, x9, x10)

inst_2174:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x1fd026 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7f8000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e9fd026; op2val:0x80000000;
op3val:0x807f8000; valaddr_reg:x12; val_offset:6459*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 6459*FLEN/8, x13, x9, x10)

inst_2175:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x1fd026 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x007fff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e9fd026; op2val:0x80000000;
op3val:0x80007fff; valaddr_reg:x12; val_offset:6462*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 6462*FLEN/8, x13, x9, x10)

inst_2176:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x1fd026 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7fc000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e9fd026; op2val:0x80000000;
op3val:0x807fc000; valaddr_reg:x12; val_offset:6465*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 6465*FLEN/8, x13, x9, x10)

inst_2177:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x1fd026 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x003fff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e9fd026; op2val:0x80000000;
op3val:0x80003fff; valaddr_reg:x12; val_offset:6468*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 6468*FLEN/8, x13, x9, x10)

inst_2178:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x1fd026 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7fe000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e9fd026; op2val:0x80000000;
op3val:0x807fe000; valaddr_reg:x12; val_offset:6471*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 6471*FLEN/8, x13, x9, x10)

inst_2179:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x1fd026 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x001fff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e9fd026; op2val:0x80000000;
op3val:0x80001fff; valaddr_reg:x12; val_offset:6474*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 6474*FLEN/8, x13, x9, x10)

inst_2180:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x1fd026 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7ff000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e9fd026; op2val:0x80000000;
op3val:0x807ff000; valaddr_reg:x12; val_offset:6477*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 6477*FLEN/8, x13, x9, x10)

inst_2181:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x1fd026 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000fff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e9fd026; op2val:0x80000000;
op3val:0x80000fff; valaddr_reg:x12; val_offset:6480*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 6480*FLEN/8, x13, x9, x10)

inst_2182:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x1fd026 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7ff800 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e9fd026; op2val:0x80000000;
op3val:0x807ff800; valaddr_reg:x12; val_offset:6483*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 6483*FLEN/8, x13, x9, x10)

inst_2183:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x1fd026 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x0007ff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e9fd026; op2val:0x80000000;
op3val:0x800007ff; valaddr_reg:x12; val_offset:6486*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 6486*FLEN/8, x13, x9, x10)

inst_2184:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x1fd026 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7ffc00 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e9fd026; op2val:0x80000000;
op3val:0x807ffc00; valaddr_reg:x12; val_offset:6489*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 6489*FLEN/8, x13, x9, x10)

inst_2185:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x1fd026 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x0003ff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e9fd026; op2val:0x80000000;
op3val:0x800003ff; valaddr_reg:x12; val_offset:6492*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 6492*FLEN/8, x13, x9, x10)

inst_2186:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x1fd026 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7ffe00 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e9fd026; op2val:0x80000000;
op3val:0x807ffe00; valaddr_reg:x12; val_offset:6495*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 6495*FLEN/8, x13, x9, x10)

inst_2187:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x1fd026 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x0001ff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e9fd026; op2val:0x80000000;
op3val:0x800001ff; valaddr_reg:x12; val_offset:6498*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 6498*FLEN/8, x13, x9, x10)

inst_2188:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x1fd026 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7fff00 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e9fd026; op2val:0x80000000;
op3val:0x807fff00; valaddr_reg:x12; val_offset:6501*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 6501*FLEN/8, x13, x9, x10)

inst_2189:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x1fd026 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x0000ff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e9fd026; op2val:0x80000000;
op3val:0x800000ff; valaddr_reg:x12; val_offset:6504*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 6504*FLEN/8, x13, x9, x10)

inst_2190:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x1fd026 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7fff80 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e9fd026; op2val:0x80000000;
op3val:0x807fff80; valaddr_reg:x12; val_offset:6507*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 6507*FLEN/8, x13, x9, x10)

inst_2191:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x1fd026 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x00007f and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e9fd026; op2val:0x80000000;
op3val:0x8000007f; valaddr_reg:x12; val_offset:6510*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 6510*FLEN/8, x13, x9, x10)

inst_2192:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x1fd026 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7fffc0 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e9fd026; op2val:0x80000000;
op3val:0x807fffc0; valaddr_reg:x12; val_offset:6513*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 6513*FLEN/8, x13, x9, x10)

inst_2193:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x1fd026 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x00003f and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e9fd026; op2val:0x80000000;
op3val:0x8000003f; valaddr_reg:x12; val_offset:6516*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 6516*FLEN/8, x13, x9, x10)

inst_2194:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x1fd026 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7fffe0 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e9fd026; op2val:0x80000000;
op3val:0x807fffe0; valaddr_reg:x12; val_offset:6519*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 6519*FLEN/8, x13, x9, x10)

inst_2195:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x1fd026 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x00001f and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e9fd026; op2val:0x80000000;
op3val:0x8000001f; valaddr_reg:x12; val_offset:6522*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 6522*FLEN/8, x13, x9, x10)

inst_2196:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x1fd026 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7ffff0 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e9fd026; op2val:0x80000000;
op3val:0x807ffff0; valaddr_reg:x12; val_offset:6525*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 6525*FLEN/8, x13, x9, x10)

inst_2197:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x1fd026 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x00000f and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e9fd026; op2val:0x80000000;
op3val:0x8000000f; valaddr_reg:x12; val_offset:6528*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 6528*FLEN/8, x13, x9, x10)

inst_2198:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x1fd026 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7ffff8 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e9fd026; op2val:0x80000000;
op3val:0x807ffff8; valaddr_reg:x12; val_offset:6531*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 6531*FLEN/8, x13, x9, x10)

inst_2199:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x1fd026 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000007 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e9fd026; op2val:0x80000000;
op3val:0x80000007; valaddr_reg:x12; val_offset:6534*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 6534*FLEN/8, x13, x9, x10)

RVTEST_SIGBASE(x9,signature_x9_17)
inst_2200:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x1fd026 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7ffffc and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e9fd026; op2val:0x80000000;
op3val:0x807ffffc; valaddr_reg:x12; val_offset:6537*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 6537*FLEN/8, x13, x9, x10)

inst_2201:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x1fd026 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000003 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e9fd026; op2val:0x80000000;
op3val:0x80000003; valaddr_reg:x12; val_offset:6540*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 6540*FLEN/8, x13, x9, x10)

inst_2202:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x1fd026 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7ffffe and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e9fd026; op2val:0x80000000;
op3val:0x807ffffe; valaddr_reg:x12; val_offset:6543*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 6543*FLEN/8, x13, x9, x10)

inst_2203:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x1fd026 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e9fd026; op2val:0x80000000;
op3val:0x80000001; valaddr_reg:x12; val_offset:6546*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 6546*FLEN/8, x13, x9, x10)

inst_2204:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x1fd026 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x36db6d and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e9fd026; op2val:0x80000000;
op3val:0x8036db6d; valaddr_reg:x12; val_offset:6549*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 6549*FLEN/8, x13, x9, x10)

inst_2205:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x1fd026 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x6db6db and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e9fd026; op2val:0x80000000;
op3val:0x806db6db; valaddr_reg:x12; val_offset:6552*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 6552*FLEN/8, x13, x9, x10)

inst_2206:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x1fd026 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x199999 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e9fd026; op2val:0x80000000;
op3val:0x80199999; valaddr_reg:x12; val_offset:6555*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 6555*FLEN/8, x13, x9, x10)

inst_2207:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x1fd026 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x666666 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e9fd026; op2val:0x80000000;
op3val:0x80666666; valaddr_reg:x12; val_offset:6558*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 6558*FLEN/8, x13, x9, x10)

inst_2208:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x1fd026 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3bbbbb and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e9fd026; op2val:0x80000000;
op3val:0x803bbbbb; valaddr_reg:x12; val_offset:6561*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 6561*FLEN/8, x13, x9, x10)

inst_2209:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x1fd026 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x444444 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e9fd026; op2val:0x80000000;
op3val:0x80444444; valaddr_reg:x12; val_offset:6564*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 6564*FLEN/8, x13, x9, x10)

inst_2210:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x1fd026 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x249249 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e9fd026; op2val:0x80000000;
op3val:0x80249249; valaddr_reg:x12; val_offset:6567*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 6567*FLEN/8, x13, x9, x10)

inst_2211:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x1fd026 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x5b6db6 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e9fd026; op2val:0x80000000;
op3val:0x805b6db6; valaddr_reg:x12; val_offset:6570*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 6570*FLEN/8, x13, x9, x10)

inst_2212:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x1fd026 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x333333 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e9fd026; op2val:0x80000000;
op3val:0x80333333; valaddr_reg:x12; val_offset:6573*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 6573*FLEN/8, x13, x9, x10)

inst_2213:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x1fd026 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x4ccccc and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e9fd026; op2val:0x80000000;
op3val:0x804ccccc; valaddr_reg:x12; val_offset:6576*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 6576*FLEN/8, x13, x9, x10)

inst_2214:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x310f69 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xaf and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f310f69; op2val:0x80000000;
op3val:0xd7800000; valaddr_reg:x12; val_offset:6579*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 6579*FLEN/8, x13, x9, x10)

inst_2215:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x310f69 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xaf and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f310f69; op2val:0x80000000;
op3val:0xd7ffffff; valaddr_reg:x12; val_offset:6582*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 6582*FLEN/8, x13, x9, x10)

inst_2216:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x310f69 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xaf and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f310f69; op2val:0x80000000;
op3val:0xd7c00000; valaddr_reg:x12; val_offset:6585*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 6585*FLEN/8, x13, x9, x10)

inst_2217:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x310f69 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xaf and fm3 == 0x3fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f310f69; op2val:0x80000000;
op3val:0xd7bfffff; valaddr_reg:x12; val_offset:6588*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 6588*FLEN/8, x13, x9, x10)

inst_2218:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x310f69 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xaf and fm3 == 0x600000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f310f69; op2val:0x80000000;
op3val:0xd7e00000; valaddr_reg:x12; val_offset:6591*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 6591*FLEN/8, x13, x9, x10)

inst_2219:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x310f69 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xaf and fm3 == 0x1fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f310f69; op2val:0x80000000;
op3val:0xd79fffff; valaddr_reg:x12; val_offset:6594*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 6594*FLEN/8, x13, x9, x10)

inst_2220:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x310f69 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xaf and fm3 == 0x700000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f310f69; op2val:0x80000000;
op3val:0xd7f00000; valaddr_reg:x12; val_offset:6597*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 6597*FLEN/8, x13, x9, x10)

inst_2221:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x310f69 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xaf and fm3 == 0x0fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f310f69; op2val:0x80000000;
op3val:0xd78fffff; valaddr_reg:x12; val_offset:6600*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 6600*FLEN/8, x13, x9, x10)

inst_2222:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x310f69 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xaf and fm3 == 0x780000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f310f69; op2val:0x80000000;
op3val:0xd7f80000; valaddr_reg:x12; val_offset:6603*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 6603*FLEN/8, x13, x9, x10)

inst_2223:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x310f69 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xaf and fm3 == 0x07ffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f310f69; op2val:0x80000000;
op3val:0xd787ffff; valaddr_reg:x12; val_offset:6606*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 6606*FLEN/8, x13, x9, x10)

inst_2224:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x310f69 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xaf and fm3 == 0x7c0000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f310f69; op2val:0x80000000;
op3val:0xd7fc0000; valaddr_reg:x12; val_offset:6609*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 6609*FLEN/8, x13, x9, x10)

inst_2225:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x310f69 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xaf and fm3 == 0x03ffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f310f69; op2val:0x80000000;
op3val:0xd783ffff; valaddr_reg:x12; val_offset:6612*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 6612*FLEN/8, x13, x9, x10)

inst_2226:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x310f69 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xaf and fm3 == 0x7e0000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f310f69; op2val:0x80000000;
op3val:0xd7fe0000; valaddr_reg:x12; val_offset:6615*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 6615*FLEN/8, x13, x9, x10)

inst_2227:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x310f69 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xaf and fm3 == 0x01ffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f310f69; op2val:0x80000000;
op3val:0xd781ffff; valaddr_reg:x12; val_offset:6618*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 6618*FLEN/8, x13, x9, x10)

inst_2228:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x310f69 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xaf and fm3 == 0x7f0000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f310f69; op2val:0x80000000;
op3val:0xd7ff0000; valaddr_reg:x12; val_offset:6621*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 6621*FLEN/8, x13, x9, x10)

inst_2229:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x310f69 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xaf and fm3 == 0x00ffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f310f69; op2val:0x80000000;
op3val:0xd780ffff; valaddr_reg:x12; val_offset:6624*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 6624*FLEN/8, x13, x9, x10)

inst_2230:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x310f69 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xaf and fm3 == 0x7f8000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f310f69; op2val:0x80000000;
op3val:0xd7ff8000; valaddr_reg:x12; val_offset:6627*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 6627*FLEN/8, x13, x9, x10)

inst_2231:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x310f69 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xaf and fm3 == 0x007fff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f310f69; op2val:0x80000000;
op3val:0xd7807fff; valaddr_reg:x12; val_offset:6630*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 6630*FLEN/8, x13, x9, x10)

inst_2232:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x310f69 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xaf and fm3 == 0x7fc000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f310f69; op2val:0x80000000;
op3val:0xd7ffc000; valaddr_reg:x12; val_offset:6633*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 6633*FLEN/8, x13, x9, x10)

inst_2233:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x310f69 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xaf and fm3 == 0x003fff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f310f69; op2val:0x80000000;
op3val:0xd7803fff; valaddr_reg:x12; val_offset:6636*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 6636*FLEN/8, x13, x9, x10)

inst_2234:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x310f69 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xaf and fm3 == 0x7fe000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f310f69; op2val:0x80000000;
op3val:0xd7ffe000; valaddr_reg:x12; val_offset:6639*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 6639*FLEN/8, x13, x9, x10)

inst_2235:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x310f69 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xaf and fm3 == 0x001fff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f310f69; op2val:0x80000000;
op3val:0xd7801fff; valaddr_reg:x12; val_offset:6642*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 6642*FLEN/8, x13, x9, x10)

inst_2236:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x310f69 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xaf and fm3 == 0x7ff000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f310f69; op2val:0x80000000;
op3val:0xd7fff000; valaddr_reg:x12; val_offset:6645*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 6645*FLEN/8, x13, x9, x10)

inst_2237:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x310f69 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xaf and fm3 == 0x000fff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f310f69; op2val:0x80000000;
op3val:0xd7800fff; valaddr_reg:x12; val_offset:6648*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 6648*FLEN/8, x13, x9, x10)

inst_2238:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x310f69 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xaf and fm3 == 0x7ff800 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f310f69; op2val:0x80000000;
op3val:0xd7fff800; valaddr_reg:x12; val_offset:6651*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 6651*FLEN/8, x13, x9, x10)

inst_2239:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x310f69 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xaf and fm3 == 0x0007ff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f310f69; op2val:0x80000000;
op3val:0xd78007ff; valaddr_reg:x12; val_offset:6654*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 6654*FLEN/8, x13, x9, x10)

inst_2240:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x310f69 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xaf and fm3 == 0x7ffc00 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f310f69; op2val:0x80000000;
op3val:0xd7fffc00; valaddr_reg:x12; val_offset:6657*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 6657*FLEN/8, x13, x9, x10)

inst_2241:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x310f69 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xaf and fm3 == 0x0003ff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f310f69; op2val:0x80000000;
op3val:0xd78003ff; valaddr_reg:x12; val_offset:6660*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 6660*FLEN/8, x13, x9, x10)

inst_2242:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x310f69 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xaf and fm3 == 0x7ffe00 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f310f69; op2val:0x80000000;
op3val:0xd7fffe00; valaddr_reg:x12; val_offset:6663*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 6663*FLEN/8, x13, x9, x10)

inst_2243:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x310f69 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xaf and fm3 == 0x0001ff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f310f69; op2val:0x80000000;
op3val:0xd78001ff; valaddr_reg:x12; val_offset:6666*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 6666*FLEN/8, x13, x9, x10)

inst_2244:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x310f69 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xaf and fm3 == 0x7fff00 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f310f69; op2val:0x80000000;
op3val:0xd7ffff00; valaddr_reg:x12; val_offset:6669*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 6669*FLEN/8, x13, x9, x10)

inst_2245:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x310f69 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xaf and fm3 == 0x0000ff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f310f69; op2val:0x80000000;
op3val:0xd78000ff; valaddr_reg:x12; val_offset:6672*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 6672*FLEN/8, x13, x9, x10)

inst_2246:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x310f69 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xaf and fm3 == 0x7fff80 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f310f69; op2val:0x80000000;
op3val:0xd7ffff80; valaddr_reg:x12; val_offset:6675*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 6675*FLEN/8, x13, x9, x10)

inst_2247:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x310f69 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xaf and fm3 == 0x00007f and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f310f69; op2val:0x80000000;
op3val:0xd780007f; valaddr_reg:x12; val_offset:6678*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 6678*FLEN/8, x13, x9, x10)

inst_2248:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x310f69 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xaf and fm3 == 0x7fffc0 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f310f69; op2val:0x80000000;
op3val:0xd7ffffc0; valaddr_reg:x12; val_offset:6681*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 6681*FLEN/8, x13, x9, x10)

inst_2249:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x310f69 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xaf and fm3 == 0x00003f and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f310f69; op2val:0x80000000;
op3val:0xd780003f; valaddr_reg:x12; val_offset:6684*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 6684*FLEN/8, x13, x9, x10)

inst_2250:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x310f69 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xaf and fm3 == 0x7fffe0 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f310f69; op2val:0x80000000;
op3val:0xd7ffffe0; valaddr_reg:x12; val_offset:6687*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 6687*FLEN/8, x13, x9, x10)

inst_2251:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x310f69 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xaf and fm3 == 0x00001f and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f310f69; op2val:0x80000000;
op3val:0xd780001f; valaddr_reg:x12; val_offset:6690*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 6690*FLEN/8, x13, x9, x10)

inst_2252:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x310f69 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xaf and fm3 == 0x7ffff0 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f310f69; op2val:0x80000000;
op3val:0xd7fffff0; valaddr_reg:x12; val_offset:6693*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 6693*FLEN/8, x13, x9, x10)

inst_2253:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x310f69 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xaf and fm3 == 0x00000f and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f310f69; op2val:0x80000000;
op3val:0xd780000f; valaddr_reg:x12; val_offset:6696*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 6696*FLEN/8, x13, x9, x10)

inst_2254:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x310f69 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xaf and fm3 == 0x7ffff8 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f310f69; op2val:0x80000000;
op3val:0xd7fffff8; valaddr_reg:x12; val_offset:6699*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 6699*FLEN/8, x13, x9, x10)

inst_2255:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x310f69 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xaf and fm3 == 0x000007 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f310f69; op2val:0x80000000;
op3val:0xd7800007; valaddr_reg:x12; val_offset:6702*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 6702*FLEN/8, x13, x9, x10)

inst_2256:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x310f69 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xaf and fm3 == 0x7ffffc and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f310f69; op2val:0x80000000;
op3val:0xd7fffffc; valaddr_reg:x12; val_offset:6705*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 6705*FLEN/8, x13, x9, x10)

inst_2257:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x310f69 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xaf and fm3 == 0x000003 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f310f69; op2val:0x80000000;
op3val:0xd7800003; valaddr_reg:x12; val_offset:6708*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 6708*FLEN/8, x13, x9, x10)

inst_2258:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x310f69 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xaf and fm3 == 0x7ffffe and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f310f69; op2val:0x80000000;
op3val:0xd7fffffe; valaddr_reg:x12; val_offset:6711*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 6711*FLEN/8, x13, x9, x10)

inst_2259:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x310f69 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xaf and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f310f69; op2val:0x80000000;
op3val:0xd7800001; valaddr_reg:x12; val_offset:6714*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 6714*FLEN/8, x13, x9, x10)

#endif
RVTEST_CODE_END
RVMODEL_HALT
RVTEST_DATA_BEGIN
.align 4
rvtest_data:
.word 0xbabecafe
.word 0xabecafeb
.word 0xbecafeba
.word 0xecafebab
test_dataset_0:
NAN_BOXED(0,32,FLEN)
NAN_BOXED(5991862,32,FLEN)
NAN_BOXED(2134511176,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(3355443,32,FLEN)
NAN_BOXED(2134511176,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(5033164,32,FLEN)
NAN_BOXED(2131451163,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(192937984,32,FLEN)
NAN_BOXED(2131451163,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(201326591,32,FLEN)
NAN_BOXED(2131451163,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(197132288,32,FLEN)
NAN_BOXED(2131451163,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(197132287,32,FLEN)
NAN_BOXED(2131451163,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(199229440,32,FLEN)
NAN_BOXED(2131451163,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(195035135,32,FLEN)
NAN_BOXED(2131451163,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(200278016,32,FLEN)
NAN_BOXED(2131451163,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(193986559,32,FLEN)
NAN_BOXED(2131451163,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(200802304,32,FLEN)
NAN_BOXED(2131451163,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(193462271,32,FLEN)
NAN_BOXED(2131451163,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(201064448,32,FLEN)
NAN_BOXED(2131451163,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(193200127,32,FLEN)
NAN_BOXED(2131451163,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(201195520,32,FLEN)
NAN_BOXED(2131451163,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(193069055,32,FLEN)
NAN_BOXED(2131451163,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(201261056,32,FLEN)
NAN_BOXED(2131451163,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(193003519,32,FLEN)
NAN_BOXED(2131451163,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(201293824,32,FLEN)
NAN_BOXED(2131451163,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(192970751,32,FLEN)
NAN_BOXED(2131451163,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(201310208,32,FLEN)
NAN_BOXED(2131451163,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(192954367,32,FLEN)
NAN_BOXED(2131451163,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(201318400,32,FLEN)
NAN_BOXED(2131451163,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(192946175,32,FLEN)
NAN_BOXED(2131451163,32,FLEN)
NAN_BOXED(0,32,FLEN)
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NAN_BOXED(2124402726,32,FLEN)
NAN_BOXED(2147483648,32,FLEN)
NAN_BOXED(2147483655,32,FLEN)
NAN_BOXED(2124402726,32,FLEN)
NAN_BOXED(2147483648,32,FLEN)
NAN_BOXED(2155872252,32,FLEN)
NAN_BOXED(2124402726,32,FLEN)
NAN_BOXED(2147483648,32,FLEN)
NAN_BOXED(2147483651,32,FLEN)
NAN_BOXED(2124402726,32,FLEN)
NAN_BOXED(2147483648,32,FLEN)
NAN_BOXED(2155872254,32,FLEN)
NAN_BOXED(2124402726,32,FLEN)
NAN_BOXED(2147483648,32,FLEN)
NAN_BOXED(2147483649,32,FLEN)
NAN_BOXED(2124402726,32,FLEN)
NAN_BOXED(2147483648,32,FLEN)
NAN_BOXED(2151078765,32,FLEN)
NAN_BOXED(2124402726,32,FLEN)
NAN_BOXED(2147483648,32,FLEN)
NAN_BOXED(2154673883,32,FLEN)
NAN_BOXED(2124402726,32,FLEN)
NAN_BOXED(2147483648,32,FLEN)
NAN_BOXED(2149161369,32,FLEN)
NAN_BOXED(2124402726,32,FLEN)
NAN_BOXED(2147483648,32,FLEN)
NAN_BOXED(2154194534,32,FLEN)
NAN_BOXED(2124402726,32,FLEN)
NAN_BOXED(2147483648,32,FLEN)
NAN_BOXED(2151398331,32,FLEN)
NAN_BOXED(2124402726,32,FLEN)
NAN_BOXED(2147483648,32,FLEN)
NAN_BOXED(2151957572,32,FLEN)
NAN_BOXED(2124402726,32,FLEN)
NAN_BOXED(2147483648,32,FLEN)
NAN_BOXED(2149880393,32,FLEN)
NAN_BOXED(2124402726,32,FLEN)
NAN_BOXED(2147483648,32,FLEN)
NAN_BOXED(2153475510,32,FLEN)
NAN_BOXED(2124402726,32,FLEN)
NAN_BOXED(2147483648,32,FLEN)
NAN_BOXED(2150839091,32,FLEN)
NAN_BOXED(2124402726,32,FLEN)
NAN_BOXED(2147483648,32,FLEN)
NAN_BOXED(2152516812,32,FLEN)
NAN_BOXED(2133921641,32,FLEN)
NAN_BOXED(2147483648,32,FLEN)
NAN_BOXED(3615490048,32,FLEN)
NAN_BOXED(2133921641,32,FLEN)
NAN_BOXED(2147483648,32,FLEN)
NAN_BOXED(3623878655,32,FLEN)
NAN_BOXED(2133921641,32,FLEN)
NAN_BOXED(2147483648,32,FLEN)
NAN_BOXED(3619684352,32,FLEN)
NAN_BOXED(2133921641,32,FLEN)
NAN_BOXED(2147483648,32,FLEN)
NAN_BOXED(3619684351,32,FLEN)
NAN_BOXED(2133921641,32,FLEN)
NAN_BOXED(2147483648,32,FLEN)
NAN_BOXED(3621781504,32,FLEN)
NAN_BOXED(2133921641,32,FLEN)
NAN_BOXED(2147483648,32,FLEN)
NAN_BOXED(3617587199,32,FLEN)
NAN_BOXED(2133921641,32,FLEN)
NAN_BOXED(2147483648,32,FLEN)
NAN_BOXED(3622830080,32,FLEN)
NAN_BOXED(2133921641,32,FLEN)
NAN_BOXED(2147483648,32,FLEN)
NAN_BOXED(3616538623,32,FLEN)
NAN_BOXED(2133921641,32,FLEN)
NAN_BOXED(2147483648,32,FLEN)
NAN_BOXED(3623354368,32,FLEN)
NAN_BOXED(2133921641,32,FLEN)
NAN_BOXED(2147483648,32,FLEN)
NAN_BOXED(3616014335,32,FLEN)
NAN_BOXED(2133921641,32,FLEN)
NAN_BOXED(2147483648,32,FLEN)
NAN_BOXED(3623616512,32,FLEN)
NAN_BOXED(2133921641,32,FLEN)
NAN_BOXED(2147483648,32,FLEN)
NAN_BOXED(3615752191,32,FLEN)
NAN_BOXED(2133921641,32,FLEN)
NAN_BOXED(2147483648,32,FLEN)
NAN_BOXED(3623747584,32,FLEN)
NAN_BOXED(2133921641,32,FLEN)
NAN_BOXED(2147483648,32,FLEN)
NAN_BOXED(3615621119,32,FLEN)
NAN_BOXED(2133921641,32,FLEN)
NAN_BOXED(2147483648,32,FLEN)
NAN_BOXED(3623813120,32,FLEN)
NAN_BOXED(2133921641,32,FLEN)
NAN_BOXED(2147483648,32,FLEN)
NAN_BOXED(3615555583,32,FLEN)
NAN_BOXED(2133921641,32,FLEN)
NAN_BOXED(2147483648,32,FLEN)
NAN_BOXED(3623845888,32,FLEN)
NAN_BOXED(2133921641,32,FLEN)
NAN_BOXED(2147483648,32,FLEN)
NAN_BOXED(3615522815,32,FLEN)
NAN_BOXED(2133921641,32,FLEN)
NAN_BOXED(2147483648,32,FLEN)
NAN_BOXED(3623862272,32,FLEN)
NAN_BOXED(2133921641,32,FLEN)
NAN_BOXED(2147483648,32,FLEN)
NAN_BOXED(3615506431,32,FLEN)
NAN_BOXED(2133921641,32,FLEN)
NAN_BOXED(2147483648,32,FLEN)
NAN_BOXED(3623870464,32,FLEN)
NAN_BOXED(2133921641,32,FLEN)
NAN_BOXED(2147483648,32,FLEN)
NAN_BOXED(3615498239,32,FLEN)
NAN_BOXED(2133921641,32,FLEN)
NAN_BOXED(2147483648,32,FLEN)
NAN_BOXED(3623874560,32,FLEN)
NAN_BOXED(2133921641,32,FLEN)
NAN_BOXED(2147483648,32,FLEN)
NAN_BOXED(3615494143,32,FLEN)
NAN_BOXED(2133921641,32,FLEN)
NAN_BOXED(2147483648,32,FLEN)
NAN_BOXED(3623876608,32,FLEN)
NAN_BOXED(2133921641,32,FLEN)
NAN_BOXED(2147483648,32,FLEN)
NAN_BOXED(3615492095,32,FLEN)
NAN_BOXED(2133921641,32,FLEN)
NAN_BOXED(2147483648,32,FLEN)
NAN_BOXED(3623877632,32,FLEN)
NAN_BOXED(2133921641,32,FLEN)
NAN_BOXED(2147483648,32,FLEN)
NAN_BOXED(3615491071,32,FLEN)
NAN_BOXED(2133921641,32,FLEN)
NAN_BOXED(2147483648,32,FLEN)
NAN_BOXED(3623878144,32,FLEN)
NAN_BOXED(2133921641,32,FLEN)
NAN_BOXED(2147483648,32,FLEN)
NAN_BOXED(3615490559,32,FLEN)
NAN_BOXED(2133921641,32,FLEN)
NAN_BOXED(2147483648,32,FLEN)
NAN_BOXED(3623878400,32,FLEN)
NAN_BOXED(2133921641,32,FLEN)
NAN_BOXED(2147483648,32,FLEN)
NAN_BOXED(3615490303,32,FLEN)
NAN_BOXED(2133921641,32,FLEN)
NAN_BOXED(2147483648,32,FLEN)
NAN_BOXED(3623878528,32,FLEN)
NAN_BOXED(2133921641,32,FLEN)
NAN_BOXED(2147483648,32,FLEN)
NAN_BOXED(3615490175,32,FLEN)
NAN_BOXED(2133921641,32,FLEN)
NAN_BOXED(2147483648,32,FLEN)
NAN_BOXED(3623878592,32,FLEN)
NAN_BOXED(2133921641,32,FLEN)
NAN_BOXED(2147483648,32,FLEN)
NAN_BOXED(3615490111,32,FLEN)
NAN_BOXED(2133921641,32,FLEN)
NAN_BOXED(2147483648,32,FLEN)
NAN_BOXED(3623878624,32,FLEN)
NAN_BOXED(2133921641,32,FLEN)
NAN_BOXED(2147483648,32,FLEN)
NAN_BOXED(3615490079,32,FLEN)
NAN_BOXED(2133921641,32,FLEN)
NAN_BOXED(2147483648,32,FLEN)
NAN_BOXED(3623878640,32,FLEN)
NAN_BOXED(2133921641,32,FLEN)
NAN_BOXED(2147483648,32,FLEN)
NAN_BOXED(3615490063,32,FLEN)
NAN_BOXED(2133921641,32,FLEN)
NAN_BOXED(2147483648,32,FLEN)
NAN_BOXED(3623878648,32,FLEN)
NAN_BOXED(2133921641,32,FLEN)
NAN_BOXED(2147483648,32,FLEN)
NAN_BOXED(3615490055,32,FLEN)
NAN_BOXED(2133921641,32,FLEN)
NAN_BOXED(2147483648,32,FLEN)
NAN_BOXED(3623878652,32,FLEN)
NAN_BOXED(2133921641,32,FLEN)
NAN_BOXED(2147483648,32,FLEN)
NAN_BOXED(3615490051,32,FLEN)
NAN_BOXED(2133921641,32,FLEN)
NAN_BOXED(2147483648,32,FLEN)
NAN_BOXED(3623878654,32,FLEN)
NAN_BOXED(2133921641,32,FLEN)
NAN_BOXED(2147483648,32,FLEN)
NAN_BOXED(3615490049,32,FLEN)
NAN_BOXED(2133921641,32,FLEN)
NAN_BOXED(2147483648,32,FLEN)
NAN_BOXED(2155872248,32,FLEN)
NAN_BOXED(2133921641,32,FLEN)
NAN_BOXED(2147483648,32,FLEN)
NAN_BOXED(2147483655,32,FLEN)
NAN_BOXED(2133921641,32,FLEN)
NAN_BOXED(2147483648,32,FLEN)
NAN_BOXED(2155872252,32,FLEN)
NAN_BOXED(2133921641,32,FLEN)
NAN_BOXED(2147483648,32,FLEN)
NAN_BOXED(2147483651,32,FLEN)
NAN_BOXED(2133921641,32,FLEN)
NAN_BOXED(2147483648,32,FLEN)
NAN_BOXED(2155872254,32,FLEN)
NAN_BOXED(2133921641,32,FLEN)
NAN_BOXED(2147483648,32,FLEN)
NAN_BOXED(2147483649,32,FLEN)
NAN_BOXED(2133921641,32,FLEN)
NAN_BOXED(2147483648,32,FLEN)
NAN_BOXED(2151078765,32,FLEN)
NAN_BOXED(2133921641,32,FLEN)
NAN_BOXED(2147483648,32,FLEN)
NAN_BOXED(2154673883,32,FLEN)
NAN_BOXED(2133921641,32,FLEN)
NAN_BOXED(2147483648,32,FLEN)
NAN_BOXED(2149161369,32,FLEN)
NAN_BOXED(2133921641,32,FLEN)
NAN_BOXED(2147483648,32,FLEN)
NAN_BOXED(2154194534,32,FLEN)
NAN_BOXED(2133921641,32,FLEN)
NAN_BOXED(2147483648,32,FLEN)
NAN_BOXED(2151398331,32,FLEN)
NAN_BOXED(2133921641,32,FLEN)
NAN_BOXED(2147483648,32,FLEN)
NAN_BOXED(2151957572,32,FLEN)
NAN_BOXED(2133921641,32,FLEN)
NAN_BOXED(2147483648,32,FLEN)
NAN_BOXED(2149880393,32,FLEN)
NAN_BOXED(2133921641,32,FLEN)
NAN_BOXED(2147483648,32,FLEN)
NAN_BOXED(2153475510,32,FLEN)
NAN_BOXED(2133921641,32,FLEN)
NAN_BOXED(2147483648,32,FLEN)
NAN_BOXED(2150839091,32,FLEN)
NAN_BOXED(2133921641,32,FLEN)
NAN_BOXED(2147483648,32,FLEN)
NAN_BOXED(2152516812,32,FLEN)
NAN_BOXED(2107218356,32,FLEN)
NAN_BOXED(2147483648,32,FLEN)
NAN_BOXED(2147483648,32,FLEN)
NAN_BOXED(2107218356,32,FLEN)
NAN_BOXED(2147483648,32,FLEN)
NAN_BOXED(2155872255,32,FLEN)
NAN_BOXED(2107218356,32,FLEN)
NAN_BOXED(2147483648,32,FLEN)
NAN_BOXED(2151677952,32,FLEN)
NAN_BOXED(2107218356,32,FLEN)
NAN_BOXED(2147483648,32,FLEN)
NAN_BOXED(2151677951,32,FLEN)
NAN_BOXED(2107218356,32,FLEN)
NAN_BOXED(2147483648,32,FLEN)
NAN_BOXED(2153775104,32,FLEN)
NAN_BOXED(2107218356,32,FLEN)
NAN_BOXED(2147483648,32,FLEN)
NAN_BOXED(2149580799,32,FLEN)
NAN_BOXED(2107218356,32,FLEN)
NAN_BOXED(2147483648,32,FLEN)
NAN_BOXED(2154823680,32,FLEN)
NAN_BOXED(2107218356,32,FLEN)
NAN_BOXED(2147483648,32,FLEN)
NAN_BOXED(2148532223,32,FLEN)
NAN_BOXED(2107218356,32,FLEN)
NAN_BOXED(2147483648,32,FLEN)
NAN_BOXED(2155347968,32,FLEN)
NAN_BOXED(2107218356,32,FLEN)
NAN_BOXED(2147483648,32,FLEN)
NAN_BOXED(2148007935,32,FLEN)
NAN_BOXED(2107218356,32,FLEN)
NAN_BOXED(2147483648,32,FLEN)
NAN_BOXED(2155610112,32,FLEN)
NAN_BOXED(2107218356,32,FLEN)
NAN_BOXED(2147483648,32,FLEN)
NAN_BOXED(2147745791,32,FLEN)
NAN_BOXED(2107218356,32,FLEN)
NAN_BOXED(2147483648,32,FLEN)
NAN_BOXED(2155741184,32,FLEN)
NAN_BOXED(2107218356,32,FLEN)
NAN_BOXED(2147483648,32,FLEN)
NAN_BOXED(2147614719,32,FLEN)
NAN_BOXED(2107218356,32,FLEN)
NAN_BOXED(2147483648,32,FLEN)
NAN_BOXED(2155806720,32,FLEN)
NAN_BOXED(2107218356,32,FLEN)
NAN_BOXED(2147483648,32,FLEN)
NAN_BOXED(2147549183,32,FLEN)
NAN_BOXED(2107218356,32,FLEN)
NAN_BOXED(2147483648,32,FLEN)
NAN_BOXED(2155839488,32,FLEN)
NAN_BOXED(2107218356,32,FLEN)
NAN_BOXED(2147483648,32,FLEN)
NAN_BOXED(2147516415,32,FLEN)
NAN_BOXED(2107218356,32,FLEN)
NAN_BOXED(2147483648,32,FLEN)
NAN_BOXED(2155855872,32,FLEN)
NAN_BOXED(2107218356,32,FLEN)
NAN_BOXED(2147483648,32,FLEN)
NAN_BOXED(2147500031,32,FLEN)
NAN_BOXED(2107218356,32,FLEN)
NAN_BOXED(2147483648,32,FLEN)
NAN_BOXED(2155864064,32,FLEN)
NAN_BOXED(2107218356,32,FLEN)
NAN_BOXED(2147483648,32,FLEN)
NAN_BOXED(2147491839,32,FLEN)
NAN_BOXED(2107218356,32,FLEN)
NAN_BOXED(2147483648,32,FLEN)
NAN_BOXED(2155868160,32,FLEN)
NAN_BOXED(2107218356,32,FLEN)
NAN_BOXED(2147483648,32,FLEN)
NAN_BOXED(2147487743,32,FLEN)
NAN_BOXED(2107218356,32,FLEN)
NAN_BOXED(2147483648,32,FLEN)
NAN_BOXED(2155870208,32,FLEN)
NAN_BOXED(2107218356,32,FLEN)
NAN_BOXED(2147483648,32,FLEN)
NAN_BOXED(2147485695,32,FLEN)
NAN_BOXED(2107218356,32,FLEN)
NAN_BOXED(2147483648,32,FLEN)
NAN_BOXED(2155871232,32,FLEN)
NAN_BOXED(2107218356,32,FLEN)
RVTEST_DATA_END

RVMODEL_DATA_BEGIN
rvtest_sig_begin:
sig_begin_canary:
CANARY;



signature_x1_0:
    .fill 0*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_1:
    .fill 48*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_0:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_1:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_2:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_3:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_4:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_5:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_6:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_7:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_8:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_9:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_10:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_11:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_12:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_13:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_14:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_15:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_16:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_17:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_18:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_19:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_20:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_21:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_22:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_23:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_24:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_25:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_26:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_27:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_28:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_29:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_30:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_31:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_32:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_33:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_34:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_35:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_36:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_37:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_38:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_39:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_40:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_41:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_42:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_43:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_44:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_45:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_46:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_47:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_48:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_49:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_50:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_51:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_52:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_53:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_54:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_55:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_56:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_57:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_58:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_59:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_60:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_61:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_62:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_63:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_64:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_65:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_66:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_67:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_68:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_69:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_70:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_71:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_72:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_73:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_74:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_75:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_76:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_77:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_78:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_79:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_80:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_81:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_82:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_83:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_84:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_85:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_86:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_87:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_88:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_89:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_90:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_91:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_92:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_93:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_94:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_95:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_96:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_97:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_98:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_99:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_100:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_101:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_102:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_103:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_104:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_105:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_106:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_107:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_108:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_109:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_110:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_111:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_112:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_113:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_114:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_115:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_116:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_117:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_118:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_119:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_120:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_121:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_122:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_123:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_124:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_125:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_126:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_127:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_128:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_129:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_130:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_131:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_132:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_133:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_134:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_135:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_136:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_137:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_138:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_139:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_140:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_141:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_142:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_143:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_144:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_145:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_146:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_147:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_148:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_149:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_150:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_151:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_152:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_153:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_154:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_155:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_156:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_157:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_158:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_159:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_160:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_161:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_162:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_163:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_164:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_165:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_166:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_167:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_168:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_169:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_170:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_171:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_172:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_173:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_174:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_175:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_176:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_177:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_178:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_179:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_180:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_181:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_182:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_183:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_184:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_185:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_186:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_187:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_188:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_189:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_190:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_191:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_192:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_193:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_194:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_195:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_196:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_197:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_198:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_199:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_200:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_201:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_202:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_203:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_204:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_205:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_206:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_207:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_208:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_209:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_210:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_211:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_212:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_213:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_214:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_215:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_216:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_217:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_218:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_219:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_220:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_221:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_222:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_223:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_224:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_225:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_226:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_227:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_228:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_229:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_230:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_231:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_232:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_233:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_234:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_235:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_236:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_237:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_238:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_239:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_240:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_241:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_242:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_243:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_244:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_245:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_246:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_247:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_248:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_249:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_250:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_251:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_252:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_253:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_254:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_255:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_256:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_257:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_258:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_259:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_260:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_261:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_262:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_263:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_264:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_265:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_266:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_267:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_268:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_269:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_270:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_271:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_272:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_273:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_274:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_275:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_276:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_277:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_278:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_279:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_280:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_281:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_282:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_283:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_284:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_285:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_286:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_287:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_288:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_289:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_290:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_291:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_292:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_293:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_294:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_295:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_296:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_297:
    .fill 180*((SIGALIGN)/4),4,0xdeadbeef

#ifdef rvtest_mtrap_routine
tsig_begin_canary:
CANARY;

mtrap_sigptr:
    .fill 64*XLEN/32,4,0xdeadbeef

tsig_end_canary:
CANARY;
#endif

#ifdef rvtest_gpr_save

gpr_save:
    .fill 32*XLEN/32,4,0xdeadbeef

#endif


sig_end_canary:
CANARY;
rvtest_sig_end:
RVMODEL_DATA_END
