
// -----------
// This file was generated by riscv_ctg (https://github.com/riscv-software-src/riscv-ctg)
// version   : 0.11.0
// timestamp : Tue Jan 30 08:45:11 2024 GMT
// usage     : riscv_ctg \
//                  -- cgf //                  --cgf /home/riscv/riscv-ctg/sample_cgfs/dataset.cgf \
//                  --cgf /home/riscv/riscv-ctg/sample_cgfs/sample_cgfs_fext/RV32H/rv32h_fnmsub.cgf \
 \
//                  -- xlen 32  \
// -----------
//
// -----------
// Copyright (c) 2020. RISC-V International. All rights reserved.
// SPDX-License-Identifier: BSD-3-Clause
// -----------
//
// This assembly file tests the fnmsub.h instruction of the RISC-V RV32F_Zicsr_Zfh,RV32FD_Zicsr,RV64F_Zicsr_Zfh,RV64FD_Zicsr extension for the fnmsub_b18 covergroup.
// 
#include "model_test.h"
#include "arch_test.h"
RVTEST_ISA("RV32IF_Zicsr_Zfh,RV32IFD_Zicsr,RV64IF_Zicsr_Zfh,RV64IFD_Zicsr")

.section .text.init
.globl rvtest_entry_point
rvtest_entry_point:
RVMODEL_BOOT
RVTEST_CODE_BEGIN

#ifdef TEST_CASE_1

RVTEST_CASE(0,"//check ISA:=regex(.*I.*F.*Zfh.*);def TEST_CASE_1=True;",fnmsub_b18)

RVTEST_FP_ENABLE()
RVTEST_VALBASEUPD(x3,test_dataset_0)
RVTEST_SIGBASE(x1,signature_x1_1)

inst_0:
// rs1 == rs2 == rs3 == rd, rs1==f31, rs2==f31, rs3==f31, rd==f31,fs1 == 0 and fe1 == 0x1c and fm1 == 0x39c and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f31; op2:f31; op3:f31; dest:f31; op1val:0x739c; op2val:0x739c;
op3val:0x739c; valaddr_reg:x3; val_offset:0*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f31, f31, f31, dyn, 0, 0, x3, 0*FLEN/8, x4, x1, x2)

inst_1:
// rs1 == rd == rs3 != rs2, rs1==f30, rs2==f29, rs3==f30, rd==f30,fs1 == 0 and fe1 == 0x1e and fm1 == 0x05a and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f30; dest:f30; op1val:0x785a; op2val:0x8000;
op3val:0x785a; valaddr_reg:x3; val_offset:3*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f30, f30, f29, f30, dyn, 0, 0, x3, 3*FLEN/8, x4, x1, x2)

inst_2:
// rs1 == rd != rs2 and rs1 == rd != rs3 and rs3 != rs2, rs1==f29, rs2==f30, rs3==f28, rd==f29,fs1 == 0 and fe1 == 0x1d and fm1 == 0x1ea and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f29; op2:f30; op3:f28; dest:f29; op1val:0x75ea; op2val:0x8000;
op3val:0x7bff; valaddr_reg:x3; val_offset:6*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f29, f29, f30, f28, dyn, 0, 0, x3, 6*FLEN/8, x4, x1, x2)

inst_3:
// rs2 == rd != rs1 and rs2 == rd != rs3 and rs3 != rs1, rs1==f27, rs2==f28, rs3==f29, rd==f28,fs1 == 0 and fe1 == 0x1e and fm1 == 0x0d4 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f27; op2:f28; op3:f29; dest:f28; op1val:0x78d4; op2val:0x8000;
op3val:0x7bff; valaddr_reg:x3; val_offset:9*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f28, f27, f28, f29, dyn, 0, 0, x3, 9*FLEN/8, x4, x1, x2)

inst_4:
// rd == rs2 == rs3 != rs1, rs1==f28, rs2==f27, rs3==f27, rd==f27,fs1 == 0 and fe1 == 0x1e and fm1 == 0x100 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f28; op2:f27; op3:f27; dest:f27; op1val:0x7900; op2val:0x8000;
op3val:0x8000; valaddr_reg:x3; val_offset:12*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f27, f28, f27, f27, dyn, 0, 0, x3, 12*FLEN/8, x4, x1, x2)

inst_5:
// rs3 == rd != rs1 and rs3 == rd != rs2 and rs2 != rs1, rs1==f25, rs2==f24, rs3==f26, rd==f26,fs1 == 0 and fe1 == 0x1b and fm1 == 0x031 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f25; op2:f24; op3:f26; dest:f26; op1val:0x6c31; op2val:0x8000;
op3val:0x7bff; valaddr_reg:x3; val_offset:15*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f26, f25, f24, f26, dyn, 0, 0, x3, 15*FLEN/8, x4, x1, x2)

inst_6:
// rs1 == rs3 != rs2 and rs1 == rs3 != rd and rd != rs2, rs1==f24, rs2==f26, rs3==f24, rd==f25,fs1 == 0 and fe1 == 0x18 and fm1 == 0x2bf and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f24; op2:f26; op3:f24; dest:f25; op1val:0x62bf; op2val:0x8000;
op3val:0x62bf; valaddr_reg:x3; val_offset:18*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f25, f24, f26, f24, dyn, 0, 0, x3, 18*FLEN/8, x4, x1, x2)

inst_7:
// rs1 == rs2 == rs3 != rd, rs1==f23, rs2==f23, rs3==f23, rd==f24,fs1 == 0 and fe1 == 0x1e and fm1 == 0x2b2 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f23; op2:f23; op3:f23; dest:f24; op1val:0x7ab2; op2val:0x7ab2;
op3val:0x7ab2; valaddr_reg:x3; val_offset:21*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f24, f23, f23, f23, dyn, 0, 0, x3, 21*FLEN/8, x4, x1, x2)

inst_8:
// rs2 == rs3 != rs1 and rs2 == rs3 != rd and rd != rs1, rs1==f26, rs2==f25, rs3==f25, rd==f23,fs1 == 0 and fe1 == 0x1d and fm1 == 0x025 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f26; op2:f25; op3:f25; dest:f23; op1val:0x7425; op2val:0x0;
op3val:0x0; valaddr_reg:x3; val_offset:24*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f23, f26, f25, f25, dyn, 0, 0, x3, 24*FLEN/8, x4, x1, x2)

inst_9:
// rs1 == rs2 != rs3 and rs1 == rs2 != rd and rd != rs3, rs1==f21, rs2==f21, rs3==f20, rd==f22,fs1 == 0 and fe1 == 0x1c and fm1 == 0x37e and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f21; op2:f21; op3:f20; dest:f22; op1val:0x737e; op2val:0x737e;
op3val:0x7bff; valaddr_reg:x3; val_offset:27*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f22, f21, f21, f20, dyn, 0, 0, x3, 27*FLEN/8, x4, x1, x2)

inst_10:
// rs1 == rs2 == rd != rs3, rs1==f20, rs2==f20, rs3==f22, rd==f20,fs1 == 0 and fe1 == 0x1e and fm1 == 0x3f6 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f20; op2:f20; op3:f22; dest:f20; op1val:0x7bf6; op2val:0x7bf6;
op3val:0x7bff; valaddr_reg:x3; val_offset:30*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f20, f20, f20, f22, dyn, 0, 0, x3, 30*FLEN/8, x4, x1, x2)

inst_11:
// rs1 != rs2 and rs1 != rd and rs1 != rs3 and rs2 != rs3 and rs2 != rd and rs3 != rd, rs1==f22, rs2==f19, rs3==f18, rd==f21,fs1 == 0 and fe1 == 0x1d and fm1 == 0x385 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f22; op2:f19; op3:f18; dest:f21; op1val:0x7785; op2val:0x0;
op3val:0x7bff; valaddr_reg:x3; val_offset:33*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f21, f22, f19, f18, dyn, 0, 0, x3, 33*FLEN/8, x4, x1, x2)

inst_12:
// rs1==f18, rs2==f22, rs3==f21, rd==f19,fs1 == 0 and fe1 == 0x1e and fm1 == 0x2b0 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f18; op2:f22; op3:f21; dest:f19; op1val:0x7ab0; op2val:0x0;
op3val:0x7bff; valaddr_reg:x3; val_offset:36*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f19, f18, f22, f21, dyn, 0, 0, x3, 36*FLEN/8, x4, x1, x2)

inst_13:
// rs1==f19, rs2==f17, rs3==f16, rd==f18,fs1 == 0 and fe1 == 0x1d and fm1 == 0x39e and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f19; op2:f17; op3:f16; dest:f18; op1val:0x779e; op2val:0x0;
op3val:0x7bff; valaddr_reg:x3; val_offset:39*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f18, f19, f17, f16, dyn, 0, 0, x3, 39*FLEN/8, x4, x1, x2)

inst_14:
// rs1==f16, rs2==f18, rs3==f19, rd==f17,fs1 == 0 and fe1 == 0x1e and fm1 == 0x11c and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f16; op2:f18; op3:f19; dest:f17; op1val:0x791c; op2val:0x0;
op3val:0x7bff; valaddr_reg:x3; val_offset:42*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f17, f16, f18, f19, dyn, 0, 0, x3, 42*FLEN/8, x4, x1, x2)

inst_15:
// rs1==f17, rs2==f15, rs3==f14, rd==f16,fs1 == 0 and fe1 == 0x1c and fm1 == 0x0d1 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f17; op2:f15; op3:f14; dest:f16; op1val:0x70d1; op2val:0x0;
op3val:0x7bff; valaddr_reg:x3; val_offset:45*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f16, f17, f15, f14, dyn, 0, 0, x3, 45*FLEN/8, x4, x1, x2)

inst_16:
// rs1==f14, rs2==f16, rs3==f17, rd==f15,fs1 == 0 and fe1 == 0x1e and fm1 == 0x113 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f14; op2:f16; op3:f17; dest:f15; op1val:0x7913; op2val:0x0;
op3val:0x7bff; valaddr_reg:x3; val_offset:48*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f15, f14, f16, f17, dyn, 0, 0, x3, 48*FLEN/8, x4, x1, x2)

inst_17:
// rs1==f15, rs2==f13, rs3==f12, rd==f14,fs1 == 0 and fe1 == 0x1e and fm1 == 0x2f0 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f15; op2:f13; op3:f12; dest:f14; op1val:0x7af0; op2val:0x0;
op3val:0x7bff; valaddr_reg:x3; val_offset:51*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f14, f15, f13, f12, dyn, 0, 0, x3, 51*FLEN/8, x4, x1, x2)

inst_18:
// rs1==f12, rs2==f14, rs3==f15, rd==f13,fs1 == 0 and fe1 == 0x1e and fm1 == 0x02e and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f12; op2:f14; op3:f15; dest:f13; op1val:0x782e; op2val:0x0;
op3val:0x7bff; valaddr_reg:x3; val_offset:54*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f13, f12, f14, f15, dyn, 0, 0, x3, 54*FLEN/8, x4, x1, x2)

inst_19:
// rs1==f13, rs2==f11, rs3==f10, rd==f12,fs1 == 0 and fe1 == 0x1e and fm1 == 0x1ed and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f13; op2:f11; op3:f10; dest:f12; op1val:0x79ed; op2val:0x0;
op3val:0x7bff; valaddr_reg:x3; val_offset:57*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f12, f13, f11, f10, dyn, 0, 0, x3, 57*FLEN/8, x4, x1, x2)

inst_20:
// rs1==f10, rs2==f12, rs3==f13, rd==f11,fs1 == 0 and fe1 == 0x1e and fm1 == 0x15e and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f10; op2:f12; op3:f13; dest:f11; op1val:0x795e; op2val:0x0;
op3val:0x7bff; valaddr_reg:x3; val_offset:60*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f11, f10, f12, f13, dyn, 0, 0, x3, 60*FLEN/8, x4, x1, x2)

inst_21:
// rs1==f11, rs2==f9, rs3==f8, rd==f10,fs1 == 0 and fe1 == 0x1b and fm1 == 0x018 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f11; op2:f9; op3:f8; dest:f10; op1val:0x6c18; op2val:0x8000;
op3val:0x7bff; valaddr_reg:x3; val_offset:63*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f10, f11, f9, f8, dyn, 0, 0, x3, 63*FLEN/8, x4, x1, x2)

inst_22:
// rs1==f8, rs2==f10, rs3==f11, rd==f9,fs1 == 0 and fe1 == 0x1e and fm1 == 0x210 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f8; op2:f10; op3:f11; dest:f9; op1val:0x7a10; op2val:0x8000;
op3val:0x7bff; valaddr_reg:x3; val_offset:66*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f9, f8, f10, f11, dyn, 0, 0, x3, 66*FLEN/8, x4, x1, x2)

inst_23:
// rs1==f9, rs2==f7, rs3==f6, rd==f8,fs1 == 0 and fe1 == 0x1e and fm1 == 0x0b9 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f9; op2:f7; op3:f6; dest:f8; op1val:0x78b9; op2val:0x8000;
op3val:0x7bff; valaddr_reg:x3; val_offset:69*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f8, f9, f7, f6, dyn, 0, 0, x3, 69*FLEN/8, x4, x1, x2)

inst_24:
// rs1==f6, rs2==f8, rs3==f9, rd==f7,fs1 == 0 and fe1 == 0x1d and fm1 == 0x0d1 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f6; op2:f8; op3:f9; dest:f7; op1val:0x74d1; op2val:0x8000;
op3val:0x7bff; valaddr_reg:x3; val_offset:72*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f7, f6, f8, f9, dyn, 0, 0, x3, 72*FLEN/8, x4, x1, x2)

inst_25:
// rs1==f7, rs2==f5, rs3==f4, rd==f6,fs1 == 0 and fe1 == 0x19 and fm1 == 0x3f0 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f7; op2:f5; op3:f4; dest:f6; op1val:0x67f0; op2val:0x8000;
op3val:0x7bff; valaddr_reg:x3; val_offset:75*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f6, f7, f5, f4, dyn, 0, 0, x3, 75*FLEN/8, x4, x1, x2)

inst_26:
// rs1==f4, rs2==f6, rs3==f7, rd==f5,fs1 == 0 and fe1 == 0x1e and fm1 == 0x2eb and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f4; op2:f6; op3:f7; dest:f5; op1val:0x7aeb; op2val:0x8000;
op3val:0x7bff; valaddr_reg:x3; val_offset:78*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f5, f4, f6, f7, dyn, 0, 0, x3, 78*FLEN/8, x4, x1, x2)

inst_27:
// rs1==f5, rs2==f3, rs3==f2, rd==f4,fs1 == 0 and fe1 == 0x1d and fm1 == 0x38f and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f5; op2:f3; op3:f2; dest:f4; op1val:0x778f; op2val:0x8000;
op3val:0x7bff; valaddr_reg:x3; val_offset:81*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f4, f5, f3, f2, dyn, 0, 0, x3, 81*FLEN/8, x4, x1, x2)

inst_28:
// rs1==f2, rs2==f4, rs3==f5, rd==f3,fs1 == 0 and fe1 == 0x1e and fm1 == 0x1bf and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f2; op2:f4; op3:f5; dest:f3; op1val:0x79bf; op2val:0x8000;
op3val:0x7bff; valaddr_reg:x3; val_offset:84*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f3, f2, f4, f5, dyn, 0, 0, x3, 84*FLEN/8, x4, x1, x2)

inst_29:
// rs1==f3, rs2==f1, rs3==f0, rd==f2,fs1 == 0 and fe1 == 0x1e and fm1 == 0x306 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f3; op2:f1; op3:f0; dest:f2; op1val:0x7b06; op2val:0x8000;
op3val:0x7bff; valaddr_reg:x3; val_offset:87*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f2, f3, f1, f0, dyn, 0, 0, x3, 87*FLEN/8, x4, x1, x2)

inst_30:
// rs1==f0, rs2==f2, rs3==f3, rd==f1,fs1 == 0 and fe1 == 0x1e and fm1 == 0x1b5 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f0; op2:f2; op3:f3; dest:f1; op1val:0x79b5; op2val:0x8000;
op3val:0x7bff; valaddr_reg:x3; val_offset:90*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f1, f0, f2, f3, dyn, 0, 0, x3, 90*FLEN/8, x4, x1, x2)

inst_31:
// rs1==f1,fs1 == 0 and fe1 == 0x1e and fm1 == 0x35d and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f1; op2:f30; op3:f29; dest:f31; op1val:0x7b5d; op2val:0x8000;
op3val:0x7bff; valaddr_reg:x3; val_offset:93*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f1, f30, f29, dyn, 0, 0, x3, 93*FLEN/8, x4, x1, x2)

inst_32:
// rs2==f0,fs1 == 0 and fe1 == 0x1d and fm1 == 0x251 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f0; op3:f29; dest:f31; op1val:0x7651; op2val:0x8000;
op3val:0x7bff; valaddr_reg:x3; val_offset:96*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f0, f29, dyn, 0, 0, x3, 96*FLEN/8, x4, x1, x2)

inst_33:
// rs3==f1,fs1 == 0 and fe1 == 0x1e and fm1 == 0x267 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f1; dest:f31; op1val:0x7a67; op2val:0x8000;
op3val:0x7bff; valaddr_reg:x3; val_offset:99*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f1, dyn, 0, 0, x3, 99*FLEN/8, x4, x1, x2)

inst_34:
// rd==f0,fs1 == 0 and fe1 == 0x1d and fm1 == 0x31c and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f31; op2:f30; op3:f29; dest:f0; op1val:0x771c; op2val:0x8000;
op3val:0x7bff; valaddr_reg:x3; val_offset:102*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f0, f31, f30, f29, dyn, 0, 0, x3, 102*FLEN/8, x4, x1, x2)

inst_35:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x37b and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7b7b; op2val:0x0;
op3val:0x7bff; valaddr_reg:x3; val_offset:105*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 105*FLEN/8, x4, x1, x2)

inst_36:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x307 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7b07; op2val:0x0;
op3val:0x7bff; valaddr_reg:x3; val_offset:108*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 108*FLEN/8, x4, x1, x2)

inst_37:
// fs1 == 0 and fe1 == 0x1b and fm1 == 0x23c and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x6e3c; op2val:0x0;
op3val:0x7bff; valaddr_reg:x3; val_offset:111*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 111*FLEN/8, x4, x1, x2)

inst_38:
// fs1 == 0 and fe1 == 0x1c and fm1 == 0x059 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7059; op2val:0x0;
op3val:0x7bff; valaddr_reg:x3; val_offset:114*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 114*FLEN/8, x4, x1, x2)

inst_39:
// fs1 == 0 and fe1 == 0x1c and fm1 == 0x2f0 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x72f0; op2val:0x0;
op3val:0x7bff; valaddr_reg:x3; val_offset:117*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 117*FLEN/8, x4, x1, x2)

inst_40:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3b8 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7bb8; op2val:0x0;
op3val:0x7bff; valaddr_reg:x3; val_offset:120*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 120*FLEN/8, x4, x1, x2)

inst_41:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x2f9 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x76f9; op2val:0x0;
op3val:0x7bff; valaddr_reg:x3; val_offset:123*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 123*FLEN/8, x4, x1, x2)

inst_42:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x102 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7902; op2val:0x0;
op3val:0x7bff; valaddr_reg:x3; val_offset:126*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 126*FLEN/8, x4, x1, x2)

inst_43:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x0d0 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x74d0; op2val:0x0;
op3val:0x7bff; valaddr_reg:x3; val_offset:129*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 129*FLEN/8, x4, x1, x2)

inst_44:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x00e and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x780e; op2val:0x0;
op3val:0x7bff; valaddr_reg:x3; val_offset:132*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 132*FLEN/8, x4, x1, x2)

inst_45:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x22b and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x762b; op2val:0x0;
op3val:0x7bff; valaddr_reg:x3; val_offset:135*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 135*FLEN/8, x4, x1, x2)

inst_46:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x19c and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x759c; op2val:0x0;
op3val:0x7bff; valaddr_reg:x3; val_offset:138*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 138*FLEN/8, x4, x1, x2)

inst_47:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0ad and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x78ad; op2val:0x0;
op3val:0x7bff; valaddr_reg:x3; val_offset:141*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 141*FLEN/8, x4, x1, x2)

inst_48:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0ab and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x78ab; op2val:0x0;
op3val:0x7bff; valaddr_reg:x3; val_offset:144*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 144*FLEN/8, x4, x1, x2)

inst_49:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x33a and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7b3a; op2val:0x8000;
op3val:0x7bff; valaddr_reg:x3; val_offset:147*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 147*FLEN/8, x4, x1, x2)

inst_50:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x174 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7974; op2val:0x8000;
op3val:0x7bff; valaddr_reg:x3; val_offset:150*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 150*FLEN/8, x4, x1, x2)

inst_51:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x36d and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7b6d; op2val:0x8000;
op3val:0x7bff; valaddr_reg:x3; val_offset:153*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 153*FLEN/8, x4, x1, x2)

inst_52:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2d9 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7ad9; op2val:0x8000;
op3val:0x7bff; valaddr_reg:x3; val_offset:156*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 156*FLEN/8, x4, x1, x2)

inst_53:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ec and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7bec; op2val:0x8000;
op3val:0x7bff; valaddr_reg:x3; val_offset:159*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 159*FLEN/8, x4, x1, x2)

inst_54:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x15e and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x795e; op2val:0x8000;
op3val:0x7bff; valaddr_reg:x3; val_offset:162*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 162*FLEN/8, x4, x1, x2)

inst_55:
// fs1 == 0 and fe1 == 0x1c and fm1 == 0x137 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7137; op2val:0x8000;
op3val:0x7bff; valaddr_reg:x3; val_offset:165*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 165*FLEN/8, x4, x1, x2)

inst_56:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2e1 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7ae1; op2val:0x8000;
op3val:0x7bff; valaddr_reg:x3; val_offset:168*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 168*FLEN/8, x4, x1, x2)

inst_57:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3b6 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7bb6; op2val:0x8000;
op3val:0x7bff; valaddr_reg:x3; val_offset:171*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 171*FLEN/8, x4, x1, x2)

inst_58:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x33b and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7b3b; op2val:0x8000;
op3val:0x7bff; valaddr_reg:x3; val_offset:174*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 174*FLEN/8, x4, x1, x2)

inst_59:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x08c and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x788c; op2val:0x8000;
op3val:0x7bff; valaddr_reg:x3; val_offset:177*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 177*FLEN/8, x4, x1, x2)

inst_60:
// fs1 == 0 and fe1 == 0x1c and fm1 == 0x2c0 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x72c0; op2val:0x8000;
op3val:0x7bff; valaddr_reg:x3; val_offset:180*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 180*FLEN/8, x4, x1, x2)

inst_61:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2a6 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7aa6; op2val:0x8000;
op3val:0x7bff; valaddr_reg:x3; val_offset:183*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 183*FLEN/8, x4, x1, x2)

inst_62:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x096 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7896; op2val:0x0;
op3val:0x7bff; valaddr_reg:x3; val_offset:186*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 186*FLEN/8, x4, x1, x2)

inst_63:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x08e and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x748e; op2val:0x0;
op3val:0x7bff; valaddr_reg:x3; val_offset:189*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 189*FLEN/8, x4, x1, x2)

inst_64:
// fs1 == 0 and fe1 == 0x1b and fm1 == 0x00f and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x6c0f; op2val:0x0;
op3val:0x7bff; valaddr_reg:x3; val_offset:192*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 192*FLEN/8, x4, x1, x2)

inst_65:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2d4 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7ad4; op2val:0x0;
op3val:0x7bff; valaddr_reg:x3; val_offset:195*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 195*FLEN/8, x4, x1, x2)

inst_66:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ea and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7bea; op2val:0x0;
op3val:0x7bff; valaddr_reg:x3; val_offset:198*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 198*FLEN/8, x4, x1, x2)

inst_67:
// fs1 == 0 and fe1 == 0x1b and fm1 == 0x1a9 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x6da9; op2val:0x0;
op3val:0x7bff; valaddr_reg:x3; val_offset:201*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 201*FLEN/8, x4, x1, x2)

inst_68:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x266 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7a66; op2val:0x0;
op3val:0x7bff; valaddr_reg:x3; val_offset:204*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 204*FLEN/8, x4, x1, x2)

inst_69:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x290 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7690; op2val:0x0;
op3val:0x7bff; valaddr_reg:x3; val_offset:207*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 207*FLEN/8, x4, x1, x2)

inst_70:
// fs1 == 0 and fe1 == 0x1c and fm1 == 0x0d2 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x70d2; op2val:0x0;
op3val:0x7bff; valaddr_reg:x3; val_offset:210*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 210*FLEN/8, x4, x1, x2)

inst_71:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x0b3 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x74b3; op2val:0x0;
op3val:0x7bff; valaddr_reg:x3; val_offset:213*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 213*FLEN/8, x4, x1, x2)

inst_72:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x225 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7a25; op2val:0x0;
op3val:0x7bff; valaddr_reg:x3; val_offset:216*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 216*FLEN/8, x4, x1, x2)

inst_73:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2fa and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7afa; op2val:0x0;
op3val:0x7bff; valaddr_reg:x3; val_offset:219*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 219*FLEN/8, x4, x1, x2)

inst_74:
// fs1 == 0 and fe1 == 0x1a and fm1 == 0x1a7 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x69a7; op2val:0x0;
op3val:0x7bff; valaddr_reg:x3; val_offset:222*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 222*FLEN/8, x4, x1, x2)

inst_75:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0e9 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x78e9; op2val:0x0;
op3val:0x7bff; valaddr_reg:x3; val_offset:225*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 225*FLEN/8, x4, x1, x2)

inst_76:
// fs1 == 0 and fe1 == 0x1a and fm1 == 0x1c0 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x69c0; op2val:0x8000;
op3val:0x7bff; valaddr_reg:x3; val_offset:228*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 228*FLEN/8, x4, x1, x2)

inst_77:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1be and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x79be; op2val:0x8000;
op3val:0x7bff; valaddr_reg:x3; val_offset:231*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 231*FLEN/8, x4, x1, x2)

inst_78:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x14a and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x754a; op2val:0x8000;
op3val:0x7bff; valaddr_reg:x3; val_offset:234*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 234*FLEN/8, x4, x1, x2)

inst_79:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x30b and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7b0b; op2val:0x8000;
op3val:0x7bff; valaddr_reg:x3; val_offset:237*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 237*FLEN/8, x4, x1, x2)

inst_80:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3d7 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7bd7; op2val:0x8000;
op3val:0x7bff; valaddr_reg:x3; val_offset:240*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 240*FLEN/8, x4, x1, x2)

inst_81:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x00a and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x780a; op2val:0x8000;
op3val:0x7bff; valaddr_reg:x3; val_offset:243*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 243*FLEN/8, x4, x1, x2)

inst_82:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3fb and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7bfb; op2val:0x8000;
op3val:0x7bff; valaddr_reg:x3; val_offset:246*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 246*FLEN/8, x4, x1, x2)

inst_83:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x0f3 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x74f3; op2val:0x8000;
op3val:0x7bff; valaddr_reg:x3; val_offset:249*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 249*FLEN/8, x4, x1, x2)

inst_84:
// fs1 == 0 and fe1 == 0x1b and fm1 == 0x0ec and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x6cec; op2val:0x8000;
op3val:0x7bff; valaddr_reg:x3; val_offset:252*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 252*FLEN/8, x4, x1, x2)

inst_85:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0cb and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x78cb; op2val:0x8000;
op3val:0x7bff; valaddr_reg:x3; val_offset:255*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 255*FLEN/8, x4, x1, x2)

inst_86:
// fs1 == 0 and fe1 == 0x1a and fm1 == 0x004 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x6804; op2val:0x8000;
op3val:0x7bff; valaddr_reg:x3; val_offset:258*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 258*FLEN/8, x4, x1, x2)

inst_87:
// fs1 == 0 and fe1 == 0x1c and fm1 == 0x250 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7250; op2val:0x8000;
op3val:0x7bff; valaddr_reg:x3; val_offset:261*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 261*FLEN/8, x4, x1, x2)

inst_88:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x286 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7686; op2val:0x8000;
op3val:0x7bff; valaddr_reg:x3; val_offset:264*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 264*FLEN/8, x4, x1, x2)

inst_89:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0e1 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x78e1; op2val:0x8000;
op3val:0x7bff; valaddr_reg:x3; val_offset:267*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 267*FLEN/8, x4, x1, x2)

inst_90:
// fs1 == 0 and fe1 == 0x1c and fm1 == 0x0ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x70ff; op2val:0x0;
op3val:0x7bff; valaddr_reg:x3; val_offset:270*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 270*FLEN/8, x4, x1, x2)

inst_91:
// fs1 == 0 and fe1 == 0x1a and fm1 == 0x16e and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x696e; op2val:0x0;
op3val:0x7bff; valaddr_reg:x3; val_offset:273*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 273*FLEN/8, x4, x1, x2)

inst_92:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x104 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7504; op2val:0x0;
op3val:0x7bff; valaddr_reg:x3; val_offset:276*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 276*FLEN/8, x4, x1, x2)

inst_93:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3aa and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7baa; op2val:0x0;
op3val:0x7bff; valaddr_reg:x3; val_offset:279*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 279*FLEN/8, x4, x1, x2)

inst_94:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x32b and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7b2b; op2val:0x0;
op3val:0x7bff; valaddr_reg:x3; val_offset:282*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 282*FLEN/8, x4, x1, x2)

inst_95:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x20a and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x760a; op2val:0x0;
op3val:0x7bff; valaddr_reg:x3; val_offset:285*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 285*FLEN/8, x4, x1, x2)

inst_96:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x35c and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x775c; op2val:0x0;
op3val:0x7bff; valaddr_reg:x3; val_offset:288*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 288*FLEN/8, x4, x1, x2)

inst_97:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x028 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7828; op2val:0x0;
op3val:0x7bff; valaddr_reg:x3; val_offset:291*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 291*FLEN/8, x4, x1, x2)

inst_98:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x126 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7926; op2val:0x0;
op3val:0x7bff; valaddr_reg:x3; val_offset:294*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 294*FLEN/8, x4, x1, x2)

inst_99:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0c3 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x78c3; op2val:0x0;
op3val:0x7bff; valaddr_reg:x3; val_offset:297*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 297*FLEN/8, x4, x1, x2)

inst_100:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x078 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7878; op2val:0x0;
op3val:0x7bff; valaddr_reg:x3; val_offset:300*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 300*FLEN/8, x4, x1, x2)

inst_101:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0f5 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x78f5; op2val:0x0;
op3val:0x7bff; valaddr_reg:x3; val_offset:303*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 303*FLEN/8, x4, x1, x2)

inst_102:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x385 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7b85; op2val:0x0;
op3val:0x7bff; valaddr_reg:x3; val_offset:306*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 306*FLEN/8, x4, x1, x2)

inst_103:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x00d and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x780d; op2val:0x8000;
op3val:0x7bff; valaddr_reg:x3; val_offset:309*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 309*FLEN/8, x4, x1, x2)

inst_104:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x2e5 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x76e5; op2val:0x8000;
op3val:0x7bff; valaddr_reg:x3; val_offset:312*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 312*FLEN/8, x4, x1, x2)

inst_105:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1c2 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x79c2; op2val:0x8000;
op3val:0x7bff; valaddr_reg:x3; val_offset:315*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 315*FLEN/8, x4, x1, x2)

inst_106:
// fs1 == 0 and fe1 == 0x1c and fm1 == 0x399 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7399; op2val:0x8000;
op3val:0x7bff; valaddr_reg:x3; val_offset:318*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 318*FLEN/8, x4, x1, x2)

inst_107:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x0d0 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x74d0; op2val:0x8000;
op3val:0x7bff; valaddr_reg:x3; val_offset:321*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 321*FLEN/8, x4, x1, x2)

inst_108:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3d1 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7bd1; op2val:0x8000;
op3val:0x7bff; valaddr_reg:x3; val_offset:324*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 324*FLEN/8, x4, x1, x2)

inst_109:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x02a and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x782a; op2val:0x8000;
op3val:0x7bff; valaddr_reg:x3; val_offset:327*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 327*FLEN/8, x4, x1, x2)

inst_110:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x062 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7862; op2val:0x8000;
op3val:0x7bff; valaddr_reg:x3; val_offset:330*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 330*FLEN/8, x4, x1, x2)

inst_111:
// fs1 == 0 and fe1 == 0x18 and fm1 == 0x1de and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x61de; op2val:0x8000;
op3val:0x7bff; valaddr_reg:x3; val_offset:333*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 333*FLEN/8, x4, x1, x2)

inst_112:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x2a3 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x76a3; op2val:0x8000;
op3val:0x7bff; valaddr_reg:x3; val_offset:336*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 336*FLEN/8, x4, x1, x2)

inst_113:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0a3 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x78a3; op2val:0x8000;
op3val:0x7bff; valaddr_reg:x3; val_offset:339*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 339*FLEN/8, x4, x1, x2)

inst_114:
// fs1 == 0 and fe1 == 0x19 and fm1 == 0x122 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x6522; op2val:0x8000;
op3val:0x7bff; valaddr_reg:x3; val_offset:342*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 342*FLEN/8, x4, x1, x2)

inst_115:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0ec and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x78ec; op2val:0x8000;
op3val:0x7bff; valaddr_reg:x3; val_offset:345*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 345*FLEN/8, x4, x1, x2)

inst_116:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x10e and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x790e; op2val:0x8000;
op3val:0x7bff; valaddr_reg:x3; val_offset:348*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 348*FLEN/8, x4, x1, x2)

inst_117:
// fs1 == 0 and fe1 == 0x1a and fm1 == 0x3b0 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x6bb0; op2val:0x0;
op3val:0x7bff; valaddr_reg:x3; val_offset:351*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 351*FLEN/8, x4, x1, x2)

inst_118:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x104 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7904; op2val:0x0;
op3val:0x7bff; valaddr_reg:x3; val_offset:354*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 354*FLEN/8, x4, x1, x2)

inst_119:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x374 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7774; op2val:0x0;
op3val:0x7bff; valaddr_reg:x3; val_offset:357*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 357*FLEN/8, x4, x1, x2)

inst_120:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x16e and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x796e; op2val:0x0;
op3val:0x7bff; valaddr_reg:x3; val_offset:360*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 360*FLEN/8, x4, x1, x2)

inst_121:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x1a3 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x75a3; op2val:0x0;
op3val:0x7bff; valaddr_reg:x3; val_offset:363*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 363*FLEN/8, x4, x1, x2)

inst_122:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1a7 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x79a7; op2val:0x0;
op3val:0x7bff; valaddr_reg:x3; val_offset:366*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 366*FLEN/8, x4, x1, x2)

inst_123:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1e6 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x79e6; op2val:0x0;
op3val:0x7bff; valaddr_reg:x3; val_offset:369*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 369*FLEN/8, x4, x1, x2)

inst_124:
// fs1 == 0 and fe1 == 0x19 and fm1 == 0x1ae and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x65ae; op2val:0x0;
op3val:0x7bff; valaddr_reg:x3; val_offset:372*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 372*FLEN/8, x4, x1, x2)

inst_125:
// fs1 == 0 and fe1 == 0x1a and fm1 == 0x3c0 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x6bc0; op2val:0x0;
op3val:0x7bff; valaddr_reg:x3; val_offset:375*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 375*FLEN/8, x4, x1, x2)

inst_126:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x167 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7967; op2val:0x0;
op3val:0x7bff; valaddr_reg:x3; val_offset:378*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 378*FLEN/8, x4, x1, x2)

inst_127:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3b3 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7bb3; op2val:0x0;
op3val:0x7bff; valaddr_reg:x3; val_offset:381*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 381*FLEN/8, x4, x1, x2)
RVTEST_SIGBASE(x1,signature_x1_2)

inst_128:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x004 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7404; op2val:0x0;
op3val:0x7bff; valaddr_reg:x3; val_offset:384*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 384*FLEN/8, x4, x1, x2)

inst_129:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x34c and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x774c; op2val:0x0;
op3val:0x7bff; valaddr_reg:x3; val_offset:387*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 387*FLEN/8, x4, x1, x2)

inst_130:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0bd and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x78bd; op2val:0x0;
op3val:0x7bff; valaddr_reg:x3; val_offset:390*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 390*FLEN/8, x4, x1, x2)

inst_131:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x11e and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x751e; op2val:0x8000;
op3val:0x7bff; valaddr_reg:x3; val_offset:393*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 393*FLEN/8, x4, x1, x2)

inst_132:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x1d2 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x75d2; op2val:0x8000;
op3val:0x7bff; valaddr_reg:x3; val_offset:396*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 396*FLEN/8, x4, x1, x2)

inst_133:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x100 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7500; op2val:0x8000;
op3val:0x7bff; valaddr_reg:x3; val_offset:399*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 399*FLEN/8, x4, x1, x2)

inst_134:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x1e7 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x75e7; op2val:0x8000;
op3val:0x7bff; valaddr_reg:x3; val_offset:402*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 402*FLEN/8, x4, x1, x2)

inst_135:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0c3 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x78c3; op2val:0x8000;
op3val:0x7bff; valaddr_reg:x3; val_offset:405*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 405*FLEN/8, x4, x1, x2)

inst_136:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x0cd and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x74cd; op2val:0x8000;
op3val:0x7bff; valaddr_reg:x3; val_offset:408*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 408*FLEN/8, x4, x1, x2)

inst_137:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x208 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7608; op2val:0x8000;
op3val:0x7bff; valaddr_reg:x3; val_offset:411*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 411*FLEN/8, x4, x1, x2)

inst_138:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x22c and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7a2c; op2val:0x8000;
op3val:0x7bff; valaddr_reg:x3; val_offset:414*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 414*FLEN/8, x4, x1, x2)

inst_139:
// fs1 == 0 and fe1 == 0x19 and fm1 == 0x2e4 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x66e4; op2val:0x8000;
op3val:0x7bff; valaddr_reg:x3; val_offset:417*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 417*FLEN/8, x4, x1, x2)

inst_140:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x08d and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x788d; op2val:0x8000;
op3val:0x7bff; valaddr_reg:x3; val_offset:420*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 420*FLEN/8, x4, x1, x2)

inst_141:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1e0 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x79e0; op2val:0x8000;
op3val:0x7bff; valaddr_reg:x3; val_offset:423*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 423*FLEN/8, x4, x1, x2)

inst_142:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x0f5 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x74f5; op2val:0x8000;
op3val:0x7bff; valaddr_reg:x3; val_offset:426*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 426*FLEN/8, x4, x1, x2)

inst_143:
// fs1 == 0 and fe1 == 0x1c and fm1 == 0x31e and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x731e; op2val:0x8000;
op3val:0x7bff; valaddr_reg:x3; val_offset:429*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 429*FLEN/8, x4, x1, x2)

inst_144:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x26d and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7a6d; op2val:0x8000;
op3val:0x7bff; valaddr_reg:x3; val_offset:432*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 432*FLEN/8, x4, x1, x2)

inst_145:
// fs1 == 0 and fe1 == 0x1c and fm1 == 0x3a2 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x73a2; op2val:0x0;
op3val:0x7bff; valaddr_reg:x3; val_offset:435*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 435*FLEN/8, x4, x1, x2)

inst_146:
// fs1 == 0 and fe1 == 0x1c and fm1 == 0x1fe and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x71fe; op2val:0x0;
op3val:0x7bff; valaddr_reg:x3; val_offset:438*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 438*FLEN/8, x4, x1, x2)

inst_147:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x2f5 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x76f5; op2val:0x0;
op3val:0x7bff; valaddr_reg:x3; val_offset:441*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 441*FLEN/8, x4, x1, x2)

inst_148:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x194 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7994; op2val:0x0;
op3val:0x7bff; valaddr_reg:x3; val_offset:444*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 444*FLEN/8, x4, x1, x2)

inst_149:
// fs1 == 0 and fe1 == 0x1b and fm1 == 0x283 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x6e83; op2val:0x0;
op3val:0x7bff; valaddr_reg:x3; val_offset:447*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 447*FLEN/8, x4, x1, x2)

inst_150:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x126 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7526; op2val:0x0;
op3val:0x7bff; valaddr_reg:x3; val_offset:450*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 450*FLEN/8, x4, x1, x2)

inst_151:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x156 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7556; op2val:0x0;
op3val:0x7bff; valaddr_reg:x3; val_offset:453*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 453*FLEN/8, x4, x1, x2)

inst_152:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2aa and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7aaa; op2val:0x0;
op3val:0x7bff; valaddr_reg:x3; val_offset:456*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 456*FLEN/8, x4, x1, x2)

inst_153:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x302 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7702; op2val:0x0;
op3val:0x7bff; valaddr_reg:x3; val_offset:459*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 459*FLEN/8, x4, x1, x2)

inst_154:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2d7 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7ad7; op2val:0x0;
op3val:0x7bff; valaddr_reg:x3; val_offset:462*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 462*FLEN/8, x4, x1, x2)

inst_155:
// fs1 == 0 and fe1 == 0x1c and fm1 == 0x16a and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x716a; op2val:0x0;
op3val:0x7bff; valaddr_reg:x3; val_offset:465*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 465*FLEN/8, x4, x1, x2)

inst_156:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x162 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7562; op2val:0x0;
op3val:0x7bff; valaddr_reg:x3; val_offset:468*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 468*FLEN/8, x4, x1, x2)

inst_157:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x133 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7933; op2val:0x0;
op3val:0x7bff; valaddr_reg:x3; val_offset:471*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 471*FLEN/8, x4, x1, x2)

inst_158:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x313 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7b13; op2val:0x0;
op3val:0x7bff; valaddr_reg:x3; val_offset:474*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 474*FLEN/8, x4, x1, x2)

inst_159:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x336 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7736; op2val:0x8000;
op3val:0x7bff; valaddr_reg:x3; val_offset:477*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 477*FLEN/8, x4, x1, x2)

inst_160:
// fs1 == 0 and fe1 == 0x1c and fm1 == 0x332 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7332; op2val:0x8000;
op3val:0x7bff; valaddr_reg:x3; val_offset:480*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 480*FLEN/8, x4, x1, x2)

inst_161:
// fs1 == 0 and fe1 == 0x1b and fm1 == 0x3bc and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x6fbc; op2val:0x8000;
op3val:0x7bff; valaddr_reg:x3; val_offset:483*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 483*FLEN/8, x4, x1, x2)

inst_162:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x03c and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x783c; op2val:0x8000;
op3val:0x7bff; valaddr_reg:x3; val_offset:486*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 486*FLEN/8, x4, x1, x2)

inst_163:
// fs1 == 0 and fe1 == 0x1c and fm1 == 0x21a and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x721a; op2val:0x8000;
op3val:0x7bff; valaddr_reg:x3; val_offset:489*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 489*FLEN/8, x4, x1, x2)

inst_164:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x273 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7a73; op2val:0x8000;
op3val:0x7bff; valaddr_reg:x3; val_offset:492*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 492*FLEN/8, x4, x1, x2)

inst_165:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2b4 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7ab4; op2val:0x8000;
op3val:0x7bff; valaddr_reg:x3; val_offset:495*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 495*FLEN/8, x4, x1, x2)

inst_166:
// fs1 == 0 and fe1 == 0x1c and fm1 == 0x1df and fs2 == 1 and fe2 == 0x07 and fm2 == 0x2cf and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x71df; op2val:0x9ecf;
op3val:0x7bff; valaddr_reg:x3; val_offset:498*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 498*FLEN/8, x4, x1, x2)

inst_167:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x074 and fs2 == 1 and fe2 == 0x07 and fm2 == 0x07d and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7474; op2val:0x9c7d;
op3val:0x7bff; valaddr_reg:x3; val_offset:501*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 501*FLEN/8, x4, x1, x2)

inst_168:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x274 and fs2 == 1 and fe2 == 0x05 and fm2 == 0x232 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7a74; op2val:0x9632;
op3val:0x7bff; valaddr_reg:x3; val_offset:504*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 504*FLEN/8, x4, x1, x2)

inst_169:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x122 and fs2 == 1 and fe2 == 0x05 and fm2 == 0x3ca and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7922; op2val:0x97ca;
op3val:0x7bff; valaddr_reg:x3; val_offset:507*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 507*FLEN/8, x4, x1, x2)

inst_170:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x272 and fs2 == 1 and fe2 == 0x05 and fm2 == 0x234 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7a72; op2val:0x9634;
op3val:0x7bff; valaddr_reg:x3; val_offset:510*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 510*FLEN/8, x4, x1, x2)

inst_171:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x185 and fs2 == 1 and fe2 == 0x06 and fm2 == 0x33e and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7585; op2val:0x9b3e;
op3val:0x7bff; valaddr_reg:x3; val_offset:513*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 513*FLEN/8, x4, x1, x2)

inst_172:
// fs1 == 0 and fe1 == 0x1c and fm1 == 0x026 and fs2 == 1 and fe2 == 0x08 and fm2 == 0x0d2 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7026; op2val:0xa0d2;
op3val:0x7bff; valaddr_reg:x3; val_offset:516*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 516*FLEN/8, x4, x1, x2)

inst_173:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x0ab and fs2 == 0 and fe2 == 0x07 and fm2 == 0x048 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x74ab; op2val:0x1c48;
op3val:0x7bff; valaddr_reg:x3; val_offset:519*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 519*FLEN/8, x4, x1, x2)

inst_174:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x259 and fs2 == 0 and fe2 == 0x05 and fm2 == 0x24d and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7a59; op2val:0x164d;
op3val:0x7bff; valaddr_reg:x3; val_offset:522*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 522*FLEN/8, x4, x1, x2)

inst_175:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x056 and fs2 == 0 and fe2 == 0x07 and fm2 == 0x09c and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7456; op2val:0x1c9c;
op3val:0x7bff; valaddr_reg:x3; val_offset:525*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 525*FLEN/8, x4, x1, x2)

inst_176:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x18a and fs2 == 0 and fe2 == 0x06 and fm2 == 0x338 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x758a; op2val:0x1b38;
op3val:0x7bff; valaddr_reg:x3; val_offset:528*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 528*FLEN/8, x4, x1, x2)

inst_177:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x2aa and fs2 == 0 and fe2 == 0x06 and fm2 == 0x1ff and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x76aa; op2val:0x19ff;
op3val:0x7bff; valaddr_reg:x3; val_offset:531*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 531*FLEN/8, x4, x1, x2)

inst_178:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x2b6 and fs2 == 0 and fe2 == 0x06 and fm2 == 0x1f5 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x76b6; op2val:0x19f5;
op3val:0x7bff; valaddr_reg:x3; val_offset:534*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 534*FLEN/8, x4, x1, x2)

inst_179:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x28c and fs2 == 0 and fe2 == 0x06 and fm2 == 0x21b and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x768c; op2val:0x1a1b;
op3val:0x7bff; valaddr_reg:x3; val_offset:537*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 537*FLEN/8, x4, x1, x2)

inst_180:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x35c and fs2 == 0 and fe2 == 0x05 and fm2 == 0x16f and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7b5c; op2val:0x156f;
op3val:0x7bff; valaddr_reg:x3; val_offset:540*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 540*FLEN/8, x4, x1, x2)

inst_181:
// fs1 == 0 and fe1 == 0x1c and fm1 == 0x0fd and fs2 == 0 and fe2 == 0x08 and fm2 == 0x002 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x70fd; op2val:0x2002;
op3val:0x7bff; valaddr_reg:x3; val_offset:543*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 543*FLEN/8, x4, x1, x2)

inst_182:
// fs1 == 0 and fe1 == 0x17 and fm1 == 0x0c9 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x02d and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x5cc9; op2val:0x342d;
op3val:0x7bff; valaddr_reg:x3; val_offset:546*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 546*FLEN/8, x4, x1, x2)

inst_183:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x38a and fs2 == 0 and fe2 == 0x05 and fm2 == 0x14d and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7b8a; op2val:0x154d;
op3val:0x7bff; valaddr_reg:x3; val_offset:549*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 549*FLEN/8, x4, x1, x2)

inst_184:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x309 and fs2 == 0 and fe2 == 0x05 and fm2 == 0x1af and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7b09; op2val:0x15af;
op3val:0x7bff; valaddr_reg:x3; val_offset:552*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 552*FLEN/8, x4, x1, x2)

inst_185:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3e4 and fs2 == 0 and fe2 == 0x05 and fm2 == 0x111 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7be4; op2val:0x1511;
op3val:0x7bff; valaddr_reg:x3; val_offset:555*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 555*FLEN/8, x4, x1, x2)

inst_186:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x2f2 and fs2 == 0 and fe2 == 0x06 and fm2 == 0x1c2 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x76f2; op2val:0x19c2;
op3val:0x7bff; valaddr_reg:x3; val_offset:558*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 558*FLEN/8, x4, x1, x2)

inst_187:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x398 and fs2 == 1 and fe2 == 0x05 and fm2 == 0x143 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7b98; op2val:0x9543;
op3val:0x7bff; valaddr_reg:x3; val_offset:561*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 561*FLEN/8, x4, x1, x2)

inst_188:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x36a and fs2 == 1 and fe2 == 0x05 and fm2 == 0x164 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7b6a; op2val:0x9564;
op3val:0x7bff; valaddr_reg:x3; val_offset:564*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 564*FLEN/8, x4, x1, x2)

inst_189:
// fs1 == 0 and fe1 == 0x1c and fm1 == 0x31a and fs2 == 1 and fe2 == 0x07 and fm2 == 0x1a1 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x731a; op2val:0x9da1;
op3val:0x7bff; valaddr_reg:x3; val_offset:567*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 567*FLEN/8, x4, x1, x2)

inst_190:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1f6 and fs2 == 1 and fe2 == 0x05 and fm2 == 0x2b5 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x79f6; op2val:0x96b5;
op3val:0x7bff; valaddr_reg:x3; val_offset:570*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 570*FLEN/8, x4, x1, x2)

inst_191:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2b0 and fs2 == 1 and fe2 == 0x05 and fm2 == 0x1fa and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7ab0; op2val:0x95fa;
op3val:0x7bff; valaddr_reg:x3; val_offset:573*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 573*FLEN/8, x4, x1, x2)

inst_192:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x14d and fs2 == 1 and fe2 == 0x05 and fm2 == 0x38b and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x794d; op2val:0x978b;
op3val:0x7bff; valaddr_reg:x3; val_offset:576*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 576*FLEN/8, x4, x1, x2)

inst_193:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x026 and fs2 == 1 and fe2 == 0x06 and fm2 == 0x0d1 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7826; op2val:0x98d1;
op3val:0x7bff; valaddr_reg:x3; val_offset:579*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 579*FLEN/8, x4, x1, x2)

inst_194:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x09f and fs2 == 1 and fe2 == 0x00 and fm2 == 0x029 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x749f; op2val:0x8029;
op3val:0x7bff; valaddr_reg:x3; val_offset:582*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 582*FLEN/8, x4, x1, x2)

inst_195:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x174 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x023 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7574; op2val:0x8023;
op3val:0x7bff; valaddr_reg:x3; val_offset:585*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 585*FLEN/8, x4, x1, x2)

inst_196:
// fs1 == 0 and fe1 == 0x1c and fm1 == 0x346 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x034 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7346; op2val:0x8034;
op3val:0x7bff; valaddr_reg:x3; val_offset:588*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 588*FLEN/8, x4, x1, x2)

inst_197:
// fs1 == 0 and fe1 == 0x1b and fm1 == 0x05a and fs2 == 1 and fe2 == 0x00 and fm2 == 0x0b0 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x6c5a; op2val:0x80b0;
op3val:0x7bff; valaddr_reg:x3; val_offset:591*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 591*FLEN/8, x4, x1, x2)

inst_198:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0b5 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x014 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x78b5; op2val:0x8014;
op3val:0x7bff; valaddr_reg:x3; val_offset:594*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 594*FLEN/8, x4, x1, x2)

inst_199:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x097 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x029 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7497; op2val:0x8029;
op3val:0x7bff; valaddr_reg:x3; val_offset:597*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 597*FLEN/8, x4, x1, x2)

inst_200:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x27a and fs2 == 1 and fe2 == 0x00 and fm2 == 0x00e and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7a7a; op2val:0x800e;
op3val:0x7bff; valaddr_reg:x3; val_offset:600*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 600*FLEN/8, x4, x1, x2)

inst_201:
// fs1 == 0 and fe1 == 0x1a and fm1 == 0x1c4 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x10a and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x69c4; op2val:0x10a;
op3val:0x7bff; valaddr_reg:x3; val_offset:603*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 603*FLEN/8, x4, x1, x2)

inst_202:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x339 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x00d and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7b39; op2val:0xd;
op3val:0x7bff; valaddr_reg:x3; val_offset:606*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 606*FLEN/8, x4, x1, x2)

inst_203:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x18c and fs2 == 0 and fe2 == 0x00 and fm2 == 0x011 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x798c; op2val:0x11;
op3val:0x7bff; valaddr_reg:x3; val_offset:609*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 609*FLEN/8, x4, x1, x2)

inst_204:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x363 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x00c and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7b63; op2val:0xc;
op3val:0x7bff; valaddr_reg:x3; val_offset:612*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 612*FLEN/8, x4, x1, x2)

inst_205:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x32b and fs2 == 0 and fe2 == 0x00 and fm2 == 0x00d and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7b2b; op2val:0xd;
op3val:0x7bff; valaddr_reg:x3; val_offset:615*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 615*FLEN/8, x4, x1, x2)

inst_206:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x331 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x00d and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7b31; op2val:0xd;
op3val:0x7bff; valaddr_reg:x3; val_offset:618*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 618*FLEN/8, x4, x1, x2)

inst_207:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x09d and fs2 == 0 and fe2 == 0x00 and fm2 == 0x014 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x789d; op2val:0x14;
op3val:0x7bff; valaddr_reg:x3; val_offset:621*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 621*FLEN/8, x4, x1, x2)

inst_208:
// fs1 == 0 and fe1 == 0x18 and fm1 == 0x2bc and fs2 == 0 and fe2 == 0x00 and fm2 == 0x390 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x62bc; op2val:0x390;
op3val:0x7bff; valaddr_reg:x3; val_offset:624*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 624*FLEN/8, x4, x1, x2)

inst_209:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1f5 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x010 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x79f5; op2val:0x10;
op3val:0x7bff; valaddr_reg:x3; val_offset:627*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 627*FLEN/8, x4, x1, x2)

inst_210:
// fs1 == 0 and fe1 == 0x1c and fm1 == 0x17e and fs2 == 0 and fe2 == 0x00 and fm2 == 0x045 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x717e; op2val:0x45;
op3val:0x7bff; valaddr_reg:x3; val_offset:630*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 630*FLEN/8, x4, x1, x2)

inst_211:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x0cb and fs2 == 0 and fe2 == 0x00 and fm2 == 0x028 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x74cb; op2val:0x28;
op3val:0x7bff; valaddr_reg:x3; val_offset:633*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 633*FLEN/8, x4, x1, x2)

inst_212:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x14c and fs2 == 0 and fe2 == 0x00 and fm2 == 0x012 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x794c; op2val:0x12;
op3val:0x7bff; valaddr_reg:x3; val_offset:636*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 636*FLEN/8, x4, x1, x2)

inst_213:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x032 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x016 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7832; op2val:0x16;
op3val:0x7bff; valaddr_reg:x3; val_offset:639*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 639*FLEN/8, x4, x1, x2)

inst_214:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x29d and fs2 == 0 and fe2 == 0x00 and fm2 == 0x01d and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x769d; op2val:0x1d;
op3val:0x7bff; valaddr_reg:x3; val_offset:642*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 642*FLEN/8, x4, x1, x2)

inst_215:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x382 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x00c and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7b82; op2val:0x800c;
op3val:0x7bff; valaddr_reg:x3; val_offset:645*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 645*FLEN/8, x4, x1, x2)

inst_216:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0e5 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x013 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x78e5; op2val:0x8013;
op3val:0x7bff; valaddr_reg:x3; val_offset:648*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 648*FLEN/8, x4, x1, x2)

inst_217:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x175 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x023 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7575; op2val:0x8023;
op3val:0x7bff; valaddr_reg:x3; val_offset:651*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 651*FLEN/8, x4, x1, x2)

inst_218:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x009 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x02f and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7409; op2val:0x802f;
op3val:0x7bff; valaddr_reg:x3; val_offset:654*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 654*FLEN/8, x4, x1, x2)

inst_219:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2e3 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x00d and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7ae3; op2val:0x800d;
op3val:0x7bff; valaddr_reg:x3; val_offset:657*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 657*FLEN/8, x4, x1, x2)

inst_220:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x3a1 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x019 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x77a1; op2val:0x8019;
op3val:0x7bff; valaddr_reg:x3; val_offset:660*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 660*FLEN/8, x4, x1, x2)

inst_221:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x241 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x00f and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7a41; op2val:0x800f;
op3val:0x7bff; valaddr_reg:x3; val_offset:663*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 663*FLEN/8, x4, x1, x2)

inst_222:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x1a0 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x1af and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x75a0; op2val:0xc1af;
op3val:0x7bff; valaddr_reg:x3; val_offset:666*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 666*FLEN/8, x4, x1, x2)

inst_223:
// fs1 == 0 and fe1 == 0x1c and fm1 == 0x24f and fs2 == 0 and fe2 == 0x11 and fm2 == 0x111 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x724f; op2val:0x4511;
op3val:0x7bff; valaddr_reg:x3; val_offset:669*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 669*FLEN/8, x4, x1, x2)

inst_224:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x046 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x37b and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7846; op2val:0xbf7b;
op3val:0x7bff; valaddr_reg:x3; val_offset:672*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 672*FLEN/8, x4, x1, x2)

inst_225:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x288 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x0e5 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7a88; op2val:0x3ce5;
op3val:0x7bff; valaddr_reg:x3; val_offset:675*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 675*FLEN/8, x4, x1, x2)

inst_226:
// fs1 == 0 and fe1 == 0x1c and fm1 == 0x17a and fs2 == 1 and fe2 == 0x11 and fm2 == 0x1d6 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x717a; op2val:0xc5d6;
op3val:0x7bff; valaddr_reg:x3; val_offset:678*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 678*FLEN/8, x4, x1, x2)

inst_227:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x254 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x10d and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7a54; op2val:0x3d0d;
op3val:0x7bff; valaddr_reg:x3; val_offset:681*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 681*FLEN/8, x4, x1, x2)

inst_228:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x35e and fs2 == 1 and fe2 == 0x0f and fm2 == 0x056 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7b5e; op2val:0xbc56;
op3val:0x7bff; valaddr_reg:x3; val_offset:684*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 684*FLEN/8, x4, x1, x2)

inst_229:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x271 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x0f6 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7a71; op2val:0x3cf6;
op3val:0x7bff; valaddr_reg:x3; val_offset:687*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 687*FLEN/8, x4, x1, x2)

inst_230:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x295 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x0db and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7a95; op2val:0xbcdb;
op3val:0x7bff; valaddr_reg:x3; val_offset:690*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 690*FLEN/8, x4, x1, x2)

inst_231:
// fs1 == 0 and fe1 == 0x17 and fm1 == 0x3b2 and fs2 == 0 and fe2 == 0x16 and fm2 == 0x027 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x5fb2; op2val:0x5827;
op3val:0x7bff; valaddr_reg:x3; val_offset:693*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 693*FLEN/8, x4, x1, x2)

inst_232:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x106 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x25c and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7906; op2val:0xbe5c;
op3val:0x7bff; valaddr_reg:x3; val_offset:696*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 696*FLEN/8, x4, x1, x2)

inst_233:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2e5 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x0a3 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7ae5; op2val:0x3ca3;
op3val:0x7bff; valaddr_reg:x3; val_offset:699*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 699*FLEN/8, x4, x1, x2)

inst_234:
// fs1 == 0 and fe1 == 0x1a and fm1 == 0x263 and fs2 == 1 and fe2 == 0x13 and fm2 == 0x101 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x6a63; op2val:0xcd01;
op3val:0x7bff; valaddr_reg:x3; val_offset:702*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 702*FLEN/8, x4, x1, x2)

inst_235:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x057 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x35e and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7457; op2val:0x435e;
op3val:0x7bff; valaddr_reg:x3; val_offset:705*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 705*FLEN/8, x4, x1, x2)

inst_236:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x04b and fs2 == 1 and fe2 == 0x0d and fm2 == 0x372 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x744b; op2val:0xb772;
op3val:0x7bff; valaddr_reg:x3; val_offset:708*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 708*FLEN/8, x4, x1, x2)

inst_237:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x037 and fs2 == 0 and fe2 == 0x0c and fm2 == 0x396 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7837; op2val:0x3396;
op3val:0x7bff; valaddr_reg:x3; val_offset:711*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 711*FLEN/8, x4, x1, x2)

inst_238:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x2c3 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x0ba and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x76c3; op2val:0xb8ba;
op3val:0x7bff; valaddr_reg:x3; val_offset:714*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 714*FLEN/8, x4, x1, x2)

inst_239:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x390 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x03a and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7790; op2val:0x383a;
op3val:0x7bff; valaddr_reg:x3; val_offset:717*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 717*FLEN/8, x4, x1, x2)

inst_240:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x235 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x126 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7a35; op2val:0xb926;
op3val:0x7bff; valaddr_reg:x3; val_offset:720*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 720*FLEN/8, x4, x1, x2)

inst_241:
// fs1 == 0 and fe1 == 0x15 and fm1 == 0x377 and fs2 == 0 and fe2 == 0x17 and fm2 == 0x048 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x5777; op2val:0x5c48;
op3val:0x7bff; valaddr_reg:x3; val_offset:723*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 723*FLEN/8, x4, x1, x2)

inst_242:
// fs1 == 0 and fe1 == 0x1a and fm1 == 0x304 and fs2 == 1 and fe2 == 0x13 and fm2 == 0x08e and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x6b04; op2val:0xcc8e;
op3val:0x7bff; valaddr_reg:x3; val_offset:726*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 726*FLEN/8, x4, x1, x2)

inst_243:
// fs1 == 0 and fe1 == 0x1c and fm1 == 0x00e and fs2 == 0 and fe2 == 0x11 and fm2 == 0x3e1 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x700e; op2val:0x47e1;
op3val:0x7bff; valaddr_reg:x3; val_offset:729*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 729*FLEN/8, x4, x1, x2)

inst_244:
// fs1 == 0 and fe1 == 0x1b and fm1 == 0x3f9 and fs2 == 1 and fe2 == 0x13 and fm2 == 0x002 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x6ff9; op2val:0xcc02;
op3val:0x7bff; valaddr_reg:x3; val_offset:732*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 732*FLEN/8, x4, x1, x2)

inst_245:
// fs1 == 0 and fe1 == 0x1b and fm1 == 0x060 and fs2 == 0 and fe2 == 0x13 and fm2 == 0x34e and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x6c60; op2val:0x4f4e;
op3val:0x7bff; valaddr_reg:x3; val_offset:735*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 735*FLEN/8, x4, x1, x2)

inst_246:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3cb and fs2 == 1 and fe2 == 0x11 and fm2 == 0x01a and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7bcb; op2val:0xc41a;
op3val:0x7bff; valaddr_reg:x3; val_offset:738*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 738*FLEN/8, x4, x1, x2)

inst_247:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2d5 and fs2 == 0 and fe2 == 0x11 and fm2 == 0x0ae and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7ad5; op2val:0x44ae;
op3val:0x7bff; valaddr_reg:x3; val_offset:741*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 741*FLEN/8, x4, x1, x2)

inst_248:
// fs1 == 0 and fe1 == 0x1b and fm1 == 0x182 and fs2 == 1 and fe2 == 0x15 and fm2 == 0x1cd and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x6d82; op2val:0xd5cd;
op3val:0x7bff; valaddr_reg:x3; val_offset:744*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 744*FLEN/8, x4, x1, x2)

inst_249:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x003 and fs2 == 0 and fe2 == 0x12 and fm2 == 0x3f7 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7803; op2val:0x4bf7;
op3val:0x7bff; valaddr_reg:x3; val_offset:747*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 747*FLEN/8, x4, x1, x2)

inst_250:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x10d and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x750d; op2val:0x8000;
op3val:0x7bff; valaddr_reg:x3; val_offset:750*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 750*FLEN/8, x4, x1, x2)

inst_251:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x107 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7507; op2val:0x8000;
op3val:0x7bff; valaddr_reg:x3; val_offset:753*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 753*FLEN/8, x4, x1, x2)

inst_252:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x19e and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x759e; op2val:0x8000;
op3val:0x7bff; valaddr_reg:x3; val_offset:756*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 756*FLEN/8, x4, x1, x2)

inst_253:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x12c and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x792c; op2val:0x8000;
op3val:0x7bff; valaddr_reg:x3; val_offset:759*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 759*FLEN/8, x4, x1, x2)

inst_254:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0b0 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x78b0; op2val:0x8000;
op3val:0x7bff; valaddr_reg:x3; val_offset:762*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 762*FLEN/8, x4, x1, x2)

inst_255:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x1c5 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x75c5; op2val:0x8000;
op3val:0x7bff; valaddr_reg:x3; val_offset:765*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 765*FLEN/8, x4, x1, x2)
RVTEST_SIGBASE(x1,signature_x1_3)

inst_256:
// fs1 == 0 and fe1 == 0x1c and fm1 == 0x21c and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x721c; op2val:0x8000;
op3val:0x7bff; valaddr_reg:x3; val_offset:768*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 768*FLEN/8, x4, x1, x2)

inst_257:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x142 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7542; op2val:0x8000;
op3val:0x7bff; valaddr_reg:x3; val_offset:771*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 771*FLEN/8, x4, x1, x2)

inst_258:
// fs1 == 0 and fe1 == 0x1b and fm1 == 0x3ea and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x6fea; op2val:0x8000;
op3val:0x7bff; valaddr_reg:x3; val_offset:774*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 774*FLEN/8, x4, x1, x2)

inst_259:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x071 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7871; op2val:0x8000;
op3val:0x7bff; valaddr_reg:x3; val_offset:777*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 777*FLEN/8, x4, x1, x2)

inst_260:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1b9 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x79b9; op2val:0x8000;
op3val:0x7bff; valaddr_reg:x3; val_offset:780*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 780*FLEN/8, x4, x1, x2)

inst_261:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x214 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7614; op2val:0x8000;
op3val:0x7bff; valaddr_reg:x3; val_offset:783*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 783*FLEN/8, x4, x1, x2)

inst_262:
// fs1 == 0 and fe1 == 0x1b and fm1 == 0x11c and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x6d1c; op2val:0x8000;
op3val:0x7bff; valaddr_reg:x3; val_offset:786*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 786*FLEN/8, x4, x1, x2)

inst_263:
// fs1 == 0 and fe1 == 0x1c and fm1 == 0x1b6 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x71b6; op2val:0x8000;
op3val:0x7bff; valaddr_reg:x3; val_offset:789*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 789*FLEN/8, x4, x1, x2)

inst_264:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x1f8 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x75f8; op2val:0x8000;
op3val:0x7bff; valaddr_reg:x3; val_offset:792*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 792*FLEN/8, x4, x1, x2)

inst_265:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0d5 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x78d5; op2val:0x8000;
op3val:0x7bff; valaddr_reg:x3; val_offset:795*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 795*FLEN/8, x4, x1, x2)

inst_266:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x242 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7a42; op2val:0x0;
op3val:0x7bff; valaddr_reg:x3; val_offset:798*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 798*FLEN/8, x4, x1, x2)

inst_267:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x214 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7614; op2val:0x0;
op3val:0x7bff; valaddr_reg:x3; val_offset:801*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 801*FLEN/8, x4, x1, x2)

inst_268:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x267 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7a67; op2val:0x0;
op3val:0x7bff; valaddr_reg:x3; val_offset:804*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 804*FLEN/8, x4, x1, x2)

inst_269:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0fb and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x78fb; op2val:0x0;
op3val:0x7bff; valaddr_reg:x3; val_offset:807*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 807*FLEN/8, x4, x1, x2)

inst_270:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x2e6 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x76e6; op2val:0x0;
op3val:0x7bff; valaddr_reg:x3; val_offset:810*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 810*FLEN/8, x4, x1, x2)

inst_271:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x1f4 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x75f4; op2val:0x0;
op3val:0x7bff; valaddr_reg:x3; val_offset:813*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 813*FLEN/8, x4, x1, x2)

inst_272:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x3ef and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x77ef; op2val:0x0;
op3val:0x7bff; valaddr_reg:x3; val_offset:816*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 816*FLEN/8, x4, x1, x2)

inst_273:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x19e and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x799e; op2val:0x0;
op3val:0x7bff; valaddr_reg:x3; val_offset:819*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 819*FLEN/8, x4, x1, x2)

inst_274:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x2b9 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x76b9; op2val:0x0;
op3val:0x7bff; valaddr_reg:x3; val_offset:822*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 822*FLEN/8, x4, x1, x2)

inst_275:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x18c and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x798c; op2val:0x0;
op3val:0x7bff; valaddr_reg:x3; val_offset:825*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 825*FLEN/8, x4, x1, x2)

inst_276:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x35e and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x775e; op2val:0x0;
op3val:0x7bff; valaddr_reg:x3; val_offset:828*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 828*FLEN/8, x4, x1, x2)

inst_277:
// fs1 == 0 and fe1 == 0x1c and fm1 == 0x3d6 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x73d6; op2val:0x0;
op3val:0x7bff; valaddr_reg:x3; val_offset:831*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 831*FLEN/8, x4, x1, x2)

inst_278:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x048 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7848; op2val:0x0;
op3val:0x7bff; valaddr_reg:x3; val_offset:834*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 834*FLEN/8, x4, x1, x2)

inst_279:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x18f and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x798f; op2val:0x0;
op3val:0x7bff; valaddr_reg:x3; val_offset:837*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 837*FLEN/8, x4, x1, x2)

inst_280:
// fs1 == 0 and fe1 == 0x1b and fm1 == 0x094 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x6c94; op2val:0x0;
op3val:0x7bff; valaddr_reg:x3; val_offset:840*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 840*FLEN/8, x4, x1, x2)

inst_281:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x2cb and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x76cb; op2val:0x0;
op3val:0x7bff; valaddr_reg:x3; val_offset:843*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 843*FLEN/8, x4, x1, x2)

inst_282:
// fs1 == 0 and fe1 == 0x1c and fm1 == 0x39c and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x739c; op2val:0x8000;
op3val:0x7bff; valaddr_reg:x3; val_offset:846*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 846*FLEN/8, x4, x1, x2)

inst_283:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x05a and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x785a; op2val:0x8000;
op3val:0x7bff; valaddr_reg:x3; val_offset:849*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 849*FLEN/8, x4, x1, x2)

inst_284:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x100 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7900; op2val:0x8000;
op3val:0x7bff; valaddr_reg:x3; val_offset:852*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 852*FLEN/8, x4, x1, x2)

inst_285:
// fs1 == 0 and fe1 == 0x18 and fm1 == 0x2bf and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x62bf; op2val:0x8000;
op3val:0x7bff; valaddr_reg:x3; val_offset:855*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 855*FLEN/8, x4, x1, x2)

inst_286:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2b2 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7ab2; op2val:0x0;
op3val:0x7bff; valaddr_reg:x3; val_offset:858*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 858*FLEN/8, x4, x1, x2)

inst_287:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x025 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7425; op2val:0x0;
op3val:0x7bff; valaddr_reg:x3; val_offset:861*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 861*FLEN/8, x4, x1, x2)

inst_288:
// fs1 == 0 and fe1 == 0x1c and fm1 == 0x37e and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x737e; op2val:0x0;
op3val:0x7bff; valaddr_reg:x3; val_offset:864*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 864*FLEN/8, x4, x1, x2)

inst_289:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3f6 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7bf6; op2val:0x0;
op3val:0x7bff; valaddr_reg:x3; val_offset:867*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 867*FLEN/8, x4, x1, x2)
#endif


RVTEST_CODE_END
RVMODEL_HALT

RVTEST_DATA_BEGIN
.align 4
rvtest_data:
.word 0xbabecafe
.word 0xabecafeb
.word 0xbecafeba
.word 0xecafebab
test_dataset_0:
NAN_BOXED(29596,16,FLEN)
NAN_BOXED(29596,16,FLEN)
NAN_BOXED(29596,16,FLEN)
NAN_BOXED(30810,16,FLEN)
NAN_BOXED(32768,16,FLEN)
NAN_BOXED(30810,16,FLEN)
NAN_BOXED(30186,16,FLEN)
NAN_BOXED(32768,16,FLEN)
NAN_BOXED(31743,16,FLEN)
NAN_BOXED(30932,16,FLEN)
NAN_BOXED(32768,16,FLEN)
NAN_BOXED(31743,16,FLEN)
NAN_BOXED(30976,16,FLEN)
NAN_BOXED(32768,16,FLEN)
NAN_BOXED(32768,16,FLEN)
NAN_BOXED(27697,16,FLEN)
NAN_BOXED(32768,16,FLEN)
NAN_BOXED(31743,16,FLEN)
NAN_BOXED(25279,16,FLEN)
NAN_BOXED(32768,16,FLEN)
NAN_BOXED(25279,16,FLEN)
NAN_BOXED(31410,16,FLEN)
NAN_BOXED(31410,16,FLEN)
NAN_BOXED(31410,16,FLEN)
NAN_BOXED(29733,16,FLEN)
NAN_BOXED(0,16,FLEN)
NAN_BOXED(0,16,FLEN)
NAN_BOXED(29566,16,FLEN)
NAN_BOXED(29566,16,FLEN)
NAN_BOXED(31743,16,FLEN)
NAN_BOXED(31734,16,FLEN)
NAN_BOXED(31734,16,FLEN)
NAN_BOXED(31743,16,FLEN)
NAN_BOXED(30597,16,FLEN)
NAN_BOXED(0,16,FLEN)
NAN_BOXED(31743,16,FLEN)
NAN_BOXED(31408,16,FLEN)
NAN_BOXED(0,16,FLEN)
NAN_BOXED(31743,16,FLEN)
NAN_BOXED(30622,16,FLEN)
NAN_BOXED(0,16,FLEN)
NAN_BOXED(31743,16,FLEN)
NAN_BOXED(31004,16,FLEN)
NAN_BOXED(0,16,FLEN)
NAN_BOXED(31743,16,FLEN)
NAN_BOXED(28881,16,FLEN)
NAN_BOXED(0,16,FLEN)
NAN_BOXED(31743,16,FLEN)
NAN_BOXED(30995,16,FLEN)
NAN_BOXED(0,16,FLEN)
NAN_BOXED(31743,16,FLEN)
NAN_BOXED(31472,16,FLEN)
NAN_BOXED(0,16,FLEN)
NAN_BOXED(31743,16,FLEN)
NAN_BOXED(30766,16,FLEN)
NAN_BOXED(0,16,FLEN)
NAN_BOXED(31743,16,FLEN)
NAN_BOXED(31213,16,FLEN)
NAN_BOXED(0,16,FLEN)
NAN_BOXED(31743,16,FLEN)
NAN_BOXED(31070,16,FLEN)
NAN_BOXED(0,16,FLEN)
NAN_BOXED(31743,16,FLEN)
NAN_BOXED(27672,16,FLEN)
NAN_BOXED(32768,16,FLEN)
NAN_BOXED(31743,16,FLEN)
NAN_BOXED(31248,16,FLEN)
NAN_BOXED(32768,16,FLEN)
NAN_BOXED(31743,16,FLEN)
NAN_BOXED(30905,16,FLEN)
NAN_BOXED(32768,16,FLEN)
NAN_BOXED(31743,16,FLEN)
NAN_BOXED(29905,16,FLEN)
NAN_BOXED(32768,16,FLEN)
NAN_BOXED(31743,16,FLEN)
NAN_BOXED(26608,16,FLEN)
NAN_BOXED(32768,16,FLEN)
NAN_BOXED(31743,16,FLEN)
NAN_BOXED(31467,16,FLEN)
NAN_BOXED(32768,16,FLEN)
NAN_BOXED(31743,16,FLEN)
NAN_BOXED(30607,16,FLEN)
NAN_BOXED(32768,16,FLEN)
NAN_BOXED(31743,16,FLEN)
NAN_BOXED(31167,16,FLEN)
NAN_BOXED(32768,16,FLEN)
NAN_BOXED(31743,16,FLEN)
NAN_BOXED(31494,16,FLEN)
NAN_BOXED(32768,16,FLEN)
NAN_BOXED(31743,16,FLEN)
NAN_BOXED(31157,16,FLEN)
NAN_BOXED(32768,16,FLEN)
NAN_BOXED(31743,16,FLEN)
NAN_BOXED(31581,16,FLEN)
NAN_BOXED(32768,16,FLEN)
NAN_BOXED(31743,16,FLEN)
NAN_BOXED(30289,16,FLEN)
NAN_BOXED(32768,16,FLEN)
NAN_BOXED(31743,16,FLEN)
NAN_BOXED(31335,16,FLEN)
NAN_BOXED(32768,16,FLEN)
NAN_BOXED(31743,16,FLEN)
NAN_BOXED(30492,16,FLEN)
NAN_BOXED(32768,16,FLEN)
NAN_BOXED(31743,16,FLEN)
NAN_BOXED(31611,16,FLEN)
NAN_BOXED(0,16,FLEN)
NAN_BOXED(31743,16,FLEN)
NAN_BOXED(31495,16,FLEN)
NAN_BOXED(0,16,FLEN)
NAN_BOXED(31743,16,FLEN)
NAN_BOXED(28220,16,FLEN)
NAN_BOXED(0,16,FLEN)
NAN_BOXED(31743,16,FLEN)
NAN_BOXED(28761,16,FLEN)
NAN_BOXED(0,16,FLEN)
NAN_BOXED(31743,16,FLEN)
NAN_BOXED(29424,16,FLEN)
NAN_BOXED(0,16,FLEN)
NAN_BOXED(31743,16,FLEN)
NAN_BOXED(31672,16,FLEN)
NAN_BOXED(0,16,FLEN)
NAN_BOXED(31743,16,FLEN)
NAN_BOXED(30457,16,FLEN)
NAN_BOXED(0,16,FLEN)
NAN_BOXED(31743,16,FLEN)
NAN_BOXED(30978,16,FLEN)
NAN_BOXED(0,16,FLEN)
NAN_BOXED(31743,16,FLEN)
NAN_BOXED(29904,16,FLEN)
NAN_BOXED(0,16,FLEN)
NAN_BOXED(31743,16,FLEN)
NAN_BOXED(30734,16,FLEN)
NAN_BOXED(0,16,FLEN)
NAN_BOXED(31743,16,FLEN)
NAN_BOXED(30251,16,FLEN)
NAN_BOXED(0,16,FLEN)
NAN_BOXED(31743,16,FLEN)
NAN_BOXED(30108,16,FLEN)
NAN_BOXED(0,16,FLEN)
NAN_BOXED(31743,16,FLEN)
NAN_BOXED(30893,16,FLEN)
NAN_BOXED(0,16,FLEN)
NAN_BOXED(31743,16,FLEN)
NAN_BOXED(30891,16,FLEN)
NAN_BOXED(0,16,FLEN)
NAN_BOXED(31743,16,FLEN)
NAN_BOXED(31546,16,FLEN)
NAN_BOXED(32768,16,FLEN)
NAN_BOXED(31743,16,FLEN)
NAN_BOXED(31092,16,FLEN)
NAN_BOXED(32768,16,FLEN)
NAN_BOXED(31743,16,FLEN)
NAN_BOXED(31597,16,FLEN)
NAN_BOXED(32768,16,FLEN)
NAN_BOXED(31743,16,FLEN)
NAN_BOXED(31449,16,FLEN)
NAN_BOXED(32768,16,FLEN)
NAN_BOXED(31743,16,FLEN)
NAN_BOXED(31724,16,FLEN)
NAN_BOXED(32768,16,FLEN)
NAN_BOXED(31743,16,FLEN)
NAN_BOXED(31070,16,FLEN)
NAN_BOXED(32768,16,FLEN)
NAN_BOXED(31743,16,FLEN)
NAN_BOXED(28983,16,FLEN)
NAN_BOXED(32768,16,FLEN)
NAN_BOXED(31743,16,FLEN)
NAN_BOXED(31457,16,FLEN)
NAN_BOXED(32768,16,FLEN)
NAN_BOXED(31743,16,FLEN)
NAN_BOXED(31670,16,FLEN)
NAN_BOXED(32768,16,FLEN)
NAN_BOXED(31743,16,FLEN)
NAN_BOXED(31547,16,FLEN)
NAN_BOXED(32768,16,FLEN)
NAN_BOXED(31743,16,FLEN)
NAN_BOXED(30860,16,FLEN)
NAN_BOXED(32768,16,FLEN)
NAN_BOXED(31743,16,FLEN)
NAN_BOXED(29376,16,FLEN)
NAN_BOXED(32768,16,FLEN)
NAN_BOXED(31743,16,FLEN)
NAN_BOXED(31398,16,FLEN)
NAN_BOXED(32768,16,FLEN)
NAN_BOXED(31743,16,FLEN)
NAN_BOXED(30870,16,FLEN)
NAN_BOXED(0,16,FLEN)
NAN_BOXED(31743,16,FLEN)
NAN_BOXED(29838,16,FLEN)
NAN_BOXED(0,16,FLEN)
NAN_BOXED(31743,16,FLEN)
NAN_BOXED(27663,16,FLEN)
NAN_BOXED(0,16,FLEN)
NAN_BOXED(31743,16,FLEN)
NAN_BOXED(31444,16,FLEN)
NAN_BOXED(0,16,FLEN)
NAN_BOXED(31743,16,FLEN)
NAN_BOXED(31722,16,FLEN)
NAN_BOXED(0,16,FLEN)
NAN_BOXED(31743,16,FLEN)
NAN_BOXED(28073,16,FLEN)
NAN_BOXED(0,16,FLEN)
NAN_BOXED(31743,16,FLEN)
NAN_BOXED(31334,16,FLEN)
NAN_BOXED(0,16,FLEN)
NAN_BOXED(31743,16,FLEN)
NAN_BOXED(30352,16,FLEN)
NAN_BOXED(0,16,FLEN)
NAN_BOXED(31743,16,FLEN)
NAN_BOXED(28882,16,FLEN)
NAN_BOXED(0,16,FLEN)
NAN_BOXED(31743,16,FLEN)
NAN_BOXED(29875,16,FLEN)
NAN_BOXED(0,16,FLEN)
NAN_BOXED(31743,16,FLEN)
NAN_BOXED(31269,16,FLEN)
NAN_BOXED(0,16,FLEN)
NAN_BOXED(31743,16,FLEN)
NAN_BOXED(31482,16,FLEN)
NAN_BOXED(0,16,FLEN)
NAN_BOXED(31743,16,FLEN)
NAN_BOXED(27047,16,FLEN)
NAN_BOXED(0,16,FLEN)
NAN_BOXED(31743,16,FLEN)
NAN_BOXED(30953,16,FLEN)
NAN_BOXED(0,16,FLEN)
NAN_BOXED(31743,16,FLEN)
NAN_BOXED(27072,16,FLEN)
NAN_BOXED(32768,16,FLEN)
NAN_BOXED(31743,16,FLEN)
NAN_BOXED(31166,16,FLEN)
NAN_BOXED(32768,16,FLEN)
NAN_BOXED(31743,16,FLEN)
NAN_BOXED(30026,16,FLEN)
NAN_BOXED(32768,16,FLEN)
NAN_BOXED(31743,16,FLEN)
NAN_BOXED(31499,16,FLEN)
NAN_BOXED(32768,16,FLEN)
NAN_BOXED(31743,16,FLEN)
NAN_BOXED(31703,16,FLEN)
NAN_BOXED(32768,16,FLEN)
NAN_BOXED(31743,16,FLEN)
NAN_BOXED(30730,16,FLEN)
NAN_BOXED(32768,16,FLEN)
NAN_BOXED(31743,16,FLEN)
NAN_BOXED(31739,16,FLEN)
NAN_BOXED(32768,16,FLEN)
NAN_BOXED(31743,16,FLEN)
NAN_BOXED(29939,16,FLEN)
NAN_BOXED(32768,16,FLEN)
NAN_BOXED(31743,16,FLEN)
NAN_BOXED(27884,16,FLEN)
NAN_BOXED(32768,16,FLEN)
NAN_BOXED(31743,16,FLEN)
NAN_BOXED(30923,16,FLEN)
NAN_BOXED(32768,16,FLEN)
NAN_BOXED(31743,16,FLEN)
NAN_BOXED(26628,16,FLEN)
NAN_BOXED(32768,16,FLEN)
NAN_BOXED(31743,16,FLEN)
NAN_BOXED(29264,16,FLEN)
NAN_BOXED(32768,16,FLEN)
NAN_BOXED(31743,16,FLEN)
NAN_BOXED(30342,16,FLEN)
NAN_BOXED(32768,16,FLEN)
NAN_BOXED(31743,16,FLEN)
NAN_BOXED(30945,16,FLEN)
NAN_BOXED(32768,16,FLEN)
NAN_BOXED(31743,16,FLEN)
NAN_BOXED(28927,16,FLEN)
NAN_BOXED(0,16,FLEN)
NAN_BOXED(31743,16,FLEN)
NAN_BOXED(26990,16,FLEN)
NAN_BOXED(0,16,FLEN)
NAN_BOXED(31743,16,FLEN)
NAN_BOXED(29956,16,FLEN)
NAN_BOXED(0,16,FLEN)
NAN_BOXED(31743,16,FLEN)
NAN_BOXED(31658,16,FLEN)
NAN_BOXED(0,16,FLEN)
NAN_BOXED(31743,16,FLEN)
NAN_BOXED(31531,16,FLEN)
NAN_BOXED(0,16,FLEN)
NAN_BOXED(31743,16,FLEN)
NAN_BOXED(30218,16,FLEN)
NAN_BOXED(0,16,FLEN)
NAN_BOXED(31743,16,FLEN)
NAN_BOXED(30556,16,FLEN)
NAN_BOXED(0,16,FLEN)
NAN_BOXED(31743,16,FLEN)
NAN_BOXED(30760,16,FLEN)
NAN_BOXED(0,16,FLEN)
NAN_BOXED(31743,16,FLEN)
NAN_BOXED(31014,16,FLEN)
NAN_BOXED(0,16,FLEN)
NAN_BOXED(31743,16,FLEN)
NAN_BOXED(30915,16,FLEN)
NAN_BOXED(0,16,FLEN)
NAN_BOXED(31743,16,FLEN)
NAN_BOXED(30840,16,FLEN)
NAN_BOXED(0,16,FLEN)
NAN_BOXED(31743,16,FLEN)
NAN_BOXED(30965,16,FLEN)
NAN_BOXED(0,16,FLEN)
NAN_BOXED(31743,16,FLEN)
NAN_BOXED(31621,16,FLEN)
NAN_BOXED(0,16,FLEN)
NAN_BOXED(31743,16,FLEN)
NAN_BOXED(30733,16,FLEN)
NAN_BOXED(32768,16,FLEN)
NAN_BOXED(31743,16,FLEN)
NAN_BOXED(30437,16,FLEN)
NAN_BOXED(32768,16,FLEN)
NAN_BOXED(31743,16,FLEN)
NAN_BOXED(31170,16,FLEN)
NAN_BOXED(32768,16,FLEN)
NAN_BOXED(31743,16,FLEN)
NAN_BOXED(29593,16,FLEN)
NAN_BOXED(32768,16,FLEN)
NAN_BOXED(31743,16,FLEN)
NAN_BOXED(29904,16,FLEN)
NAN_BOXED(32768,16,FLEN)
NAN_BOXED(31743,16,FLEN)
NAN_BOXED(31697,16,FLEN)
NAN_BOXED(32768,16,FLEN)
NAN_BOXED(31743,16,FLEN)
NAN_BOXED(30762,16,FLEN)
NAN_BOXED(32768,16,FLEN)
NAN_BOXED(31743,16,FLEN)
NAN_BOXED(30818,16,FLEN)
NAN_BOXED(32768,16,FLEN)
NAN_BOXED(31743,16,FLEN)
NAN_BOXED(25054,16,FLEN)
NAN_BOXED(32768,16,FLEN)
NAN_BOXED(31743,16,FLEN)
NAN_BOXED(30371,16,FLEN)
NAN_BOXED(32768,16,FLEN)
NAN_BOXED(31743,16,FLEN)
NAN_BOXED(30883,16,FLEN)
NAN_BOXED(32768,16,FLEN)
NAN_BOXED(31743,16,FLEN)
NAN_BOXED(25890,16,FLEN)
NAN_BOXED(32768,16,FLEN)
NAN_BOXED(31743,16,FLEN)
NAN_BOXED(30956,16,FLEN)
NAN_BOXED(32768,16,FLEN)
NAN_BOXED(31743,16,FLEN)
NAN_BOXED(30990,16,FLEN)
NAN_BOXED(32768,16,FLEN)
NAN_BOXED(31743,16,FLEN)
NAN_BOXED(27568,16,FLEN)
NAN_BOXED(0,16,FLEN)
NAN_BOXED(31743,16,FLEN)
NAN_BOXED(30980,16,FLEN)
NAN_BOXED(0,16,FLEN)
NAN_BOXED(31743,16,FLEN)
NAN_BOXED(30580,16,FLEN)
NAN_BOXED(0,16,FLEN)
NAN_BOXED(31743,16,FLEN)
NAN_BOXED(31086,16,FLEN)
NAN_BOXED(0,16,FLEN)
NAN_BOXED(31743,16,FLEN)
NAN_BOXED(30115,16,FLEN)
NAN_BOXED(0,16,FLEN)
NAN_BOXED(31743,16,FLEN)
NAN_BOXED(31143,16,FLEN)
NAN_BOXED(0,16,FLEN)
NAN_BOXED(31743,16,FLEN)
NAN_BOXED(31206,16,FLEN)
NAN_BOXED(0,16,FLEN)
NAN_BOXED(31743,16,FLEN)
NAN_BOXED(26030,16,FLEN)
NAN_BOXED(0,16,FLEN)
NAN_BOXED(31743,16,FLEN)
NAN_BOXED(27584,16,FLEN)
NAN_BOXED(0,16,FLEN)
NAN_BOXED(31743,16,FLEN)
NAN_BOXED(31079,16,FLEN)
NAN_BOXED(0,16,FLEN)
NAN_BOXED(31743,16,FLEN)
NAN_BOXED(31667,16,FLEN)
NAN_BOXED(0,16,FLEN)
NAN_BOXED(31743,16,FLEN)
NAN_BOXED(29700,16,FLEN)
NAN_BOXED(0,16,FLEN)
NAN_BOXED(31743,16,FLEN)
NAN_BOXED(30540,16,FLEN)
NAN_BOXED(0,16,FLEN)
NAN_BOXED(31743,16,FLEN)
NAN_BOXED(30909,16,FLEN)
NAN_BOXED(0,16,FLEN)
NAN_BOXED(31743,16,FLEN)
NAN_BOXED(29982,16,FLEN)
NAN_BOXED(32768,16,FLEN)
NAN_BOXED(31743,16,FLEN)
NAN_BOXED(30162,16,FLEN)
NAN_BOXED(32768,16,FLEN)
NAN_BOXED(31743,16,FLEN)
NAN_BOXED(29952,16,FLEN)
NAN_BOXED(32768,16,FLEN)
NAN_BOXED(31743,16,FLEN)
NAN_BOXED(30183,16,FLEN)
NAN_BOXED(32768,16,FLEN)
NAN_BOXED(31743,16,FLEN)
NAN_BOXED(30915,16,FLEN)
NAN_BOXED(32768,16,FLEN)
NAN_BOXED(31743,16,FLEN)
NAN_BOXED(29901,16,FLEN)
NAN_BOXED(32768,16,FLEN)
NAN_BOXED(31743,16,FLEN)
NAN_BOXED(30216,16,FLEN)
NAN_BOXED(32768,16,FLEN)
NAN_BOXED(31743,16,FLEN)
NAN_BOXED(31276,16,FLEN)
NAN_BOXED(32768,16,FLEN)
NAN_BOXED(31743,16,FLEN)
NAN_BOXED(26340,16,FLEN)
NAN_BOXED(32768,16,FLEN)
NAN_BOXED(31743,16,FLEN)
NAN_BOXED(30861,16,FLEN)
NAN_BOXED(32768,16,FLEN)
NAN_BOXED(31743,16,FLEN)
NAN_BOXED(31200,16,FLEN)
NAN_BOXED(32768,16,FLEN)
NAN_BOXED(31743,16,FLEN)
NAN_BOXED(29941,16,FLEN)
NAN_BOXED(32768,16,FLEN)
NAN_BOXED(31743,16,FLEN)
NAN_BOXED(29470,16,FLEN)
NAN_BOXED(32768,16,FLEN)
NAN_BOXED(31743,16,FLEN)
NAN_BOXED(31341,16,FLEN)
NAN_BOXED(32768,16,FLEN)
NAN_BOXED(31743,16,FLEN)
NAN_BOXED(29602,16,FLEN)
NAN_BOXED(0,16,FLEN)
NAN_BOXED(31743,16,FLEN)
NAN_BOXED(29182,16,FLEN)
NAN_BOXED(0,16,FLEN)
NAN_BOXED(31743,16,FLEN)
NAN_BOXED(30453,16,FLEN)
NAN_BOXED(0,16,FLEN)
NAN_BOXED(31743,16,FLEN)
NAN_BOXED(31124,16,FLEN)
NAN_BOXED(0,16,FLEN)
NAN_BOXED(31743,16,FLEN)
NAN_BOXED(28291,16,FLEN)
NAN_BOXED(0,16,FLEN)
NAN_BOXED(31743,16,FLEN)
NAN_BOXED(29990,16,FLEN)
NAN_BOXED(0,16,FLEN)
NAN_BOXED(31743,16,FLEN)
NAN_BOXED(30038,16,FLEN)
NAN_BOXED(0,16,FLEN)
NAN_BOXED(31743,16,FLEN)
NAN_BOXED(31402,16,FLEN)
NAN_BOXED(0,16,FLEN)
NAN_BOXED(31743,16,FLEN)
NAN_BOXED(30466,16,FLEN)
NAN_BOXED(0,16,FLEN)
NAN_BOXED(31743,16,FLEN)
NAN_BOXED(31447,16,FLEN)
NAN_BOXED(0,16,FLEN)
NAN_BOXED(31743,16,FLEN)
NAN_BOXED(29034,16,FLEN)
NAN_BOXED(0,16,FLEN)
NAN_BOXED(31743,16,FLEN)
NAN_BOXED(30050,16,FLEN)
NAN_BOXED(0,16,FLEN)
NAN_BOXED(31743,16,FLEN)
NAN_BOXED(31027,16,FLEN)
NAN_BOXED(0,16,FLEN)
NAN_BOXED(31743,16,FLEN)
NAN_BOXED(31507,16,FLEN)
NAN_BOXED(0,16,FLEN)
NAN_BOXED(31743,16,FLEN)
NAN_BOXED(30518,16,FLEN)
NAN_BOXED(32768,16,FLEN)
NAN_BOXED(31743,16,FLEN)
NAN_BOXED(29490,16,FLEN)
NAN_BOXED(32768,16,FLEN)
NAN_BOXED(31743,16,FLEN)
NAN_BOXED(28604,16,FLEN)
NAN_BOXED(32768,16,FLEN)
NAN_BOXED(31743,16,FLEN)
NAN_BOXED(30780,16,FLEN)
NAN_BOXED(32768,16,FLEN)
NAN_BOXED(31743,16,FLEN)
NAN_BOXED(29210,16,FLEN)
NAN_BOXED(32768,16,FLEN)
NAN_BOXED(31743,16,FLEN)
NAN_BOXED(31347,16,FLEN)
NAN_BOXED(32768,16,FLEN)
NAN_BOXED(31743,16,FLEN)
NAN_BOXED(31412,16,FLEN)
NAN_BOXED(32768,16,FLEN)
NAN_BOXED(31743,16,FLEN)
NAN_BOXED(29151,16,FLEN)
NAN_BOXED(40655,16,FLEN)
NAN_BOXED(31743,16,FLEN)
NAN_BOXED(29812,16,FLEN)
NAN_BOXED(40061,16,FLEN)
NAN_BOXED(31743,16,FLEN)
NAN_BOXED(31348,16,FLEN)
NAN_BOXED(38450,16,FLEN)
NAN_BOXED(31743,16,FLEN)
NAN_BOXED(31010,16,FLEN)
NAN_BOXED(38858,16,FLEN)
NAN_BOXED(31743,16,FLEN)
NAN_BOXED(31346,16,FLEN)
NAN_BOXED(38452,16,FLEN)
NAN_BOXED(31743,16,FLEN)
NAN_BOXED(30085,16,FLEN)
NAN_BOXED(39742,16,FLEN)
NAN_BOXED(31743,16,FLEN)
NAN_BOXED(28710,16,FLEN)
NAN_BOXED(41170,16,FLEN)
NAN_BOXED(31743,16,FLEN)
NAN_BOXED(29867,16,FLEN)
NAN_BOXED(7240,16,FLEN)
NAN_BOXED(31743,16,FLEN)
NAN_BOXED(31321,16,FLEN)
NAN_BOXED(5709,16,FLEN)
NAN_BOXED(31743,16,FLEN)
NAN_BOXED(29782,16,FLEN)
NAN_BOXED(7324,16,FLEN)
NAN_BOXED(31743,16,FLEN)
NAN_BOXED(30090,16,FLEN)
NAN_BOXED(6968,16,FLEN)
NAN_BOXED(31743,16,FLEN)
NAN_BOXED(30378,16,FLEN)
NAN_BOXED(6655,16,FLEN)
NAN_BOXED(31743,16,FLEN)
NAN_BOXED(30390,16,FLEN)
NAN_BOXED(6645,16,FLEN)
NAN_BOXED(31743,16,FLEN)
NAN_BOXED(30348,16,FLEN)
NAN_BOXED(6683,16,FLEN)
NAN_BOXED(31743,16,FLEN)
NAN_BOXED(31580,16,FLEN)
NAN_BOXED(5487,16,FLEN)
NAN_BOXED(31743,16,FLEN)
NAN_BOXED(28925,16,FLEN)
NAN_BOXED(8194,16,FLEN)
NAN_BOXED(31743,16,FLEN)
NAN_BOXED(23753,16,FLEN)
NAN_BOXED(13357,16,FLEN)
NAN_BOXED(31743,16,FLEN)
NAN_BOXED(31626,16,FLEN)
NAN_BOXED(5453,16,FLEN)
NAN_BOXED(31743,16,FLEN)
NAN_BOXED(31497,16,FLEN)
NAN_BOXED(5551,16,FLEN)
NAN_BOXED(31743,16,FLEN)
NAN_BOXED(31716,16,FLEN)
NAN_BOXED(5393,16,FLEN)
NAN_BOXED(31743,16,FLEN)
NAN_BOXED(30450,16,FLEN)
NAN_BOXED(6594,16,FLEN)
NAN_BOXED(31743,16,FLEN)
NAN_BOXED(31640,16,FLEN)
NAN_BOXED(38211,16,FLEN)
NAN_BOXED(31743,16,FLEN)
NAN_BOXED(31594,16,FLEN)
NAN_BOXED(38244,16,FLEN)
NAN_BOXED(31743,16,FLEN)
NAN_BOXED(29466,16,FLEN)
NAN_BOXED(40353,16,FLEN)
NAN_BOXED(31743,16,FLEN)
NAN_BOXED(31222,16,FLEN)
NAN_BOXED(38581,16,FLEN)
NAN_BOXED(31743,16,FLEN)
NAN_BOXED(31408,16,FLEN)
NAN_BOXED(38394,16,FLEN)
NAN_BOXED(31743,16,FLEN)
NAN_BOXED(31053,16,FLEN)
NAN_BOXED(38795,16,FLEN)
NAN_BOXED(31743,16,FLEN)
NAN_BOXED(30758,16,FLEN)
NAN_BOXED(39121,16,FLEN)
NAN_BOXED(31743,16,FLEN)
NAN_BOXED(29855,16,FLEN)
NAN_BOXED(32809,16,FLEN)
NAN_BOXED(31743,16,FLEN)
NAN_BOXED(30068,16,FLEN)
NAN_BOXED(32803,16,FLEN)
NAN_BOXED(31743,16,FLEN)
NAN_BOXED(29510,16,FLEN)
NAN_BOXED(32820,16,FLEN)
NAN_BOXED(31743,16,FLEN)
NAN_BOXED(27738,16,FLEN)
NAN_BOXED(32944,16,FLEN)
NAN_BOXED(31743,16,FLEN)
NAN_BOXED(30901,16,FLEN)
NAN_BOXED(32788,16,FLEN)
NAN_BOXED(31743,16,FLEN)
NAN_BOXED(29847,16,FLEN)
NAN_BOXED(32809,16,FLEN)
NAN_BOXED(31743,16,FLEN)
NAN_BOXED(31354,16,FLEN)
NAN_BOXED(32782,16,FLEN)
NAN_BOXED(31743,16,FLEN)
NAN_BOXED(27076,16,FLEN)
NAN_BOXED(266,16,FLEN)
NAN_BOXED(31743,16,FLEN)
NAN_BOXED(31545,16,FLEN)
NAN_BOXED(13,16,FLEN)
NAN_BOXED(31743,16,FLEN)
NAN_BOXED(31116,16,FLEN)
NAN_BOXED(17,16,FLEN)
NAN_BOXED(31743,16,FLEN)
NAN_BOXED(31587,16,FLEN)
NAN_BOXED(12,16,FLEN)
NAN_BOXED(31743,16,FLEN)
NAN_BOXED(31531,16,FLEN)
NAN_BOXED(13,16,FLEN)
NAN_BOXED(31743,16,FLEN)
NAN_BOXED(31537,16,FLEN)
NAN_BOXED(13,16,FLEN)
NAN_BOXED(31743,16,FLEN)
NAN_BOXED(30877,16,FLEN)
NAN_BOXED(20,16,FLEN)
NAN_BOXED(31743,16,FLEN)
NAN_BOXED(25276,16,FLEN)
NAN_BOXED(912,16,FLEN)
NAN_BOXED(31743,16,FLEN)
NAN_BOXED(31221,16,FLEN)
NAN_BOXED(16,16,FLEN)
NAN_BOXED(31743,16,FLEN)
NAN_BOXED(29054,16,FLEN)
NAN_BOXED(69,16,FLEN)
NAN_BOXED(31743,16,FLEN)
NAN_BOXED(29899,16,FLEN)
NAN_BOXED(40,16,FLEN)
NAN_BOXED(31743,16,FLEN)
NAN_BOXED(31052,16,FLEN)
NAN_BOXED(18,16,FLEN)
NAN_BOXED(31743,16,FLEN)
NAN_BOXED(30770,16,FLEN)
NAN_BOXED(22,16,FLEN)
NAN_BOXED(31743,16,FLEN)
NAN_BOXED(30365,16,FLEN)
NAN_BOXED(29,16,FLEN)
NAN_BOXED(31743,16,FLEN)
NAN_BOXED(31618,16,FLEN)
NAN_BOXED(32780,16,FLEN)
NAN_BOXED(31743,16,FLEN)
NAN_BOXED(30949,16,FLEN)
NAN_BOXED(32787,16,FLEN)
NAN_BOXED(31743,16,FLEN)
NAN_BOXED(30069,16,FLEN)
NAN_BOXED(32803,16,FLEN)
NAN_BOXED(31743,16,FLEN)
NAN_BOXED(29705,16,FLEN)
NAN_BOXED(32815,16,FLEN)
NAN_BOXED(31743,16,FLEN)
NAN_BOXED(31459,16,FLEN)
NAN_BOXED(32781,16,FLEN)
NAN_BOXED(31743,16,FLEN)
NAN_BOXED(30625,16,FLEN)
NAN_BOXED(32793,16,FLEN)
NAN_BOXED(31743,16,FLEN)
NAN_BOXED(31297,16,FLEN)
NAN_BOXED(32783,16,FLEN)
NAN_BOXED(31743,16,FLEN)
NAN_BOXED(30112,16,FLEN)
NAN_BOXED(49583,16,FLEN)
NAN_BOXED(31743,16,FLEN)
NAN_BOXED(29263,16,FLEN)
NAN_BOXED(17681,16,FLEN)
NAN_BOXED(31743,16,FLEN)
NAN_BOXED(30790,16,FLEN)
NAN_BOXED(49019,16,FLEN)
NAN_BOXED(31743,16,FLEN)
NAN_BOXED(31368,16,FLEN)
NAN_BOXED(15589,16,FLEN)
NAN_BOXED(31743,16,FLEN)
NAN_BOXED(29050,16,FLEN)
NAN_BOXED(50646,16,FLEN)
NAN_BOXED(31743,16,FLEN)
NAN_BOXED(31316,16,FLEN)
NAN_BOXED(15629,16,FLEN)
NAN_BOXED(31743,16,FLEN)
NAN_BOXED(31582,16,FLEN)
NAN_BOXED(48214,16,FLEN)
NAN_BOXED(31743,16,FLEN)
NAN_BOXED(31345,16,FLEN)
NAN_BOXED(15606,16,FLEN)
NAN_BOXED(31743,16,FLEN)
NAN_BOXED(31381,16,FLEN)
NAN_BOXED(48347,16,FLEN)
NAN_BOXED(31743,16,FLEN)
NAN_BOXED(24498,16,FLEN)
NAN_BOXED(22567,16,FLEN)
NAN_BOXED(31743,16,FLEN)
NAN_BOXED(30982,16,FLEN)
NAN_BOXED(48732,16,FLEN)
NAN_BOXED(31743,16,FLEN)
NAN_BOXED(31461,16,FLEN)
NAN_BOXED(15523,16,FLEN)
NAN_BOXED(31743,16,FLEN)
NAN_BOXED(27235,16,FLEN)
NAN_BOXED(52481,16,FLEN)
NAN_BOXED(31743,16,FLEN)
NAN_BOXED(29783,16,FLEN)
NAN_BOXED(17246,16,FLEN)
NAN_BOXED(31743,16,FLEN)
NAN_BOXED(29771,16,FLEN)
NAN_BOXED(46962,16,FLEN)
NAN_BOXED(31743,16,FLEN)
NAN_BOXED(30775,16,FLEN)
NAN_BOXED(13206,16,FLEN)
NAN_BOXED(31743,16,FLEN)
NAN_BOXED(30403,16,FLEN)
NAN_BOXED(47290,16,FLEN)
NAN_BOXED(31743,16,FLEN)
NAN_BOXED(30608,16,FLEN)
NAN_BOXED(14394,16,FLEN)
NAN_BOXED(31743,16,FLEN)
NAN_BOXED(31285,16,FLEN)
NAN_BOXED(47398,16,FLEN)
NAN_BOXED(31743,16,FLEN)
NAN_BOXED(22391,16,FLEN)
NAN_BOXED(23624,16,FLEN)
NAN_BOXED(31743,16,FLEN)
NAN_BOXED(27396,16,FLEN)
NAN_BOXED(52366,16,FLEN)
NAN_BOXED(31743,16,FLEN)
NAN_BOXED(28686,16,FLEN)
NAN_BOXED(18401,16,FLEN)
NAN_BOXED(31743,16,FLEN)
NAN_BOXED(28665,16,FLEN)
NAN_BOXED(52226,16,FLEN)
NAN_BOXED(31743,16,FLEN)
NAN_BOXED(27744,16,FLEN)
NAN_BOXED(20302,16,FLEN)
NAN_BOXED(31743,16,FLEN)
NAN_BOXED(31691,16,FLEN)
NAN_BOXED(50202,16,FLEN)
NAN_BOXED(31743,16,FLEN)
NAN_BOXED(31445,16,FLEN)
NAN_BOXED(17582,16,FLEN)
NAN_BOXED(31743,16,FLEN)
NAN_BOXED(28034,16,FLEN)
NAN_BOXED(54733,16,FLEN)
NAN_BOXED(31743,16,FLEN)
NAN_BOXED(30723,16,FLEN)
NAN_BOXED(19447,16,FLEN)
NAN_BOXED(31743,16,FLEN)
NAN_BOXED(29965,16,FLEN)
NAN_BOXED(32768,16,FLEN)
NAN_BOXED(31743,16,FLEN)
NAN_BOXED(29959,16,FLEN)
NAN_BOXED(32768,16,FLEN)
NAN_BOXED(31743,16,FLEN)
NAN_BOXED(30110,16,FLEN)
NAN_BOXED(32768,16,FLEN)
NAN_BOXED(31743,16,FLEN)
NAN_BOXED(31020,16,FLEN)
NAN_BOXED(32768,16,FLEN)
NAN_BOXED(31743,16,FLEN)
NAN_BOXED(30896,16,FLEN)
NAN_BOXED(32768,16,FLEN)
NAN_BOXED(31743,16,FLEN)
NAN_BOXED(30149,16,FLEN)
NAN_BOXED(32768,16,FLEN)
NAN_BOXED(31743,16,FLEN)
NAN_BOXED(29212,16,FLEN)
NAN_BOXED(32768,16,FLEN)
NAN_BOXED(31743,16,FLEN)
NAN_BOXED(30018,16,FLEN)
NAN_BOXED(32768,16,FLEN)
NAN_BOXED(31743,16,FLEN)
NAN_BOXED(28650,16,FLEN)
NAN_BOXED(32768,16,FLEN)
NAN_BOXED(31743,16,FLEN)
NAN_BOXED(30833,16,FLEN)
NAN_BOXED(32768,16,FLEN)
NAN_BOXED(31743,16,FLEN)
NAN_BOXED(31161,16,FLEN)
NAN_BOXED(32768,16,FLEN)
NAN_BOXED(31743,16,FLEN)
NAN_BOXED(30228,16,FLEN)
NAN_BOXED(32768,16,FLEN)
NAN_BOXED(31743,16,FLEN)
NAN_BOXED(27932,16,FLEN)
NAN_BOXED(32768,16,FLEN)
NAN_BOXED(31743,16,FLEN)
NAN_BOXED(29110,16,FLEN)
NAN_BOXED(32768,16,FLEN)
NAN_BOXED(31743,16,FLEN)
NAN_BOXED(30200,16,FLEN)
NAN_BOXED(32768,16,FLEN)
NAN_BOXED(31743,16,FLEN)
NAN_BOXED(30933,16,FLEN)
NAN_BOXED(32768,16,FLEN)
NAN_BOXED(31743,16,FLEN)
NAN_BOXED(31298,16,FLEN)
NAN_BOXED(0,16,FLEN)
NAN_BOXED(31743,16,FLEN)
NAN_BOXED(30228,16,FLEN)
NAN_BOXED(0,16,FLEN)
NAN_BOXED(31743,16,FLEN)
NAN_BOXED(31335,16,FLEN)
NAN_BOXED(0,16,FLEN)
NAN_BOXED(31743,16,FLEN)
NAN_BOXED(30971,16,FLEN)
NAN_BOXED(0,16,FLEN)
NAN_BOXED(31743,16,FLEN)
NAN_BOXED(30438,16,FLEN)
NAN_BOXED(0,16,FLEN)
NAN_BOXED(31743,16,FLEN)
NAN_BOXED(30196,16,FLEN)
NAN_BOXED(0,16,FLEN)
NAN_BOXED(31743,16,FLEN)
NAN_BOXED(30703,16,FLEN)
NAN_BOXED(0,16,FLEN)
NAN_BOXED(31743,16,FLEN)
NAN_BOXED(31134,16,FLEN)
NAN_BOXED(0,16,FLEN)
NAN_BOXED(31743,16,FLEN)
NAN_BOXED(30393,16,FLEN)
NAN_BOXED(0,16,FLEN)
NAN_BOXED(31743,16,FLEN)
NAN_BOXED(31116,16,FLEN)
NAN_BOXED(0,16,FLEN)
NAN_BOXED(31743,16,FLEN)
NAN_BOXED(30558,16,FLEN)
NAN_BOXED(0,16,FLEN)
NAN_BOXED(31743,16,FLEN)
NAN_BOXED(29654,16,FLEN)
NAN_BOXED(0,16,FLEN)
NAN_BOXED(31743,16,FLEN)
NAN_BOXED(30792,16,FLEN)
NAN_BOXED(0,16,FLEN)
NAN_BOXED(31743,16,FLEN)
NAN_BOXED(31119,16,FLEN)
NAN_BOXED(0,16,FLEN)
NAN_BOXED(31743,16,FLEN)
NAN_BOXED(27796,16,FLEN)
NAN_BOXED(0,16,FLEN)
NAN_BOXED(31743,16,FLEN)
NAN_BOXED(30411,16,FLEN)
NAN_BOXED(0,16,FLEN)
NAN_BOXED(31743,16,FLEN)
NAN_BOXED(29596,16,FLEN)
NAN_BOXED(32768,16,FLEN)
NAN_BOXED(31743,16,FLEN)
NAN_BOXED(30810,16,FLEN)
NAN_BOXED(32768,16,FLEN)
NAN_BOXED(31743,16,FLEN)
NAN_BOXED(30976,16,FLEN)
NAN_BOXED(32768,16,FLEN)
NAN_BOXED(31743,16,FLEN)
NAN_BOXED(25279,16,FLEN)
NAN_BOXED(32768,16,FLEN)
NAN_BOXED(31743,16,FLEN)
NAN_BOXED(31410,16,FLEN)
NAN_BOXED(0,16,FLEN)
NAN_BOXED(31743,16,FLEN)
NAN_BOXED(29733,16,FLEN)
NAN_BOXED(0,16,FLEN)
NAN_BOXED(31743,16,FLEN)
NAN_BOXED(29566,16,FLEN)
NAN_BOXED(0,16,FLEN)
NAN_BOXED(31743,16,FLEN)
NAN_BOXED(31734,16,FLEN)
NAN_BOXED(0,16,FLEN)
NAN_BOXED(31743,16,FLEN)
RVTEST_DATA_END

RVMODEL_DATA_BEGIN
rvtest_sig_begin:
sig_begin_canary:
CANARY;



signature_x1_0:
    .fill 0*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_1:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_2:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_3:
    .fill 68*((SIGALIGN)/4),4,0xdeadbeef

#ifdef rvtest_mtrap_routine
tsig_begin_canary:
CANARY;

mtrap_sigptr:
    .fill 64*XLEN/32,4,0xdeadbeef

tsig_end_canary:
CANARY;
#endif

#ifdef rvtest_gpr_save

gpr_save:
    .fill 32*XLEN/32,4,0xdeadbeef

#endif


sig_end_canary:
CANARY;
rvtest_sig_end:
RVMODEL_DATA_END
