
// -----------
// This file was generated by riscv_ctg (https://github.com/riscv-software-src/riscv-ctg)
// version   : 0.11.0
// timestamp : Tue Jan 30 08:45:11 2024 GMT
// usage     : riscv_ctg \
//                  -- cgf //                  --cgf /home/riscv/riscv-ctg/sample_cgfs/dataset.cgf \
//                  --cgf /home/riscv/riscv-ctg/sample_cgfs/sample_cgfs_fext/RV32H/rv32h_fnmsub.cgf \
 \
//                  -- xlen 32  \
// -----------
//
// -----------
// Copyright (c) 2020. RISC-V International. All rights reserved.
// SPDX-License-Identifier: BSD-3-Clause
// -----------
//
// This assembly file tests the fnmsub.h instruction of the RISC-V RV32F_Zicsr_Zfh,RV32FD_Zicsr,RV64F_Zicsr_Zfh,RV64FD_Zicsr extension for the fnmsub_b1 covergroup.
// 
#include "model_test.h"
#include "arch_test.h"
RVTEST_ISA("RV32IF_Zicsr_Zfh,RV32IFD_Zicsr,RV64IF_Zicsr_Zfh,RV64IFD_Zicsr")

.section .text.init
.globl rvtest_entry_point
rvtest_entry_point:
RVMODEL_BOOT
RVTEST_CODE_BEGIN

#ifdef TEST_CASE_1

RVTEST_CASE(0,"//check ISA:=regex(.*I.*F.*Zfh.*);def TEST_CASE_1=True;",fnmsub_b1)

RVTEST_FP_ENABLE()
RVTEST_VALBASEUPD(x3,test_dataset_0)
RVTEST_SIGBASE(x1,signature_x1_1)

inst_8437:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7c00; op2val:0xfc00;
op3val:0xfbff; valaddr_reg:x3; val_offset:25311*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 25311*FLEN/8, x4, x1, x2)

inst_8438:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7c00; op2val:0xfc00;
op3val:0x7c00; valaddr_reg:x3; val_offset:25314*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 25314*FLEN/8, x4, x1, x2)

inst_8439:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7c00; op2val:0xfc00;
op3val:0xfc00; valaddr_reg:x3; val_offset:25317*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 25317*FLEN/8, x4, x1, x2)

inst_8440:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7c00; op2val:0xfc00;
op3val:0x7e00; valaddr_reg:x3; val_offset:25320*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 25320*FLEN/8, x4, x1, x2)

inst_8441:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7c00; op2val:0xfc00;
op3val:0xfe00; valaddr_reg:x3; val_offset:25323*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 25323*FLEN/8, x4, x1, x2)

inst_8442:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x201 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7c00; op2val:0xfc00;
op3val:0x7e01; valaddr_reg:x3; val_offset:25326*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 25326*FLEN/8, x4, x1, x2)

inst_8443:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x255 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7c00; op2val:0xfc00;
op3val:0xfe55; valaddr_reg:x3; val_offset:25329*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 25329*FLEN/8, x4, x1, x2)

inst_8444:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7c00; op2val:0xfc00;
op3val:0x7c01; valaddr_reg:x3; val_offset:25332*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 25332*FLEN/8, x4, x1, x2)

inst_8445:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x155 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7c00; op2val:0xfc00;
op3val:0xfd55; valaddr_reg:x3; val_offset:25335*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 25335*FLEN/8, x4, x1, x2)

inst_8446:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7c00; op2val:0xfc00;
op3val:0x3c00; valaddr_reg:x3; val_offset:25338*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 25338*FLEN/8, x4, x1, x2)

inst_8447:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7c00; op2val:0xfc00;
op3val:0xbc00; valaddr_reg:x3; val_offset:25341*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 25341*FLEN/8, x4, x1, x2)

RVTEST_SIGBASE(x1,signature_x1_67)
inst_8448:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7c00; op2val:0x7e00;
op3val:0x0; valaddr_reg:x3; val_offset:25344*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 25344*FLEN/8, x4, x1, x2)

inst_8449:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7c00; op2val:0x7e00;
op3val:0x8000; valaddr_reg:x3; val_offset:25347*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 25347*FLEN/8, x4, x1, x2)

inst_8450:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7c00; op2val:0x7e00;
op3val:0x1; valaddr_reg:x3; val_offset:25350*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 25350*FLEN/8, x4, x1, x2)

inst_8451:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7c00; op2val:0x7e00;
op3val:0x8001; valaddr_reg:x3; val_offset:25353*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 25353*FLEN/8, x4, x1, x2)

inst_8452:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x002 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7c00; op2val:0x7e00;
op3val:0x2; valaddr_reg:x3; val_offset:25356*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 25356*FLEN/8, x4, x1, x2)

inst_8453:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3fe and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7c00; op2val:0x7e00;
op3val:0x83fe; valaddr_reg:x3; val_offset:25359*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 25359*FLEN/8, x4, x1, x2)

inst_8454:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7c00; op2val:0x7e00;
op3val:0x3ff; valaddr_reg:x3; val_offset:25362*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 25362*FLEN/8, x4, x1, x2)

inst_8455:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7c00; op2val:0x7e00;
op3val:0x83ff; valaddr_reg:x3; val_offset:25365*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 25365*FLEN/8, x4, x1, x2)

inst_8456:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7c00; op2val:0x7e00;
op3val:0x400; valaddr_reg:x3; val_offset:25368*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 25368*FLEN/8, x4, x1, x2)

inst_8457:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7c00; op2val:0x7e00;
op3val:0x8400; valaddr_reg:x3; val_offset:25371*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 25371*FLEN/8, x4, x1, x2)

inst_8458:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7c00; op2val:0x7e00;
op3val:0x401; valaddr_reg:x3; val_offset:25374*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 25374*FLEN/8, x4, x1, x2)

inst_8459:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7c00; op2val:0x7e00;
op3val:0x8455; valaddr_reg:x3; val_offset:25377*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 25377*FLEN/8, x4, x1, x2)

inst_8460:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7c00; op2val:0x7e00;
op3val:0x7bff; valaddr_reg:x3; val_offset:25380*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 25380*FLEN/8, x4, x1, x2)

inst_8461:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7c00; op2val:0x7e00;
op3val:0xfbff; valaddr_reg:x3; val_offset:25383*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 25383*FLEN/8, x4, x1, x2)

inst_8462:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7c00; op2val:0x7e00;
op3val:0x7c00; valaddr_reg:x3; val_offset:25386*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 25386*FLEN/8, x4, x1, x2)

inst_8463:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7c00; op2val:0x7e00;
op3val:0xfc00; valaddr_reg:x3; val_offset:25389*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 25389*FLEN/8, x4, x1, x2)

inst_8464:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7c00; op2val:0x7e00;
op3val:0x7e00; valaddr_reg:x3; val_offset:25392*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 25392*FLEN/8, x4, x1, x2)

inst_8465:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7c00; op2val:0x7e00;
op3val:0xfe00; valaddr_reg:x3; val_offset:25395*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 25395*FLEN/8, x4, x1, x2)

inst_8466:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x201 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7c00; op2val:0x7e00;
op3val:0x7e01; valaddr_reg:x3; val_offset:25398*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 25398*FLEN/8, x4, x1, x2)

inst_8467:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x255 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7c00; op2val:0x7e00;
op3val:0xfe55; valaddr_reg:x3; val_offset:25401*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 25401*FLEN/8, x4, x1, x2)

inst_8468:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7c00; op2val:0x7e00;
op3val:0x7c01; valaddr_reg:x3; val_offset:25404*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 25404*FLEN/8, x4, x1, x2)

inst_8469:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x155 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7c00; op2val:0x7e00;
op3val:0xfd55; valaddr_reg:x3; val_offset:25407*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 25407*FLEN/8, x4, x1, x2)

inst_8470:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 0 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7c00; op2val:0x7e00;
op3val:0x3c00; valaddr_reg:x3; val_offset:25410*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 25410*FLEN/8, x4, x1, x2)

inst_8471:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 1 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7c00; op2val:0x7e00;
op3val:0xbc00; valaddr_reg:x3; val_offset:25413*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 25413*FLEN/8, x4, x1, x2)

inst_8472:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7c00; op2val:0xfe00;
op3val:0x0; valaddr_reg:x3; val_offset:25416*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 25416*FLEN/8, x4, x1, x2)

inst_8473:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7c00; op2val:0xfe00;
op3val:0x8000; valaddr_reg:x3; val_offset:25419*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 25419*FLEN/8, x4, x1, x2)

inst_8474:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7c00; op2val:0xfe00;
op3val:0x1; valaddr_reg:x3; val_offset:25422*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 25422*FLEN/8, x4, x1, x2)

inst_8475:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7c00; op2val:0xfe00;
op3val:0x8001; valaddr_reg:x3; val_offset:25425*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 25425*FLEN/8, x4, x1, x2)

inst_8476:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x002 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7c00; op2val:0xfe00;
op3val:0x2; valaddr_reg:x3; val_offset:25428*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 25428*FLEN/8, x4, x1, x2)

inst_8477:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3fe and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7c00; op2val:0xfe00;
op3val:0x83fe; valaddr_reg:x3; val_offset:25431*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 25431*FLEN/8, x4, x1, x2)

inst_8478:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7c00; op2val:0xfe00;
op3val:0x3ff; valaddr_reg:x3; val_offset:25434*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 25434*FLEN/8, x4, x1, x2)

inst_8479:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7c00; op2val:0xfe00;
op3val:0x83ff; valaddr_reg:x3; val_offset:25437*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 25437*FLEN/8, x4, x1, x2)

inst_8480:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7c00; op2val:0xfe00;
op3val:0x400; valaddr_reg:x3; val_offset:25440*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 25440*FLEN/8, x4, x1, x2)

inst_8481:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7c00; op2val:0xfe00;
op3val:0x8400; valaddr_reg:x3; val_offset:25443*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 25443*FLEN/8, x4, x1, x2)

inst_8482:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7c00; op2val:0xfe00;
op3val:0x401; valaddr_reg:x3; val_offset:25446*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 25446*FLEN/8, x4, x1, x2)

inst_8483:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7c00; op2val:0xfe00;
op3val:0x8455; valaddr_reg:x3; val_offset:25449*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 25449*FLEN/8, x4, x1, x2)

inst_8484:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7c00; op2val:0xfe00;
op3val:0x7bff; valaddr_reg:x3; val_offset:25452*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 25452*FLEN/8, x4, x1, x2)

inst_8485:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7c00; op2val:0xfe00;
op3val:0xfbff; valaddr_reg:x3; val_offset:25455*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 25455*FLEN/8, x4, x1, x2)

inst_8486:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7c00; op2val:0xfe00;
op3val:0x7c00; valaddr_reg:x3; val_offset:25458*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 25458*FLEN/8, x4, x1, x2)

inst_8487:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7c00; op2val:0xfe00;
op3val:0xfc00; valaddr_reg:x3; val_offset:25461*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 25461*FLEN/8, x4, x1, x2)

inst_8488:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7c00; op2val:0xfe00;
op3val:0x7e00; valaddr_reg:x3; val_offset:25464*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 25464*FLEN/8, x4, x1, x2)

inst_8489:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7c00; op2val:0xfe00;
op3val:0xfe00; valaddr_reg:x3; val_offset:25467*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 25467*FLEN/8, x4, x1, x2)

inst_8490:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x201 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7c00; op2val:0xfe00;
op3val:0x7e01; valaddr_reg:x3; val_offset:25470*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 25470*FLEN/8, x4, x1, x2)

inst_8491:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x255 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7c00; op2val:0xfe00;
op3val:0xfe55; valaddr_reg:x3; val_offset:25473*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 25473*FLEN/8, x4, x1, x2)

inst_8492:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7c00; op2val:0xfe00;
op3val:0x7c01; valaddr_reg:x3; val_offset:25476*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 25476*FLEN/8, x4, x1, x2)

inst_8493:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x155 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7c00; op2val:0xfe00;
op3val:0xfd55; valaddr_reg:x3; val_offset:25479*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 25479*FLEN/8, x4, x1, x2)

inst_8494:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 0 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7c00; op2val:0xfe00;
op3val:0x3c00; valaddr_reg:x3; val_offset:25482*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 25482*FLEN/8, x4, x1, x2)

inst_8495:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 1 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7c00; op2val:0xfe00;
op3val:0xbc00; valaddr_reg:x3; val_offset:25485*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 25485*FLEN/8, x4, x1, x2)

inst_8496:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7c00; op2val:0x7e01;
op3val:0x0; valaddr_reg:x3; val_offset:25488*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 25488*FLEN/8, x4, x1, x2)

inst_8497:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7c00; op2val:0x7e01;
op3val:0x8000; valaddr_reg:x3; val_offset:25491*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 25491*FLEN/8, x4, x1, x2)

inst_8498:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7c00; op2val:0x7e01;
op3val:0x1; valaddr_reg:x3; val_offset:25494*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 25494*FLEN/8, x4, x1, x2)

inst_8499:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7c00; op2val:0x7e01;
op3val:0x8001; valaddr_reg:x3; val_offset:25497*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 25497*FLEN/8, x4, x1, x2)

inst_8500:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x002 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7c00; op2val:0x7e01;
op3val:0x2; valaddr_reg:x3; val_offset:25500*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 25500*FLEN/8, x4, x1, x2)

inst_8501:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3fe and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7c00; op2val:0x7e01;
op3val:0x83fe; valaddr_reg:x3; val_offset:25503*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 25503*FLEN/8, x4, x1, x2)

inst_8502:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7c00; op2val:0x7e01;
op3val:0x3ff; valaddr_reg:x3; val_offset:25506*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 25506*FLEN/8, x4, x1, x2)

inst_8503:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7c00; op2val:0x7e01;
op3val:0x83ff; valaddr_reg:x3; val_offset:25509*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 25509*FLEN/8, x4, x1, x2)

inst_8504:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7c00; op2val:0x7e01;
op3val:0x400; valaddr_reg:x3; val_offset:25512*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 25512*FLEN/8, x4, x1, x2)

inst_8505:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7c00; op2val:0x7e01;
op3val:0x8400; valaddr_reg:x3; val_offset:25515*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 25515*FLEN/8, x4, x1, x2)

inst_8506:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7c00; op2val:0x7e01;
op3val:0x401; valaddr_reg:x3; val_offset:25518*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 25518*FLEN/8, x4, x1, x2)

inst_8507:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7c00; op2val:0x7e01;
op3val:0x8455; valaddr_reg:x3; val_offset:25521*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 25521*FLEN/8, x4, x1, x2)

inst_8508:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7c00; op2val:0x7e01;
op3val:0x7bff; valaddr_reg:x3; val_offset:25524*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 25524*FLEN/8, x4, x1, x2)

inst_8509:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7c00; op2val:0x7e01;
op3val:0xfbff; valaddr_reg:x3; val_offset:25527*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 25527*FLEN/8, x4, x1, x2)

inst_8510:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7c00; op2val:0x7e01;
op3val:0x7c00; valaddr_reg:x3; val_offset:25530*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 25530*FLEN/8, x4, x1, x2)

inst_8511:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7c00; op2val:0x7e01;
op3val:0xfc00; valaddr_reg:x3; val_offset:25533*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 25533*FLEN/8, x4, x1, x2)

inst_8512:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7c00; op2val:0x7e01;
op3val:0x7e00; valaddr_reg:x3; val_offset:25536*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 25536*FLEN/8, x4, x1, x2)

inst_8513:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7c00; op2val:0x7e01;
op3val:0xfe00; valaddr_reg:x3; val_offset:25539*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 25539*FLEN/8, x4, x1, x2)

inst_8514:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x201 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7c00; op2val:0x7e01;
op3val:0x7e01; valaddr_reg:x3; val_offset:25542*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 25542*FLEN/8, x4, x1, x2)

inst_8515:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x255 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7c00; op2val:0x7e01;
op3val:0xfe55; valaddr_reg:x3; val_offset:25545*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 25545*FLEN/8, x4, x1, x2)

inst_8516:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7c00; op2val:0x7e01;
op3val:0x7c01; valaddr_reg:x3; val_offset:25548*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 25548*FLEN/8, x4, x1, x2)

inst_8517:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x155 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7c00; op2val:0x7e01;
op3val:0xfd55; valaddr_reg:x3; val_offset:25551*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 25551*FLEN/8, x4, x1, x2)

inst_8518:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fs3 == 0 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7c00; op2val:0x7e01;
op3val:0x3c00; valaddr_reg:x3; val_offset:25554*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 25554*FLEN/8, x4, x1, x2)

inst_8519:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fs3 == 1 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7c00; op2val:0x7e01;
op3val:0xbc00; valaddr_reg:x3; val_offset:25557*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 25557*FLEN/8, x4, x1, x2)

inst_8520:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7c00; op2val:0xfe55;
op3val:0x0; valaddr_reg:x3; val_offset:25560*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 25560*FLEN/8, x4, x1, x2)

inst_8521:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7c00; op2val:0xfe55;
op3val:0x8000; valaddr_reg:x3; val_offset:25563*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 25563*FLEN/8, x4, x1, x2)

inst_8522:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7c00; op2val:0xfe55;
op3val:0x1; valaddr_reg:x3; val_offset:25566*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 25566*FLEN/8, x4, x1, x2)

inst_8523:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7c00; op2val:0xfe55;
op3val:0x8001; valaddr_reg:x3; val_offset:25569*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 25569*FLEN/8, x4, x1, x2)

inst_8524:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x002 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7c00; op2val:0xfe55;
op3val:0x2; valaddr_reg:x3; val_offset:25572*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 25572*FLEN/8, x4, x1, x2)

inst_8525:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3fe and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7c00; op2val:0xfe55;
op3val:0x83fe; valaddr_reg:x3; val_offset:25575*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 25575*FLEN/8, x4, x1, x2)

inst_8526:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7c00; op2val:0xfe55;
op3val:0x3ff; valaddr_reg:x3; val_offset:25578*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 25578*FLEN/8, x4, x1, x2)

inst_8527:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7c00; op2val:0xfe55;
op3val:0x83ff; valaddr_reg:x3; val_offset:25581*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 25581*FLEN/8, x4, x1, x2)

inst_8528:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7c00; op2val:0xfe55;
op3val:0x400; valaddr_reg:x3; val_offset:25584*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 25584*FLEN/8, x4, x1, x2)

inst_8529:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7c00; op2val:0xfe55;
op3val:0x8400; valaddr_reg:x3; val_offset:25587*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 25587*FLEN/8, x4, x1, x2)

inst_8530:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7c00; op2val:0xfe55;
op3val:0x401; valaddr_reg:x3; val_offset:25590*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 25590*FLEN/8, x4, x1, x2)

inst_8531:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7c00; op2val:0xfe55;
op3val:0x8455; valaddr_reg:x3; val_offset:25593*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 25593*FLEN/8, x4, x1, x2)

inst_8532:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7c00; op2val:0xfe55;
op3val:0x7bff; valaddr_reg:x3; val_offset:25596*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 25596*FLEN/8, x4, x1, x2)

inst_8533:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7c00; op2val:0xfe55;
op3val:0xfbff; valaddr_reg:x3; val_offset:25599*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 25599*FLEN/8, x4, x1, x2)

inst_8534:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7c00; op2val:0xfe55;
op3val:0x7c00; valaddr_reg:x3; val_offset:25602*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 25602*FLEN/8, x4, x1, x2)

inst_8535:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7c00; op2val:0xfe55;
op3val:0xfc00; valaddr_reg:x3; val_offset:25605*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 25605*FLEN/8, x4, x1, x2)

inst_8536:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7c00; op2val:0xfe55;
op3val:0x7e00; valaddr_reg:x3; val_offset:25608*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 25608*FLEN/8, x4, x1, x2)

inst_8537:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7c00; op2val:0xfe55;
op3val:0xfe00; valaddr_reg:x3; val_offset:25611*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 25611*FLEN/8, x4, x1, x2)

inst_8538:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x201 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7c00; op2val:0xfe55;
op3val:0x7e01; valaddr_reg:x3; val_offset:25614*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 25614*FLEN/8, x4, x1, x2)

inst_8539:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x255 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7c00; op2val:0xfe55;
op3val:0xfe55; valaddr_reg:x3; val_offset:25617*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 25617*FLEN/8, x4, x1, x2)

inst_8540:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7c00; op2val:0xfe55;
op3val:0x7c01; valaddr_reg:x3; val_offset:25620*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 25620*FLEN/8, x4, x1, x2)

inst_8541:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x155 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7c00; op2val:0xfe55;
op3val:0xfd55; valaddr_reg:x3; val_offset:25623*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 25623*FLEN/8, x4, x1, x2)

inst_8542:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fs3 == 0 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7c00; op2val:0xfe55;
op3val:0x3c00; valaddr_reg:x3; val_offset:25626*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 25626*FLEN/8, x4, x1, x2)

inst_8543:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fs3 == 1 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7c00; op2val:0xfe55;
op3val:0xbc00; valaddr_reg:x3; val_offset:25629*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 25629*FLEN/8, x4, x1, x2)

inst_8544:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7c00; op2val:0x7c01;
op3val:0x0; valaddr_reg:x3; val_offset:25632*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 25632*FLEN/8, x4, x1, x2)

inst_8545:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7c00; op2val:0x7c01;
op3val:0x8000; valaddr_reg:x3; val_offset:25635*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 25635*FLEN/8, x4, x1, x2)

inst_8546:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7c00; op2val:0x7c01;
op3val:0x1; valaddr_reg:x3; val_offset:25638*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 25638*FLEN/8, x4, x1, x2)

inst_8547:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7c00; op2val:0x7c01;
op3val:0x8001; valaddr_reg:x3; val_offset:25641*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 25641*FLEN/8, x4, x1, x2)

inst_8548:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x002 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7c00; op2val:0x7c01;
op3val:0x2; valaddr_reg:x3; val_offset:25644*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 25644*FLEN/8, x4, x1, x2)

inst_8549:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3fe and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7c00; op2val:0x7c01;
op3val:0x83fe; valaddr_reg:x3; val_offset:25647*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 25647*FLEN/8, x4, x1, x2)

inst_8550:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7c00; op2val:0x7c01;
op3val:0x3ff; valaddr_reg:x3; val_offset:25650*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 25650*FLEN/8, x4, x1, x2)

inst_8551:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7c00; op2val:0x7c01;
op3val:0x83ff; valaddr_reg:x3; val_offset:25653*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 25653*FLEN/8, x4, x1, x2)

inst_8552:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7c00; op2val:0x7c01;
op3val:0x400; valaddr_reg:x3; val_offset:25656*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 25656*FLEN/8, x4, x1, x2)

inst_8553:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7c00; op2val:0x7c01;
op3val:0x8400; valaddr_reg:x3; val_offset:25659*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 25659*FLEN/8, x4, x1, x2)

inst_8554:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7c00; op2val:0x7c01;
op3val:0x401; valaddr_reg:x3; val_offset:25662*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 25662*FLEN/8, x4, x1, x2)

inst_8555:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7c00; op2val:0x7c01;
op3val:0x8455; valaddr_reg:x3; val_offset:25665*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 25665*FLEN/8, x4, x1, x2)

inst_8556:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7c00; op2val:0x7c01;
op3val:0x7bff; valaddr_reg:x3; val_offset:25668*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 25668*FLEN/8, x4, x1, x2)

inst_8557:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7c00; op2val:0x7c01;
op3val:0xfbff; valaddr_reg:x3; val_offset:25671*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 25671*FLEN/8, x4, x1, x2)

inst_8558:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7c00; op2val:0x7c01;
op3val:0x7c00; valaddr_reg:x3; val_offset:25674*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 25674*FLEN/8, x4, x1, x2)

inst_8559:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7c00; op2val:0x7c01;
op3val:0xfc00; valaddr_reg:x3; val_offset:25677*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 25677*FLEN/8, x4, x1, x2)

inst_8560:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7c00; op2val:0x7c01;
op3val:0x7e00; valaddr_reg:x3; val_offset:25680*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 25680*FLEN/8, x4, x1, x2)

inst_8561:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7c00; op2val:0x7c01;
op3val:0xfe00; valaddr_reg:x3; val_offset:25683*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 25683*FLEN/8, x4, x1, x2)

inst_8562:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x201 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7c00; op2val:0x7c01;
op3val:0x7e01; valaddr_reg:x3; val_offset:25686*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 25686*FLEN/8, x4, x1, x2)

inst_8563:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x255 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7c00; op2val:0x7c01;
op3val:0xfe55; valaddr_reg:x3; val_offset:25689*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 25689*FLEN/8, x4, x1, x2)

inst_8564:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7c00; op2val:0x7c01;
op3val:0x7c01; valaddr_reg:x3; val_offset:25692*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 25692*FLEN/8, x4, x1, x2)

inst_8565:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x155 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7c00; op2val:0x7c01;
op3val:0xfd55; valaddr_reg:x3; val_offset:25695*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 25695*FLEN/8, x4, x1, x2)

inst_8566:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fs3 == 0 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7c00; op2val:0x7c01;
op3val:0x3c00; valaddr_reg:x3; val_offset:25698*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 25698*FLEN/8, x4, x1, x2)

inst_8567:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fs3 == 1 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7c00; op2val:0x7c01;
op3val:0xbc00; valaddr_reg:x3; val_offset:25701*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 25701*FLEN/8, x4, x1, x2)

inst_8568:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7c00; op2val:0xfd55;
op3val:0x0; valaddr_reg:x3; val_offset:25704*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 25704*FLEN/8, x4, x1, x2)

inst_8569:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7c00; op2val:0xfd55;
op3val:0x8000; valaddr_reg:x3; val_offset:25707*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 25707*FLEN/8, x4, x1, x2)

inst_8570:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7c00; op2val:0xfd55;
op3val:0x1; valaddr_reg:x3; val_offset:25710*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 25710*FLEN/8, x4, x1, x2)

inst_8571:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7c00; op2val:0xfd55;
op3val:0x8001; valaddr_reg:x3; val_offset:25713*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 25713*FLEN/8, x4, x1, x2)

inst_8572:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x002 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7c00; op2val:0xfd55;
op3val:0x2; valaddr_reg:x3; val_offset:25716*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 25716*FLEN/8, x4, x1, x2)

inst_8573:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3fe and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7c00; op2val:0xfd55;
op3val:0x83fe; valaddr_reg:x3; val_offset:25719*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 25719*FLEN/8, x4, x1, x2)

inst_8574:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7c00; op2val:0xfd55;
op3val:0x3ff; valaddr_reg:x3; val_offset:25722*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 25722*FLEN/8, x4, x1, x2)

inst_8575:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7c00; op2val:0xfd55;
op3val:0x83ff; valaddr_reg:x3; val_offset:25725*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 25725*FLEN/8, x4, x1, x2)

RVTEST_SIGBASE(x1,signature_x1_68)
inst_8576:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7c00; op2val:0xfd55;
op3val:0x400; valaddr_reg:x3; val_offset:25728*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 25728*FLEN/8, x4, x1, x2)

inst_8577:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7c00; op2val:0xfd55;
op3val:0x8400; valaddr_reg:x3; val_offset:25731*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 25731*FLEN/8, x4, x1, x2)

inst_8578:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7c00; op2val:0xfd55;
op3val:0x401; valaddr_reg:x3; val_offset:25734*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 25734*FLEN/8, x4, x1, x2)

inst_8579:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7c00; op2val:0xfd55;
op3val:0x8455; valaddr_reg:x3; val_offset:25737*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 25737*FLEN/8, x4, x1, x2)

inst_8580:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7c00; op2val:0xfd55;
op3val:0x7bff; valaddr_reg:x3; val_offset:25740*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 25740*FLEN/8, x4, x1, x2)

inst_8581:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7c00; op2val:0xfd55;
op3val:0xfbff; valaddr_reg:x3; val_offset:25743*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 25743*FLEN/8, x4, x1, x2)

inst_8582:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7c00; op2val:0xfd55;
op3val:0x7c00; valaddr_reg:x3; val_offset:25746*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 25746*FLEN/8, x4, x1, x2)

inst_8583:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7c00; op2val:0xfd55;
op3val:0xfc00; valaddr_reg:x3; val_offset:25749*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 25749*FLEN/8, x4, x1, x2)

inst_8584:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7c00; op2val:0xfd55;
op3val:0x7e00; valaddr_reg:x3; val_offset:25752*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 25752*FLEN/8, x4, x1, x2)

inst_8585:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7c00; op2val:0xfd55;
op3val:0xfe00; valaddr_reg:x3; val_offset:25755*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 25755*FLEN/8, x4, x1, x2)

inst_8586:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x201 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7c00; op2val:0xfd55;
op3val:0x7e01; valaddr_reg:x3; val_offset:25758*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 25758*FLEN/8, x4, x1, x2)

inst_8587:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x255 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7c00; op2val:0xfd55;
op3val:0xfe55; valaddr_reg:x3; val_offset:25761*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 25761*FLEN/8, x4, x1, x2)

inst_8588:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7c00; op2val:0xfd55;
op3val:0x7c01; valaddr_reg:x3; val_offset:25764*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 25764*FLEN/8, x4, x1, x2)

inst_8589:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x155 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7c00; op2val:0xfd55;
op3val:0xfd55; valaddr_reg:x3; val_offset:25767*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 25767*FLEN/8, x4, x1, x2)

inst_8590:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fs3 == 0 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7c00; op2val:0xfd55;
op3val:0x3c00; valaddr_reg:x3; val_offset:25770*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 25770*FLEN/8, x4, x1, x2)

inst_8591:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fs3 == 1 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7c00; op2val:0xfd55;
op3val:0xbc00; valaddr_reg:x3; val_offset:25773*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 25773*FLEN/8, x4, x1, x2)

inst_8592:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7c00; op2val:0x3c00;
op3val:0x0; valaddr_reg:x3; val_offset:25776*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 25776*FLEN/8, x4, x1, x2)

inst_8593:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7c00; op2val:0x3c00;
op3val:0x8000; valaddr_reg:x3; val_offset:25779*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 25779*FLEN/8, x4, x1, x2)

inst_8594:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7c00; op2val:0x3c00;
op3val:0x1; valaddr_reg:x3; val_offset:25782*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 25782*FLEN/8, x4, x1, x2)

inst_8595:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7c00; op2val:0x3c00;
op3val:0x8001; valaddr_reg:x3; val_offset:25785*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 25785*FLEN/8, x4, x1, x2)

inst_8596:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x002 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7c00; op2val:0x3c00;
op3val:0x2; valaddr_reg:x3; val_offset:25788*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 25788*FLEN/8, x4, x1, x2)

inst_8597:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3fe and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7c00; op2val:0x3c00;
op3val:0x83fe; valaddr_reg:x3; val_offset:25791*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 25791*FLEN/8, x4, x1, x2)

inst_8598:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7c00; op2val:0x3c00;
op3val:0x3ff; valaddr_reg:x3; val_offset:25794*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 25794*FLEN/8, x4, x1, x2)

inst_8599:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7c00; op2val:0x3c00;
op3val:0x83ff; valaddr_reg:x3; val_offset:25797*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 25797*FLEN/8, x4, x1, x2)

inst_8600:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7c00; op2val:0x3c00;
op3val:0x400; valaddr_reg:x3; val_offset:25800*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 25800*FLEN/8, x4, x1, x2)

inst_8601:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7c00; op2val:0x3c00;
op3val:0x8400; valaddr_reg:x3; val_offset:25803*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 25803*FLEN/8, x4, x1, x2)

inst_8602:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7c00; op2val:0x3c00;
op3val:0x401; valaddr_reg:x3; val_offset:25806*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 25806*FLEN/8, x4, x1, x2)

inst_8603:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7c00; op2val:0x3c00;
op3val:0x8455; valaddr_reg:x3; val_offset:25809*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 25809*FLEN/8, x4, x1, x2)

inst_8604:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7c00; op2val:0x3c00;
op3val:0x7bff; valaddr_reg:x3; val_offset:25812*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 25812*FLEN/8, x4, x1, x2)

inst_8605:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7c00; op2val:0x3c00;
op3val:0xfbff; valaddr_reg:x3; val_offset:25815*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 25815*FLEN/8, x4, x1, x2)

inst_8606:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7c00; op2val:0x3c00;
op3val:0x7c00; valaddr_reg:x3; val_offset:25818*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 25818*FLEN/8, x4, x1, x2)

inst_8607:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7c00; op2val:0x3c00;
op3val:0xfc00; valaddr_reg:x3; val_offset:25821*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 25821*FLEN/8, x4, x1, x2)

inst_8608:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7c00; op2val:0x3c00;
op3val:0x7e00; valaddr_reg:x3; val_offset:25824*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 25824*FLEN/8, x4, x1, x2)

inst_8609:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7c00; op2val:0x3c00;
op3val:0xfe00; valaddr_reg:x3; val_offset:25827*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 25827*FLEN/8, x4, x1, x2)

inst_8610:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x201 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7c00; op2val:0x3c00;
op3val:0x7e01; valaddr_reg:x3; val_offset:25830*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 25830*FLEN/8, x4, x1, x2)

inst_8611:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x255 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7c00; op2val:0x3c00;
op3val:0xfe55; valaddr_reg:x3; val_offset:25833*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 25833*FLEN/8, x4, x1, x2)

inst_8612:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7c00; op2val:0x3c00;
op3val:0x7c01; valaddr_reg:x3; val_offset:25836*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 25836*FLEN/8, x4, x1, x2)

inst_8613:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x155 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7c00; op2val:0x3c00;
op3val:0xfd55; valaddr_reg:x3; val_offset:25839*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 25839*FLEN/8, x4, x1, x2)

inst_8614:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7c00; op2val:0x3c00;
op3val:0x3c00; valaddr_reg:x3; val_offset:25842*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 25842*FLEN/8, x4, x1, x2)

inst_8615:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7c00; op2val:0x3c00;
op3val:0xbc00; valaddr_reg:x3; val_offset:25845*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 25845*FLEN/8, x4, x1, x2)

inst_8616:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7c00; op2val:0xbc00;
op3val:0x0; valaddr_reg:x3; val_offset:25848*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 25848*FLEN/8, x4, x1, x2)

inst_8617:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7c00; op2val:0xbc00;
op3val:0x8000; valaddr_reg:x3; val_offset:25851*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 25851*FLEN/8, x4, x1, x2)

inst_8618:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7c00; op2val:0xbc00;
op3val:0x1; valaddr_reg:x3; val_offset:25854*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 25854*FLEN/8, x4, x1, x2)

inst_8619:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7c00; op2val:0xbc00;
op3val:0x8001; valaddr_reg:x3; val_offset:25857*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 25857*FLEN/8, x4, x1, x2)

inst_8620:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x002 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7c00; op2val:0xbc00;
op3val:0x2; valaddr_reg:x3; val_offset:25860*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 25860*FLEN/8, x4, x1, x2)

inst_8621:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3fe and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7c00; op2val:0xbc00;
op3val:0x83fe; valaddr_reg:x3; val_offset:25863*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 25863*FLEN/8, x4, x1, x2)

inst_8622:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7c00; op2val:0xbc00;
op3val:0x3ff; valaddr_reg:x3; val_offset:25866*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 25866*FLEN/8, x4, x1, x2)

inst_8623:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7c00; op2val:0xbc00;
op3val:0x83ff; valaddr_reg:x3; val_offset:25869*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 25869*FLEN/8, x4, x1, x2)

inst_8624:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7c00; op2val:0xbc00;
op3val:0x400; valaddr_reg:x3; val_offset:25872*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 25872*FLEN/8, x4, x1, x2)

inst_8625:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7c00; op2val:0xbc00;
op3val:0x8400; valaddr_reg:x3; val_offset:25875*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 25875*FLEN/8, x4, x1, x2)

inst_8626:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7c00; op2val:0xbc00;
op3val:0x401; valaddr_reg:x3; val_offset:25878*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 25878*FLEN/8, x4, x1, x2)

inst_8627:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7c00; op2val:0xbc00;
op3val:0x8455; valaddr_reg:x3; val_offset:25881*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 25881*FLEN/8, x4, x1, x2)

inst_8628:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7c00; op2val:0xbc00;
op3val:0x7bff; valaddr_reg:x3; val_offset:25884*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 25884*FLEN/8, x4, x1, x2)

inst_8629:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7c00; op2val:0xbc00;
op3val:0xfbff; valaddr_reg:x3; val_offset:25887*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 25887*FLEN/8, x4, x1, x2)

inst_8630:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7c00; op2val:0xbc00;
op3val:0x7c00; valaddr_reg:x3; val_offset:25890*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 25890*FLEN/8, x4, x1, x2)

inst_8631:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7c00; op2val:0xbc00;
op3val:0xfc00; valaddr_reg:x3; val_offset:25893*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 25893*FLEN/8, x4, x1, x2)

inst_8632:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7c00; op2val:0xbc00;
op3val:0x7e00; valaddr_reg:x3; val_offset:25896*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 25896*FLEN/8, x4, x1, x2)

inst_8633:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7c00; op2val:0xbc00;
op3val:0xfe00; valaddr_reg:x3; val_offset:25899*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 25899*FLEN/8, x4, x1, x2)

inst_8634:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x201 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7c00; op2val:0xbc00;
op3val:0x7e01; valaddr_reg:x3; val_offset:25902*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 25902*FLEN/8, x4, x1, x2)

inst_8635:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x255 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7c00; op2val:0xbc00;
op3val:0xfe55; valaddr_reg:x3; val_offset:25905*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 25905*FLEN/8, x4, x1, x2)

inst_8636:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7c00; op2val:0xbc00;
op3val:0x7c01; valaddr_reg:x3; val_offset:25908*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 25908*FLEN/8, x4, x1, x2)

inst_8637:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x155 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7c00; op2val:0xbc00;
op3val:0xfd55; valaddr_reg:x3; val_offset:25911*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 25911*FLEN/8, x4, x1, x2)

inst_8638:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7c00; op2val:0xbc00;
op3val:0x3c00; valaddr_reg:x3; val_offset:25914*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 25914*FLEN/8, x4, x1, x2)

inst_8639:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7c00; op2val:0xbc00;
op3val:0xbc00; valaddr_reg:x3; val_offset:25917*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 25917*FLEN/8, x4, x1, x2)

inst_8640:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfc00; op2val:0x0;
op3val:0x0; valaddr_reg:x3; val_offset:25920*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 25920*FLEN/8, x4, x1, x2)

inst_8641:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfc00; op2val:0x0;
op3val:0x8000; valaddr_reg:x3; val_offset:25923*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 25923*FLEN/8, x4, x1, x2)

inst_8642:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfc00; op2val:0x0;
op3val:0x1; valaddr_reg:x3; val_offset:25926*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 25926*FLEN/8, x4, x1, x2)

inst_8643:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfc00; op2val:0x0;
op3val:0x8001; valaddr_reg:x3; val_offset:25929*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 25929*FLEN/8, x4, x1, x2)

inst_8644:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x002 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfc00; op2val:0x0;
op3val:0x2; valaddr_reg:x3; val_offset:25932*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 25932*FLEN/8, x4, x1, x2)

inst_8645:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3fe and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfc00; op2val:0x0;
op3val:0x83fe; valaddr_reg:x3; val_offset:25935*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 25935*FLEN/8, x4, x1, x2)

inst_8646:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfc00; op2val:0x0;
op3val:0x3ff; valaddr_reg:x3; val_offset:25938*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 25938*FLEN/8, x4, x1, x2)

inst_8647:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfc00; op2val:0x0;
op3val:0x83ff; valaddr_reg:x3; val_offset:25941*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 25941*FLEN/8, x4, x1, x2)

inst_8648:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfc00; op2val:0x0;
op3val:0x400; valaddr_reg:x3; val_offset:25944*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 25944*FLEN/8, x4, x1, x2)

inst_8649:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfc00; op2val:0x0;
op3val:0x8400; valaddr_reg:x3; val_offset:25947*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 25947*FLEN/8, x4, x1, x2)

inst_8650:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfc00; op2val:0x0;
op3val:0x401; valaddr_reg:x3; val_offset:25950*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 25950*FLEN/8, x4, x1, x2)

inst_8651:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfc00; op2val:0x0;
op3val:0x8455; valaddr_reg:x3; val_offset:25953*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 25953*FLEN/8, x4, x1, x2)

inst_8652:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfc00; op2val:0x0;
op3val:0x7bff; valaddr_reg:x3; val_offset:25956*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 25956*FLEN/8, x4, x1, x2)

inst_8653:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfc00; op2val:0x0;
op3val:0xfbff; valaddr_reg:x3; val_offset:25959*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 25959*FLEN/8, x4, x1, x2)

inst_8654:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfc00; op2val:0x0;
op3val:0x7c00; valaddr_reg:x3; val_offset:25962*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 25962*FLEN/8, x4, x1, x2)

inst_8655:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfc00; op2val:0x0;
op3val:0xfc00; valaddr_reg:x3; val_offset:25965*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 25965*FLEN/8, x4, x1, x2)

inst_8656:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfc00; op2val:0x0;
op3val:0x7e00; valaddr_reg:x3; val_offset:25968*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 25968*FLEN/8, x4, x1, x2)

inst_8657:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfc00; op2val:0x0;
op3val:0xfe00; valaddr_reg:x3; val_offset:25971*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 25971*FLEN/8, x4, x1, x2)

inst_8658:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x201 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfc00; op2val:0x0;
op3val:0x7e01; valaddr_reg:x3; val_offset:25974*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 25974*FLEN/8, x4, x1, x2)

inst_8659:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x255 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfc00; op2val:0x0;
op3val:0xfe55; valaddr_reg:x3; val_offset:25977*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 25977*FLEN/8, x4, x1, x2)

inst_8660:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfc00; op2val:0x0;
op3val:0x7c01; valaddr_reg:x3; val_offset:25980*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 25980*FLEN/8, x4, x1, x2)

inst_8661:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x155 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfc00; op2val:0x0;
op3val:0xfd55; valaddr_reg:x3; val_offset:25983*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 25983*FLEN/8, x4, x1, x2)

inst_8662:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfc00; op2val:0x0;
op3val:0x3c00; valaddr_reg:x3; val_offset:25986*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 25986*FLEN/8, x4, x1, x2)

inst_8663:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfc00; op2val:0x0;
op3val:0xbc00; valaddr_reg:x3; val_offset:25989*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 25989*FLEN/8, x4, x1, x2)

inst_8664:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfc00; op2val:0x8000;
op3val:0x0; valaddr_reg:x3; val_offset:25992*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 25992*FLEN/8, x4, x1, x2)

inst_8665:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfc00; op2val:0x8000;
op3val:0x8000; valaddr_reg:x3; val_offset:25995*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 25995*FLEN/8, x4, x1, x2)

inst_8666:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfc00; op2val:0x8000;
op3val:0x1; valaddr_reg:x3; val_offset:25998*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 25998*FLEN/8, x4, x1, x2)

inst_8667:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfc00; op2val:0x8000;
op3val:0x8001; valaddr_reg:x3; val_offset:26001*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 26001*FLEN/8, x4, x1, x2)

inst_8668:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x002 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfc00; op2val:0x8000;
op3val:0x2; valaddr_reg:x3; val_offset:26004*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 26004*FLEN/8, x4, x1, x2)

inst_8669:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3fe and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfc00; op2val:0x8000;
op3val:0x83fe; valaddr_reg:x3; val_offset:26007*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 26007*FLEN/8, x4, x1, x2)

inst_8670:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfc00; op2val:0x8000;
op3val:0x3ff; valaddr_reg:x3; val_offset:26010*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 26010*FLEN/8, x4, x1, x2)

inst_8671:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfc00; op2val:0x8000;
op3val:0x83ff; valaddr_reg:x3; val_offset:26013*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 26013*FLEN/8, x4, x1, x2)

inst_8672:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfc00; op2val:0x8000;
op3val:0x400; valaddr_reg:x3; val_offset:26016*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 26016*FLEN/8, x4, x1, x2)

inst_8673:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfc00; op2val:0x8000;
op3val:0x8400; valaddr_reg:x3; val_offset:26019*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 26019*FLEN/8, x4, x1, x2)

inst_8674:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfc00; op2val:0x8000;
op3val:0x401; valaddr_reg:x3; val_offset:26022*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 26022*FLEN/8, x4, x1, x2)

inst_8675:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfc00; op2val:0x8000;
op3val:0x8455; valaddr_reg:x3; val_offset:26025*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 26025*FLEN/8, x4, x1, x2)

inst_8676:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfc00; op2val:0x8000;
op3val:0x7bff; valaddr_reg:x3; val_offset:26028*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 26028*FLEN/8, x4, x1, x2)

inst_8677:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfc00; op2val:0x8000;
op3val:0xfbff; valaddr_reg:x3; val_offset:26031*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 26031*FLEN/8, x4, x1, x2)

inst_8678:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfc00; op2val:0x8000;
op3val:0x7c00; valaddr_reg:x3; val_offset:26034*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 26034*FLEN/8, x4, x1, x2)

inst_8679:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfc00; op2val:0x8000;
op3val:0xfc00; valaddr_reg:x3; val_offset:26037*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 26037*FLEN/8, x4, x1, x2)

inst_8680:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfc00; op2val:0x8000;
op3val:0x7e00; valaddr_reg:x3; val_offset:26040*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 26040*FLEN/8, x4, x1, x2)

inst_8681:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfc00; op2val:0x8000;
op3val:0xfe00; valaddr_reg:x3; val_offset:26043*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 26043*FLEN/8, x4, x1, x2)

inst_8682:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x201 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfc00; op2val:0x8000;
op3val:0x7e01; valaddr_reg:x3; val_offset:26046*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 26046*FLEN/8, x4, x1, x2)

inst_8683:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x255 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfc00; op2val:0x8000;
op3val:0xfe55; valaddr_reg:x3; val_offset:26049*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 26049*FLEN/8, x4, x1, x2)

inst_8684:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfc00; op2val:0x8000;
op3val:0x7c01; valaddr_reg:x3; val_offset:26052*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 26052*FLEN/8, x4, x1, x2)

inst_8685:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x155 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfc00; op2val:0x8000;
op3val:0xfd55; valaddr_reg:x3; val_offset:26055*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 26055*FLEN/8, x4, x1, x2)

inst_8686:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfc00; op2val:0x8000;
op3val:0x3c00; valaddr_reg:x3; val_offset:26058*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 26058*FLEN/8, x4, x1, x2)

inst_8687:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfc00; op2val:0x8000;
op3val:0xbc00; valaddr_reg:x3; val_offset:26061*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 26061*FLEN/8, x4, x1, x2)

inst_8688:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfc00; op2val:0x1;
op3val:0x0; valaddr_reg:x3; val_offset:26064*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 26064*FLEN/8, x4, x1, x2)

inst_8689:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfc00; op2val:0x1;
op3val:0x8000; valaddr_reg:x3; val_offset:26067*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 26067*FLEN/8, x4, x1, x2)

inst_8690:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfc00; op2val:0x1;
op3val:0x1; valaddr_reg:x3; val_offset:26070*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 26070*FLEN/8, x4, x1, x2)

inst_8691:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfc00; op2val:0x1;
op3val:0x8001; valaddr_reg:x3; val_offset:26073*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 26073*FLEN/8, x4, x1, x2)

inst_8692:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x002 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfc00; op2val:0x1;
op3val:0x2; valaddr_reg:x3; val_offset:26076*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 26076*FLEN/8, x4, x1, x2)

inst_8693:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3fe and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfc00; op2val:0x1;
op3val:0x83fe; valaddr_reg:x3; val_offset:26079*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 26079*FLEN/8, x4, x1, x2)

inst_8694:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfc00; op2val:0x1;
op3val:0x3ff; valaddr_reg:x3; val_offset:26082*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 26082*FLEN/8, x4, x1, x2)

inst_8695:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfc00; op2val:0x1;
op3val:0x83ff; valaddr_reg:x3; val_offset:26085*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 26085*FLEN/8, x4, x1, x2)

inst_8696:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfc00; op2val:0x1;
op3val:0x400; valaddr_reg:x3; val_offset:26088*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 26088*FLEN/8, x4, x1, x2)

inst_8697:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfc00; op2val:0x1;
op3val:0x8400; valaddr_reg:x3; val_offset:26091*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 26091*FLEN/8, x4, x1, x2)

inst_8698:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfc00; op2val:0x1;
op3val:0x401; valaddr_reg:x3; val_offset:26094*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 26094*FLEN/8, x4, x1, x2)

inst_8699:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfc00; op2val:0x1;
op3val:0x8455; valaddr_reg:x3; val_offset:26097*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 26097*FLEN/8, x4, x1, x2)

inst_8700:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfc00; op2val:0x1;
op3val:0x7bff; valaddr_reg:x3; val_offset:26100*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 26100*FLEN/8, x4, x1, x2)

inst_8701:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfc00; op2val:0x1;
op3val:0xfbff; valaddr_reg:x3; val_offset:26103*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 26103*FLEN/8, x4, x1, x2)

inst_8702:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfc00; op2val:0x1;
op3val:0x7c00; valaddr_reg:x3; val_offset:26106*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 26106*FLEN/8, x4, x1, x2)

inst_8703:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfc00; op2val:0x1;
op3val:0xfc00; valaddr_reg:x3; val_offset:26109*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 26109*FLEN/8, x4, x1, x2)

RVTEST_SIGBASE(x1,signature_x1_69)
inst_8704:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfc00; op2val:0x1;
op3val:0x7e00; valaddr_reg:x3; val_offset:26112*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 26112*FLEN/8, x4, x1, x2)

inst_8705:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfc00; op2val:0x1;
op3val:0xfe00; valaddr_reg:x3; val_offset:26115*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 26115*FLEN/8, x4, x1, x2)

inst_8706:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x201 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfc00; op2val:0x1;
op3val:0x7e01; valaddr_reg:x3; val_offset:26118*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 26118*FLEN/8, x4, x1, x2)

inst_8707:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x255 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfc00; op2val:0x1;
op3val:0xfe55; valaddr_reg:x3; val_offset:26121*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 26121*FLEN/8, x4, x1, x2)

inst_8708:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfc00; op2val:0x1;
op3val:0x7c01; valaddr_reg:x3; val_offset:26124*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 26124*FLEN/8, x4, x1, x2)

inst_8709:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x155 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfc00; op2val:0x1;
op3val:0xfd55; valaddr_reg:x3; val_offset:26127*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 26127*FLEN/8, x4, x1, x2)

inst_8710:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfc00; op2val:0x1;
op3val:0x3c00; valaddr_reg:x3; val_offset:26130*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 26130*FLEN/8, x4, x1, x2)

inst_8711:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfc00; op2val:0x1;
op3val:0xbc00; valaddr_reg:x3; val_offset:26133*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 26133*FLEN/8, x4, x1, x2)

inst_8712:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfc00; op2val:0x8001;
op3val:0x0; valaddr_reg:x3; val_offset:26136*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 26136*FLEN/8, x4, x1, x2)

inst_8713:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfc00; op2val:0x8001;
op3val:0x8000; valaddr_reg:x3; val_offset:26139*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 26139*FLEN/8, x4, x1, x2)

inst_8714:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfc00; op2val:0x8001;
op3val:0x1; valaddr_reg:x3; val_offset:26142*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 26142*FLEN/8, x4, x1, x2)

inst_8715:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfc00; op2val:0x8001;
op3val:0x8001; valaddr_reg:x3; val_offset:26145*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 26145*FLEN/8, x4, x1, x2)

inst_8716:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x002 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfc00; op2val:0x8001;
op3val:0x2; valaddr_reg:x3; val_offset:26148*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 26148*FLEN/8, x4, x1, x2)

inst_8717:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3fe and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfc00; op2val:0x8001;
op3val:0x83fe; valaddr_reg:x3; val_offset:26151*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 26151*FLEN/8, x4, x1, x2)

inst_8718:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfc00; op2val:0x8001;
op3val:0x3ff; valaddr_reg:x3; val_offset:26154*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 26154*FLEN/8, x4, x1, x2)

inst_8719:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfc00; op2val:0x8001;
op3val:0x83ff; valaddr_reg:x3; val_offset:26157*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 26157*FLEN/8, x4, x1, x2)

inst_8720:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfc00; op2val:0x8001;
op3val:0x400; valaddr_reg:x3; val_offset:26160*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 26160*FLEN/8, x4, x1, x2)

inst_8721:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfc00; op2val:0x8001;
op3val:0x8400; valaddr_reg:x3; val_offset:26163*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 26163*FLEN/8, x4, x1, x2)

inst_8722:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfc00; op2val:0x8001;
op3val:0x401; valaddr_reg:x3; val_offset:26166*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 26166*FLEN/8, x4, x1, x2)

inst_8723:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfc00; op2val:0x8001;
op3val:0x8455; valaddr_reg:x3; val_offset:26169*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 26169*FLEN/8, x4, x1, x2)

inst_8724:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfc00; op2val:0x8001;
op3val:0x7bff; valaddr_reg:x3; val_offset:26172*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 26172*FLEN/8, x4, x1, x2)

inst_8725:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfc00; op2val:0x8001;
op3val:0xfbff; valaddr_reg:x3; val_offset:26175*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 26175*FLEN/8, x4, x1, x2)

inst_8726:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfc00; op2val:0x8001;
op3val:0x7c00; valaddr_reg:x3; val_offset:26178*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 26178*FLEN/8, x4, x1, x2)

inst_8727:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfc00; op2val:0x8001;
op3val:0xfc00; valaddr_reg:x3; val_offset:26181*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 26181*FLEN/8, x4, x1, x2)

inst_8728:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfc00; op2val:0x8001;
op3val:0x7e00; valaddr_reg:x3; val_offset:26184*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 26184*FLEN/8, x4, x1, x2)

inst_8729:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfc00; op2val:0x8001;
op3val:0xfe00; valaddr_reg:x3; val_offset:26187*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 26187*FLEN/8, x4, x1, x2)

inst_8730:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x201 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfc00; op2val:0x8001;
op3val:0x7e01; valaddr_reg:x3; val_offset:26190*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 26190*FLEN/8, x4, x1, x2)

inst_8731:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x255 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfc00; op2val:0x8001;
op3val:0xfe55; valaddr_reg:x3; val_offset:26193*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 26193*FLEN/8, x4, x1, x2)

inst_8732:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfc00; op2val:0x8001;
op3val:0x7c01; valaddr_reg:x3; val_offset:26196*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 26196*FLEN/8, x4, x1, x2)

inst_8733:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x155 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfc00; op2val:0x8001;
op3val:0xfd55; valaddr_reg:x3; val_offset:26199*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 26199*FLEN/8, x4, x1, x2)

inst_8734:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfc00; op2val:0x8001;
op3val:0x3c00; valaddr_reg:x3; val_offset:26202*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 26202*FLEN/8, x4, x1, x2)

inst_8735:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfc00; op2val:0x8001;
op3val:0xbc00; valaddr_reg:x3; val_offset:26205*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 26205*FLEN/8, x4, x1, x2)

inst_8736:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfc00; op2val:0x2;
op3val:0x0; valaddr_reg:x3; val_offset:26208*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 26208*FLEN/8, x4, x1, x2)

inst_8737:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfc00; op2val:0x2;
op3val:0x8000; valaddr_reg:x3; val_offset:26211*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 26211*FLEN/8, x4, x1, x2)

inst_8738:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfc00; op2val:0x2;
op3val:0x1; valaddr_reg:x3; val_offset:26214*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 26214*FLEN/8, x4, x1, x2)

inst_8739:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfc00; op2val:0x2;
op3val:0x8001; valaddr_reg:x3; val_offset:26217*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 26217*FLEN/8, x4, x1, x2)

inst_8740:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x002 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfc00; op2val:0x2;
op3val:0x2; valaddr_reg:x3; val_offset:26220*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 26220*FLEN/8, x4, x1, x2)

inst_8741:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3fe and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfc00; op2val:0x2;
op3val:0x83fe; valaddr_reg:x3; val_offset:26223*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 26223*FLEN/8, x4, x1, x2)

inst_8742:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfc00; op2val:0x2;
op3val:0x3ff; valaddr_reg:x3; val_offset:26226*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 26226*FLEN/8, x4, x1, x2)

inst_8743:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfc00; op2val:0x2;
op3val:0x83ff; valaddr_reg:x3; val_offset:26229*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 26229*FLEN/8, x4, x1, x2)

inst_8744:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfc00; op2val:0x2;
op3val:0x400; valaddr_reg:x3; val_offset:26232*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 26232*FLEN/8, x4, x1, x2)

inst_8745:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfc00; op2val:0x2;
op3val:0x8400; valaddr_reg:x3; val_offset:26235*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 26235*FLEN/8, x4, x1, x2)

inst_8746:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfc00; op2val:0x2;
op3val:0x401; valaddr_reg:x3; val_offset:26238*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 26238*FLEN/8, x4, x1, x2)

inst_8747:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfc00; op2val:0x2;
op3val:0x8455; valaddr_reg:x3; val_offset:26241*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 26241*FLEN/8, x4, x1, x2)

inst_8748:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfc00; op2val:0x2;
op3val:0x7bff; valaddr_reg:x3; val_offset:26244*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 26244*FLEN/8, x4, x1, x2)

inst_8749:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfc00; op2val:0x2;
op3val:0xfbff; valaddr_reg:x3; val_offset:26247*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 26247*FLEN/8, x4, x1, x2)

inst_8750:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfc00; op2val:0x2;
op3val:0x7c00; valaddr_reg:x3; val_offset:26250*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 26250*FLEN/8, x4, x1, x2)

inst_8751:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfc00; op2val:0x2;
op3val:0xfc00; valaddr_reg:x3; val_offset:26253*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 26253*FLEN/8, x4, x1, x2)

inst_8752:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfc00; op2val:0x2;
op3val:0x7e00; valaddr_reg:x3; val_offset:26256*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 26256*FLEN/8, x4, x1, x2)

inst_8753:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfc00; op2val:0x2;
op3val:0xfe00; valaddr_reg:x3; val_offset:26259*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 26259*FLEN/8, x4, x1, x2)

inst_8754:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x201 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfc00; op2val:0x2;
op3val:0x7e01; valaddr_reg:x3; val_offset:26262*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 26262*FLEN/8, x4, x1, x2)

inst_8755:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x255 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfc00; op2val:0x2;
op3val:0xfe55; valaddr_reg:x3; val_offset:26265*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 26265*FLEN/8, x4, x1, x2)

inst_8756:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfc00; op2val:0x2;
op3val:0x7c01; valaddr_reg:x3; val_offset:26268*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 26268*FLEN/8, x4, x1, x2)

inst_8757:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x155 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfc00; op2val:0x2;
op3val:0xfd55; valaddr_reg:x3; val_offset:26271*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 26271*FLEN/8, x4, x1, x2)

inst_8758:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fs3 == 0 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfc00; op2val:0x2;
op3val:0x3c00; valaddr_reg:x3; val_offset:26274*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 26274*FLEN/8, x4, x1, x2)

inst_8759:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fs3 == 1 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfc00; op2val:0x2;
op3val:0xbc00; valaddr_reg:x3; val_offset:26277*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 26277*FLEN/8, x4, x1, x2)

inst_8760:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfc00; op2val:0x83fe;
op3val:0x0; valaddr_reg:x3; val_offset:26280*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 26280*FLEN/8, x4, x1, x2)

inst_8761:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfc00; op2val:0x83fe;
op3val:0x8000; valaddr_reg:x3; val_offset:26283*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 26283*FLEN/8, x4, x1, x2)

inst_8762:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fs3 == 0 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfc00; op2val:0x83fe;
op3val:0x1; valaddr_reg:x3; val_offset:26286*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 26286*FLEN/8, x4, x1, x2)

inst_8763:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fs3 == 1 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfc00; op2val:0x83fe;
op3val:0x8001; valaddr_reg:x3; val_offset:26289*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 26289*FLEN/8, x4, x1, x2)

inst_8764:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fs3 == 0 and fe3 == 0x00 and fm3 == 0x002 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfc00; op2val:0x83fe;
op3val:0x2; valaddr_reg:x3; val_offset:26292*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 26292*FLEN/8, x4, x1, x2)

inst_8765:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3fe and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfc00; op2val:0x83fe;
op3val:0x83fe; valaddr_reg:x3; val_offset:26295*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 26295*FLEN/8, x4, x1, x2)

inst_8766:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fs3 == 0 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfc00; op2val:0x83fe;
op3val:0x3ff; valaddr_reg:x3; val_offset:26298*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 26298*FLEN/8, x4, x1, x2)

inst_8767:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfc00; op2val:0x83fe;
op3val:0x83ff; valaddr_reg:x3; val_offset:26301*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 26301*FLEN/8, x4, x1, x2)

inst_8768:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfc00; op2val:0x83fe;
op3val:0x400; valaddr_reg:x3; val_offset:26304*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 26304*FLEN/8, x4, x1, x2)

inst_8769:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfc00; op2val:0x83fe;
op3val:0x8400; valaddr_reg:x3; val_offset:26307*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 26307*FLEN/8, x4, x1, x2)

inst_8770:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fs3 == 0 and fe3 == 0x01 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfc00; op2val:0x83fe;
op3val:0x401; valaddr_reg:x3; val_offset:26310*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 26310*FLEN/8, x4, x1, x2)

inst_8771:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfc00; op2val:0x83fe;
op3val:0x8455; valaddr_reg:x3; val_offset:26313*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 26313*FLEN/8, x4, x1, x2)

inst_8772:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfc00; op2val:0x83fe;
op3val:0x7bff; valaddr_reg:x3; val_offset:26316*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 26316*FLEN/8, x4, x1, x2)

inst_8773:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfc00; op2val:0x83fe;
op3val:0xfbff; valaddr_reg:x3; val_offset:26319*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 26319*FLEN/8, x4, x1, x2)

inst_8774:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fs3 == 0 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfc00; op2val:0x83fe;
op3val:0x7c00; valaddr_reg:x3; val_offset:26322*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 26322*FLEN/8, x4, x1, x2)

inst_8775:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fs3 == 1 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfc00; op2val:0x83fe;
op3val:0xfc00; valaddr_reg:x3; val_offset:26325*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 26325*FLEN/8, x4, x1, x2)

inst_8776:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fs3 == 0 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfc00; op2val:0x83fe;
op3val:0x7e00; valaddr_reg:x3; val_offset:26328*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 26328*FLEN/8, x4, x1, x2)

inst_8777:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fs3 == 1 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfc00; op2val:0x83fe;
op3val:0xfe00; valaddr_reg:x3; val_offset:26331*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 26331*FLEN/8, x4, x1, x2)

inst_8778:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fs3 == 0 and fe3 == 0x1f and fm3 == 0x201 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfc00; op2val:0x83fe;
op3val:0x7e01; valaddr_reg:x3; val_offset:26334*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 26334*FLEN/8, x4, x1, x2)

inst_8779:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fs3 == 1 and fe3 == 0x1f and fm3 == 0x255 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfc00; op2val:0x83fe;
op3val:0xfe55; valaddr_reg:x3; val_offset:26337*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 26337*FLEN/8, x4, x1, x2)

inst_8780:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fs3 == 0 and fe3 == 0x1f and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfc00; op2val:0x83fe;
op3val:0x7c01; valaddr_reg:x3; val_offset:26340*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 26340*FLEN/8, x4, x1, x2)

inst_8781:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fs3 == 1 and fe3 == 0x1f and fm3 == 0x155 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfc00; op2val:0x83fe;
op3val:0xfd55; valaddr_reg:x3; val_offset:26343*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 26343*FLEN/8, x4, x1, x2)

inst_8782:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fs3 == 0 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfc00; op2val:0x83fe;
op3val:0x3c00; valaddr_reg:x3; val_offset:26346*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 26346*FLEN/8, x4, x1, x2)

inst_8783:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fs3 == 1 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfc00; op2val:0x83fe;
op3val:0xbc00; valaddr_reg:x3; val_offset:26349*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 26349*FLEN/8, x4, x1, x2)

inst_8784:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfc00; op2val:0x3ff;
op3val:0x0; valaddr_reg:x3; val_offset:26352*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 26352*FLEN/8, x4, x1, x2)

inst_8785:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfc00; op2val:0x3ff;
op3val:0x8000; valaddr_reg:x3; val_offset:26355*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 26355*FLEN/8, x4, x1, x2)

inst_8786:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfc00; op2val:0x3ff;
op3val:0x1; valaddr_reg:x3; val_offset:26358*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 26358*FLEN/8, x4, x1, x2)

inst_8787:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfc00; op2val:0x3ff;
op3val:0x8001; valaddr_reg:x3; val_offset:26361*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 26361*FLEN/8, x4, x1, x2)

inst_8788:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x002 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfc00; op2val:0x3ff;
op3val:0x2; valaddr_reg:x3; val_offset:26364*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 26364*FLEN/8, x4, x1, x2)

inst_8789:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3fe and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfc00; op2val:0x3ff;
op3val:0x83fe; valaddr_reg:x3; val_offset:26367*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 26367*FLEN/8, x4, x1, x2)

inst_8790:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfc00; op2val:0x3ff;
op3val:0x3ff; valaddr_reg:x3; val_offset:26370*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 26370*FLEN/8, x4, x1, x2)

inst_8791:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfc00; op2val:0x3ff;
op3val:0x83ff; valaddr_reg:x3; val_offset:26373*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 26373*FLEN/8, x4, x1, x2)

inst_8792:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfc00; op2val:0x3ff;
op3val:0x400; valaddr_reg:x3; val_offset:26376*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 26376*FLEN/8, x4, x1, x2)

inst_8793:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfc00; op2val:0x3ff;
op3val:0x8400; valaddr_reg:x3; val_offset:26379*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 26379*FLEN/8, x4, x1, x2)

inst_8794:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x01 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfc00; op2val:0x3ff;
op3val:0x401; valaddr_reg:x3; val_offset:26382*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 26382*FLEN/8, x4, x1, x2)

inst_8795:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfc00; op2val:0x3ff;
op3val:0x8455; valaddr_reg:x3; val_offset:26385*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 26385*FLEN/8, x4, x1, x2)

inst_8796:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfc00; op2val:0x3ff;
op3val:0x7bff; valaddr_reg:x3; val_offset:26388*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 26388*FLEN/8, x4, x1, x2)

inst_8797:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfc00; op2val:0x3ff;
op3val:0xfbff; valaddr_reg:x3; val_offset:26391*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 26391*FLEN/8, x4, x1, x2)

inst_8798:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfc00; op2val:0x3ff;
op3val:0x7c00; valaddr_reg:x3; val_offset:26394*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 26394*FLEN/8, x4, x1, x2)

inst_8799:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfc00; op2val:0x3ff;
op3val:0xfc00; valaddr_reg:x3; val_offset:26397*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 26397*FLEN/8, x4, x1, x2)

inst_8800:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfc00; op2val:0x3ff;
op3val:0x7e00; valaddr_reg:x3; val_offset:26400*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 26400*FLEN/8, x4, x1, x2)

inst_8801:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfc00; op2val:0x3ff;
op3val:0xfe00; valaddr_reg:x3; val_offset:26403*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 26403*FLEN/8, x4, x1, x2)

inst_8802:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x1f and fm3 == 0x201 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfc00; op2val:0x3ff;
op3val:0x7e01; valaddr_reg:x3; val_offset:26406*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 26406*FLEN/8, x4, x1, x2)

inst_8803:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x1f and fm3 == 0x255 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfc00; op2val:0x3ff;
op3val:0xfe55; valaddr_reg:x3; val_offset:26409*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 26409*FLEN/8, x4, x1, x2)

inst_8804:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x1f and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfc00; op2val:0x3ff;
op3val:0x7c01; valaddr_reg:x3; val_offset:26412*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 26412*FLEN/8, x4, x1, x2)

inst_8805:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x1f and fm3 == 0x155 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfc00; op2val:0x3ff;
op3val:0xfd55; valaddr_reg:x3; val_offset:26415*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 26415*FLEN/8, x4, x1, x2)

inst_8806:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfc00; op2val:0x3ff;
op3val:0x3c00; valaddr_reg:x3; val_offset:26418*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 26418*FLEN/8, x4, x1, x2)

inst_8807:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfc00; op2val:0x3ff;
op3val:0xbc00; valaddr_reg:x3; val_offset:26421*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 26421*FLEN/8, x4, x1, x2)

inst_8808:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfc00; op2val:0x83ff;
op3val:0x0; valaddr_reg:x3; val_offset:26424*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 26424*FLEN/8, x4, x1, x2)

inst_8809:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfc00; op2val:0x83ff;
op3val:0x8000; valaddr_reg:x3; val_offset:26427*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 26427*FLEN/8, x4, x1, x2)

inst_8810:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfc00; op2val:0x83ff;
op3val:0x1; valaddr_reg:x3; val_offset:26430*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 26430*FLEN/8, x4, x1, x2)

inst_8811:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfc00; op2val:0x83ff;
op3val:0x8001; valaddr_reg:x3; val_offset:26433*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 26433*FLEN/8, x4, x1, x2)

inst_8812:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x002 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfc00; op2val:0x83ff;
op3val:0x2; valaddr_reg:x3; val_offset:26436*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 26436*FLEN/8, x4, x1, x2)

inst_8813:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3fe and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfc00; op2val:0x83ff;
op3val:0x83fe; valaddr_reg:x3; val_offset:26439*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 26439*FLEN/8, x4, x1, x2)

inst_8814:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfc00; op2val:0x83ff;
op3val:0x3ff; valaddr_reg:x3; val_offset:26442*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 26442*FLEN/8, x4, x1, x2)

inst_8815:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfc00; op2val:0x83ff;
op3val:0x83ff; valaddr_reg:x3; val_offset:26445*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 26445*FLEN/8, x4, x1, x2)

inst_8816:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfc00; op2val:0x83ff;
op3val:0x400; valaddr_reg:x3; val_offset:26448*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 26448*FLEN/8, x4, x1, x2)

inst_8817:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfc00; op2val:0x83ff;
op3val:0x8400; valaddr_reg:x3; val_offset:26451*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 26451*FLEN/8, x4, x1, x2)

inst_8818:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x01 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfc00; op2val:0x83ff;
op3val:0x401; valaddr_reg:x3; val_offset:26454*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 26454*FLEN/8, x4, x1, x2)

inst_8819:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfc00; op2val:0x83ff;
op3val:0x8455; valaddr_reg:x3; val_offset:26457*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 26457*FLEN/8, x4, x1, x2)

inst_8820:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfc00; op2val:0x83ff;
op3val:0x7bff; valaddr_reg:x3; val_offset:26460*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 26460*FLEN/8, x4, x1, x2)

inst_8821:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfc00; op2val:0x83ff;
op3val:0xfbff; valaddr_reg:x3; val_offset:26463*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 26463*FLEN/8, x4, x1, x2)

inst_8822:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfc00; op2val:0x83ff;
op3val:0x7c00; valaddr_reg:x3; val_offset:26466*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 26466*FLEN/8, x4, x1, x2)

inst_8823:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfc00; op2val:0x83ff;
op3val:0xfc00; valaddr_reg:x3; val_offset:26469*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 26469*FLEN/8, x4, x1, x2)

inst_8824:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfc00; op2val:0x83ff;
op3val:0x7e00; valaddr_reg:x3; val_offset:26472*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 26472*FLEN/8, x4, x1, x2)

inst_8825:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfc00; op2val:0x83ff;
op3val:0xfe00; valaddr_reg:x3; val_offset:26475*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 26475*FLEN/8, x4, x1, x2)

inst_8826:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x1f and fm3 == 0x201 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfc00; op2val:0x83ff;
op3val:0x7e01; valaddr_reg:x3; val_offset:26478*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 26478*FLEN/8, x4, x1, x2)

inst_8827:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x1f and fm3 == 0x255 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfc00; op2val:0x83ff;
op3val:0xfe55; valaddr_reg:x3; val_offset:26481*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 26481*FLEN/8, x4, x1, x2)

inst_8828:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x1f and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfc00; op2val:0x83ff;
op3val:0x7c01; valaddr_reg:x3; val_offset:26484*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 26484*FLEN/8, x4, x1, x2)

inst_8829:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x1f and fm3 == 0x155 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfc00; op2val:0x83ff;
op3val:0xfd55; valaddr_reg:x3; val_offset:26487*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 26487*FLEN/8, x4, x1, x2)

inst_8830:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfc00; op2val:0x83ff;
op3val:0x3c00; valaddr_reg:x3; val_offset:26490*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 26490*FLEN/8, x4, x1, x2)

inst_8831:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfc00; op2val:0x83ff;
op3val:0xbc00; valaddr_reg:x3; val_offset:26493*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 26493*FLEN/8, x4, x1, x2)

RVTEST_SIGBASE(x1,signature_x1_70)
inst_8832:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfc00; op2val:0x400;
op3val:0x0; valaddr_reg:x3; val_offset:26496*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 26496*FLEN/8, x4, x1, x2)

inst_8833:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfc00; op2val:0x400;
op3val:0x8000; valaddr_reg:x3; val_offset:26499*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 26499*FLEN/8, x4, x1, x2)

inst_8834:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfc00; op2val:0x400;
op3val:0x1; valaddr_reg:x3; val_offset:26502*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 26502*FLEN/8, x4, x1, x2)

inst_8835:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfc00; op2val:0x400;
op3val:0x8001; valaddr_reg:x3; val_offset:26505*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 26505*FLEN/8, x4, x1, x2)

inst_8836:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x002 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfc00; op2val:0x400;
op3val:0x2; valaddr_reg:x3; val_offset:26508*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 26508*FLEN/8, x4, x1, x2)

inst_8837:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3fe and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfc00; op2val:0x400;
op3val:0x83fe; valaddr_reg:x3; val_offset:26511*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 26511*FLEN/8, x4, x1, x2)

inst_8838:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfc00; op2val:0x400;
op3val:0x3ff; valaddr_reg:x3; val_offset:26514*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 26514*FLEN/8, x4, x1, x2)

inst_8839:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfc00; op2val:0x400;
op3val:0x83ff; valaddr_reg:x3; val_offset:26517*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 26517*FLEN/8, x4, x1, x2)

inst_8840:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfc00; op2val:0x400;
op3val:0x400; valaddr_reg:x3; val_offset:26520*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 26520*FLEN/8, x4, x1, x2)

inst_8841:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfc00; op2val:0x400;
op3val:0x8400; valaddr_reg:x3; val_offset:26523*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 26523*FLEN/8, x4, x1, x2)

inst_8842:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfc00; op2val:0x400;
op3val:0x401; valaddr_reg:x3; val_offset:26526*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 26526*FLEN/8, x4, x1, x2)

inst_8843:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfc00; op2val:0x400;
op3val:0x8455; valaddr_reg:x3; val_offset:26529*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 26529*FLEN/8, x4, x1, x2)

inst_8844:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfc00; op2val:0x400;
op3val:0x7bff; valaddr_reg:x3; val_offset:26532*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 26532*FLEN/8, x4, x1, x2)

inst_8845:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfc00; op2val:0x400;
op3val:0xfbff; valaddr_reg:x3; val_offset:26535*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 26535*FLEN/8, x4, x1, x2)

inst_8846:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfc00; op2val:0x400;
op3val:0x7c00; valaddr_reg:x3; val_offset:26538*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 26538*FLEN/8, x4, x1, x2)

inst_8847:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfc00; op2val:0x400;
op3val:0xfc00; valaddr_reg:x3; val_offset:26541*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 26541*FLEN/8, x4, x1, x2)

inst_8848:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfc00; op2val:0x400;
op3val:0x7e00; valaddr_reg:x3; val_offset:26544*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 26544*FLEN/8, x4, x1, x2)

inst_8849:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfc00; op2val:0x400;
op3val:0xfe00; valaddr_reg:x3; val_offset:26547*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 26547*FLEN/8, x4, x1, x2)

inst_8850:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x201 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfc00; op2val:0x400;
op3val:0x7e01; valaddr_reg:x3; val_offset:26550*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 26550*FLEN/8, x4, x1, x2)

inst_8851:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x255 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfc00; op2val:0x400;
op3val:0xfe55; valaddr_reg:x3; val_offset:26553*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 26553*FLEN/8, x4, x1, x2)

inst_8852:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfc00; op2val:0x400;
op3val:0x7c01; valaddr_reg:x3; val_offset:26556*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 26556*FLEN/8, x4, x1, x2)

inst_8853:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x155 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfc00; op2val:0x400;
op3val:0xfd55; valaddr_reg:x3; val_offset:26559*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 26559*FLEN/8, x4, x1, x2)

inst_8854:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfc00; op2val:0x400;
op3val:0x3c00; valaddr_reg:x3; val_offset:26562*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 26562*FLEN/8, x4, x1, x2)

inst_8855:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfc00; op2val:0x400;
op3val:0xbc00; valaddr_reg:x3; val_offset:26565*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 26565*FLEN/8, x4, x1, x2)

inst_8856:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfc00; op2val:0x8400;
op3val:0x0; valaddr_reg:x3; val_offset:26568*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 26568*FLEN/8, x4, x1, x2)

inst_8857:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfc00; op2val:0x8400;
op3val:0x8000; valaddr_reg:x3; val_offset:26571*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 26571*FLEN/8, x4, x1, x2)

inst_8858:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfc00; op2val:0x8400;
op3val:0x1; valaddr_reg:x3; val_offset:26574*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 26574*FLEN/8, x4, x1, x2)

inst_8859:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfc00; op2val:0x8400;
op3val:0x8001; valaddr_reg:x3; val_offset:26577*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 26577*FLEN/8, x4, x1, x2)

inst_8860:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x002 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfc00; op2val:0x8400;
op3val:0x2; valaddr_reg:x3; val_offset:26580*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 26580*FLEN/8, x4, x1, x2)

inst_8861:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3fe and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfc00; op2val:0x8400;
op3val:0x83fe; valaddr_reg:x3; val_offset:26583*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 26583*FLEN/8, x4, x1, x2)

inst_8862:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfc00; op2val:0x8400;
op3val:0x3ff; valaddr_reg:x3; val_offset:26586*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 26586*FLEN/8, x4, x1, x2)

inst_8863:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfc00; op2val:0x8400;
op3val:0x83ff; valaddr_reg:x3; val_offset:26589*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 26589*FLEN/8, x4, x1, x2)

inst_8864:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfc00; op2val:0x8400;
op3val:0x400; valaddr_reg:x3; val_offset:26592*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 26592*FLEN/8, x4, x1, x2)

inst_8865:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfc00; op2val:0x8400;
op3val:0x8400; valaddr_reg:x3; val_offset:26595*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 26595*FLEN/8, x4, x1, x2)

inst_8866:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfc00; op2val:0x8400;
op3val:0x401; valaddr_reg:x3; val_offset:26598*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 26598*FLEN/8, x4, x1, x2)

inst_8867:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfc00; op2val:0x8400;
op3val:0x8455; valaddr_reg:x3; val_offset:26601*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 26601*FLEN/8, x4, x1, x2)

inst_8868:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfc00; op2val:0x8400;
op3val:0x7bff; valaddr_reg:x3; val_offset:26604*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 26604*FLEN/8, x4, x1, x2)

inst_8869:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfc00; op2val:0x8400;
op3val:0xfbff; valaddr_reg:x3; val_offset:26607*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 26607*FLEN/8, x4, x1, x2)

inst_8870:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfc00; op2val:0x8400;
op3val:0x7c00; valaddr_reg:x3; val_offset:26610*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 26610*FLEN/8, x4, x1, x2)

inst_8871:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfc00; op2val:0x8400;
op3val:0xfc00; valaddr_reg:x3; val_offset:26613*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 26613*FLEN/8, x4, x1, x2)

inst_8872:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfc00; op2val:0x8400;
op3val:0x7e00; valaddr_reg:x3; val_offset:26616*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 26616*FLEN/8, x4, x1, x2)

inst_8873:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfc00; op2val:0x8400;
op3val:0xfe00; valaddr_reg:x3; val_offset:26619*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 26619*FLEN/8, x4, x1, x2)

inst_8874:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x201 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfc00; op2val:0x8400;
op3val:0x7e01; valaddr_reg:x3; val_offset:26622*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 26622*FLEN/8, x4, x1, x2)

inst_8875:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x255 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfc00; op2val:0x8400;
op3val:0xfe55; valaddr_reg:x3; val_offset:26625*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 26625*FLEN/8, x4, x1, x2)

inst_8876:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfc00; op2val:0x8400;
op3val:0x7c01; valaddr_reg:x3; val_offset:26628*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 26628*FLEN/8, x4, x1, x2)

inst_8877:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x155 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfc00; op2val:0x8400;
op3val:0xfd55; valaddr_reg:x3; val_offset:26631*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 26631*FLEN/8, x4, x1, x2)

inst_8878:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfc00; op2val:0x8400;
op3val:0x3c00; valaddr_reg:x3; val_offset:26634*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 26634*FLEN/8, x4, x1, x2)

inst_8879:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfc00; op2val:0x8400;
op3val:0xbc00; valaddr_reg:x3; val_offset:26637*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 26637*FLEN/8, x4, x1, x2)

inst_8880:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfc00; op2val:0x401;
op3val:0x0; valaddr_reg:x3; val_offset:26640*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 26640*FLEN/8, x4, x1, x2)

inst_8881:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfc00; op2val:0x401;
op3val:0x8000; valaddr_reg:x3; val_offset:26643*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 26643*FLEN/8, x4, x1, x2)

inst_8882:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfc00; op2val:0x401;
op3val:0x1; valaddr_reg:x3; val_offset:26646*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 26646*FLEN/8, x4, x1, x2)

inst_8883:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfc00; op2val:0x401;
op3val:0x8001; valaddr_reg:x3; val_offset:26649*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 26649*FLEN/8, x4, x1, x2)

inst_8884:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x002 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfc00; op2val:0x401;
op3val:0x2; valaddr_reg:x3; val_offset:26652*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 26652*FLEN/8, x4, x1, x2)

inst_8885:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3fe and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfc00; op2val:0x401;
op3val:0x83fe; valaddr_reg:x3; val_offset:26655*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 26655*FLEN/8, x4, x1, x2)

inst_8886:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfc00; op2val:0x401;
op3val:0x3ff; valaddr_reg:x3; val_offset:26658*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 26658*FLEN/8, x4, x1, x2)

inst_8887:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfc00; op2val:0x401;
op3val:0x83ff; valaddr_reg:x3; val_offset:26661*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 26661*FLEN/8, x4, x1, x2)

inst_8888:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfc00; op2val:0x401;
op3val:0x400; valaddr_reg:x3; val_offset:26664*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 26664*FLEN/8, x4, x1, x2)

inst_8889:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfc00; op2val:0x401;
op3val:0x8400; valaddr_reg:x3; val_offset:26667*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 26667*FLEN/8, x4, x1, x2)

inst_8890:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfc00; op2val:0x401;
op3val:0x401; valaddr_reg:x3; val_offset:26670*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 26670*FLEN/8, x4, x1, x2)

inst_8891:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfc00; op2val:0x401;
op3val:0x8455; valaddr_reg:x3; val_offset:26673*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 26673*FLEN/8, x4, x1, x2)

inst_8892:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfc00; op2val:0x401;
op3val:0x7bff; valaddr_reg:x3; val_offset:26676*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 26676*FLEN/8, x4, x1, x2)

inst_8893:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfc00; op2val:0x401;
op3val:0xfbff; valaddr_reg:x3; val_offset:26679*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 26679*FLEN/8, x4, x1, x2)

inst_8894:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfc00; op2val:0x401;
op3val:0x7c00; valaddr_reg:x3; val_offset:26682*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 26682*FLEN/8, x4, x1, x2)

inst_8895:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfc00; op2val:0x401;
op3val:0xfc00; valaddr_reg:x3; val_offset:26685*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 26685*FLEN/8, x4, x1, x2)

inst_8896:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfc00; op2val:0x401;
op3val:0x7e00; valaddr_reg:x3; val_offset:26688*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 26688*FLEN/8, x4, x1, x2)

inst_8897:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfc00; op2val:0x401;
op3val:0xfe00; valaddr_reg:x3; val_offset:26691*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 26691*FLEN/8, x4, x1, x2)

inst_8898:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x201 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfc00; op2val:0x401;
op3val:0x7e01; valaddr_reg:x3; val_offset:26694*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 26694*FLEN/8, x4, x1, x2)

inst_8899:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x255 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfc00; op2val:0x401;
op3val:0xfe55; valaddr_reg:x3; val_offset:26697*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 26697*FLEN/8, x4, x1, x2)

inst_8900:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfc00; op2val:0x401;
op3val:0x7c01; valaddr_reg:x3; val_offset:26700*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 26700*FLEN/8, x4, x1, x2)

inst_8901:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x155 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfc00; op2val:0x401;
op3val:0xfd55; valaddr_reg:x3; val_offset:26703*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 26703*FLEN/8, x4, x1, x2)

inst_8902:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfc00; op2val:0x401;
op3val:0x3c00; valaddr_reg:x3; val_offset:26706*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 26706*FLEN/8, x4, x1, x2)

inst_8903:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfc00; op2val:0x401;
op3val:0xbc00; valaddr_reg:x3; val_offset:26709*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 26709*FLEN/8, x4, x1, x2)

inst_8904:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfc00; op2val:0x8455;
op3val:0x0; valaddr_reg:x3; val_offset:26712*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 26712*FLEN/8, x4, x1, x2)

inst_8905:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfc00; op2val:0x8455;
op3val:0x8000; valaddr_reg:x3; val_offset:26715*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 26715*FLEN/8, x4, x1, x2)

inst_8906:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfc00; op2val:0x8455;
op3val:0x1; valaddr_reg:x3; val_offset:26718*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 26718*FLEN/8, x4, x1, x2)

inst_8907:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfc00; op2val:0x8455;
op3val:0x8001; valaddr_reg:x3; val_offset:26721*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 26721*FLEN/8, x4, x1, x2)

inst_8908:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x002 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfc00; op2val:0x8455;
op3val:0x2; valaddr_reg:x3; val_offset:26724*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 26724*FLEN/8, x4, x1, x2)

inst_8909:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3fe and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfc00; op2val:0x8455;
op3val:0x83fe; valaddr_reg:x3; val_offset:26727*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 26727*FLEN/8, x4, x1, x2)

inst_8910:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfc00; op2val:0x8455;
op3val:0x3ff; valaddr_reg:x3; val_offset:26730*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 26730*FLEN/8, x4, x1, x2)

inst_8911:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfc00; op2val:0x8455;
op3val:0x83ff; valaddr_reg:x3; val_offset:26733*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 26733*FLEN/8, x4, x1, x2)

inst_8912:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfc00; op2val:0x8455;
op3val:0x400; valaddr_reg:x3; val_offset:26736*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 26736*FLEN/8, x4, x1, x2)

inst_8913:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfc00; op2val:0x8455;
op3val:0x8400; valaddr_reg:x3; val_offset:26739*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 26739*FLEN/8, x4, x1, x2)

inst_8914:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfc00; op2val:0x8455;
op3val:0x401; valaddr_reg:x3; val_offset:26742*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 26742*FLEN/8, x4, x1, x2)

inst_8915:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfc00; op2val:0x8455;
op3val:0x8455; valaddr_reg:x3; val_offset:26745*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 26745*FLEN/8, x4, x1, x2)

inst_8916:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfc00; op2val:0x8455;
op3val:0x7bff; valaddr_reg:x3; val_offset:26748*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 26748*FLEN/8, x4, x1, x2)

inst_8917:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfc00; op2val:0x8455;
op3val:0xfbff; valaddr_reg:x3; val_offset:26751*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 26751*FLEN/8, x4, x1, x2)

inst_8918:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfc00; op2val:0x8455;
op3val:0x7c00; valaddr_reg:x3; val_offset:26754*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 26754*FLEN/8, x4, x1, x2)

inst_8919:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfc00; op2val:0x8455;
op3val:0xfc00; valaddr_reg:x3; val_offset:26757*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 26757*FLEN/8, x4, x1, x2)

inst_8920:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfc00; op2val:0x8455;
op3val:0x7e00; valaddr_reg:x3; val_offset:26760*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 26760*FLEN/8, x4, x1, x2)

inst_8921:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfc00; op2val:0x8455;
op3val:0xfe00; valaddr_reg:x3; val_offset:26763*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 26763*FLEN/8, x4, x1, x2)

inst_8922:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x201 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfc00; op2val:0x8455;
op3val:0x7e01; valaddr_reg:x3; val_offset:26766*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 26766*FLEN/8, x4, x1, x2)

inst_8923:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x255 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfc00; op2val:0x8455;
op3val:0xfe55; valaddr_reg:x3; val_offset:26769*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 26769*FLEN/8, x4, x1, x2)

inst_8924:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfc00; op2val:0x8455;
op3val:0x7c01; valaddr_reg:x3; val_offset:26772*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 26772*FLEN/8, x4, x1, x2)

inst_8925:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x155 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfc00; op2val:0x8455;
op3val:0xfd55; valaddr_reg:x3; val_offset:26775*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 26775*FLEN/8, x4, x1, x2)

inst_8926:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fs3 == 0 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfc00; op2val:0x8455;
op3val:0x3c00; valaddr_reg:x3; val_offset:26778*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 26778*FLEN/8, x4, x1, x2)

inst_8927:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fs3 == 1 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfc00; op2val:0x8455;
op3val:0xbc00; valaddr_reg:x3; val_offset:26781*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 26781*FLEN/8, x4, x1, x2)

inst_8928:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfc00; op2val:0x7bff;
op3val:0x0; valaddr_reg:x3; val_offset:26784*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 26784*FLEN/8, x4, x1, x2)

inst_8929:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfc00; op2val:0x7bff;
op3val:0x8000; valaddr_reg:x3; val_offset:26787*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 26787*FLEN/8, x4, x1, x2)

inst_8930:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfc00; op2val:0x7bff;
op3val:0x1; valaddr_reg:x3; val_offset:26790*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 26790*FLEN/8, x4, x1, x2)

inst_8931:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfc00; op2val:0x7bff;
op3val:0x8001; valaddr_reg:x3; val_offset:26793*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 26793*FLEN/8, x4, x1, x2)

inst_8932:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x002 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfc00; op2val:0x7bff;
op3val:0x2; valaddr_reg:x3; val_offset:26796*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 26796*FLEN/8, x4, x1, x2)

inst_8933:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3fe and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfc00; op2val:0x7bff;
op3val:0x83fe; valaddr_reg:x3; val_offset:26799*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 26799*FLEN/8, x4, x1, x2)

inst_8934:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfc00; op2val:0x7bff;
op3val:0x3ff; valaddr_reg:x3; val_offset:26802*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 26802*FLEN/8, x4, x1, x2)

inst_8935:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfc00; op2val:0x7bff;
op3val:0x83ff; valaddr_reg:x3; val_offset:26805*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 26805*FLEN/8, x4, x1, x2)

inst_8936:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfc00; op2val:0x7bff;
op3val:0x400; valaddr_reg:x3; val_offset:26808*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 26808*FLEN/8, x4, x1, x2)

inst_8937:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfc00; op2val:0x7bff;
op3val:0x8400; valaddr_reg:x3; val_offset:26811*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 26811*FLEN/8, x4, x1, x2)

inst_8938:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x01 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfc00; op2val:0x7bff;
op3val:0x401; valaddr_reg:x3; val_offset:26814*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 26814*FLEN/8, x4, x1, x2)

inst_8939:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfc00; op2val:0x7bff;
op3val:0x8455; valaddr_reg:x3; val_offset:26817*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 26817*FLEN/8, x4, x1, x2)

inst_8940:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfc00; op2val:0x7bff;
op3val:0x7bff; valaddr_reg:x3; val_offset:26820*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 26820*FLEN/8, x4, x1, x2)

inst_8941:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfc00; op2val:0x7bff;
op3val:0xfbff; valaddr_reg:x3; val_offset:26823*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 26823*FLEN/8, x4, x1, x2)

inst_8942:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfc00; op2val:0x7bff;
op3val:0x7c00; valaddr_reg:x3; val_offset:26826*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 26826*FLEN/8, x4, x1, x2)

inst_8943:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfc00; op2val:0x7bff;
op3val:0xfc00; valaddr_reg:x3; val_offset:26829*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 26829*FLEN/8, x4, x1, x2)

inst_8944:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfc00; op2val:0x7bff;
op3val:0x7e00; valaddr_reg:x3; val_offset:26832*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 26832*FLEN/8, x4, x1, x2)

inst_8945:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfc00; op2val:0x7bff;
op3val:0xfe00; valaddr_reg:x3; val_offset:26835*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 26835*FLEN/8, x4, x1, x2)

inst_8946:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x1f and fm3 == 0x201 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfc00; op2val:0x7bff;
op3val:0x7e01; valaddr_reg:x3; val_offset:26838*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 26838*FLEN/8, x4, x1, x2)

inst_8947:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x1f and fm3 == 0x255 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfc00; op2val:0x7bff;
op3val:0xfe55; valaddr_reg:x3; val_offset:26841*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 26841*FLEN/8, x4, x1, x2)

inst_8948:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x1f and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfc00; op2val:0x7bff;
op3val:0x7c01; valaddr_reg:x3; val_offset:26844*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 26844*FLEN/8, x4, x1, x2)

inst_8949:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x1f and fm3 == 0x155 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfc00; op2val:0x7bff;
op3val:0xfd55; valaddr_reg:x3; val_offset:26847*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 26847*FLEN/8, x4, x1, x2)

inst_8950:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfc00; op2val:0x7bff;
op3val:0x3c00; valaddr_reg:x3; val_offset:26850*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 26850*FLEN/8, x4, x1, x2)

inst_8951:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfc00; op2val:0x7bff;
op3val:0xbc00; valaddr_reg:x3; val_offset:26853*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 26853*FLEN/8, x4, x1, x2)

inst_8952:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfc00; op2val:0xfbff;
op3val:0x0; valaddr_reg:x3; val_offset:26856*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 26856*FLEN/8, x4, x1, x2)

inst_8953:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfc00; op2val:0xfbff;
op3val:0x8000; valaddr_reg:x3; val_offset:26859*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 26859*FLEN/8, x4, x1, x2)

inst_8954:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfc00; op2val:0xfbff;
op3val:0x1; valaddr_reg:x3; val_offset:26862*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 26862*FLEN/8, x4, x1, x2)

inst_8955:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfc00; op2val:0xfbff;
op3val:0x8001; valaddr_reg:x3; val_offset:26865*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 26865*FLEN/8, x4, x1, x2)

inst_8956:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x002 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfc00; op2val:0xfbff;
op3val:0x2; valaddr_reg:x3; val_offset:26868*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 26868*FLEN/8, x4, x1, x2)

inst_8957:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3fe and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfc00; op2val:0xfbff;
op3val:0x83fe; valaddr_reg:x3; val_offset:26871*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 26871*FLEN/8, x4, x1, x2)

inst_8958:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfc00; op2val:0xfbff;
op3val:0x3ff; valaddr_reg:x3; val_offset:26874*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 26874*FLEN/8, x4, x1, x2)

inst_8959:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfc00; op2val:0xfbff;
op3val:0x83ff; valaddr_reg:x3; val_offset:26877*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 26877*FLEN/8, x4, x1, x2)

RVTEST_SIGBASE(x1,signature_x1_71)
inst_8960:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfc00; op2val:0xfbff;
op3val:0x400; valaddr_reg:x3; val_offset:26880*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 26880*FLEN/8, x4, x1, x2)

inst_8961:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfc00; op2val:0xfbff;
op3val:0x8400; valaddr_reg:x3; val_offset:26883*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 26883*FLEN/8, x4, x1, x2)

inst_8962:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x01 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfc00; op2val:0xfbff;
op3val:0x401; valaddr_reg:x3; val_offset:26886*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 26886*FLEN/8, x4, x1, x2)

inst_8963:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfc00; op2val:0xfbff;
op3val:0x8455; valaddr_reg:x3; val_offset:26889*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 26889*FLEN/8, x4, x1, x2)

inst_8964:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfc00; op2val:0xfbff;
op3val:0x7bff; valaddr_reg:x3; val_offset:26892*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 26892*FLEN/8, x4, x1, x2)

inst_8965:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfc00; op2val:0xfbff;
op3val:0xfbff; valaddr_reg:x3; val_offset:26895*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 26895*FLEN/8, x4, x1, x2)

inst_8966:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfc00; op2val:0xfbff;
op3val:0x7c00; valaddr_reg:x3; val_offset:26898*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 26898*FLEN/8, x4, x1, x2)

inst_8967:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfc00; op2val:0xfbff;
op3val:0xfc00; valaddr_reg:x3; val_offset:26901*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 26901*FLEN/8, x4, x1, x2)

inst_8968:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfc00; op2val:0xfbff;
op3val:0x7e00; valaddr_reg:x3; val_offset:26904*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 26904*FLEN/8, x4, x1, x2)

inst_8969:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfc00; op2val:0xfbff;
op3val:0xfe00; valaddr_reg:x3; val_offset:26907*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 26907*FLEN/8, x4, x1, x2)

inst_8970:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x1f and fm3 == 0x201 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfc00; op2val:0xfbff;
op3val:0x7e01; valaddr_reg:x3; val_offset:26910*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 26910*FLEN/8, x4, x1, x2)

inst_8971:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x1f and fm3 == 0x255 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfc00; op2val:0xfbff;
op3val:0xfe55; valaddr_reg:x3; val_offset:26913*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 26913*FLEN/8, x4, x1, x2)

inst_8972:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x1f and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfc00; op2val:0xfbff;
op3val:0x7c01; valaddr_reg:x3; val_offset:26916*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 26916*FLEN/8, x4, x1, x2)

inst_8973:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x1f and fm3 == 0x155 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfc00; op2val:0xfbff;
op3val:0xfd55; valaddr_reg:x3; val_offset:26919*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 26919*FLEN/8, x4, x1, x2)

inst_8974:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfc00; op2val:0xfbff;
op3val:0x3c00; valaddr_reg:x3; val_offset:26922*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 26922*FLEN/8, x4, x1, x2)

inst_8975:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfc00; op2val:0xfbff;
op3val:0xbc00; valaddr_reg:x3; val_offset:26925*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 26925*FLEN/8, x4, x1, x2)

inst_8976:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfc00; op2val:0x7c00;
op3val:0x0; valaddr_reg:x3; val_offset:26928*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 26928*FLEN/8, x4, x1, x2)

inst_8977:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfc00; op2val:0x7c00;
op3val:0x8000; valaddr_reg:x3; val_offset:26931*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 26931*FLEN/8, x4, x1, x2)

inst_8978:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfc00; op2val:0x7c00;
op3val:0x1; valaddr_reg:x3; val_offset:26934*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 26934*FLEN/8, x4, x1, x2)

inst_8979:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfc00; op2val:0x7c00;
op3val:0x8001; valaddr_reg:x3; val_offset:26937*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 26937*FLEN/8, x4, x1, x2)

inst_8980:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x002 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfc00; op2val:0x7c00;
op3val:0x2; valaddr_reg:x3; val_offset:26940*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 26940*FLEN/8, x4, x1, x2)

inst_8981:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3fe and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfc00; op2val:0x7c00;
op3val:0x83fe; valaddr_reg:x3; val_offset:26943*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 26943*FLEN/8, x4, x1, x2)

inst_8982:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfc00; op2val:0x7c00;
op3val:0x3ff; valaddr_reg:x3; val_offset:26946*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 26946*FLEN/8, x4, x1, x2)

inst_8983:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfc00; op2val:0x7c00;
op3val:0x83ff; valaddr_reg:x3; val_offset:26949*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 26949*FLEN/8, x4, x1, x2)

inst_8984:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfc00; op2val:0x7c00;
op3val:0x400; valaddr_reg:x3; val_offset:26952*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 26952*FLEN/8, x4, x1, x2)

inst_8985:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfc00; op2val:0x7c00;
op3val:0x8400; valaddr_reg:x3; val_offset:26955*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 26955*FLEN/8, x4, x1, x2)

inst_8986:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfc00; op2val:0x7c00;
op3val:0x401; valaddr_reg:x3; val_offset:26958*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 26958*FLEN/8, x4, x1, x2)

inst_8987:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfc00; op2val:0x7c00;
op3val:0x8455; valaddr_reg:x3; val_offset:26961*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 26961*FLEN/8, x4, x1, x2)

inst_8988:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfc00; op2val:0x7c00;
op3val:0x7bff; valaddr_reg:x3; val_offset:26964*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 26964*FLEN/8, x4, x1, x2)

inst_8989:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfc00; op2val:0x7c00;
op3val:0xfbff; valaddr_reg:x3; val_offset:26967*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 26967*FLEN/8, x4, x1, x2)

inst_8990:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfc00; op2val:0x7c00;
op3val:0x7c00; valaddr_reg:x3; val_offset:26970*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 26970*FLEN/8, x4, x1, x2)

inst_8991:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfc00; op2val:0x7c00;
op3val:0xfc00; valaddr_reg:x3; val_offset:26973*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 26973*FLEN/8, x4, x1, x2)

inst_8992:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfc00; op2val:0x7c00;
op3val:0x7e00; valaddr_reg:x3; val_offset:26976*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 26976*FLEN/8, x4, x1, x2)

inst_8993:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfc00; op2val:0x7c00;
op3val:0xfe00; valaddr_reg:x3; val_offset:26979*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 26979*FLEN/8, x4, x1, x2)

inst_8994:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x201 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfc00; op2val:0x7c00;
op3val:0x7e01; valaddr_reg:x3; val_offset:26982*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 26982*FLEN/8, x4, x1, x2)

inst_8995:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x255 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfc00; op2val:0x7c00;
op3val:0xfe55; valaddr_reg:x3; val_offset:26985*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 26985*FLEN/8, x4, x1, x2)

inst_8996:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfc00; op2val:0x7c00;
op3val:0x7c01; valaddr_reg:x3; val_offset:26988*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 26988*FLEN/8, x4, x1, x2)

inst_8997:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x155 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfc00; op2val:0x7c00;
op3val:0xfd55; valaddr_reg:x3; val_offset:26991*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 26991*FLEN/8, x4, x1, x2)

inst_8998:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfc00; op2val:0x7c00;
op3val:0x3c00; valaddr_reg:x3; val_offset:26994*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 26994*FLEN/8, x4, x1, x2)

inst_8999:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfc00; op2val:0x7c00;
op3val:0xbc00; valaddr_reg:x3; val_offset:26997*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 26997*FLEN/8, x4, x1, x2)

inst_9000:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfc00; op2val:0xfc00;
op3val:0x0; valaddr_reg:x3; val_offset:27000*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 27000*FLEN/8, x4, x1, x2)

inst_9001:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfc00; op2val:0xfc00;
op3val:0x8000; valaddr_reg:x3; val_offset:27003*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 27003*FLEN/8, x4, x1, x2)

inst_9002:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfc00; op2val:0xfc00;
op3val:0x1; valaddr_reg:x3; val_offset:27006*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 27006*FLEN/8, x4, x1, x2)

inst_9003:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfc00; op2val:0xfc00;
op3val:0x8001; valaddr_reg:x3; val_offset:27009*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 27009*FLEN/8, x4, x1, x2)

inst_9004:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x002 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfc00; op2val:0xfc00;
op3val:0x2; valaddr_reg:x3; val_offset:27012*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 27012*FLEN/8, x4, x1, x2)

inst_9005:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3fe and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfc00; op2val:0xfc00;
op3val:0x83fe; valaddr_reg:x3; val_offset:27015*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 27015*FLEN/8, x4, x1, x2)

inst_9006:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfc00; op2val:0xfc00;
op3val:0x3ff; valaddr_reg:x3; val_offset:27018*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 27018*FLEN/8, x4, x1, x2)

inst_9007:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfc00; op2val:0xfc00;
op3val:0x83ff; valaddr_reg:x3; val_offset:27021*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 27021*FLEN/8, x4, x1, x2)

inst_9008:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfc00; op2val:0xfc00;
op3val:0x400; valaddr_reg:x3; val_offset:27024*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 27024*FLEN/8, x4, x1, x2)

inst_9009:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfc00; op2val:0xfc00;
op3val:0x8400; valaddr_reg:x3; val_offset:27027*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 27027*FLEN/8, x4, x1, x2)

inst_9010:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfc00; op2val:0xfc00;
op3val:0x401; valaddr_reg:x3; val_offset:27030*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 27030*FLEN/8, x4, x1, x2)

inst_9011:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfc00; op2val:0xfc00;
op3val:0x8455; valaddr_reg:x3; val_offset:27033*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 27033*FLEN/8, x4, x1, x2)

inst_9012:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfc00; op2val:0xfc00;
op3val:0x7bff; valaddr_reg:x3; val_offset:27036*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 27036*FLEN/8, x4, x1, x2)

inst_9013:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfc00; op2val:0xfc00;
op3val:0xfbff; valaddr_reg:x3; val_offset:27039*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 27039*FLEN/8, x4, x1, x2)

inst_9014:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfc00; op2val:0xfc00;
op3val:0x7c00; valaddr_reg:x3; val_offset:27042*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 27042*FLEN/8, x4, x1, x2)

inst_9015:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfc00; op2val:0xfc00;
op3val:0xfc00; valaddr_reg:x3; val_offset:27045*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 27045*FLEN/8, x4, x1, x2)

inst_9016:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfc00; op2val:0xfc00;
op3val:0x7e00; valaddr_reg:x3; val_offset:27048*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 27048*FLEN/8, x4, x1, x2)

inst_9017:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfc00; op2val:0xfc00;
op3val:0xfe00; valaddr_reg:x3; val_offset:27051*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 27051*FLEN/8, x4, x1, x2)

inst_9018:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x201 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfc00; op2val:0xfc00;
op3val:0x7e01; valaddr_reg:x3; val_offset:27054*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 27054*FLEN/8, x4, x1, x2)

inst_9019:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x255 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfc00; op2val:0xfc00;
op3val:0xfe55; valaddr_reg:x3; val_offset:27057*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 27057*FLEN/8, x4, x1, x2)

inst_9020:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfc00; op2val:0xfc00;
op3val:0x7c01; valaddr_reg:x3; val_offset:27060*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 27060*FLEN/8, x4, x1, x2)

inst_9021:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x155 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfc00; op2val:0xfc00;
op3val:0xfd55; valaddr_reg:x3; val_offset:27063*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 27063*FLEN/8, x4, x1, x2)

inst_9022:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfc00; op2val:0xfc00;
op3val:0x3c00; valaddr_reg:x3; val_offset:27066*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 27066*FLEN/8, x4, x1, x2)

inst_9023:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfc00; op2val:0xfc00;
op3val:0xbc00; valaddr_reg:x3; val_offset:27069*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 27069*FLEN/8, x4, x1, x2)

inst_9024:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfc00; op2val:0x7e00;
op3val:0x0; valaddr_reg:x3; val_offset:27072*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 27072*FLEN/8, x4, x1, x2)

inst_9025:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfc00; op2val:0x7e00;
op3val:0x8000; valaddr_reg:x3; val_offset:27075*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 27075*FLEN/8, x4, x1, x2)

inst_9026:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfc00; op2val:0x7e00;
op3val:0x1; valaddr_reg:x3; val_offset:27078*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 27078*FLEN/8, x4, x1, x2)

inst_9027:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfc00; op2val:0x7e00;
op3val:0x8001; valaddr_reg:x3; val_offset:27081*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 27081*FLEN/8, x4, x1, x2)

inst_9028:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x002 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfc00; op2val:0x7e00;
op3val:0x2; valaddr_reg:x3; val_offset:27084*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 27084*FLEN/8, x4, x1, x2)

inst_9029:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3fe and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfc00; op2val:0x7e00;
op3val:0x83fe; valaddr_reg:x3; val_offset:27087*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 27087*FLEN/8, x4, x1, x2)

inst_9030:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfc00; op2val:0x7e00;
op3val:0x3ff; valaddr_reg:x3; val_offset:27090*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 27090*FLEN/8, x4, x1, x2)

inst_9031:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfc00; op2val:0x7e00;
op3val:0x83ff; valaddr_reg:x3; val_offset:27093*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 27093*FLEN/8, x4, x1, x2)

inst_9032:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfc00; op2val:0x7e00;
op3val:0x400; valaddr_reg:x3; val_offset:27096*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 27096*FLEN/8, x4, x1, x2)

inst_9033:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfc00; op2val:0x7e00;
op3val:0x8400; valaddr_reg:x3; val_offset:27099*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 27099*FLEN/8, x4, x1, x2)

inst_9034:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfc00; op2val:0x7e00;
op3val:0x401; valaddr_reg:x3; val_offset:27102*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 27102*FLEN/8, x4, x1, x2)

inst_9035:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfc00; op2val:0x7e00;
op3val:0x8455; valaddr_reg:x3; val_offset:27105*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 27105*FLEN/8, x4, x1, x2)

inst_9036:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfc00; op2val:0x7e00;
op3val:0x7bff; valaddr_reg:x3; val_offset:27108*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 27108*FLEN/8, x4, x1, x2)

inst_9037:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfc00; op2val:0x7e00;
op3val:0xfbff; valaddr_reg:x3; val_offset:27111*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 27111*FLEN/8, x4, x1, x2)

inst_9038:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfc00; op2val:0x7e00;
op3val:0x7c00; valaddr_reg:x3; val_offset:27114*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 27114*FLEN/8, x4, x1, x2)

inst_9039:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfc00; op2val:0x7e00;
op3val:0xfc00; valaddr_reg:x3; val_offset:27117*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 27117*FLEN/8, x4, x1, x2)

inst_9040:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfc00; op2val:0x7e00;
op3val:0x7e00; valaddr_reg:x3; val_offset:27120*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 27120*FLEN/8, x4, x1, x2)

inst_9041:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfc00; op2val:0x7e00;
op3val:0xfe00; valaddr_reg:x3; val_offset:27123*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 27123*FLEN/8, x4, x1, x2)

inst_9042:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x201 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfc00; op2val:0x7e00;
op3val:0x7e01; valaddr_reg:x3; val_offset:27126*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 27126*FLEN/8, x4, x1, x2)

inst_9043:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x255 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfc00; op2val:0x7e00;
op3val:0xfe55; valaddr_reg:x3; val_offset:27129*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 27129*FLEN/8, x4, x1, x2)

inst_9044:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfc00; op2val:0x7e00;
op3val:0x7c01; valaddr_reg:x3; val_offset:27132*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 27132*FLEN/8, x4, x1, x2)

inst_9045:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x155 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfc00; op2val:0x7e00;
op3val:0xfd55; valaddr_reg:x3; val_offset:27135*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 27135*FLEN/8, x4, x1, x2)

inst_9046:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 0 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfc00; op2val:0x7e00;
op3val:0x3c00; valaddr_reg:x3; val_offset:27138*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 27138*FLEN/8, x4, x1, x2)

inst_9047:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 1 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfc00; op2val:0x7e00;
op3val:0xbc00; valaddr_reg:x3; val_offset:27141*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 27141*FLEN/8, x4, x1, x2)

inst_9048:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfc00; op2val:0xfe00;
op3val:0x0; valaddr_reg:x3; val_offset:27144*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 27144*FLEN/8, x4, x1, x2)

inst_9049:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfc00; op2val:0xfe00;
op3val:0x8000; valaddr_reg:x3; val_offset:27147*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 27147*FLEN/8, x4, x1, x2)

inst_9050:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfc00; op2val:0xfe00;
op3val:0x1; valaddr_reg:x3; val_offset:27150*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 27150*FLEN/8, x4, x1, x2)

inst_9051:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfc00; op2val:0xfe00;
op3val:0x8001; valaddr_reg:x3; val_offset:27153*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 27153*FLEN/8, x4, x1, x2)

inst_9052:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x002 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfc00; op2val:0xfe00;
op3val:0x2; valaddr_reg:x3; val_offset:27156*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 27156*FLEN/8, x4, x1, x2)

inst_9053:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3fe and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfc00; op2val:0xfe00;
op3val:0x83fe; valaddr_reg:x3; val_offset:27159*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 27159*FLEN/8, x4, x1, x2)

inst_9054:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfc00; op2val:0xfe00;
op3val:0x3ff; valaddr_reg:x3; val_offset:27162*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 27162*FLEN/8, x4, x1, x2)

inst_9055:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfc00; op2val:0xfe00;
op3val:0x83ff; valaddr_reg:x3; val_offset:27165*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 27165*FLEN/8, x4, x1, x2)

inst_9056:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfc00; op2val:0xfe00;
op3val:0x400; valaddr_reg:x3; val_offset:27168*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 27168*FLEN/8, x4, x1, x2)

inst_9057:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfc00; op2val:0xfe00;
op3val:0x8400; valaddr_reg:x3; val_offset:27171*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 27171*FLEN/8, x4, x1, x2)

inst_9058:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfc00; op2val:0xfe00;
op3val:0x401; valaddr_reg:x3; val_offset:27174*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 27174*FLEN/8, x4, x1, x2)

inst_9059:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfc00; op2val:0xfe00;
op3val:0x8455; valaddr_reg:x3; val_offset:27177*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 27177*FLEN/8, x4, x1, x2)

inst_9060:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfc00; op2val:0xfe00;
op3val:0x7bff; valaddr_reg:x3; val_offset:27180*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 27180*FLEN/8, x4, x1, x2)

inst_9061:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfc00; op2val:0xfe00;
op3val:0xfbff; valaddr_reg:x3; val_offset:27183*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 27183*FLEN/8, x4, x1, x2)

inst_9062:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfc00; op2val:0xfe00;
op3val:0x7c00; valaddr_reg:x3; val_offset:27186*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 27186*FLEN/8, x4, x1, x2)

inst_9063:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfc00; op2val:0xfe00;
op3val:0xfc00; valaddr_reg:x3; val_offset:27189*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 27189*FLEN/8, x4, x1, x2)

inst_9064:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfc00; op2val:0xfe00;
op3val:0x7e00; valaddr_reg:x3; val_offset:27192*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 27192*FLEN/8, x4, x1, x2)

inst_9065:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfc00; op2val:0xfe00;
op3val:0xfe00; valaddr_reg:x3; val_offset:27195*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 27195*FLEN/8, x4, x1, x2)

inst_9066:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x201 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfc00; op2val:0xfe00;
op3val:0x7e01; valaddr_reg:x3; val_offset:27198*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 27198*FLEN/8, x4, x1, x2)

inst_9067:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x255 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfc00; op2val:0xfe00;
op3val:0xfe55; valaddr_reg:x3; val_offset:27201*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 27201*FLEN/8, x4, x1, x2)

inst_9068:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfc00; op2val:0xfe00;
op3val:0x7c01; valaddr_reg:x3; val_offset:27204*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 27204*FLEN/8, x4, x1, x2)

inst_9069:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x155 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfc00; op2val:0xfe00;
op3val:0xfd55; valaddr_reg:x3; val_offset:27207*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 27207*FLEN/8, x4, x1, x2)

inst_9070:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 0 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfc00; op2val:0xfe00;
op3val:0x3c00; valaddr_reg:x3; val_offset:27210*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 27210*FLEN/8, x4, x1, x2)

inst_9071:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 1 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfc00; op2val:0xfe00;
op3val:0xbc00; valaddr_reg:x3; val_offset:27213*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 27213*FLEN/8, x4, x1, x2)

inst_9072:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfc00; op2val:0x7e01;
op3val:0x0; valaddr_reg:x3; val_offset:27216*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 27216*FLEN/8, x4, x1, x2)

inst_9073:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfc00; op2val:0x7e01;
op3val:0x8000; valaddr_reg:x3; val_offset:27219*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 27219*FLEN/8, x4, x1, x2)

inst_9074:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfc00; op2val:0x7e01;
op3val:0x1; valaddr_reg:x3; val_offset:27222*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 27222*FLEN/8, x4, x1, x2)

inst_9075:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfc00; op2val:0x7e01;
op3val:0x8001; valaddr_reg:x3; val_offset:27225*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 27225*FLEN/8, x4, x1, x2)

inst_9076:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x002 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfc00; op2val:0x7e01;
op3val:0x2; valaddr_reg:x3; val_offset:27228*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 27228*FLEN/8, x4, x1, x2)

inst_9077:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3fe and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfc00; op2val:0x7e01;
op3val:0x83fe; valaddr_reg:x3; val_offset:27231*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 27231*FLEN/8, x4, x1, x2)

inst_9078:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfc00; op2val:0x7e01;
op3val:0x3ff; valaddr_reg:x3; val_offset:27234*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 27234*FLEN/8, x4, x1, x2)

inst_9079:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfc00; op2val:0x7e01;
op3val:0x83ff; valaddr_reg:x3; val_offset:27237*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 27237*FLEN/8, x4, x1, x2)

inst_9080:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfc00; op2val:0x7e01;
op3val:0x400; valaddr_reg:x3; val_offset:27240*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 27240*FLEN/8, x4, x1, x2)

inst_9081:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfc00; op2val:0x7e01;
op3val:0x8400; valaddr_reg:x3; val_offset:27243*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 27243*FLEN/8, x4, x1, x2)

inst_9082:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfc00; op2val:0x7e01;
op3val:0x401; valaddr_reg:x3; val_offset:27246*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 27246*FLEN/8, x4, x1, x2)

inst_9083:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfc00; op2val:0x7e01;
op3val:0x8455; valaddr_reg:x3; val_offset:27249*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 27249*FLEN/8, x4, x1, x2)

inst_9084:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfc00; op2val:0x7e01;
op3val:0x7bff; valaddr_reg:x3; val_offset:27252*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 27252*FLEN/8, x4, x1, x2)

inst_9085:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfc00; op2val:0x7e01;
op3val:0xfbff; valaddr_reg:x3; val_offset:27255*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 27255*FLEN/8, x4, x1, x2)

inst_9086:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfc00; op2val:0x7e01;
op3val:0x7c00; valaddr_reg:x3; val_offset:27258*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 27258*FLEN/8, x4, x1, x2)

inst_9087:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfc00; op2val:0x7e01;
op3val:0xfc00; valaddr_reg:x3; val_offset:27261*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 27261*FLEN/8, x4, x1, x2)

RVTEST_SIGBASE(x1,signature_x1_72)
inst_9088:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfc00; op2val:0x7e01;
op3val:0x7e00; valaddr_reg:x3; val_offset:27264*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 27264*FLEN/8, x4, x1, x2)

inst_9089:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfc00; op2val:0x7e01;
op3val:0xfe00; valaddr_reg:x3; val_offset:27267*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 27267*FLEN/8, x4, x1, x2)

inst_9090:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x201 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfc00; op2val:0x7e01;
op3val:0x7e01; valaddr_reg:x3; val_offset:27270*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 27270*FLEN/8, x4, x1, x2)

inst_9091:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x255 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfc00; op2val:0x7e01;
op3val:0xfe55; valaddr_reg:x3; val_offset:27273*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 27273*FLEN/8, x4, x1, x2)

inst_9092:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfc00; op2val:0x7e01;
op3val:0x7c01; valaddr_reg:x3; val_offset:27276*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 27276*FLEN/8, x4, x1, x2)

inst_9093:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x155 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfc00; op2val:0x7e01;
op3val:0xfd55; valaddr_reg:x3; val_offset:27279*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 27279*FLEN/8, x4, x1, x2)

inst_9094:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fs3 == 0 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfc00; op2val:0x7e01;
op3val:0x3c00; valaddr_reg:x3; val_offset:27282*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 27282*FLEN/8, x4, x1, x2)

inst_9095:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fs3 == 1 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfc00; op2val:0x7e01;
op3val:0xbc00; valaddr_reg:x3; val_offset:27285*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 27285*FLEN/8, x4, x1, x2)

inst_9096:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfc00; op2val:0xfe55;
op3val:0x0; valaddr_reg:x3; val_offset:27288*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 27288*FLEN/8, x4, x1, x2)

inst_9097:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfc00; op2val:0xfe55;
op3val:0x8000; valaddr_reg:x3; val_offset:27291*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 27291*FLEN/8, x4, x1, x2)

inst_9098:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfc00; op2val:0xfe55;
op3val:0x1; valaddr_reg:x3; val_offset:27294*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 27294*FLEN/8, x4, x1, x2)

inst_9099:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfc00; op2val:0xfe55;
op3val:0x8001; valaddr_reg:x3; val_offset:27297*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 27297*FLEN/8, x4, x1, x2)

inst_9100:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x002 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfc00; op2val:0xfe55;
op3val:0x2; valaddr_reg:x3; val_offset:27300*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 27300*FLEN/8, x4, x1, x2)

inst_9101:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3fe and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfc00; op2val:0xfe55;
op3val:0x83fe; valaddr_reg:x3; val_offset:27303*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 27303*FLEN/8, x4, x1, x2)

inst_9102:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfc00; op2val:0xfe55;
op3val:0x3ff; valaddr_reg:x3; val_offset:27306*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 27306*FLEN/8, x4, x1, x2)

inst_9103:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfc00; op2val:0xfe55;
op3val:0x83ff; valaddr_reg:x3; val_offset:27309*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 27309*FLEN/8, x4, x1, x2)

inst_9104:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfc00; op2val:0xfe55;
op3val:0x400; valaddr_reg:x3; val_offset:27312*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 27312*FLEN/8, x4, x1, x2)

inst_9105:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfc00; op2val:0xfe55;
op3val:0x8400; valaddr_reg:x3; val_offset:27315*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 27315*FLEN/8, x4, x1, x2)

inst_9106:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfc00; op2val:0xfe55;
op3val:0x401; valaddr_reg:x3; val_offset:27318*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 27318*FLEN/8, x4, x1, x2)

inst_9107:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfc00; op2val:0xfe55;
op3val:0x8455; valaddr_reg:x3; val_offset:27321*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 27321*FLEN/8, x4, x1, x2)

inst_9108:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfc00; op2val:0xfe55;
op3val:0x7bff; valaddr_reg:x3; val_offset:27324*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 27324*FLEN/8, x4, x1, x2)

inst_9109:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfc00; op2val:0xfe55;
op3val:0xfbff; valaddr_reg:x3; val_offset:27327*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 27327*FLEN/8, x4, x1, x2)

inst_9110:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfc00; op2val:0xfe55;
op3val:0x7c00; valaddr_reg:x3; val_offset:27330*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 27330*FLEN/8, x4, x1, x2)

inst_9111:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfc00; op2val:0xfe55;
op3val:0xfc00; valaddr_reg:x3; val_offset:27333*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 27333*FLEN/8, x4, x1, x2)

inst_9112:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfc00; op2val:0xfe55;
op3val:0x7e00; valaddr_reg:x3; val_offset:27336*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 27336*FLEN/8, x4, x1, x2)

inst_9113:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfc00; op2val:0xfe55;
op3val:0xfe00; valaddr_reg:x3; val_offset:27339*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 27339*FLEN/8, x4, x1, x2)

inst_9114:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x201 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfc00; op2val:0xfe55;
op3val:0x7e01; valaddr_reg:x3; val_offset:27342*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 27342*FLEN/8, x4, x1, x2)

inst_9115:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x255 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfc00; op2val:0xfe55;
op3val:0xfe55; valaddr_reg:x3; val_offset:27345*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 27345*FLEN/8, x4, x1, x2)

inst_9116:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfc00; op2val:0xfe55;
op3val:0x7c01; valaddr_reg:x3; val_offset:27348*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 27348*FLEN/8, x4, x1, x2)

inst_9117:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x155 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfc00; op2val:0xfe55;
op3val:0xfd55; valaddr_reg:x3; val_offset:27351*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 27351*FLEN/8, x4, x1, x2)

inst_9118:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fs3 == 0 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfc00; op2val:0xfe55;
op3val:0x3c00; valaddr_reg:x3; val_offset:27354*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 27354*FLEN/8, x4, x1, x2)

inst_9119:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fs3 == 1 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfc00; op2val:0xfe55;
op3val:0xbc00; valaddr_reg:x3; val_offset:27357*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 27357*FLEN/8, x4, x1, x2)

inst_9120:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfc00; op2val:0x7c01;
op3val:0x0; valaddr_reg:x3; val_offset:27360*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 27360*FLEN/8, x4, x1, x2)

inst_9121:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfc00; op2val:0x7c01;
op3val:0x8000; valaddr_reg:x3; val_offset:27363*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 27363*FLEN/8, x4, x1, x2)

inst_9122:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfc00; op2val:0x7c01;
op3val:0x1; valaddr_reg:x3; val_offset:27366*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 27366*FLEN/8, x4, x1, x2)

inst_9123:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfc00; op2val:0x7c01;
op3val:0x8001; valaddr_reg:x3; val_offset:27369*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 27369*FLEN/8, x4, x1, x2)

inst_9124:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x002 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfc00; op2val:0x7c01;
op3val:0x2; valaddr_reg:x3; val_offset:27372*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 27372*FLEN/8, x4, x1, x2)

inst_9125:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3fe and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfc00; op2val:0x7c01;
op3val:0x83fe; valaddr_reg:x3; val_offset:27375*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 27375*FLEN/8, x4, x1, x2)

inst_9126:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfc00; op2val:0x7c01;
op3val:0x3ff; valaddr_reg:x3; val_offset:27378*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 27378*FLEN/8, x4, x1, x2)

inst_9127:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfc00; op2val:0x7c01;
op3val:0x83ff; valaddr_reg:x3; val_offset:27381*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 27381*FLEN/8, x4, x1, x2)

inst_9128:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfc00; op2val:0x7c01;
op3val:0x400; valaddr_reg:x3; val_offset:27384*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 27384*FLEN/8, x4, x1, x2)

inst_9129:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfc00; op2val:0x7c01;
op3val:0x8400; valaddr_reg:x3; val_offset:27387*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 27387*FLEN/8, x4, x1, x2)

inst_9130:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfc00; op2val:0x7c01;
op3val:0x401; valaddr_reg:x3; val_offset:27390*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 27390*FLEN/8, x4, x1, x2)

inst_9131:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfc00; op2val:0x7c01;
op3val:0x8455; valaddr_reg:x3; val_offset:27393*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 27393*FLEN/8, x4, x1, x2)

inst_9132:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfc00; op2val:0x7c01;
op3val:0x7bff; valaddr_reg:x3; val_offset:27396*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 27396*FLEN/8, x4, x1, x2)

inst_9133:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfc00; op2val:0x7c01;
op3val:0xfbff; valaddr_reg:x3; val_offset:27399*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 27399*FLEN/8, x4, x1, x2)

inst_9134:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfc00; op2val:0x7c01;
op3val:0x7c00; valaddr_reg:x3; val_offset:27402*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 27402*FLEN/8, x4, x1, x2)

inst_9135:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfc00; op2val:0x7c01;
op3val:0xfc00; valaddr_reg:x3; val_offset:27405*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 27405*FLEN/8, x4, x1, x2)

inst_9136:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfc00; op2val:0x7c01;
op3val:0x7e00; valaddr_reg:x3; val_offset:27408*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 27408*FLEN/8, x4, x1, x2)

inst_9137:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfc00; op2val:0x7c01;
op3val:0xfe00; valaddr_reg:x3; val_offset:27411*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 27411*FLEN/8, x4, x1, x2)

inst_9138:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x201 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfc00; op2val:0x7c01;
op3val:0x7e01; valaddr_reg:x3; val_offset:27414*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 27414*FLEN/8, x4, x1, x2)

inst_9139:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x255 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfc00; op2val:0x7c01;
op3val:0xfe55; valaddr_reg:x3; val_offset:27417*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 27417*FLEN/8, x4, x1, x2)

inst_9140:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfc00; op2val:0x7c01;
op3val:0x7c01; valaddr_reg:x3; val_offset:27420*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 27420*FLEN/8, x4, x1, x2)

inst_9141:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x155 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfc00; op2val:0x7c01;
op3val:0xfd55; valaddr_reg:x3; val_offset:27423*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 27423*FLEN/8, x4, x1, x2)

inst_9142:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fs3 == 0 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfc00; op2val:0x7c01;
op3val:0x3c00; valaddr_reg:x3; val_offset:27426*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 27426*FLEN/8, x4, x1, x2)

inst_9143:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fs3 == 1 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfc00; op2val:0x7c01;
op3val:0xbc00; valaddr_reg:x3; val_offset:27429*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 27429*FLEN/8, x4, x1, x2)

inst_9144:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfc00; op2val:0xfd55;
op3val:0x0; valaddr_reg:x3; val_offset:27432*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 27432*FLEN/8, x4, x1, x2)

inst_9145:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfc00; op2val:0xfd55;
op3val:0x8000; valaddr_reg:x3; val_offset:27435*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 27435*FLEN/8, x4, x1, x2)

inst_9146:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfc00; op2val:0xfd55;
op3val:0x1; valaddr_reg:x3; val_offset:27438*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 27438*FLEN/8, x4, x1, x2)

inst_9147:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfc00; op2val:0xfd55;
op3val:0x8001; valaddr_reg:x3; val_offset:27441*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 27441*FLEN/8, x4, x1, x2)

inst_9148:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x002 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfc00; op2val:0xfd55;
op3val:0x2; valaddr_reg:x3; val_offset:27444*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 27444*FLEN/8, x4, x1, x2)

inst_9149:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3fe and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfc00; op2val:0xfd55;
op3val:0x83fe; valaddr_reg:x3; val_offset:27447*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 27447*FLEN/8, x4, x1, x2)

inst_9150:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfc00; op2val:0xfd55;
op3val:0x3ff; valaddr_reg:x3; val_offset:27450*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 27450*FLEN/8, x4, x1, x2)

inst_9151:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfc00; op2val:0xfd55;
op3val:0x83ff; valaddr_reg:x3; val_offset:27453*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 27453*FLEN/8, x4, x1, x2)

inst_9152:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfc00; op2val:0xfd55;
op3val:0x400; valaddr_reg:x3; val_offset:27456*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 27456*FLEN/8, x4, x1, x2)

inst_9153:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfc00; op2val:0xfd55;
op3val:0x8400; valaddr_reg:x3; val_offset:27459*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 27459*FLEN/8, x4, x1, x2)

inst_9154:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfc00; op2val:0xfd55;
op3val:0x401; valaddr_reg:x3; val_offset:27462*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 27462*FLEN/8, x4, x1, x2)

inst_9155:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfc00; op2val:0xfd55;
op3val:0x8455; valaddr_reg:x3; val_offset:27465*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 27465*FLEN/8, x4, x1, x2)

inst_9156:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfc00; op2val:0xfd55;
op3val:0x7bff; valaddr_reg:x3; val_offset:27468*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 27468*FLEN/8, x4, x1, x2)

inst_9157:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfc00; op2val:0xfd55;
op3val:0xfbff; valaddr_reg:x3; val_offset:27471*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 27471*FLEN/8, x4, x1, x2)

inst_9158:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfc00; op2val:0xfd55;
op3val:0x7c00; valaddr_reg:x3; val_offset:27474*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 27474*FLEN/8, x4, x1, x2)

inst_9159:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfc00; op2val:0xfd55;
op3val:0xfc00; valaddr_reg:x3; val_offset:27477*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 27477*FLEN/8, x4, x1, x2)

inst_9160:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfc00; op2val:0xfd55;
op3val:0x7e00; valaddr_reg:x3; val_offset:27480*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 27480*FLEN/8, x4, x1, x2)

inst_9161:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfc00; op2val:0xfd55;
op3val:0xfe00; valaddr_reg:x3; val_offset:27483*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 27483*FLEN/8, x4, x1, x2)

inst_9162:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x201 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfc00; op2val:0xfd55;
op3val:0x7e01; valaddr_reg:x3; val_offset:27486*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 27486*FLEN/8, x4, x1, x2)

#endif
RVTEST_CODE_END
RVMODEL_HALT
RVTEST_DATA_BEGIN
.align 4
rvtest_data:
.word 0xbabecafe
.word 0xabecafeb
.word 0xbecafeba
.word 0xecafebab
test_dataset_0:
NAN_BOXED(64512,16,FLEN)
NAN_BOXED(31745,16,FLEN)
NAN_BOXED(31744,16,FLEN)
NAN_BOXED(64512,16,FLEN)
NAN_BOXED(64853,16,FLEN)
NAN_BOXED(31744,16,FLEN)
NAN_BOXED(64512,16,FLEN)
NAN_BOXED(15360,16,FLEN)
NAN_BOXED(31744,16,FLEN)
NAN_BOXED(64512,16,FLEN)
NAN_BOXED(48128,16,FLEN)
NAN_BOXED(31744,16,FLEN)
NAN_BOXED(32256,16,FLEN)
NAN_BOXED(0,16,FLEN)
NAN_BOXED(31744,16,FLEN)
NAN_BOXED(32256,16,FLEN)
NAN_BOXED(32768,16,FLEN)
NAN_BOXED(31744,16,FLEN)
NAN_BOXED(32256,16,FLEN)
NAN_BOXED(1,16,FLEN)
NAN_BOXED(31744,16,FLEN)
NAN_BOXED(32256,16,FLEN)
NAN_BOXED(32769,16,FLEN)
NAN_BOXED(31744,16,FLEN)
NAN_BOXED(32256,16,FLEN)
NAN_BOXED(2,16,FLEN)
NAN_BOXED(31744,16,FLEN)
NAN_BOXED(32256,16,FLEN)
NAN_BOXED(33790,16,FLEN)
NAN_BOXED(31744,16,FLEN)
NAN_BOXED(32256,16,FLEN)
NAN_BOXED(1023,16,FLEN)
NAN_BOXED(31744,16,FLEN)
NAN_BOXED(32256,16,FLEN)
NAN_BOXED(33791,16,FLEN)
NAN_BOXED(31744,16,FLEN)
NAN_BOXED(32256,16,FLEN)
NAN_BOXED(1024,16,FLEN)
NAN_BOXED(31744,16,FLEN)
NAN_BOXED(32256,16,FLEN)
NAN_BOXED(33792,16,FLEN)
NAN_BOXED(31744,16,FLEN)
NAN_BOXED(32256,16,FLEN)
NAN_BOXED(1025,16,FLEN)
NAN_BOXED(31744,16,FLEN)
NAN_BOXED(32256,16,FLEN)
NAN_BOXED(33877,16,FLEN)
NAN_BOXED(31744,16,FLEN)
NAN_BOXED(32256,16,FLEN)
NAN_BOXED(31743,16,FLEN)
NAN_BOXED(31744,16,FLEN)
NAN_BOXED(32256,16,FLEN)
NAN_BOXED(64511,16,FLEN)
NAN_BOXED(31744,16,FLEN)
NAN_BOXED(32256,16,FLEN)
NAN_BOXED(31744,16,FLEN)
NAN_BOXED(31744,16,FLEN)
NAN_BOXED(32256,16,FLEN)
NAN_BOXED(64512,16,FLEN)
NAN_BOXED(31744,16,FLEN)
NAN_BOXED(32256,16,FLEN)
NAN_BOXED(32256,16,FLEN)
NAN_BOXED(31744,16,FLEN)
NAN_BOXED(32256,16,FLEN)
NAN_BOXED(65024,16,FLEN)
NAN_BOXED(31744,16,FLEN)
NAN_BOXED(32256,16,FLEN)
NAN_BOXED(32257,16,FLEN)
NAN_BOXED(31744,16,FLEN)
NAN_BOXED(32256,16,FLEN)
NAN_BOXED(65109,16,FLEN)
NAN_BOXED(31744,16,FLEN)
NAN_BOXED(32256,16,FLEN)
NAN_BOXED(31745,16,FLEN)
NAN_BOXED(31744,16,FLEN)
NAN_BOXED(32256,16,FLEN)
NAN_BOXED(64853,16,FLEN)
NAN_BOXED(31744,16,FLEN)
NAN_BOXED(32256,16,FLEN)
NAN_BOXED(15360,16,FLEN)
NAN_BOXED(31744,16,FLEN)
NAN_BOXED(32256,16,FLEN)
NAN_BOXED(48128,16,FLEN)
NAN_BOXED(31744,16,FLEN)
NAN_BOXED(65024,16,FLEN)
NAN_BOXED(0,16,FLEN)
NAN_BOXED(31744,16,FLEN)
NAN_BOXED(65024,16,FLEN)
NAN_BOXED(32768,16,FLEN)
NAN_BOXED(31744,16,FLEN)
NAN_BOXED(65024,16,FLEN)
NAN_BOXED(1,16,FLEN)
NAN_BOXED(31744,16,FLEN)
NAN_BOXED(65024,16,FLEN)
NAN_BOXED(32769,16,FLEN)
NAN_BOXED(31744,16,FLEN)
NAN_BOXED(65024,16,FLEN)
NAN_BOXED(2,16,FLEN)
NAN_BOXED(31744,16,FLEN)
NAN_BOXED(65024,16,FLEN)
NAN_BOXED(33790,16,FLEN)
NAN_BOXED(31744,16,FLEN)
NAN_BOXED(65024,16,FLEN)
NAN_BOXED(1023,16,FLEN)
NAN_BOXED(31744,16,FLEN)
NAN_BOXED(65024,16,FLEN)
NAN_BOXED(33791,16,FLEN)
NAN_BOXED(31744,16,FLEN)
NAN_BOXED(65024,16,FLEN)
NAN_BOXED(1024,16,FLEN)
NAN_BOXED(31744,16,FLEN)
NAN_BOXED(65024,16,FLEN)
NAN_BOXED(33792,16,FLEN)
NAN_BOXED(31744,16,FLEN)
NAN_BOXED(65024,16,FLEN)
NAN_BOXED(1025,16,FLEN)
NAN_BOXED(31744,16,FLEN)
NAN_BOXED(65024,16,FLEN)
NAN_BOXED(33877,16,FLEN)
NAN_BOXED(31744,16,FLEN)
NAN_BOXED(65024,16,FLEN)
NAN_BOXED(31743,16,FLEN)
NAN_BOXED(31744,16,FLEN)
NAN_BOXED(65024,16,FLEN)
NAN_BOXED(64511,16,FLEN)
NAN_BOXED(31744,16,FLEN)
NAN_BOXED(65024,16,FLEN)
NAN_BOXED(31744,16,FLEN)
NAN_BOXED(31744,16,FLEN)
NAN_BOXED(65024,16,FLEN)
NAN_BOXED(64512,16,FLEN)
NAN_BOXED(31744,16,FLEN)
NAN_BOXED(65024,16,FLEN)
NAN_BOXED(32256,16,FLEN)
NAN_BOXED(31744,16,FLEN)
NAN_BOXED(65024,16,FLEN)
NAN_BOXED(65024,16,FLEN)
NAN_BOXED(31744,16,FLEN)
NAN_BOXED(65024,16,FLEN)
NAN_BOXED(32257,16,FLEN)
NAN_BOXED(31744,16,FLEN)
NAN_BOXED(65024,16,FLEN)
NAN_BOXED(65109,16,FLEN)
NAN_BOXED(31744,16,FLEN)
NAN_BOXED(65024,16,FLEN)
NAN_BOXED(31745,16,FLEN)
NAN_BOXED(31744,16,FLEN)
NAN_BOXED(65024,16,FLEN)
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NAN_BOXED(1024,16,FLEN)
NAN_BOXED(64512,16,FLEN)
NAN_BOXED(15360,16,FLEN)
NAN_BOXED(33792,16,FLEN)
NAN_BOXED(64512,16,FLEN)
NAN_BOXED(15360,16,FLEN)
NAN_BOXED(1025,16,FLEN)
NAN_BOXED(64512,16,FLEN)
NAN_BOXED(15360,16,FLEN)
NAN_BOXED(33877,16,FLEN)
NAN_BOXED(64512,16,FLEN)
NAN_BOXED(15360,16,FLEN)
NAN_BOXED(31743,16,FLEN)
NAN_BOXED(64512,16,FLEN)
NAN_BOXED(15360,16,FLEN)
NAN_BOXED(64511,16,FLEN)
NAN_BOXED(64512,16,FLEN)
NAN_BOXED(15360,16,FLEN)
NAN_BOXED(31744,16,FLEN)
NAN_BOXED(64512,16,FLEN)
NAN_BOXED(15360,16,FLEN)
NAN_BOXED(64512,16,FLEN)
NAN_BOXED(64512,16,FLEN)
NAN_BOXED(15360,16,FLEN)
NAN_BOXED(32256,16,FLEN)
NAN_BOXED(64512,16,FLEN)
NAN_BOXED(15360,16,FLEN)
NAN_BOXED(65024,16,FLEN)
NAN_BOXED(64512,16,FLEN)
NAN_BOXED(15360,16,FLEN)
NAN_BOXED(32257,16,FLEN)
NAN_BOXED(64512,16,FLEN)
NAN_BOXED(15360,16,FLEN)
NAN_BOXED(65109,16,FLEN)
NAN_BOXED(64512,16,FLEN)
NAN_BOXED(15360,16,FLEN)
NAN_BOXED(31745,16,FLEN)
NAN_BOXED(64512,16,FLEN)
NAN_BOXED(15360,16,FLEN)
NAN_BOXED(64853,16,FLEN)
NAN_BOXED(64512,16,FLEN)
NAN_BOXED(15360,16,FLEN)
NAN_BOXED(15360,16,FLEN)
NAN_BOXED(64512,16,FLEN)
NAN_BOXED(15360,16,FLEN)
NAN_BOXED(48128,16,FLEN)
NAN_BOXED(64512,16,FLEN)
NAN_BOXED(48128,16,FLEN)
NAN_BOXED(0,16,FLEN)
NAN_BOXED(64512,16,FLEN)
NAN_BOXED(48128,16,FLEN)
NAN_BOXED(32768,16,FLEN)
NAN_BOXED(64512,16,FLEN)
NAN_BOXED(48128,16,FLEN)
NAN_BOXED(1,16,FLEN)
NAN_BOXED(64512,16,FLEN)
NAN_BOXED(48128,16,FLEN)
NAN_BOXED(32769,16,FLEN)
NAN_BOXED(64512,16,FLEN)
NAN_BOXED(48128,16,FLEN)
NAN_BOXED(2,16,FLEN)
NAN_BOXED(64512,16,FLEN)
NAN_BOXED(48128,16,FLEN)
NAN_BOXED(33790,16,FLEN)
NAN_BOXED(64512,16,FLEN)
NAN_BOXED(48128,16,FLEN)
NAN_BOXED(1023,16,FLEN)
NAN_BOXED(64512,16,FLEN)
NAN_BOXED(48128,16,FLEN)
NAN_BOXED(33791,16,FLEN)
NAN_BOXED(64512,16,FLEN)
NAN_BOXED(48128,16,FLEN)
NAN_BOXED(1024,16,FLEN)
NAN_BOXED(64512,16,FLEN)
NAN_BOXED(48128,16,FLEN)
NAN_BOXED(33792,16,FLEN)
NAN_BOXED(64512,16,FLEN)
NAN_BOXED(48128,16,FLEN)
NAN_BOXED(1025,16,FLEN)
NAN_BOXED(64512,16,FLEN)
NAN_BOXED(48128,16,FLEN)
NAN_BOXED(33877,16,FLEN)
NAN_BOXED(64512,16,FLEN)
NAN_BOXED(48128,16,FLEN)
NAN_BOXED(31743,16,FLEN)
NAN_BOXED(64512,16,FLEN)
NAN_BOXED(48128,16,FLEN)
NAN_BOXED(64511,16,FLEN)
NAN_BOXED(64512,16,FLEN)
NAN_BOXED(48128,16,FLEN)
NAN_BOXED(31744,16,FLEN)
NAN_BOXED(64512,16,FLEN)
NAN_BOXED(48128,16,FLEN)
NAN_BOXED(64512,16,FLEN)
NAN_BOXED(64512,16,FLEN)
NAN_BOXED(48128,16,FLEN)
NAN_BOXED(32256,16,FLEN)
NAN_BOXED(64512,16,FLEN)
NAN_BOXED(48128,16,FLEN)
NAN_BOXED(65024,16,FLEN)
NAN_BOXED(64512,16,FLEN)
NAN_BOXED(48128,16,FLEN)
NAN_BOXED(32257,16,FLEN)
NAN_BOXED(64512,16,FLEN)
NAN_BOXED(48128,16,FLEN)
NAN_BOXED(65109,16,FLEN)
NAN_BOXED(64512,16,FLEN)
RVTEST_DATA_END

RVMODEL_DATA_BEGIN
rvtest_sig_begin:
sig_begin_canary:
CANARY;



signature_x1_0:
    .fill 0*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_1:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_2:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_3:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_4:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_5:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_6:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_7:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_8:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_9:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_10:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_11:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_12:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_13:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_14:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_15:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_16:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_17:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_18:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_19:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_20:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_21:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_22:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_23:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_24:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_25:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_26:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_27:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_28:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_29:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_30:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_31:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_32:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_33:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_34:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_35:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_36:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_37:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_38:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_39:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_40:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_41:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_42:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_43:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_44:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_45:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_46:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_47:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_48:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_49:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_50:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_51:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_52:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_53:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_54:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_55:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_56:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_57:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_58:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_59:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_60:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_61:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_62:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_63:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_64:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_65:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_66:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_67:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_68:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_69:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_70:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_71:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_72:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_73:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_74:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_75:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_76:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_77:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_78:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_79:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_80:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_81:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_82:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_83:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_84:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_85:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_86:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_87:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_88:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_89:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_90:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_91:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_92:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_93:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_94:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_95:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_96:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_97:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_98:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_99:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_100:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_101:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_102:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_103:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_104:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_105:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_106:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_107:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_108:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_109:
    .fill 14*((SIGALIGN)/4),4,0xdeadbeef

#ifdef rvtest_mtrap_routine
tsig_begin_canary:
CANARY;

mtrap_sigptr:
    .fill 64*XLEN/32,4,0xdeadbeef

tsig_end_canary:
CANARY;
#endif

#ifdef rvtest_gpr_save

gpr_save:
    .fill 32*XLEN/32,4,0xdeadbeef

#endif


sig_end_canary:
CANARY;
rvtest_sig_end:
RVMODEL_DATA_END
