
// -----------
// This file was generated by riscv_ctg (https://github.com/riscv-software-src/riscv-ctg)
// version   : 0.7.1
// timestamp : Fri Jun 17 14:17:59 2022 GMT
// usage     : riscv_ctg \
//                  -- cgf //                  --cgf /scratch/pawan/work/normalised/RV32F/fmadd.s.cgf \
 \
//                  -- xlen 32  \
//                  --randomize \
// -----------
//
// -----------
// Copyright (c) 2020. RISC-V International. All rights reserved.
// SPDX-License-Identifier: BSD-3-Clause
// -----------
//
// This assembly file tests the fmadd.s instruction of the RISC-V RV32F_Zicsr,RV32FD_Zicsr,RV64F_Zicsr,RV64FD_Zicsr extension for the fmadd_b15 covergroup.
// 
#include "model_test.h"
#include "arch_test.h"
RVTEST_ISA("RV32IF_Zicsr,RV32IFD_Zicsr,RV64IF_Zicsr,RV64IFD_Zicsr,RV32EF_Zicsr,RV32EFD_Zicsr,RV64EF_Zicsr,RV64EFD_Zicsr")

.section .text.init
.globl rvtest_entry_point
rvtest_entry_point:
RVMODEL_BOOT
RVTEST_CODE_BEGIN

#ifdef TEST_CASE_1

RVTEST_CASE(0,"//check ISA:=regex(.*I.*F.*);def TEST_CASE_1=True;",fmadd_b15)
RVTEST_CASE(1,"//check ISA:=regex(.*E.*F.*);def TEST_CASE_1=True;",fmadd_b15)
RVTEST_FP_ENABLE()
RVTEST_VALBASEUPD(x3,test_dataset_0)
RVTEST_SIGBASE(x1,signature_x1_1)

inst_32256:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x20dec0 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x32ec4e and fs3 == 0 and fe3 == 0x47 and fm3 == 0x00ffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f20dec0; op2val:0x32ec4e;
op3val:0x2380ffff; valaddr_reg:x3; val_offset:96768*0 + 3*-1*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 96768*0 + 3*0*FLEN/8, x4, x1, x2)

inst_32257:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x20dec0 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x32ec4e and fs3 == 0 and fe3 == 0x47 and fm3 == 0x01ffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f20dec0; op2val:0x32ec4e;
op3val:0x2381ffff; valaddr_reg:x3; val_offset:96771*0 + 3*0*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 96771*0 + 3*1*FLEN/8, x4, x1, x2)

inst_32258:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x20dec0 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x32ec4e and fs3 == 0 and fe3 == 0x47 and fm3 == 0x03ffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f20dec0; op2val:0x32ec4e;
op3val:0x2383ffff; valaddr_reg:x3; val_offset:96774*0 + 3*1*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 96774*0 + 3*2*FLEN/8, x4, x1, x2)

inst_32259:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x20dec0 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x32ec4e and fs3 == 0 and fe3 == 0x47 and fm3 == 0x07ffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f20dec0; op2val:0x32ec4e;
op3val:0x2387ffff; valaddr_reg:x3; val_offset:96777*0 + 3*2*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 96777*0 + 3*3*FLEN/8, x4, x1, x2)

inst_32260:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x20dec0 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x32ec4e and fs3 == 0 and fe3 == 0x47 and fm3 == 0x0fffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f20dec0; op2val:0x32ec4e;
op3val:0x238fffff; valaddr_reg:x3; val_offset:96780*0 + 3*3*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 96780*0 + 3*4*FLEN/8, x4, x1, x2)

inst_32261:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x20dec0 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x32ec4e and fs3 == 0 and fe3 == 0x47 and fm3 == 0x1fffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f20dec0; op2val:0x32ec4e;
op3val:0x239fffff; valaddr_reg:x3; val_offset:96783*0 + 3*4*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 96783*0 + 3*5*FLEN/8, x4, x1, x2)

inst_32262:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x20dec0 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x32ec4e and fs3 == 0 and fe3 == 0x47 and fm3 == 0x3fffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f20dec0; op2val:0x32ec4e;
op3val:0x23bfffff; valaddr_reg:x3; val_offset:96786*0 + 3*5*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 96786*0 + 3*6*FLEN/8, x4, x1, x2)

inst_32263:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x20dec0 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x32ec4e and fs3 == 0 and fe3 == 0x47 and fm3 == 0x400000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f20dec0; op2val:0x32ec4e;
op3val:0x23c00000; valaddr_reg:x3; val_offset:96789*0 + 3*6*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 96789*0 + 3*7*FLEN/8, x4, x1, x2)

inst_32264:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x20dec0 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x32ec4e and fs3 == 0 and fe3 == 0x47 and fm3 == 0x600000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f20dec0; op2val:0x32ec4e;
op3val:0x23e00000; valaddr_reg:x3; val_offset:96792*0 + 3*7*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 96792*0 + 3*8*FLEN/8, x4, x1, x2)

inst_32265:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x20dec0 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x32ec4e and fs3 == 0 and fe3 == 0x47 and fm3 == 0x700000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f20dec0; op2val:0x32ec4e;
op3val:0x23f00000; valaddr_reg:x3; val_offset:96795*0 + 3*8*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 96795*0 + 3*9*FLEN/8, x4, x1, x2)

inst_32266:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x20dec0 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x32ec4e and fs3 == 0 and fe3 == 0x47 and fm3 == 0x780000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f20dec0; op2val:0x32ec4e;
op3val:0x23f80000; valaddr_reg:x3; val_offset:96798*0 + 3*9*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 96798*0 + 3*10*FLEN/8, x4, x1, x2)

inst_32267:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x20dec0 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x32ec4e and fs3 == 0 and fe3 == 0x47 and fm3 == 0x7c0000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f20dec0; op2val:0x32ec4e;
op3val:0x23fc0000; valaddr_reg:x3; val_offset:96801*0 + 3*10*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 96801*0 + 3*11*FLEN/8, x4, x1, x2)

inst_32268:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x20dec0 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x32ec4e and fs3 == 0 and fe3 == 0x47 and fm3 == 0x7e0000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f20dec0; op2val:0x32ec4e;
op3val:0x23fe0000; valaddr_reg:x3; val_offset:96804*0 + 3*11*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 96804*0 + 3*12*FLEN/8, x4, x1, x2)

inst_32269:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x20dec0 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x32ec4e and fs3 == 0 and fe3 == 0x47 and fm3 == 0x7f0000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f20dec0; op2val:0x32ec4e;
op3val:0x23ff0000; valaddr_reg:x3; val_offset:96807*0 + 3*12*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 96807*0 + 3*13*FLEN/8, x4, x1, x2)

inst_32270:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x20dec0 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x32ec4e and fs3 == 0 and fe3 == 0x47 and fm3 == 0x7f8000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f20dec0; op2val:0x32ec4e;
op3val:0x23ff8000; valaddr_reg:x3; val_offset:96810*0 + 3*13*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 96810*0 + 3*14*FLEN/8, x4, x1, x2)

inst_32271:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x20dec0 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x32ec4e and fs3 == 0 and fe3 == 0x47 and fm3 == 0x7fc000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f20dec0; op2val:0x32ec4e;
op3val:0x23ffc000; valaddr_reg:x3; val_offset:96813*0 + 3*14*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 96813*0 + 3*15*FLEN/8, x4, x1, x2)

inst_32272:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x20dec0 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x32ec4e and fs3 == 0 and fe3 == 0x47 and fm3 == 0x7fe000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f20dec0; op2val:0x32ec4e;
op3val:0x23ffe000; valaddr_reg:x3; val_offset:96816*0 + 3*15*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 96816*0 + 3*16*FLEN/8, x4, x1, x2)

inst_32273:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x20dec0 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x32ec4e and fs3 == 0 and fe3 == 0x47 and fm3 == 0x7ff000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f20dec0; op2val:0x32ec4e;
op3val:0x23fff000; valaddr_reg:x3; val_offset:96819*0 + 3*16*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 96819*0 + 3*17*FLEN/8, x4, x1, x2)

inst_32274:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x20dec0 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x32ec4e and fs3 == 0 and fe3 == 0x47 and fm3 == 0x7ff800 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f20dec0; op2val:0x32ec4e;
op3val:0x23fff800; valaddr_reg:x3; val_offset:96822*0 + 3*17*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 96822*0 + 3*18*FLEN/8, x4, x1, x2)

inst_32275:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x20dec0 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x32ec4e and fs3 == 0 and fe3 == 0x47 and fm3 == 0x7ffc00 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f20dec0; op2val:0x32ec4e;
op3val:0x23fffc00; valaddr_reg:x3; val_offset:96825*0 + 3*18*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 96825*0 + 3*19*FLEN/8, x4, x1, x2)

inst_32276:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x20dec0 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x32ec4e and fs3 == 0 and fe3 == 0x47 and fm3 == 0x7ffe00 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f20dec0; op2val:0x32ec4e;
op3val:0x23fffe00; valaddr_reg:x3; val_offset:96828*0 + 3*19*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 96828*0 + 3*20*FLEN/8, x4, x1, x2)

inst_32277:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x20dec0 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x32ec4e and fs3 == 0 and fe3 == 0x47 and fm3 == 0x7fff00 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f20dec0; op2val:0x32ec4e;
op3val:0x23ffff00; valaddr_reg:x3; val_offset:96831*0 + 3*20*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 96831*0 + 3*21*FLEN/8, x4, x1, x2)

inst_32278:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x20dec0 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x32ec4e and fs3 == 0 and fe3 == 0x47 and fm3 == 0x7fff80 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f20dec0; op2val:0x32ec4e;
op3val:0x23ffff80; valaddr_reg:x3; val_offset:96834*0 + 3*21*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 96834*0 + 3*22*FLEN/8, x4, x1, x2)

inst_32279:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x20dec0 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x32ec4e and fs3 == 0 and fe3 == 0x47 and fm3 == 0x7fffc0 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f20dec0; op2val:0x32ec4e;
op3val:0x23ffffc0; valaddr_reg:x3; val_offset:96837*0 + 3*22*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 96837*0 + 3*23*FLEN/8, x4, x1, x2)

inst_32280:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x20dec0 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x32ec4e and fs3 == 0 and fe3 == 0x47 and fm3 == 0x7fffe0 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f20dec0; op2val:0x32ec4e;
op3val:0x23ffffe0; valaddr_reg:x3; val_offset:96840*0 + 3*23*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 96840*0 + 3*24*FLEN/8, x4, x1, x2)

inst_32281:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x20dec0 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x32ec4e and fs3 == 0 and fe3 == 0x47 and fm3 == 0x7ffff0 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f20dec0; op2val:0x32ec4e;
op3val:0x23fffff0; valaddr_reg:x3; val_offset:96843*0 + 3*24*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 96843*0 + 3*25*FLEN/8, x4, x1, x2)

inst_32282:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x20dec0 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x32ec4e and fs3 == 0 and fe3 == 0x47 and fm3 == 0x7ffff8 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f20dec0; op2val:0x32ec4e;
op3val:0x23fffff8; valaddr_reg:x3; val_offset:96846*0 + 3*25*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 96846*0 + 3*26*FLEN/8, x4, x1, x2)

inst_32283:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x20dec0 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x32ec4e and fs3 == 0 and fe3 == 0x47 and fm3 == 0x7ffffc and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f20dec0; op2val:0x32ec4e;
op3val:0x23fffffc; valaddr_reg:x3; val_offset:96849*0 + 3*26*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 96849*0 + 3*27*FLEN/8, x4, x1, x2)

inst_32284:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x20dec0 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x32ec4e and fs3 == 0 and fe3 == 0x47 and fm3 == 0x7ffffe and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f20dec0; op2val:0x32ec4e;
op3val:0x23fffffe; valaddr_reg:x3; val_offset:96852*0 + 3*27*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 96852*0 + 3*28*FLEN/8, x4, x1, x2)

inst_32285:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x20dec0 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x32ec4e and fs3 == 0 and fe3 == 0x47 and fm3 == 0x7fffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f20dec0; op2val:0x32ec4e;
op3val:0x23ffffff; valaddr_reg:x3; val_offset:96855*0 + 3*28*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 96855*0 + 3*29*FLEN/8, x4, x1, x2)

inst_32286:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x20dec0 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x32ec4e and fs3 == 0 and fe3 == 0x7f and fm3 == 0x000001 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f20dec0; op2val:0x32ec4e;
op3val:0x3f800001; valaddr_reg:x3; val_offset:96858*0 + 3*29*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 96858*0 + 3*30*FLEN/8, x4, x1, x2)

inst_32287:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x20dec0 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x32ec4e and fs3 == 0 and fe3 == 0x7f and fm3 == 0x000003 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f20dec0; op2val:0x32ec4e;
op3val:0x3f800003; valaddr_reg:x3; val_offset:96861*0 + 3*30*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 96861*0 + 3*31*FLEN/8, x4, x1, x2)

inst_32288:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x20dec0 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x32ec4e and fs3 == 0 and fe3 == 0x7f and fm3 == 0x000007 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f20dec0; op2val:0x32ec4e;
op3val:0x3f800007; valaddr_reg:x3; val_offset:96864*0 + 3*31*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 96864*0 + 3*32*FLEN/8, x4, x1, x2)

inst_32289:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x20dec0 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x32ec4e and fs3 == 0 and fe3 == 0x7f and fm3 == 0x199999 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f20dec0; op2val:0x32ec4e;
op3val:0x3f999999; valaddr_reg:x3; val_offset:96867*0 + 3*32*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 96867*0 + 3*33*FLEN/8, x4, x1, x2)

inst_32290:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x20dec0 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x32ec4e and fs3 == 0 and fe3 == 0x7f and fm3 == 0x249249 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f20dec0; op2val:0x32ec4e;
op3val:0x3fa49249; valaddr_reg:x3; val_offset:96870*0 + 3*33*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 96870*0 + 3*34*FLEN/8, x4, x1, x2)

inst_32291:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x20dec0 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x32ec4e and fs3 == 0 and fe3 == 0x7f and fm3 == 0x333333 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f20dec0; op2val:0x32ec4e;
op3val:0x3fb33333; valaddr_reg:x3; val_offset:96873*0 + 3*34*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 96873*0 + 3*35*FLEN/8, x4, x1, x2)

inst_32292:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x20dec0 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x32ec4e and fs3 == 0 and fe3 == 0x7f and fm3 == 0x36db6d and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f20dec0; op2val:0x32ec4e;
op3val:0x3fb6db6d; valaddr_reg:x3; val_offset:96876*0 + 3*35*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 96876*0 + 3*36*FLEN/8, x4, x1, x2)

inst_32293:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x20dec0 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x32ec4e and fs3 == 0 and fe3 == 0x7f and fm3 == 0x3bbbbb and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f20dec0; op2val:0x32ec4e;
op3val:0x3fbbbbbb; valaddr_reg:x3; val_offset:96879*0 + 3*36*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 96879*0 + 3*37*FLEN/8, x4, x1, x2)

inst_32294:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x20dec0 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x32ec4e and fs3 == 0 and fe3 == 0x7f and fm3 == 0x444444 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f20dec0; op2val:0x32ec4e;
op3val:0x3fc44444; valaddr_reg:x3; val_offset:96882*0 + 3*37*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 96882*0 + 3*38*FLEN/8, x4, x1, x2)

inst_32295:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x20dec0 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x32ec4e and fs3 == 0 and fe3 == 0x7f and fm3 == 0x4ccccc and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f20dec0; op2val:0x32ec4e;
op3val:0x3fcccccc; valaddr_reg:x3; val_offset:96885*0 + 3*38*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 96885*0 + 3*39*FLEN/8, x4, x1, x2)

inst_32296:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x20dec0 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x32ec4e and fs3 == 0 and fe3 == 0x7f and fm3 == 0x5b6db6 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f20dec0; op2val:0x32ec4e;
op3val:0x3fdb6db6; valaddr_reg:x3; val_offset:96888*0 + 3*39*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 96888*0 + 3*40*FLEN/8, x4, x1, x2)

inst_32297:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x20dec0 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x32ec4e and fs3 == 0 and fe3 == 0x7f and fm3 == 0x666666 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f20dec0; op2val:0x32ec4e;
op3val:0x3fe66666; valaddr_reg:x3; val_offset:96891*0 + 3*40*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 96891*0 + 3*41*FLEN/8, x4, x1, x2)

inst_32298:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x20dec0 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x32ec4e and fs3 == 0 and fe3 == 0x7f and fm3 == 0x6db6db and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f20dec0; op2val:0x32ec4e;
op3val:0x3fedb6db; valaddr_reg:x3; val_offset:96894*0 + 3*41*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 96894*0 + 3*42*FLEN/8, x4, x1, x2)

inst_32299:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x20dec0 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x32ec4e and fs3 == 0 and fe3 == 0x7f and fm3 == 0x7ffff8 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f20dec0; op2val:0x32ec4e;
op3val:0x3ffffff8; valaddr_reg:x3; val_offset:96897*0 + 3*42*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 96897*0 + 3*43*FLEN/8, x4, x1, x2)

inst_32300:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x20dec0 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x32ec4e and fs3 == 0 and fe3 == 0x7f and fm3 == 0x7ffffc and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f20dec0; op2val:0x32ec4e;
op3val:0x3ffffffc; valaddr_reg:x3; val_offset:96900*0 + 3*43*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 96900*0 + 3*44*FLEN/8, x4, x1, x2)

inst_32301:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x20dec0 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x32ec4e and fs3 == 0 and fe3 == 0x7f and fm3 == 0x7ffffe and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f20dec0; op2val:0x32ec4e;
op3val:0x3ffffffe; valaddr_reg:x3; val_offset:96903*0 + 3*44*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 96903*0 + 3*45*FLEN/8, x4, x1, x2)

inst_32302:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x217160 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000001 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f217160; op2val:0x0;
op3val:0x1; valaddr_reg:x3; val_offset:96906*0 + 3*45*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 96906*0 + 3*46*FLEN/8, x4, x1, x2)

inst_32303:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x217160 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000003 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f217160; op2val:0x0;
op3val:0x3; valaddr_reg:x3; val_offset:96909*0 + 3*46*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 96909*0 + 3*47*FLEN/8, x4, x1, x2)

inst_32304:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x217160 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000007 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f217160; op2val:0x0;
op3val:0x7; valaddr_reg:x3; val_offset:96912*0 + 3*47*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 96912*0 + 3*48*FLEN/8, x4, x1, x2)

inst_32305:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x217160 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x199999 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f217160; op2val:0x0;
op3val:0x199999; valaddr_reg:x3; val_offset:96915*0 + 3*48*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 96915*0 + 3*49*FLEN/8, x4, x1, x2)

inst_32306:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x217160 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x249249 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f217160; op2val:0x0;
op3val:0x249249; valaddr_reg:x3; val_offset:96918*0 + 3*49*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 96918*0 + 3*50*FLEN/8, x4, x1, x2)

inst_32307:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x217160 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x333333 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f217160; op2val:0x0;
op3val:0x333333; valaddr_reg:x3; val_offset:96921*0 + 3*50*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 96921*0 + 3*51*FLEN/8, x4, x1, x2)

inst_32308:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x217160 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x36db6d and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f217160; op2val:0x0;
op3val:0x36db6d; valaddr_reg:x3; val_offset:96924*0 + 3*51*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 96924*0 + 3*52*FLEN/8, x4, x1, x2)

inst_32309:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x217160 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x3bbbbb and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f217160; op2val:0x0;
op3val:0x3bbbbb; valaddr_reg:x3; val_offset:96927*0 + 3*52*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 96927*0 + 3*53*FLEN/8, x4, x1, x2)

inst_32310:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x217160 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x444444 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f217160; op2val:0x0;
op3val:0x444444; valaddr_reg:x3; val_offset:96930*0 + 3*53*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 96930*0 + 3*54*FLEN/8, x4, x1, x2)

inst_32311:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x217160 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x4ccccc and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f217160; op2val:0x0;
op3val:0x4ccccc; valaddr_reg:x3; val_offset:96933*0 + 3*54*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 96933*0 + 3*55*FLEN/8, x4, x1, x2)

inst_32312:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x217160 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x5b6db6 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f217160; op2val:0x0;
op3val:0x5b6db6; valaddr_reg:x3; val_offset:96936*0 + 3*55*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 96936*0 + 3*56*FLEN/8, x4, x1, x2)

inst_32313:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x217160 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x666666 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f217160; op2val:0x0;
op3val:0x666666; valaddr_reg:x3; val_offset:96939*0 + 3*56*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 96939*0 + 3*57*FLEN/8, x4, x1, x2)

inst_32314:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x217160 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x6db6db and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f217160; op2val:0x0;
op3val:0x6db6db; valaddr_reg:x3; val_offset:96942*0 + 3*57*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 96942*0 + 3*58*FLEN/8, x4, x1, x2)

inst_32315:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x217160 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x7ffff8 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f217160; op2val:0x0;
op3val:0x7ffff8; valaddr_reg:x3; val_offset:96945*0 + 3*58*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 96945*0 + 3*59*FLEN/8, x4, x1, x2)

inst_32316:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x217160 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x7ffffc and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f217160; op2val:0x0;
op3val:0x7ffffc; valaddr_reg:x3; val_offset:96948*0 + 3*59*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 96948*0 + 3*60*FLEN/8, x4, x1, x2)

inst_32317:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x217160 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x7ffffe and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f217160; op2val:0x0;
op3val:0x7ffffe; valaddr_reg:x3; val_offset:96951*0 + 3*60*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 96951*0 + 3*61*FLEN/8, x4, x1, x2)

inst_32318:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x217160 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x10 and fm3 == 0x000000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f217160; op2val:0x0;
op3val:0x8000000; valaddr_reg:x3; val_offset:96954*0 + 3*61*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 96954*0 + 3*62*FLEN/8, x4, x1, x2)

inst_32319:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x217160 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x10 and fm3 == 0x000001 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f217160; op2val:0x0;
op3val:0x8000001; valaddr_reg:x3; val_offset:96957*0 + 3*62*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 96957*0 + 3*63*FLEN/8, x4, x1, x2)

inst_32320:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x217160 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x10 and fm3 == 0x000003 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f217160; op2val:0x0;
op3val:0x8000003; valaddr_reg:x3; val_offset:96960*0 + 3*63*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 96960*0 + 3*64*FLEN/8, x4, x1, x2)

inst_32321:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x217160 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x10 and fm3 == 0x000007 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f217160; op2val:0x0;
op3val:0x8000007; valaddr_reg:x3; val_offset:96963*0 + 3*64*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 96963*0 + 3*65*FLEN/8, x4, x1, x2)

inst_32322:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x217160 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x10 and fm3 == 0x00000f and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f217160; op2val:0x0;
op3val:0x800000f; valaddr_reg:x3; val_offset:96966*0 + 3*65*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 96966*0 + 3*66*FLEN/8, x4, x1, x2)

inst_32323:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x217160 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x10 and fm3 == 0x00001f and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f217160; op2val:0x0;
op3val:0x800001f; valaddr_reg:x3; val_offset:96969*0 + 3*66*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 96969*0 + 3*67*FLEN/8, x4, x1, x2)

inst_32324:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x217160 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x10 and fm3 == 0x00003f and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f217160; op2val:0x0;
op3val:0x800003f; valaddr_reg:x3; val_offset:96972*0 + 3*67*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 96972*0 + 3*68*FLEN/8, x4, x1, x2)

inst_32325:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x217160 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x10 and fm3 == 0x00007f and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f217160; op2val:0x0;
op3val:0x800007f; valaddr_reg:x3; val_offset:96975*0 + 3*68*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 96975*0 + 3*69*FLEN/8, x4, x1, x2)

inst_32326:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x217160 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x10 and fm3 == 0x0000ff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f217160; op2val:0x0;
op3val:0x80000ff; valaddr_reg:x3; val_offset:96978*0 + 3*69*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 96978*0 + 3*70*FLEN/8, x4, x1, x2)

inst_32327:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x217160 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x10 and fm3 == 0x0001ff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f217160; op2val:0x0;
op3val:0x80001ff; valaddr_reg:x3; val_offset:96981*0 + 3*70*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 96981*0 + 3*71*FLEN/8, x4, x1, x2)

inst_32328:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x217160 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x10 and fm3 == 0x0003ff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f217160; op2val:0x0;
op3val:0x80003ff; valaddr_reg:x3; val_offset:96984*0 + 3*71*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 96984*0 + 3*72*FLEN/8, x4, x1, x2)

inst_32329:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x217160 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x10 and fm3 == 0x0007ff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f217160; op2val:0x0;
op3val:0x80007ff; valaddr_reg:x3; val_offset:96987*0 + 3*72*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 96987*0 + 3*73*FLEN/8, x4, x1, x2)

inst_32330:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x217160 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x10 and fm3 == 0x000fff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f217160; op2val:0x0;
op3val:0x8000fff; valaddr_reg:x3; val_offset:96990*0 + 3*73*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 96990*0 + 3*74*FLEN/8, x4, x1, x2)

inst_32331:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x217160 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x10 and fm3 == 0x001fff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f217160; op2val:0x0;
op3val:0x8001fff; valaddr_reg:x3; val_offset:96993*0 + 3*74*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 96993*0 + 3*75*FLEN/8, x4, x1, x2)

inst_32332:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x217160 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x10 and fm3 == 0x003fff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f217160; op2val:0x0;
op3val:0x8003fff; valaddr_reg:x3; val_offset:96996*0 + 3*75*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 96996*0 + 3*76*FLEN/8, x4, x1, x2)

inst_32333:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x217160 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x10 and fm3 == 0x007fff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f217160; op2val:0x0;
op3val:0x8007fff; valaddr_reg:x3; val_offset:96999*0 + 3*76*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 96999*0 + 3*77*FLEN/8, x4, x1, x2)

inst_32334:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x217160 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x10 and fm3 == 0x00ffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f217160; op2val:0x0;
op3val:0x800ffff; valaddr_reg:x3; val_offset:97002*0 + 3*77*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 97002*0 + 3*78*FLEN/8, x4, x1, x2)

inst_32335:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x217160 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x10 and fm3 == 0x01ffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f217160; op2val:0x0;
op3val:0x801ffff; valaddr_reg:x3; val_offset:97005*0 + 3*78*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 97005*0 + 3*79*FLEN/8, x4, x1, x2)

inst_32336:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x217160 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x10 and fm3 == 0x03ffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f217160; op2val:0x0;
op3val:0x803ffff; valaddr_reg:x3; val_offset:97008*0 + 3*79*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 97008*0 + 3*80*FLEN/8, x4, x1, x2)

inst_32337:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x217160 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x10 and fm3 == 0x07ffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f217160; op2val:0x0;
op3val:0x807ffff; valaddr_reg:x3; val_offset:97011*0 + 3*80*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 97011*0 + 3*81*FLEN/8, x4, x1, x2)

inst_32338:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x217160 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x10 and fm3 == 0x0fffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f217160; op2val:0x0;
op3val:0x80fffff; valaddr_reg:x3; val_offset:97014*0 + 3*81*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 97014*0 + 3*82*FLEN/8, x4, x1, x2)

inst_32339:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x217160 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x10 and fm3 == 0x1fffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f217160; op2val:0x0;
op3val:0x81fffff; valaddr_reg:x3; val_offset:97017*0 + 3*82*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 97017*0 + 3*83*FLEN/8, x4, x1, x2)

inst_32340:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x217160 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x10 and fm3 == 0x3fffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f217160; op2val:0x0;
op3val:0x83fffff; valaddr_reg:x3; val_offset:97020*0 + 3*83*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 97020*0 + 3*84*FLEN/8, x4, x1, x2)

inst_32341:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x217160 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x10 and fm3 == 0x400000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f217160; op2val:0x0;
op3val:0x8400000; valaddr_reg:x3; val_offset:97023*0 + 3*84*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 97023*0 + 3*85*FLEN/8, x4, x1, x2)

inst_32342:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x217160 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x10 and fm3 == 0x600000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f217160; op2val:0x0;
op3val:0x8600000; valaddr_reg:x3; val_offset:97026*0 + 3*85*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 97026*0 + 3*86*FLEN/8, x4, x1, x2)

inst_32343:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x217160 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x10 and fm3 == 0x700000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f217160; op2val:0x0;
op3val:0x8700000; valaddr_reg:x3; val_offset:97029*0 + 3*86*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 97029*0 + 3*87*FLEN/8, x4, x1, x2)

inst_32344:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x217160 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x10 and fm3 == 0x780000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f217160; op2val:0x0;
op3val:0x8780000; valaddr_reg:x3; val_offset:97032*0 + 3*87*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 97032*0 + 3*88*FLEN/8, x4, x1, x2)

inst_32345:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x217160 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x10 and fm3 == 0x7c0000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f217160; op2val:0x0;
op3val:0x87c0000; valaddr_reg:x3; val_offset:97035*0 + 3*88*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 97035*0 + 3*89*FLEN/8, x4, x1, x2)

inst_32346:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x217160 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x10 and fm3 == 0x7e0000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f217160; op2val:0x0;
op3val:0x87e0000; valaddr_reg:x3; val_offset:97038*0 + 3*89*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 97038*0 + 3*90*FLEN/8, x4, x1, x2)

inst_32347:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x217160 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x10 and fm3 == 0x7f0000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f217160; op2val:0x0;
op3val:0x87f0000; valaddr_reg:x3; val_offset:97041*0 + 3*90*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 97041*0 + 3*91*FLEN/8, x4, x1, x2)

inst_32348:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x217160 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x10 and fm3 == 0x7f8000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f217160; op2val:0x0;
op3val:0x87f8000; valaddr_reg:x3; val_offset:97044*0 + 3*91*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 97044*0 + 3*92*FLEN/8, x4, x1, x2)

inst_32349:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x217160 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x10 and fm3 == 0x7fc000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f217160; op2val:0x0;
op3val:0x87fc000; valaddr_reg:x3; val_offset:97047*0 + 3*92*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 97047*0 + 3*93*FLEN/8, x4, x1, x2)

inst_32350:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x217160 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x10 and fm3 == 0x7fe000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f217160; op2val:0x0;
op3val:0x87fe000; valaddr_reg:x3; val_offset:97050*0 + 3*93*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 97050*0 + 3*94*FLEN/8, x4, x1, x2)

inst_32351:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x217160 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x10 and fm3 == 0x7ff000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f217160; op2val:0x0;
op3val:0x87ff000; valaddr_reg:x3; val_offset:97053*0 + 3*94*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 97053*0 + 3*95*FLEN/8, x4, x1, x2)

inst_32352:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x217160 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x10 and fm3 == 0x7ff800 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f217160; op2val:0x0;
op3val:0x87ff800; valaddr_reg:x3; val_offset:97056*0 + 3*95*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 97056*0 + 3*96*FLEN/8, x4, x1, x2)

inst_32353:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x217160 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x10 and fm3 == 0x7ffc00 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f217160; op2val:0x0;
op3val:0x87ffc00; valaddr_reg:x3; val_offset:97059*0 + 3*96*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 97059*0 + 3*97*FLEN/8, x4, x1, x2)

inst_32354:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x217160 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x10 and fm3 == 0x7ffe00 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f217160; op2val:0x0;
op3val:0x87ffe00; valaddr_reg:x3; val_offset:97062*0 + 3*97*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 97062*0 + 3*98*FLEN/8, x4, x1, x2)

inst_32355:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x217160 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x10 and fm3 == 0x7fff00 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f217160; op2val:0x0;
op3val:0x87fff00; valaddr_reg:x3; val_offset:97065*0 + 3*98*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 97065*0 + 3*99*FLEN/8, x4, x1, x2)

inst_32356:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x217160 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x10 and fm3 == 0x7fff80 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f217160; op2val:0x0;
op3val:0x87fff80; valaddr_reg:x3; val_offset:97068*0 + 3*99*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 97068*0 + 3*100*FLEN/8, x4, x1, x2)

inst_32357:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x217160 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x10 and fm3 == 0x7fffc0 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f217160; op2val:0x0;
op3val:0x87fffc0; valaddr_reg:x3; val_offset:97071*0 + 3*100*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 97071*0 + 3*101*FLEN/8, x4, x1, x2)

inst_32358:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x217160 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x10 and fm3 == 0x7fffe0 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f217160; op2val:0x0;
op3val:0x87fffe0; valaddr_reg:x3; val_offset:97074*0 + 3*101*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 97074*0 + 3*102*FLEN/8, x4, x1, x2)

inst_32359:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x217160 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x10 and fm3 == 0x7ffff0 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f217160; op2val:0x0;
op3val:0x87ffff0; valaddr_reg:x3; val_offset:97077*0 + 3*102*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 97077*0 + 3*103*FLEN/8, x4, x1, x2)

inst_32360:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x217160 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x10 and fm3 == 0x7ffff8 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f217160; op2val:0x0;
op3val:0x87ffff8; valaddr_reg:x3; val_offset:97080*0 + 3*103*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 97080*0 + 3*104*FLEN/8, x4, x1, x2)

inst_32361:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x217160 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x10 and fm3 == 0x7ffffc and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f217160; op2val:0x0;
op3val:0x87ffffc; valaddr_reg:x3; val_offset:97083*0 + 3*104*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 97083*0 + 3*105*FLEN/8, x4, x1, x2)

inst_32362:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x217160 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x10 and fm3 == 0x7ffffe and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f217160; op2val:0x0;
op3val:0x87ffffe; valaddr_reg:x3; val_offset:97086*0 + 3*105*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 97086*0 + 3*106*FLEN/8, x4, x1, x2)

inst_32363:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x217160 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x10 and fm3 == 0x7fffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f217160; op2val:0x0;
op3val:0x87fffff; valaddr_reg:x3; val_offset:97089*0 + 3*106*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 97089*0 + 3*107*FLEN/8, x4, x1, x2)

inst_32364:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x21ba5d and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000001 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f21ba5d; op2val:0x0;
op3val:0x1; valaddr_reg:x3; val_offset:97092*0 + 3*107*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 97092*0 + 3*108*FLEN/8, x4, x1, x2)

inst_32365:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x21ba5d and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000003 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f21ba5d; op2val:0x0;
op3val:0x3; valaddr_reg:x3; val_offset:97095*0 + 3*108*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 97095*0 + 3*109*FLEN/8, x4, x1, x2)

inst_32366:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x21ba5d and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000007 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f21ba5d; op2val:0x0;
op3val:0x7; valaddr_reg:x3; val_offset:97098*0 + 3*109*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 97098*0 + 3*110*FLEN/8, x4, x1, x2)

inst_32367:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x21ba5d and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x199999 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f21ba5d; op2val:0x0;
op3val:0x199999; valaddr_reg:x3; val_offset:97101*0 + 3*110*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 97101*0 + 3*111*FLEN/8, x4, x1, x2)

inst_32368:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x21ba5d and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x249249 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f21ba5d; op2val:0x0;
op3val:0x249249; valaddr_reg:x3; val_offset:97104*0 + 3*111*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 97104*0 + 3*112*FLEN/8, x4, x1, x2)

inst_32369:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x21ba5d and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x333333 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f21ba5d; op2val:0x0;
op3val:0x333333; valaddr_reg:x3; val_offset:97107*0 + 3*112*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 97107*0 + 3*113*FLEN/8, x4, x1, x2)

inst_32370:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x21ba5d and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x36db6d and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f21ba5d; op2val:0x0;
op3val:0x36db6d; valaddr_reg:x3; val_offset:97110*0 + 3*113*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 97110*0 + 3*114*FLEN/8, x4, x1, x2)

inst_32371:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x21ba5d and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x3bbbbb and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f21ba5d; op2val:0x0;
op3val:0x3bbbbb; valaddr_reg:x3; val_offset:97113*0 + 3*114*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 97113*0 + 3*115*FLEN/8, x4, x1, x2)

inst_32372:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x21ba5d and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x444444 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f21ba5d; op2val:0x0;
op3val:0x444444; valaddr_reg:x3; val_offset:97116*0 + 3*115*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 97116*0 + 3*116*FLEN/8, x4, x1, x2)

inst_32373:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x21ba5d and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x4ccccc and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f21ba5d; op2val:0x0;
op3val:0x4ccccc; valaddr_reg:x3; val_offset:97119*0 + 3*116*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 97119*0 + 3*117*FLEN/8, x4, x1, x2)

inst_32374:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x21ba5d and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x5b6db6 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f21ba5d; op2val:0x0;
op3val:0x5b6db6; valaddr_reg:x3; val_offset:97122*0 + 3*117*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 97122*0 + 3*118*FLEN/8, x4, x1, x2)

inst_32375:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x21ba5d and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x666666 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f21ba5d; op2val:0x0;
op3val:0x666666; valaddr_reg:x3; val_offset:97125*0 + 3*118*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 97125*0 + 3*119*FLEN/8, x4, x1, x2)

inst_32376:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x21ba5d and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x6db6db and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f21ba5d; op2val:0x0;
op3val:0x6db6db; valaddr_reg:x3; val_offset:97128*0 + 3*119*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 97128*0 + 3*120*FLEN/8, x4, x1, x2)

inst_32377:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x21ba5d and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x7ffff8 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f21ba5d; op2val:0x0;
op3val:0x7ffff8; valaddr_reg:x3; val_offset:97131*0 + 3*120*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 97131*0 + 3*121*FLEN/8, x4, x1, x2)

inst_32378:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x21ba5d and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x7ffffc and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f21ba5d; op2val:0x0;
op3val:0x7ffffc; valaddr_reg:x3; val_offset:97134*0 + 3*121*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 97134*0 + 3*122*FLEN/8, x4, x1, x2)

inst_32379:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x21ba5d and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x7ffffe and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f21ba5d; op2val:0x0;
op3val:0x7ffffe; valaddr_reg:x3; val_offset:97137*0 + 3*122*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 97137*0 + 3*123*FLEN/8, x4, x1, x2)

inst_32380:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x21ba5d and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x11 and fm3 == 0x000000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f21ba5d; op2val:0x0;
op3val:0x8800000; valaddr_reg:x3; val_offset:97140*0 + 3*123*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 97140*0 + 3*124*FLEN/8, x4, x1, x2)

inst_32381:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x21ba5d and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x11 and fm3 == 0x000001 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f21ba5d; op2val:0x0;
op3val:0x8800001; valaddr_reg:x3; val_offset:97143*0 + 3*124*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 97143*0 + 3*125*FLEN/8, x4, x1, x2)

inst_32382:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x21ba5d and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x11 and fm3 == 0x000003 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f21ba5d; op2val:0x0;
op3val:0x8800003; valaddr_reg:x3; val_offset:97146*0 + 3*125*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 97146*0 + 3*126*FLEN/8, x4, x1, x2)

inst_32383:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x21ba5d and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x11 and fm3 == 0x000007 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f21ba5d; op2val:0x0;
op3val:0x8800007; valaddr_reg:x3; val_offset:97149*0 + 3*126*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 97149*0 + 3*127*FLEN/8, x4, x1, x2)
RVTEST_SIGBASE(x1,signature_x1_2)

inst_32384:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x21ba5d and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x11 and fm3 == 0x00000f and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f21ba5d; op2val:0x0;
op3val:0x880000f; valaddr_reg:x3; val_offset:97152*0 + 3*127*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 97152*0 + 3*128*FLEN/8, x4, x1, x2)

inst_32385:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x21ba5d and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x11 and fm3 == 0x00001f and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f21ba5d; op2val:0x0;
op3val:0x880001f; valaddr_reg:x3; val_offset:97155*0 + 3*128*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 97155*0 + 3*129*FLEN/8, x4, x1, x2)

inst_32386:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x21ba5d and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x11 and fm3 == 0x00003f and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f21ba5d; op2val:0x0;
op3val:0x880003f; valaddr_reg:x3; val_offset:97158*0 + 3*129*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 97158*0 + 3*130*FLEN/8, x4, x1, x2)

inst_32387:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x21ba5d and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x11 and fm3 == 0x00007f and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f21ba5d; op2val:0x0;
op3val:0x880007f; valaddr_reg:x3; val_offset:97161*0 + 3*130*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 97161*0 + 3*131*FLEN/8, x4, x1, x2)

inst_32388:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x21ba5d and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x11 and fm3 == 0x0000ff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f21ba5d; op2val:0x0;
op3val:0x88000ff; valaddr_reg:x3; val_offset:97164*0 + 3*131*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 97164*0 + 3*132*FLEN/8, x4, x1, x2)

inst_32389:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x21ba5d and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x11 and fm3 == 0x0001ff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f21ba5d; op2val:0x0;
op3val:0x88001ff; valaddr_reg:x3; val_offset:97167*0 + 3*132*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 97167*0 + 3*133*FLEN/8, x4, x1, x2)

inst_32390:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x21ba5d and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x11 and fm3 == 0x0003ff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f21ba5d; op2val:0x0;
op3val:0x88003ff; valaddr_reg:x3; val_offset:97170*0 + 3*133*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 97170*0 + 3*134*FLEN/8, x4, x1, x2)

inst_32391:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x21ba5d and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x11 and fm3 == 0x0007ff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f21ba5d; op2val:0x0;
op3val:0x88007ff; valaddr_reg:x3; val_offset:97173*0 + 3*134*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 97173*0 + 3*135*FLEN/8, x4, x1, x2)

inst_32392:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x21ba5d and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x11 and fm3 == 0x000fff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f21ba5d; op2val:0x0;
op3val:0x8800fff; valaddr_reg:x3; val_offset:97176*0 + 3*135*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 97176*0 + 3*136*FLEN/8, x4, x1, x2)

inst_32393:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x21ba5d and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x11 and fm3 == 0x001fff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f21ba5d; op2val:0x0;
op3val:0x8801fff; valaddr_reg:x3; val_offset:97179*0 + 3*136*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 97179*0 + 3*137*FLEN/8, x4, x1, x2)

inst_32394:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x21ba5d and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x11 and fm3 == 0x003fff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f21ba5d; op2val:0x0;
op3val:0x8803fff; valaddr_reg:x3; val_offset:97182*0 + 3*137*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 97182*0 + 3*138*FLEN/8, x4, x1, x2)

inst_32395:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x21ba5d and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x11 and fm3 == 0x007fff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f21ba5d; op2val:0x0;
op3val:0x8807fff; valaddr_reg:x3; val_offset:97185*0 + 3*138*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 97185*0 + 3*139*FLEN/8, x4, x1, x2)

inst_32396:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x21ba5d and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x11 and fm3 == 0x00ffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f21ba5d; op2val:0x0;
op3val:0x880ffff; valaddr_reg:x3; val_offset:97188*0 + 3*139*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 97188*0 + 3*140*FLEN/8, x4, x1, x2)

inst_32397:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x21ba5d and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x11 and fm3 == 0x01ffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f21ba5d; op2val:0x0;
op3val:0x881ffff; valaddr_reg:x3; val_offset:97191*0 + 3*140*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 97191*0 + 3*141*FLEN/8, x4, x1, x2)

inst_32398:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x21ba5d and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x11 and fm3 == 0x03ffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f21ba5d; op2val:0x0;
op3val:0x883ffff; valaddr_reg:x3; val_offset:97194*0 + 3*141*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 97194*0 + 3*142*FLEN/8, x4, x1, x2)

inst_32399:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x21ba5d and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x11 and fm3 == 0x07ffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f21ba5d; op2val:0x0;
op3val:0x887ffff; valaddr_reg:x3; val_offset:97197*0 + 3*142*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 97197*0 + 3*143*FLEN/8, x4, x1, x2)

inst_32400:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x21ba5d and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x11 and fm3 == 0x0fffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f21ba5d; op2val:0x0;
op3val:0x88fffff; valaddr_reg:x3; val_offset:97200*0 + 3*143*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 97200*0 + 3*144*FLEN/8, x4, x1, x2)

inst_32401:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x21ba5d and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x11 and fm3 == 0x1fffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f21ba5d; op2val:0x0;
op3val:0x89fffff; valaddr_reg:x3; val_offset:97203*0 + 3*144*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 97203*0 + 3*145*FLEN/8, x4, x1, x2)

inst_32402:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x21ba5d and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x11 and fm3 == 0x3fffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f21ba5d; op2val:0x0;
op3val:0x8bfffff; valaddr_reg:x3; val_offset:97206*0 + 3*145*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 97206*0 + 3*146*FLEN/8, x4, x1, x2)

inst_32403:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x21ba5d and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x11 and fm3 == 0x400000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f21ba5d; op2val:0x0;
op3val:0x8c00000; valaddr_reg:x3; val_offset:97209*0 + 3*146*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 97209*0 + 3*147*FLEN/8, x4, x1, x2)

inst_32404:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x21ba5d and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x11 and fm3 == 0x600000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f21ba5d; op2val:0x0;
op3val:0x8e00000; valaddr_reg:x3; val_offset:97212*0 + 3*147*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 97212*0 + 3*148*FLEN/8, x4, x1, x2)

inst_32405:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x21ba5d and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x11 and fm3 == 0x700000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f21ba5d; op2val:0x0;
op3val:0x8f00000; valaddr_reg:x3; val_offset:97215*0 + 3*148*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 97215*0 + 3*149*FLEN/8, x4, x1, x2)

inst_32406:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x21ba5d and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x11 and fm3 == 0x780000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f21ba5d; op2val:0x0;
op3val:0x8f80000; valaddr_reg:x3; val_offset:97218*0 + 3*149*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 97218*0 + 3*150*FLEN/8, x4, x1, x2)

inst_32407:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x21ba5d and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x11 and fm3 == 0x7c0000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f21ba5d; op2val:0x0;
op3val:0x8fc0000; valaddr_reg:x3; val_offset:97221*0 + 3*150*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 97221*0 + 3*151*FLEN/8, x4, x1, x2)

inst_32408:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x21ba5d and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x11 and fm3 == 0x7e0000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f21ba5d; op2val:0x0;
op3val:0x8fe0000; valaddr_reg:x3; val_offset:97224*0 + 3*151*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 97224*0 + 3*152*FLEN/8, x4, x1, x2)

inst_32409:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x21ba5d and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x11 and fm3 == 0x7f0000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f21ba5d; op2val:0x0;
op3val:0x8ff0000; valaddr_reg:x3; val_offset:97227*0 + 3*152*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 97227*0 + 3*153*FLEN/8, x4, x1, x2)

inst_32410:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x21ba5d and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x11 and fm3 == 0x7f8000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f21ba5d; op2val:0x0;
op3val:0x8ff8000; valaddr_reg:x3; val_offset:97230*0 + 3*153*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 97230*0 + 3*154*FLEN/8, x4, x1, x2)

inst_32411:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x21ba5d and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x11 and fm3 == 0x7fc000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f21ba5d; op2val:0x0;
op3val:0x8ffc000; valaddr_reg:x3; val_offset:97233*0 + 3*154*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 97233*0 + 3*155*FLEN/8, x4, x1, x2)

inst_32412:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x21ba5d and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x11 and fm3 == 0x7fe000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f21ba5d; op2val:0x0;
op3val:0x8ffe000; valaddr_reg:x3; val_offset:97236*0 + 3*155*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 97236*0 + 3*156*FLEN/8, x4, x1, x2)

inst_32413:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x21ba5d and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x11 and fm3 == 0x7ff000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f21ba5d; op2val:0x0;
op3val:0x8fff000; valaddr_reg:x3; val_offset:97239*0 + 3*156*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 97239*0 + 3*157*FLEN/8, x4, x1, x2)

inst_32414:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x21ba5d and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x11 and fm3 == 0x7ff800 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f21ba5d; op2val:0x0;
op3val:0x8fff800; valaddr_reg:x3; val_offset:97242*0 + 3*157*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 97242*0 + 3*158*FLEN/8, x4, x1, x2)

inst_32415:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x21ba5d and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x11 and fm3 == 0x7ffc00 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f21ba5d; op2val:0x0;
op3val:0x8fffc00; valaddr_reg:x3; val_offset:97245*0 + 3*158*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 97245*0 + 3*159*FLEN/8, x4, x1, x2)

inst_32416:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x21ba5d and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x11 and fm3 == 0x7ffe00 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f21ba5d; op2val:0x0;
op3val:0x8fffe00; valaddr_reg:x3; val_offset:97248*0 + 3*159*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 97248*0 + 3*160*FLEN/8, x4, x1, x2)

inst_32417:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x21ba5d and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x11 and fm3 == 0x7fff00 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f21ba5d; op2val:0x0;
op3val:0x8ffff00; valaddr_reg:x3; val_offset:97251*0 + 3*160*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 97251*0 + 3*161*FLEN/8, x4, x1, x2)

inst_32418:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x21ba5d and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x11 and fm3 == 0x7fff80 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f21ba5d; op2val:0x0;
op3val:0x8ffff80; valaddr_reg:x3; val_offset:97254*0 + 3*161*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 97254*0 + 3*162*FLEN/8, x4, x1, x2)

inst_32419:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x21ba5d and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x11 and fm3 == 0x7fffc0 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f21ba5d; op2val:0x0;
op3val:0x8ffffc0; valaddr_reg:x3; val_offset:97257*0 + 3*162*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 97257*0 + 3*163*FLEN/8, x4, x1, x2)

inst_32420:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x21ba5d and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x11 and fm3 == 0x7fffe0 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f21ba5d; op2val:0x0;
op3val:0x8ffffe0; valaddr_reg:x3; val_offset:97260*0 + 3*163*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 97260*0 + 3*164*FLEN/8, x4, x1, x2)

inst_32421:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x21ba5d and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x11 and fm3 == 0x7ffff0 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f21ba5d; op2val:0x0;
op3val:0x8fffff0; valaddr_reg:x3; val_offset:97263*0 + 3*164*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 97263*0 + 3*165*FLEN/8, x4, x1, x2)

inst_32422:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x21ba5d and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x11 and fm3 == 0x7ffff8 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f21ba5d; op2val:0x0;
op3val:0x8fffff8; valaddr_reg:x3; val_offset:97266*0 + 3*165*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 97266*0 + 3*166*FLEN/8, x4, x1, x2)

inst_32423:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x21ba5d and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x11 and fm3 == 0x7ffffc and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f21ba5d; op2val:0x0;
op3val:0x8fffffc; valaddr_reg:x3; val_offset:97269*0 + 3*166*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 97269*0 + 3*167*FLEN/8, x4, x1, x2)

inst_32424:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x21ba5d and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x11 and fm3 == 0x7ffffe and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f21ba5d; op2val:0x0;
op3val:0x8fffffe; valaddr_reg:x3; val_offset:97272*0 + 3*167*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 97272*0 + 3*168*FLEN/8, x4, x1, x2)

inst_32425:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x21ba5d and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x11 and fm3 == 0x7fffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f21ba5d; op2val:0x0;
op3val:0x8ffffff; valaddr_reg:x3; val_offset:97275*0 + 3*168*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 97275*0 + 3*169*FLEN/8, x4, x1, x2)

inst_32426:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x220a0f and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000001 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f220a0f; op2val:0x0;
op3val:0x1; valaddr_reg:x3; val_offset:97278*0 + 3*169*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 97278*0 + 3*170*FLEN/8, x4, x1, x2)

inst_32427:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x220a0f and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000003 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f220a0f; op2val:0x0;
op3val:0x3; valaddr_reg:x3; val_offset:97281*0 + 3*170*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 97281*0 + 3*171*FLEN/8, x4, x1, x2)

inst_32428:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x220a0f and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000007 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f220a0f; op2val:0x0;
op3val:0x7; valaddr_reg:x3; val_offset:97284*0 + 3*171*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 97284*0 + 3*172*FLEN/8, x4, x1, x2)

inst_32429:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x220a0f and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x199999 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f220a0f; op2val:0x0;
op3val:0x199999; valaddr_reg:x3; val_offset:97287*0 + 3*172*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 97287*0 + 3*173*FLEN/8, x4, x1, x2)

inst_32430:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x220a0f and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x249249 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f220a0f; op2val:0x0;
op3val:0x249249; valaddr_reg:x3; val_offset:97290*0 + 3*173*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 97290*0 + 3*174*FLEN/8, x4, x1, x2)

inst_32431:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x220a0f and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x333333 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f220a0f; op2val:0x0;
op3val:0x333333; valaddr_reg:x3; val_offset:97293*0 + 3*174*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 97293*0 + 3*175*FLEN/8, x4, x1, x2)

inst_32432:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x220a0f and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x36db6d and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f220a0f; op2val:0x0;
op3val:0x36db6d; valaddr_reg:x3; val_offset:97296*0 + 3*175*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 97296*0 + 3*176*FLEN/8, x4, x1, x2)

inst_32433:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x220a0f and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x3bbbbb and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f220a0f; op2val:0x0;
op3val:0x3bbbbb; valaddr_reg:x3; val_offset:97299*0 + 3*176*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 97299*0 + 3*177*FLEN/8, x4, x1, x2)

inst_32434:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x220a0f and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x444444 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f220a0f; op2val:0x0;
op3val:0x444444; valaddr_reg:x3; val_offset:97302*0 + 3*177*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 97302*0 + 3*178*FLEN/8, x4, x1, x2)

inst_32435:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x220a0f and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x4ccccc and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f220a0f; op2val:0x0;
op3val:0x4ccccc; valaddr_reg:x3; val_offset:97305*0 + 3*178*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 97305*0 + 3*179*FLEN/8, x4, x1, x2)

inst_32436:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x220a0f and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x5b6db6 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f220a0f; op2val:0x0;
op3val:0x5b6db6; valaddr_reg:x3; val_offset:97308*0 + 3*179*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 97308*0 + 3*180*FLEN/8, x4, x1, x2)

inst_32437:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x220a0f and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x666666 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f220a0f; op2val:0x0;
op3val:0x666666; valaddr_reg:x3; val_offset:97311*0 + 3*180*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 97311*0 + 3*181*FLEN/8, x4, x1, x2)

inst_32438:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x220a0f and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x6db6db and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f220a0f; op2val:0x0;
op3val:0x6db6db; valaddr_reg:x3; val_offset:97314*0 + 3*181*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 97314*0 + 3*182*FLEN/8, x4, x1, x2)

inst_32439:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x220a0f and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x7ffff8 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f220a0f; op2val:0x0;
op3val:0x7ffff8; valaddr_reg:x3; val_offset:97317*0 + 3*182*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 97317*0 + 3*183*FLEN/8, x4, x1, x2)

inst_32440:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x220a0f and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x7ffffc and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f220a0f; op2val:0x0;
op3val:0x7ffffc; valaddr_reg:x3; val_offset:97320*0 + 3*183*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 97320*0 + 3*184*FLEN/8, x4, x1, x2)

inst_32441:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x220a0f and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x7ffffe and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f220a0f; op2val:0x0;
op3val:0x7ffffe; valaddr_reg:x3; val_offset:97323*0 + 3*184*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 97323*0 + 3*185*FLEN/8, x4, x1, x2)

inst_32442:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x220a0f and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x1c and fm3 == 0x000000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f220a0f; op2val:0x0;
op3val:0xe000000; valaddr_reg:x3; val_offset:97326*0 + 3*185*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 97326*0 + 3*186*FLEN/8, x4, x1, x2)

inst_32443:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x220a0f and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x1c and fm3 == 0x000001 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f220a0f; op2val:0x0;
op3val:0xe000001; valaddr_reg:x3; val_offset:97329*0 + 3*186*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 97329*0 + 3*187*FLEN/8, x4, x1, x2)

inst_32444:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x220a0f and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x1c and fm3 == 0x000003 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f220a0f; op2val:0x0;
op3val:0xe000003; valaddr_reg:x3; val_offset:97332*0 + 3*187*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 97332*0 + 3*188*FLEN/8, x4, x1, x2)

inst_32445:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x220a0f and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x1c and fm3 == 0x000007 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f220a0f; op2val:0x0;
op3val:0xe000007; valaddr_reg:x3; val_offset:97335*0 + 3*188*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 97335*0 + 3*189*FLEN/8, x4, x1, x2)

inst_32446:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x220a0f and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x1c and fm3 == 0x00000f and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f220a0f; op2val:0x0;
op3val:0xe00000f; valaddr_reg:x3; val_offset:97338*0 + 3*189*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 97338*0 + 3*190*FLEN/8, x4, x1, x2)

inst_32447:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x220a0f and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x1c and fm3 == 0x00001f and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f220a0f; op2val:0x0;
op3val:0xe00001f; valaddr_reg:x3; val_offset:97341*0 + 3*190*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 97341*0 + 3*191*FLEN/8, x4, x1, x2)

inst_32448:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x220a0f and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x1c and fm3 == 0x00003f and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f220a0f; op2val:0x0;
op3val:0xe00003f; valaddr_reg:x3; val_offset:97344*0 + 3*191*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 97344*0 + 3*192*FLEN/8, x4, x1, x2)

inst_32449:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x220a0f and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x1c and fm3 == 0x00007f and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f220a0f; op2val:0x0;
op3val:0xe00007f; valaddr_reg:x3; val_offset:97347*0 + 3*192*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 97347*0 + 3*193*FLEN/8, x4, x1, x2)

inst_32450:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x220a0f and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x1c and fm3 == 0x0000ff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f220a0f; op2val:0x0;
op3val:0xe0000ff; valaddr_reg:x3; val_offset:97350*0 + 3*193*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 97350*0 + 3*194*FLEN/8, x4, x1, x2)

inst_32451:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x220a0f and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x1c and fm3 == 0x0001ff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f220a0f; op2val:0x0;
op3val:0xe0001ff; valaddr_reg:x3; val_offset:97353*0 + 3*194*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 97353*0 + 3*195*FLEN/8, x4, x1, x2)

inst_32452:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x220a0f and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x1c and fm3 == 0x0003ff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f220a0f; op2val:0x0;
op3val:0xe0003ff; valaddr_reg:x3; val_offset:97356*0 + 3*195*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 97356*0 + 3*196*FLEN/8, x4, x1, x2)

inst_32453:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x220a0f and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x1c and fm3 == 0x0007ff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f220a0f; op2val:0x0;
op3val:0xe0007ff; valaddr_reg:x3; val_offset:97359*0 + 3*196*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 97359*0 + 3*197*FLEN/8, x4, x1, x2)

inst_32454:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x220a0f and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x1c and fm3 == 0x000fff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f220a0f; op2val:0x0;
op3val:0xe000fff; valaddr_reg:x3; val_offset:97362*0 + 3*197*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 97362*0 + 3*198*FLEN/8, x4, x1, x2)

inst_32455:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x220a0f and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x1c and fm3 == 0x001fff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f220a0f; op2val:0x0;
op3val:0xe001fff; valaddr_reg:x3; val_offset:97365*0 + 3*198*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 97365*0 + 3*199*FLEN/8, x4, x1, x2)

inst_32456:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x220a0f and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x1c and fm3 == 0x003fff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f220a0f; op2val:0x0;
op3val:0xe003fff; valaddr_reg:x3; val_offset:97368*0 + 3*199*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 97368*0 + 3*200*FLEN/8, x4, x1, x2)

inst_32457:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x220a0f and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x1c and fm3 == 0x007fff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f220a0f; op2val:0x0;
op3val:0xe007fff; valaddr_reg:x3; val_offset:97371*0 + 3*200*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 97371*0 + 3*201*FLEN/8, x4, x1, x2)

inst_32458:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x220a0f and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x1c and fm3 == 0x00ffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f220a0f; op2val:0x0;
op3val:0xe00ffff; valaddr_reg:x3; val_offset:97374*0 + 3*201*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 97374*0 + 3*202*FLEN/8, x4, x1, x2)

inst_32459:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x220a0f and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x1c and fm3 == 0x01ffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f220a0f; op2val:0x0;
op3val:0xe01ffff; valaddr_reg:x3; val_offset:97377*0 + 3*202*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 97377*0 + 3*203*FLEN/8, x4, x1, x2)

inst_32460:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x220a0f and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x1c and fm3 == 0x03ffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f220a0f; op2val:0x0;
op3val:0xe03ffff; valaddr_reg:x3; val_offset:97380*0 + 3*203*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 97380*0 + 3*204*FLEN/8, x4, x1, x2)

inst_32461:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x220a0f and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x1c and fm3 == 0x07ffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f220a0f; op2val:0x0;
op3val:0xe07ffff; valaddr_reg:x3; val_offset:97383*0 + 3*204*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 97383*0 + 3*205*FLEN/8, x4, x1, x2)

inst_32462:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x220a0f and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x1c and fm3 == 0x0fffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f220a0f; op2val:0x0;
op3val:0xe0fffff; valaddr_reg:x3; val_offset:97386*0 + 3*205*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 97386*0 + 3*206*FLEN/8, x4, x1, x2)

inst_32463:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x220a0f and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x1c and fm3 == 0x1fffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f220a0f; op2val:0x0;
op3val:0xe1fffff; valaddr_reg:x3; val_offset:97389*0 + 3*206*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 97389*0 + 3*207*FLEN/8, x4, x1, x2)

inst_32464:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x220a0f and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x1c and fm3 == 0x3fffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f220a0f; op2val:0x0;
op3val:0xe3fffff; valaddr_reg:x3; val_offset:97392*0 + 3*207*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 97392*0 + 3*208*FLEN/8, x4, x1, x2)

inst_32465:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x220a0f and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x1c and fm3 == 0x400000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f220a0f; op2val:0x0;
op3val:0xe400000; valaddr_reg:x3; val_offset:97395*0 + 3*208*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 97395*0 + 3*209*FLEN/8, x4, x1, x2)

inst_32466:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x220a0f and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x1c and fm3 == 0x600000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f220a0f; op2val:0x0;
op3val:0xe600000; valaddr_reg:x3; val_offset:97398*0 + 3*209*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 97398*0 + 3*210*FLEN/8, x4, x1, x2)

inst_32467:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x220a0f and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x1c and fm3 == 0x700000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f220a0f; op2val:0x0;
op3val:0xe700000; valaddr_reg:x3; val_offset:97401*0 + 3*210*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 97401*0 + 3*211*FLEN/8, x4, x1, x2)

inst_32468:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x220a0f and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x1c and fm3 == 0x780000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f220a0f; op2val:0x0;
op3val:0xe780000; valaddr_reg:x3; val_offset:97404*0 + 3*211*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 97404*0 + 3*212*FLEN/8, x4, x1, x2)

inst_32469:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x220a0f and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x1c and fm3 == 0x7c0000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f220a0f; op2val:0x0;
op3val:0xe7c0000; valaddr_reg:x3; val_offset:97407*0 + 3*212*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 97407*0 + 3*213*FLEN/8, x4, x1, x2)

inst_32470:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x220a0f and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x1c and fm3 == 0x7e0000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f220a0f; op2val:0x0;
op3val:0xe7e0000; valaddr_reg:x3; val_offset:97410*0 + 3*213*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 97410*0 + 3*214*FLEN/8, x4, x1, x2)

inst_32471:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x220a0f and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x1c and fm3 == 0x7f0000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f220a0f; op2val:0x0;
op3val:0xe7f0000; valaddr_reg:x3; val_offset:97413*0 + 3*214*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 97413*0 + 3*215*FLEN/8, x4, x1, x2)

inst_32472:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x220a0f and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x1c and fm3 == 0x7f8000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f220a0f; op2val:0x0;
op3val:0xe7f8000; valaddr_reg:x3; val_offset:97416*0 + 3*215*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 97416*0 + 3*216*FLEN/8, x4, x1, x2)

inst_32473:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x220a0f and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x1c and fm3 == 0x7fc000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f220a0f; op2val:0x0;
op3val:0xe7fc000; valaddr_reg:x3; val_offset:97419*0 + 3*216*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 97419*0 + 3*217*FLEN/8, x4, x1, x2)

inst_32474:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x220a0f and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x1c and fm3 == 0x7fe000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f220a0f; op2val:0x0;
op3val:0xe7fe000; valaddr_reg:x3; val_offset:97422*0 + 3*217*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 97422*0 + 3*218*FLEN/8, x4, x1, x2)

inst_32475:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x220a0f and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x1c and fm3 == 0x7ff000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f220a0f; op2val:0x0;
op3val:0xe7ff000; valaddr_reg:x3; val_offset:97425*0 + 3*218*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 97425*0 + 3*219*FLEN/8, x4, x1, x2)

inst_32476:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x220a0f and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x1c and fm3 == 0x7ff800 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f220a0f; op2val:0x0;
op3val:0xe7ff800; valaddr_reg:x3; val_offset:97428*0 + 3*219*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 97428*0 + 3*220*FLEN/8, x4, x1, x2)

inst_32477:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x220a0f and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x1c and fm3 == 0x7ffc00 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f220a0f; op2val:0x0;
op3val:0xe7ffc00; valaddr_reg:x3; val_offset:97431*0 + 3*220*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 97431*0 + 3*221*FLEN/8, x4, x1, x2)

inst_32478:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x220a0f and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x1c and fm3 == 0x7ffe00 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f220a0f; op2val:0x0;
op3val:0xe7ffe00; valaddr_reg:x3; val_offset:97434*0 + 3*221*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 97434*0 + 3*222*FLEN/8, x4, x1, x2)

inst_32479:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x220a0f and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x1c and fm3 == 0x7fff00 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f220a0f; op2val:0x0;
op3val:0xe7fff00; valaddr_reg:x3; val_offset:97437*0 + 3*222*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 97437*0 + 3*223*FLEN/8, x4, x1, x2)

inst_32480:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x220a0f and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x1c and fm3 == 0x7fff80 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f220a0f; op2val:0x0;
op3val:0xe7fff80; valaddr_reg:x3; val_offset:97440*0 + 3*223*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 97440*0 + 3*224*FLEN/8, x4, x1, x2)

inst_32481:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x220a0f and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x1c and fm3 == 0x7fffc0 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f220a0f; op2val:0x0;
op3val:0xe7fffc0; valaddr_reg:x3; val_offset:97443*0 + 3*224*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 97443*0 + 3*225*FLEN/8, x4, x1, x2)

inst_32482:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x220a0f and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x1c and fm3 == 0x7fffe0 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f220a0f; op2val:0x0;
op3val:0xe7fffe0; valaddr_reg:x3; val_offset:97446*0 + 3*225*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 97446*0 + 3*226*FLEN/8, x4, x1, x2)

inst_32483:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x220a0f and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x1c and fm3 == 0x7ffff0 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f220a0f; op2val:0x0;
op3val:0xe7ffff0; valaddr_reg:x3; val_offset:97449*0 + 3*226*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 97449*0 + 3*227*FLEN/8, x4, x1, x2)

inst_32484:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x220a0f and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x1c and fm3 == 0x7ffff8 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f220a0f; op2val:0x0;
op3val:0xe7ffff8; valaddr_reg:x3; val_offset:97452*0 + 3*227*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 97452*0 + 3*228*FLEN/8, x4, x1, x2)

inst_32485:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x220a0f and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x1c and fm3 == 0x7ffffc and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f220a0f; op2val:0x0;
op3val:0xe7ffffc; valaddr_reg:x3; val_offset:97455*0 + 3*228*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 97455*0 + 3*229*FLEN/8, x4, x1, x2)

inst_32486:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x220a0f and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x1c and fm3 == 0x7ffffe and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f220a0f; op2val:0x0;
op3val:0xe7ffffe; valaddr_reg:x3; val_offset:97458*0 + 3*229*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 97458*0 + 3*230*FLEN/8, x4, x1, x2)

inst_32487:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x220a0f and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x1c and fm3 == 0x7fffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f220a0f; op2val:0x0;
op3val:0xe7fffff; valaddr_reg:x3; val_offset:97461*0 + 3*230*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 97461*0 + 3*231*FLEN/8, x4, x1, x2)

inst_32488:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x222105 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f222105; op2val:0x0;
op3val:0x0; valaddr_reg:x3; val_offset:97464*0 + 3*231*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 97464*0 + 3*232*FLEN/8, x4, x1, x2)

inst_32489:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x222105 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000001 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f222105; op2val:0x0;
op3val:0x1; valaddr_reg:x3; val_offset:97467*0 + 3*232*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 97467*0 + 3*233*FLEN/8, x4, x1, x2)

inst_32490:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x222105 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000003 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f222105; op2val:0x0;
op3val:0x3; valaddr_reg:x3; val_offset:97470*0 + 3*233*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 97470*0 + 3*234*FLEN/8, x4, x1, x2)

inst_32491:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x222105 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000007 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f222105; op2val:0x0;
op3val:0x7; valaddr_reg:x3; val_offset:97473*0 + 3*234*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 97473*0 + 3*235*FLEN/8, x4, x1, x2)

inst_32492:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x222105 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x00000f and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f222105; op2val:0x0;
op3val:0xf; valaddr_reg:x3; val_offset:97476*0 + 3*235*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 97476*0 + 3*236*FLEN/8, x4, x1, x2)

inst_32493:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x222105 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x00001f and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f222105; op2val:0x0;
op3val:0x1f; valaddr_reg:x3; val_offset:97479*0 + 3*236*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 97479*0 + 3*237*FLEN/8, x4, x1, x2)

inst_32494:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x222105 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x00003f and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f222105; op2val:0x0;
op3val:0x3f; valaddr_reg:x3; val_offset:97482*0 + 3*237*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 97482*0 + 3*238*FLEN/8, x4, x1, x2)

inst_32495:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x222105 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x00007f and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f222105; op2val:0x0;
op3val:0x7f; valaddr_reg:x3; val_offset:97485*0 + 3*238*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 97485*0 + 3*239*FLEN/8, x4, x1, x2)

inst_32496:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x222105 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x0000ff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f222105; op2val:0x0;
op3val:0xff; valaddr_reg:x3; val_offset:97488*0 + 3*239*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 97488*0 + 3*240*FLEN/8, x4, x1, x2)

inst_32497:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x222105 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x0001ff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f222105; op2val:0x0;
op3val:0x1ff; valaddr_reg:x3; val_offset:97491*0 + 3*240*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 97491*0 + 3*241*FLEN/8, x4, x1, x2)

inst_32498:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x222105 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x0003ff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f222105; op2val:0x0;
op3val:0x3ff; valaddr_reg:x3; val_offset:97494*0 + 3*241*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 97494*0 + 3*242*FLEN/8, x4, x1, x2)

inst_32499:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x222105 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x0007ff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f222105; op2val:0x0;
op3val:0x7ff; valaddr_reg:x3; val_offset:97497*0 + 3*242*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 97497*0 + 3*243*FLEN/8, x4, x1, x2)

inst_32500:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x222105 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000fff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f222105; op2val:0x0;
op3val:0xfff; valaddr_reg:x3; val_offset:97500*0 + 3*243*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 97500*0 + 3*244*FLEN/8, x4, x1, x2)

inst_32501:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x222105 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x001fff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f222105; op2val:0x0;
op3val:0x1fff; valaddr_reg:x3; val_offset:97503*0 + 3*244*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 97503*0 + 3*245*FLEN/8, x4, x1, x2)

inst_32502:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x222105 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x003fff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f222105; op2val:0x0;
op3val:0x3fff; valaddr_reg:x3; val_offset:97506*0 + 3*245*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 97506*0 + 3*246*FLEN/8, x4, x1, x2)

inst_32503:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x222105 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x007fff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f222105; op2val:0x0;
op3val:0x7fff; valaddr_reg:x3; val_offset:97509*0 + 3*246*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 97509*0 + 3*247*FLEN/8, x4, x1, x2)

inst_32504:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x222105 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x00ffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f222105; op2val:0x0;
op3val:0xffff; valaddr_reg:x3; val_offset:97512*0 + 3*247*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 97512*0 + 3*248*FLEN/8, x4, x1, x2)

inst_32505:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x222105 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x01ffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f222105; op2val:0x0;
op3val:0x1ffff; valaddr_reg:x3; val_offset:97515*0 + 3*248*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 97515*0 + 3*249*FLEN/8, x4, x1, x2)

inst_32506:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x222105 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x03ffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f222105; op2val:0x0;
op3val:0x3ffff; valaddr_reg:x3; val_offset:97518*0 + 3*249*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 97518*0 + 3*250*FLEN/8, x4, x1, x2)

inst_32507:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x222105 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x07ffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f222105; op2val:0x0;
op3val:0x7ffff; valaddr_reg:x3; val_offset:97521*0 + 3*250*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 97521*0 + 3*251*FLEN/8, x4, x1, x2)

inst_32508:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x222105 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x0fffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f222105; op2val:0x0;
op3val:0xfffff; valaddr_reg:x3; val_offset:97524*0 + 3*251*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 97524*0 + 3*252*FLEN/8, x4, x1, x2)

inst_32509:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x222105 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x199999 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f222105; op2val:0x0;
op3val:0x199999; valaddr_reg:x3; val_offset:97527*0 + 3*252*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 97527*0 + 3*253*FLEN/8, x4, x1, x2)

inst_32510:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x222105 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x1fffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f222105; op2val:0x0;
op3val:0x1fffff; valaddr_reg:x3; val_offset:97530*0 + 3*253*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 97530*0 + 3*254*FLEN/8, x4, x1, x2)

inst_32511:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x222105 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x249249 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f222105; op2val:0x0;
op3val:0x249249; valaddr_reg:x3; val_offset:97533*0 + 3*254*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 97533*0 + 3*255*FLEN/8, x4, x1, x2)
RVTEST_SIGBASE(x1,signature_x1_3)

inst_32512:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x222105 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x333333 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f222105; op2val:0x0;
op3val:0x333333; valaddr_reg:x3; val_offset:97536*0 + 3*256*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 97536*0 + 3*256*FLEN/8, x4, x1, x2)

inst_32513:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x222105 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x36db6d and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f222105; op2val:0x0;
op3val:0x36db6d; valaddr_reg:x3; val_offset:97539*0 + 3*257*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 97539*0 + 3*257*FLEN/8, x4, x1, x2)

inst_32514:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x222105 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x3bbbbb and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f222105; op2val:0x0;
op3val:0x3bbbbb; valaddr_reg:x3; val_offset:97542*0 + 3*258*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 97542*0 + 3*258*FLEN/8, x4, x1, x2)

inst_32515:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x222105 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x3fffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f222105; op2val:0x0;
op3val:0x3fffff; valaddr_reg:x3; val_offset:97545*0 + 3*259*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 97545*0 + 3*259*FLEN/8, x4, x1, x2)

inst_32516:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x222105 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x400000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f222105; op2val:0x0;
op3val:0x400000; valaddr_reg:x3; val_offset:97548*0 + 3*260*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 97548*0 + 3*260*FLEN/8, x4, x1, x2)

inst_32517:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x222105 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x444444 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f222105; op2val:0x0;
op3val:0x444444; valaddr_reg:x3; val_offset:97551*0 + 3*261*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 97551*0 + 3*261*FLEN/8, x4, x1, x2)

inst_32518:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x222105 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x4ccccc and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f222105; op2val:0x0;
op3val:0x4ccccc; valaddr_reg:x3; val_offset:97554*0 + 3*262*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 97554*0 + 3*262*FLEN/8, x4, x1, x2)

inst_32519:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x222105 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x5b6db6 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f222105; op2val:0x0;
op3val:0x5b6db6; valaddr_reg:x3; val_offset:97557*0 + 3*263*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 97557*0 + 3*263*FLEN/8, x4, x1, x2)

inst_32520:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x222105 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x600000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f222105; op2val:0x0;
op3val:0x600000; valaddr_reg:x3; val_offset:97560*0 + 3*264*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 97560*0 + 3*264*FLEN/8, x4, x1, x2)

inst_32521:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x222105 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x666666 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f222105; op2val:0x0;
op3val:0x666666; valaddr_reg:x3; val_offset:97563*0 + 3*265*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 97563*0 + 3*265*FLEN/8, x4, x1, x2)

inst_32522:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x222105 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x6db6db and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f222105; op2val:0x0;
op3val:0x6db6db; valaddr_reg:x3; val_offset:97566*0 + 3*266*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 97566*0 + 3*266*FLEN/8, x4, x1, x2)

inst_32523:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x222105 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x700000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f222105; op2val:0x0;
op3val:0x700000; valaddr_reg:x3; val_offset:97569*0 + 3*267*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 97569*0 + 3*267*FLEN/8, x4, x1, x2)

inst_32524:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x222105 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x780000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f222105; op2val:0x0;
op3val:0x780000; valaddr_reg:x3; val_offset:97572*0 + 3*268*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 97572*0 + 3*268*FLEN/8, x4, x1, x2)

inst_32525:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x222105 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x7c0000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f222105; op2val:0x0;
op3val:0x7c0000; valaddr_reg:x3; val_offset:97575*0 + 3*269*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 97575*0 + 3*269*FLEN/8, x4, x1, x2)

inst_32526:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x222105 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x7e0000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f222105; op2val:0x0;
op3val:0x7e0000; valaddr_reg:x3; val_offset:97578*0 + 3*270*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 97578*0 + 3*270*FLEN/8, x4, x1, x2)

inst_32527:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x222105 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x7f0000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f222105; op2val:0x0;
op3val:0x7f0000; valaddr_reg:x3; val_offset:97581*0 + 3*271*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 97581*0 + 3*271*FLEN/8, x4, x1, x2)

inst_32528:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x222105 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x7f8000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f222105; op2val:0x0;
op3val:0x7f8000; valaddr_reg:x3; val_offset:97584*0 + 3*272*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 97584*0 + 3*272*FLEN/8, x4, x1, x2)

inst_32529:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x222105 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x7fc000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f222105; op2val:0x0;
op3val:0x7fc000; valaddr_reg:x3; val_offset:97587*0 + 3*273*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 97587*0 + 3*273*FLEN/8, x4, x1, x2)

inst_32530:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x222105 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x7fe000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f222105; op2val:0x0;
op3val:0x7fe000; valaddr_reg:x3; val_offset:97590*0 + 3*274*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 97590*0 + 3*274*FLEN/8, x4, x1, x2)

inst_32531:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x222105 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x7ff000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f222105; op2val:0x0;
op3val:0x7ff000; valaddr_reg:x3; val_offset:97593*0 + 3*275*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 97593*0 + 3*275*FLEN/8, x4, x1, x2)

inst_32532:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x222105 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x7ff800 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f222105; op2val:0x0;
op3val:0x7ff800; valaddr_reg:x3; val_offset:97596*0 + 3*276*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 97596*0 + 3*276*FLEN/8, x4, x1, x2)

inst_32533:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x222105 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x7ffc00 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f222105; op2val:0x0;
op3val:0x7ffc00; valaddr_reg:x3; val_offset:97599*0 + 3*277*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 97599*0 + 3*277*FLEN/8, x4, x1, x2)

inst_32534:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x222105 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x7ffe00 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f222105; op2val:0x0;
op3val:0x7ffe00; valaddr_reg:x3; val_offset:97602*0 + 3*278*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 97602*0 + 3*278*FLEN/8, x4, x1, x2)

inst_32535:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x222105 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x7fff00 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f222105; op2val:0x0;
op3val:0x7fff00; valaddr_reg:x3; val_offset:97605*0 + 3*279*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 97605*0 + 3*279*FLEN/8, x4, x1, x2)

inst_32536:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x222105 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x7fff80 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f222105; op2val:0x0;
op3val:0x7fff80; valaddr_reg:x3; val_offset:97608*0 + 3*280*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 97608*0 + 3*280*FLEN/8, x4, x1, x2)

inst_32537:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x222105 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x7fffc0 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f222105; op2val:0x0;
op3val:0x7fffc0; valaddr_reg:x3; val_offset:97611*0 + 3*281*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 97611*0 + 3*281*FLEN/8, x4, x1, x2)

inst_32538:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x222105 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x7fffe0 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f222105; op2val:0x0;
op3val:0x7fffe0; valaddr_reg:x3; val_offset:97614*0 + 3*282*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 97614*0 + 3*282*FLEN/8, x4, x1, x2)

inst_32539:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x222105 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x7ffff0 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f222105; op2val:0x0;
op3val:0x7ffff0; valaddr_reg:x3; val_offset:97617*0 + 3*283*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 97617*0 + 3*283*FLEN/8, x4, x1, x2)

inst_32540:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x222105 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x7ffff8 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f222105; op2val:0x0;
op3val:0x7ffff8; valaddr_reg:x3; val_offset:97620*0 + 3*284*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 97620*0 + 3*284*FLEN/8, x4, x1, x2)

inst_32541:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x222105 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x7ffffc and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f222105; op2val:0x0;
op3val:0x7ffffc; valaddr_reg:x3; val_offset:97623*0 + 3*285*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 97623*0 + 3*285*FLEN/8, x4, x1, x2)

inst_32542:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x222105 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x7ffffe and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f222105; op2val:0x0;
op3val:0x7ffffe; valaddr_reg:x3; val_offset:97626*0 + 3*286*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 97626*0 + 3*286*FLEN/8, x4, x1, x2)

inst_32543:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x222105 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x7fffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f222105; op2val:0x0;
op3val:0x7fffff; valaddr_reg:x3; val_offset:97629*0 + 3*287*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 97629*0 + 3*287*FLEN/8, x4, x1, x2)

inst_32544:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x22559e and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000001 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f22559e; op2val:0x80000000;
op3val:0x80000001; valaddr_reg:x3; val_offset:97632*0 + 3*288*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 97632*0 + 3*288*FLEN/8, x4, x1, x2)

inst_32545:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x22559e and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000003 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f22559e; op2val:0x80000000;
op3val:0x80000003; valaddr_reg:x3; val_offset:97635*0 + 3*289*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 97635*0 + 3*289*FLEN/8, x4, x1, x2)

inst_32546:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x22559e and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000007 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f22559e; op2val:0x80000000;
op3val:0x80000007; valaddr_reg:x3; val_offset:97638*0 + 3*290*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 97638*0 + 3*290*FLEN/8, x4, x1, x2)

inst_32547:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x22559e and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x199999 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f22559e; op2val:0x80000000;
op3val:0x80199999; valaddr_reg:x3; val_offset:97641*0 + 3*291*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 97641*0 + 3*291*FLEN/8, x4, x1, x2)

inst_32548:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x22559e and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x249249 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f22559e; op2val:0x80000000;
op3val:0x80249249; valaddr_reg:x3; val_offset:97644*0 + 3*292*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 97644*0 + 3*292*FLEN/8, x4, x1, x2)

inst_32549:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x22559e and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x333333 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f22559e; op2val:0x80000000;
op3val:0x80333333; valaddr_reg:x3; val_offset:97647*0 + 3*293*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 97647*0 + 3*293*FLEN/8, x4, x1, x2)

inst_32550:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x22559e and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x36db6d and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f22559e; op2val:0x80000000;
op3val:0x8036db6d; valaddr_reg:x3; val_offset:97650*0 + 3*294*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 97650*0 + 3*294*FLEN/8, x4, x1, x2)

inst_32551:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x22559e and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3bbbbb and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f22559e; op2val:0x80000000;
op3val:0x803bbbbb; valaddr_reg:x3; val_offset:97653*0 + 3*295*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 97653*0 + 3*295*FLEN/8, x4, x1, x2)

inst_32552:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x22559e and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x444444 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f22559e; op2val:0x80000000;
op3val:0x80444444; valaddr_reg:x3; val_offset:97656*0 + 3*296*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 97656*0 + 3*296*FLEN/8, x4, x1, x2)

inst_32553:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x22559e and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x4ccccc and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f22559e; op2val:0x80000000;
op3val:0x804ccccc; valaddr_reg:x3; val_offset:97659*0 + 3*297*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 97659*0 + 3*297*FLEN/8, x4, x1, x2)

inst_32554:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x22559e and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x5b6db6 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f22559e; op2val:0x80000000;
op3val:0x805b6db6; valaddr_reg:x3; val_offset:97662*0 + 3*298*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 97662*0 + 3*298*FLEN/8, x4, x1, x2)

inst_32555:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x22559e and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x666666 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f22559e; op2val:0x80000000;
op3val:0x80666666; valaddr_reg:x3; val_offset:97665*0 + 3*299*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 97665*0 + 3*299*FLEN/8, x4, x1, x2)

inst_32556:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x22559e and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x6db6db and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f22559e; op2val:0x80000000;
op3val:0x806db6db; valaddr_reg:x3; val_offset:97668*0 + 3*300*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 97668*0 + 3*300*FLEN/8, x4, x1, x2)

inst_32557:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x22559e and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7ffff8 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f22559e; op2val:0x80000000;
op3val:0x807ffff8; valaddr_reg:x3; val_offset:97671*0 + 3*301*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 97671*0 + 3*301*FLEN/8, x4, x1, x2)

inst_32558:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x22559e and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7ffffc and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f22559e; op2val:0x80000000;
op3val:0x807ffffc; valaddr_reg:x3; val_offset:97674*0 + 3*302*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 97674*0 + 3*302*FLEN/8, x4, x1, x2)

inst_32559:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x22559e and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7ffffe and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f22559e; op2val:0x80000000;
op3val:0x807ffffe; valaddr_reg:x3; val_offset:97677*0 + 3*303*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 97677*0 + 3*303*FLEN/8, x4, x1, x2)

inst_32560:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x22559e and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x0d and fm3 == 0x000000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f22559e; op2val:0x80000000;
op3val:0x86800000; valaddr_reg:x3; val_offset:97680*0 + 3*304*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 97680*0 + 3*304*FLEN/8, x4, x1, x2)

inst_32561:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x22559e and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x0d and fm3 == 0x000001 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f22559e; op2val:0x80000000;
op3val:0x86800001; valaddr_reg:x3; val_offset:97683*0 + 3*305*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 97683*0 + 3*305*FLEN/8, x4, x1, x2)

inst_32562:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x22559e and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x0d and fm3 == 0x000003 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f22559e; op2val:0x80000000;
op3val:0x86800003; valaddr_reg:x3; val_offset:97686*0 + 3*306*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 97686*0 + 3*306*FLEN/8, x4, x1, x2)

inst_32563:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x22559e and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x0d and fm3 == 0x000007 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f22559e; op2val:0x80000000;
op3val:0x86800007; valaddr_reg:x3; val_offset:97689*0 + 3*307*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 97689*0 + 3*307*FLEN/8, x4, x1, x2)

inst_32564:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x22559e and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x0d and fm3 == 0x00000f and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f22559e; op2val:0x80000000;
op3val:0x8680000f; valaddr_reg:x3; val_offset:97692*0 + 3*308*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 97692*0 + 3*308*FLEN/8, x4, x1, x2)

inst_32565:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x22559e and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x0d and fm3 == 0x00001f and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f22559e; op2val:0x80000000;
op3val:0x8680001f; valaddr_reg:x3; val_offset:97695*0 + 3*309*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 97695*0 + 3*309*FLEN/8, x4, x1, x2)

inst_32566:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x22559e and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x0d and fm3 == 0x00003f and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f22559e; op2val:0x80000000;
op3val:0x8680003f; valaddr_reg:x3; val_offset:97698*0 + 3*310*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 97698*0 + 3*310*FLEN/8, x4, x1, x2)

inst_32567:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x22559e and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x0d and fm3 == 0x00007f and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f22559e; op2val:0x80000000;
op3val:0x8680007f; valaddr_reg:x3; val_offset:97701*0 + 3*311*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 97701*0 + 3*311*FLEN/8, x4, x1, x2)

inst_32568:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x22559e and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x0d and fm3 == 0x0000ff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f22559e; op2val:0x80000000;
op3val:0x868000ff; valaddr_reg:x3; val_offset:97704*0 + 3*312*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 97704*0 + 3*312*FLEN/8, x4, x1, x2)

inst_32569:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x22559e and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x0d and fm3 == 0x0001ff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f22559e; op2val:0x80000000;
op3val:0x868001ff; valaddr_reg:x3; val_offset:97707*0 + 3*313*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 97707*0 + 3*313*FLEN/8, x4, x1, x2)

inst_32570:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x22559e and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x0d and fm3 == 0x0003ff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f22559e; op2val:0x80000000;
op3val:0x868003ff; valaddr_reg:x3; val_offset:97710*0 + 3*314*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 97710*0 + 3*314*FLEN/8, x4, x1, x2)

inst_32571:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x22559e and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x0d and fm3 == 0x0007ff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f22559e; op2val:0x80000000;
op3val:0x868007ff; valaddr_reg:x3; val_offset:97713*0 + 3*315*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 97713*0 + 3*315*FLEN/8, x4, x1, x2)

inst_32572:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x22559e and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x0d and fm3 == 0x000fff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f22559e; op2val:0x80000000;
op3val:0x86800fff; valaddr_reg:x3; val_offset:97716*0 + 3*316*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 97716*0 + 3*316*FLEN/8, x4, x1, x2)

inst_32573:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x22559e and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x0d and fm3 == 0x001fff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f22559e; op2val:0x80000000;
op3val:0x86801fff; valaddr_reg:x3; val_offset:97719*0 + 3*317*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 97719*0 + 3*317*FLEN/8, x4, x1, x2)

inst_32574:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x22559e and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x0d and fm3 == 0x003fff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f22559e; op2val:0x80000000;
op3val:0x86803fff; valaddr_reg:x3; val_offset:97722*0 + 3*318*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 97722*0 + 3*318*FLEN/8, x4, x1, x2)

inst_32575:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x22559e and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x0d and fm3 == 0x007fff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f22559e; op2val:0x80000000;
op3val:0x86807fff; valaddr_reg:x3; val_offset:97725*0 + 3*319*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 97725*0 + 3*319*FLEN/8, x4, x1, x2)

inst_32576:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x22559e and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x0d and fm3 == 0x00ffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f22559e; op2val:0x80000000;
op3val:0x8680ffff; valaddr_reg:x3; val_offset:97728*0 + 3*320*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 97728*0 + 3*320*FLEN/8, x4, x1, x2)

inst_32577:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x22559e and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x0d and fm3 == 0x01ffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f22559e; op2val:0x80000000;
op3val:0x8681ffff; valaddr_reg:x3; val_offset:97731*0 + 3*321*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 97731*0 + 3*321*FLEN/8, x4, x1, x2)

inst_32578:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x22559e and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x0d and fm3 == 0x03ffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f22559e; op2val:0x80000000;
op3val:0x8683ffff; valaddr_reg:x3; val_offset:97734*0 + 3*322*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 97734*0 + 3*322*FLEN/8, x4, x1, x2)

inst_32579:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x22559e and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x0d and fm3 == 0x07ffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f22559e; op2val:0x80000000;
op3val:0x8687ffff; valaddr_reg:x3; val_offset:97737*0 + 3*323*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 97737*0 + 3*323*FLEN/8, x4, x1, x2)

inst_32580:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x22559e and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x0d and fm3 == 0x0fffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f22559e; op2val:0x80000000;
op3val:0x868fffff; valaddr_reg:x3; val_offset:97740*0 + 3*324*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 97740*0 + 3*324*FLEN/8, x4, x1, x2)

inst_32581:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x22559e and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x0d and fm3 == 0x1fffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f22559e; op2val:0x80000000;
op3val:0x869fffff; valaddr_reg:x3; val_offset:97743*0 + 3*325*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 97743*0 + 3*325*FLEN/8, x4, x1, x2)

inst_32582:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x22559e and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x0d and fm3 == 0x3fffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f22559e; op2val:0x80000000;
op3val:0x86bfffff; valaddr_reg:x3; val_offset:97746*0 + 3*326*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 97746*0 + 3*326*FLEN/8, x4, x1, x2)

inst_32583:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x22559e and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x0d and fm3 == 0x400000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f22559e; op2val:0x80000000;
op3val:0x86c00000; valaddr_reg:x3; val_offset:97749*0 + 3*327*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 97749*0 + 3*327*FLEN/8, x4, x1, x2)

inst_32584:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x22559e and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x0d and fm3 == 0x600000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f22559e; op2val:0x80000000;
op3val:0x86e00000; valaddr_reg:x3; val_offset:97752*0 + 3*328*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 97752*0 + 3*328*FLEN/8, x4, x1, x2)

inst_32585:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x22559e and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x0d and fm3 == 0x700000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f22559e; op2val:0x80000000;
op3val:0x86f00000; valaddr_reg:x3; val_offset:97755*0 + 3*329*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 97755*0 + 3*329*FLEN/8, x4, x1, x2)

inst_32586:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x22559e and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x0d and fm3 == 0x780000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f22559e; op2val:0x80000000;
op3val:0x86f80000; valaddr_reg:x3; val_offset:97758*0 + 3*330*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 97758*0 + 3*330*FLEN/8, x4, x1, x2)

inst_32587:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x22559e and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x0d and fm3 == 0x7c0000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f22559e; op2val:0x80000000;
op3val:0x86fc0000; valaddr_reg:x3; val_offset:97761*0 + 3*331*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 97761*0 + 3*331*FLEN/8, x4, x1, x2)

inst_32588:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x22559e and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x0d and fm3 == 0x7e0000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f22559e; op2val:0x80000000;
op3val:0x86fe0000; valaddr_reg:x3; val_offset:97764*0 + 3*332*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 97764*0 + 3*332*FLEN/8, x4, x1, x2)

inst_32589:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x22559e and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x0d and fm3 == 0x7f0000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f22559e; op2val:0x80000000;
op3val:0x86ff0000; valaddr_reg:x3; val_offset:97767*0 + 3*333*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 97767*0 + 3*333*FLEN/8, x4, x1, x2)

inst_32590:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x22559e and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x0d and fm3 == 0x7f8000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f22559e; op2val:0x80000000;
op3val:0x86ff8000; valaddr_reg:x3; val_offset:97770*0 + 3*334*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 97770*0 + 3*334*FLEN/8, x4, x1, x2)

inst_32591:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x22559e and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x0d and fm3 == 0x7fc000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f22559e; op2val:0x80000000;
op3val:0x86ffc000; valaddr_reg:x3; val_offset:97773*0 + 3*335*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 97773*0 + 3*335*FLEN/8, x4, x1, x2)

inst_32592:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x22559e and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x0d and fm3 == 0x7fe000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f22559e; op2val:0x80000000;
op3val:0x86ffe000; valaddr_reg:x3; val_offset:97776*0 + 3*336*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 97776*0 + 3*336*FLEN/8, x4, x1, x2)

inst_32593:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x22559e and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x0d and fm3 == 0x7ff000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f22559e; op2val:0x80000000;
op3val:0x86fff000; valaddr_reg:x3; val_offset:97779*0 + 3*337*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 97779*0 + 3*337*FLEN/8, x4, x1, x2)

inst_32594:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x22559e and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x0d and fm3 == 0x7ff800 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f22559e; op2val:0x80000000;
op3val:0x86fff800; valaddr_reg:x3; val_offset:97782*0 + 3*338*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 97782*0 + 3*338*FLEN/8, x4, x1, x2)

inst_32595:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x22559e and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x0d and fm3 == 0x7ffc00 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f22559e; op2val:0x80000000;
op3val:0x86fffc00; valaddr_reg:x3; val_offset:97785*0 + 3*339*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 97785*0 + 3*339*FLEN/8, x4, x1, x2)

inst_32596:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x22559e and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x0d and fm3 == 0x7ffe00 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f22559e; op2val:0x80000000;
op3val:0x86fffe00; valaddr_reg:x3; val_offset:97788*0 + 3*340*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 97788*0 + 3*340*FLEN/8, x4, x1, x2)

inst_32597:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x22559e and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x0d and fm3 == 0x7fff00 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f22559e; op2val:0x80000000;
op3val:0x86ffff00; valaddr_reg:x3; val_offset:97791*0 + 3*341*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 97791*0 + 3*341*FLEN/8, x4, x1, x2)

inst_32598:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x22559e and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x0d and fm3 == 0x7fff80 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f22559e; op2val:0x80000000;
op3val:0x86ffff80; valaddr_reg:x3; val_offset:97794*0 + 3*342*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 97794*0 + 3*342*FLEN/8, x4, x1, x2)

inst_32599:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x22559e and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x0d and fm3 == 0x7fffc0 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f22559e; op2val:0x80000000;
op3val:0x86ffffc0; valaddr_reg:x3; val_offset:97797*0 + 3*343*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 97797*0 + 3*343*FLEN/8, x4, x1, x2)

inst_32600:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x22559e and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x0d and fm3 == 0x7fffe0 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f22559e; op2val:0x80000000;
op3val:0x86ffffe0; valaddr_reg:x3; val_offset:97800*0 + 3*344*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 97800*0 + 3*344*FLEN/8, x4, x1, x2)

inst_32601:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x22559e and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x0d and fm3 == 0x7ffff0 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f22559e; op2val:0x80000000;
op3val:0x86fffff0; valaddr_reg:x3; val_offset:97803*0 + 3*345*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 97803*0 + 3*345*FLEN/8, x4, x1, x2)

inst_32602:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x22559e and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x0d and fm3 == 0x7ffff8 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f22559e; op2val:0x80000000;
op3val:0x86fffff8; valaddr_reg:x3; val_offset:97806*0 + 3*346*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 97806*0 + 3*346*FLEN/8, x4, x1, x2)

inst_32603:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x22559e and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x0d and fm3 == 0x7ffffc and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f22559e; op2val:0x80000000;
op3val:0x86fffffc; valaddr_reg:x3; val_offset:97809*0 + 3*347*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 97809*0 + 3*347*FLEN/8, x4, x1, x2)

inst_32604:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x22559e and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x0d and fm3 == 0x7ffffe and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f22559e; op2val:0x80000000;
op3val:0x86fffffe; valaddr_reg:x3; val_offset:97812*0 + 3*348*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 97812*0 + 3*348*FLEN/8, x4, x1, x2)

inst_32605:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x22559e and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x0d and fm3 == 0x7fffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f22559e; op2val:0x80000000;
op3val:0x86ffffff; valaddr_reg:x3; val_offset:97815*0 + 3*349*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 97815*0 + 3*349*FLEN/8, x4, x1, x2)

inst_32606:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x228047 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x326976 and fs3 == 1 and fe3 == 0x7f and fm3 == 0x000001 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f228047; op2val:0x80326976;
op3val:0xbf800001; valaddr_reg:x3; val_offset:97818*0 + 3*350*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 97818*0 + 3*350*FLEN/8, x4, x1, x2)

inst_32607:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x228047 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x326976 and fs3 == 1 and fe3 == 0x7f and fm3 == 0x000003 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f228047; op2val:0x80326976;
op3val:0xbf800003; valaddr_reg:x3; val_offset:97821*0 + 3*351*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 97821*0 + 3*351*FLEN/8, x4, x1, x2)

inst_32608:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x228047 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x326976 and fs3 == 1 and fe3 == 0x7f and fm3 == 0x000007 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f228047; op2val:0x80326976;
op3val:0xbf800007; valaddr_reg:x3; val_offset:97824*0 + 3*352*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 97824*0 + 3*352*FLEN/8, x4, x1, x2)

inst_32609:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x228047 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x326976 and fs3 == 1 and fe3 == 0x7f and fm3 == 0x199999 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f228047; op2val:0x80326976;
op3val:0xbf999999; valaddr_reg:x3; val_offset:97827*0 + 3*353*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 97827*0 + 3*353*FLEN/8, x4, x1, x2)

inst_32610:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x228047 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x326976 and fs3 == 1 and fe3 == 0x7f and fm3 == 0x249249 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f228047; op2val:0x80326976;
op3val:0xbfa49249; valaddr_reg:x3; val_offset:97830*0 + 3*354*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 97830*0 + 3*354*FLEN/8, x4, x1, x2)

inst_32611:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x228047 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x326976 and fs3 == 1 and fe3 == 0x7f and fm3 == 0x333333 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f228047; op2val:0x80326976;
op3val:0xbfb33333; valaddr_reg:x3; val_offset:97833*0 + 3*355*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 97833*0 + 3*355*FLEN/8, x4, x1, x2)

inst_32612:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x228047 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x326976 and fs3 == 1 and fe3 == 0x7f and fm3 == 0x36db6d and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f228047; op2val:0x80326976;
op3val:0xbfb6db6d; valaddr_reg:x3; val_offset:97836*0 + 3*356*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 97836*0 + 3*356*FLEN/8, x4, x1, x2)

inst_32613:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x228047 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x326976 and fs3 == 1 and fe3 == 0x7f and fm3 == 0x3bbbbb and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f228047; op2val:0x80326976;
op3val:0xbfbbbbbb; valaddr_reg:x3; val_offset:97839*0 + 3*357*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 97839*0 + 3*357*FLEN/8, x4, x1, x2)

inst_32614:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x228047 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x326976 and fs3 == 1 and fe3 == 0x7f and fm3 == 0x444444 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f228047; op2val:0x80326976;
op3val:0xbfc44444; valaddr_reg:x3; val_offset:97842*0 + 3*358*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 97842*0 + 3*358*FLEN/8, x4, x1, x2)

inst_32615:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x228047 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x326976 and fs3 == 1 and fe3 == 0x7f and fm3 == 0x4ccccc and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f228047; op2val:0x80326976;
op3val:0xbfcccccc; valaddr_reg:x3; val_offset:97845*0 + 3*359*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 97845*0 + 3*359*FLEN/8, x4, x1, x2)

inst_32616:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x228047 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x326976 and fs3 == 1 and fe3 == 0x7f and fm3 == 0x5b6db6 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f228047; op2val:0x80326976;
op3val:0xbfdb6db6; valaddr_reg:x3; val_offset:97848*0 + 3*360*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 97848*0 + 3*360*FLEN/8, x4, x1, x2)

inst_32617:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x228047 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x326976 and fs3 == 1 and fe3 == 0x7f and fm3 == 0x666666 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f228047; op2val:0x80326976;
op3val:0xbfe66666; valaddr_reg:x3; val_offset:97851*0 + 3*361*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 97851*0 + 3*361*FLEN/8, x4, x1, x2)

inst_32618:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x228047 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x326976 and fs3 == 1 and fe3 == 0x7f and fm3 == 0x6db6db and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f228047; op2val:0x80326976;
op3val:0xbfedb6db; valaddr_reg:x3; val_offset:97854*0 + 3*362*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 97854*0 + 3*362*FLEN/8, x4, x1, x2)

inst_32619:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x228047 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x326976 and fs3 == 1 and fe3 == 0x7f and fm3 == 0x7ffff8 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f228047; op2val:0x80326976;
op3val:0xbffffff8; valaddr_reg:x3; val_offset:97857*0 + 3*363*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 97857*0 + 3*363*FLEN/8, x4, x1, x2)

inst_32620:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x228047 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x326976 and fs3 == 1 and fe3 == 0x7f and fm3 == 0x7ffffc and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f228047; op2val:0x80326976;
op3val:0xbffffffc; valaddr_reg:x3; val_offset:97860*0 + 3*364*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 97860*0 + 3*364*FLEN/8, x4, x1, x2)

inst_32621:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x228047 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x326976 and fs3 == 1 and fe3 == 0x7f and fm3 == 0x7ffffe and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f228047; op2val:0x80326976;
op3val:0xbffffffe; valaddr_reg:x3; val_offset:97863*0 + 3*365*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 97863*0 + 3*365*FLEN/8, x4, x1, x2)

inst_32622:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x228047 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x326976 and fs3 == 1 and fe3 == 0x8e and fm3 == 0x000000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f228047; op2val:0x80326976;
op3val:0xc7000000; valaddr_reg:x3; val_offset:97866*0 + 3*366*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 97866*0 + 3*366*FLEN/8, x4, x1, x2)

inst_32623:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x228047 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x326976 and fs3 == 1 and fe3 == 0x8e and fm3 == 0x000001 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f228047; op2val:0x80326976;
op3val:0xc7000001; valaddr_reg:x3; val_offset:97869*0 + 3*367*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 97869*0 + 3*367*FLEN/8, x4, x1, x2)

inst_32624:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x228047 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x326976 and fs3 == 1 and fe3 == 0x8e and fm3 == 0x000003 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f228047; op2val:0x80326976;
op3val:0xc7000003; valaddr_reg:x3; val_offset:97872*0 + 3*368*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 97872*0 + 3*368*FLEN/8, x4, x1, x2)

inst_32625:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x228047 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x326976 and fs3 == 1 and fe3 == 0x8e and fm3 == 0x000007 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f228047; op2val:0x80326976;
op3val:0xc7000007; valaddr_reg:x3; val_offset:97875*0 + 3*369*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 97875*0 + 3*369*FLEN/8, x4, x1, x2)

inst_32626:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x228047 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x326976 and fs3 == 1 and fe3 == 0x8e and fm3 == 0x00000f and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f228047; op2val:0x80326976;
op3val:0xc700000f; valaddr_reg:x3; val_offset:97878*0 + 3*370*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 97878*0 + 3*370*FLEN/8, x4, x1, x2)

inst_32627:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x228047 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x326976 and fs3 == 1 and fe3 == 0x8e and fm3 == 0x00001f and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f228047; op2val:0x80326976;
op3val:0xc700001f; valaddr_reg:x3; val_offset:97881*0 + 3*371*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 97881*0 + 3*371*FLEN/8, x4, x1, x2)

inst_32628:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x228047 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x326976 and fs3 == 1 and fe3 == 0x8e and fm3 == 0x00003f and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f228047; op2val:0x80326976;
op3val:0xc700003f; valaddr_reg:x3; val_offset:97884*0 + 3*372*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 97884*0 + 3*372*FLEN/8, x4, x1, x2)

inst_32629:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x228047 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x326976 and fs3 == 1 and fe3 == 0x8e and fm3 == 0x00007f and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f228047; op2val:0x80326976;
op3val:0xc700007f; valaddr_reg:x3; val_offset:97887*0 + 3*373*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 97887*0 + 3*373*FLEN/8, x4, x1, x2)

inst_32630:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x228047 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x326976 and fs3 == 1 and fe3 == 0x8e and fm3 == 0x0000ff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f228047; op2val:0x80326976;
op3val:0xc70000ff; valaddr_reg:x3; val_offset:97890*0 + 3*374*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 97890*0 + 3*374*FLEN/8, x4, x1, x2)

inst_32631:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x228047 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x326976 and fs3 == 1 and fe3 == 0x8e and fm3 == 0x0001ff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f228047; op2val:0x80326976;
op3val:0xc70001ff; valaddr_reg:x3; val_offset:97893*0 + 3*375*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 97893*0 + 3*375*FLEN/8, x4, x1, x2)

inst_32632:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x228047 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x326976 and fs3 == 1 and fe3 == 0x8e and fm3 == 0x0003ff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f228047; op2val:0x80326976;
op3val:0xc70003ff; valaddr_reg:x3; val_offset:97896*0 + 3*376*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 97896*0 + 3*376*FLEN/8, x4, x1, x2)

inst_32633:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x228047 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x326976 and fs3 == 1 and fe3 == 0x8e and fm3 == 0x0007ff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f228047; op2val:0x80326976;
op3val:0xc70007ff; valaddr_reg:x3; val_offset:97899*0 + 3*377*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 97899*0 + 3*377*FLEN/8, x4, x1, x2)

inst_32634:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x228047 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x326976 and fs3 == 1 and fe3 == 0x8e and fm3 == 0x000fff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f228047; op2val:0x80326976;
op3val:0xc7000fff; valaddr_reg:x3; val_offset:97902*0 + 3*378*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 97902*0 + 3*378*FLEN/8, x4, x1, x2)

inst_32635:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x228047 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x326976 and fs3 == 1 and fe3 == 0x8e and fm3 == 0x001fff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f228047; op2val:0x80326976;
op3val:0xc7001fff; valaddr_reg:x3; val_offset:97905*0 + 3*379*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 97905*0 + 3*379*FLEN/8, x4, x1, x2)

inst_32636:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x228047 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x326976 and fs3 == 1 and fe3 == 0x8e and fm3 == 0x003fff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f228047; op2val:0x80326976;
op3val:0xc7003fff; valaddr_reg:x3; val_offset:97908*0 + 3*380*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 97908*0 + 3*380*FLEN/8, x4, x1, x2)

inst_32637:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x228047 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x326976 and fs3 == 1 and fe3 == 0x8e and fm3 == 0x007fff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f228047; op2val:0x80326976;
op3val:0xc7007fff; valaddr_reg:x3; val_offset:97911*0 + 3*381*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 97911*0 + 3*381*FLEN/8, x4, x1, x2)

inst_32638:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x228047 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x326976 and fs3 == 1 and fe3 == 0x8e and fm3 == 0x00ffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f228047; op2val:0x80326976;
op3val:0xc700ffff; valaddr_reg:x3; val_offset:97914*0 + 3*382*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 97914*0 + 3*382*FLEN/8, x4, x1, x2)

inst_32639:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x228047 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x326976 and fs3 == 1 and fe3 == 0x8e and fm3 == 0x01ffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f228047; op2val:0x80326976;
op3val:0xc701ffff; valaddr_reg:x3; val_offset:97917*0 + 3*383*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 97917*0 + 3*383*FLEN/8, x4, x1, x2)
RVTEST_SIGBASE(x1,signature_x1_4)

inst_32640:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x228047 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x326976 and fs3 == 1 and fe3 == 0x8e and fm3 == 0x03ffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f228047; op2val:0x80326976;
op3val:0xc703ffff; valaddr_reg:x3; val_offset:97920*0 + 3*384*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 97920*0 + 3*384*FLEN/8, x4, x1, x2)

inst_32641:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x228047 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x326976 and fs3 == 1 and fe3 == 0x8e and fm3 == 0x07ffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f228047; op2val:0x80326976;
op3val:0xc707ffff; valaddr_reg:x3; val_offset:97923*0 + 3*385*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 97923*0 + 3*385*FLEN/8, x4, x1, x2)

inst_32642:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x228047 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x326976 and fs3 == 1 and fe3 == 0x8e and fm3 == 0x0fffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f228047; op2val:0x80326976;
op3val:0xc70fffff; valaddr_reg:x3; val_offset:97926*0 + 3*386*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 97926*0 + 3*386*FLEN/8, x4, x1, x2)

inst_32643:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x228047 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x326976 and fs3 == 1 and fe3 == 0x8e and fm3 == 0x1fffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f228047; op2val:0x80326976;
op3val:0xc71fffff; valaddr_reg:x3; val_offset:97929*0 + 3*387*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 97929*0 + 3*387*FLEN/8, x4, x1, x2)

inst_32644:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x228047 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x326976 and fs3 == 1 and fe3 == 0x8e and fm3 == 0x3fffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f228047; op2val:0x80326976;
op3val:0xc73fffff; valaddr_reg:x3; val_offset:97932*0 + 3*388*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 97932*0 + 3*388*FLEN/8, x4, x1, x2)

inst_32645:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x228047 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x326976 and fs3 == 1 and fe3 == 0x8e and fm3 == 0x400000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f228047; op2val:0x80326976;
op3val:0xc7400000; valaddr_reg:x3; val_offset:97935*0 + 3*389*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 97935*0 + 3*389*FLEN/8, x4, x1, x2)

inst_32646:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x228047 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x326976 and fs3 == 1 and fe3 == 0x8e and fm3 == 0x600000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f228047; op2val:0x80326976;
op3val:0xc7600000; valaddr_reg:x3; val_offset:97938*0 + 3*390*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 97938*0 + 3*390*FLEN/8, x4, x1, x2)

inst_32647:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x228047 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x326976 and fs3 == 1 and fe3 == 0x8e and fm3 == 0x700000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f228047; op2val:0x80326976;
op3val:0xc7700000; valaddr_reg:x3; val_offset:97941*0 + 3*391*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 97941*0 + 3*391*FLEN/8, x4, x1, x2)

inst_32648:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x228047 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x326976 and fs3 == 1 and fe3 == 0x8e and fm3 == 0x780000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f228047; op2val:0x80326976;
op3val:0xc7780000; valaddr_reg:x3; val_offset:97944*0 + 3*392*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 97944*0 + 3*392*FLEN/8, x4, x1, x2)

inst_32649:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x228047 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x326976 and fs3 == 1 and fe3 == 0x8e and fm3 == 0x7c0000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f228047; op2val:0x80326976;
op3val:0xc77c0000; valaddr_reg:x3; val_offset:97947*0 + 3*393*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 97947*0 + 3*393*FLEN/8, x4, x1, x2)

inst_32650:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x228047 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x326976 and fs3 == 1 and fe3 == 0x8e and fm3 == 0x7e0000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f228047; op2val:0x80326976;
op3val:0xc77e0000; valaddr_reg:x3; val_offset:97950*0 + 3*394*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 97950*0 + 3*394*FLEN/8, x4, x1, x2)

inst_32651:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x228047 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x326976 and fs3 == 1 and fe3 == 0x8e and fm3 == 0x7f0000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f228047; op2val:0x80326976;
op3val:0xc77f0000; valaddr_reg:x3; val_offset:97953*0 + 3*395*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 97953*0 + 3*395*FLEN/8, x4, x1, x2)

inst_32652:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x228047 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x326976 and fs3 == 1 and fe3 == 0x8e and fm3 == 0x7f8000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f228047; op2val:0x80326976;
op3val:0xc77f8000; valaddr_reg:x3; val_offset:97956*0 + 3*396*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 97956*0 + 3*396*FLEN/8, x4, x1, x2)

inst_32653:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x228047 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x326976 and fs3 == 1 and fe3 == 0x8e and fm3 == 0x7fc000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f228047; op2val:0x80326976;
op3val:0xc77fc000; valaddr_reg:x3; val_offset:97959*0 + 3*397*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 97959*0 + 3*397*FLEN/8, x4, x1, x2)

inst_32654:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x228047 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x326976 and fs3 == 1 and fe3 == 0x8e and fm3 == 0x7fe000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f228047; op2val:0x80326976;
op3val:0xc77fe000; valaddr_reg:x3; val_offset:97962*0 + 3*398*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 97962*0 + 3*398*FLEN/8, x4, x1, x2)

inst_32655:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x228047 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x326976 and fs3 == 1 and fe3 == 0x8e and fm3 == 0x7ff000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f228047; op2val:0x80326976;
op3val:0xc77ff000; valaddr_reg:x3; val_offset:97965*0 + 3*399*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 97965*0 + 3*399*FLEN/8, x4, x1, x2)

inst_32656:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x228047 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x326976 and fs3 == 1 and fe3 == 0x8e and fm3 == 0x7ff800 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f228047; op2val:0x80326976;
op3val:0xc77ff800; valaddr_reg:x3; val_offset:97968*0 + 3*400*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 97968*0 + 3*400*FLEN/8, x4, x1, x2)

inst_32657:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x228047 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x326976 and fs3 == 1 and fe3 == 0x8e and fm3 == 0x7ffc00 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f228047; op2val:0x80326976;
op3val:0xc77ffc00; valaddr_reg:x3; val_offset:97971*0 + 3*401*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 97971*0 + 3*401*FLEN/8, x4, x1, x2)

inst_32658:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x228047 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x326976 and fs3 == 1 and fe3 == 0x8e and fm3 == 0x7ffe00 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f228047; op2val:0x80326976;
op3val:0xc77ffe00; valaddr_reg:x3; val_offset:97974*0 + 3*402*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 97974*0 + 3*402*FLEN/8, x4, x1, x2)

inst_32659:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x228047 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x326976 and fs3 == 1 and fe3 == 0x8e and fm3 == 0x7fff00 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f228047; op2val:0x80326976;
op3val:0xc77fff00; valaddr_reg:x3; val_offset:97977*0 + 3*403*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 97977*0 + 3*403*FLEN/8, x4, x1, x2)

inst_32660:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x228047 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x326976 and fs3 == 1 and fe3 == 0x8e and fm3 == 0x7fff80 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f228047; op2val:0x80326976;
op3val:0xc77fff80; valaddr_reg:x3; val_offset:97980*0 + 3*404*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 97980*0 + 3*404*FLEN/8, x4, x1, x2)

inst_32661:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x228047 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x326976 and fs3 == 1 and fe3 == 0x8e and fm3 == 0x7fffc0 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f228047; op2val:0x80326976;
op3val:0xc77fffc0; valaddr_reg:x3; val_offset:97983*0 + 3*405*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 97983*0 + 3*405*FLEN/8, x4, x1, x2)

inst_32662:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x228047 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x326976 and fs3 == 1 and fe3 == 0x8e and fm3 == 0x7fffe0 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f228047; op2val:0x80326976;
op3val:0xc77fffe0; valaddr_reg:x3; val_offset:97986*0 + 3*406*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 97986*0 + 3*406*FLEN/8, x4, x1, x2)

inst_32663:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x228047 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x326976 and fs3 == 1 and fe3 == 0x8e and fm3 == 0x7ffff0 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f228047; op2val:0x80326976;
op3val:0xc77ffff0; valaddr_reg:x3; val_offset:97989*0 + 3*407*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 97989*0 + 3*407*FLEN/8, x4, x1, x2)

inst_32664:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x228047 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x326976 and fs3 == 1 and fe3 == 0x8e and fm3 == 0x7ffff8 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f228047; op2val:0x80326976;
op3val:0xc77ffff8; valaddr_reg:x3; val_offset:97992*0 + 3*408*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 97992*0 + 3*408*FLEN/8, x4, x1, x2)

inst_32665:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x228047 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x326976 and fs3 == 1 and fe3 == 0x8e and fm3 == 0x7ffffc and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f228047; op2val:0x80326976;
op3val:0xc77ffffc; valaddr_reg:x3; val_offset:97995*0 + 3*409*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 97995*0 + 3*409*FLEN/8, x4, x1, x2)

inst_32666:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x228047 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x326976 and fs3 == 1 and fe3 == 0x8e and fm3 == 0x7ffffe and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f228047; op2val:0x80326976;
op3val:0xc77ffffe; valaddr_reg:x3; val_offset:97998*0 + 3*410*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 97998*0 + 3*410*FLEN/8, x4, x1, x2)

inst_32667:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x228047 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x326976 and fs3 == 1 and fe3 == 0x8e and fm3 == 0x7fffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f228047; op2val:0x80326976;
op3val:0xc77fffff; valaddr_reg:x3; val_offset:98001*0 + 3*411*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 98001*0 + 3*411*FLEN/8, x4, x1, x2)

inst_32668:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x231790 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x323ab3 and fs3 == 1 and fe3 == 0x7f and fm3 == 0x000001 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f231790; op2val:0x80323ab3;
op3val:0xbf800001; valaddr_reg:x3; val_offset:98004*0 + 3*412*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 98004*0 + 3*412*FLEN/8, x4, x1, x2)

inst_32669:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x231790 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x323ab3 and fs3 == 1 and fe3 == 0x7f and fm3 == 0x000003 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f231790; op2val:0x80323ab3;
op3val:0xbf800003; valaddr_reg:x3; val_offset:98007*0 + 3*413*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 98007*0 + 3*413*FLEN/8, x4, x1, x2)

inst_32670:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x231790 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x323ab3 and fs3 == 1 and fe3 == 0x7f and fm3 == 0x000007 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f231790; op2val:0x80323ab3;
op3val:0xbf800007; valaddr_reg:x3; val_offset:98010*0 + 3*414*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 98010*0 + 3*414*FLEN/8, x4, x1, x2)

inst_32671:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x231790 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x323ab3 and fs3 == 1 and fe3 == 0x7f and fm3 == 0x199999 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f231790; op2val:0x80323ab3;
op3val:0xbf999999; valaddr_reg:x3; val_offset:98013*0 + 3*415*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 98013*0 + 3*415*FLEN/8, x4, x1, x2)

inst_32672:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x231790 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x323ab3 and fs3 == 1 and fe3 == 0x7f and fm3 == 0x249249 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f231790; op2val:0x80323ab3;
op3val:0xbfa49249; valaddr_reg:x3; val_offset:98016*0 + 3*416*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 98016*0 + 3*416*FLEN/8, x4, x1, x2)

inst_32673:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x231790 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x323ab3 and fs3 == 1 and fe3 == 0x7f and fm3 == 0x333333 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f231790; op2val:0x80323ab3;
op3val:0xbfb33333; valaddr_reg:x3; val_offset:98019*0 + 3*417*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 98019*0 + 3*417*FLEN/8, x4, x1, x2)

inst_32674:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x231790 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x323ab3 and fs3 == 1 and fe3 == 0x7f and fm3 == 0x36db6d and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f231790; op2val:0x80323ab3;
op3val:0xbfb6db6d; valaddr_reg:x3; val_offset:98022*0 + 3*418*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 98022*0 + 3*418*FLEN/8, x4, x1, x2)

inst_32675:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x231790 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x323ab3 and fs3 == 1 and fe3 == 0x7f and fm3 == 0x3bbbbb and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f231790; op2val:0x80323ab3;
op3val:0xbfbbbbbb; valaddr_reg:x3; val_offset:98025*0 + 3*419*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 98025*0 + 3*419*FLEN/8, x4, x1, x2)

inst_32676:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x231790 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x323ab3 and fs3 == 1 and fe3 == 0x7f and fm3 == 0x444444 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f231790; op2val:0x80323ab3;
op3val:0xbfc44444; valaddr_reg:x3; val_offset:98028*0 + 3*420*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 98028*0 + 3*420*FLEN/8, x4, x1, x2)

inst_32677:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x231790 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x323ab3 and fs3 == 1 and fe3 == 0x7f and fm3 == 0x4ccccc and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f231790; op2val:0x80323ab3;
op3val:0xbfcccccc; valaddr_reg:x3; val_offset:98031*0 + 3*421*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 98031*0 + 3*421*FLEN/8, x4, x1, x2)

inst_32678:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x231790 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x323ab3 and fs3 == 1 and fe3 == 0x7f and fm3 == 0x5b6db6 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f231790; op2val:0x80323ab3;
op3val:0xbfdb6db6; valaddr_reg:x3; val_offset:98034*0 + 3*422*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 98034*0 + 3*422*FLEN/8, x4, x1, x2)

inst_32679:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x231790 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x323ab3 and fs3 == 1 and fe3 == 0x7f and fm3 == 0x666666 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f231790; op2val:0x80323ab3;
op3val:0xbfe66666; valaddr_reg:x3; val_offset:98037*0 + 3*423*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 98037*0 + 3*423*FLEN/8, x4, x1, x2)

inst_32680:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x231790 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x323ab3 and fs3 == 1 and fe3 == 0x7f and fm3 == 0x6db6db and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f231790; op2val:0x80323ab3;
op3val:0xbfedb6db; valaddr_reg:x3; val_offset:98040*0 + 3*424*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 98040*0 + 3*424*FLEN/8, x4, x1, x2)

inst_32681:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x231790 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x323ab3 and fs3 == 1 and fe3 == 0x7f and fm3 == 0x7ffff8 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f231790; op2val:0x80323ab3;
op3val:0xbffffff8; valaddr_reg:x3; val_offset:98043*0 + 3*425*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 98043*0 + 3*425*FLEN/8, x4, x1, x2)

inst_32682:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x231790 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x323ab3 and fs3 == 1 and fe3 == 0x7f and fm3 == 0x7ffffc and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f231790; op2val:0x80323ab3;
op3val:0xbffffffc; valaddr_reg:x3; val_offset:98046*0 + 3*426*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 98046*0 + 3*426*FLEN/8, x4, x1, x2)

inst_32683:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x231790 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x323ab3 and fs3 == 1 and fe3 == 0x7f and fm3 == 0x7ffffe and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f231790; op2val:0x80323ab3;
op3val:0xbffffffe; valaddr_reg:x3; val_offset:98049*0 + 3*427*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 98049*0 + 3*427*FLEN/8, x4, x1, x2)

inst_32684:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x231790 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x323ab3 and fs3 == 1 and fe3 == 0x8d and fm3 == 0x000000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f231790; op2val:0x80323ab3;
op3val:0xc6800000; valaddr_reg:x3; val_offset:98052*0 + 3*428*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 98052*0 + 3*428*FLEN/8, x4, x1, x2)

inst_32685:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x231790 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x323ab3 and fs3 == 1 and fe3 == 0x8d and fm3 == 0x000001 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f231790; op2val:0x80323ab3;
op3val:0xc6800001; valaddr_reg:x3; val_offset:98055*0 + 3*429*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 98055*0 + 3*429*FLEN/8, x4, x1, x2)

inst_32686:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x231790 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x323ab3 and fs3 == 1 and fe3 == 0x8d and fm3 == 0x000003 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f231790; op2val:0x80323ab3;
op3val:0xc6800003; valaddr_reg:x3; val_offset:98058*0 + 3*430*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 98058*0 + 3*430*FLEN/8, x4, x1, x2)

inst_32687:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x231790 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x323ab3 and fs3 == 1 and fe3 == 0x8d and fm3 == 0x000007 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f231790; op2val:0x80323ab3;
op3val:0xc6800007; valaddr_reg:x3; val_offset:98061*0 + 3*431*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 98061*0 + 3*431*FLEN/8, x4, x1, x2)

inst_32688:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x231790 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x323ab3 and fs3 == 1 and fe3 == 0x8d and fm3 == 0x00000f and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f231790; op2val:0x80323ab3;
op3val:0xc680000f; valaddr_reg:x3; val_offset:98064*0 + 3*432*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 98064*0 + 3*432*FLEN/8, x4, x1, x2)

inst_32689:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x231790 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x323ab3 and fs3 == 1 and fe3 == 0x8d and fm3 == 0x00001f and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f231790; op2val:0x80323ab3;
op3val:0xc680001f; valaddr_reg:x3; val_offset:98067*0 + 3*433*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 98067*0 + 3*433*FLEN/8, x4, x1, x2)

inst_32690:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x231790 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x323ab3 and fs3 == 1 and fe3 == 0x8d and fm3 == 0x00003f and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f231790; op2val:0x80323ab3;
op3val:0xc680003f; valaddr_reg:x3; val_offset:98070*0 + 3*434*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 98070*0 + 3*434*FLEN/8, x4, x1, x2)

inst_32691:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x231790 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x323ab3 and fs3 == 1 and fe3 == 0x8d and fm3 == 0x00007f and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f231790; op2val:0x80323ab3;
op3val:0xc680007f; valaddr_reg:x3; val_offset:98073*0 + 3*435*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 98073*0 + 3*435*FLEN/8, x4, x1, x2)

inst_32692:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x231790 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x323ab3 and fs3 == 1 and fe3 == 0x8d and fm3 == 0x0000ff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f231790; op2val:0x80323ab3;
op3val:0xc68000ff; valaddr_reg:x3; val_offset:98076*0 + 3*436*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 98076*0 + 3*436*FLEN/8, x4, x1, x2)

inst_32693:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x231790 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x323ab3 and fs3 == 1 and fe3 == 0x8d and fm3 == 0x0001ff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f231790; op2val:0x80323ab3;
op3val:0xc68001ff; valaddr_reg:x3; val_offset:98079*0 + 3*437*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 98079*0 + 3*437*FLEN/8, x4, x1, x2)

inst_32694:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x231790 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x323ab3 and fs3 == 1 and fe3 == 0x8d and fm3 == 0x0003ff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f231790; op2val:0x80323ab3;
op3val:0xc68003ff; valaddr_reg:x3; val_offset:98082*0 + 3*438*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 98082*0 + 3*438*FLEN/8, x4, x1, x2)

inst_32695:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x231790 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x323ab3 and fs3 == 1 and fe3 == 0x8d and fm3 == 0x0007ff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f231790; op2val:0x80323ab3;
op3val:0xc68007ff; valaddr_reg:x3; val_offset:98085*0 + 3*439*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 98085*0 + 3*439*FLEN/8, x4, x1, x2)

inst_32696:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x231790 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x323ab3 and fs3 == 1 and fe3 == 0x8d and fm3 == 0x000fff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f231790; op2val:0x80323ab3;
op3val:0xc6800fff; valaddr_reg:x3; val_offset:98088*0 + 3*440*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 98088*0 + 3*440*FLEN/8, x4, x1, x2)

inst_32697:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x231790 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x323ab3 and fs3 == 1 and fe3 == 0x8d and fm3 == 0x001fff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f231790; op2val:0x80323ab3;
op3val:0xc6801fff; valaddr_reg:x3; val_offset:98091*0 + 3*441*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 98091*0 + 3*441*FLEN/8, x4, x1, x2)

inst_32698:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x231790 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x323ab3 and fs3 == 1 and fe3 == 0x8d and fm3 == 0x003fff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f231790; op2val:0x80323ab3;
op3val:0xc6803fff; valaddr_reg:x3; val_offset:98094*0 + 3*442*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 98094*0 + 3*442*FLEN/8, x4, x1, x2)

inst_32699:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x231790 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x323ab3 and fs3 == 1 and fe3 == 0x8d and fm3 == 0x007fff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f231790; op2val:0x80323ab3;
op3val:0xc6807fff; valaddr_reg:x3; val_offset:98097*0 + 3*443*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 98097*0 + 3*443*FLEN/8, x4, x1, x2)

inst_32700:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x231790 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x323ab3 and fs3 == 1 and fe3 == 0x8d and fm3 == 0x00ffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f231790; op2val:0x80323ab3;
op3val:0xc680ffff; valaddr_reg:x3; val_offset:98100*0 + 3*444*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 98100*0 + 3*444*FLEN/8, x4, x1, x2)

inst_32701:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x231790 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x323ab3 and fs3 == 1 and fe3 == 0x8d and fm3 == 0x01ffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f231790; op2val:0x80323ab3;
op3val:0xc681ffff; valaddr_reg:x3; val_offset:98103*0 + 3*445*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 98103*0 + 3*445*FLEN/8, x4, x1, x2)

inst_32702:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x231790 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x323ab3 and fs3 == 1 and fe3 == 0x8d and fm3 == 0x03ffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f231790; op2val:0x80323ab3;
op3val:0xc683ffff; valaddr_reg:x3; val_offset:98106*0 + 3*446*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 98106*0 + 3*446*FLEN/8, x4, x1, x2)

inst_32703:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x231790 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x323ab3 and fs3 == 1 and fe3 == 0x8d and fm3 == 0x07ffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f231790; op2val:0x80323ab3;
op3val:0xc687ffff; valaddr_reg:x3; val_offset:98109*0 + 3*447*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 98109*0 + 3*447*FLEN/8, x4, x1, x2)

inst_32704:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x231790 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x323ab3 and fs3 == 1 and fe3 == 0x8d and fm3 == 0x0fffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f231790; op2val:0x80323ab3;
op3val:0xc68fffff; valaddr_reg:x3; val_offset:98112*0 + 3*448*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 98112*0 + 3*448*FLEN/8, x4, x1, x2)

inst_32705:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x231790 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x323ab3 and fs3 == 1 and fe3 == 0x8d and fm3 == 0x1fffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f231790; op2val:0x80323ab3;
op3val:0xc69fffff; valaddr_reg:x3; val_offset:98115*0 + 3*449*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 98115*0 + 3*449*FLEN/8, x4, x1, x2)

inst_32706:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x231790 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x323ab3 and fs3 == 1 and fe3 == 0x8d and fm3 == 0x3fffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f231790; op2val:0x80323ab3;
op3val:0xc6bfffff; valaddr_reg:x3; val_offset:98118*0 + 3*450*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 98118*0 + 3*450*FLEN/8, x4, x1, x2)

inst_32707:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x231790 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x323ab3 and fs3 == 1 and fe3 == 0x8d and fm3 == 0x400000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f231790; op2val:0x80323ab3;
op3val:0xc6c00000; valaddr_reg:x3; val_offset:98121*0 + 3*451*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 98121*0 + 3*451*FLEN/8, x4, x1, x2)

inst_32708:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x231790 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x323ab3 and fs3 == 1 and fe3 == 0x8d and fm3 == 0x600000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f231790; op2val:0x80323ab3;
op3val:0xc6e00000; valaddr_reg:x3; val_offset:98124*0 + 3*452*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 98124*0 + 3*452*FLEN/8, x4, x1, x2)

inst_32709:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x231790 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x323ab3 and fs3 == 1 and fe3 == 0x8d and fm3 == 0x700000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f231790; op2val:0x80323ab3;
op3val:0xc6f00000; valaddr_reg:x3; val_offset:98127*0 + 3*453*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 98127*0 + 3*453*FLEN/8, x4, x1, x2)

inst_32710:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x231790 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x323ab3 and fs3 == 1 and fe3 == 0x8d and fm3 == 0x780000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f231790; op2val:0x80323ab3;
op3val:0xc6f80000; valaddr_reg:x3; val_offset:98130*0 + 3*454*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 98130*0 + 3*454*FLEN/8, x4, x1, x2)

inst_32711:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x231790 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x323ab3 and fs3 == 1 and fe3 == 0x8d and fm3 == 0x7c0000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f231790; op2val:0x80323ab3;
op3val:0xc6fc0000; valaddr_reg:x3; val_offset:98133*0 + 3*455*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 98133*0 + 3*455*FLEN/8, x4, x1, x2)

inst_32712:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x231790 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x323ab3 and fs3 == 1 and fe3 == 0x8d and fm3 == 0x7e0000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f231790; op2val:0x80323ab3;
op3val:0xc6fe0000; valaddr_reg:x3; val_offset:98136*0 + 3*456*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 98136*0 + 3*456*FLEN/8, x4, x1, x2)

inst_32713:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x231790 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x323ab3 and fs3 == 1 and fe3 == 0x8d and fm3 == 0x7f0000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f231790; op2val:0x80323ab3;
op3val:0xc6ff0000; valaddr_reg:x3; val_offset:98139*0 + 3*457*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 98139*0 + 3*457*FLEN/8, x4, x1, x2)

inst_32714:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x231790 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x323ab3 and fs3 == 1 and fe3 == 0x8d and fm3 == 0x7f8000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f231790; op2val:0x80323ab3;
op3val:0xc6ff8000; valaddr_reg:x3; val_offset:98142*0 + 3*458*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 98142*0 + 3*458*FLEN/8, x4, x1, x2)

inst_32715:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x231790 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x323ab3 and fs3 == 1 and fe3 == 0x8d and fm3 == 0x7fc000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f231790; op2val:0x80323ab3;
op3val:0xc6ffc000; valaddr_reg:x3; val_offset:98145*0 + 3*459*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 98145*0 + 3*459*FLEN/8, x4, x1, x2)

inst_32716:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x231790 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x323ab3 and fs3 == 1 and fe3 == 0x8d and fm3 == 0x7fe000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f231790; op2val:0x80323ab3;
op3val:0xc6ffe000; valaddr_reg:x3; val_offset:98148*0 + 3*460*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 98148*0 + 3*460*FLEN/8, x4, x1, x2)

inst_32717:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x231790 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x323ab3 and fs3 == 1 and fe3 == 0x8d and fm3 == 0x7ff000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f231790; op2val:0x80323ab3;
op3val:0xc6fff000; valaddr_reg:x3; val_offset:98151*0 + 3*461*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 98151*0 + 3*461*FLEN/8, x4, x1, x2)

inst_32718:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x231790 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x323ab3 and fs3 == 1 and fe3 == 0x8d and fm3 == 0x7ff800 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f231790; op2val:0x80323ab3;
op3val:0xc6fff800; valaddr_reg:x3; val_offset:98154*0 + 3*462*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 98154*0 + 3*462*FLEN/8, x4, x1, x2)

inst_32719:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x231790 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x323ab3 and fs3 == 1 and fe3 == 0x8d and fm3 == 0x7ffc00 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f231790; op2val:0x80323ab3;
op3val:0xc6fffc00; valaddr_reg:x3; val_offset:98157*0 + 3*463*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 98157*0 + 3*463*FLEN/8, x4, x1, x2)

inst_32720:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x231790 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x323ab3 and fs3 == 1 and fe3 == 0x8d and fm3 == 0x7ffe00 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f231790; op2val:0x80323ab3;
op3val:0xc6fffe00; valaddr_reg:x3; val_offset:98160*0 + 3*464*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 98160*0 + 3*464*FLEN/8, x4, x1, x2)

inst_32721:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x231790 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x323ab3 and fs3 == 1 and fe3 == 0x8d and fm3 == 0x7fff00 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f231790; op2val:0x80323ab3;
op3val:0xc6ffff00; valaddr_reg:x3; val_offset:98163*0 + 3*465*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 98163*0 + 3*465*FLEN/8, x4, x1, x2)

inst_32722:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x231790 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x323ab3 and fs3 == 1 and fe3 == 0x8d and fm3 == 0x7fff80 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f231790; op2val:0x80323ab3;
op3val:0xc6ffff80; valaddr_reg:x3; val_offset:98166*0 + 3*466*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 98166*0 + 3*466*FLEN/8, x4, x1, x2)

inst_32723:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x231790 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x323ab3 and fs3 == 1 and fe3 == 0x8d and fm3 == 0x7fffc0 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f231790; op2val:0x80323ab3;
op3val:0xc6ffffc0; valaddr_reg:x3; val_offset:98169*0 + 3*467*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 98169*0 + 3*467*FLEN/8, x4, x1, x2)

inst_32724:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x231790 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x323ab3 and fs3 == 1 and fe3 == 0x8d and fm3 == 0x7fffe0 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f231790; op2val:0x80323ab3;
op3val:0xc6ffffe0; valaddr_reg:x3; val_offset:98172*0 + 3*468*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 98172*0 + 3*468*FLEN/8, x4, x1, x2)

inst_32725:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x231790 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x323ab3 and fs3 == 1 and fe3 == 0x8d and fm3 == 0x7ffff0 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f231790; op2val:0x80323ab3;
op3val:0xc6fffff0; valaddr_reg:x3; val_offset:98175*0 + 3*469*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 98175*0 + 3*469*FLEN/8, x4, x1, x2)

inst_32726:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x231790 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x323ab3 and fs3 == 1 and fe3 == 0x8d and fm3 == 0x7ffff8 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f231790; op2val:0x80323ab3;
op3val:0xc6fffff8; valaddr_reg:x3; val_offset:98178*0 + 3*470*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 98178*0 + 3*470*FLEN/8, x4, x1, x2)

inst_32727:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x231790 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x323ab3 and fs3 == 1 and fe3 == 0x8d and fm3 == 0x7ffffc and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f231790; op2val:0x80323ab3;
op3val:0xc6fffffc; valaddr_reg:x3; val_offset:98181*0 + 3*471*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 98181*0 + 3*471*FLEN/8, x4, x1, x2)

inst_32728:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x231790 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x323ab3 and fs3 == 1 and fe3 == 0x8d and fm3 == 0x7ffffe and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f231790; op2val:0x80323ab3;
op3val:0xc6fffffe; valaddr_reg:x3; val_offset:98184*0 + 3*472*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 98184*0 + 3*472*FLEN/8, x4, x1, x2)

inst_32729:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x231790 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x323ab3 and fs3 == 1 and fe3 == 0x8d and fm3 == 0x7fffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f231790; op2val:0x80323ab3;
op3val:0xc6ffffff; valaddr_reg:x3; val_offset:98187*0 + 3*473*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 98187*0 + 3*473*FLEN/8, x4, x1, x2)

inst_32730:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x234a7c and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000001 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f234a7c; op2val:0x0;
op3val:0x1; valaddr_reg:x3; val_offset:98190*0 + 3*474*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 98190*0 + 3*474*FLEN/8, x4, x1, x2)

inst_32731:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x234a7c and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000003 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f234a7c; op2val:0x0;
op3val:0x3; valaddr_reg:x3; val_offset:98193*0 + 3*475*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 98193*0 + 3*475*FLEN/8, x4, x1, x2)

inst_32732:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x234a7c and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000007 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f234a7c; op2val:0x0;
op3val:0x7; valaddr_reg:x3; val_offset:98196*0 + 3*476*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 98196*0 + 3*476*FLEN/8, x4, x1, x2)

inst_32733:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x234a7c and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x199999 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f234a7c; op2val:0x0;
op3val:0x199999; valaddr_reg:x3; val_offset:98199*0 + 3*477*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 98199*0 + 3*477*FLEN/8, x4, x1, x2)

inst_32734:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x234a7c and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x249249 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f234a7c; op2val:0x0;
op3val:0x249249; valaddr_reg:x3; val_offset:98202*0 + 3*478*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 98202*0 + 3*478*FLEN/8, x4, x1, x2)

inst_32735:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x234a7c and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x333333 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f234a7c; op2val:0x0;
op3val:0x333333; valaddr_reg:x3; val_offset:98205*0 + 3*479*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 98205*0 + 3*479*FLEN/8, x4, x1, x2)

inst_32736:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x234a7c and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x36db6d and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f234a7c; op2val:0x0;
op3val:0x36db6d; valaddr_reg:x3; val_offset:98208*0 + 3*480*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 98208*0 + 3*480*FLEN/8, x4, x1, x2)

inst_32737:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x234a7c and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x3bbbbb and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f234a7c; op2val:0x0;
op3val:0x3bbbbb; valaddr_reg:x3; val_offset:98211*0 + 3*481*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 98211*0 + 3*481*FLEN/8, x4, x1, x2)

inst_32738:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x234a7c and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x444444 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f234a7c; op2val:0x0;
op3val:0x444444; valaddr_reg:x3; val_offset:98214*0 + 3*482*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 98214*0 + 3*482*FLEN/8, x4, x1, x2)

inst_32739:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x234a7c and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x4ccccc and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f234a7c; op2val:0x0;
op3val:0x4ccccc; valaddr_reg:x3; val_offset:98217*0 + 3*483*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 98217*0 + 3*483*FLEN/8, x4, x1, x2)

inst_32740:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x234a7c and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x5b6db6 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f234a7c; op2val:0x0;
op3val:0x5b6db6; valaddr_reg:x3; val_offset:98220*0 + 3*484*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 98220*0 + 3*484*FLEN/8, x4, x1, x2)

inst_32741:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x234a7c and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x666666 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f234a7c; op2val:0x0;
op3val:0x666666; valaddr_reg:x3; val_offset:98223*0 + 3*485*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 98223*0 + 3*485*FLEN/8, x4, x1, x2)

inst_32742:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x234a7c and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x6db6db and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f234a7c; op2val:0x0;
op3val:0x6db6db; valaddr_reg:x3; val_offset:98226*0 + 3*486*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 98226*0 + 3*486*FLEN/8, x4, x1, x2)

inst_32743:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x234a7c and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x7ffff8 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f234a7c; op2val:0x0;
op3val:0x7ffff8; valaddr_reg:x3; val_offset:98229*0 + 3*487*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 98229*0 + 3*487*FLEN/8, x4, x1, x2)

inst_32744:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x234a7c and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x7ffffc and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f234a7c; op2val:0x0;
op3val:0x7ffffc; valaddr_reg:x3; val_offset:98232*0 + 3*488*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 98232*0 + 3*488*FLEN/8, x4, x1, x2)

inst_32745:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x234a7c and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x7ffffe and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f234a7c; op2val:0x0;
op3val:0x7ffffe; valaddr_reg:x3; val_offset:98235*0 + 3*489*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 98235*0 + 3*489*FLEN/8, x4, x1, x2)

inst_32746:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x234a7c and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x14 and fm3 == 0x000000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f234a7c; op2val:0x0;
op3val:0xa000000; valaddr_reg:x3; val_offset:98238*0 + 3*490*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 98238*0 + 3*490*FLEN/8, x4, x1, x2)

inst_32747:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x234a7c and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x14 and fm3 == 0x000001 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f234a7c; op2val:0x0;
op3val:0xa000001; valaddr_reg:x3; val_offset:98241*0 + 3*491*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 98241*0 + 3*491*FLEN/8, x4, x1, x2)

inst_32748:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x234a7c and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x14 and fm3 == 0x000003 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f234a7c; op2val:0x0;
op3val:0xa000003; valaddr_reg:x3; val_offset:98244*0 + 3*492*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 98244*0 + 3*492*FLEN/8, x4, x1, x2)

inst_32749:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x234a7c and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x14 and fm3 == 0x000007 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f234a7c; op2val:0x0;
op3val:0xa000007; valaddr_reg:x3; val_offset:98247*0 + 3*493*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 98247*0 + 3*493*FLEN/8, x4, x1, x2)

inst_32750:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x234a7c and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x14 and fm3 == 0x00000f and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f234a7c; op2val:0x0;
op3val:0xa00000f; valaddr_reg:x3; val_offset:98250*0 + 3*494*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 98250*0 + 3*494*FLEN/8, x4, x1, x2)

inst_32751:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x234a7c and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x14 and fm3 == 0x00001f and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f234a7c; op2val:0x0;
op3val:0xa00001f; valaddr_reg:x3; val_offset:98253*0 + 3*495*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 98253*0 + 3*495*FLEN/8, x4, x1, x2)

inst_32752:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x234a7c and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x14 and fm3 == 0x00003f and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f234a7c; op2val:0x0;
op3val:0xa00003f; valaddr_reg:x3; val_offset:98256*0 + 3*496*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 98256*0 + 3*496*FLEN/8, x4, x1, x2)

inst_32753:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x234a7c and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x14 and fm3 == 0x00007f and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f234a7c; op2val:0x0;
op3val:0xa00007f; valaddr_reg:x3; val_offset:98259*0 + 3*497*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 98259*0 + 3*497*FLEN/8, x4, x1, x2)

inst_32754:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x234a7c and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x14 and fm3 == 0x0000ff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f234a7c; op2val:0x0;
op3val:0xa0000ff; valaddr_reg:x3; val_offset:98262*0 + 3*498*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 98262*0 + 3*498*FLEN/8, x4, x1, x2)

inst_32755:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x234a7c and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x14 and fm3 == 0x0001ff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f234a7c; op2val:0x0;
op3val:0xa0001ff; valaddr_reg:x3; val_offset:98265*0 + 3*499*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 98265*0 + 3*499*FLEN/8, x4, x1, x2)

inst_32756:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x234a7c and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x14 and fm3 == 0x0003ff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f234a7c; op2val:0x0;
op3val:0xa0003ff; valaddr_reg:x3; val_offset:98268*0 + 3*500*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 98268*0 + 3*500*FLEN/8, x4, x1, x2)

inst_32757:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x234a7c and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x14 and fm3 == 0x0007ff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f234a7c; op2val:0x0;
op3val:0xa0007ff; valaddr_reg:x3; val_offset:98271*0 + 3*501*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 98271*0 + 3*501*FLEN/8, x4, x1, x2)

inst_32758:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x234a7c and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x14 and fm3 == 0x000fff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f234a7c; op2val:0x0;
op3val:0xa000fff; valaddr_reg:x3; val_offset:98274*0 + 3*502*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 98274*0 + 3*502*FLEN/8, x4, x1, x2)

inst_32759:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x234a7c and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x14 and fm3 == 0x001fff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f234a7c; op2val:0x0;
op3val:0xa001fff; valaddr_reg:x3; val_offset:98277*0 + 3*503*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 98277*0 + 3*503*FLEN/8, x4, x1, x2)

inst_32760:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x234a7c and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x14 and fm3 == 0x003fff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f234a7c; op2val:0x0;
op3val:0xa003fff; valaddr_reg:x3; val_offset:98280*0 + 3*504*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 98280*0 + 3*504*FLEN/8, x4, x1, x2)

inst_32761:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x234a7c and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x14 and fm3 == 0x007fff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f234a7c; op2val:0x0;
op3val:0xa007fff; valaddr_reg:x3; val_offset:98283*0 + 3*505*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 98283*0 + 3*505*FLEN/8, x4, x1, x2)

inst_32762:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x234a7c and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x14 and fm3 == 0x00ffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f234a7c; op2val:0x0;
op3val:0xa00ffff; valaddr_reg:x3; val_offset:98286*0 + 3*506*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 98286*0 + 3*506*FLEN/8, x4, x1, x2)

inst_32763:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x234a7c and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x14 and fm3 == 0x01ffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f234a7c; op2val:0x0;
op3val:0xa01ffff; valaddr_reg:x3; val_offset:98289*0 + 3*507*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 98289*0 + 3*507*FLEN/8, x4, x1, x2)

inst_32764:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x234a7c and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x14 and fm3 == 0x03ffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f234a7c; op2val:0x0;
op3val:0xa03ffff; valaddr_reg:x3; val_offset:98292*0 + 3*508*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 98292*0 + 3*508*FLEN/8, x4, x1, x2)

inst_32765:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x234a7c and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x14 and fm3 == 0x07ffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f234a7c; op2val:0x0;
op3val:0xa07ffff; valaddr_reg:x3; val_offset:98295*0 + 3*509*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 98295*0 + 3*509*FLEN/8, x4, x1, x2)

inst_32766:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x234a7c and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x14 and fm3 == 0x0fffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f234a7c; op2val:0x0;
op3val:0xa0fffff; valaddr_reg:x3; val_offset:98298*0 + 3*510*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 98298*0 + 3*510*FLEN/8, x4, x1, x2)

inst_32767:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x234a7c and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x14 and fm3 == 0x1fffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f234a7c; op2val:0x0;
op3val:0xa1fffff; valaddr_reg:x3; val_offset:98301*0 + 3*511*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 98301*0 + 3*511*FLEN/8, x4, x1, x2)
RVTEST_SIGBASE(x1,signature_x1_5)

inst_32768:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x234a7c and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x14 and fm3 == 0x3fffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f234a7c; op2val:0x0;
op3val:0xa3fffff; valaddr_reg:x3; val_offset:98304*0 + 3*512*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 98304*0 + 3*512*FLEN/8, x4, x1, x2)

inst_32769:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x234a7c and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x14 and fm3 == 0x400000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f234a7c; op2val:0x0;
op3val:0xa400000; valaddr_reg:x3; val_offset:98307*0 + 3*513*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 98307*0 + 3*513*FLEN/8, x4, x1, x2)

inst_32770:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x234a7c and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x14 and fm3 == 0x600000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f234a7c; op2val:0x0;
op3val:0xa600000; valaddr_reg:x3; val_offset:98310*0 + 3*514*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 98310*0 + 3*514*FLEN/8, x4, x1, x2)

inst_32771:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x234a7c and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x14 and fm3 == 0x700000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f234a7c; op2val:0x0;
op3val:0xa700000; valaddr_reg:x3; val_offset:98313*0 + 3*515*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 98313*0 + 3*515*FLEN/8, x4, x1, x2)

inst_32772:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x234a7c and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x14 and fm3 == 0x780000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f234a7c; op2val:0x0;
op3val:0xa780000; valaddr_reg:x3; val_offset:98316*0 + 3*516*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 98316*0 + 3*516*FLEN/8, x4, x1, x2)

inst_32773:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x234a7c and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x14 and fm3 == 0x7c0000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f234a7c; op2val:0x0;
op3val:0xa7c0000; valaddr_reg:x3; val_offset:98319*0 + 3*517*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 98319*0 + 3*517*FLEN/8, x4, x1, x2)

inst_32774:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x234a7c and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x14 and fm3 == 0x7e0000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f234a7c; op2val:0x0;
op3val:0xa7e0000; valaddr_reg:x3; val_offset:98322*0 + 3*518*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 98322*0 + 3*518*FLEN/8, x4, x1, x2)

inst_32775:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x234a7c and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x14 and fm3 == 0x7f0000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f234a7c; op2val:0x0;
op3val:0xa7f0000; valaddr_reg:x3; val_offset:98325*0 + 3*519*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 98325*0 + 3*519*FLEN/8, x4, x1, x2)

inst_32776:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x234a7c and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x14 and fm3 == 0x7f8000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f234a7c; op2val:0x0;
op3val:0xa7f8000; valaddr_reg:x3; val_offset:98328*0 + 3*520*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 98328*0 + 3*520*FLEN/8, x4, x1, x2)

inst_32777:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x234a7c and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x14 and fm3 == 0x7fc000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f234a7c; op2val:0x0;
op3val:0xa7fc000; valaddr_reg:x3; val_offset:98331*0 + 3*521*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 98331*0 + 3*521*FLEN/8, x4, x1, x2)

inst_32778:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x234a7c and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x14 and fm3 == 0x7fe000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f234a7c; op2val:0x0;
op3val:0xa7fe000; valaddr_reg:x3; val_offset:98334*0 + 3*522*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 98334*0 + 3*522*FLEN/8, x4, x1, x2)

inst_32779:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x234a7c and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x14 and fm3 == 0x7ff000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f234a7c; op2val:0x0;
op3val:0xa7ff000; valaddr_reg:x3; val_offset:98337*0 + 3*523*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 98337*0 + 3*523*FLEN/8, x4, x1, x2)

inst_32780:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x234a7c and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x14 and fm3 == 0x7ff800 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f234a7c; op2val:0x0;
op3val:0xa7ff800; valaddr_reg:x3; val_offset:98340*0 + 3*524*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 98340*0 + 3*524*FLEN/8, x4, x1, x2)

inst_32781:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x234a7c and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x14 and fm3 == 0x7ffc00 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f234a7c; op2val:0x0;
op3val:0xa7ffc00; valaddr_reg:x3; val_offset:98343*0 + 3*525*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 98343*0 + 3*525*FLEN/8, x4, x1, x2)

inst_32782:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x234a7c and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x14 and fm3 == 0x7ffe00 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f234a7c; op2val:0x0;
op3val:0xa7ffe00; valaddr_reg:x3; val_offset:98346*0 + 3*526*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 98346*0 + 3*526*FLEN/8, x4, x1, x2)

inst_32783:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x234a7c and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x14 and fm3 == 0x7fff00 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f234a7c; op2val:0x0;
op3val:0xa7fff00; valaddr_reg:x3; val_offset:98349*0 + 3*527*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 98349*0 + 3*527*FLEN/8, x4, x1, x2)

inst_32784:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x234a7c and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x14 and fm3 == 0x7fff80 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f234a7c; op2val:0x0;
op3val:0xa7fff80; valaddr_reg:x3; val_offset:98352*0 + 3*528*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 98352*0 + 3*528*FLEN/8, x4, x1, x2)

inst_32785:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x234a7c and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x14 and fm3 == 0x7fffc0 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f234a7c; op2val:0x0;
op3val:0xa7fffc0; valaddr_reg:x3; val_offset:98355*0 + 3*529*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 98355*0 + 3*529*FLEN/8, x4, x1, x2)

inst_32786:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x234a7c and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x14 and fm3 == 0x7fffe0 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f234a7c; op2val:0x0;
op3val:0xa7fffe0; valaddr_reg:x3; val_offset:98358*0 + 3*530*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 98358*0 + 3*530*FLEN/8, x4, x1, x2)

inst_32787:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x234a7c and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x14 and fm3 == 0x7ffff0 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f234a7c; op2val:0x0;
op3val:0xa7ffff0; valaddr_reg:x3; val_offset:98361*0 + 3*531*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 98361*0 + 3*531*FLEN/8, x4, x1, x2)

inst_32788:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x234a7c and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x14 and fm3 == 0x7ffff8 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f234a7c; op2val:0x0;
op3val:0xa7ffff8; valaddr_reg:x3; val_offset:98364*0 + 3*532*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 98364*0 + 3*532*FLEN/8, x4, x1, x2)

inst_32789:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x234a7c and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x14 and fm3 == 0x7ffffc and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f234a7c; op2val:0x0;
op3val:0xa7ffffc; valaddr_reg:x3; val_offset:98367*0 + 3*533*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 98367*0 + 3*533*FLEN/8, x4, x1, x2)

inst_32790:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x234a7c and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x14 and fm3 == 0x7ffffe and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f234a7c; op2val:0x0;
op3val:0xa7ffffe; valaddr_reg:x3; val_offset:98370*0 + 3*534*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 98370*0 + 3*534*FLEN/8, x4, x1, x2)

inst_32791:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x234a7c and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x14 and fm3 == 0x7fffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f234a7c; op2val:0x0;
op3val:0xa7fffff; valaddr_reg:x3; val_offset:98373*0 + 3*535*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 98373*0 + 3*535*FLEN/8, x4, x1, x2)

inst_32792:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x237022 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x321f7b and fs3 == 1 and fe3 == 0x7f and fm3 == 0x000001 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f237022; op2val:0x80321f7b;
op3val:0xbf800001; valaddr_reg:x3; val_offset:98376*0 + 3*536*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 98376*0 + 3*536*FLEN/8, x4, x1, x2)

inst_32793:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x237022 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x321f7b and fs3 == 1 and fe3 == 0x7f and fm3 == 0x000003 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f237022; op2val:0x80321f7b;
op3val:0xbf800003; valaddr_reg:x3; val_offset:98379*0 + 3*537*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 98379*0 + 3*537*FLEN/8, x4, x1, x2)

inst_32794:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x237022 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x321f7b and fs3 == 1 and fe3 == 0x7f and fm3 == 0x000007 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f237022; op2val:0x80321f7b;
op3val:0xbf800007; valaddr_reg:x3; val_offset:98382*0 + 3*538*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 98382*0 + 3*538*FLEN/8, x4, x1, x2)

inst_32795:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x237022 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x321f7b and fs3 == 1 and fe3 == 0x7f and fm3 == 0x199999 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f237022; op2val:0x80321f7b;
op3val:0xbf999999; valaddr_reg:x3; val_offset:98385*0 + 3*539*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 98385*0 + 3*539*FLEN/8, x4, x1, x2)

inst_32796:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x237022 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x321f7b and fs3 == 1 and fe3 == 0x7f and fm3 == 0x249249 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f237022; op2val:0x80321f7b;
op3val:0xbfa49249; valaddr_reg:x3; val_offset:98388*0 + 3*540*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 98388*0 + 3*540*FLEN/8, x4, x1, x2)

inst_32797:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x237022 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x321f7b and fs3 == 1 and fe3 == 0x7f and fm3 == 0x333333 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f237022; op2val:0x80321f7b;
op3val:0xbfb33333; valaddr_reg:x3; val_offset:98391*0 + 3*541*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 98391*0 + 3*541*FLEN/8, x4, x1, x2)

inst_32798:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x237022 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x321f7b and fs3 == 1 and fe3 == 0x7f and fm3 == 0x36db6d and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f237022; op2val:0x80321f7b;
op3val:0xbfb6db6d; valaddr_reg:x3; val_offset:98394*0 + 3*542*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 98394*0 + 3*542*FLEN/8, x4, x1, x2)

inst_32799:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x237022 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x321f7b and fs3 == 1 and fe3 == 0x7f and fm3 == 0x3bbbbb and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f237022; op2val:0x80321f7b;
op3val:0xbfbbbbbb; valaddr_reg:x3; val_offset:98397*0 + 3*543*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 98397*0 + 3*543*FLEN/8, x4, x1, x2)

inst_32800:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x237022 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x321f7b and fs3 == 1 and fe3 == 0x7f and fm3 == 0x444444 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f237022; op2val:0x80321f7b;
op3val:0xbfc44444; valaddr_reg:x3; val_offset:98400*0 + 3*544*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 98400*0 + 3*544*FLEN/8, x4, x1, x2)

inst_32801:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x237022 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x321f7b and fs3 == 1 and fe3 == 0x7f and fm3 == 0x4ccccc and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f237022; op2val:0x80321f7b;
op3val:0xbfcccccc; valaddr_reg:x3; val_offset:98403*0 + 3*545*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 98403*0 + 3*545*FLEN/8, x4, x1, x2)

inst_32802:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x237022 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x321f7b and fs3 == 1 and fe3 == 0x7f and fm3 == 0x5b6db6 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f237022; op2val:0x80321f7b;
op3val:0xbfdb6db6; valaddr_reg:x3; val_offset:98406*0 + 3*546*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 98406*0 + 3*546*FLEN/8, x4, x1, x2)

inst_32803:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x237022 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x321f7b and fs3 == 1 and fe3 == 0x7f and fm3 == 0x666666 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f237022; op2val:0x80321f7b;
op3val:0xbfe66666; valaddr_reg:x3; val_offset:98409*0 + 3*547*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 98409*0 + 3*547*FLEN/8, x4, x1, x2)

inst_32804:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x237022 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x321f7b and fs3 == 1 and fe3 == 0x7f and fm3 == 0x6db6db and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f237022; op2val:0x80321f7b;
op3val:0xbfedb6db; valaddr_reg:x3; val_offset:98412*0 + 3*548*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 98412*0 + 3*548*FLEN/8, x4, x1, x2)

inst_32805:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x237022 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x321f7b and fs3 == 1 and fe3 == 0x7f and fm3 == 0x7ffff8 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f237022; op2val:0x80321f7b;
op3val:0xbffffff8; valaddr_reg:x3; val_offset:98415*0 + 3*549*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 98415*0 + 3*549*FLEN/8, x4, x1, x2)

inst_32806:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x237022 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x321f7b and fs3 == 1 and fe3 == 0x7f and fm3 == 0x7ffffc and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f237022; op2val:0x80321f7b;
op3val:0xbffffffc; valaddr_reg:x3; val_offset:98418*0 + 3*550*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 98418*0 + 3*550*FLEN/8, x4, x1, x2)

inst_32807:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x237022 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x321f7b and fs3 == 1 and fe3 == 0x7f and fm3 == 0x7ffffe and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f237022; op2val:0x80321f7b;
op3val:0xbffffffe; valaddr_reg:x3; val_offset:98421*0 + 3*551*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 98421*0 + 3*551*FLEN/8, x4, x1, x2)

inst_32808:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x237022 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x321f7b and fs3 == 1 and fe3 == 0x86 and fm3 == 0x000000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f237022; op2val:0x80321f7b;
op3val:0xc3000000; valaddr_reg:x3; val_offset:98424*0 + 3*552*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 98424*0 + 3*552*FLEN/8, x4, x1, x2)

inst_32809:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x237022 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x321f7b and fs3 == 1 and fe3 == 0x86 and fm3 == 0x000001 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f237022; op2val:0x80321f7b;
op3val:0xc3000001; valaddr_reg:x3; val_offset:98427*0 + 3*553*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 98427*0 + 3*553*FLEN/8, x4, x1, x2)

inst_32810:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x237022 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x321f7b and fs3 == 1 and fe3 == 0x86 and fm3 == 0x000003 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f237022; op2val:0x80321f7b;
op3val:0xc3000003; valaddr_reg:x3; val_offset:98430*0 + 3*554*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 98430*0 + 3*554*FLEN/8, x4, x1, x2)

inst_32811:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x237022 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x321f7b and fs3 == 1 and fe3 == 0x86 and fm3 == 0x000007 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f237022; op2val:0x80321f7b;
op3val:0xc3000007; valaddr_reg:x3; val_offset:98433*0 + 3*555*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 98433*0 + 3*555*FLEN/8, x4, x1, x2)

inst_32812:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x237022 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x321f7b and fs3 == 1 and fe3 == 0x86 and fm3 == 0x00000f and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f237022; op2val:0x80321f7b;
op3val:0xc300000f; valaddr_reg:x3; val_offset:98436*0 + 3*556*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 98436*0 + 3*556*FLEN/8, x4, x1, x2)

inst_32813:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x237022 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x321f7b and fs3 == 1 and fe3 == 0x86 and fm3 == 0x00001f and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f237022; op2val:0x80321f7b;
op3val:0xc300001f; valaddr_reg:x3; val_offset:98439*0 + 3*557*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 98439*0 + 3*557*FLEN/8, x4, x1, x2)

inst_32814:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x237022 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x321f7b and fs3 == 1 and fe3 == 0x86 and fm3 == 0x00003f and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f237022; op2val:0x80321f7b;
op3val:0xc300003f; valaddr_reg:x3; val_offset:98442*0 + 3*558*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 98442*0 + 3*558*FLEN/8, x4, x1, x2)

inst_32815:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x237022 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x321f7b and fs3 == 1 and fe3 == 0x86 and fm3 == 0x00007f and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f237022; op2val:0x80321f7b;
op3val:0xc300007f; valaddr_reg:x3; val_offset:98445*0 + 3*559*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 98445*0 + 3*559*FLEN/8, x4, x1, x2)

inst_32816:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x237022 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x321f7b and fs3 == 1 and fe3 == 0x86 and fm3 == 0x0000ff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f237022; op2val:0x80321f7b;
op3val:0xc30000ff; valaddr_reg:x3; val_offset:98448*0 + 3*560*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 98448*0 + 3*560*FLEN/8, x4, x1, x2)

inst_32817:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x237022 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x321f7b and fs3 == 1 and fe3 == 0x86 and fm3 == 0x0001ff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f237022; op2val:0x80321f7b;
op3val:0xc30001ff; valaddr_reg:x3; val_offset:98451*0 + 3*561*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 98451*0 + 3*561*FLEN/8, x4, x1, x2)

inst_32818:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x237022 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x321f7b and fs3 == 1 and fe3 == 0x86 and fm3 == 0x0003ff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f237022; op2val:0x80321f7b;
op3val:0xc30003ff; valaddr_reg:x3; val_offset:98454*0 + 3*562*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 98454*0 + 3*562*FLEN/8, x4, x1, x2)

inst_32819:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x237022 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x321f7b and fs3 == 1 and fe3 == 0x86 and fm3 == 0x0007ff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f237022; op2val:0x80321f7b;
op3val:0xc30007ff; valaddr_reg:x3; val_offset:98457*0 + 3*563*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 98457*0 + 3*563*FLEN/8, x4, x1, x2)

inst_32820:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x237022 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x321f7b and fs3 == 1 and fe3 == 0x86 and fm3 == 0x000fff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f237022; op2val:0x80321f7b;
op3val:0xc3000fff; valaddr_reg:x3; val_offset:98460*0 + 3*564*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 98460*0 + 3*564*FLEN/8, x4, x1, x2)

inst_32821:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x237022 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x321f7b and fs3 == 1 and fe3 == 0x86 and fm3 == 0x001fff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f237022; op2val:0x80321f7b;
op3val:0xc3001fff; valaddr_reg:x3; val_offset:98463*0 + 3*565*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 98463*0 + 3*565*FLEN/8, x4, x1, x2)

inst_32822:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x237022 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x321f7b and fs3 == 1 and fe3 == 0x86 and fm3 == 0x003fff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f237022; op2val:0x80321f7b;
op3val:0xc3003fff; valaddr_reg:x3; val_offset:98466*0 + 3*566*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 98466*0 + 3*566*FLEN/8, x4, x1, x2)

inst_32823:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x237022 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x321f7b and fs3 == 1 and fe3 == 0x86 and fm3 == 0x007fff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f237022; op2val:0x80321f7b;
op3val:0xc3007fff; valaddr_reg:x3; val_offset:98469*0 + 3*567*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 98469*0 + 3*567*FLEN/8, x4, x1, x2)

inst_32824:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x237022 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x321f7b and fs3 == 1 and fe3 == 0x86 and fm3 == 0x00ffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f237022; op2val:0x80321f7b;
op3val:0xc300ffff; valaddr_reg:x3; val_offset:98472*0 + 3*568*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 98472*0 + 3*568*FLEN/8, x4, x1, x2)

inst_32825:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x237022 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x321f7b and fs3 == 1 and fe3 == 0x86 and fm3 == 0x01ffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f237022; op2val:0x80321f7b;
op3val:0xc301ffff; valaddr_reg:x3; val_offset:98475*0 + 3*569*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 98475*0 + 3*569*FLEN/8, x4, x1, x2)

inst_32826:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x237022 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x321f7b and fs3 == 1 and fe3 == 0x86 and fm3 == 0x03ffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f237022; op2val:0x80321f7b;
op3val:0xc303ffff; valaddr_reg:x3; val_offset:98478*0 + 3*570*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 98478*0 + 3*570*FLEN/8, x4, x1, x2)

inst_32827:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x237022 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x321f7b and fs3 == 1 and fe3 == 0x86 and fm3 == 0x07ffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f237022; op2val:0x80321f7b;
op3val:0xc307ffff; valaddr_reg:x3; val_offset:98481*0 + 3*571*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 98481*0 + 3*571*FLEN/8, x4, x1, x2)

inst_32828:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x237022 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x321f7b and fs3 == 1 and fe3 == 0x86 and fm3 == 0x0fffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f237022; op2val:0x80321f7b;
op3val:0xc30fffff; valaddr_reg:x3; val_offset:98484*0 + 3*572*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 98484*0 + 3*572*FLEN/8, x4, x1, x2)

inst_32829:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x237022 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x321f7b and fs3 == 1 and fe3 == 0x86 and fm3 == 0x1fffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f237022; op2val:0x80321f7b;
op3val:0xc31fffff; valaddr_reg:x3; val_offset:98487*0 + 3*573*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 98487*0 + 3*573*FLEN/8, x4, x1, x2)

inst_32830:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x237022 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x321f7b and fs3 == 1 and fe3 == 0x86 and fm3 == 0x3fffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f237022; op2val:0x80321f7b;
op3val:0xc33fffff; valaddr_reg:x3; val_offset:98490*0 + 3*574*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 98490*0 + 3*574*FLEN/8, x4, x1, x2)

inst_32831:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x237022 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x321f7b and fs3 == 1 and fe3 == 0x86 and fm3 == 0x400000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f237022; op2val:0x80321f7b;
op3val:0xc3400000; valaddr_reg:x3; val_offset:98493*0 + 3*575*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 98493*0 + 3*575*FLEN/8, x4, x1, x2)

inst_32832:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x237022 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x321f7b and fs3 == 1 and fe3 == 0x86 and fm3 == 0x600000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f237022; op2val:0x80321f7b;
op3val:0xc3600000; valaddr_reg:x3; val_offset:98496*0 + 3*576*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 98496*0 + 3*576*FLEN/8, x4, x1, x2)

inst_32833:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x237022 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x321f7b and fs3 == 1 and fe3 == 0x86 and fm3 == 0x700000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f237022; op2val:0x80321f7b;
op3val:0xc3700000; valaddr_reg:x3; val_offset:98499*0 + 3*577*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 98499*0 + 3*577*FLEN/8, x4, x1, x2)

inst_32834:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x237022 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x321f7b and fs3 == 1 and fe3 == 0x86 and fm3 == 0x780000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f237022; op2val:0x80321f7b;
op3val:0xc3780000; valaddr_reg:x3; val_offset:98502*0 + 3*578*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 98502*0 + 3*578*FLEN/8, x4, x1, x2)

inst_32835:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x237022 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x321f7b and fs3 == 1 and fe3 == 0x86 and fm3 == 0x7c0000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f237022; op2val:0x80321f7b;
op3val:0xc37c0000; valaddr_reg:x3; val_offset:98505*0 + 3*579*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 98505*0 + 3*579*FLEN/8, x4, x1, x2)

inst_32836:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x237022 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x321f7b and fs3 == 1 and fe3 == 0x86 and fm3 == 0x7e0000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f237022; op2val:0x80321f7b;
op3val:0xc37e0000; valaddr_reg:x3; val_offset:98508*0 + 3*580*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 98508*0 + 3*580*FLEN/8, x4, x1, x2)

inst_32837:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x237022 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x321f7b and fs3 == 1 and fe3 == 0x86 and fm3 == 0x7f0000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f237022; op2val:0x80321f7b;
op3val:0xc37f0000; valaddr_reg:x3; val_offset:98511*0 + 3*581*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 98511*0 + 3*581*FLEN/8, x4, x1, x2)

inst_32838:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x237022 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x321f7b and fs3 == 1 and fe3 == 0x86 and fm3 == 0x7f8000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f237022; op2val:0x80321f7b;
op3val:0xc37f8000; valaddr_reg:x3; val_offset:98514*0 + 3*582*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 98514*0 + 3*582*FLEN/8, x4, x1, x2)

inst_32839:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x237022 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x321f7b and fs3 == 1 and fe3 == 0x86 and fm3 == 0x7fc000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f237022; op2val:0x80321f7b;
op3val:0xc37fc000; valaddr_reg:x3; val_offset:98517*0 + 3*583*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 98517*0 + 3*583*FLEN/8, x4, x1, x2)

inst_32840:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x237022 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x321f7b and fs3 == 1 and fe3 == 0x86 and fm3 == 0x7fe000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f237022; op2val:0x80321f7b;
op3val:0xc37fe000; valaddr_reg:x3; val_offset:98520*0 + 3*584*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 98520*0 + 3*584*FLEN/8, x4, x1, x2)

inst_32841:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x237022 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x321f7b and fs3 == 1 and fe3 == 0x86 and fm3 == 0x7ff000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f237022; op2val:0x80321f7b;
op3val:0xc37ff000; valaddr_reg:x3; val_offset:98523*0 + 3*585*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 98523*0 + 3*585*FLEN/8, x4, x1, x2)

inst_32842:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x237022 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x321f7b and fs3 == 1 and fe3 == 0x86 and fm3 == 0x7ff800 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f237022; op2val:0x80321f7b;
op3val:0xc37ff800; valaddr_reg:x3; val_offset:98526*0 + 3*586*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 98526*0 + 3*586*FLEN/8, x4, x1, x2)

inst_32843:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x237022 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x321f7b and fs3 == 1 and fe3 == 0x86 and fm3 == 0x7ffc00 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f237022; op2val:0x80321f7b;
op3val:0xc37ffc00; valaddr_reg:x3; val_offset:98529*0 + 3*587*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 98529*0 + 3*587*FLEN/8, x4, x1, x2)

inst_32844:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x237022 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x321f7b and fs3 == 1 and fe3 == 0x86 and fm3 == 0x7ffe00 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f237022; op2val:0x80321f7b;
op3val:0xc37ffe00; valaddr_reg:x3; val_offset:98532*0 + 3*588*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 98532*0 + 3*588*FLEN/8, x4, x1, x2)

inst_32845:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x237022 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x321f7b and fs3 == 1 and fe3 == 0x86 and fm3 == 0x7fff00 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f237022; op2val:0x80321f7b;
op3val:0xc37fff00; valaddr_reg:x3; val_offset:98535*0 + 3*589*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 98535*0 + 3*589*FLEN/8, x4, x1, x2)

inst_32846:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x237022 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x321f7b and fs3 == 1 and fe3 == 0x86 and fm3 == 0x7fff80 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f237022; op2val:0x80321f7b;
op3val:0xc37fff80; valaddr_reg:x3; val_offset:98538*0 + 3*590*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 98538*0 + 3*590*FLEN/8, x4, x1, x2)

inst_32847:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x237022 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x321f7b and fs3 == 1 and fe3 == 0x86 and fm3 == 0x7fffc0 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f237022; op2val:0x80321f7b;
op3val:0xc37fffc0; valaddr_reg:x3; val_offset:98541*0 + 3*591*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 98541*0 + 3*591*FLEN/8, x4, x1, x2)

inst_32848:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x237022 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x321f7b and fs3 == 1 and fe3 == 0x86 and fm3 == 0x7fffe0 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f237022; op2val:0x80321f7b;
op3val:0xc37fffe0; valaddr_reg:x3; val_offset:98544*0 + 3*592*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 98544*0 + 3*592*FLEN/8, x4, x1, x2)

inst_32849:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x237022 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x321f7b and fs3 == 1 and fe3 == 0x86 and fm3 == 0x7ffff0 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f237022; op2val:0x80321f7b;
op3val:0xc37ffff0; valaddr_reg:x3; val_offset:98547*0 + 3*593*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 98547*0 + 3*593*FLEN/8, x4, x1, x2)

inst_32850:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x237022 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x321f7b and fs3 == 1 and fe3 == 0x86 and fm3 == 0x7ffff8 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f237022; op2val:0x80321f7b;
op3val:0xc37ffff8; valaddr_reg:x3; val_offset:98550*0 + 3*594*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 98550*0 + 3*594*FLEN/8, x4, x1, x2)

inst_32851:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x237022 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x321f7b and fs3 == 1 and fe3 == 0x86 and fm3 == 0x7ffffc and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f237022; op2val:0x80321f7b;
op3val:0xc37ffffc; valaddr_reg:x3; val_offset:98553*0 + 3*595*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 98553*0 + 3*595*FLEN/8, x4, x1, x2)

inst_32852:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x237022 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x321f7b and fs3 == 1 and fe3 == 0x86 and fm3 == 0x7ffffe and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f237022; op2val:0x80321f7b;
op3val:0xc37ffffe; valaddr_reg:x3; val_offset:98556*0 + 3*596*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 98556*0 + 3*596*FLEN/8, x4, x1, x2)

inst_32853:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x237022 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x321f7b and fs3 == 1 and fe3 == 0x86 and fm3 == 0x7fffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f237022; op2val:0x80321f7b;
op3val:0xc37fffff; valaddr_reg:x3; val_offset:98559*0 + 3*597*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 98559*0 + 3*597*FLEN/8, x4, x1, x2)

inst_32854:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x23bfb5 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000001 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f23bfb5; op2val:0x80000000;
op3val:0x80000001; valaddr_reg:x3; val_offset:98562*0 + 3*598*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 98562*0 + 3*598*FLEN/8, x4, x1, x2)

inst_32855:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x23bfb5 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000003 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f23bfb5; op2val:0x80000000;
op3val:0x80000003; valaddr_reg:x3; val_offset:98565*0 + 3*599*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 98565*0 + 3*599*FLEN/8, x4, x1, x2)

inst_32856:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x23bfb5 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000007 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f23bfb5; op2val:0x80000000;
op3val:0x80000007; valaddr_reg:x3; val_offset:98568*0 + 3*600*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 98568*0 + 3*600*FLEN/8, x4, x1, x2)

inst_32857:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x23bfb5 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x199999 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f23bfb5; op2val:0x80000000;
op3val:0x80199999; valaddr_reg:x3; val_offset:98571*0 + 3*601*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 98571*0 + 3*601*FLEN/8, x4, x1, x2)

inst_32858:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x23bfb5 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x249249 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f23bfb5; op2val:0x80000000;
op3val:0x80249249; valaddr_reg:x3; val_offset:98574*0 + 3*602*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 98574*0 + 3*602*FLEN/8, x4, x1, x2)

inst_32859:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x23bfb5 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x333333 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f23bfb5; op2val:0x80000000;
op3val:0x80333333; valaddr_reg:x3; val_offset:98577*0 + 3*603*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 98577*0 + 3*603*FLEN/8, x4, x1, x2)

inst_32860:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x23bfb5 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x36db6d and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f23bfb5; op2val:0x80000000;
op3val:0x8036db6d; valaddr_reg:x3; val_offset:98580*0 + 3*604*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 98580*0 + 3*604*FLEN/8, x4, x1, x2)

inst_32861:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x23bfb5 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3bbbbb and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f23bfb5; op2val:0x80000000;
op3val:0x803bbbbb; valaddr_reg:x3; val_offset:98583*0 + 3*605*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 98583*0 + 3*605*FLEN/8, x4, x1, x2)

inst_32862:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x23bfb5 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x444444 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f23bfb5; op2val:0x80000000;
op3val:0x80444444; valaddr_reg:x3; val_offset:98586*0 + 3*606*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 98586*0 + 3*606*FLEN/8, x4, x1, x2)

inst_32863:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x23bfb5 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x4ccccc and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f23bfb5; op2val:0x80000000;
op3val:0x804ccccc; valaddr_reg:x3; val_offset:98589*0 + 3*607*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 98589*0 + 3*607*FLEN/8, x4, x1, x2)

inst_32864:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x23bfb5 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x5b6db6 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f23bfb5; op2val:0x80000000;
op3val:0x805b6db6; valaddr_reg:x3; val_offset:98592*0 + 3*608*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 98592*0 + 3*608*FLEN/8, x4, x1, x2)

inst_32865:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x23bfb5 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x666666 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f23bfb5; op2val:0x80000000;
op3val:0x80666666; valaddr_reg:x3; val_offset:98595*0 + 3*609*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 98595*0 + 3*609*FLEN/8, x4, x1, x2)

inst_32866:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x23bfb5 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x6db6db and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f23bfb5; op2val:0x80000000;
op3val:0x806db6db; valaddr_reg:x3; val_offset:98598*0 + 3*610*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 98598*0 + 3*610*FLEN/8, x4, x1, x2)

inst_32867:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x23bfb5 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7ffff8 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f23bfb5; op2val:0x80000000;
op3val:0x807ffff8; valaddr_reg:x3; val_offset:98601*0 + 3*611*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 98601*0 + 3*611*FLEN/8, x4, x1, x2)

inst_32868:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x23bfb5 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7ffffc and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f23bfb5; op2val:0x80000000;
op3val:0x807ffffc; valaddr_reg:x3; val_offset:98604*0 + 3*612*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 98604*0 + 3*612*FLEN/8, x4, x1, x2)

inst_32869:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x23bfb5 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7ffffe and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f23bfb5; op2val:0x80000000;
op3val:0x807ffffe; valaddr_reg:x3; val_offset:98607*0 + 3*613*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 98607*0 + 3*613*FLEN/8, x4, x1, x2)

inst_32870:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x23bfb5 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x0e and fm3 == 0x000000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f23bfb5; op2val:0x80000000;
op3val:0x87000000; valaddr_reg:x3; val_offset:98610*0 + 3*614*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 98610*0 + 3*614*FLEN/8, x4, x1, x2)

inst_32871:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x23bfb5 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x0e and fm3 == 0x000001 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f23bfb5; op2val:0x80000000;
op3val:0x87000001; valaddr_reg:x3; val_offset:98613*0 + 3*615*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 98613*0 + 3*615*FLEN/8, x4, x1, x2)

inst_32872:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x23bfb5 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x0e and fm3 == 0x000003 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f23bfb5; op2val:0x80000000;
op3val:0x87000003; valaddr_reg:x3; val_offset:98616*0 + 3*616*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 98616*0 + 3*616*FLEN/8, x4, x1, x2)

inst_32873:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x23bfb5 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x0e and fm3 == 0x000007 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f23bfb5; op2val:0x80000000;
op3val:0x87000007; valaddr_reg:x3; val_offset:98619*0 + 3*617*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 98619*0 + 3*617*FLEN/8, x4, x1, x2)

inst_32874:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x23bfb5 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x0e and fm3 == 0x00000f and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f23bfb5; op2val:0x80000000;
op3val:0x8700000f; valaddr_reg:x3; val_offset:98622*0 + 3*618*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 98622*0 + 3*618*FLEN/8, x4, x1, x2)

inst_32875:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x23bfb5 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x0e and fm3 == 0x00001f and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f23bfb5; op2val:0x80000000;
op3val:0x8700001f; valaddr_reg:x3; val_offset:98625*0 + 3*619*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 98625*0 + 3*619*FLEN/8, x4, x1, x2)

inst_32876:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x23bfb5 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x0e and fm3 == 0x00003f and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f23bfb5; op2val:0x80000000;
op3val:0x8700003f; valaddr_reg:x3; val_offset:98628*0 + 3*620*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 98628*0 + 3*620*FLEN/8, x4, x1, x2)

inst_32877:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x23bfb5 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x0e and fm3 == 0x00007f and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f23bfb5; op2val:0x80000000;
op3val:0x8700007f; valaddr_reg:x3; val_offset:98631*0 + 3*621*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 98631*0 + 3*621*FLEN/8, x4, x1, x2)

inst_32878:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x23bfb5 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x0e and fm3 == 0x0000ff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f23bfb5; op2val:0x80000000;
op3val:0x870000ff; valaddr_reg:x3; val_offset:98634*0 + 3*622*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 98634*0 + 3*622*FLEN/8, x4, x1, x2)

inst_32879:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x23bfb5 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x0e and fm3 == 0x0001ff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f23bfb5; op2val:0x80000000;
op3val:0x870001ff; valaddr_reg:x3; val_offset:98637*0 + 3*623*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 98637*0 + 3*623*FLEN/8, x4, x1, x2)

inst_32880:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x23bfb5 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x0e and fm3 == 0x0003ff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f23bfb5; op2val:0x80000000;
op3val:0x870003ff; valaddr_reg:x3; val_offset:98640*0 + 3*624*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 98640*0 + 3*624*FLEN/8, x4, x1, x2)

inst_32881:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x23bfb5 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x0e and fm3 == 0x0007ff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f23bfb5; op2val:0x80000000;
op3val:0x870007ff; valaddr_reg:x3; val_offset:98643*0 + 3*625*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 98643*0 + 3*625*FLEN/8, x4, x1, x2)

inst_32882:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x23bfb5 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x0e and fm3 == 0x000fff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f23bfb5; op2val:0x80000000;
op3val:0x87000fff; valaddr_reg:x3; val_offset:98646*0 + 3*626*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 98646*0 + 3*626*FLEN/8, x4, x1, x2)

inst_32883:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x23bfb5 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x0e and fm3 == 0x001fff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f23bfb5; op2val:0x80000000;
op3val:0x87001fff; valaddr_reg:x3; val_offset:98649*0 + 3*627*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 98649*0 + 3*627*FLEN/8, x4, x1, x2)

inst_32884:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x23bfb5 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x0e and fm3 == 0x003fff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f23bfb5; op2val:0x80000000;
op3val:0x87003fff; valaddr_reg:x3; val_offset:98652*0 + 3*628*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 98652*0 + 3*628*FLEN/8, x4, x1, x2)

inst_32885:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x23bfb5 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x0e and fm3 == 0x007fff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f23bfb5; op2val:0x80000000;
op3val:0x87007fff; valaddr_reg:x3; val_offset:98655*0 + 3*629*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 98655*0 + 3*629*FLEN/8, x4, x1, x2)

inst_32886:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x23bfb5 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x0e and fm3 == 0x00ffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f23bfb5; op2val:0x80000000;
op3val:0x8700ffff; valaddr_reg:x3; val_offset:98658*0 + 3*630*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 98658*0 + 3*630*FLEN/8, x4, x1, x2)

inst_32887:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x23bfb5 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x0e and fm3 == 0x01ffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f23bfb5; op2val:0x80000000;
op3val:0x8701ffff; valaddr_reg:x3; val_offset:98661*0 + 3*631*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 98661*0 + 3*631*FLEN/8, x4, x1, x2)

inst_32888:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x23bfb5 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x0e and fm3 == 0x03ffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f23bfb5; op2val:0x80000000;
op3val:0x8703ffff; valaddr_reg:x3; val_offset:98664*0 + 3*632*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 98664*0 + 3*632*FLEN/8, x4, x1, x2)

inst_32889:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x23bfb5 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x0e and fm3 == 0x07ffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f23bfb5; op2val:0x80000000;
op3val:0x8707ffff; valaddr_reg:x3; val_offset:98667*0 + 3*633*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 98667*0 + 3*633*FLEN/8, x4, x1, x2)

inst_32890:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x23bfb5 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x0e and fm3 == 0x0fffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f23bfb5; op2val:0x80000000;
op3val:0x870fffff; valaddr_reg:x3; val_offset:98670*0 + 3*634*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 98670*0 + 3*634*FLEN/8, x4, x1, x2)

inst_32891:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x23bfb5 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x0e and fm3 == 0x1fffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f23bfb5; op2val:0x80000000;
op3val:0x871fffff; valaddr_reg:x3; val_offset:98673*0 + 3*635*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 98673*0 + 3*635*FLEN/8, x4, x1, x2)

inst_32892:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x23bfb5 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x0e and fm3 == 0x3fffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f23bfb5; op2val:0x80000000;
op3val:0x873fffff; valaddr_reg:x3; val_offset:98676*0 + 3*636*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 98676*0 + 3*636*FLEN/8, x4, x1, x2)

inst_32893:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x23bfb5 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x0e and fm3 == 0x400000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f23bfb5; op2val:0x80000000;
op3val:0x87400000; valaddr_reg:x3; val_offset:98679*0 + 3*637*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 98679*0 + 3*637*FLEN/8, x4, x1, x2)

inst_32894:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x23bfb5 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x0e and fm3 == 0x600000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f23bfb5; op2val:0x80000000;
op3val:0x87600000; valaddr_reg:x3; val_offset:98682*0 + 3*638*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 98682*0 + 3*638*FLEN/8, x4, x1, x2)

inst_32895:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x23bfb5 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x0e and fm3 == 0x700000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f23bfb5; op2val:0x80000000;
op3val:0x87700000; valaddr_reg:x3; val_offset:98685*0 + 3*639*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 98685*0 + 3*639*FLEN/8, x4, x1, x2)
RVTEST_SIGBASE(x1,signature_x1_6)

inst_32896:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x23bfb5 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x0e and fm3 == 0x780000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f23bfb5; op2val:0x80000000;
op3val:0x87780000; valaddr_reg:x3; val_offset:98688*0 + 3*640*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 98688*0 + 3*640*FLEN/8, x4, x1, x2)

inst_32897:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x23bfb5 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x0e and fm3 == 0x7c0000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f23bfb5; op2val:0x80000000;
op3val:0x877c0000; valaddr_reg:x3; val_offset:98691*0 + 3*641*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 98691*0 + 3*641*FLEN/8, x4, x1, x2)

inst_32898:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x23bfb5 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x0e and fm3 == 0x7e0000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f23bfb5; op2val:0x80000000;
op3val:0x877e0000; valaddr_reg:x3; val_offset:98694*0 + 3*642*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 98694*0 + 3*642*FLEN/8, x4, x1, x2)

inst_32899:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x23bfb5 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x0e and fm3 == 0x7f0000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f23bfb5; op2val:0x80000000;
op3val:0x877f0000; valaddr_reg:x3; val_offset:98697*0 + 3*643*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 98697*0 + 3*643*FLEN/8, x4, x1, x2)

inst_32900:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x23bfb5 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x0e and fm3 == 0x7f8000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f23bfb5; op2val:0x80000000;
op3val:0x877f8000; valaddr_reg:x3; val_offset:98700*0 + 3*644*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 98700*0 + 3*644*FLEN/8, x4, x1, x2)

inst_32901:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x23bfb5 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x0e and fm3 == 0x7fc000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f23bfb5; op2val:0x80000000;
op3val:0x877fc000; valaddr_reg:x3; val_offset:98703*0 + 3*645*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 98703*0 + 3*645*FLEN/8, x4, x1, x2)

inst_32902:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x23bfb5 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x0e and fm3 == 0x7fe000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f23bfb5; op2val:0x80000000;
op3val:0x877fe000; valaddr_reg:x3; val_offset:98706*0 + 3*646*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 98706*0 + 3*646*FLEN/8, x4, x1, x2)

inst_32903:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x23bfb5 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x0e and fm3 == 0x7ff000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f23bfb5; op2val:0x80000000;
op3val:0x877ff000; valaddr_reg:x3; val_offset:98709*0 + 3*647*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 98709*0 + 3*647*FLEN/8, x4, x1, x2)

inst_32904:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x23bfb5 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x0e and fm3 == 0x7ff800 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f23bfb5; op2val:0x80000000;
op3val:0x877ff800; valaddr_reg:x3; val_offset:98712*0 + 3*648*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 98712*0 + 3*648*FLEN/8, x4, x1, x2)

inst_32905:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x23bfb5 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x0e and fm3 == 0x7ffc00 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f23bfb5; op2val:0x80000000;
op3val:0x877ffc00; valaddr_reg:x3; val_offset:98715*0 + 3*649*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 98715*0 + 3*649*FLEN/8, x4, x1, x2)

inst_32906:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x23bfb5 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x0e and fm3 == 0x7ffe00 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f23bfb5; op2val:0x80000000;
op3val:0x877ffe00; valaddr_reg:x3; val_offset:98718*0 + 3*650*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 98718*0 + 3*650*FLEN/8, x4, x1, x2)

inst_32907:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x23bfb5 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x0e and fm3 == 0x7fff00 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f23bfb5; op2val:0x80000000;
op3val:0x877fff00; valaddr_reg:x3; val_offset:98721*0 + 3*651*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 98721*0 + 3*651*FLEN/8, x4, x1, x2)

inst_32908:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x23bfb5 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x0e and fm3 == 0x7fff80 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f23bfb5; op2val:0x80000000;
op3val:0x877fff80; valaddr_reg:x3; val_offset:98724*0 + 3*652*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 98724*0 + 3*652*FLEN/8, x4, x1, x2)

inst_32909:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x23bfb5 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x0e and fm3 == 0x7fffc0 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f23bfb5; op2val:0x80000000;
op3val:0x877fffc0; valaddr_reg:x3; val_offset:98727*0 + 3*653*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 98727*0 + 3*653*FLEN/8, x4, x1, x2)

inst_32910:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x23bfb5 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x0e and fm3 == 0x7fffe0 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f23bfb5; op2val:0x80000000;
op3val:0x877fffe0; valaddr_reg:x3; val_offset:98730*0 + 3*654*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 98730*0 + 3*654*FLEN/8, x4, x1, x2)

inst_32911:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x23bfb5 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x0e and fm3 == 0x7ffff0 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f23bfb5; op2val:0x80000000;
op3val:0x877ffff0; valaddr_reg:x3; val_offset:98733*0 + 3*655*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 98733*0 + 3*655*FLEN/8, x4, x1, x2)

inst_32912:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x23bfb5 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x0e and fm3 == 0x7ffff8 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f23bfb5; op2val:0x80000000;
op3val:0x877ffff8; valaddr_reg:x3; val_offset:98736*0 + 3*656*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 98736*0 + 3*656*FLEN/8, x4, x1, x2)

inst_32913:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x23bfb5 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x0e and fm3 == 0x7ffffc and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f23bfb5; op2val:0x80000000;
op3val:0x877ffffc; valaddr_reg:x3; val_offset:98739*0 + 3*657*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 98739*0 + 3*657*FLEN/8, x4, x1, x2)

inst_32914:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x23bfb5 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x0e and fm3 == 0x7ffffe and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f23bfb5; op2val:0x80000000;
op3val:0x877ffffe; valaddr_reg:x3; val_offset:98742*0 + 3*658*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 98742*0 + 3*658*FLEN/8, x4, x1, x2)

inst_32915:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x23bfb5 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x0e and fm3 == 0x7fffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f23bfb5; op2val:0x80000000;
op3val:0x877fffff; valaddr_reg:x3; val_offset:98745*0 + 3*659*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 98745*0 + 3*659*FLEN/8, x4, x1, x2)

inst_32916:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x23ecb7 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x31f963 and fs3 == 1 and fe3 == 0x43 and fm3 == 0x000000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f23ecb7; op2val:0x8031f963;
op3val:0xa1800000; valaddr_reg:x3; val_offset:98748*0 + 3*660*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 98748*0 + 3*660*FLEN/8, x4, x1, x2)

inst_32917:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x23ecb7 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x31f963 and fs3 == 1 and fe3 == 0x43 and fm3 == 0x000001 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f23ecb7; op2val:0x8031f963;
op3val:0xa1800001; valaddr_reg:x3; val_offset:98751*0 + 3*661*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 98751*0 + 3*661*FLEN/8, x4, x1, x2)

inst_32918:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x23ecb7 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x31f963 and fs3 == 1 and fe3 == 0x43 and fm3 == 0x000003 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f23ecb7; op2val:0x8031f963;
op3val:0xa1800003; valaddr_reg:x3; val_offset:98754*0 + 3*662*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 98754*0 + 3*662*FLEN/8, x4, x1, x2)

inst_32919:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x23ecb7 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x31f963 and fs3 == 1 and fe3 == 0x43 and fm3 == 0x000007 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f23ecb7; op2val:0x8031f963;
op3val:0xa1800007; valaddr_reg:x3; val_offset:98757*0 + 3*663*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 98757*0 + 3*663*FLEN/8, x4, x1, x2)

inst_32920:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x23ecb7 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x31f963 and fs3 == 1 and fe3 == 0x43 and fm3 == 0x00000f and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f23ecb7; op2val:0x8031f963;
op3val:0xa180000f; valaddr_reg:x3; val_offset:98760*0 + 3*664*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 98760*0 + 3*664*FLEN/8, x4, x1, x2)

inst_32921:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x23ecb7 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x31f963 and fs3 == 1 and fe3 == 0x43 and fm3 == 0x00001f and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f23ecb7; op2val:0x8031f963;
op3val:0xa180001f; valaddr_reg:x3; val_offset:98763*0 + 3*665*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 98763*0 + 3*665*FLEN/8, x4, x1, x2)

inst_32922:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x23ecb7 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x31f963 and fs3 == 1 and fe3 == 0x43 and fm3 == 0x00003f and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f23ecb7; op2val:0x8031f963;
op3val:0xa180003f; valaddr_reg:x3; val_offset:98766*0 + 3*666*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 98766*0 + 3*666*FLEN/8, x4, x1, x2)

inst_32923:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x23ecb7 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x31f963 and fs3 == 1 and fe3 == 0x43 and fm3 == 0x00007f and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f23ecb7; op2val:0x8031f963;
op3val:0xa180007f; valaddr_reg:x3; val_offset:98769*0 + 3*667*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 98769*0 + 3*667*FLEN/8, x4, x1, x2)

inst_32924:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x23ecb7 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x31f963 and fs3 == 1 and fe3 == 0x43 and fm3 == 0x0000ff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f23ecb7; op2val:0x8031f963;
op3val:0xa18000ff; valaddr_reg:x3; val_offset:98772*0 + 3*668*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 98772*0 + 3*668*FLEN/8, x4, x1, x2)

inst_32925:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x23ecb7 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x31f963 and fs3 == 1 and fe3 == 0x43 and fm3 == 0x0001ff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f23ecb7; op2val:0x8031f963;
op3val:0xa18001ff; valaddr_reg:x3; val_offset:98775*0 + 3*669*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 98775*0 + 3*669*FLEN/8, x4, x1, x2)

inst_32926:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x23ecb7 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x31f963 and fs3 == 1 and fe3 == 0x43 and fm3 == 0x0003ff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f23ecb7; op2val:0x8031f963;
op3val:0xa18003ff; valaddr_reg:x3; val_offset:98778*0 + 3*670*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 98778*0 + 3*670*FLEN/8, x4, x1, x2)

inst_32927:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x23ecb7 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x31f963 and fs3 == 1 and fe3 == 0x43 and fm3 == 0x0007ff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f23ecb7; op2val:0x8031f963;
op3val:0xa18007ff; valaddr_reg:x3; val_offset:98781*0 + 3*671*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 98781*0 + 3*671*FLEN/8, x4, x1, x2)

inst_32928:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x23ecb7 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x31f963 and fs3 == 1 and fe3 == 0x43 and fm3 == 0x000fff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f23ecb7; op2val:0x8031f963;
op3val:0xa1800fff; valaddr_reg:x3; val_offset:98784*0 + 3*672*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 98784*0 + 3*672*FLEN/8, x4, x1, x2)

inst_32929:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x23ecb7 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x31f963 and fs3 == 1 and fe3 == 0x43 and fm3 == 0x001fff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f23ecb7; op2val:0x8031f963;
op3val:0xa1801fff; valaddr_reg:x3; val_offset:98787*0 + 3*673*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 98787*0 + 3*673*FLEN/8, x4, x1, x2)

inst_32930:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x23ecb7 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x31f963 and fs3 == 1 and fe3 == 0x43 and fm3 == 0x003fff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f23ecb7; op2val:0x8031f963;
op3val:0xa1803fff; valaddr_reg:x3; val_offset:98790*0 + 3*674*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 98790*0 + 3*674*FLEN/8, x4, x1, x2)

inst_32931:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x23ecb7 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x31f963 and fs3 == 1 and fe3 == 0x43 and fm3 == 0x007fff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f23ecb7; op2val:0x8031f963;
op3val:0xa1807fff; valaddr_reg:x3; val_offset:98793*0 + 3*675*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 98793*0 + 3*675*FLEN/8, x4, x1, x2)

inst_32932:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x23ecb7 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x31f963 and fs3 == 1 and fe3 == 0x43 and fm3 == 0x00ffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f23ecb7; op2val:0x8031f963;
op3val:0xa180ffff; valaddr_reg:x3; val_offset:98796*0 + 3*676*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 98796*0 + 3*676*FLEN/8, x4, x1, x2)

inst_32933:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x23ecb7 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x31f963 and fs3 == 1 and fe3 == 0x43 and fm3 == 0x01ffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f23ecb7; op2val:0x8031f963;
op3val:0xa181ffff; valaddr_reg:x3; val_offset:98799*0 + 3*677*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 98799*0 + 3*677*FLEN/8, x4, x1, x2)

inst_32934:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x23ecb7 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x31f963 and fs3 == 1 and fe3 == 0x43 and fm3 == 0x03ffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f23ecb7; op2val:0x8031f963;
op3val:0xa183ffff; valaddr_reg:x3; val_offset:98802*0 + 3*678*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 98802*0 + 3*678*FLEN/8, x4, x1, x2)

inst_32935:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x23ecb7 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x31f963 and fs3 == 1 and fe3 == 0x43 and fm3 == 0x07ffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f23ecb7; op2val:0x8031f963;
op3val:0xa187ffff; valaddr_reg:x3; val_offset:98805*0 + 3*679*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 98805*0 + 3*679*FLEN/8, x4, x1, x2)

inst_32936:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x23ecb7 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x31f963 and fs3 == 1 and fe3 == 0x43 and fm3 == 0x0fffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f23ecb7; op2val:0x8031f963;
op3val:0xa18fffff; valaddr_reg:x3; val_offset:98808*0 + 3*680*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 98808*0 + 3*680*FLEN/8, x4, x1, x2)

inst_32937:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x23ecb7 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x31f963 and fs3 == 1 and fe3 == 0x43 and fm3 == 0x1fffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f23ecb7; op2val:0x8031f963;
op3val:0xa19fffff; valaddr_reg:x3; val_offset:98811*0 + 3*681*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 98811*0 + 3*681*FLEN/8, x4, x1, x2)

inst_32938:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x23ecb7 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x31f963 and fs3 == 1 and fe3 == 0x43 and fm3 == 0x3fffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f23ecb7; op2val:0x8031f963;
op3val:0xa1bfffff; valaddr_reg:x3; val_offset:98814*0 + 3*682*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 98814*0 + 3*682*FLEN/8, x4, x1, x2)

inst_32939:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x23ecb7 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x31f963 and fs3 == 1 and fe3 == 0x43 and fm3 == 0x400000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f23ecb7; op2val:0x8031f963;
op3val:0xa1c00000; valaddr_reg:x3; val_offset:98817*0 + 3*683*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 98817*0 + 3*683*FLEN/8, x4, x1, x2)

inst_32940:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x23ecb7 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x31f963 and fs3 == 1 and fe3 == 0x43 and fm3 == 0x600000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f23ecb7; op2val:0x8031f963;
op3val:0xa1e00000; valaddr_reg:x3; val_offset:98820*0 + 3*684*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 98820*0 + 3*684*FLEN/8, x4, x1, x2)

inst_32941:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x23ecb7 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x31f963 and fs3 == 1 and fe3 == 0x43 and fm3 == 0x700000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f23ecb7; op2val:0x8031f963;
op3val:0xa1f00000; valaddr_reg:x3; val_offset:98823*0 + 3*685*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 98823*0 + 3*685*FLEN/8, x4, x1, x2)

inst_32942:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x23ecb7 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x31f963 and fs3 == 1 and fe3 == 0x43 and fm3 == 0x780000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f23ecb7; op2val:0x8031f963;
op3val:0xa1f80000; valaddr_reg:x3; val_offset:98826*0 + 3*686*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 98826*0 + 3*686*FLEN/8, x4, x1, x2)

inst_32943:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x23ecb7 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x31f963 and fs3 == 1 and fe3 == 0x43 and fm3 == 0x7c0000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f23ecb7; op2val:0x8031f963;
op3val:0xa1fc0000; valaddr_reg:x3; val_offset:98829*0 + 3*687*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 98829*0 + 3*687*FLEN/8, x4, x1, x2)

inst_32944:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x23ecb7 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x31f963 and fs3 == 1 and fe3 == 0x43 and fm3 == 0x7e0000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f23ecb7; op2val:0x8031f963;
op3val:0xa1fe0000; valaddr_reg:x3; val_offset:98832*0 + 3*688*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 98832*0 + 3*688*FLEN/8, x4, x1, x2)

inst_32945:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x23ecb7 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x31f963 and fs3 == 1 and fe3 == 0x43 and fm3 == 0x7f0000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f23ecb7; op2val:0x8031f963;
op3val:0xa1ff0000; valaddr_reg:x3; val_offset:98835*0 + 3*689*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 98835*0 + 3*689*FLEN/8, x4, x1, x2)

inst_32946:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x23ecb7 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x31f963 and fs3 == 1 and fe3 == 0x43 and fm3 == 0x7f8000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f23ecb7; op2val:0x8031f963;
op3val:0xa1ff8000; valaddr_reg:x3; val_offset:98838*0 + 3*690*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 98838*0 + 3*690*FLEN/8, x4, x1, x2)

inst_32947:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x23ecb7 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x31f963 and fs3 == 1 and fe3 == 0x43 and fm3 == 0x7fc000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f23ecb7; op2val:0x8031f963;
op3val:0xa1ffc000; valaddr_reg:x3; val_offset:98841*0 + 3*691*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 98841*0 + 3*691*FLEN/8, x4, x1, x2)

inst_32948:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x23ecb7 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x31f963 and fs3 == 1 and fe3 == 0x43 and fm3 == 0x7fe000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f23ecb7; op2val:0x8031f963;
op3val:0xa1ffe000; valaddr_reg:x3; val_offset:98844*0 + 3*692*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 98844*0 + 3*692*FLEN/8, x4, x1, x2)

inst_32949:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x23ecb7 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x31f963 and fs3 == 1 and fe3 == 0x43 and fm3 == 0x7ff000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f23ecb7; op2val:0x8031f963;
op3val:0xa1fff000; valaddr_reg:x3; val_offset:98847*0 + 3*693*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 98847*0 + 3*693*FLEN/8, x4, x1, x2)

inst_32950:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x23ecb7 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x31f963 and fs3 == 1 and fe3 == 0x43 and fm3 == 0x7ff800 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f23ecb7; op2val:0x8031f963;
op3val:0xa1fff800; valaddr_reg:x3; val_offset:98850*0 + 3*694*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 98850*0 + 3*694*FLEN/8, x4, x1, x2)

inst_32951:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x23ecb7 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x31f963 and fs3 == 1 and fe3 == 0x43 and fm3 == 0x7ffc00 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f23ecb7; op2val:0x8031f963;
op3val:0xa1fffc00; valaddr_reg:x3; val_offset:98853*0 + 3*695*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 98853*0 + 3*695*FLEN/8, x4, x1, x2)

inst_32952:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x23ecb7 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x31f963 and fs3 == 1 and fe3 == 0x43 and fm3 == 0x7ffe00 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f23ecb7; op2val:0x8031f963;
op3val:0xa1fffe00; valaddr_reg:x3; val_offset:98856*0 + 3*696*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 98856*0 + 3*696*FLEN/8, x4, x1, x2)

inst_32953:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x23ecb7 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x31f963 and fs3 == 1 and fe3 == 0x43 and fm3 == 0x7fff00 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f23ecb7; op2val:0x8031f963;
op3val:0xa1ffff00; valaddr_reg:x3; val_offset:98859*0 + 3*697*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 98859*0 + 3*697*FLEN/8, x4, x1, x2)

inst_32954:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x23ecb7 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x31f963 and fs3 == 1 and fe3 == 0x43 and fm3 == 0x7fff80 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f23ecb7; op2val:0x8031f963;
op3val:0xa1ffff80; valaddr_reg:x3; val_offset:98862*0 + 3*698*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 98862*0 + 3*698*FLEN/8, x4, x1, x2)

inst_32955:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x23ecb7 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x31f963 and fs3 == 1 and fe3 == 0x43 and fm3 == 0x7fffc0 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f23ecb7; op2val:0x8031f963;
op3val:0xa1ffffc0; valaddr_reg:x3; val_offset:98865*0 + 3*699*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 98865*0 + 3*699*FLEN/8, x4, x1, x2)

inst_32956:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x23ecb7 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x31f963 and fs3 == 1 and fe3 == 0x43 and fm3 == 0x7fffe0 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f23ecb7; op2val:0x8031f963;
op3val:0xa1ffffe0; valaddr_reg:x3; val_offset:98868*0 + 3*700*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 98868*0 + 3*700*FLEN/8, x4, x1, x2)

inst_32957:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x23ecb7 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x31f963 and fs3 == 1 and fe3 == 0x43 and fm3 == 0x7ffff0 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f23ecb7; op2val:0x8031f963;
op3val:0xa1fffff0; valaddr_reg:x3; val_offset:98871*0 + 3*701*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 98871*0 + 3*701*FLEN/8, x4, x1, x2)

inst_32958:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x23ecb7 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x31f963 and fs3 == 1 and fe3 == 0x43 and fm3 == 0x7ffff8 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f23ecb7; op2val:0x8031f963;
op3val:0xa1fffff8; valaddr_reg:x3; val_offset:98874*0 + 3*702*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 98874*0 + 3*702*FLEN/8, x4, x1, x2)

inst_32959:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x23ecb7 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x31f963 and fs3 == 1 and fe3 == 0x43 and fm3 == 0x7ffffc and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f23ecb7; op2val:0x8031f963;
op3val:0xa1fffffc; valaddr_reg:x3; val_offset:98877*0 + 3*703*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 98877*0 + 3*703*FLEN/8, x4, x1, x2)

inst_32960:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x23ecb7 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x31f963 and fs3 == 1 and fe3 == 0x43 and fm3 == 0x7ffffe and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f23ecb7; op2val:0x8031f963;
op3val:0xa1fffffe; valaddr_reg:x3; val_offset:98880*0 + 3*704*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 98880*0 + 3*704*FLEN/8, x4, x1, x2)

inst_32961:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x23ecb7 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x31f963 and fs3 == 1 and fe3 == 0x43 and fm3 == 0x7fffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f23ecb7; op2val:0x8031f963;
op3val:0xa1ffffff; valaddr_reg:x3; val_offset:98883*0 + 3*705*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 98883*0 + 3*705*FLEN/8, x4, x1, x2)

inst_32962:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x23ecb7 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x31f963 and fs3 == 1 and fe3 == 0x7f and fm3 == 0x000001 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f23ecb7; op2val:0x8031f963;
op3val:0xbf800001; valaddr_reg:x3; val_offset:98886*0 + 3*706*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 98886*0 + 3*706*FLEN/8, x4, x1, x2)

inst_32963:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x23ecb7 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x31f963 and fs3 == 1 and fe3 == 0x7f and fm3 == 0x000003 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f23ecb7; op2val:0x8031f963;
op3val:0xbf800003; valaddr_reg:x3; val_offset:98889*0 + 3*707*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 98889*0 + 3*707*FLEN/8, x4, x1, x2)

inst_32964:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x23ecb7 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x31f963 and fs3 == 1 and fe3 == 0x7f and fm3 == 0x000007 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f23ecb7; op2val:0x8031f963;
op3val:0xbf800007; valaddr_reg:x3; val_offset:98892*0 + 3*708*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 98892*0 + 3*708*FLEN/8, x4, x1, x2)

inst_32965:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x23ecb7 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x31f963 and fs3 == 1 and fe3 == 0x7f and fm3 == 0x199999 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f23ecb7; op2val:0x8031f963;
op3val:0xbf999999; valaddr_reg:x3; val_offset:98895*0 + 3*709*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 98895*0 + 3*709*FLEN/8, x4, x1, x2)

inst_32966:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x23ecb7 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x31f963 and fs3 == 1 and fe3 == 0x7f and fm3 == 0x249249 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f23ecb7; op2val:0x8031f963;
op3val:0xbfa49249; valaddr_reg:x3; val_offset:98898*0 + 3*710*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 98898*0 + 3*710*FLEN/8, x4, x1, x2)

inst_32967:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x23ecb7 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x31f963 and fs3 == 1 and fe3 == 0x7f and fm3 == 0x333333 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f23ecb7; op2val:0x8031f963;
op3val:0xbfb33333; valaddr_reg:x3; val_offset:98901*0 + 3*711*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 98901*0 + 3*711*FLEN/8, x4, x1, x2)

inst_32968:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x23ecb7 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x31f963 and fs3 == 1 and fe3 == 0x7f and fm3 == 0x36db6d and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f23ecb7; op2val:0x8031f963;
op3val:0xbfb6db6d; valaddr_reg:x3; val_offset:98904*0 + 3*712*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 98904*0 + 3*712*FLEN/8, x4, x1, x2)

inst_32969:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x23ecb7 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x31f963 and fs3 == 1 and fe3 == 0x7f and fm3 == 0x3bbbbb and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f23ecb7; op2val:0x8031f963;
op3val:0xbfbbbbbb; valaddr_reg:x3; val_offset:98907*0 + 3*713*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 98907*0 + 3*713*FLEN/8, x4, x1, x2)

inst_32970:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x23ecb7 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x31f963 and fs3 == 1 and fe3 == 0x7f and fm3 == 0x444444 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f23ecb7; op2val:0x8031f963;
op3val:0xbfc44444; valaddr_reg:x3; val_offset:98910*0 + 3*714*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 98910*0 + 3*714*FLEN/8, x4, x1, x2)

inst_32971:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x23ecb7 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x31f963 and fs3 == 1 and fe3 == 0x7f and fm3 == 0x4ccccc and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f23ecb7; op2val:0x8031f963;
op3val:0xbfcccccc; valaddr_reg:x3; val_offset:98913*0 + 3*715*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 98913*0 + 3*715*FLEN/8, x4, x1, x2)

inst_32972:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x23ecb7 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x31f963 and fs3 == 1 and fe3 == 0x7f and fm3 == 0x5b6db6 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f23ecb7; op2val:0x8031f963;
op3val:0xbfdb6db6; valaddr_reg:x3; val_offset:98916*0 + 3*716*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 98916*0 + 3*716*FLEN/8, x4, x1, x2)

inst_32973:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x23ecb7 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x31f963 and fs3 == 1 and fe3 == 0x7f and fm3 == 0x666666 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f23ecb7; op2val:0x8031f963;
op3val:0xbfe66666; valaddr_reg:x3; val_offset:98919*0 + 3*717*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 98919*0 + 3*717*FLEN/8, x4, x1, x2)

inst_32974:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x23ecb7 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x31f963 and fs3 == 1 and fe3 == 0x7f and fm3 == 0x6db6db and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f23ecb7; op2val:0x8031f963;
op3val:0xbfedb6db; valaddr_reg:x3; val_offset:98922*0 + 3*718*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 98922*0 + 3*718*FLEN/8, x4, x1, x2)

inst_32975:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x23ecb7 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x31f963 and fs3 == 1 and fe3 == 0x7f and fm3 == 0x7ffff8 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f23ecb7; op2val:0x8031f963;
op3val:0xbffffff8; valaddr_reg:x3; val_offset:98925*0 + 3*719*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 98925*0 + 3*719*FLEN/8, x4, x1, x2)

inst_32976:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x23ecb7 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x31f963 and fs3 == 1 and fe3 == 0x7f and fm3 == 0x7ffffc and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f23ecb7; op2val:0x8031f963;
op3val:0xbffffffc; valaddr_reg:x3; val_offset:98928*0 + 3*720*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 98928*0 + 3*720*FLEN/8, x4, x1, x2)

inst_32977:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x23ecb7 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x31f963 and fs3 == 1 and fe3 == 0x7f and fm3 == 0x7ffffe and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f23ecb7; op2val:0x8031f963;
op3val:0xbffffffe; valaddr_reg:x3; val_offset:98931*0 + 3*721*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 98931*0 + 3*721*FLEN/8, x4, x1, x2)

inst_32978:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x2438d0 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x31e23b and fs3 == 0 and fe3 == 0x62 and fm3 == 0x000000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f2438d0; op2val:0x31e23b;
op3val:0x31000000; valaddr_reg:x3; val_offset:98934*0 + 3*722*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 98934*0 + 3*722*FLEN/8, x4, x1, x2)

inst_32979:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x2438d0 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x31e23b and fs3 == 0 and fe3 == 0x62 and fm3 == 0x000001 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f2438d0; op2val:0x31e23b;
op3val:0x31000001; valaddr_reg:x3; val_offset:98937*0 + 3*723*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 98937*0 + 3*723*FLEN/8, x4, x1, x2)

inst_32980:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x2438d0 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x31e23b and fs3 == 0 and fe3 == 0x62 and fm3 == 0x000003 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f2438d0; op2val:0x31e23b;
op3val:0x31000003; valaddr_reg:x3; val_offset:98940*0 + 3*724*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 98940*0 + 3*724*FLEN/8, x4, x1, x2)

inst_32981:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x2438d0 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x31e23b and fs3 == 0 and fe3 == 0x62 and fm3 == 0x000007 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f2438d0; op2val:0x31e23b;
op3val:0x31000007; valaddr_reg:x3; val_offset:98943*0 + 3*725*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 98943*0 + 3*725*FLEN/8, x4, x1, x2)

inst_32982:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x2438d0 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x31e23b and fs3 == 0 and fe3 == 0x62 and fm3 == 0x00000f and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f2438d0; op2val:0x31e23b;
op3val:0x3100000f; valaddr_reg:x3; val_offset:98946*0 + 3*726*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 98946*0 + 3*726*FLEN/8, x4, x1, x2)

inst_32983:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x2438d0 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x31e23b and fs3 == 0 and fe3 == 0x62 and fm3 == 0x00001f and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f2438d0; op2val:0x31e23b;
op3val:0x3100001f; valaddr_reg:x3; val_offset:98949*0 + 3*727*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 98949*0 + 3*727*FLEN/8, x4, x1, x2)

inst_32984:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x2438d0 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x31e23b and fs3 == 0 and fe3 == 0x62 and fm3 == 0x00003f and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f2438d0; op2val:0x31e23b;
op3val:0x3100003f; valaddr_reg:x3; val_offset:98952*0 + 3*728*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 98952*0 + 3*728*FLEN/8, x4, x1, x2)

inst_32985:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x2438d0 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x31e23b and fs3 == 0 and fe3 == 0x62 and fm3 == 0x00007f and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f2438d0; op2val:0x31e23b;
op3val:0x3100007f; valaddr_reg:x3; val_offset:98955*0 + 3*729*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 98955*0 + 3*729*FLEN/8, x4, x1, x2)

inst_32986:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x2438d0 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x31e23b and fs3 == 0 and fe3 == 0x62 and fm3 == 0x0000ff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f2438d0; op2val:0x31e23b;
op3val:0x310000ff; valaddr_reg:x3; val_offset:98958*0 + 3*730*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 98958*0 + 3*730*FLEN/8, x4, x1, x2)

inst_32987:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x2438d0 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x31e23b and fs3 == 0 and fe3 == 0x62 and fm3 == 0x0001ff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f2438d0; op2val:0x31e23b;
op3val:0x310001ff; valaddr_reg:x3; val_offset:98961*0 + 3*731*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 98961*0 + 3*731*FLEN/8, x4, x1, x2)

inst_32988:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x2438d0 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x31e23b and fs3 == 0 and fe3 == 0x62 and fm3 == 0x0003ff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f2438d0; op2val:0x31e23b;
op3val:0x310003ff; valaddr_reg:x3; val_offset:98964*0 + 3*732*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 98964*0 + 3*732*FLEN/8, x4, x1, x2)

inst_32989:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x2438d0 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x31e23b and fs3 == 0 and fe3 == 0x62 and fm3 == 0x0007ff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f2438d0; op2val:0x31e23b;
op3val:0x310007ff; valaddr_reg:x3; val_offset:98967*0 + 3*733*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 98967*0 + 3*733*FLEN/8, x4, x1, x2)

inst_32990:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x2438d0 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x31e23b and fs3 == 0 and fe3 == 0x62 and fm3 == 0x000fff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f2438d0; op2val:0x31e23b;
op3val:0x31000fff; valaddr_reg:x3; val_offset:98970*0 + 3*734*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 98970*0 + 3*734*FLEN/8, x4, x1, x2)

inst_32991:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x2438d0 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x31e23b and fs3 == 0 and fe3 == 0x62 and fm3 == 0x001fff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f2438d0; op2val:0x31e23b;
op3val:0x31001fff; valaddr_reg:x3; val_offset:98973*0 + 3*735*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 98973*0 + 3*735*FLEN/8, x4, x1, x2)

inst_32992:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x2438d0 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x31e23b and fs3 == 0 and fe3 == 0x62 and fm3 == 0x003fff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f2438d0; op2val:0x31e23b;
op3val:0x31003fff; valaddr_reg:x3; val_offset:98976*0 + 3*736*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 98976*0 + 3*736*FLEN/8, x4, x1, x2)

inst_32993:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x2438d0 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x31e23b and fs3 == 0 and fe3 == 0x62 and fm3 == 0x007fff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f2438d0; op2val:0x31e23b;
op3val:0x31007fff; valaddr_reg:x3; val_offset:98979*0 + 3*737*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 98979*0 + 3*737*FLEN/8, x4, x1, x2)

inst_32994:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x2438d0 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x31e23b and fs3 == 0 and fe3 == 0x62 and fm3 == 0x00ffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f2438d0; op2val:0x31e23b;
op3val:0x3100ffff; valaddr_reg:x3; val_offset:98982*0 + 3*738*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 98982*0 + 3*738*FLEN/8, x4, x1, x2)

inst_32995:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x2438d0 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x31e23b and fs3 == 0 and fe3 == 0x62 and fm3 == 0x01ffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f2438d0; op2val:0x31e23b;
op3val:0x3101ffff; valaddr_reg:x3; val_offset:98985*0 + 3*739*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 98985*0 + 3*739*FLEN/8, x4, x1, x2)

inst_32996:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x2438d0 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x31e23b and fs3 == 0 and fe3 == 0x62 and fm3 == 0x03ffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f2438d0; op2val:0x31e23b;
op3val:0x3103ffff; valaddr_reg:x3; val_offset:98988*0 + 3*740*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 98988*0 + 3*740*FLEN/8, x4, x1, x2)

inst_32997:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x2438d0 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x31e23b and fs3 == 0 and fe3 == 0x62 and fm3 == 0x07ffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f2438d0; op2val:0x31e23b;
op3val:0x3107ffff; valaddr_reg:x3; val_offset:98991*0 + 3*741*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 98991*0 + 3*741*FLEN/8, x4, x1, x2)

inst_32998:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x2438d0 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x31e23b and fs3 == 0 and fe3 == 0x62 and fm3 == 0x0fffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f2438d0; op2val:0x31e23b;
op3val:0x310fffff; valaddr_reg:x3; val_offset:98994*0 + 3*742*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 98994*0 + 3*742*FLEN/8, x4, x1, x2)

inst_32999:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x2438d0 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x31e23b and fs3 == 0 and fe3 == 0x62 and fm3 == 0x1fffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f2438d0; op2val:0x31e23b;
op3val:0x311fffff; valaddr_reg:x3; val_offset:98997*0 + 3*743*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 98997*0 + 3*743*FLEN/8, x4, x1, x2)

inst_33000:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x2438d0 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x31e23b and fs3 == 0 and fe3 == 0x62 and fm3 == 0x3fffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f2438d0; op2val:0x31e23b;
op3val:0x313fffff; valaddr_reg:x3; val_offset:99000*0 + 3*744*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 99000*0 + 3*744*FLEN/8, x4, x1, x2)

inst_33001:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x2438d0 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x31e23b and fs3 == 0 and fe3 == 0x62 and fm3 == 0x400000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f2438d0; op2val:0x31e23b;
op3val:0x31400000; valaddr_reg:x3; val_offset:99003*0 + 3*745*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 99003*0 + 3*745*FLEN/8, x4, x1, x2)

inst_33002:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x2438d0 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x31e23b and fs3 == 0 and fe3 == 0x62 and fm3 == 0x600000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f2438d0; op2val:0x31e23b;
op3val:0x31600000; valaddr_reg:x3; val_offset:99006*0 + 3*746*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 99006*0 + 3*746*FLEN/8, x4, x1, x2)

inst_33003:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x2438d0 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x31e23b and fs3 == 0 and fe3 == 0x62 and fm3 == 0x700000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f2438d0; op2val:0x31e23b;
op3val:0x31700000; valaddr_reg:x3; val_offset:99009*0 + 3*747*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 99009*0 + 3*747*FLEN/8, x4, x1, x2)

inst_33004:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x2438d0 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x31e23b and fs3 == 0 and fe3 == 0x62 and fm3 == 0x780000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f2438d0; op2val:0x31e23b;
op3val:0x31780000; valaddr_reg:x3; val_offset:99012*0 + 3*748*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 99012*0 + 3*748*FLEN/8, x4, x1, x2)

inst_33005:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x2438d0 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x31e23b and fs3 == 0 and fe3 == 0x62 and fm3 == 0x7c0000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f2438d0; op2val:0x31e23b;
op3val:0x317c0000; valaddr_reg:x3; val_offset:99015*0 + 3*749*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 99015*0 + 3*749*FLEN/8, x4, x1, x2)

inst_33006:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x2438d0 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x31e23b and fs3 == 0 and fe3 == 0x62 and fm3 == 0x7e0000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f2438d0; op2val:0x31e23b;
op3val:0x317e0000; valaddr_reg:x3; val_offset:99018*0 + 3*750*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 99018*0 + 3*750*FLEN/8, x4, x1, x2)

inst_33007:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x2438d0 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x31e23b and fs3 == 0 and fe3 == 0x62 and fm3 == 0x7f0000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f2438d0; op2val:0x31e23b;
op3val:0x317f0000; valaddr_reg:x3; val_offset:99021*0 + 3*751*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 99021*0 + 3*751*FLEN/8, x4, x1, x2)

inst_33008:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x2438d0 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x31e23b and fs3 == 0 and fe3 == 0x62 and fm3 == 0x7f8000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f2438d0; op2val:0x31e23b;
op3val:0x317f8000; valaddr_reg:x3; val_offset:99024*0 + 3*752*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 99024*0 + 3*752*FLEN/8, x4, x1, x2)

inst_33009:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x2438d0 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x31e23b and fs3 == 0 and fe3 == 0x62 and fm3 == 0x7fc000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f2438d0; op2val:0x31e23b;
op3val:0x317fc000; valaddr_reg:x3; val_offset:99027*0 + 3*753*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 99027*0 + 3*753*FLEN/8, x4, x1, x2)

inst_33010:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x2438d0 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x31e23b and fs3 == 0 and fe3 == 0x62 and fm3 == 0x7fe000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f2438d0; op2val:0x31e23b;
op3val:0x317fe000; valaddr_reg:x3; val_offset:99030*0 + 3*754*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 99030*0 + 3*754*FLEN/8, x4, x1, x2)

inst_33011:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x2438d0 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x31e23b and fs3 == 0 and fe3 == 0x62 and fm3 == 0x7ff000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f2438d0; op2val:0x31e23b;
op3val:0x317ff000; valaddr_reg:x3; val_offset:99033*0 + 3*755*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 99033*0 + 3*755*FLEN/8, x4, x1, x2)

inst_33012:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x2438d0 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x31e23b and fs3 == 0 and fe3 == 0x62 and fm3 == 0x7ff800 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f2438d0; op2val:0x31e23b;
op3val:0x317ff800; valaddr_reg:x3; val_offset:99036*0 + 3*756*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 99036*0 + 3*756*FLEN/8, x4, x1, x2)

inst_33013:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x2438d0 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x31e23b and fs3 == 0 and fe3 == 0x62 and fm3 == 0x7ffc00 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f2438d0; op2val:0x31e23b;
op3val:0x317ffc00; valaddr_reg:x3; val_offset:99039*0 + 3*757*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 99039*0 + 3*757*FLEN/8, x4, x1, x2)

inst_33014:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x2438d0 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x31e23b and fs3 == 0 and fe3 == 0x62 and fm3 == 0x7ffe00 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f2438d0; op2val:0x31e23b;
op3val:0x317ffe00; valaddr_reg:x3; val_offset:99042*0 + 3*758*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 99042*0 + 3*758*FLEN/8, x4, x1, x2)

inst_33015:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x2438d0 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x31e23b and fs3 == 0 and fe3 == 0x62 and fm3 == 0x7fff00 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f2438d0; op2val:0x31e23b;
op3val:0x317fff00; valaddr_reg:x3; val_offset:99045*0 + 3*759*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 99045*0 + 3*759*FLEN/8, x4, x1, x2)

inst_33016:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x2438d0 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x31e23b and fs3 == 0 and fe3 == 0x62 and fm3 == 0x7fff80 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f2438d0; op2val:0x31e23b;
op3val:0x317fff80; valaddr_reg:x3; val_offset:99048*0 + 3*760*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 99048*0 + 3*760*FLEN/8, x4, x1, x2)

inst_33017:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x2438d0 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x31e23b and fs3 == 0 and fe3 == 0x62 and fm3 == 0x7fffc0 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f2438d0; op2val:0x31e23b;
op3val:0x317fffc0; valaddr_reg:x3; val_offset:99051*0 + 3*761*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 99051*0 + 3*761*FLEN/8, x4, x1, x2)

inst_33018:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x2438d0 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x31e23b and fs3 == 0 and fe3 == 0x62 and fm3 == 0x7fffe0 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f2438d0; op2val:0x31e23b;
op3val:0x317fffe0; valaddr_reg:x3; val_offset:99054*0 + 3*762*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 99054*0 + 3*762*FLEN/8, x4, x1, x2)

inst_33019:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x2438d0 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x31e23b and fs3 == 0 and fe3 == 0x62 and fm3 == 0x7ffff0 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f2438d0; op2val:0x31e23b;
op3val:0x317ffff0; valaddr_reg:x3; val_offset:99057*0 + 3*763*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 99057*0 + 3*763*FLEN/8, x4, x1, x2)

inst_33020:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x2438d0 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x31e23b and fs3 == 0 and fe3 == 0x62 and fm3 == 0x7ffff8 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f2438d0; op2val:0x31e23b;
op3val:0x317ffff8; valaddr_reg:x3; val_offset:99060*0 + 3*764*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 99060*0 + 3*764*FLEN/8, x4, x1, x2)

inst_33021:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x2438d0 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x31e23b and fs3 == 0 and fe3 == 0x62 and fm3 == 0x7ffffc and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f2438d0; op2val:0x31e23b;
op3val:0x317ffffc; valaddr_reg:x3; val_offset:99063*0 + 3*765*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 99063*0 + 3*765*FLEN/8, x4, x1, x2)

inst_33022:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x2438d0 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x31e23b and fs3 == 0 and fe3 == 0x62 and fm3 == 0x7ffffe and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f2438d0; op2val:0x31e23b;
op3val:0x317ffffe; valaddr_reg:x3; val_offset:99066*0 + 3*766*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 99066*0 + 3*766*FLEN/8, x4, x1, x2)

inst_33023:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x2438d0 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x31e23b and fs3 == 0 and fe3 == 0x62 and fm3 == 0x7fffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f2438d0; op2val:0x31e23b;
op3val:0x317fffff; valaddr_reg:x3; val_offset:99069*0 + 3*767*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 99069*0 + 3*767*FLEN/8, x4, x1, x2)
#endif


RVTEST_CODE_END
RVMODEL_HALT

RVTEST_DATA_BEGIN
.align 4
rvtest_data:
.word 0xbabecafe
.word 0xabecafeb
.word 0xbecafeba
.word 0xecafebab
test_dataset_0:
NAN_BOXED(0x7f20dec0,32,FLEN)
NAN_BOXED(0x32ec4e,32,FLEN)
NAN_BOXED(0x2380ffff,32,FLEN)
NAN_BOXED(0x7f20dec0,32,FLEN)
NAN_BOXED(0x32ec4e,32,FLEN)
NAN_BOXED(0x2381ffff,32,FLEN)
NAN_BOXED(0x7f20dec0,32,FLEN)
NAN_BOXED(0x32ec4e,32,FLEN)
NAN_BOXED(0x2383ffff,32,FLEN)
NAN_BOXED(0x7f20dec0,32,FLEN)
NAN_BOXED(0x32ec4e,32,FLEN)
NAN_BOXED(0x2387ffff,32,FLEN)
NAN_BOXED(0x7f20dec0,32,FLEN)
NAN_BOXED(0x32ec4e,32,FLEN)
NAN_BOXED(0x238fffff,32,FLEN)
NAN_BOXED(0x7f20dec0,32,FLEN)
NAN_BOXED(0x32ec4e,32,FLEN)
NAN_BOXED(0x239fffff,32,FLEN)
NAN_BOXED(0x7f20dec0,32,FLEN)
NAN_BOXED(0x32ec4e,32,FLEN)
NAN_BOXED(0x23bfffff,32,FLEN)
NAN_BOXED(0x7f20dec0,32,FLEN)
NAN_BOXED(0x32ec4e,32,FLEN)
NAN_BOXED(0x23c00000,32,FLEN)
NAN_BOXED(0x7f20dec0,32,FLEN)
NAN_BOXED(0x32ec4e,32,FLEN)
NAN_BOXED(0x23e00000,32,FLEN)
NAN_BOXED(0x7f20dec0,32,FLEN)
NAN_BOXED(0x32ec4e,32,FLEN)
NAN_BOXED(0x23f00000,32,FLEN)
NAN_BOXED(0x7f20dec0,32,FLEN)
NAN_BOXED(0x32ec4e,32,FLEN)
NAN_BOXED(0x23f80000,32,FLEN)
NAN_BOXED(0x7f20dec0,32,FLEN)
NAN_BOXED(0x32ec4e,32,FLEN)
NAN_BOXED(0x23fc0000,32,FLEN)
NAN_BOXED(0x7f20dec0,32,FLEN)
NAN_BOXED(0x32ec4e,32,FLEN)
NAN_BOXED(0x23fe0000,32,FLEN)
NAN_BOXED(0x7f20dec0,32,FLEN)
NAN_BOXED(0x32ec4e,32,FLEN)
NAN_BOXED(0x23ff0000,32,FLEN)
NAN_BOXED(0x7f20dec0,32,FLEN)
NAN_BOXED(0x32ec4e,32,FLEN)
NAN_BOXED(0x23ff8000,32,FLEN)
NAN_BOXED(0x7f20dec0,32,FLEN)
NAN_BOXED(0x32ec4e,32,FLEN)
NAN_BOXED(0x23ffc000,32,FLEN)
NAN_BOXED(0x7f20dec0,32,FLEN)
NAN_BOXED(0x32ec4e,32,FLEN)
NAN_BOXED(0x23ffe000,32,FLEN)
NAN_BOXED(0x7f20dec0,32,FLEN)
NAN_BOXED(0x32ec4e,32,FLEN)
NAN_BOXED(0x23fff000,32,FLEN)
NAN_BOXED(0x7f20dec0,32,FLEN)
NAN_BOXED(0x32ec4e,32,FLEN)
NAN_BOXED(0x23fff800,32,FLEN)
NAN_BOXED(0x7f20dec0,32,FLEN)
NAN_BOXED(0x32ec4e,32,FLEN)
NAN_BOXED(0x23fffc00,32,FLEN)
NAN_BOXED(0x7f20dec0,32,FLEN)
NAN_BOXED(0x32ec4e,32,FLEN)
NAN_BOXED(0x23fffe00,32,FLEN)
NAN_BOXED(0x7f20dec0,32,FLEN)
NAN_BOXED(0x32ec4e,32,FLEN)
NAN_BOXED(0x23ffff00,32,FLEN)
NAN_BOXED(0x7f20dec0,32,FLEN)
NAN_BOXED(0x32ec4e,32,FLEN)
NAN_BOXED(0x23ffff80,32,FLEN)
NAN_BOXED(0x7f20dec0,32,FLEN)
NAN_BOXED(0x32ec4e,32,FLEN)
NAN_BOXED(0x23ffffc0,32,FLEN)
NAN_BOXED(0x7f20dec0,32,FLEN)
NAN_BOXED(0x32ec4e,32,FLEN)
NAN_BOXED(0x23ffffe0,32,FLEN)
NAN_BOXED(0x7f20dec0,32,FLEN)
NAN_BOXED(0x32ec4e,32,FLEN)
NAN_BOXED(0x23fffff0,32,FLEN)
NAN_BOXED(0x7f20dec0,32,FLEN)
NAN_BOXED(0x32ec4e,32,FLEN)
NAN_BOXED(0x23fffff8,32,FLEN)
NAN_BOXED(0x7f20dec0,32,FLEN)
NAN_BOXED(0x32ec4e,32,FLEN)
NAN_BOXED(0x23fffffc,32,FLEN)
NAN_BOXED(0x7f20dec0,32,FLEN)
NAN_BOXED(0x32ec4e,32,FLEN)
NAN_BOXED(0x23fffffe,32,FLEN)
NAN_BOXED(0x7f20dec0,32,FLEN)
NAN_BOXED(0x32ec4e,32,FLEN)
NAN_BOXED(0x23ffffff,32,FLEN)
NAN_BOXED(0x7f20dec0,32,FLEN)
NAN_BOXED(0x32ec4e,32,FLEN)
NAN_BOXED(0x3f800001,32,FLEN)
NAN_BOXED(0x7f20dec0,32,FLEN)
NAN_BOXED(0x32ec4e,32,FLEN)
NAN_BOXED(0x3f800003,32,FLEN)
NAN_BOXED(0x7f20dec0,32,FLEN)
NAN_BOXED(0x32ec4e,32,FLEN)
NAN_BOXED(0x3f800007,32,FLEN)
NAN_BOXED(0x7f20dec0,32,FLEN)
NAN_BOXED(0x32ec4e,32,FLEN)
NAN_BOXED(0x3f999999,32,FLEN)
NAN_BOXED(0x7f20dec0,32,FLEN)
NAN_BOXED(0x32ec4e,32,FLEN)
NAN_BOXED(0x3fa49249,32,FLEN)
NAN_BOXED(0x7f20dec0,32,FLEN)
NAN_BOXED(0x32ec4e,32,FLEN)
NAN_BOXED(0x3fb33333,32,FLEN)
NAN_BOXED(0x7f20dec0,32,FLEN)
NAN_BOXED(0x32ec4e,32,FLEN)
NAN_BOXED(0x3fb6db6d,32,FLEN)
NAN_BOXED(0x7f20dec0,32,FLEN)
NAN_BOXED(0x32ec4e,32,FLEN)
NAN_BOXED(0x3fbbbbbb,32,FLEN)
NAN_BOXED(0x7f20dec0,32,FLEN)
NAN_BOXED(0x32ec4e,32,FLEN)
NAN_BOXED(0x3fc44444,32,FLEN)
NAN_BOXED(0x7f20dec0,32,FLEN)
NAN_BOXED(0x32ec4e,32,FLEN)
NAN_BOXED(0x3fcccccc,32,FLEN)
NAN_BOXED(0x7f20dec0,32,FLEN)
NAN_BOXED(0x32ec4e,32,FLEN)
NAN_BOXED(0x3fdb6db6,32,FLEN)
NAN_BOXED(0x7f20dec0,32,FLEN)
NAN_BOXED(0x32ec4e,32,FLEN)
NAN_BOXED(0x3fe66666,32,FLEN)
NAN_BOXED(0x7f20dec0,32,FLEN)
NAN_BOXED(0x32ec4e,32,FLEN)
NAN_BOXED(0x3fedb6db,32,FLEN)
NAN_BOXED(0x7f20dec0,32,FLEN)
NAN_BOXED(0x32ec4e,32,FLEN)
NAN_BOXED(0x3ffffff8,32,FLEN)
NAN_BOXED(0x7f20dec0,32,FLEN)
NAN_BOXED(0x32ec4e,32,FLEN)
NAN_BOXED(0x3ffffffc,32,FLEN)
NAN_BOXED(0x7f20dec0,32,FLEN)
NAN_BOXED(0x32ec4e,32,FLEN)
NAN_BOXED(0x3ffffffe,32,FLEN)
NAN_BOXED(0x7f217160,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x1,32,FLEN)
NAN_BOXED(0x7f217160,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x3,32,FLEN)
NAN_BOXED(0x7f217160,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x7,32,FLEN)
NAN_BOXED(0x7f217160,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x199999,32,FLEN)
NAN_BOXED(0x7f217160,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x249249,32,FLEN)
NAN_BOXED(0x7f217160,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x333333,32,FLEN)
NAN_BOXED(0x7f217160,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x36db6d,32,FLEN)
NAN_BOXED(0x7f217160,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x3bbbbb,32,FLEN)
NAN_BOXED(0x7f217160,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x444444,32,FLEN)
NAN_BOXED(0x7f217160,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x4ccccc,32,FLEN)
NAN_BOXED(0x7f217160,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x5b6db6,32,FLEN)
NAN_BOXED(0x7f217160,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x666666,32,FLEN)
NAN_BOXED(0x7f217160,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x6db6db,32,FLEN)
NAN_BOXED(0x7f217160,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x7ffff8,32,FLEN)
NAN_BOXED(0x7f217160,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x7ffffc,32,FLEN)
NAN_BOXED(0x7f217160,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x7ffffe,32,FLEN)
NAN_BOXED(0x7f217160,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x8000000,32,FLEN)
NAN_BOXED(0x7f217160,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x8000001,32,FLEN)
NAN_BOXED(0x7f217160,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x8000003,32,FLEN)
NAN_BOXED(0x7f217160,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x8000007,32,FLEN)
NAN_BOXED(0x7f217160,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x800000f,32,FLEN)
NAN_BOXED(0x7f217160,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x800001f,32,FLEN)
NAN_BOXED(0x7f217160,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x800003f,32,FLEN)
NAN_BOXED(0x7f217160,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x800007f,32,FLEN)
NAN_BOXED(0x7f217160,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x80000ff,32,FLEN)
NAN_BOXED(0x7f217160,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x80001ff,32,FLEN)
NAN_BOXED(0x7f217160,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x80003ff,32,FLEN)
NAN_BOXED(0x7f217160,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x80007ff,32,FLEN)
NAN_BOXED(0x7f217160,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x8000fff,32,FLEN)
NAN_BOXED(0x7f217160,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x8001fff,32,FLEN)
NAN_BOXED(0x7f217160,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x8003fff,32,FLEN)
NAN_BOXED(0x7f217160,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x8007fff,32,FLEN)
NAN_BOXED(0x7f217160,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x800ffff,32,FLEN)
NAN_BOXED(0x7f217160,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x801ffff,32,FLEN)
NAN_BOXED(0x7f217160,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x803ffff,32,FLEN)
NAN_BOXED(0x7f217160,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x807ffff,32,FLEN)
NAN_BOXED(0x7f217160,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x80fffff,32,FLEN)
NAN_BOXED(0x7f217160,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x81fffff,32,FLEN)
NAN_BOXED(0x7f217160,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x83fffff,32,FLEN)
NAN_BOXED(0x7f217160,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x8400000,32,FLEN)
NAN_BOXED(0x7f217160,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x8600000,32,FLEN)
NAN_BOXED(0x7f217160,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x8700000,32,FLEN)
NAN_BOXED(0x7f217160,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x8780000,32,FLEN)
NAN_BOXED(0x7f217160,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x87c0000,32,FLEN)
NAN_BOXED(0x7f217160,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x87e0000,32,FLEN)
NAN_BOXED(0x7f217160,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x87f0000,32,FLEN)
NAN_BOXED(0x7f217160,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x87f8000,32,FLEN)
NAN_BOXED(0x7f217160,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x87fc000,32,FLEN)
NAN_BOXED(0x7f217160,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x87fe000,32,FLEN)
NAN_BOXED(0x7f217160,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x87ff000,32,FLEN)
NAN_BOXED(0x7f217160,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x87ff800,32,FLEN)
NAN_BOXED(0x7f217160,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x87ffc00,32,FLEN)
NAN_BOXED(0x7f217160,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x87ffe00,32,FLEN)
NAN_BOXED(0x7f217160,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x87fff00,32,FLEN)
NAN_BOXED(0x7f217160,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x87fff80,32,FLEN)
NAN_BOXED(0x7f217160,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x87fffc0,32,FLEN)
NAN_BOXED(0x7f217160,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x87fffe0,32,FLEN)
NAN_BOXED(0x7f217160,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x87ffff0,32,FLEN)
NAN_BOXED(0x7f217160,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x87ffff8,32,FLEN)
NAN_BOXED(0x7f217160,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x87ffffc,32,FLEN)
NAN_BOXED(0x7f217160,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x87ffffe,32,FLEN)
NAN_BOXED(0x7f217160,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x87fffff,32,FLEN)
NAN_BOXED(0x7f21ba5d,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x1,32,FLEN)
NAN_BOXED(0x7f21ba5d,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x3,32,FLEN)
NAN_BOXED(0x7f21ba5d,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x7,32,FLEN)
NAN_BOXED(0x7f21ba5d,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x199999,32,FLEN)
NAN_BOXED(0x7f21ba5d,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x249249,32,FLEN)
NAN_BOXED(0x7f21ba5d,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x333333,32,FLEN)
NAN_BOXED(0x7f21ba5d,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x36db6d,32,FLEN)
NAN_BOXED(0x7f21ba5d,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x3bbbbb,32,FLEN)
NAN_BOXED(0x7f21ba5d,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x444444,32,FLEN)
NAN_BOXED(0x7f21ba5d,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x4ccccc,32,FLEN)
NAN_BOXED(0x7f21ba5d,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x5b6db6,32,FLEN)
NAN_BOXED(0x7f21ba5d,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x666666,32,FLEN)
NAN_BOXED(0x7f21ba5d,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x6db6db,32,FLEN)
NAN_BOXED(0x7f21ba5d,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x7ffff8,32,FLEN)
NAN_BOXED(0x7f21ba5d,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x7ffffc,32,FLEN)
NAN_BOXED(0x7f21ba5d,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x7ffffe,32,FLEN)
NAN_BOXED(0x7f21ba5d,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x8800000,32,FLEN)
NAN_BOXED(0x7f21ba5d,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x8800001,32,FLEN)
NAN_BOXED(0x7f21ba5d,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x8800003,32,FLEN)
NAN_BOXED(0x7f21ba5d,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x8800007,32,FLEN)
NAN_BOXED(0x7f21ba5d,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x880000f,32,FLEN)
NAN_BOXED(0x7f21ba5d,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x880001f,32,FLEN)
NAN_BOXED(0x7f21ba5d,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x880003f,32,FLEN)
NAN_BOXED(0x7f21ba5d,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x880007f,32,FLEN)
NAN_BOXED(0x7f21ba5d,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x88000ff,32,FLEN)
NAN_BOXED(0x7f21ba5d,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x88001ff,32,FLEN)
NAN_BOXED(0x7f21ba5d,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x88003ff,32,FLEN)
NAN_BOXED(0x7f21ba5d,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x88007ff,32,FLEN)
NAN_BOXED(0x7f21ba5d,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x8800fff,32,FLEN)
NAN_BOXED(0x7f21ba5d,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x8801fff,32,FLEN)
NAN_BOXED(0x7f21ba5d,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x8803fff,32,FLEN)
NAN_BOXED(0x7f21ba5d,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x8807fff,32,FLEN)
NAN_BOXED(0x7f21ba5d,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x880ffff,32,FLEN)
NAN_BOXED(0x7f21ba5d,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x881ffff,32,FLEN)
NAN_BOXED(0x7f21ba5d,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x883ffff,32,FLEN)
NAN_BOXED(0x7f21ba5d,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x887ffff,32,FLEN)
NAN_BOXED(0x7f21ba5d,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x88fffff,32,FLEN)
NAN_BOXED(0x7f21ba5d,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x89fffff,32,FLEN)
NAN_BOXED(0x7f21ba5d,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x8bfffff,32,FLEN)
NAN_BOXED(0x7f21ba5d,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x8c00000,32,FLEN)
NAN_BOXED(0x7f21ba5d,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x8e00000,32,FLEN)
NAN_BOXED(0x7f21ba5d,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x8f00000,32,FLEN)
NAN_BOXED(0x7f21ba5d,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x8f80000,32,FLEN)
NAN_BOXED(0x7f21ba5d,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x8fc0000,32,FLEN)
NAN_BOXED(0x7f21ba5d,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x8fe0000,32,FLEN)
NAN_BOXED(0x7f21ba5d,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x8ff0000,32,FLEN)
NAN_BOXED(0x7f21ba5d,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x8ff8000,32,FLEN)
NAN_BOXED(0x7f21ba5d,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x8ffc000,32,FLEN)
NAN_BOXED(0x7f21ba5d,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x8ffe000,32,FLEN)
NAN_BOXED(0x7f21ba5d,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x8fff000,32,FLEN)
NAN_BOXED(0x7f21ba5d,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x8fff800,32,FLEN)
NAN_BOXED(0x7f21ba5d,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x8fffc00,32,FLEN)
NAN_BOXED(0x7f21ba5d,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x8fffe00,32,FLEN)
NAN_BOXED(0x7f21ba5d,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x8ffff00,32,FLEN)
NAN_BOXED(0x7f21ba5d,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x8ffff80,32,FLEN)
NAN_BOXED(0x7f21ba5d,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x8ffffc0,32,FLEN)
NAN_BOXED(0x7f21ba5d,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x8ffffe0,32,FLEN)
NAN_BOXED(0x7f21ba5d,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x8fffff0,32,FLEN)
NAN_BOXED(0x7f21ba5d,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x8fffff8,32,FLEN)
NAN_BOXED(0x7f21ba5d,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x8fffffc,32,FLEN)
NAN_BOXED(0x7f21ba5d,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x8fffffe,32,FLEN)
NAN_BOXED(0x7f21ba5d,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x8ffffff,32,FLEN)
NAN_BOXED(0x7f220a0f,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x1,32,FLEN)
NAN_BOXED(0x7f220a0f,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x3,32,FLEN)
NAN_BOXED(0x7f220a0f,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x7,32,FLEN)
NAN_BOXED(0x7f220a0f,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x199999,32,FLEN)
NAN_BOXED(0x7f220a0f,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x249249,32,FLEN)
NAN_BOXED(0x7f220a0f,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x333333,32,FLEN)
NAN_BOXED(0x7f220a0f,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x36db6d,32,FLEN)
NAN_BOXED(0x7f220a0f,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x3bbbbb,32,FLEN)
NAN_BOXED(0x7f220a0f,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x444444,32,FLEN)
NAN_BOXED(0x7f220a0f,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x4ccccc,32,FLEN)
NAN_BOXED(0x7f220a0f,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x5b6db6,32,FLEN)
NAN_BOXED(0x7f220a0f,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x666666,32,FLEN)
NAN_BOXED(0x7f220a0f,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x6db6db,32,FLEN)
NAN_BOXED(0x7f220a0f,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x7ffff8,32,FLEN)
NAN_BOXED(0x7f220a0f,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x7ffffc,32,FLEN)
NAN_BOXED(0x7f220a0f,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x7ffffe,32,FLEN)
NAN_BOXED(0x7f220a0f,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xe000000,32,FLEN)
NAN_BOXED(0x7f220a0f,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xe000001,32,FLEN)
NAN_BOXED(0x7f220a0f,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xe000003,32,FLEN)
NAN_BOXED(0x7f220a0f,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xe000007,32,FLEN)
NAN_BOXED(0x7f220a0f,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xe00000f,32,FLEN)
NAN_BOXED(0x7f220a0f,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xe00001f,32,FLEN)
NAN_BOXED(0x7f220a0f,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xe00003f,32,FLEN)
NAN_BOXED(0x7f220a0f,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xe00007f,32,FLEN)
NAN_BOXED(0x7f220a0f,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xe0000ff,32,FLEN)
NAN_BOXED(0x7f220a0f,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xe0001ff,32,FLEN)
NAN_BOXED(0x7f220a0f,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xe0003ff,32,FLEN)
NAN_BOXED(0x7f220a0f,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xe0007ff,32,FLEN)
NAN_BOXED(0x7f220a0f,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xe000fff,32,FLEN)
NAN_BOXED(0x7f220a0f,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xe001fff,32,FLEN)
NAN_BOXED(0x7f220a0f,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xe003fff,32,FLEN)
NAN_BOXED(0x7f220a0f,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xe007fff,32,FLEN)
NAN_BOXED(0x7f220a0f,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xe00ffff,32,FLEN)
NAN_BOXED(0x7f220a0f,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xe01ffff,32,FLEN)
NAN_BOXED(0x7f220a0f,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xe03ffff,32,FLEN)
NAN_BOXED(0x7f220a0f,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xe07ffff,32,FLEN)
NAN_BOXED(0x7f220a0f,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xe0fffff,32,FLEN)
NAN_BOXED(0x7f220a0f,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xe1fffff,32,FLEN)
NAN_BOXED(0x7f220a0f,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xe3fffff,32,FLEN)
NAN_BOXED(0x7f220a0f,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xe400000,32,FLEN)
NAN_BOXED(0x7f220a0f,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xe600000,32,FLEN)
NAN_BOXED(0x7f220a0f,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xe700000,32,FLEN)
NAN_BOXED(0x7f220a0f,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xe780000,32,FLEN)
NAN_BOXED(0x7f220a0f,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xe7c0000,32,FLEN)
NAN_BOXED(0x7f220a0f,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xe7e0000,32,FLEN)
NAN_BOXED(0x7f220a0f,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xe7f0000,32,FLEN)
NAN_BOXED(0x7f220a0f,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xe7f8000,32,FLEN)
NAN_BOXED(0x7f220a0f,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xe7fc000,32,FLEN)
NAN_BOXED(0x7f220a0f,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xe7fe000,32,FLEN)
NAN_BOXED(0x7f220a0f,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xe7ff000,32,FLEN)
NAN_BOXED(0x7f220a0f,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xe7ff800,32,FLEN)
NAN_BOXED(0x7f220a0f,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xe7ffc00,32,FLEN)
NAN_BOXED(0x7f220a0f,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xe7ffe00,32,FLEN)
NAN_BOXED(0x7f220a0f,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xe7fff00,32,FLEN)
NAN_BOXED(0x7f220a0f,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xe7fff80,32,FLEN)
NAN_BOXED(0x7f220a0f,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xe7fffc0,32,FLEN)
NAN_BOXED(0x7f220a0f,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xe7fffe0,32,FLEN)
NAN_BOXED(0x7f220a0f,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xe7ffff0,32,FLEN)
NAN_BOXED(0x7f220a0f,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xe7ffff8,32,FLEN)
NAN_BOXED(0x7f220a0f,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xe7ffffc,32,FLEN)
NAN_BOXED(0x7f220a0f,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xe7ffffe,32,FLEN)
NAN_BOXED(0x7f220a0f,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xe7fffff,32,FLEN)
NAN_BOXED(0x7f222105,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x7f222105,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x1,32,FLEN)
NAN_BOXED(0x7f222105,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x3,32,FLEN)
NAN_BOXED(0x7f222105,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x7,32,FLEN)
NAN_BOXED(0x7f222105,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xf,32,FLEN)
NAN_BOXED(0x7f222105,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x1f,32,FLEN)
NAN_BOXED(0x7f222105,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x3f,32,FLEN)
NAN_BOXED(0x7f222105,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x7f,32,FLEN)
NAN_BOXED(0x7f222105,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xff,32,FLEN)
NAN_BOXED(0x7f222105,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x1ff,32,FLEN)
NAN_BOXED(0x7f222105,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x3ff,32,FLEN)
NAN_BOXED(0x7f222105,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x7ff,32,FLEN)
NAN_BOXED(0x7f222105,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xfff,32,FLEN)
NAN_BOXED(0x7f222105,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x1fff,32,FLEN)
NAN_BOXED(0x7f222105,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x3fff,32,FLEN)
NAN_BOXED(0x7f222105,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x7fff,32,FLEN)
NAN_BOXED(0x7f222105,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xffff,32,FLEN)
NAN_BOXED(0x7f222105,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x1ffff,32,FLEN)
NAN_BOXED(0x7f222105,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x3ffff,32,FLEN)
NAN_BOXED(0x7f222105,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x7ffff,32,FLEN)
NAN_BOXED(0x7f222105,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xfffff,32,FLEN)
NAN_BOXED(0x7f222105,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x199999,32,FLEN)
NAN_BOXED(0x7f222105,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x1fffff,32,FLEN)
NAN_BOXED(0x7f222105,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x249249,32,FLEN)
NAN_BOXED(0x7f222105,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x333333,32,FLEN)
NAN_BOXED(0x7f222105,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x36db6d,32,FLEN)
NAN_BOXED(0x7f222105,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x3bbbbb,32,FLEN)
NAN_BOXED(0x7f222105,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x3fffff,32,FLEN)
NAN_BOXED(0x7f222105,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x400000,32,FLEN)
NAN_BOXED(0x7f222105,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x444444,32,FLEN)
NAN_BOXED(0x7f222105,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x4ccccc,32,FLEN)
NAN_BOXED(0x7f222105,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x5b6db6,32,FLEN)
NAN_BOXED(0x7f222105,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x600000,32,FLEN)
NAN_BOXED(0x7f222105,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x666666,32,FLEN)
NAN_BOXED(0x7f222105,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x6db6db,32,FLEN)
NAN_BOXED(0x7f222105,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x700000,32,FLEN)
NAN_BOXED(0x7f222105,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x780000,32,FLEN)
NAN_BOXED(0x7f222105,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x7c0000,32,FLEN)
NAN_BOXED(0x7f222105,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x7e0000,32,FLEN)
NAN_BOXED(0x7f222105,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x7f0000,32,FLEN)
NAN_BOXED(0x7f222105,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x7f8000,32,FLEN)
NAN_BOXED(0x7f222105,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x7fc000,32,FLEN)
NAN_BOXED(0x7f222105,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x7fe000,32,FLEN)
NAN_BOXED(0x7f222105,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x7ff000,32,FLEN)
NAN_BOXED(0x7f222105,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x7ff800,32,FLEN)
NAN_BOXED(0x7f222105,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x7ffc00,32,FLEN)
NAN_BOXED(0x7f222105,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x7ffe00,32,FLEN)
NAN_BOXED(0x7f222105,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x7fff00,32,FLEN)
NAN_BOXED(0x7f222105,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x7fff80,32,FLEN)
NAN_BOXED(0x7f222105,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x7fffc0,32,FLEN)
NAN_BOXED(0x7f222105,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x7fffe0,32,FLEN)
NAN_BOXED(0x7f222105,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x7ffff0,32,FLEN)
NAN_BOXED(0x7f222105,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x7ffff8,32,FLEN)
NAN_BOXED(0x7f222105,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x7ffffc,32,FLEN)
NAN_BOXED(0x7f222105,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x7ffffe,32,FLEN)
NAN_BOXED(0x7f222105,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x7fffff,32,FLEN)
NAN_BOXED(0x7f22559e,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x80000001,32,FLEN)
NAN_BOXED(0x7f22559e,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x80000003,32,FLEN)
NAN_BOXED(0x7f22559e,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x80000007,32,FLEN)
NAN_BOXED(0x7f22559e,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x80199999,32,FLEN)
NAN_BOXED(0x7f22559e,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x80249249,32,FLEN)
NAN_BOXED(0x7f22559e,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x80333333,32,FLEN)
NAN_BOXED(0x7f22559e,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x8036db6d,32,FLEN)
NAN_BOXED(0x7f22559e,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x803bbbbb,32,FLEN)
NAN_BOXED(0x7f22559e,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x80444444,32,FLEN)
NAN_BOXED(0x7f22559e,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x804ccccc,32,FLEN)
NAN_BOXED(0x7f22559e,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x805b6db6,32,FLEN)
NAN_BOXED(0x7f22559e,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x80666666,32,FLEN)
NAN_BOXED(0x7f22559e,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x806db6db,32,FLEN)
NAN_BOXED(0x7f22559e,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x807ffff8,32,FLEN)
NAN_BOXED(0x7f22559e,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x807ffffc,32,FLEN)
NAN_BOXED(0x7f22559e,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x807ffffe,32,FLEN)
NAN_BOXED(0x7f22559e,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x86800000,32,FLEN)
NAN_BOXED(0x7f22559e,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x86800001,32,FLEN)
NAN_BOXED(0x7f22559e,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x86800003,32,FLEN)
NAN_BOXED(0x7f22559e,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x86800007,32,FLEN)
NAN_BOXED(0x7f22559e,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x8680000f,32,FLEN)
NAN_BOXED(0x7f22559e,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x8680001f,32,FLEN)
NAN_BOXED(0x7f22559e,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x8680003f,32,FLEN)
NAN_BOXED(0x7f22559e,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x8680007f,32,FLEN)
NAN_BOXED(0x7f22559e,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x868000ff,32,FLEN)
NAN_BOXED(0x7f22559e,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x868001ff,32,FLEN)
NAN_BOXED(0x7f22559e,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x868003ff,32,FLEN)
NAN_BOXED(0x7f22559e,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x868007ff,32,FLEN)
NAN_BOXED(0x7f22559e,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x86800fff,32,FLEN)
NAN_BOXED(0x7f22559e,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x86801fff,32,FLEN)
NAN_BOXED(0x7f22559e,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x86803fff,32,FLEN)
NAN_BOXED(0x7f22559e,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x86807fff,32,FLEN)
NAN_BOXED(0x7f22559e,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x8680ffff,32,FLEN)
NAN_BOXED(0x7f22559e,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x8681ffff,32,FLEN)
NAN_BOXED(0x7f22559e,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x8683ffff,32,FLEN)
NAN_BOXED(0x7f22559e,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x8687ffff,32,FLEN)
NAN_BOXED(0x7f22559e,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x868fffff,32,FLEN)
NAN_BOXED(0x7f22559e,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x869fffff,32,FLEN)
NAN_BOXED(0x7f22559e,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x86bfffff,32,FLEN)
NAN_BOXED(0x7f22559e,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x86c00000,32,FLEN)
NAN_BOXED(0x7f22559e,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x86e00000,32,FLEN)
NAN_BOXED(0x7f22559e,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x86f00000,32,FLEN)
NAN_BOXED(0x7f22559e,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x86f80000,32,FLEN)
NAN_BOXED(0x7f22559e,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x86fc0000,32,FLEN)
NAN_BOXED(0x7f22559e,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x86fe0000,32,FLEN)
NAN_BOXED(0x7f22559e,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x86ff0000,32,FLEN)
NAN_BOXED(0x7f22559e,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x86ff8000,32,FLEN)
NAN_BOXED(0x7f22559e,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x86ffc000,32,FLEN)
NAN_BOXED(0x7f22559e,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x86ffe000,32,FLEN)
NAN_BOXED(0x7f22559e,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x86fff000,32,FLEN)
NAN_BOXED(0x7f22559e,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x86fff800,32,FLEN)
NAN_BOXED(0x7f22559e,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x86fffc00,32,FLEN)
NAN_BOXED(0x7f22559e,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x86fffe00,32,FLEN)
NAN_BOXED(0x7f22559e,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x86ffff00,32,FLEN)
NAN_BOXED(0x7f22559e,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x86ffff80,32,FLEN)
NAN_BOXED(0x7f22559e,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x86ffffc0,32,FLEN)
NAN_BOXED(0x7f22559e,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x86ffffe0,32,FLEN)
NAN_BOXED(0x7f22559e,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x86fffff0,32,FLEN)
NAN_BOXED(0x7f22559e,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x86fffff8,32,FLEN)
NAN_BOXED(0x7f22559e,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x86fffffc,32,FLEN)
NAN_BOXED(0x7f22559e,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x86fffffe,32,FLEN)
NAN_BOXED(0x7f22559e,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x86ffffff,32,FLEN)
NAN_BOXED(0x7f228047,32,FLEN)
NAN_BOXED(0x80326976,32,FLEN)
NAN_BOXED(0xbf800001,32,FLEN)
NAN_BOXED(0x7f228047,32,FLEN)
NAN_BOXED(0x80326976,32,FLEN)
NAN_BOXED(0xbf800003,32,FLEN)
NAN_BOXED(0x7f228047,32,FLEN)
NAN_BOXED(0x80326976,32,FLEN)
NAN_BOXED(0xbf800007,32,FLEN)
NAN_BOXED(0x7f228047,32,FLEN)
NAN_BOXED(0x80326976,32,FLEN)
NAN_BOXED(0xbf999999,32,FLEN)
NAN_BOXED(0x7f228047,32,FLEN)
NAN_BOXED(0x80326976,32,FLEN)
NAN_BOXED(0xbfa49249,32,FLEN)
NAN_BOXED(0x7f228047,32,FLEN)
NAN_BOXED(0x80326976,32,FLEN)
NAN_BOXED(0xbfb33333,32,FLEN)
NAN_BOXED(0x7f228047,32,FLEN)
NAN_BOXED(0x80326976,32,FLEN)
NAN_BOXED(0xbfb6db6d,32,FLEN)
NAN_BOXED(0x7f228047,32,FLEN)
NAN_BOXED(0x80326976,32,FLEN)
NAN_BOXED(0xbfbbbbbb,32,FLEN)
NAN_BOXED(0x7f228047,32,FLEN)
NAN_BOXED(0x80326976,32,FLEN)
NAN_BOXED(0xbfc44444,32,FLEN)
NAN_BOXED(0x7f228047,32,FLEN)
NAN_BOXED(0x80326976,32,FLEN)
NAN_BOXED(0xbfcccccc,32,FLEN)
NAN_BOXED(0x7f228047,32,FLEN)
NAN_BOXED(0x80326976,32,FLEN)
NAN_BOXED(0xbfdb6db6,32,FLEN)
NAN_BOXED(0x7f228047,32,FLEN)
NAN_BOXED(0x80326976,32,FLEN)
NAN_BOXED(0xbfe66666,32,FLEN)
NAN_BOXED(0x7f228047,32,FLEN)
NAN_BOXED(0x80326976,32,FLEN)
NAN_BOXED(0xbfedb6db,32,FLEN)
NAN_BOXED(0x7f228047,32,FLEN)
NAN_BOXED(0x80326976,32,FLEN)
NAN_BOXED(0xbffffff8,32,FLEN)
NAN_BOXED(0x7f228047,32,FLEN)
NAN_BOXED(0x80326976,32,FLEN)
NAN_BOXED(0xbffffffc,32,FLEN)
NAN_BOXED(0x7f228047,32,FLEN)
NAN_BOXED(0x80326976,32,FLEN)
NAN_BOXED(0xbffffffe,32,FLEN)
NAN_BOXED(0x7f228047,32,FLEN)
NAN_BOXED(0x80326976,32,FLEN)
NAN_BOXED(0xc7000000,32,FLEN)
NAN_BOXED(0x7f228047,32,FLEN)
NAN_BOXED(0x80326976,32,FLEN)
NAN_BOXED(0xc7000001,32,FLEN)
NAN_BOXED(0x7f228047,32,FLEN)
NAN_BOXED(0x80326976,32,FLEN)
NAN_BOXED(0xc7000003,32,FLEN)
NAN_BOXED(0x7f228047,32,FLEN)
NAN_BOXED(0x80326976,32,FLEN)
NAN_BOXED(0xc7000007,32,FLEN)
NAN_BOXED(0x7f228047,32,FLEN)
NAN_BOXED(0x80326976,32,FLEN)
NAN_BOXED(0xc700000f,32,FLEN)
NAN_BOXED(0x7f228047,32,FLEN)
NAN_BOXED(0x80326976,32,FLEN)
NAN_BOXED(0xc700001f,32,FLEN)
NAN_BOXED(0x7f228047,32,FLEN)
NAN_BOXED(0x80326976,32,FLEN)
NAN_BOXED(0xc700003f,32,FLEN)
NAN_BOXED(0x7f228047,32,FLEN)
NAN_BOXED(0x80326976,32,FLEN)
NAN_BOXED(0xc700007f,32,FLEN)
NAN_BOXED(0x7f228047,32,FLEN)
NAN_BOXED(0x80326976,32,FLEN)
NAN_BOXED(0xc70000ff,32,FLEN)
NAN_BOXED(0x7f228047,32,FLEN)
NAN_BOXED(0x80326976,32,FLEN)
NAN_BOXED(0xc70001ff,32,FLEN)
NAN_BOXED(0x7f228047,32,FLEN)
NAN_BOXED(0x80326976,32,FLEN)
NAN_BOXED(0xc70003ff,32,FLEN)
NAN_BOXED(0x7f228047,32,FLEN)
NAN_BOXED(0x80326976,32,FLEN)
NAN_BOXED(0xc70007ff,32,FLEN)
NAN_BOXED(0x7f228047,32,FLEN)
NAN_BOXED(0x80326976,32,FLEN)
NAN_BOXED(0xc7000fff,32,FLEN)
NAN_BOXED(0x7f228047,32,FLEN)
NAN_BOXED(0x80326976,32,FLEN)
NAN_BOXED(0xc7001fff,32,FLEN)
NAN_BOXED(0x7f228047,32,FLEN)
NAN_BOXED(0x80326976,32,FLEN)
NAN_BOXED(0xc7003fff,32,FLEN)
NAN_BOXED(0x7f228047,32,FLEN)
NAN_BOXED(0x80326976,32,FLEN)
NAN_BOXED(0xc7007fff,32,FLEN)
NAN_BOXED(0x7f228047,32,FLEN)
NAN_BOXED(0x80326976,32,FLEN)
NAN_BOXED(0xc700ffff,32,FLEN)
NAN_BOXED(0x7f228047,32,FLEN)
NAN_BOXED(0x80326976,32,FLEN)
NAN_BOXED(0xc701ffff,32,FLEN)
NAN_BOXED(0x7f228047,32,FLEN)
NAN_BOXED(0x80326976,32,FLEN)
NAN_BOXED(0xc703ffff,32,FLEN)
NAN_BOXED(0x7f228047,32,FLEN)
NAN_BOXED(0x80326976,32,FLEN)
NAN_BOXED(0xc707ffff,32,FLEN)
NAN_BOXED(0x7f228047,32,FLEN)
NAN_BOXED(0x80326976,32,FLEN)
NAN_BOXED(0xc70fffff,32,FLEN)
NAN_BOXED(0x7f228047,32,FLEN)
NAN_BOXED(0x80326976,32,FLEN)
NAN_BOXED(0xc71fffff,32,FLEN)
NAN_BOXED(0x7f228047,32,FLEN)
NAN_BOXED(0x80326976,32,FLEN)
NAN_BOXED(0xc73fffff,32,FLEN)
NAN_BOXED(0x7f228047,32,FLEN)
NAN_BOXED(0x80326976,32,FLEN)
NAN_BOXED(0xc7400000,32,FLEN)
NAN_BOXED(0x7f228047,32,FLEN)
NAN_BOXED(0x80326976,32,FLEN)
NAN_BOXED(0xc7600000,32,FLEN)
NAN_BOXED(0x7f228047,32,FLEN)
NAN_BOXED(0x80326976,32,FLEN)
NAN_BOXED(0xc7700000,32,FLEN)
NAN_BOXED(0x7f228047,32,FLEN)
NAN_BOXED(0x80326976,32,FLEN)
NAN_BOXED(0xc7780000,32,FLEN)
NAN_BOXED(0x7f228047,32,FLEN)
NAN_BOXED(0x80326976,32,FLEN)
NAN_BOXED(0xc77c0000,32,FLEN)
NAN_BOXED(0x7f228047,32,FLEN)
NAN_BOXED(0x80326976,32,FLEN)
NAN_BOXED(0xc77e0000,32,FLEN)
NAN_BOXED(0x7f228047,32,FLEN)
NAN_BOXED(0x80326976,32,FLEN)
NAN_BOXED(0xc77f0000,32,FLEN)
NAN_BOXED(0x7f228047,32,FLEN)
NAN_BOXED(0x80326976,32,FLEN)
NAN_BOXED(0xc77f8000,32,FLEN)
NAN_BOXED(0x7f228047,32,FLEN)
NAN_BOXED(0x80326976,32,FLEN)
NAN_BOXED(0xc77fc000,32,FLEN)
NAN_BOXED(0x7f228047,32,FLEN)
NAN_BOXED(0x80326976,32,FLEN)
NAN_BOXED(0xc77fe000,32,FLEN)
NAN_BOXED(0x7f228047,32,FLEN)
NAN_BOXED(0x80326976,32,FLEN)
NAN_BOXED(0xc77ff000,32,FLEN)
NAN_BOXED(0x7f228047,32,FLEN)
NAN_BOXED(0x80326976,32,FLEN)
NAN_BOXED(0xc77ff800,32,FLEN)
NAN_BOXED(0x7f228047,32,FLEN)
NAN_BOXED(0x80326976,32,FLEN)
NAN_BOXED(0xc77ffc00,32,FLEN)
NAN_BOXED(0x7f228047,32,FLEN)
NAN_BOXED(0x80326976,32,FLEN)
NAN_BOXED(0xc77ffe00,32,FLEN)
NAN_BOXED(0x7f228047,32,FLEN)
NAN_BOXED(0x80326976,32,FLEN)
NAN_BOXED(0xc77fff00,32,FLEN)
NAN_BOXED(0x7f228047,32,FLEN)
NAN_BOXED(0x80326976,32,FLEN)
NAN_BOXED(0xc77fff80,32,FLEN)
NAN_BOXED(0x7f228047,32,FLEN)
NAN_BOXED(0x80326976,32,FLEN)
NAN_BOXED(0xc77fffc0,32,FLEN)
NAN_BOXED(0x7f228047,32,FLEN)
NAN_BOXED(0x80326976,32,FLEN)
NAN_BOXED(0xc77fffe0,32,FLEN)
NAN_BOXED(0x7f228047,32,FLEN)
NAN_BOXED(0x80326976,32,FLEN)
NAN_BOXED(0xc77ffff0,32,FLEN)
NAN_BOXED(0x7f228047,32,FLEN)
NAN_BOXED(0x80326976,32,FLEN)
NAN_BOXED(0xc77ffff8,32,FLEN)
NAN_BOXED(0x7f228047,32,FLEN)
NAN_BOXED(0x80326976,32,FLEN)
NAN_BOXED(0xc77ffffc,32,FLEN)
NAN_BOXED(0x7f228047,32,FLEN)
NAN_BOXED(0x80326976,32,FLEN)
NAN_BOXED(0xc77ffffe,32,FLEN)
NAN_BOXED(0x7f228047,32,FLEN)
NAN_BOXED(0x80326976,32,FLEN)
NAN_BOXED(0xc77fffff,32,FLEN)
NAN_BOXED(0x7f231790,32,FLEN)
NAN_BOXED(0x80323ab3,32,FLEN)
NAN_BOXED(0xbf800001,32,FLEN)
NAN_BOXED(0x7f231790,32,FLEN)
NAN_BOXED(0x80323ab3,32,FLEN)
NAN_BOXED(0xbf800003,32,FLEN)
NAN_BOXED(0x7f231790,32,FLEN)
NAN_BOXED(0x80323ab3,32,FLEN)
NAN_BOXED(0xbf800007,32,FLEN)
NAN_BOXED(0x7f231790,32,FLEN)
NAN_BOXED(0x80323ab3,32,FLEN)
NAN_BOXED(0xbf999999,32,FLEN)
NAN_BOXED(0x7f231790,32,FLEN)
NAN_BOXED(0x80323ab3,32,FLEN)
NAN_BOXED(0xbfa49249,32,FLEN)
NAN_BOXED(0x7f231790,32,FLEN)
NAN_BOXED(0x80323ab3,32,FLEN)
NAN_BOXED(0xbfb33333,32,FLEN)
NAN_BOXED(0x7f231790,32,FLEN)
NAN_BOXED(0x80323ab3,32,FLEN)
NAN_BOXED(0xbfb6db6d,32,FLEN)
NAN_BOXED(0x7f231790,32,FLEN)
NAN_BOXED(0x80323ab3,32,FLEN)
NAN_BOXED(0xbfbbbbbb,32,FLEN)
NAN_BOXED(0x7f231790,32,FLEN)
NAN_BOXED(0x80323ab3,32,FLEN)
NAN_BOXED(0xbfc44444,32,FLEN)
NAN_BOXED(0x7f231790,32,FLEN)
NAN_BOXED(0x80323ab3,32,FLEN)
NAN_BOXED(0xbfcccccc,32,FLEN)
NAN_BOXED(0x7f231790,32,FLEN)
NAN_BOXED(0x80323ab3,32,FLEN)
NAN_BOXED(0xbfdb6db6,32,FLEN)
NAN_BOXED(0x7f231790,32,FLEN)
NAN_BOXED(0x80323ab3,32,FLEN)
NAN_BOXED(0xbfe66666,32,FLEN)
NAN_BOXED(0x7f231790,32,FLEN)
NAN_BOXED(0x80323ab3,32,FLEN)
NAN_BOXED(0xbfedb6db,32,FLEN)
NAN_BOXED(0x7f231790,32,FLEN)
NAN_BOXED(0x80323ab3,32,FLEN)
NAN_BOXED(0xbffffff8,32,FLEN)
NAN_BOXED(0x7f231790,32,FLEN)
NAN_BOXED(0x80323ab3,32,FLEN)
NAN_BOXED(0xbffffffc,32,FLEN)
NAN_BOXED(0x7f231790,32,FLEN)
NAN_BOXED(0x80323ab3,32,FLEN)
NAN_BOXED(0xbffffffe,32,FLEN)
NAN_BOXED(0x7f231790,32,FLEN)
NAN_BOXED(0x80323ab3,32,FLEN)
NAN_BOXED(0xc6800000,32,FLEN)
NAN_BOXED(0x7f231790,32,FLEN)
NAN_BOXED(0x80323ab3,32,FLEN)
NAN_BOXED(0xc6800001,32,FLEN)
NAN_BOXED(0x7f231790,32,FLEN)
NAN_BOXED(0x80323ab3,32,FLEN)
NAN_BOXED(0xc6800003,32,FLEN)
NAN_BOXED(0x7f231790,32,FLEN)
NAN_BOXED(0x80323ab3,32,FLEN)
NAN_BOXED(0xc6800007,32,FLEN)
NAN_BOXED(0x7f231790,32,FLEN)
NAN_BOXED(0x80323ab3,32,FLEN)
NAN_BOXED(0xc680000f,32,FLEN)
NAN_BOXED(0x7f231790,32,FLEN)
NAN_BOXED(0x80323ab3,32,FLEN)
NAN_BOXED(0xc680001f,32,FLEN)
NAN_BOXED(0x7f231790,32,FLEN)
NAN_BOXED(0x80323ab3,32,FLEN)
NAN_BOXED(0xc680003f,32,FLEN)
NAN_BOXED(0x7f231790,32,FLEN)
NAN_BOXED(0x80323ab3,32,FLEN)
NAN_BOXED(0xc680007f,32,FLEN)
NAN_BOXED(0x7f231790,32,FLEN)
NAN_BOXED(0x80323ab3,32,FLEN)
NAN_BOXED(0xc68000ff,32,FLEN)
NAN_BOXED(0x7f231790,32,FLEN)
NAN_BOXED(0x80323ab3,32,FLEN)
NAN_BOXED(0xc68001ff,32,FLEN)
NAN_BOXED(0x7f231790,32,FLEN)
NAN_BOXED(0x80323ab3,32,FLEN)
NAN_BOXED(0xc68003ff,32,FLEN)
NAN_BOXED(0x7f231790,32,FLEN)
NAN_BOXED(0x80323ab3,32,FLEN)
NAN_BOXED(0xc68007ff,32,FLEN)
NAN_BOXED(0x7f231790,32,FLEN)
NAN_BOXED(0x80323ab3,32,FLEN)
NAN_BOXED(0xc6800fff,32,FLEN)
NAN_BOXED(0x7f231790,32,FLEN)
NAN_BOXED(0x80323ab3,32,FLEN)
NAN_BOXED(0xc6801fff,32,FLEN)
NAN_BOXED(0x7f231790,32,FLEN)
NAN_BOXED(0x80323ab3,32,FLEN)
NAN_BOXED(0xc6803fff,32,FLEN)
NAN_BOXED(0x7f231790,32,FLEN)
NAN_BOXED(0x80323ab3,32,FLEN)
NAN_BOXED(0xc6807fff,32,FLEN)
NAN_BOXED(0x7f231790,32,FLEN)
NAN_BOXED(0x80323ab3,32,FLEN)
NAN_BOXED(0xc680ffff,32,FLEN)
NAN_BOXED(0x7f231790,32,FLEN)
NAN_BOXED(0x80323ab3,32,FLEN)
NAN_BOXED(0xc681ffff,32,FLEN)
NAN_BOXED(0x7f231790,32,FLEN)
NAN_BOXED(0x80323ab3,32,FLEN)
NAN_BOXED(0xc683ffff,32,FLEN)
NAN_BOXED(0x7f231790,32,FLEN)
NAN_BOXED(0x80323ab3,32,FLEN)
NAN_BOXED(0xc687ffff,32,FLEN)
NAN_BOXED(0x7f231790,32,FLEN)
NAN_BOXED(0x80323ab3,32,FLEN)
NAN_BOXED(0xc68fffff,32,FLEN)
NAN_BOXED(0x7f231790,32,FLEN)
NAN_BOXED(0x80323ab3,32,FLEN)
NAN_BOXED(0xc69fffff,32,FLEN)
NAN_BOXED(0x7f231790,32,FLEN)
NAN_BOXED(0x80323ab3,32,FLEN)
NAN_BOXED(0xc6bfffff,32,FLEN)
NAN_BOXED(0x7f231790,32,FLEN)
NAN_BOXED(0x80323ab3,32,FLEN)
NAN_BOXED(0xc6c00000,32,FLEN)
NAN_BOXED(0x7f231790,32,FLEN)
NAN_BOXED(0x80323ab3,32,FLEN)
NAN_BOXED(0xc6e00000,32,FLEN)
NAN_BOXED(0x7f231790,32,FLEN)
NAN_BOXED(0x80323ab3,32,FLEN)
NAN_BOXED(0xc6f00000,32,FLEN)
NAN_BOXED(0x7f231790,32,FLEN)
NAN_BOXED(0x80323ab3,32,FLEN)
NAN_BOXED(0xc6f80000,32,FLEN)
NAN_BOXED(0x7f231790,32,FLEN)
NAN_BOXED(0x80323ab3,32,FLEN)
NAN_BOXED(0xc6fc0000,32,FLEN)
NAN_BOXED(0x7f231790,32,FLEN)
NAN_BOXED(0x80323ab3,32,FLEN)
NAN_BOXED(0xc6fe0000,32,FLEN)
NAN_BOXED(0x7f231790,32,FLEN)
NAN_BOXED(0x80323ab3,32,FLEN)
NAN_BOXED(0xc6ff0000,32,FLEN)
NAN_BOXED(0x7f231790,32,FLEN)
NAN_BOXED(0x80323ab3,32,FLEN)
NAN_BOXED(0xc6ff8000,32,FLEN)
NAN_BOXED(0x7f231790,32,FLEN)
NAN_BOXED(0x80323ab3,32,FLEN)
NAN_BOXED(0xc6ffc000,32,FLEN)
NAN_BOXED(0x7f231790,32,FLEN)
NAN_BOXED(0x80323ab3,32,FLEN)
NAN_BOXED(0xc6ffe000,32,FLEN)
NAN_BOXED(0x7f231790,32,FLEN)
NAN_BOXED(0x80323ab3,32,FLEN)
NAN_BOXED(0xc6fff000,32,FLEN)
NAN_BOXED(0x7f231790,32,FLEN)
NAN_BOXED(0x80323ab3,32,FLEN)
NAN_BOXED(0xc6fff800,32,FLEN)
NAN_BOXED(0x7f231790,32,FLEN)
NAN_BOXED(0x80323ab3,32,FLEN)
NAN_BOXED(0xc6fffc00,32,FLEN)
NAN_BOXED(0x7f231790,32,FLEN)
NAN_BOXED(0x80323ab3,32,FLEN)
NAN_BOXED(0xc6fffe00,32,FLEN)
NAN_BOXED(0x7f231790,32,FLEN)
NAN_BOXED(0x80323ab3,32,FLEN)
NAN_BOXED(0xc6ffff00,32,FLEN)
NAN_BOXED(0x7f231790,32,FLEN)
NAN_BOXED(0x80323ab3,32,FLEN)
NAN_BOXED(0xc6ffff80,32,FLEN)
NAN_BOXED(0x7f231790,32,FLEN)
NAN_BOXED(0x80323ab3,32,FLEN)
NAN_BOXED(0xc6ffffc0,32,FLEN)
NAN_BOXED(0x7f231790,32,FLEN)
NAN_BOXED(0x80323ab3,32,FLEN)
NAN_BOXED(0xc6ffffe0,32,FLEN)
NAN_BOXED(0x7f231790,32,FLEN)
NAN_BOXED(0x80323ab3,32,FLEN)
NAN_BOXED(0xc6fffff0,32,FLEN)
NAN_BOXED(0x7f231790,32,FLEN)
NAN_BOXED(0x80323ab3,32,FLEN)
NAN_BOXED(0xc6fffff8,32,FLEN)
NAN_BOXED(0x7f231790,32,FLEN)
NAN_BOXED(0x80323ab3,32,FLEN)
NAN_BOXED(0xc6fffffc,32,FLEN)
NAN_BOXED(0x7f231790,32,FLEN)
NAN_BOXED(0x80323ab3,32,FLEN)
NAN_BOXED(0xc6fffffe,32,FLEN)
NAN_BOXED(0x7f231790,32,FLEN)
NAN_BOXED(0x80323ab3,32,FLEN)
NAN_BOXED(0xc6ffffff,32,FLEN)
NAN_BOXED(0x7f234a7c,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x1,32,FLEN)
NAN_BOXED(0x7f234a7c,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x3,32,FLEN)
NAN_BOXED(0x7f234a7c,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x7,32,FLEN)
NAN_BOXED(0x7f234a7c,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x199999,32,FLEN)
NAN_BOXED(0x7f234a7c,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x249249,32,FLEN)
NAN_BOXED(0x7f234a7c,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x333333,32,FLEN)
NAN_BOXED(0x7f234a7c,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x36db6d,32,FLEN)
NAN_BOXED(0x7f234a7c,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x3bbbbb,32,FLEN)
NAN_BOXED(0x7f234a7c,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x444444,32,FLEN)
NAN_BOXED(0x7f234a7c,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x4ccccc,32,FLEN)
NAN_BOXED(0x7f234a7c,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x5b6db6,32,FLEN)
NAN_BOXED(0x7f234a7c,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x666666,32,FLEN)
NAN_BOXED(0x7f234a7c,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x6db6db,32,FLEN)
NAN_BOXED(0x7f234a7c,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x7ffff8,32,FLEN)
NAN_BOXED(0x7f234a7c,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x7ffffc,32,FLEN)
NAN_BOXED(0x7f234a7c,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x7ffffe,32,FLEN)
NAN_BOXED(0x7f234a7c,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xa000000,32,FLEN)
NAN_BOXED(0x7f234a7c,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xa000001,32,FLEN)
NAN_BOXED(0x7f234a7c,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xa000003,32,FLEN)
NAN_BOXED(0x7f234a7c,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xa000007,32,FLEN)
NAN_BOXED(0x7f234a7c,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xa00000f,32,FLEN)
NAN_BOXED(0x7f234a7c,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xa00001f,32,FLEN)
NAN_BOXED(0x7f234a7c,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xa00003f,32,FLEN)
NAN_BOXED(0x7f234a7c,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xa00007f,32,FLEN)
NAN_BOXED(0x7f234a7c,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xa0000ff,32,FLEN)
NAN_BOXED(0x7f234a7c,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xa0001ff,32,FLEN)
NAN_BOXED(0x7f234a7c,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xa0003ff,32,FLEN)
NAN_BOXED(0x7f234a7c,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xa0007ff,32,FLEN)
NAN_BOXED(0x7f234a7c,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xa000fff,32,FLEN)
NAN_BOXED(0x7f234a7c,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xa001fff,32,FLEN)
NAN_BOXED(0x7f234a7c,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xa003fff,32,FLEN)
NAN_BOXED(0x7f234a7c,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xa007fff,32,FLEN)
NAN_BOXED(0x7f234a7c,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xa00ffff,32,FLEN)
NAN_BOXED(0x7f234a7c,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xa01ffff,32,FLEN)
NAN_BOXED(0x7f234a7c,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xa03ffff,32,FLEN)
NAN_BOXED(0x7f234a7c,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xa07ffff,32,FLEN)
NAN_BOXED(0x7f234a7c,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xa0fffff,32,FLEN)
NAN_BOXED(0x7f234a7c,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xa1fffff,32,FLEN)
NAN_BOXED(0x7f234a7c,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xa3fffff,32,FLEN)
NAN_BOXED(0x7f234a7c,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xa400000,32,FLEN)
NAN_BOXED(0x7f234a7c,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xa600000,32,FLEN)
NAN_BOXED(0x7f234a7c,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xa700000,32,FLEN)
NAN_BOXED(0x7f234a7c,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xa780000,32,FLEN)
NAN_BOXED(0x7f234a7c,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xa7c0000,32,FLEN)
NAN_BOXED(0x7f234a7c,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xa7e0000,32,FLEN)
NAN_BOXED(0x7f234a7c,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xa7f0000,32,FLEN)
NAN_BOXED(0x7f234a7c,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xa7f8000,32,FLEN)
NAN_BOXED(0x7f234a7c,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xa7fc000,32,FLEN)
NAN_BOXED(0x7f234a7c,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xa7fe000,32,FLEN)
NAN_BOXED(0x7f234a7c,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xa7ff000,32,FLEN)
NAN_BOXED(0x7f234a7c,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xa7ff800,32,FLEN)
NAN_BOXED(0x7f234a7c,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xa7ffc00,32,FLEN)
NAN_BOXED(0x7f234a7c,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xa7ffe00,32,FLEN)
NAN_BOXED(0x7f234a7c,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xa7fff00,32,FLEN)
NAN_BOXED(0x7f234a7c,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xa7fff80,32,FLEN)
NAN_BOXED(0x7f234a7c,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xa7fffc0,32,FLEN)
NAN_BOXED(0x7f234a7c,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xa7fffe0,32,FLEN)
NAN_BOXED(0x7f234a7c,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xa7ffff0,32,FLEN)
NAN_BOXED(0x7f234a7c,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xa7ffff8,32,FLEN)
NAN_BOXED(0x7f234a7c,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xa7ffffc,32,FLEN)
NAN_BOXED(0x7f234a7c,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xa7ffffe,32,FLEN)
NAN_BOXED(0x7f234a7c,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xa7fffff,32,FLEN)
NAN_BOXED(0x7f237022,32,FLEN)
NAN_BOXED(0x80321f7b,32,FLEN)
NAN_BOXED(0xbf800001,32,FLEN)
NAN_BOXED(0x7f237022,32,FLEN)
NAN_BOXED(0x80321f7b,32,FLEN)
NAN_BOXED(0xbf800003,32,FLEN)
NAN_BOXED(0x7f237022,32,FLEN)
NAN_BOXED(0x80321f7b,32,FLEN)
NAN_BOXED(0xbf800007,32,FLEN)
NAN_BOXED(0x7f237022,32,FLEN)
NAN_BOXED(0x80321f7b,32,FLEN)
NAN_BOXED(0xbf999999,32,FLEN)
NAN_BOXED(0x7f237022,32,FLEN)
NAN_BOXED(0x80321f7b,32,FLEN)
NAN_BOXED(0xbfa49249,32,FLEN)
NAN_BOXED(0x7f237022,32,FLEN)
NAN_BOXED(0x80321f7b,32,FLEN)
NAN_BOXED(0xbfb33333,32,FLEN)
NAN_BOXED(0x7f237022,32,FLEN)
NAN_BOXED(0x80321f7b,32,FLEN)
NAN_BOXED(0xbfb6db6d,32,FLEN)
NAN_BOXED(0x7f237022,32,FLEN)
NAN_BOXED(0x80321f7b,32,FLEN)
NAN_BOXED(0xbfbbbbbb,32,FLEN)
NAN_BOXED(0x7f237022,32,FLEN)
NAN_BOXED(0x80321f7b,32,FLEN)
NAN_BOXED(0xbfc44444,32,FLEN)
NAN_BOXED(0x7f237022,32,FLEN)
NAN_BOXED(0x80321f7b,32,FLEN)
NAN_BOXED(0xbfcccccc,32,FLEN)
NAN_BOXED(0x7f237022,32,FLEN)
NAN_BOXED(0x80321f7b,32,FLEN)
NAN_BOXED(0xbfdb6db6,32,FLEN)
NAN_BOXED(0x7f237022,32,FLEN)
NAN_BOXED(0x80321f7b,32,FLEN)
NAN_BOXED(0xbfe66666,32,FLEN)
NAN_BOXED(0x7f237022,32,FLEN)
NAN_BOXED(0x80321f7b,32,FLEN)
NAN_BOXED(0xbfedb6db,32,FLEN)
NAN_BOXED(0x7f237022,32,FLEN)
NAN_BOXED(0x80321f7b,32,FLEN)
NAN_BOXED(0xbffffff8,32,FLEN)
NAN_BOXED(0x7f237022,32,FLEN)
NAN_BOXED(0x80321f7b,32,FLEN)
NAN_BOXED(0xbffffffc,32,FLEN)
NAN_BOXED(0x7f237022,32,FLEN)
NAN_BOXED(0x80321f7b,32,FLEN)
NAN_BOXED(0xbffffffe,32,FLEN)
NAN_BOXED(0x7f237022,32,FLEN)
NAN_BOXED(0x80321f7b,32,FLEN)
NAN_BOXED(0xc3000000,32,FLEN)
NAN_BOXED(0x7f237022,32,FLEN)
NAN_BOXED(0x80321f7b,32,FLEN)
NAN_BOXED(0xc3000001,32,FLEN)
NAN_BOXED(0x7f237022,32,FLEN)
NAN_BOXED(0x80321f7b,32,FLEN)
NAN_BOXED(0xc3000003,32,FLEN)
NAN_BOXED(0x7f237022,32,FLEN)
NAN_BOXED(0x80321f7b,32,FLEN)
NAN_BOXED(0xc3000007,32,FLEN)
NAN_BOXED(0x7f237022,32,FLEN)
NAN_BOXED(0x80321f7b,32,FLEN)
NAN_BOXED(0xc300000f,32,FLEN)
NAN_BOXED(0x7f237022,32,FLEN)
NAN_BOXED(0x80321f7b,32,FLEN)
NAN_BOXED(0xc300001f,32,FLEN)
NAN_BOXED(0x7f237022,32,FLEN)
NAN_BOXED(0x80321f7b,32,FLEN)
NAN_BOXED(0xc300003f,32,FLEN)
NAN_BOXED(0x7f237022,32,FLEN)
NAN_BOXED(0x80321f7b,32,FLEN)
NAN_BOXED(0xc300007f,32,FLEN)
NAN_BOXED(0x7f237022,32,FLEN)
NAN_BOXED(0x80321f7b,32,FLEN)
NAN_BOXED(0xc30000ff,32,FLEN)
NAN_BOXED(0x7f237022,32,FLEN)
NAN_BOXED(0x80321f7b,32,FLEN)
NAN_BOXED(0xc30001ff,32,FLEN)
NAN_BOXED(0x7f237022,32,FLEN)
NAN_BOXED(0x80321f7b,32,FLEN)
NAN_BOXED(0xc30003ff,32,FLEN)
NAN_BOXED(0x7f237022,32,FLEN)
NAN_BOXED(0x80321f7b,32,FLEN)
NAN_BOXED(0xc30007ff,32,FLEN)
NAN_BOXED(0x7f237022,32,FLEN)
NAN_BOXED(0x80321f7b,32,FLEN)
NAN_BOXED(0xc3000fff,32,FLEN)
NAN_BOXED(0x7f237022,32,FLEN)
NAN_BOXED(0x80321f7b,32,FLEN)
NAN_BOXED(0xc3001fff,32,FLEN)
NAN_BOXED(0x7f237022,32,FLEN)
NAN_BOXED(0x80321f7b,32,FLEN)
NAN_BOXED(0xc3003fff,32,FLEN)
NAN_BOXED(0x7f237022,32,FLEN)
NAN_BOXED(0x80321f7b,32,FLEN)
NAN_BOXED(0xc3007fff,32,FLEN)
NAN_BOXED(0x7f237022,32,FLEN)
NAN_BOXED(0x80321f7b,32,FLEN)
NAN_BOXED(0xc300ffff,32,FLEN)
NAN_BOXED(0x7f237022,32,FLEN)
NAN_BOXED(0x80321f7b,32,FLEN)
NAN_BOXED(0xc301ffff,32,FLEN)
NAN_BOXED(0x7f237022,32,FLEN)
NAN_BOXED(0x80321f7b,32,FLEN)
NAN_BOXED(0xc303ffff,32,FLEN)
NAN_BOXED(0x7f237022,32,FLEN)
NAN_BOXED(0x80321f7b,32,FLEN)
NAN_BOXED(0xc307ffff,32,FLEN)
NAN_BOXED(0x7f237022,32,FLEN)
NAN_BOXED(0x80321f7b,32,FLEN)
NAN_BOXED(0xc30fffff,32,FLEN)
NAN_BOXED(0x7f237022,32,FLEN)
NAN_BOXED(0x80321f7b,32,FLEN)
NAN_BOXED(0xc31fffff,32,FLEN)
NAN_BOXED(0x7f237022,32,FLEN)
NAN_BOXED(0x80321f7b,32,FLEN)
NAN_BOXED(0xc33fffff,32,FLEN)
NAN_BOXED(0x7f237022,32,FLEN)
NAN_BOXED(0x80321f7b,32,FLEN)
NAN_BOXED(0xc3400000,32,FLEN)
NAN_BOXED(0x7f237022,32,FLEN)
NAN_BOXED(0x80321f7b,32,FLEN)
NAN_BOXED(0xc3600000,32,FLEN)
NAN_BOXED(0x7f237022,32,FLEN)
NAN_BOXED(0x80321f7b,32,FLEN)
NAN_BOXED(0xc3700000,32,FLEN)
NAN_BOXED(0x7f237022,32,FLEN)
NAN_BOXED(0x80321f7b,32,FLEN)
NAN_BOXED(0xc3780000,32,FLEN)
NAN_BOXED(0x7f237022,32,FLEN)
NAN_BOXED(0x80321f7b,32,FLEN)
NAN_BOXED(0xc37c0000,32,FLEN)
NAN_BOXED(0x7f237022,32,FLEN)
NAN_BOXED(0x80321f7b,32,FLEN)
NAN_BOXED(0xc37e0000,32,FLEN)
NAN_BOXED(0x7f237022,32,FLEN)
NAN_BOXED(0x80321f7b,32,FLEN)
NAN_BOXED(0xc37f0000,32,FLEN)
NAN_BOXED(0x7f237022,32,FLEN)
NAN_BOXED(0x80321f7b,32,FLEN)
NAN_BOXED(0xc37f8000,32,FLEN)
NAN_BOXED(0x7f237022,32,FLEN)
NAN_BOXED(0x80321f7b,32,FLEN)
NAN_BOXED(0xc37fc000,32,FLEN)
NAN_BOXED(0x7f237022,32,FLEN)
NAN_BOXED(0x80321f7b,32,FLEN)
NAN_BOXED(0xc37fe000,32,FLEN)
NAN_BOXED(0x7f237022,32,FLEN)
NAN_BOXED(0x80321f7b,32,FLEN)
NAN_BOXED(0xc37ff000,32,FLEN)
NAN_BOXED(0x7f237022,32,FLEN)
NAN_BOXED(0x80321f7b,32,FLEN)
NAN_BOXED(0xc37ff800,32,FLEN)
NAN_BOXED(0x7f237022,32,FLEN)
NAN_BOXED(0x80321f7b,32,FLEN)
NAN_BOXED(0xc37ffc00,32,FLEN)
NAN_BOXED(0x7f237022,32,FLEN)
NAN_BOXED(0x80321f7b,32,FLEN)
NAN_BOXED(0xc37ffe00,32,FLEN)
NAN_BOXED(0x7f237022,32,FLEN)
NAN_BOXED(0x80321f7b,32,FLEN)
NAN_BOXED(0xc37fff00,32,FLEN)
NAN_BOXED(0x7f237022,32,FLEN)
NAN_BOXED(0x80321f7b,32,FLEN)
NAN_BOXED(0xc37fff80,32,FLEN)
NAN_BOXED(0x7f237022,32,FLEN)
NAN_BOXED(0x80321f7b,32,FLEN)
NAN_BOXED(0xc37fffc0,32,FLEN)
NAN_BOXED(0x7f237022,32,FLEN)
NAN_BOXED(0x80321f7b,32,FLEN)
NAN_BOXED(0xc37fffe0,32,FLEN)
NAN_BOXED(0x7f237022,32,FLEN)
NAN_BOXED(0x80321f7b,32,FLEN)
NAN_BOXED(0xc37ffff0,32,FLEN)
NAN_BOXED(0x7f237022,32,FLEN)
NAN_BOXED(0x80321f7b,32,FLEN)
NAN_BOXED(0xc37ffff8,32,FLEN)
NAN_BOXED(0x7f237022,32,FLEN)
NAN_BOXED(0x80321f7b,32,FLEN)
NAN_BOXED(0xc37ffffc,32,FLEN)
NAN_BOXED(0x7f237022,32,FLEN)
NAN_BOXED(0x80321f7b,32,FLEN)
NAN_BOXED(0xc37ffffe,32,FLEN)
NAN_BOXED(0x7f237022,32,FLEN)
NAN_BOXED(0x80321f7b,32,FLEN)
NAN_BOXED(0xc37fffff,32,FLEN)
NAN_BOXED(0x7f23bfb5,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x80000001,32,FLEN)
NAN_BOXED(0x7f23bfb5,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x80000003,32,FLEN)
NAN_BOXED(0x7f23bfb5,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x80000007,32,FLEN)
NAN_BOXED(0x7f23bfb5,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x80199999,32,FLEN)
NAN_BOXED(0x7f23bfb5,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x80249249,32,FLEN)
NAN_BOXED(0x7f23bfb5,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x80333333,32,FLEN)
NAN_BOXED(0x7f23bfb5,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x8036db6d,32,FLEN)
NAN_BOXED(0x7f23bfb5,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x803bbbbb,32,FLEN)
NAN_BOXED(0x7f23bfb5,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x80444444,32,FLEN)
NAN_BOXED(0x7f23bfb5,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x804ccccc,32,FLEN)
NAN_BOXED(0x7f23bfb5,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x805b6db6,32,FLEN)
NAN_BOXED(0x7f23bfb5,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x80666666,32,FLEN)
NAN_BOXED(0x7f23bfb5,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x806db6db,32,FLEN)
NAN_BOXED(0x7f23bfb5,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x807ffff8,32,FLEN)
NAN_BOXED(0x7f23bfb5,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x807ffffc,32,FLEN)
NAN_BOXED(0x7f23bfb5,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x807ffffe,32,FLEN)
NAN_BOXED(0x7f23bfb5,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x87000000,32,FLEN)
NAN_BOXED(0x7f23bfb5,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x87000001,32,FLEN)
NAN_BOXED(0x7f23bfb5,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x87000003,32,FLEN)
NAN_BOXED(0x7f23bfb5,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x87000007,32,FLEN)
NAN_BOXED(0x7f23bfb5,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x8700000f,32,FLEN)
NAN_BOXED(0x7f23bfb5,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x8700001f,32,FLEN)
NAN_BOXED(0x7f23bfb5,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x8700003f,32,FLEN)
NAN_BOXED(0x7f23bfb5,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x8700007f,32,FLEN)
NAN_BOXED(0x7f23bfb5,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x870000ff,32,FLEN)
NAN_BOXED(0x7f23bfb5,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x870001ff,32,FLEN)
NAN_BOXED(0x7f23bfb5,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x870003ff,32,FLEN)
NAN_BOXED(0x7f23bfb5,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x870007ff,32,FLEN)
NAN_BOXED(0x7f23bfb5,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x87000fff,32,FLEN)
NAN_BOXED(0x7f23bfb5,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x87001fff,32,FLEN)
NAN_BOXED(0x7f23bfb5,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x87003fff,32,FLEN)
NAN_BOXED(0x7f23bfb5,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x87007fff,32,FLEN)
NAN_BOXED(0x7f23bfb5,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x8700ffff,32,FLEN)
NAN_BOXED(0x7f23bfb5,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x8701ffff,32,FLEN)
NAN_BOXED(0x7f23bfb5,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x8703ffff,32,FLEN)
NAN_BOXED(0x7f23bfb5,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x8707ffff,32,FLEN)
NAN_BOXED(0x7f23bfb5,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x870fffff,32,FLEN)
NAN_BOXED(0x7f23bfb5,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x871fffff,32,FLEN)
NAN_BOXED(0x7f23bfb5,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x873fffff,32,FLEN)
NAN_BOXED(0x7f23bfb5,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x87400000,32,FLEN)
NAN_BOXED(0x7f23bfb5,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x87600000,32,FLEN)
NAN_BOXED(0x7f23bfb5,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x87700000,32,FLEN)
NAN_BOXED(0x7f23bfb5,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x87780000,32,FLEN)
NAN_BOXED(0x7f23bfb5,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x877c0000,32,FLEN)
NAN_BOXED(0x7f23bfb5,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x877e0000,32,FLEN)
NAN_BOXED(0x7f23bfb5,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x877f0000,32,FLEN)
NAN_BOXED(0x7f23bfb5,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x877f8000,32,FLEN)
NAN_BOXED(0x7f23bfb5,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x877fc000,32,FLEN)
NAN_BOXED(0x7f23bfb5,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x877fe000,32,FLEN)
NAN_BOXED(0x7f23bfb5,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x877ff000,32,FLEN)
NAN_BOXED(0x7f23bfb5,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x877ff800,32,FLEN)
NAN_BOXED(0x7f23bfb5,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x877ffc00,32,FLEN)
NAN_BOXED(0x7f23bfb5,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x877ffe00,32,FLEN)
NAN_BOXED(0x7f23bfb5,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x877fff00,32,FLEN)
NAN_BOXED(0x7f23bfb5,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x877fff80,32,FLEN)
NAN_BOXED(0x7f23bfb5,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x877fffc0,32,FLEN)
NAN_BOXED(0x7f23bfb5,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x877fffe0,32,FLEN)
NAN_BOXED(0x7f23bfb5,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x877ffff0,32,FLEN)
NAN_BOXED(0x7f23bfb5,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x877ffff8,32,FLEN)
NAN_BOXED(0x7f23bfb5,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x877ffffc,32,FLEN)
NAN_BOXED(0x7f23bfb5,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x877ffffe,32,FLEN)
NAN_BOXED(0x7f23bfb5,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x877fffff,32,FLEN)
NAN_BOXED(0x7f23ecb7,32,FLEN)
NAN_BOXED(0x8031f963,32,FLEN)
NAN_BOXED(0xa1800000,32,FLEN)
NAN_BOXED(0x7f23ecb7,32,FLEN)
NAN_BOXED(0x8031f963,32,FLEN)
NAN_BOXED(0xa1800001,32,FLEN)
NAN_BOXED(0x7f23ecb7,32,FLEN)
NAN_BOXED(0x8031f963,32,FLEN)
NAN_BOXED(0xa1800003,32,FLEN)
NAN_BOXED(0x7f23ecb7,32,FLEN)
NAN_BOXED(0x8031f963,32,FLEN)
NAN_BOXED(0xa1800007,32,FLEN)
NAN_BOXED(0x7f23ecb7,32,FLEN)
NAN_BOXED(0x8031f963,32,FLEN)
NAN_BOXED(0xa180000f,32,FLEN)
NAN_BOXED(0x7f23ecb7,32,FLEN)
NAN_BOXED(0x8031f963,32,FLEN)
NAN_BOXED(0xa180001f,32,FLEN)
NAN_BOXED(0x7f23ecb7,32,FLEN)
NAN_BOXED(0x8031f963,32,FLEN)
NAN_BOXED(0xa180003f,32,FLEN)
NAN_BOXED(0x7f23ecb7,32,FLEN)
NAN_BOXED(0x8031f963,32,FLEN)
NAN_BOXED(0xa180007f,32,FLEN)
NAN_BOXED(0x7f23ecb7,32,FLEN)
NAN_BOXED(0x8031f963,32,FLEN)
NAN_BOXED(0xa18000ff,32,FLEN)
NAN_BOXED(0x7f23ecb7,32,FLEN)
NAN_BOXED(0x8031f963,32,FLEN)
NAN_BOXED(0xa18001ff,32,FLEN)
NAN_BOXED(0x7f23ecb7,32,FLEN)
NAN_BOXED(0x8031f963,32,FLEN)
NAN_BOXED(0xa18003ff,32,FLEN)
NAN_BOXED(0x7f23ecb7,32,FLEN)
NAN_BOXED(0x8031f963,32,FLEN)
NAN_BOXED(0xa18007ff,32,FLEN)
NAN_BOXED(0x7f23ecb7,32,FLEN)
NAN_BOXED(0x8031f963,32,FLEN)
NAN_BOXED(0xa1800fff,32,FLEN)
NAN_BOXED(0x7f23ecb7,32,FLEN)
NAN_BOXED(0x8031f963,32,FLEN)
NAN_BOXED(0xa1801fff,32,FLEN)
NAN_BOXED(0x7f23ecb7,32,FLEN)
NAN_BOXED(0x8031f963,32,FLEN)
NAN_BOXED(0xa1803fff,32,FLEN)
NAN_BOXED(0x7f23ecb7,32,FLEN)
NAN_BOXED(0x8031f963,32,FLEN)
NAN_BOXED(0xa1807fff,32,FLEN)
NAN_BOXED(0x7f23ecb7,32,FLEN)
NAN_BOXED(0x8031f963,32,FLEN)
NAN_BOXED(0xa180ffff,32,FLEN)
NAN_BOXED(0x7f23ecb7,32,FLEN)
NAN_BOXED(0x8031f963,32,FLEN)
NAN_BOXED(0xa181ffff,32,FLEN)
NAN_BOXED(0x7f23ecb7,32,FLEN)
NAN_BOXED(0x8031f963,32,FLEN)
NAN_BOXED(0xa183ffff,32,FLEN)
NAN_BOXED(0x7f23ecb7,32,FLEN)
NAN_BOXED(0x8031f963,32,FLEN)
NAN_BOXED(0xa187ffff,32,FLEN)
NAN_BOXED(0x7f23ecb7,32,FLEN)
NAN_BOXED(0x8031f963,32,FLEN)
NAN_BOXED(0xa18fffff,32,FLEN)
NAN_BOXED(0x7f23ecb7,32,FLEN)
NAN_BOXED(0x8031f963,32,FLEN)
NAN_BOXED(0xa19fffff,32,FLEN)
NAN_BOXED(0x7f23ecb7,32,FLEN)
NAN_BOXED(0x8031f963,32,FLEN)
NAN_BOXED(0xa1bfffff,32,FLEN)
NAN_BOXED(0x7f23ecb7,32,FLEN)
NAN_BOXED(0x8031f963,32,FLEN)
NAN_BOXED(0xa1c00000,32,FLEN)
NAN_BOXED(0x7f23ecb7,32,FLEN)
NAN_BOXED(0x8031f963,32,FLEN)
NAN_BOXED(0xa1e00000,32,FLEN)
NAN_BOXED(0x7f23ecb7,32,FLEN)
NAN_BOXED(0x8031f963,32,FLEN)
NAN_BOXED(0xa1f00000,32,FLEN)
NAN_BOXED(0x7f23ecb7,32,FLEN)
NAN_BOXED(0x8031f963,32,FLEN)
NAN_BOXED(0xa1f80000,32,FLEN)
NAN_BOXED(0x7f23ecb7,32,FLEN)
NAN_BOXED(0x8031f963,32,FLEN)
NAN_BOXED(0xa1fc0000,32,FLEN)
NAN_BOXED(0x7f23ecb7,32,FLEN)
NAN_BOXED(0x8031f963,32,FLEN)
NAN_BOXED(0xa1fe0000,32,FLEN)
NAN_BOXED(0x7f23ecb7,32,FLEN)
NAN_BOXED(0x8031f963,32,FLEN)
NAN_BOXED(0xa1ff0000,32,FLEN)
NAN_BOXED(0x7f23ecb7,32,FLEN)
NAN_BOXED(0x8031f963,32,FLEN)
NAN_BOXED(0xa1ff8000,32,FLEN)
NAN_BOXED(0x7f23ecb7,32,FLEN)
NAN_BOXED(0x8031f963,32,FLEN)
NAN_BOXED(0xa1ffc000,32,FLEN)
NAN_BOXED(0x7f23ecb7,32,FLEN)
NAN_BOXED(0x8031f963,32,FLEN)
NAN_BOXED(0xa1ffe000,32,FLEN)
NAN_BOXED(0x7f23ecb7,32,FLEN)
NAN_BOXED(0x8031f963,32,FLEN)
NAN_BOXED(0xa1fff000,32,FLEN)
NAN_BOXED(0x7f23ecb7,32,FLEN)
NAN_BOXED(0x8031f963,32,FLEN)
NAN_BOXED(0xa1fff800,32,FLEN)
NAN_BOXED(0x7f23ecb7,32,FLEN)
NAN_BOXED(0x8031f963,32,FLEN)
NAN_BOXED(0xa1fffc00,32,FLEN)
NAN_BOXED(0x7f23ecb7,32,FLEN)
NAN_BOXED(0x8031f963,32,FLEN)
NAN_BOXED(0xa1fffe00,32,FLEN)
NAN_BOXED(0x7f23ecb7,32,FLEN)
NAN_BOXED(0x8031f963,32,FLEN)
NAN_BOXED(0xa1ffff00,32,FLEN)
NAN_BOXED(0x7f23ecb7,32,FLEN)
NAN_BOXED(0x8031f963,32,FLEN)
NAN_BOXED(0xa1ffff80,32,FLEN)
NAN_BOXED(0x7f23ecb7,32,FLEN)
NAN_BOXED(0x8031f963,32,FLEN)
NAN_BOXED(0xa1ffffc0,32,FLEN)
NAN_BOXED(0x7f23ecb7,32,FLEN)
NAN_BOXED(0x8031f963,32,FLEN)
NAN_BOXED(0xa1ffffe0,32,FLEN)
NAN_BOXED(0x7f23ecb7,32,FLEN)
NAN_BOXED(0x8031f963,32,FLEN)
NAN_BOXED(0xa1fffff0,32,FLEN)
NAN_BOXED(0x7f23ecb7,32,FLEN)
NAN_BOXED(0x8031f963,32,FLEN)
NAN_BOXED(0xa1fffff8,32,FLEN)
NAN_BOXED(0x7f23ecb7,32,FLEN)
NAN_BOXED(0x8031f963,32,FLEN)
NAN_BOXED(0xa1fffffc,32,FLEN)
NAN_BOXED(0x7f23ecb7,32,FLEN)
NAN_BOXED(0x8031f963,32,FLEN)
NAN_BOXED(0xa1fffffe,32,FLEN)
NAN_BOXED(0x7f23ecb7,32,FLEN)
NAN_BOXED(0x8031f963,32,FLEN)
NAN_BOXED(0xa1ffffff,32,FLEN)
NAN_BOXED(0x7f23ecb7,32,FLEN)
NAN_BOXED(0x8031f963,32,FLEN)
NAN_BOXED(0xbf800001,32,FLEN)
NAN_BOXED(0x7f23ecb7,32,FLEN)
NAN_BOXED(0x8031f963,32,FLEN)
NAN_BOXED(0xbf800003,32,FLEN)
NAN_BOXED(0x7f23ecb7,32,FLEN)
NAN_BOXED(0x8031f963,32,FLEN)
NAN_BOXED(0xbf800007,32,FLEN)
NAN_BOXED(0x7f23ecb7,32,FLEN)
NAN_BOXED(0x8031f963,32,FLEN)
NAN_BOXED(0xbf999999,32,FLEN)
NAN_BOXED(0x7f23ecb7,32,FLEN)
NAN_BOXED(0x8031f963,32,FLEN)
NAN_BOXED(0xbfa49249,32,FLEN)
NAN_BOXED(0x7f23ecb7,32,FLEN)
NAN_BOXED(0x8031f963,32,FLEN)
NAN_BOXED(0xbfb33333,32,FLEN)
NAN_BOXED(0x7f23ecb7,32,FLEN)
NAN_BOXED(0x8031f963,32,FLEN)
NAN_BOXED(0xbfb6db6d,32,FLEN)
NAN_BOXED(0x7f23ecb7,32,FLEN)
NAN_BOXED(0x8031f963,32,FLEN)
NAN_BOXED(0xbfbbbbbb,32,FLEN)
NAN_BOXED(0x7f23ecb7,32,FLEN)
NAN_BOXED(0x8031f963,32,FLEN)
NAN_BOXED(0xbfc44444,32,FLEN)
NAN_BOXED(0x7f23ecb7,32,FLEN)
NAN_BOXED(0x8031f963,32,FLEN)
NAN_BOXED(0xbfcccccc,32,FLEN)
NAN_BOXED(0x7f23ecb7,32,FLEN)
NAN_BOXED(0x8031f963,32,FLEN)
NAN_BOXED(0xbfdb6db6,32,FLEN)
NAN_BOXED(0x7f23ecb7,32,FLEN)
NAN_BOXED(0x8031f963,32,FLEN)
NAN_BOXED(0xbfe66666,32,FLEN)
NAN_BOXED(0x7f23ecb7,32,FLEN)
NAN_BOXED(0x8031f963,32,FLEN)
NAN_BOXED(0xbfedb6db,32,FLEN)
NAN_BOXED(0x7f23ecb7,32,FLEN)
NAN_BOXED(0x8031f963,32,FLEN)
NAN_BOXED(0xbffffff8,32,FLEN)
NAN_BOXED(0x7f23ecb7,32,FLEN)
NAN_BOXED(0x8031f963,32,FLEN)
NAN_BOXED(0xbffffffc,32,FLEN)
NAN_BOXED(0x7f23ecb7,32,FLEN)
NAN_BOXED(0x8031f963,32,FLEN)
NAN_BOXED(0xbffffffe,32,FLEN)
NAN_BOXED(0x7f2438d0,32,FLEN)
NAN_BOXED(0x31e23b,32,FLEN)
NAN_BOXED(0x31000000,32,FLEN)
NAN_BOXED(0x7f2438d0,32,FLEN)
NAN_BOXED(0x31e23b,32,FLEN)
NAN_BOXED(0x31000001,32,FLEN)
NAN_BOXED(0x7f2438d0,32,FLEN)
NAN_BOXED(0x31e23b,32,FLEN)
NAN_BOXED(0x31000003,32,FLEN)
NAN_BOXED(0x7f2438d0,32,FLEN)
NAN_BOXED(0x31e23b,32,FLEN)
NAN_BOXED(0x31000007,32,FLEN)
NAN_BOXED(0x7f2438d0,32,FLEN)
NAN_BOXED(0x31e23b,32,FLEN)
NAN_BOXED(0x3100000f,32,FLEN)
NAN_BOXED(0x7f2438d0,32,FLEN)
NAN_BOXED(0x31e23b,32,FLEN)
NAN_BOXED(0x3100001f,32,FLEN)
NAN_BOXED(0x7f2438d0,32,FLEN)
NAN_BOXED(0x31e23b,32,FLEN)
NAN_BOXED(0x3100003f,32,FLEN)
NAN_BOXED(0x7f2438d0,32,FLEN)
NAN_BOXED(0x31e23b,32,FLEN)
NAN_BOXED(0x3100007f,32,FLEN)
NAN_BOXED(0x7f2438d0,32,FLEN)
NAN_BOXED(0x31e23b,32,FLEN)
NAN_BOXED(0x310000ff,32,FLEN)
NAN_BOXED(0x7f2438d0,32,FLEN)
NAN_BOXED(0x31e23b,32,FLEN)
NAN_BOXED(0x310001ff,32,FLEN)
NAN_BOXED(0x7f2438d0,32,FLEN)
NAN_BOXED(0x31e23b,32,FLEN)
NAN_BOXED(0x310003ff,32,FLEN)
NAN_BOXED(0x7f2438d0,32,FLEN)
NAN_BOXED(0x31e23b,32,FLEN)
NAN_BOXED(0x310007ff,32,FLEN)
NAN_BOXED(0x7f2438d0,32,FLEN)
NAN_BOXED(0x31e23b,32,FLEN)
NAN_BOXED(0x31000fff,32,FLEN)
NAN_BOXED(0x7f2438d0,32,FLEN)
NAN_BOXED(0x31e23b,32,FLEN)
NAN_BOXED(0x31001fff,32,FLEN)
NAN_BOXED(0x7f2438d0,32,FLEN)
NAN_BOXED(0x31e23b,32,FLEN)
NAN_BOXED(0x31003fff,32,FLEN)
NAN_BOXED(0x7f2438d0,32,FLEN)
NAN_BOXED(0x31e23b,32,FLEN)
NAN_BOXED(0x31007fff,32,FLEN)
NAN_BOXED(0x7f2438d0,32,FLEN)
NAN_BOXED(0x31e23b,32,FLEN)
NAN_BOXED(0x3100ffff,32,FLEN)
NAN_BOXED(0x7f2438d0,32,FLEN)
NAN_BOXED(0x31e23b,32,FLEN)
NAN_BOXED(0x3101ffff,32,FLEN)
NAN_BOXED(0x7f2438d0,32,FLEN)
NAN_BOXED(0x31e23b,32,FLEN)
NAN_BOXED(0x3103ffff,32,FLEN)
NAN_BOXED(0x7f2438d0,32,FLEN)
NAN_BOXED(0x31e23b,32,FLEN)
NAN_BOXED(0x3107ffff,32,FLEN)
NAN_BOXED(0x7f2438d0,32,FLEN)
NAN_BOXED(0x31e23b,32,FLEN)
NAN_BOXED(0x310fffff,32,FLEN)
NAN_BOXED(0x7f2438d0,32,FLEN)
NAN_BOXED(0x31e23b,32,FLEN)
NAN_BOXED(0x311fffff,32,FLEN)
NAN_BOXED(0x7f2438d0,32,FLEN)
NAN_BOXED(0x31e23b,32,FLEN)
NAN_BOXED(0x313fffff,32,FLEN)
NAN_BOXED(0x7f2438d0,32,FLEN)
NAN_BOXED(0x31e23b,32,FLEN)
NAN_BOXED(0x31400000,32,FLEN)
NAN_BOXED(0x7f2438d0,32,FLEN)
NAN_BOXED(0x31e23b,32,FLEN)
NAN_BOXED(0x31600000,32,FLEN)
NAN_BOXED(0x7f2438d0,32,FLEN)
NAN_BOXED(0x31e23b,32,FLEN)
NAN_BOXED(0x31700000,32,FLEN)
NAN_BOXED(0x7f2438d0,32,FLEN)
NAN_BOXED(0x31e23b,32,FLEN)
NAN_BOXED(0x31780000,32,FLEN)
NAN_BOXED(0x7f2438d0,32,FLEN)
NAN_BOXED(0x31e23b,32,FLEN)
NAN_BOXED(0x317c0000,32,FLEN)
NAN_BOXED(0x7f2438d0,32,FLEN)
NAN_BOXED(0x31e23b,32,FLEN)
NAN_BOXED(0x317e0000,32,FLEN)
NAN_BOXED(0x7f2438d0,32,FLEN)
NAN_BOXED(0x31e23b,32,FLEN)
NAN_BOXED(0x317f0000,32,FLEN)
NAN_BOXED(0x7f2438d0,32,FLEN)
NAN_BOXED(0x31e23b,32,FLEN)
NAN_BOXED(0x317f8000,32,FLEN)
NAN_BOXED(0x7f2438d0,32,FLEN)
NAN_BOXED(0x31e23b,32,FLEN)
NAN_BOXED(0x317fc000,32,FLEN)
NAN_BOXED(0x7f2438d0,32,FLEN)
NAN_BOXED(0x31e23b,32,FLEN)
NAN_BOXED(0x317fe000,32,FLEN)
NAN_BOXED(0x7f2438d0,32,FLEN)
NAN_BOXED(0x31e23b,32,FLEN)
NAN_BOXED(0x317ff000,32,FLEN)
NAN_BOXED(0x7f2438d0,32,FLEN)
NAN_BOXED(0x31e23b,32,FLEN)
NAN_BOXED(0x317ff800,32,FLEN)
NAN_BOXED(0x7f2438d0,32,FLEN)
NAN_BOXED(0x31e23b,32,FLEN)
NAN_BOXED(0x317ffc00,32,FLEN)
NAN_BOXED(0x7f2438d0,32,FLEN)
NAN_BOXED(0x31e23b,32,FLEN)
NAN_BOXED(0x317ffe00,32,FLEN)
NAN_BOXED(0x7f2438d0,32,FLEN)
NAN_BOXED(0x31e23b,32,FLEN)
NAN_BOXED(0x317fff00,32,FLEN)
NAN_BOXED(0x7f2438d0,32,FLEN)
NAN_BOXED(0x31e23b,32,FLEN)
NAN_BOXED(0x317fff80,32,FLEN)
NAN_BOXED(0x7f2438d0,32,FLEN)
NAN_BOXED(0x31e23b,32,FLEN)
NAN_BOXED(0x317fffc0,32,FLEN)
NAN_BOXED(0x7f2438d0,32,FLEN)
NAN_BOXED(0x31e23b,32,FLEN)
NAN_BOXED(0x317fffe0,32,FLEN)
NAN_BOXED(0x7f2438d0,32,FLEN)
NAN_BOXED(0x31e23b,32,FLEN)
NAN_BOXED(0x317ffff0,32,FLEN)
NAN_BOXED(0x7f2438d0,32,FLEN)
NAN_BOXED(0x31e23b,32,FLEN)
NAN_BOXED(0x317ffff8,32,FLEN)
NAN_BOXED(0x7f2438d0,32,FLEN)
NAN_BOXED(0x31e23b,32,FLEN)
NAN_BOXED(0x317ffffc,32,FLEN)
NAN_BOXED(0x7f2438d0,32,FLEN)
NAN_BOXED(0x31e23b,32,FLEN)
NAN_BOXED(0x317ffffe,32,FLEN)
NAN_BOXED(0x7f2438d0,32,FLEN)
NAN_BOXED(0x31e23b,32,FLEN)
NAN_BOXED(0x317fffff,32,FLEN)
RVTEST_DATA_END

RVMODEL_DATA_BEGIN
rvtest_sig_begin:
sig_begin_canary:
CANARY;


signature_x1_0:
    .fill 0*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_1:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_2:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_3:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_4:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_5:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_6:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef

#ifdef rvtest_mtrap_routine

tsig_begin_canary:
CANARY;
tsig_begin_canary:
CANARY;
mtrap_sigptr:
    .fill 64*(XLEN/32),4,0xdeadbeef
tsig_end_canary:
CANARY;
tsig_end_canary:
CANARY;

#endif

#ifdef rvtest_gpr_save

gpr_save:
    .fill 32*XLEN/32,4,0xdeadbeef

#endif

sig_end_canary:
CANARY;
rvtest_sig_end:
RVMODEL_DATA_END
