
// -----------
// This file was generated by riscv_ctg (https://github.com/riscv-software-src/riscv-ctg)
// version   : 0.7.1
// timestamp : Fri Jun 17 14:18:09 2022 GMT
// usage     : riscv_ctg \
//                  -- cgf //                  --cgf /scratch/pawan/work/normalised/RV32F/fnmadd.s.cgf \
 \
//                  -- xlen 32  \
//                  --randomize \
// -----------
//
// -----------
// Copyright (c) 2020. RISC-V International. All rights reserved.
// SPDX-License-Identifier: BSD-3-Clause
// -----------
//
// This assembly file tests the fnmadd.s instruction of the RISC-V RV32F_Zicsr,RV32FD_Zicsr,RV64F_Zicsr,RV64FD_Zicsr extension for the fnmadd_b15 covergroup.
// 
#include "model_test.h"
#include "arch_test.h"
RVTEST_ISA("RV32IF_Zicsr,RV32IFD_Zicsr,RV64IF_Zicsr,RV64IFD_Zicsr,RV32EF_Zicsr,RV32EFD_Zicsr,RV64EF_Zicsr,RV64EFD_Zicsr")

.section .text.init
.globl rvtest_entry_point
rvtest_entry_point:
RVMODEL_BOOT
RVTEST_CODE_BEGIN

#ifdef TEST_CASE_1

RVTEST_CASE(0,"//check ISA:=regex(.*I.*F.*);def TEST_CASE_1=True;",fnmadd_b15)
RVTEST_CASE(1,"//check ISA:=regex(.*E.*F.*);def TEST_CASE_1=True;",fnmadd_b15)
RVTEST_FP_ENABLE()
RVTEST_VALBASEUPD(x3,test_dataset_0)
RVTEST_SIGBASE(x1,signature_x1_1)

inst_3840:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x355b9c and fs2 == 0 and fe2 == 0x82 and fm2 == 0x34ae72 and fs3 == 0 and fe3 == 0x06 and fm3 == 0x003fff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7db55b9c; op2val:0x4134ae72;
op3val:0x3003fff; valaddr_reg:x3; val_offset:11520*0 + 3*-1*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 11520*0 + 3*0*FLEN/8, x4, x1, x2)

inst_3841:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x355b9c and fs2 == 0 and fe2 == 0x82 and fm2 == 0x34ae72 and fs3 == 0 and fe3 == 0x06 and fm3 == 0x007fff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7db55b9c; op2val:0x4134ae72;
op3val:0x3007fff; valaddr_reg:x3; val_offset:11523*0 + 3*0*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 11523*0 + 3*1*FLEN/8, x4, x1, x2)

inst_3842:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x355b9c and fs2 == 0 and fe2 == 0x82 and fm2 == 0x34ae72 and fs3 == 0 and fe3 == 0x06 and fm3 == 0x00ffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7db55b9c; op2val:0x4134ae72;
op3val:0x300ffff; valaddr_reg:x3; val_offset:11526*0 + 3*1*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 11526*0 + 3*2*FLEN/8, x4, x1, x2)

inst_3843:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x355b9c and fs2 == 0 and fe2 == 0x82 and fm2 == 0x34ae72 and fs3 == 0 and fe3 == 0x06 and fm3 == 0x01ffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7db55b9c; op2val:0x4134ae72;
op3val:0x301ffff; valaddr_reg:x3; val_offset:11529*0 + 3*2*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 11529*0 + 3*3*FLEN/8, x4, x1, x2)

inst_3844:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x355b9c and fs2 == 0 and fe2 == 0x82 and fm2 == 0x34ae72 and fs3 == 0 and fe3 == 0x06 and fm3 == 0x03ffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7db55b9c; op2val:0x4134ae72;
op3val:0x303ffff; valaddr_reg:x3; val_offset:11532*0 + 3*3*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 11532*0 + 3*4*FLEN/8, x4, x1, x2)

inst_3845:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x355b9c and fs2 == 0 and fe2 == 0x82 and fm2 == 0x34ae72 and fs3 == 0 and fe3 == 0x06 and fm3 == 0x07ffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7db55b9c; op2val:0x4134ae72;
op3val:0x307ffff; valaddr_reg:x3; val_offset:11535*0 + 3*4*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 11535*0 + 3*5*FLEN/8, x4, x1, x2)

inst_3846:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x355b9c and fs2 == 0 and fe2 == 0x82 and fm2 == 0x34ae72 and fs3 == 0 and fe3 == 0x06 and fm3 == 0x0fffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7db55b9c; op2val:0x4134ae72;
op3val:0x30fffff; valaddr_reg:x3; val_offset:11538*0 + 3*5*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 11538*0 + 3*6*FLEN/8, x4, x1, x2)

inst_3847:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x355b9c and fs2 == 0 and fe2 == 0x82 and fm2 == 0x34ae72 and fs3 == 0 and fe3 == 0x06 and fm3 == 0x1fffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7db55b9c; op2val:0x4134ae72;
op3val:0x31fffff; valaddr_reg:x3; val_offset:11541*0 + 3*6*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 11541*0 + 3*7*FLEN/8, x4, x1, x2)

inst_3848:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x355b9c and fs2 == 0 and fe2 == 0x82 and fm2 == 0x34ae72 and fs3 == 0 and fe3 == 0x06 and fm3 == 0x3fffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7db55b9c; op2val:0x4134ae72;
op3val:0x33fffff; valaddr_reg:x3; val_offset:11544*0 + 3*7*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 11544*0 + 3*8*FLEN/8, x4, x1, x2)

inst_3849:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x355b9c and fs2 == 0 and fe2 == 0x82 and fm2 == 0x34ae72 and fs3 == 0 and fe3 == 0x06 and fm3 == 0x400000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7db55b9c; op2val:0x4134ae72;
op3val:0x3400000; valaddr_reg:x3; val_offset:11547*0 + 3*8*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 11547*0 + 3*9*FLEN/8, x4, x1, x2)

inst_3850:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x355b9c and fs2 == 0 and fe2 == 0x82 and fm2 == 0x34ae72 and fs3 == 0 and fe3 == 0x06 and fm3 == 0x600000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7db55b9c; op2val:0x4134ae72;
op3val:0x3600000; valaddr_reg:x3; val_offset:11550*0 + 3*9*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 11550*0 + 3*10*FLEN/8, x4, x1, x2)

inst_3851:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x355b9c and fs2 == 0 and fe2 == 0x82 and fm2 == 0x34ae72 and fs3 == 0 and fe3 == 0x06 and fm3 == 0x700000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7db55b9c; op2val:0x4134ae72;
op3val:0x3700000; valaddr_reg:x3; val_offset:11553*0 + 3*10*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 11553*0 + 3*11*FLEN/8, x4, x1, x2)

inst_3852:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x355b9c and fs2 == 0 and fe2 == 0x82 and fm2 == 0x34ae72 and fs3 == 0 and fe3 == 0x06 and fm3 == 0x780000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7db55b9c; op2val:0x4134ae72;
op3val:0x3780000; valaddr_reg:x3; val_offset:11556*0 + 3*11*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 11556*0 + 3*12*FLEN/8, x4, x1, x2)

inst_3853:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x355b9c and fs2 == 0 and fe2 == 0x82 and fm2 == 0x34ae72 and fs3 == 0 and fe3 == 0x06 and fm3 == 0x7c0000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7db55b9c; op2val:0x4134ae72;
op3val:0x37c0000; valaddr_reg:x3; val_offset:11559*0 + 3*12*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 11559*0 + 3*13*FLEN/8, x4, x1, x2)

inst_3854:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x355b9c and fs2 == 0 and fe2 == 0x82 and fm2 == 0x34ae72 and fs3 == 0 and fe3 == 0x06 and fm3 == 0x7e0000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7db55b9c; op2val:0x4134ae72;
op3val:0x37e0000; valaddr_reg:x3; val_offset:11562*0 + 3*13*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 11562*0 + 3*14*FLEN/8, x4, x1, x2)

inst_3855:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x355b9c and fs2 == 0 and fe2 == 0x82 and fm2 == 0x34ae72 and fs3 == 0 and fe3 == 0x06 and fm3 == 0x7f0000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7db55b9c; op2val:0x4134ae72;
op3val:0x37f0000; valaddr_reg:x3; val_offset:11565*0 + 3*14*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 11565*0 + 3*15*FLEN/8, x4, x1, x2)

inst_3856:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x355b9c and fs2 == 0 and fe2 == 0x82 and fm2 == 0x34ae72 and fs3 == 0 and fe3 == 0x06 and fm3 == 0x7f8000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7db55b9c; op2val:0x4134ae72;
op3val:0x37f8000; valaddr_reg:x3; val_offset:11568*0 + 3*15*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 11568*0 + 3*16*FLEN/8, x4, x1, x2)

inst_3857:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x355b9c and fs2 == 0 and fe2 == 0x82 and fm2 == 0x34ae72 and fs3 == 0 and fe3 == 0x06 and fm3 == 0x7fc000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7db55b9c; op2val:0x4134ae72;
op3val:0x37fc000; valaddr_reg:x3; val_offset:11571*0 + 3*16*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 11571*0 + 3*17*FLEN/8, x4, x1, x2)

inst_3858:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x355b9c and fs2 == 0 and fe2 == 0x82 and fm2 == 0x34ae72 and fs3 == 0 and fe3 == 0x06 and fm3 == 0x7fe000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7db55b9c; op2val:0x4134ae72;
op3val:0x37fe000; valaddr_reg:x3; val_offset:11574*0 + 3*17*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 11574*0 + 3*18*FLEN/8, x4, x1, x2)

inst_3859:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x355b9c and fs2 == 0 and fe2 == 0x82 and fm2 == 0x34ae72 and fs3 == 0 and fe3 == 0x06 and fm3 == 0x7ff000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7db55b9c; op2val:0x4134ae72;
op3val:0x37ff000; valaddr_reg:x3; val_offset:11577*0 + 3*18*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 11577*0 + 3*19*FLEN/8, x4, x1, x2)

inst_3860:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x355b9c and fs2 == 0 and fe2 == 0x82 and fm2 == 0x34ae72 and fs3 == 0 and fe3 == 0x06 and fm3 == 0x7ff800 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7db55b9c; op2val:0x4134ae72;
op3val:0x37ff800; valaddr_reg:x3; val_offset:11580*0 + 3*19*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 11580*0 + 3*20*FLEN/8, x4, x1, x2)

inst_3861:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x355b9c and fs2 == 0 and fe2 == 0x82 and fm2 == 0x34ae72 and fs3 == 0 and fe3 == 0x06 and fm3 == 0x7ffc00 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7db55b9c; op2val:0x4134ae72;
op3val:0x37ffc00; valaddr_reg:x3; val_offset:11583*0 + 3*20*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 11583*0 + 3*21*FLEN/8, x4, x1, x2)

inst_3862:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x355b9c and fs2 == 0 and fe2 == 0x82 and fm2 == 0x34ae72 and fs3 == 0 and fe3 == 0x06 and fm3 == 0x7ffe00 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7db55b9c; op2val:0x4134ae72;
op3val:0x37ffe00; valaddr_reg:x3; val_offset:11586*0 + 3*21*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 11586*0 + 3*22*FLEN/8, x4, x1, x2)

inst_3863:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x355b9c and fs2 == 0 and fe2 == 0x82 and fm2 == 0x34ae72 and fs3 == 0 and fe3 == 0x06 and fm3 == 0x7fff00 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7db55b9c; op2val:0x4134ae72;
op3val:0x37fff00; valaddr_reg:x3; val_offset:11589*0 + 3*22*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 11589*0 + 3*23*FLEN/8, x4, x1, x2)

inst_3864:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x355b9c and fs2 == 0 and fe2 == 0x82 and fm2 == 0x34ae72 and fs3 == 0 and fe3 == 0x06 and fm3 == 0x7fff80 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7db55b9c; op2val:0x4134ae72;
op3val:0x37fff80; valaddr_reg:x3; val_offset:11592*0 + 3*23*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 11592*0 + 3*24*FLEN/8, x4, x1, x2)

inst_3865:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x355b9c and fs2 == 0 and fe2 == 0x82 and fm2 == 0x34ae72 and fs3 == 0 and fe3 == 0x06 and fm3 == 0x7fffc0 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7db55b9c; op2val:0x4134ae72;
op3val:0x37fffc0; valaddr_reg:x3; val_offset:11595*0 + 3*24*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 11595*0 + 3*25*FLEN/8, x4, x1, x2)

inst_3866:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x355b9c and fs2 == 0 and fe2 == 0x82 and fm2 == 0x34ae72 and fs3 == 0 and fe3 == 0x06 and fm3 == 0x7fffe0 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7db55b9c; op2val:0x4134ae72;
op3val:0x37fffe0; valaddr_reg:x3; val_offset:11598*0 + 3*25*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 11598*0 + 3*26*FLEN/8, x4, x1, x2)

inst_3867:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x355b9c and fs2 == 0 and fe2 == 0x82 and fm2 == 0x34ae72 and fs3 == 0 and fe3 == 0x06 and fm3 == 0x7ffff0 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7db55b9c; op2val:0x4134ae72;
op3val:0x37ffff0; valaddr_reg:x3; val_offset:11601*0 + 3*26*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 11601*0 + 3*27*FLEN/8, x4, x1, x2)

inst_3868:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x355b9c and fs2 == 0 and fe2 == 0x82 and fm2 == 0x34ae72 and fs3 == 0 and fe3 == 0x06 and fm3 == 0x7ffff8 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7db55b9c; op2val:0x4134ae72;
op3val:0x37ffff8; valaddr_reg:x3; val_offset:11604*0 + 3*27*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 11604*0 + 3*28*FLEN/8, x4, x1, x2)

inst_3869:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x355b9c and fs2 == 0 and fe2 == 0x82 and fm2 == 0x34ae72 and fs3 == 0 and fe3 == 0x06 and fm3 == 0x7ffffc and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7db55b9c; op2val:0x4134ae72;
op3val:0x37ffffc; valaddr_reg:x3; val_offset:11607*0 + 3*28*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 11607*0 + 3*29*FLEN/8, x4, x1, x2)

inst_3870:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x355b9c and fs2 == 0 and fe2 == 0x82 and fm2 == 0x34ae72 and fs3 == 0 and fe3 == 0x06 and fm3 == 0x7ffffe and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7db55b9c; op2val:0x4134ae72;
op3val:0x37ffffe; valaddr_reg:x3; val_offset:11610*0 + 3*29*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 11610*0 + 3*30*FLEN/8, x4, x1, x2)

inst_3871:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x355b9c and fs2 == 0 and fe2 == 0x82 and fm2 == 0x34ae72 and fs3 == 0 and fe3 == 0x06 and fm3 == 0x7fffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7db55b9c; op2val:0x4134ae72;
op3val:0x37fffff; valaddr_reg:x3; val_offset:11613*0 + 3*30*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 11613*0 + 3*31*FLEN/8, x4, x1, x2)

inst_3872:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x355b9c and fs2 == 0 and fe2 == 0x82 and fm2 == 0x34ae72 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x000001 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7db55b9c; op2val:0x4134ae72;
op3val:0x7f000001; valaddr_reg:x3; val_offset:11616*0 + 3*31*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 11616*0 + 3*32*FLEN/8, x4, x1, x2)

inst_3873:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x355b9c and fs2 == 0 and fe2 == 0x82 and fm2 == 0x34ae72 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x000003 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7db55b9c; op2val:0x4134ae72;
op3val:0x7f000003; valaddr_reg:x3; val_offset:11619*0 + 3*32*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 11619*0 + 3*33*FLEN/8, x4, x1, x2)

inst_3874:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x355b9c and fs2 == 0 and fe2 == 0x82 and fm2 == 0x34ae72 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x000007 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7db55b9c; op2val:0x4134ae72;
op3val:0x7f000007; valaddr_reg:x3; val_offset:11622*0 + 3*33*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 11622*0 + 3*34*FLEN/8, x4, x1, x2)

inst_3875:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x355b9c and fs2 == 0 and fe2 == 0x82 and fm2 == 0x34ae72 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x199999 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7db55b9c; op2val:0x4134ae72;
op3val:0x7f199999; valaddr_reg:x3; val_offset:11625*0 + 3*34*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 11625*0 + 3*35*FLEN/8, x4, x1, x2)

inst_3876:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x355b9c and fs2 == 0 and fe2 == 0x82 and fm2 == 0x34ae72 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x249249 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7db55b9c; op2val:0x4134ae72;
op3val:0x7f249249; valaddr_reg:x3; val_offset:11628*0 + 3*35*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 11628*0 + 3*36*FLEN/8, x4, x1, x2)

inst_3877:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x355b9c and fs2 == 0 and fe2 == 0x82 and fm2 == 0x34ae72 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x333333 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7db55b9c; op2val:0x4134ae72;
op3val:0x7f333333; valaddr_reg:x3; val_offset:11631*0 + 3*36*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 11631*0 + 3*37*FLEN/8, x4, x1, x2)

inst_3878:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x355b9c and fs2 == 0 and fe2 == 0x82 and fm2 == 0x34ae72 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x36db6d and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7db55b9c; op2val:0x4134ae72;
op3val:0x7f36db6d; valaddr_reg:x3; val_offset:11634*0 + 3*37*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 11634*0 + 3*38*FLEN/8, x4, x1, x2)

inst_3879:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x355b9c and fs2 == 0 and fe2 == 0x82 and fm2 == 0x34ae72 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x3bbbbb and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7db55b9c; op2val:0x4134ae72;
op3val:0x7f3bbbbb; valaddr_reg:x3; val_offset:11637*0 + 3*38*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 11637*0 + 3*39*FLEN/8, x4, x1, x2)

inst_3880:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x355b9c and fs2 == 0 and fe2 == 0x82 and fm2 == 0x34ae72 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x444444 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7db55b9c; op2val:0x4134ae72;
op3val:0x7f444444; valaddr_reg:x3; val_offset:11640*0 + 3*39*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 11640*0 + 3*40*FLEN/8, x4, x1, x2)

inst_3881:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x355b9c and fs2 == 0 and fe2 == 0x82 and fm2 == 0x34ae72 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x4ccccc and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7db55b9c; op2val:0x4134ae72;
op3val:0x7f4ccccc; valaddr_reg:x3; val_offset:11643*0 + 3*40*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 11643*0 + 3*41*FLEN/8, x4, x1, x2)

inst_3882:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x355b9c and fs2 == 0 and fe2 == 0x82 and fm2 == 0x34ae72 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x5b6db6 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7db55b9c; op2val:0x4134ae72;
op3val:0x7f5b6db6; valaddr_reg:x3; val_offset:11646*0 + 3*41*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 11646*0 + 3*42*FLEN/8, x4, x1, x2)

inst_3883:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x355b9c and fs2 == 0 and fe2 == 0x82 and fm2 == 0x34ae72 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x666666 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7db55b9c; op2val:0x4134ae72;
op3val:0x7f666666; valaddr_reg:x3; val_offset:11649*0 + 3*42*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 11649*0 + 3*43*FLEN/8, x4, x1, x2)

inst_3884:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x355b9c and fs2 == 0 and fe2 == 0x82 and fm2 == 0x34ae72 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x6db6db and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7db55b9c; op2val:0x4134ae72;
op3val:0x7f6db6db; valaddr_reg:x3; val_offset:11652*0 + 3*43*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 11652*0 + 3*44*FLEN/8, x4, x1, x2)

inst_3885:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x355b9c and fs2 == 0 and fe2 == 0x82 and fm2 == 0x34ae72 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x7ffff8 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7db55b9c; op2val:0x4134ae72;
op3val:0x7f7ffff8; valaddr_reg:x3; val_offset:11655*0 + 3*44*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 11655*0 + 3*45*FLEN/8, x4, x1, x2)

inst_3886:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x355b9c and fs2 == 0 and fe2 == 0x82 and fm2 == 0x34ae72 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x7ffffc and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7db55b9c; op2val:0x4134ae72;
op3val:0x7f7ffffc; valaddr_reg:x3; val_offset:11658*0 + 3*45*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 11658*0 + 3*46*FLEN/8, x4, x1, x2)

inst_3887:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x355b9c and fs2 == 0 and fe2 == 0x82 and fm2 == 0x34ae72 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x7ffffe and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7db55b9c; op2val:0x4134ae72;
op3val:0x7f7ffffe; valaddr_reg:x3; val_offset:11661*0 + 3*46*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 11661*0 + 3*47*FLEN/8, x4, x1, x2)

inst_3888:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x3b15b6 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000001 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7dbb15b6; op2val:0x80000000;
op3val:0x80800001; valaddr_reg:x3; val_offset:11664*0 + 3*47*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 11664*0 + 3*48*FLEN/8, x4, x1, x2)

inst_3889:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x3b15b6 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000003 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7dbb15b6; op2val:0x80000000;
op3val:0x80800003; valaddr_reg:x3; val_offset:11667*0 + 3*48*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 11667*0 + 3*49*FLEN/8, x4, x1, x2)

inst_3890:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x3b15b6 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000007 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7dbb15b6; op2val:0x80000000;
op3val:0x80800007; valaddr_reg:x3; val_offset:11670*0 + 3*49*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 11670*0 + 3*50*FLEN/8, x4, x1, x2)

inst_3891:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x3b15b6 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x199999 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7dbb15b6; op2val:0x80000000;
op3val:0x80999999; valaddr_reg:x3; val_offset:11673*0 + 3*50*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 11673*0 + 3*51*FLEN/8, x4, x1, x2)

inst_3892:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x3b15b6 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x249249 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7dbb15b6; op2val:0x80000000;
op3val:0x80a49249; valaddr_reg:x3; val_offset:11676*0 + 3*51*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 11676*0 + 3*52*FLEN/8, x4, x1, x2)

inst_3893:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x3b15b6 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x333333 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7dbb15b6; op2val:0x80000000;
op3val:0x80b33333; valaddr_reg:x3; val_offset:11679*0 + 3*52*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 11679*0 + 3*53*FLEN/8, x4, x1, x2)

inst_3894:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x3b15b6 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x36db6d and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7dbb15b6; op2val:0x80000000;
op3val:0x80b6db6d; valaddr_reg:x3; val_offset:11682*0 + 3*53*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 11682*0 + 3*54*FLEN/8, x4, x1, x2)

inst_3895:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x3b15b6 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x3bbbbb and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7dbb15b6; op2val:0x80000000;
op3val:0x80bbbbbb; valaddr_reg:x3; val_offset:11685*0 + 3*54*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 11685*0 + 3*55*FLEN/8, x4, x1, x2)

inst_3896:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x3b15b6 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x444444 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7dbb15b6; op2val:0x80000000;
op3val:0x80c44444; valaddr_reg:x3; val_offset:11688*0 + 3*55*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 11688*0 + 3*56*FLEN/8, x4, x1, x2)

inst_3897:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x3b15b6 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x4ccccc and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7dbb15b6; op2val:0x80000000;
op3val:0x80cccccc; valaddr_reg:x3; val_offset:11691*0 + 3*56*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 11691*0 + 3*57*FLEN/8, x4, x1, x2)

inst_3898:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x3b15b6 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x5b6db6 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7dbb15b6; op2val:0x80000000;
op3val:0x80db6db6; valaddr_reg:x3; val_offset:11694*0 + 3*57*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 11694*0 + 3*58*FLEN/8, x4, x1, x2)

inst_3899:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x3b15b6 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x666666 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7dbb15b6; op2val:0x80000000;
op3val:0x80e66666; valaddr_reg:x3; val_offset:11697*0 + 3*58*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 11697*0 + 3*59*FLEN/8, x4, x1, x2)

inst_3900:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x3b15b6 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x6db6db and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7dbb15b6; op2val:0x80000000;
op3val:0x80edb6db; valaddr_reg:x3; val_offset:11700*0 + 3*59*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 11700*0 + 3*60*FLEN/8, x4, x1, x2)

inst_3901:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x3b15b6 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x7ffff8 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7dbb15b6; op2val:0x80000000;
op3val:0x80fffff8; valaddr_reg:x3; val_offset:11703*0 + 3*60*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 11703*0 + 3*61*FLEN/8, x4, x1, x2)

inst_3902:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x3b15b6 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x7ffffc and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7dbb15b6; op2val:0x80000000;
op3val:0x80fffffc; valaddr_reg:x3; val_offset:11706*0 + 3*61*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 11706*0 + 3*62*FLEN/8, x4, x1, x2)

inst_3903:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x3b15b6 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x7ffffe and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7dbb15b6; op2val:0x80000000;
op3val:0x80fffffe; valaddr_reg:x3; val_offset:11709*0 + 3*62*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 11709*0 + 3*63*FLEN/8, x4, x1, x2)

inst_3904:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x3b15b6 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x1d and fm3 == 0x000000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7dbb15b6; op2val:0x80000000;
op3val:0x8e800000; valaddr_reg:x3; val_offset:11712*0 + 3*63*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 11712*0 + 3*64*FLEN/8, x4, x1, x2)

inst_3905:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x3b15b6 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x1d and fm3 == 0x000001 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7dbb15b6; op2val:0x80000000;
op3val:0x8e800001; valaddr_reg:x3; val_offset:11715*0 + 3*64*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 11715*0 + 3*65*FLEN/8, x4, x1, x2)

inst_3906:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x3b15b6 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x1d and fm3 == 0x000003 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7dbb15b6; op2val:0x80000000;
op3val:0x8e800003; valaddr_reg:x3; val_offset:11718*0 + 3*65*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 11718*0 + 3*66*FLEN/8, x4, x1, x2)

inst_3907:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x3b15b6 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x1d and fm3 == 0x000007 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7dbb15b6; op2val:0x80000000;
op3val:0x8e800007; valaddr_reg:x3; val_offset:11721*0 + 3*66*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 11721*0 + 3*67*FLEN/8, x4, x1, x2)

inst_3908:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x3b15b6 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x1d and fm3 == 0x00000f and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7dbb15b6; op2val:0x80000000;
op3val:0x8e80000f; valaddr_reg:x3; val_offset:11724*0 + 3*67*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 11724*0 + 3*68*FLEN/8, x4, x1, x2)

inst_3909:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x3b15b6 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x1d and fm3 == 0x00001f and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7dbb15b6; op2val:0x80000000;
op3val:0x8e80001f; valaddr_reg:x3; val_offset:11727*0 + 3*68*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 11727*0 + 3*69*FLEN/8, x4, x1, x2)

inst_3910:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x3b15b6 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x1d and fm3 == 0x00003f and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7dbb15b6; op2val:0x80000000;
op3val:0x8e80003f; valaddr_reg:x3; val_offset:11730*0 + 3*69*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 11730*0 + 3*70*FLEN/8, x4, x1, x2)

inst_3911:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x3b15b6 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x1d and fm3 == 0x00007f and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7dbb15b6; op2val:0x80000000;
op3val:0x8e80007f; valaddr_reg:x3; val_offset:11733*0 + 3*70*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 11733*0 + 3*71*FLEN/8, x4, x1, x2)

inst_3912:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x3b15b6 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x1d and fm3 == 0x0000ff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7dbb15b6; op2val:0x80000000;
op3val:0x8e8000ff; valaddr_reg:x3; val_offset:11736*0 + 3*71*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 11736*0 + 3*72*FLEN/8, x4, x1, x2)

inst_3913:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x3b15b6 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x1d and fm3 == 0x0001ff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7dbb15b6; op2val:0x80000000;
op3val:0x8e8001ff; valaddr_reg:x3; val_offset:11739*0 + 3*72*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 11739*0 + 3*73*FLEN/8, x4, x1, x2)

inst_3914:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x3b15b6 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x1d and fm3 == 0x0003ff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7dbb15b6; op2val:0x80000000;
op3val:0x8e8003ff; valaddr_reg:x3; val_offset:11742*0 + 3*73*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 11742*0 + 3*74*FLEN/8, x4, x1, x2)

inst_3915:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x3b15b6 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x1d and fm3 == 0x0007ff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7dbb15b6; op2val:0x80000000;
op3val:0x8e8007ff; valaddr_reg:x3; val_offset:11745*0 + 3*74*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 11745*0 + 3*75*FLEN/8, x4, x1, x2)

inst_3916:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x3b15b6 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x1d and fm3 == 0x000fff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7dbb15b6; op2val:0x80000000;
op3val:0x8e800fff; valaddr_reg:x3; val_offset:11748*0 + 3*75*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 11748*0 + 3*76*FLEN/8, x4, x1, x2)

inst_3917:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x3b15b6 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x1d and fm3 == 0x001fff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7dbb15b6; op2val:0x80000000;
op3val:0x8e801fff; valaddr_reg:x3; val_offset:11751*0 + 3*76*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 11751*0 + 3*77*FLEN/8, x4, x1, x2)

inst_3918:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x3b15b6 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x1d and fm3 == 0x003fff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7dbb15b6; op2val:0x80000000;
op3val:0x8e803fff; valaddr_reg:x3; val_offset:11754*0 + 3*77*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 11754*0 + 3*78*FLEN/8, x4, x1, x2)

inst_3919:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x3b15b6 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x1d and fm3 == 0x007fff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7dbb15b6; op2val:0x80000000;
op3val:0x8e807fff; valaddr_reg:x3; val_offset:11757*0 + 3*78*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 11757*0 + 3*79*FLEN/8, x4, x1, x2)

inst_3920:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x3b15b6 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x1d and fm3 == 0x00ffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7dbb15b6; op2val:0x80000000;
op3val:0x8e80ffff; valaddr_reg:x3; val_offset:11760*0 + 3*79*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 11760*0 + 3*80*FLEN/8, x4, x1, x2)

inst_3921:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x3b15b6 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x1d and fm3 == 0x01ffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7dbb15b6; op2val:0x80000000;
op3val:0x8e81ffff; valaddr_reg:x3; val_offset:11763*0 + 3*80*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 11763*0 + 3*81*FLEN/8, x4, x1, x2)

inst_3922:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x3b15b6 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x1d and fm3 == 0x03ffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7dbb15b6; op2val:0x80000000;
op3val:0x8e83ffff; valaddr_reg:x3; val_offset:11766*0 + 3*81*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 11766*0 + 3*82*FLEN/8, x4, x1, x2)

inst_3923:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x3b15b6 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x1d and fm3 == 0x07ffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7dbb15b6; op2val:0x80000000;
op3val:0x8e87ffff; valaddr_reg:x3; val_offset:11769*0 + 3*82*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 11769*0 + 3*83*FLEN/8, x4, x1, x2)

inst_3924:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x3b15b6 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x1d and fm3 == 0x0fffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7dbb15b6; op2val:0x80000000;
op3val:0x8e8fffff; valaddr_reg:x3; val_offset:11772*0 + 3*83*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 11772*0 + 3*84*FLEN/8, x4, x1, x2)

inst_3925:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x3b15b6 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x1d and fm3 == 0x1fffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7dbb15b6; op2val:0x80000000;
op3val:0x8e9fffff; valaddr_reg:x3; val_offset:11775*0 + 3*84*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 11775*0 + 3*85*FLEN/8, x4, x1, x2)

inst_3926:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x3b15b6 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x1d and fm3 == 0x3fffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7dbb15b6; op2val:0x80000000;
op3val:0x8ebfffff; valaddr_reg:x3; val_offset:11778*0 + 3*85*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 11778*0 + 3*86*FLEN/8, x4, x1, x2)

inst_3927:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x3b15b6 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x1d and fm3 == 0x400000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7dbb15b6; op2val:0x80000000;
op3val:0x8ec00000; valaddr_reg:x3; val_offset:11781*0 + 3*86*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 11781*0 + 3*87*FLEN/8, x4, x1, x2)

inst_3928:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x3b15b6 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x1d and fm3 == 0x600000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7dbb15b6; op2val:0x80000000;
op3val:0x8ee00000; valaddr_reg:x3; val_offset:11784*0 + 3*87*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 11784*0 + 3*88*FLEN/8, x4, x1, x2)

inst_3929:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x3b15b6 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x1d and fm3 == 0x700000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7dbb15b6; op2val:0x80000000;
op3val:0x8ef00000; valaddr_reg:x3; val_offset:11787*0 + 3*88*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 11787*0 + 3*89*FLEN/8, x4, x1, x2)

inst_3930:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x3b15b6 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x1d and fm3 == 0x780000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7dbb15b6; op2val:0x80000000;
op3val:0x8ef80000; valaddr_reg:x3; val_offset:11790*0 + 3*89*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 11790*0 + 3*90*FLEN/8, x4, x1, x2)

inst_3931:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x3b15b6 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x1d and fm3 == 0x7c0000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7dbb15b6; op2val:0x80000000;
op3val:0x8efc0000; valaddr_reg:x3; val_offset:11793*0 + 3*90*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 11793*0 + 3*91*FLEN/8, x4, x1, x2)

inst_3932:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x3b15b6 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x1d and fm3 == 0x7e0000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7dbb15b6; op2val:0x80000000;
op3val:0x8efe0000; valaddr_reg:x3; val_offset:11796*0 + 3*91*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 11796*0 + 3*92*FLEN/8, x4, x1, x2)

inst_3933:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x3b15b6 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x1d and fm3 == 0x7f0000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7dbb15b6; op2val:0x80000000;
op3val:0x8eff0000; valaddr_reg:x3; val_offset:11799*0 + 3*92*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 11799*0 + 3*93*FLEN/8, x4, x1, x2)

inst_3934:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x3b15b6 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x1d and fm3 == 0x7f8000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7dbb15b6; op2val:0x80000000;
op3val:0x8eff8000; valaddr_reg:x3; val_offset:11802*0 + 3*93*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 11802*0 + 3*94*FLEN/8, x4, x1, x2)

inst_3935:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x3b15b6 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x1d and fm3 == 0x7fc000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7dbb15b6; op2val:0x80000000;
op3val:0x8effc000; valaddr_reg:x3; val_offset:11805*0 + 3*94*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 11805*0 + 3*95*FLEN/8, x4, x1, x2)

inst_3936:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x3b15b6 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x1d and fm3 == 0x7fe000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7dbb15b6; op2val:0x80000000;
op3val:0x8effe000; valaddr_reg:x3; val_offset:11808*0 + 3*95*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 11808*0 + 3*96*FLEN/8, x4, x1, x2)

inst_3937:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x3b15b6 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x1d and fm3 == 0x7ff000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7dbb15b6; op2val:0x80000000;
op3val:0x8efff000; valaddr_reg:x3; val_offset:11811*0 + 3*96*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 11811*0 + 3*97*FLEN/8, x4, x1, x2)

inst_3938:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x3b15b6 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x1d and fm3 == 0x7ff800 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7dbb15b6; op2val:0x80000000;
op3val:0x8efff800; valaddr_reg:x3; val_offset:11814*0 + 3*97*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 11814*0 + 3*98*FLEN/8, x4, x1, x2)

inst_3939:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x3b15b6 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x1d and fm3 == 0x7ffc00 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7dbb15b6; op2val:0x80000000;
op3val:0x8efffc00; valaddr_reg:x3; val_offset:11817*0 + 3*98*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 11817*0 + 3*99*FLEN/8, x4, x1, x2)

inst_3940:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x3b15b6 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x1d and fm3 == 0x7ffe00 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7dbb15b6; op2val:0x80000000;
op3val:0x8efffe00; valaddr_reg:x3; val_offset:11820*0 + 3*99*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 11820*0 + 3*100*FLEN/8, x4, x1, x2)

inst_3941:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x3b15b6 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x1d and fm3 == 0x7fff00 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7dbb15b6; op2val:0x80000000;
op3val:0x8effff00; valaddr_reg:x3; val_offset:11823*0 + 3*100*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 11823*0 + 3*101*FLEN/8, x4, x1, x2)

inst_3942:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x3b15b6 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x1d and fm3 == 0x7fff80 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7dbb15b6; op2val:0x80000000;
op3val:0x8effff80; valaddr_reg:x3; val_offset:11826*0 + 3*101*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 11826*0 + 3*102*FLEN/8, x4, x1, x2)

inst_3943:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x3b15b6 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x1d and fm3 == 0x7fffc0 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7dbb15b6; op2val:0x80000000;
op3val:0x8effffc0; valaddr_reg:x3; val_offset:11829*0 + 3*102*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 11829*0 + 3*103*FLEN/8, x4, x1, x2)

inst_3944:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x3b15b6 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x1d and fm3 == 0x7fffe0 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7dbb15b6; op2val:0x80000000;
op3val:0x8effffe0; valaddr_reg:x3; val_offset:11832*0 + 3*103*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 11832*0 + 3*104*FLEN/8, x4, x1, x2)

inst_3945:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x3b15b6 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x1d and fm3 == 0x7ffff0 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7dbb15b6; op2val:0x80000000;
op3val:0x8efffff0; valaddr_reg:x3; val_offset:11835*0 + 3*104*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 11835*0 + 3*105*FLEN/8, x4, x1, x2)

inst_3946:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x3b15b6 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x1d and fm3 == 0x7ffff8 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7dbb15b6; op2val:0x80000000;
op3val:0x8efffff8; valaddr_reg:x3; val_offset:11838*0 + 3*105*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 11838*0 + 3*106*FLEN/8, x4, x1, x2)

inst_3947:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x3b15b6 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x1d and fm3 == 0x7ffffc and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7dbb15b6; op2val:0x80000000;
op3val:0x8efffffc; valaddr_reg:x3; val_offset:11841*0 + 3*106*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 11841*0 + 3*107*FLEN/8, x4, x1, x2)

inst_3948:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x3b15b6 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x1d and fm3 == 0x7ffffe and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7dbb15b6; op2val:0x80000000;
op3val:0x8efffffe; valaddr_reg:x3; val_offset:11844*0 + 3*107*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 11844*0 + 3*108*FLEN/8, x4, x1, x2)

inst_3949:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x3b15b6 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x1d and fm3 == 0x7fffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7dbb15b6; op2val:0x80000000;
op3val:0x8effffff; valaddr_reg:x3; val_offset:11847*0 + 3*108*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 11847*0 + 3*109*FLEN/8, x4, x1, x2)

inst_3950:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x4006c8 and fs2 == 1 and fe2 == 0x02 and fm2 == 0x2aa4a3 and fs3 == 1 and fe3 == 0x7f and fm3 == 0x000001 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7dc006c8; op2val:0x812aa4a3;
op3val:0xbf800001; valaddr_reg:x3; val_offset:11850*0 + 3*109*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 11850*0 + 3*110*FLEN/8, x4, x1, x2)

inst_3951:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x4006c8 and fs2 == 1 and fe2 == 0x02 and fm2 == 0x2aa4a3 and fs3 == 1 and fe3 == 0x7f and fm3 == 0x000003 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7dc006c8; op2val:0x812aa4a3;
op3val:0xbf800003; valaddr_reg:x3; val_offset:11853*0 + 3*110*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 11853*0 + 3*111*FLEN/8, x4, x1, x2)

inst_3952:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x4006c8 and fs2 == 1 and fe2 == 0x02 and fm2 == 0x2aa4a3 and fs3 == 1 and fe3 == 0x7f and fm3 == 0x000007 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7dc006c8; op2val:0x812aa4a3;
op3val:0xbf800007; valaddr_reg:x3; val_offset:11856*0 + 3*111*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 11856*0 + 3*112*FLEN/8, x4, x1, x2)

inst_3953:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x4006c8 and fs2 == 1 and fe2 == 0x02 and fm2 == 0x2aa4a3 and fs3 == 1 and fe3 == 0x7f and fm3 == 0x199999 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7dc006c8; op2val:0x812aa4a3;
op3val:0xbf999999; valaddr_reg:x3; val_offset:11859*0 + 3*112*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 11859*0 + 3*113*FLEN/8, x4, x1, x2)

inst_3954:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x4006c8 and fs2 == 1 and fe2 == 0x02 and fm2 == 0x2aa4a3 and fs3 == 1 and fe3 == 0x7f and fm3 == 0x249249 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7dc006c8; op2val:0x812aa4a3;
op3val:0xbfa49249; valaddr_reg:x3; val_offset:11862*0 + 3*113*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 11862*0 + 3*114*FLEN/8, x4, x1, x2)

inst_3955:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x4006c8 and fs2 == 1 and fe2 == 0x02 and fm2 == 0x2aa4a3 and fs3 == 1 and fe3 == 0x7f and fm3 == 0x333333 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7dc006c8; op2val:0x812aa4a3;
op3val:0xbfb33333; valaddr_reg:x3; val_offset:11865*0 + 3*114*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 11865*0 + 3*115*FLEN/8, x4, x1, x2)

inst_3956:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x4006c8 and fs2 == 1 and fe2 == 0x02 and fm2 == 0x2aa4a3 and fs3 == 1 and fe3 == 0x7f and fm3 == 0x36db6d and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7dc006c8; op2val:0x812aa4a3;
op3val:0xbfb6db6d; valaddr_reg:x3; val_offset:11868*0 + 3*115*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 11868*0 + 3*116*FLEN/8, x4, x1, x2)

inst_3957:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x4006c8 and fs2 == 1 and fe2 == 0x02 and fm2 == 0x2aa4a3 and fs3 == 1 and fe3 == 0x7f and fm3 == 0x3bbbbb and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7dc006c8; op2val:0x812aa4a3;
op3val:0xbfbbbbbb; valaddr_reg:x3; val_offset:11871*0 + 3*116*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 11871*0 + 3*117*FLEN/8, x4, x1, x2)

inst_3958:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x4006c8 and fs2 == 1 and fe2 == 0x02 and fm2 == 0x2aa4a3 and fs3 == 1 and fe3 == 0x7f and fm3 == 0x444444 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7dc006c8; op2val:0x812aa4a3;
op3val:0xbfc44444; valaddr_reg:x3; val_offset:11874*0 + 3*117*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 11874*0 + 3*118*FLEN/8, x4, x1, x2)

inst_3959:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x4006c8 and fs2 == 1 and fe2 == 0x02 and fm2 == 0x2aa4a3 and fs3 == 1 and fe3 == 0x7f and fm3 == 0x4ccccc and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7dc006c8; op2val:0x812aa4a3;
op3val:0xbfcccccc; valaddr_reg:x3; val_offset:11877*0 + 3*118*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 11877*0 + 3*119*FLEN/8, x4, x1, x2)

inst_3960:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x4006c8 and fs2 == 1 and fe2 == 0x02 and fm2 == 0x2aa4a3 and fs3 == 1 and fe3 == 0x7f and fm3 == 0x5b6db6 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7dc006c8; op2val:0x812aa4a3;
op3val:0xbfdb6db6; valaddr_reg:x3; val_offset:11880*0 + 3*119*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 11880*0 + 3*120*FLEN/8, x4, x1, x2)

inst_3961:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x4006c8 and fs2 == 1 and fe2 == 0x02 and fm2 == 0x2aa4a3 and fs3 == 1 and fe3 == 0x7f and fm3 == 0x666666 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7dc006c8; op2val:0x812aa4a3;
op3val:0xbfe66666; valaddr_reg:x3; val_offset:11883*0 + 3*120*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 11883*0 + 3*121*FLEN/8, x4, x1, x2)

inst_3962:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x4006c8 and fs2 == 1 and fe2 == 0x02 and fm2 == 0x2aa4a3 and fs3 == 1 and fe3 == 0x7f and fm3 == 0x6db6db and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7dc006c8; op2val:0x812aa4a3;
op3val:0xbfedb6db; valaddr_reg:x3; val_offset:11886*0 + 3*121*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 11886*0 + 3*122*FLEN/8, x4, x1, x2)

inst_3963:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x4006c8 and fs2 == 1 and fe2 == 0x02 and fm2 == 0x2aa4a3 and fs3 == 1 and fe3 == 0x7f and fm3 == 0x7ffff8 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7dc006c8; op2val:0x812aa4a3;
op3val:0xbffffff8; valaddr_reg:x3; val_offset:11889*0 + 3*122*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 11889*0 + 3*123*FLEN/8, x4, x1, x2)

inst_3964:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x4006c8 and fs2 == 1 and fe2 == 0x02 and fm2 == 0x2aa4a3 and fs3 == 1 and fe3 == 0x7f and fm3 == 0x7ffffc and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7dc006c8; op2val:0x812aa4a3;
op3val:0xbffffffc; valaddr_reg:x3; val_offset:11892*0 + 3*123*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 11892*0 + 3*124*FLEN/8, x4, x1, x2)

inst_3965:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x4006c8 and fs2 == 1 and fe2 == 0x02 and fm2 == 0x2aa4a3 and fs3 == 1 and fe3 == 0x7f and fm3 == 0x7ffffe and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7dc006c8; op2val:0x812aa4a3;
op3val:0xbffffffe; valaddr_reg:x3; val_offset:11895*0 + 3*124*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 11895*0 + 3*125*FLEN/8, x4, x1, x2)

inst_3966:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x4006c8 and fs2 == 1 and fe2 == 0x02 and fm2 == 0x2aa4a3 and fs3 == 1 and fe3 == 0x80 and fm3 == 0x000000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7dc006c8; op2val:0x812aa4a3;
op3val:0xc0000000; valaddr_reg:x3; val_offset:11898*0 + 3*125*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 11898*0 + 3*126*FLEN/8, x4, x1, x2)

inst_3967:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x4006c8 and fs2 == 1 and fe2 == 0x02 and fm2 == 0x2aa4a3 and fs3 == 1 and fe3 == 0x80 and fm3 == 0x000001 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7dc006c8; op2val:0x812aa4a3;
op3val:0xc0000001; valaddr_reg:x3; val_offset:11901*0 + 3*126*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 11901*0 + 3*127*FLEN/8, x4, x1, x2)
RVTEST_SIGBASE(x1,signature_x1_2)

inst_3968:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x4006c8 and fs2 == 1 and fe2 == 0x02 and fm2 == 0x2aa4a3 and fs3 == 1 and fe3 == 0x80 and fm3 == 0x000003 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7dc006c8; op2val:0x812aa4a3;
op3val:0xc0000003; valaddr_reg:x3; val_offset:11904*0 + 3*127*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 11904*0 + 3*128*FLEN/8, x4, x1, x2)

inst_3969:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x4006c8 and fs2 == 1 and fe2 == 0x02 and fm2 == 0x2aa4a3 and fs3 == 1 and fe3 == 0x80 and fm3 == 0x000007 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7dc006c8; op2val:0x812aa4a3;
op3val:0xc0000007; valaddr_reg:x3; val_offset:11907*0 + 3*128*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 11907*0 + 3*129*FLEN/8, x4, x1, x2)

inst_3970:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x4006c8 and fs2 == 1 and fe2 == 0x02 and fm2 == 0x2aa4a3 and fs3 == 1 and fe3 == 0x80 and fm3 == 0x00000f and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7dc006c8; op2val:0x812aa4a3;
op3val:0xc000000f; valaddr_reg:x3; val_offset:11910*0 + 3*129*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 11910*0 + 3*130*FLEN/8, x4, x1, x2)

inst_3971:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x4006c8 and fs2 == 1 and fe2 == 0x02 and fm2 == 0x2aa4a3 and fs3 == 1 and fe3 == 0x80 and fm3 == 0x00001f and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7dc006c8; op2val:0x812aa4a3;
op3val:0xc000001f; valaddr_reg:x3; val_offset:11913*0 + 3*130*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 11913*0 + 3*131*FLEN/8, x4, x1, x2)

inst_3972:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x4006c8 and fs2 == 1 and fe2 == 0x02 and fm2 == 0x2aa4a3 and fs3 == 1 and fe3 == 0x80 and fm3 == 0x00003f and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7dc006c8; op2val:0x812aa4a3;
op3val:0xc000003f; valaddr_reg:x3; val_offset:11916*0 + 3*131*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 11916*0 + 3*132*FLEN/8, x4, x1, x2)

inst_3973:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x4006c8 and fs2 == 1 and fe2 == 0x02 and fm2 == 0x2aa4a3 and fs3 == 1 and fe3 == 0x80 and fm3 == 0x00007f and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7dc006c8; op2val:0x812aa4a3;
op3val:0xc000007f; valaddr_reg:x3; val_offset:11919*0 + 3*132*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 11919*0 + 3*133*FLEN/8, x4, x1, x2)

inst_3974:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x4006c8 and fs2 == 1 and fe2 == 0x02 and fm2 == 0x2aa4a3 and fs3 == 1 and fe3 == 0x80 and fm3 == 0x0000ff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7dc006c8; op2val:0x812aa4a3;
op3val:0xc00000ff; valaddr_reg:x3; val_offset:11922*0 + 3*133*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 11922*0 + 3*134*FLEN/8, x4, x1, x2)

inst_3975:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x4006c8 and fs2 == 1 and fe2 == 0x02 and fm2 == 0x2aa4a3 and fs3 == 1 and fe3 == 0x80 and fm3 == 0x0001ff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7dc006c8; op2val:0x812aa4a3;
op3val:0xc00001ff; valaddr_reg:x3; val_offset:11925*0 + 3*134*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 11925*0 + 3*135*FLEN/8, x4, x1, x2)

inst_3976:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x4006c8 and fs2 == 1 and fe2 == 0x02 and fm2 == 0x2aa4a3 and fs3 == 1 and fe3 == 0x80 and fm3 == 0x0003ff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7dc006c8; op2val:0x812aa4a3;
op3val:0xc00003ff; valaddr_reg:x3; val_offset:11928*0 + 3*135*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 11928*0 + 3*136*FLEN/8, x4, x1, x2)

inst_3977:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x4006c8 and fs2 == 1 and fe2 == 0x02 and fm2 == 0x2aa4a3 and fs3 == 1 and fe3 == 0x80 and fm3 == 0x0007ff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7dc006c8; op2val:0x812aa4a3;
op3val:0xc00007ff; valaddr_reg:x3; val_offset:11931*0 + 3*136*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 11931*0 + 3*137*FLEN/8, x4, x1, x2)

inst_3978:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x4006c8 and fs2 == 1 and fe2 == 0x02 and fm2 == 0x2aa4a3 and fs3 == 1 and fe3 == 0x80 and fm3 == 0x000fff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7dc006c8; op2val:0x812aa4a3;
op3val:0xc0000fff; valaddr_reg:x3; val_offset:11934*0 + 3*137*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 11934*0 + 3*138*FLEN/8, x4, x1, x2)

inst_3979:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x4006c8 and fs2 == 1 and fe2 == 0x02 and fm2 == 0x2aa4a3 and fs3 == 1 and fe3 == 0x80 and fm3 == 0x001fff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7dc006c8; op2val:0x812aa4a3;
op3val:0xc0001fff; valaddr_reg:x3; val_offset:11937*0 + 3*138*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 11937*0 + 3*139*FLEN/8, x4, x1, x2)

inst_3980:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x4006c8 and fs2 == 1 and fe2 == 0x02 and fm2 == 0x2aa4a3 and fs3 == 1 and fe3 == 0x80 and fm3 == 0x003fff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7dc006c8; op2val:0x812aa4a3;
op3val:0xc0003fff; valaddr_reg:x3; val_offset:11940*0 + 3*139*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 11940*0 + 3*140*FLEN/8, x4, x1, x2)

inst_3981:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x4006c8 and fs2 == 1 and fe2 == 0x02 and fm2 == 0x2aa4a3 and fs3 == 1 and fe3 == 0x80 and fm3 == 0x007fff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7dc006c8; op2val:0x812aa4a3;
op3val:0xc0007fff; valaddr_reg:x3; val_offset:11943*0 + 3*140*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 11943*0 + 3*141*FLEN/8, x4, x1, x2)

inst_3982:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x4006c8 and fs2 == 1 and fe2 == 0x02 and fm2 == 0x2aa4a3 and fs3 == 1 and fe3 == 0x80 and fm3 == 0x00ffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7dc006c8; op2val:0x812aa4a3;
op3val:0xc000ffff; valaddr_reg:x3; val_offset:11946*0 + 3*141*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 11946*0 + 3*142*FLEN/8, x4, x1, x2)

inst_3983:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x4006c8 and fs2 == 1 and fe2 == 0x02 and fm2 == 0x2aa4a3 and fs3 == 1 and fe3 == 0x80 and fm3 == 0x01ffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7dc006c8; op2val:0x812aa4a3;
op3val:0xc001ffff; valaddr_reg:x3; val_offset:11949*0 + 3*142*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 11949*0 + 3*143*FLEN/8, x4, x1, x2)

inst_3984:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x4006c8 and fs2 == 1 and fe2 == 0x02 and fm2 == 0x2aa4a3 and fs3 == 1 and fe3 == 0x80 and fm3 == 0x03ffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7dc006c8; op2val:0x812aa4a3;
op3val:0xc003ffff; valaddr_reg:x3; val_offset:11952*0 + 3*143*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 11952*0 + 3*144*FLEN/8, x4, x1, x2)

inst_3985:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x4006c8 and fs2 == 1 and fe2 == 0x02 and fm2 == 0x2aa4a3 and fs3 == 1 and fe3 == 0x80 and fm3 == 0x07ffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7dc006c8; op2val:0x812aa4a3;
op3val:0xc007ffff; valaddr_reg:x3; val_offset:11955*0 + 3*144*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 11955*0 + 3*145*FLEN/8, x4, x1, x2)

inst_3986:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x4006c8 and fs2 == 1 and fe2 == 0x02 and fm2 == 0x2aa4a3 and fs3 == 1 and fe3 == 0x80 and fm3 == 0x0fffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7dc006c8; op2val:0x812aa4a3;
op3val:0xc00fffff; valaddr_reg:x3; val_offset:11958*0 + 3*145*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 11958*0 + 3*146*FLEN/8, x4, x1, x2)

inst_3987:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x4006c8 and fs2 == 1 and fe2 == 0x02 and fm2 == 0x2aa4a3 and fs3 == 1 and fe3 == 0x80 and fm3 == 0x1fffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7dc006c8; op2val:0x812aa4a3;
op3val:0xc01fffff; valaddr_reg:x3; val_offset:11961*0 + 3*146*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 11961*0 + 3*147*FLEN/8, x4, x1, x2)

inst_3988:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x4006c8 and fs2 == 1 and fe2 == 0x02 and fm2 == 0x2aa4a3 and fs3 == 1 and fe3 == 0x80 and fm3 == 0x3fffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7dc006c8; op2val:0x812aa4a3;
op3val:0xc03fffff; valaddr_reg:x3; val_offset:11964*0 + 3*147*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 11964*0 + 3*148*FLEN/8, x4, x1, x2)

inst_3989:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x4006c8 and fs2 == 1 and fe2 == 0x02 and fm2 == 0x2aa4a3 and fs3 == 1 and fe3 == 0x80 and fm3 == 0x400000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7dc006c8; op2val:0x812aa4a3;
op3val:0xc0400000; valaddr_reg:x3; val_offset:11967*0 + 3*148*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 11967*0 + 3*149*FLEN/8, x4, x1, x2)

inst_3990:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x4006c8 and fs2 == 1 and fe2 == 0x02 and fm2 == 0x2aa4a3 and fs3 == 1 and fe3 == 0x80 and fm3 == 0x600000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7dc006c8; op2val:0x812aa4a3;
op3val:0xc0600000; valaddr_reg:x3; val_offset:11970*0 + 3*149*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 11970*0 + 3*150*FLEN/8, x4, x1, x2)

inst_3991:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x4006c8 and fs2 == 1 and fe2 == 0x02 and fm2 == 0x2aa4a3 and fs3 == 1 and fe3 == 0x80 and fm3 == 0x700000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7dc006c8; op2val:0x812aa4a3;
op3val:0xc0700000; valaddr_reg:x3; val_offset:11973*0 + 3*150*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 11973*0 + 3*151*FLEN/8, x4, x1, x2)

inst_3992:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x4006c8 and fs2 == 1 and fe2 == 0x02 and fm2 == 0x2aa4a3 and fs3 == 1 and fe3 == 0x80 and fm3 == 0x780000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7dc006c8; op2val:0x812aa4a3;
op3val:0xc0780000; valaddr_reg:x3; val_offset:11976*0 + 3*151*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 11976*0 + 3*152*FLEN/8, x4, x1, x2)

inst_3993:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x4006c8 and fs2 == 1 and fe2 == 0x02 and fm2 == 0x2aa4a3 and fs3 == 1 and fe3 == 0x80 and fm3 == 0x7c0000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7dc006c8; op2val:0x812aa4a3;
op3val:0xc07c0000; valaddr_reg:x3; val_offset:11979*0 + 3*152*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 11979*0 + 3*153*FLEN/8, x4, x1, x2)

inst_3994:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x4006c8 and fs2 == 1 and fe2 == 0x02 and fm2 == 0x2aa4a3 and fs3 == 1 and fe3 == 0x80 and fm3 == 0x7e0000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7dc006c8; op2val:0x812aa4a3;
op3val:0xc07e0000; valaddr_reg:x3; val_offset:11982*0 + 3*153*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 11982*0 + 3*154*FLEN/8, x4, x1, x2)

inst_3995:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x4006c8 and fs2 == 1 and fe2 == 0x02 and fm2 == 0x2aa4a3 and fs3 == 1 and fe3 == 0x80 and fm3 == 0x7f0000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7dc006c8; op2val:0x812aa4a3;
op3val:0xc07f0000; valaddr_reg:x3; val_offset:11985*0 + 3*154*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 11985*0 + 3*155*FLEN/8, x4, x1, x2)

inst_3996:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x4006c8 and fs2 == 1 and fe2 == 0x02 and fm2 == 0x2aa4a3 and fs3 == 1 and fe3 == 0x80 and fm3 == 0x7f8000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7dc006c8; op2val:0x812aa4a3;
op3val:0xc07f8000; valaddr_reg:x3; val_offset:11988*0 + 3*155*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 11988*0 + 3*156*FLEN/8, x4, x1, x2)

inst_3997:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x4006c8 and fs2 == 1 and fe2 == 0x02 and fm2 == 0x2aa4a3 and fs3 == 1 and fe3 == 0x80 and fm3 == 0x7fc000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7dc006c8; op2val:0x812aa4a3;
op3val:0xc07fc000; valaddr_reg:x3; val_offset:11991*0 + 3*156*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 11991*0 + 3*157*FLEN/8, x4, x1, x2)

inst_3998:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x4006c8 and fs2 == 1 and fe2 == 0x02 and fm2 == 0x2aa4a3 and fs3 == 1 and fe3 == 0x80 and fm3 == 0x7fe000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7dc006c8; op2val:0x812aa4a3;
op3val:0xc07fe000; valaddr_reg:x3; val_offset:11994*0 + 3*157*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 11994*0 + 3*158*FLEN/8, x4, x1, x2)

inst_3999:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x4006c8 and fs2 == 1 and fe2 == 0x02 and fm2 == 0x2aa4a3 and fs3 == 1 and fe3 == 0x80 and fm3 == 0x7ff000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7dc006c8; op2val:0x812aa4a3;
op3val:0xc07ff000; valaddr_reg:x3; val_offset:11997*0 + 3*158*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 11997*0 + 3*159*FLEN/8, x4, x1, x2)

inst_4000:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x4006c8 and fs2 == 1 and fe2 == 0x02 and fm2 == 0x2aa4a3 and fs3 == 1 and fe3 == 0x80 and fm3 == 0x7ff800 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7dc006c8; op2val:0x812aa4a3;
op3val:0xc07ff800; valaddr_reg:x3; val_offset:12000*0 + 3*159*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 12000*0 + 3*160*FLEN/8, x4, x1, x2)

inst_4001:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x4006c8 and fs2 == 1 and fe2 == 0x02 and fm2 == 0x2aa4a3 and fs3 == 1 and fe3 == 0x80 and fm3 == 0x7ffc00 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7dc006c8; op2val:0x812aa4a3;
op3val:0xc07ffc00; valaddr_reg:x3; val_offset:12003*0 + 3*160*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 12003*0 + 3*161*FLEN/8, x4, x1, x2)

inst_4002:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x4006c8 and fs2 == 1 and fe2 == 0x02 and fm2 == 0x2aa4a3 and fs3 == 1 and fe3 == 0x80 and fm3 == 0x7ffe00 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7dc006c8; op2val:0x812aa4a3;
op3val:0xc07ffe00; valaddr_reg:x3; val_offset:12006*0 + 3*161*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 12006*0 + 3*162*FLEN/8, x4, x1, x2)

inst_4003:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x4006c8 and fs2 == 1 and fe2 == 0x02 and fm2 == 0x2aa4a3 and fs3 == 1 and fe3 == 0x80 and fm3 == 0x7fff00 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7dc006c8; op2val:0x812aa4a3;
op3val:0xc07fff00; valaddr_reg:x3; val_offset:12009*0 + 3*162*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 12009*0 + 3*163*FLEN/8, x4, x1, x2)

inst_4004:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x4006c8 and fs2 == 1 and fe2 == 0x02 and fm2 == 0x2aa4a3 and fs3 == 1 and fe3 == 0x80 and fm3 == 0x7fff80 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7dc006c8; op2val:0x812aa4a3;
op3val:0xc07fff80; valaddr_reg:x3; val_offset:12012*0 + 3*163*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 12012*0 + 3*164*FLEN/8, x4, x1, x2)

inst_4005:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x4006c8 and fs2 == 1 and fe2 == 0x02 and fm2 == 0x2aa4a3 and fs3 == 1 and fe3 == 0x80 and fm3 == 0x7fffc0 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7dc006c8; op2val:0x812aa4a3;
op3val:0xc07fffc0; valaddr_reg:x3; val_offset:12015*0 + 3*164*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 12015*0 + 3*165*FLEN/8, x4, x1, x2)

inst_4006:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x4006c8 and fs2 == 1 and fe2 == 0x02 and fm2 == 0x2aa4a3 and fs3 == 1 and fe3 == 0x80 and fm3 == 0x7fffe0 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7dc006c8; op2val:0x812aa4a3;
op3val:0xc07fffe0; valaddr_reg:x3; val_offset:12018*0 + 3*165*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 12018*0 + 3*166*FLEN/8, x4, x1, x2)

inst_4007:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x4006c8 and fs2 == 1 and fe2 == 0x02 and fm2 == 0x2aa4a3 and fs3 == 1 and fe3 == 0x80 and fm3 == 0x7ffff0 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7dc006c8; op2val:0x812aa4a3;
op3val:0xc07ffff0; valaddr_reg:x3; val_offset:12021*0 + 3*166*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 12021*0 + 3*167*FLEN/8, x4, x1, x2)

inst_4008:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x4006c8 and fs2 == 1 and fe2 == 0x02 and fm2 == 0x2aa4a3 and fs3 == 1 and fe3 == 0x80 and fm3 == 0x7ffff8 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7dc006c8; op2val:0x812aa4a3;
op3val:0xc07ffff8; valaddr_reg:x3; val_offset:12024*0 + 3*167*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 12024*0 + 3*168*FLEN/8, x4, x1, x2)

inst_4009:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x4006c8 and fs2 == 1 and fe2 == 0x02 and fm2 == 0x2aa4a3 and fs3 == 1 and fe3 == 0x80 and fm3 == 0x7ffffc and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7dc006c8; op2val:0x812aa4a3;
op3val:0xc07ffffc; valaddr_reg:x3; val_offset:12027*0 + 3*168*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 12027*0 + 3*169*FLEN/8, x4, x1, x2)

inst_4010:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x4006c8 and fs2 == 1 and fe2 == 0x02 and fm2 == 0x2aa4a3 and fs3 == 1 and fe3 == 0x80 and fm3 == 0x7ffffe and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7dc006c8; op2val:0x812aa4a3;
op3val:0xc07ffffe; valaddr_reg:x3; val_offset:12030*0 + 3*169*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 12030*0 + 3*170*FLEN/8, x4, x1, x2)

inst_4011:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x4006c8 and fs2 == 1 and fe2 == 0x02 and fm2 == 0x2aa4a3 and fs3 == 1 and fe3 == 0x80 and fm3 == 0x7fffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7dc006c8; op2val:0x812aa4a3;
op3val:0xc07fffff; valaddr_reg:x3; val_offset:12033*0 + 3*170*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 12033*0 + 3*171*FLEN/8, x4, x1, x2)

inst_4012:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x4032ba and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7dc032ba; op2val:0x80000000;
op3val:0x80000000; valaddr_reg:x3; val_offset:12036*0 + 3*171*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 12036*0 + 3*172*FLEN/8, x4, x1, x2)

inst_4013:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x4032ba and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000001 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7dc032ba; op2val:0x80000000;
op3val:0x80000001; valaddr_reg:x3; val_offset:12039*0 + 3*172*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 12039*0 + 3*173*FLEN/8, x4, x1, x2)

inst_4014:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x4032ba and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000003 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7dc032ba; op2val:0x80000000;
op3val:0x80000003; valaddr_reg:x3; val_offset:12042*0 + 3*173*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 12042*0 + 3*174*FLEN/8, x4, x1, x2)

inst_4015:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x4032ba and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000007 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7dc032ba; op2val:0x80000000;
op3val:0x80000007; valaddr_reg:x3; val_offset:12045*0 + 3*174*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 12045*0 + 3*175*FLEN/8, x4, x1, x2)

inst_4016:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x4032ba and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x00000f and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7dc032ba; op2val:0x80000000;
op3val:0x8000000f; valaddr_reg:x3; val_offset:12048*0 + 3*175*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 12048*0 + 3*176*FLEN/8, x4, x1, x2)

inst_4017:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x4032ba and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x00001f and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7dc032ba; op2val:0x80000000;
op3val:0x8000001f; valaddr_reg:x3; val_offset:12051*0 + 3*176*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 12051*0 + 3*177*FLEN/8, x4, x1, x2)

inst_4018:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x4032ba and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x00003f and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7dc032ba; op2val:0x80000000;
op3val:0x8000003f; valaddr_reg:x3; val_offset:12054*0 + 3*177*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 12054*0 + 3*178*FLEN/8, x4, x1, x2)

inst_4019:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x4032ba and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x00007f and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7dc032ba; op2val:0x80000000;
op3val:0x8000007f; valaddr_reg:x3; val_offset:12057*0 + 3*178*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 12057*0 + 3*179*FLEN/8, x4, x1, x2)

inst_4020:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x4032ba and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x0000ff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7dc032ba; op2val:0x80000000;
op3val:0x800000ff; valaddr_reg:x3; val_offset:12060*0 + 3*179*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 12060*0 + 3*180*FLEN/8, x4, x1, x2)

inst_4021:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x4032ba and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x0001ff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7dc032ba; op2val:0x80000000;
op3val:0x800001ff; valaddr_reg:x3; val_offset:12063*0 + 3*180*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 12063*0 + 3*181*FLEN/8, x4, x1, x2)

inst_4022:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x4032ba and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x0003ff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7dc032ba; op2val:0x80000000;
op3val:0x800003ff; valaddr_reg:x3; val_offset:12066*0 + 3*181*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 12066*0 + 3*182*FLEN/8, x4, x1, x2)

inst_4023:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x4032ba and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x0007ff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7dc032ba; op2val:0x80000000;
op3val:0x800007ff; valaddr_reg:x3; val_offset:12069*0 + 3*182*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 12069*0 + 3*183*FLEN/8, x4, x1, x2)

inst_4024:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x4032ba and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000fff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7dc032ba; op2val:0x80000000;
op3val:0x80000fff; valaddr_reg:x3; val_offset:12072*0 + 3*183*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 12072*0 + 3*184*FLEN/8, x4, x1, x2)

inst_4025:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x4032ba and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x001fff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7dc032ba; op2val:0x80000000;
op3val:0x80001fff; valaddr_reg:x3; val_offset:12075*0 + 3*184*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 12075*0 + 3*185*FLEN/8, x4, x1, x2)

inst_4026:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x4032ba and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x003fff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7dc032ba; op2val:0x80000000;
op3val:0x80003fff; valaddr_reg:x3; val_offset:12078*0 + 3*185*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 12078*0 + 3*186*FLEN/8, x4, x1, x2)

inst_4027:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x4032ba and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x007fff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7dc032ba; op2val:0x80000000;
op3val:0x80007fff; valaddr_reg:x3; val_offset:12081*0 + 3*186*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 12081*0 + 3*187*FLEN/8, x4, x1, x2)

inst_4028:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x4032ba and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x00ffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7dc032ba; op2val:0x80000000;
op3val:0x8000ffff; valaddr_reg:x3; val_offset:12084*0 + 3*187*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 12084*0 + 3*188*FLEN/8, x4, x1, x2)

inst_4029:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x4032ba and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x01ffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7dc032ba; op2val:0x80000000;
op3val:0x8001ffff; valaddr_reg:x3; val_offset:12087*0 + 3*188*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 12087*0 + 3*189*FLEN/8, x4, x1, x2)

inst_4030:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x4032ba and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x03ffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7dc032ba; op2val:0x80000000;
op3val:0x8003ffff; valaddr_reg:x3; val_offset:12090*0 + 3*189*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 12090*0 + 3*190*FLEN/8, x4, x1, x2)

inst_4031:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x4032ba and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x07ffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7dc032ba; op2val:0x80000000;
op3val:0x8007ffff; valaddr_reg:x3; val_offset:12093*0 + 3*190*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 12093*0 + 3*191*FLEN/8, x4, x1, x2)

inst_4032:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x4032ba and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x0fffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7dc032ba; op2val:0x80000000;
op3val:0x800fffff; valaddr_reg:x3; val_offset:12096*0 + 3*191*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 12096*0 + 3*192*FLEN/8, x4, x1, x2)

inst_4033:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x4032ba and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x199999 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7dc032ba; op2val:0x80000000;
op3val:0x80199999; valaddr_reg:x3; val_offset:12099*0 + 3*192*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 12099*0 + 3*193*FLEN/8, x4, x1, x2)

inst_4034:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x4032ba and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x1fffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7dc032ba; op2val:0x80000000;
op3val:0x801fffff; valaddr_reg:x3; val_offset:12102*0 + 3*193*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 12102*0 + 3*194*FLEN/8, x4, x1, x2)

inst_4035:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x4032ba and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x249249 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7dc032ba; op2val:0x80000000;
op3val:0x80249249; valaddr_reg:x3; val_offset:12105*0 + 3*194*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 12105*0 + 3*195*FLEN/8, x4, x1, x2)

inst_4036:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x4032ba and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x333333 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7dc032ba; op2val:0x80000000;
op3val:0x80333333; valaddr_reg:x3; val_offset:12108*0 + 3*195*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 12108*0 + 3*196*FLEN/8, x4, x1, x2)

inst_4037:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x4032ba and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x36db6d and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7dc032ba; op2val:0x80000000;
op3val:0x8036db6d; valaddr_reg:x3; val_offset:12111*0 + 3*196*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 12111*0 + 3*197*FLEN/8, x4, x1, x2)

inst_4038:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x4032ba and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3bbbbb and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7dc032ba; op2val:0x80000000;
op3val:0x803bbbbb; valaddr_reg:x3; val_offset:12114*0 + 3*197*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 12114*0 + 3*198*FLEN/8, x4, x1, x2)

inst_4039:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x4032ba and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3fffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7dc032ba; op2val:0x80000000;
op3val:0x803fffff; valaddr_reg:x3; val_offset:12117*0 + 3*198*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 12117*0 + 3*199*FLEN/8, x4, x1, x2)

inst_4040:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x4032ba and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x400000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7dc032ba; op2val:0x80000000;
op3val:0x80400000; valaddr_reg:x3; val_offset:12120*0 + 3*199*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 12120*0 + 3*200*FLEN/8, x4, x1, x2)

inst_4041:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x4032ba and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x444444 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7dc032ba; op2val:0x80000000;
op3val:0x80444444; valaddr_reg:x3; val_offset:12123*0 + 3*200*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 12123*0 + 3*201*FLEN/8, x4, x1, x2)

inst_4042:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x4032ba and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x4ccccc and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7dc032ba; op2val:0x80000000;
op3val:0x804ccccc; valaddr_reg:x3; val_offset:12126*0 + 3*201*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 12126*0 + 3*202*FLEN/8, x4, x1, x2)

inst_4043:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x4032ba and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x5b6db6 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7dc032ba; op2val:0x80000000;
op3val:0x805b6db6; valaddr_reg:x3; val_offset:12129*0 + 3*202*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 12129*0 + 3*203*FLEN/8, x4, x1, x2)

inst_4044:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x4032ba and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x600000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7dc032ba; op2val:0x80000000;
op3val:0x80600000; valaddr_reg:x3; val_offset:12132*0 + 3*203*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 12132*0 + 3*204*FLEN/8, x4, x1, x2)

inst_4045:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x4032ba and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x666666 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7dc032ba; op2val:0x80000000;
op3val:0x80666666; valaddr_reg:x3; val_offset:12135*0 + 3*204*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 12135*0 + 3*205*FLEN/8, x4, x1, x2)

inst_4046:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x4032ba and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x6db6db and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7dc032ba; op2val:0x80000000;
op3val:0x806db6db; valaddr_reg:x3; val_offset:12138*0 + 3*205*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 12138*0 + 3*206*FLEN/8, x4, x1, x2)

inst_4047:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x4032ba and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x700000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7dc032ba; op2val:0x80000000;
op3val:0x80700000; valaddr_reg:x3; val_offset:12141*0 + 3*206*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 12141*0 + 3*207*FLEN/8, x4, x1, x2)

inst_4048:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x4032ba and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x780000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7dc032ba; op2val:0x80000000;
op3val:0x80780000; valaddr_reg:x3; val_offset:12144*0 + 3*207*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 12144*0 + 3*208*FLEN/8, x4, x1, x2)

inst_4049:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x4032ba and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7c0000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7dc032ba; op2val:0x80000000;
op3val:0x807c0000; valaddr_reg:x3; val_offset:12147*0 + 3*208*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 12147*0 + 3*209*FLEN/8, x4, x1, x2)

inst_4050:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x4032ba and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7e0000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7dc032ba; op2val:0x80000000;
op3val:0x807e0000; valaddr_reg:x3; val_offset:12150*0 + 3*209*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 12150*0 + 3*210*FLEN/8, x4, x1, x2)

inst_4051:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x4032ba and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7f0000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7dc032ba; op2val:0x80000000;
op3val:0x807f0000; valaddr_reg:x3; val_offset:12153*0 + 3*210*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 12153*0 + 3*211*FLEN/8, x4, x1, x2)

inst_4052:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x4032ba and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7f8000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7dc032ba; op2val:0x80000000;
op3val:0x807f8000; valaddr_reg:x3; val_offset:12156*0 + 3*211*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 12156*0 + 3*212*FLEN/8, x4, x1, x2)

inst_4053:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x4032ba and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7fc000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7dc032ba; op2val:0x80000000;
op3val:0x807fc000; valaddr_reg:x3; val_offset:12159*0 + 3*212*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 12159*0 + 3*213*FLEN/8, x4, x1, x2)

inst_4054:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x4032ba and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7fe000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7dc032ba; op2val:0x80000000;
op3val:0x807fe000; valaddr_reg:x3; val_offset:12162*0 + 3*213*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 12162*0 + 3*214*FLEN/8, x4, x1, x2)

inst_4055:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x4032ba and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7ff000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7dc032ba; op2val:0x80000000;
op3val:0x807ff000; valaddr_reg:x3; val_offset:12165*0 + 3*214*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 12165*0 + 3*215*FLEN/8, x4, x1, x2)

inst_4056:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x4032ba and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7ff800 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7dc032ba; op2val:0x80000000;
op3val:0x807ff800; valaddr_reg:x3; val_offset:12168*0 + 3*215*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 12168*0 + 3*216*FLEN/8, x4, x1, x2)

inst_4057:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x4032ba and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7ffc00 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7dc032ba; op2val:0x80000000;
op3val:0x807ffc00; valaddr_reg:x3; val_offset:12171*0 + 3*216*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 12171*0 + 3*217*FLEN/8, x4, x1, x2)

inst_4058:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x4032ba and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7ffe00 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7dc032ba; op2val:0x80000000;
op3val:0x807ffe00; valaddr_reg:x3; val_offset:12174*0 + 3*217*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 12174*0 + 3*218*FLEN/8, x4, x1, x2)

inst_4059:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x4032ba and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7fff00 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7dc032ba; op2val:0x80000000;
op3val:0x807fff00; valaddr_reg:x3; val_offset:12177*0 + 3*218*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 12177*0 + 3*219*FLEN/8, x4, x1, x2)

inst_4060:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x4032ba and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7fff80 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7dc032ba; op2val:0x80000000;
op3val:0x807fff80; valaddr_reg:x3; val_offset:12180*0 + 3*219*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 12180*0 + 3*220*FLEN/8, x4, x1, x2)

inst_4061:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x4032ba and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7fffc0 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7dc032ba; op2val:0x80000000;
op3val:0x807fffc0; valaddr_reg:x3; val_offset:12183*0 + 3*220*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 12183*0 + 3*221*FLEN/8, x4, x1, x2)

inst_4062:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x4032ba and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7fffe0 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7dc032ba; op2val:0x80000000;
op3val:0x807fffe0; valaddr_reg:x3; val_offset:12186*0 + 3*221*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 12186*0 + 3*222*FLEN/8, x4, x1, x2)

inst_4063:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x4032ba and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7ffff0 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7dc032ba; op2val:0x80000000;
op3val:0x807ffff0; valaddr_reg:x3; val_offset:12189*0 + 3*222*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 12189*0 + 3*223*FLEN/8, x4, x1, x2)

inst_4064:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x4032ba and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7ffff8 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7dc032ba; op2val:0x80000000;
op3val:0x807ffff8; valaddr_reg:x3; val_offset:12192*0 + 3*223*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 12192*0 + 3*224*FLEN/8, x4, x1, x2)

inst_4065:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x4032ba and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7ffffc and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7dc032ba; op2val:0x80000000;
op3val:0x807ffffc; valaddr_reg:x3; val_offset:12195*0 + 3*224*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 12195*0 + 3*225*FLEN/8, x4, x1, x2)

inst_4066:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x4032ba and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7ffffe and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7dc032ba; op2val:0x80000000;
op3val:0x807ffffe; valaddr_reg:x3; val_offset:12198*0 + 3*225*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 12198*0 + 3*226*FLEN/8, x4, x1, x2)

inst_4067:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x4032ba and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7fffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7dc032ba; op2val:0x80000000;
op3val:0x807fffff; valaddr_reg:x3; val_offset:12201*0 + 3*226*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 12201*0 + 3*227*FLEN/8, x4, x1, x2)

inst_4068:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x410cb0 and fs2 == 0 and fe2 == 0x02 and fm2 == 0x29bd20 and fs3 == 0 and fe3 == 0x7f and fm3 == 0x000001 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7dc10cb0; op2val:0x129bd20;
op3val:0x3f800001; valaddr_reg:x3; val_offset:12204*0 + 3*227*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 12204*0 + 3*228*FLEN/8, x4, x1, x2)

inst_4069:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x410cb0 and fs2 == 0 and fe2 == 0x02 and fm2 == 0x29bd20 and fs3 == 0 and fe3 == 0x7f and fm3 == 0x000003 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7dc10cb0; op2val:0x129bd20;
op3val:0x3f800003; valaddr_reg:x3; val_offset:12207*0 + 3*228*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 12207*0 + 3*229*FLEN/8, x4, x1, x2)

inst_4070:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x410cb0 and fs2 == 0 and fe2 == 0x02 and fm2 == 0x29bd20 and fs3 == 0 and fe3 == 0x7f and fm3 == 0x000007 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7dc10cb0; op2val:0x129bd20;
op3val:0x3f800007; valaddr_reg:x3; val_offset:12210*0 + 3*229*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 12210*0 + 3*230*FLEN/8, x4, x1, x2)

inst_4071:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x410cb0 and fs2 == 0 and fe2 == 0x02 and fm2 == 0x29bd20 and fs3 == 0 and fe3 == 0x7f and fm3 == 0x199999 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7dc10cb0; op2val:0x129bd20;
op3val:0x3f999999; valaddr_reg:x3; val_offset:12213*0 + 3*230*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 12213*0 + 3*231*FLEN/8, x4, x1, x2)

inst_4072:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x410cb0 and fs2 == 0 and fe2 == 0x02 and fm2 == 0x29bd20 and fs3 == 0 and fe3 == 0x7f and fm3 == 0x249249 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7dc10cb0; op2val:0x129bd20;
op3val:0x3fa49249; valaddr_reg:x3; val_offset:12216*0 + 3*231*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 12216*0 + 3*232*FLEN/8, x4, x1, x2)

inst_4073:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x410cb0 and fs2 == 0 and fe2 == 0x02 and fm2 == 0x29bd20 and fs3 == 0 and fe3 == 0x7f and fm3 == 0x333333 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7dc10cb0; op2val:0x129bd20;
op3val:0x3fb33333; valaddr_reg:x3; val_offset:12219*0 + 3*232*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 12219*0 + 3*233*FLEN/8, x4, x1, x2)

inst_4074:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x410cb0 and fs2 == 0 and fe2 == 0x02 and fm2 == 0x29bd20 and fs3 == 0 and fe3 == 0x7f and fm3 == 0x36db6d and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7dc10cb0; op2val:0x129bd20;
op3val:0x3fb6db6d; valaddr_reg:x3; val_offset:12222*0 + 3*233*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 12222*0 + 3*234*FLEN/8, x4, x1, x2)

inst_4075:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x410cb0 and fs2 == 0 and fe2 == 0x02 and fm2 == 0x29bd20 and fs3 == 0 and fe3 == 0x7f and fm3 == 0x3bbbbb and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7dc10cb0; op2val:0x129bd20;
op3val:0x3fbbbbbb; valaddr_reg:x3; val_offset:12225*0 + 3*234*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 12225*0 + 3*235*FLEN/8, x4, x1, x2)

inst_4076:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x410cb0 and fs2 == 0 and fe2 == 0x02 and fm2 == 0x29bd20 and fs3 == 0 and fe3 == 0x7f and fm3 == 0x444444 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7dc10cb0; op2val:0x129bd20;
op3val:0x3fc44444; valaddr_reg:x3; val_offset:12228*0 + 3*235*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 12228*0 + 3*236*FLEN/8, x4, x1, x2)

inst_4077:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x410cb0 and fs2 == 0 and fe2 == 0x02 and fm2 == 0x29bd20 and fs3 == 0 and fe3 == 0x7f and fm3 == 0x4ccccc and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7dc10cb0; op2val:0x129bd20;
op3val:0x3fcccccc; valaddr_reg:x3; val_offset:12231*0 + 3*236*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 12231*0 + 3*237*FLEN/8, x4, x1, x2)

inst_4078:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x410cb0 and fs2 == 0 and fe2 == 0x02 and fm2 == 0x29bd20 and fs3 == 0 and fe3 == 0x7f and fm3 == 0x5b6db6 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7dc10cb0; op2val:0x129bd20;
op3val:0x3fdb6db6; valaddr_reg:x3; val_offset:12234*0 + 3*237*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 12234*0 + 3*238*FLEN/8, x4, x1, x2)

inst_4079:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x410cb0 and fs2 == 0 and fe2 == 0x02 and fm2 == 0x29bd20 and fs3 == 0 and fe3 == 0x7f and fm3 == 0x666666 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7dc10cb0; op2val:0x129bd20;
op3val:0x3fe66666; valaddr_reg:x3; val_offset:12237*0 + 3*238*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 12237*0 + 3*239*FLEN/8, x4, x1, x2)

inst_4080:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x410cb0 and fs2 == 0 and fe2 == 0x02 and fm2 == 0x29bd20 and fs3 == 0 and fe3 == 0x7f and fm3 == 0x6db6db and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7dc10cb0; op2val:0x129bd20;
op3val:0x3fedb6db; valaddr_reg:x3; val_offset:12240*0 + 3*239*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 12240*0 + 3*240*FLEN/8, x4, x1, x2)

inst_4081:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x410cb0 and fs2 == 0 and fe2 == 0x02 and fm2 == 0x29bd20 and fs3 == 0 and fe3 == 0x7f and fm3 == 0x7ffff8 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7dc10cb0; op2val:0x129bd20;
op3val:0x3ffffff8; valaddr_reg:x3; val_offset:12243*0 + 3*240*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 12243*0 + 3*241*FLEN/8, x4, x1, x2)

inst_4082:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x410cb0 and fs2 == 0 and fe2 == 0x02 and fm2 == 0x29bd20 and fs3 == 0 and fe3 == 0x7f and fm3 == 0x7ffffc and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7dc10cb0; op2val:0x129bd20;
op3val:0x3ffffffc; valaddr_reg:x3; val_offset:12246*0 + 3*241*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 12246*0 + 3*242*FLEN/8, x4, x1, x2)

inst_4083:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x410cb0 and fs2 == 0 and fe2 == 0x02 and fm2 == 0x29bd20 and fs3 == 0 and fe3 == 0x7f and fm3 == 0x7ffffe and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7dc10cb0; op2val:0x129bd20;
op3val:0x3ffffffe; valaddr_reg:x3; val_offset:12249*0 + 3*242*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 12249*0 + 3*243*FLEN/8, x4, x1, x2)

inst_4084:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x410cb0 and fs2 == 0 and fe2 == 0x02 and fm2 == 0x29bd20 and fs3 == 0 and fe3 == 0x9d and fm3 == 0x000000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7dc10cb0; op2val:0x129bd20;
op3val:0x4e800000; valaddr_reg:x3; val_offset:12252*0 + 3*243*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 12252*0 + 3*244*FLEN/8, x4, x1, x2)

inst_4085:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x410cb0 and fs2 == 0 and fe2 == 0x02 and fm2 == 0x29bd20 and fs3 == 0 and fe3 == 0x9d and fm3 == 0x000001 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7dc10cb0; op2val:0x129bd20;
op3val:0x4e800001; valaddr_reg:x3; val_offset:12255*0 + 3*244*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 12255*0 + 3*245*FLEN/8, x4, x1, x2)

inst_4086:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x410cb0 and fs2 == 0 and fe2 == 0x02 and fm2 == 0x29bd20 and fs3 == 0 and fe3 == 0x9d and fm3 == 0x000003 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7dc10cb0; op2val:0x129bd20;
op3val:0x4e800003; valaddr_reg:x3; val_offset:12258*0 + 3*245*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 12258*0 + 3*246*FLEN/8, x4, x1, x2)

inst_4087:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x410cb0 and fs2 == 0 and fe2 == 0x02 and fm2 == 0x29bd20 and fs3 == 0 and fe3 == 0x9d and fm3 == 0x000007 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7dc10cb0; op2val:0x129bd20;
op3val:0x4e800007; valaddr_reg:x3; val_offset:12261*0 + 3*246*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 12261*0 + 3*247*FLEN/8, x4, x1, x2)

inst_4088:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x410cb0 and fs2 == 0 and fe2 == 0x02 and fm2 == 0x29bd20 and fs3 == 0 and fe3 == 0x9d and fm3 == 0x00000f and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7dc10cb0; op2val:0x129bd20;
op3val:0x4e80000f; valaddr_reg:x3; val_offset:12264*0 + 3*247*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 12264*0 + 3*248*FLEN/8, x4, x1, x2)

inst_4089:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x410cb0 and fs2 == 0 and fe2 == 0x02 and fm2 == 0x29bd20 and fs3 == 0 and fe3 == 0x9d and fm3 == 0x00001f and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7dc10cb0; op2val:0x129bd20;
op3val:0x4e80001f; valaddr_reg:x3; val_offset:12267*0 + 3*248*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 12267*0 + 3*249*FLEN/8, x4, x1, x2)

inst_4090:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x410cb0 and fs2 == 0 and fe2 == 0x02 and fm2 == 0x29bd20 and fs3 == 0 and fe3 == 0x9d and fm3 == 0x00003f and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7dc10cb0; op2val:0x129bd20;
op3val:0x4e80003f; valaddr_reg:x3; val_offset:12270*0 + 3*249*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 12270*0 + 3*250*FLEN/8, x4, x1, x2)

inst_4091:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x410cb0 and fs2 == 0 and fe2 == 0x02 and fm2 == 0x29bd20 and fs3 == 0 and fe3 == 0x9d and fm3 == 0x00007f and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7dc10cb0; op2val:0x129bd20;
op3val:0x4e80007f; valaddr_reg:x3; val_offset:12273*0 + 3*250*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 12273*0 + 3*251*FLEN/8, x4, x1, x2)

inst_4092:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x410cb0 and fs2 == 0 and fe2 == 0x02 and fm2 == 0x29bd20 and fs3 == 0 and fe3 == 0x9d and fm3 == 0x0000ff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7dc10cb0; op2val:0x129bd20;
op3val:0x4e8000ff; valaddr_reg:x3; val_offset:12276*0 + 3*251*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 12276*0 + 3*252*FLEN/8, x4, x1, x2)

inst_4093:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x410cb0 and fs2 == 0 and fe2 == 0x02 and fm2 == 0x29bd20 and fs3 == 0 and fe3 == 0x9d and fm3 == 0x0001ff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7dc10cb0; op2val:0x129bd20;
op3val:0x4e8001ff; valaddr_reg:x3; val_offset:12279*0 + 3*252*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 12279*0 + 3*253*FLEN/8, x4, x1, x2)

inst_4094:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x410cb0 and fs2 == 0 and fe2 == 0x02 and fm2 == 0x29bd20 and fs3 == 0 and fe3 == 0x9d and fm3 == 0x0003ff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7dc10cb0; op2val:0x129bd20;
op3val:0x4e8003ff; valaddr_reg:x3; val_offset:12282*0 + 3*253*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 12282*0 + 3*254*FLEN/8, x4, x1, x2)

inst_4095:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x410cb0 and fs2 == 0 and fe2 == 0x02 and fm2 == 0x29bd20 and fs3 == 0 and fe3 == 0x9d and fm3 == 0x0007ff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7dc10cb0; op2val:0x129bd20;
op3val:0x4e8007ff; valaddr_reg:x3; val_offset:12285*0 + 3*254*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 12285*0 + 3*255*FLEN/8, x4, x1, x2)
RVTEST_SIGBASE(x1,signature_x1_3)

inst_4096:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x410cb0 and fs2 == 0 and fe2 == 0x02 and fm2 == 0x29bd20 and fs3 == 0 and fe3 == 0x9d and fm3 == 0x000fff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7dc10cb0; op2val:0x129bd20;
op3val:0x4e800fff; valaddr_reg:x3; val_offset:12288*0 + 3*256*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 12288*0 + 3*256*FLEN/8, x4, x1, x2)

inst_4097:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x410cb0 and fs2 == 0 and fe2 == 0x02 and fm2 == 0x29bd20 and fs3 == 0 and fe3 == 0x9d and fm3 == 0x001fff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7dc10cb0; op2val:0x129bd20;
op3val:0x4e801fff; valaddr_reg:x3; val_offset:12291*0 + 3*257*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 12291*0 + 3*257*FLEN/8, x4, x1, x2)

inst_4098:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x410cb0 and fs2 == 0 and fe2 == 0x02 and fm2 == 0x29bd20 and fs3 == 0 and fe3 == 0x9d and fm3 == 0x003fff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7dc10cb0; op2val:0x129bd20;
op3val:0x4e803fff; valaddr_reg:x3; val_offset:12294*0 + 3*258*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 12294*0 + 3*258*FLEN/8, x4, x1, x2)

inst_4099:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x410cb0 and fs2 == 0 and fe2 == 0x02 and fm2 == 0x29bd20 and fs3 == 0 and fe3 == 0x9d and fm3 == 0x007fff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7dc10cb0; op2val:0x129bd20;
op3val:0x4e807fff; valaddr_reg:x3; val_offset:12297*0 + 3*259*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 12297*0 + 3*259*FLEN/8, x4, x1, x2)

inst_4100:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x410cb0 and fs2 == 0 and fe2 == 0x02 and fm2 == 0x29bd20 and fs3 == 0 and fe3 == 0x9d and fm3 == 0x00ffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7dc10cb0; op2val:0x129bd20;
op3val:0x4e80ffff; valaddr_reg:x3; val_offset:12300*0 + 3*260*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 12300*0 + 3*260*FLEN/8, x4, x1, x2)

inst_4101:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x410cb0 and fs2 == 0 and fe2 == 0x02 and fm2 == 0x29bd20 and fs3 == 0 and fe3 == 0x9d and fm3 == 0x01ffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7dc10cb0; op2val:0x129bd20;
op3val:0x4e81ffff; valaddr_reg:x3; val_offset:12303*0 + 3*261*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 12303*0 + 3*261*FLEN/8, x4, x1, x2)

inst_4102:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x410cb0 and fs2 == 0 and fe2 == 0x02 and fm2 == 0x29bd20 and fs3 == 0 and fe3 == 0x9d and fm3 == 0x03ffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7dc10cb0; op2val:0x129bd20;
op3val:0x4e83ffff; valaddr_reg:x3; val_offset:12306*0 + 3*262*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 12306*0 + 3*262*FLEN/8, x4, x1, x2)

inst_4103:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x410cb0 and fs2 == 0 and fe2 == 0x02 and fm2 == 0x29bd20 and fs3 == 0 and fe3 == 0x9d and fm3 == 0x07ffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7dc10cb0; op2val:0x129bd20;
op3val:0x4e87ffff; valaddr_reg:x3; val_offset:12309*0 + 3*263*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 12309*0 + 3*263*FLEN/8, x4, x1, x2)

inst_4104:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x410cb0 and fs2 == 0 and fe2 == 0x02 and fm2 == 0x29bd20 and fs3 == 0 and fe3 == 0x9d and fm3 == 0x0fffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7dc10cb0; op2val:0x129bd20;
op3val:0x4e8fffff; valaddr_reg:x3; val_offset:12312*0 + 3*264*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 12312*0 + 3*264*FLEN/8, x4, x1, x2)

inst_4105:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x410cb0 and fs2 == 0 and fe2 == 0x02 and fm2 == 0x29bd20 and fs3 == 0 and fe3 == 0x9d and fm3 == 0x1fffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7dc10cb0; op2val:0x129bd20;
op3val:0x4e9fffff; valaddr_reg:x3; val_offset:12315*0 + 3*265*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 12315*0 + 3*265*FLEN/8, x4, x1, x2)

inst_4106:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x410cb0 and fs2 == 0 and fe2 == 0x02 and fm2 == 0x29bd20 and fs3 == 0 and fe3 == 0x9d and fm3 == 0x3fffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7dc10cb0; op2val:0x129bd20;
op3val:0x4ebfffff; valaddr_reg:x3; val_offset:12318*0 + 3*266*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 12318*0 + 3*266*FLEN/8, x4, x1, x2)

inst_4107:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x410cb0 and fs2 == 0 and fe2 == 0x02 and fm2 == 0x29bd20 and fs3 == 0 and fe3 == 0x9d and fm3 == 0x400000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7dc10cb0; op2val:0x129bd20;
op3val:0x4ec00000; valaddr_reg:x3; val_offset:12321*0 + 3*267*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 12321*0 + 3*267*FLEN/8, x4, x1, x2)

inst_4108:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x410cb0 and fs2 == 0 and fe2 == 0x02 and fm2 == 0x29bd20 and fs3 == 0 and fe3 == 0x9d and fm3 == 0x600000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7dc10cb0; op2val:0x129bd20;
op3val:0x4ee00000; valaddr_reg:x3; val_offset:12324*0 + 3*268*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 12324*0 + 3*268*FLEN/8, x4, x1, x2)

inst_4109:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x410cb0 and fs2 == 0 and fe2 == 0x02 and fm2 == 0x29bd20 and fs3 == 0 and fe3 == 0x9d and fm3 == 0x700000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7dc10cb0; op2val:0x129bd20;
op3val:0x4ef00000; valaddr_reg:x3; val_offset:12327*0 + 3*269*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 12327*0 + 3*269*FLEN/8, x4, x1, x2)

inst_4110:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x410cb0 and fs2 == 0 and fe2 == 0x02 and fm2 == 0x29bd20 and fs3 == 0 and fe3 == 0x9d and fm3 == 0x780000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7dc10cb0; op2val:0x129bd20;
op3val:0x4ef80000; valaddr_reg:x3; val_offset:12330*0 + 3*270*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 12330*0 + 3*270*FLEN/8, x4, x1, x2)

inst_4111:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x410cb0 and fs2 == 0 and fe2 == 0x02 and fm2 == 0x29bd20 and fs3 == 0 and fe3 == 0x9d and fm3 == 0x7c0000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7dc10cb0; op2val:0x129bd20;
op3val:0x4efc0000; valaddr_reg:x3; val_offset:12333*0 + 3*271*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 12333*0 + 3*271*FLEN/8, x4, x1, x2)

inst_4112:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x410cb0 and fs2 == 0 and fe2 == 0x02 and fm2 == 0x29bd20 and fs3 == 0 and fe3 == 0x9d and fm3 == 0x7e0000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7dc10cb0; op2val:0x129bd20;
op3val:0x4efe0000; valaddr_reg:x3; val_offset:12336*0 + 3*272*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 12336*0 + 3*272*FLEN/8, x4, x1, x2)

inst_4113:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x410cb0 and fs2 == 0 and fe2 == 0x02 and fm2 == 0x29bd20 and fs3 == 0 and fe3 == 0x9d and fm3 == 0x7f0000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7dc10cb0; op2val:0x129bd20;
op3val:0x4eff0000; valaddr_reg:x3; val_offset:12339*0 + 3*273*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 12339*0 + 3*273*FLEN/8, x4, x1, x2)

inst_4114:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x410cb0 and fs2 == 0 and fe2 == 0x02 and fm2 == 0x29bd20 and fs3 == 0 and fe3 == 0x9d and fm3 == 0x7f8000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7dc10cb0; op2val:0x129bd20;
op3val:0x4eff8000; valaddr_reg:x3; val_offset:12342*0 + 3*274*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 12342*0 + 3*274*FLEN/8, x4, x1, x2)

inst_4115:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x410cb0 and fs2 == 0 and fe2 == 0x02 and fm2 == 0x29bd20 and fs3 == 0 and fe3 == 0x9d and fm3 == 0x7fc000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7dc10cb0; op2val:0x129bd20;
op3val:0x4effc000; valaddr_reg:x3; val_offset:12345*0 + 3*275*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 12345*0 + 3*275*FLEN/8, x4, x1, x2)

inst_4116:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x410cb0 and fs2 == 0 and fe2 == 0x02 and fm2 == 0x29bd20 and fs3 == 0 and fe3 == 0x9d and fm3 == 0x7fe000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7dc10cb0; op2val:0x129bd20;
op3val:0x4effe000; valaddr_reg:x3; val_offset:12348*0 + 3*276*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 12348*0 + 3*276*FLEN/8, x4, x1, x2)

inst_4117:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x410cb0 and fs2 == 0 and fe2 == 0x02 and fm2 == 0x29bd20 and fs3 == 0 and fe3 == 0x9d and fm3 == 0x7ff000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7dc10cb0; op2val:0x129bd20;
op3val:0x4efff000; valaddr_reg:x3; val_offset:12351*0 + 3*277*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 12351*0 + 3*277*FLEN/8, x4, x1, x2)

inst_4118:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x410cb0 and fs2 == 0 and fe2 == 0x02 and fm2 == 0x29bd20 and fs3 == 0 and fe3 == 0x9d and fm3 == 0x7ff800 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7dc10cb0; op2val:0x129bd20;
op3val:0x4efff800; valaddr_reg:x3; val_offset:12354*0 + 3*278*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 12354*0 + 3*278*FLEN/8, x4, x1, x2)

inst_4119:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x410cb0 and fs2 == 0 and fe2 == 0x02 and fm2 == 0x29bd20 and fs3 == 0 and fe3 == 0x9d and fm3 == 0x7ffc00 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7dc10cb0; op2val:0x129bd20;
op3val:0x4efffc00; valaddr_reg:x3; val_offset:12357*0 + 3*279*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 12357*0 + 3*279*FLEN/8, x4, x1, x2)

inst_4120:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x410cb0 and fs2 == 0 and fe2 == 0x02 and fm2 == 0x29bd20 and fs3 == 0 and fe3 == 0x9d and fm3 == 0x7ffe00 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7dc10cb0; op2val:0x129bd20;
op3val:0x4efffe00; valaddr_reg:x3; val_offset:12360*0 + 3*280*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 12360*0 + 3*280*FLEN/8, x4, x1, x2)

inst_4121:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x410cb0 and fs2 == 0 and fe2 == 0x02 and fm2 == 0x29bd20 and fs3 == 0 and fe3 == 0x9d and fm3 == 0x7fff00 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7dc10cb0; op2val:0x129bd20;
op3val:0x4effff00; valaddr_reg:x3; val_offset:12363*0 + 3*281*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 12363*0 + 3*281*FLEN/8, x4, x1, x2)

inst_4122:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x410cb0 and fs2 == 0 and fe2 == 0x02 and fm2 == 0x29bd20 and fs3 == 0 and fe3 == 0x9d and fm3 == 0x7fff80 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7dc10cb0; op2val:0x129bd20;
op3val:0x4effff80; valaddr_reg:x3; val_offset:12366*0 + 3*282*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 12366*0 + 3*282*FLEN/8, x4, x1, x2)

inst_4123:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x410cb0 and fs2 == 0 and fe2 == 0x02 and fm2 == 0x29bd20 and fs3 == 0 and fe3 == 0x9d and fm3 == 0x7fffc0 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7dc10cb0; op2val:0x129bd20;
op3val:0x4effffc0; valaddr_reg:x3; val_offset:12369*0 + 3*283*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 12369*0 + 3*283*FLEN/8, x4, x1, x2)

inst_4124:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x410cb0 and fs2 == 0 and fe2 == 0x02 and fm2 == 0x29bd20 and fs3 == 0 and fe3 == 0x9d and fm3 == 0x7fffe0 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7dc10cb0; op2val:0x129bd20;
op3val:0x4effffe0; valaddr_reg:x3; val_offset:12372*0 + 3*284*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 12372*0 + 3*284*FLEN/8, x4, x1, x2)

inst_4125:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x410cb0 and fs2 == 0 and fe2 == 0x02 and fm2 == 0x29bd20 and fs3 == 0 and fe3 == 0x9d and fm3 == 0x7ffff0 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7dc10cb0; op2val:0x129bd20;
op3val:0x4efffff0; valaddr_reg:x3; val_offset:12375*0 + 3*285*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 12375*0 + 3*285*FLEN/8, x4, x1, x2)

inst_4126:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x410cb0 and fs2 == 0 and fe2 == 0x02 and fm2 == 0x29bd20 and fs3 == 0 and fe3 == 0x9d and fm3 == 0x7ffff8 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7dc10cb0; op2val:0x129bd20;
op3val:0x4efffff8; valaddr_reg:x3; val_offset:12378*0 + 3*286*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 12378*0 + 3*286*FLEN/8, x4, x1, x2)

inst_4127:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x410cb0 and fs2 == 0 and fe2 == 0x02 and fm2 == 0x29bd20 and fs3 == 0 and fe3 == 0x9d and fm3 == 0x7ffffc and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7dc10cb0; op2val:0x129bd20;
op3val:0x4efffffc; valaddr_reg:x3; val_offset:12381*0 + 3*287*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 12381*0 + 3*287*FLEN/8, x4, x1, x2)

inst_4128:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x410cb0 and fs2 == 0 and fe2 == 0x02 and fm2 == 0x29bd20 and fs3 == 0 and fe3 == 0x9d and fm3 == 0x7ffffe and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7dc10cb0; op2val:0x129bd20;
op3val:0x4efffffe; valaddr_reg:x3; val_offset:12384*0 + 3*288*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 12384*0 + 3*288*FLEN/8, x4, x1, x2)

inst_4129:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x410cb0 and fs2 == 0 and fe2 == 0x02 and fm2 == 0x29bd20 and fs3 == 0 and fe3 == 0x9d and fm3 == 0x7fffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7dc10cb0; op2val:0x129bd20;
op3val:0x4effffff; valaddr_reg:x3; val_offset:12387*0 + 3*289*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 12387*0 + 3*289*FLEN/8, x4, x1, x2)

inst_4130:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x4686f0 and fs2 == 0 and fe2 == 0x02 and fm2 == 0x250e37 and fs3 == 0 and fe3 == 0x54 and fm3 == 0x000000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7dc686f0; op2val:0x1250e37;
op3val:0x2a000000; valaddr_reg:x3; val_offset:12390*0 + 3*290*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 12390*0 + 3*290*FLEN/8, x4, x1, x2)

inst_4131:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x4686f0 and fs2 == 0 and fe2 == 0x02 and fm2 == 0x250e37 and fs3 == 0 and fe3 == 0x54 and fm3 == 0x000001 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7dc686f0; op2val:0x1250e37;
op3val:0x2a000001; valaddr_reg:x3; val_offset:12393*0 + 3*291*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 12393*0 + 3*291*FLEN/8, x4, x1, x2)

inst_4132:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x4686f0 and fs2 == 0 and fe2 == 0x02 and fm2 == 0x250e37 and fs3 == 0 and fe3 == 0x54 and fm3 == 0x000003 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7dc686f0; op2val:0x1250e37;
op3val:0x2a000003; valaddr_reg:x3; val_offset:12396*0 + 3*292*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 12396*0 + 3*292*FLEN/8, x4, x1, x2)

inst_4133:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x4686f0 and fs2 == 0 and fe2 == 0x02 and fm2 == 0x250e37 and fs3 == 0 and fe3 == 0x54 and fm3 == 0x000007 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7dc686f0; op2val:0x1250e37;
op3val:0x2a000007; valaddr_reg:x3; val_offset:12399*0 + 3*293*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 12399*0 + 3*293*FLEN/8, x4, x1, x2)

inst_4134:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x4686f0 and fs2 == 0 and fe2 == 0x02 and fm2 == 0x250e37 and fs3 == 0 and fe3 == 0x54 and fm3 == 0x00000f and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7dc686f0; op2val:0x1250e37;
op3val:0x2a00000f; valaddr_reg:x3; val_offset:12402*0 + 3*294*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 12402*0 + 3*294*FLEN/8, x4, x1, x2)

inst_4135:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x4686f0 and fs2 == 0 and fe2 == 0x02 and fm2 == 0x250e37 and fs3 == 0 and fe3 == 0x54 and fm3 == 0x00001f and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7dc686f0; op2val:0x1250e37;
op3val:0x2a00001f; valaddr_reg:x3; val_offset:12405*0 + 3*295*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 12405*0 + 3*295*FLEN/8, x4, x1, x2)

inst_4136:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x4686f0 and fs2 == 0 and fe2 == 0x02 and fm2 == 0x250e37 and fs3 == 0 and fe3 == 0x54 and fm3 == 0x00003f and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7dc686f0; op2val:0x1250e37;
op3val:0x2a00003f; valaddr_reg:x3; val_offset:12408*0 + 3*296*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 12408*0 + 3*296*FLEN/8, x4, x1, x2)

inst_4137:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x4686f0 and fs2 == 0 and fe2 == 0x02 and fm2 == 0x250e37 and fs3 == 0 and fe3 == 0x54 and fm3 == 0x00007f and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7dc686f0; op2val:0x1250e37;
op3val:0x2a00007f; valaddr_reg:x3; val_offset:12411*0 + 3*297*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 12411*0 + 3*297*FLEN/8, x4, x1, x2)

inst_4138:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x4686f0 and fs2 == 0 and fe2 == 0x02 and fm2 == 0x250e37 and fs3 == 0 and fe3 == 0x54 and fm3 == 0x0000ff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7dc686f0; op2val:0x1250e37;
op3val:0x2a0000ff; valaddr_reg:x3; val_offset:12414*0 + 3*298*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 12414*0 + 3*298*FLEN/8, x4, x1, x2)

inst_4139:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x4686f0 and fs2 == 0 and fe2 == 0x02 and fm2 == 0x250e37 and fs3 == 0 and fe3 == 0x54 and fm3 == 0x0001ff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7dc686f0; op2val:0x1250e37;
op3val:0x2a0001ff; valaddr_reg:x3; val_offset:12417*0 + 3*299*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 12417*0 + 3*299*FLEN/8, x4, x1, x2)

inst_4140:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x4686f0 and fs2 == 0 and fe2 == 0x02 and fm2 == 0x250e37 and fs3 == 0 and fe3 == 0x54 and fm3 == 0x0003ff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7dc686f0; op2val:0x1250e37;
op3val:0x2a0003ff; valaddr_reg:x3; val_offset:12420*0 + 3*300*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 12420*0 + 3*300*FLEN/8, x4, x1, x2)

inst_4141:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x4686f0 and fs2 == 0 and fe2 == 0x02 and fm2 == 0x250e37 and fs3 == 0 and fe3 == 0x54 and fm3 == 0x0007ff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7dc686f0; op2val:0x1250e37;
op3val:0x2a0007ff; valaddr_reg:x3; val_offset:12423*0 + 3*301*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 12423*0 + 3*301*FLEN/8, x4, x1, x2)

inst_4142:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x4686f0 and fs2 == 0 and fe2 == 0x02 and fm2 == 0x250e37 and fs3 == 0 and fe3 == 0x54 and fm3 == 0x000fff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7dc686f0; op2val:0x1250e37;
op3val:0x2a000fff; valaddr_reg:x3; val_offset:12426*0 + 3*302*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 12426*0 + 3*302*FLEN/8, x4, x1, x2)

inst_4143:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x4686f0 and fs2 == 0 and fe2 == 0x02 and fm2 == 0x250e37 and fs3 == 0 and fe3 == 0x54 and fm3 == 0x001fff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7dc686f0; op2val:0x1250e37;
op3val:0x2a001fff; valaddr_reg:x3; val_offset:12429*0 + 3*303*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 12429*0 + 3*303*FLEN/8, x4, x1, x2)

inst_4144:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x4686f0 and fs2 == 0 and fe2 == 0x02 and fm2 == 0x250e37 and fs3 == 0 and fe3 == 0x54 and fm3 == 0x003fff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7dc686f0; op2val:0x1250e37;
op3val:0x2a003fff; valaddr_reg:x3; val_offset:12432*0 + 3*304*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 12432*0 + 3*304*FLEN/8, x4, x1, x2)

inst_4145:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x4686f0 and fs2 == 0 and fe2 == 0x02 and fm2 == 0x250e37 and fs3 == 0 and fe3 == 0x54 and fm3 == 0x007fff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7dc686f0; op2val:0x1250e37;
op3val:0x2a007fff; valaddr_reg:x3; val_offset:12435*0 + 3*305*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 12435*0 + 3*305*FLEN/8, x4, x1, x2)

inst_4146:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x4686f0 and fs2 == 0 and fe2 == 0x02 and fm2 == 0x250e37 and fs3 == 0 and fe3 == 0x54 and fm3 == 0x00ffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7dc686f0; op2val:0x1250e37;
op3val:0x2a00ffff; valaddr_reg:x3; val_offset:12438*0 + 3*306*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 12438*0 + 3*306*FLEN/8, x4, x1, x2)

inst_4147:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x4686f0 and fs2 == 0 and fe2 == 0x02 and fm2 == 0x250e37 and fs3 == 0 and fe3 == 0x54 and fm3 == 0x01ffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7dc686f0; op2val:0x1250e37;
op3val:0x2a01ffff; valaddr_reg:x3; val_offset:12441*0 + 3*307*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 12441*0 + 3*307*FLEN/8, x4, x1, x2)

inst_4148:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x4686f0 and fs2 == 0 and fe2 == 0x02 and fm2 == 0x250e37 and fs3 == 0 and fe3 == 0x54 and fm3 == 0x03ffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7dc686f0; op2val:0x1250e37;
op3val:0x2a03ffff; valaddr_reg:x3; val_offset:12444*0 + 3*308*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 12444*0 + 3*308*FLEN/8, x4, x1, x2)

inst_4149:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x4686f0 and fs2 == 0 and fe2 == 0x02 and fm2 == 0x250e37 and fs3 == 0 and fe3 == 0x54 and fm3 == 0x07ffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7dc686f0; op2val:0x1250e37;
op3val:0x2a07ffff; valaddr_reg:x3; val_offset:12447*0 + 3*309*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 12447*0 + 3*309*FLEN/8, x4, x1, x2)

inst_4150:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x4686f0 and fs2 == 0 and fe2 == 0x02 and fm2 == 0x250e37 and fs3 == 0 and fe3 == 0x54 and fm3 == 0x0fffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7dc686f0; op2val:0x1250e37;
op3val:0x2a0fffff; valaddr_reg:x3; val_offset:12450*0 + 3*310*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 12450*0 + 3*310*FLEN/8, x4, x1, x2)

inst_4151:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x4686f0 and fs2 == 0 and fe2 == 0x02 and fm2 == 0x250e37 and fs3 == 0 and fe3 == 0x54 and fm3 == 0x1fffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7dc686f0; op2val:0x1250e37;
op3val:0x2a1fffff; valaddr_reg:x3; val_offset:12453*0 + 3*311*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 12453*0 + 3*311*FLEN/8, x4, x1, x2)

inst_4152:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x4686f0 and fs2 == 0 and fe2 == 0x02 and fm2 == 0x250e37 and fs3 == 0 and fe3 == 0x54 and fm3 == 0x3fffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7dc686f0; op2val:0x1250e37;
op3val:0x2a3fffff; valaddr_reg:x3; val_offset:12456*0 + 3*312*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 12456*0 + 3*312*FLEN/8, x4, x1, x2)

inst_4153:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x4686f0 and fs2 == 0 and fe2 == 0x02 and fm2 == 0x250e37 and fs3 == 0 and fe3 == 0x54 and fm3 == 0x400000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7dc686f0; op2val:0x1250e37;
op3val:0x2a400000; valaddr_reg:x3; val_offset:12459*0 + 3*313*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 12459*0 + 3*313*FLEN/8, x4, x1, x2)

inst_4154:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x4686f0 and fs2 == 0 and fe2 == 0x02 and fm2 == 0x250e37 and fs3 == 0 and fe3 == 0x54 and fm3 == 0x600000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7dc686f0; op2val:0x1250e37;
op3val:0x2a600000; valaddr_reg:x3; val_offset:12462*0 + 3*314*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 12462*0 + 3*314*FLEN/8, x4, x1, x2)

inst_4155:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x4686f0 and fs2 == 0 and fe2 == 0x02 and fm2 == 0x250e37 and fs3 == 0 and fe3 == 0x54 and fm3 == 0x700000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7dc686f0; op2val:0x1250e37;
op3val:0x2a700000; valaddr_reg:x3; val_offset:12465*0 + 3*315*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 12465*0 + 3*315*FLEN/8, x4, x1, x2)

inst_4156:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x4686f0 and fs2 == 0 and fe2 == 0x02 and fm2 == 0x250e37 and fs3 == 0 and fe3 == 0x54 and fm3 == 0x780000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7dc686f0; op2val:0x1250e37;
op3val:0x2a780000; valaddr_reg:x3; val_offset:12468*0 + 3*316*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 12468*0 + 3*316*FLEN/8, x4, x1, x2)

inst_4157:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x4686f0 and fs2 == 0 and fe2 == 0x02 and fm2 == 0x250e37 and fs3 == 0 and fe3 == 0x54 and fm3 == 0x7c0000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7dc686f0; op2val:0x1250e37;
op3val:0x2a7c0000; valaddr_reg:x3; val_offset:12471*0 + 3*317*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 12471*0 + 3*317*FLEN/8, x4, x1, x2)

inst_4158:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x4686f0 and fs2 == 0 and fe2 == 0x02 and fm2 == 0x250e37 and fs3 == 0 and fe3 == 0x54 and fm3 == 0x7e0000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7dc686f0; op2val:0x1250e37;
op3val:0x2a7e0000; valaddr_reg:x3; val_offset:12474*0 + 3*318*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 12474*0 + 3*318*FLEN/8, x4, x1, x2)

inst_4159:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x4686f0 and fs2 == 0 and fe2 == 0x02 and fm2 == 0x250e37 and fs3 == 0 and fe3 == 0x54 and fm3 == 0x7f0000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7dc686f0; op2val:0x1250e37;
op3val:0x2a7f0000; valaddr_reg:x3; val_offset:12477*0 + 3*319*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 12477*0 + 3*319*FLEN/8, x4, x1, x2)

inst_4160:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x4686f0 and fs2 == 0 and fe2 == 0x02 and fm2 == 0x250e37 and fs3 == 0 and fe3 == 0x54 and fm3 == 0x7f8000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7dc686f0; op2val:0x1250e37;
op3val:0x2a7f8000; valaddr_reg:x3; val_offset:12480*0 + 3*320*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 12480*0 + 3*320*FLEN/8, x4, x1, x2)

inst_4161:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x4686f0 and fs2 == 0 and fe2 == 0x02 and fm2 == 0x250e37 and fs3 == 0 and fe3 == 0x54 and fm3 == 0x7fc000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7dc686f0; op2val:0x1250e37;
op3val:0x2a7fc000; valaddr_reg:x3; val_offset:12483*0 + 3*321*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 12483*0 + 3*321*FLEN/8, x4, x1, x2)

inst_4162:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x4686f0 and fs2 == 0 and fe2 == 0x02 and fm2 == 0x250e37 and fs3 == 0 and fe3 == 0x54 and fm3 == 0x7fe000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7dc686f0; op2val:0x1250e37;
op3val:0x2a7fe000; valaddr_reg:x3; val_offset:12486*0 + 3*322*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 12486*0 + 3*322*FLEN/8, x4, x1, x2)

inst_4163:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x4686f0 and fs2 == 0 and fe2 == 0x02 and fm2 == 0x250e37 and fs3 == 0 and fe3 == 0x54 and fm3 == 0x7ff000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7dc686f0; op2val:0x1250e37;
op3val:0x2a7ff000; valaddr_reg:x3; val_offset:12489*0 + 3*323*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 12489*0 + 3*323*FLEN/8, x4, x1, x2)

inst_4164:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x4686f0 and fs2 == 0 and fe2 == 0x02 and fm2 == 0x250e37 and fs3 == 0 and fe3 == 0x54 and fm3 == 0x7ff800 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7dc686f0; op2val:0x1250e37;
op3val:0x2a7ff800; valaddr_reg:x3; val_offset:12492*0 + 3*324*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 12492*0 + 3*324*FLEN/8, x4, x1, x2)

inst_4165:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x4686f0 and fs2 == 0 and fe2 == 0x02 and fm2 == 0x250e37 and fs3 == 0 and fe3 == 0x54 and fm3 == 0x7ffc00 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7dc686f0; op2val:0x1250e37;
op3val:0x2a7ffc00; valaddr_reg:x3; val_offset:12495*0 + 3*325*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 12495*0 + 3*325*FLEN/8, x4, x1, x2)

inst_4166:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x4686f0 and fs2 == 0 and fe2 == 0x02 and fm2 == 0x250e37 and fs3 == 0 and fe3 == 0x54 and fm3 == 0x7ffe00 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7dc686f0; op2val:0x1250e37;
op3val:0x2a7ffe00; valaddr_reg:x3; val_offset:12498*0 + 3*326*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 12498*0 + 3*326*FLEN/8, x4, x1, x2)

inst_4167:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x4686f0 and fs2 == 0 and fe2 == 0x02 and fm2 == 0x250e37 and fs3 == 0 and fe3 == 0x54 and fm3 == 0x7fff00 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7dc686f0; op2val:0x1250e37;
op3val:0x2a7fff00; valaddr_reg:x3; val_offset:12501*0 + 3*327*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 12501*0 + 3*327*FLEN/8, x4, x1, x2)

inst_4168:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x4686f0 and fs2 == 0 and fe2 == 0x02 and fm2 == 0x250e37 and fs3 == 0 and fe3 == 0x54 and fm3 == 0x7fff80 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7dc686f0; op2val:0x1250e37;
op3val:0x2a7fff80; valaddr_reg:x3; val_offset:12504*0 + 3*328*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 12504*0 + 3*328*FLEN/8, x4, x1, x2)

inst_4169:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x4686f0 and fs2 == 0 and fe2 == 0x02 and fm2 == 0x250e37 and fs3 == 0 and fe3 == 0x54 and fm3 == 0x7fffc0 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7dc686f0; op2val:0x1250e37;
op3val:0x2a7fffc0; valaddr_reg:x3; val_offset:12507*0 + 3*329*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 12507*0 + 3*329*FLEN/8, x4, x1, x2)

inst_4170:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x4686f0 and fs2 == 0 and fe2 == 0x02 and fm2 == 0x250e37 and fs3 == 0 and fe3 == 0x54 and fm3 == 0x7fffe0 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7dc686f0; op2val:0x1250e37;
op3val:0x2a7fffe0; valaddr_reg:x3; val_offset:12510*0 + 3*330*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 12510*0 + 3*330*FLEN/8, x4, x1, x2)

inst_4171:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x4686f0 and fs2 == 0 and fe2 == 0x02 and fm2 == 0x250e37 and fs3 == 0 and fe3 == 0x54 and fm3 == 0x7ffff0 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7dc686f0; op2val:0x1250e37;
op3val:0x2a7ffff0; valaddr_reg:x3; val_offset:12513*0 + 3*331*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 12513*0 + 3*331*FLEN/8, x4, x1, x2)

inst_4172:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x4686f0 and fs2 == 0 and fe2 == 0x02 and fm2 == 0x250e37 and fs3 == 0 and fe3 == 0x54 and fm3 == 0x7ffff8 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7dc686f0; op2val:0x1250e37;
op3val:0x2a7ffff8; valaddr_reg:x3; val_offset:12516*0 + 3*332*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 12516*0 + 3*332*FLEN/8, x4, x1, x2)

inst_4173:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x4686f0 and fs2 == 0 and fe2 == 0x02 and fm2 == 0x250e37 and fs3 == 0 and fe3 == 0x54 and fm3 == 0x7ffffc and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7dc686f0; op2val:0x1250e37;
op3val:0x2a7ffffc; valaddr_reg:x3; val_offset:12519*0 + 3*333*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 12519*0 + 3*333*FLEN/8, x4, x1, x2)

inst_4174:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x4686f0 and fs2 == 0 and fe2 == 0x02 and fm2 == 0x250e37 and fs3 == 0 and fe3 == 0x54 and fm3 == 0x7ffffe and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7dc686f0; op2val:0x1250e37;
op3val:0x2a7ffffe; valaddr_reg:x3; val_offset:12522*0 + 3*334*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 12522*0 + 3*334*FLEN/8, x4, x1, x2)

inst_4175:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x4686f0 and fs2 == 0 and fe2 == 0x02 and fm2 == 0x250e37 and fs3 == 0 and fe3 == 0x54 and fm3 == 0x7fffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7dc686f0; op2val:0x1250e37;
op3val:0x2a7fffff; valaddr_reg:x3; val_offset:12525*0 + 3*335*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 12525*0 + 3*335*FLEN/8, x4, x1, x2)

inst_4176:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x4686f0 and fs2 == 0 and fe2 == 0x02 and fm2 == 0x250e37 and fs3 == 0 and fe3 == 0x7f and fm3 == 0x000001 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7dc686f0; op2val:0x1250e37;
op3val:0x3f800001; valaddr_reg:x3; val_offset:12528*0 + 3*336*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 12528*0 + 3*336*FLEN/8, x4, x1, x2)

inst_4177:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x4686f0 and fs2 == 0 and fe2 == 0x02 and fm2 == 0x250e37 and fs3 == 0 and fe3 == 0x7f and fm3 == 0x000003 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7dc686f0; op2val:0x1250e37;
op3val:0x3f800003; valaddr_reg:x3; val_offset:12531*0 + 3*337*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 12531*0 + 3*337*FLEN/8, x4, x1, x2)

inst_4178:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x4686f0 and fs2 == 0 and fe2 == 0x02 and fm2 == 0x250e37 and fs3 == 0 and fe3 == 0x7f and fm3 == 0x000007 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7dc686f0; op2val:0x1250e37;
op3val:0x3f800007; valaddr_reg:x3; val_offset:12534*0 + 3*338*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 12534*0 + 3*338*FLEN/8, x4, x1, x2)

inst_4179:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x4686f0 and fs2 == 0 and fe2 == 0x02 and fm2 == 0x250e37 and fs3 == 0 and fe3 == 0x7f and fm3 == 0x199999 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7dc686f0; op2val:0x1250e37;
op3val:0x3f999999; valaddr_reg:x3; val_offset:12537*0 + 3*339*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 12537*0 + 3*339*FLEN/8, x4, x1, x2)

inst_4180:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x4686f0 and fs2 == 0 and fe2 == 0x02 and fm2 == 0x250e37 and fs3 == 0 and fe3 == 0x7f and fm3 == 0x249249 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7dc686f0; op2val:0x1250e37;
op3val:0x3fa49249; valaddr_reg:x3; val_offset:12540*0 + 3*340*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 12540*0 + 3*340*FLEN/8, x4, x1, x2)

inst_4181:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x4686f0 and fs2 == 0 and fe2 == 0x02 and fm2 == 0x250e37 and fs3 == 0 and fe3 == 0x7f and fm3 == 0x333333 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7dc686f0; op2val:0x1250e37;
op3val:0x3fb33333; valaddr_reg:x3; val_offset:12543*0 + 3*341*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 12543*0 + 3*341*FLEN/8, x4, x1, x2)

inst_4182:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x4686f0 and fs2 == 0 and fe2 == 0x02 and fm2 == 0x250e37 and fs3 == 0 and fe3 == 0x7f and fm3 == 0x36db6d and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7dc686f0; op2val:0x1250e37;
op3val:0x3fb6db6d; valaddr_reg:x3; val_offset:12546*0 + 3*342*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 12546*0 + 3*342*FLEN/8, x4, x1, x2)

inst_4183:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x4686f0 and fs2 == 0 and fe2 == 0x02 and fm2 == 0x250e37 and fs3 == 0 and fe3 == 0x7f and fm3 == 0x3bbbbb and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7dc686f0; op2val:0x1250e37;
op3val:0x3fbbbbbb; valaddr_reg:x3; val_offset:12549*0 + 3*343*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 12549*0 + 3*343*FLEN/8, x4, x1, x2)

inst_4184:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x4686f0 and fs2 == 0 and fe2 == 0x02 and fm2 == 0x250e37 and fs3 == 0 and fe3 == 0x7f and fm3 == 0x444444 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7dc686f0; op2val:0x1250e37;
op3val:0x3fc44444; valaddr_reg:x3; val_offset:12552*0 + 3*344*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 12552*0 + 3*344*FLEN/8, x4, x1, x2)

inst_4185:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x4686f0 and fs2 == 0 and fe2 == 0x02 and fm2 == 0x250e37 and fs3 == 0 and fe3 == 0x7f and fm3 == 0x4ccccc and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7dc686f0; op2val:0x1250e37;
op3val:0x3fcccccc; valaddr_reg:x3; val_offset:12555*0 + 3*345*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 12555*0 + 3*345*FLEN/8, x4, x1, x2)

inst_4186:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x4686f0 and fs2 == 0 and fe2 == 0x02 and fm2 == 0x250e37 and fs3 == 0 and fe3 == 0x7f and fm3 == 0x5b6db6 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7dc686f0; op2val:0x1250e37;
op3val:0x3fdb6db6; valaddr_reg:x3; val_offset:12558*0 + 3*346*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 12558*0 + 3*346*FLEN/8, x4, x1, x2)

inst_4187:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x4686f0 and fs2 == 0 and fe2 == 0x02 and fm2 == 0x250e37 and fs3 == 0 and fe3 == 0x7f and fm3 == 0x666666 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7dc686f0; op2val:0x1250e37;
op3val:0x3fe66666; valaddr_reg:x3; val_offset:12561*0 + 3*347*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 12561*0 + 3*347*FLEN/8, x4, x1, x2)

inst_4188:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x4686f0 and fs2 == 0 and fe2 == 0x02 and fm2 == 0x250e37 and fs3 == 0 and fe3 == 0x7f and fm3 == 0x6db6db and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7dc686f0; op2val:0x1250e37;
op3val:0x3fedb6db; valaddr_reg:x3; val_offset:12564*0 + 3*348*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 12564*0 + 3*348*FLEN/8, x4, x1, x2)

inst_4189:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x4686f0 and fs2 == 0 and fe2 == 0x02 and fm2 == 0x250e37 and fs3 == 0 and fe3 == 0x7f and fm3 == 0x7ffff8 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7dc686f0; op2val:0x1250e37;
op3val:0x3ffffff8; valaddr_reg:x3; val_offset:12567*0 + 3*349*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 12567*0 + 3*349*FLEN/8, x4, x1, x2)

inst_4190:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x4686f0 and fs2 == 0 and fe2 == 0x02 and fm2 == 0x250e37 and fs3 == 0 and fe3 == 0x7f and fm3 == 0x7ffffc and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7dc686f0; op2val:0x1250e37;
op3val:0x3ffffffc; valaddr_reg:x3; val_offset:12570*0 + 3*350*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 12570*0 + 3*350*FLEN/8, x4, x1, x2)

inst_4191:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x4686f0 and fs2 == 0 and fe2 == 0x02 and fm2 == 0x250e37 and fs3 == 0 and fe3 == 0x7f and fm3 == 0x7ffffe and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7dc686f0; op2val:0x1250e37;
op3val:0x3ffffffe; valaddr_reg:x3; val_offset:12573*0 + 3*351*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 12573*0 + 3*351*FLEN/8, x4, x1, x2)

inst_4192:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x4847e0 and fs2 == 1 and fe2 == 0x02 and fm2 == 0x239c3d and fs3 == 1 and fe3 == 0x41 and fm3 == 0x000000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7dc847e0; op2val:0x81239c3d;
op3val:0xa0800000; valaddr_reg:x3; val_offset:12576*0 + 3*352*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 12576*0 + 3*352*FLEN/8, x4, x1, x2)

inst_4193:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x4847e0 and fs2 == 1 and fe2 == 0x02 and fm2 == 0x239c3d and fs3 == 1 and fe3 == 0x41 and fm3 == 0x000001 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7dc847e0; op2val:0x81239c3d;
op3val:0xa0800001; valaddr_reg:x3; val_offset:12579*0 + 3*353*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 12579*0 + 3*353*FLEN/8, x4, x1, x2)

inst_4194:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x4847e0 and fs2 == 1 and fe2 == 0x02 and fm2 == 0x239c3d and fs3 == 1 and fe3 == 0x41 and fm3 == 0x000003 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7dc847e0; op2val:0x81239c3d;
op3val:0xa0800003; valaddr_reg:x3; val_offset:12582*0 + 3*354*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 12582*0 + 3*354*FLEN/8, x4, x1, x2)

inst_4195:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x4847e0 and fs2 == 1 and fe2 == 0x02 and fm2 == 0x239c3d and fs3 == 1 and fe3 == 0x41 and fm3 == 0x000007 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7dc847e0; op2val:0x81239c3d;
op3val:0xa0800007; valaddr_reg:x3; val_offset:12585*0 + 3*355*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 12585*0 + 3*355*FLEN/8, x4, x1, x2)

inst_4196:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x4847e0 and fs2 == 1 and fe2 == 0x02 and fm2 == 0x239c3d and fs3 == 1 and fe3 == 0x41 and fm3 == 0x00000f and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7dc847e0; op2val:0x81239c3d;
op3val:0xa080000f; valaddr_reg:x3; val_offset:12588*0 + 3*356*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 12588*0 + 3*356*FLEN/8, x4, x1, x2)

inst_4197:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x4847e0 and fs2 == 1 and fe2 == 0x02 and fm2 == 0x239c3d and fs3 == 1 and fe3 == 0x41 and fm3 == 0x00001f and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7dc847e0; op2val:0x81239c3d;
op3val:0xa080001f; valaddr_reg:x3; val_offset:12591*0 + 3*357*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 12591*0 + 3*357*FLEN/8, x4, x1, x2)

inst_4198:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x4847e0 and fs2 == 1 and fe2 == 0x02 and fm2 == 0x239c3d and fs3 == 1 and fe3 == 0x41 and fm3 == 0x00003f and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7dc847e0; op2val:0x81239c3d;
op3val:0xa080003f; valaddr_reg:x3; val_offset:12594*0 + 3*358*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 12594*0 + 3*358*FLEN/8, x4, x1, x2)

inst_4199:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x4847e0 and fs2 == 1 and fe2 == 0x02 and fm2 == 0x239c3d and fs3 == 1 and fe3 == 0x41 and fm3 == 0x00007f and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7dc847e0; op2val:0x81239c3d;
op3val:0xa080007f; valaddr_reg:x3; val_offset:12597*0 + 3*359*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 12597*0 + 3*359*FLEN/8, x4, x1, x2)

inst_4200:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x4847e0 and fs2 == 1 and fe2 == 0x02 and fm2 == 0x239c3d and fs3 == 1 and fe3 == 0x41 and fm3 == 0x0000ff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7dc847e0; op2val:0x81239c3d;
op3val:0xa08000ff; valaddr_reg:x3; val_offset:12600*0 + 3*360*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 12600*0 + 3*360*FLEN/8, x4, x1, x2)

inst_4201:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x4847e0 and fs2 == 1 and fe2 == 0x02 and fm2 == 0x239c3d and fs3 == 1 and fe3 == 0x41 and fm3 == 0x0001ff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7dc847e0; op2val:0x81239c3d;
op3val:0xa08001ff; valaddr_reg:x3; val_offset:12603*0 + 3*361*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 12603*0 + 3*361*FLEN/8, x4, x1, x2)

inst_4202:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x4847e0 and fs2 == 1 and fe2 == 0x02 and fm2 == 0x239c3d and fs3 == 1 and fe3 == 0x41 and fm3 == 0x0003ff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7dc847e0; op2val:0x81239c3d;
op3val:0xa08003ff; valaddr_reg:x3; val_offset:12606*0 + 3*362*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 12606*0 + 3*362*FLEN/8, x4, x1, x2)

inst_4203:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x4847e0 and fs2 == 1 and fe2 == 0x02 and fm2 == 0x239c3d and fs3 == 1 and fe3 == 0x41 and fm3 == 0x0007ff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7dc847e0; op2val:0x81239c3d;
op3val:0xa08007ff; valaddr_reg:x3; val_offset:12609*0 + 3*363*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 12609*0 + 3*363*FLEN/8, x4, x1, x2)

inst_4204:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x4847e0 and fs2 == 1 and fe2 == 0x02 and fm2 == 0x239c3d and fs3 == 1 and fe3 == 0x41 and fm3 == 0x000fff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7dc847e0; op2val:0x81239c3d;
op3val:0xa0800fff; valaddr_reg:x3; val_offset:12612*0 + 3*364*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 12612*0 + 3*364*FLEN/8, x4, x1, x2)

inst_4205:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x4847e0 and fs2 == 1 and fe2 == 0x02 and fm2 == 0x239c3d and fs3 == 1 and fe3 == 0x41 and fm3 == 0x001fff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7dc847e0; op2val:0x81239c3d;
op3val:0xa0801fff; valaddr_reg:x3; val_offset:12615*0 + 3*365*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 12615*0 + 3*365*FLEN/8, x4, x1, x2)

inst_4206:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x4847e0 and fs2 == 1 and fe2 == 0x02 and fm2 == 0x239c3d and fs3 == 1 and fe3 == 0x41 and fm3 == 0x003fff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7dc847e0; op2val:0x81239c3d;
op3val:0xa0803fff; valaddr_reg:x3; val_offset:12618*0 + 3*366*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 12618*0 + 3*366*FLEN/8, x4, x1, x2)

inst_4207:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x4847e0 and fs2 == 1 and fe2 == 0x02 and fm2 == 0x239c3d and fs3 == 1 and fe3 == 0x41 and fm3 == 0x007fff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7dc847e0; op2val:0x81239c3d;
op3val:0xa0807fff; valaddr_reg:x3; val_offset:12621*0 + 3*367*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 12621*0 + 3*367*FLEN/8, x4, x1, x2)

inst_4208:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x4847e0 and fs2 == 1 and fe2 == 0x02 and fm2 == 0x239c3d and fs3 == 1 and fe3 == 0x41 and fm3 == 0x00ffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7dc847e0; op2val:0x81239c3d;
op3val:0xa080ffff; valaddr_reg:x3; val_offset:12624*0 + 3*368*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 12624*0 + 3*368*FLEN/8, x4, x1, x2)

inst_4209:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x4847e0 and fs2 == 1 and fe2 == 0x02 and fm2 == 0x239c3d and fs3 == 1 and fe3 == 0x41 and fm3 == 0x01ffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7dc847e0; op2val:0x81239c3d;
op3val:0xa081ffff; valaddr_reg:x3; val_offset:12627*0 + 3*369*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 12627*0 + 3*369*FLEN/8, x4, x1, x2)

inst_4210:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x4847e0 and fs2 == 1 and fe2 == 0x02 and fm2 == 0x239c3d and fs3 == 1 and fe3 == 0x41 and fm3 == 0x03ffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7dc847e0; op2val:0x81239c3d;
op3val:0xa083ffff; valaddr_reg:x3; val_offset:12630*0 + 3*370*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 12630*0 + 3*370*FLEN/8, x4, x1, x2)

inst_4211:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x4847e0 and fs2 == 1 and fe2 == 0x02 and fm2 == 0x239c3d and fs3 == 1 and fe3 == 0x41 and fm3 == 0x07ffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7dc847e0; op2val:0x81239c3d;
op3val:0xa087ffff; valaddr_reg:x3; val_offset:12633*0 + 3*371*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 12633*0 + 3*371*FLEN/8, x4, x1, x2)

inst_4212:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x4847e0 and fs2 == 1 and fe2 == 0x02 and fm2 == 0x239c3d and fs3 == 1 and fe3 == 0x41 and fm3 == 0x0fffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7dc847e0; op2val:0x81239c3d;
op3val:0xa08fffff; valaddr_reg:x3; val_offset:12636*0 + 3*372*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 12636*0 + 3*372*FLEN/8, x4, x1, x2)

inst_4213:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x4847e0 and fs2 == 1 and fe2 == 0x02 and fm2 == 0x239c3d and fs3 == 1 and fe3 == 0x41 and fm3 == 0x1fffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7dc847e0; op2val:0x81239c3d;
op3val:0xa09fffff; valaddr_reg:x3; val_offset:12639*0 + 3*373*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 12639*0 + 3*373*FLEN/8, x4, x1, x2)

inst_4214:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x4847e0 and fs2 == 1 and fe2 == 0x02 and fm2 == 0x239c3d and fs3 == 1 and fe3 == 0x41 and fm3 == 0x3fffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7dc847e0; op2val:0x81239c3d;
op3val:0xa0bfffff; valaddr_reg:x3; val_offset:12642*0 + 3*374*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 12642*0 + 3*374*FLEN/8, x4, x1, x2)

inst_4215:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x4847e0 and fs2 == 1 and fe2 == 0x02 and fm2 == 0x239c3d and fs3 == 1 and fe3 == 0x41 and fm3 == 0x400000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7dc847e0; op2val:0x81239c3d;
op3val:0xa0c00000; valaddr_reg:x3; val_offset:12645*0 + 3*375*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 12645*0 + 3*375*FLEN/8, x4, x1, x2)

inst_4216:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x4847e0 and fs2 == 1 and fe2 == 0x02 and fm2 == 0x239c3d and fs3 == 1 and fe3 == 0x41 and fm3 == 0x600000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7dc847e0; op2val:0x81239c3d;
op3val:0xa0e00000; valaddr_reg:x3; val_offset:12648*0 + 3*376*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 12648*0 + 3*376*FLEN/8, x4, x1, x2)

inst_4217:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x4847e0 and fs2 == 1 and fe2 == 0x02 and fm2 == 0x239c3d and fs3 == 1 and fe3 == 0x41 and fm3 == 0x700000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7dc847e0; op2val:0x81239c3d;
op3val:0xa0f00000; valaddr_reg:x3; val_offset:12651*0 + 3*377*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 12651*0 + 3*377*FLEN/8, x4, x1, x2)

inst_4218:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x4847e0 and fs2 == 1 and fe2 == 0x02 and fm2 == 0x239c3d and fs3 == 1 and fe3 == 0x41 and fm3 == 0x780000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7dc847e0; op2val:0x81239c3d;
op3val:0xa0f80000; valaddr_reg:x3; val_offset:12654*0 + 3*378*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 12654*0 + 3*378*FLEN/8, x4, x1, x2)

inst_4219:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x4847e0 and fs2 == 1 and fe2 == 0x02 and fm2 == 0x239c3d and fs3 == 1 and fe3 == 0x41 and fm3 == 0x7c0000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7dc847e0; op2val:0x81239c3d;
op3val:0xa0fc0000; valaddr_reg:x3; val_offset:12657*0 + 3*379*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 12657*0 + 3*379*FLEN/8, x4, x1, x2)

inst_4220:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x4847e0 and fs2 == 1 and fe2 == 0x02 and fm2 == 0x239c3d and fs3 == 1 and fe3 == 0x41 and fm3 == 0x7e0000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7dc847e0; op2val:0x81239c3d;
op3val:0xa0fe0000; valaddr_reg:x3; val_offset:12660*0 + 3*380*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 12660*0 + 3*380*FLEN/8, x4, x1, x2)

inst_4221:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x4847e0 and fs2 == 1 and fe2 == 0x02 and fm2 == 0x239c3d and fs3 == 1 and fe3 == 0x41 and fm3 == 0x7f0000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7dc847e0; op2val:0x81239c3d;
op3val:0xa0ff0000; valaddr_reg:x3; val_offset:12663*0 + 3*381*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 12663*0 + 3*381*FLEN/8, x4, x1, x2)

inst_4222:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x4847e0 and fs2 == 1 and fe2 == 0x02 and fm2 == 0x239c3d and fs3 == 1 and fe3 == 0x41 and fm3 == 0x7f8000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7dc847e0; op2val:0x81239c3d;
op3val:0xa0ff8000; valaddr_reg:x3; val_offset:12666*0 + 3*382*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 12666*0 + 3*382*FLEN/8, x4, x1, x2)

inst_4223:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x4847e0 and fs2 == 1 and fe2 == 0x02 and fm2 == 0x239c3d and fs3 == 1 and fe3 == 0x41 and fm3 == 0x7fc000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7dc847e0; op2val:0x81239c3d;
op3val:0xa0ffc000; valaddr_reg:x3; val_offset:12669*0 + 3*383*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 12669*0 + 3*383*FLEN/8, x4, x1, x2)
RVTEST_SIGBASE(x1,signature_x1_4)

inst_4224:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x4847e0 and fs2 == 1 and fe2 == 0x02 and fm2 == 0x239c3d and fs3 == 1 and fe3 == 0x41 and fm3 == 0x7fe000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7dc847e0; op2val:0x81239c3d;
op3val:0xa0ffe000; valaddr_reg:x3; val_offset:12672*0 + 3*384*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 12672*0 + 3*384*FLEN/8, x4, x1, x2)

inst_4225:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x4847e0 and fs2 == 1 and fe2 == 0x02 and fm2 == 0x239c3d and fs3 == 1 and fe3 == 0x41 and fm3 == 0x7ff000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7dc847e0; op2val:0x81239c3d;
op3val:0xa0fff000; valaddr_reg:x3; val_offset:12675*0 + 3*385*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 12675*0 + 3*385*FLEN/8, x4, x1, x2)

inst_4226:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x4847e0 and fs2 == 1 and fe2 == 0x02 and fm2 == 0x239c3d and fs3 == 1 and fe3 == 0x41 and fm3 == 0x7ff800 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7dc847e0; op2val:0x81239c3d;
op3val:0xa0fff800; valaddr_reg:x3; val_offset:12678*0 + 3*386*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 12678*0 + 3*386*FLEN/8, x4, x1, x2)

inst_4227:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x4847e0 and fs2 == 1 and fe2 == 0x02 and fm2 == 0x239c3d and fs3 == 1 and fe3 == 0x41 and fm3 == 0x7ffc00 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7dc847e0; op2val:0x81239c3d;
op3val:0xa0fffc00; valaddr_reg:x3; val_offset:12681*0 + 3*387*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 12681*0 + 3*387*FLEN/8, x4, x1, x2)

inst_4228:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x4847e0 and fs2 == 1 and fe2 == 0x02 and fm2 == 0x239c3d and fs3 == 1 and fe3 == 0x41 and fm3 == 0x7ffe00 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7dc847e0; op2val:0x81239c3d;
op3val:0xa0fffe00; valaddr_reg:x3; val_offset:12684*0 + 3*388*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 12684*0 + 3*388*FLEN/8, x4, x1, x2)

inst_4229:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x4847e0 and fs2 == 1 and fe2 == 0x02 and fm2 == 0x239c3d and fs3 == 1 and fe3 == 0x41 and fm3 == 0x7fff00 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7dc847e0; op2val:0x81239c3d;
op3val:0xa0ffff00; valaddr_reg:x3; val_offset:12687*0 + 3*389*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 12687*0 + 3*389*FLEN/8, x4, x1, x2)

inst_4230:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x4847e0 and fs2 == 1 and fe2 == 0x02 and fm2 == 0x239c3d and fs3 == 1 and fe3 == 0x41 and fm3 == 0x7fff80 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7dc847e0; op2val:0x81239c3d;
op3val:0xa0ffff80; valaddr_reg:x3; val_offset:12690*0 + 3*390*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 12690*0 + 3*390*FLEN/8, x4, x1, x2)

inst_4231:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x4847e0 and fs2 == 1 and fe2 == 0x02 and fm2 == 0x239c3d and fs3 == 1 and fe3 == 0x41 and fm3 == 0x7fffc0 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7dc847e0; op2val:0x81239c3d;
op3val:0xa0ffffc0; valaddr_reg:x3; val_offset:12693*0 + 3*391*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 12693*0 + 3*391*FLEN/8, x4, x1, x2)

inst_4232:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x4847e0 and fs2 == 1 and fe2 == 0x02 and fm2 == 0x239c3d and fs3 == 1 and fe3 == 0x41 and fm3 == 0x7fffe0 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7dc847e0; op2val:0x81239c3d;
op3val:0xa0ffffe0; valaddr_reg:x3; val_offset:12696*0 + 3*392*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 12696*0 + 3*392*FLEN/8, x4, x1, x2)

inst_4233:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x4847e0 and fs2 == 1 and fe2 == 0x02 and fm2 == 0x239c3d and fs3 == 1 and fe3 == 0x41 and fm3 == 0x7ffff0 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7dc847e0; op2val:0x81239c3d;
op3val:0xa0fffff0; valaddr_reg:x3; val_offset:12699*0 + 3*393*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 12699*0 + 3*393*FLEN/8, x4, x1, x2)

inst_4234:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x4847e0 and fs2 == 1 and fe2 == 0x02 and fm2 == 0x239c3d and fs3 == 1 and fe3 == 0x41 and fm3 == 0x7ffff8 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7dc847e0; op2val:0x81239c3d;
op3val:0xa0fffff8; valaddr_reg:x3; val_offset:12702*0 + 3*394*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 12702*0 + 3*394*FLEN/8, x4, x1, x2)

inst_4235:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x4847e0 and fs2 == 1 and fe2 == 0x02 and fm2 == 0x239c3d and fs3 == 1 and fe3 == 0x41 and fm3 == 0x7ffffc and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7dc847e0; op2val:0x81239c3d;
op3val:0xa0fffffc; valaddr_reg:x3; val_offset:12705*0 + 3*395*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 12705*0 + 3*395*FLEN/8, x4, x1, x2)

inst_4236:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x4847e0 and fs2 == 1 and fe2 == 0x02 and fm2 == 0x239c3d and fs3 == 1 and fe3 == 0x41 and fm3 == 0x7ffffe and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7dc847e0; op2val:0x81239c3d;
op3val:0xa0fffffe; valaddr_reg:x3; val_offset:12708*0 + 3*396*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 12708*0 + 3*396*FLEN/8, x4, x1, x2)

inst_4237:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x4847e0 and fs2 == 1 and fe2 == 0x02 and fm2 == 0x239c3d and fs3 == 1 and fe3 == 0x41 and fm3 == 0x7fffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7dc847e0; op2val:0x81239c3d;
op3val:0xa0ffffff; valaddr_reg:x3; val_offset:12711*0 + 3*397*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 12711*0 + 3*397*FLEN/8, x4, x1, x2)

inst_4238:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x4847e0 and fs2 == 1 and fe2 == 0x02 and fm2 == 0x239c3d and fs3 == 1 and fe3 == 0x7f and fm3 == 0x000001 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7dc847e0; op2val:0x81239c3d;
op3val:0xbf800001; valaddr_reg:x3; val_offset:12714*0 + 3*398*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 12714*0 + 3*398*FLEN/8, x4, x1, x2)

inst_4239:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x4847e0 and fs2 == 1 and fe2 == 0x02 and fm2 == 0x239c3d and fs3 == 1 and fe3 == 0x7f and fm3 == 0x000003 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7dc847e0; op2val:0x81239c3d;
op3val:0xbf800003; valaddr_reg:x3; val_offset:12717*0 + 3*399*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 12717*0 + 3*399*FLEN/8, x4, x1, x2)

inst_4240:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x4847e0 and fs2 == 1 and fe2 == 0x02 and fm2 == 0x239c3d and fs3 == 1 and fe3 == 0x7f and fm3 == 0x000007 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7dc847e0; op2val:0x81239c3d;
op3val:0xbf800007; valaddr_reg:x3; val_offset:12720*0 + 3*400*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 12720*0 + 3*400*FLEN/8, x4, x1, x2)

inst_4241:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x4847e0 and fs2 == 1 and fe2 == 0x02 and fm2 == 0x239c3d and fs3 == 1 and fe3 == 0x7f and fm3 == 0x199999 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7dc847e0; op2val:0x81239c3d;
op3val:0xbf999999; valaddr_reg:x3; val_offset:12723*0 + 3*401*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 12723*0 + 3*401*FLEN/8, x4, x1, x2)

inst_4242:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x4847e0 and fs2 == 1 and fe2 == 0x02 and fm2 == 0x239c3d and fs3 == 1 and fe3 == 0x7f and fm3 == 0x249249 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7dc847e0; op2val:0x81239c3d;
op3val:0xbfa49249; valaddr_reg:x3; val_offset:12726*0 + 3*402*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 12726*0 + 3*402*FLEN/8, x4, x1, x2)

inst_4243:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x4847e0 and fs2 == 1 and fe2 == 0x02 and fm2 == 0x239c3d and fs3 == 1 and fe3 == 0x7f and fm3 == 0x333333 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7dc847e0; op2val:0x81239c3d;
op3val:0xbfb33333; valaddr_reg:x3; val_offset:12729*0 + 3*403*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 12729*0 + 3*403*FLEN/8, x4, x1, x2)

inst_4244:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x4847e0 and fs2 == 1 and fe2 == 0x02 and fm2 == 0x239c3d and fs3 == 1 and fe3 == 0x7f and fm3 == 0x36db6d and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7dc847e0; op2val:0x81239c3d;
op3val:0xbfb6db6d; valaddr_reg:x3; val_offset:12732*0 + 3*404*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 12732*0 + 3*404*FLEN/8, x4, x1, x2)

inst_4245:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x4847e0 and fs2 == 1 and fe2 == 0x02 and fm2 == 0x239c3d and fs3 == 1 and fe3 == 0x7f and fm3 == 0x3bbbbb and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7dc847e0; op2val:0x81239c3d;
op3val:0xbfbbbbbb; valaddr_reg:x3; val_offset:12735*0 + 3*405*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 12735*0 + 3*405*FLEN/8, x4, x1, x2)

inst_4246:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x4847e0 and fs2 == 1 and fe2 == 0x02 and fm2 == 0x239c3d and fs3 == 1 and fe3 == 0x7f and fm3 == 0x444444 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7dc847e0; op2val:0x81239c3d;
op3val:0xbfc44444; valaddr_reg:x3; val_offset:12738*0 + 3*406*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 12738*0 + 3*406*FLEN/8, x4, x1, x2)

inst_4247:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x4847e0 and fs2 == 1 and fe2 == 0x02 and fm2 == 0x239c3d and fs3 == 1 and fe3 == 0x7f and fm3 == 0x4ccccc and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7dc847e0; op2val:0x81239c3d;
op3val:0xbfcccccc; valaddr_reg:x3; val_offset:12741*0 + 3*407*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 12741*0 + 3*407*FLEN/8, x4, x1, x2)

inst_4248:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x4847e0 and fs2 == 1 and fe2 == 0x02 and fm2 == 0x239c3d and fs3 == 1 and fe3 == 0x7f and fm3 == 0x5b6db6 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7dc847e0; op2val:0x81239c3d;
op3val:0xbfdb6db6; valaddr_reg:x3; val_offset:12744*0 + 3*408*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 12744*0 + 3*408*FLEN/8, x4, x1, x2)

inst_4249:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x4847e0 and fs2 == 1 and fe2 == 0x02 and fm2 == 0x239c3d and fs3 == 1 and fe3 == 0x7f and fm3 == 0x666666 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7dc847e0; op2val:0x81239c3d;
op3val:0xbfe66666; valaddr_reg:x3; val_offset:12747*0 + 3*409*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 12747*0 + 3*409*FLEN/8, x4, x1, x2)

inst_4250:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x4847e0 and fs2 == 1 and fe2 == 0x02 and fm2 == 0x239c3d and fs3 == 1 and fe3 == 0x7f and fm3 == 0x6db6db and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7dc847e0; op2val:0x81239c3d;
op3val:0xbfedb6db; valaddr_reg:x3; val_offset:12750*0 + 3*410*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 12750*0 + 3*410*FLEN/8, x4, x1, x2)

inst_4251:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x4847e0 and fs2 == 1 and fe2 == 0x02 and fm2 == 0x239c3d and fs3 == 1 and fe3 == 0x7f and fm3 == 0x7ffff8 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7dc847e0; op2val:0x81239c3d;
op3val:0xbffffff8; valaddr_reg:x3; val_offset:12753*0 + 3*411*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 12753*0 + 3*411*FLEN/8, x4, x1, x2)

inst_4252:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x4847e0 and fs2 == 1 and fe2 == 0x02 and fm2 == 0x239c3d and fs3 == 1 and fe3 == 0x7f and fm3 == 0x7ffffc and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7dc847e0; op2val:0x81239c3d;
op3val:0xbffffffc; valaddr_reg:x3; val_offset:12756*0 + 3*412*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 12756*0 + 3*412*FLEN/8, x4, x1, x2)

inst_4253:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x4847e0 and fs2 == 1 and fe2 == 0x02 and fm2 == 0x239c3d and fs3 == 1 and fe3 == 0x7f and fm3 == 0x7ffffe and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7dc847e0; op2val:0x81239c3d;
op3val:0xbffffffe; valaddr_reg:x3; val_offset:12759*0 + 3*413*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 12759*0 + 3*413*FLEN/8, x4, x1, x2)

inst_4254:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x4c506a and fs2 == 1 and fe2 == 0x02 and fm2 == 0x206168 and fs3 == 1 and fe3 == 0x6b and fm3 == 0x000000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7dcc506a; op2val:0x81206168;
op3val:0xb5800000; valaddr_reg:x3; val_offset:12762*0 + 3*414*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 12762*0 + 3*414*FLEN/8, x4, x1, x2)

inst_4255:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x4c506a and fs2 == 1 and fe2 == 0x02 and fm2 == 0x206168 and fs3 == 1 and fe3 == 0x6b and fm3 == 0x000001 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7dcc506a; op2val:0x81206168;
op3val:0xb5800001; valaddr_reg:x3; val_offset:12765*0 + 3*415*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 12765*0 + 3*415*FLEN/8, x4, x1, x2)

inst_4256:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x4c506a and fs2 == 1 and fe2 == 0x02 and fm2 == 0x206168 and fs3 == 1 and fe3 == 0x6b and fm3 == 0x000003 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7dcc506a; op2val:0x81206168;
op3val:0xb5800003; valaddr_reg:x3; val_offset:12768*0 + 3*416*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 12768*0 + 3*416*FLEN/8, x4, x1, x2)

inst_4257:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x4c506a and fs2 == 1 and fe2 == 0x02 and fm2 == 0x206168 and fs3 == 1 and fe3 == 0x6b and fm3 == 0x000007 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7dcc506a; op2val:0x81206168;
op3val:0xb5800007; valaddr_reg:x3; val_offset:12771*0 + 3*417*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 12771*0 + 3*417*FLEN/8, x4, x1, x2)

inst_4258:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x4c506a and fs2 == 1 and fe2 == 0x02 and fm2 == 0x206168 and fs3 == 1 and fe3 == 0x6b and fm3 == 0x00000f and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7dcc506a; op2val:0x81206168;
op3val:0xb580000f; valaddr_reg:x3; val_offset:12774*0 + 3*418*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 12774*0 + 3*418*FLEN/8, x4, x1, x2)

inst_4259:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x4c506a and fs2 == 1 and fe2 == 0x02 and fm2 == 0x206168 and fs3 == 1 and fe3 == 0x6b and fm3 == 0x00001f and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7dcc506a; op2val:0x81206168;
op3val:0xb580001f; valaddr_reg:x3; val_offset:12777*0 + 3*419*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 12777*0 + 3*419*FLEN/8, x4, x1, x2)

inst_4260:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x4c506a and fs2 == 1 and fe2 == 0x02 and fm2 == 0x206168 and fs3 == 1 and fe3 == 0x6b and fm3 == 0x00003f and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7dcc506a; op2val:0x81206168;
op3val:0xb580003f; valaddr_reg:x3; val_offset:12780*0 + 3*420*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 12780*0 + 3*420*FLEN/8, x4, x1, x2)

inst_4261:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x4c506a and fs2 == 1 and fe2 == 0x02 and fm2 == 0x206168 and fs3 == 1 and fe3 == 0x6b and fm3 == 0x00007f and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7dcc506a; op2val:0x81206168;
op3val:0xb580007f; valaddr_reg:x3; val_offset:12783*0 + 3*421*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 12783*0 + 3*421*FLEN/8, x4, x1, x2)

inst_4262:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x4c506a and fs2 == 1 and fe2 == 0x02 and fm2 == 0x206168 and fs3 == 1 and fe3 == 0x6b and fm3 == 0x0000ff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7dcc506a; op2val:0x81206168;
op3val:0xb58000ff; valaddr_reg:x3; val_offset:12786*0 + 3*422*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 12786*0 + 3*422*FLEN/8, x4, x1, x2)

inst_4263:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x4c506a and fs2 == 1 and fe2 == 0x02 and fm2 == 0x206168 and fs3 == 1 and fe3 == 0x6b and fm3 == 0x0001ff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7dcc506a; op2val:0x81206168;
op3val:0xb58001ff; valaddr_reg:x3; val_offset:12789*0 + 3*423*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 12789*0 + 3*423*FLEN/8, x4, x1, x2)

inst_4264:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x4c506a and fs2 == 1 and fe2 == 0x02 and fm2 == 0x206168 and fs3 == 1 and fe3 == 0x6b and fm3 == 0x0003ff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7dcc506a; op2val:0x81206168;
op3val:0xb58003ff; valaddr_reg:x3; val_offset:12792*0 + 3*424*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 12792*0 + 3*424*FLEN/8, x4, x1, x2)

inst_4265:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x4c506a and fs2 == 1 and fe2 == 0x02 and fm2 == 0x206168 and fs3 == 1 and fe3 == 0x6b and fm3 == 0x0007ff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7dcc506a; op2val:0x81206168;
op3val:0xb58007ff; valaddr_reg:x3; val_offset:12795*0 + 3*425*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 12795*0 + 3*425*FLEN/8, x4, x1, x2)

inst_4266:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x4c506a and fs2 == 1 and fe2 == 0x02 and fm2 == 0x206168 and fs3 == 1 and fe3 == 0x6b and fm3 == 0x000fff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7dcc506a; op2val:0x81206168;
op3val:0xb5800fff; valaddr_reg:x3; val_offset:12798*0 + 3*426*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 12798*0 + 3*426*FLEN/8, x4, x1, x2)

inst_4267:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x4c506a and fs2 == 1 and fe2 == 0x02 and fm2 == 0x206168 and fs3 == 1 and fe3 == 0x6b and fm3 == 0x001fff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7dcc506a; op2val:0x81206168;
op3val:0xb5801fff; valaddr_reg:x3; val_offset:12801*0 + 3*427*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 12801*0 + 3*427*FLEN/8, x4, x1, x2)

inst_4268:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x4c506a and fs2 == 1 and fe2 == 0x02 and fm2 == 0x206168 and fs3 == 1 and fe3 == 0x6b and fm3 == 0x003fff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7dcc506a; op2val:0x81206168;
op3val:0xb5803fff; valaddr_reg:x3; val_offset:12804*0 + 3*428*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 12804*0 + 3*428*FLEN/8, x4, x1, x2)

inst_4269:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x4c506a and fs2 == 1 and fe2 == 0x02 and fm2 == 0x206168 and fs3 == 1 and fe3 == 0x6b and fm3 == 0x007fff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7dcc506a; op2val:0x81206168;
op3val:0xb5807fff; valaddr_reg:x3; val_offset:12807*0 + 3*429*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 12807*0 + 3*429*FLEN/8, x4, x1, x2)

inst_4270:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x4c506a and fs2 == 1 and fe2 == 0x02 and fm2 == 0x206168 and fs3 == 1 and fe3 == 0x6b and fm3 == 0x00ffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7dcc506a; op2val:0x81206168;
op3val:0xb580ffff; valaddr_reg:x3; val_offset:12810*0 + 3*430*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 12810*0 + 3*430*FLEN/8, x4, x1, x2)

inst_4271:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x4c506a and fs2 == 1 and fe2 == 0x02 and fm2 == 0x206168 and fs3 == 1 and fe3 == 0x6b and fm3 == 0x01ffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7dcc506a; op2val:0x81206168;
op3val:0xb581ffff; valaddr_reg:x3; val_offset:12813*0 + 3*431*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 12813*0 + 3*431*FLEN/8, x4, x1, x2)

inst_4272:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x4c506a and fs2 == 1 and fe2 == 0x02 and fm2 == 0x206168 and fs3 == 1 and fe3 == 0x6b and fm3 == 0x03ffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7dcc506a; op2val:0x81206168;
op3val:0xb583ffff; valaddr_reg:x3; val_offset:12816*0 + 3*432*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 12816*0 + 3*432*FLEN/8, x4, x1, x2)

inst_4273:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x4c506a and fs2 == 1 and fe2 == 0x02 and fm2 == 0x206168 and fs3 == 1 and fe3 == 0x6b and fm3 == 0x07ffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7dcc506a; op2val:0x81206168;
op3val:0xb587ffff; valaddr_reg:x3; val_offset:12819*0 + 3*433*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 12819*0 + 3*433*FLEN/8, x4, x1, x2)

inst_4274:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x4c506a and fs2 == 1 and fe2 == 0x02 and fm2 == 0x206168 and fs3 == 1 and fe3 == 0x6b and fm3 == 0x0fffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7dcc506a; op2val:0x81206168;
op3val:0xb58fffff; valaddr_reg:x3; val_offset:12822*0 + 3*434*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 12822*0 + 3*434*FLEN/8, x4, x1, x2)

inst_4275:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x4c506a and fs2 == 1 and fe2 == 0x02 and fm2 == 0x206168 and fs3 == 1 and fe3 == 0x6b and fm3 == 0x1fffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7dcc506a; op2val:0x81206168;
op3val:0xb59fffff; valaddr_reg:x3; val_offset:12825*0 + 3*435*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 12825*0 + 3*435*FLEN/8, x4, x1, x2)

inst_4276:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x4c506a and fs2 == 1 and fe2 == 0x02 and fm2 == 0x206168 and fs3 == 1 and fe3 == 0x6b and fm3 == 0x3fffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7dcc506a; op2val:0x81206168;
op3val:0xb5bfffff; valaddr_reg:x3; val_offset:12828*0 + 3*436*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 12828*0 + 3*436*FLEN/8, x4, x1, x2)

inst_4277:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x4c506a and fs2 == 1 and fe2 == 0x02 and fm2 == 0x206168 and fs3 == 1 and fe3 == 0x6b and fm3 == 0x400000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7dcc506a; op2val:0x81206168;
op3val:0xb5c00000; valaddr_reg:x3; val_offset:12831*0 + 3*437*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 12831*0 + 3*437*FLEN/8, x4, x1, x2)

inst_4278:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x4c506a and fs2 == 1 and fe2 == 0x02 and fm2 == 0x206168 and fs3 == 1 and fe3 == 0x6b and fm3 == 0x600000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7dcc506a; op2val:0x81206168;
op3val:0xb5e00000; valaddr_reg:x3; val_offset:12834*0 + 3*438*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 12834*0 + 3*438*FLEN/8, x4, x1, x2)

inst_4279:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x4c506a and fs2 == 1 and fe2 == 0x02 and fm2 == 0x206168 and fs3 == 1 and fe3 == 0x6b and fm3 == 0x700000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7dcc506a; op2val:0x81206168;
op3val:0xb5f00000; valaddr_reg:x3; val_offset:12837*0 + 3*439*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 12837*0 + 3*439*FLEN/8, x4, x1, x2)

inst_4280:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x4c506a and fs2 == 1 and fe2 == 0x02 and fm2 == 0x206168 and fs3 == 1 and fe3 == 0x6b and fm3 == 0x780000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7dcc506a; op2val:0x81206168;
op3val:0xb5f80000; valaddr_reg:x3; val_offset:12840*0 + 3*440*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 12840*0 + 3*440*FLEN/8, x4, x1, x2)

inst_4281:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x4c506a and fs2 == 1 and fe2 == 0x02 and fm2 == 0x206168 and fs3 == 1 and fe3 == 0x6b and fm3 == 0x7c0000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7dcc506a; op2val:0x81206168;
op3val:0xb5fc0000; valaddr_reg:x3; val_offset:12843*0 + 3*441*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 12843*0 + 3*441*FLEN/8, x4, x1, x2)

inst_4282:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x4c506a and fs2 == 1 and fe2 == 0x02 and fm2 == 0x206168 and fs3 == 1 and fe3 == 0x6b and fm3 == 0x7e0000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7dcc506a; op2val:0x81206168;
op3val:0xb5fe0000; valaddr_reg:x3; val_offset:12846*0 + 3*442*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 12846*0 + 3*442*FLEN/8, x4, x1, x2)

inst_4283:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x4c506a and fs2 == 1 and fe2 == 0x02 and fm2 == 0x206168 and fs3 == 1 and fe3 == 0x6b and fm3 == 0x7f0000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7dcc506a; op2val:0x81206168;
op3val:0xb5ff0000; valaddr_reg:x3; val_offset:12849*0 + 3*443*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 12849*0 + 3*443*FLEN/8, x4, x1, x2)

inst_4284:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x4c506a and fs2 == 1 and fe2 == 0x02 and fm2 == 0x206168 and fs3 == 1 and fe3 == 0x6b and fm3 == 0x7f8000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7dcc506a; op2val:0x81206168;
op3val:0xb5ff8000; valaddr_reg:x3; val_offset:12852*0 + 3*444*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 12852*0 + 3*444*FLEN/8, x4, x1, x2)

inst_4285:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x4c506a and fs2 == 1 and fe2 == 0x02 and fm2 == 0x206168 and fs3 == 1 and fe3 == 0x6b and fm3 == 0x7fc000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7dcc506a; op2val:0x81206168;
op3val:0xb5ffc000; valaddr_reg:x3; val_offset:12855*0 + 3*445*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 12855*0 + 3*445*FLEN/8, x4, x1, x2)

inst_4286:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x4c506a and fs2 == 1 and fe2 == 0x02 and fm2 == 0x206168 and fs3 == 1 and fe3 == 0x6b and fm3 == 0x7fe000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7dcc506a; op2val:0x81206168;
op3val:0xb5ffe000; valaddr_reg:x3; val_offset:12858*0 + 3*446*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 12858*0 + 3*446*FLEN/8, x4, x1, x2)

inst_4287:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x4c506a and fs2 == 1 and fe2 == 0x02 and fm2 == 0x206168 and fs3 == 1 and fe3 == 0x6b and fm3 == 0x7ff000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7dcc506a; op2val:0x81206168;
op3val:0xb5fff000; valaddr_reg:x3; val_offset:12861*0 + 3*447*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 12861*0 + 3*447*FLEN/8, x4, x1, x2)

inst_4288:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x4c506a and fs2 == 1 and fe2 == 0x02 and fm2 == 0x206168 and fs3 == 1 and fe3 == 0x6b and fm3 == 0x7ff800 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7dcc506a; op2val:0x81206168;
op3val:0xb5fff800; valaddr_reg:x3; val_offset:12864*0 + 3*448*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 12864*0 + 3*448*FLEN/8, x4, x1, x2)

inst_4289:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x4c506a and fs2 == 1 and fe2 == 0x02 and fm2 == 0x206168 and fs3 == 1 and fe3 == 0x6b and fm3 == 0x7ffc00 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7dcc506a; op2val:0x81206168;
op3val:0xb5fffc00; valaddr_reg:x3; val_offset:12867*0 + 3*449*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 12867*0 + 3*449*FLEN/8, x4, x1, x2)

inst_4290:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x4c506a and fs2 == 1 and fe2 == 0x02 and fm2 == 0x206168 and fs3 == 1 and fe3 == 0x6b and fm3 == 0x7ffe00 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7dcc506a; op2val:0x81206168;
op3val:0xb5fffe00; valaddr_reg:x3; val_offset:12870*0 + 3*450*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 12870*0 + 3*450*FLEN/8, x4, x1, x2)

inst_4291:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x4c506a and fs2 == 1 and fe2 == 0x02 and fm2 == 0x206168 and fs3 == 1 and fe3 == 0x6b and fm3 == 0x7fff00 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7dcc506a; op2val:0x81206168;
op3val:0xb5ffff00; valaddr_reg:x3; val_offset:12873*0 + 3*451*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 12873*0 + 3*451*FLEN/8, x4, x1, x2)

inst_4292:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x4c506a and fs2 == 1 and fe2 == 0x02 and fm2 == 0x206168 and fs3 == 1 and fe3 == 0x6b and fm3 == 0x7fff80 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7dcc506a; op2val:0x81206168;
op3val:0xb5ffff80; valaddr_reg:x3; val_offset:12876*0 + 3*452*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 12876*0 + 3*452*FLEN/8, x4, x1, x2)

inst_4293:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x4c506a and fs2 == 1 and fe2 == 0x02 and fm2 == 0x206168 and fs3 == 1 and fe3 == 0x6b and fm3 == 0x7fffc0 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7dcc506a; op2val:0x81206168;
op3val:0xb5ffffc0; valaddr_reg:x3; val_offset:12879*0 + 3*453*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 12879*0 + 3*453*FLEN/8, x4, x1, x2)

inst_4294:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x4c506a and fs2 == 1 and fe2 == 0x02 and fm2 == 0x206168 and fs3 == 1 and fe3 == 0x6b and fm3 == 0x7fffe0 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7dcc506a; op2val:0x81206168;
op3val:0xb5ffffe0; valaddr_reg:x3; val_offset:12882*0 + 3*454*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 12882*0 + 3*454*FLEN/8, x4, x1, x2)

inst_4295:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x4c506a and fs2 == 1 and fe2 == 0x02 and fm2 == 0x206168 and fs3 == 1 and fe3 == 0x6b and fm3 == 0x7ffff0 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7dcc506a; op2val:0x81206168;
op3val:0xb5fffff0; valaddr_reg:x3; val_offset:12885*0 + 3*455*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 12885*0 + 3*455*FLEN/8, x4, x1, x2)

inst_4296:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x4c506a and fs2 == 1 and fe2 == 0x02 and fm2 == 0x206168 and fs3 == 1 and fe3 == 0x6b and fm3 == 0x7ffff8 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7dcc506a; op2val:0x81206168;
op3val:0xb5fffff8; valaddr_reg:x3; val_offset:12888*0 + 3*456*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 12888*0 + 3*456*FLEN/8, x4, x1, x2)

inst_4297:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x4c506a and fs2 == 1 and fe2 == 0x02 and fm2 == 0x206168 and fs3 == 1 and fe3 == 0x6b and fm3 == 0x7ffffc and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7dcc506a; op2val:0x81206168;
op3val:0xb5fffffc; valaddr_reg:x3; val_offset:12891*0 + 3*457*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 12891*0 + 3*457*FLEN/8, x4, x1, x2)

inst_4298:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x4c506a and fs2 == 1 and fe2 == 0x02 and fm2 == 0x206168 and fs3 == 1 and fe3 == 0x6b and fm3 == 0x7ffffe and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7dcc506a; op2val:0x81206168;
op3val:0xb5fffffe; valaddr_reg:x3; val_offset:12894*0 + 3*458*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 12894*0 + 3*458*FLEN/8, x4, x1, x2)

inst_4299:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x4c506a and fs2 == 1 and fe2 == 0x02 and fm2 == 0x206168 and fs3 == 1 and fe3 == 0x6b and fm3 == 0x7fffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7dcc506a; op2val:0x81206168;
op3val:0xb5ffffff; valaddr_reg:x3; val_offset:12897*0 + 3*459*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 12897*0 + 3*459*FLEN/8, x4, x1, x2)

inst_4300:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x4c506a and fs2 == 1 and fe2 == 0x02 and fm2 == 0x206168 and fs3 == 1 and fe3 == 0x7f and fm3 == 0x000001 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7dcc506a; op2val:0x81206168;
op3val:0xbf800001; valaddr_reg:x3; val_offset:12900*0 + 3*460*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 12900*0 + 3*460*FLEN/8, x4, x1, x2)

inst_4301:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x4c506a and fs2 == 1 and fe2 == 0x02 and fm2 == 0x206168 and fs3 == 1 and fe3 == 0x7f and fm3 == 0x000003 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7dcc506a; op2val:0x81206168;
op3val:0xbf800003; valaddr_reg:x3; val_offset:12903*0 + 3*461*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 12903*0 + 3*461*FLEN/8, x4, x1, x2)

inst_4302:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x4c506a and fs2 == 1 and fe2 == 0x02 and fm2 == 0x206168 and fs3 == 1 and fe3 == 0x7f and fm3 == 0x000007 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7dcc506a; op2val:0x81206168;
op3val:0xbf800007; valaddr_reg:x3; val_offset:12906*0 + 3*462*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 12906*0 + 3*462*FLEN/8, x4, x1, x2)

inst_4303:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x4c506a and fs2 == 1 and fe2 == 0x02 and fm2 == 0x206168 and fs3 == 1 and fe3 == 0x7f and fm3 == 0x199999 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7dcc506a; op2val:0x81206168;
op3val:0xbf999999; valaddr_reg:x3; val_offset:12909*0 + 3*463*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 12909*0 + 3*463*FLEN/8, x4, x1, x2)

inst_4304:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x4c506a and fs2 == 1 and fe2 == 0x02 and fm2 == 0x206168 and fs3 == 1 and fe3 == 0x7f and fm3 == 0x249249 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7dcc506a; op2val:0x81206168;
op3val:0xbfa49249; valaddr_reg:x3; val_offset:12912*0 + 3*464*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 12912*0 + 3*464*FLEN/8, x4, x1, x2)

inst_4305:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x4c506a and fs2 == 1 and fe2 == 0x02 and fm2 == 0x206168 and fs3 == 1 and fe3 == 0x7f and fm3 == 0x333333 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7dcc506a; op2val:0x81206168;
op3val:0xbfb33333; valaddr_reg:x3; val_offset:12915*0 + 3*465*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 12915*0 + 3*465*FLEN/8, x4, x1, x2)

inst_4306:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x4c506a and fs2 == 1 and fe2 == 0x02 and fm2 == 0x206168 and fs3 == 1 and fe3 == 0x7f and fm3 == 0x36db6d and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7dcc506a; op2val:0x81206168;
op3val:0xbfb6db6d; valaddr_reg:x3; val_offset:12918*0 + 3*466*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 12918*0 + 3*466*FLEN/8, x4, x1, x2)

inst_4307:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x4c506a and fs2 == 1 and fe2 == 0x02 and fm2 == 0x206168 and fs3 == 1 and fe3 == 0x7f and fm3 == 0x3bbbbb and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7dcc506a; op2val:0x81206168;
op3val:0xbfbbbbbb; valaddr_reg:x3; val_offset:12921*0 + 3*467*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 12921*0 + 3*467*FLEN/8, x4, x1, x2)

inst_4308:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x4c506a and fs2 == 1 and fe2 == 0x02 and fm2 == 0x206168 and fs3 == 1 and fe3 == 0x7f and fm3 == 0x444444 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7dcc506a; op2val:0x81206168;
op3val:0xbfc44444; valaddr_reg:x3; val_offset:12924*0 + 3*468*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 12924*0 + 3*468*FLEN/8, x4, x1, x2)

inst_4309:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x4c506a and fs2 == 1 and fe2 == 0x02 and fm2 == 0x206168 and fs3 == 1 and fe3 == 0x7f and fm3 == 0x4ccccc and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7dcc506a; op2val:0x81206168;
op3val:0xbfcccccc; valaddr_reg:x3; val_offset:12927*0 + 3*469*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 12927*0 + 3*469*FLEN/8, x4, x1, x2)

inst_4310:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x4c506a and fs2 == 1 and fe2 == 0x02 and fm2 == 0x206168 and fs3 == 1 and fe3 == 0x7f and fm3 == 0x5b6db6 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7dcc506a; op2val:0x81206168;
op3val:0xbfdb6db6; valaddr_reg:x3; val_offset:12930*0 + 3*470*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 12930*0 + 3*470*FLEN/8, x4, x1, x2)

inst_4311:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x4c506a and fs2 == 1 and fe2 == 0x02 and fm2 == 0x206168 and fs3 == 1 and fe3 == 0x7f and fm3 == 0x666666 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7dcc506a; op2val:0x81206168;
op3val:0xbfe66666; valaddr_reg:x3; val_offset:12933*0 + 3*471*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 12933*0 + 3*471*FLEN/8, x4, x1, x2)

inst_4312:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x4c506a and fs2 == 1 and fe2 == 0x02 and fm2 == 0x206168 and fs3 == 1 and fe3 == 0x7f and fm3 == 0x6db6db and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7dcc506a; op2val:0x81206168;
op3val:0xbfedb6db; valaddr_reg:x3; val_offset:12936*0 + 3*472*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 12936*0 + 3*472*FLEN/8, x4, x1, x2)

inst_4313:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x4c506a and fs2 == 1 and fe2 == 0x02 and fm2 == 0x206168 and fs3 == 1 and fe3 == 0x7f and fm3 == 0x7ffff8 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7dcc506a; op2val:0x81206168;
op3val:0xbffffff8; valaddr_reg:x3; val_offset:12939*0 + 3*473*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 12939*0 + 3*473*FLEN/8, x4, x1, x2)

inst_4314:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x4c506a and fs2 == 1 and fe2 == 0x02 and fm2 == 0x206168 and fs3 == 1 and fe3 == 0x7f and fm3 == 0x7ffffc and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7dcc506a; op2val:0x81206168;
op3val:0xbffffffc; valaddr_reg:x3; val_offset:12942*0 + 3*474*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 12942*0 + 3*474*FLEN/8, x4, x1, x2)

inst_4315:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x4c506a and fs2 == 1 and fe2 == 0x02 and fm2 == 0x206168 and fs3 == 1 and fe3 == 0x7f and fm3 == 0x7ffffe and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7dcc506a; op2val:0x81206168;
op3val:0xbffffffe; valaddr_reg:x3; val_offset:12945*0 + 3*475*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 12945*0 + 3*475*FLEN/8, x4, x1, x2)

inst_4316:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x4e622b and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7dce622b; op2val:0x0;
op3val:0x0; valaddr_reg:x3; val_offset:12948*0 + 3*476*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 12948*0 + 3*476*FLEN/8, x4, x1, x2)

inst_4317:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x4e622b and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000001 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7dce622b; op2val:0x0;
op3val:0x1; valaddr_reg:x3; val_offset:12951*0 + 3*477*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 12951*0 + 3*477*FLEN/8, x4, x1, x2)

inst_4318:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x4e622b and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000003 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7dce622b; op2val:0x0;
op3val:0x3; valaddr_reg:x3; val_offset:12954*0 + 3*478*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 12954*0 + 3*478*FLEN/8, x4, x1, x2)

inst_4319:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x4e622b and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000007 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7dce622b; op2val:0x0;
op3val:0x7; valaddr_reg:x3; val_offset:12957*0 + 3*479*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 12957*0 + 3*479*FLEN/8, x4, x1, x2)

inst_4320:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x4e622b and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x00000f and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7dce622b; op2val:0x0;
op3val:0xf; valaddr_reg:x3; val_offset:12960*0 + 3*480*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 12960*0 + 3*480*FLEN/8, x4, x1, x2)

inst_4321:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x4e622b and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x00001f and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7dce622b; op2val:0x0;
op3val:0x1f; valaddr_reg:x3; val_offset:12963*0 + 3*481*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 12963*0 + 3*481*FLEN/8, x4, x1, x2)

inst_4322:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x4e622b and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x00003f and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7dce622b; op2val:0x0;
op3val:0x3f; valaddr_reg:x3; val_offset:12966*0 + 3*482*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 12966*0 + 3*482*FLEN/8, x4, x1, x2)

inst_4323:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x4e622b and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x00007f and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7dce622b; op2val:0x0;
op3val:0x7f; valaddr_reg:x3; val_offset:12969*0 + 3*483*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 12969*0 + 3*483*FLEN/8, x4, x1, x2)

inst_4324:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x4e622b and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x0000ff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7dce622b; op2val:0x0;
op3val:0xff; valaddr_reg:x3; val_offset:12972*0 + 3*484*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 12972*0 + 3*484*FLEN/8, x4, x1, x2)

inst_4325:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x4e622b and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x0001ff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7dce622b; op2val:0x0;
op3val:0x1ff; valaddr_reg:x3; val_offset:12975*0 + 3*485*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 12975*0 + 3*485*FLEN/8, x4, x1, x2)

inst_4326:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x4e622b and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x0003ff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7dce622b; op2val:0x0;
op3val:0x3ff; valaddr_reg:x3; val_offset:12978*0 + 3*486*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 12978*0 + 3*486*FLEN/8, x4, x1, x2)

inst_4327:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x4e622b and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x0007ff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7dce622b; op2val:0x0;
op3val:0x7ff; valaddr_reg:x3; val_offset:12981*0 + 3*487*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 12981*0 + 3*487*FLEN/8, x4, x1, x2)

inst_4328:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x4e622b and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000fff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7dce622b; op2val:0x0;
op3val:0xfff; valaddr_reg:x3; val_offset:12984*0 + 3*488*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 12984*0 + 3*488*FLEN/8, x4, x1, x2)

inst_4329:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x4e622b and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x001fff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7dce622b; op2val:0x0;
op3val:0x1fff; valaddr_reg:x3; val_offset:12987*0 + 3*489*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 12987*0 + 3*489*FLEN/8, x4, x1, x2)

inst_4330:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x4e622b and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x003fff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7dce622b; op2val:0x0;
op3val:0x3fff; valaddr_reg:x3; val_offset:12990*0 + 3*490*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 12990*0 + 3*490*FLEN/8, x4, x1, x2)

inst_4331:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x4e622b and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x007fff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7dce622b; op2val:0x0;
op3val:0x7fff; valaddr_reg:x3; val_offset:12993*0 + 3*491*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 12993*0 + 3*491*FLEN/8, x4, x1, x2)

inst_4332:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x4e622b and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x00ffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7dce622b; op2val:0x0;
op3val:0xffff; valaddr_reg:x3; val_offset:12996*0 + 3*492*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 12996*0 + 3*492*FLEN/8, x4, x1, x2)

inst_4333:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x4e622b and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x01ffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7dce622b; op2val:0x0;
op3val:0x1ffff; valaddr_reg:x3; val_offset:12999*0 + 3*493*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 12999*0 + 3*493*FLEN/8, x4, x1, x2)

inst_4334:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x4e622b and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x03ffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7dce622b; op2val:0x0;
op3val:0x3ffff; valaddr_reg:x3; val_offset:13002*0 + 3*494*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 13002*0 + 3*494*FLEN/8, x4, x1, x2)

inst_4335:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x4e622b and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x07ffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7dce622b; op2val:0x0;
op3val:0x7ffff; valaddr_reg:x3; val_offset:13005*0 + 3*495*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 13005*0 + 3*495*FLEN/8, x4, x1, x2)

inst_4336:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x4e622b and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x0fffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7dce622b; op2val:0x0;
op3val:0xfffff; valaddr_reg:x3; val_offset:13008*0 + 3*496*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 13008*0 + 3*496*FLEN/8, x4, x1, x2)

inst_4337:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x4e622b and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x199999 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7dce622b; op2val:0x0;
op3val:0x199999; valaddr_reg:x3; val_offset:13011*0 + 3*497*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 13011*0 + 3*497*FLEN/8, x4, x1, x2)

inst_4338:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x4e622b and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x1fffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7dce622b; op2val:0x0;
op3val:0x1fffff; valaddr_reg:x3; val_offset:13014*0 + 3*498*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 13014*0 + 3*498*FLEN/8, x4, x1, x2)

inst_4339:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x4e622b and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x249249 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7dce622b; op2val:0x0;
op3val:0x249249; valaddr_reg:x3; val_offset:13017*0 + 3*499*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 13017*0 + 3*499*FLEN/8, x4, x1, x2)

inst_4340:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x4e622b and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x333333 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7dce622b; op2val:0x0;
op3val:0x333333; valaddr_reg:x3; val_offset:13020*0 + 3*500*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 13020*0 + 3*500*FLEN/8, x4, x1, x2)

inst_4341:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x4e622b and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x36db6d and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7dce622b; op2val:0x0;
op3val:0x36db6d; valaddr_reg:x3; val_offset:13023*0 + 3*501*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 13023*0 + 3*501*FLEN/8, x4, x1, x2)

inst_4342:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x4e622b and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x3bbbbb and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7dce622b; op2val:0x0;
op3val:0x3bbbbb; valaddr_reg:x3; val_offset:13026*0 + 3*502*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 13026*0 + 3*502*FLEN/8, x4, x1, x2)

inst_4343:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x4e622b and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x3fffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7dce622b; op2val:0x0;
op3val:0x3fffff; valaddr_reg:x3; val_offset:13029*0 + 3*503*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 13029*0 + 3*503*FLEN/8, x4, x1, x2)

inst_4344:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x4e622b and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x400000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7dce622b; op2val:0x0;
op3val:0x400000; valaddr_reg:x3; val_offset:13032*0 + 3*504*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 13032*0 + 3*504*FLEN/8, x4, x1, x2)

inst_4345:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x4e622b and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x444444 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7dce622b; op2val:0x0;
op3val:0x444444; valaddr_reg:x3; val_offset:13035*0 + 3*505*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 13035*0 + 3*505*FLEN/8, x4, x1, x2)

inst_4346:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x4e622b and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x4ccccc and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7dce622b; op2val:0x0;
op3val:0x4ccccc; valaddr_reg:x3; val_offset:13038*0 + 3*506*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 13038*0 + 3*506*FLEN/8, x4, x1, x2)

inst_4347:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x4e622b and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x5b6db6 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7dce622b; op2val:0x0;
op3val:0x5b6db6; valaddr_reg:x3; val_offset:13041*0 + 3*507*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 13041*0 + 3*507*FLEN/8, x4, x1, x2)

inst_4348:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x4e622b and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x600000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7dce622b; op2val:0x0;
op3val:0x600000; valaddr_reg:x3; val_offset:13044*0 + 3*508*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 13044*0 + 3*508*FLEN/8, x4, x1, x2)

inst_4349:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x4e622b and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x666666 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7dce622b; op2val:0x0;
op3val:0x666666; valaddr_reg:x3; val_offset:13047*0 + 3*509*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 13047*0 + 3*509*FLEN/8, x4, x1, x2)

inst_4350:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x4e622b and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x6db6db and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7dce622b; op2val:0x0;
op3val:0x6db6db; valaddr_reg:x3; val_offset:13050*0 + 3*510*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 13050*0 + 3*510*FLEN/8, x4, x1, x2)

inst_4351:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x4e622b and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x700000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7dce622b; op2val:0x0;
op3val:0x700000; valaddr_reg:x3; val_offset:13053*0 + 3*511*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 13053*0 + 3*511*FLEN/8, x4, x1, x2)
RVTEST_SIGBASE(x1,signature_x1_5)

inst_4352:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x4e622b and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x780000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7dce622b; op2val:0x0;
op3val:0x780000; valaddr_reg:x3; val_offset:13056*0 + 3*512*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 13056*0 + 3*512*FLEN/8, x4, x1, x2)

inst_4353:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x4e622b and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x7c0000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7dce622b; op2val:0x0;
op3val:0x7c0000; valaddr_reg:x3; val_offset:13059*0 + 3*513*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 13059*0 + 3*513*FLEN/8, x4, x1, x2)

inst_4354:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x4e622b and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x7e0000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7dce622b; op2val:0x0;
op3val:0x7e0000; valaddr_reg:x3; val_offset:13062*0 + 3*514*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 13062*0 + 3*514*FLEN/8, x4, x1, x2)

inst_4355:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x4e622b and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x7f0000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7dce622b; op2val:0x0;
op3val:0x7f0000; valaddr_reg:x3; val_offset:13065*0 + 3*515*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 13065*0 + 3*515*FLEN/8, x4, x1, x2)

inst_4356:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x4e622b and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x7f8000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7dce622b; op2val:0x0;
op3val:0x7f8000; valaddr_reg:x3; val_offset:13068*0 + 3*516*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 13068*0 + 3*516*FLEN/8, x4, x1, x2)

inst_4357:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x4e622b and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x7fc000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7dce622b; op2val:0x0;
op3val:0x7fc000; valaddr_reg:x3; val_offset:13071*0 + 3*517*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 13071*0 + 3*517*FLEN/8, x4, x1, x2)

inst_4358:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x4e622b and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x7fe000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7dce622b; op2val:0x0;
op3val:0x7fe000; valaddr_reg:x3; val_offset:13074*0 + 3*518*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 13074*0 + 3*518*FLEN/8, x4, x1, x2)

inst_4359:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x4e622b and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x7ff000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7dce622b; op2val:0x0;
op3val:0x7ff000; valaddr_reg:x3; val_offset:13077*0 + 3*519*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 13077*0 + 3*519*FLEN/8, x4, x1, x2)

inst_4360:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x4e622b and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x7ff800 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7dce622b; op2val:0x0;
op3val:0x7ff800; valaddr_reg:x3; val_offset:13080*0 + 3*520*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 13080*0 + 3*520*FLEN/8, x4, x1, x2)

inst_4361:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x4e622b and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x7ffc00 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7dce622b; op2val:0x0;
op3val:0x7ffc00; valaddr_reg:x3; val_offset:13083*0 + 3*521*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 13083*0 + 3*521*FLEN/8, x4, x1, x2)

inst_4362:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x4e622b and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x7ffe00 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7dce622b; op2val:0x0;
op3val:0x7ffe00; valaddr_reg:x3; val_offset:13086*0 + 3*522*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 13086*0 + 3*522*FLEN/8, x4, x1, x2)

inst_4363:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x4e622b and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x7fff00 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7dce622b; op2val:0x0;
op3val:0x7fff00; valaddr_reg:x3; val_offset:13089*0 + 3*523*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 13089*0 + 3*523*FLEN/8, x4, x1, x2)

inst_4364:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x4e622b and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x7fff80 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7dce622b; op2val:0x0;
op3val:0x7fff80; valaddr_reg:x3; val_offset:13092*0 + 3*524*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 13092*0 + 3*524*FLEN/8, x4, x1, x2)

inst_4365:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x4e622b and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x7fffc0 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7dce622b; op2val:0x0;
op3val:0x7fffc0; valaddr_reg:x3; val_offset:13095*0 + 3*525*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 13095*0 + 3*525*FLEN/8, x4, x1, x2)

inst_4366:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x4e622b and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x7fffe0 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7dce622b; op2val:0x0;
op3val:0x7fffe0; valaddr_reg:x3; val_offset:13098*0 + 3*526*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 13098*0 + 3*526*FLEN/8, x4, x1, x2)

inst_4367:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x4e622b and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x7ffff0 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7dce622b; op2val:0x0;
op3val:0x7ffff0; valaddr_reg:x3; val_offset:13101*0 + 3*527*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 13101*0 + 3*527*FLEN/8, x4, x1, x2)

inst_4368:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x4e622b and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x7ffff8 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7dce622b; op2val:0x0;
op3val:0x7ffff8; valaddr_reg:x3; val_offset:13104*0 + 3*528*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 13104*0 + 3*528*FLEN/8, x4, x1, x2)

inst_4369:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x4e622b and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x7ffffc and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7dce622b; op2val:0x0;
op3val:0x7ffffc; valaddr_reg:x3; val_offset:13107*0 + 3*529*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 13107*0 + 3*529*FLEN/8, x4, x1, x2)

inst_4370:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x4e622b and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x7ffffe and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7dce622b; op2val:0x0;
op3val:0x7ffffe; valaddr_reg:x3; val_offset:13110*0 + 3*530*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 13110*0 + 3*530*FLEN/8, x4, x1, x2)

inst_4371:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x4e622b and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x7fffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7dce622b; op2val:0x0;
op3val:0x7fffff; valaddr_reg:x3; val_offset:13113*0 + 3*531*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 13113*0 + 3*531*FLEN/8, x4, x1, x2)

inst_4372:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x4f9471 and fs2 == 1 and fe2 == 0x02 and fm2 == 0x1ddb79 and fs3 == 1 and fe3 == 0x5e and fm3 == 0x000000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7dcf9471; op2val:0x811ddb79;
op3val:0xaf000000; valaddr_reg:x3; val_offset:13116*0 + 3*532*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 13116*0 + 3*532*FLEN/8, x4, x1, x2)

inst_4373:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x4f9471 and fs2 == 1 and fe2 == 0x02 and fm2 == 0x1ddb79 and fs3 == 1 and fe3 == 0x5e and fm3 == 0x000001 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7dcf9471; op2val:0x811ddb79;
op3val:0xaf000001; valaddr_reg:x3; val_offset:13119*0 + 3*533*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 13119*0 + 3*533*FLEN/8, x4, x1, x2)

inst_4374:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x4f9471 and fs2 == 1 and fe2 == 0x02 and fm2 == 0x1ddb79 and fs3 == 1 and fe3 == 0x5e and fm3 == 0x000003 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7dcf9471; op2val:0x811ddb79;
op3val:0xaf000003; valaddr_reg:x3; val_offset:13122*0 + 3*534*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 13122*0 + 3*534*FLEN/8, x4, x1, x2)

inst_4375:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x4f9471 and fs2 == 1 and fe2 == 0x02 and fm2 == 0x1ddb79 and fs3 == 1 and fe3 == 0x5e and fm3 == 0x000007 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7dcf9471; op2val:0x811ddb79;
op3val:0xaf000007; valaddr_reg:x3; val_offset:13125*0 + 3*535*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 13125*0 + 3*535*FLEN/8, x4, x1, x2)

inst_4376:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x4f9471 and fs2 == 1 and fe2 == 0x02 and fm2 == 0x1ddb79 and fs3 == 1 and fe3 == 0x5e and fm3 == 0x00000f and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7dcf9471; op2val:0x811ddb79;
op3val:0xaf00000f; valaddr_reg:x3; val_offset:13128*0 + 3*536*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 13128*0 + 3*536*FLEN/8, x4, x1, x2)

inst_4377:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x4f9471 and fs2 == 1 and fe2 == 0x02 and fm2 == 0x1ddb79 and fs3 == 1 and fe3 == 0x5e and fm3 == 0x00001f and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7dcf9471; op2val:0x811ddb79;
op3val:0xaf00001f; valaddr_reg:x3; val_offset:13131*0 + 3*537*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 13131*0 + 3*537*FLEN/8, x4, x1, x2)

inst_4378:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x4f9471 and fs2 == 1 and fe2 == 0x02 and fm2 == 0x1ddb79 and fs3 == 1 and fe3 == 0x5e and fm3 == 0x00003f and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7dcf9471; op2val:0x811ddb79;
op3val:0xaf00003f; valaddr_reg:x3; val_offset:13134*0 + 3*538*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 13134*0 + 3*538*FLEN/8, x4, x1, x2)

inst_4379:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x4f9471 and fs2 == 1 and fe2 == 0x02 and fm2 == 0x1ddb79 and fs3 == 1 and fe3 == 0x5e and fm3 == 0x00007f and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7dcf9471; op2val:0x811ddb79;
op3val:0xaf00007f; valaddr_reg:x3; val_offset:13137*0 + 3*539*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 13137*0 + 3*539*FLEN/8, x4, x1, x2)

inst_4380:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x4f9471 and fs2 == 1 and fe2 == 0x02 and fm2 == 0x1ddb79 and fs3 == 1 and fe3 == 0x5e and fm3 == 0x0000ff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7dcf9471; op2val:0x811ddb79;
op3val:0xaf0000ff; valaddr_reg:x3; val_offset:13140*0 + 3*540*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 13140*0 + 3*540*FLEN/8, x4, x1, x2)

inst_4381:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x4f9471 and fs2 == 1 and fe2 == 0x02 and fm2 == 0x1ddb79 and fs3 == 1 and fe3 == 0x5e and fm3 == 0x0001ff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7dcf9471; op2val:0x811ddb79;
op3val:0xaf0001ff; valaddr_reg:x3; val_offset:13143*0 + 3*541*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 13143*0 + 3*541*FLEN/8, x4, x1, x2)

inst_4382:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x4f9471 and fs2 == 1 and fe2 == 0x02 and fm2 == 0x1ddb79 and fs3 == 1 and fe3 == 0x5e and fm3 == 0x0003ff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7dcf9471; op2val:0x811ddb79;
op3val:0xaf0003ff; valaddr_reg:x3; val_offset:13146*0 + 3*542*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 13146*0 + 3*542*FLEN/8, x4, x1, x2)

inst_4383:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x4f9471 and fs2 == 1 and fe2 == 0x02 and fm2 == 0x1ddb79 and fs3 == 1 and fe3 == 0x5e and fm3 == 0x0007ff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7dcf9471; op2val:0x811ddb79;
op3val:0xaf0007ff; valaddr_reg:x3; val_offset:13149*0 + 3*543*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 13149*0 + 3*543*FLEN/8, x4, x1, x2)

inst_4384:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x4f9471 and fs2 == 1 and fe2 == 0x02 and fm2 == 0x1ddb79 and fs3 == 1 and fe3 == 0x5e and fm3 == 0x000fff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7dcf9471; op2val:0x811ddb79;
op3val:0xaf000fff; valaddr_reg:x3; val_offset:13152*0 + 3*544*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 13152*0 + 3*544*FLEN/8, x4, x1, x2)

inst_4385:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x4f9471 and fs2 == 1 and fe2 == 0x02 and fm2 == 0x1ddb79 and fs3 == 1 and fe3 == 0x5e and fm3 == 0x001fff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7dcf9471; op2val:0x811ddb79;
op3val:0xaf001fff; valaddr_reg:x3; val_offset:13155*0 + 3*545*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 13155*0 + 3*545*FLEN/8, x4, x1, x2)

inst_4386:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x4f9471 and fs2 == 1 and fe2 == 0x02 and fm2 == 0x1ddb79 and fs3 == 1 and fe3 == 0x5e and fm3 == 0x003fff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7dcf9471; op2val:0x811ddb79;
op3val:0xaf003fff; valaddr_reg:x3; val_offset:13158*0 + 3*546*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 13158*0 + 3*546*FLEN/8, x4, x1, x2)

inst_4387:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x4f9471 and fs2 == 1 and fe2 == 0x02 and fm2 == 0x1ddb79 and fs3 == 1 and fe3 == 0x5e and fm3 == 0x007fff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7dcf9471; op2val:0x811ddb79;
op3val:0xaf007fff; valaddr_reg:x3; val_offset:13161*0 + 3*547*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 13161*0 + 3*547*FLEN/8, x4, x1, x2)

inst_4388:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x4f9471 and fs2 == 1 and fe2 == 0x02 and fm2 == 0x1ddb79 and fs3 == 1 and fe3 == 0x5e and fm3 == 0x00ffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7dcf9471; op2val:0x811ddb79;
op3val:0xaf00ffff; valaddr_reg:x3; val_offset:13164*0 + 3*548*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 13164*0 + 3*548*FLEN/8, x4, x1, x2)

inst_4389:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x4f9471 and fs2 == 1 and fe2 == 0x02 and fm2 == 0x1ddb79 and fs3 == 1 and fe3 == 0x5e and fm3 == 0x01ffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7dcf9471; op2val:0x811ddb79;
op3val:0xaf01ffff; valaddr_reg:x3; val_offset:13167*0 + 3*549*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 13167*0 + 3*549*FLEN/8, x4, x1, x2)

inst_4390:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x4f9471 and fs2 == 1 and fe2 == 0x02 and fm2 == 0x1ddb79 and fs3 == 1 and fe3 == 0x5e and fm3 == 0x03ffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7dcf9471; op2val:0x811ddb79;
op3val:0xaf03ffff; valaddr_reg:x3; val_offset:13170*0 + 3*550*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 13170*0 + 3*550*FLEN/8, x4, x1, x2)

inst_4391:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x4f9471 and fs2 == 1 and fe2 == 0x02 and fm2 == 0x1ddb79 and fs3 == 1 and fe3 == 0x5e and fm3 == 0x07ffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7dcf9471; op2val:0x811ddb79;
op3val:0xaf07ffff; valaddr_reg:x3; val_offset:13173*0 + 3*551*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 13173*0 + 3*551*FLEN/8, x4, x1, x2)

inst_4392:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x4f9471 and fs2 == 1 and fe2 == 0x02 and fm2 == 0x1ddb79 and fs3 == 1 and fe3 == 0x5e and fm3 == 0x0fffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7dcf9471; op2val:0x811ddb79;
op3val:0xaf0fffff; valaddr_reg:x3; val_offset:13176*0 + 3*552*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 13176*0 + 3*552*FLEN/8, x4, x1, x2)

inst_4393:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x4f9471 and fs2 == 1 and fe2 == 0x02 and fm2 == 0x1ddb79 and fs3 == 1 and fe3 == 0x5e and fm3 == 0x1fffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7dcf9471; op2val:0x811ddb79;
op3val:0xaf1fffff; valaddr_reg:x3; val_offset:13179*0 + 3*553*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 13179*0 + 3*553*FLEN/8, x4, x1, x2)

inst_4394:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x4f9471 and fs2 == 1 and fe2 == 0x02 and fm2 == 0x1ddb79 and fs3 == 1 and fe3 == 0x5e and fm3 == 0x3fffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7dcf9471; op2val:0x811ddb79;
op3val:0xaf3fffff; valaddr_reg:x3; val_offset:13182*0 + 3*554*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 13182*0 + 3*554*FLEN/8, x4, x1, x2)

inst_4395:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x4f9471 and fs2 == 1 and fe2 == 0x02 and fm2 == 0x1ddb79 and fs3 == 1 and fe3 == 0x5e and fm3 == 0x400000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7dcf9471; op2val:0x811ddb79;
op3val:0xaf400000; valaddr_reg:x3; val_offset:13185*0 + 3*555*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 13185*0 + 3*555*FLEN/8, x4, x1, x2)

inst_4396:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x4f9471 and fs2 == 1 and fe2 == 0x02 and fm2 == 0x1ddb79 and fs3 == 1 and fe3 == 0x5e and fm3 == 0x600000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7dcf9471; op2val:0x811ddb79;
op3val:0xaf600000; valaddr_reg:x3; val_offset:13188*0 + 3*556*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 13188*0 + 3*556*FLEN/8, x4, x1, x2)

inst_4397:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x4f9471 and fs2 == 1 and fe2 == 0x02 and fm2 == 0x1ddb79 and fs3 == 1 and fe3 == 0x5e and fm3 == 0x700000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7dcf9471; op2val:0x811ddb79;
op3val:0xaf700000; valaddr_reg:x3; val_offset:13191*0 + 3*557*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 13191*0 + 3*557*FLEN/8, x4, x1, x2)

inst_4398:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x4f9471 and fs2 == 1 and fe2 == 0x02 and fm2 == 0x1ddb79 and fs3 == 1 and fe3 == 0x5e and fm3 == 0x780000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7dcf9471; op2val:0x811ddb79;
op3val:0xaf780000; valaddr_reg:x3; val_offset:13194*0 + 3*558*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 13194*0 + 3*558*FLEN/8, x4, x1, x2)

inst_4399:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x4f9471 and fs2 == 1 and fe2 == 0x02 and fm2 == 0x1ddb79 and fs3 == 1 and fe3 == 0x5e and fm3 == 0x7c0000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7dcf9471; op2val:0x811ddb79;
op3val:0xaf7c0000; valaddr_reg:x3; val_offset:13197*0 + 3*559*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 13197*0 + 3*559*FLEN/8, x4, x1, x2)

inst_4400:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x4f9471 and fs2 == 1 and fe2 == 0x02 and fm2 == 0x1ddb79 and fs3 == 1 and fe3 == 0x5e and fm3 == 0x7e0000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7dcf9471; op2val:0x811ddb79;
op3val:0xaf7e0000; valaddr_reg:x3; val_offset:13200*0 + 3*560*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 13200*0 + 3*560*FLEN/8, x4, x1, x2)

inst_4401:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x4f9471 and fs2 == 1 and fe2 == 0x02 and fm2 == 0x1ddb79 and fs3 == 1 and fe3 == 0x5e and fm3 == 0x7f0000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7dcf9471; op2val:0x811ddb79;
op3val:0xaf7f0000; valaddr_reg:x3; val_offset:13203*0 + 3*561*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 13203*0 + 3*561*FLEN/8, x4, x1, x2)

inst_4402:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x4f9471 and fs2 == 1 and fe2 == 0x02 and fm2 == 0x1ddb79 and fs3 == 1 and fe3 == 0x5e and fm3 == 0x7f8000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7dcf9471; op2val:0x811ddb79;
op3val:0xaf7f8000; valaddr_reg:x3; val_offset:13206*0 + 3*562*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 13206*0 + 3*562*FLEN/8, x4, x1, x2)

inst_4403:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x4f9471 and fs2 == 1 and fe2 == 0x02 and fm2 == 0x1ddb79 and fs3 == 1 and fe3 == 0x5e and fm3 == 0x7fc000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7dcf9471; op2val:0x811ddb79;
op3val:0xaf7fc000; valaddr_reg:x3; val_offset:13209*0 + 3*563*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 13209*0 + 3*563*FLEN/8, x4, x1, x2)

inst_4404:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x4f9471 and fs2 == 1 and fe2 == 0x02 and fm2 == 0x1ddb79 and fs3 == 1 and fe3 == 0x5e and fm3 == 0x7fe000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7dcf9471; op2val:0x811ddb79;
op3val:0xaf7fe000; valaddr_reg:x3; val_offset:13212*0 + 3*564*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 13212*0 + 3*564*FLEN/8, x4, x1, x2)

inst_4405:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x4f9471 and fs2 == 1 and fe2 == 0x02 and fm2 == 0x1ddb79 and fs3 == 1 and fe3 == 0x5e and fm3 == 0x7ff000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7dcf9471; op2val:0x811ddb79;
op3val:0xaf7ff000; valaddr_reg:x3; val_offset:13215*0 + 3*565*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 13215*0 + 3*565*FLEN/8, x4, x1, x2)

inst_4406:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x4f9471 and fs2 == 1 and fe2 == 0x02 and fm2 == 0x1ddb79 and fs3 == 1 and fe3 == 0x5e and fm3 == 0x7ff800 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7dcf9471; op2val:0x811ddb79;
op3val:0xaf7ff800; valaddr_reg:x3; val_offset:13218*0 + 3*566*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 13218*0 + 3*566*FLEN/8, x4, x1, x2)

inst_4407:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x4f9471 and fs2 == 1 and fe2 == 0x02 and fm2 == 0x1ddb79 and fs3 == 1 and fe3 == 0x5e and fm3 == 0x7ffc00 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7dcf9471; op2val:0x811ddb79;
op3val:0xaf7ffc00; valaddr_reg:x3; val_offset:13221*0 + 3*567*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 13221*0 + 3*567*FLEN/8, x4, x1, x2)

inst_4408:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x4f9471 and fs2 == 1 and fe2 == 0x02 and fm2 == 0x1ddb79 and fs3 == 1 and fe3 == 0x5e and fm3 == 0x7ffe00 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7dcf9471; op2val:0x811ddb79;
op3val:0xaf7ffe00; valaddr_reg:x3; val_offset:13224*0 + 3*568*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 13224*0 + 3*568*FLEN/8, x4, x1, x2)

inst_4409:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x4f9471 and fs2 == 1 and fe2 == 0x02 and fm2 == 0x1ddb79 and fs3 == 1 and fe3 == 0x5e and fm3 == 0x7fff00 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7dcf9471; op2val:0x811ddb79;
op3val:0xaf7fff00; valaddr_reg:x3; val_offset:13227*0 + 3*569*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 13227*0 + 3*569*FLEN/8, x4, x1, x2)

inst_4410:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x4f9471 and fs2 == 1 and fe2 == 0x02 and fm2 == 0x1ddb79 and fs3 == 1 and fe3 == 0x5e and fm3 == 0x7fff80 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7dcf9471; op2val:0x811ddb79;
op3val:0xaf7fff80; valaddr_reg:x3; val_offset:13230*0 + 3*570*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 13230*0 + 3*570*FLEN/8, x4, x1, x2)

inst_4411:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x4f9471 and fs2 == 1 and fe2 == 0x02 and fm2 == 0x1ddb79 and fs3 == 1 and fe3 == 0x5e and fm3 == 0x7fffc0 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7dcf9471; op2val:0x811ddb79;
op3val:0xaf7fffc0; valaddr_reg:x3; val_offset:13233*0 + 3*571*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 13233*0 + 3*571*FLEN/8, x4, x1, x2)

inst_4412:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x4f9471 and fs2 == 1 and fe2 == 0x02 and fm2 == 0x1ddb79 and fs3 == 1 and fe3 == 0x5e and fm3 == 0x7fffe0 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7dcf9471; op2val:0x811ddb79;
op3val:0xaf7fffe0; valaddr_reg:x3; val_offset:13236*0 + 3*572*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 13236*0 + 3*572*FLEN/8, x4, x1, x2)

inst_4413:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x4f9471 and fs2 == 1 and fe2 == 0x02 and fm2 == 0x1ddb79 and fs3 == 1 and fe3 == 0x5e and fm3 == 0x7ffff0 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7dcf9471; op2val:0x811ddb79;
op3val:0xaf7ffff0; valaddr_reg:x3; val_offset:13239*0 + 3*573*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 13239*0 + 3*573*FLEN/8, x4, x1, x2)

inst_4414:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x4f9471 and fs2 == 1 and fe2 == 0x02 and fm2 == 0x1ddb79 and fs3 == 1 and fe3 == 0x5e and fm3 == 0x7ffff8 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7dcf9471; op2val:0x811ddb79;
op3val:0xaf7ffff8; valaddr_reg:x3; val_offset:13242*0 + 3*574*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 13242*0 + 3*574*FLEN/8, x4, x1, x2)

inst_4415:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x4f9471 and fs2 == 1 and fe2 == 0x02 and fm2 == 0x1ddb79 and fs3 == 1 and fe3 == 0x5e and fm3 == 0x7ffffc and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7dcf9471; op2val:0x811ddb79;
op3val:0xaf7ffffc; valaddr_reg:x3; val_offset:13245*0 + 3*575*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 13245*0 + 3*575*FLEN/8, x4, x1, x2)

inst_4416:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x4f9471 and fs2 == 1 and fe2 == 0x02 and fm2 == 0x1ddb79 and fs3 == 1 and fe3 == 0x5e and fm3 == 0x7ffffe and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7dcf9471; op2val:0x811ddb79;
op3val:0xaf7ffffe; valaddr_reg:x3; val_offset:13248*0 + 3*576*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 13248*0 + 3*576*FLEN/8, x4, x1, x2)

inst_4417:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x4f9471 and fs2 == 1 and fe2 == 0x02 and fm2 == 0x1ddb79 and fs3 == 1 and fe3 == 0x5e and fm3 == 0x7fffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7dcf9471; op2val:0x811ddb79;
op3val:0xaf7fffff; valaddr_reg:x3; val_offset:13251*0 + 3*577*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 13251*0 + 3*577*FLEN/8, x4, x1, x2)

inst_4418:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x4f9471 and fs2 == 1 and fe2 == 0x02 and fm2 == 0x1ddb79 and fs3 == 1 and fe3 == 0x7f and fm3 == 0x000001 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7dcf9471; op2val:0x811ddb79;
op3val:0xbf800001; valaddr_reg:x3; val_offset:13254*0 + 3*578*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 13254*0 + 3*578*FLEN/8, x4, x1, x2)

inst_4419:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x4f9471 and fs2 == 1 and fe2 == 0x02 and fm2 == 0x1ddb79 and fs3 == 1 and fe3 == 0x7f and fm3 == 0x000003 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7dcf9471; op2val:0x811ddb79;
op3val:0xbf800003; valaddr_reg:x3; val_offset:13257*0 + 3*579*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 13257*0 + 3*579*FLEN/8, x4, x1, x2)

inst_4420:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x4f9471 and fs2 == 1 and fe2 == 0x02 and fm2 == 0x1ddb79 and fs3 == 1 and fe3 == 0x7f and fm3 == 0x000007 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7dcf9471; op2val:0x811ddb79;
op3val:0xbf800007; valaddr_reg:x3; val_offset:13260*0 + 3*580*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 13260*0 + 3*580*FLEN/8, x4, x1, x2)

inst_4421:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x4f9471 and fs2 == 1 and fe2 == 0x02 and fm2 == 0x1ddb79 and fs3 == 1 and fe3 == 0x7f and fm3 == 0x199999 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7dcf9471; op2val:0x811ddb79;
op3val:0xbf999999; valaddr_reg:x3; val_offset:13263*0 + 3*581*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 13263*0 + 3*581*FLEN/8, x4, x1, x2)

inst_4422:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x4f9471 and fs2 == 1 and fe2 == 0x02 and fm2 == 0x1ddb79 and fs3 == 1 and fe3 == 0x7f and fm3 == 0x249249 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7dcf9471; op2val:0x811ddb79;
op3val:0xbfa49249; valaddr_reg:x3; val_offset:13266*0 + 3*582*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 13266*0 + 3*582*FLEN/8, x4, x1, x2)

inst_4423:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x4f9471 and fs2 == 1 and fe2 == 0x02 and fm2 == 0x1ddb79 and fs3 == 1 and fe3 == 0x7f and fm3 == 0x333333 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7dcf9471; op2val:0x811ddb79;
op3val:0xbfb33333; valaddr_reg:x3; val_offset:13269*0 + 3*583*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 13269*0 + 3*583*FLEN/8, x4, x1, x2)

inst_4424:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x4f9471 and fs2 == 1 and fe2 == 0x02 and fm2 == 0x1ddb79 and fs3 == 1 and fe3 == 0x7f and fm3 == 0x36db6d and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7dcf9471; op2val:0x811ddb79;
op3val:0xbfb6db6d; valaddr_reg:x3; val_offset:13272*0 + 3*584*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 13272*0 + 3*584*FLEN/8, x4, x1, x2)

inst_4425:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x4f9471 and fs2 == 1 and fe2 == 0x02 and fm2 == 0x1ddb79 and fs3 == 1 and fe3 == 0x7f and fm3 == 0x3bbbbb and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7dcf9471; op2val:0x811ddb79;
op3val:0xbfbbbbbb; valaddr_reg:x3; val_offset:13275*0 + 3*585*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 13275*0 + 3*585*FLEN/8, x4, x1, x2)

inst_4426:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x4f9471 and fs2 == 1 and fe2 == 0x02 and fm2 == 0x1ddb79 and fs3 == 1 and fe3 == 0x7f and fm3 == 0x444444 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7dcf9471; op2val:0x811ddb79;
op3val:0xbfc44444; valaddr_reg:x3; val_offset:13278*0 + 3*586*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 13278*0 + 3*586*FLEN/8, x4, x1, x2)

inst_4427:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x4f9471 and fs2 == 1 and fe2 == 0x02 and fm2 == 0x1ddb79 and fs3 == 1 and fe3 == 0x7f and fm3 == 0x4ccccc and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7dcf9471; op2val:0x811ddb79;
op3val:0xbfcccccc; valaddr_reg:x3; val_offset:13281*0 + 3*587*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 13281*0 + 3*587*FLEN/8, x4, x1, x2)

inst_4428:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x4f9471 and fs2 == 1 and fe2 == 0x02 and fm2 == 0x1ddb79 and fs3 == 1 and fe3 == 0x7f and fm3 == 0x5b6db6 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7dcf9471; op2val:0x811ddb79;
op3val:0xbfdb6db6; valaddr_reg:x3; val_offset:13284*0 + 3*588*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 13284*0 + 3*588*FLEN/8, x4, x1, x2)

inst_4429:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x4f9471 and fs2 == 1 and fe2 == 0x02 and fm2 == 0x1ddb79 and fs3 == 1 and fe3 == 0x7f and fm3 == 0x666666 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7dcf9471; op2val:0x811ddb79;
op3val:0xbfe66666; valaddr_reg:x3; val_offset:13287*0 + 3*589*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 13287*0 + 3*589*FLEN/8, x4, x1, x2)

inst_4430:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x4f9471 and fs2 == 1 and fe2 == 0x02 and fm2 == 0x1ddb79 and fs3 == 1 and fe3 == 0x7f and fm3 == 0x6db6db and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7dcf9471; op2val:0x811ddb79;
op3val:0xbfedb6db; valaddr_reg:x3; val_offset:13290*0 + 3*590*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 13290*0 + 3*590*FLEN/8, x4, x1, x2)

inst_4431:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x4f9471 and fs2 == 1 and fe2 == 0x02 and fm2 == 0x1ddb79 and fs3 == 1 and fe3 == 0x7f and fm3 == 0x7ffff8 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7dcf9471; op2val:0x811ddb79;
op3val:0xbffffff8; valaddr_reg:x3; val_offset:13293*0 + 3*591*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 13293*0 + 3*591*FLEN/8, x4, x1, x2)

inst_4432:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x4f9471 and fs2 == 1 and fe2 == 0x02 and fm2 == 0x1ddb79 and fs3 == 1 and fe3 == 0x7f and fm3 == 0x7ffffc and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7dcf9471; op2val:0x811ddb79;
op3val:0xbffffffc; valaddr_reg:x3; val_offset:13296*0 + 3*592*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 13296*0 + 3*592*FLEN/8, x4, x1, x2)

inst_4433:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x4f9471 and fs2 == 1 and fe2 == 0x02 and fm2 == 0x1ddb79 and fs3 == 1 and fe3 == 0x7f and fm3 == 0x7ffffe and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7dcf9471; op2val:0x811ddb79;
op3val:0xbffffffe; valaddr_reg:x3; val_offset:13299*0 + 3*593*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 13299*0 + 3*593*FLEN/8, x4, x1, x2)

inst_4434:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x51cef3 and fs2 == 0 and fe2 == 0x82 and fm2 == 0x1c2e3a and fs3 == 0 and fe3 == 0xc1 and fm3 == 0x000000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7dd1cef3; op2val:0x411c2e3a;
op3val:0x60800000; valaddr_reg:x3; val_offset:13302*0 + 3*594*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 13302*0 + 3*594*FLEN/8, x4, x1, x2)

inst_4435:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x51cef3 and fs2 == 0 and fe2 == 0x82 and fm2 == 0x1c2e3a and fs3 == 0 and fe3 == 0xc1 and fm3 == 0x000001 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7dd1cef3; op2val:0x411c2e3a;
op3val:0x60800001; valaddr_reg:x3; val_offset:13305*0 + 3*595*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 13305*0 + 3*595*FLEN/8, x4, x1, x2)

inst_4436:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x51cef3 and fs2 == 0 and fe2 == 0x82 and fm2 == 0x1c2e3a and fs3 == 0 and fe3 == 0xc1 and fm3 == 0x000003 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7dd1cef3; op2val:0x411c2e3a;
op3val:0x60800003; valaddr_reg:x3; val_offset:13308*0 + 3*596*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 13308*0 + 3*596*FLEN/8, x4, x1, x2)

inst_4437:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x51cef3 and fs2 == 0 and fe2 == 0x82 and fm2 == 0x1c2e3a and fs3 == 0 and fe3 == 0xc1 and fm3 == 0x000007 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7dd1cef3; op2val:0x411c2e3a;
op3val:0x60800007; valaddr_reg:x3; val_offset:13311*0 + 3*597*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 13311*0 + 3*597*FLEN/8, x4, x1, x2)

inst_4438:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x51cef3 and fs2 == 0 and fe2 == 0x82 and fm2 == 0x1c2e3a and fs3 == 0 and fe3 == 0xc1 and fm3 == 0x00000f and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7dd1cef3; op2val:0x411c2e3a;
op3val:0x6080000f; valaddr_reg:x3; val_offset:13314*0 + 3*598*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 13314*0 + 3*598*FLEN/8, x4, x1, x2)

inst_4439:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x51cef3 and fs2 == 0 and fe2 == 0x82 and fm2 == 0x1c2e3a and fs3 == 0 and fe3 == 0xc1 and fm3 == 0x00001f and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7dd1cef3; op2val:0x411c2e3a;
op3val:0x6080001f; valaddr_reg:x3; val_offset:13317*0 + 3*599*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 13317*0 + 3*599*FLEN/8, x4, x1, x2)

inst_4440:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x51cef3 and fs2 == 0 and fe2 == 0x82 and fm2 == 0x1c2e3a and fs3 == 0 and fe3 == 0xc1 and fm3 == 0x00003f and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7dd1cef3; op2val:0x411c2e3a;
op3val:0x6080003f; valaddr_reg:x3; val_offset:13320*0 + 3*600*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 13320*0 + 3*600*FLEN/8, x4, x1, x2)

inst_4441:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x51cef3 and fs2 == 0 and fe2 == 0x82 and fm2 == 0x1c2e3a and fs3 == 0 and fe3 == 0xc1 and fm3 == 0x00007f and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7dd1cef3; op2val:0x411c2e3a;
op3val:0x6080007f; valaddr_reg:x3; val_offset:13323*0 + 3*601*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 13323*0 + 3*601*FLEN/8, x4, x1, x2)

inst_4442:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x51cef3 and fs2 == 0 and fe2 == 0x82 and fm2 == 0x1c2e3a and fs3 == 0 and fe3 == 0xc1 and fm3 == 0x0000ff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7dd1cef3; op2val:0x411c2e3a;
op3val:0x608000ff; valaddr_reg:x3; val_offset:13326*0 + 3*602*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 13326*0 + 3*602*FLEN/8, x4, x1, x2)

inst_4443:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x51cef3 and fs2 == 0 and fe2 == 0x82 and fm2 == 0x1c2e3a and fs3 == 0 and fe3 == 0xc1 and fm3 == 0x0001ff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7dd1cef3; op2val:0x411c2e3a;
op3val:0x608001ff; valaddr_reg:x3; val_offset:13329*0 + 3*603*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 13329*0 + 3*603*FLEN/8, x4, x1, x2)

inst_4444:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x51cef3 and fs2 == 0 and fe2 == 0x82 and fm2 == 0x1c2e3a and fs3 == 0 and fe3 == 0xc1 and fm3 == 0x0003ff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7dd1cef3; op2val:0x411c2e3a;
op3val:0x608003ff; valaddr_reg:x3; val_offset:13332*0 + 3*604*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 13332*0 + 3*604*FLEN/8, x4, x1, x2)

inst_4445:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x51cef3 and fs2 == 0 and fe2 == 0x82 and fm2 == 0x1c2e3a and fs3 == 0 and fe3 == 0xc1 and fm3 == 0x0007ff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7dd1cef3; op2val:0x411c2e3a;
op3val:0x608007ff; valaddr_reg:x3; val_offset:13335*0 + 3*605*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 13335*0 + 3*605*FLEN/8, x4, x1, x2)

inst_4446:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x51cef3 and fs2 == 0 and fe2 == 0x82 and fm2 == 0x1c2e3a and fs3 == 0 and fe3 == 0xc1 and fm3 == 0x000fff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7dd1cef3; op2val:0x411c2e3a;
op3val:0x60800fff; valaddr_reg:x3; val_offset:13338*0 + 3*606*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 13338*0 + 3*606*FLEN/8, x4, x1, x2)

inst_4447:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x51cef3 and fs2 == 0 and fe2 == 0x82 and fm2 == 0x1c2e3a and fs3 == 0 and fe3 == 0xc1 and fm3 == 0x001fff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7dd1cef3; op2val:0x411c2e3a;
op3val:0x60801fff; valaddr_reg:x3; val_offset:13341*0 + 3*607*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 13341*0 + 3*607*FLEN/8, x4, x1, x2)

inst_4448:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x51cef3 and fs2 == 0 and fe2 == 0x82 and fm2 == 0x1c2e3a and fs3 == 0 and fe3 == 0xc1 and fm3 == 0x003fff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7dd1cef3; op2val:0x411c2e3a;
op3val:0x60803fff; valaddr_reg:x3; val_offset:13344*0 + 3*608*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 13344*0 + 3*608*FLEN/8, x4, x1, x2)

inst_4449:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x51cef3 and fs2 == 0 and fe2 == 0x82 and fm2 == 0x1c2e3a and fs3 == 0 and fe3 == 0xc1 and fm3 == 0x007fff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7dd1cef3; op2val:0x411c2e3a;
op3val:0x60807fff; valaddr_reg:x3; val_offset:13347*0 + 3*609*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 13347*0 + 3*609*FLEN/8, x4, x1, x2)

inst_4450:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x51cef3 and fs2 == 0 and fe2 == 0x82 and fm2 == 0x1c2e3a and fs3 == 0 and fe3 == 0xc1 and fm3 == 0x00ffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7dd1cef3; op2val:0x411c2e3a;
op3val:0x6080ffff; valaddr_reg:x3; val_offset:13350*0 + 3*610*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 13350*0 + 3*610*FLEN/8, x4, x1, x2)

inst_4451:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x51cef3 and fs2 == 0 and fe2 == 0x82 and fm2 == 0x1c2e3a and fs3 == 0 and fe3 == 0xc1 and fm3 == 0x01ffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7dd1cef3; op2val:0x411c2e3a;
op3val:0x6081ffff; valaddr_reg:x3; val_offset:13353*0 + 3*611*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 13353*0 + 3*611*FLEN/8, x4, x1, x2)

inst_4452:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x51cef3 and fs2 == 0 and fe2 == 0x82 and fm2 == 0x1c2e3a and fs3 == 0 and fe3 == 0xc1 and fm3 == 0x03ffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7dd1cef3; op2val:0x411c2e3a;
op3val:0x6083ffff; valaddr_reg:x3; val_offset:13356*0 + 3*612*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 13356*0 + 3*612*FLEN/8, x4, x1, x2)

inst_4453:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x51cef3 and fs2 == 0 and fe2 == 0x82 and fm2 == 0x1c2e3a and fs3 == 0 and fe3 == 0xc1 and fm3 == 0x07ffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7dd1cef3; op2val:0x411c2e3a;
op3val:0x6087ffff; valaddr_reg:x3; val_offset:13359*0 + 3*613*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 13359*0 + 3*613*FLEN/8, x4, x1, x2)

inst_4454:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x51cef3 and fs2 == 0 and fe2 == 0x82 and fm2 == 0x1c2e3a and fs3 == 0 and fe3 == 0xc1 and fm3 == 0x0fffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7dd1cef3; op2val:0x411c2e3a;
op3val:0x608fffff; valaddr_reg:x3; val_offset:13362*0 + 3*614*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 13362*0 + 3*614*FLEN/8, x4, x1, x2)

inst_4455:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x51cef3 and fs2 == 0 and fe2 == 0x82 and fm2 == 0x1c2e3a and fs3 == 0 and fe3 == 0xc1 and fm3 == 0x1fffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7dd1cef3; op2val:0x411c2e3a;
op3val:0x609fffff; valaddr_reg:x3; val_offset:13365*0 + 3*615*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 13365*0 + 3*615*FLEN/8, x4, x1, x2)

inst_4456:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x51cef3 and fs2 == 0 and fe2 == 0x82 and fm2 == 0x1c2e3a and fs3 == 0 and fe3 == 0xc1 and fm3 == 0x3fffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7dd1cef3; op2val:0x411c2e3a;
op3val:0x60bfffff; valaddr_reg:x3; val_offset:13368*0 + 3*616*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 13368*0 + 3*616*FLEN/8, x4, x1, x2)

inst_4457:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x51cef3 and fs2 == 0 and fe2 == 0x82 and fm2 == 0x1c2e3a and fs3 == 0 and fe3 == 0xc1 and fm3 == 0x400000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7dd1cef3; op2val:0x411c2e3a;
op3val:0x60c00000; valaddr_reg:x3; val_offset:13371*0 + 3*617*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 13371*0 + 3*617*FLEN/8, x4, x1, x2)

inst_4458:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x51cef3 and fs2 == 0 and fe2 == 0x82 and fm2 == 0x1c2e3a and fs3 == 0 and fe3 == 0xc1 and fm3 == 0x600000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7dd1cef3; op2val:0x411c2e3a;
op3val:0x60e00000; valaddr_reg:x3; val_offset:13374*0 + 3*618*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 13374*0 + 3*618*FLEN/8, x4, x1, x2)

inst_4459:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x51cef3 and fs2 == 0 and fe2 == 0x82 and fm2 == 0x1c2e3a and fs3 == 0 and fe3 == 0xc1 and fm3 == 0x700000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7dd1cef3; op2val:0x411c2e3a;
op3val:0x60f00000; valaddr_reg:x3; val_offset:13377*0 + 3*619*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 13377*0 + 3*619*FLEN/8, x4, x1, x2)

inst_4460:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x51cef3 and fs2 == 0 and fe2 == 0x82 and fm2 == 0x1c2e3a and fs3 == 0 and fe3 == 0xc1 and fm3 == 0x780000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7dd1cef3; op2val:0x411c2e3a;
op3val:0x60f80000; valaddr_reg:x3; val_offset:13380*0 + 3*620*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 13380*0 + 3*620*FLEN/8, x4, x1, x2)

inst_4461:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x51cef3 and fs2 == 0 and fe2 == 0x82 and fm2 == 0x1c2e3a and fs3 == 0 and fe3 == 0xc1 and fm3 == 0x7c0000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7dd1cef3; op2val:0x411c2e3a;
op3val:0x60fc0000; valaddr_reg:x3; val_offset:13383*0 + 3*621*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 13383*0 + 3*621*FLEN/8, x4, x1, x2)

inst_4462:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x51cef3 and fs2 == 0 and fe2 == 0x82 and fm2 == 0x1c2e3a and fs3 == 0 and fe3 == 0xc1 and fm3 == 0x7e0000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7dd1cef3; op2val:0x411c2e3a;
op3val:0x60fe0000; valaddr_reg:x3; val_offset:13386*0 + 3*622*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 13386*0 + 3*622*FLEN/8, x4, x1, x2)

inst_4463:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x51cef3 and fs2 == 0 and fe2 == 0x82 and fm2 == 0x1c2e3a and fs3 == 0 and fe3 == 0xc1 and fm3 == 0x7f0000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7dd1cef3; op2val:0x411c2e3a;
op3val:0x60ff0000; valaddr_reg:x3; val_offset:13389*0 + 3*623*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 13389*0 + 3*623*FLEN/8, x4, x1, x2)

inst_4464:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x51cef3 and fs2 == 0 and fe2 == 0x82 and fm2 == 0x1c2e3a and fs3 == 0 and fe3 == 0xc1 and fm3 == 0x7f8000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7dd1cef3; op2val:0x411c2e3a;
op3val:0x60ff8000; valaddr_reg:x3; val_offset:13392*0 + 3*624*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 13392*0 + 3*624*FLEN/8, x4, x1, x2)

inst_4465:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x51cef3 and fs2 == 0 and fe2 == 0x82 and fm2 == 0x1c2e3a and fs3 == 0 and fe3 == 0xc1 and fm3 == 0x7fc000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7dd1cef3; op2val:0x411c2e3a;
op3val:0x60ffc000; valaddr_reg:x3; val_offset:13395*0 + 3*625*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 13395*0 + 3*625*FLEN/8, x4, x1, x2)

inst_4466:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x51cef3 and fs2 == 0 and fe2 == 0x82 and fm2 == 0x1c2e3a and fs3 == 0 and fe3 == 0xc1 and fm3 == 0x7fe000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7dd1cef3; op2val:0x411c2e3a;
op3val:0x60ffe000; valaddr_reg:x3; val_offset:13398*0 + 3*626*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 13398*0 + 3*626*FLEN/8, x4, x1, x2)

inst_4467:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x51cef3 and fs2 == 0 and fe2 == 0x82 and fm2 == 0x1c2e3a and fs3 == 0 and fe3 == 0xc1 and fm3 == 0x7ff000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7dd1cef3; op2val:0x411c2e3a;
op3val:0x60fff000; valaddr_reg:x3; val_offset:13401*0 + 3*627*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 13401*0 + 3*627*FLEN/8, x4, x1, x2)

inst_4468:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x51cef3 and fs2 == 0 and fe2 == 0x82 and fm2 == 0x1c2e3a and fs3 == 0 and fe3 == 0xc1 and fm3 == 0x7ff800 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7dd1cef3; op2val:0x411c2e3a;
op3val:0x60fff800; valaddr_reg:x3; val_offset:13404*0 + 3*628*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 13404*0 + 3*628*FLEN/8, x4, x1, x2)

inst_4469:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x51cef3 and fs2 == 0 and fe2 == 0x82 and fm2 == 0x1c2e3a and fs3 == 0 and fe3 == 0xc1 and fm3 == 0x7ffc00 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7dd1cef3; op2val:0x411c2e3a;
op3val:0x60fffc00; valaddr_reg:x3; val_offset:13407*0 + 3*629*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 13407*0 + 3*629*FLEN/8, x4, x1, x2)

inst_4470:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x51cef3 and fs2 == 0 and fe2 == 0x82 and fm2 == 0x1c2e3a and fs3 == 0 and fe3 == 0xc1 and fm3 == 0x7ffe00 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7dd1cef3; op2val:0x411c2e3a;
op3val:0x60fffe00; valaddr_reg:x3; val_offset:13410*0 + 3*630*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 13410*0 + 3*630*FLEN/8, x4, x1, x2)

inst_4471:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x51cef3 and fs2 == 0 and fe2 == 0x82 and fm2 == 0x1c2e3a and fs3 == 0 and fe3 == 0xc1 and fm3 == 0x7fff00 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7dd1cef3; op2val:0x411c2e3a;
op3val:0x60ffff00; valaddr_reg:x3; val_offset:13413*0 + 3*631*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 13413*0 + 3*631*FLEN/8, x4, x1, x2)

inst_4472:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x51cef3 and fs2 == 0 and fe2 == 0x82 and fm2 == 0x1c2e3a and fs3 == 0 and fe3 == 0xc1 and fm3 == 0x7fff80 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7dd1cef3; op2val:0x411c2e3a;
op3val:0x60ffff80; valaddr_reg:x3; val_offset:13416*0 + 3*632*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 13416*0 + 3*632*FLEN/8, x4, x1, x2)

inst_4473:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x51cef3 and fs2 == 0 and fe2 == 0x82 and fm2 == 0x1c2e3a and fs3 == 0 and fe3 == 0xc1 and fm3 == 0x7fffc0 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7dd1cef3; op2val:0x411c2e3a;
op3val:0x60ffffc0; valaddr_reg:x3; val_offset:13419*0 + 3*633*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 13419*0 + 3*633*FLEN/8, x4, x1, x2)

inst_4474:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x51cef3 and fs2 == 0 and fe2 == 0x82 and fm2 == 0x1c2e3a and fs3 == 0 and fe3 == 0xc1 and fm3 == 0x7fffe0 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7dd1cef3; op2val:0x411c2e3a;
op3val:0x60ffffe0; valaddr_reg:x3; val_offset:13422*0 + 3*634*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 13422*0 + 3*634*FLEN/8, x4, x1, x2)

inst_4475:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x51cef3 and fs2 == 0 and fe2 == 0x82 and fm2 == 0x1c2e3a and fs3 == 0 and fe3 == 0xc1 and fm3 == 0x7ffff0 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7dd1cef3; op2val:0x411c2e3a;
op3val:0x60fffff0; valaddr_reg:x3; val_offset:13425*0 + 3*635*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 13425*0 + 3*635*FLEN/8, x4, x1, x2)

inst_4476:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x51cef3 and fs2 == 0 and fe2 == 0x82 and fm2 == 0x1c2e3a and fs3 == 0 and fe3 == 0xc1 and fm3 == 0x7ffff8 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7dd1cef3; op2val:0x411c2e3a;
op3val:0x60fffff8; valaddr_reg:x3; val_offset:13428*0 + 3*636*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 13428*0 + 3*636*FLEN/8, x4, x1, x2)

inst_4477:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x51cef3 and fs2 == 0 and fe2 == 0x82 and fm2 == 0x1c2e3a and fs3 == 0 and fe3 == 0xc1 and fm3 == 0x7ffffc and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7dd1cef3; op2val:0x411c2e3a;
op3val:0x60fffffc; valaddr_reg:x3; val_offset:13431*0 + 3*637*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 13431*0 + 3*637*FLEN/8, x4, x1, x2)

inst_4478:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x51cef3 and fs2 == 0 and fe2 == 0x82 and fm2 == 0x1c2e3a and fs3 == 0 and fe3 == 0xc1 and fm3 == 0x7ffffe and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7dd1cef3; op2val:0x411c2e3a;
op3val:0x60fffffe; valaddr_reg:x3; val_offset:13434*0 + 3*638*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 13434*0 + 3*638*FLEN/8, x4, x1, x2)

inst_4479:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x51cef3 and fs2 == 0 and fe2 == 0x82 and fm2 == 0x1c2e3a and fs3 == 0 and fe3 == 0xc1 and fm3 == 0x7fffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7dd1cef3; op2val:0x411c2e3a;
op3val:0x60ffffff; valaddr_reg:x3; val_offset:13437*0 + 3*639*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 13437*0 + 3*639*FLEN/8, x4, x1, x2)
RVTEST_SIGBASE(x1,signature_x1_6)

inst_4480:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x51cef3 and fs2 == 0 and fe2 == 0x82 and fm2 == 0x1c2e3a and fs3 == 0 and fe3 == 0xfe and fm3 == 0x000001 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7dd1cef3; op2val:0x411c2e3a;
op3val:0x7f000001; valaddr_reg:x3; val_offset:13440*0 + 3*640*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 13440*0 + 3*640*FLEN/8, x4, x1, x2)

inst_4481:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x51cef3 and fs2 == 0 and fe2 == 0x82 and fm2 == 0x1c2e3a and fs3 == 0 and fe3 == 0xfe and fm3 == 0x000003 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7dd1cef3; op2val:0x411c2e3a;
op3val:0x7f000003; valaddr_reg:x3; val_offset:13443*0 + 3*641*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 13443*0 + 3*641*FLEN/8, x4, x1, x2)

inst_4482:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x51cef3 and fs2 == 0 and fe2 == 0x82 and fm2 == 0x1c2e3a and fs3 == 0 and fe3 == 0xfe and fm3 == 0x000007 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7dd1cef3; op2val:0x411c2e3a;
op3val:0x7f000007; valaddr_reg:x3; val_offset:13446*0 + 3*642*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 13446*0 + 3*642*FLEN/8, x4, x1, x2)

inst_4483:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x51cef3 and fs2 == 0 and fe2 == 0x82 and fm2 == 0x1c2e3a and fs3 == 0 and fe3 == 0xfe and fm3 == 0x199999 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7dd1cef3; op2val:0x411c2e3a;
op3val:0x7f199999; valaddr_reg:x3; val_offset:13449*0 + 3*643*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 13449*0 + 3*643*FLEN/8, x4, x1, x2)

inst_4484:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x51cef3 and fs2 == 0 and fe2 == 0x82 and fm2 == 0x1c2e3a and fs3 == 0 and fe3 == 0xfe and fm3 == 0x249249 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7dd1cef3; op2val:0x411c2e3a;
op3val:0x7f249249; valaddr_reg:x3; val_offset:13452*0 + 3*644*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 13452*0 + 3*644*FLEN/8, x4, x1, x2)

inst_4485:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x51cef3 and fs2 == 0 and fe2 == 0x82 and fm2 == 0x1c2e3a and fs3 == 0 and fe3 == 0xfe and fm3 == 0x333333 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7dd1cef3; op2val:0x411c2e3a;
op3val:0x7f333333; valaddr_reg:x3; val_offset:13455*0 + 3*645*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 13455*0 + 3*645*FLEN/8, x4, x1, x2)

inst_4486:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x51cef3 and fs2 == 0 and fe2 == 0x82 and fm2 == 0x1c2e3a and fs3 == 0 and fe3 == 0xfe and fm3 == 0x36db6d and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7dd1cef3; op2val:0x411c2e3a;
op3val:0x7f36db6d; valaddr_reg:x3; val_offset:13458*0 + 3*646*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 13458*0 + 3*646*FLEN/8, x4, x1, x2)

inst_4487:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x51cef3 and fs2 == 0 and fe2 == 0x82 and fm2 == 0x1c2e3a and fs3 == 0 and fe3 == 0xfe and fm3 == 0x3bbbbb and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7dd1cef3; op2val:0x411c2e3a;
op3val:0x7f3bbbbb; valaddr_reg:x3; val_offset:13461*0 + 3*647*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 13461*0 + 3*647*FLEN/8, x4, x1, x2)

inst_4488:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x51cef3 and fs2 == 0 and fe2 == 0x82 and fm2 == 0x1c2e3a and fs3 == 0 and fe3 == 0xfe and fm3 == 0x444444 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7dd1cef3; op2val:0x411c2e3a;
op3val:0x7f444444; valaddr_reg:x3; val_offset:13464*0 + 3*648*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 13464*0 + 3*648*FLEN/8, x4, x1, x2)

inst_4489:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x51cef3 and fs2 == 0 and fe2 == 0x82 and fm2 == 0x1c2e3a and fs3 == 0 and fe3 == 0xfe and fm3 == 0x4ccccc and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7dd1cef3; op2val:0x411c2e3a;
op3val:0x7f4ccccc; valaddr_reg:x3; val_offset:13467*0 + 3*649*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 13467*0 + 3*649*FLEN/8, x4, x1, x2)

inst_4490:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x51cef3 and fs2 == 0 and fe2 == 0x82 and fm2 == 0x1c2e3a and fs3 == 0 and fe3 == 0xfe and fm3 == 0x5b6db6 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7dd1cef3; op2val:0x411c2e3a;
op3val:0x7f5b6db6; valaddr_reg:x3; val_offset:13470*0 + 3*650*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 13470*0 + 3*650*FLEN/8, x4, x1, x2)

inst_4491:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x51cef3 and fs2 == 0 and fe2 == 0x82 and fm2 == 0x1c2e3a and fs3 == 0 and fe3 == 0xfe and fm3 == 0x666666 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7dd1cef3; op2val:0x411c2e3a;
op3val:0x7f666666; valaddr_reg:x3; val_offset:13473*0 + 3*651*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 13473*0 + 3*651*FLEN/8, x4, x1, x2)

inst_4492:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x51cef3 and fs2 == 0 and fe2 == 0x82 and fm2 == 0x1c2e3a and fs3 == 0 and fe3 == 0xfe and fm3 == 0x6db6db and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7dd1cef3; op2val:0x411c2e3a;
op3val:0x7f6db6db; valaddr_reg:x3; val_offset:13476*0 + 3*652*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 13476*0 + 3*652*FLEN/8, x4, x1, x2)

inst_4493:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x51cef3 and fs2 == 0 and fe2 == 0x82 and fm2 == 0x1c2e3a and fs3 == 0 and fe3 == 0xfe and fm3 == 0x7ffff8 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7dd1cef3; op2val:0x411c2e3a;
op3val:0x7f7ffff8; valaddr_reg:x3; val_offset:13479*0 + 3*653*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 13479*0 + 3*653*FLEN/8, x4, x1, x2)

inst_4494:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x51cef3 and fs2 == 0 and fe2 == 0x82 and fm2 == 0x1c2e3a and fs3 == 0 and fe3 == 0xfe and fm3 == 0x7ffffc and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7dd1cef3; op2val:0x411c2e3a;
op3val:0x7f7ffffc; valaddr_reg:x3; val_offset:13482*0 + 3*654*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 13482*0 + 3*654*FLEN/8, x4, x1, x2)

inst_4495:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x51cef3 and fs2 == 0 and fe2 == 0x82 and fm2 == 0x1c2e3a and fs3 == 0 and fe3 == 0xfe and fm3 == 0x7ffffe and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7dd1cef3; op2val:0x411c2e3a;
op3val:0x7f7ffffe; valaddr_reg:x3; val_offset:13485*0 + 3*655*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 13485*0 + 3*655*FLEN/8, x4, x1, x2)

inst_4496:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x546786 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000001 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7dd46786; op2val:0x0;
op3val:0x1; valaddr_reg:x3; val_offset:13488*0 + 3*656*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 13488*0 + 3*656*FLEN/8, x4, x1, x2)

inst_4497:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x546786 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000003 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7dd46786; op2val:0x0;
op3val:0x3; valaddr_reg:x3; val_offset:13491*0 + 3*657*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 13491*0 + 3*657*FLEN/8, x4, x1, x2)

inst_4498:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x546786 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000007 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7dd46786; op2val:0x0;
op3val:0x7; valaddr_reg:x3; val_offset:13494*0 + 3*658*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 13494*0 + 3*658*FLEN/8, x4, x1, x2)

inst_4499:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x546786 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x199999 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7dd46786; op2val:0x0;
op3val:0x199999; valaddr_reg:x3; val_offset:13497*0 + 3*659*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 13497*0 + 3*659*FLEN/8, x4, x1, x2)

inst_4500:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x546786 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x249249 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7dd46786; op2val:0x0;
op3val:0x249249; valaddr_reg:x3; val_offset:13500*0 + 3*660*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 13500*0 + 3*660*FLEN/8, x4, x1, x2)

inst_4501:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x546786 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x333333 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7dd46786; op2val:0x0;
op3val:0x333333; valaddr_reg:x3; val_offset:13503*0 + 3*661*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 13503*0 + 3*661*FLEN/8, x4, x1, x2)

inst_4502:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x546786 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x36db6d and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7dd46786; op2val:0x0;
op3val:0x36db6d; valaddr_reg:x3; val_offset:13506*0 + 3*662*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 13506*0 + 3*662*FLEN/8, x4, x1, x2)

inst_4503:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x546786 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x3bbbbb and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7dd46786; op2val:0x0;
op3val:0x3bbbbb; valaddr_reg:x3; val_offset:13509*0 + 3*663*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 13509*0 + 3*663*FLEN/8, x4, x1, x2)

inst_4504:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x546786 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x444444 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7dd46786; op2val:0x0;
op3val:0x444444; valaddr_reg:x3; val_offset:13512*0 + 3*664*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 13512*0 + 3*664*FLEN/8, x4, x1, x2)

inst_4505:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x546786 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x4ccccc and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7dd46786; op2val:0x0;
op3val:0x4ccccc; valaddr_reg:x3; val_offset:13515*0 + 3*665*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 13515*0 + 3*665*FLEN/8, x4, x1, x2)

inst_4506:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x546786 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x5b6db6 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7dd46786; op2val:0x0;
op3val:0x5b6db6; valaddr_reg:x3; val_offset:13518*0 + 3*666*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 13518*0 + 3*666*FLEN/8, x4, x1, x2)

inst_4507:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x546786 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x666666 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7dd46786; op2val:0x0;
op3val:0x666666; valaddr_reg:x3; val_offset:13521*0 + 3*667*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 13521*0 + 3*667*FLEN/8, x4, x1, x2)

inst_4508:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x546786 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x6db6db and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7dd46786; op2val:0x0;
op3val:0x6db6db; valaddr_reg:x3; val_offset:13524*0 + 3*668*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 13524*0 + 3*668*FLEN/8, x4, x1, x2)

inst_4509:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x546786 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x7ffff8 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7dd46786; op2val:0x0;
op3val:0x7ffff8; valaddr_reg:x3; val_offset:13527*0 + 3*669*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 13527*0 + 3*669*FLEN/8, x4, x1, x2)

inst_4510:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x546786 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x7ffffc and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7dd46786; op2val:0x0;
op3val:0x7ffffc; valaddr_reg:x3; val_offset:13530*0 + 3*670*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 13530*0 + 3*670*FLEN/8, x4, x1, x2)

inst_4511:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x546786 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x7ffffe and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7dd46786; op2val:0x0;
op3val:0x7ffffe; valaddr_reg:x3; val_offset:13533*0 + 3*671*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 13533*0 + 3*671*FLEN/8, x4, x1, x2)

inst_4512:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x546786 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x20 and fm3 == 0x000000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7dd46786; op2val:0x0;
op3val:0x10000000; valaddr_reg:x3; val_offset:13536*0 + 3*672*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 13536*0 + 3*672*FLEN/8, x4, x1, x2)

inst_4513:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x546786 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x20 and fm3 == 0x000001 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7dd46786; op2val:0x0;
op3val:0x10000001; valaddr_reg:x3; val_offset:13539*0 + 3*673*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 13539*0 + 3*673*FLEN/8, x4, x1, x2)

inst_4514:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x546786 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x20 and fm3 == 0x000003 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7dd46786; op2val:0x0;
op3val:0x10000003; valaddr_reg:x3; val_offset:13542*0 + 3*674*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 13542*0 + 3*674*FLEN/8, x4, x1, x2)

inst_4515:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x546786 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x20 and fm3 == 0x000007 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7dd46786; op2val:0x0;
op3val:0x10000007; valaddr_reg:x3; val_offset:13545*0 + 3*675*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 13545*0 + 3*675*FLEN/8, x4, x1, x2)

inst_4516:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x546786 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x20 and fm3 == 0x00000f and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7dd46786; op2val:0x0;
op3val:0x1000000f; valaddr_reg:x3; val_offset:13548*0 + 3*676*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 13548*0 + 3*676*FLEN/8, x4, x1, x2)

inst_4517:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x546786 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x20 and fm3 == 0x00001f and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7dd46786; op2val:0x0;
op3val:0x1000001f; valaddr_reg:x3; val_offset:13551*0 + 3*677*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 13551*0 + 3*677*FLEN/8, x4, x1, x2)

inst_4518:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x546786 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x20 and fm3 == 0x00003f and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7dd46786; op2val:0x0;
op3val:0x1000003f; valaddr_reg:x3; val_offset:13554*0 + 3*678*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 13554*0 + 3*678*FLEN/8, x4, x1, x2)

inst_4519:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x546786 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x20 and fm3 == 0x00007f and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7dd46786; op2val:0x0;
op3val:0x1000007f; valaddr_reg:x3; val_offset:13557*0 + 3*679*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 13557*0 + 3*679*FLEN/8, x4, x1, x2)

inst_4520:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x546786 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x20 and fm3 == 0x0000ff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7dd46786; op2val:0x0;
op3val:0x100000ff; valaddr_reg:x3; val_offset:13560*0 + 3*680*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 13560*0 + 3*680*FLEN/8, x4, x1, x2)

inst_4521:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x546786 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x20 and fm3 == 0x0001ff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7dd46786; op2val:0x0;
op3val:0x100001ff; valaddr_reg:x3; val_offset:13563*0 + 3*681*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 13563*0 + 3*681*FLEN/8, x4, x1, x2)

inst_4522:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x546786 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x20 and fm3 == 0x0003ff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7dd46786; op2val:0x0;
op3val:0x100003ff; valaddr_reg:x3; val_offset:13566*0 + 3*682*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 13566*0 + 3*682*FLEN/8, x4, x1, x2)

inst_4523:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x546786 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x20 and fm3 == 0x0007ff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7dd46786; op2val:0x0;
op3val:0x100007ff; valaddr_reg:x3; val_offset:13569*0 + 3*683*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 13569*0 + 3*683*FLEN/8, x4, x1, x2)

inst_4524:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x546786 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x20 and fm3 == 0x000fff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7dd46786; op2val:0x0;
op3val:0x10000fff; valaddr_reg:x3; val_offset:13572*0 + 3*684*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 13572*0 + 3*684*FLEN/8, x4, x1, x2)

inst_4525:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x546786 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x20 and fm3 == 0x001fff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7dd46786; op2val:0x0;
op3val:0x10001fff; valaddr_reg:x3; val_offset:13575*0 + 3*685*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 13575*0 + 3*685*FLEN/8, x4, x1, x2)

inst_4526:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x546786 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x20 and fm3 == 0x003fff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7dd46786; op2val:0x0;
op3val:0x10003fff; valaddr_reg:x3; val_offset:13578*0 + 3*686*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 13578*0 + 3*686*FLEN/8, x4, x1, x2)

inst_4527:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x546786 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x20 and fm3 == 0x007fff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7dd46786; op2val:0x0;
op3val:0x10007fff; valaddr_reg:x3; val_offset:13581*0 + 3*687*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 13581*0 + 3*687*FLEN/8, x4, x1, x2)

inst_4528:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x546786 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x20 and fm3 == 0x00ffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7dd46786; op2val:0x0;
op3val:0x1000ffff; valaddr_reg:x3; val_offset:13584*0 + 3*688*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 13584*0 + 3*688*FLEN/8, x4, x1, x2)

inst_4529:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x546786 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x20 and fm3 == 0x01ffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7dd46786; op2val:0x0;
op3val:0x1001ffff; valaddr_reg:x3; val_offset:13587*0 + 3*689*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 13587*0 + 3*689*FLEN/8, x4, x1, x2)

inst_4530:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x546786 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x20 and fm3 == 0x03ffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7dd46786; op2val:0x0;
op3val:0x1003ffff; valaddr_reg:x3; val_offset:13590*0 + 3*690*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 13590*0 + 3*690*FLEN/8, x4, x1, x2)

inst_4531:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x546786 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x20 and fm3 == 0x07ffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7dd46786; op2val:0x0;
op3val:0x1007ffff; valaddr_reg:x3; val_offset:13593*0 + 3*691*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 13593*0 + 3*691*FLEN/8, x4, x1, x2)

inst_4532:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x546786 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x20 and fm3 == 0x0fffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7dd46786; op2val:0x0;
op3val:0x100fffff; valaddr_reg:x3; val_offset:13596*0 + 3*692*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 13596*0 + 3*692*FLEN/8, x4, x1, x2)

inst_4533:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x546786 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x20 and fm3 == 0x1fffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7dd46786; op2val:0x0;
op3val:0x101fffff; valaddr_reg:x3; val_offset:13599*0 + 3*693*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 13599*0 + 3*693*FLEN/8, x4, x1, x2)

inst_4534:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x546786 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x20 and fm3 == 0x3fffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7dd46786; op2val:0x0;
op3val:0x103fffff; valaddr_reg:x3; val_offset:13602*0 + 3*694*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 13602*0 + 3*694*FLEN/8, x4, x1, x2)

inst_4535:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x546786 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x20 and fm3 == 0x400000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7dd46786; op2val:0x0;
op3val:0x10400000; valaddr_reg:x3; val_offset:13605*0 + 3*695*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 13605*0 + 3*695*FLEN/8, x4, x1, x2)

inst_4536:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x546786 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x20 and fm3 == 0x600000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7dd46786; op2val:0x0;
op3val:0x10600000; valaddr_reg:x3; val_offset:13608*0 + 3*696*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 13608*0 + 3*696*FLEN/8, x4, x1, x2)

inst_4537:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x546786 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x20 and fm3 == 0x700000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7dd46786; op2val:0x0;
op3val:0x10700000; valaddr_reg:x3; val_offset:13611*0 + 3*697*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 13611*0 + 3*697*FLEN/8, x4, x1, x2)

inst_4538:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x546786 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x20 and fm3 == 0x780000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7dd46786; op2val:0x0;
op3val:0x10780000; valaddr_reg:x3; val_offset:13614*0 + 3*698*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 13614*0 + 3*698*FLEN/8, x4, x1, x2)

inst_4539:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x546786 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x20 and fm3 == 0x7c0000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7dd46786; op2val:0x0;
op3val:0x107c0000; valaddr_reg:x3; val_offset:13617*0 + 3*699*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 13617*0 + 3*699*FLEN/8, x4, x1, x2)

inst_4540:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x546786 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x20 and fm3 == 0x7e0000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7dd46786; op2val:0x0;
op3val:0x107e0000; valaddr_reg:x3; val_offset:13620*0 + 3*700*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 13620*0 + 3*700*FLEN/8, x4, x1, x2)

inst_4541:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x546786 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x20 and fm3 == 0x7f0000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7dd46786; op2val:0x0;
op3val:0x107f0000; valaddr_reg:x3; val_offset:13623*0 + 3*701*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 13623*0 + 3*701*FLEN/8, x4, x1, x2)

inst_4542:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x546786 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x20 and fm3 == 0x7f8000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7dd46786; op2val:0x0;
op3val:0x107f8000; valaddr_reg:x3; val_offset:13626*0 + 3*702*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 13626*0 + 3*702*FLEN/8, x4, x1, x2)

inst_4543:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x546786 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x20 and fm3 == 0x7fc000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7dd46786; op2val:0x0;
op3val:0x107fc000; valaddr_reg:x3; val_offset:13629*0 + 3*703*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 13629*0 + 3*703*FLEN/8, x4, x1, x2)

inst_4544:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x546786 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x20 and fm3 == 0x7fe000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7dd46786; op2val:0x0;
op3val:0x107fe000; valaddr_reg:x3; val_offset:13632*0 + 3*704*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 13632*0 + 3*704*FLEN/8, x4, x1, x2)

inst_4545:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x546786 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x20 and fm3 == 0x7ff000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7dd46786; op2val:0x0;
op3val:0x107ff000; valaddr_reg:x3; val_offset:13635*0 + 3*705*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 13635*0 + 3*705*FLEN/8, x4, x1, x2)

inst_4546:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x546786 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x20 and fm3 == 0x7ff800 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7dd46786; op2val:0x0;
op3val:0x107ff800; valaddr_reg:x3; val_offset:13638*0 + 3*706*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 13638*0 + 3*706*FLEN/8, x4, x1, x2)

inst_4547:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x546786 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x20 and fm3 == 0x7ffc00 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7dd46786; op2val:0x0;
op3val:0x107ffc00; valaddr_reg:x3; val_offset:13641*0 + 3*707*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 13641*0 + 3*707*FLEN/8, x4, x1, x2)

inst_4548:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x546786 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x20 and fm3 == 0x7ffe00 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7dd46786; op2val:0x0;
op3val:0x107ffe00; valaddr_reg:x3; val_offset:13644*0 + 3*708*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 13644*0 + 3*708*FLEN/8, x4, x1, x2)

inst_4549:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x546786 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x20 and fm3 == 0x7fff00 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7dd46786; op2val:0x0;
op3val:0x107fff00; valaddr_reg:x3; val_offset:13647*0 + 3*709*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 13647*0 + 3*709*FLEN/8, x4, x1, x2)

inst_4550:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x546786 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x20 and fm3 == 0x7fff80 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7dd46786; op2val:0x0;
op3val:0x107fff80; valaddr_reg:x3; val_offset:13650*0 + 3*710*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 13650*0 + 3*710*FLEN/8, x4, x1, x2)

inst_4551:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x546786 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x20 and fm3 == 0x7fffc0 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7dd46786; op2val:0x0;
op3val:0x107fffc0; valaddr_reg:x3; val_offset:13653*0 + 3*711*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 13653*0 + 3*711*FLEN/8, x4, x1, x2)

inst_4552:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x546786 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x20 and fm3 == 0x7fffe0 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7dd46786; op2val:0x0;
op3val:0x107fffe0; valaddr_reg:x3; val_offset:13656*0 + 3*712*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 13656*0 + 3*712*FLEN/8, x4, x1, x2)

inst_4553:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x546786 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x20 and fm3 == 0x7ffff0 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7dd46786; op2val:0x0;
op3val:0x107ffff0; valaddr_reg:x3; val_offset:13659*0 + 3*713*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 13659*0 + 3*713*FLEN/8, x4, x1, x2)

inst_4554:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x546786 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x20 and fm3 == 0x7ffff8 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7dd46786; op2val:0x0;
op3val:0x107ffff8; valaddr_reg:x3; val_offset:13662*0 + 3*714*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 13662*0 + 3*714*FLEN/8, x4, x1, x2)

inst_4555:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x546786 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x20 and fm3 == 0x7ffffc and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7dd46786; op2val:0x0;
op3val:0x107ffffc; valaddr_reg:x3; val_offset:13665*0 + 3*715*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 13665*0 + 3*715*FLEN/8, x4, x1, x2)

inst_4556:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x546786 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x20 and fm3 == 0x7ffffe and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7dd46786; op2val:0x0;
op3val:0x107ffffe; valaddr_reg:x3; val_offset:13668*0 + 3*716*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 13668*0 + 3*716*FLEN/8, x4, x1, x2)

inst_4557:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x546786 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x20 and fm3 == 0x7fffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7dd46786; op2val:0x0;
op3val:0x107fffff; valaddr_reg:x3; val_offset:13671*0 + 3*717*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 13671*0 + 3*717*FLEN/8, x4, x1, x2)

inst_4558:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x55b2a1 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000001 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7dd5b2a1; op2val:0x0;
op3val:0x800001; valaddr_reg:x3; val_offset:13674*0 + 3*718*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 13674*0 + 3*718*FLEN/8, x4, x1, x2)

inst_4559:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x55b2a1 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000003 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7dd5b2a1; op2val:0x0;
op3val:0x800003; valaddr_reg:x3; val_offset:13677*0 + 3*719*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 13677*0 + 3*719*FLEN/8, x4, x1, x2)

inst_4560:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x55b2a1 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000007 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7dd5b2a1; op2val:0x0;
op3val:0x800007; valaddr_reg:x3; val_offset:13680*0 + 3*720*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 13680*0 + 3*720*FLEN/8, x4, x1, x2)

inst_4561:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x55b2a1 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x199999 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7dd5b2a1; op2val:0x0;
op3val:0x999999; valaddr_reg:x3; val_offset:13683*0 + 3*721*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 13683*0 + 3*721*FLEN/8, x4, x1, x2)

inst_4562:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x55b2a1 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x249249 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7dd5b2a1; op2val:0x0;
op3val:0xa49249; valaddr_reg:x3; val_offset:13686*0 + 3*722*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 13686*0 + 3*722*FLEN/8, x4, x1, x2)

inst_4563:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x55b2a1 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x333333 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7dd5b2a1; op2val:0x0;
op3val:0xb33333; valaddr_reg:x3; val_offset:13689*0 + 3*723*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 13689*0 + 3*723*FLEN/8, x4, x1, x2)

inst_4564:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x55b2a1 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x36db6d and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7dd5b2a1; op2val:0x0;
op3val:0xb6db6d; valaddr_reg:x3; val_offset:13692*0 + 3*724*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 13692*0 + 3*724*FLEN/8, x4, x1, x2)

inst_4565:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x55b2a1 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x3bbbbb and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7dd5b2a1; op2val:0x0;
op3val:0xbbbbbb; valaddr_reg:x3; val_offset:13695*0 + 3*725*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 13695*0 + 3*725*FLEN/8, x4, x1, x2)

inst_4566:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x55b2a1 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x444444 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7dd5b2a1; op2val:0x0;
op3val:0xc44444; valaddr_reg:x3; val_offset:13698*0 + 3*726*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 13698*0 + 3*726*FLEN/8, x4, x1, x2)

inst_4567:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x55b2a1 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x4ccccc and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7dd5b2a1; op2val:0x0;
op3val:0xcccccc; valaddr_reg:x3; val_offset:13701*0 + 3*727*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 13701*0 + 3*727*FLEN/8, x4, x1, x2)

inst_4568:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x55b2a1 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x5b6db6 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7dd5b2a1; op2val:0x0;
op3val:0xdb6db6; valaddr_reg:x3; val_offset:13704*0 + 3*728*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 13704*0 + 3*728*FLEN/8, x4, x1, x2)

inst_4569:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x55b2a1 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x666666 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7dd5b2a1; op2val:0x0;
op3val:0xe66666; valaddr_reg:x3; val_offset:13707*0 + 3*729*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 13707*0 + 3*729*FLEN/8, x4, x1, x2)

inst_4570:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x55b2a1 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x6db6db and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7dd5b2a1; op2val:0x0;
op3val:0xedb6db; valaddr_reg:x3; val_offset:13710*0 + 3*730*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 13710*0 + 3*730*FLEN/8, x4, x1, x2)

inst_4571:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x55b2a1 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x7ffff8 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7dd5b2a1; op2val:0x0;
op3val:0xfffff8; valaddr_reg:x3; val_offset:13713*0 + 3*731*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 13713*0 + 3*731*FLEN/8, x4, x1, x2)

inst_4572:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x55b2a1 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x7ffffc and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7dd5b2a1; op2val:0x0;
op3val:0xfffffc; valaddr_reg:x3; val_offset:13716*0 + 3*732*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 13716*0 + 3*732*FLEN/8, x4, x1, x2)

inst_4573:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x55b2a1 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x7ffffe and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7dd5b2a1; op2val:0x0;
op3val:0xfffffe; valaddr_reg:x3; val_offset:13719*0 + 3*733*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 13719*0 + 3*733*FLEN/8, x4, x1, x2)

inst_4574:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x55b2a1 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x17 and fm3 == 0x000000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7dd5b2a1; op2val:0x0;
op3val:0xb800000; valaddr_reg:x3; val_offset:13722*0 + 3*734*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 13722*0 + 3*734*FLEN/8, x4, x1, x2)

inst_4575:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x55b2a1 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x17 and fm3 == 0x000001 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7dd5b2a1; op2val:0x0;
op3val:0xb800001; valaddr_reg:x3; val_offset:13725*0 + 3*735*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 13725*0 + 3*735*FLEN/8, x4, x1, x2)

inst_4576:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x55b2a1 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x17 and fm3 == 0x000003 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7dd5b2a1; op2val:0x0;
op3val:0xb800003; valaddr_reg:x3; val_offset:13728*0 + 3*736*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 13728*0 + 3*736*FLEN/8, x4, x1, x2)

inst_4577:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x55b2a1 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x17 and fm3 == 0x000007 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7dd5b2a1; op2val:0x0;
op3val:0xb800007; valaddr_reg:x3; val_offset:13731*0 + 3*737*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 13731*0 + 3*737*FLEN/8, x4, x1, x2)

inst_4578:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x55b2a1 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x17 and fm3 == 0x00000f and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7dd5b2a1; op2val:0x0;
op3val:0xb80000f; valaddr_reg:x3; val_offset:13734*0 + 3*738*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 13734*0 + 3*738*FLEN/8, x4, x1, x2)

inst_4579:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x55b2a1 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x17 and fm3 == 0x00001f and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7dd5b2a1; op2val:0x0;
op3val:0xb80001f; valaddr_reg:x3; val_offset:13737*0 + 3*739*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 13737*0 + 3*739*FLEN/8, x4, x1, x2)

inst_4580:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x55b2a1 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x17 and fm3 == 0x00003f and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7dd5b2a1; op2val:0x0;
op3val:0xb80003f; valaddr_reg:x3; val_offset:13740*0 + 3*740*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 13740*0 + 3*740*FLEN/8, x4, x1, x2)

inst_4581:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x55b2a1 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x17 and fm3 == 0x00007f and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7dd5b2a1; op2val:0x0;
op3val:0xb80007f; valaddr_reg:x3; val_offset:13743*0 + 3*741*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 13743*0 + 3*741*FLEN/8, x4, x1, x2)

inst_4582:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x55b2a1 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x17 and fm3 == 0x0000ff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7dd5b2a1; op2val:0x0;
op3val:0xb8000ff; valaddr_reg:x3; val_offset:13746*0 + 3*742*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 13746*0 + 3*742*FLEN/8, x4, x1, x2)

inst_4583:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x55b2a1 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x17 and fm3 == 0x0001ff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7dd5b2a1; op2val:0x0;
op3val:0xb8001ff; valaddr_reg:x3; val_offset:13749*0 + 3*743*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 13749*0 + 3*743*FLEN/8, x4, x1, x2)

inst_4584:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x55b2a1 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x17 and fm3 == 0x0003ff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7dd5b2a1; op2val:0x0;
op3val:0xb8003ff; valaddr_reg:x3; val_offset:13752*0 + 3*744*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 13752*0 + 3*744*FLEN/8, x4, x1, x2)

inst_4585:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x55b2a1 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x17 and fm3 == 0x0007ff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7dd5b2a1; op2val:0x0;
op3val:0xb8007ff; valaddr_reg:x3; val_offset:13755*0 + 3*745*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 13755*0 + 3*745*FLEN/8, x4, x1, x2)

inst_4586:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x55b2a1 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x17 and fm3 == 0x000fff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7dd5b2a1; op2val:0x0;
op3val:0xb800fff; valaddr_reg:x3; val_offset:13758*0 + 3*746*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 13758*0 + 3*746*FLEN/8, x4, x1, x2)

inst_4587:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x55b2a1 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x17 and fm3 == 0x001fff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7dd5b2a1; op2val:0x0;
op3val:0xb801fff; valaddr_reg:x3; val_offset:13761*0 + 3*747*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 13761*0 + 3*747*FLEN/8, x4, x1, x2)

inst_4588:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x55b2a1 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x17 and fm3 == 0x003fff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7dd5b2a1; op2val:0x0;
op3val:0xb803fff; valaddr_reg:x3; val_offset:13764*0 + 3*748*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 13764*0 + 3*748*FLEN/8, x4, x1, x2)

inst_4589:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x55b2a1 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x17 and fm3 == 0x007fff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7dd5b2a1; op2val:0x0;
op3val:0xb807fff; valaddr_reg:x3; val_offset:13767*0 + 3*749*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 13767*0 + 3*749*FLEN/8, x4, x1, x2)

inst_4590:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x55b2a1 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x17 and fm3 == 0x00ffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7dd5b2a1; op2val:0x0;
op3val:0xb80ffff; valaddr_reg:x3; val_offset:13770*0 + 3*750*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 13770*0 + 3*750*FLEN/8, x4, x1, x2)

inst_4591:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x55b2a1 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x17 and fm3 == 0x01ffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7dd5b2a1; op2val:0x0;
op3val:0xb81ffff; valaddr_reg:x3; val_offset:13773*0 + 3*751*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 13773*0 + 3*751*FLEN/8, x4, x1, x2)

inst_4592:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x55b2a1 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x17 and fm3 == 0x03ffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7dd5b2a1; op2val:0x0;
op3val:0xb83ffff; valaddr_reg:x3; val_offset:13776*0 + 3*752*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 13776*0 + 3*752*FLEN/8, x4, x1, x2)

inst_4593:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x55b2a1 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x17 and fm3 == 0x07ffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7dd5b2a1; op2val:0x0;
op3val:0xb87ffff; valaddr_reg:x3; val_offset:13779*0 + 3*753*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 13779*0 + 3*753*FLEN/8, x4, x1, x2)

inst_4594:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x55b2a1 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x17 and fm3 == 0x0fffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7dd5b2a1; op2val:0x0;
op3val:0xb8fffff; valaddr_reg:x3; val_offset:13782*0 + 3*754*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 13782*0 + 3*754*FLEN/8, x4, x1, x2)

inst_4595:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x55b2a1 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x17 and fm3 == 0x1fffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7dd5b2a1; op2val:0x0;
op3val:0xb9fffff; valaddr_reg:x3; val_offset:13785*0 + 3*755*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 13785*0 + 3*755*FLEN/8, x4, x1, x2)

inst_4596:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x55b2a1 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x17 and fm3 == 0x3fffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7dd5b2a1; op2val:0x0;
op3val:0xbbfffff; valaddr_reg:x3; val_offset:13788*0 + 3*756*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 13788*0 + 3*756*FLEN/8, x4, x1, x2)

inst_4597:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x55b2a1 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x17 and fm3 == 0x400000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7dd5b2a1; op2val:0x0;
op3val:0xbc00000; valaddr_reg:x3; val_offset:13791*0 + 3*757*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 13791*0 + 3*757*FLEN/8, x4, x1, x2)

inst_4598:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x55b2a1 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x17 and fm3 == 0x600000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7dd5b2a1; op2val:0x0;
op3val:0xbe00000; valaddr_reg:x3; val_offset:13794*0 + 3*758*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 13794*0 + 3*758*FLEN/8, x4, x1, x2)

inst_4599:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x55b2a1 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x17 and fm3 == 0x700000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7dd5b2a1; op2val:0x0;
op3val:0xbf00000; valaddr_reg:x3; val_offset:13797*0 + 3*759*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 13797*0 + 3*759*FLEN/8, x4, x1, x2)

inst_4600:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x55b2a1 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x17 and fm3 == 0x780000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7dd5b2a1; op2val:0x0;
op3val:0xbf80000; valaddr_reg:x3; val_offset:13800*0 + 3*760*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 13800*0 + 3*760*FLEN/8, x4, x1, x2)

inst_4601:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x55b2a1 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x17 and fm3 == 0x7c0000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7dd5b2a1; op2val:0x0;
op3val:0xbfc0000; valaddr_reg:x3; val_offset:13803*0 + 3*761*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 13803*0 + 3*761*FLEN/8, x4, x1, x2)

inst_4602:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x55b2a1 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x17 and fm3 == 0x7e0000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7dd5b2a1; op2val:0x0;
op3val:0xbfe0000; valaddr_reg:x3; val_offset:13806*0 + 3*762*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 13806*0 + 3*762*FLEN/8, x4, x1, x2)

inst_4603:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x55b2a1 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x17 and fm3 == 0x7f0000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7dd5b2a1; op2val:0x0;
op3val:0xbff0000; valaddr_reg:x3; val_offset:13809*0 + 3*763*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 13809*0 + 3*763*FLEN/8, x4, x1, x2)

inst_4604:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x55b2a1 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x17 and fm3 == 0x7f8000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7dd5b2a1; op2val:0x0;
op3val:0xbff8000; valaddr_reg:x3; val_offset:13812*0 + 3*764*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 13812*0 + 3*764*FLEN/8, x4, x1, x2)

inst_4605:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x55b2a1 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x17 and fm3 == 0x7fc000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7dd5b2a1; op2val:0x0;
op3val:0xbffc000; valaddr_reg:x3; val_offset:13815*0 + 3*765*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 13815*0 + 3*765*FLEN/8, x4, x1, x2)

inst_4606:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x55b2a1 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x17 and fm3 == 0x7fe000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7dd5b2a1; op2val:0x0;
op3val:0xbffe000; valaddr_reg:x3; val_offset:13818*0 + 3*766*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 13818*0 + 3*766*FLEN/8, x4, x1, x2)

inst_4607:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x55b2a1 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x17 and fm3 == 0x7ff000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7dd5b2a1; op2val:0x0;
op3val:0xbfff000; valaddr_reg:x3; val_offset:13821*0 + 3*767*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 13821*0 + 3*767*FLEN/8, x4, x1, x2)
#endif


RVTEST_CODE_END
RVMODEL_HALT

RVTEST_DATA_BEGIN
.align 4
rvtest_data:
.word 0xbabecafe
.word 0xabecafeb
.word 0xbecafeba
.word 0xecafebab
test_dataset_0:
NAN_BOXED(0x7db55b9c,32,FLEN)
NAN_BOXED(0x4134ae72,32,FLEN)
NAN_BOXED(0x3003fff,32,FLEN)
NAN_BOXED(0x7db55b9c,32,FLEN)
NAN_BOXED(0x4134ae72,32,FLEN)
NAN_BOXED(0x3007fff,32,FLEN)
NAN_BOXED(0x7db55b9c,32,FLEN)
NAN_BOXED(0x4134ae72,32,FLEN)
NAN_BOXED(0x300ffff,32,FLEN)
NAN_BOXED(0x7db55b9c,32,FLEN)
NAN_BOXED(0x4134ae72,32,FLEN)
NAN_BOXED(0x301ffff,32,FLEN)
NAN_BOXED(0x7db55b9c,32,FLEN)
NAN_BOXED(0x4134ae72,32,FLEN)
NAN_BOXED(0x303ffff,32,FLEN)
NAN_BOXED(0x7db55b9c,32,FLEN)
NAN_BOXED(0x4134ae72,32,FLEN)
NAN_BOXED(0x307ffff,32,FLEN)
NAN_BOXED(0x7db55b9c,32,FLEN)
NAN_BOXED(0x4134ae72,32,FLEN)
NAN_BOXED(0x30fffff,32,FLEN)
NAN_BOXED(0x7db55b9c,32,FLEN)
NAN_BOXED(0x4134ae72,32,FLEN)
NAN_BOXED(0x31fffff,32,FLEN)
NAN_BOXED(0x7db55b9c,32,FLEN)
NAN_BOXED(0x4134ae72,32,FLEN)
NAN_BOXED(0x33fffff,32,FLEN)
NAN_BOXED(0x7db55b9c,32,FLEN)
NAN_BOXED(0x4134ae72,32,FLEN)
NAN_BOXED(0x3400000,32,FLEN)
NAN_BOXED(0x7db55b9c,32,FLEN)
NAN_BOXED(0x4134ae72,32,FLEN)
NAN_BOXED(0x3600000,32,FLEN)
NAN_BOXED(0x7db55b9c,32,FLEN)
NAN_BOXED(0x4134ae72,32,FLEN)
NAN_BOXED(0x3700000,32,FLEN)
NAN_BOXED(0x7db55b9c,32,FLEN)
NAN_BOXED(0x4134ae72,32,FLEN)
NAN_BOXED(0x3780000,32,FLEN)
NAN_BOXED(0x7db55b9c,32,FLEN)
NAN_BOXED(0x4134ae72,32,FLEN)
NAN_BOXED(0x37c0000,32,FLEN)
NAN_BOXED(0x7db55b9c,32,FLEN)
NAN_BOXED(0x4134ae72,32,FLEN)
NAN_BOXED(0x37e0000,32,FLEN)
NAN_BOXED(0x7db55b9c,32,FLEN)
NAN_BOXED(0x4134ae72,32,FLEN)
NAN_BOXED(0x37f0000,32,FLEN)
NAN_BOXED(0x7db55b9c,32,FLEN)
NAN_BOXED(0x4134ae72,32,FLEN)
NAN_BOXED(0x37f8000,32,FLEN)
NAN_BOXED(0x7db55b9c,32,FLEN)
NAN_BOXED(0x4134ae72,32,FLEN)
NAN_BOXED(0x37fc000,32,FLEN)
NAN_BOXED(0x7db55b9c,32,FLEN)
NAN_BOXED(0x4134ae72,32,FLEN)
NAN_BOXED(0x37fe000,32,FLEN)
NAN_BOXED(0x7db55b9c,32,FLEN)
NAN_BOXED(0x4134ae72,32,FLEN)
NAN_BOXED(0x37ff000,32,FLEN)
NAN_BOXED(0x7db55b9c,32,FLEN)
NAN_BOXED(0x4134ae72,32,FLEN)
NAN_BOXED(0x37ff800,32,FLEN)
NAN_BOXED(0x7db55b9c,32,FLEN)
NAN_BOXED(0x4134ae72,32,FLEN)
NAN_BOXED(0x37ffc00,32,FLEN)
NAN_BOXED(0x7db55b9c,32,FLEN)
NAN_BOXED(0x4134ae72,32,FLEN)
NAN_BOXED(0x37ffe00,32,FLEN)
NAN_BOXED(0x7db55b9c,32,FLEN)
NAN_BOXED(0x4134ae72,32,FLEN)
NAN_BOXED(0x37fff00,32,FLEN)
NAN_BOXED(0x7db55b9c,32,FLEN)
NAN_BOXED(0x4134ae72,32,FLEN)
NAN_BOXED(0x37fff80,32,FLEN)
NAN_BOXED(0x7db55b9c,32,FLEN)
NAN_BOXED(0x4134ae72,32,FLEN)
NAN_BOXED(0x37fffc0,32,FLEN)
NAN_BOXED(0x7db55b9c,32,FLEN)
NAN_BOXED(0x4134ae72,32,FLEN)
NAN_BOXED(0x37fffe0,32,FLEN)
NAN_BOXED(0x7db55b9c,32,FLEN)
NAN_BOXED(0x4134ae72,32,FLEN)
NAN_BOXED(0x37ffff0,32,FLEN)
NAN_BOXED(0x7db55b9c,32,FLEN)
NAN_BOXED(0x4134ae72,32,FLEN)
NAN_BOXED(0x37ffff8,32,FLEN)
NAN_BOXED(0x7db55b9c,32,FLEN)
NAN_BOXED(0x4134ae72,32,FLEN)
NAN_BOXED(0x37ffffc,32,FLEN)
NAN_BOXED(0x7db55b9c,32,FLEN)
NAN_BOXED(0x4134ae72,32,FLEN)
NAN_BOXED(0x37ffffe,32,FLEN)
NAN_BOXED(0x7db55b9c,32,FLEN)
NAN_BOXED(0x4134ae72,32,FLEN)
NAN_BOXED(0x37fffff,32,FLEN)
NAN_BOXED(0x7db55b9c,32,FLEN)
NAN_BOXED(0x4134ae72,32,FLEN)
NAN_BOXED(0x7f000001,32,FLEN)
NAN_BOXED(0x7db55b9c,32,FLEN)
NAN_BOXED(0x4134ae72,32,FLEN)
NAN_BOXED(0x7f000003,32,FLEN)
NAN_BOXED(0x7db55b9c,32,FLEN)
NAN_BOXED(0x4134ae72,32,FLEN)
NAN_BOXED(0x7f000007,32,FLEN)
NAN_BOXED(0x7db55b9c,32,FLEN)
NAN_BOXED(0x4134ae72,32,FLEN)
NAN_BOXED(0x7f199999,32,FLEN)
NAN_BOXED(0x7db55b9c,32,FLEN)
NAN_BOXED(0x4134ae72,32,FLEN)
NAN_BOXED(0x7f249249,32,FLEN)
NAN_BOXED(0x7db55b9c,32,FLEN)
NAN_BOXED(0x4134ae72,32,FLEN)
NAN_BOXED(0x7f333333,32,FLEN)
NAN_BOXED(0x7db55b9c,32,FLEN)
NAN_BOXED(0x4134ae72,32,FLEN)
NAN_BOXED(0x7f36db6d,32,FLEN)
NAN_BOXED(0x7db55b9c,32,FLEN)
NAN_BOXED(0x4134ae72,32,FLEN)
NAN_BOXED(0x7f3bbbbb,32,FLEN)
NAN_BOXED(0x7db55b9c,32,FLEN)
NAN_BOXED(0x4134ae72,32,FLEN)
NAN_BOXED(0x7f444444,32,FLEN)
NAN_BOXED(0x7db55b9c,32,FLEN)
NAN_BOXED(0x4134ae72,32,FLEN)
NAN_BOXED(0x7f4ccccc,32,FLEN)
NAN_BOXED(0x7db55b9c,32,FLEN)
NAN_BOXED(0x4134ae72,32,FLEN)
NAN_BOXED(0x7f5b6db6,32,FLEN)
NAN_BOXED(0x7db55b9c,32,FLEN)
NAN_BOXED(0x4134ae72,32,FLEN)
NAN_BOXED(0x7f666666,32,FLEN)
NAN_BOXED(0x7db55b9c,32,FLEN)
NAN_BOXED(0x4134ae72,32,FLEN)
NAN_BOXED(0x7f6db6db,32,FLEN)
NAN_BOXED(0x7db55b9c,32,FLEN)
NAN_BOXED(0x4134ae72,32,FLEN)
NAN_BOXED(0x7f7ffff8,32,FLEN)
NAN_BOXED(0x7db55b9c,32,FLEN)
NAN_BOXED(0x4134ae72,32,FLEN)
NAN_BOXED(0x7f7ffffc,32,FLEN)
NAN_BOXED(0x7db55b9c,32,FLEN)
NAN_BOXED(0x4134ae72,32,FLEN)
NAN_BOXED(0x7f7ffffe,32,FLEN)
NAN_BOXED(0x7dbb15b6,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x80800001,32,FLEN)
NAN_BOXED(0x7dbb15b6,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x80800003,32,FLEN)
NAN_BOXED(0x7dbb15b6,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x80800007,32,FLEN)
NAN_BOXED(0x7dbb15b6,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x80999999,32,FLEN)
NAN_BOXED(0x7dbb15b6,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x80a49249,32,FLEN)
NAN_BOXED(0x7dbb15b6,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x80b33333,32,FLEN)
NAN_BOXED(0x7dbb15b6,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x80b6db6d,32,FLEN)
NAN_BOXED(0x7dbb15b6,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x80bbbbbb,32,FLEN)
NAN_BOXED(0x7dbb15b6,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x80c44444,32,FLEN)
NAN_BOXED(0x7dbb15b6,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x80cccccc,32,FLEN)
NAN_BOXED(0x7dbb15b6,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x80db6db6,32,FLEN)
NAN_BOXED(0x7dbb15b6,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x80e66666,32,FLEN)
NAN_BOXED(0x7dbb15b6,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x80edb6db,32,FLEN)
NAN_BOXED(0x7dbb15b6,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x80fffff8,32,FLEN)
NAN_BOXED(0x7dbb15b6,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x80fffffc,32,FLEN)
NAN_BOXED(0x7dbb15b6,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x80fffffe,32,FLEN)
NAN_BOXED(0x7dbb15b6,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x8e800000,32,FLEN)
NAN_BOXED(0x7dbb15b6,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x8e800001,32,FLEN)
NAN_BOXED(0x7dbb15b6,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x8e800003,32,FLEN)
NAN_BOXED(0x7dbb15b6,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x8e800007,32,FLEN)
NAN_BOXED(0x7dbb15b6,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x8e80000f,32,FLEN)
NAN_BOXED(0x7dbb15b6,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x8e80001f,32,FLEN)
NAN_BOXED(0x7dbb15b6,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x8e80003f,32,FLEN)
NAN_BOXED(0x7dbb15b6,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x8e80007f,32,FLEN)
NAN_BOXED(0x7dbb15b6,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x8e8000ff,32,FLEN)
NAN_BOXED(0x7dbb15b6,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x8e8001ff,32,FLEN)
NAN_BOXED(0x7dbb15b6,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x8e8003ff,32,FLEN)
NAN_BOXED(0x7dbb15b6,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x8e8007ff,32,FLEN)
NAN_BOXED(0x7dbb15b6,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x8e800fff,32,FLEN)
NAN_BOXED(0x7dbb15b6,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x8e801fff,32,FLEN)
NAN_BOXED(0x7dbb15b6,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x8e803fff,32,FLEN)
NAN_BOXED(0x7dbb15b6,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x8e807fff,32,FLEN)
NAN_BOXED(0x7dbb15b6,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x8e80ffff,32,FLEN)
NAN_BOXED(0x7dbb15b6,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x8e81ffff,32,FLEN)
NAN_BOXED(0x7dbb15b6,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x8e83ffff,32,FLEN)
NAN_BOXED(0x7dbb15b6,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x8e87ffff,32,FLEN)
NAN_BOXED(0x7dbb15b6,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x8e8fffff,32,FLEN)
NAN_BOXED(0x7dbb15b6,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x8e9fffff,32,FLEN)
NAN_BOXED(0x7dbb15b6,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x8ebfffff,32,FLEN)
NAN_BOXED(0x7dbb15b6,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x8ec00000,32,FLEN)
NAN_BOXED(0x7dbb15b6,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x8ee00000,32,FLEN)
NAN_BOXED(0x7dbb15b6,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x8ef00000,32,FLEN)
NAN_BOXED(0x7dbb15b6,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x8ef80000,32,FLEN)
NAN_BOXED(0x7dbb15b6,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x8efc0000,32,FLEN)
NAN_BOXED(0x7dbb15b6,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x8efe0000,32,FLEN)
NAN_BOXED(0x7dbb15b6,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x8eff0000,32,FLEN)
NAN_BOXED(0x7dbb15b6,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x8eff8000,32,FLEN)
NAN_BOXED(0x7dbb15b6,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x8effc000,32,FLEN)
NAN_BOXED(0x7dbb15b6,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x8effe000,32,FLEN)
NAN_BOXED(0x7dbb15b6,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x8efff000,32,FLEN)
NAN_BOXED(0x7dbb15b6,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x8efff800,32,FLEN)
NAN_BOXED(0x7dbb15b6,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x8efffc00,32,FLEN)
NAN_BOXED(0x7dbb15b6,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x8efffe00,32,FLEN)
NAN_BOXED(0x7dbb15b6,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x8effff00,32,FLEN)
NAN_BOXED(0x7dbb15b6,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x8effff80,32,FLEN)
NAN_BOXED(0x7dbb15b6,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x8effffc0,32,FLEN)
NAN_BOXED(0x7dbb15b6,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x8effffe0,32,FLEN)
NAN_BOXED(0x7dbb15b6,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x8efffff0,32,FLEN)
NAN_BOXED(0x7dbb15b6,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x8efffff8,32,FLEN)
NAN_BOXED(0x7dbb15b6,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x8efffffc,32,FLEN)
NAN_BOXED(0x7dbb15b6,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x8efffffe,32,FLEN)
NAN_BOXED(0x7dbb15b6,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x8effffff,32,FLEN)
NAN_BOXED(0x7dc006c8,32,FLEN)
NAN_BOXED(0x812aa4a3,32,FLEN)
NAN_BOXED(0xbf800001,32,FLEN)
NAN_BOXED(0x7dc006c8,32,FLEN)
NAN_BOXED(0x812aa4a3,32,FLEN)
NAN_BOXED(0xbf800003,32,FLEN)
NAN_BOXED(0x7dc006c8,32,FLEN)
NAN_BOXED(0x812aa4a3,32,FLEN)
NAN_BOXED(0xbf800007,32,FLEN)
NAN_BOXED(0x7dc006c8,32,FLEN)
NAN_BOXED(0x812aa4a3,32,FLEN)
NAN_BOXED(0xbf999999,32,FLEN)
NAN_BOXED(0x7dc006c8,32,FLEN)
NAN_BOXED(0x812aa4a3,32,FLEN)
NAN_BOXED(0xbfa49249,32,FLEN)
NAN_BOXED(0x7dc006c8,32,FLEN)
NAN_BOXED(0x812aa4a3,32,FLEN)
NAN_BOXED(0xbfb33333,32,FLEN)
NAN_BOXED(0x7dc006c8,32,FLEN)
NAN_BOXED(0x812aa4a3,32,FLEN)
NAN_BOXED(0xbfb6db6d,32,FLEN)
NAN_BOXED(0x7dc006c8,32,FLEN)
NAN_BOXED(0x812aa4a3,32,FLEN)
NAN_BOXED(0xbfbbbbbb,32,FLEN)
NAN_BOXED(0x7dc006c8,32,FLEN)
NAN_BOXED(0x812aa4a3,32,FLEN)
NAN_BOXED(0xbfc44444,32,FLEN)
NAN_BOXED(0x7dc006c8,32,FLEN)
NAN_BOXED(0x812aa4a3,32,FLEN)
NAN_BOXED(0xbfcccccc,32,FLEN)
NAN_BOXED(0x7dc006c8,32,FLEN)
NAN_BOXED(0x812aa4a3,32,FLEN)
NAN_BOXED(0xbfdb6db6,32,FLEN)
NAN_BOXED(0x7dc006c8,32,FLEN)
NAN_BOXED(0x812aa4a3,32,FLEN)
NAN_BOXED(0xbfe66666,32,FLEN)
NAN_BOXED(0x7dc006c8,32,FLEN)
NAN_BOXED(0x812aa4a3,32,FLEN)
NAN_BOXED(0xbfedb6db,32,FLEN)
NAN_BOXED(0x7dc006c8,32,FLEN)
NAN_BOXED(0x812aa4a3,32,FLEN)
NAN_BOXED(0xbffffff8,32,FLEN)
NAN_BOXED(0x7dc006c8,32,FLEN)
NAN_BOXED(0x812aa4a3,32,FLEN)
NAN_BOXED(0xbffffffc,32,FLEN)
NAN_BOXED(0x7dc006c8,32,FLEN)
NAN_BOXED(0x812aa4a3,32,FLEN)
NAN_BOXED(0xbffffffe,32,FLEN)
NAN_BOXED(0x7dc006c8,32,FLEN)
NAN_BOXED(0x812aa4a3,32,FLEN)
NAN_BOXED(0xc0000000,32,FLEN)
NAN_BOXED(0x7dc006c8,32,FLEN)
NAN_BOXED(0x812aa4a3,32,FLEN)
NAN_BOXED(0xc0000001,32,FLEN)
NAN_BOXED(0x7dc006c8,32,FLEN)
NAN_BOXED(0x812aa4a3,32,FLEN)
NAN_BOXED(0xc0000003,32,FLEN)
NAN_BOXED(0x7dc006c8,32,FLEN)
NAN_BOXED(0x812aa4a3,32,FLEN)
NAN_BOXED(0xc0000007,32,FLEN)
NAN_BOXED(0x7dc006c8,32,FLEN)
NAN_BOXED(0x812aa4a3,32,FLEN)
NAN_BOXED(0xc000000f,32,FLEN)
NAN_BOXED(0x7dc006c8,32,FLEN)
NAN_BOXED(0x812aa4a3,32,FLEN)
NAN_BOXED(0xc000001f,32,FLEN)
NAN_BOXED(0x7dc006c8,32,FLEN)
NAN_BOXED(0x812aa4a3,32,FLEN)
NAN_BOXED(0xc000003f,32,FLEN)
NAN_BOXED(0x7dc006c8,32,FLEN)
NAN_BOXED(0x812aa4a3,32,FLEN)
NAN_BOXED(0xc000007f,32,FLEN)
NAN_BOXED(0x7dc006c8,32,FLEN)
NAN_BOXED(0x812aa4a3,32,FLEN)
NAN_BOXED(0xc00000ff,32,FLEN)
NAN_BOXED(0x7dc006c8,32,FLEN)
NAN_BOXED(0x812aa4a3,32,FLEN)
NAN_BOXED(0xc00001ff,32,FLEN)
NAN_BOXED(0x7dc006c8,32,FLEN)
NAN_BOXED(0x812aa4a3,32,FLEN)
NAN_BOXED(0xc00003ff,32,FLEN)
NAN_BOXED(0x7dc006c8,32,FLEN)
NAN_BOXED(0x812aa4a3,32,FLEN)
NAN_BOXED(0xc00007ff,32,FLEN)
NAN_BOXED(0x7dc006c8,32,FLEN)
NAN_BOXED(0x812aa4a3,32,FLEN)
NAN_BOXED(0xc0000fff,32,FLEN)
NAN_BOXED(0x7dc006c8,32,FLEN)
NAN_BOXED(0x812aa4a3,32,FLEN)
NAN_BOXED(0xc0001fff,32,FLEN)
NAN_BOXED(0x7dc006c8,32,FLEN)
NAN_BOXED(0x812aa4a3,32,FLEN)
NAN_BOXED(0xc0003fff,32,FLEN)
NAN_BOXED(0x7dc006c8,32,FLEN)
NAN_BOXED(0x812aa4a3,32,FLEN)
NAN_BOXED(0xc0007fff,32,FLEN)
NAN_BOXED(0x7dc006c8,32,FLEN)
NAN_BOXED(0x812aa4a3,32,FLEN)
NAN_BOXED(0xc000ffff,32,FLEN)
NAN_BOXED(0x7dc006c8,32,FLEN)
NAN_BOXED(0x812aa4a3,32,FLEN)
NAN_BOXED(0xc001ffff,32,FLEN)
NAN_BOXED(0x7dc006c8,32,FLEN)
NAN_BOXED(0x812aa4a3,32,FLEN)
NAN_BOXED(0xc003ffff,32,FLEN)
NAN_BOXED(0x7dc006c8,32,FLEN)
NAN_BOXED(0x812aa4a3,32,FLEN)
NAN_BOXED(0xc007ffff,32,FLEN)
NAN_BOXED(0x7dc006c8,32,FLEN)
NAN_BOXED(0x812aa4a3,32,FLEN)
NAN_BOXED(0xc00fffff,32,FLEN)
NAN_BOXED(0x7dc006c8,32,FLEN)
NAN_BOXED(0x812aa4a3,32,FLEN)
NAN_BOXED(0xc01fffff,32,FLEN)
NAN_BOXED(0x7dc006c8,32,FLEN)
NAN_BOXED(0x812aa4a3,32,FLEN)
NAN_BOXED(0xc03fffff,32,FLEN)
NAN_BOXED(0x7dc006c8,32,FLEN)
NAN_BOXED(0x812aa4a3,32,FLEN)
NAN_BOXED(0xc0400000,32,FLEN)
NAN_BOXED(0x7dc006c8,32,FLEN)
NAN_BOXED(0x812aa4a3,32,FLEN)
NAN_BOXED(0xc0600000,32,FLEN)
NAN_BOXED(0x7dc006c8,32,FLEN)
NAN_BOXED(0x812aa4a3,32,FLEN)
NAN_BOXED(0xc0700000,32,FLEN)
NAN_BOXED(0x7dc006c8,32,FLEN)
NAN_BOXED(0x812aa4a3,32,FLEN)
NAN_BOXED(0xc0780000,32,FLEN)
NAN_BOXED(0x7dc006c8,32,FLEN)
NAN_BOXED(0x812aa4a3,32,FLEN)
NAN_BOXED(0xc07c0000,32,FLEN)
NAN_BOXED(0x7dc006c8,32,FLEN)
NAN_BOXED(0x812aa4a3,32,FLEN)
NAN_BOXED(0xc07e0000,32,FLEN)
NAN_BOXED(0x7dc006c8,32,FLEN)
NAN_BOXED(0x812aa4a3,32,FLEN)
NAN_BOXED(0xc07f0000,32,FLEN)
NAN_BOXED(0x7dc006c8,32,FLEN)
NAN_BOXED(0x812aa4a3,32,FLEN)
NAN_BOXED(0xc07f8000,32,FLEN)
NAN_BOXED(0x7dc006c8,32,FLEN)
NAN_BOXED(0x812aa4a3,32,FLEN)
NAN_BOXED(0xc07fc000,32,FLEN)
NAN_BOXED(0x7dc006c8,32,FLEN)
NAN_BOXED(0x812aa4a3,32,FLEN)
NAN_BOXED(0xc07fe000,32,FLEN)
NAN_BOXED(0x7dc006c8,32,FLEN)
NAN_BOXED(0x812aa4a3,32,FLEN)
NAN_BOXED(0xc07ff000,32,FLEN)
NAN_BOXED(0x7dc006c8,32,FLEN)
NAN_BOXED(0x812aa4a3,32,FLEN)
NAN_BOXED(0xc07ff800,32,FLEN)
NAN_BOXED(0x7dc006c8,32,FLEN)
NAN_BOXED(0x812aa4a3,32,FLEN)
NAN_BOXED(0xc07ffc00,32,FLEN)
NAN_BOXED(0x7dc006c8,32,FLEN)
NAN_BOXED(0x812aa4a3,32,FLEN)
NAN_BOXED(0xc07ffe00,32,FLEN)
NAN_BOXED(0x7dc006c8,32,FLEN)
NAN_BOXED(0x812aa4a3,32,FLEN)
NAN_BOXED(0xc07fff00,32,FLEN)
NAN_BOXED(0x7dc006c8,32,FLEN)
NAN_BOXED(0x812aa4a3,32,FLEN)
NAN_BOXED(0xc07fff80,32,FLEN)
NAN_BOXED(0x7dc006c8,32,FLEN)
NAN_BOXED(0x812aa4a3,32,FLEN)
NAN_BOXED(0xc07fffc0,32,FLEN)
NAN_BOXED(0x7dc006c8,32,FLEN)
NAN_BOXED(0x812aa4a3,32,FLEN)
NAN_BOXED(0xc07fffe0,32,FLEN)
NAN_BOXED(0x7dc006c8,32,FLEN)
NAN_BOXED(0x812aa4a3,32,FLEN)
NAN_BOXED(0xc07ffff0,32,FLEN)
NAN_BOXED(0x7dc006c8,32,FLEN)
NAN_BOXED(0x812aa4a3,32,FLEN)
NAN_BOXED(0xc07ffff8,32,FLEN)
NAN_BOXED(0x7dc006c8,32,FLEN)
NAN_BOXED(0x812aa4a3,32,FLEN)
NAN_BOXED(0xc07ffffc,32,FLEN)
NAN_BOXED(0x7dc006c8,32,FLEN)
NAN_BOXED(0x812aa4a3,32,FLEN)
NAN_BOXED(0xc07ffffe,32,FLEN)
NAN_BOXED(0x7dc006c8,32,FLEN)
NAN_BOXED(0x812aa4a3,32,FLEN)
NAN_BOXED(0xc07fffff,32,FLEN)
NAN_BOXED(0x7dc032ba,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x7dc032ba,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x80000001,32,FLEN)
NAN_BOXED(0x7dc032ba,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x80000003,32,FLEN)
NAN_BOXED(0x7dc032ba,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x80000007,32,FLEN)
NAN_BOXED(0x7dc032ba,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x8000000f,32,FLEN)
NAN_BOXED(0x7dc032ba,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x8000001f,32,FLEN)
NAN_BOXED(0x7dc032ba,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x8000003f,32,FLEN)
NAN_BOXED(0x7dc032ba,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x8000007f,32,FLEN)
NAN_BOXED(0x7dc032ba,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x800000ff,32,FLEN)
NAN_BOXED(0x7dc032ba,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x800001ff,32,FLEN)
NAN_BOXED(0x7dc032ba,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x800003ff,32,FLEN)
NAN_BOXED(0x7dc032ba,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x800007ff,32,FLEN)
NAN_BOXED(0x7dc032ba,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x80000fff,32,FLEN)
NAN_BOXED(0x7dc032ba,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x80001fff,32,FLEN)
NAN_BOXED(0x7dc032ba,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x80003fff,32,FLEN)
NAN_BOXED(0x7dc032ba,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x80007fff,32,FLEN)
NAN_BOXED(0x7dc032ba,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x8000ffff,32,FLEN)
NAN_BOXED(0x7dc032ba,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x8001ffff,32,FLEN)
NAN_BOXED(0x7dc032ba,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x8003ffff,32,FLEN)
NAN_BOXED(0x7dc032ba,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x8007ffff,32,FLEN)
NAN_BOXED(0x7dc032ba,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x800fffff,32,FLEN)
NAN_BOXED(0x7dc032ba,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x80199999,32,FLEN)
NAN_BOXED(0x7dc032ba,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x801fffff,32,FLEN)
NAN_BOXED(0x7dc032ba,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x80249249,32,FLEN)
NAN_BOXED(0x7dc032ba,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x80333333,32,FLEN)
NAN_BOXED(0x7dc032ba,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x8036db6d,32,FLEN)
NAN_BOXED(0x7dc032ba,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x803bbbbb,32,FLEN)
NAN_BOXED(0x7dc032ba,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x803fffff,32,FLEN)
NAN_BOXED(0x7dc032ba,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x80400000,32,FLEN)
NAN_BOXED(0x7dc032ba,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x80444444,32,FLEN)
NAN_BOXED(0x7dc032ba,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x804ccccc,32,FLEN)
NAN_BOXED(0x7dc032ba,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x805b6db6,32,FLEN)
NAN_BOXED(0x7dc032ba,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x80600000,32,FLEN)
NAN_BOXED(0x7dc032ba,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x80666666,32,FLEN)
NAN_BOXED(0x7dc032ba,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x806db6db,32,FLEN)
NAN_BOXED(0x7dc032ba,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x80700000,32,FLEN)
NAN_BOXED(0x7dc032ba,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x80780000,32,FLEN)
NAN_BOXED(0x7dc032ba,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x807c0000,32,FLEN)
NAN_BOXED(0x7dc032ba,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x807e0000,32,FLEN)
NAN_BOXED(0x7dc032ba,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x807f0000,32,FLEN)
NAN_BOXED(0x7dc032ba,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x807f8000,32,FLEN)
NAN_BOXED(0x7dc032ba,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x807fc000,32,FLEN)
NAN_BOXED(0x7dc032ba,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x807fe000,32,FLEN)
NAN_BOXED(0x7dc032ba,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x807ff000,32,FLEN)
NAN_BOXED(0x7dc032ba,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x807ff800,32,FLEN)
NAN_BOXED(0x7dc032ba,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x807ffc00,32,FLEN)
NAN_BOXED(0x7dc032ba,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x807ffe00,32,FLEN)
NAN_BOXED(0x7dc032ba,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x807fff00,32,FLEN)
NAN_BOXED(0x7dc032ba,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x807fff80,32,FLEN)
NAN_BOXED(0x7dc032ba,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x807fffc0,32,FLEN)
NAN_BOXED(0x7dc032ba,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x807fffe0,32,FLEN)
NAN_BOXED(0x7dc032ba,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x807ffff0,32,FLEN)
NAN_BOXED(0x7dc032ba,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x807ffff8,32,FLEN)
NAN_BOXED(0x7dc032ba,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x807ffffc,32,FLEN)
NAN_BOXED(0x7dc032ba,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x807ffffe,32,FLEN)
NAN_BOXED(0x7dc032ba,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x807fffff,32,FLEN)
NAN_BOXED(0x7dc10cb0,32,FLEN)
NAN_BOXED(0x129bd20,32,FLEN)
NAN_BOXED(0x3f800001,32,FLEN)
NAN_BOXED(0x7dc10cb0,32,FLEN)
NAN_BOXED(0x129bd20,32,FLEN)
NAN_BOXED(0x3f800003,32,FLEN)
NAN_BOXED(0x7dc10cb0,32,FLEN)
NAN_BOXED(0x129bd20,32,FLEN)
NAN_BOXED(0x3f800007,32,FLEN)
NAN_BOXED(0x7dc10cb0,32,FLEN)
NAN_BOXED(0x129bd20,32,FLEN)
NAN_BOXED(0x3f999999,32,FLEN)
NAN_BOXED(0x7dc10cb0,32,FLEN)
NAN_BOXED(0x129bd20,32,FLEN)
NAN_BOXED(0x3fa49249,32,FLEN)
NAN_BOXED(0x7dc10cb0,32,FLEN)
NAN_BOXED(0x129bd20,32,FLEN)
NAN_BOXED(0x3fb33333,32,FLEN)
NAN_BOXED(0x7dc10cb0,32,FLEN)
NAN_BOXED(0x129bd20,32,FLEN)
NAN_BOXED(0x3fb6db6d,32,FLEN)
NAN_BOXED(0x7dc10cb0,32,FLEN)
NAN_BOXED(0x129bd20,32,FLEN)
NAN_BOXED(0x3fbbbbbb,32,FLEN)
NAN_BOXED(0x7dc10cb0,32,FLEN)
NAN_BOXED(0x129bd20,32,FLEN)
NAN_BOXED(0x3fc44444,32,FLEN)
NAN_BOXED(0x7dc10cb0,32,FLEN)
NAN_BOXED(0x129bd20,32,FLEN)
NAN_BOXED(0x3fcccccc,32,FLEN)
NAN_BOXED(0x7dc10cb0,32,FLEN)
NAN_BOXED(0x129bd20,32,FLEN)
NAN_BOXED(0x3fdb6db6,32,FLEN)
NAN_BOXED(0x7dc10cb0,32,FLEN)
NAN_BOXED(0x129bd20,32,FLEN)
NAN_BOXED(0x3fe66666,32,FLEN)
NAN_BOXED(0x7dc10cb0,32,FLEN)
NAN_BOXED(0x129bd20,32,FLEN)
NAN_BOXED(0x3fedb6db,32,FLEN)
NAN_BOXED(0x7dc10cb0,32,FLEN)
NAN_BOXED(0x129bd20,32,FLEN)
NAN_BOXED(0x3ffffff8,32,FLEN)
NAN_BOXED(0x7dc10cb0,32,FLEN)
NAN_BOXED(0x129bd20,32,FLEN)
NAN_BOXED(0x3ffffffc,32,FLEN)
NAN_BOXED(0x7dc10cb0,32,FLEN)
NAN_BOXED(0x129bd20,32,FLEN)
NAN_BOXED(0x3ffffffe,32,FLEN)
NAN_BOXED(0x7dc10cb0,32,FLEN)
NAN_BOXED(0x129bd20,32,FLEN)
NAN_BOXED(0x4e800000,32,FLEN)
NAN_BOXED(0x7dc10cb0,32,FLEN)
NAN_BOXED(0x129bd20,32,FLEN)
NAN_BOXED(0x4e800001,32,FLEN)
NAN_BOXED(0x7dc10cb0,32,FLEN)
NAN_BOXED(0x129bd20,32,FLEN)
NAN_BOXED(0x4e800003,32,FLEN)
NAN_BOXED(0x7dc10cb0,32,FLEN)
NAN_BOXED(0x129bd20,32,FLEN)
NAN_BOXED(0x4e800007,32,FLEN)
NAN_BOXED(0x7dc10cb0,32,FLEN)
NAN_BOXED(0x129bd20,32,FLEN)
NAN_BOXED(0x4e80000f,32,FLEN)
NAN_BOXED(0x7dc10cb0,32,FLEN)
NAN_BOXED(0x129bd20,32,FLEN)
NAN_BOXED(0x4e80001f,32,FLEN)
NAN_BOXED(0x7dc10cb0,32,FLEN)
NAN_BOXED(0x129bd20,32,FLEN)
NAN_BOXED(0x4e80003f,32,FLEN)
NAN_BOXED(0x7dc10cb0,32,FLEN)
NAN_BOXED(0x129bd20,32,FLEN)
NAN_BOXED(0x4e80007f,32,FLEN)
NAN_BOXED(0x7dc10cb0,32,FLEN)
NAN_BOXED(0x129bd20,32,FLEN)
NAN_BOXED(0x4e8000ff,32,FLEN)
NAN_BOXED(0x7dc10cb0,32,FLEN)
NAN_BOXED(0x129bd20,32,FLEN)
NAN_BOXED(0x4e8001ff,32,FLEN)
NAN_BOXED(0x7dc10cb0,32,FLEN)
NAN_BOXED(0x129bd20,32,FLEN)
NAN_BOXED(0x4e8003ff,32,FLEN)
NAN_BOXED(0x7dc10cb0,32,FLEN)
NAN_BOXED(0x129bd20,32,FLEN)
NAN_BOXED(0x4e8007ff,32,FLEN)
NAN_BOXED(0x7dc10cb0,32,FLEN)
NAN_BOXED(0x129bd20,32,FLEN)
NAN_BOXED(0x4e800fff,32,FLEN)
NAN_BOXED(0x7dc10cb0,32,FLEN)
NAN_BOXED(0x129bd20,32,FLEN)
NAN_BOXED(0x4e801fff,32,FLEN)
NAN_BOXED(0x7dc10cb0,32,FLEN)
NAN_BOXED(0x129bd20,32,FLEN)
NAN_BOXED(0x4e803fff,32,FLEN)
NAN_BOXED(0x7dc10cb0,32,FLEN)
NAN_BOXED(0x129bd20,32,FLEN)
NAN_BOXED(0x4e807fff,32,FLEN)
NAN_BOXED(0x7dc10cb0,32,FLEN)
NAN_BOXED(0x129bd20,32,FLEN)
NAN_BOXED(0x4e80ffff,32,FLEN)
NAN_BOXED(0x7dc10cb0,32,FLEN)
NAN_BOXED(0x129bd20,32,FLEN)
NAN_BOXED(0x4e81ffff,32,FLEN)
NAN_BOXED(0x7dc10cb0,32,FLEN)
NAN_BOXED(0x129bd20,32,FLEN)
NAN_BOXED(0x4e83ffff,32,FLEN)
NAN_BOXED(0x7dc10cb0,32,FLEN)
NAN_BOXED(0x129bd20,32,FLEN)
NAN_BOXED(0x4e87ffff,32,FLEN)
NAN_BOXED(0x7dc10cb0,32,FLEN)
NAN_BOXED(0x129bd20,32,FLEN)
NAN_BOXED(0x4e8fffff,32,FLEN)
NAN_BOXED(0x7dc10cb0,32,FLEN)
NAN_BOXED(0x129bd20,32,FLEN)
NAN_BOXED(0x4e9fffff,32,FLEN)
NAN_BOXED(0x7dc10cb0,32,FLEN)
NAN_BOXED(0x129bd20,32,FLEN)
NAN_BOXED(0x4ebfffff,32,FLEN)
NAN_BOXED(0x7dc10cb0,32,FLEN)
NAN_BOXED(0x129bd20,32,FLEN)
NAN_BOXED(0x4ec00000,32,FLEN)
NAN_BOXED(0x7dc10cb0,32,FLEN)
NAN_BOXED(0x129bd20,32,FLEN)
NAN_BOXED(0x4ee00000,32,FLEN)
NAN_BOXED(0x7dc10cb0,32,FLEN)
NAN_BOXED(0x129bd20,32,FLEN)
NAN_BOXED(0x4ef00000,32,FLEN)
NAN_BOXED(0x7dc10cb0,32,FLEN)
NAN_BOXED(0x129bd20,32,FLEN)
NAN_BOXED(0x4ef80000,32,FLEN)
NAN_BOXED(0x7dc10cb0,32,FLEN)
NAN_BOXED(0x129bd20,32,FLEN)
NAN_BOXED(0x4efc0000,32,FLEN)
NAN_BOXED(0x7dc10cb0,32,FLEN)
NAN_BOXED(0x129bd20,32,FLEN)
NAN_BOXED(0x4efe0000,32,FLEN)
NAN_BOXED(0x7dc10cb0,32,FLEN)
NAN_BOXED(0x129bd20,32,FLEN)
NAN_BOXED(0x4eff0000,32,FLEN)
NAN_BOXED(0x7dc10cb0,32,FLEN)
NAN_BOXED(0x129bd20,32,FLEN)
NAN_BOXED(0x4eff8000,32,FLEN)
NAN_BOXED(0x7dc10cb0,32,FLEN)
NAN_BOXED(0x129bd20,32,FLEN)
NAN_BOXED(0x4effc000,32,FLEN)
NAN_BOXED(0x7dc10cb0,32,FLEN)
NAN_BOXED(0x129bd20,32,FLEN)
NAN_BOXED(0x4effe000,32,FLEN)
NAN_BOXED(0x7dc10cb0,32,FLEN)
NAN_BOXED(0x129bd20,32,FLEN)
NAN_BOXED(0x4efff000,32,FLEN)
NAN_BOXED(0x7dc10cb0,32,FLEN)
NAN_BOXED(0x129bd20,32,FLEN)
NAN_BOXED(0x4efff800,32,FLEN)
NAN_BOXED(0x7dc10cb0,32,FLEN)
NAN_BOXED(0x129bd20,32,FLEN)
NAN_BOXED(0x4efffc00,32,FLEN)
NAN_BOXED(0x7dc10cb0,32,FLEN)
NAN_BOXED(0x129bd20,32,FLEN)
NAN_BOXED(0x4efffe00,32,FLEN)
NAN_BOXED(0x7dc10cb0,32,FLEN)
NAN_BOXED(0x129bd20,32,FLEN)
NAN_BOXED(0x4effff00,32,FLEN)
NAN_BOXED(0x7dc10cb0,32,FLEN)
NAN_BOXED(0x129bd20,32,FLEN)
NAN_BOXED(0x4effff80,32,FLEN)
NAN_BOXED(0x7dc10cb0,32,FLEN)
NAN_BOXED(0x129bd20,32,FLEN)
NAN_BOXED(0x4effffc0,32,FLEN)
NAN_BOXED(0x7dc10cb0,32,FLEN)
NAN_BOXED(0x129bd20,32,FLEN)
NAN_BOXED(0x4effffe0,32,FLEN)
NAN_BOXED(0x7dc10cb0,32,FLEN)
NAN_BOXED(0x129bd20,32,FLEN)
NAN_BOXED(0x4efffff0,32,FLEN)
NAN_BOXED(0x7dc10cb0,32,FLEN)
NAN_BOXED(0x129bd20,32,FLEN)
NAN_BOXED(0x4efffff8,32,FLEN)
NAN_BOXED(0x7dc10cb0,32,FLEN)
NAN_BOXED(0x129bd20,32,FLEN)
NAN_BOXED(0x4efffffc,32,FLEN)
NAN_BOXED(0x7dc10cb0,32,FLEN)
NAN_BOXED(0x129bd20,32,FLEN)
NAN_BOXED(0x4efffffe,32,FLEN)
NAN_BOXED(0x7dc10cb0,32,FLEN)
NAN_BOXED(0x129bd20,32,FLEN)
NAN_BOXED(0x4effffff,32,FLEN)
NAN_BOXED(0x7dc686f0,32,FLEN)
NAN_BOXED(0x1250e37,32,FLEN)
NAN_BOXED(0x2a000000,32,FLEN)
NAN_BOXED(0x7dc686f0,32,FLEN)
NAN_BOXED(0x1250e37,32,FLEN)
NAN_BOXED(0x2a000001,32,FLEN)
NAN_BOXED(0x7dc686f0,32,FLEN)
NAN_BOXED(0x1250e37,32,FLEN)
NAN_BOXED(0x2a000003,32,FLEN)
NAN_BOXED(0x7dc686f0,32,FLEN)
NAN_BOXED(0x1250e37,32,FLEN)
NAN_BOXED(0x2a000007,32,FLEN)
NAN_BOXED(0x7dc686f0,32,FLEN)
NAN_BOXED(0x1250e37,32,FLEN)
NAN_BOXED(0x2a00000f,32,FLEN)
NAN_BOXED(0x7dc686f0,32,FLEN)
NAN_BOXED(0x1250e37,32,FLEN)
NAN_BOXED(0x2a00001f,32,FLEN)
NAN_BOXED(0x7dc686f0,32,FLEN)
NAN_BOXED(0x1250e37,32,FLEN)
NAN_BOXED(0x2a00003f,32,FLEN)
NAN_BOXED(0x7dc686f0,32,FLEN)
NAN_BOXED(0x1250e37,32,FLEN)
NAN_BOXED(0x2a00007f,32,FLEN)
NAN_BOXED(0x7dc686f0,32,FLEN)
NAN_BOXED(0x1250e37,32,FLEN)
NAN_BOXED(0x2a0000ff,32,FLEN)
NAN_BOXED(0x7dc686f0,32,FLEN)
NAN_BOXED(0x1250e37,32,FLEN)
NAN_BOXED(0x2a0001ff,32,FLEN)
NAN_BOXED(0x7dc686f0,32,FLEN)
NAN_BOXED(0x1250e37,32,FLEN)
NAN_BOXED(0x2a0003ff,32,FLEN)
NAN_BOXED(0x7dc686f0,32,FLEN)
NAN_BOXED(0x1250e37,32,FLEN)
NAN_BOXED(0x2a0007ff,32,FLEN)
NAN_BOXED(0x7dc686f0,32,FLEN)
NAN_BOXED(0x1250e37,32,FLEN)
NAN_BOXED(0x2a000fff,32,FLEN)
NAN_BOXED(0x7dc686f0,32,FLEN)
NAN_BOXED(0x1250e37,32,FLEN)
NAN_BOXED(0x2a001fff,32,FLEN)
NAN_BOXED(0x7dc686f0,32,FLEN)
NAN_BOXED(0x1250e37,32,FLEN)
NAN_BOXED(0x2a003fff,32,FLEN)
NAN_BOXED(0x7dc686f0,32,FLEN)
NAN_BOXED(0x1250e37,32,FLEN)
NAN_BOXED(0x2a007fff,32,FLEN)
NAN_BOXED(0x7dc686f0,32,FLEN)
NAN_BOXED(0x1250e37,32,FLEN)
NAN_BOXED(0x2a00ffff,32,FLEN)
NAN_BOXED(0x7dc686f0,32,FLEN)
NAN_BOXED(0x1250e37,32,FLEN)
NAN_BOXED(0x2a01ffff,32,FLEN)
NAN_BOXED(0x7dc686f0,32,FLEN)
NAN_BOXED(0x1250e37,32,FLEN)
NAN_BOXED(0x2a03ffff,32,FLEN)
NAN_BOXED(0x7dc686f0,32,FLEN)
NAN_BOXED(0x1250e37,32,FLEN)
NAN_BOXED(0x2a07ffff,32,FLEN)
NAN_BOXED(0x7dc686f0,32,FLEN)
NAN_BOXED(0x1250e37,32,FLEN)
NAN_BOXED(0x2a0fffff,32,FLEN)
NAN_BOXED(0x7dc686f0,32,FLEN)
NAN_BOXED(0x1250e37,32,FLEN)
NAN_BOXED(0x2a1fffff,32,FLEN)
NAN_BOXED(0x7dc686f0,32,FLEN)
NAN_BOXED(0x1250e37,32,FLEN)
NAN_BOXED(0x2a3fffff,32,FLEN)
NAN_BOXED(0x7dc686f0,32,FLEN)
NAN_BOXED(0x1250e37,32,FLEN)
NAN_BOXED(0x2a400000,32,FLEN)
NAN_BOXED(0x7dc686f0,32,FLEN)
NAN_BOXED(0x1250e37,32,FLEN)
NAN_BOXED(0x2a600000,32,FLEN)
NAN_BOXED(0x7dc686f0,32,FLEN)
NAN_BOXED(0x1250e37,32,FLEN)
NAN_BOXED(0x2a700000,32,FLEN)
NAN_BOXED(0x7dc686f0,32,FLEN)
NAN_BOXED(0x1250e37,32,FLEN)
NAN_BOXED(0x2a780000,32,FLEN)
NAN_BOXED(0x7dc686f0,32,FLEN)
NAN_BOXED(0x1250e37,32,FLEN)
NAN_BOXED(0x2a7c0000,32,FLEN)
NAN_BOXED(0x7dc686f0,32,FLEN)
NAN_BOXED(0x1250e37,32,FLEN)
NAN_BOXED(0x2a7e0000,32,FLEN)
NAN_BOXED(0x7dc686f0,32,FLEN)
NAN_BOXED(0x1250e37,32,FLEN)
NAN_BOXED(0x2a7f0000,32,FLEN)
NAN_BOXED(0x7dc686f0,32,FLEN)
NAN_BOXED(0x1250e37,32,FLEN)
NAN_BOXED(0x2a7f8000,32,FLEN)
NAN_BOXED(0x7dc686f0,32,FLEN)
NAN_BOXED(0x1250e37,32,FLEN)
NAN_BOXED(0x2a7fc000,32,FLEN)
NAN_BOXED(0x7dc686f0,32,FLEN)
NAN_BOXED(0x1250e37,32,FLEN)
NAN_BOXED(0x2a7fe000,32,FLEN)
NAN_BOXED(0x7dc686f0,32,FLEN)
NAN_BOXED(0x1250e37,32,FLEN)
NAN_BOXED(0x2a7ff000,32,FLEN)
NAN_BOXED(0x7dc686f0,32,FLEN)
NAN_BOXED(0x1250e37,32,FLEN)
NAN_BOXED(0x2a7ff800,32,FLEN)
NAN_BOXED(0x7dc686f0,32,FLEN)
NAN_BOXED(0x1250e37,32,FLEN)
NAN_BOXED(0x2a7ffc00,32,FLEN)
NAN_BOXED(0x7dc686f0,32,FLEN)
NAN_BOXED(0x1250e37,32,FLEN)
NAN_BOXED(0x2a7ffe00,32,FLEN)
NAN_BOXED(0x7dc686f0,32,FLEN)
NAN_BOXED(0x1250e37,32,FLEN)
NAN_BOXED(0x2a7fff00,32,FLEN)
NAN_BOXED(0x7dc686f0,32,FLEN)
NAN_BOXED(0x1250e37,32,FLEN)
NAN_BOXED(0x2a7fff80,32,FLEN)
NAN_BOXED(0x7dc686f0,32,FLEN)
NAN_BOXED(0x1250e37,32,FLEN)
NAN_BOXED(0x2a7fffc0,32,FLEN)
NAN_BOXED(0x7dc686f0,32,FLEN)
NAN_BOXED(0x1250e37,32,FLEN)
NAN_BOXED(0x2a7fffe0,32,FLEN)
NAN_BOXED(0x7dc686f0,32,FLEN)
NAN_BOXED(0x1250e37,32,FLEN)
NAN_BOXED(0x2a7ffff0,32,FLEN)
NAN_BOXED(0x7dc686f0,32,FLEN)
NAN_BOXED(0x1250e37,32,FLEN)
NAN_BOXED(0x2a7ffff8,32,FLEN)
NAN_BOXED(0x7dc686f0,32,FLEN)
NAN_BOXED(0x1250e37,32,FLEN)
NAN_BOXED(0x2a7ffffc,32,FLEN)
NAN_BOXED(0x7dc686f0,32,FLEN)
NAN_BOXED(0x1250e37,32,FLEN)
NAN_BOXED(0x2a7ffffe,32,FLEN)
NAN_BOXED(0x7dc686f0,32,FLEN)
NAN_BOXED(0x1250e37,32,FLEN)
NAN_BOXED(0x2a7fffff,32,FLEN)
NAN_BOXED(0x7dc686f0,32,FLEN)
NAN_BOXED(0x1250e37,32,FLEN)
NAN_BOXED(0x3f800001,32,FLEN)
NAN_BOXED(0x7dc686f0,32,FLEN)
NAN_BOXED(0x1250e37,32,FLEN)
NAN_BOXED(0x3f800003,32,FLEN)
NAN_BOXED(0x7dc686f0,32,FLEN)
NAN_BOXED(0x1250e37,32,FLEN)
NAN_BOXED(0x3f800007,32,FLEN)
NAN_BOXED(0x7dc686f0,32,FLEN)
NAN_BOXED(0x1250e37,32,FLEN)
NAN_BOXED(0x3f999999,32,FLEN)
NAN_BOXED(0x7dc686f0,32,FLEN)
NAN_BOXED(0x1250e37,32,FLEN)
NAN_BOXED(0x3fa49249,32,FLEN)
NAN_BOXED(0x7dc686f0,32,FLEN)
NAN_BOXED(0x1250e37,32,FLEN)
NAN_BOXED(0x3fb33333,32,FLEN)
NAN_BOXED(0x7dc686f0,32,FLEN)
NAN_BOXED(0x1250e37,32,FLEN)
NAN_BOXED(0x3fb6db6d,32,FLEN)
NAN_BOXED(0x7dc686f0,32,FLEN)
NAN_BOXED(0x1250e37,32,FLEN)
NAN_BOXED(0x3fbbbbbb,32,FLEN)
NAN_BOXED(0x7dc686f0,32,FLEN)
NAN_BOXED(0x1250e37,32,FLEN)
NAN_BOXED(0x3fc44444,32,FLEN)
NAN_BOXED(0x7dc686f0,32,FLEN)
NAN_BOXED(0x1250e37,32,FLEN)
NAN_BOXED(0x3fcccccc,32,FLEN)
NAN_BOXED(0x7dc686f0,32,FLEN)
NAN_BOXED(0x1250e37,32,FLEN)
NAN_BOXED(0x3fdb6db6,32,FLEN)
NAN_BOXED(0x7dc686f0,32,FLEN)
NAN_BOXED(0x1250e37,32,FLEN)
NAN_BOXED(0x3fe66666,32,FLEN)
NAN_BOXED(0x7dc686f0,32,FLEN)
NAN_BOXED(0x1250e37,32,FLEN)
NAN_BOXED(0x3fedb6db,32,FLEN)
NAN_BOXED(0x7dc686f0,32,FLEN)
NAN_BOXED(0x1250e37,32,FLEN)
NAN_BOXED(0x3ffffff8,32,FLEN)
NAN_BOXED(0x7dc686f0,32,FLEN)
NAN_BOXED(0x1250e37,32,FLEN)
NAN_BOXED(0x3ffffffc,32,FLEN)
NAN_BOXED(0x7dc686f0,32,FLEN)
NAN_BOXED(0x1250e37,32,FLEN)
NAN_BOXED(0x3ffffffe,32,FLEN)
NAN_BOXED(0x7dc847e0,32,FLEN)
NAN_BOXED(0x81239c3d,32,FLEN)
NAN_BOXED(0xa0800000,32,FLEN)
NAN_BOXED(0x7dc847e0,32,FLEN)
NAN_BOXED(0x81239c3d,32,FLEN)
NAN_BOXED(0xa0800001,32,FLEN)
NAN_BOXED(0x7dc847e0,32,FLEN)
NAN_BOXED(0x81239c3d,32,FLEN)
NAN_BOXED(0xa0800003,32,FLEN)
NAN_BOXED(0x7dc847e0,32,FLEN)
NAN_BOXED(0x81239c3d,32,FLEN)
NAN_BOXED(0xa0800007,32,FLEN)
NAN_BOXED(0x7dc847e0,32,FLEN)
NAN_BOXED(0x81239c3d,32,FLEN)
NAN_BOXED(0xa080000f,32,FLEN)
NAN_BOXED(0x7dc847e0,32,FLEN)
NAN_BOXED(0x81239c3d,32,FLEN)
NAN_BOXED(0xa080001f,32,FLEN)
NAN_BOXED(0x7dc847e0,32,FLEN)
NAN_BOXED(0x81239c3d,32,FLEN)
NAN_BOXED(0xa080003f,32,FLEN)
NAN_BOXED(0x7dc847e0,32,FLEN)
NAN_BOXED(0x81239c3d,32,FLEN)
NAN_BOXED(0xa080007f,32,FLEN)
NAN_BOXED(0x7dc847e0,32,FLEN)
NAN_BOXED(0x81239c3d,32,FLEN)
NAN_BOXED(0xa08000ff,32,FLEN)
NAN_BOXED(0x7dc847e0,32,FLEN)
NAN_BOXED(0x81239c3d,32,FLEN)
NAN_BOXED(0xa08001ff,32,FLEN)
NAN_BOXED(0x7dc847e0,32,FLEN)
NAN_BOXED(0x81239c3d,32,FLEN)
NAN_BOXED(0xa08003ff,32,FLEN)
NAN_BOXED(0x7dc847e0,32,FLEN)
NAN_BOXED(0x81239c3d,32,FLEN)
NAN_BOXED(0xa08007ff,32,FLEN)
NAN_BOXED(0x7dc847e0,32,FLEN)
NAN_BOXED(0x81239c3d,32,FLEN)
NAN_BOXED(0xa0800fff,32,FLEN)
NAN_BOXED(0x7dc847e0,32,FLEN)
NAN_BOXED(0x81239c3d,32,FLEN)
NAN_BOXED(0xa0801fff,32,FLEN)
NAN_BOXED(0x7dc847e0,32,FLEN)
NAN_BOXED(0x81239c3d,32,FLEN)
NAN_BOXED(0xa0803fff,32,FLEN)
NAN_BOXED(0x7dc847e0,32,FLEN)
NAN_BOXED(0x81239c3d,32,FLEN)
NAN_BOXED(0xa0807fff,32,FLEN)
NAN_BOXED(0x7dc847e0,32,FLEN)
NAN_BOXED(0x81239c3d,32,FLEN)
NAN_BOXED(0xa080ffff,32,FLEN)
NAN_BOXED(0x7dc847e0,32,FLEN)
NAN_BOXED(0x81239c3d,32,FLEN)
NAN_BOXED(0xa081ffff,32,FLEN)
NAN_BOXED(0x7dc847e0,32,FLEN)
NAN_BOXED(0x81239c3d,32,FLEN)
NAN_BOXED(0xa083ffff,32,FLEN)
NAN_BOXED(0x7dc847e0,32,FLEN)
NAN_BOXED(0x81239c3d,32,FLEN)
NAN_BOXED(0xa087ffff,32,FLEN)
NAN_BOXED(0x7dc847e0,32,FLEN)
NAN_BOXED(0x81239c3d,32,FLEN)
NAN_BOXED(0xa08fffff,32,FLEN)
NAN_BOXED(0x7dc847e0,32,FLEN)
NAN_BOXED(0x81239c3d,32,FLEN)
NAN_BOXED(0xa09fffff,32,FLEN)
NAN_BOXED(0x7dc847e0,32,FLEN)
NAN_BOXED(0x81239c3d,32,FLEN)
NAN_BOXED(0xa0bfffff,32,FLEN)
NAN_BOXED(0x7dc847e0,32,FLEN)
NAN_BOXED(0x81239c3d,32,FLEN)
NAN_BOXED(0xa0c00000,32,FLEN)
NAN_BOXED(0x7dc847e0,32,FLEN)
NAN_BOXED(0x81239c3d,32,FLEN)
NAN_BOXED(0xa0e00000,32,FLEN)
NAN_BOXED(0x7dc847e0,32,FLEN)
NAN_BOXED(0x81239c3d,32,FLEN)
NAN_BOXED(0xa0f00000,32,FLEN)
NAN_BOXED(0x7dc847e0,32,FLEN)
NAN_BOXED(0x81239c3d,32,FLEN)
NAN_BOXED(0xa0f80000,32,FLEN)
NAN_BOXED(0x7dc847e0,32,FLEN)
NAN_BOXED(0x81239c3d,32,FLEN)
NAN_BOXED(0xa0fc0000,32,FLEN)
NAN_BOXED(0x7dc847e0,32,FLEN)
NAN_BOXED(0x81239c3d,32,FLEN)
NAN_BOXED(0xa0fe0000,32,FLEN)
NAN_BOXED(0x7dc847e0,32,FLEN)
NAN_BOXED(0x81239c3d,32,FLEN)
NAN_BOXED(0xa0ff0000,32,FLEN)
NAN_BOXED(0x7dc847e0,32,FLEN)
NAN_BOXED(0x81239c3d,32,FLEN)
NAN_BOXED(0xa0ff8000,32,FLEN)
NAN_BOXED(0x7dc847e0,32,FLEN)
NAN_BOXED(0x81239c3d,32,FLEN)
NAN_BOXED(0xa0ffc000,32,FLEN)
NAN_BOXED(0x7dc847e0,32,FLEN)
NAN_BOXED(0x81239c3d,32,FLEN)
NAN_BOXED(0xa0ffe000,32,FLEN)
NAN_BOXED(0x7dc847e0,32,FLEN)
NAN_BOXED(0x81239c3d,32,FLEN)
NAN_BOXED(0xa0fff000,32,FLEN)
NAN_BOXED(0x7dc847e0,32,FLEN)
NAN_BOXED(0x81239c3d,32,FLEN)
NAN_BOXED(0xa0fff800,32,FLEN)
NAN_BOXED(0x7dc847e0,32,FLEN)
NAN_BOXED(0x81239c3d,32,FLEN)
NAN_BOXED(0xa0fffc00,32,FLEN)
NAN_BOXED(0x7dc847e0,32,FLEN)
NAN_BOXED(0x81239c3d,32,FLEN)
NAN_BOXED(0xa0fffe00,32,FLEN)
NAN_BOXED(0x7dc847e0,32,FLEN)
NAN_BOXED(0x81239c3d,32,FLEN)
NAN_BOXED(0xa0ffff00,32,FLEN)
NAN_BOXED(0x7dc847e0,32,FLEN)
NAN_BOXED(0x81239c3d,32,FLEN)
NAN_BOXED(0xa0ffff80,32,FLEN)
NAN_BOXED(0x7dc847e0,32,FLEN)
NAN_BOXED(0x81239c3d,32,FLEN)
NAN_BOXED(0xa0ffffc0,32,FLEN)
NAN_BOXED(0x7dc847e0,32,FLEN)
NAN_BOXED(0x81239c3d,32,FLEN)
NAN_BOXED(0xa0ffffe0,32,FLEN)
NAN_BOXED(0x7dc847e0,32,FLEN)
NAN_BOXED(0x81239c3d,32,FLEN)
NAN_BOXED(0xa0fffff0,32,FLEN)
NAN_BOXED(0x7dc847e0,32,FLEN)
NAN_BOXED(0x81239c3d,32,FLEN)
NAN_BOXED(0xa0fffff8,32,FLEN)
NAN_BOXED(0x7dc847e0,32,FLEN)
NAN_BOXED(0x81239c3d,32,FLEN)
NAN_BOXED(0xa0fffffc,32,FLEN)
NAN_BOXED(0x7dc847e0,32,FLEN)
NAN_BOXED(0x81239c3d,32,FLEN)
NAN_BOXED(0xa0fffffe,32,FLEN)
NAN_BOXED(0x7dc847e0,32,FLEN)
NAN_BOXED(0x81239c3d,32,FLEN)
NAN_BOXED(0xa0ffffff,32,FLEN)
NAN_BOXED(0x7dc847e0,32,FLEN)
NAN_BOXED(0x81239c3d,32,FLEN)
NAN_BOXED(0xbf800001,32,FLEN)
NAN_BOXED(0x7dc847e0,32,FLEN)
NAN_BOXED(0x81239c3d,32,FLEN)
NAN_BOXED(0xbf800003,32,FLEN)
NAN_BOXED(0x7dc847e0,32,FLEN)
NAN_BOXED(0x81239c3d,32,FLEN)
NAN_BOXED(0xbf800007,32,FLEN)
NAN_BOXED(0x7dc847e0,32,FLEN)
NAN_BOXED(0x81239c3d,32,FLEN)
NAN_BOXED(0xbf999999,32,FLEN)
NAN_BOXED(0x7dc847e0,32,FLEN)
NAN_BOXED(0x81239c3d,32,FLEN)
NAN_BOXED(0xbfa49249,32,FLEN)
NAN_BOXED(0x7dc847e0,32,FLEN)
NAN_BOXED(0x81239c3d,32,FLEN)
NAN_BOXED(0xbfb33333,32,FLEN)
NAN_BOXED(0x7dc847e0,32,FLEN)
NAN_BOXED(0x81239c3d,32,FLEN)
NAN_BOXED(0xbfb6db6d,32,FLEN)
NAN_BOXED(0x7dc847e0,32,FLEN)
NAN_BOXED(0x81239c3d,32,FLEN)
NAN_BOXED(0xbfbbbbbb,32,FLEN)
NAN_BOXED(0x7dc847e0,32,FLEN)
NAN_BOXED(0x81239c3d,32,FLEN)
NAN_BOXED(0xbfc44444,32,FLEN)
NAN_BOXED(0x7dc847e0,32,FLEN)
NAN_BOXED(0x81239c3d,32,FLEN)
NAN_BOXED(0xbfcccccc,32,FLEN)
NAN_BOXED(0x7dc847e0,32,FLEN)
NAN_BOXED(0x81239c3d,32,FLEN)
NAN_BOXED(0xbfdb6db6,32,FLEN)
NAN_BOXED(0x7dc847e0,32,FLEN)
NAN_BOXED(0x81239c3d,32,FLEN)
NAN_BOXED(0xbfe66666,32,FLEN)
NAN_BOXED(0x7dc847e0,32,FLEN)
NAN_BOXED(0x81239c3d,32,FLEN)
NAN_BOXED(0xbfedb6db,32,FLEN)
NAN_BOXED(0x7dc847e0,32,FLEN)
NAN_BOXED(0x81239c3d,32,FLEN)
NAN_BOXED(0xbffffff8,32,FLEN)
NAN_BOXED(0x7dc847e0,32,FLEN)
NAN_BOXED(0x81239c3d,32,FLEN)
NAN_BOXED(0xbffffffc,32,FLEN)
NAN_BOXED(0x7dc847e0,32,FLEN)
NAN_BOXED(0x81239c3d,32,FLEN)
NAN_BOXED(0xbffffffe,32,FLEN)
NAN_BOXED(0x7dcc506a,32,FLEN)
NAN_BOXED(0x81206168,32,FLEN)
NAN_BOXED(0xb5800000,32,FLEN)
NAN_BOXED(0x7dcc506a,32,FLEN)
NAN_BOXED(0x81206168,32,FLEN)
NAN_BOXED(0xb5800001,32,FLEN)
NAN_BOXED(0x7dcc506a,32,FLEN)
NAN_BOXED(0x81206168,32,FLEN)
NAN_BOXED(0xb5800003,32,FLEN)
NAN_BOXED(0x7dcc506a,32,FLEN)
NAN_BOXED(0x81206168,32,FLEN)
NAN_BOXED(0xb5800007,32,FLEN)
NAN_BOXED(0x7dcc506a,32,FLEN)
NAN_BOXED(0x81206168,32,FLEN)
NAN_BOXED(0xb580000f,32,FLEN)
NAN_BOXED(0x7dcc506a,32,FLEN)
NAN_BOXED(0x81206168,32,FLEN)
NAN_BOXED(0xb580001f,32,FLEN)
NAN_BOXED(0x7dcc506a,32,FLEN)
NAN_BOXED(0x81206168,32,FLEN)
NAN_BOXED(0xb580003f,32,FLEN)
NAN_BOXED(0x7dcc506a,32,FLEN)
NAN_BOXED(0x81206168,32,FLEN)
NAN_BOXED(0xb580007f,32,FLEN)
NAN_BOXED(0x7dcc506a,32,FLEN)
NAN_BOXED(0x81206168,32,FLEN)
NAN_BOXED(0xb58000ff,32,FLEN)
NAN_BOXED(0x7dcc506a,32,FLEN)
NAN_BOXED(0x81206168,32,FLEN)
NAN_BOXED(0xb58001ff,32,FLEN)
NAN_BOXED(0x7dcc506a,32,FLEN)
NAN_BOXED(0x81206168,32,FLEN)
NAN_BOXED(0xb58003ff,32,FLEN)
NAN_BOXED(0x7dcc506a,32,FLEN)
NAN_BOXED(0x81206168,32,FLEN)
NAN_BOXED(0xb58007ff,32,FLEN)
NAN_BOXED(0x7dcc506a,32,FLEN)
NAN_BOXED(0x81206168,32,FLEN)
NAN_BOXED(0xb5800fff,32,FLEN)
NAN_BOXED(0x7dcc506a,32,FLEN)
NAN_BOXED(0x81206168,32,FLEN)
NAN_BOXED(0xb5801fff,32,FLEN)
NAN_BOXED(0x7dcc506a,32,FLEN)
NAN_BOXED(0x81206168,32,FLEN)
NAN_BOXED(0xb5803fff,32,FLEN)
NAN_BOXED(0x7dcc506a,32,FLEN)
NAN_BOXED(0x81206168,32,FLEN)
NAN_BOXED(0xb5807fff,32,FLEN)
NAN_BOXED(0x7dcc506a,32,FLEN)
NAN_BOXED(0x81206168,32,FLEN)
NAN_BOXED(0xb580ffff,32,FLEN)
NAN_BOXED(0x7dcc506a,32,FLEN)
NAN_BOXED(0x81206168,32,FLEN)
NAN_BOXED(0xb581ffff,32,FLEN)
NAN_BOXED(0x7dcc506a,32,FLEN)
NAN_BOXED(0x81206168,32,FLEN)
NAN_BOXED(0xb583ffff,32,FLEN)
NAN_BOXED(0x7dcc506a,32,FLEN)
NAN_BOXED(0x81206168,32,FLEN)
NAN_BOXED(0xb587ffff,32,FLEN)
NAN_BOXED(0x7dcc506a,32,FLEN)
NAN_BOXED(0x81206168,32,FLEN)
NAN_BOXED(0xb58fffff,32,FLEN)
NAN_BOXED(0x7dcc506a,32,FLEN)
NAN_BOXED(0x81206168,32,FLEN)
NAN_BOXED(0xb59fffff,32,FLEN)
NAN_BOXED(0x7dcc506a,32,FLEN)
NAN_BOXED(0x81206168,32,FLEN)
NAN_BOXED(0xb5bfffff,32,FLEN)
NAN_BOXED(0x7dcc506a,32,FLEN)
NAN_BOXED(0x81206168,32,FLEN)
NAN_BOXED(0xb5c00000,32,FLEN)
NAN_BOXED(0x7dcc506a,32,FLEN)
NAN_BOXED(0x81206168,32,FLEN)
NAN_BOXED(0xb5e00000,32,FLEN)
NAN_BOXED(0x7dcc506a,32,FLEN)
NAN_BOXED(0x81206168,32,FLEN)
NAN_BOXED(0xb5f00000,32,FLEN)
NAN_BOXED(0x7dcc506a,32,FLEN)
NAN_BOXED(0x81206168,32,FLEN)
NAN_BOXED(0xb5f80000,32,FLEN)
NAN_BOXED(0x7dcc506a,32,FLEN)
NAN_BOXED(0x81206168,32,FLEN)
NAN_BOXED(0xb5fc0000,32,FLEN)
NAN_BOXED(0x7dcc506a,32,FLEN)
NAN_BOXED(0x81206168,32,FLEN)
NAN_BOXED(0xb5fe0000,32,FLEN)
NAN_BOXED(0x7dcc506a,32,FLEN)
NAN_BOXED(0x81206168,32,FLEN)
NAN_BOXED(0xb5ff0000,32,FLEN)
NAN_BOXED(0x7dcc506a,32,FLEN)
NAN_BOXED(0x81206168,32,FLEN)
NAN_BOXED(0xb5ff8000,32,FLEN)
NAN_BOXED(0x7dcc506a,32,FLEN)
NAN_BOXED(0x81206168,32,FLEN)
NAN_BOXED(0xb5ffc000,32,FLEN)
NAN_BOXED(0x7dcc506a,32,FLEN)
NAN_BOXED(0x81206168,32,FLEN)
NAN_BOXED(0xb5ffe000,32,FLEN)
NAN_BOXED(0x7dcc506a,32,FLEN)
NAN_BOXED(0x81206168,32,FLEN)
NAN_BOXED(0xb5fff000,32,FLEN)
NAN_BOXED(0x7dcc506a,32,FLEN)
NAN_BOXED(0x81206168,32,FLEN)
NAN_BOXED(0xb5fff800,32,FLEN)
NAN_BOXED(0x7dcc506a,32,FLEN)
NAN_BOXED(0x81206168,32,FLEN)
NAN_BOXED(0xb5fffc00,32,FLEN)
NAN_BOXED(0x7dcc506a,32,FLEN)
NAN_BOXED(0x81206168,32,FLEN)
NAN_BOXED(0xb5fffe00,32,FLEN)
NAN_BOXED(0x7dcc506a,32,FLEN)
NAN_BOXED(0x81206168,32,FLEN)
NAN_BOXED(0xb5ffff00,32,FLEN)
NAN_BOXED(0x7dcc506a,32,FLEN)
NAN_BOXED(0x81206168,32,FLEN)
NAN_BOXED(0xb5ffff80,32,FLEN)
NAN_BOXED(0x7dcc506a,32,FLEN)
NAN_BOXED(0x81206168,32,FLEN)
NAN_BOXED(0xb5ffffc0,32,FLEN)
NAN_BOXED(0x7dcc506a,32,FLEN)
NAN_BOXED(0x81206168,32,FLEN)
NAN_BOXED(0xb5ffffe0,32,FLEN)
NAN_BOXED(0x7dcc506a,32,FLEN)
NAN_BOXED(0x81206168,32,FLEN)
NAN_BOXED(0xb5fffff0,32,FLEN)
NAN_BOXED(0x7dcc506a,32,FLEN)
NAN_BOXED(0x81206168,32,FLEN)
NAN_BOXED(0xb5fffff8,32,FLEN)
NAN_BOXED(0x7dcc506a,32,FLEN)
NAN_BOXED(0x81206168,32,FLEN)
NAN_BOXED(0xb5fffffc,32,FLEN)
NAN_BOXED(0x7dcc506a,32,FLEN)
NAN_BOXED(0x81206168,32,FLEN)
NAN_BOXED(0xb5fffffe,32,FLEN)
NAN_BOXED(0x7dcc506a,32,FLEN)
NAN_BOXED(0x81206168,32,FLEN)
NAN_BOXED(0xb5ffffff,32,FLEN)
NAN_BOXED(0x7dcc506a,32,FLEN)
NAN_BOXED(0x81206168,32,FLEN)
NAN_BOXED(0xbf800001,32,FLEN)
NAN_BOXED(0x7dcc506a,32,FLEN)
NAN_BOXED(0x81206168,32,FLEN)
NAN_BOXED(0xbf800003,32,FLEN)
NAN_BOXED(0x7dcc506a,32,FLEN)
NAN_BOXED(0x81206168,32,FLEN)
NAN_BOXED(0xbf800007,32,FLEN)
NAN_BOXED(0x7dcc506a,32,FLEN)
NAN_BOXED(0x81206168,32,FLEN)
NAN_BOXED(0xbf999999,32,FLEN)
NAN_BOXED(0x7dcc506a,32,FLEN)
NAN_BOXED(0x81206168,32,FLEN)
NAN_BOXED(0xbfa49249,32,FLEN)
NAN_BOXED(0x7dcc506a,32,FLEN)
NAN_BOXED(0x81206168,32,FLEN)
NAN_BOXED(0xbfb33333,32,FLEN)
NAN_BOXED(0x7dcc506a,32,FLEN)
NAN_BOXED(0x81206168,32,FLEN)
NAN_BOXED(0xbfb6db6d,32,FLEN)
NAN_BOXED(0x7dcc506a,32,FLEN)
NAN_BOXED(0x81206168,32,FLEN)
NAN_BOXED(0xbfbbbbbb,32,FLEN)
NAN_BOXED(0x7dcc506a,32,FLEN)
NAN_BOXED(0x81206168,32,FLEN)
NAN_BOXED(0xbfc44444,32,FLEN)
NAN_BOXED(0x7dcc506a,32,FLEN)
NAN_BOXED(0x81206168,32,FLEN)
NAN_BOXED(0xbfcccccc,32,FLEN)
NAN_BOXED(0x7dcc506a,32,FLEN)
NAN_BOXED(0x81206168,32,FLEN)
NAN_BOXED(0xbfdb6db6,32,FLEN)
NAN_BOXED(0x7dcc506a,32,FLEN)
NAN_BOXED(0x81206168,32,FLEN)
NAN_BOXED(0xbfe66666,32,FLEN)
NAN_BOXED(0x7dcc506a,32,FLEN)
NAN_BOXED(0x81206168,32,FLEN)
NAN_BOXED(0xbfedb6db,32,FLEN)
NAN_BOXED(0x7dcc506a,32,FLEN)
NAN_BOXED(0x81206168,32,FLEN)
NAN_BOXED(0xbffffff8,32,FLEN)
NAN_BOXED(0x7dcc506a,32,FLEN)
NAN_BOXED(0x81206168,32,FLEN)
NAN_BOXED(0xbffffffc,32,FLEN)
NAN_BOXED(0x7dcc506a,32,FLEN)
NAN_BOXED(0x81206168,32,FLEN)
NAN_BOXED(0xbffffffe,32,FLEN)
NAN_BOXED(0x7dce622b,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x7dce622b,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x1,32,FLEN)
NAN_BOXED(0x7dce622b,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x3,32,FLEN)
NAN_BOXED(0x7dce622b,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x7,32,FLEN)
NAN_BOXED(0x7dce622b,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xf,32,FLEN)
NAN_BOXED(0x7dce622b,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x1f,32,FLEN)
NAN_BOXED(0x7dce622b,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x3f,32,FLEN)
NAN_BOXED(0x7dce622b,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x7f,32,FLEN)
NAN_BOXED(0x7dce622b,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xff,32,FLEN)
NAN_BOXED(0x7dce622b,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x1ff,32,FLEN)
NAN_BOXED(0x7dce622b,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x3ff,32,FLEN)
NAN_BOXED(0x7dce622b,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x7ff,32,FLEN)
NAN_BOXED(0x7dce622b,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xfff,32,FLEN)
NAN_BOXED(0x7dce622b,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x1fff,32,FLEN)
NAN_BOXED(0x7dce622b,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x3fff,32,FLEN)
NAN_BOXED(0x7dce622b,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x7fff,32,FLEN)
NAN_BOXED(0x7dce622b,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xffff,32,FLEN)
NAN_BOXED(0x7dce622b,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x1ffff,32,FLEN)
NAN_BOXED(0x7dce622b,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x3ffff,32,FLEN)
NAN_BOXED(0x7dce622b,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x7ffff,32,FLEN)
NAN_BOXED(0x7dce622b,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xfffff,32,FLEN)
NAN_BOXED(0x7dce622b,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x199999,32,FLEN)
NAN_BOXED(0x7dce622b,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x1fffff,32,FLEN)
NAN_BOXED(0x7dce622b,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x249249,32,FLEN)
NAN_BOXED(0x7dce622b,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x333333,32,FLEN)
NAN_BOXED(0x7dce622b,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x36db6d,32,FLEN)
NAN_BOXED(0x7dce622b,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x3bbbbb,32,FLEN)
NAN_BOXED(0x7dce622b,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x3fffff,32,FLEN)
NAN_BOXED(0x7dce622b,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x400000,32,FLEN)
NAN_BOXED(0x7dce622b,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x444444,32,FLEN)
NAN_BOXED(0x7dce622b,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x4ccccc,32,FLEN)
NAN_BOXED(0x7dce622b,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x5b6db6,32,FLEN)
NAN_BOXED(0x7dce622b,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x600000,32,FLEN)
NAN_BOXED(0x7dce622b,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x666666,32,FLEN)
NAN_BOXED(0x7dce622b,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x6db6db,32,FLEN)
NAN_BOXED(0x7dce622b,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x700000,32,FLEN)
NAN_BOXED(0x7dce622b,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x780000,32,FLEN)
NAN_BOXED(0x7dce622b,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x7c0000,32,FLEN)
NAN_BOXED(0x7dce622b,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x7e0000,32,FLEN)
NAN_BOXED(0x7dce622b,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x7f0000,32,FLEN)
NAN_BOXED(0x7dce622b,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x7f8000,32,FLEN)
NAN_BOXED(0x7dce622b,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x7fc000,32,FLEN)
NAN_BOXED(0x7dce622b,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x7fe000,32,FLEN)
NAN_BOXED(0x7dce622b,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x7ff000,32,FLEN)
NAN_BOXED(0x7dce622b,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x7ff800,32,FLEN)
NAN_BOXED(0x7dce622b,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x7ffc00,32,FLEN)
NAN_BOXED(0x7dce622b,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x7ffe00,32,FLEN)
NAN_BOXED(0x7dce622b,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x7fff00,32,FLEN)
NAN_BOXED(0x7dce622b,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x7fff80,32,FLEN)
NAN_BOXED(0x7dce622b,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x7fffc0,32,FLEN)
NAN_BOXED(0x7dce622b,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x7fffe0,32,FLEN)
NAN_BOXED(0x7dce622b,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x7ffff0,32,FLEN)
NAN_BOXED(0x7dce622b,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x7ffff8,32,FLEN)
NAN_BOXED(0x7dce622b,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x7ffffc,32,FLEN)
NAN_BOXED(0x7dce622b,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x7ffffe,32,FLEN)
NAN_BOXED(0x7dce622b,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x7fffff,32,FLEN)
NAN_BOXED(0x7dcf9471,32,FLEN)
NAN_BOXED(0x811ddb79,32,FLEN)
NAN_BOXED(0xaf000000,32,FLEN)
NAN_BOXED(0x7dcf9471,32,FLEN)
NAN_BOXED(0x811ddb79,32,FLEN)
NAN_BOXED(0xaf000001,32,FLEN)
NAN_BOXED(0x7dcf9471,32,FLEN)
NAN_BOXED(0x811ddb79,32,FLEN)
NAN_BOXED(0xaf000003,32,FLEN)
NAN_BOXED(0x7dcf9471,32,FLEN)
NAN_BOXED(0x811ddb79,32,FLEN)
NAN_BOXED(0xaf000007,32,FLEN)
NAN_BOXED(0x7dcf9471,32,FLEN)
NAN_BOXED(0x811ddb79,32,FLEN)
NAN_BOXED(0xaf00000f,32,FLEN)
NAN_BOXED(0x7dcf9471,32,FLEN)
NAN_BOXED(0x811ddb79,32,FLEN)
NAN_BOXED(0xaf00001f,32,FLEN)
NAN_BOXED(0x7dcf9471,32,FLEN)
NAN_BOXED(0x811ddb79,32,FLEN)
NAN_BOXED(0xaf00003f,32,FLEN)
NAN_BOXED(0x7dcf9471,32,FLEN)
NAN_BOXED(0x811ddb79,32,FLEN)
NAN_BOXED(0xaf00007f,32,FLEN)
NAN_BOXED(0x7dcf9471,32,FLEN)
NAN_BOXED(0x811ddb79,32,FLEN)
NAN_BOXED(0xaf0000ff,32,FLEN)
NAN_BOXED(0x7dcf9471,32,FLEN)
NAN_BOXED(0x811ddb79,32,FLEN)
NAN_BOXED(0xaf0001ff,32,FLEN)
NAN_BOXED(0x7dcf9471,32,FLEN)
NAN_BOXED(0x811ddb79,32,FLEN)
NAN_BOXED(0xaf0003ff,32,FLEN)
NAN_BOXED(0x7dcf9471,32,FLEN)
NAN_BOXED(0x811ddb79,32,FLEN)
NAN_BOXED(0xaf0007ff,32,FLEN)
NAN_BOXED(0x7dcf9471,32,FLEN)
NAN_BOXED(0x811ddb79,32,FLEN)
NAN_BOXED(0xaf000fff,32,FLEN)
NAN_BOXED(0x7dcf9471,32,FLEN)
NAN_BOXED(0x811ddb79,32,FLEN)
NAN_BOXED(0xaf001fff,32,FLEN)
NAN_BOXED(0x7dcf9471,32,FLEN)
NAN_BOXED(0x811ddb79,32,FLEN)
NAN_BOXED(0xaf003fff,32,FLEN)
NAN_BOXED(0x7dcf9471,32,FLEN)
NAN_BOXED(0x811ddb79,32,FLEN)
NAN_BOXED(0xaf007fff,32,FLEN)
NAN_BOXED(0x7dcf9471,32,FLEN)
NAN_BOXED(0x811ddb79,32,FLEN)
NAN_BOXED(0xaf00ffff,32,FLEN)
NAN_BOXED(0x7dcf9471,32,FLEN)
NAN_BOXED(0x811ddb79,32,FLEN)
NAN_BOXED(0xaf01ffff,32,FLEN)
NAN_BOXED(0x7dcf9471,32,FLEN)
NAN_BOXED(0x811ddb79,32,FLEN)
NAN_BOXED(0xaf03ffff,32,FLEN)
NAN_BOXED(0x7dcf9471,32,FLEN)
NAN_BOXED(0x811ddb79,32,FLEN)
NAN_BOXED(0xaf07ffff,32,FLEN)
NAN_BOXED(0x7dcf9471,32,FLEN)
NAN_BOXED(0x811ddb79,32,FLEN)
NAN_BOXED(0xaf0fffff,32,FLEN)
NAN_BOXED(0x7dcf9471,32,FLEN)
NAN_BOXED(0x811ddb79,32,FLEN)
NAN_BOXED(0xaf1fffff,32,FLEN)
NAN_BOXED(0x7dcf9471,32,FLEN)
NAN_BOXED(0x811ddb79,32,FLEN)
NAN_BOXED(0xaf3fffff,32,FLEN)
NAN_BOXED(0x7dcf9471,32,FLEN)
NAN_BOXED(0x811ddb79,32,FLEN)
NAN_BOXED(0xaf400000,32,FLEN)
NAN_BOXED(0x7dcf9471,32,FLEN)
NAN_BOXED(0x811ddb79,32,FLEN)
NAN_BOXED(0xaf600000,32,FLEN)
NAN_BOXED(0x7dcf9471,32,FLEN)
NAN_BOXED(0x811ddb79,32,FLEN)
NAN_BOXED(0xaf700000,32,FLEN)
NAN_BOXED(0x7dcf9471,32,FLEN)
NAN_BOXED(0x811ddb79,32,FLEN)
NAN_BOXED(0xaf780000,32,FLEN)
NAN_BOXED(0x7dcf9471,32,FLEN)
NAN_BOXED(0x811ddb79,32,FLEN)
NAN_BOXED(0xaf7c0000,32,FLEN)
NAN_BOXED(0x7dcf9471,32,FLEN)
NAN_BOXED(0x811ddb79,32,FLEN)
NAN_BOXED(0xaf7e0000,32,FLEN)
NAN_BOXED(0x7dcf9471,32,FLEN)
NAN_BOXED(0x811ddb79,32,FLEN)
NAN_BOXED(0xaf7f0000,32,FLEN)
NAN_BOXED(0x7dcf9471,32,FLEN)
NAN_BOXED(0x811ddb79,32,FLEN)
NAN_BOXED(0xaf7f8000,32,FLEN)
NAN_BOXED(0x7dcf9471,32,FLEN)
NAN_BOXED(0x811ddb79,32,FLEN)
NAN_BOXED(0xaf7fc000,32,FLEN)
NAN_BOXED(0x7dcf9471,32,FLEN)
NAN_BOXED(0x811ddb79,32,FLEN)
NAN_BOXED(0xaf7fe000,32,FLEN)
NAN_BOXED(0x7dcf9471,32,FLEN)
NAN_BOXED(0x811ddb79,32,FLEN)
NAN_BOXED(0xaf7ff000,32,FLEN)
NAN_BOXED(0x7dcf9471,32,FLEN)
NAN_BOXED(0x811ddb79,32,FLEN)
NAN_BOXED(0xaf7ff800,32,FLEN)
NAN_BOXED(0x7dcf9471,32,FLEN)
NAN_BOXED(0x811ddb79,32,FLEN)
NAN_BOXED(0xaf7ffc00,32,FLEN)
NAN_BOXED(0x7dcf9471,32,FLEN)
NAN_BOXED(0x811ddb79,32,FLEN)
NAN_BOXED(0xaf7ffe00,32,FLEN)
NAN_BOXED(0x7dcf9471,32,FLEN)
NAN_BOXED(0x811ddb79,32,FLEN)
NAN_BOXED(0xaf7fff00,32,FLEN)
NAN_BOXED(0x7dcf9471,32,FLEN)
NAN_BOXED(0x811ddb79,32,FLEN)
NAN_BOXED(0xaf7fff80,32,FLEN)
NAN_BOXED(0x7dcf9471,32,FLEN)
NAN_BOXED(0x811ddb79,32,FLEN)
NAN_BOXED(0xaf7fffc0,32,FLEN)
NAN_BOXED(0x7dcf9471,32,FLEN)
NAN_BOXED(0x811ddb79,32,FLEN)
NAN_BOXED(0xaf7fffe0,32,FLEN)
NAN_BOXED(0x7dcf9471,32,FLEN)
NAN_BOXED(0x811ddb79,32,FLEN)
NAN_BOXED(0xaf7ffff0,32,FLEN)
NAN_BOXED(0x7dcf9471,32,FLEN)
NAN_BOXED(0x811ddb79,32,FLEN)
NAN_BOXED(0xaf7ffff8,32,FLEN)
NAN_BOXED(0x7dcf9471,32,FLEN)
NAN_BOXED(0x811ddb79,32,FLEN)
NAN_BOXED(0xaf7ffffc,32,FLEN)
NAN_BOXED(0x7dcf9471,32,FLEN)
NAN_BOXED(0x811ddb79,32,FLEN)
NAN_BOXED(0xaf7ffffe,32,FLEN)
NAN_BOXED(0x7dcf9471,32,FLEN)
NAN_BOXED(0x811ddb79,32,FLEN)
NAN_BOXED(0xaf7fffff,32,FLEN)
NAN_BOXED(0x7dcf9471,32,FLEN)
NAN_BOXED(0x811ddb79,32,FLEN)
NAN_BOXED(0xbf800001,32,FLEN)
NAN_BOXED(0x7dcf9471,32,FLEN)
NAN_BOXED(0x811ddb79,32,FLEN)
NAN_BOXED(0xbf800003,32,FLEN)
NAN_BOXED(0x7dcf9471,32,FLEN)
NAN_BOXED(0x811ddb79,32,FLEN)
NAN_BOXED(0xbf800007,32,FLEN)
NAN_BOXED(0x7dcf9471,32,FLEN)
NAN_BOXED(0x811ddb79,32,FLEN)
NAN_BOXED(0xbf999999,32,FLEN)
NAN_BOXED(0x7dcf9471,32,FLEN)
NAN_BOXED(0x811ddb79,32,FLEN)
NAN_BOXED(0xbfa49249,32,FLEN)
NAN_BOXED(0x7dcf9471,32,FLEN)
NAN_BOXED(0x811ddb79,32,FLEN)
NAN_BOXED(0xbfb33333,32,FLEN)
NAN_BOXED(0x7dcf9471,32,FLEN)
NAN_BOXED(0x811ddb79,32,FLEN)
NAN_BOXED(0xbfb6db6d,32,FLEN)
NAN_BOXED(0x7dcf9471,32,FLEN)
NAN_BOXED(0x811ddb79,32,FLEN)
NAN_BOXED(0xbfbbbbbb,32,FLEN)
NAN_BOXED(0x7dcf9471,32,FLEN)
NAN_BOXED(0x811ddb79,32,FLEN)
NAN_BOXED(0xbfc44444,32,FLEN)
NAN_BOXED(0x7dcf9471,32,FLEN)
NAN_BOXED(0x811ddb79,32,FLEN)
NAN_BOXED(0xbfcccccc,32,FLEN)
NAN_BOXED(0x7dcf9471,32,FLEN)
NAN_BOXED(0x811ddb79,32,FLEN)
NAN_BOXED(0xbfdb6db6,32,FLEN)
NAN_BOXED(0x7dcf9471,32,FLEN)
NAN_BOXED(0x811ddb79,32,FLEN)
NAN_BOXED(0xbfe66666,32,FLEN)
NAN_BOXED(0x7dcf9471,32,FLEN)
NAN_BOXED(0x811ddb79,32,FLEN)
NAN_BOXED(0xbfedb6db,32,FLEN)
NAN_BOXED(0x7dcf9471,32,FLEN)
NAN_BOXED(0x811ddb79,32,FLEN)
NAN_BOXED(0xbffffff8,32,FLEN)
NAN_BOXED(0x7dcf9471,32,FLEN)
NAN_BOXED(0x811ddb79,32,FLEN)
NAN_BOXED(0xbffffffc,32,FLEN)
NAN_BOXED(0x7dcf9471,32,FLEN)
NAN_BOXED(0x811ddb79,32,FLEN)
NAN_BOXED(0xbffffffe,32,FLEN)
NAN_BOXED(0x7dd1cef3,32,FLEN)
NAN_BOXED(0x411c2e3a,32,FLEN)
NAN_BOXED(0x60800000,32,FLEN)
NAN_BOXED(0x7dd1cef3,32,FLEN)
NAN_BOXED(0x411c2e3a,32,FLEN)
NAN_BOXED(0x60800001,32,FLEN)
NAN_BOXED(0x7dd1cef3,32,FLEN)
NAN_BOXED(0x411c2e3a,32,FLEN)
NAN_BOXED(0x60800003,32,FLEN)
NAN_BOXED(0x7dd1cef3,32,FLEN)
NAN_BOXED(0x411c2e3a,32,FLEN)
NAN_BOXED(0x60800007,32,FLEN)
NAN_BOXED(0x7dd1cef3,32,FLEN)
NAN_BOXED(0x411c2e3a,32,FLEN)
NAN_BOXED(0x6080000f,32,FLEN)
NAN_BOXED(0x7dd1cef3,32,FLEN)
NAN_BOXED(0x411c2e3a,32,FLEN)
NAN_BOXED(0x6080001f,32,FLEN)
NAN_BOXED(0x7dd1cef3,32,FLEN)
NAN_BOXED(0x411c2e3a,32,FLEN)
NAN_BOXED(0x6080003f,32,FLEN)
NAN_BOXED(0x7dd1cef3,32,FLEN)
NAN_BOXED(0x411c2e3a,32,FLEN)
NAN_BOXED(0x6080007f,32,FLEN)
NAN_BOXED(0x7dd1cef3,32,FLEN)
NAN_BOXED(0x411c2e3a,32,FLEN)
NAN_BOXED(0x608000ff,32,FLEN)
NAN_BOXED(0x7dd1cef3,32,FLEN)
NAN_BOXED(0x411c2e3a,32,FLEN)
NAN_BOXED(0x608001ff,32,FLEN)
NAN_BOXED(0x7dd1cef3,32,FLEN)
NAN_BOXED(0x411c2e3a,32,FLEN)
NAN_BOXED(0x608003ff,32,FLEN)
NAN_BOXED(0x7dd1cef3,32,FLEN)
NAN_BOXED(0x411c2e3a,32,FLEN)
NAN_BOXED(0x608007ff,32,FLEN)
NAN_BOXED(0x7dd1cef3,32,FLEN)
NAN_BOXED(0x411c2e3a,32,FLEN)
NAN_BOXED(0x60800fff,32,FLEN)
NAN_BOXED(0x7dd1cef3,32,FLEN)
NAN_BOXED(0x411c2e3a,32,FLEN)
NAN_BOXED(0x60801fff,32,FLEN)
NAN_BOXED(0x7dd1cef3,32,FLEN)
NAN_BOXED(0x411c2e3a,32,FLEN)
NAN_BOXED(0x60803fff,32,FLEN)
NAN_BOXED(0x7dd1cef3,32,FLEN)
NAN_BOXED(0x411c2e3a,32,FLEN)
NAN_BOXED(0x60807fff,32,FLEN)
NAN_BOXED(0x7dd1cef3,32,FLEN)
NAN_BOXED(0x411c2e3a,32,FLEN)
NAN_BOXED(0x6080ffff,32,FLEN)
NAN_BOXED(0x7dd1cef3,32,FLEN)
NAN_BOXED(0x411c2e3a,32,FLEN)
NAN_BOXED(0x6081ffff,32,FLEN)
NAN_BOXED(0x7dd1cef3,32,FLEN)
NAN_BOXED(0x411c2e3a,32,FLEN)
NAN_BOXED(0x6083ffff,32,FLEN)
NAN_BOXED(0x7dd1cef3,32,FLEN)
NAN_BOXED(0x411c2e3a,32,FLEN)
NAN_BOXED(0x6087ffff,32,FLEN)
NAN_BOXED(0x7dd1cef3,32,FLEN)
NAN_BOXED(0x411c2e3a,32,FLEN)
NAN_BOXED(0x608fffff,32,FLEN)
NAN_BOXED(0x7dd1cef3,32,FLEN)
NAN_BOXED(0x411c2e3a,32,FLEN)
NAN_BOXED(0x609fffff,32,FLEN)
NAN_BOXED(0x7dd1cef3,32,FLEN)
NAN_BOXED(0x411c2e3a,32,FLEN)
NAN_BOXED(0x60bfffff,32,FLEN)
NAN_BOXED(0x7dd1cef3,32,FLEN)
NAN_BOXED(0x411c2e3a,32,FLEN)
NAN_BOXED(0x60c00000,32,FLEN)
NAN_BOXED(0x7dd1cef3,32,FLEN)
NAN_BOXED(0x411c2e3a,32,FLEN)
NAN_BOXED(0x60e00000,32,FLEN)
NAN_BOXED(0x7dd1cef3,32,FLEN)
NAN_BOXED(0x411c2e3a,32,FLEN)
NAN_BOXED(0x60f00000,32,FLEN)
NAN_BOXED(0x7dd1cef3,32,FLEN)
NAN_BOXED(0x411c2e3a,32,FLEN)
NAN_BOXED(0x60f80000,32,FLEN)
NAN_BOXED(0x7dd1cef3,32,FLEN)
NAN_BOXED(0x411c2e3a,32,FLEN)
NAN_BOXED(0x60fc0000,32,FLEN)
NAN_BOXED(0x7dd1cef3,32,FLEN)
NAN_BOXED(0x411c2e3a,32,FLEN)
NAN_BOXED(0x60fe0000,32,FLEN)
NAN_BOXED(0x7dd1cef3,32,FLEN)
NAN_BOXED(0x411c2e3a,32,FLEN)
NAN_BOXED(0x60ff0000,32,FLEN)
NAN_BOXED(0x7dd1cef3,32,FLEN)
NAN_BOXED(0x411c2e3a,32,FLEN)
NAN_BOXED(0x60ff8000,32,FLEN)
NAN_BOXED(0x7dd1cef3,32,FLEN)
NAN_BOXED(0x411c2e3a,32,FLEN)
NAN_BOXED(0x60ffc000,32,FLEN)
NAN_BOXED(0x7dd1cef3,32,FLEN)
NAN_BOXED(0x411c2e3a,32,FLEN)
NAN_BOXED(0x60ffe000,32,FLEN)
NAN_BOXED(0x7dd1cef3,32,FLEN)
NAN_BOXED(0x411c2e3a,32,FLEN)
NAN_BOXED(0x60fff000,32,FLEN)
NAN_BOXED(0x7dd1cef3,32,FLEN)
NAN_BOXED(0x411c2e3a,32,FLEN)
NAN_BOXED(0x60fff800,32,FLEN)
NAN_BOXED(0x7dd1cef3,32,FLEN)
NAN_BOXED(0x411c2e3a,32,FLEN)
NAN_BOXED(0x60fffc00,32,FLEN)
NAN_BOXED(0x7dd1cef3,32,FLEN)
NAN_BOXED(0x411c2e3a,32,FLEN)
NAN_BOXED(0x60fffe00,32,FLEN)
NAN_BOXED(0x7dd1cef3,32,FLEN)
NAN_BOXED(0x411c2e3a,32,FLEN)
NAN_BOXED(0x60ffff00,32,FLEN)
NAN_BOXED(0x7dd1cef3,32,FLEN)
NAN_BOXED(0x411c2e3a,32,FLEN)
NAN_BOXED(0x60ffff80,32,FLEN)
NAN_BOXED(0x7dd1cef3,32,FLEN)
NAN_BOXED(0x411c2e3a,32,FLEN)
NAN_BOXED(0x60ffffc0,32,FLEN)
NAN_BOXED(0x7dd1cef3,32,FLEN)
NAN_BOXED(0x411c2e3a,32,FLEN)
NAN_BOXED(0x60ffffe0,32,FLEN)
NAN_BOXED(0x7dd1cef3,32,FLEN)
NAN_BOXED(0x411c2e3a,32,FLEN)
NAN_BOXED(0x60fffff0,32,FLEN)
NAN_BOXED(0x7dd1cef3,32,FLEN)
NAN_BOXED(0x411c2e3a,32,FLEN)
NAN_BOXED(0x60fffff8,32,FLEN)
NAN_BOXED(0x7dd1cef3,32,FLEN)
NAN_BOXED(0x411c2e3a,32,FLEN)
NAN_BOXED(0x60fffffc,32,FLEN)
NAN_BOXED(0x7dd1cef3,32,FLEN)
NAN_BOXED(0x411c2e3a,32,FLEN)
NAN_BOXED(0x60fffffe,32,FLEN)
NAN_BOXED(0x7dd1cef3,32,FLEN)
NAN_BOXED(0x411c2e3a,32,FLEN)
NAN_BOXED(0x60ffffff,32,FLEN)
NAN_BOXED(0x7dd1cef3,32,FLEN)
NAN_BOXED(0x411c2e3a,32,FLEN)
NAN_BOXED(0x7f000001,32,FLEN)
NAN_BOXED(0x7dd1cef3,32,FLEN)
NAN_BOXED(0x411c2e3a,32,FLEN)
NAN_BOXED(0x7f000003,32,FLEN)
NAN_BOXED(0x7dd1cef3,32,FLEN)
NAN_BOXED(0x411c2e3a,32,FLEN)
NAN_BOXED(0x7f000007,32,FLEN)
NAN_BOXED(0x7dd1cef3,32,FLEN)
NAN_BOXED(0x411c2e3a,32,FLEN)
NAN_BOXED(0x7f199999,32,FLEN)
NAN_BOXED(0x7dd1cef3,32,FLEN)
NAN_BOXED(0x411c2e3a,32,FLEN)
NAN_BOXED(0x7f249249,32,FLEN)
NAN_BOXED(0x7dd1cef3,32,FLEN)
NAN_BOXED(0x411c2e3a,32,FLEN)
NAN_BOXED(0x7f333333,32,FLEN)
NAN_BOXED(0x7dd1cef3,32,FLEN)
NAN_BOXED(0x411c2e3a,32,FLEN)
NAN_BOXED(0x7f36db6d,32,FLEN)
NAN_BOXED(0x7dd1cef3,32,FLEN)
NAN_BOXED(0x411c2e3a,32,FLEN)
NAN_BOXED(0x7f3bbbbb,32,FLEN)
NAN_BOXED(0x7dd1cef3,32,FLEN)
NAN_BOXED(0x411c2e3a,32,FLEN)
NAN_BOXED(0x7f444444,32,FLEN)
NAN_BOXED(0x7dd1cef3,32,FLEN)
NAN_BOXED(0x411c2e3a,32,FLEN)
NAN_BOXED(0x7f4ccccc,32,FLEN)
NAN_BOXED(0x7dd1cef3,32,FLEN)
NAN_BOXED(0x411c2e3a,32,FLEN)
NAN_BOXED(0x7f5b6db6,32,FLEN)
NAN_BOXED(0x7dd1cef3,32,FLEN)
NAN_BOXED(0x411c2e3a,32,FLEN)
NAN_BOXED(0x7f666666,32,FLEN)
NAN_BOXED(0x7dd1cef3,32,FLEN)
NAN_BOXED(0x411c2e3a,32,FLEN)
NAN_BOXED(0x7f6db6db,32,FLEN)
NAN_BOXED(0x7dd1cef3,32,FLEN)
NAN_BOXED(0x411c2e3a,32,FLEN)
NAN_BOXED(0x7f7ffff8,32,FLEN)
NAN_BOXED(0x7dd1cef3,32,FLEN)
NAN_BOXED(0x411c2e3a,32,FLEN)
NAN_BOXED(0x7f7ffffc,32,FLEN)
NAN_BOXED(0x7dd1cef3,32,FLEN)
NAN_BOXED(0x411c2e3a,32,FLEN)
NAN_BOXED(0x7f7ffffe,32,FLEN)
NAN_BOXED(0x7dd46786,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x1,32,FLEN)
NAN_BOXED(0x7dd46786,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x3,32,FLEN)
NAN_BOXED(0x7dd46786,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x7,32,FLEN)
NAN_BOXED(0x7dd46786,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x199999,32,FLEN)
NAN_BOXED(0x7dd46786,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x249249,32,FLEN)
NAN_BOXED(0x7dd46786,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x333333,32,FLEN)
NAN_BOXED(0x7dd46786,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x36db6d,32,FLEN)
NAN_BOXED(0x7dd46786,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x3bbbbb,32,FLEN)
NAN_BOXED(0x7dd46786,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x444444,32,FLEN)
NAN_BOXED(0x7dd46786,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x4ccccc,32,FLEN)
NAN_BOXED(0x7dd46786,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x5b6db6,32,FLEN)
NAN_BOXED(0x7dd46786,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x666666,32,FLEN)
NAN_BOXED(0x7dd46786,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x6db6db,32,FLEN)
NAN_BOXED(0x7dd46786,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x7ffff8,32,FLEN)
NAN_BOXED(0x7dd46786,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x7ffffc,32,FLEN)
NAN_BOXED(0x7dd46786,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x7ffffe,32,FLEN)
NAN_BOXED(0x7dd46786,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x10000000,32,FLEN)
NAN_BOXED(0x7dd46786,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x10000001,32,FLEN)
NAN_BOXED(0x7dd46786,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x10000003,32,FLEN)
NAN_BOXED(0x7dd46786,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x10000007,32,FLEN)
NAN_BOXED(0x7dd46786,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x1000000f,32,FLEN)
NAN_BOXED(0x7dd46786,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x1000001f,32,FLEN)
NAN_BOXED(0x7dd46786,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x1000003f,32,FLEN)
NAN_BOXED(0x7dd46786,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x1000007f,32,FLEN)
NAN_BOXED(0x7dd46786,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x100000ff,32,FLEN)
NAN_BOXED(0x7dd46786,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x100001ff,32,FLEN)
NAN_BOXED(0x7dd46786,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x100003ff,32,FLEN)
NAN_BOXED(0x7dd46786,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x100007ff,32,FLEN)
NAN_BOXED(0x7dd46786,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x10000fff,32,FLEN)
NAN_BOXED(0x7dd46786,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x10001fff,32,FLEN)
NAN_BOXED(0x7dd46786,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x10003fff,32,FLEN)
NAN_BOXED(0x7dd46786,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x10007fff,32,FLEN)
NAN_BOXED(0x7dd46786,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x1000ffff,32,FLEN)
NAN_BOXED(0x7dd46786,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x1001ffff,32,FLEN)
NAN_BOXED(0x7dd46786,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x1003ffff,32,FLEN)
NAN_BOXED(0x7dd46786,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x1007ffff,32,FLEN)
NAN_BOXED(0x7dd46786,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x100fffff,32,FLEN)
NAN_BOXED(0x7dd46786,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x101fffff,32,FLEN)
NAN_BOXED(0x7dd46786,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x103fffff,32,FLEN)
NAN_BOXED(0x7dd46786,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x10400000,32,FLEN)
NAN_BOXED(0x7dd46786,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x10600000,32,FLEN)
NAN_BOXED(0x7dd46786,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x10700000,32,FLEN)
NAN_BOXED(0x7dd46786,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x10780000,32,FLEN)
NAN_BOXED(0x7dd46786,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x107c0000,32,FLEN)
NAN_BOXED(0x7dd46786,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x107e0000,32,FLEN)
NAN_BOXED(0x7dd46786,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x107f0000,32,FLEN)
NAN_BOXED(0x7dd46786,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x107f8000,32,FLEN)
NAN_BOXED(0x7dd46786,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x107fc000,32,FLEN)
NAN_BOXED(0x7dd46786,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x107fe000,32,FLEN)
NAN_BOXED(0x7dd46786,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x107ff000,32,FLEN)
NAN_BOXED(0x7dd46786,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x107ff800,32,FLEN)
NAN_BOXED(0x7dd46786,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x107ffc00,32,FLEN)
NAN_BOXED(0x7dd46786,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x107ffe00,32,FLEN)
NAN_BOXED(0x7dd46786,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x107fff00,32,FLEN)
NAN_BOXED(0x7dd46786,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x107fff80,32,FLEN)
NAN_BOXED(0x7dd46786,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x107fffc0,32,FLEN)
NAN_BOXED(0x7dd46786,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x107fffe0,32,FLEN)
NAN_BOXED(0x7dd46786,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x107ffff0,32,FLEN)
NAN_BOXED(0x7dd46786,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x107ffff8,32,FLEN)
NAN_BOXED(0x7dd46786,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x107ffffc,32,FLEN)
NAN_BOXED(0x7dd46786,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x107ffffe,32,FLEN)
NAN_BOXED(0x7dd46786,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x107fffff,32,FLEN)
NAN_BOXED(0x7dd5b2a1,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x800001,32,FLEN)
NAN_BOXED(0x7dd5b2a1,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x800003,32,FLEN)
NAN_BOXED(0x7dd5b2a1,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x800007,32,FLEN)
NAN_BOXED(0x7dd5b2a1,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x999999,32,FLEN)
NAN_BOXED(0x7dd5b2a1,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xa49249,32,FLEN)
NAN_BOXED(0x7dd5b2a1,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xb33333,32,FLEN)
NAN_BOXED(0x7dd5b2a1,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xb6db6d,32,FLEN)
NAN_BOXED(0x7dd5b2a1,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xbbbbbb,32,FLEN)
NAN_BOXED(0x7dd5b2a1,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xc44444,32,FLEN)
NAN_BOXED(0x7dd5b2a1,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xcccccc,32,FLEN)
NAN_BOXED(0x7dd5b2a1,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xdb6db6,32,FLEN)
NAN_BOXED(0x7dd5b2a1,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xe66666,32,FLEN)
NAN_BOXED(0x7dd5b2a1,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xedb6db,32,FLEN)
NAN_BOXED(0x7dd5b2a1,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xfffff8,32,FLEN)
NAN_BOXED(0x7dd5b2a1,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xfffffc,32,FLEN)
NAN_BOXED(0x7dd5b2a1,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xfffffe,32,FLEN)
NAN_BOXED(0x7dd5b2a1,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xb800000,32,FLEN)
NAN_BOXED(0x7dd5b2a1,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xb800001,32,FLEN)
NAN_BOXED(0x7dd5b2a1,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xb800003,32,FLEN)
NAN_BOXED(0x7dd5b2a1,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xb800007,32,FLEN)
NAN_BOXED(0x7dd5b2a1,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xb80000f,32,FLEN)
NAN_BOXED(0x7dd5b2a1,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xb80001f,32,FLEN)
NAN_BOXED(0x7dd5b2a1,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xb80003f,32,FLEN)
NAN_BOXED(0x7dd5b2a1,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xb80007f,32,FLEN)
NAN_BOXED(0x7dd5b2a1,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xb8000ff,32,FLEN)
NAN_BOXED(0x7dd5b2a1,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xb8001ff,32,FLEN)
NAN_BOXED(0x7dd5b2a1,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xb8003ff,32,FLEN)
NAN_BOXED(0x7dd5b2a1,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xb8007ff,32,FLEN)
NAN_BOXED(0x7dd5b2a1,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xb800fff,32,FLEN)
NAN_BOXED(0x7dd5b2a1,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xb801fff,32,FLEN)
NAN_BOXED(0x7dd5b2a1,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xb803fff,32,FLEN)
NAN_BOXED(0x7dd5b2a1,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xb807fff,32,FLEN)
NAN_BOXED(0x7dd5b2a1,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xb80ffff,32,FLEN)
NAN_BOXED(0x7dd5b2a1,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xb81ffff,32,FLEN)
NAN_BOXED(0x7dd5b2a1,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xb83ffff,32,FLEN)
NAN_BOXED(0x7dd5b2a1,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xb87ffff,32,FLEN)
NAN_BOXED(0x7dd5b2a1,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xb8fffff,32,FLEN)
NAN_BOXED(0x7dd5b2a1,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xb9fffff,32,FLEN)
NAN_BOXED(0x7dd5b2a1,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xbbfffff,32,FLEN)
NAN_BOXED(0x7dd5b2a1,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xbc00000,32,FLEN)
NAN_BOXED(0x7dd5b2a1,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xbe00000,32,FLEN)
NAN_BOXED(0x7dd5b2a1,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xbf00000,32,FLEN)
NAN_BOXED(0x7dd5b2a1,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xbf80000,32,FLEN)
NAN_BOXED(0x7dd5b2a1,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xbfc0000,32,FLEN)
NAN_BOXED(0x7dd5b2a1,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xbfe0000,32,FLEN)
NAN_BOXED(0x7dd5b2a1,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xbff0000,32,FLEN)
NAN_BOXED(0x7dd5b2a1,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xbff8000,32,FLEN)
NAN_BOXED(0x7dd5b2a1,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xbffc000,32,FLEN)
NAN_BOXED(0x7dd5b2a1,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xbffe000,32,FLEN)
NAN_BOXED(0x7dd5b2a1,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xbfff000,32,FLEN)
RVTEST_DATA_END

RVMODEL_DATA_BEGIN
rvtest_sig_begin:
sig_begin_canary:
CANARY;


signature_x1_0:
    .fill 0*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_1:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_2:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_3:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_4:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_5:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_6:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef

#ifdef rvtest_mtrap_routine

tsig_begin_canary:
CANARY;
tsig_begin_canary:
CANARY;
mtrap_sigptr:
    .fill 64*(XLEN/32),4,0xdeadbeef
tsig_end_canary:
CANARY;
tsig_end_canary:
CANARY;

#endif

#ifdef rvtest_gpr_save

gpr_save:
    .fill 32*XLEN/32,4,0xdeadbeef

#endif

sig_end_canary:
CANARY;
rvtest_sig_end:
RVMODEL_DATA_END
