
// -----------
// This file was generated by riscv_ctg (https://github.com/riscv-software-src/riscv-ctg)
// version   : 0.12.2
// timestamp : Wed Sep 25 06:07:02 2024 GMT
// usage     : riscv_ctg \
//                  -- cgf //                  --cgf /home/riscv/testing/riscv-ctg/sample_cgfs/dataset.cgf \
//                  --cgf /home/riscv/testing/riscv-ctg/sample_cgfs/sample_cgfs_fext/RV32Zhinx/rv32h_fnmsub.cgf \
 \
//                  -- xlen 32  \
//                  --randomize \
// -----------
//
// -----------
// Copyright (c) 2020. RISC-V International. All rights reserved.
// SPDX-License-Identifier: BSD-3-Clause
// -----------
//
// This assembly file tests the fnmsub.h instruction of the RISC-V RV32_Zfinx_Zhinx,RV64_Zfinx_Zhinx extension for the fnmsub_b7 covergroup.
// 
#include "model_test.h"
#include "arch_test.h"
RVTEST_ISA("RV32I_Zfinx_Zhinx,RV64I_Zfinx_Zhinx")

.section .text.init
.globl rvtest_entry_point
rvtest_entry_point:
RVMODEL_BOOT
RVTEST_CODE_BEGIN

#ifdef TEST_CASE_1

RVTEST_CASE(0,"//check ISA:=regex(.*I.*Zfinx.*Zhinx.*);def TEST_CASE_1=True;",fnmsub_b7)

RVTEST_FP_ENABLE()
RVTEST_VALBASEUPD(x4,test_dataset_0)
RVTEST_SIGBASE(x2,signature_x2_1)

inst_0:
// rs1 == rs2 != rs3 and rs1 == rs2 != rd and rd != rs3, rs1==x0, rs2==x0, rs3==x6, rd==x12,fs1 == 0 and fe1 == 0x1c and fm1 == 0x340 and fs2 == 1 and fe2 == 0x11 and fm2 == 0x03e and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3b1 and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x0; op2:x0; op3:x6; dest:x12; op1val:0x0; op2val:0x0;
op3val:0x7bb1; valaddr_reg:x4; val_offset:0*FLEN/8; rmval:dyn;
testreg:x3; fcsr_val:96 */
TEST_FPR4_OP(fnmsub.h, x12, x0, x0, x6, dyn, 96, 0, x4, 0*FLEN/8, x13, x2, x3)

inst_1:
// rs1 == rd != rs2 and rs1 == rd != rs3 and rs3 != rs2, rs1==x8, rs2==x22, rs3==x23, rd==x8,fs1 == 0 and fe1 == 0x1c and fm1 == 0x00a and fs2 == 1 and fe2 == 0x11 and fm2 == 0x194 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x1a2 and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x8; op2:x22; op3:x23; dest:x8; op1val:0x700a; op2val:0xc594;
op3val:0x79a2; valaddr_reg:x4; val_offset:3*FLEN/8; rmval:dyn;
testreg:x3; fcsr_val:96 */
TEST_FPR4_OP(fnmsub.h, x8, x8, x22, x23, dyn, 96, 0, x4, 3*FLEN/8, x13, x2, x3)

inst_2:
// rs1 != rs2 and rs1 != rd and rs1 != rs3 and rs2 != rs3 and rs2 != rd and rs3 != rd, rs1==x10, rs2==x28, rs3==x12, rd==x7,fs1 == 0 and fe1 == 0x1b and fm1 == 0x173 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x1cf and fs3 == 0 and fe3 == 0x1c and fm3 == 0x3ea and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x10; op2:x28; op3:x12; dest:x7; op1val:0x6d73; op2val:0xc1cf;
op3val:0x73ea; valaddr_reg:x4; val_offset:6*FLEN/8; rmval:dyn;
testreg:x3; fcsr_val:96 */
TEST_FPR4_OP(fnmsub.h, x7, x10, x28, x12, dyn, 96, 0, x4, 6*FLEN/8, x13, x2, x3)

inst_3:
// rs1 == rs3 != rs2 and rs1 == rs3 != rd and rd != rs2, rs1==x18, rs2==x6, rs3==x18, rd==x31,fs1 == 0 and fe1 == 0x1e and fm1 == 0x3fd and fs2 == 1 and fe2 == 0x0c and fm2 == 0x2b4 and fs3 == 0 and fe3 == 0x1c and fm3 == 0x2b2 and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x18; op2:x6; op3:x18; dest:x31; op1val:0x7bfd; op2val:0xb2b4;
op3val:0x7bfd; valaddr_reg:x4; val_offset:9*FLEN/8; rmval:dyn;
testreg:x3; fcsr_val:96 */
TEST_FPR4_OP(fnmsub.h, x31, x18, x6, x18, dyn, 96, 0, x4, 9*FLEN/8, x13, x2, x3)

inst_4:
// rs1 == rs2 == rs3 != rd, rs1==x5, rs2==x5, rs3==x5, rd==x19,fs1 == 0 and fe1 == 0x1e and fm1 == 0x121 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x1b8 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x357 and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x5; op2:x5; op3:x5; dest:x19; op1val:0x7921; op2val:0x7921;
op3val:0x7921; valaddr_reg:x4; val_offset:12*FLEN/8; rmval:dyn;
testreg:x3; fcsr_val:96 */
TEST_FPR4_OP(fnmsub.h, x19, x5, x5, x5, dyn, 96, 0, x4, 12*FLEN/8, x13, x2, x3)

inst_5:
// rs3 == rd != rs1 and rs3 == rd != rs2 and rs2 != rs1, rs1==x9, rs2==x30, rs3==x16, rd==x16,fs1 == 0 and fe1 == 0x1d and fm1 == 0x33f and fs2 == 1 and fe2 == 0x0f and fm2 == 0x05e and fs3 == 0 and fe3 == 0x1d and fm3 == 0x3ea and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x9; op2:x30; op3:x16; dest:x16; op1val:0x773f; op2val:0xbc5e;
op3val:0x77ea; valaddr_reg:x4; val_offset:15*FLEN/8; rmval:dyn;
testreg:x3; fcsr_val:96 */
TEST_FPR4_OP(fnmsub.h, x16, x9, x30, x16, dyn, 96, 0, x4, 15*FLEN/8, x13, x2, x3)

inst_6:
// rd == rs2 == rs3 != rs1, rs1==x31, rs2==x29, rs3==x29, rd==x29,fs1 == 0 and fe1 == 0x1c and fm1 == 0x226 and fs2 == 1 and fe2 == 0x11 and fm2 == 0x051 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x2a4 and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x31; op2:x29; op3:x29; dest:x29; op1val:0x7226; op2val:0xc451;
op3val:0xc451; valaddr_reg:x4; val_offset:18*FLEN/8; rmval:dyn;
testreg:x3; fcsr_val:96 */
TEST_FPR4_OP(fnmsub.h, x29, x31, x29, x29, dyn, 96, 0, x4, 18*FLEN/8, x13, x2, x3)

inst_7:
// rs1 == rd == rs3 != rs2, rs1==x17, rs2==x14, rs3==x17, rd==x17,fs1 == 0 and fe1 == 0x1b and fm1 == 0x1ba and fs2 == 1 and fe2 == 0x10 and fm2 == 0x13a and fs3 == 0 and fe3 == 0x1c and fm3 == 0x37d and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x17; op2:x14; op3:x17; dest:x17; op1val:0x6dba; op2val:0xc13a;
op3val:0x6dba; valaddr_reg:x4; val_offset:21*FLEN/8; rmval:dyn;
testreg:x3; fcsr_val:96 */
TEST_FPR4_OP(fnmsub.h, x17, x17, x14, x17, dyn, 96, 0, x4, 21*FLEN/8, x13, x2, x3)

inst_8:
// rs1 == rs2 == rs3 == rd, rs1==x21, rs2==x21, rs3==x21, rd==x21,fs1 == 0 and fe1 == 0x19 and fm1 == 0x11e and fs2 == 1 and fe2 == 0x12 and fm2 == 0x2aa and fs3 == 0 and fe3 == 0x1d and fm3 == 0x044 and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x21; op2:x21; op3:x21; dest:x21; op1val:0x651e; op2val:0x651e;
op3val:0x651e; valaddr_reg:x4; val_offset:24*FLEN/8; rmval:dyn;
testreg:x3; fcsr_val:96 */
TEST_FPR4_OP(fnmsub.h, x21, x21, x21, x21, dyn, 96, 0, x4, 24*FLEN/8, x13, x2, x3)

inst_9:
// rs1 == rs2 == rd != rs3, rs1==x1, rs2==x1, rs3==x31, rd==x1,fs1 == 0 and fe1 == 0x1d and fm1 == 0x285 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x06c and fs3 == 0 and fe3 == 0x1e and fm3 == 0x336 and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x1; op2:x1; op3:x31; dest:x1; op1val:0x7685; op2val:0x7685;
op3val:0x7b36; valaddr_reg:x4; val_offset:27*FLEN/8; rmval:dyn;
testreg:x3; fcsr_val:96 */
TEST_FPR4_OP(fnmsub.h, x1, x1, x1, x31, dyn, 96, 0, x4, 27*FLEN/8, x13, x2, x3)

inst_10:
// rs2 == rd != rs1 and rs2 == rd != rs3 and rs3 != rs1, rs1==x24, rs2==x11, rs3==x0, rd==x11,fs1 == 0 and fe1 == 0x1d and fm1 == 0x20f and fs2 == 1 and fe2 == 0x0d and fm2 == 0x0cd and fs3 == 0 and fe3 == 0x1b and fm3 == 0x346 and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x24; op2:x11; op3:x0; dest:x11; op1val:0x760f; op2val:0xb4cd;
op3val:0x0; valaddr_reg:x4; val_offset:30*FLEN/8; rmval:dyn;
testreg:x3; fcsr_val:96 */
TEST_FPR4_OP(fnmsub.h, x11, x24, x11, x0, dyn, 96, 0, x4, 30*FLEN/8, x13, x2, x3)

inst_11:
// rs2 == rs3 != rs1 and rs2 == rs3 != rd and rd != rs1, rs1==x26, rs2==x7, rs3==x7, rd==x10,fs1 == 0 and fe1 == 0x1d and fm1 == 0x021 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x3ad and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ed and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x26; op2:x7; op3:x7; dest:x10; op1val:0x7421; op2val:0xc3ad;
op3val:0xc3ad; valaddr_reg:x4; val_offset:33*FLEN/8; rmval:dyn;
testreg:x3; fcsr_val:96 */
TEST_FPR4_OP(fnmsub.h, x10, x26, x7, x7, dyn, 96, 0, x4, 33*FLEN/8, x13, x2, x3)
RVTEST_VALBASEUPD(x7,test_dataset_1)

inst_12:
// rs1==x22, rs2==x20, rs3==x10, rd==x28,fs1 == 0 and fe1 == 0x1b and fm1 == 0x009 and fs2 == 1 and fe2 == 0x12 and fm2 == 0x0e9 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x0f5 and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x22; op2:x20; op3:x10; dest:x28; op1val:0x6c09; op2val:0xc8e9;
op3val:0x78f5; valaddr_reg:x7; val_offset:0*FLEN/8; rmval:dyn;
testreg:x3; fcsr_val:96 */
TEST_FPR4_OP(fnmsub.h, x28, x22, x20, x10, dyn, 96, 0, x7, 0*FLEN/8, x8, x2, x3)

inst_13:
// rs1==x13, rs2==x10, rs3==x8, rd==x9,fs1 == 0 and fe1 == 0x1d and fm1 == 0x208 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x301 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x148 and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x13; op2:x10; op3:x8; dest:x9; op1val:0x7608; op2val:0xbf01;
op3val:0x7948; valaddr_reg:x7; val_offset:3*FLEN/8; rmval:dyn;
testreg:x3; fcsr_val:96 */
TEST_FPR4_OP(fnmsub.h, x9, x13, x10, x8, dyn, 96, 0, x7, 3*FLEN/8, x8, x2, x3)

inst_14:
// rs1==x23, rs2==x3, rs3==x14, rd==x20,fs1 == 0 and fe1 == 0x1d and fm1 == 0x169 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x015 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x187 and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x23; op2:x3; op3:x14; dest:x20; op1val:0x7569; op2val:0xc015;
op3val:0x7987; valaddr_reg:x7; val_offset:6*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:96 */
TEST_FPR4_OP(fnmsub.h, x20, x23, x3, x14, dyn, 96, 0, x7, 6*FLEN/8, x8, x2, x5)
RVTEST_SIGBASE(x1,signature_x1_0)

inst_15:
// rs1==x29, rs2==x18, rs3==x1, rd==x3,fs1 == 0 and fe1 == 0x1d and fm1 == 0x3f5 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x139 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x131 and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x29; op2:x18; op3:x1; dest:x3; op1val:0x77f5; op2val:0xbd39;
op3val:0x7931; valaddr_reg:x7; val_offset:9*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:96 */
TEST_FPR4_OP(fnmsub.h, x3, x29, x18, x1, dyn, 96, 0, x7, 9*FLEN/8, x8, x1, x5)

inst_16:
// rs1==x12, rs2==x31, rs3==x28, rd==x13,fs1 == 0 and fe1 == 0x1e and fm1 == 0x335 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x129 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x0a6 and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x12; op2:x31; op3:x28; dest:x13; op1val:0x7b35; op2val:0xb929;
op3val:0x78a6; valaddr_reg:x7; val_offset:12*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:96 */
TEST_FPR4_OP(fnmsub.h, x13, x12, x31, x28, dyn, 96, 0, x7, 12*FLEN/8, x8, x1, x5)

inst_17:
// rs1==x16, rs2==x26, rs3==x20, rd==x15,fs1 == 0 and fe1 == 0x1c and fm1 == 0x08b and fs2 == 1 and fe2 == 0x0d and fm2 == 0x33f and fs3 == 0 and fe3 == 0x1b and fm3 == 0x01e and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x16; op2:x26; op3:x20; dest:x15; op1val:0x708b; op2val:0xb73f;
op3val:0x6c1e; valaddr_reg:x7; val_offset:15*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:96 */
TEST_FPR4_OP(fnmsub.h, x15, x16, x26, x20, dyn, 96, 0, x7, 15*FLEN/8, x8, x1, x5)

inst_18:
// rs1==x15, rs2==x25, rs3==x11, rd==x2,fs1 == 0 and fe1 == 0x1e and fm1 == 0x390 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x021 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x3d0 and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x15; op2:x25; op3:x11; dest:x2; op1val:0x7b90; op2val:0xb821;
op3val:0x77d0; valaddr_reg:x7; val_offset:18*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:96 */
TEST_FPR4_OP(fnmsub.h, x2, x15, x25, x11, dyn, 96, 0, x7, 18*FLEN/8, x8, x1, x5)

inst_19:
// rs1==x6, rs2==x27, rs3==x9, rd==x14,fs1 == 0 and fe1 == 0x1c and fm1 == 0x233 and fs2 == 1 and fe2 == 0x11 and fm2 == 0x0e1 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x390 and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x6; op2:x27; op3:x9; dest:x14; op1val:0x7233; op2val:0xc4e1;
op3val:0x7b90; valaddr_reg:x7; val_offset:21*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:96 */
TEST_FPR4_OP(fnmsub.h, x14, x6, x27, x9, dyn, 96, 0, x7, 21*FLEN/8, x8, x1, x5)

inst_20:
// rs1==x25, rs2==x17, rs3==x19, rd==x18,fs1 == 0 and fe1 == 0x1e and fm1 == 0x0a1 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x109 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x1d4 and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x25; op2:x17; op3:x19; dest:x18; op1val:0x78a1; op2val:0xbd09;
op3val:0x79d4; valaddr_reg:x7; val_offset:24*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:96 */
TEST_FPR4_OP(fnmsub.h, x18, x25, x17, x19, dyn, 96, 0, x7, 24*FLEN/8, x8, x1, x5)

inst_21:
// rs1==x4, rs2==x16, rs3==x27, rd==x6,fs1 == 0 and fe1 == 0x1e and fm1 == 0x30b and fs2 == 1 and fe2 == 0x0d and fm2 == 0x130 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x091 and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x4; op2:x16; op3:x27; dest:x6; op1val:0x7b0b; op2val:0xb530;
op3val:0x7491; valaddr_reg:x7; val_offset:27*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:96 */
TEST_FPR4_OP(fnmsub.h, x6, x4, x16, x27, dyn, 96, 0, x7, 27*FLEN/8, x8, x1, x5)
RVTEST_VALBASEUPD(x6,test_dataset_2)

inst_22:
// rs1==x20, rs2==x15, rs3==x2, rd==x22,fs1 == 0 and fe1 == 0x1d and fm1 == 0x1b4 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x0ec and fs3 == 0 and fe3 == 0x1e and fm3 == 0x305 and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x20; op2:x15; op3:x2; dest:x22; op1val:0x75b4; op2val:0xc0ec;
op3val:0x7b05; valaddr_reg:x6; val_offset:0*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:96 */
TEST_FPR4_OP(fnmsub.h, x22, x20, x15, x2, dyn, 96, 0, x6, 0*FLEN/8, x10, x1, x5)

inst_23:
// rs1==x19, rs2==x4, rs3==x13, rd==x26,fs1 == 0 and fe1 == 0x1c and fm1 == 0x051 and fs2 == 1 and fe2 == 0x11 and fm2 == 0x1a9 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x21c and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x19; op2:x4; op3:x13; dest:x26; op1val:0x7051; op2val:0xc5a9;
op3val:0x7a1c; valaddr_reg:x6; val_offset:3*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:96 */
TEST_FPR4_OP(fnmsub.h, x26, x19, x4, x13, dyn, 96, 0, x6, 3*FLEN/8, x10, x1, x5)

inst_24:
// rs1==x2, rs2==x13, rs3==x22, rd==x23,fs1 == 0 and fe1 == 0x1b and fm1 == 0x23e and fs2 == 1 and fe2 == 0x11 and fm2 == 0x311 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x184 and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x2; op2:x13; op3:x22; dest:x23; op1val:0x6e3e; op2val:0xc711;
op3val:0x7984; valaddr_reg:x6; val_offset:6*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:96 */
TEST_FPR4_OP(fnmsub.h, x23, x2, x13, x22, dyn, 96, 0, x6, 6*FLEN/8, x10, x1, x5)

inst_25:
// rs1==x30, rs2==x19, rs3==x25, rd==x4,fs1 == 0 and fe1 == 0x1e and fm1 == 0x19d and fs2 == 1 and fe2 == 0x0f and fm2 == 0x169 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x398 and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x19; op3:x25; dest:x4; op1val:0x799d; op2val:0xbd69;
op3val:0x7b98; valaddr_reg:x6; val_offset:9*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:96 */
TEST_FPR4_OP(fnmsub.h, x4, x30, x19, x25, dyn, 96, 0, x6, 9*FLEN/8, x10, x1, x5)

inst_26:
// rs1==x11, rs2==x23, rs3==x3, rd==x0,fs1 == 0 and fe1 == 0x1e and fm1 == 0x2be and fs2 == 1 and fe2 == 0x0e and fm2 == 0x0c6 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x006 and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x11; op2:x23; op3:x3; dest:x0; op1val:0x7abe; op2val:0xb8c6;
op3val:0x7806; valaddr_reg:x6; val_offset:12*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:96 */
TEST_FPR4_OP(fnmsub.h, x0, x11, x23, x3, dyn, 96, 0, x6, 12*FLEN/8, x10, x1, x5)

inst_27:
// rs1==x28, rs2==x24, rs3==x26, rd==x27,fs1 == 0 and fe1 == 0x1c and fm1 == 0x252 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x213 and fs3 == 0 and fe3 == 0x1c and fm3 == 0x0cd and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x28; op2:x24; op3:x26; dest:x27; op1val:0x7252; op2val:0xba13;
op3val:0x70cd; valaddr_reg:x6; val_offset:15*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:96 */
TEST_FPR4_OP(fnmsub.h, x27, x28, x24, x26, dyn, 96, 0, x6, 15*FLEN/8, x10, x1, x5)

inst_28:
// rs1==x27, rs2==x8, rs3==x24, rd==x30,fs1 == 0 and fe1 == 0x1e and fm1 == 0x03a and fs2 == 1 and fe2 == 0x0e and fm2 == 0x3b6 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x013 and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x27; op2:x8; op3:x24; dest:x30; op1val:0x783a; op2val:0xbbb6;
op3val:0x7813; valaddr_reg:x6; val_offset:18*FLEN/8; rmval:dyn;
testreg:x4; fcsr_val:96 */
TEST_FPR4_OP(fnmsub.h, x30, x27, x8, x24, dyn, 96, 0, x6, 18*FLEN/8, x10, x1, x4)
RVTEST_SIGBASE(x1,signature_x1_1)

inst_29:
// rs1==x14, rs2==x2, rs3==x30, rd==x24,fs1 == 0 and fe1 == 0x1b and fm1 == 0x091 and fs2 == 1 and fe2 == 0x12 and fm2 == 0x252 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x338 and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x14; op2:x2; op3:x30; dest:x24; op1val:0x6c91; op2val:0xca52;
op3val:0x7b38; valaddr_reg:x6; val_offset:21*FLEN/8; rmval:dyn;
testreg:x4; fcsr_val:96 */
TEST_FPR4_OP(fnmsub.h, x24, x14, x2, x30, dyn, 96, 0, x6, 21*FLEN/8, x10, x1, x4)

inst_30:
// rs1==x7, rs2==x12, rs3==x4, rd==x25,fs1 == 0 and fe1 == 0x1e and fm1 == 0x00e and fs2 == 1 and fe2 == 0x0f and fm2 == 0x187 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x19b and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x7; op2:x12; op3:x4; dest:x25; op1val:0x780e; op2val:0xbd87;
op3val:0x799b; valaddr_reg:x6; val_offset:24*FLEN/8; rmval:dyn;
testreg:x4; fcsr_val:96 */
TEST_FPR4_OP(fnmsub.h, x25, x7, x12, x4, dyn, 96, 0, x6, 24*FLEN/8, x10, x1, x4)

inst_31:
// rs1==x3, rs2==x9, rs3==x15, rd==x5,fs1 == 0 and fe1 == 0x1c and fm1 == 0x309 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x06f and fs3 == 0 and fe3 == 0x1c and fm3 == 0x3cd and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x3; op2:x9; op3:x15; dest:x5; op1val:0x7309; op2val:0xbc6f;
op3val:0x73cd; valaddr_reg:x6; val_offset:27*FLEN/8; rmval:dyn;
testreg:x4; fcsr_val:96 */
TEST_FPR4_OP(fnmsub.h, x5, x3, x9, x15, dyn, 96, 0, x6, 27*FLEN/8, x10, x1, x4)

inst_32:
// fs1 == 0 and fe1 == 0x18 and fm1 == 0x21b and fs2 == 1 and fe2 == 0x13 and fm2 == 0x331 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x17d and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x621b; op2val:0xcf31;
op3val:0x757d; valaddr_reg:x6; val_offset:30*FLEN/8; rmval:dyn;
testreg:x4; fcsr_val:96 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x6, 30*FLEN/8, x10, x1, x4)
RVTEST_VALBASEUPD(x2,test_dataset_3)

inst_33:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x044 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x258 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x2c5 and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7444; op2val:0xbe58;
op3val:0x76c5; valaddr_reg:x2; val_offset:0*FLEN/8; rmval:dyn;
testreg:x4; fcsr_val:96 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x2, 0*FLEN/8, x3, x1, x4)

inst_34:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x207 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x06d and fs3 == 0 and fe3 == 0x1e and fm3 == 0x2ab and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7607; op2val:0xc06d;
op3val:0x7aab; valaddr_reg:x2; val_offset:3*FLEN/8; rmval:dyn;
testreg:x4; fcsr_val:96 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x2, 3*FLEN/8, x3, x1, x4)

inst_35:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x320 and fs2 == 1 and fe2 == 0x0c and fm2 == 0x24a and fs3 == 0 and fe3 == 0x1c and fm3 == 0x19b and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7b20; op2val:0xb24a;
op3val:0x719b; valaddr_reg:x2; val_offset:6*FLEN/8; rmval:dyn;
testreg:x4; fcsr_val:96 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x2, 6*FLEN/8, x3, x1, x4)

inst_36:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x256 and fs2 == 1 and fe2 == 0x0d and fm2 == 0x2b5 and fs3 == 0 and fe3 == 0x1c and fm3 == 0x150 and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7656; op2val:0xb6b5;
op3val:0x7150; valaddr_reg:x2; val_offset:9*FLEN/8; rmval:dyn;
testreg:x4; fcsr_val:96 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x2, 9*FLEN/8, x3, x1, x4)

inst_37:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x14d and fs2 == 1 and fe2 == 0x0f and fm2 == 0x1e1 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3cb and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x794d; op2val:0xbde1;
op3val:0x7bcb; valaddr_reg:x2; val_offset:12*FLEN/8; rmval:dyn;
testreg:x4; fcsr_val:96 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x2, 12*FLEN/8, x3, x1, x4)

inst_38:
// fs1 == 0 and fe1 == 0x1c and fm1 == 0x274 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x398 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x220 and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7274; op2val:0xc398;
op3val:0x7a20; valaddr_reg:x2; val_offset:15*FLEN/8; rmval:dyn;
testreg:x4; fcsr_val:96 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x2, 15*FLEN/8, x3, x1, x4)

inst_39:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x0cc and fs2 == 1 and fe2 == 0x0a and fm2 == 0x1a5 and fs3 == 0 and fe3 == 0x18 and fm3 == 0x2c5 and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x74cc; op2val:0xa9a5;
op3val:0x62c5; valaddr_reg:x2; val_offset:18*FLEN/8; rmval:dyn;
testreg:x4; fcsr_val:96 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x2, 18*FLEN/8, x3, x1, x4)

inst_40:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x21c and fs2 == 1 and fe2 == 0x0d and fm2 == 0x327 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x177 and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7a1c; op2val:0xb727;
op3val:0x7577; valaddr_reg:x2; val_offset:21*FLEN/8; rmval:dyn;
testreg:x4; fcsr_val:96 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x2, 21*FLEN/8, x3, x1, x4)

inst_41:
// fs1 == 0 and fe1 == 0x1c and fm1 == 0x171 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x11e and fs3 == 0 and fe3 == 0x1d and fm3 == 0x2f7 and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7171; op2val:0xc11e;
op3val:0x76f7; valaddr_reg:x2; val_offset:24*FLEN/8; rmval:dyn;
testreg:x4; fcsr_val:96 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x2, 24*FLEN/8, x3, x1, x4)

inst_42:
// fs1 == 0 and fe1 == 0x1c and fm1 == 0x369 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x318 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x28e and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7369; op2val:0xbf18;
op3val:0x768e; valaddr_reg:x2; val_offset:27*FLEN/8; rmval:dyn;
testreg:x4; fcsr_val:96 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x2, 27*FLEN/8, x3, x1, x4)

inst_43:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x322 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x383 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x2af and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7722; op2val:0xbb83;
op3val:0x76af; valaddr_reg:x2; val_offset:30*FLEN/8; rmval:dyn;
testreg:x4; fcsr_val:96 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x2, 30*FLEN/8, x3, x1, x4)

inst_44:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0b4 and fs2 == 1 and fe2 == 0x0d and fm2 == 0x3e0 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x09e and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x78b4; op2val:0xb7e0;
op3val:0x749e; valaddr_reg:x2; val_offset:33*FLEN/8; rmval:dyn;
testreg:x4; fcsr_val:96 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x2, 33*FLEN/8, x3, x1, x4)

inst_45:
// fs1 == 0 and fe1 == 0x1b and fm1 == 0x215 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x340 and fs3 == 0 and fe3 == 0x1b and fm3 == 0x174 and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6e15; op2val:0xbb40;
op3val:0x6d74; valaddr_reg:x2; val_offset:36*FLEN/8; rmval:dyn;
testreg:x4; fcsr_val:96 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x2, 36*FLEN/8, x3, x1, x4)

inst_46:
// fs1 == 0 and fe1 == 0x1b and fm1 == 0x2d0 and fs2 == 1 and fe2 == 0x11 and fm2 == 0x0e6 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x02a and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6ed0; op2val:0xc4e6;
op3val:0x782a; valaddr_reg:x2; val_offset:39*FLEN/8; rmval:dyn;
testreg:x4; fcsr_val:96 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x2, 39*FLEN/8, x3, x1, x4)

inst_47:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x1c2 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x07d and fs3 == 0 and fe3 == 0x1e and fm3 == 0x275 and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x75c2; op2val:0xc07d;
op3val:0x7a75; valaddr_reg:x2; val_offset:42*FLEN/8; rmval:dyn;
testreg:x4; fcsr_val:96 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x2, 42*FLEN/8, x3, x1, x4)

inst_48:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x009 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x19e and fs3 == 0 and fe3 == 0x1e and fm3 == 0x1a9 and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7809; op2val:0xbd9e;
op3val:0x79a9; valaddr_reg:x2; val_offset:45*FLEN/8; rmval:dyn;
testreg:x4; fcsr_val:96 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x2, 45*FLEN/8, x3, x1, x4)

inst_49:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3d6 and fs2 == 1 and fe2 == 0x0b and fm2 == 0x01c and fs3 == 0 and fe3 == 0x1b and fm3 == 0x007 and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bd6; op2val:0xac1c;
op3val:0x6c07; valaddr_reg:x2; val_offset:48*FLEN/8; rmval:dyn;
testreg:x4; fcsr_val:96 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x2, 48*FLEN/8, x3, x1, x4)

inst_50:
// fs1 == 0 and fe1 == 0x19 and fm1 == 0x056 and fs2 == 1 and fe2 == 0x12 and fm2 == 0x023 and fs3 == 0 and fe3 == 0x1c and fm3 == 0x07d and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6456; op2val:0xc823;
op3val:0x707d; valaddr_reg:x2; val_offset:51*FLEN/8; rmval:dyn;
testreg:x4; fcsr_val:96 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x2, 51*FLEN/8, x3, x1, x4)

inst_51:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x22d and fs2 == 1 and fe2 == 0x0f and fm2 == 0x1f0 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x096 and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x762d; op2val:0xbdf0;
op3val:0x7896; valaddr_reg:x2; val_offset:54*FLEN/8; rmval:dyn;
testreg:x4; fcsr_val:96 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x2, 54*FLEN/8, x3, x1, x4)

inst_52:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1f2 and fs2 == 1 and fe2 == 0x0d and fm2 == 0x38f and fs3 == 0 and fe3 == 0x1d and fm3 == 0x19e and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x79f2; op2val:0xb78f;
op3val:0x759e; valaddr_reg:x2; val_offset:57*FLEN/8; rmval:dyn;
testreg:x4; fcsr_val:96 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x2, 57*FLEN/8, x3, x1, x4)

inst_53:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3b7 and fs2 == 1 and fe2 == 0x06 and fm2 == 0x246 and fs3 == 0 and fe3 == 0x16 and fm3 == 0x20c and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bb7; op2val:0x9a46;
op3val:0x5a0c; valaddr_reg:x2; val_offset:60*FLEN/8; rmval:dyn;
testreg:x4; fcsr_val:96 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x2, 60*FLEN/8, x3, x1, x4)

inst_54:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2ae and fs2 == 1 and fe2 == 0x0d and fm2 == 0x005 and fs3 == 0 and fe3 == 0x1c and fm3 == 0x2b8 and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7aae; op2val:0xb405;
op3val:0x72b8; valaddr_reg:x2; val_offset:63*FLEN/8; rmval:dyn;
testreg:x4; fcsr_val:96 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x2, 63*FLEN/8, x3, x1, x4)

inst_55:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2ff and fs2 == 1 and fe2 == 0x0a and fm2 == 0x0d8 and fs3 == 0 and fe3 == 0x1a and fm3 == 0x03d and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7aff; op2val:0xa8d8;
op3val:0x683d; valaddr_reg:x2; val_offset:66*FLEN/8; rmval:dyn;
testreg:x4; fcsr_val:96 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x2, 66*FLEN/8, x3, x1, x4)

inst_56:
// fs1 == 0 and fe1 == 0x1c and fm1 == 0x340 and fs2 == 1 and fe2 == 0x11 and fm2 == 0x03e and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3b1 and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7340; op2val:0xc43e;
op3val:0x7bb1; valaddr_reg:x2; val_offset:69*FLEN/8; rmval:dyn;
testreg:x4; fcsr_val:96 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x2, 69*FLEN/8, x3, x1, x4)

inst_57:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3fd and fs2 == 1 and fe2 == 0x0c and fm2 == 0x2b4 and fs3 == 0 and fe3 == 0x1c and fm3 == 0x2b2 and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bfd; op2val:0xb2b4;
op3val:0x72b2; valaddr_reg:x2; val_offset:72*FLEN/8; rmval:dyn;
testreg:x4; fcsr_val:96 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x2, 72*FLEN/8, x3, x1, x4)

inst_58:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x121 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x1b8 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x357 and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7921; op2val:0xb9b8;
op3val:0x7757; valaddr_reg:x2; val_offset:75*FLEN/8; rmval:dyn;
testreg:x4; fcsr_val:96 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x2, 75*FLEN/8, x3, x1, x4)

inst_59:
// fs1 == 0 and fe1 == 0x1c and fm1 == 0x226 and fs2 == 1 and fe2 == 0x11 and fm2 == 0x051 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x2a4 and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7226; op2val:0xc451;
op3val:0x7aa4; valaddr_reg:x2; val_offset:78*FLEN/8; rmval:dyn;
testreg:x4; fcsr_val:96 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x2, 78*FLEN/8, x3, x1, x4)

inst_60:
// fs1 == 0 and fe1 == 0x1b and fm1 == 0x1ba and fs2 == 1 and fe2 == 0x10 and fm2 == 0x13a and fs3 == 0 and fe3 == 0x1c and fm3 == 0x37d and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6dba; op2val:0xc13a;
op3val:0x737d; valaddr_reg:x2; val_offset:81*FLEN/8; rmval:dyn;
testreg:x4; fcsr_val:96 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x2, 81*FLEN/8, x3, x1, x4)

inst_61:
// fs1 == 0 and fe1 == 0x19 and fm1 == 0x11e and fs2 == 1 and fe2 == 0x12 and fm2 == 0x2aa and fs3 == 0 and fe3 == 0x1d and fm3 == 0x044 and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x651e; op2val:0xcaaa;
op3val:0x7444; valaddr_reg:x2; val_offset:84*FLEN/8; rmval:dyn;
testreg:x4; fcsr_val:96 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x2, 84*FLEN/8, x3, x1, x4)

inst_62:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x285 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x06c and fs3 == 0 and fe3 == 0x1e and fm3 == 0x336 and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7685; op2val:0xc06c;
op3val:0x7b36; valaddr_reg:x2; val_offset:87*FLEN/8; rmval:dyn;
testreg:x4; fcsr_val:96 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x2, 87*FLEN/8, x3, x1, x4)

inst_63:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x20f and fs2 == 1 and fe2 == 0x0d and fm2 == 0x0cd and fs3 == 0 and fe3 == 0x1b and fm3 == 0x346 and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x760f; op2val:0xb4cd;
op3val:0x6f46; valaddr_reg:x2; val_offset:90*FLEN/8; rmval:dyn;
testreg:x4; fcsr_val:96 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x2, 90*FLEN/8, x3, x1, x4)

inst_64:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x021 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x3ad and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ed and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7421; op2val:0xc3ad;
op3val:0x7bed; valaddr_reg:x2; val_offset:93*FLEN/8; rmval:dyn;
testreg:x4; fcsr_val:96 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x2, 93*FLEN/8, x3, x1, x4)

inst_65:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2be and fs2 == 1 and fe2 == 0x0e and fm2 == 0x0c6 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x006 and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7abe; op2val:0xb8c6;
op3val:0x7806; valaddr_reg:x2; val_offset:96*FLEN/8; rmval:dyn;
testreg:x4; fcsr_val:96 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x2, 96*FLEN/8, x3, x1, x4)
#endif


RVTEST_CODE_END
RVMODEL_HALT

RVTEST_DATA_BEGIN
.align 4
rvtest_data:
.word 0xbabecafe
.word 0xabecafeb
.word 0xbecafeba
.word 0xecafebab
test_dataset_0:
NAN_BOXED(0,32,FLEN)
NAN_BOXED(0,16,FLEN)
NAN_BOXED(31665,32,FLEN)
NAN_BOXED(28682,32,FLEN)
NAN_BOXED(50580,16,FLEN)
NAN_BOXED(31138,32,FLEN)
NAN_BOXED(28019,32,FLEN)
NAN_BOXED(49615,16,FLEN)
NAN_BOXED(29674,32,FLEN)
NAN_BOXED(31741,32,FLEN)
NAN_BOXED(45748,16,FLEN)
NAN_BOXED(31741,32,FLEN)
NAN_BOXED(31009,32,FLEN)
NAN_BOXED(31009,16,FLEN)
NAN_BOXED(31009,32,FLEN)
NAN_BOXED(30527,32,FLEN)
NAN_BOXED(48222,16,FLEN)
NAN_BOXED(30698,32,FLEN)
NAN_BOXED(29222,32,FLEN)
NAN_BOXED(50257,16,FLEN)
NAN_BOXED(50257,32,FLEN)
NAN_BOXED(28090,32,FLEN)
NAN_BOXED(49466,16,FLEN)
NAN_BOXED(28090,32,FLEN)
NAN_BOXED(25886,32,FLEN)
NAN_BOXED(25886,16,FLEN)
NAN_BOXED(25886,32,FLEN)
NAN_BOXED(30341,32,FLEN)
NAN_BOXED(30341,16,FLEN)
NAN_BOXED(31542,32,FLEN)
NAN_BOXED(30223,32,FLEN)
NAN_BOXED(46285,16,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(29729,32,FLEN)
NAN_BOXED(50093,16,FLEN)
NAN_BOXED(50093,32,FLEN)
test_dataset_1:
NAN_BOXED(27657,32,FLEN)
NAN_BOXED(51433,16,FLEN)
NAN_BOXED(30965,32,FLEN)
NAN_BOXED(30216,32,FLEN)
NAN_BOXED(48897,16,FLEN)
NAN_BOXED(31048,32,FLEN)
NAN_BOXED(30057,32,FLEN)
NAN_BOXED(49173,16,FLEN)
NAN_BOXED(31111,32,FLEN)
NAN_BOXED(30709,32,FLEN)
NAN_BOXED(48441,16,FLEN)
NAN_BOXED(31025,32,FLEN)
NAN_BOXED(31541,32,FLEN)
NAN_BOXED(47401,16,FLEN)
NAN_BOXED(30886,32,FLEN)
NAN_BOXED(28811,32,FLEN)
NAN_BOXED(46911,16,FLEN)
NAN_BOXED(27678,32,FLEN)
NAN_BOXED(31632,32,FLEN)
NAN_BOXED(47137,16,FLEN)
NAN_BOXED(30672,32,FLEN)
NAN_BOXED(29235,32,FLEN)
NAN_BOXED(50401,16,FLEN)
NAN_BOXED(31632,32,FLEN)
NAN_BOXED(30881,32,FLEN)
NAN_BOXED(48393,16,FLEN)
NAN_BOXED(31188,32,FLEN)
NAN_BOXED(31499,32,FLEN)
NAN_BOXED(46384,16,FLEN)
NAN_BOXED(29841,32,FLEN)
test_dataset_2:
NAN_BOXED(30132,32,FLEN)
NAN_BOXED(49388,16,FLEN)
NAN_BOXED(31493,32,FLEN)
NAN_BOXED(28753,32,FLEN)
NAN_BOXED(50601,16,FLEN)
NAN_BOXED(31260,32,FLEN)
NAN_BOXED(28222,32,FLEN)
NAN_BOXED(50961,16,FLEN)
NAN_BOXED(31108,32,FLEN)
NAN_BOXED(31133,32,FLEN)
NAN_BOXED(48489,16,FLEN)
NAN_BOXED(31640,32,FLEN)
NAN_BOXED(31422,32,FLEN)
NAN_BOXED(47302,16,FLEN)
NAN_BOXED(30726,32,FLEN)
NAN_BOXED(29266,32,FLEN)
NAN_BOXED(47635,16,FLEN)
NAN_BOXED(28877,32,FLEN)
NAN_BOXED(30778,32,FLEN)
NAN_BOXED(48054,16,FLEN)
NAN_BOXED(30739,32,FLEN)
NAN_BOXED(27793,32,FLEN)
NAN_BOXED(51794,16,FLEN)
NAN_BOXED(31544,32,FLEN)
NAN_BOXED(30734,32,FLEN)
NAN_BOXED(48519,16,FLEN)
NAN_BOXED(31131,32,FLEN)
NAN_BOXED(29449,32,FLEN)
NAN_BOXED(48239,16,FLEN)
NAN_BOXED(29645,32,FLEN)
NAN_BOXED(25115,32,FLEN)
NAN_BOXED(53041,16,FLEN)
NAN_BOXED(30077,32,FLEN)
test_dataset_3:
NAN_BOXED(29764,16,FLEN)
NAN_BOXED(48728,16,FLEN)
NAN_BOXED(30405,16,FLEN)
NAN_BOXED(30215,16,FLEN)
NAN_BOXED(49261,16,FLEN)
NAN_BOXED(31403,16,FLEN)
NAN_BOXED(31520,16,FLEN)
NAN_BOXED(45642,16,FLEN)
NAN_BOXED(29083,16,FLEN)
NAN_BOXED(30294,16,FLEN)
NAN_BOXED(46773,16,FLEN)
NAN_BOXED(29008,16,FLEN)
NAN_BOXED(31053,16,FLEN)
NAN_BOXED(48609,16,FLEN)
NAN_BOXED(31691,16,FLEN)
NAN_BOXED(29300,16,FLEN)
NAN_BOXED(50072,16,FLEN)
NAN_BOXED(31264,16,FLEN)
NAN_BOXED(29900,16,FLEN)
NAN_BOXED(43429,16,FLEN)
NAN_BOXED(25285,16,FLEN)
NAN_BOXED(31260,16,FLEN)
NAN_BOXED(46887,16,FLEN)
NAN_BOXED(30071,16,FLEN)
NAN_BOXED(29041,16,FLEN)
NAN_BOXED(49438,16,FLEN)
NAN_BOXED(30455,16,FLEN)
NAN_BOXED(29545,16,FLEN)
NAN_BOXED(48920,16,FLEN)
NAN_BOXED(30350,16,FLEN)
NAN_BOXED(30498,16,FLEN)
NAN_BOXED(48003,16,FLEN)
NAN_BOXED(30383,16,FLEN)
NAN_BOXED(30900,16,FLEN)
NAN_BOXED(47072,16,FLEN)
NAN_BOXED(29854,16,FLEN)
NAN_BOXED(28181,16,FLEN)
NAN_BOXED(47936,16,FLEN)
NAN_BOXED(28020,16,FLEN)
NAN_BOXED(28368,16,FLEN)
NAN_BOXED(50406,16,FLEN)
NAN_BOXED(30762,16,FLEN)
NAN_BOXED(30146,16,FLEN)
NAN_BOXED(49277,16,FLEN)
NAN_BOXED(31349,16,FLEN)
NAN_BOXED(30729,16,FLEN)
NAN_BOXED(48542,16,FLEN)
NAN_BOXED(31145,16,FLEN)
NAN_BOXED(31702,16,FLEN)
NAN_BOXED(44060,16,FLEN)
NAN_BOXED(27655,16,FLEN)
NAN_BOXED(25686,16,FLEN)
NAN_BOXED(51235,16,FLEN)
NAN_BOXED(28797,16,FLEN)
NAN_BOXED(30253,16,FLEN)
NAN_BOXED(48624,16,FLEN)
NAN_BOXED(30870,16,FLEN)
NAN_BOXED(31218,16,FLEN)
NAN_BOXED(46991,16,FLEN)
NAN_BOXED(30110,16,FLEN)
NAN_BOXED(31671,16,FLEN)
NAN_BOXED(39494,16,FLEN)
NAN_BOXED(23052,16,FLEN)
NAN_BOXED(31406,16,FLEN)
NAN_BOXED(46085,16,FLEN)
NAN_BOXED(29368,16,FLEN)
NAN_BOXED(31487,16,FLEN)
NAN_BOXED(43224,16,FLEN)
NAN_BOXED(26685,16,FLEN)
NAN_BOXED(29504,16,FLEN)
NAN_BOXED(50238,16,FLEN)
NAN_BOXED(31665,16,FLEN)
NAN_BOXED(31741,16,FLEN)
NAN_BOXED(45748,16,FLEN)
NAN_BOXED(29362,16,FLEN)
NAN_BOXED(31009,16,FLEN)
NAN_BOXED(47544,16,FLEN)
NAN_BOXED(30551,16,FLEN)
NAN_BOXED(29222,16,FLEN)
NAN_BOXED(50257,16,FLEN)
NAN_BOXED(31396,16,FLEN)
NAN_BOXED(28090,16,FLEN)
NAN_BOXED(49466,16,FLEN)
NAN_BOXED(29565,16,FLEN)
NAN_BOXED(25886,16,FLEN)
NAN_BOXED(51882,16,FLEN)
NAN_BOXED(29764,16,FLEN)
NAN_BOXED(30341,16,FLEN)
NAN_BOXED(49260,16,FLEN)
NAN_BOXED(31542,16,FLEN)
NAN_BOXED(30223,16,FLEN)
NAN_BOXED(46285,16,FLEN)
NAN_BOXED(28486,16,FLEN)
NAN_BOXED(29729,16,FLEN)
NAN_BOXED(50093,16,FLEN)
NAN_BOXED(31725,16,FLEN)
NAN_BOXED(31422,16,FLEN)
NAN_BOXED(47302,16,FLEN)
NAN_BOXED(30726,16,FLEN)
RVTEST_DATA_END

RVMODEL_DATA_BEGIN
rvtest_sig_begin:
sig_begin_canary:
CANARY;



signature_x2_0:
    .fill 0*((SIGALIGN)/4),4,0xdeadbeef


signature_x2_1:
    .fill 30*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_0:
    .fill 28*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_1:
    .fill 74*((SIGALIGN)/4),4,0xdeadbeef

#ifdef rvtest_mtrap_routine
tsig_begin_canary:
CANARY;

mtrap_sigptr:
    .fill 64*XLEN/32,4,0xdeadbeef

tsig_end_canary:
CANARY;
#endif

#ifdef rvtest_gpr_save

gpr_save:
    .fill 32*XLEN/32,4,0xdeadbeef

#endif


sig_end_canary:
CANARY;
rvtest_sig_end:
RVMODEL_DATA_END
