
// -----------
// This file was generated by riscv_ctg (https://github.com/riscv-software-src/riscv-ctg)
// version   : 0.7.1
// timestamp : Fri Jun 17 14:17:59 2022 GMT
// usage     : riscv_ctg \
//                  -- cgf //                  --cgf /scratch/pawan/work/normalised/RV32F/fmadd.s.cgf \
 \
//                  -- xlen 32  \
//                  --randomize \
// -----------
//
// -----------
// Copyright (c) 2020. RISC-V International. All rights reserved.
// SPDX-License-Identifier: BSD-3-Clause
// -----------
//
// This assembly file tests the fmadd.s instruction of the RISC-V RV32F_Zicsr,RV32FD_Zicsr,RV64F_Zicsr,RV64FD_Zicsr extension for the fmadd_b15 covergroup.
// 
#include "model_test.h"
#include "arch_test.h"
RVTEST_ISA("RV32IF_Zicsr,RV32IFD_Zicsr,RV64IF_Zicsr,RV64IFD_Zicsr,RV32EF_Zicsr,RV32EFD_Zicsr,RV64EF_Zicsr,RV64EFD_Zicsr")

.section .text.init
.globl rvtest_entry_point
rvtest_entry_point:
RVMODEL_BOOT
RVTEST_CODE_BEGIN

#ifdef TEST_CASE_1

RVTEST_CASE(0,"//check ISA:=regex(.*I.*F.*);def TEST_CASE_1=True;",fmadd_b15)
RVTEST_CASE(1,"//check ISA:=regex(.*E.*F.*);def TEST_CASE_1=True;",fmadd_b15)
RVTEST_FP_ENABLE()
RVTEST_VALBASEUPD(x3,test_dataset_0)
RVTEST_SIGBASE(x1,signature_x1_1)

inst_3072:
// fs1 == 0 and fe1 == 0xfa and fm1 == 0x677175 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x0a and fm3 == 0x7ffe00 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7d677175; op2val:0x80000000;
op3val:0x857ffe00; valaddr_reg:x3; val_offset:9216*0 + 3*-1*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 9216*0 + 3*0*FLEN/8, x4, x1, x2)

inst_3073:
// fs1 == 0 and fe1 == 0xfa and fm1 == 0x677175 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x0a and fm3 == 0x7fff00 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7d677175; op2val:0x80000000;
op3val:0x857fff00; valaddr_reg:x3; val_offset:9219*0 + 3*0*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 9219*0 + 3*1*FLEN/8, x4, x1, x2)

inst_3074:
// fs1 == 0 and fe1 == 0xfa and fm1 == 0x677175 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x0a and fm3 == 0x7fff80 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7d677175; op2val:0x80000000;
op3val:0x857fff80; valaddr_reg:x3; val_offset:9222*0 + 3*1*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 9222*0 + 3*2*FLEN/8, x4, x1, x2)

inst_3075:
// fs1 == 0 and fe1 == 0xfa and fm1 == 0x677175 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x0a and fm3 == 0x7fffc0 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7d677175; op2val:0x80000000;
op3val:0x857fffc0; valaddr_reg:x3; val_offset:9225*0 + 3*2*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 9225*0 + 3*3*FLEN/8, x4, x1, x2)

inst_3076:
// fs1 == 0 and fe1 == 0xfa and fm1 == 0x677175 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x0a and fm3 == 0x7fffe0 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7d677175; op2val:0x80000000;
op3val:0x857fffe0; valaddr_reg:x3; val_offset:9228*0 + 3*3*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 9228*0 + 3*4*FLEN/8, x4, x1, x2)

inst_3077:
// fs1 == 0 and fe1 == 0xfa and fm1 == 0x677175 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x0a and fm3 == 0x7ffff0 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7d677175; op2val:0x80000000;
op3val:0x857ffff0; valaddr_reg:x3; val_offset:9231*0 + 3*4*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 9231*0 + 3*5*FLEN/8, x4, x1, x2)

inst_3078:
// fs1 == 0 and fe1 == 0xfa and fm1 == 0x677175 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x0a and fm3 == 0x7ffff8 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7d677175; op2val:0x80000000;
op3val:0x857ffff8; valaddr_reg:x3; val_offset:9234*0 + 3*5*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 9234*0 + 3*6*FLEN/8, x4, x1, x2)

inst_3079:
// fs1 == 0 and fe1 == 0xfa and fm1 == 0x677175 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x0a and fm3 == 0x7ffffc and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7d677175; op2val:0x80000000;
op3val:0x857ffffc; valaddr_reg:x3; val_offset:9237*0 + 3*6*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 9237*0 + 3*7*FLEN/8, x4, x1, x2)

inst_3080:
// fs1 == 0 and fe1 == 0xfa and fm1 == 0x677175 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x0a and fm3 == 0x7ffffe and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7d677175; op2val:0x80000000;
op3val:0x857ffffe; valaddr_reg:x3; val_offset:9240*0 + 3*7*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 9240*0 + 3*8*FLEN/8, x4, x1, x2)

inst_3081:
// fs1 == 0 and fe1 == 0xfa and fm1 == 0x677175 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x0a and fm3 == 0x7fffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7d677175; op2val:0x80000000;
op3val:0x857fffff; valaddr_reg:x3; val_offset:9243*0 + 3*8*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 9243*0 + 3*9*FLEN/8, x4, x1, x2)

inst_3082:
// fs1 == 0 and fe1 == 0xfa and fm1 == 0x6a9275 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000001 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7d6a9275; op2val:0x80000000;
op3val:0x80000001; valaddr_reg:x3; val_offset:9246*0 + 3*9*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 9246*0 + 3*10*FLEN/8, x4, x1, x2)

inst_3083:
// fs1 == 0 and fe1 == 0xfa and fm1 == 0x6a9275 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000003 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7d6a9275; op2val:0x80000000;
op3val:0x80000003; valaddr_reg:x3; val_offset:9249*0 + 3*10*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 9249*0 + 3*11*FLEN/8, x4, x1, x2)

inst_3084:
// fs1 == 0 and fe1 == 0xfa and fm1 == 0x6a9275 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000007 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7d6a9275; op2val:0x80000000;
op3val:0x80000007; valaddr_reg:x3; val_offset:9252*0 + 3*11*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 9252*0 + 3*12*FLEN/8, x4, x1, x2)

inst_3085:
// fs1 == 0 and fe1 == 0xfa and fm1 == 0x6a9275 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x199999 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7d6a9275; op2val:0x80000000;
op3val:0x80199999; valaddr_reg:x3; val_offset:9255*0 + 3*12*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 9255*0 + 3*13*FLEN/8, x4, x1, x2)

inst_3086:
// fs1 == 0 and fe1 == 0xfa and fm1 == 0x6a9275 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x249249 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7d6a9275; op2val:0x80000000;
op3val:0x80249249; valaddr_reg:x3; val_offset:9258*0 + 3*13*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 9258*0 + 3*14*FLEN/8, x4, x1, x2)

inst_3087:
// fs1 == 0 and fe1 == 0xfa and fm1 == 0x6a9275 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x333333 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7d6a9275; op2val:0x80000000;
op3val:0x80333333; valaddr_reg:x3; val_offset:9261*0 + 3*14*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 9261*0 + 3*15*FLEN/8, x4, x1, x2)

inst_3088:
// fs1 == 0 and fe1 == 0xfa and fm1 == 0x6a9275 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x36db6d and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7d6a9275; op2val:0x80000000;
op3val:0x8036db6d; valaddr_reg:x3; val_offset:9264*0 + 3*15*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 9264*0 + 3*16*FLEN/8, x4, x1, x2)

inst_3089:
// fs1 == 0 and fe1 == 0xfa and fm1 == 0x6a9275 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3bbbbb and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7d6a9275; op2val:0x80000000;
op3val:0x803bbbbb; valaddr_reg:x3; val_offset:9267*0 + 3*16*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 9267*0 + 3*17*FLEN/8, x4, x1, x2)

inst_3090:
// fs1 == 0 and fe1 == 0xfa and fm1 == 0x6a9275 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x444444 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7d6a9275; op2val:0x80000000;
op3val:0x80444444; valaddr_reg:x3; val_offset:9270*0 + 3*17*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 9270*0 + 3*18*FLEN/8, x4, x1, x2)

inst_3091:
// fs1 == 0 and fe1 == 0xfa and fm1 == 0x6a9275 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x4ccccc and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7d6a9275; op2val:0x80000000;
op3val:0x804ccccc; valaddr_reg:x3; val_offset:9273*0 + 3*18*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 9273*0 + 3*19*FLEN/8, x4, x1, x2)

inst_3092:
// fs1 == 0 and fe1 == 0xfa and fm1 == 0x6a9275 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x5b6db6 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7d6a9275; op2val:0x80000000;
op3val:0x805b6db6; valaddr_reg:x3; val_offset:9276*0 + 3*19*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 9276*0 + 3*20*FLEN/8, x4, x1, x2)

inst_3093:
// fs1 == 0 and fe1 == 0xfa and fm1 == 0x6a9275 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x666666 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7d6a9275; op2val:0x80000000;
op3val:0x80666666; valaddr_reg:x3; val_offset:9279*0 + 3*20*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 9279*0 + 3*21*FLEN/8, x4, x1, x2)

inst_3094:
// fs1 == 0 and fe1 == 0xfa and fm1 == 0x6a9275 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x6db6db and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7d6a9275; op2val:0x80000000;
op3val:0x806db6db; valaddr_reg:x3; val_offset:9282*0 + 3*21*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 9282*0 + 3*22*FLEN/8, x4, x1, x2)

inst_3095:
// fs1 == 0 and fe1 == 0xfa and fm1 == 0x6a9275 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7ffff8 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7d6a9275; op2val:0x80000000;
op3val:0x807ffff8; valaddr_reg:x3; val_offset:9285*0 + 3*22*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 9285*0 + 3*23*FLEN/8, x4, x1, x2)

inst_3096:
// fs1 == 0 and fe1 == 0xfa and fm1 == 0x6a9275 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7ffffc and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7d6a9275; op2val:0x80000000;
op3val:0x807ffffc; valaddr_reg:x3; val_offset:9288*0 + 3*23*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 9288*0 + 3*24*FLEN/8, x4, x1, x2)

inst_3097:
// fs1 == 0 and fe1 == 0xfa and fm1 == 0x6a9275 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7ffffe and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7d6a9275; op2val:0x80000000;
op3val:0x807ffffe; valaddr_reg:x3; val_offset:9291*0 + 3*24*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 9291*0 + 3*25*FLEN/8, x4, x1, x2)

inst_3098:
// fs1 == 0 and fe1 == 0xfa and fm1 == 0x6a9275 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x06 and fm3 == 0x000000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7d6a9275; op2val:0x80000000;
op3val:0x83000000; valaddr_reg:x3; val_offset:9294*0 + 3*25*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 9294*0 + 3*26*FLEN/8, x4, x1, x2)

inst_3099:
// fs1 == 0 and fe1 == 0xfa and fm1 == 0x6a9275 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x06 and fm3 == 0x000001 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7d6a9275; op2val:0x80000000;
op3val:0x83000001; valaddr_reg:x3; val_offset:9297*0 + 3*26*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 9297*0 + 3*27*FLEN/8, x4, x1, x2)

inst_3100:
// fs1 == 0 and fe1 == 0xfa and fm1 == 0x6a9275 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x06 and fm3 == 0x000003 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7d6a9275; op2val:0x80000000;
op3val:0x83000003; valaddr_reg:x3; val_offset:9300*0 + 3*27*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 9300*0 + 3*28*FLEN/8, x4, x1, x2)

inst_3101:
// fs1 == 0 and fe1 == 0xfa and fm1 == 0x6a9275 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x06 and fm3 == 0x000007 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7d6a9275; op2val:0x80000000;
op3val:0x83000007; valaddr_reg:x3; val_offset:9303*0 + 3*28*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 9303*0 + 3*29*FLEN/8, x4, x1, x2)

inst_3102:
// fs1 == 0 and fe1 == 0xfa and fm1 == 0x6a9275 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x06 and fm3 == 0x00000f and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7d6a9275; op2val:0x80000000;
op3val:0x8300000f; valaddr_reg:x3; val_offset:9306*0 + 3*29*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 9306*0 + 3*30*FLEN/8, x4, x1, x2)

inst_3103:
// fs1 == 0 and fe1 == 0xfa and fm1 == 0x6a9275 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x06 and fm3 == 0x00001f and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7d6a9275; op2val:0x80000000;
op3val:0x8300001f; valaddr_reg:x3; val_offset:9309*0 + 3*30*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 9309*0 + 3*31*FLEN/8, x4, x1, x2)

inst_3104:
// fs1 == 0 and fe1 == 0xfa and fm1 == 0x6a9275 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x06 and fm3 == 0x00003f and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7d6a9275; op2val:0x80000000;
op3val:0x8300003f; valaddr_reg:x3; val_offset:9312*0 + 3*31*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 9312*0 + 3*32*FLEN/8, x4, x1, x2)

inst_3105:
// fs1 == 0 and fe1 == 0xfa and fm1 == 0x6a9275 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x06 and fm3 == 0x00007f and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7d6a9275; op2val:0x80000000;
op3val:0x8300007f; valaddr_reg:x3; val_offset:9315*0 + 3*32*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 9315*0 + 3*33*FLEN/8, x4, x1, x2)

inst_3106:
// fs1 == 0 and fe1 == 0xfa and fm1 == 0x6a9275 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x06 and fm3 == 0x0000ff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7d6a9275; op2val:0x80000000;
op3val:0x830000ff; valaddr_reg:x3; val_offset:9318*0 + 3*33*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 9318*0 + 3*34*FLEN/8, x4, x1, x2)

inst_3107:
// fs1 == 0 and fe1 == 0xfa and fm1 == 0x6a9275 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x06 and fm3 == 0x0001ff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7d6a9275; op2val:0x80000000;
op3val:0x830001ff; valaddr_reg:x3; val_offset:9321*0 + 3*34*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 9321*0 + 3*35*FLEN/8, x4, x1, x2)

inst_3108:
// fs1 == 0 and fe1 == 0xfa and fm1 == 0x6a9275 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x06 and fm3 == 0x0003ff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7d6a9275; op2val:0x80000000;
op3val:0x830003ff; valaddr_reg:x3; val_offset:9324*0 + 3*35*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 9324*0 + 3*36*FLEN/8, x4, x1, x2)

inst_3109:
// fs1 == 0 and fe1 == 0xfa and fm1 == 0x6a9275 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x06 and fm3 == 0x0007ff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7d6a9275; op2val:0x80000000;
op3val:0x830007ff; valaddr_reg:x3; val_offset:9327*0 + 3*36*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 9327*0 + 3*37*FLEN/8, x4, x1, x2)

inst_3110:
// fs1 == 0 and fe1 == 0xfa and fm1 == 0x6a9275 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x06 and fm3 == 0x000fff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7d6a9275; op2val:0x80000000;
op3val:0x83000fff; valaddr_reg:x3; val_offset:9330*0 + 3*37*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 9330*0 + 3*38*FLEN/8, x4, x1, x2)

inst_3111:
// fs1 == 0 and fe1 == 0xfa and fm1 == 0x6a9275 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x06 and fm3 == 0x001fff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7d6a9275; op2val:0x80000000;
op3val:0x83001fff; valaddr_reg:x3; val_offset:9333*0 + 3*38*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 9333*0 + 3*39*FLEN/8, x4, x1, x2)

inst_3112:
// fs1 == 0 and fe1 == 0xfa and fm1 == 0x6a9275 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x06 and fm3 == 0x003fff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7d6a9275; op2val:0x80000000;
op3val:0x83003fff; valaddr_reg:x3; val_offset:9336*0 + 3*39*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 9336*0 + 3*40*FLEN/8, x4, x1, x2)

inst_3113:
// fs1 == 0 and fe1 == 0xfa and fm1 == 0x6a9275 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x06 and fm3 == 0x007fff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7d6a9275; op2val:0x80000000;
op3val:0x83007fff; valaddr_reg:x3; val_offset:9339*0 + 3*40*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 9339*0 + 3*41*FLEN/8, x4, x1, x2)

inst_3114:
// fs1 == 0 and fe1 == 0xfa and fm1 == 0x6a9275 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x06 and fm3 == 0x00ffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7d6a9275; op2val:0x80000000;
op3val:0x8300ffff; valaddr_reg:x3; val_offset:9342*0 + 3*41*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 9342*0 + 3*42*FLEN/8, x4, x1, x2)

inst_3115:
// fs1 == 0 and fe1 == 0xfa and fm1 == 0x6a9275 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x06 and fm3 == 0x01ffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7d6a9275; op2val:0x80000000;
op3val:0x8301ffff; valaddr_reg:x3; val_offset:9345*0 + 3*42*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 9345*0 + 3*43*FLEN/8, x4, x1, x2)

inst_3116:
// fs1 == 0 and fe1 == 0xfa and fm1 == 0x6a9275 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x06 and fm3 == 0x03ffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7d6a9275; op2val:0x80000000;
op3val:0x8303ffff; valaddr_reg:x3; val_offset:9348*0 + 3*43*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 9348*0 + 3*44*FLEN/8, x4, x1, x2)

inst_3117:
// fs1 == 0 and fe1 == 0xfa and fm1 == 0x6a9275 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x06 and fm3 == 0x07ffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7d6a9275; op2val:0x80000000;
op3val:0x8307ffff; valaddr_reg:x3; val_offset:9351*0 + 3*44*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 9351*0 + 3*45*FLEN/8, x4, x1, x2)

inst_3118:
// fs1 == 0 and fe1 == 0xfa and fm1 == 0x6a9275 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x06 and fm3 == 0x0fffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7d6a9275; op2val:0x80000000;
op3val:0x830fffff; valaddr_reg:x3; val_offset:9354*0 + 3*45*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 9354*0 + 3*46*FLEN/8, x4, x1, x2)

inst_3119:
// fs1 == 0 and fe1 == 0xfa and fm1 == 0x6a9275 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x06 and fm3 == 0x1fffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7d6a9275; op2val:0x80000000;
op3val:0x831fffff; valaddr_reg:x3; val_offset:9357*0 + 3*46*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 9357*0 + 3*47*FLEN/8, x4, x1, x2)

inst_3120:
// fs1 == 0 and fe1 == 0xfa and fm1 == 0x6a9275 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x06 and fm3 == 0x3fffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7d6a9275; op2val:0x80000000;
op3val:0x833fffff; valaddr_reg:x3; val_offset:9360*0 + 3*47*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 9360*0 + 3*48*FLEN/8, x4, x1, x2)

inst_3121:
// fs1 == 0 and fe1 == 0xfa and fm1 == 0x6a9275 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x06 and fm3 == 0x400000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7d6a9275; op2val:0x80000000;
op3val:0x83400000; valaddr_reg:x3; val_offset:9363*0 + 3*48*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 9363*0 + 3*49*FLEN/8, x4, x1, x2)

inst_3122:
// fs1 == 0 and fe1 == 0xfa and fm1 == 0x6a9275 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x06 and fm3 == 0x600000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7d6a9275; op2val:0x80000000;
op3val:0x83600000; valaddr_reg:x3; val_offset:9366*0 + 3*49*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 9366*0 + 3*50*FLEN/8, x4, x1, x2)

inst_3123:
// fs1 == 0 and fe1 == 0xfa and fm1 == 0x6a9275 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x06 and fm3 == 0x700000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7d6a9275; op2val:0x80000000;
op3val:0x83700000; valaddr_reg:x3; val_offset:9369*0 + 3*50*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 9369*0 + 3*51*FLEN/8, x4, x1, x2)

inst_3124:
// fs1 == 0 and fe1 == 0xfa and fm1 == 0x6a9275 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x06 and fm3 == 0x780000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7d6a9275; op2val:0x80000000;
op3val:0x83780000; valaddr_reg:x3; val_offset:9372*0 + 3*51*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 9372*0 + 3*52*FLEN/8, x4, x1, x2)

inst_3125:
// fs1 == 0 and fe1 == 0xfa and fm1 == 0x6a9275 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x06 and fm3 == 0x7c0000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7d6a9275; op2val:0x80000000;
op3val:0x837c0000; valaddr_reg:x3; val_offset:9375*0 + 3*52*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 9375*0 + 3*53*FLEN/8, x4, x1, x2)

inst_3126:
// fs1 == 0 and fe1 == 0xfa and fm1 == 0x6a9275 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x06 and fm3 == 0x7e0000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7d6a9275; op2val:0x80000000;
op3val:0x837e0000; valaddr_reg:x3; val_offset:9378*0 + 3*53*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 9378*0 + 3*54*FLEN/8, x4, x1, x2)

inst_3127:
// fs1 == 0 and fe1 == 0xfa and fm1 == 0x6a9275 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x06 and fm3 == 0x7f0000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7d6a9275; op2val:0x80000000;
op3val:0x837f0000; valaddr_reg:x3; val_offset:9381*0 + 3*54*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 9381*0 + 3*55*FLEN/8, x4, x1, x2)

inst_3128:
// fs1 == 0 and fe1 == 0xfa and fm1 == 0x6a9275 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x06 and fm3 == 0x7f8000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7d6a9275; op2val:0x80000000;
op3val:0x837f8000; valaddr_reg:x3; val_offset:9384*0 + 3*55*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 9384*0 + 3*56*FLEN/8, x4, x1, x2)

inst_3129:
// fs1 == 0 and fe1 == 0xfa and fm1 == 0x6a9275 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x06 and fm3 == 0x7fc000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7d6a9275; op2val:0x80000000;
op3val:0x837fc000; valaddr_reg:x3; val_offset:9387*0 + 3*56*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 9387*0 + 3*57*FLEN/8, x4, x1, x2)

inst_3130:
// fs1 == 0 and fe1 == 0xfa and fm1 == 0x6a9275 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x06 and fm3 == 0x7fe000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7d6a9275; op2val:0x80000000;
op3val:0x837fe000; valaddr_reg:x3; val_offset:9390*0 + 3*57*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 9390*0 + 3*58*FLEN/8, x4, x1, x2)

inst_3131:
// fs1 == 0 and fe1 == 0xfa and fm1 == 0x6a9275 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x06 and fm3 == 0x7ff000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7d6a9275; op2val:0x80000000;
op3val:0x837ff000; valaddr_reg:x3; val_offset:9393*0 + 3*58*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 9393*0 + 3*59*FLEN/8, x4, x1, x2)

inst_3132:
// fs1 == 0 and fe1 == 0xfa and fm1 == 0x6a9275 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x06 and fm3 == 0x7ff800 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7d6a9275; op2val:0x80000000;
op3val:0x837ff800; valaddr_reg:x3; val_offset:9396*0 + 3*59*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 9396*0 + 3*60*FLEN/8, x4, x1, x2)

inst_3133:
// fs1 == 0 and fe1 == 0xfa and fm1 == 0x6a9275 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x06 and fm3 == 0x7ffc00 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7d6a9275; op2val:0x80000000;
op3val:0x837ffc00; valaddr_reg:x3; val_offset:9399*0 + 3*60*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 9399*0 + 3*61*FLEN/8, x4, x1, x2)

inst_3134:
// fs1 == 0 and fe1 == 0xfa and fm1 == 0x6a9275 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x06 and fm3 == 0x7ffe00 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7d6a9275; op2val:0x80000000;
op3val:0x837ffe00; valaddr_reg:x3; val_offset:9402*0 + 3*61*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 9402*0 + 3*62*FLEN/8, x4, x1, x2)

inst_3135:
// fs1 == 0 and fe1 == 0xfa and fm1 == 0x6a9275 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x06 and fm3 == 0x7fff00 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7d6a9275; op2val:0x80000000;
op3val:0x837fff00; valaddr_reg:x3; val_offset:9405*0 + 3*62*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 9405*0 + 3*63*FLEN/8, x4, x1, x2)

inst_3136:
// fs1 == 0 and fe1 == 0xfa and fm1 == 0x6a9275 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x06 and fm3 == 0x7fff80 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7d6a9275; op2val:0x80000000;
op3val:0x837fff80; valaddr_reg:x3; val_offset:9408*0 + 3*63*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 9408*0 + 3*64*FLEN/8, x4, x1, x2)

inst_3137:
// fs1 == 0 and fe1 == 0xfa and fm1 == 0x6a9275 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x06 and fm3 == 0x7fffc0 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7d6a9275; op2val:0x80000000;
op3val:0x837fffc0; valaddr_reg:x3; val_offset:9411*0 + 3*64*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 9411*0 + 3*65*FLEN/8, x4, x1, x2)

inst_3138:
// fs1 == 0 and fe1 == 0xfa and fm1 == 0x6a9275 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x06 and fm3 == 0x7fffe0 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7d6a9275; op2val:0x80000000;
op3val:0x837fffe0; valaddr_reg:x3; val_offset:9414*0 + 3*65*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 9414*0 + 3*66*FLEN/8, x4, x1, x2)

inst_3139:
// fs1 == 0 and fe1 == 0xfa and fm1 == 0x6a9275 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x06 and fm3 == 0x7ffff0 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7d6a9275; op2val:0x80000000;
op3val:0x837ffff0; valaddr_reg:x3; val_offset:9417*0 + 3*66*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 9417*0 + 3*67*FLEN/8, x4, x1, x2)

inst_3140:
// fs1 == 0 and fe1 == 0xfa and fm1 == 0x6a9275 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x06 and fm3 == 0x7ffff8 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7d6a9275; op2val:0x80000000;
op3val:0x837ffff8; valaddr_reg:x3; val_offset:9420*0 + 3*67*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 9420*0 + 3*68*FLEN/8, x4, x1, x2)

inst_3141:
// fs1 == 0 and fe1 == 0xfa and fm1 == 0x6a9275 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x06 and fm3 == 0x7ffffc and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7d6a9275; op2val:0x80000000;
op3val:0x837ffffc; valaddr_reg:x3; val_offset:9423*0 + 3*68*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 9423*0 + 3*69*FLEN/8, x4, x1, x2)

inst_3142:
// fs1 == 0 and fe1 == 0xfa and fm1 == 0x6a9275 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x06 and fm3 == 0x7ffffe and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7d6a9275; op2val:0x80000000;
op3val:0x837ffffe; valaddr_reg:x3; val_offset:9426*0 + 3*69*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 9426*0 + 3*70*FLEN/8, x4, x1, x2)

inst_3143:
// fs1 == 0 and fe1 == 0xfa and fm1 == 0x6a9275 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x06 and fm3 == 0x7fffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7d6a9275; op2val:0x80000000;
op3val:0x837fffff; valaddr_reg:x3; val_offset:9429*0 + 3*70*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 9429*0 + 3*71*FLEN/8, x4, x1, x2)

inst_3144:
// fs1 == 0 and fe1 == 0xfa and fm1 == 0x72ea27 and fs2 == 0 and fe2 == 0x03 and fm2 == 0x06e525 and fs3 == 0 and fe3 == 0x7f and fm3 == 0x000001 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7d72ea27; op2val:0x186e525;
op3val:0x3f800001; valaddr_reg:x3; val_offset:9432*0 + 3*71*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 9432*0 + 3*72*FLEN/8, x4, x1, x2)

inst_3145:
// fs1 == 0 and fe1 == 0xfa and fm1 == 0x72ea27 and fs2 == 0 and fe2 == 0x03 and fm2 == 0x06e525 and fs3 == 0 and fe3 == 0x7f and fm3 == 0x000003 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7d72ea27; op2val:0x186e525;
op3val:0x3f800003; valaddr_reg:x3; val_offset:9435*0 + 3*72*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 9435*0 + 3*73*FLEN/8, x4, x1, x2)

inst_3146:
// fs1 == 0 and fe1 == 0xfa and fm1 == 0x72ea27 and fs2 == 0 and fe2 == 0x03 and fm2 == 0x06e525 and fs3 == 0 and fe3 == 0x7f and fm3 == 0x000007 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7d72ea27; op2val:0x186e525;
op3val:0x3f800007; valaddr_reg:x3; val_offset:9438*0 + 3*73*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 9438*0 + 3*74*FLEN/8, x4, x1, x2)

inst_3147:
// fs1 == 0 and fe1 == 0xfa and fm1 == 0x72ea27 and fs2 == 0 and fe2 == 0x03 and fm2 == 0x06e525 and fs3 == 0 and fe3 == 0x7f and fm3 == 0x199999 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7d72ea27; op2val:0x186e525;
op3val:0x3f999999; valaddr_reg:x3; val_offset:9441*0 + 3*74*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 9441*0 + 3*75*FLEN/8, x4, x1, x2)

inst_3148:
// fs1 == 0 and fe1 == 0xfa and fm1 == 0x72ea27 and fs2 == 0 and fe2 == 0x03 and fm2 == 0x06e525 and fs3 == 0 and fe3 == 0x7f and fm3 == 0x249249 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7d72ea27; op2val:0x186e525;
op3val:0x3fa49249; valaddr_reg:x3; val_offset:9444*0 + 3*75*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 9444*0 + 3*76*FLEN/8, x4, x1, x2)

inst_3149:
// fs1 == 0 and fe1 == 0xfa and fm1 == 0x72ea27 and fs2 == 0 and fe2 == 0x03 and fm2 == 0x06e525 and fs3 == 0 and fe3 == 0x7f and fm3 == 0x333333 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7d72ea27; op2val:0x186e525;
op3val:0x3fb33333; valaddr_reg:x3; val_offset:9447*0 + 3*76*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 9447*0 + 3*77*FLEN/8, x4, x1, x2)

inst_3150:
// fs1 == 0 and fe1 == 0xfa and fm1 == 0x72ea27 and fs2 == 0 and fe2 == 0x03 and fm2 == 0x06e525 and fs3 == 0 and fe3 == 0x7f and fm3 == 0x36db6d and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7d72ea27; op2val:0x186e525;
op3val:0x3fb6db6d; valaddr_reg:x3; val_offset:9450*0 + 3*77*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 9450*0 + 3*78*FLEN/8, x4, x1, x2)

inst_3151:
// fs1 == 0 and fe1 == 0xfa and fm1 == 0x72ea27 and fs2 == 0 and fe2 == 0x03 and fm2 == 0x06e525 and fs3 == 0 and fe3 == 0x7f and fm3 == 0x3bbbbb and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7d72ea27; op2val:0x186e525;
op3val:0x3fbbbbbb; valaddr_reg:x3; val_offset:9453*0 + 3*78*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 9453*0 + 3*79*FLEN/8, x4, x1, x2)

inst_3152:
// fs1 == 0 and fe1 == 0xfa and fm1 == 0x72ea27 and fs2 == 0 and fe2 == 0x03 and fm2 == 0x06e525 and fs3 == 0 and fe3 == 0x7f and fm3 == 0x444444 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7d72ea27; op2val:0x186e525;
op3val:0x3fc44444; valaddr_reg:x3; val_offset:9456*0 + 3*79*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 9456*0 + 3*80*FLEN/8, x4, x1, x2)

inst_3153:
// fs1 == 0 and fe1 == 0xfa and fm1 == 0x72ea27 and fs2 == 0 and fe2 == 0x03 and fm2 == 0x06e525 and fs3 == 0 and fe3 == 0x7f and fm3 == 0x4ccccc and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7d72ea27; op2val:0x186e525;
op3val:0x3fcccccc; valaddr_reg:x3; val_offset:9459*0 + 3*80*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 9459*0 + 3*81*FLEN/8, x4, x1, x2)

inst_3154:
// fs1 == 0 and fe1 == 0xfa and fm1 == 0x72ea27 and fs2 == 0 and fe2 == 0x03 and fm2 == 0x06e525 and fs3 == 0 and fe3 == 0x7f and fm3 == 0x5b6db6 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7d72ea27; op2val:0x186e525;
op3val:0x3fdb6db6; valaddr_reg:x3; val_offset:9462*0 + 3*81*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 9462*0 + 3*82*FLEN/8, x4, x1, x2)

inst_3155:
// fs1 == 0 and fe1 == 0xfa and fm1 == 0x72ea27 and fs2 == 0 and fe2 == 0x03 and fm2 == 0x06e525 and fs3 == 0 and fe3 == 0x7f and fm3 == 0x666666 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7d72ea27; op2val:0x186e525;
op3val:0x3fe66666; valaddr_reg:x3; val_offset:9465*0 + 3*82*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 9465*0 + 3*83*FLEN/8, x4, x1, x2)

inst_3156:
// fs1 == 0 and fe1 == 0xfa and fm1 == 0x72ea27 and fs2 == 0 and fe2 == 0x03 and fm2 == 0x06e525 and fs3 == 0 and fe3 == 0x7f and fm3 == 0x6db6db and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7d72ea27; op2val:0x186e525;
op3val:0x3fedb6db; valaddr_reg:x3; val_offset:9468*0 + 3*83*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 9468*0 + 3*84*FLEN/8, x4, x1, x2)

inst_3157:
// fs1 == 0 and fe1 == 0xfa and fm1 == 0x72ea27 and fs2 == 0 and fe2 == 0x03 and fm2 == 0x06e525 and fs3 == 0 and fe3 == 0x7f and fm3 == 0x7ffff8 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7d72ea27; op2val:0x186e525;
op3val:0x3ffffff8; valaddr_reg:x3; val_offset:9471*0 + 3*84*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 9471*0 + 3*85*FLEN/8, x4, x1, x2)

inst_3158:
// fs1 == 0 and fe1 == 0xfa and fm1 == 0x72ea27 and fs2 == 0 and fe2 == 0x03 and fm2 == 0x06e525 and fs3 == 0 and fe3 == 0x7f and fm3 == 0x7ffffc and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7d72ea27; op2val:0x186e525;
op3val:0x3ffffffc; valaddr_reg:x3; val_offset:9474*0 + 3*85*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 9474*0 + 3*86*FLEN/8, x4, x1, x2)

inst_3159:
// fs1 == 0 and fe1 == 0xfa and fm1 == 0x72ea27 and fs2 == 0 and fe2 == 0x03 and fm2 == 0x06e525 and fs3 == 0 and fe3 == 0x7f and fm3 == 0x7ffffe and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7d72ea27; op2val:0x186e525;
op3val:0x3ffffffe; valaddr_reg:x3; val_offset:9477*0 + 3*86*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 9477*0 + 3*87*FLEN/8, x4, x1, x2)

inst_3160:
// fs1 == 0 and fe1 == 0xfa and fm1 == 0x72ea27 and fs2 == 0 and fe2 == 0x03 and fm2 == 0x06e525 and fs3 == 0 and fe3 == 0x9e and fm3 == 0x000000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7d72ea27; op2val:0x186e525;
op3val:0x4f000000; valaddr_reg:x3; val_offset:9480*0 + 3*87*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 9480*0 + 3*88*FLEN/8, x4, x1, x2)

inst_3161:
// fs1 == 0 and fe1 == 0xfa and fm1 == 0x72ea27 and fs2 == 0 and fe2 == 0x03 and fm2 == 0x06e525 and fs3 == 0 and fe3 == 0x9e and fm3 == 0x000001 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7d72ea27; op2val:0x186e525;
op3val:0x4f000001; valaddr_reg:x3; val_offset:9483*0 + 3*88*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 9483*0 + 3*89*FLEN/8, x4, x1, x2)

inst_3162:
// fs1 == 0 and fe1 == 0xfa and fm1 == 0x72ea27 and fs2 == 0 and fe2 == 0x03 and fm2 == 0x06e525 and fs3 == 0 and fe3 == 0x9e and fm3 == 0x000003 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7d72ea27; op2val:0x186e525;
op3val:0x4f000003; valaddr_reg:x3; val_offset:9486*0 + 3*89*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 9486*0 + 3*90*FLEN/8, x4, x1, x2)

inst_3163:
// fs1 == 0 and fe1 == 0xfa and fm1 == 0x72ea27 and fs2 == 0 and fe2 == 0x03 and fm2 == 0x06e525 and fs3 == 0 and fe3 == 0x9e and fm3 == 0x000007 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7d72ea27; op2val:0x186e525;
op3val:0x4f000007; valaddr_reg:x3; val_offset:9489*0 + 3*90*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 9489*0 + 3*91*FLEN/8, x4, x1, x2)

inst_3164:
// fs1 == 0 and fe1 == 0xfa and fm1 == 0x72ea27 and fs2 == 0 and fe2 == 0x03 and fm2 == 0x06e525 and fs3 == 0 and fe3 == 0x9e and fm3 == 0x00000f and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7d72ea27; op2val:0x186e525;
op3val:0x4f00000f; valaddr_reg:x3; val_offset:9492*0 + 3*91*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 9492*0 + 3*92*FLEN/8, x4, x1, x2)

inst_3165:
// fs1 == 0 and fe1 == 0xfa and fm1 == 0x72ea27 and fs2 == 0 and fe2 == 0x03 and fm2 == 0x06e525 and fs3 == 0 and fe3 == 0x9e and fm3 == 0x00001f and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7d72ea27; op2val:0x186e525;
op3val:0x4f00001f; valaddr_reg:x3; val_offset:9495*0 + 3*92*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 9495*0 + 3*93*FLEN/8, x4, x1, x2)

inst_3166:
// fs1 == 0 and fe1 == 0xfa and fm1 == 0x72ea27 and fs2 == 0 and fe2 == 0x03 and fm2 == 0x06e525 and fs3 == 0 and fe3 == 0x9e and fm3 == 0x00003f and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7d72ea27; op2val:0x186e525;
op3val:0x4f00003f; valaddr_reg:x3; val_offset:9498*0 + 3*93*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 9498*0 + 3*94*FLEN/8, x4, x1, x2)

inst_3167:
// fs1 == 0 and fe1 == 0xfa and fm1 == 0x72ea27 and fs2 == 0 and fe2 == 0x03 and fm2 == 0x06e525 and fs3 == 0 and fe3 == 0x9e and fm3 == 0x00007f and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7d72ea27; op2val:0x186e525;
op3val:0x4f00007f; valaddr_reg:x3; val_offset:9501*0 + 3*94*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 9501*0 + 3*95*FLEN/8, x4, x1, x2)

inst_3168:
// fs1 == 0 and fe1 == 0xfa and fm1 == 0x72ea27 and fs2 == 0 and fe2 == 0x03 and fm2 == 0x06e525 and fs3 == 0 and fe3 == 0x9e and fm3 == 0x0000ff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7d72ea27; op2val:0x186e525;
op3val:0x4f0000ff; valaddr_reg:x3; val_offset:9504*0 + 3*95*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 9504*0 + 3*96*FLEN/8, x4, x1, x2)

inst_3169:
// fs1 == 0 and fe1 == 0xfa and fm1 == 0x72ea27 and fs2 == 0 and fe2 == 0x03 and fm2 == 0x06e525 and fs3 == 0 and fe3 == 0x9e and fm3 == 0x0001ff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7d72ea27; op2val:0x186e525;
op3val:0x4f0001ff; valaddr_reg:x3; val_offset:9507*0 + 3*96*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 9507*0 + 3*97*FLEN/8, x4, x1, x2)

inst_3170:
// fs1 == 0 and fe1 == 0xfa and fm1 == 0x72ea27 and fs2 == 0 and fe2 == 0x03 and fm2 == 0x06e525 and fs3 == 0 and fe3 == 0x9e and fm3 == 0x0003ff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7d72ea27; op2val:0x186e525;
op3val:0x4f0003ff; valaddr_reg:x3; val_offset:9510*0 + 3*97*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 9510*0 + 3*98*FLEN/8, x4, x1, x2)

inst_3171:
// fs1 == 0 and fe1 == 0xfa and fm1 == 0x72ea27 and fs2 == 0 and fe2 == 0x03 and fm2 == 0x06e525 and fs3 == 0 and fe3 == 0x9e and fm3 == 0x0007ff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7d72ea27; op2val:0x186e525;
op3val:0x4f0007ff; valaddr_reg:x3; val_offset:9513*0 + 3*98*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 9513*0 + 3*99*FLEN/8, x4, x1, x2)

inst_3172:
// fs1 == 0 and fe1 == 0xfa and fm1 == 0x72ea27 and fs2 == 0 and fe2 == 0x03 and fm2 == 0x06e525 and fs3 == 0 and fe3 == 0x9e and fm3 == 0x000fff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7d72ea27; op2val:0x186e525;
op3val:0x4f000fff; valaddr_reg:x3; val_offset:9516*0 + 3*99*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 9516*0 + 3*100*FLEN/8, x4, x1, x2)

inst_3173:
// fs1 == 0 and fe1 == 0xfa and fm1 == 0x72ea27 and fs2 == 0 and fe2 == 0x03 and fm2 == 0x06e525 and fs3 == 0 and fe3 == 0x9e and fm3 == 0x001fff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7d72ea27; op2val:0x186e525;
op3val:0x4f001fff; valaddr_reg:x3; val_offset:9519*0 + 3*100*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 9519*0 + 3*101*FLEN/8, x4, x1, x2)

inst_3174:
// fs1 == 0 and fe1 == 0xfa and fm1 == 0x72ea27 and fs2 == 0 and fe2 == 0x03 and fm2 == 0x06e525 and fs3 == 0 and fe3 == 0x9e and fm3 == 0x003fff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7d72ea27; op2val:0x186e525;
op3val:0x4f003fff; valaddr_reg:x3; val_offset:9522*0 + 3*101*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 9522*0 + 3*102*FLEN/8, x4, x1, x2)

inst_3175:
// fs1 == 0 and fe1 == 0xfa and fm1 == 0x72ea27 and fs2 == 0 and fe2 == 0x03 and fm2 == 0x06e525 and fs3 == 0 and fe3 == 0x9e and fm3 == 0x007fff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7d72ea27; op2val:0x186e525;
op3val:0x4f007fff; valaddr_reg:x3; val_offset:9525*0 + 3*102*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 9525*0 + 3*103*FLEN/8, x4, x1, x2)

inst_3176:
// fs1 == 0 and fe1 == 0xfa and fm1 == 0x72ea27 and fs2 == 0 and fe2 == 0x03 and fm2 == 0x06e525 and fs3 == 0 and fe3 == 0x9e and fm3 == 0x00ffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7d72ea27; op2val:0x186e525;
op3val:0x4f00ffff; valaddr_reg:x3; val_offset:9528*0 + 3*103*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 9528*0 + 3*104*FLEN/8, x4, x1, x2)

inst_3177:
// fs1 == 0 and fe1 == 0xfa and fm1 == 0x72ea27 and fs2 == 0 and fe2 == 0x03 and fm2 == 0x06e525 and fs3 == 0 and fe3 == 0x9e and fm3 == 0x01ffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7d72ea27; op2val:0x186e525;
op3val:0x4f01ffff; valaddr_reg:x3; val_offset:9531*0 + 3*104*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 9531*0 + 3*105*FLEN/8, x4, x1, x2)

inst_3178:
// fs1 == 0 and fe1 == 0xfa and fm1 == 0x72ea27 and fs2 == 0 and fe2 == 0x03 and fm2 == 0x06e525 and fs3 == 0 and fe3 == 0x9e and fm3 == 0x03ffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7d72ea27; op2val:0x186e525;
op3val:0x4f03ffff; valaddr_reg:x3; val_offset:9534*0 + 3*105*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 9534*0 + 3*106*FLEN/8, x4, x1, x2)

inst_3179:
// fs1 == 0 and fe1 == 0xfa and fm1 == 0x72ea27 and fs2 == 0 and fe2 == 0x03 and fm2 == 0x06e525 and fs3 == 0 and fe3 == 0x9e and fm3 == 0x07ffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7d72ea27; op2val:0x186e525;
op3val:0x4f07ffff; valaddr_reg:x3; val_offset:9537*0 + 3*106*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 9537*0 + 3*107*FLEN/8, x4, x1, x2)

inst_3180:
// fs1 == 0 and fe1 == 0xfa and fm1 == 0x72ea27 and fs2 == 0 and fe2 == 0x03 and fm2 == 0x06e525 and fs3 == 0 and fe3 == 0x9e and fm3 == 0x0fffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7d72ea27; op2val:0x186e525;
op3val:0x4f0fffff; valaddr_reg:x3; val_offset:9540*0 + 3*107*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 9540*0 + 3*108*FLEN/8, x4, x1, x2)

inst_3181:
// fs1 == 0 and fe1 == 0xfa and fm1 == 0x72ea27 and fs2 == 0 and fe2 == 0x03 and fm2 == 0x06e525 and fs3 == 0 and fe3 == 0x9e and fm3 == 0x1fffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7d72ea27; op2val:0x186e525;
op3val:0x4f1fffff; valaddr_reg:x3; val_offset:9543*0 + 3*108*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 9543*0 + 3*109*FLEN/8, x4, x1, x2)

inst_3182:
// fs1 == 0 and fe1 == 0xfa and fm1 == 0x72ea27 and fs2 == 0 and fe2 == 0x03 and fm2 == 0x06e525 and fs3 == 0 and fe3 == 0x9e and fm3 == 0x3fffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7d72ea27; op2val:0x186e525;
op3val:0x4f3fffff; valaddr_reg:x3; val_offset:9546*0 + 3*109*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 9546*0 + 3*110*FLEN/8, x4, x1, x2)

inst_3183:
// fs1 == 0 and fe1 == 0xfa and fm1 == 0x72ea27 and fs2 == 0 and fe2 == 0x03 and fm2 == 0x06e525 and fs3 == 0 and fe3 == 0x9e and fm3 == 0x400000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7d72ea27; op2val:0x186e525;
op3val:0x4f400000; valaddr_reg:x3; val_offset:9549*0 + 3*110*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 9549*0 + 3*111*FLEN/8, x4, x1, x2)

inst_3184:
// fs1 == 0 and fe1 == 0xfa and fm1 == 0x72ea27 and fs2 == 0 and fe2 == 0x03 and fm2 == 0x06e525 and fs3 == 0 and fe3 == 0x9e and fm3 == 0x600000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7d72ea27; op2val:0x186e525;
op3val:0x4f600000; valaddr_reg:x3; val_offset:9552*0 + 3*111*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 9552*0 + 3*112*FLEN/8, x4, x1, x2)

inst_3185:
// fs1 == 0 and fe1 == 0xfa and fm1 == 0x72ea27 and fs2 == 0 and fe2 == 0x03 and fm2 == 0x06e525 and fs3 == 0 and fe3 == 0x9e and fm3 == 0x700000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7d72ea27; op2val:0x186e525;
op3val:0x4f700000; valaddr_reg:x3; val_offset:9555*0 + 3*112*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 9555*0 + 3*113*FLEN/8, x4, x1, x2)

inst_3186:
// fs1 == 0 and fe1 == 0xfa and fm1 == 0x72ea27 and fs2 == 0 and fe2 == 0x03 and fm2 == 0x06e525 and fs3 == 0 and fe3 == 0x9e and fm3 == 0x780000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7d72ea27; op2val:0x186e525;
op3val:0x4f780000; valaddr_reg:x3; val_offset:9558*0 + 3*113*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 9558*0 + 3*114*FLEN/8, x4, x1, x2)

inst_3187:
// fs1 == 0 and fe1 == 0xfa and fm1 == 0x72ea27 and fs2 == 0 and fe2 == 0x03 and fm2 == 0x06e525 and fs3 == 0 and fe3 == 0x9e and fm3 == 0x7c0000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7d72ea27; op2val:0x186e525;
op3val:0x4f7c0000; valaddr_reg:x3; val_offset:9561*0 + 3*114*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 9561*0 + 3*115*FLEN/8, x4, x1, x2)

inst_3188:
// fs1 == 0 and fe1 == 0xfa and fm1 == 0x72ea27 and fs2 == 0 and fe2 == 0x03 and fm2 == 0x06e525 and fs3 == 0 and fe3 == 0x9e and fm3 == 0x7e0000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7d72ea27; op2val:0x186e525;
op3val:0x4f7e0000; valaddr_reg:x3; val_offset:9564*0 + 3*115*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 9564*0 + 3*116*FLEN/8, x4, x1, x2)

inst_3189:
// fs1 == 0 and fe1 == 0xfa and fm1 == 0x72ea27 and fs2 == 0 and fe2 == 0x03 and fm2 == 0x06e525 and fs3 == 0 and fe3 == 0x9e and fm3 == 0x7f0000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7d72ea27; op2val:0x186e525;
op3val:0x4f7f0000; valaddr_reg:x3; val_offset:9567*0 + 3*116*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 9567*0 + 3*117*FLEN/8, x4, x1, x2)

inst_3190:
// fs1 == 0 and fe1 == 0xfa and fm1 == 0x72ea27 and fs2 == 0 and fe2 == 0x03 and fm2 == 0x06e525 and fs3 == 0 and fe3 == 0x9e and fm3 == 0x7f8000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7d72ea27; op2val:0x186e525;
op3val:0x4f7f8000; valaddr_reg:x3; val_offset:9570*0 + 3*117*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 9570*0 + 3*118*FLEN/8, x4, x1, x2)

inst_3191:
// fs1 == 0 and fe1 == 0xfa and fm1 == 0x72ea27 and fs2 == 0 and fe2 == 0x03 and fm2 == 0x06e525 and fs3 == 0 and fe3 == 0x9e and fm3 == 0x7fc000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7d72ea27; op2val:0x186e525;
op3val:0x4f7fc000; valaddr_reg:x3; val_offset:9573*0 + 3*118*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 9573*0 + 3*119*FLEN/8, x4, x1, x2)

inst_3192:
// fs1 == 0 and fe1 == 0xfa and fm1 == 0x72ea27 and fs2 == 0 and fe2 == 0x03 and fm2 == 0x06e525 and fs3 == 0 and fe3 == 0x9e and fm3 == 0x7fe000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7d72ea27; op2val:0x186e525;
op3val:0x4f7fe000; valaddr_reg:x3; val_offset:9576*0 + 3*119*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 9576*0 + 3*120*FLEN/8, x4, x1, x2)

inst_3193:
// fs1 == 0 and fe1 == 0xfa and fm1 == 0x72ea27 and fs2 == 0 and fe2 == 0x03 and fm2 == 0x06e525 and fs3 == 0 and fe3 == 0x9e and fm3 == 0x7ff000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7d72ea27; op2val:0x186e525;
op3val:0x4f7ff000; valaddr_reg:x3; val_offset:9579*0 + 3*120*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 9579*0 + 3*121*FLEN/8, x4, x1, x2)

inst_3194:
// fs1 == 0 and fe1 == 0xfa and fm1 == 0x72ea27 and fs2 == 0 and fe2 == 0x03 and fm2 == 0x06e525 and fs3 == 0 and fe3 == 0x9e and fm3 == 0x7ff800 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7d72ea27; op2val:0x186e525;
op3val:0x4f7ff800; valaddr_reg:x3; val_offset:9582*0 + 3*121*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 9582*0 + 3*122*FLEN/8, x4, x1, x2)

inst_3195:
// fs1 == 0 and fe1 == 0xfa and fm1 == 0x72ea27 and fs2 == 0 and fe2 == 0x03 and fm2 == 0x06e525 and fs3 == 0 and fe3 == 0x9e and fm3 == 0x7ffc00 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7d72ea27; op2val:0x186e525;
op3val:0x4f7ffc00; valaddr_reg:x3; val_offset:9585*0 + 3*122*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 9585*0 + 3*123*FLEN/8, x4, x1, x2)

inst_3196:
// fs1 == 0 and fe1 == 0xfa and fm1 == 0x72ea27 and fs2 == 0 and fe2 == 0x03 and fm2 == 0x06e525 and fs3 == 0 and fe3 == 0x9e and fm3 == 0x7ffe00 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7d72ea27; op2val:0x186e525;
op3val:0x4f7ffe00; valaddr_reg:x3; val_offset:9588*0 + 3*123*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 9588*0 + 3*124*FLEN/8, x4, x1, x2)

inst_3197:
// fs1 == 0 and fe1 == 0xfa and fm1 == 0x72ea27 and fs2 == 0 and fe2 == 0x03 and fm2 == 0x06e525 and fs3 == 0 and fe3 == 0x9e and fm3 == 0x7fff00 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7d72ea27; op2val:0x186e525;
op3val:0x4f7fff00; valaddr_reg:x3; val_offset:9591*0 + 3*124*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 9591*0 + 3*125*FLEN/8, x4, x1, x2)

inst_3198:
// fs1 == 0 and fe1 == 0xfa and fm1 == 0x72ea27 and fs2 == 0 and fe2 == 0x03 and fm2 == 0x06e525 and fs3 == 0 and fe3 == 0x9e and fm3 == 0x7fff80 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7d72ea27; op2val:0x186e525;
op3val:0x4f7fff80; valaddr_reg:x3; val_offset:9594*0 + 3*125*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 9594*0 + 3*126*FLEN/8, x4, x1, x2)

inst_3199:
// fs1 == 0 and fe1 == 0xfa and fm1 == 0x72ea27 and fs2 == 0 and fe2 == 0x03 and fm2 == 0x06e525 and fs3 == 0 and fe3 == 0x9e and fm3 == 0x7fffc0 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7d72ea27; op2val:0x186e525;
op3val:0x4f7fffc0; valaddr_reg:x3; val_offset:9597*0 + 3*126*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 9597*0 + 3*127*FLEN/8, x4, x1, x2)
RVTEST_SIGBASE(x1,signature_x1_2)

inst_3200:
// fs1 == 0 and fe1 == 0xfa and fm1 == 0x72ea27 and fs2 == 0 and fe2 == 0x03 and fm2 == 0x06e525 and fs3 == 0 and fe3 == 0x9e and fm3 == 0x7fffe0 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7d72ea27; op2val:0x186e525;
op3val:0x4f7fffe0; valaddr_reg:x3; val_offset:9600*0 + 3*127*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 9600*0 + 3*128*FLEN/8, x4, x1, x2)

inst_3201:
// fs1 == 0 and fe1 == 0xfa and fm1 == 0x72ea27 and fs2 == 0 and fe2 == 0x03 and fm2 == 0x06e525 and fs3 == 0 and fe3 == 0x9e and fm3 == 0x7ffff0 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7d72ea27; op2val:0x186e525;
op3val:0x4f7ffff0; valaddr_reg:x3; val_offset:9603*0 + 3*128*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 9603*0 + 3*129*FLEN/8, x4, x1, x2)

inst_3202:
// fs1 == 0 and fe1 == 0xfa and fm1 == 0x72ea27 and fs2 == 0 and fe2 == 0x03 and fm2 == 0x06e525 and fs3 == 0 and fe3 == 0x9e and fm3 == 0x7ffff8 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7d72ea27; op2val:0x186e525;
op3val:0x4f7ffff8; valaddr_reg:x3; val_offset:9606*0 + 3*129*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 9606*0 + 3*130*FLEN/8, x4, x1, x2)

inst_3203:
// fs1 == 0 and fe1 == 0xfa and fm1 == 0x72ea27 and fs2 == 0 and fe2 == 0x03 and fm2 == 0x06e525 and fs3 == 0 and fe3 == 0x9e and fm3 == 0x7ffffc and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7d72ea27; op2val:0x186e525;
op3val:0x4f7ffffc; valaddr_reg:x3; val_offset:9609*0 + 3*130*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 9609*0 + 3*131*FLEN/8, x4, x1, x2)

inst_3204:
// fs1 == 0 and fe1 == 0xfa and fm1 == 0x72ea27 and fs2 == 0 and fe2 == 0x03 and fm2 == 0x06e525 and fs3 == 0 and fe3 == 0x9e and fm3 == 0x7ffffe and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7d72ea27; op2val:0x186e525;
op3val:0x4f7ffffe; valaddr_reg:x3; val_offset:9612*0 + 3*131*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 9612*0 + 3*132*FLEN/8, x4, x1, x2)

inst_3205:
// fs1 == 0 and fe1 == 0xfa and fm1 == 0x72ea27 and fs2 == 0 and fe2 == 0x03 and fm2 == 0x06e525 and fs3 == 0 and fe3 == 0x9e and fm3 == 0x7fffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7d72ea27; op2val:0x186e525;
op3val:0x4f7fffff; valaddr_reg:x3; val_offset:9615*0 + 3*132*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 9615*0 + 3*133*FLEN/8, x4, x1, x2)

inst_3206:
// fs1 == 0 and fe1 == 0xfa and fm1 == 0x7685d7 and fs2 == 0 and fe2 == 0x03 and fm2 == 0x04ebb6 and fs3 == 0 and fe3 == 0x43 and fm3 == 0x000000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7d7685d7; op2val:0x184ebb6;
op3val:0x21800000; valaddr_reg:x3; val_offset:9618*0 + 3*133*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 9618*0 + 3*134*FLEN/8, x4, x1, x2)

inst_3207:
// fs1 == 0 and fe1 == 0xfa and fm1 == 0x7685d7 and fs2 == 0 and fe2 == 0x03 and fm2 == 0x04ebb6 and fs3 == 0 and fe3 == 0x43 and fm3 == 0x000001 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7d7685d7; op2val:0x184ebb6;
op3val:0x21800001; valaddr_reg:x3; val_offset:9621*0 + 3*134*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 9621*0 + 3*135*FLEN/8, x4, x1, x2)

inst_3208:
// fs1 == 0 and fe1 == 0xfa and fm1 == 0x7685d7 and fs2 == 0 and fe2 == 0x03 and fm2 == 0x04ebb6 and fs3 == 0 and fe3 == 0x43 and fm3 == 0x000003 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7d7685d7; op2val:0x184ebb6;
op3val:0x21800003; valaddr_reg:x3; val_offset:9624*0 + 3*135*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 9624*0 + 3*136*FLEN/8, x4, x1, x2)

inst_3209:
// fs1 == 0 and fe1 == 0xfa and fm1 == 0x7685d7 and fs2 == 0 and fe2 == 0x03 and fm2 == 0x04ebb6 and fs3 == 0 and fe3 == 0x43 and fm3 == 0x000007 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7d7685d7; op2val:0x184ebb6;
op3val:0x21800007; valaddr_reg:x3; val_offset:9627*0 + 3*136*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 9627*0 + 3*137*FLEN/8, x4, x1, x2)

inst_3210:
// fs1 == 0 and fe1 == 0xfa and fm1 == 0x7685d7 and fs2 == 0 and fe2 == 0x03 and fm2 == 0x04ebb6 and fs3 == 0 and fe3 == 0x43 and fm3 == 0x00000f and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7d7685d7; op2val:0x184ebb6;
op3val:0x2180000f; valaddr_reg:x3; val_offset:9630*0 + 3*137*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 9630*0 + 3*138*FLEN/8, x4, x1, x2)

inst_3211:
// fs1 == 0 and fe1 == 0xfa and fm1 == 0x7685d7 and fs2 == 0 and fe2 == 0x03 and fm2 == 0x04ebb6 and fs3 == 0 and fe3 == 0x43 and fm3 == 0x00001f and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7d7685d7; op2val:0x184ebb6;
op3val:0x2180001f; valaddr_reg:x3; val_offset:9633*0 + 3*138*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 9633*0 + 3*139*FLEN/8, x4, x1, x2)

inst_3212:
// fs1 == 0 and fe1 == 0xfa and fm1 == 0x7685d7 and fs2 == 0 and fe2 == 0x03 and fm2 == 0x04ebb6 and fs3 == 0 and fe3 == 0x43 and fm3 == 0x00003f and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7d7685d7; op2val:0x184ebb6;
op3val:0x2180003f; valaddr_reg:x3; val_offset:9636*0 + 3*139*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 9636*0 + 3*140*FLEN/8, x4, x1, x2)

inst_3213:
// fs1 == 0 and fe1 == 0xfa and fm1 == 0x7685d7 and fs2 == 0 and fe2 == 0x03 and fm2 == 0x04ebb6 and fs3 == 0 and fe3 == 0x43 and fm3 == 0x00007f and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7d7685d7; op2val:0x184ebb6;
op3val:0x2180007f; valaddr_reg:x3; val_offset:9639*0 + 3*140*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 9639*0 + 3*141*FLEN/8, x4, x1, x2)

inst_3214:
// fs1 == 0 and fe1 == 0xfa and fm1 == 0x7685d7 and fs2 == 0 and fe2 == 0x03 and fm2 == 0x04ebb6 and fs3 == 0 and fe3 == 0x43 and fm3 == 0x0000ff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7d7685d7; op2val:0x184ebb6;
op3val:0x218000ff; valaddr_reg:x3; val_offset:9642*0 + 3*141*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 9642*0 + 3*142*FLEN/8, x4, x1, x2)

inst_3215:
// fs1 == 0 and fe1 == 0xfa and fm1 == 0x7685d7 and fs2 == 0 and fe2 == 0x03 and fm2 == 0x04ebb6 and fs3 == 0 and fe3 == 0x43 and fm3 == 0x0001ff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7d7685d7; op2val:0x184ebb6;
op3val:0x218001ff; valaddr_reg:x3; val_offset:9645*0 + 3*142*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 9645*0 + 3*143*FLEN/8, x4, x1, x2)

inst_3216:
// fs1 == 0 and fe1 == 0xfa and fm1 == 0x7685d7 and fs2 == 0 and fe2 == 0x03 and fm2 == 0x04ebb6 and fs3 == 0 and fe3 == 0x43 and fm3 == 0x0003ff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7d7685d7; op2val:0x184ebb6;
op3val:0x218003ff; valaddr_reg:x3; val_offset:9648*0 + 3*143*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 9648*0 + 3*144*FLEN/8, x4, x1, x2)

inst_3217:
// fs1 == 0 and fe1 == 0xfa and fm1 == 0x7685d7 and fs2 == 0 and fe2 == 0x03 and fm2 == 0x04ebb6 and fs3 == 0 and fe3 == 0x43 and fm3 == 0x0007ff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7d7685d7; op2val:0x184ebb6;
op3val:0x218007ff; valaddr_reg:x3; val_offset:9651*0 + 3*144*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 9651*0 + 3*145*FLEN/8, x4, x1, x2)

inst_3218:
// fs1 == 0 and fe1 == 0xfa and fm1 == 0x7685d7 and fs2 == 0 and fe2 == 0x03 and fm2 == 0x04ebb6 and fs3 == 0 and fe3 == 0x43 and fm3 == 0x000fff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7d7685d7; op2val:0x184ebb6;
op3val:0x21800fff; valaddr_reg:x3; val_offset:9654*0 + 3*145*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 9654*0 + 3*146*FLEN/8, x4, x1, x2)

inst_3219:
// fs1 == 0 and fe1 == 0xfa and fm1 == 0x7685d7 and fs2 == 0 and fe2 == 0x03 and fm2 == 0x04ebb6 and fs3 == 0 and fe3 == 0x43 and fm3 == 0x001fff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7d7685d7; op2val:0x184ebb6;
op3val:0x21801fff; valaddr_reg:x3; val_offset:9657*0 + 3*146*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 9657*0 + 3*147*FLEN/8, x4, x1, x2)

inst_3220:
// fs1 == 0 and fe1 == 0xfa and fm1 == 0x7685d7 and fs2 == 0 and fe2 == 0x03 and fm2 == 0x04ebb6 and fs3 == 0 and fe3 == 0x43 and fm3 == 0x003fff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7d7685d7; op2val:0x184ebb6;
op3val:0x21803fff; valaddr_reg:x3; val_offset:9660*0 + 3*147*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 9660*0 + 3*148*FLEN/8, x4, x1, x2)

inst_3221:
// fs1 == 0 and fe1 == 0xfa and fm1 == 0x7685d7 and fs2 == 0 and fe2 == 0x03 and fm2 == 0x04ebb6 and fs3 == 0 and fe3 == 0x43 and fm3 == 0x007fff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7d7685d7; op2val:0x184ebb6;
op3val:0x21807fff; valaddr_reg:x3; val_offset:9663*0 + 3*148*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 9663*0 + 3*149*FLEN/8, x4, x1, x2)

inst_3222:
// fs1 == 0 and fe1 == 0xfa and fm1 == 0x7685d7 and fs2 == 0 and fe2 == 0x03 and fm2 == 0x04ebb6 and fs3 == 0 and fe3 == 0x43 and fm3 == 0x00ffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7d7685d7; op2val:0x184ebb6;
op3val:0x2180ffff; valaddr_reg:x3; val_offset:9666*0 + 3*149*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 9666*0 + 3*150*FLEN/8, x4, x1, x2)

inst_3223:
// fs1 == 0 and fe1 == 0xfa and fm1 == 0x7685d7 and fs2 == 0 and fe2 == 0x03 and fm2 == 0x04ebb6 and fs3 == 0 and fe3 == 0x43 and fm3 == 0x01ffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7d7685d7; op2val:0x184ebb6;
op3val:0x2181ffff; valaddr_reg:x3; val_offset:9669*0 + 3*150*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 9669*0 + 3*151*FLEN/8, x4, x1, x2)

inst_3224:
// fs1 == 0 and fe1 == 0xfa and fm1 == 0x7685d7 and fs2 == 0 and fe2 == 0x03 and fm2 == 0x04ebb6 and fs3 == 0 and fe3 == 0x43 and fm3 == 0x03ffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7d7685d7; op2val:0x184ebb6;
op3val:0x2183ffff; valaddr_reg:x3; val_offset:9672*0 + 3*151*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 9672*0 + 3*152*FLEN/8, x4, x1, x2)

inst_3225:
// fs1 == 0 and fe1 == 0xfa and fm1 == 0x7685d7 and fs2 == 0 and fe2 == 0x03 and fm2 == 0x04ebb6 and fs3 == 0 and fe3 == 0x43 and fm3 == 0x07ffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7d7685d7; op2val:0x184ebb6;
op3val:0x2187ffff; valaddr_reg:x3; val_offset:9675*0 + 3*152*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 9675*0 + 3*153*FLEN/8, x4, x1, x2)

inst_3226:
// fs1 == 0 and fe1 == 0xfa and fm1 == 0x7685d7 and fs2 == 0 and fe2 == 0x03 and fm2 == 0x04ebb6 and fs3 == 0 and fe3 == 0x43 and fm3 == 0x0fffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7d7685d7; op2val:0x184ebb6;
op3val:0x218fffff; valaddr_reg:x3; val_offset:9678*0 + 3*153*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 9678*0 + 3*154*FLEN/8, x4, x1, x2)

inst_3227:
// fs1 == 0 and fe1 == 0xfa and fm1 == 0x7685d7 and fs2 == 0 and fe2 == 0x03 and fm2 == 0x04ebb6 and fs3 == 0 and fe3 == 0x43 and fm3 == 0x1fffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7d7685d7; op2val:0x184ebb6;
op3val:0x219fffff; valaddr_reg:x3; val_offset:9681*0 + 3*154*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 9681*0 + 3*155*FLEN/8, x4, x1, x2)

inst_3228:
// fs1 == 0 and fe1 == 0xfa and fm1 == 0x7685d7 and fs2 == 0 and fe2 == 0x03 and fm2 == 0x04ebb6 and fs3 == 0 and fe3 == 0x43 and fm3 == 0x3fffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7d7685d7; op2val:0x184ebb6;
op3val:0x21bfffff; valaddr_reg:x3; val_offset:9684*0 + 3*155*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 9684*0 + 3*156*FLEN/8, x4, x1, x2)

inst_3229:
// fs1 == 0 and fe1 == 0xfa and fm1 == 0x7685d7 and fs2 == 0 and fe2 == 0x03 and fm2 == 0x04ebb6 and fs3 == 0 and fe3 == 0x43 and fm3 == 0x400000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7d7685d7; op2val:0x184ebb6;
op3val:0x21c00000; valaddr_reg:x3; val_offset:9687*0 + 3*156*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 9687*0 + 3*157*FLEN/8, x4, x1, x2)

inst_3230:
// fs1 == 0 and fe1 == 0xfa and fm1 == 0x7685d7 and fs2 == 0 and fe2 == 0x03 and fm2 == 0x04ebb6 and fs3 == 0 and fe3 == 0x43 and fm3 == 0x600000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7d7685d7; op2val:0x184ebb6;
op3val:0x21e00000; valaddr_reg:x3; val_offset:9690*0 + 3*157*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 9690*0 + 3*158*FLEN/8, x4, x1, x2)

inst_3231:
// fs1 == 0 and fe1 == 0xfa and fm1 == 0x7685d7 and fs2 == 0 and fe2 == 0x03 and fm2 == 0x04ebb6 and fs3 == 0 and fe3 == 0x43 and fm3 == 0x700000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7d7685d7; op2val:0x184ebb6;
op3val:0x21f00000; valaddr_reg:x3; val_offset:9693*0 + 3*158*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 9693*0 + 3*159*FLEN/8, x4, x1, x2)

inst_3232:
// fs1 == 0 and fe1 == 0xfa and fm1 == 0x7685d7 and fs2 == 0 and fe2 == 0x03 and fm2 == 0x04ebb6 and fs3 == 0 and fe3 == 0x43 and fm3 == 0x780000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7d7685d7; op2val:0x184ebb6;
op3val:0x21f80000; valaddr_reg:x3; val_offset:9696*0 + 3*159*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 9696*0 + 3*160*FLEN/8, x4, x1, x2)

inst_3233:
// fs1 == 0 and fe1 == 0xfa and fm1 == 0x7685d7 and fs2 == 0 and fe2 == 0x03 and fm2 == 0x04ebb6 and fs3 == 0 and fe3 == 0x43 and fm3 == 0x7c0000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7d7685d7; op2val:0x184ebb6;
op3val:0x21fc0000; valaddr_reg:x3; val_offset:9699*0 + 3*160*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 9699*0 + 3*161*FLEN/8, x4, x1, x2)

inst_3234:
// fs1 == 0 and fe1 == 0xfa and fm1 == 0x7685d7 and fs2 == 0 and fe2 == 0x03 and fm2 == 0x04ebb6 and fs3 == 0 and fe3 == 0x43 and fm3 == 0x7e0000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7d7685d7; op2val:0x184ebb6;
op3val:0x21fe0000; valaddr_reg:x3; val_offset:9702*0 + 3*161*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 9702*0 + 3*162*FLEN/8, x4, x1, x2)

inst_3235:
// fs1 == 0 and fe1 == 0xfa and fm1 == 0x7685d7 and fs2 == 0 and fe2 == 0x03 and fm2 == 0x04ebb6 and fs3 == 0 and fe3 == 0x43 and fm3 == 0x7f0000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7d7685d7; op2val:0x184ebb6;
op3val:0x21ff0000; valaddr_reg:x3; val_offset:9705*0 + 3*162*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 9705*0 + 3*163*FLEN/8, x4, x1, x2)

inst_3236:
// fs1 == 0 and fe1 == 0xfa and fm1 == 0x7685d7 and fs2 == 0 and fe2 == 0x03 and fm2 == 0x04ebb6 and fs3 == 0 and fe3 == 0x43 and fm3 == 0x7f8000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7d7685d7; op2val:0x184ebb6;
op3val:0x21ff8000; valaddr_reg:x3; val_offset:9708*0 + 3*163*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 9708*0 + 3*164*FLEN/8, x4, x1, x2)

inst_3237:
// fs1 == 0 and fe1 == 0xfa and fm1 == 0x7685d7 and fs2 == 0 and fe2 == 0x03 and fm2 == 0x04ebb6 and fs3 == 0 and fe3 == 0x43 and fm3 == 0x7fc000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7d7685d7; op2val:0x184ebb6;
op3val:0x21ffc000; valaddr_reg:x3; val_offset:9711*0 + 3*164*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 9711*0 + 3*165*FLEN/8, x4, x1, x2)

inst_3238:
// fs1 == 0 and fe1 == 0xfa and fm1 == 0x7685d7 and fs2 == 0 and fe2 == 0x03 and fm2 == 0x04ebb6 and fs3 == 0 and fe3 == 0x43 and fm3 == 0x7fe000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7d7685d7; op2val:0x184ebb6;
op3val:0x21ffe000; valaddr_reg:x3; val_offset:9714*0 + 3*165*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 9714*0 + 3*166*FLEN/8, x4, x1, x2)

inst_3239:
// fs1 == 0 and fe1 == 0xfa and fm1 == 0x7685d7 and fs2 == 0 and fe2 == 0x03 and fm2 == 0x04ebb6 and fs3 == 0 and fe3 == 0x43 and fm3 == 0x7ff000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7d7685d7; op2val:0x184ebb6;
op3val:0x21fff000; valaddr_reg:x3; val_offset:9717*0 + 3*166*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 9717*0 + 3*167*FLEN/8, x4, x1, x2)

inst_3240:
// fs1 == 0 and fe1 == 0xfa and fm1 == 0x7685d7 and fs2 == 0 and fe2 == 0x03 and fm2 == 0x04ebb6 and fs3 == 0 and fe3 == 0x43 and fm3 == 0x7ff800 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7d7685d7; op2val:0x184ebb6;
op3val:0x21fff800; valaddr_reg:x3; val_offset:9720*0 + 3*167*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 9720*0 + 3*168*FLEN/8, x4, x1, x2)

inst_3241:
// fs1 == 0 and fe1 == 0xfa and fm1 == 0x7685d7 and fs2 == 0 and fe2 == 0x03 and fm2 == 0x04ebb6 and fs3 == 0 and fe3 == 0x43 and fm3 == 0x7ffc00 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7d7685d7; op2val:0x184ebb6;
op3val:0x21fffc00; valaddr_reg:x3; val_offset:9723*0 + 3*168*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 9723*0 + 3*169*FLEN/8, x4, x1, x2)

inst_3242:
// fs1 == 0 and fe1 == 0xfa and fm1 == 0x7685d7 and fs2 == 0 and fe2 == 0x03 and fm2 == 0x04ebb6 and fs3 == 0 and fe3 == 0x43 and fm3 == 0x7ffe00 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7d7685d7; op2val:0x184ebb6;
op3val:0x21fffe00; valaddr_reg:x3; val_offset:9726*0 + 3*169*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 9726*0 + 3*170*FLEN/8, x4, x1, x2)

inst_3243:
// fs1 == 0 and fe1 == 0xfa and fm1 == 0x7685d7 and fs2 == 0 and fe2 == 0x03 and fm2 == 0x04ebb6 and fs3 == 0 and fe3 == 0x43 and fm3 == 0x7fff00 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7d7685d7; op2val:0x184ebb6;
op3val:0x21ffff00; valaddr_reg:x3; val_offset:9729*0 + 3*170*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 9729*0 + 3*171*FLEN/8, x4, x1, x2)

inst_3244:
// fs1 == 0 and fe1 == 0xfa and fm1 == 0x7685d7 and fs2 == 0 and fe2 == 0x03 and fm2 == 0x04ebb6 and fs3 == 0 and fe3 == 0x43 and fm3 == 0x7fff80 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7d7685d7; op2val:0x184ebb6;
op3val:0x21ffff80; valaddr_reg:x3; val_offset:9732*0 + 3*171*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 9732*0 + 3*172*FLEN/8, x4, x1, x2)

inst_3245:
// fs1 == 0 and fe1 == 0xfa and fm1 == 0x7685d7 and fs2 == 0 and fe2 == 0x03 and fm2 == 0x04ebb6 and fs3 == 0 and fe3 == 0x43 and fm3 == 0x7fffc0 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7d7685d7; op2val:0x184ebb6;
op3val:0x21ffffc0; valaddr_reg:x3; val_offset:9735*0 + 3*172*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 9735*0 + 3*173*FLEN/8, x4, x1, x2)

inst_3246:
// fs1 == 0 and fe1 == 0xfa and fm1 == 0x7685d7 and fs2 == 0 and fe2 == 0x03 and fm2 == 0x04ebb6 and fs3 == 0 and fe3 == 0x43 and fm3 == 0x7fffe0 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7d7685d7; op2val:0x184ebb6;
op3val:0x21ffffe0; valaddr_reg:x3; val_offset:9738*0 + 3*173*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 9738*0 + 3*174*FLEN/8, x4, x1, x2)

inst_3247:
// fs1 == 0 and fe1 == 0xfa and fm1 == 0x7685d7 and fs2 == 0 and fe2 == 0x03 and fm2 == 0x04ebb6 and fs3 == 0 and fe3 == 0x43 and fm3 == 0x7ffff0 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7d7685d7; op2val:0x184ebb6;
op3val:0x21fffff0; valaddr_reg:x3; val_offset:9741*0 + 3*174*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 9741*0 + 3*175*FLEN/8, x4, x1, x2)

inst_3248:
// fs1 == 0 and fe1 == 0xfa and fm1 == 0x7685d7 and fs2 == 0 and fe2 == 0x03 and fm2 == 0x04ebb6 and fs3 == 0 and fe3 == 0x43 and fm3 == 0x7ffff8 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7d7685d7; op2val:0x184ebb6;
op3val:0x21fffff8; valaddr_reg:x3; val_offset:9744*0 + 3*175*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 9744*0 + 3*176*FLEN/8, x4, x1, x2)

inst_3249:
// fs1 == 0 and fe1 == 0xfa and fm1 == 0x7685d7 and fs2 == 0 and fe2 == 0x03 and fm2 == 0x04ebb6 and fs3 == 0 and fe3 == 0x43 and fm3 == 0x7ffffc and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7d7685d7; op2val:0x184ebb6;
op3val:0x21fffffc; valaddr_reg:x3; val_offset:9747*0 + 3*176*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 9747*0 + 3*177*FLEN/8, x4, x1, x2)

inst_3250:
// fs1 == 0 and fe1 == 0xfa and fm1 == 0x7685d7 and fs2 == 0 and fe2 == 0x03 and fm2 == 0x04ebb6 and fs3 == 0 and fe3 == 0x43 and fm3 == 0x7ffffe and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7d7685d7; op2val:0x184ebb6;
op3val:0x21fffffe; valaddr_reg:x3; val_offset:9750*0 + 3*177*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 9750*0 + 3*178*FLEN/8, x4, x1, x2)

inst_3251:
// fs1 == 0 and fe1 == 0xfa and fm1 == 0x7685d7 and fs2 == 0 and fe2 == 0x03 and fm2 == 0x04ebb6 and fs3 == 0 and fe3 == 0x43 and fm3 == 0x7fffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7d7685d7; op2val:0x184ebb6;
op3val:0x21ffffff; valaddr_reg:x3; val_offset:9753*0 + 3*178*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 9753*0 + 3*179*FLEN/8, x4, x1, x2)

inst_3252:
// fs1 == 0 and fe1 == 0xfa and fm1 == 0x7685d7 and fs2 == 0 and fe2 == 0x03 and fm2 == 0x04ebb6 and fs3 == 0 and fe3 == 0x7f and fm3 == 0x000001 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7d7685d7; op2val:0x184ebb6;
op3val:0x3f800001; valaddr_reg:x3; val_offset:9756*0 + 3*179*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 9756*0 + 3*180*FLEN/8, x4, x1, x2)

inst_3253:
// fs1 == 0 and fe1 == 0xfa and fm1 == 0x7685d7 and fs2 == 0 and fe2 == 0x03 and fm2 == 0x04ebb6 and fs3 == 0 and fe3 == 0x7f and fm3 == 0x000003 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7d7685d7; op2val:0x184ebb6;
op3val:0x3f800003; valaddr_reg:x3; val_offset:9759*0 + 3*180*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 9759*0 + 3*181*FLEN/8, x4, x1, x2)

inst_3254:
// fs1 == 0 and fe1 == 0xfa and fm1 == 0x7685d7 and fs2 == 0 and fe2 == 0x03 and fm2 == 0x04ebb6 and fs3 == 0 and fe3 == 0x7f and fm3 == 0x000007 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7d7685d7; op2val:0x184ebb6;
op3val:0x3f800007; valaddr_reg:x3; val_offset:9762*0 + 3*181*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 9762*0 + 3*182*FLEN/8, x4, x1, x2)

inst_3255:
// fs1 == 0 and fe1 == 0xfa and fm1 == 0x7685d7 and fs2 == 0 and fe2 == 0x03 and fm2 == 0x04ebb6 and fs3 == 0 and fe3 == 0x7f and fm3 == 0x199999 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7d7685d7; op2val:0x184ebb6;
op3val:0x3f999999; valaddr_reg:x3; val_offset:9765*0 + 3*182*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 9765*0 + 3*183*FLEN/8, x4, x1, x2)

inst_3256:
// fs1 == 0 and fe1 == 0xfa and fm1 == 0x7685d7 and fs2 == 0 and fe2 == 0x03 and fm2 == 0x04ebb6 and fs3 == 0 and fe3 == 0x7f and fm3 == 0x249249 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7d7685d7; op2val:0x184ebb6;
op3val:0x3fa49249; valaddr_reg:x3; val_offset:9768*0 + 3*183*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 9768*0 + 3*184*FLEN/8, x4, x1, x2)

inst_3257:
// fs1 == 0 and fe1 == 0xfa and fm1 == 0x7685d7 and fs2 == 0 and fe2 == 0x03 and fm2 == 0x04ebb6 and fs3 == 0 and fe3 == 0x7f and fm3 == 0x333333 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7d7685d7; op2val:0x184ebb6;
op3val:0x3fb33333; valaddr_reg:x3; val_offset:9771*0 + 3*184*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 9771*0 + 3*185*FLEN/8, x4, x1, x2)

inst_3258:
// fs1 == 0 and fe1 == 0xfa and fm1 == 0x7685d7 and fs2 == 0 and fe2 == 0x03 and fm2 == 0x04ebb6 and fs3 == 0 and fe3 == 0x7f and fm3 == 0x36db6d and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7d7685d7; op2val:0x184ebb6;
op3val:0x3fb6db6d; valaddr_reg:x3; val_offset:9774*0 + 3*185*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 9774*0 + 3*186*FLEN/8, x4, x1, x2)

inst_3259:
// fs1 == 0 and fe1 == 0xfa and fm1 == 0x7685d7 and fs2 == 0 and fe2 == 0x03 and fm2 == 0x04ebb6 and fs3 == 0 and fe3 == 0x7f and fm3 == 0x3bbbbb and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7d7685d7; op2val:0x184ebb6;
op3val:0x3fbbbbbb; valaddr_reg:x3; val_offset:9777*0 + 3*186*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 9777*0 + 3*187*FLEN/8, x4, x1, x2)

inst_3260:
// fs1 == 0 and fe1 == 0xfa and fm1 == 0x7685d7 and fs2 == 0 and fe2 == 0x03 and fm2 == 0x04ebb6 and fs3 == 0 and fe3 == 0x7f and fm3 == 0x444444 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7d7685d7; op2val:0x184ebb6;
op3val:0x3fc44444; valaddr_reg:x3; val_offset:9780*0 + 3*187*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 9780*0 + 3*188*FLEN/8, x4, x1, x2)

inst_3261:
// fs1 == 0 and fe1 == 0xfa and fm1 == 0x7685d7 and fs2 == 0 and fe2 == 0x03 and fm2 == 0x04ebb6 and fs3 == 0 and fe3 == 0x7f and fm3 == 0x4ccccc and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7d7685d7; op2val:0x184ebb6;
op3val:0x3fcccccc; valaddr_reg:x3; val_offset:9783*0 + 3*188*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 9783*0 + 3*189*FLEN/8, x4, x1, x2)

inst_3262:
// fs1 == 0 and fe1 == 0xfa and fm1 == 0x7685d7 and fs2 == 0 and fe2 == 0x03 and fm2 == 0x04ebb6 and fs3 == 0 and fe3 == 0x7f and fm3 == 0x5b6db6 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7d7685d7; op2val:0x184ebb6;
op3val:0x3fdb6db6; valaddr_reg:x3; val_offset:9786*0 + 3*189*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 9786*0 + 3*190*FLEN/8, x4, x1, x2)

inst_3263:
// fs1 == 0 and fe1 == 0xfa and fm1 == 0x7685d7 and fs2 == 0 and fe2 == 0x03 and fm2 == 0x04ebb6 and fs3 == 0 and fe3 == 0x7f and fm3 == 0x666666 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7d7685d7; op2val:0x184ebb6;
op3val:0x3fe66666; valaddr_reg:x3; val_offset:9789*0 + 3*190*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 9789*0 + 3*191*FLEN/8, x4, x1, x2)

inst_3264:
// fs1 == 0 and fe1 == 0xfa and fm1 == 0x7685d7 and fs2 == 0 and fe2 == 0x03 and fm2 == 0x04ebb6 and fs3 == 0 and fe3 == 0x7f and fm3 == 0x6db6db and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7d7685d7; op2val:0x184ebb6;
op3val:0x3fedb6db; valaddr_reg:x3; val_offset:9792*0 + 3*191*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 9792*0 + 3*192*FLEN/8, x4, x1, x2)

inst_3265:
// fs1 == 0 and fe1 == 0xfa and fm1 == 0x7685d7 and fs2 == 0 and fe2 == 0x03 and fm2 == 0x04ebb6 and fs3 == 0 and fe3 == 0x7f and fm3 == 0x7ffff8 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7d7685d7; op2val:0x184ebb6;
op3val:0x3ffffff8; valaddr_reg:x3; val_offset:9795*0 + 3*192*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 9795*0 + 3*193*FLEN/8, x4, x1, x2)

inst_3266:
// fs1 == 0 and fe1 == 0xfa and fm1 == 0x7685d7 and fs2 == 0 and fe2 == 0x03 and fm2 == 0x04ebb6 and fs3 == 0 and fe3 == 0x7f and fm3 == 0x7ffffc and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7d7685d7; op2val:0x184ebb6;
op3val:0x3ffffffc; valaddr_reg:x3; val_offset:9798*0 + 3*193*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 9798*0 + 3*194*FLEN/8, x4, x1, x2)

inst_3267:
// fs1 == 0 and fe1 == 0xfa and fm1 == 0x7685d7 and fs2 == 0 and fe2 == 0x03 and fm2 == 0x04ebb6 and fs3 == 0 and fe3 == 0x7f and fm3 == 0x7ffffe and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7d7685d7; op2val:0x184ebb6;
op3val:0x3ffffffe; valaddr_reg:x3; val_offset:9801*0 + 3*194*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 9801*0 + 3*195*FLEN/8, x4, x1, x2)

inst_3268:
// fs1 == 0 and fe1 == 0xfa and fm1 == 0x772129 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000001 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7d772129; op2val:0x80000000;
op3val:0x80000001; valaddr_reg:x3; val_offset:9804*0 + 3*195*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 9804*0 + 3*196*FLEN/8, x4, x1, x2)

inst_3269:
// fs1 == 0 and fe1 == 0xfa and fm1 == 0x772129 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000003 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7d772129; op2val:0x80000000;
op3val:0x80000003; valaddr_reg:x3; val_offset:9807*0 + 3*196*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 9807*0 + 3*197*FLEN/8, x4, x1, x2)

inst_3270:
// fs1 == 0 and fe1 == 0xfa and fm1 == 0x772129 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000007 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7d772129; op2val:0x80000000;
op3val:0x80000007; valaddr_reg:x3; val_offset:9810*0 + 3*197*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 9810*0 + 3*198*FLEN/8, x4, x1, x2)

inst_3271:
// fs1 == 0 and fe1 == 0xfa and fm1 == 0x772129 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x199999 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7d772129; op2val:0x80000000;
op3val:0x80199999; valaddr_reg:x3; val_offset:9813*0 + 3*198*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 9813*0 + 3*199*FLEN/8, x4, x1, x2)

inst_3272:
// fs1 == 0 and fe1 == 0xfa and fm1 == 0x772129 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x249249 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7d772129; op2val:0x80000000;
op3val:0x80249249; valaddr_reg:x3; val_offset:9816*0 + 3*199*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 9816*0 + 3*200*FLEN/8, x4, x1, x2)

inst_3273:
// fs1 == 0 and fe1 == 0xfa and fm1 == 0x772129 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x333333 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7d772129; op2val:0x80000000;
op3val:0x80333333; valaddr_reg:x3; val_offset:9819*0 + 3*200*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 9819*0 + 3*201*FLEN/8, x4, x1, x2)

inst_3274:
// fs1 == 0 and fe1 == 0xfa and fm1 == 0x772129 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x36db6d and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7d772129; op2val:0x80000000;
op3val:0x8036db6d; valaddr_reg:x3; val_offset:9822*0 + 3*201*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 9822*0 + 3*202*FLEN/8, x4, x1, x2)

inst_3275:
// fs1 == 0 and fe1 == 0xfa and fm1 == 0x772129 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3bbbbb and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7d772129; op2val:0x80000000;
op3val:0x803bbbbb; valaddr_reg:x3; val_offset:9825*0 + 3*202*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 9825*0 + 3*203*FLEN/8, x4, x1, x2)

inst_3276:
// fs1 == 0 and fe1 == 0xfa and fm1 == 0x772129 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x444444 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7d772129; op2val:0x80000000;
op3val:0x80444444; valaddr_reg:x3; val_offset:9828*0 + 3*203*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 9828*0 + 3*204*FLEN/8, x4, x1, x2)

inst_3277:
// fs1 == 0 and fe1 == 0xfa and fm1 == 0x772129 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x4ccccc and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7d772129; op2val:0x80000000;
op3val:0x804ccccc; valaddr_reg:x3; val_offset:9831*0 + 3*204*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 9831*0 + 3*205*FLEN/8, x4, x1, x2)

inst_3278:
// fs1 == 0 and fe1 == 0xfa and fm1 == 0x772129 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x5b6db6 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7d772129; op2val:0x80000000;
op3val:0x805b6db6; valaddr_reg:x3; val_offset:9834*0 + 3*205*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 9834*0 + 3*206*FLEN/8, x4, x1, x2)

inst_3279:
// fs1 == 0 and fe1 == 0xfa and fm1 == 0x772129 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x666666 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7d772129; op2val:0x80000000;
op3val:0x80666666; valaddr_reg:x3; val_offset:9837*0 + 3*206*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 9837*0 + 3*207*FLEN/8, x4, x1, x2)

inst_3280:
// fs1 == 0 and fe1 == 0xfa and fm1 == 0x772129 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x6db6db and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7d772129; op2val:0x80000000;
op3val:0x806db6db; valaddr_reg:x3; val_offset:9840*0 + 3*207*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 9840*0 + 3*208*FLEN/8, x4, x1, x2)

inst_3281:
// fs1 == 0 and fe1 == 0xfa and fm1 == 0x772129 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7ffff8 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7d772129; op2val:0x80000000;
op3val:0x807ffff8; valaddr_reg:x3; val_offset:9843*0 + 3*208*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 9843*0 + 3*209*FLEN/8, x4, x1, x2)

inst_3282:
// fs1 == 0 and fe1 == 0xfa and fm1 == 0x772129 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7ffffc and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7d772129; op2val:0x80000000;
op3val:0x807ffffc; valaddr_reg:x3; val_offset:9846*0 + 3*209*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 9846*0 + 3*210*FLEN/8, x4, x1, x2)

inst_3283:
// fs1 == 0 and fe1 == 0xfa and fm1 == 0x772129 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7ffffe and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7d772129; op2val:0x80000000;
op3val:0x807ffffe; valaddr_reg:x3; val_offset:9849*0 + 3*210*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 9849*0 + 3*211*FLEN/8, x4, x1, x2)

inst_3284:
// fs1 == 0 and fe1 == 0xfa and fm1 == 0x772129 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x0e and fm3 == 0x000000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7d772129; op2val:0x80000000;
op3val:0x87000000; valaddr_reg:x3; val_offset:9852*0 + 3*211*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 9852*0 + 3*212*FLEN/8, x4, x1, x2)

inst_3285:
// fs1 == 0 and fe1 == 0xfa and fm1 == 0x772129 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x0e and fm3 == 0x000001 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7d772129; op2val:0x80000000;
op3val:0x87000001; valaddr_reg:x3; val_offset:9855*0 + 3*212*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 9855*0 + 3*213*FLEN/8, x4, x1, x2)

inst_3286:
// fs1 == 0 and fe1 == 0xfa and fm1 == 0x772129 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x0e and fm3 == 0x000003 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7d772129; op2val:0x80000000;
op3val:0x87000003; valaddr_reg:x3; val_offset:9858*0 + 3*213*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 9858*0 + 3*214*FLEN/8, x4, x1, x2)

inst_3287:
// fs1 == 0 and fe1 == 0xfa and fm1 == 0x772129 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x0e and fm3 == 0x000007 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7d772129; op2val:0x80000000;
op3val:0x87000007; valaddr_reg:x3; val_offset:9861*0 + 3*214*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 9861*0 + 3*215*FLEN/8, x4, x1, x2)

inst_3288:
// fs1 == 0 and fe1 == 0xfa and fm1 == 0x772129 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x0e and fm3 == 0x00000f and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7d772129; op2val:0x80000000;
op3val:0x8700000f; valaddr_reg:x3; val_offset:9864*0 + 3*215*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 9864*0 + 3*216*FLEN/8, x4, x1, x2)

inst_3289:
// fs1 == 0 and fe1 == 0xfa and fm1 == 0x772129 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x0e and fm3 == 0x00001f and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7d772129; op2val:0x80000000;
op3val:0x8700001f; valaddr_reg:x3; val_offset:9867*0 + 3*216*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 9867*0 + 3*217*FLEN/8, x4, x1, x2)

inst_3290:
// fs1 == 0 and fe1 == 0xfa and fm1 == 0x772129 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x0e and fm3 == 0x00003f and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7d772129; op2val:0x80000000;
op3val:0x8700003f; valaddr_reg:x3; val_offset:9870*0 + 3*217*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 9870*0 + 3*218*FLEN/8, x4, x1, x2)

inst_3291:
// fs1 == 0 and fe1 == 0xfa and fm1 == 0x772129 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x0e and fm3 == 0x00007f and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7d772129; op2val:0x80000000;
op3val:0x8700007f; valaddr_reg:x3; val_offset:9873*0 + 3*218*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 9873*0 + 3*219*FLEN/8, x4, x1, x2)

inst_3292:
// fs1 == 0 and fe1 == 0xfa and fm1 == 0x772129 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x0e and fm3 == 0x0000ff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7d772129; op2val:0x80000000;
op3val:0x870000ff; valaddr_reg:x3; val_offset:9876*0 + 3*219*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 9876*0 + 3*220*FLEN/8, x4, x1, x2)

inst_3293:
// fs1 == 0 and fe1 == 0xfa and fm1 == 0x772129 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x0e and fm3 == 0x0001ff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7d772129; op2val:0x80000000;
op3val:0x870001ff; valaddr_reg:x3; val_offset:9879*0 + 3*220*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 9879*0 + 3*221*FLEN/8, x4, x1, x2)

inst_3294:
// fs1 == 0 and fe1 == 0xfa and fm1 == 0x772129 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x0e and fm3 == 0x0003ff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7d772129; op2val:0x80000000;
op3val:0x870003ff; valaddr_reg:x3; val_offset:9882*0 + 3*221*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 9882*0 + 3*222*FLEN/8, x4, x1, x2)

inst_3295:
// fs1 == 0 and fe1 == 0xfa and fm1 == 0x772129 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x0e and fm3 == 0x0007ff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7d772129; op2val:0x80000000;
op3val:0x870007ff; valaddr_reg:x3; val_offset:9885*0 + 3*222*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 9885*0 + 3*223*FLEN/8, x4, x1, x2)

inst_3296:
// fs1 == 0 and fe1 == 0xfa and fm1 == 0x772129 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x0e and fm3 == 0x000fff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7d772129; op2val:0x80000000;
op3val:0x87000fff; valaddr_reg:x3; val_offset:9888*0 + 3*223*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 9888*0 + 3*224*FLEN/8, x4, x1, x2)

inst_3297:
// fs1 == 0 and fe1 == 0xfa and fm1 == 0x772129 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x0e and fm3 == 0x001fff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7d772129; op2val:0x80000000;
op3val:0x87001fff; valaddr_reg:x3; val_offset:9891*0 + 3*224*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 9891*0 + 3*225*FLEN/8, x4, x1, x2)

inst_3298:
// fs1 == 0 and fe1 == 0xfa and fm1 == 0x772129 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x0e and fm3 == 0x003fff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7d772129; op2val:0x80000000;
op3val:0x87003fff; valaddr_reg:x3; val_offset:9894*0 + 3*225*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 9894*0 + 3*226*FLEN/8, x4, x1, x2)

inst_3299:
// fs1 == 0 and fe1 == 0xfa and fm1 == 0x772129 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x0e and fm3 == 0x007fff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7d772129; op2val:0x80000000;
op3val:0x87007fff; valaddr_reg:x3; val_offset:9897*0 + 3*226*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 9897*0 + 3*227*FLEN/8, x4, x1, x2)

inst_3300:
// fs1 == 0 and fe1 == 0xfa and fm1 == 0x772129 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x0e and fm3 == 0x00ffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7d772129; op2val:0x80000000;
op3val:0x8700ffff; valaddr_reg:x3; val_offset:9900*0 + 3*227*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 9900*0 + 3*228*FLEN/8, x4, x1, x2)

inst_3301:
// fs1 == 0 and fe1 == 0xfa and fm1 == 0x772129 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x0e and fm3 == 0x01ffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7d772129; op2val:0x80000000;
op3val:0x8701ffff; valaddr_reg:x3; val_offset:9903*0 + 3*228*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 9903*0 + 3*229*FLEN/8, x4, x1, x2)

inst_3302:
// fs1 == 0 and fe1 == 0xfa and fm1 == 0x772129 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x0e and fm3 == 0x03ffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7d772129; op2val:0x80000000;
op3val:0x8703ffff; valaddr_reg:x3; val_offset:9906*0 + 3*229*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 9906*0 + 3*230*FLEN/8, x4, x1, x2)

inst_3303:
// fs1 == 0 and fe1 == 0xfa and fm1 == 0x772129 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x0e and fm3 == 0x07ffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7d772129; op2val:0x80000000;
op3val:0x8707ffff; valaddr_reg:x3; val_offset:9909*0 + 3*230*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 9909*0 + 3*231*FLEN/8, x4, x1, x2)

inst_3304:
// fs1 == 0 and fe1 == 0xfa and fm1 == 0x772129 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x0e and fm3 == 0x0fffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7d772129; op2val:0x80000000;
op3val:0x870fffff; valaddr_reg:x3; val_offset:9912*0 + 3*231*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 9912*0 + 3*232*FLEN/8, x4, x1, x2)

inst_3305:
// fs1 == 0 and fe1 == 0xfa and fm1 == 0x772129 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x0e and fm3 == 0x1fffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7d772129; op2val:0x80000000;
op3val:0x871fffff; valaddr_reg:x3; val_offset:9915*0 + 3*232*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 9915*0 + 3*233*FLEN/8, x4, x1, x2)

inst_3306:
// fs1 == 0 and fe1 == 0xfa and fm1 == 0x772129 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x0e and fm3 == 0x3fffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7d772129; op2val:0x80000000;
op3val:0x873fffff; valaddr_reg:x3; val_offset:9918*0 + 3*233*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 9918*0 + 3*234*FLEN/8, x4, x1, x2)

inst_3307:
// fs1 == 0 and fe1 == 0xfa and fm1 == 0x772129 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x0e and fm3 == 0x400000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7d772129; op2val:0x80000000;
op3val:0x87400000; valaddr_reg:x3; val_offset:9921*0 + 3*234*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 9921*0 + 3*235*FLEN/8, x4, x1, x2)

inst_3308:
// fs1 == 0 and fe1 == 0xfa and fm1 == 0x772129 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x0e and fm3 == 0x600000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7d772129; op2val:0x80000000;
op3val:0x87600000; valaddr_reg:x3; val_offset:9924*0 + 3*235*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 9924*0 + 3*236*FLEN/8, x4, x1, x2)

inst_3309:
// fs1 == 0 and fe1 == 0xfa and fm1 == 0x772129 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x0e and fm3 == 0x700000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7d772129; op2val:0x80000000;
op3val:0x87700000; valaddr_reg:x3; val_offset:9927*0 + 3*236*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 9927*0 + 3*237*FLEN/8, x4, x1, x2)

inst_3310:
// fs1 == 0 and fe1 == 0xfa and fm1 == 0x772129 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x0e and fm3 == 0x780000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7d772129; op2val:0x80000000;
op3val:0x87780000; valaddr_reg:x3; val_offset:9930*0 + 3*237*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 9930*0 + 3*238*FLEN/8, x4, x1, x2)

inst_3311:
// fs1 == 0 and fe1 == 0xfa and fm1 == 0x772129 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x0e and fm3 == 0x7c0000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7d772129; op2val:0x80000000;
op3val:0x877c0000; valaddr_reg:x3; val_offset:9933*0 + 3*238*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 9933*0 + 3*239*FLEN/8, x4, x1, x2)

inst_3312:
// fs1 == 0 and fe1 == 0xfa and fm1 == 0x772129 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x0e and fm3 == 0x7e0000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7d772129; op2val:0x80000000;
op3val:0x877e0000; valaddr_reg:x3; val_offset:9936*0 + 3*239*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 9936*0 + 3*240*FLEN/8, x4, x1, x2)

inst_3313:
// fs1 == 0 and fe1 == 0xfa and fm1 == 0x772129 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x0e and fm3 == 0x7f0000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7d772129; op2val:0x80000000;
op3val:0x877f0000; valaddr_reg:x3; val_offset:9939*0 + 3*240*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 9939*0 + 3*241*FLEN/8, x4, x1, x2)

inst_3314:
// fs1 == 0 and fe1 == 0xfa and fm1 == 0x772129 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x0e and fm3 == 0x7f8000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7d772129; op2val:0x80000000;
op3val:0x877f8000; valaddr_reg:x3; val_offset:9942*0 + 3*241*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 9942*0 + 3*242*FLEN/8, x4, x1, x2)

inst_3315:
// fs1 == 0 and fe1 == 0xfa and fm1 == 0x772129 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x0e and fm3 == 0x7fc000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7d772129; op2val:0x80000000;
op3val:0x877fc000; valaddr_reg:x3; val_offset:9945*0 + 3*242*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 9945*0 + 3*243*FLEN/8, x4, x1, x2)

inst_3316:
// fs1 == 0 and fe1 == 0xfa and fm1 == 0x772129 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x0e and fm3 == 0x7fe000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7d772129; op2val:0x80000000;
op3val:0x877fe000; valaddr_reg:x3; val_offset:9948*0 + 3*243*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 9948*0 + 3*244*FLEN/8, x4, x1, x2)

inst_3317:
// fs1 == 0 and fe1 == 0xfa and fm1 == 0x772129 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x0e and fm3 == 0x7ff000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7d772129; op2val:0x80000000;
op3val:0x877ff000; valaddr_reg:x3; val_offset:9951*0 + 3*244*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 9951*0 + 3*245*FLEN/8, x4, x1, x2)

inst_3318:
// fs1 == 0 and fe1 == 0xfa and fm1 == 0x772129 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x0e and fm3 == 0x7ff800 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7d772129; op2val:0x80000000;
op3val:0x877ff800; valaddr_reg:x3; val_offset:9954*0 + 3*245*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 9954*0 + 3*246*FLEN/8, x4, x1, x2)

inst_3319:
// fs1 == 0 and fe1 == 0xfa and fm1 == 0x772129 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x0e and fm3 == 0x7ffc00 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7d772129; op2val:0x80000000;
op3val:0x877ffc00; valaddr_reg:x3; val_offset:9957*0 + 3*246*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 9957*0 + 3*247*FLEN/8, x4, x1, x2)

inst_3320:
// fs1 == 0 and fe1 == 0xfa and fm1 == 0x772129 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x0e and fm3 == 0x7ffe00 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7d772129; op2val:0x80000000;
op3val:0x877ffe00; valaddr_reg:x3; val_offset:9960*0 + 3*247*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 9960*0 + 3*248*FLEN/8, x4, x1, x2)

inst_3321:
// fs1 == 0 and fe1 == 0xfa and fm1 == 0x772129 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x0e and fm3 == 0x7fff00 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7d772129; op2val:0x80000000;
op3val:0x877fff00; valaddr_reg:x3; val_offset:9963*0 + 3*248*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 9963*0 + 3*249*FLEN/8, x4, x1, x2)

inst_3322:
// fs1 == 0 and fe1 == 0xfa and fm1 == 0x772129 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x0e and fm3 == 0x7fff80 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7d772129; op2val:0x80000000;
op3val:0x877fff80; valaddr_reg:x3; val_offset:9966*0 + 3*249*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 9966*0 + 3*250*FLEN/8, x4, x1, x2)

inst_3323:
// fs1 == 0 and fe1 == 0xfa and fm1 == 0x772129 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x0e and fm3 == 0x7fffc0 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7d772129; op2val:0x80000000;
op3val:0x877fffc0; valaddr_reg:x3; val_offset:9969*0 + 3*250*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 9969*0 + 3*251*FLEN/8, x4, x1, x2)

inst_3324:
// fs1 == 0 and fe1 == 0xfa and fm1 == 0x772129 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x0e and fm3 == 0x7fffe0 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7d772129; op2val:0x80000000;
op3val:0x877fffe0; valaddr_reg:x3; val_offset:9972*0 + 3*251*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 9972*0 + 3*252*FLEN/8, x4, x1, x2)

inst_3325:
// fs1 == 0 and fe1 == 0xfa and fm1 == 0x772129 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x0e and fm3 == 0x7ffff0 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7d772129; op2val:0x80000000;
op3val:0x877ffff0; valaddr_reg:x3; val_offset:9975*0 + 3*252*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 9975*0 + 3*253*FLEN/8, x4, x1, x2)

inst_3326:
// fs1 == 0 and fe1 == 0xfa and fm1 == 0x772129 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x0e and fm3 == 0x7ffff8 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7d772129; op2val:0x80000000;
op3val:0x877ffff8; valaddr_reg:x3; val_offset:9978*0 + 3*253*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 9978*0 + 3*254*FLEN/8, x4, x1, x2)

inst_3327:
// fs1 == 0 and fe1 == 0xfa and fm1 == 0x772129 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x0e and fm3 == 0x7ffffc and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7d772129; op2val:0x80000000;
op3val:0x877ffffc; valaddr_reg:x3; val_offset:9981*0 + 3*254*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 9981*0 + 3*255*FLEN/8, x4, x1, x2)
RVTEST_SIGBASE(x1,signature_x1_3)

inst_3328:
// fs1 == 0 and fe1 == 0xfa and fm1 == 0x772129 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x0e and fm3 == 0x7ffffe and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7d772129; op2val:0x80000000;
op3val:0x877ffffe; valaddr_reg:x3; val_offset:9984*0 + 3*256*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 9984*0 + 3*256*FLEN/8, x4, x1, x2)

inst_3329:
// fs1 == 0 and fe1 == 0xfa and fm1 == 0x772129 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x0e and fm3 == 0x7fffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7d772129; op2val:0x80000000;
op3val:0x877fffff; valaddr_reg:x3; val_offset:9987*0 + 3*257*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 9987*0 + 3*257*FLEN/8, x4, x1, x2)

inst_3330:
// fs1 == 0 and fe1 == 0xfa and fm1 == 0x77fb3b and fs2 == 1 and fe2 == 0x03 and fm2 == 0x042392 and fs3 == 1 and fe3 == 0x48 and fm3 == 0x000000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7d77fb3b; op2val:0x81842392;
op3val:0xa4000000; valaddr_reg:x3; val_offset:9990*0 + 3*258*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 9990*0 + 3*258*FLEN/8, x4, x1, x2)

inst_3331:
// fs1 == 0 and fe1 == 0xfa and fm1 == 0x77fb3b and fs2 == 1 and fe2 == 0x03 and fm2 == 0x042392 and fs3 == 1 and fe3 == 0x48 and fm3 == 0x000001 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7d77fb3b; op2val:0x81842392;
op3val:0xa4000001; valaddr_reg:x3; val_offset:9993*0 + 3*259*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 9993*0 + 3*259*FLEN/8, x4, x1, x2)

inst_3332:
// fs1 == 0 and fe1 == 0xfa and fm1 == 0x77fb3b and fs2 == 1 and fe2 == 0x03 and fm2 == 0x042392 and fs3 == 1 and fe3 == 0x48 and fm3 == 0x000003 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7d77fb3b; op2val:0x81842392;
op3val:0xa4000003; valaddr_reg:x3; val_offset:9996*0 + 3*260*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 9996*0 + 3*260*FLEN/8, x4, x1, x2)

inst_3333:
// fs1 == 0 and fe1 == 0xfa and fm1 == 0x77fb3b and fs2 == 1 and fe2 == 0x03 and fm2 == 0x042392 and fs3 == 1 and fe3 == 0x48 and fm3 == 0x000007 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7d77fb3b; op2val:0x81842392;
op3val:0xa4000007; valaddr_reg:x3; val_offset:9999*0 + 3*261*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 9999*0 + 3*261*FLEN/8, x4, x1, x2)

inst_3334:
// fs1 == 0 and fe1 == 0xfa and fm1 == 0x77fb3b and fs2 == 1 and fe2 == 0x03 and fm2 == 0x042392 and fs3 == 1 and fe3 == 0x48 and fm3 == 0x00000f and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7d77fb3b; op2val:0x81842392;
op3val:0xa400000f; valaddr_reg:x3; val_offset:10002*0 + 3*262*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 10002*0 + 3*262*FLEN/8, x4, x1, x2)

inst_3335:
// fs1 == 0 and fe1 == 0xfa and fm1 == 0x77fb3b and fs2 == 1 and fe2 == 0x03 and fm2 == 0x042392 and fs3 == 1 and fe3 == 0x48 and fm3 == 0x00001f and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7d77fb3b; op2val:0x81842392;
op3val:0xa400001f; valaddr_reg:x3; val_offset:10005*0 + 3*263*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 10005*0 + 3*263*FLEN/8, x4, x1, x2)

inst_3336:
// fs1 == 0 and fe1 == 0xfa and fm1 == 0x77fb3b and fs2 == 1 and fe2 == 0x03 and fm2 == 0x042392 and fs3 == 1 and fe3 == 0x48 and fm3 == 0x00003f and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7d77fb3b; op2val:0x81842392;
op3val:0xa400003f; valaddr_reg:x3; val_offset:10008*0 + 3*264*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 10008*0 + 3*264*FLEN/8, x4, x1, x2)

inst_3337:
// fs1 == 0 and fe1 == 0xfa and fm1 == 0x77fb3b and fs2 == 1 and fe2 == 0x03 and fm2 == 0x042392 and fs3 == 1 and fe3 == 0x48 and fm3 == 0x00007f and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7d77fb3b; op2val:0x81842392;
op3val:0xa400007f; valaddr_reg:x3; val_offset:10011*0 + 3*265*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 10011*0 + 3*265*FLEN/8, x4, x1, x2)

inst_3338:
// fs1 == 0 and fe1 == 0xfa and fm1 == 0x77fb3b and fs2 == 1 and fe2 == 0x03 and fm2 == 0x042392 and fs3 == 1 and fe3 == 0x48 and fm3 == 0x0000ff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7d77fb3b; op2val:0x81842392;
op3val:0xa40000ff; valaddr_reg:x3; val_offset:10014*0 + 3*266*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 10014*0 + 3*266*FLEN/8, x4, x1, x2)

inst_3339:
// fs1 == 0 and fe1 == 0xfa and fm1 == 0x77fb3b and fs2 == 1 and fe2 == 0x03 and fm2 == 0x042392 and fs3 == 1 and fe3 == 0x48 and fm3 == 0x0001ff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7d77fb3b; op2val:0x81842392;
op3val:0xa40001ff; valaddr_reg:x3; val_offset:10017*0 + 3*267*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 10017*0 + 3*267*FLEN/8, x4, x1, x2)

inst_3340:
// fs1 == 0 and fe1 == 0xfa and fm1 == 0x77fb3b and fs2 == 1 and fe2 == 0x03 and fm2 == 0x042392 and fs3 == 1 and fe3 == 0x48 and fm3 == 0x0003ff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7d77fb3b; op2val:0x81842392;
op3val:0xa40003ff; valaddr_reg:x3; val_offset:10020*0 + 3*268*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 10020*0 + 3*268*FLEN/8, x4, x1, x2)

inst_3341:
// fs1 == 0 and fe1 == 0xfa and fm1 == 0x77fb3b and fs2 == 1 and fe2 == 0x03 and fm2 == 0x042392 and fs3 == 1 and fe3 == 0x48 and fm3 == 0x0007ff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7d77fb3b; op2val:0x81842392;
op3val:0xa40007ff; valaddr_reg:x3; val_offset:10023*0 + 3*269*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 10023*0 + 3*269*FLEN/8, x4, x1, x2)

inst_3342:
// fs1 == 0 and fe1 == 0xfa and fm1 == 0x77fb3b and fs2 == 1 and fe2 == 0x03 and fm2 == 0x042392 and fs3 == 1 and fe3 == 0x48 and fm3 == 0x000fff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7d77fb3b; op2val:0x81842392;
op3val:0xa4000fff; valaddr_reg:x3; val_offset:10026*0 + 3*270*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 10026*0 + 3*270*FLEN/8, x4, x1, x2)

inst_3343:
// fs1 == 0 and fe1 == 0xfa and fm1 == 0x77fb3b and fs2 == 1 and fe2 == 0x03 and fm2 == 0x042392 and fs3 == 1 and fe3 == 0x48 and fm3 == 0x001fff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7d77fb3b; op2val:0x81842392;
op3val:0xa4001fff; valaddr_reg:x3; val_offset:10029*0 + 3*271*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 10029*0 + 3*271*FLEN/8, x4, x1, x2)

inst_3344:
// fs1 == 0 and fe1 == 0xfa and fm1 == 0x77fb3b and fs2 == 1 and fe2 == 0x03 and fm2 == 0x042392 and fs3 == 1 and fe3 == 0x48 and fm3 == 0x003fff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7d77fb3b; op2val:0x81842392;
op3val:0xa4003fff; valaddr_reg:x3; val_offset:10032*0 + 3*272*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 10032*0 + 3*272*FLEN/8, x4, x1, x2)

inst_3345:
// fs1 == 0 and fe1 == 0xfa and fm1 == 0x77fb3b and fs2 == 1 and fe2 == 0x03 and fm2 == 0x042392 and fs3 == 1 and fe3 == 0x48 and fm3 == 0x007fff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7d77fb3b; op2val:0x81842392;
op3val:0xa4007fff; valaddr_reg:x3; val_offset:10035*0 + 3*273*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 10035*0 + 3*273*FLEN/8, x4, x1, x2)

inst_3346:
// fs1 == 0 and fe1 == 0xfa and fm1 == 0x77fb3b and fs2 == 1 and fe2 == 0x03 and fm2 == 0x042392 and fs3 == 1 and fe3 == 0x48 and fm3 == 0x00ffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7d77fb3b; op2val:0x81842392;
op3val:0xa400ffff; valaddr_reg:x3; val_offset:10038*0 + 3*274*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 10038*0 + 3*274*FLEN/8, x4, x1, x2)

inst_3347:
// fs1 == 0 and fe1 == 0xfa and fm1 == 0x77fb3b and fs2 == 1 and fe2 == 0x03 and fm2 == 0x042392 and fs3 == 1 and fe3 == 0x48 and fm3 == 0x01ffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7d77fb3b; op2val:0x81842392;
op3val:0xa401ffff; valaddr_reg:x3; val_offset:10041*0 + 3*275*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 10041*0 + 3*275*FLEN/8, x4, x1, x2)

inst_3348:
// fs1 == 0 and fe1 == 0xfa and fm1 == 0x77fb3b and fs2 == 1 and fe2 == 0x03 and fm2 == 0x042392 and fs3 == 1 and fe3 == 0x48 and fm3 == 0x03ffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7d77fb3b; op2val:0x81842392;
op3val:0xa403ffff; valaddr_reg:x3; val_offset:10044*0 + 3*276*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 10044*0 + 3*276*FLEN/8, x4, x1, x2)

inst_3349:
// fs1 == 0 and fe1 == 0xfa and fm1 == 0x77fb3b and fs2 == 1 and fe2 == 0x03 and fm2 == 0x042392 and fs3 == 1 and fe3 == 0x48 and fm3 == 0x07ffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7d77fb3b; op2val:0x81842392;
op3val:0xa407ffff; valaddr_reg:x3; val_offset:10047*0 + 3*277*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 10047*0 + 3*277*FLEN/8, x4, x1, x2)

inst_3350:
// fs1 == 0 and fe1 == 0xfa and fm1 == 0x77fb3b and fs2 == 1 and fe2 == 0x03 and fm2 == 0x042392 and fs3 == 1 and fe3 == 0x48 and fm3 == 0x0fffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7d77fb3b; op2val:0x81842392;
op3val:0xa40fffff; valaddr_reg:x3; val_offset:10050*0 + 3*278*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 10050*0 + 3*278*FLEN/8, x4, x1, x2)

inst_3351:
// fs1 == 0 and fe1 == 0xfa and fm1 == 0x77fb3b and fs2 == 1 and fe2 == 0x03 and fm2 == 0x042392 and fs3 == 1 and fe3 == 0x48 and fm3 == 0x1fffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7d77fb3b; op2val:0x81842392;
op3val:0xa41fffff; valaddr_reg:x3; val_offset:10053*0 + 3*279*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 10053*0 + 3*279*FLEN/8, x4, x1, x2)

inst_3352:
// fs1 == 0 and fe1 == 0xfa and fm1 == 0x77fb3b and fs2 == 1 and fe2 == 0x03 and fm2 == 0x042392 and fs3 == 1 and fe3 == 0x48 and fm3 == 0x3fffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7d77fb3b; op2val:0x81842392;
op3val:0xa43fffff; valaddr_reg:x3; val_offset:10056*0 + 3*280*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 10056*0 + 3*280*FLEN/8, x4, x1, x2)

inst_3353:
// fs1 == 0 and fe1 == 0xfa and fm1 == 0x77fb3b and fs2 == 1 and fe2 == 0x03 and fm2 == 0x042392 and fs3 == 1 and fe3 == 0x48 and fm3 == 0x400000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7d77fb3b; op2val:0x81842392;
op3val:0xa4400000; valaddr_reg:x3; val_offset:10059*0 + 3*281*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 10059*0 + 3*281*FLEN/8, x4, x1, x2)

inst_3354:
// fs1 == 0 and fe1 == 0xfa and fm1 == 0x77fb3b and fs2 == 1 and fe2 == 0x03 and fm2 == 0x042392 and fs3 == 1 and fe3 == 0x48 and fm3 == 0x600000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7d77fb3b; op2val:0x81842392;
op3val:0xa4600000; valaddr_reg:x3; val_offset:10062*0 + 3*282*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 10062*0 + 3*282*FLEN/8, x4, x1, x2)

inst_3355:
// fs1 == 0 and fe1 == 0xfa and fm1 == 0x77fb3b and fs2 == 1 and fe2 == 0x03 and fm2 == 0x042392 and fs3 == 1 and fe3 == 0x48 and fm3 == 0x700000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7d77fb3b; op2val:0x81842392;
op3val:0xa4700000; valaddr_reg:x3; val_offset:10065*0 + 3*283*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 10065*0 + 3*283*FLEN/8, x4, x1, x2)

inst_3356:
// fs1 == 0 and fe1 == 0xfa and fm1 == 0x77fb3b and fs2 == 1 and fe2 == 0x03 and fm2 == 0x042392 and fs3 == 1 and fe3 == 0x48 and fm3 == 0x780000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7d77fb3b; op2val:0x81842392;
op3val:0xa4780000; valaddr_reg:x3; val_offset:10068*0 + 3*284*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 10068*0 + 3*284*FLEN/8, x4, x1, x2)

inst_3357:
// fs1 == 0 and fe1 == 0xfa and fm1 == 0x77fb3b and fs2 == 1 and fe2 == 0x03 and fm2 == 0x042392 and fs3 == 1 and fe3 == 0x48 and fm3 == 0x7c0000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7d77fb3b; op2val:0x81842392;
op3val:0xa47c0000; valaddr_reg:x3; val_offset:10071*0 + 3*285*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 10071*0 + 3*285*FLEN/8, x4, x1, x2)

inst_3358:
// fs1 == 0 and fe1 == 0xfa and fm1 == 0x77fb3b and fs2 == 1 and fe2 == 0x03 and fm2 == 0x042392 and fs3 == 1 and fe3 == 0x48 and fm3 == 0x7e0000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7d77fb3b; op2val:0x81842392;
op3val:0xa47e0000; valaddr_reg:x3; val_offset:10074*0 + 3*286*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 10074*0 + 3*286*FLEN/8, x4, x1, x2)

inst_3359:
// fs1 == 0 and fe1 == 0xfa and fm1 == 0x77fb3b and fs2 == 1 and fe2 == 0x03 and fm2 == 0x042392 and fs3 == 1 and fe3 == 0x48 and fm3 == 0x7f0000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7d77fb3b; op2val:0x81842392;
op3val:0xa47f0000; valaddr_reg:x3; val_offset:10077*0 + 3*287*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 10077*0 + 3*287*FLEN/8, x4, x1, x2)

inst_3360:
// fs1 == 0 and fe1 == 0xfa and fm1 == 0x77fb3b and fs2 == 1 and fe2 == 0x03 and fm2 == 0x042392 and fs3 == 1 and fe3 == 0x48 and fm3 == 0x7f8000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7d77fb3b; op2val:0x81842392;
op3val:0xa47f8000; valaddr_reg:x3; val_offset:10080*0 + 3*288*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 10080*0 + 3*288*FLEN/8, x4, x1, x2)

inst_3361:
// fs1 == 0 and fe1 == 0xfa and fm1 == 0x77fb3b and fs2 == 1 and fe2 == 0x03 and fm2 == 0x042392 and fs3 == 1 and fe3 == 0x48 and fm3 == 0x7fc000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7d77fb3b; op2val:0x81842392;
op3val:0xa47fc000; valaddr_reg:x3; val_offset:10083*0 + 3*289*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 10083*0 + 3*289*FLEN/8, x4, x1, x2)

inst_3362:
// fs1 == 0 and fe1 == 0xfa and fm1 == 0x77fb3b and fs2 == 1 and fe2 == 0x03 and fm2 == 0x042392 and fs3 == 1 and fe3 == 0x48 and fm3 == 0x7fe000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7d77fb3b; op2val:0x81842392;
op3val:0xa47fe000; valaddr_reg:x3; val_offset:10086*0 + 3*290*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 10086*0 + 3*290*FLEN/8, x4, x1, x2)

inst_3363:
// fs1 == 0 and fe1 == 0xfa and fm1 == 0x77fb3b and fs2 == 1 and fe2 == 0x03 and fm2 == 0x042392 and fs3 == 1 and fe3 == 0x48 and fm3 == 0x7ff000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7d77fb3b; op2val:0x81842392;
op3val:0xa47ff000; valaddr_reg:x3; val_offset:10089*0 + 3*291*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 10089*0 + 3*291*FLEN/8, x4, x1, x2)

inst_3364:
// fs1 == 0 and fe1 == 0xfa and fm1 == 0x77fb3b and fs2 == 1 and fe2 == 0x03 and fm2 == 0x042392 and fs3 == 1 and fe3 == 0x48 and fm3 == 0x7ff800 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7d77fb3b; op2val:0x81842392;
op3val:0xa47ff800; valaddr_reg:x3; val_offset:10092*0 + 3*292*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 10092*0 + 3*292*FLEN/8, x4, x1, x2)

inst_3365:
// fs1 == 0 and fe1 == 0xfa and fm1 == 0x77fb3b and fs2 == 1 and fe2 == 0x03 and fm2 == 0x042392 and fs3 == 1 and fe3 == 0x48 and fm3 == 0x7ffc00 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7d77fb3b; op2val:0x81842392;
op3val:0xa47ffc00; valaddr_reg:x3; val_offset:10095*0 + 3*293*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 10095*0 + 3*293*FLEN/8, x4, x1, x2)

inst_3366:
// fs1 == 0 and fe1 == 0xfa and fm1 == 0x77fb3b and fs2 == 1 and fe2 == 0x03 and fm2 == 0x042392 and fs3 == 1 and fe3 == 0x48 and fm3 == 0x7ffe00 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7d77fb3b; op2val:0x81842392;
op3val:0xa47ffe00; valaddr_reg:x3; val_offset:10098*0 + 3*294*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 10098*0 + 3*294*FLEN/8, x4, x1, x2)

inst_3367:
// fs1 == 0 and fe1 == 0xfa and fm1 == 0x77fb3b and fs2 == 1 and fe2 == 0x03 and fm2 == 0x042392 and fs3 == 1 and fe3 == 0x48 and fm3 == 0x7fff00 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7d77fb3b; op2val:0x81842392;
op3val:0xa47fff00; valaddr_reg:x3; val_offset:10101*0 + 3*295*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 10101*0 + 3*295*FLEN/8, x4, x1, x2)

inst_3368:
// fs1 == 0 and fe1 == 0xfa and fm1 == 0x77fb3b and fs2 == 1 and fe2 == 0x03 and fm2 == 0x042392 and fs3 == 1 and fe3 == 0x48 and fm3 == 0x7fff80 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7d77fb3b; op2val:0x81842392;
op3val:0xa47fff80; valaddr_reg:x3; val_offset:10104*0 + 3*296*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 10104*0 + 3*296*FLEN/8, x4, x1, x2)

inst_3369:
// fs1 == 0 and fe1 == 0xfa and fm1 == 0x77fb3b and fs2 == 1 and fe2 == 0x03 and fm2 == 0x042392 and fs3 == 1 and fe3 == 0x48 and fm3 == 0x7fffc0 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7d77fb3b; op2val:0x81842392;
op3val:0xa47fffc0; valaddr_reg:x3; val_offset:10107*0 + 3*297*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 10107*0 + 3*297*FLEN/8, x4, x1, x2)

inst_3370:
// fs1 == 0 and fe1 == 0xfa and fm1 == 0x77fb3b and fs2 == 1 and fe2 == 0x03 and fm2 == 0x042392 and fs3 == 1 and fe3 == 0x48 and fm3 == 0x7fffe0 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7d77fb3b; op2val:0x81842392;
op3val:0xa47fffe0; valaddr_reg:x3; val_offset:10110*0 + 3*298*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 10110*0 + 3*298*FLEN/8, x4, x1, x2)

inst_3371:
// fs1 == 0 and fe1 == 0xfa and fm1 == 0x77fb3b and fs2 == 1 and fe2 == 0x03 and fm2 == 0x042392 and fs3 == 1 and fe3 == 0x48 and fm3 == 0x7ffff0 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7d77fb3b; op2val:0x81842392;
op3val:0xa47ffff0; valaddr_reg:x3; val_offset:10113*0 + 3*299*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 10113*0 + 3*299*FLEN/8, x4, x1, x2)

inst_3372:
// fs1 == 0 and fe1 == 0xfa and fm1 == 0x77fb3b and fs2 == 1 and fe2 == 0x03 and fm2 == 0x042392 and fs3 == 1 and fe3 == 0x48 and fm3 == 0x7ffff8 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7d77fb3b; op2val:0x81842392;
op3val:0xa47ffff8; valaddr_reg:x3; val_offset:10116*0 + 3*300*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 10116*0 + 3*300*FLEN/8, x4, x1, x2)

inst_3373:
// fs1 == 0 and fe1 == 0xfa and fm1 == 0x77fb3b and fs2 == 1 and fe2 == 0x03 and fm2 == 0x042392 and fs3 == 1 and fe3 == 0x48 and fm3 == 0x7ffffc and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7d77fb3b; op2val:0x81842392;
op3val:0xa47ffffc; valaddr_reg:x3; val_offset:10119*0 + 3*301*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 10119*0 + 3*301*FLEN/8, x4, x1, x2)

inst_3374:
// fs1 == 0 and fe1 == 0xfa and fm1 == 0x77fb3b and fs2 == 1 and fe2 == 0x03 and fm2 == 0x042392 and fs3 == 1 and fe3 == 0x48 and fm3 == 0x7ffffe and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7d77fb3b; op2val:0x81842392;
op3val:0xa47ffffe; valaddr_reg:x3; val_offset:10122*0 + 3*302*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 10122*0 + 3*302*FLEN/8, x4, x1, x2)

inst_3375:
// fs1 == 0 and fe1 == 0xfa and fm1 == 0x77fb3b and fs2 == 1 and fe2 == 0x03 and fm2 == 0x042392 and fs3 == 1 and fe3 == 0x48 and fm3 == 0x7fffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7d77fb3b; op2val:0x81842392;
op3val:0xa47fffff; valaddr_reg:x3; val_offset:10125*0 + 3*303*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 10125*0 + 3*303*FLEN/8, x4, x1, x2)

inst_3376:
// fs1 == 0 and fe1 == 0xfa and fm1 == 0x77fb3b and fs2 == 1 and fe2 == 0x03 and fm2 == 0x042392 and fs3 == 1 and fe3 == 0x7f and fm3 == 0x000001 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7d77fb3b; op2val:0x81842392;
op3val:0xbf800001; valaddr_reg:x3; val_offset:10128*0 + 3*304*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 10128*0 + 3*304*FLEN/8, x4, x1, x2)

inst_3377:
// fs1 == 0 and fe1 == 0xfa and fm1 == 0x77fb3b and fs2 == 1 and fe2 == 0x03 and fm2 == 0x042392 and fs3 == 1 and fe3 == 0x7f and fm3 == 0x000003 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7d77fb3b; op2val:0x81842392;
op3val:0xbf800003; valaddr_reg:x3; val_offset:10131*0 + 3*305*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 10131*0 + 3*305*FLEN/8, x4, x1, x2)

inst_3378:
// fs1 == 0 and fe1 == 0xfa and fm1 == 0x77fb3b and fs2 == 1 and fe2 == 0x03 and fm2 == 0x042392 and fs3 == 1 and fe3 == 0x7f and fm3 == 0x000007 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7d77fb3b; op2val:0x81842392;
op3val:0xbf800007; valaddr_reg:x3; val_offset:10134*0 + 3*306*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 10134*0 + 3*306*FLEN/8, x4, x1, x2)

inst_3379:
// fs1 == 0 and fe1 == 0xfa and fm1 == 0x77fb3b and fs2 == 1 and fe2 == 0x03 and fm2 == 0x042392 and fs3 == 1 and fe3 == 0x7f and fm3 == 0x199999 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7d77fb3b; op2val:0x81842392;
op3val:0xbf999999; valaddr_reg:x3; val_offset:10137*0 + 3*307*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 10137*0 + 3*307*FLEN/8, x4, x1, x2)

inst_3380:
// fs1 == 0 and fe1 == 0xfa and fm1 == 0x77fb3b and fs2 == 1 and fe2 == 0x03 and fm2 == 0x042392 and fs3 == 1 and fe3 == 0x7f and fm3 == 0x249249 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7d77fb3b; op2val:0x81842392;
op3val:0xbfa49249; valaddr_reg:x3; val_offset:10140*0 + 3*308*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 10140*0 + 3*308*FLEN/8, x4, x1, x2)

inst_3381:
// fs1 == 0 and fe1 == 0xfa and fm1 == 0x77fb3b and fs2 == 1 and fe2 == 0x03 and fm2 == 0x042392 and fs3 == 1 and fe3 == 0x7f and fm3 == 0x333333 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7d77fb3b; op2val:0x81842392;
op3val:0xbfb33333; valaddr_reg:x3; val_offset:10143*0 + 3*309*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 10143*0 + 3*309*FLEN/8, x4, x1, x2)

inst_3382:
// fs1 == 0 and fe1 == 0xfa and fm1 == 0x77fb3b and fs2 == 1 and fe2 == 0x03 and fm2 == 0x042392 and fs3 == 1 and fe3 == 0x7f and fm3 == 0x36db6d and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7d77fb3b; op2val:0x81842392;
op3val:0xbfb6db6d; valaddr_reg:x3; val_offset:10146*0 + 3*310*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 10146*0 + 3*310*FLEN/8, x4, x1, x2)

inst_3383:
// fs1 == 0 and fe1 == 0xfa and fm1 == 0x77fb3b and fs2 == 1 and fe2 == 0x03 and fm2 == 0x042392 and fs3 == 1 and fe3 == 0x7f and fm3 == 0x3bbbbb and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7d77fb3b; op2val:0x81842392;
op3val:0xbfbbbbbb; valaddr_reg:x3; val_offset:10149*0 + 3*311*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 10149*0 + 3*311*FLEN/8, x4, x1, x2)

inst_3384:
// fs1 == 0 and fe1 == 0xfa and fm1 == 0x77fb3b and fs2 == 1 and fe2 == 0x03 and fm2 == 0x042392 and fs3 == 1 and fe3 == 0x7f and fm3 == 0x444444 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7d77fb3b; op2val:0x81842392;
op3val:0xbfc44444; valaddr_reg:x3; val_offset:10152*0 + 3*312*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 10152*0 + 3*312*FLEN/8, x4, x1, x2)

inst_3385:
// fs1 == 0 and fe1 == 0xfa and fm1 == 0x77fb3b and fs2 == 1 and fe2 == 0x03 and fm2 == 0x042392 and fs3 == 1 and fe3 == 0x7f and fm3 == 0x4ccccc and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7d77fb3b; op2val:0x81842392;
op3val:0xbfcccccc; valaddr_reg:x3; val_offset:10155*0 + 3*313*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 10155*0 + 3*313*FLEN/8, x4, x1, x2)

inst_3386:
// fs1 == 0 and fe1 == 0xfa and fm1 == 0x77fb3b and fs2 == 1 and fe2 == 0x03 and fm2 == 0x042392 and fs3 == 1 and fe3 == 0x7f and fm3 == 0x5b6db6 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7d77fb3b; op2val:0x81842392;
op3val:0xbfdb6db6; valaddr_reg:x3; val_offset:10158*0 + 3*314*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 10158*0 + 3*314*FLEN/8, x4, x1, x2)

inst_3387:
// fs1 == 0 and fe1 == 0xfa and fm1 == 0x77fb3b and fs2 == 1 and fe2 == 0x03 and fm2 == 0x042392 and fs3 == 1 and fe3 == 0x7f and fm3 == 0x666666 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7d77fb3b; op2val:0x81842392;
op3val:0xbfe66666; valaddr_reg:x3; val_offset:10161*0 + 3*315*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 10161*0 + 3*315*FLEN/8, x4, x1, x2)

inst_3388:
// fs1 == 0 and fe1 == 0xfa and fm1 == 0x77fb3b and fs2 == 1 and fe2 == 0x03 and fm2 == 0x042392 and fs3 == 1 and fe3 == 0x7f and fm3 == 0x6db6db and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7d77fb3b; op2val:0x81842392;
op3val:0xbfedb6db; valaddr_reg:x3; val_offset:10164*0 + 3*316*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 10164*0 + 3*316*FLEN/8, x4, x1, x2)

inst_3389:
// fs1 == 0 and fe1 == 0xfa and fm1 == 0x77fb3b and fs2 == 1 and fe2 == 0x03 and fm2 == 0x042392 and fs3 == 1 and fe3 == 0x7f and fm3 == 0x7ffff8 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7d77fb3b; op2val:0x81842392;
op3val:0xbffffff8; valaddr_reg:x3; val_offset:10167*0 + 3*317*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 10167*0 + 3*317*FLEN/8, x4, x1, x2)

inst_3390:
// fs1 == 0 and fe1 == 0xfa and fm1 == 0x77fb3b and fs2 == 1 and fe2 == 0x03 and fm2 == 0x042392 and fs3 == 1 and fe3 == 0x7f and fm3 == 0x7ffffc and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7d77fb3b; op2val:0x81842392;
op3val:0xbffffffc; valaddr_reg:x3; val_offset:10170*0 + 3*318*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 10170*0 + 3*318*FLEN/8, x4, x1, x2)

inst_3391:
// fs1 == 0 and fe1 == 0xfa and fm1 == 0x77fb3b and fs2 == 1 and fe2 == 0x03 and fm2 == 0x042392 and fs3 == 1 and fe3 == 0x7f and fm3 == 0x7ffffe and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7d77fb3b; op2val:0x81842392;
op3val:0xbffffffe; valaddr_reg:x3; val_offset:10173*0 + 3*319*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 10173*0 + 3*319*FLEN/8, x4, x1, x2)

inst_3392:
// fs1 == 0 and fe1 == 0xfa and fm1 == 0x783eca and fs2 == 0 and fe2 == 0x83 and fm2 == 0x03ff9c and fs3 == 0 and fe3 == 0xe4 and fm3 == 0x000000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7d783eca; op2val:0x4183ff9c;
op3val:0x72000000; valaddr_reg:x3; val_offset:10176*0 + 3*320*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 10176*0 + 3*320*FLEN/8, x4, x1, x2)

inst_3393:
// fs1 == 0 and fe1 == 0xfa and fm1 == 0x783eca and fs2 == 0 and fe2 == 0x83 and fm2 == 0x03ff9c and fs3 == 0 and fe3 == 0xe4 and fm3 == 0x000001 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7d783eca; op2val:0x4183ff9c;
op3val:0x72000001; valaddr_reg:x3; val_offset:10179*0 + 3*321*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 10179*0 + 3*321*FLEN/8, x4, x1, x2)

inst_3394:
// fs1 == 0 and fe1 == 0xfa and fm1 == 0x783eca and fs2 == 0 and fe2 == 0x83 and fm2 == 0x03ff9c and fs3 == 0 and fe3 == 0xe4 and fm3 == 0x000003 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7d783eca; op2val:0x4183ff9c;
op3val:0x72000003; valaddr_reg:x3; val_offset:10182*0 + 3*322*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 10182*0 + 3*322*FLEN/8, x4, x1, x2)

inst_3395:
// fs1 == 0 and fe1 == 0xfa and fm1 == 0x783eca and fs2 == 0 and fe2 == 0x83 and fm2 == 0x03ff9c and fs3 == 0 and fe3 == 0xe4 and fm3 == 0x000007 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7d783eca; op2val:0x4183ff9c;
op3val:0x72000007; valaddr_reg:x3; val_offset:10185*0 + 3*323*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 10185*0 + 3*323*FLEN/8, x4, x1, x2)

inst_3396:
// fs1 == 0 and fe1 == 0xfa and fm1 == 0x783eca and fs2 == 0 and fe2 == 0x83 and fm2 == 0x03ff9c and fs3 == 0 and fe3 == 0xe4 and fm3 == 0x00000f and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7d783eca; op2val:0x4183ff9c;
op3val:0x7200000f; valaddr_reg:x3; val_offset:10188*0 + 3*324*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 10188*0 + 3*324*FLEN/8, x4, x1, x2)

inst_3397:
// fs1 == 0 and fe1 == 0xfa and fm1 == 0x783eca and fs2 == 0 and fe2 == 0x83 and fm2 == 0x03ff9c and fs3 == 0 and fe3 == 0xe4 and fm3 == 0x00001f and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7d783eca; op2val:0x4183ff9c;
op3val:0x7200001f; valaddr_reg:x3; val_offset:10191*0 + 3*325*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 10191*0 + 3*325*FLEN/8, x4, x1, x2)

inst_3398:
// fs1 == 0 and fe1 == 0xfa and fm1 == 0x783eca and fs2 == 0 and fe2 == 0x83 and fm2 == 0x03ff9c and fs3 == 0 and fe3 == 0xe4 and fm3 == 0x00003f and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7d783eca; op2val:0x4183ff9c;
op3val:0x7200003f; valaddr_reg:x3; val_offset:10194*0 + 3*326*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 10194*0 + 3*326*FLEN/8, x4, x1, x2)

inst_3399:
// fs1 == 0 and fe1 == 0xfa and fm1 == 0x783eca and fs2 == 0 and fe2 == 0x83 and fm2 == 0x03ff9c and fs3 == 0 and fe3 == 0xe4 and fm3 == 0x00007f and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7d783eca; op2val:0x4183ff9c;
op3val:0x7200007f; valaddr_reg:x3; val_offset:10197*0 + 3*327*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 10197*0 + 3*327*FLEN/8, x4, x1, x2)

inst_3400:
// fs1 == 0 and fe1 == 0xfa and fm1 == 0x783eca and fs2 == 0 and fe2 == 0x83 and fm2 == 0x03ff9c and fs3 == 0 and fe3 == 0xe4 and fm3 == 0x0000ff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7d783eca; op2val:0x4183ff9c;
op3val:0x720000ff; valaddr_reg:x3; val_offset:10200*0 + 3*328*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 10200*0 + 3*328*FLEN/8, x4, x1, x2)

inst_3401:
// fs1 == 0 and fe1 == 0xfa and fm1 == 0x783eca and fs2 == 0 and fe2 == 0x83 and fm2 == 0x03ff9c and fs3 == 0 and fe3 == 0xe4 and fm3 == 0x0001ff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7d783eca; op2val:0x4183ff9c;
op3val:0x720001ff; valaddr_reg:x3; val_offset:10203*0 + 3*329*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 10203*0 + 3*329*FLEN/8, x4, x1, x2)

inst_3402:
// fs1 == 0 and fe1 == 0xfa and fm1 == 0x783eca and fs2 == 0 and fe2 == 0x83 and fm2 == 0x03ff9c and fs3 == 0 and fe3 == 0xe4 and fm3 == 0x0003ff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7d783eca; op2val:0x4183ff9c;
op3val:0x720003ff; valaddr_reg:x3; val_offset:10206*0 + 3*330*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 10206*0 + 3*330*FLEN/8, x4, x1, x2)

inst_3403:
// fs1 == 0 and fe1 == 0xfa and fm1 == 0x783eca and fs2 == 0 and fe2 == 0x83 and fm2 == 0x03ff9c and fs3 == 0 and fe3 == 0xe4 and fm3 == 0x0007ff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7d783eca; op2val:0x4183ff9c;
op3val:0x720007ff; valaddr_reg:x3; val_offset:10209*0 + 3*331*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 10209*0 + 3*331*FLEN/8, x4, x1, x2)

inst_3404:
// fs1 == 0 and fe1 == 0xfa and fm1 == 0x783eca and fs2 == 0 and fe2 == 0x83 and fm2 == 0x03ff9c and fs3 == 0 and fe3 == 0xe4 and fm3 == 0x000fff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7d783eca; op2val:0x4183ff9c;
op3val:0x72000fff; valaddr_reg:x3; val_offset:10212*0 + 3*332*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 10212*0 + 3*332*FLEN/8, x4, x1, x2)

inst_3405:
// fs1 == 0 and fe1 == 0xfa and fm1 == 0x783eca and fs2 == 0 and fe2 == 0x83 and fm2 == 0x03ff9c and fs3 == 0 and fe3 == 0xe4 and fm3 == 0x001fff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7d783eca; op2val:0x4183ff9c;
op3val:0x72001fff; valaddr_reg:x3; val_offset:10215*0 + 3*333*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 10215*0 + 3*333*FLEN/8, x4, x1, x2)

inst_3406:
// fs1 == 0 and fe1 == 0xfa and fm1 == 0x783eca and fs2 == 0 and fe2 == 0x83 and fm2 == 0x03ff9c and fs3 == 0 and fe3 == 0xe4 and fm3 == 0x003fff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7d783eca; op2val:0x4183ff9c;
op3val:0x72003fff; valaddr_reg:x3; val_offset:10218*0 + 3*334*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 10218*0 + 3*334*FLEN/8, x4, x1, x2)

inst_3407:
// fs1 == 0 and fe1 == 0xfa and fm1 == 0x783eca and fs2 == 0 and fe2 == 0x83 and fm2 == 0x03ff9c and fs3 == 0 and fe3 == 0xe4 and fm3 == 0x007fff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7d783eca; op2val:0x4183ff9c;
op3val:0x72007fff; valaddr_reg:x3; val_offset:10221*0 + 3*335*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 10221*0 + 3*335*FLEN/8, x4, x1, x2)

inst_3408:
// fs1 == 0 and fe1 == 0xfa and fm1 == 0x783eca and fs2 == 0 and fe2 == 0x83 and fm2 == 0x03ff9c and fs3 == 0 and fe3 == 0xe4 and fm3 == 0x00ffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7d783eca; op2val:0x4183ff9c;
op3val:0x7200ffff; valaddr_reg:x3; val_offset:10224*0 + 3*336*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 10224*0 + 3*336*FLEN/8, x4, x1, x2)

inst_3409:
// fs1 == 0 and fe1 == 0xfa and fm1 == 0x783eca and fs2 == 0 and fe2 == 0x83 and fm2 == 0x03ff9c and fs3 == 0 and fe3 == 0xe4 and fm3 == 0x01ffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7d783eca; op2val:0x4183ff9c;
op3val:0x7201ffff; valaddr_reg:x3; val_offset:10227*0 + 3*337*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 10227*0 + 3*337*FLEN/8, x4, x1, x2)

inst_3410:
// fs1 == 0 and fe1 == 0xfa and fm1 == 0x783eca and fs2 == 0 and fe2 == 0x83 and fm2 == 0x03ff9c and fs3 == 0 and fe3 == 0xe4 and fm3 == 0x03ffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7d783eca; op2val:0x4183ff9c;
op3val:0x7203ffff; valaddr_reg:x3; val_offset:10230*0 + 3*338*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 10230*0 + 3*338*FLEN/8, x4, x1, x2)

inst_3411:
// fs1 == 0 and fe1 == 0xfa and fm1 == 0x783eca and fs2 == 0 and fe2 == 0x83 and fm2 == 0x03ff9c and fs3 == 0 and fe3 == 0xe4 and fm3 == 0x07ffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7d783eca; op2val:0x4183ff9c;
op3val:0x7207ffff; valaddr_reg:x3; val_offset:10233*0 + 3*339*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 10233*0 + 3*339*FLEN/8, x4, x1, x2)

inst_3412:
// fs1 == 0 and fe1 == 0xfa and fm1 == 0x783eca and fs2 == 0 and fe2 == 0x83 and fm2 == 0x03ff9c and fs3 == 0 and fe3 == 0xe4 and fm3 == 0x0fffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7d783eca; op2val:0x4183ff9c;
op3val:0x720fffff; valaddr_reg:x3; val_offset:10236*0 + 3*340*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 10236*0 + 3*340*FLEN/8, x4, x1, x2)

inst_3413:
// fs1 == 0 and fe1 == 0xfa and fm1 == 0x783eca and fs2 == 0 and fe2 == 0x83 and fm2 == 0x03ff9c and fs3 == 0 and fe3 == 0xe4 and fm3 == 0x1fffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7d783eca; op2val:0x4183ff9c;
op3val:0x721fffff; valaddr_reg:x3; val_offset:10239*0 + 3*341*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 10239*0 + 3*341*FLEN/8, x4, x1, x2)

inst_3414:
// fs1 == 0 and fe1 == 0xfa and fm1 == 0x783eca and fs2 == 0 and fe2 == 0x83 and fm2 == 0x03ff9c and fs3 == 0 and fe3 == 0xe4 and fm3 == 0x3fffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7d783eca; op2val:0x4183ff9c;
op3val:0x723fffff; valaddr_reg:x3; val_offset:10242*0 + 3*342*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 10242*0 + 3*342*FLEN/8, x4, x1, x2)

inst_3415:
// fs1 == 0 and fe1 == 0xfa and fm1 == 0x783eca and fs2 == 0 and fe2 == 0x83 and fm2 == 0x03ff9c and fs3 == 0 and fe3 == 0xe4 and fm3 == 0x400000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7d783eca; op2val:0x4183ff9c;
op3val:0x72400000; valaddr_reg:x3; val_offset:10245*0 + 3*343*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 10245*0 + 3*343*FLEN/8, x4, x1, x2)

inst_3416:
// fs1 == 0 and fe1 == 0xfa and fm1 == 0x783eca and fs2 == 0 and fe2 == 0x83 and fm2 == 0x03ff9c and fs3 == 0 and fe3 == 0xe4 and fm3 == 0x600000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7d783eca; op2val:0x4183ff9c;
op3val:0x72600000; valaddr_reg:x3; val_offset:10248*0 + 3*344*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 10248*0 + 3*344*FLEN/8, x4, x1, x2)

inst_3417:
// fs1 == 0 and fe1 == 0xfa and fm1 == 0x783eca and fs2 == 0 and fe2 == 0x83 and fm2 == 0x03ff9c and fs3 == 0 and fe3 == 0xe4 and fm3 == 0x700000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7d783eca; op2val:0x4183ff9c;
op3val:0x72700000; valaddr_reg:x3; val_offset:10251*0 + 3*345*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 10251*0 + 3*345*FLEN/8, x4, x1, x2)

inst_3418:
// fs1 == 0 and fe1 == 0xfa and fm1 == 0x783eca and fs2 == 0 and fe2 == 0x83 and fm2 == 0x03ff9c and fs3 == 0 and fe3 == 0xe4 and fm3 == 0x780000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7d783eca; op2val:0x4183ff9c;
op3val:0x72780000; valaddr_reg:x3; val_offset:10254*0 + 3*346*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 10254*0 + 3*346*FLEN/8, x4, x1, x2)

inst_3419:
// fs1 == 0 and fe1 == 0xfa and fm1 == 0x783eca and fs2 == 0 and fe2 == 0x83 and fm2 == 0x03ff9c and fs3 == 0 and fe3 == 0xe4 and fm3 == 0x7c0000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7d783eca; op2val:0x4183ff9c;
op3val:0x727c0000; valaddr_reg:x3; val_offset:10257*0 + 3*347*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 10257*0 + 3*347*FLEN/8, x4, x1, x2)

inst_3420:
// fs1 == 0 and fe1 == 0xfa and fm1 == 0x783eca and fs2 == 0 and fe2 == 0x83 and fm2 == 0x03ff9c and fs3 == 0 and fe3 == 0xe4 and fm3 == 0x7e0000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7d783eca; op2val:0x4183ff9c;
op3val:0x727e0000; valaddr_reg:x3; val_offset:10260*0 + 3*348*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 10260*0 + 3*348*FLEN/8, x4, x1, x2)

inst_3421:
// fs1 == 0 and fe1 == 0xfa and fm1 == 0x783eca and fs2 == 0 and fe2 == 0x83 and fm2 == 0x03ff9c and fs3 == 0 and fe3 == 0xe4 and fm3 == 0x7f0000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7d783eca; op2val:0x4183ff9c;
op3val:0x727f0000; valaddr_reg:x3; val_offset:10263*0 + 3*349*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 10263*0 + 3*349*FLEN/8, x4, x1, x2)

inst_3422:
// fs1 == 0 and fe1 == 0xfa and fm1 == 0x783eca and fs2 == 0 and fe2 == 0x83 and fm2 == 0x03ff9c and fs3 == 0 and fe3 == 0xe4 and fm3 == 0x7f8000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7d783eca; op2val:0x4183ff9c;
op3val:0x727f8000; valaddr_reg:x3; val_offset:10266*0 + 3*350*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 10266*0 + 3*350*FLEN/8, x4, x1, x2)

inst_3423:
// fs1 == 0 and fe1 == 0xfa and fm1 == 0x783eca and fs2 == 0 and fe2 == 0x83 and fm2 == 0x03ff9c and fs3 == 0 and fe3 == 0xe4 and fm3 == 0x7fc000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7d783eca; op2val:0x4183ff9c;
op3val:0x727fc000; valaddr_reg:x3; val_offset:10269*0 + 3*351*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 10269*0 + 3*351*FLEN/8, x4, x1, x2)

inst_3424:
// fs1 == 0 and fe1 == 0xfa and fm1 == 0x783eca and fs2 == 0 and fe2 == 0x83 and fm2 == 0x03ff9c and fs3 == 0 and fe3 == 0xe4 and fm3 == 0x7fe000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7d783eca; op2val:0x4183ff9c;
op3val:0x727fe000; valaddr_reg:x3; val_offset:10272*0 + 3*352*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 10272*0 + 3*352*FLEN/8, x4, x1, x2)

inst_3425:
// fs1 == 0 and fe1 == 0xfa and fm1 == 0x783eca and fs2 == 0 and fe2 == 0x83 and fm2 == 0x03ff9c and fs3 == 0 and fe3 == 0xe4 and fm3 == 0x7ff000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7d783eca; op2val:0x4183ff9c;
op3val:0x727ff000; valaddr_reg:x3; val_offset:10275*0 + 3*353*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 10275*0 + 3*353*FLEN/8, x4, x1, x2)

inst_3426:
// fs1 == 0 and fe1 == 0xfa and fm1 == 0x783eca and fs2 == 0 and fe2 == 0x83 and fm2 == 0x03ff9c and fs3 == 0 and fe3 == 0xe4 and fm3 == 0x7ff800 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7d783eca; op2val:0x4183ff9c;
op3val:0x727ff800; valaddr_reg:x3; val_offset:10278*0 + 3*354*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 10278*0 + 3*354*FLEN/8, x4, x1, x2)

inst_3427:
// fs1 == 0 and fe1 == 0xfa and fm1 == 0x783eca and fs2 == 0 and fe2 == 0x83 and fm2 == 0x03ff9c and fs3 == 0 and fe3 == 0xe4 and fm3 == 0x7ffc00 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7d783eca; op2val:0x4183ff9c;
op3val:0x727ffc00; valaddr_reg:x3; val_offset:10281*0 + 3*355*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 10281*0 + 3*355*FLEN/8, x4, x1, x2)

inst_3428:
// fs1 == 0 and fe1 == 0xfa and fm1 == 0x783eca and fs2 == 0 and fe2 == 0x83 and fm2 == 0x03ff9c and fs3 == 0 and fe3 == 0xe4 and fm3 == 0x7ffe00 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7d783eca; op2val:0x4183ff9c;
op3val:0x727ffe00; valaddr_reg:x3; val_offset:10284*0 + 3*356*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 10284*0 + 3*356*FLEN/8, x4, x1, x2)

inst_3429:
// fs1 == 0 and fe1 == 0xfa and fm1 == 0x783eca and fs2 == 0 and fe2 == 0x83 and fm2 == 0x03ff9c and fs3 == 0 and fe3 == 0xe4 and fm3 == 0x7fff00 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7d783eca; op2val:0x4183ff9c;
op3val:0x727fff00; valaddr_reg:x3; val_offset:10287*0 + 3*357*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 10287*0 + 3*357*FLEN/8, x4, x1, x2)

inst_3430:
// fs1 == 0 and fe1 == 0xfa and fm1 == 0x783eca and fs2 == 0 and fe2 == 0x83 and fm2 == 0x03ff9c and fs3 == 0 and fe3 == 0xe4 and fm3 == 0x7fff80 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7d783eca; op2val:0x4183ff9c;
op3val:0x727fff80; valaddr_reg:x3; val_offset:10290*0 + 3*358*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 10290*0 + 3*358*FLEN/8, x4, x1, x2)

inst_3431:
// fs1 == 0 and fe1 == 0xfa and fm1 == 0x783eca and fs2 == 0 and fe2 == 0x83 and fm2 == 0x03ff9c and fs3 == 0 and fe3 == 0xe4 and fm3 == 0x7fffc0 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7d783eca; op2val:0x4183ff9c;
op3val:0x727fffc0; valaddr_reg:x3; val_offset:10293*0 + 3*359*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 10293*0 + 3*359*FLEN/8, x4, x1, x2)

inst_3432:
// fs1 == 0 and fe1 == 0xfa and fm1 == 0x783eca and fs2 == 0 and fe2 == 0x83 and fm2 == 0x03ff9c and fs3 == 0 and fe3 == 0xe4 and fm3 == 0x7fffe0 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7d783eca; op2val:0x4183ff9c;
op3val:0x727fffe0; valaddr_reg:x3; val_offset:10296*0 + 3*360*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 10296*0 + 3*360*FLEN/8, x4, x1, x2)

inst_3433:
// fs1 == 0 and fe1 == 0xfa and fm1 == 0x783eca and fs2 == 0 and fe2 == 0x83 and fm2 == 0x03ff9c and fs3 == 0 and fe3 == 0xe4 and fm3 == 0x7ffff0 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7d783eca; op2val:0x4183ff9c;
op3val:0x727ffff0; valaddr_reg:x3; val_offset:10299*0 + 3*361*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 10299*0 + 3*361*FLEN/8, x4, x1, x2)

inst_3434:
// fs1 == 0 and fe1 == 0xfa and fm1 == 0x783eca and fs2 == 0 and fe2 == 0x83 and fm2 == 0x03ff9c and fs3 == 0 and fe3 == 0xe4 and fm3 == 0x7ffff8 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7d783eca; op2val:0x4183ff9c;
op3val:0x727ffff8; valaddr_reg:x3; val_offset:10302*0 + 3*362*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 10302*0 + 3*362*FLEN/8, x4, x1, x2)

inst_3435:
// fs1 == 0 and fe1 == 0xfa and fm1 == 0x783eca and fs2 == 0 and fe2 == 0x83 and fm2 == 0x03ff9c and fs3 == 0 and fe3 == 0xe4 and fm3 == 0x7ffffc and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7d783eca; op2val:0x4183ff9c;
op3val:0x727ffffc; valaddr_reg:x3; val_offset:10305*0 + 3*363*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 10305*0 + 3*363*FLEN/8, x4, x1, x2)

inst_3436:
// fs1 == 0 and fe1 == 0xfa and fm1 == 0x783eca and fs2 == 0 and fe2 == 0x83 and fm2 == 0x03ff9c and fs3 == 0 and fe3 == 0xe4 and fm3 == 0x7ffffe and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7d783eca; op2val:0x4183ff9c;
op3val:0x727ffffe; valaddr_reg:x3; val_offset:10308*0 + 3*364*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 10308*0 + 3*364*FLEN/8, x4, x1, x2)

inst_3437:
// fs1 == 0 and fe1 == 0xfa and fm1 == 0x783eca and fs2 == 0 and fe2 == 0x83 and fm2 == 0x03ff9c and fs3 == 0 and fe3 == 0xe4 and fm3 == 0x7fffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7d783eca; op2val:0x4183ff9c;
op3val:0x727fffff; valaddr_reg:x3; val_offset:10311*0 + 3*365*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 10311*0 + 3*365*FLEN/8, x4, x1, x2)

inst_3438:
// fs1 == 0 and fe1 == 0xfa and fm1 == 0x783eca and fs2 == 0 and fe2 == 0x83 and fm2 == 0x03ff9c and fs3 == 0 and fe3 == 0xfe and fm3 == 0x000001 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7d783eca; op2val:0x4183ff9c;
op3val:0x7f000001; valaddr_reg:x3; val_offset:10314*0 + 3*366*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 10314*0 + 3*366*FLEN/8, x4, x1, x2)

inst_3439:
// fs1 == 0 and fe1 == 0xfa and fm1 == 0x783eca and fs2 == 0 and fe2 == 0x83 and fm2 == 0x03ff9c and fs3 == 0 and fe3 == 0xfe and fm3 == 0x000003 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7d783eca; op2val:0x4183ff9c;
op3val:0x7f000003; valaddr_reg:x3; val_offset:10317*0 + 3*367*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 10317*0 + 3*367*FLEN/8, x4, x1, x2)

inst_3440:
// fs1 == 0 and fe1 == 0xfa and fm1 == 0x783eca and fs2 == 0 and fe2 == 0x83 and fm2 == 0x03ff9c and fs3 == 0 and fe3 == 0xfe and fm3 == 0x000007 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7d783eca; op2val:0x4183ff9c;
op3val:0x7f000007; valaddr_reg:x3; val_offset:10320*0 + 3*368*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 10320*0 + 3*368*FLEN/8, x4, x1, x2)

inst_3441:
// fs1 == 0 and fe1 == 0xfa and fm1 == 0x783eca and fs2 == 0 and fe2 == 0x83 and fm2 == 0x03ff9c and fs3 == 0 and fe3 == 0xfe and fm3 == 0x199999 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7d783eca; op2val:0x4183ff9c;
op3val:0x7f199999; valaddr_reg:x3; val_offset:10323*0 + 3*369*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 10323*0 + 3*369*FLEN/8, x4, x1, x2)

inst_3442:
// fs1 == 0 and fe1 == 0xfa and fm1 == 0x783eca and fs2 == 0 and fe2 == 0x83 and fm2 == 0x03ff9c and fs3 == 0 and fe3 == 0xfe and fm3 == 0x249249 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7d783eca; op2val:0x4183ff9c;
op3val:0x7f249249; valaddr_reg:x3; val_offset:10326*0 + 3*370*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 10326*0 + 3*370*FLEN/8, x4, x1, x2)

inst_3443:
// fs1 == 0 and fe1 == 0xfa and fm1 == 0x783eca and fs2 == 0 and fe2 == 0x83 and fm2 == 0x03ff9c and fs3 == 0 and fe3 == 0xfe and fm3 == 0x333333 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7d783eca; op2val:0x4183ff9c;
op3val:0x7f333333; valaddr_reg:x3; val_offset:10329*0 + 3*371*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 10329*0 + 3*371*FLEN/8, x4, x1, x2)

inst_3444:
// fs1 == 0 and fe1 == 0xfa and fm1 == 0x783eca and fs2 == 0 and fe2 == 0x83 and fm2 == 0x03ff9c and fs3 == 0 and fe3 == 0xfe and fm3 == 0x36db6d and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7d783eca; op2val:0x4183ff9c;
op3val:0x7f36db6d; valaddr_reg:x3; val_offset:10332*0 + 3*372*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 10332*0 + 3*372*FLEN/8, x4, x1, x2)

inst_3445:
// fs1 == 0 and fe1 == 0xfa and fm1 == 0x783eca and fs2 == 0 and fe2 == 0x83 and fm2 == 0x03ff9c and fs3 == 0 and fe3 == 0xfe and fm3 == 0x3bbbbb and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7d783eca; op2val:0x4183ff9c;
op3val:0x7f3bbbbb; valaddr_reg:x3; val_offset:10335*0 + 3*373*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 10335*0 + 3*373*FLEN/8, x4, x1, x2)

inst_3446:
// fs1 == 0 and fe1 == 0xfa and fm1 == 0x783eca and fs2 == 0 and fe2 == 0x83 and fm2 == 0x03ff9c and fs3 == 0 and fe3 == 0xfe and fm3 == 0x444444 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7d783eca; op2val:0x4183ff9c;
op3val:0x7f444444; valaddr_reg:x3; val_offset:10338*0 + 3*374*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 10338*0 + 3*374*FLEN/8, x4, x1, x2)

inst_3447:
// fs1 == 0 and fe1 == 0xfa and fm1 == 0x783eca and fs2 == 0 and fe2 == 0x83 and fm2 == 0x03ff9c and fs3 == 0 and fe3 == 0xfe and fm3 == 0x4ccccc and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7d783eca; op2val:0x4183ff9c;
op3val:0x7f4ccccc; valaddr_reg:x3; val_offset:10341*0 + 3*375*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 10341*0 + 3*375*FLEN/8, x4, x1, x2)

inst_3448:
// fs1 == 0 and fe1 == 0xfa and fm1 == 0x783eca and fs2 == 0 and fe2 == 0x83 and fm2 == 0x03ff9c and fs3 == 0 and fe3 == 0xfe and fm3 == 0x5b6db6 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7d783eca; op2val:0x4183ff9c;
op3val:0x7f5b6db6; valaddr_reg:x3; val_offset:10344*0 + 3*376*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 10344*0 + 3*376*FLEN/8, x4, x1, x2)

inst_3449:
// fs1 == 0 and fe1 == 0xfa and fm1 == 0x783eca and fs2 == 0 and fe2 == 0x83 and fm2 == 0x03ff9c and fs3 == 0 and fe3 == 0xfe and fm3 == 0x666666 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7d783eca; op2val:0x4183ff9c;
op3val:0x7f666666; valaddr_reg:x3; val_offset:10347*0 + 3*377*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 10347*0 + 3*377*FLEN/8, x4, x1, x2)

inst_3450:
// fs1 == 0 and fe1 == 0xfa and fm1 == 0x783eca and fs2 == 0 and fe2 == 0x83 and fm2 == 0x03ff9c and fs3 == 0 and fe3 == 0xfe and fm3 == 0x6db6db and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7d783eca; op2val:0x4183ff9c;
op3val:0x7f6db6db; valaddr_reg:x3; val_offset:10350*0 + 3*378*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 10350*0 + 3*378*FLEN/8, x4, x1, x2)

inst_3451:
// fs1 == 0 and fe1 == 0xfa and fm1 == 0x783eca and fs2 == 0 and fe2 == 0x83 and fm2 == 0x03ff9c and fs3 == 0 and fe3 == 0xfe and fm3 == 0x7ffff8 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7d783eca; op2val:0x4183ff9c;
op3val:0x7f7ffff8; valaddr_reg:x3; val_offset:10353*0 + 3*379*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 10353*0 + 3*379*FLEN/8, x4, x1, x2)

inst_3452:
// fs1 == 0 and fe1 == 0xfa and fm1 == 0x783eca and fs2 == 0 and fe2 == 0x83 and fm2 == 0x03ff9c and fs3 == 0 and fe3 == 0xfe and fm3 == 0x7ffffc and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7d783eca; op2val:0x4183ff9c;
op3val:0x7f7ffffc; valaddr_reg:x3; val_offset:10356*0 + 3*380*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 10356*0 + 3*380*FLEN/8, x4, x1, x2)

inst_3453:
// fs1 == 0 and fe1 == 0xfa and fm1 == 0x783eca and fs2 == 0 and fe2 == 0x83 and fm2 == 0x03ff9c and fs3 == 0 and fe3 == 0xfe and fm3 == 0x7ffffe and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7d783eca; op2val:0x4183ff9c;
op3val:0x7f7ffffe; valaddr_reg:x3; val_offset:10359*0 + 3*381*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 10359*0 + 3*381*FLEN/8, x4, x1, x2)

inst_3454:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x0081b9 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000001 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7d8081b9; op2val:0x80000000;
op3val:0x80000001; valaddr_reg:x3; val_offset:10362*0 + 3*382*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 10362*0 + 3*382*FLEN/8, x4, x1, x2)

inst_3455:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x0081b9 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000003 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7d8081b9; op2val:0x80000000;
op3val:0x80000003; valaddr_reg:x3; val_offset:10365*0 + 3*383*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 10365*0 + 3*383*FLEN/8, x4, x1, x2)
RVTEST_SIGBASE(x1,signature_x1_4)

inst_3456:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x0081b9 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000007 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7d8081b9; op2val:0x80000000;
op3val:0x80000007; valaddr_reg:x3; val_offset:10368*0 + 3*384*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 10368*0 + 3*384*FLEN/8, x4, x1, x2)

inst_3457:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x0081b9 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x199999 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7d8081b9; op2val:0x80000000;
op3val:0x80199999; valaddr_reg:x3; val_offset:10371*0 + 3*385*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 10371*0 + 3*385*FLEN/8, x4, x1, x2)

inst_3458:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x0081b9 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x249249 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7d8081b9; op2val:0x80000000;
op3val:0x80249249; valaddr_reg:x3; val_offset:10374*0 + 3*386*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 10374*0 + 3*386*FLEN/8, x4, x1, x2)

inst_3459:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x0081b9 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x333333 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7d8081b9; op2val:0x80000000;
op3val:0x80333333; valaddr_reg:x3; val_offset:10377*0 + 3*387*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 10377*0 + 3*387*FLEN/8, x4, x1, x2)

inst_3460:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x0081b9 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x36db6d and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7d8081b9; op2val:0x80000000;
op3val:0x8036db6d; valaddr_reg:x3; val_offset:10380*0 + 3*388*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 10380*0 + 3*388*FLEN/8, x4, x1, x2)

inst_3461:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x0081b9 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3bbbbb and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7d8081b9; op2val:0x80000000;
op3val:0x803bbbbb; valaddr_reg:x3; val_offset:10383*0 + 3*389*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 10383*0 + 3*389*FLEN/8, x4, x1, x2)

inst_3462:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x0081b9 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x444444 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7d8081b9; op2val:0x80000000;
op3val:0x80444444; valaddr_reg:x3; val_offset:10386*0 + 3*390*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 10386*0 + 3*390*FLEN/8, x4, x1, x2)

inst_3463:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x0081b9 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x4ccccc and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7d8081b9; op2val:0x80000000;
op3val:0x804ccccc; valaddr_reg:x3; val_offset:10389*0 + 3*391*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 10389*0 + 3*391*FLEN/8, x4, x1, x2)

inst_3464:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x0081b9 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x5b6db6 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7d8081b9; op2val:0x80000000;
op3val:0x805b6db6; valaddr_reg:x3; val_offset:10392*0 + 3*392*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 10392*0 + 3*392*FLEN/8, x4, x1, x2)

inst_3465:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x0081b9 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x666666 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7d8081b9; op2val:0x80000000;
op3val:0x80666666; valaddr_reg:x3; val_offset:10395*0 + 3*393*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 10395*0 + 3*393*FLEN/8, x4, x1, x2)

inst_3466:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x0081b9 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x6db6db and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7d8081b9; op2val:0x80000000;
op3val:0x806db6db; valaddr_reg:x3; val_offset:10398*0 + 3*394*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 10398*0 + 3*394*FLEN/8, x4, x1, x2)

inst_3467:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x0081b9 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7ffff8 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7d8081b9; op2val:0x80000000;
op3val:0x807ffff8; valaddr_reg:x3; val_offset:10401*0 + 3*395*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 10401*0 + 3*395*FLEN/8, x4, x1, x2)

inst_3468:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x0081b9 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7ffffc and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7d8081b9; op2val:0x80000000;
op3val:0x807ffffc; valaddr_reg:x3; val_offset:10404*0 + 3*396*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 10404*0 + 3*396*FLEN/8, x4, x1, x2)

inst_3469:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x0081b9 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7ffffe and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7d8081b9; op2val:0x80000000;
op3val:0x807ffffe; valaddr_reg:x3; val_offset:10407*0 + 3*397*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 10407*0 + 3*397*FLEN/8, x4, x1, x2)

inst_3470:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x0081b9 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x06 and fm3 == 0x000000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7d8081b9; op2val:0x80000000;
op3val:0x83000000; valaddr_reg:x3; val_offset:10410*0 + 3*398*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 10410*0 + 3*398*FLEN/8, x4, x1, x2)

inst_3471:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x0081b9 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x06 and fm3 == 0x000001 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7d8081b9; op2val:0x80000000;
op3val:0x83000001; valaddr_reg:x3; val_offset:10413*0 + 3*399*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 10413*0 + 3*399*FLEN/8, x4, x1, x2)

inst_3472:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x0081b9 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x06 and fm3 == 0x000003 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7d8081b9; op2val:0x80000000;
op3val:0x83000003; valaddr_reg:x3; val_offset:10416*0 + 3*400*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 10416*0 + 3*400*FLEN/8, x4, x1, x2)

inst_3473:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x0081b9 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x06 and fm3 == 0x000007 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7d8081b9; op2val:0x80000000;
op3val:0x83000007; valaddr_reg:x3; val_offset:10419*0 + 3*401*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 10419*0 + 3*401*FLEN/8, x4, x1, x2)

inst_3474:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x0081b9 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x06 and fm3 == 0x00000f and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7d8081b9; op2val:0x80000000;
op3val:0x8300000f; valaddr_reg:x3; val_offset:10422*0 + 3*402*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 10422*0 + 3*402*FLEN/8, x4, x1, x2)

inst_3475:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x0081b9 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x06 and fm3 == 0x00001f and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7d8081b9; op2val:0x80000000;
op3val:0x8300001f; valaddr_reg:x3; val_offset:10425*0 + 3*403*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 10425*0 + 3*403*FLEN/8, x4, x1, x2)

inst_3476:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x0081b9 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x06 and fm3 == 0x00003f and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7d8081b9; op2val:0x80000000;
op3val:0x8300003f; valaddr_reg:x3; val_offset:10428*0 + 3*404*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 10428*0 + 3*404*FLEN/8, x4, x1, x2)

inst_3477:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x0081b9 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x06 and fm3 == 0x00007f and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7d8081b9; op2val:0x80000000;
op3val:0x8300007f; valaddr_reg:x3; val_offset:10431*0 + 3*405*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 10431*0 + 3*405*FLEN/8, x4, x1, x2)

inst_3478:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x0081b9 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x06 and fm3 == 0x0000ff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7d8081b9; op2val:0x80000000;
op3val:0x830000ff; valaddr_reg:x3; val_offset:10434*0 + 3*406*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 10434*0 + 3*406*FLEN/8, x4, x1, x2)

inst_3479:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x0081b9 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x06 and fm3 == 0x0001ff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7d8081b9; op2val:0x80000000;
op3val:0x830001ff; valaddr_reg:x3; val_offset:10437*0 + 3*407*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 10437*0 + 3*407*FLEN/8, x4, x1, x2)

inst_3480:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x0081b9 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x06 and fm3 == 0x0003ff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7d8081b9; op2val:0x80000000;
op3val:0x830003ff; valaddr_reg:x3; val_offset:10440*0 + 3*408*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 10440*0 + 3*408*FLEN/8, x4, x1, x2)

inst_3481:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x0081b9 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x06 and fm3 == 0x0007ff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7d8081b9; op2val:0x80000000;
op3val:0x830007ff; valaddr_reg:x3; val_offset:10443*0 + 3*409*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 10443*0 + 3*409*FLEN/8, x4, x1, x2)

inst_3482:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x0081b9 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x06 and fm3 == 0x000fff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7d8081b9; op2val:0x80000000;
op3val:0x83000fff; valaddr_reg:x3; val_offset:10446*0 + 3*410*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 10446*0 + 3*410*FLEN/8, x4, x1, x2)

inst_3483:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x0081b9 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x06 and fm3 == 0x001fff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7d8081b9; op2val:0x80000000;
op3val:0x83001fff; valaddr_reg:x3; val_offset:10449*0 + 3*411*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 10449*0 + 3*411*FLEN/8, x4, x1, x2)

inst_3484:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x0081b9 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x06 and fm3 == 0x003fff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7d8081b9; op2val:0x80000000;
op3val:0x83003fff; valaddr_reg:x3; val_offset:10452*0 + 3*412*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 10452*0 + 3*412*FLEN/8, x4, x1, x2)

inst_3485:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x0081b9 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x06 and fm3 == 0x007fff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7d8081b9; op2val:0x80000000;
op3val:0x83007fff; valaddr_reg:x3; val_offset:10455*0 + 3*413*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 10455*0 + 3*413*FLEN/8, x4, x1, x2)

inst_3486:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x0081b9 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x06 and fm3 == 0x00ffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7d8081b9; op2val:0x80000000;
op3val:0x8300ffff; valaddr_reg:x3; val_offset:10458*0 + 3*414*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 10458*0 + 3*414*FLEN/8, x4, x1, x2)

inst_3487:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x0081b9 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x06 and fm3 == 0x01ffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7d8081b9; op2val:0x80000000;
op3val:0x8301ffff; valaddr_reg:x3; val_offset:10461*0 + 3*415*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 10461*0 + 3*415*FLEN/8, x4, x1, x2)

inst_3488:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x0081b9 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x06 and fm3 == 0x03ffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7d8081b9; op2val:0x80000000;
op3val:0x8303ffff; valaddr_reg:x3; val_offset:10464*0 + 3*416*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 10464*0 + 3*416*FLEN/8, x4, x1, x2)

inst_3489:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x0081b9 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x06 and fm3 == 0x07ffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7d8081b9; op2val:0x80000000;
op3val:0x8307ffff; valaddr_reg:x3; val_offset:10467*0 + 3*417*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 10467*0 + 3*417*FLEN/8, x4, x1, x2)

inst_3490:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x0081b9 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x06 and fm3 == 0x0fffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7d8081b9; op2val:0x80000000;
op3val:0x830fffff; valaddr_reg:x3; val_offset:10470*0 + 3*418*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 10470*0 + 3*418*FLEN/8, x4, x1, x2)

inst_3491:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x0081b9 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x06 and fm3 == 0x1fffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7d8081b9; op2val:0x80000000;
op3val:0x831fffff; valaddr_reg:x3; val_offset:10473*0 + 3*419*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 10473*0 + 3*419*FLEN/8, x4, x1, x2)

inst_3492:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x0081b9 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x06 and fm3 == 0x3fffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7d8081b9; op2val:0x80000000;
op3val:0x833fffff; valaddr_reg:x3; val_offset:10476*0 + 3*420*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 10476*0 + 3*420*FLEN/8, x4, x1, x2)

inst_3493:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x0081b9 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x06 and fm3 == 0x400000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7d8081b9; op2val:0x80000000;
op3val:0x83400000; valaddr_reg:x3; val_offset:10479*0 + 3*421*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 10479*0 + 3*421*FLEN/8, x4, x1, x2)

inst_3494:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x0081b9 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x06 and fm3 == 0x600000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7d8081b9; op2val:0x80000000;
op3val:0x83600000; valaddr_reg:x3; val_offset:10482*0 + 3*422*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 10482*0 + 3*422*FLEN/8, x4, x1, x2)

inst_3495:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x0081b9 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x06 and fm3 == 0x700000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7d8081b9; op2val:0x80000000;
op3val:0x83700000; valaddr_reg:x3; val_offset:10485*0 + 3*423*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 10485*0 + 3*423*FLEN/8, x4, x1, x2)

inst_3496:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x0081b9 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x06 and fm3 == 0x780000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7d8081b9; op2val:0x80000000;
op3val:0x83780000; valaddr_reg:x3; val_offset:10488*0 + 3*424*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 10488*0 + 3*424*FLEN/8, x4, x1, x2)

inst_3497:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x0081b9 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x06 and fm3 == 0x7c0000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7d8081b9; op2val:0x80000000;
op3val:0x837c0000; valaddr_reg:x3; val_offset:10491*0 + 3*425*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 10491*0 + 3*425*FLEN/8, x4, x1, x2)

inst_3498:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x0081b9 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x06 and fm3 == 0x7e0000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7d8081b9; op2val:0x80000000;
op3val:0x837e0000; valaddr_reg:x3; val_offset:10494*0 + 3*426*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 10494*0 + 3*426*FLEN/8, x4, x1, x2)

inst_3499:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x0081b9 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x06 and fm3 == 0x7f0000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7d8081b9; op2val:0x80000000;
op3val:0x837f0000; valaddr_reg:x3; val_offset:10497*0 + 3*427*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 10497*0 + 3*427*FLEN/8, x4, x1, x2)

inst_3500:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x0081b9 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x06 and fm3 == 0x7f8000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7d8081b9; op2val:0x80000000;
op3val:0x837f8000; valaddr_reg:x3; val_offset:10500*0 + 3*428*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 10500*0 + 3*428*FLEN/8, x4, x1, x2)

inst_3501:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x0081b9 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x06 and fm3 == 0x7fc000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7d8081b9; op2val:0x80000000;
op3val:0x837fc000; valaddr_reg:x3; val_offset:10503*0 + 3*429*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 10503*0 + 3*429*FLEN/8, x4, x1, x2)

inst_3502:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x0081b9 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x06 and fm3 == 0x7fe000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7d8081b9; op2val:0x80000000;
op3val:0x837fe000; valaddr_reg:x3; val_offset:10506*0 + 3*430*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 10506*0 + 3*430*FLEN/8, x4, x1, x2)

inst_3503:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x0081b9 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x06 and fm3 == 0x7ff000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7d8081b9; op2val:0x80000000;
op3val:0x837ff000; valaddr_reg:x3; val_offset:10509*0 + 3*431*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 10509*0 + 3*431*FLEN/8, x4, x1, x2)

inst_3504:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x0081b9 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x06 and fm3 == 0x7ff800 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7d8081b9; op2val:0x80000000;
op3val:0x837ff800; valaddr_reg:x3; val_offset:10512*0 + 3*432*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 10512*0 + 3*432*FLEN/8, x4, x1, x2)

inst_3505:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x0081b9 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x06 and fm3 == 0x7ffc00 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7d8081b9; op2val:0x80000000;
op3val:0x837ffc00; valaddr_reg:x3; val_offset:10515*0 + 3*433*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 10515*0 + 3*433*FLEN/8, x4, x1, x2)

inst_3506:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x0081b9 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x06 and fm3 == 0x7ffe00 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7d8081b9; op2val:0x80000000;
op3val:0x837ffe00; valaddr_reg:x3; val_offset:10518*0 + 3*434*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 10518*0 + 3*434*FLEN/8, x4, x1, x2)

inst_3507:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x0081b9 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x06 and fm3 == 0x7fff00 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7d8081b9; op2val:0x80000000;
op3val:0x837fff00; valaddr_reg:x3; val_offset:10521*0 + 3*435*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 10521*0 + 3*435*FLEN/8, x4, x1, x2)

inst_3508:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x0081b9 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x06 and fm3 == 0x7fff80 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7d8081b9; op2val:0x80000000;
op3val:0x837fff80; valaddr_reg:x3; val_offset:10524*0 + 3*436*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 10524*0 + 3*436*FLEN/8, x4, x1, x2)

inst_3509:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x0081b9 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x06 and fm3 == 0x7fffc0 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7d8081b9; op2val:0x80000000;
op3val:0x837fffc0; valaddr_reg:x3; val_offset:10527*0 + 3*437*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 10527*0 + 3*437*FLEN/8, x4, x1, x2)

inst_3510:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x0081b9 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x06 and fm3 == 0x7fffe0 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7d8081b9; op2val:0x80000000;
op3val:0x837fffe0; valaddr_reg:x3; val_offset:10530*0 + 3*438*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 10530*0 + 3*438*FLEN/8, x4, x1, x2)

inst_3511:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x0081b9 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x06 and fm3 == 0x7ffff0 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7d8081b9; op2val:0x80000000;
op3val:0x837ffff0; valaddr_reg:x3; val_offset:10533*0 + 3*439*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 10533*0 + 3*439*FLEN/8, x4, x1, x2)

inst_3512:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x0081b9 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x06 and fm3 == 0x7ffff8 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7d8081b9; op2val:0x80000000;
op3val:0x837ffff8; valaddr_reg:x3; val_offset:10536*0 + 3*440*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 10536*0 + 3*440*FLEN/8, x4, x1, x2)

inst_3513:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x0081b9 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x06 and fm3 == 0x7ffffc and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7d8081b9; op2val:0x80000000;
op3val:0x837ffffc; valaddr_reg:x3; val_offset:10539*0 + 3*441*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 10539*0 + 3*441*FLEN/8, x4, x1, x2)

inst_3514:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x0081b9 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x06 and fm3 == 0x7ffffe and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7d8081b9; op2val:0x80000000;
op3val:0x837ffffe; valaddr_reg:x3; val_offset:10542*0 + 3*442*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 10542*0 + 3*442*FLEN/8, x4, x1, x2)

inst_3515:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x0081b9 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x06 and fm3 == 0x7fffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7d8081b9; op2val:0x80000000;
op3val:0x837fffff; valaddr_reg:x3; val_offset:10545*0 + 3*443*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 10545*0 + 3*443*FLEN/8, x4, x1, x2)

inst_3516:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x020308 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000001 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7d820308; op2val:0x0;
op3val:0x1; valaddr_reg:x3; val_offset:10548*0 + 3*444*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 10548*0 + 3*444*FLEN/8, x4, x1, x2)

inst_3517:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x020308 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000003 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7d820308; op2val:0x0;
op3val:0x3; valaddr_reg:x3; val_offset:10551*0 + 3*445*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 10551*0 + 3*445*FLEN/8, x4, x1, x2)

inst_3518:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x020308 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000007 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7d820308; op2val:0x0;
op3val:0x7; valaddr_reg:x3; val_offset:10554*0 + 3*446*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 10554*0 + 3*446*FLEN/8, x4, x1, x2)

inst_3519:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x020308 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x199999 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7d820308; op2val:0x0;
op3val:0x199999; valaddr_reg:x3; val_offset:10557*0 + 3*447*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 10557*0 + 3*447*FLEN/8, x4, x1, x2)

inst_3520:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x020308 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x249249 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7d820308; op2val:0x0;
op3val:0x249249; valaddr_reg:x3; val_offset:10560*0 + 3*448*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 10560*0 + 3*448*FLEN/8, x4, x1, x2)

inst_3521:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x020308 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x333333 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7d820308; op2val:0x0;
op3val:0x333333; valaddr_reg:x3; val_offset:10563*0 + 3*449*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 10563*0 + 3*449*FLEN/8, x4, x1, x2)

inst_3522:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x020308 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x36db6d and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7d820308; op2val:0x0;
op3val:0x36db6d; valaddr_reg:x3; val_offset:10566*0 + 3*450*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 10566*0 + 3*450*FLEN/8, x4, x1, x2)

inst_3523:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x020308 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x3bbbbb and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7d820308; op2val:0x0;
op3val:0x3bbbbb; valaddr_reg:x3; val_offset:10569*0 + 3*451*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 10569*0 + 3*451*FLEN/8, x4, x1, x2)

inst_3524:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x020308 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x444444 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7d820308; op2val:0x0;
op3val:0x444444; valaddr_reg:x3; val_offset:10572*0 + 3*452*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 10572*0 + 3*452*FLEN/8, x4, x1, x2)

inst_3525:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x020308 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x4ccccc and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7d820308; op2val:0x0;
op3val:0x4ccccc; valaddr_reg:x3; val_offset:10575*0 + 3*453*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 10575*0 + 3*453*FLEN/8, x4, x1, x2)

inst_3526:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x020308 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x5b6db6 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7d820308; op2val:0x0;
op3val:0x5b6db6; valaddr_reg:x3; val_offset:10578*0 + 3*454*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 10578*0 + 3*454*FLEN/8, x4, x1, x2)

inst_3527:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x020308 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x666666 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7d820308; op2val:0x0;
op3val:0x666666; valaddr_reg:x3; val_offset:10581*0 + 3*455*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 10581*0 + 3*455*FLEN/8, x4, x1, x2)

inst_3528:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x020308 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x6db6db and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7d820308; op2val:0x0;
op3val:0x6db6db; valaddr_reg:x3; val_offset:10584*0 + 3*456*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 10584*0 + 3*456*FLEN/8, x4, x1, x2)

inst_3529:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x020308 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x7ffff8 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7d820308; op2val:0x0;
op3val:0x7ffff8; valaddr_reg:x3; val_offset:10587*0 + 3*457*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 10587*0 + 3*457*FLEN/8, x4, x1, x2)

inst_3530:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x020308 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x7ffffc and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7d820308; op2val:0x0;
op3val:0x7ffffc; valaddr_reg:x3; val_offset:10590*0 + 3*458*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 10590*0 + 3*458*FLEN/8, x4, x1, x2)

inst_3531:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x020308 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x7ffffe and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7d820308; op2val:0x0;
op3val:0x7ffffe; valaddr_reg:x3; val_offset:10593*0 + 3*459*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 10593*0 + 3*459*FLEN/8, x4, x1, x2)

inst_3532:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x020308 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x16 and fm3 == 0x000000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7d820308; op2val:0x0;
op3val:0xb000000; valaddr_reg:x3; val_offset:10596*0 + 3*460*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 10596*0 + 3*460*FLEN/8, x4, x1, x2)

inst_3533:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x020308 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x16 and fm3 == 0x000001 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7d820308; op2val:0x0;
op3val:0xb000001; valaddr_reg:x3; val_offset:10599*0 + 3*461*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 10599*0 + 3*461*FLEN/8, x4, x1, x2)

inst_3534:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x020308 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x16 and fm3 == 0x000003 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7d820308; op2val:0x0;
op3val:0xb000003; valaddr_reg:x3; val_offset:10602*0 + 3*462*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 10602*0 + 3*462*FLEN/8, x4, x1, x2)

inst_3535:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x020308 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x16 and fm3 == 0x000007 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7d820308; op2val:0x0;
op3val:0xb000007; valaddr_reg:x3; val_offset:10605*0 + 3*463*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 10605*0 + 3*463*FLEN/8, x4, x1, x2)

inst_3536:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x020308 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x16 and fm3 == 0x00000f and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7d820308; op2val:0x0;
op3val:0xb00000f; valaddr_reg:x3; val_offset:10608*0 + 3*464*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 10608*0 + 3*464*FLEN/8, x4, x1, x2)

inst_3537:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x020308 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x16 and fm3 == 0x00001f and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7d820308; op2val:0x0;
op3val:0xb00001f; valaddr_reg:x3; val_offset:10611*0 + 3*465*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 10611*0 + 3*465*FLEN/8, x4, x1, x2)

inst_3538:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x020308 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x16 and fm3 == 0x00003f and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7d820308; op2val:0x0;
op3val:0xb00003f; valaddr_reg:x3; val_offset:10614*0 + 3*466*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 10614*0 + 3*466*FLEN/8, x4, x1, x2)

inst_3539:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x020308 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x16 and fm3 == 0x00007f and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7d820308; op2val:0x0;
op3val:0xb00007f; valaddr_reg:x3; val_offset:10617*0 + 3*467*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 10617*0 + 3*467*FLEN/8, x4, x1, x2)

inst_3540:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x020308 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x16 and fm3 == 0x0000ff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7d820308; op2val:0x0;
op3val:0xb0000ff; valaddr_reg:x3; val_offset:10620*0 + 3*468*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 10620*0 + 3*468*FLEN/8, x4, x1, x2)

inst_3541:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x020308 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x16 and fm3 == 0x0001ff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7d820308; op2val:0x0;
op3val:0xb0001ff; valaddr_reg:x3; val_offset:10623*0 + 3*469*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 10623*0 + 3*469*FLEN/8, x4, x1, x2)

inst_3542:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x020308 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x16 and fm3 == 0x0003ff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7d820308; op2val:0x0;
op3val:0xb0003ff; valaddr_reg:x3; val_offset:10626*0 + 3*470*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 10626*0 + 3*470*FLEN/8, x4, x1, x2)

inst_3543:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x020308 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x16 and fm3 == 0x0007ff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7d820308; op2val:0x0;
op3val:0xb0007ff; valaddr_reg:x3; val_offset:10629*0 + 3*471*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 10629*0 + 3*471*FLEN/8, x4, x1, x2)

inst_3544:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x020308 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x16 and fm3 == 0x000fff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7d820308; op2val:0x0;
op3val:0xb000fff; valaddr_reg:x3; val_offset:10632*0 + 3*472*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 10632*0 + 3*472*FLEN/8, x4, x1, x2)

inst_3545:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x020308 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x16 and fm3 == 0x001fff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7d820308; op2val:0x0;
op3val:0xb001fff; valaddr_reg:x3; val_offset:10635*0 + 3*473*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 10635*0 + 3*473*FLEN/8, x4, x1, x2)

inst_3546:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x020308 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x16 and fm3 == 0x003fff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7d820308; op2val:0x0;
op3val:0xb003fff; valaddr_reg:x3; val_offset:10638*0 + 3*474*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 10638*0 + 3*474*FLEN/8, x4, x1, x2)

inst_3547:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x020308 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x16 and fm3 == 0x007fff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7d820308; op2val:0x0;
op3val:0xb007fff; valaddr_reg:x3; val_offset:10641*0 + 3*475*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 10641*0 + 3*475*FLEN/8, x4, x1, x2)

inst_3548:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x020308 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x16 and fm3 == 0x00ffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7d820308; op2val:0x0;
op3val:0xb00ffff; valaddr_reg:x3; val_offset:10644*0 + 3*476*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 10644*0 + 3*476*FLEN/8, x4, x1, x2)

inst_3549:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x020308 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x16 and fm3 == 0x01ffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7d820308; op2val:0x0;
op3val:0xb01ffff; valaddr_reg:x3; val_offset:10647*0 + 3*477*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 10647*0 + 3*477*FLEN/8, x4, x1, x2)

inst_3550:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x020308 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x16 and fm3 == 0x03ffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7d820308; op2val:0x0;
op3val:0xb03ffff; valaddr_reg:x3; val_offset:10650*0 + 3*478*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 10650*0 + 3*478*FLEN/8, x4, x1, x2)

inst_3551:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x020308 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x16 and fm3 == 0x07ffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7d820308; op2val:0x0;
op3val:0xb07ffff; valaddr_reg:x3; val_offset:10653*0 + 3*479*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 10653*0 + 3*479*FLEN/8, x4, x1, x2)

inst_3552:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x020308 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x16 and fm3 == 0x0fffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7d820308; op2val:0x0;
op3val:0xb0fffff; valaddr_reg:x3; val_offset:10656*0 + 3*480*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 10656*0 + 3*480*FLEN/8, x4, x1, x2)

inst_3553:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x020308 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x16 and fm3 == 0x1fffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7d820308; op2val:0x0;
op3val:0xb1fffff; valaddr_reg:x3; val_offset:10659*0 + 3*481*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 10659*0 + 3*481*FLEN/8, x4, x1, x2)

inst_3554:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x020308 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x16 and fm3 == 0x3fffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7d820308; op2val:0x0;
op3val:0xb3fffff; valaddr_reg:x3; val_offset:10662*0 + 3*482*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 10662*0 + 3*482*FLEN/8, x4, x1, x2)

inst_3555:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x020308 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x16 and fm3 == 0x400000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7d820308; op2val:0x0;
op3val:0xb400000; valaddr_reg:x3; val_offset:10665*0 + 3*483*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 10665*0 + 3*483*FLEN/8, x4, x1, x2)

inst_3556:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x020308 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x16 and fm3 == 0x600000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7d820308; op2val:0x0;
op3val:0xb600000; valaddr_reg:x3; val_offset:10668*0 + 3*484*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 10668*0 + 3*484*FLEN/8, x4, x1, x2)

inst_3557:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x020308 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x16 and fm3 == 0x700000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7d820308; op2val:0x0;
op3val:0xb700000; valaddr_reg:x3; val_offset:10671*0 + 3*485*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 10671*0 + 3*485*FLEN/8, x4, x1, x2)

inst_3558:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x020308 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x16 and fm3 == 0x780000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7d820308; op2val:0x0;
op3val:0xb780000; valaddr_reg:x3; val_offset:10674*0 + 3*486*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 10674*0 + 3*486*FLEN/8, x4, x1, x2)

inst_3559:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x020308 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x16 and fm3 == 0x7c0000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7d820308; op2val:0x0;
op3val:0xb7c0000; valaddr_reg:x3; val_offset:10677*0 + 3*487*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 10677*0 + 3*487*FLEN/8, x4, x1, x2)

inst_3560:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x020308 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x16 and fm3 == 0x7e0000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7d820308; op2val:0x0;
op3val:0xb7e0000; valaddr_reg:x3; val_offset:10680*0 + 3*488*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 10680*0 + 3*488*FLEN/8, x4, x1, x2)

inst_3561:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x020308 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x16 and fm3 == 0x7f0000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7d820308; op2val:0x0;
op3val:0xb7f0000; valaddr_reg:x3; val_offset:10683*0 + 3*489*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 10683*0 + 3*489*FLEN/8, x4, x1, x2)

inst_3562:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x020308 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x16 and fm3 == 0x7f8000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7d820308; op2val:0x0;
op3val:0xb7f8000; valaddr_reg:x3; val_offset:10686*0 + 3*490*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 10686*0 + 3*490*FLEN/8, x4, x1, x2)

inst_3563:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x020308 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x16 and fm3 == 0x7fc000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7d820308; op2val:0x0;
op3val:0xb7fc000; valaddr_reg:x3; val_offset:10689*0 + 3*491*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 10689*0 + 3*491*FLEN/8, x4, x1, x2)

inst_3564:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x020308 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x16 and fm3 == 0x7fe000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7d820308; op2val:0x0;
op3val:0xb7fe000; valaddr_reg:x3; val_offset:10692*0 + 3*492*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 10692*0 + 3*492*FLEN/8, x4, x1, x2)

inst_3565:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x020308 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x16 and fm3 == 0x7ff000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7d820308; op2val:0x0;
op3val:0xb7ff000; valaddr_reg:x3; val_offset:10695*0 + 3*493*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 10695*0 + 3*493*FLEN/8, x4, x1, x2)

inst_3566:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x020308 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x16 and fm3 == 0x7ff800 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7d820308; op2val:0x0;
op3val:0xb7ff800; valaddr_reg:x3; val_offset:10698*0 + 3*494*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 10698*0 + 3*494*FLEN/8, x4, x1, x2)

inst_3567:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x020308 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x16 and fm3 == 0x7ffc00 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7d820308; op2val:0x0;
op3val:0xb7ffc00; valaddr_reg:x3; val_offset:10701*0 + 3*495*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 10701*0 + 3*495*FLEN/8, x4, x1, x2)

inst_3568:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x020308 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x16 and fm3 == 0x7ffe00 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7d820308; op2val:0x0;
op3val:0xb7ffe00; valaddr_reg:x3; val_offset:10704*0 + 3*496*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 10704*0 + 3*496*FLEN/8, x4, x1, x2)

inst_3569:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x020308 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x16 and fm3 == 0x7fff00 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7d820308; op2val:0x0;
op3val:0xb7fff00; valaddr_reg:x3; val_offset:10707*0 + 3*497*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 10707*0 + 3*497*FLEN/8, x4, x1, x2)

inst_3570:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x020308 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x16 and fm3 == 0x7fff80 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7d820308; op2val:0x0;
op3val:0xb7fff80; valaddr_reg:x3; val_offset:10710*0 + 3*498*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 10710*0 + 3*498*FLEN/8, x4, x1, x2)

inst_3571:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x020308 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x16 and fm3 == 0x7fffc0 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7d820308; op2val:0x0;
op3val:0xb7fffc0; valaddr_reg:x3; val_offset:10713*0 + 3*499*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 10713*0 + 3*499*FLEN/8, x4, x1, x2)

inst_3572:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x020308 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x16 and fm3 == 0x7fffe0 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7d820308; op2val:0x0;
op3val:0xb7fffe0; valaddr_reg:x3; val_offset:10716*0 + 3*500*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 10716*0 + 3*500*FLEN/8, x4, x1, x2)

inst_3573:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x020308 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x16 and fm3 == 0x7ffff0 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7d820308; op2val:0x0;
op3val:0xb7ffff0; valaddr_reg:x3; val_offset:10719*0 + 3*501*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 10719*0 + 3*501*FLEN/8, x4, x1, x2)

inst_3574:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x020308 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x16 and fm3 == 0x7ffff8 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7d820308; op2val:0x0;
op3val:0xb7ffff8; valaddr_reg:x3; val_offset:10722*0 + 3*502*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 10722*0 + 3*502*FLEN/8, x4, x1, x2)

inst_3575:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x020308 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x16 and fm3 == 0x7ffffc and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7d820308; op2val:0x0;
op3val:0xb7ffffc; valaddr_reg:x3; val_offset:10725*0 + 3*503*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 10725*0 + 3*503*FLEN/8, x4, x1, x2)

inst_3576:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x020308 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x16 and fm3 == 0x7ffffe and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7d820308; op2val:0x0;
op3val:0xb7ffffe; valaddr_reg:x3; val_offset:10728*0 + 3*504*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 10728*0 + 3*504*FLEN/8, x4, x1, x2)

inst_3577:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x020308 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x16 and fm3 == 0x7fffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7d820308; op2val:0x0;
op3val:0xb7fffff; valaddr_reg:x3; val_offset:10731*0 + 3*505*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 10731*0 + 3*505*FLEN/8, x4, x1, x2)

inst_3578:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x020d6d and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000001 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7d820d6d; op2val:0x0;
op3val:0x1; valaddr_reg:x3; val_offset:10734*0 + 3*506*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 10734*0 + 3*506*FLEN/8, x4, x1, x2)

inst_3579:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x020d6d and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000003 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7d820d6d; op2val:0x0;
op3val:0x3; valaddr_reg:x3; val_offset:10737*0 + 3*507*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 10737*0 + 3*507*FLEN/8, x4, x1, x2)

inst_3580:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x020d6d and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000007 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7d820d6d; op2val:0x0;
op3val:0x7; valaddr_reg:x3; val_offset:10740*0 + 3*508*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 10740*0 + 3*508*FLEN/8, x4, x1, x2)

inst_3581:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x020d6d and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x199999 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7d820d6d; op2val:0x0;
op3val:0x199999; valaddr_reg:x3; val_offset:10743*0 + 3*509*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 10743*0 + 3*509*FLEN/8, x4, x1, x2)

inst_3582:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x020d6d and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x249249 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7d820d6d; op2val:0x0;
op3val:0x249249; valaddr_reg:x3; val_offset:10746*0 + 3*510*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 10746*0 + 3*510*FLEN/8, x4, x1, x2)

inst_3583:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x020d6d and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x333333 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7d820d6d; op2val:0x0;
op3val:0x333333; valaddr_reg:x3; val_offset:10749*0 + 3*511*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 10749*0 + 3*511*FLEN/8, x4, x1, x2)
RVTEST_SIGBASE(x1,signature_x1_5)

inst_3584:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x020d6d and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x36db6d and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7d820d6d; op2val:0x0;
op3val:0x36db6d; valaddr_reg:x3; val_offset:10752*0 + 3*512*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 10752*0 + 3*512*FLEN/8, x4, x1, x2)

inst_3585:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x020d6d and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x3bbbbb and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7d820d6d; op2val:0x0;
op3val:0x3bbbbb; valaddr_reg:x3; val_offset:10755*0 + 3*513*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 10755*0 + 3*513*FLEN/8, x4, x1, x2)

inst_3586:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x020d6d and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x444444 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7d820d6d; op2val:0x0;
op3val:0x444444; valaddr_reg:x3; val_offset:10758*0 + 3*514*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 10758*0 + 3*514*FLEN/8, x4, x1, x2)

inst_3587:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x020d6d and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x4ccccc and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7d820d6d; op2val:0x0;
op3val:0x4ccccc; valaddr_reg:x3; val_offset:10761*0 + 3*515*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 10761*0 + 3*515*FLEN/8, x4, x1, x2)

inst_3588:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x020d6d and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x5b6db6 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7d820d6d; op2val:0x0;
op3val:0x5b6db6; valaddr_reg:x3; val_offset:10764*0 + 3*516*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 10764*0 + 3*516*FLEN/8, x4, x1, x2)

inst_3589:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x020d6d and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x666666 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7d820d6d; op2val:0x0;
op3val:0x666666; valaddr_reg:x3; val_offset:10767*0 + 3*517*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 10767*0 + 3*517*FLEN/8, x4, x1, x2)

inst_3590:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x020d6d and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x6db6db and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7d820d6d; op2val:0x0;
op3val:0x6db6db; valaddr_reg:x3; val_offset:10770*0 + 3*518*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 10770*0 + 3*518*FLEN/8, x4, x1, x2)

inst_3591:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x020d6d and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x7ffff8 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7d820d6d; op2val:0x0;
op3val:0x7ffff8; valaddr_reg:x3; val_offset:10773*0 + 3*519*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 10773*0 + 3*519*FLEN/8, x4, x1, x2)

inst_3592:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x020d6d and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x7ffffc and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7d820d6d; op2val:0x0;
op3val:0x7ffffc; valaddr_reg:x3; val_offset:10776*0 + 3*520*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 10776*0 + 3*520*FLEN/8, x4, x1, x2)

inst_3593:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x020d6d and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x7ffffe and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7d820d6d; op2val:0x0;
op3val:0x7ffffe; valaddr_reg:x3; val_offset:10779*0 + 3*521*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 10779*0 + 3*521*FLEN/8, x4, x1, x2)

inst_3594:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x020d6d and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x000000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7d820d6d; op2val:0x0;
op3val:0xf800000; valaddr_reg:x3; val_offset:10782*0 + 3*522*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 10782*0 + 3*522*FLEN/8, x4, x1, x2)

inst_3595:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x020d6d and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x000001 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7d820d6d; op2val:0x0;
op3val:0xf800001; valaddr_reg:x3; val_offset:10785*0 + 3*523*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 10785*0 + 3*523*FLEN/8, x4, x1, x2)

inst_3596:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x020d6d and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x000003 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7d820d6d; op2val:0x0;
op3val:0xf800003; valaddr_reg:x3; val_offset:10788*0 + 3*524*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 10788*0 + 3*524*FLEN/8, x4, x1, x2)

inst_3597:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x020d6d and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x000007 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7d820d6d; op2val:0x0;
op3val:0xf800007; valaddr_reg:x3; val_offset:10791*0 + 3*525*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 10791*0 + 3*525*FLEN/8, x4, x1, x2)

inst_3598:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x020d6d and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x00000f and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7d820d6d; op2val:0x0;
op3val:0xf80000f; valaddr_reg:x3; val_offset:10794*0 + 3*526*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 10794*0 + 3*526*FLEN/8, x4, x1, x2)

inst_3599:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x020d6d and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x00001f and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7d820d6d; op2val:0x0;
op3val:0xf80001f; valaddr_reg:x3; val_offset:10797*0 + 3*527*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 10797*0 + 3*527*FLEN/8, x4, x1, x2)

inst_3600:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x020d6d and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x00003f and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7d820d6d; op2val:0x0;
op3val:0xf80003f; valaddr_reg:x3; val_offset:10800*0 + 3*528*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 10800*0 + 3*528*FLEN/8, x4, x1, x2)

inst_3601:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x020d6d and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x00007f and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7d820d6d; op2val:0x0;
op3val:0xf80007f; valaddr_reg:x3; val_offset:10803*0 + 3*529*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 10803*0 + 3*529*FLEN/8, x4, x1, x2)

inst_3602:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x020d6d and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x0000ff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7d820d6d; op2val:0x0;
op3val:0xf8000ff; valaddr_reg:x3; val_offset:10806*0 + 3*530*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 10806*0 + 3*530*FLEN/8, x4, x1, x2)

inst_3603:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x020d6d and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x0001ff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7d820d6d; op2val:0x0;
op3val:0xf8001ff; valaddr_reg:x3; val_offset:10809*0 + 3*531*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 10809*0 + 3*531*FLEN/8, x4, x1, x2)

inst_3604:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x020d6d and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x0003ff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7d820d6d; op2val:0x0;
op3val:0xf8003ff; valaddr_reg:x3; val_offset:10812*0 + 3*532*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 10812*0 + 3*532*FLEN/8, x4, x1, x2)

inst_3605:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x020d6d and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x0007ff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7d820d6d; op2val:0x0;
op3val:0xf8007ff; valaddr_reg:x3; val_offset:10815*0 + 3*533*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 10815*0 + 3*533*FLEN/8, x4, x1, x2)

inst_3606:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x020d6d and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x000fff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7d820d6d; op2val:0x0;
op3val:0xf800fff; valaddr_reg:x3; val_offset:10818*0 + 3*534*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 10818*0 + 3*534*FLEN/8, x4, x1, x2)

inst_3607:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x020d6d and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x001fff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7d820d6d; op2val:0x0;
op3val:0xf801fff; valaddr_reg:x3; val_offset:10821*0 + 3*535*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 10821*0 + 3*535*FLEN/8, x4, x1, x2)

inst_3608:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x020d6d and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x003fff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7d820d6d; op2val:0x0;
op3val:0xf803fff; valaddr_reg:x3; val_offset:10824*0 + 3*536*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 10824*0 + 3*536*FLEN/8, x4, x1, x2)

inst_3609:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x020d6d and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x007fff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7d820d6d; op2val:0x0;
op3val:0xf807fff; valaddr_reg:x3; val_offset:10827*0 + 3*537*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 10827*0 + 3*537*FLEN/8, x4, x1, x2)

inst_3610:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x020d6d and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x00ffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7d820d6d; op2val:0x0;
op3val:0xf80ffff; valaddr_reg:x3; val_offset:10830*0 + 3*538*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 10830*0 + 3*538*FLEN/8, x4, x1, x2)

inst_3611:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x020d6d and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x01ffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7d820d6d; op2val:0x0;
op3val:0xf81ffff; valaddr_reg:x3; val_offset:10833*0 + 3*539*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 10833*0 + 3*539*FLEN/8, x4, x1, x2)

inst_3612:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x020d6d and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x03ffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7d820d6d; op2val:0x0;
op3val:0xf83ffff; valaddr_reg:x3; val_offset:10836*0 + 3*540*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 10836*0 + 3*540*FLEN/8, x4, x1, x2)

inst_3613:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x020d6d and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x07ffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7d820d6d; op2val:0x0;
op3val:0xf87ffff; valaddr_reg:x3; val_offset:10839*0 + 3*541*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 10839*0 + 3*541*FLEN/8, x4, x1, x2)

inst_3614:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x020d6d and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x0fffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7d820d6d; op2val:0x0;
op3val:0xf8fffff; valaddr_reg:x3; val_offset:10842*0 + 3*542*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 10842*0 + 3*542*FLEN/8, x4, x1, x2)

inst_3615:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x020d6d and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x1fffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7d820d6d; op2val:0x0;
op3val:0xf9fffff; valaddr_reg:x3; val_offset:10845*0 + 3*543*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 10845*0 + 3*543*FLEN/8, x4, x1, x2)

inst_3616:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x020d6d and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x3fffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7d820d6d; op2val:0x0;
op3val:0xfbfffff; valaddr_reg:x3; val_offset:10848*0 + 3*544*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 10848*0 + 3*544*FLEN/8, x4, x1, x2)

inst_3617:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x020d6d and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x400000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7d820d6d; op2val:0x0;
op3val:0xfc00000; valaddr_reg:x3; val_offset:10851*0 + 3*545*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 10851*0 + 3*545*FLEN/8, x4, x1, x2)

inst_3618:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x020d6d and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x600000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7d820d6d; op2val:0x0;
op3val:0xfe00000; valaddr_reg:x3; val_offset:10854*0 + 3*546*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 10854*0 + 3*546*FLEN/8, x4, x1, x2)

inst_3619:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x020d6d and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x700000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7d820d6d; op2val:0x0;
op3val:0xff00000; valaddr_reg:x3; val_offset:10857*0 + 3*547*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 10857*0 + 3*547*FLEN/8, x4, x1, x2)

inst_3620:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x020d6d and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x780000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7d820d6d; op2val:0x0;
op3val:0xff80000; valaddr_reg:x3; val_offset:10860*0 + 3*548*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 10860*0 + 3*548*FLEN/8, x4, x1, x2)

inst_3621:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x020d6d and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x7c0000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7d820d6d; op2val:0x0;
op3val:0xffc0000; valaddr_reg:x3; val_offset:10863*0 + 3*549*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 10863*0 + 3*549*FLEN/8, x4, x1, x2)

inst_3622:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x020d6d and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x7e0000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7d820d6d; op2val:0x0;
op3val:0xffe0000; valaddr_reg:x3; val_offset:10866*0 + 3*550*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 10866*0 + 3*550*FLEN/8, x4, x1, x2)

inst_3623:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x020d6d and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x7f0000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7d820d6d; op2val:0x0;
op3val:0xfff0000; valaddr_reg:x3; val_offset:10869*0 + 3*551*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 10869*0 + 3*551*FLEN/8, x4, x1, x2)

inst_3624:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x020d6d and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x7f8000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7d820d6d; op2val:0x0;
op3val:0xfff8000; valaddr_reg:x3; val_offset:10872*0 + 3*552*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 10872*0 + 3*552*FLEN/8, x4, x1, x2)

inst_3625:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x020d6d and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x7fc000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7d820d6d; op2val:0x0;
op3val:0xfffc000; valaddr_reg:x3; val_offset:10875*0 + 3*553*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 10875*0 + 3*553*FLEN/8, x4, x1, x2)

inst_3626:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x020d6d and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x7fe000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7d820d6d; op2val:0x0;
op3val:0xfffe000; valaddr_reg:x3; val_offset:10878*0 + 3*554*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 10878*0 + 3*554*FLEN/8, x4, x1, x2)

inst_3627:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x020d6d and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x7ff000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7d820d6d; op2val:0x0;
op3val:0xffff000; valaddr_reg:x3; val_offset:10881*0 + 3*555*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 10881*0 + 3*555*FLEN/8, x4, x1, x2)

inst_3628:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x020d6d and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x7ff800 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7d820d6d; op2val:0x0;
op3val:0xffff800; valaddr_reg:x3; val_offset:10884*0 + 3*556*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 10884*0 + 3*556*FLEN/8, x4, x1, x2)

inst_3629:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x020d6d and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x7ffc00 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7d820d6d; op2val:0x0;
op3val:0xffffc00; valaddr_reg:x3; val_offset:10887*0 + 3*557*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 10887*0 + 3*557*FLEN/8, x4, x1, x2)

inst_3630:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x020d6d and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x7ffe00 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7d820d6d; op2val:0x0;
op3val:0xffffe00; valaddr_reg:x3; val_offset:10890*0 + 3*558*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 10890*0 + 3*558*FLEN/8, x4, x1, x2)

inst_3631:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x020d6d and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x7fff00 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7d820d6d; op2val:0x0;
op3val:0xfffff00; valaddr_reg:x3; val_offset:10893*0 + 3*559*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 10893*0 + 3*559*FLEN/8, x4, x1, x2)

inst_3632:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x020d6d and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x7fff80 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7d820d6d; op2val:0x0;
op3val:0xfffff80; valaddr_reg:x3; val_offset:10896*0 + 3*560*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 10896*0 + 3*560*FLEN/8, x4, x1, x2)

inst_3633:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x020d6d and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x7fffc0 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7d820d6d; op2val:0x0;
op3val:0xfffffc0; valaddr_reg:x3; val_offset:10899*0 + 3*561*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 10899*0 + 3*561*FLEN/8, x4, x1, x2)

inst_3634:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x020d6d and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x7fffe0 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7d820d6d; op2val:0x0;
op3val:0xfffffe0; valaddr_reg:x3; val_offset:10902*0 + 3*562*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 10902*0 + 3*562*FLEN/8, x4, x1, x2)

inst_3635:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x020d6d and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x7ffff0 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7d820d6d; op2val:0x0;
op3val:0xffffff0; valaddr_reg:x3; val_offset:10905*0 + 3*563*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 10905*0 + 3*563*FLEN/8, x4, x1, x2)

inst_3636:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x020d6d and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x7ffff8 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7d820d6d; op2val:0x0;
op3val:0xffffff8; valaddr_reg:x3; val_offset:10908*0 + 3*564*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 10908*0 + 3*564*FLEN/8, x4, x1, x2)

inst_3637:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x020d6d and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x7ffffc and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7d820d6d; op2val:0x0;
op3val:0xffffffc; valaddr_reg:x3; val_offset:10911*0 + 3*565*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 10911*0 + 3*565*FLEN/8, x4, x1, x2)

inst_3638:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x020d6d and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x7ffffe and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7d820d6d; op2val:0x0;
op3val:0xffffffe; valaddr_reg:x3; val_offset:10914*0 + 3*566*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 10914*0 + 3*566*FLEN/8, x4, x1, x2)

inst_3639:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x020d6d and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x7fffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7d820d6d; op2val:0x0;
op3val:0xfffffff; valaddr_reg:x3; val_offset:10917*0 + 3*567*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 10917*0 + 3*567*FLEN/8, x4, x1, x2)

inst_3640:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x0b3bce and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000001 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7d8b3bce; op2val:0x80000000;
op3val:0x80000001; valaddr_reg:x3; val_offset:10920*0 + 3*568*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 10920*0 + 3*568*FLEN/8, x4, x1, x2)

inst_3641:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x0b3bce and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000003 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7d8b3bce; op2val:0x80000000;
op3val:0x80000003; valaddr_reg:x3; val_offset:10923*0 + 3*569*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 10923*0 + 3*569*FLEN/8, x4, x1, x2)

inst_3642:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x0b3bce and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000007 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7d8b3bce; op2val:0x80000000;
op3val:0x80000007; valaddr_reg:x3; val_offset:10926*0 + 3*570*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 10926*0 + 3*570*FLEN/8, x4, x1, x2)

inst_3643:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x0b3bce and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x199999 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7d8b3bce; op2val:0x80000000;
op3val:0x80199999; valaddr_reg:x3; val_offset:10929*0 + 3*571*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 10929*0 + 3*571*FLEN/8, x4, x1, x2)

inst_3644:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x0b3bce and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x249249 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7d8b3bce; op2val:0x80000000;
op3val:0x80249249; valaddr_reg:x3; val_offset:10932*0 + 3*572*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 10932*0 + 3*572*FLEN/8, x4, x1, x2)

inst_3645:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x0b3bce and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x333333 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7d8b3bce; op2val:0x80000000;
op3val:0x80333333; valaddr_reg:x3; val_offset:10935*0 + 3*573*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 10935*0 + 3*573*FLEN/8, x4, x1, x2)

inst_3646:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x0b3bce and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x36db6d and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7d8b3bce; op2val:0x80000000;
op3val:0x8036db6d; valaddr_reg:x3; val_offset:10938*0 + 3*574*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 10938*0 + 3*574*FLEN/8, x4, x1, x2)

inst_3647:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x0b3bce and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3bbbbb and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7d8b3bce; op2val:0x80000000;
op3val:0x803bbbbb; valaddr_reg:x3; val_offset:10941*0 + 3*575*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 10941*0 + 3*575*FLEN/8, x4, x1, x2)

inst_3648:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x0b3bce and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x444444 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7d8b3bce; op2val:0x80000000;
op3val:0x80444444; valaddr_reg:x3; val_offset:10944*0 + 3*576*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 10944*0 + 3*576*FLEN/8, x4, x1, x2)

inst_3649:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x0b3bce and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x4ccccc and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7d8b3bce; op2val:0x80000000;
op3val:0x804ccccc; valaddr_reg:x3; val_offset:10947*0 + 3*577*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 10947*0 + 3*577*FLEN/8, x4, x1, x2)

inst_3650:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x0b3bce and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x5b6db6 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7d8b3bce; op2val:0x80000000;
op3val:0x805b6db6; valaddr_reg:x3; val_offset:10950*0 + 3*578*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 10950*0 + 3*578*FLEN/8, x4, x1, x2)

inst_3651:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x0b3bce and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x666666 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7d8b3bce; op2val:0x80000000;
op3val:0x80666666; valaddr_reg:x3; val_offset:10953*0 + 3*579*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 10953*0 + 3*579*FLEN/8, x4, x1, x2)

inst_3652:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x0b3bce and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x6db6db and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7d8b3bce; op2val:0x80000000;
op3val:0x806db6db; valaddr_reg:x3; val_offset:10956*0 + 3*580*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 10956*0 + 3*580*FLEN/8, x4, x1, x2)

inst_3653:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x0b3bce and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7ffff8 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7d8b3bce; op2val:0x80000000;
op3val:0x807ffff8; valaddr_reg:x3; val_offset:10959*0 + 3*581*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 10959*0 + 3*581*FLEN/8, x4, x1, x2)

inst_3654:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x0b3bce and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7ffffc and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7d8b3bce; op2val:0x80000000;
op3val:0x807ffffc; valaddr_reg:x3; val_offset:10962*0 + 3*582*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 10962*0 + 3*582*FLEN/8, x4, x1, x2)

inst_3655:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x0b3bce and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7ffffe and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7d8b3bce; op2val:0x80000000;
op3val:0x807ffffe; valaddr_reg:x3; val_offset:10965*0 + 3*583*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 10965*0 + 3*583*FLEN/8, x4, x1, x2)

inst_3656:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x0b3bce and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x02 and fm3 == 0x000000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7d8b3bce; op2val:0x80000000;
op3val:0x81000000; valaddr_reg:x3; val_offset:10968*0 + 3*584*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 10968*0 + 3*584*FLEN/8, x4, x1, x2)

inst_3657:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x0b3bce and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x02 and fm3 == 0x000001 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7d8b3bce; op2val:0x80000000;
op3val:0x81000001; valaddr_reg:x3; val_offset:10971*0 + 3*585*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 10971*0 + 3*585*FLEN/8, x4, x1, x2)

inst_3658:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x0b3bce and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x02 and fm3 == 0x000003 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7d8b3bce; op2val:0x80000000;
op3val:0x81000003; valaddr_reg:x3; val_offset:10974*0 + 3*586*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 10974*0 + 3*586*FLEN/8, x4, x1, x2)

inst_3659:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x0b3bce and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x02 and fm3 == 0x000007 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7d8b3bce; op2val:0x80000000;
op3val:0x81000007; valaddr_reg:x3; val_offset:10977*0 + 3*587*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 10977*0 + 3*587*FLEN/8, x4, x1, x2)

inst_3660:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x0b3bce and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x02 and fm3 == 0x00000f and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7d8b3bce; op2val:0x80000000;
op3val:0x8100000f; valaddr_reg:x3; val_offset:10980*0 + 3*588*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 10980*0 + 3*588*FLEN/8, x4, x1, x2)

inst_3661:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x0b3bce and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x02 and fm3 == 0x00001f and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7d8b3bce; op2val:0x80000000;
op3val:0x8100001f; valaddr_reg:x3; val_offset:10983*0 + 3*589*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 10983*0 + 3*589*FLEN/8, x4, x1, x2)

inst_3662:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x0b3bce and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x02 and fm3 == 0x00003f and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7d8b3bce; op2val:0x80000000;
op3val:0x8100003f; valaddr_reg:x3; val_offset:10986*0 + 3*590*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 10986*0 + 3*590*FLEN/8, x4, x1, x2)

inst_3663:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x0b3bce and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x02 and fm3 == 0x00007f and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7d8b3bce; op2val:0x80000000;
op3val:0x8100007f; valaddr_reg:x3; val_offset:10989*0 + 3*591*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 10989*0 + 3*591*FLEN/8, x4, x1, x2)

inst_3664:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x0b3bce and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x02 and fm3 == 0x0000ff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7d8b3bce; op2val:0x80000000;
op3val:0x810000ff; valaddr_reg:x3; val_offset:10992*0 + 3*592*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 10992*0 + 3*592*FLEN/8, x4, x1, x2)

inst_3665:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x0b3bce and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x02 and fm3 == 0x0001ff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7d8b3bce; op2val:0x80000000;
op3val:0x810001ff; valaddr_reg:x3; val_offset:10995*0 + 3*593*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 10995*0 + 3*593*FLEN/8, x4, x1, x2)

inst_3666:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x0b3bce and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x02 and fm3 == 0x0003ff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7d8b3bce; op2val:0x80000000;
op3val:0x810003ff; valaddr_reg:x3; val_offset:10998*0 + 3*594*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 10998*0 + 3*594*FLEN/8, x4, x1, x2)

inst_3667:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x0b3bce and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x02 and fm3 == 0x0007ff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7d8b3bce; op2val:0x80000000;
op3val:0x810007ff; valaddr_reg:x3; val_offset:11001*0 + 3*595*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 11001*0 + 3*595*FLEN/8, x4, x1, x2)

inst_3668:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x0b3bce and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x02 and fm3 == 0x000fff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7d8b3bce; op2val:0x80000000;
op3val:0x81000fff; valaddr_reg:x3; val_offset:11004*0 + 3*596*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 11004*0 + 3*596*FLEN/8, x4, x1, x2)

inst_3669:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x0b3bce and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x02 and fm3 == 0x001fff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7d8b3bce; op2val:0x80000000;
op3val:0x81001fff; valaddr_reg:x3; val_offset:11007*0 + 3*597*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 11007*0 + 3*597*FLEN/8, x4, x1, x2)

inst_3670:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x0b3bce and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x02 and fm3 == 0x003fff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7d8b3bce; op2val:0x80000000;
op3val:0x81003fff; valaddr_reg:x3; val_offset:11010*0 + 3*598*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 11010*0 + 3*598*FLEN/8, x4, x1, x2)

inst_3671:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x0b3bce and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x02 and fm3 == 0x007fff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7d8b3bce; op2val:0x80000000;
op3val:0x81007fff; valaddr_reg:x3; val_offset:11013*0 + 3*599*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 11013*0 + 3*599*FLEN/8, x4, x1, x2)

inst_3672:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x0b3bce and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x02 and fm3 == 0x00ffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7d8b3bce; op2val:0x80000000;
op3val:0x8100ffff; valaddr_reg:x3; val_offset:11016*0 + 3*600*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 11016*0 + 3*600*FLEN/8, x4, x1, x2)

inst_3673:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x0b3bce and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x02 and fm3 == 0x01ffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7d8b3bce; op2val:0x80000000;
op3val:0x8101ffff; valaddr_reg:x3; val_offset:11019*0 + 3*601*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 11019*0 + 3*601*FLEN/8, x4, x1, x2)

inst_3674:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x0b3bce and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x02 and fm3 == 0x03ffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7d8b3bce; op2val:0x80000000;
op3val:0x8103ffff; valaddr_reg:x3; val_offset:11022*0 + 3*602*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 11022*0 + 3*602*FLEN/8, x4, x1, x2)

inst_3675:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x0b3bce and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x02 and fm3 == 0x07ffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7d8b3bce; op2val:0x80000000;
op3val:0x8107ffff; valaddr_reg:x3; val_offset:11025*0 + 3*603*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 11025*0 + 3*603*FLEN/8, x4, x1, x2)

inst_3676:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x0b3bce and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x02 and fm3 == 0x0fffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7d8b3bce; op2val:0x80000000;
op3val:0x810fffff; valaddr_reg:x3; val_offset:11028*0 + 3*604*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 11028*0 + 3*604*FLEN/8, x4, x1, x2)

inst_3677:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x0b3bce and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x02 and fm3 == 0x1fffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7d8b3bce; op2val:0x80000000;
op3val:0x811fffff; valaddr_reg:x3; val_offset:11031*0 + 3*605*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 11031*0 + 3*605*FLEN/8, x4, x1, x2)

inst_3678:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x0b3bce and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x02 and fm3 == 0x3fffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7d8b3bce; op2val:0x80000000;
op3val:0x813fffff; valaddr_reg:x3; val_offset:11034*0 + 3*606*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 11034*0 + 3*606*FLEN/8, x4, x1, x2)

inst_3679:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x0b3bce and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x02 and fm3 == 0x400000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7d8b3bce; op2val:0x80000000;
op3val:0x81400000; valaddr_reg:x3; val_offset:11037*0 + 3*607*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 11037*0 + 3*607*FLEN/8, x4, x1, x2)

inst_3680:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x0b3bce and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x02 and fm3 == 0x600000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7d8b3bce; op2val:0x80000000;
op3val:0x81600000; valaddr_reg:x3; val_offset:11040*0 + 3*608*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 11040*0 + 3*608*FLEN/8, x4, x1, x2)

inst_3681:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x0b3bce and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x02 and fm3 == 0x700000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7d8b3bce; op2val:0x80000000;
op3val:0x81700000; valaddr_reg:x3; val_offset:11043*0 + 3*609*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 11043*0 + 3*609*FLEN/8, x4, x1, x2)

inst_3682:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x0b3bce and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x02 and fm3 == 0x780000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7d8b3bce; op2val:0x80000000;
op3val:0x81780000; valaddr_reg:x3; val_offset:11046*0 + 3*610*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 11046*0 + 3*610*FLEN/8, x4, x1, x2)

inst_3683:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x0b3bce and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x02 and fm3 == 0x7c0000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7d8b3bce; op2val:0x80000000;
op3val:0x817c0000; valaddr_reg:x3; val_offset:11049*0 + 3*611*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 11049*0 + 3*611*FLEN/8, x4, x1, x2)

inst_3684:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x0b3bce and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x02 and fm3 == 0x7e0000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7d8b3bce; op2val:0x80000000;
op3val:0x817e0000; valaddr_reg:x3; val_offset:11052*0 + 3*612*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 11052*0 + 3*612*FLEN/8, x4, x1, x2)

inst_3685:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x0b3bce and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x02 and fm3 == 0x7f0000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7d8b3bce; op2val:0x80000000;
op3val:0x817f0000; valaddr_reg:x3; val_offset:11055*0 + 3*613*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 11055*0 + 3*613*FLEN/8, x4, x1, x2)

inst_3686:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x0b3bce and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x02 and fm3 == 0x7f8000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7d8b3bce; op2val:0x80000000;
op3val:0x817f8000; valaddr_reg:x3; val_offset:11058*0 + 3*614*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 11058*0 + 3*614*FLEN/8, x4, x1, x2)

inst_3687:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x0b3bce and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x02 and fm3 == 0x7fc000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7d8b3bce; op2val:0x80000000;
op3val:0x817fc000; valaddr_reg:x3; val_offset:11061*0 + 3*615*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 11061*0 + 3*615*FLEN/8, x4, x1, x2)

inst_3688:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x0b3bce and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x02 and fm3 == 0x7fe000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7d8b3bce; op2val:0x80000000;
op3val:0x817fe000; valaddr_reg:x3; val_offset:11064*0 + 3*616*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 11064*0 + 3*616*FLEN/8, x4, x1, x2)

inst_3689:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x0b3bce and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x02 and fm3 == 0x7ff000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7d8b3bce; op2val:0x80000000;
op3val:0x817ff000; valaddr_reg:x3; val_offset:11067*0 + 3*617*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 11067*0 + 3*617*FLEN/8, x4, x1, x2)

inst_3690:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x0b3bce and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x02 and fm3 == 0x7ff800 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7d8b3bce; op2val:0x80000000;
op3val:0x817ff800; valaddr_reg:x3; val_offset:11070*0 + 3*618*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 11070*0 + 3*618*FLEN/8, x4, x1, x2)

inst_3691:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x0b3bce and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x02 and fm3 == 0x7ffc00 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7d8b3bce; op2val:0x80000000;
op3val:0x817ffc00; valaddr_reg:x3; val_offset:11073*0 + 3*619*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 11073*0 + 3*619*FLEN/8, x4, x1, x2)

inst_3692:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x0b3bce and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x02 and fm3 == 0x7ffe00 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7d8b3bce; op2val:0x80000000;
op3val:0x817ffe00; valaddr_reg:x3; val_offset:11076*0 + 3*620*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 11076*0 + 3*620*FLEN/8, x4, x1, x2)

inst_3693:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x0b3bce and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x02 and fm3 == 0x7fff00 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7d8b3bce; op2val:0x80000000;
op3val:0x817fff00; valaddr_reg:x3; val_offset:11079*0 + 3*621*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 11079*0 + 3*621*FLEN/8, x4, x1, x2)

inst_3694:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x0b3bce and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x02 and fm3 == 0x7fff80 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7d8b3bce; op2val:0x80000000;
op3val:0x817fff80; valaddr_reg:x3; val_offset:11082*0 + 3*622*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 11082*0 + 3*622*FLEN/8, x4, x1, x2)

inst_3695:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x0b3bce and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x02 and fm3 == 0x7fffc0 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7d8b3bce; op2val:0x80000000;
op3val:0x817fffc0; valaddr_reg:x3; val_offset:11085*0 + 3*623*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 11085*0 + 3*623*FLEN/8, x4, x1, x2)

inst_3696:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x0b3bce and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x02 and fm3 == 0x7fffe0 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7d8b3bce; op2val:0x80000000;
op3val:0x817fffe0; valaddr_reg:x3; val_offset:11088*0 + 3*624*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 11088*0 + 3*624*FLEN/8, x4, x1, x2)

inst_3697:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x0b3bce and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x02 and fm3 == 0x7ffff0 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7d8b3bce; op2val:0x80000000;
op3val:0x817ffff0; valaddr_reg:x3; val_offset:11091*0 + 3*625*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 11091*0 + 3*625*FLEN/8, x4, x1, x2)

inst_3698:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x0b3bce and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x02 and fm3 == 0x7ffff8 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7d8b3bce; op2val:0x80000000;
op3val:0x817ffff8; valaddr_reg:x3; val_offset:11094*0 + 3*626*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 11094*0 + 3*626*FLEN/8, x4, x1, x2)

inst_3699:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x0b3bce and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x02 and fm3 == 0x7ffffc and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7d8b3bce; op2val:0x80000000;
op3val:0x817ffffc; valaddr_reg:x3; val_offset:11097*0 + 3*627*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 11097*0 + 3*627*FLEN/8, x4, x1, x2)

inst_3700:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x0b3bce and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x02 and fm3 == 0x7ffffe and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7d8b3bce; op2val:0x80000000;
op3val:0x817ffffe; valaddr_reg:x3; val_offset:11100*0 + 3*628*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 11100*0 + 3*628*FLEN/8, x4, x1, x2)

inst_3701:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x0b3bce and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x02 and fm3 == 0x7fffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7d8b3bce; op2val:0x80000000;
op3val:0x817fffff; valaddr_reg:x3; val_offset:11103*0 + 3*629*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 11103*0 + 3*629*FLEN/8, x4, x1, x2)

inst_3702:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x0c97c9 and fs2 == 0 and fe2 == 0x02 and fm2 == 0x6911ef and fs3 == 0 and fe3 == 0x6d and fm3 == 0x000000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7d8c97c9; op2val:0x16911ef;
op3val:0x36800000; valaddr_reg:x3; val_offset:11106*0 + 3*630*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 11106*0 + 3*630*FLEN/8, x4, x1, x2)

inst_3703:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x0c97c9 and fs2 == 0 and fe2 == 0x02 and fm2 == 0x6911ef and fs3 == 0 and fe3 == 0x6d and fm3 == 0x000001 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7d8c97c9; op2val:0x16911ef;
op3val:0x36800001; valaddr_reg:x3; val_offset:11109*0 + 3*631*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 11109*0 + 3*631*FLEN/8, x4, x1, x2)

inst_3704:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x0c97c9 and fs2 == 0 and fe2 == 0x02 and fm2 == 0x6911ef and fs3 == 0 and fe3 == 0x6d and fm3 == 0x000003 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7d8c97c9; op2val:0x16911ef;
op3val:0x36800003; valaddr_reg:x3; val_offset:11112*0 + 3*632*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 11112*0 + 3*632*FLEN/8, x4, x1, x2)

inst_3705:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x0c97c9 and fs2 == 0 and fe2 == 0x02 and fm2 == 0x6911ef and fs3 == 0 and fe3 == 0x6d and fm3 == 0x000007 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7d8c97c9; op2val:0x16911ef;
op3val:0x36800007; valaddr_reg:x3; val_offset:11115*0 + 3*633*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 11115*0 + 3*633*FLEN/8, x4, x1, x2)

inst_3706:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x0c97c9 and fs2 == 0 and fe2 == 0x02 and fm2 == 0x6911ef and fs3 == 0 and fe3 == 0x6d and fm3 == 0x00000f and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7d8c97c9; op2val:0x16911ef;
op3val:0x3680000f; valaddr_reg:x3; val_offset:11118*0 + 3*634*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 11118*0 + 3*634*FLEN/8, x4, x1, x2)

inst_3707:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x0c97c9 and fs2 == 0 and fe2 == 0x02 and fm2 == 0x6911ef and fs3 == 0 and fe3 == 0x6d and fm3 == 0x00001f and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7d8c97c9; op2val:0x16911ef;
op3val:0x3680001f; valaddr_reg:x3; val_offset:11121*0 + 3*635*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 11121*0 + 3*635*FLEN/8, x4, x1, x2)

inst_3708:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x0c97c9 and fs2 == 0 and fe2 == 0x02 and fm2 == 0x6911ef and fs3 == 0 and fe3 == 0x6d and fm3 == 0x00003f and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7d8c97c9; op2val:0x16911ef;
op3val:0x3680003f; valaddr_reg:x3; val_offset:11124*0 + 3*636*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 11124*0 + 3*636*FLEN/8, x4, x1, x2)

inst_3709:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x0c97c9 and fs2 == 0 and fe2 == 0x02 and fm2 == 0x6911ef and fs3 == 0 and fe3 == 0x6d and fm3 == 0x00007f and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7d8c97c9; op2val:0x16911ef;
op3val:0x3680007f; valaddr_reg:x3; val_offset:11127*0 + 3*637*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 11127*0 + 3*637*FLEN/8, x4, x1, x2)

inst_3710:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x0c97c9 and fs2 == 0 and fe2 == 0x02 and fm2 == 0x6911ef and fs3 == 0 and fe3 == 0x6d and fm3 == 0x0000ff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7d8c97c9; op2val:0x16911ef;
op3val:0x368000ff; valaddr_reg:x3; val_offset:11130*0 + 3*638*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 11130*0 + 3*638*FLEN/8, x4, x1, x2)

inst_3711:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x0c97c9 and fs2 == 0 and fe2 == 0x02 and fm2 == 0x6911ef and fs3 == 0 and fe3 == 0x6d and fm3 == 0x0001ff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7d8c97c9; op2val:0x16911ef;
op3val:0x368001ff; valaddr_reg:x3; val_offset:11133*0 + 3*639*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 11133*0 + 3*639*FLEN/8, x4, x1, x2)
RVTEST_SIGBASE(x1,signature_x1_6)

inst_3712:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x0c97c9 and fs2 == 0 and fe2 == 0x02 and fm2 == 0x6911ef and fs3 == 0 and fe3 == 0x6d and fm3 == 0x0003ff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7d8c97c9; op2val:0x16911ef;
op3val:0x368003ff; valaddr_reg:x3; val_offset:11136*0 + 3*640*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 11136*0 + 3*640*FLEN/8, x4, x1, x2)

inst_3713:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x0c97c9 and fs2 == 0 and fe2 == 0x02 and fm2 == 0x6911ef and fs3 == 0 and fe3 == 0x6d and fm3 == 0x0007ff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7d8c97c9; op2val:0x16911ef;
op3val:0x368007ff; valaddr_reg:x3; val_offset:11139*0 + 3*641*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 11139*0 + 3*641*FLEN/8, x4, x1, x2)

inst_3714:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x0c97c9 and fs2 == 0 and fe2 == 0x02 and fm2 == 0x6911ef and fs3 == 0 and fe3 == 0x6d and fm3 == 0x000fff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7d8c97c9; op2val:0x16911ef;
op3val:0x36800fff; valaddr_reg:x3; val_offset:11142*0 + 3*642*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 11142*0 + 3*642*FLEN/8, x4, x1, x2)

inst_3715:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x0c97c9 and fs2 == 0 and fe2 == 0x02 and fm2 == 0x6911ef and fs3 == 0 and fe3 == 0x6d and fm3 == 0x001fff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7d8c97c9; op2val:0x16911ef;
op3val:0x36801fff; valaddr_reg:x3; val_offset:11145*0 + 3*643*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 11145*0 + 3*643*FLEN/8, x4, x1, x2)

inst_3716:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x0c97c9 and fs2 == 0 and fe2 == 0x02 and fm2 == 0x6911ef and fs3 == 0 and fe3 == 0x6d and fm3 == 0x003fff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7d8c97c9; op2val:0x16911ef;
op3val:0x36803fff; valaddr_reg:x3; val_offset:11148*0 + 3*644*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 11148*0 + 3*644*FLEN/8, x4, x1, x2)

inst_3717:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x0c97c9 and fs2 == 0 and fe2 == 0x02 and fm2 == 0x6911ef and fs3 == 0 and fe3 == 0x6d and fm3 == 0x007fff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7d8c97c9; op2val:0x16911ef;
op3val:0x36807fff; valaddr_reg:x3; val_offset:11151*0 + 3*645*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 11151*0 + 3*645*FLEN/8, x4, x1, x2)

inst_3718:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x0c97c9 and fs2 == 0 and fe2 == 0x02 and fm2 == 0x6911ef and fs3 == 0 and fe3 == 0x6d and fm3 == 0x00ffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7d8c97c9; op2val:0x16911ef;
op3val:0x3680ffff; valaddr_reg:x3; val_offset:11154*0 + 3*646*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 11154*0 + 3*646*FLEN/8, x4, x1, x2)

inst_3719:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x0c97c9 and fs2 == 0 and fe2 == 0x02 and fm2 == 0x6911ef and fs3 == 0 and fe3 == 0x6d and fm3 == 0x01ffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7d8c97c9; op2val:0x16911ef;
op3val:0x3681ffff; valaddr_reg:x3; val_offset:11157*0 + 3*647*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 11157*0 + 3*647*FLEN/8, x4, x1, x2)

inst_3720:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x0c97c9 and fs2 == 0 and fe2 == 0x02 and fm2 == 0x6911ef and fs3 == 0 and fe3 == 0x6d and fm3 == 0x03ffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7d8c97c9; op2val:0x16911ef;
op3val:0x3683ffff; valaddr_reg:x3; val_offset:11160*0 + 3*648*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 11160*0 + 3*648*FLEN/8, x4, x1, x2)

inst_3721:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x0c97c9 and fs2 == 0 and fe2 == 0x02 and fm2 == 0x6911ef and fs3 == 0 and fe3 == 0x6d and fm3 == 0x07ffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7d8c97c9; op2val:0x16911ef;
op3val:0x3687ffff; valaddr_reg:x3; val_offset:11163*0 + 3*649*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 11163*0 + 3*649*FLEN/8, x4, x1, x2)

inst_3722:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x0c97c9 and fs2 == 0 and fe2 == 0x02 and fm2 == 0x6911ef and fs3 == 0 and fe3 == 0x6d and fm3 == 0x0fffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7d8c97c9; op2val:0x16911ef;
op3val:0x368fffff; valaddr_reg:x3; val_offset:11166*0 + 3*650*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 11166*0 + 3*650*FLEN/8, x4, x1, x2)

inst_3723:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x0c97c9 and fs2 == 0 and fe2 == 0x02 and fm2 == 0x6911ef and fs3 == 0 and fe3 == 0x6d and fm3 == 0x1fffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7d8c97c9; op2val:0x16911ef;
op3val:0x369fffff; valaddr_reg:x3; val_offset:11169*0 + 3*651*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 11169*0 + 3*651*FLEN/8, x4, x1, x2)

inst_3724:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x0c97c9 and fs2 == 0 and fe2 == 0x02 and fm2 == 0x6911ef and fs3 == 0 and fe3 == 0x6d and fm3 == 0x3fffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7d8c97c9; op2val:0x16911ef;
op3val:0x36bfffff; valaddr_reg:x3; val_offset:11172*0 + 3*652*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 11172*0 + 3*652*FLEN/8, x4, x1, x2)

inst_3725:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x0c97c9 and fs2 == 0 and fe2 == 0x02 and fm2 == 0x6911ef and fs3 == 0 and fe3 == 0x6d and fm3 == 0x400000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7d8c97c9; op2val:0x16911ef;
op3val:0x36c00000; valaddr_reg:x3; val_offset:11175*0 + 3*653*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 11175*0 + 3*653*FLEN/8, x4, x1, x2)

inst_3726:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x0c97c9 and fs2 == 0 and fe2 == 0x02 and fm2 == 0x6911ef and fs3 == 0 and fe3 == 0x6d and fm3 == 0x600000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7d8c97c9; op2val:0x16911ef;
op3val:0x36e00000; valaddr_reg:x3; val_offset:11178*0 + 3*654*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 11178*0 + 3*654*FLEN/8, x4, x1, x2)

inst_3727:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x0c97c9 and fs2 == 0 and fe2 == 0x02 and fm2 == 0x6911ef and fs3 == 0 and fe3 == 0x6d and fm3 == 0x700000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7d8c97c9; op2val:0x16911ef;
op3val:0x36f00000; valaddr_reg:x3; val_offset:11181*0 + 3*655*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 11181*0 + 3*655*FLEN/8, x4, x1, x2)

inst_3728:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x0c97c9 and fs2 == 0 and fe2 == 0x02 and fm2 == 0x6911ef and fs3 == 0 and fe3 == 0x6d and fm3 == 0x780000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7d8c97c9; op2val:0x16911ef;
op3val:0x36f80000; valaddr_reg:x3; val_offset:11184*0 + 3*656*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 11184*0 + 3*656*FLEN/8, x4, x1, x2)

inst_3729:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x0c97c9 and fs2 == 0 and fe2 == 0x02 and fm2 == 0x6911ef and fs3 == 0 and fe3 == 0x6d and fm3 == 0x7c0000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7d8c97c9; op2val:0x16911ef;
op3val:0x36fc0000; valaddr_reg:x3; val_offset:11187*0 + 3*657*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 11187*0 + 3*657*FLEN/8, x4, x1, x2)

inst_3730:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x0c97c9 and fs2 == 0 and fe2 == 0x02 and fm2 == 0x6911ef and fs3 == 0 and fe3 == 0x6d and fm3 == 0x7e0000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7d8c97c9; op2val:0x16911ef;
op3val:0x36fe0000; valaddr_reg:x3; val_offset:11190*0 + 3*658*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 11190*0 + 3*658*FLEN/8, x4, x1, x2)

inst_3731:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x0c97c9 and fs2 == 0 and fe2 == 0x02 and fm2 == 0x6911ef and fs3 == 0 and fe3 == 0x6d and fm3 == 0x7f0000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7d8c97c9; op2val:0x16911ef;
op3val:0x36ff0000; valaddr_reg:x3; val_offset:11193*0 + 3*659*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 11193*0 + 3*659*FLEN/8, x4, x1, x2)

inst_3732:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x0c97c9 and fs2 == 0 and fe2 == 0x02 and fm2 == 0x6911ef and fs3 == 0 and fe3 == 0x6d and fm3 == 0x7f8000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7d8c97c9; op2val:0x16911ef;
op3val:0x36ff8000; valaddr_reg:x3; val_offset:11196*0 + 3*660*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 11196*0 + 3*660*FLEN/8, x4, x1, x2)

inst_3733:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x0c97c9 and fs2 == 0 and fe2 == 0x02 and fm2 == 0x6911ef and fs3 == 0 and fe3 == 0x6d and fm3 == 0x7fc000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7d8c97c9; op2val:0x16911ef;
op3val:0x36ffc000; valaddr_reg:x3; val_offset:11199*0 + 3*661*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 11199*0 + 3*661*FLEN/8, x4, x1, x2)

inst_3734:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x0c97c9 and fs2 == 0 and fe2 == 0x02 and fm2 == 0x6911ef and fs3 == 0 and fe3 == 0x6d and fm3 == 0x7fe000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7d8c97c9; op2val:0x16911ef;
op3val:0x36ffe000; valaddr_reg:x3; val_offset:11202*0 + 3*662*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 11202*0 + 3*662*FLEN/8, x4, x1, x2)

inst_3735:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x0c97c9 and fs2 == 0 and fe2 == 0x02 and fm2 == 0x6911ef and fs3 == 0 and fe3 == 0x6d and fm3 == 0x7ff000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7d8c97c9; op2val:0x16911ef;
op3val:0x36fff000; valaddr_reg:x3; val_offset:11205*0 + 3*663*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 11205*0 + 3*663*FLEN/8, x4, x1, x2)

inst_3736:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x0c97c9 and fs2 == 0 and fe2 == 0x02 and fm2 == 0x6911ef and fs3 == 0 and fe3 == 0x6d and fm3 == 0x7ff800 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7d8c97c9; op2val:0x16911ef;
op3val:0x36fff800; valaddr_reg:x3; val_offset:11208*0 + 3*664*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 11208*0 + 3*664*FLEN/8, x4, x1, x2)

inst_3737:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x0c97c9 and fs2 == 0 and fe2 == 0x02 and fm2 == 0x6911ef and fs3 == 0 and fe3 == 0x6d and fm3 == 0x7ffc00 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7d8c97c9; op2val:0x16911ef;
op3val:0x36fffc00; valaddr_reg:x3; val_offset:11211*0 + 3*665*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 11211*0 + 3*665*FLEN/8, x4, x1, x2)

inst_3738:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x0c97c9 and fs2 == 0 and fe2 == 0x02 and fm2 == 0x6911ef and fs3 == 0 and fe3 == 0x6d and fm3 == 0x7ffe00 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7d8c97c9; op2val:0x16911ef;
op3val:0x36fffe00; valaddr_reg:x3; val_offset:11214*0 + 3*666*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 11214*0 + 3*666*FLEN/8, x4, x1, x2)

inst_3739:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x0c97c9 and fs2 == 0 and fe2 == 0x02 and fm2 == 0x6911ef and fs3 == 0 and fe3 == 0x6d and fm3 == 0x7fff00 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7d8c97c9; op2val:0x16911ef;
op3val:0x36ffff00; valaddr_reg:x3; val_offset:11217*0 + 3*667*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 11217*0 + 3*667*FLEN/8, x4, x1, x2)

inst_3740:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x0c97c9 and fs2 == 0 and fe2 == 0x02 and fm2 == 0x6911ef and fs3 == 0 and fe3 == 0x6d and fm3 == 0x7fff80 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7d8c97c9; op2val:0x16911ef;
op3val:0x36ffff80; valaddr_reg:x3; val_offset:11220*0 + 3*668*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 11220*0 + 3*668*FLEN/8, x4, x1, x2)

inst_3741:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x0c97c9 and fs2 == 0 and fe2 == 0x02 and fm2 == 0x6911ef and fs3 == 0 and fe3 == 0x6d and fm3 == 0x7fffc0 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7d8c97c9; op2val:0x16911ef;
op3val:0x36ffffc0; valaddr_reg:x3; val_offset:11223*0 + 3*669*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 11223*0 + 3*669*FLEN/8, x4, x1, x2)

inst_3742:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x0c97c9 and fs2 == 0 and fe2 == 0x02 and fm2 == 0x6911ef and fs3 == 0 and fe3 == 0x6d and fm3 == 0x7fffe0 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7d8c97c9; op2val:0x16911ef;
op3val:0x36ffffe0; valaddr_reg:x3; val_offset:11226*0 + 3*670*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 11226*0 + 3*670*FLEN/8, x4, x1, x2)

inst_3743:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x0c97c9 and fs2 == 0 and fe2 == 0x02 and fm2 == 0x6911ef and fs3 == 0 and fe3 == 0x6d and fm3 == 0x7ffff0 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7d8c97c9; op2val:0x16911ef;
op3val:0x36fffff0; valaddr_reg:x3; val_offset:11229*0 + 3*671*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 11229*0 + 3*671*FLEN/8, x4, x1, x2)

inst_3744:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x0c97c9 and fs2 == 0 and fe2 == 0x02 and fm2 == 0x6911ef and fs3 == 0 and fe3 == 0x6d and fm3 == 0x7ffff8 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7d8c97c9; op2val:0x16911ef;
op3val:0x36fffff8; valaddr_reg:x3; val_offset:11232*0 + 3*672*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 11232*0 + 3*672*FLEN/8, x4, x1, x2)

inst_3745:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x0c97c9 and fs2 == 0 and fe2 == 0x02 and fm2 == 0x6911ef and fs3 == 0 and fe3 == 0x6d and fm3 == 0x7ffffc and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7d8c97c9; op2val:0x16911ef;
op3val:0x36fffffc; valaddr_reg:x3; val_offset:11235*0 + 3*673*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 11235*0 + 3*673*FLEN/8, x4, x1, x2)

inst_3746:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x0c97c9 and fs2 == 0 and fe2 == 0x02 and fm2 == 0x6911ef and fs3 == 0 and fe3 == 0x6d and fm3 == 0x7ffffe and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7d8c97c9; op2val:0x16911ef;
op3val:0x36fffffe; valaddr_reg:x3; val_offset:11238*0 + 3*674*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 11238*0 + 3*674*FLEN/8, x4, x1, x2)

inst_3747:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x0c97c9 and fs2 == 0 and fe2 == 0x02 and fm2 == 0x6911ef and fs3 == 0 and fe3 == 0x6d and fm3 == 0x7fffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7d8c97c9; op2val:0x16911ef;
op3val:0x36ffffff; valaddr_reg:x3; val_offset:11241*0 + 3*675*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 11241*0 + 3*675*FLEN/8, x4, x1, x2)

inst_3748:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x0c97c9 and fs2 == 0 and fe2 == 0x02 and fm2 == 0x6911ef and fs3 == 0 and fe3 == 0x7f and fm3 == 0x000001 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7d8c97c9; op2val:0x16911ef;
op3val:0x3f800001; valaddr_reg:x3; val_offset:11244*0 + 3*676*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 11244*0 + 3*676*FLEN/8, x4, x1, x2)

inst_3749:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x0c97c9 and fs2 == 0 and fe2 == 0x02 and fm2 == 0x6911ef and fs3 == 0 and fe3 == 0x7f and fm3 == 0x000003 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7d8c97c9; op2val:0x16911ef;
op3val:0x3f800003; valaddr_reg:x3; val_offset:11247*0 + 3*677*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 11247*0 + 3*677*FLEN/8, x4, x1, x2)

inst_3750:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x0c97c9 and fs2 == 0 and fe2 == 0x02 and fm2 == 0x6911ef and fs3 == 0 and fe3 == 0x7f and fm3 == 0x000007 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7d8c97c9; op2val:0x16911ef;
op3val:0x3f800007; valaddr_reg:x3; val_offset:11250*0 + 3*678*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 11250*0 + 3*678*FLEN/8, x4, x1, x2)

inst_3751:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x0c97c9 and fs2 == 0 and fe2 == 0x02 and fm2 == 0x6911ef and fs3 == 0 and fe3 == 0x7f and fm3 == 0x199999 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7d8c97c9; op2val:0x16911ef;
op3val:0x3f999999; valaddr_reg:x3; val_offset:11253*0 + 3*679*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 11253*0 + 3*679*FLEN/8, x4, x1, x2)

inst_3752:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x0c97c9 and fs2 == 0 and fe2 == 0x02 and fm2 == 0x6911ef and fs3 == 0 and fe3 == 0x7f and fm3 == 0x249249 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7d8c97c9; op2val:0x16911ef;
op3val:0x3fa49249; valaddr_reg:x3; val_offset:11256*0 + 3*680*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 11256*0 + 3*680*FLEN/8, x4, x1, x2)

inst_3753:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x0c97c9 and fs2 == 0 and fe2 == 0x02 and fm2 == 0x6911ef and fs3 == 0 and fe3 == 0x7f and fm3 == 0x333333 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7d8c97c9; op2val:0x16911ef;
op3val:0x3fb33333; valaddr_reg:x3; val_offset:11259*0 + 3*681*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 11259*0 + 3*681*FLEN/8, x4, x1, x2)

inst_3754:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x0c97c9 and fs2 == 0 and fe2 == 0x02 and fm2 == 0x6911ef and fs3 == 0 and fe3 == 0x7f and fm3 == 0x36db6d and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7d8c97c9; op2val:0x16911ef;
op3val:0x3fb6db6d; valaddr_reg:x3; val_offset:11262*0 + 3*682*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 11262*0 + 3*682*FLEN/8, x4, x1, x2)

inst_3755:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x0c97c9 and fs2 == 0 and fe2 == 0x02 and fm2 == 0x6911ef and fs3 == 0 and fe3 == 0x7f and fm3 == 0x3bbbbb and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7d8c97c9; op2val:0x16911ef;
op3val:0x3fbbbbbb; valaddr_reg:x3; val_offset:11265*0 + 3*683*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 11265*0 + 3*683*FLEN/8, x4, x1, x2)

inst_3756:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x0c97c9 and fs2 == 0 and fe2 == 0x02 and fm2 == 0x6911ef and fs3 == 0 and fe3 == 0x7f and fm3 == 0x444444 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7d8c97c9; op2val:0x16911ef;
op3val:0x3fc44444; valaddr_reg:x3; val_offset:11268*0 + 3*684*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 11268*0 + 3*684*FLEN/8, x4, x1, x2)

inst_3757:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x0c97c9 and fs2 == 0 and fe2 == 0x02 and fm2 == 0x6911ef and fs3 == 0 and fe3 == 0x7f and fm3 == 0x4ccccc and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7d8c97c9; op2val:0x16911ef;
op3val:0x3fcccccc; valaddr_reg:x3; val_offset:11271*0 + 3*685*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 11271*0 + 3*685*FLEN/8, x4, x1, x2)

inst_3758:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x0c97c9 and fs2 == 0 and fe2 == 0x02 and fm2 == 0x6911ef and fs3 == 0 and fe3 == 0x7f and fm3 == 0x5b6db6 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7d8c97c9; op2val:0x16911ef;
op3val:0x3fdb6db6; valaddr_reg:x3; val_offset:11274*0 + 3*686*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 11274*0 + 3*686*FLEN/8, x4, x1, x2)

inst_3759:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x0c97c9 and fs2 == 0 and fe2 == 0x02 and fm2 == 0x6911ef and fs3 == 0 and fe3 == 0x7f and fm3 == 0x666666 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7d8c97c9; op2val:0x16911ef;
op3val:0x3fe66666; valaddr_reg:x3; val_offset:11277*0 + 3*687*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 11277*0 + 3*687*FLEN/8, x4, x1, x2)

inst_3760:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x0c97c9 and fs2 == 0 and fe2 == 0x02 and fm2 == 0x6911ef and fs3 == 0 and fe3 == 0x7f and fm3 == 0x6db6db and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7d8c97c9; op2val:0x16911ef;
op3val:0x3fedb6db; valaddr_reg:x3; val_offset:11280*0 + 3*688*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 11280*0 + 3*688*FLEN/8, x4, x1, x2)

inst_3761:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x0c97c9 and fs2 == 0 and fe2 == 0x02 and fm2 == 0x6911ef and fs3 == 0 and fe3 == 0x7f and fm3 == 0x7ffff8 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7d8c97c9; op2val:0x16911ef;
op3val:0x3ffffff8; valaddr_reg:x3; val_offset:11283*0 + 3*689*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 11283*0 + 3*689*FLEN/8, x4, x1, x2)

inst_3762:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x0c97c9 and fs2 == 0 and fe2 == 0x02 and fm2 == 0x6911ef and fs3 == 0 and fe3 == 0x7f and fm3 == 0x7ffffc and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7d8c97c9; op2val:0x16911ef;
op3val:0x3ffffffc; valaddr_reg:x3; val_offset:11286*0 + 3*690*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 11286*0 + 3*690*FLEN/8, x4, x1, x2)

inst_3763:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x0c97c9 and fs2 == 0 and fe2 == 0x02 and fm2 == 0x6911ef and fs3 == 0 and fe3 == 0x7f and fm3 == 0x7ffffe and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7d8c97c9; op2val:0x16911ef;
op3val:0x3ffffffe; valaddr_reg:x3; val_offset:11289*0 + 3*691*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 11289*0 + 3*691*FLEN/8, x4, x1, x2)

inst_3764:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x0f43fc and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7d8f43fc; op2val:0x80000000;
op3val:0x80000000; valaddr_reg:x3; val_offset:11292*0 + 3*692*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 11292*0 + 3*692*FLEN/8, x4, x1, x2)

inst_3765:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x0f43fc and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000001 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7d8f43fc; op2val:0x80000000;
op3val:0x80000001; valaddr_reg:x3; val_offset:11295*0 + 3*693*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 11295*0 + 3*693*FLEN/8, x4, x1, x2)

inst_3766:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x0f43fc and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000003 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7d8f43fc; op2val:0x80000000;
op3val:0x80000003; valaddr_reg:x3; val_offset:11298*0 + 3*694*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 11298*0 + 3*694*FLEN/8, x4, x1, x2)

inst_3767:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x0f43fc and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000007 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7d8f43fc; op2val:0x80000000;
op3val:0x80000007; valaddr_reg:x3; val_offset:11301*0 + 3*695*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 11301*0 + 3*695*FLEN/8, x4, x1, x2)

inst_3768:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x0f43fc and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x00000f and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7d8f43fc; op2val:0x80000000;
op3val:0x8000000f; valaddr_reg:x3; val_offset:11304*0 + 3*696*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 11304*0 + 3*696*FLEN/8, x4, x1, x2)

inst_3769:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x0f43fc and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x00001f and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7d8f43fc; op2val:0x80000000;
op3val:0x8000001f; valaddr_reg:x3; val_offset:11307*0 + 3*697*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 11307*0 + 3*697*FLEN/8, x4, x1, x2)

inst_3770:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x0f43fc and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x00003f and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7d8f43fc; op2val:0x80000000;
op3val:0x8000003f; valaddr_reg:x3; val_offset:11310*0 + 3*698*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 11310*0 + 3*698*FLEN/8, x4, x1, x2)

inst_3771:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x0f43fc and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x00007f and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7d8f43fc; op2val:0x80000000;
op3val:0x8000007f; valaddr_reg:x3; val_offset:11313*0 + 3*699*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 11313*0 + 3*699*FLEN/8, x4, x1, x2)

inst_3772:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x0f43fc and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x0000ff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7d8f43fc; op2val:0x80000000;
op3val:0x800000ff; valaddr_reg:x3; val_offset:11316*0 + 3*700*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 11316*0 + 3*700*FLEN/8, x4, x1, x2)

inst_3773:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x0f43fc and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x0001ff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7d8f43fc; op2val:0x80000000;
op3val:0x800001ff; valaddr_reg:x3; val_offset:11319*0 + 3*701*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 11319*0 + 3*701*FLEN/8, x4, x1, x2)

inst_3774:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x0f43fc and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x0003ff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7d8f43fc; op2val:0x80000000;
op3val:0x800003ff; valaddr_reg:x3; val_offset:11322*0 + 3*702*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 11322*0 + 3*702*FLEN/8, x4, x1, x2)

inst_3775:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x0f43fc and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x0007ff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7d8f43fc; op2val:0x80000000;
op3val:0x800007ff; valaddr_reg:x3; val_offset:11325*0 + 3*703*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 11325*0 + 3*703*FLEN/8, x4, x1, x2)

inst_3776:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x0f43fc and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000fff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7d8f43fc; op2val:0x80000000;
op3val:0x80000fff; valaddr_reg:x3; val_offset:11328*0 + 3*704*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 11328*0 + 3*704*FLEN/8, x4, x1, x2)

inst_3777:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x0f43fc and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x001fff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7d8f43fc; op2val:0x80000000;
op3val:0x80001fff; valaddr_reg:x3; val_offset:11331*0 + 3*705*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 11331*0 + 3*705*FLEN/8, x4, x1, x2)

inst_3778:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x0f43fc and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x003fff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7d8f43fc; op2val:0x80000000;
op3val:0x80003fff; valaddr_reg:x3; val_offset:11334*0 + 3*706*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 11334*0 + 3*706*FLEN/8, x4, x1, x2)

inst_3779:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x0f43fc and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x007fff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7d8f43fc; op2val:0x80000000;
op3val:0x80007fff; valaddr_reg:x3; val_offset:11337*0 + 3*707*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 11337*0 + 3*707*FLEN/8, x4, x1, x2)

inst_3780:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x0f43fc and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x00ffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7d8f43fc; op2val:0x80000000;
op3val:0x8000ffff; valaddr_reg:x3; val_offset:11340*0 + 3*708*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 11340*0 + 3*708*FLEN/8, x4, x1, x2)

inst_3781:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x0f43fc and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x01ffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7d8f43fc; op2val:0x80000000;
op3val:0x8001ffff; valaddr_reg:x3; val_offset:11343*0 + 3*709*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 11343*0 + 3*709*FLEN/8, x4, x1, x2)

inst_3782:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x0f43fc and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x03ffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7d8f43fc; op2val:0x80000000;
op3val:0x8003ffff; valaddr_reg:x3; val_offset:11346*0 + 3*710*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 11346*0 + 3*710*FLEN/8, x4, x1, x2)

inst_3783:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x0f43fc and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x07ffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7d8f43fc; op2val:0x80000000;
op3val:0x8007ffff; valaddr_reg:x3; val_offset:11349*0 + 3*711*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 11349*0 + 3*711*FLEN/8, x4, x1, x2)

inst_3784:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x0f43fc and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x0fffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7d8f43fc; op2val:0x80000000;
op3val:0x800fffff; valaddr_reg:x3; val_offset:11352*0 + 3*712*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 11352*0 + 3*712*FLEN/8, x4, x1, x2)

inst_3785:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x0f43fc and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x199999 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7d8f43fc; op2val:0x80000000;
op3val:0x80199999; valaddr_reg:x3; val_offset:11355*0 + 3*713*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 11355*0 + 3*713*FLEN/8, x4, x1, x2)

inst_3786:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x0f43fc and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x1fffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7d8f43fc; op2val:0x80000000;
op3val:0x801fffff; valaddr_reg:x3; val_offset:11358*0 + 3*714*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 11358*0 + 3*714*FLEN/8, x4, x1, x2)

inst_3787:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x0f43fc and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x249249 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7d8f43fc; op2val:0x80000000;
op3val:0x80249249; valaddr_reg:x3; val_offset:11361*0 + 3*715*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 11361*0 + 3*715*FLEN/8, x4, x1, x2)

inst_3788:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x0f43fc and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x333333 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7d8f43fc; op2val:0x80000000;
op3val:0x80333333; valaddr_reg:x3; val_offset:11364*0 + 3*716*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 11364*0 + 3*716*FLEN/8, x4, x1, x2)

inst_3789:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x0f43fc and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x36db6d and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7d8f43fc; op2val:0x80000000;
op3val:0x8036db6d; valaddr_reg:x3; val_offset:11367*0 + 3*717*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 11367*0 + 3*717*FLEN/8, x4, x1, x2)

inst_3790:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x0f43fc and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3bbbbb and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7d8f43fc; op2val:0x80000000;
op3val:0x803bbbbb; valaddr_reg:x3; val_offset:11370*0 + 3*718*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 11370*0 + 3*718*FLEN/8, x4, x1, x2)

inst_3791:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x0f43fc and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3fffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7d8f43fc; op2val:0x80000000;
op3val:0x803fffff; valaddr_reg:x3; val_offset:11373*0 + 3*719*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 11373*0 + 3*719*FLEN/8, x4, x1, x2)

inst_3792:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x0f43fc and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x400000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7d8f43fc; op2val:0x80000000;
op3val:0x80400000; valaddr_reg:x3; val_offset:11376*0 + 3*720*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 11376*0 + 3*720*FLEN/8, x4, x1, x2)

inst_3793:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x0f43fc and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x444444 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7d8f43fc; op2val:0x80000000;
op3val:0x80444444; valaddr_reg:x3; val_offset:11379*0 + 3*721*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 11379*0 + 3*721*FLEN/8, x4, x1, x2)

inst_3794:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x0f43fc and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x4ccccc and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7d8f43fc; op2val:0x80000000;
op3val:0x804ccccc; valaddr_reg:x3; val_offset:11382*0 + 3*722*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 11382*0 + 3*722*FLEN/8, x4, x1, x2)

inst_3795:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x0f43fc and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x5b6db6 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7d8f43fc; op2val:0x80000000;
op3val:0x805b6db6; valaddr_reg:x3; val_offset:11385*0 + 3*723*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 11385*0 + 3*723*FLEN/8, x4, x1, x2)

inst_3796:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x0f43fc and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x600000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7d8f43fc; op2val:0x80000000;
op3val:0x80600000; valaddr_reg:x3; val_offset:11388*0 + 3*724*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 11388*0 + 3*724*FLEN/8, x4, x1, x2)

inst_3797:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x0f43fc and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x666666 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7d8f43fc; op2val:0x80000000;
op3val:0x80666666; valaddr_reg:x3; val_offset:11391*0 + 3*725*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 11391*0 + 3*725*FLEN/8, x4, x1, x2)

inst_3798:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x0f43fc and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x6db6db and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7d8f43fc; op2val:0x80000000;
op3val:0x806db6db; valaddr_reg:x3; val_offset:11394*0 + 3*726*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 11394*0 + 3*726*FLEN/8, x4, x1, x2)

inst_3799:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x0f43fc and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x700000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7d8f43fc; op2val:0x80000000;
op3val:0x80700000; valaddr_reg:x3; val_offset:11397*0 + 3*727*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 11397*0 + 3*727*FLEN/8, x4, x1, x2)

inst_3800:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x0f43fc and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x780000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7d8f43fc; op2val:0x80000000;
op3val:0x80780000; valaddr_reg:x3; val_offset:11400*0 + 3*728*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 11400*0 + 3*728*FLEN/8, x4, x1, x2)

inst_3801:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x0f43fc and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7c0000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7d8f43fc; op2val:0x80000000;
op3val:0x807c0000; valaddr_reg:x3; val_offset:11403*0 + 3*729*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 11403*0 + 3*729*FLEN/8, x4, x1, x2)

inst_3802:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x0f43fc and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7e0000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7d8f43fc; op2val:0x80000000;
op3val:0x807e0000; valaddr_reg:x3; val_offset:11406*0 + 3*730*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 11406*0 + 3*730*FLEN/8, x4, x1, x2)

inst_3803:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x0f43fc and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7f0000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7d8f43fc; op2val:0x80000000;
op3val:0x807f0000; valaddr_reg:x3; val_offset:11409*0 + 3*731*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 11409*0 + 3*731*FLEN/8, x4, x1, x2)

inst_3804:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x0f43fc and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7f8000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7d8f43fc; op2val:0x80000000;
op3val:0x807f8000; valaddr_reg:x3; val_offset:11412*0 + 3*732*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 11412*0 + 3*732*FLEN/8, x4, x1, x2)

inst_3805:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x0f43fc and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7fc000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7d8f43fc; op2val:0x80000000;
op3val:0x807fc000; valaddr_reg:x3; val_offset:11415*0 + 3*733*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 11415*0 + 3*733*FLEN/8, x4, x1, x2)

inst_3806:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x0f43fc and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7fe000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7d8f43fc; op2val:0x80000000;
op3val:0x807fe000; valaddr_reg:x3; val_offset:11418*0 + 3*734*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 11418*0 + 3*734*FLEN/8, x4, x1, x2)

inst_3807:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x0f43fc and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7ff000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7d8f43fc; op2val:0x80000000;
op3val:0x807ff000; valaddr_reg:x3; val_offset:11421*0 + 3*735*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 11421*0 + 3*735*FLEN/8, x4, x1, x2)

inst_3808:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x0f43fc and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7ff800 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7d8f43fc; op2val:0x80000000;
op3val:0x807ff800; valaddr_reg:x3; val_offset:11424*0 + 3*736*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 11424*0 + 3*736*FLEN/8, x4, x1, x2)

inst_3809:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x0f43fc and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7ffc00 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7d8f43fc; op2val:0x80000000;
op3val:0x807ffc00; valaddr_reg:x3; val_offset:11427*0 + 3*737*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 11427*0 + 3*737*FLEN/8, x4, x1, x2)

inst_3810:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x0f43fc and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7ffe00 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7d8f43fc; op2val:0x80000000;
op3val:0x807ffe00; valaddr_reg:x3; val_offset:11430*0 + 3*738*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 11430*0 + 3*738*FLEN/8, x4, x1, x2)

inst_3811:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x0f43fc and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7fff00 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7d8f43fc; op2val:0x80000000;
op3val:0x807fff00; valaddr_reg:x3; val_offset:11433*0 + 3*739*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 11433*0 + 3*739*FLEN/8, x4, x1, x2)

inst_3812:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x0f43fc and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7fff80 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7d8f43fc; op2val:0x80000000;
op3val:0x807fff80; valaddr_reg:x3; val_offset:11436*0 + 3*740*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 11436*0 + 3*740*FLEN/8, x4, x1, x2)

inst_3813:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x0f43fc and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7fffc0 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7d8f43fc; op2val:0x80000000;
op3val:0x807fffc0; valaddr_reg:x3; val_offset:11439*0 + 3*741*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 11439*0 + 3*741*FLEN/8, x4, x1, x2)

inst_3814:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x0f43fc and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7fffe0 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7d8f43fc; op2val:0x80000000;
op3val:0x807fffe0; valaddr_reg:x3; val_offset:11442*0 + 3*742*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 11442*0 + 3*742*FLEN/8, x4, x1, x2)

inst_3815:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x0f43fc and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7ffff0 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7d8f43fc; op2val:0x80000000;
op3val:0x807ffff0; valaddr_reg:x3; val_offset:11445*0 + 3*743*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 11445*0 + 3*743*FLEN/8, x4, x1, x2)

inst_3816:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x0f43fc and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7ffff8 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7d8f43fc; op2val:0x80000000;
op3val:0x807ffff8; valaddr_reg:x3; val_offset:11448*0 + 3*744*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 11448*0 + 3*744*FLEN/8, x4, x1, x2)

inst_3817:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x0f43fc and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7ffffc and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7d8f43fc; op2val:0x80000000;
op3val:0x807ffffc; valaddr_reg:x3; val_offset:11451*0 + 3*745*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 11451*0 + 3*745*FLEN/8, x4, x1, x2)

inst_3818:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x0f43fc and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7ffffe and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7d8f43fc; op2val:0x80000000;
op3val:0x807ffffe; valaddr_reg:x3; val_offset:11454*0 + 3*746*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 11454*0 + 3*746*FLEN/8, x4, x1, x2)

inst_3819:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x0f43fc and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7fffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7d8f43fc; op2val:0x80000000;
op3val:0x807fffff; valaddr_reg:x3; val_offset:11457*0 + 3*747*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 11457*0 + 3*747*FLEN/8, x4, x1, x2)

inst_3820:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x0f9457 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000001 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7d8f9457; op2val:0x80000000;
op3val:0x80800001; valaddr_reg:x3; val_offset:11460*0 + 3*748*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 11460*0 + 3*748*FLEN/8, x4, x1, x2)

inst_3821:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x0f9457 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000003 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7d8f9457; op2val:0x80000000;
op3val:0x80800003; valaddr_reg:x3; val_offset:11463*0 + 3*749*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 11463*0 + 3*749*FLEN/8, x4, x1, x2)

inst_3822:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x0f9457 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000007 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7d8f9457; op2val:0x80000000;
op3val:0x80800007; valaddr_reg:x3; val_offset:11466*0 + 3*750*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 11466*0 + 3*750*FLEN/8, x4, x1, x2)

inst_3823:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x0f9457 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x199999 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7d8f9457; op2val:0x80000000;
op3val:0x80999999; valaddr_reg:x3; val_offset:11469*0 + 3*751*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 11469*0 + 3*751*FLEN/8, x4, x1, x2)

inst_3824:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x0f9457 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x249249 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7d8f9457; op2val:0x80000000;
op3val:0x80a49249; valaddr_reg:x3; val_offset:11472*0 + 3*752*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 11472*0 + 3*752*FLEN/8, x4, x1, x2)

inst_3825:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x0f9457 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x333333 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7d8f9457; op2val:0x80000000;
op3val:0x80b33333; valaddr_reg:x3; val_offset:11475*0 + 3*753*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 11475*0 + 3*753*FLEN/8, x4, x1, x2)

inst_3826:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x0f9457 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x36db6d and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7d8f9457; op2val:0x80000000;
op3val:0x80b6db6d; valaddr_reg:x3; val_offset:11478*0 + 3*754*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 11478*0 + 3*754*FLEN/8, x4, x1, x2)

inst_3827:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x0f9457 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x3bbbbb and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7d8f9457; op2val:0x80000000;
op3val:0x80bbbbbb; valaddr_reg:x3; val_offset:11481*0 + 3*755*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 11481*0 + 3*755*FLEN/8, x4, x1, x2)

inst_3828:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x0f9457 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x444444 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7d8f9457; op2val:0x80000000;
op3val:0x80c44444; valaddr_reg:x3; val_offset:11484*0 + 3*756*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 11484*0 + 3*756*FLEN/8, x4, x1, x2)

inst_3829:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x0f9457 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x4ccccc and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7d8f9457; op2val:0x80000000;
op3val:0x80cccccc; valaddr_reg:x3; val_offset:11487*0 + 3*757*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 11487*0 + 3*757*FLEN/8, x4, x1, x2)

inst_3830:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x0f9457 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x5b6db6 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7d8f9457; op2val:0x80000000;
op3val:0x80db6db6; valaddr_reg:x3; val_offset:11490*0 + 3*758*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 11490*0 + 3*758*FLEN/8, x4, x1, x2)

inst_3831:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x0f9457 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x666666 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7d8f9457; op2val:0x80000000;
op3val:0x80e66666; valaddr_reg:x3; val_offset:11493*0 + 3*759*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 11493*0 + 3*759*FLEN/8, x4, x1, x2)

inst_3832:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x0f9457 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x6db6db and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7d8f9457; op2val:0x80000000;
op3val:0x80edb6db; valaddr_reg:x3; val_offset:11496*0 + 3*760*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 11496*0 + 3*760*FLEN/8, x4, x1, x2)

inst_3833:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x0f9457 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x7ffff8 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7d8f9457; op2val:0x80000000;
op3val:0x80fffff8; valaddr_reg:x3; val_offset:11499*0 + 3*761*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 11499*0 + 3*761*FLEN/8, x4, x1, x2)

inst_3834:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x0f9457 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x7ffffc and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7d8f9457; op2val:0x80000000;
op3val:0x80fffffc; valaddr_reg:x3; val_offset:11502*0 + 3*762*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 11502*0 + 3*762*FLEN/8, x4, x1, x2)

inst_3835:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x0f9457 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x7ffffe and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7d8f9457; op2val:0x80000000;
op3val:0x80fffffe; valaddr_reg:x3; val_offset:11505*0 + 3*763*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 11505*0 + 3*763*FLEN/8, x4, x1, x2)

inst_3836:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x0f9457 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x13 and fm3 == 0x000000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7d8f9457; op2val:0x80000000;
op3val:0x89800000; valaddr_reg:x3; val_offset:11508*0 + 3*764*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 11508*0 + 3*764*FLEN/8, x4, x1, x2)

inst_3837:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x0f9457 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x13 and fm3 == 0x000001 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7d8f9457; op2val:0x80000000;
op3val:0x89800001; valaddr_reg:x3; val_offset:11511*0 + 3*765*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 11511*0 + 3*765*FLEN/8, x4, x1, x2)

inst_3838:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x0f9457 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x13 and fm3 == 0x000003 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7d8f9457; op2val:0x80000000;
op3val:0x89800003; valaddr_reg:x3; val_offset:11514*0 + 3*766*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 11514*0 + 3*766*FLEN/8, x4, x1, x2)

inst_3839:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x0f9457 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x13 and fm3 == 0x000007 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7d8f9457; op2val:0x80000000;
op3val:0x89800007; valaddr_reg:x3; val_offset:11517*0 + 3*767*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 11517*0 + 3*767*FLEN/8, x4, x1, x2)
#endif


RVTEST_CODE_END
RVMODEL_HALT

RVTEST_DATA_BEGIN
.align 4
rvtest_data:
.word 0xbabecafe
.word 0xabecafeb
.word 0xbecafeba
.word 0xecafebab
test_dataset_0:
NAN_BOXED(0x7d677175,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x857ffe00,32,FLEN)
NAN_BOXED(0x7d677175,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x857fff00,32,FLEN)
NAN_BOXED(0x7d677175,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x857fff80,32,FLEN)
NAN_BOXED(0x7d677175,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x857fffc0,32,FLEN)
NAN_BOXED(0x7d677175,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x857fffe0,32,FLEN)
NAN_BOXED(0x7d677175,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x857ffff0,32,FLEN)
NAN_BOXED(0x7d677175,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x857ffff8,32,FLEN)
NAN_BOXED(0x7d677175,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x857ffffc,32,FLEN)
NAN_BOXED(0x7d677175,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x857ffffe,32,FLEN)
NAN_BOXED(0x7d677175,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x857fffff,32,FLEN)
NAN_BOXED(0x7d6a9275,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x80000001,32,FLEN)
NAN_BOXED(0x7d6a9275,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x80000003,32,FLEN)
NAN_BOXED(0x7d6a9275,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x80000007,32,FLEN)
NAN_BOXED(0x7d6a9275,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x80199999,32,FLEN)
NAN_BOXED(0x7d6a9275,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x80249249,32,FLEN)
NAN_BOXED(0x7d6a9275,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x80333333,32,FLEN)
NAN_BOXED(0x7d6a9275,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x8036db6d,32,FLEN)
NAN_BOXED(0x7d6a9275,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x803bbbbb,32,FLEN)
NAN_BOXED(0x7d6a9275,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x80444444,32,FLEN)
NAN_BOXED(0x7d6a9275,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x804ccccc,32,FLEN)
NAN_BOXED(0x7d6a9275,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x805b6db6,32,FLEN)
NAN_BOXED(0x7d6a9275,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x80666666,32,FLEN)
NAN_BOXED(0x7d6a9275,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x806db6db,32,FLEN)
NAN_BOXED(0x7d6a9275,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x807ffff8,32,FLEN)
NAN_BOXED(0x7d6a9275,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x807ffffc,32,FLEN)
NAN_BOXED(0x7d6a9275,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x807ffffe,32,FLEN)
NAN_BOXED(0x7d6a9275,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x83000000,32,FLEN)
NAN_BOXED(0x7d6a9275,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x83000001,32,FLEN)
NAN_BOXED(0x7d6a9275,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x83000003,32,FLEN)
NAN_BOXED(0x7d6a9275,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x83000007,32,FLEN)
NAN_BOXED(0x7d6a9275,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x8300000f,32,FLEN)
NAN_BOXED(0x7d6a9275,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x8300001f,32,FLEN)
NAN_BOXED(0x7d6a9275,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x8300003f,32,FLEN)
NAN_BOXED(0x7d6a9275,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x8300007f,32,FLEN)
NAN_BOXED(0x7d6a9275,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x830000ff,32,FLEN)
NAN_BOXED(0x7d6a9275,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x830001ff,32,FLEN)
NAN_BOXED(0x7d6a9275,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x830003ff,32,FLEN)
NAN_BOXED(0x7d6a9275,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x830007ff,32,FLEN)
NAN_BOXED(0x7d6a9275,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x83000fff,32,FLEN)
NAN_BOXED(0x7d6a9275,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x83001fff,32,FLEN)
NAN_BOXED(0x7d6a9275,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x83003fff,32,FLEN)
NAN_BOXED(0x7d6a9275,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x83007fff,32,FLEN)
NAN_BOXED(0x7d6a9275,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x8300ffff,32,FLEN)
NAN_BOXED(0x7d6a9275,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x8301ffff,32,FLEN)
NAN_BOXED(0x7d6a9275,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x8303ffff,32,FLEN)
NAN_BOXED(0x7d6a9275,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x8307ffff,32,FLEN)
NAN_BOXED(0x7d6a9275,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x830fffff,32,FLEN)
NAN_BOXED(0x7d6a9275,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x831fffff,32,FLEN)
NAN_BOXED(0x7d6a9275,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x833fffff,32,FLEN)
NAN_BOXED(0x7d6a9275,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x83400000,32,FLEN)
NAN_BOXED(0x7d6a9275,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x83600000,32,FLEN)
NAN_BOXED(0x7d6a9275,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x83700000,32,FLEN)
NAN_BOXED(0x7d6a9275,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x83780000,32,FLEN)
NAN_BOXED(0x7d6a9275,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x837c0000,32,FLEN)
NAN_BOXED(0x7d6a9275,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x837e0000,32,FLEN)
NAN_BOXED(0x7d6a9275,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x837f0000,32,FLEN)
NAN_BOXED(0x7d6a9275,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x837f8000,32,FLEN)
NAN_BOXED(0x7d6a9275,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x837fc000,32,FLEN)
NAN_BOXED(0x7d6a9275,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x837fe000,32,FLEN)
NAN_BOXED(0x7d6a9275,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x837ff000,32,FLEN)
NAN_BOXED(0x7d6a9275,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x837ff800,32,FLEN)
NAN_BOXED(0x7d6a9275,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x837ffc00,32,FLEN)
NAN_BOXED(0x7d6a9275,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x837ffe00,32,FLEN)
NAN_BOXED(0x7d6a9275,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x837fff00,32,FLEN)
NAN_BOXED(0x7d6a9275,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x837fff80,32,FLEN)
NAN_BOXED(0x7d6a9275,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x837fffc0,32,FLEN)
NAN_BOXED(0x7d6a9275,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x837fffe0,32,FLEN)
NAN_BOXED(0x7d6a9275,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x837ffff0,32,FLEN)
NAN_BOXED(0x7d6a9275,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x837ffff8,32,FLEN)
NAN_BOXED(0x7d6a9275,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x837ffffc,32,FLEN)
NAN_BOXED(0x7d6a9275,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x837ffffe,32,FLEN)
NAN_BOXED(0x7d6a9275,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x837fffff,32,FLEN)
NAN_BOXED(0x7d72ea27,32,FLEN)
NAN_BOXED(0x186e525,32,FLEN)
NAN_BOXED(0x3f800001,32,FLEN)
NAN_BOXED(0x7d72ea27,32,FLEN)
NAN_BOXED(0x186e525,32,FLEN)
NAN_BOXED(0x3f800003,32,FLEN)
NAN_BOXED(0x7d72ea27,32,FLEN)
NAN_BOXED(0x186e525,32,FLEN)
NAN_BOXED(0x3f800007,32,FLEN)
NAN_BOXED(0x7d72ea27,32,FLEN)
NAN_BOXED(0x186e525,32,FLEN)
NAN_BOXED(0x3f999999,32,FLEN)
NAN_BOXED(0x7d72ea27,32,FLEN)
NAN_BOXED(0x186e525,32,FLEN)
NAN_BOXED(0x3fa49249,32,FLEN)
NAN_BOXED(0x7d72ea27,32,FLEN)
NAN_BOXED(0x186e525,32,FLEN)
NAN_BOXED(0x3fb33333,32,FLEN)
NAN_BOXED(0x7d72ea27,32,FLEN)
NAN_BOXED(0x186e525,32,FLEN)
NAN_BOXED(0x3fb6db6d,32,FLEN)
NAN_BOXED(0x7d72ea27,32,FLEN)
NAN_BOXED(0x186e525,32,FLEN)
NAN_BOXED(0x3fbbbbbb,32,FLEN)
NAN_BOXED(0x7d72ea27,32,FLEN)
NAN_BOXED(0x186e525,32,FLEN)
NAN_BOXED(0x3fc44444,32,FLEN)
NAN_BOXED(0x7d72ea27,32,FLEN)
NAN_BOXED(0x186e525,32,FLEN)
NAN_BOXED(0x3fcccccc,32,FLEN)
NAN_BOXED(0x7d72ea27,32,FLEN)
NAN_BOXED(0x186e525,32,FLEN)
NAN_BOXED(0x3fdb6db6,32,FLEN)
NAN_BOXED(0x7d72ea27,32,FLEN)
NAN_BOXED(0x186e525,32,FLEN)
NAN_BOXED(0x3fe66666,32,FLEN)
NAN_BOXED(0x7d72ea27,32,FLEN)
NAN_BOXED(0x186e525,32,FLEN)
NAN_BOXED(0x3fedb6db,32,FLEN)
NAN_BOXED(0x7d72ea27,32,FLEN)
NAN_BOXED(0x186e525,32,FLEN)
NAN_BOXED(0x3ffffff8,32,FLEN)
NAN_BOXED(0x7d72ea27,32,FLEN)
NAN_BOXED(0x186e525,32,FLEN)
NAN_BOXED(0x3ffffffc,32,FLEN)
NAN_BOXED(0x7d72ea27,32,FLEN)
NAN_BOXED(0x186e525,32,FLEN)
NAN_BOXED(0x3ffffffe,32,FLEN)
NAN_BOXED(0x7d72ea27,32,FLEN)
NAN_BOXED(0x186e525,32,FLEN)
NAN_BOXED(0x4f000000,32,FLEN)
NAN_BOXED(0x7d72ea27,32,FLEN)
NAN_BOXED(0x186e525,32,FLEN)
NAN_BOXED(0x4f000001,32,FLEN)
NAN_BOXED(0x7d72ea27,32,FLEN)
NAN_BOXED(0x186e525,32,FLEN)
NAN_BOXED(0x4f000003,32,FLEN)
NAN_BOXED(0x7d72ea27,32,FLEN)
NAN_BOXED(0x186e525,32,FLEN)
NAN_BOXED(0x4f000007,32,FLEN)
NAN_BOXED(0x7d72ea27,32,FLEN)
NAN_BOXED(0x186e525,32,FLEN)
NAN_BOXED(0x4f00000f,32,FLEN)
NAN_BOXED(0x7d72ea27,32,FLEN)
NAN_BOXED(0x186e525,32,FLEN)
NAN_BOXED(0x4f00001f,32,FLEN)
NAN_BOXED(0x7d72ea27,32,FLEN)
NAN_BOXED(0x186e525,32,FLEN)
NAN_BOXED(0x4f00003f,32,FLEN)
NAN_BOXED(0x7d72ea27,32,FLEN)
NAN_BOXED(0x186e525,32,FLEN)
NAN_BOXED(0x4f00007f,32,FLEN)
NAN_BOXED(0x7d72ea27,32,FLEN)
NAN_BOXED(0x186e525,32,FLEN)
NAN_BOXED(0x4f0000ff,32,FLEN)
NAN_BOXED(0x7d72ea27,32,FLEN)
NAN_BOXED(0x186e525,32,FLEN)
NAN_BOXED(0x4f0001ff,32,FLEN)
NAN_BOXED(0x7d72ea27,32,FLEN)
NAN_BOXED(0x186e525,32,FLEN)
NAN_BOXED(0x4f0003ff,32,FLEN)
NAN_BOXED(0x7d72ea27,32,FLEN)
NAN_BOXED(0x186e525,32,FLEN)
NAN_BOXED(0x4f0007ff,32,FLEN)
NAN_BOXED(0x7d72ea27,32,FLEN)
NAN_BOXED(0x186e525,32,FLEN)
NAN_BOXED(0x4f000fff,32,FLEN)
NAN_BOXED(0x7d72ea27,32,FLEN)
NAN_BOXED(0x186e525,32,FLEN)
NAN_BOXED(0x4f001fff,32,FLEN)
NAN_BOXED(0x7d72ea27,32,FLEN)
NAN_BOXED(0x186e525,32,FLEN)
NAN_BOXED(0x4f003fff,32,FLEN)
NAN_BOXED(0x7d72ea27,32,FLEN)
NAN_BOXED(0x186e525,32,FLEN)
NAN_BOXED(0x4f007fff,32,FLEN)
NAN_BOXED(0x7d72ea27,32,FLEN)
NAN_BOXED(0x186e525,32,FLEN)
NAN_BOXED(0x4f00ffff,32,FLEN)
NAN_BOXED(0x7d72ea27,32,FLEN)
NAN_BOXED(0x186e525,32,FLEN)
NAN_BOXED(0x4f01ffff,32,FLEN)
NAN_BOXED(0x7d72ea27,32,FLEN)
NAN_BOXED(0x186e525,32,FLEN)
NAN_BOXED(0x4f03ffff,32,FLEN)
NAN_BOXED(0x7d72ea27,32,FLEN)
NAN_BOXED(0x186e525,32,FLEN)
NAN_BOXED(0x4f07ffff,32,FLEN)
NAN_BOXED(0x7d72ea27,32,FLEN)
NAN_BOXED(0x186e525,32,FLEN)
NAN_BOXED(0x4f0fffff,32,FLEN)
NAN_BOXED(0x7d72ea27,32,FLEN)
NAN_BOXED(0x186e525,32,FLEN)
NAN_BOXED(0x4f1fffff,32,FLEN)
NAN_BOXED(0x7d72ea27,32,FLEN)
NAN_BOXED(0x186e525,32,FLEN)
NAN_BOXED(0x4f3fffff,32,FLEN)
NAN_BOXED(0x7d72ea27,32,FLEN)
NAN_BOXED(0x186e525,32,FLEN)
NAN_BOXED(0x4f400000,32,FLEN)
NAN_BOXED(0x7d72ea27,32,FLEN)
NAN_BOXED(0x186e525,32,FLEN)
NAN_BOXED(0x4f600000,32,FLEN)
NAN_BOXED(0x7d72ea27,32,FLEN)
NAN_BOXED(0x186e525,32,FLEN)
NAN_BOXED(0x4f700000,32,FLEN)
NAN_BOXED(0x7d72ea27,32,FLEN)
NAN_BOXED(0x186e525,32,FLEN)
NAN_BOXED(0x4f780000,32,FLEN)
NAN_BOXED(0x7d72ea27,32,FLEN)
NAN_BOXED(0x186e525,32,FLEN)
NAN_BOXED(0x4f7c0000,32,FLEN)
NAN_BOXED(0x7d72ea27,32,FLEN)
NAN_BOXED(0x186e525,32,FLEN)
NAN_BOXED(0x4f7e0000,32,FLEN)
NAN_BOXED(0x7d72ea27,32,FLEN)
NAN_BOXED(0x186e525,32,FLEN)
NAN_BOXED(0x4f7f0000,32,FLEN)
NAN_BOXED(0x7d72ea27,32,FLEN)
NAN_BOXED(0x186e525,32,FLEN)
NAN_BOXED(0x4f7f8000,32,FLEN)
NAN_BOXED(0x7d72ea27,32,FLEN)
NAN_BOXED(0x186e525,32,FLEN)
NAN_BOXED(0x4f7fc000,32,FLEN)
NAN_BOXED(0x7d72ea27,32,FLEN)
NAN_BOXED(0x186e525,32,FLEN)
NAN_BOXED(0x4f7fe000,32,FLEN)
NAN_BOXED(0x7d72ea27,32,FLEN)
NAN_BOXED(0x186e525,32,FLEN)
NAN_BOXED(0x4f7ff000,32,FLEN)
NAN_BOXED(0x7d72ea27,32,FLEN)
NAN_BOXED(0x186e525,32,FLEN)
NAN_BOXED(0x4f7ff800,32,FLEN)
NAN_BOXED(0x7d72ea27,32,FLEN)
NAN_BOXED(0x186e525,32,FLEN)
NAN_BOXED(0x4f7ffc00,32,FLEN)
NAN_BOXED(0x7d72ea27,32,FLEN)
NAN_BOXED(0x186e525,32,FLEN)
NAN_BOXED(0x4f7ffe00,32,FLEN)
NAN_BOXED(0x7d72ea27,32,FLEN)
NAN_BOXED(0x186e525,32,FLEN)
NAN_BOXED(0x4f7fff00,32,FLEN)
NAN_BOXED(0x7d72ea27,32,FLEN)
NAN_BOXED(0x186e525,32,FLEN)
NAN_BOXED(0x4f7fff80,32,FLEN)
NAN_BOXED(0x7d72ea27,32,FLEN)
NAN_BOXED(0x186e525,32,FLEN)
NAN_BOXED(0x4f7fffc0,32,FLEN)
NAN_BOXED(0x7d72ea27,32,FLEN)
NAN_BOXED(0x186e525,32,FLEN)
NAN_BOXED(0x4f7fffe0,32,FLEN)
NAN_BOXED(0x7d72ea27,32,FLEN)
NAN_BOXED(0x186e525,32,FLEN)
NAN_BOXED(0x4f7ffff0,32,FLEN)
NAN_BOXED(0x7d72ea27,32,FLEN)
NAN_BOXED(0x186e525,32,FLEN)
NAN_BOXED(0x4f7ffff8,32,FLEN)
NAN_BOXED(0x7d72ea27,32,FLEN)
NAN_BOXED(0x186e525,32,FLEN)
NAN_BOXED(0x4f7ffffc,32,FLEN)
NAN_BOXED(0x7d72ea27,32,FLEN)
NAN_BOXED(0x186e525,32,FLEN)
NAN_BOXED(0x4f7ffffe,32,FLEN)
NAN_BOXED(0x7d72ea27,32,FLEN)
NAN_BOXED(0x186e525,32,FLEN)
NAN_BOXED(0x4f7fffff,32,FLEN)
NAN_BOXED(0x7d7685d7,32,FLEN)
NAN_BOXED(0x184ebb6,32,FLEN)
NAN_BOXED(0x21800000,32,FLEN)
NAN_BOXED(0x7d7685d7,32,FLEN)
NAN_BOXED(0x184ebb6,32,FLEN)
NAN_BOXED(0x21800001,32,FLEN)
NAN_BOXED(0x7d7685d7,32,FLEN)
NAN_BOXED(0x184ebb6,32,FLEN)
NAN_BOXED(0x21800003,32,FLEN)
NAN_BOXED(0x7d7685d7,32,FLEN)
NAN_BOXED(0x184ebb6,32,FLEN)
NAN_BOXED(0x21800007,32,FLEN)
NAN_BOXED(0x7d7685d7,32,FLEN)
NAN_BOXED(0x184ebb6,32,FLEN)
NAN_BOXED(0x2180000f,32,FLEN)
NAN_BOXED(0x7d7685d7,32,FLEN)
NAN_BOXED(0x184ebb6,32,FLEN)
NAN_BOXED(0x2180001f,32,FLEN)
NAN_BOXED(0x7d7685d7,32,FLEN)
NAN_BOXED(0x184ebb6,32,FLEN)
NAN_BOXED(0x2180003f,32,FLEN)
NAN_BOXED(0x7d7685d7,32,FLEN)
NAN_BOXED(0x184ebb6,32,FLEN)
NAN_BOXED(0x2180007f,32,FLEN)
NAN_BOXED(0x7d7685d7,32,FLEN)
NAN_BOXED(0x184ebb6,32,FLEN)
NAN_BOXED(0x218000ff,32,FLEN)
NAN_BOXED(0x7d7685d7,32,FLEN)
NAN_BOXED(0x184ebb6,32,FLEN)
NAN_BOXED(0x218001ff,32,FLEN)
NAN_BOXED(0x7d7685d7,32,FLEN)
NAN_BOXED(0x184ebb6,32,FLEN)
NAN_BOXED(0x218003ff,32,FLEN)
NAN_BOXED(0x7d7685d7,32,FLEN)
NAN_BOXED(0x184ebb6,32,FLEN)
NAN_BOXED(0x218007ff,32,FLEN)
NAN_BOXED(0x7d7685d7,32,FLEN)
NAN_BOXED(0x184ebb6,32,FLEN)
NAN_BOXED(0x21800fff,32,FLEN)
NAN_BOXED(0x7d7685d7,32,FLEN)
NAN_BOXED(0x184ebb6,32,FLEN)
NAN_BOXED(0x21801fff,32,FLEN)
NAN_BOXED(0x7d7685d7,32,FLEN)
NAN_BOXED(0x184ebb6,32,FLEN)
NAN_BOXED(0x21803fff,32,FLEN)
NAN_BOXED(0x7d7685d7,32,FLEN)
NAN_BOXED(0x184ebb6,32,FLEN)
NAN_BOXED(0x21807fff,32,FLEN)
NAN_BOXED(0x7d7685d7,32,FLEN)
NAN_BOXED(0x184ebb6,32,FLEN)
NAN_BOXED(0x2180ffff,32,FLEN)
NAN_BOXED(0x7d7685d7,32,FLEN)
NAN_BOXED(0x184ebb6,32,FLEN)
NAN_BOXED(0x2181ffff,32,FLEN)
NAN_BOXED(0x7d7685d7,32,FLEN)
NAN_BOXED(0x184ebb6,32,FLEN)
NAN_BOXED(0x2183ffff,32,FLEN)
NAN_BOXED(0x7d7685d7,32,FLEN)
NAN_BOXED(0x184ebb6,32,FLEN)
NAN_BOXED(0x2187ffff,32,FLEN)
NAN_BOXED(0x7d7685d7,32,FLEN)
NAN_BOXED(0x184ebb6,32,FLEN)
NAN_BOXED(0x218fffff,32,FLEN)
NAN_BOXED(0x7d7685d7,32,FLEN)
NAN_BOXED(0x184ebb6,32,FLEN)
NAN_BOXED(0x219fffff,32,FLEN)
NAN_BOXED(0x7d7685d7,32,FLEN)
NAN_BOXED(0x184ebb6,32,FLEN)
NAN_BOXED(0x21bfffff,32,FLEN)
NAN_BOXED(0x7d7685d7,32,FLEN)
NAN_BOXED(0x184ebb6,32,FLEN)
NAN_BOXED(0x21c00000,32,FLEN)
NAN_BOXED(0x7d7685d7,32,FLEN)
NAN_BOXED(0x184ebb6,32,FLEN)
NAN_BOXED(0x21e00000,32,FLEN)
NAN_BOXED(0x7d7685d7,32,FLEN)
NAN_BOXED(0x184ebb6,32,FLEN)
NAN_BOXED(0x21f00000,32,FLEN)
NAN_BOXED(0x7d7685d7,32,FLEN)
NAN_BOXED(0x184ebb6,32,FLEN)
NAN_BOXED(0x21f80000,32,FLEN)
NAN_BOXED(0x7d7685d7,32,FLEN)
NAN_BOXED(0x184ebb6,32,FLEN)
NAN_BOXED(0x21fc0000,32,FLEN)
NAN_BOXED(0x7d7685d7,32,FLEN)
NAN_BOXED(0x184ebb6,32,FLEN)
NAN_BOXED(0x21fe0000,32,FLEN)
NAN_BOXED(0x7d7685d7,32,FLEN)
NAN_BOXED(0x184ebb6,32,FLEN)
NAN_BOXED(0x21ff0000,32,FLEN)
NAN_BOXED(0x7d7685d7,32,FLEN)
NAN_BOXED(0x184ebb6,32,FLEN)
NAN_BOXED(0x21ff8000,32,FLEN)
NAN_BOXED(0x7d7685d7,32,FLEN)
NAN_BOXED(0x184ebb6,32,FLEN)
NAN_BOXED(0x21ffc000,32,FLEN)
NAN_BOXED(0x7d7685d7,32,FLEN)
NAN_BOXED(0x184ebb6,32,FLEN)
NAN_BOXED(0x21ffe000,32,FLEN)
NAN_BOXED(0x7d7685d7,32,FLEN)
NAN_BOXED(0x184ebb6,32,FLEN)
NAN_BOXED(0x21fff000,32,FLEN)
NAN_BOXED(0x7d7685d7,32,FLEN)
NAN_BOXED(0x184ebb6,32,FLEN)
NAN_BOXED(0x21fff800,32,FLEN)
NAN_BOXED(0x7d7685d7,32,FLEN)
NAN_BOXED(0x184ebb6,32,FLEN)
NAN_BOXED(0x21fffc00,32,FLEN)
NAN_BOXED(0x7d7685d7,32,FLEN)
NAN_BOXED(0x184ebb6,32,FLEN)
NAN_BOXED(0x21fffe00,32,FLEN)
NAN_BOXED(0x7d7685d7,32,FLEN)
NAN_BOXED(0x184ebb6,32,FLEN)
NAN_BOXED(0x21ffff00,32,FLEN)
NAN_BOXED(0x7d7685d7,32,FLEN)
NAN_BOXED(0x184ebb6,32,FLEN)
NAN_BOXED(0x21ffff80,32,FLEN)
NAN_BOXED(0x7d7685d7,32,FLEN)
NAN_BOXED(0x184ebb6,32,FLEN)
NAN_BOXED(0x21ffffc0,32,FLEN)
NAN_BOXED(0x7d7685d7,32,FLEN)
NAN_BOXED(0x184ebb6,32,FLEN)
NAN_BOXED(0x21ffffe0,32,FLEN)
NAN_BOXED(0x7d7685d7,32,FLEN)
NAN_BOXED(0x184ebb6,32,FLEN)
NAN_BOXED(0x21fffff0,32,FLEN)
NAN_BOXED(0x7d7685d7,32,FLEN)
NAN_BOXED(0x184ebb6,32,FLEN)
NAN_BOXED(0x21fffff8,32,FLEN)
NAN_BOXED(0x7d7685d7,32,FLEN)
NAN_BOXED(0x184ebb6,32,FLEN)
NAN_BOXED(0x21fffffc,32,FLEN)
NAN_BOXED(0x7d7685d7,32,FLEN)
NAN_BOXED(0x184ebb6,32,FLEN)
NAN_BOXED(0x21fffffe,32,FLEN)
NAN_BOXED(0x7d7685d7,32,FLEN)
NAN_BOXED(0x184ebb6,32,FLEN)
NAN_BOXED(0x21ffffff,32,FLEN)
NAN_BOXED(0x7d7685d7,32,FLEN)
NAN_BOXED(0x184ebb6,32,FLEN)
NAN_BOXED(0x3f800001,32,FLEN)
NAN_BOXED(0x7d7685d7,32,FLEN)
NAN_BOXED(0x184ebb6,32,FLEN)
NAN_BOXED(0x3f800003,32,FLEN)
NAN_BOXED(0x7d7685d7,32,FLEN)
NAN_BOXED(0x184ebb6,32,FLEN)
NAN_BOXED(0x3f800007,32,FLEN)
NAN_BOXED(0x7d7685d7,32,FLEN)
NAN_BOXED(0x184ebb6,32,FLEN)
NAN_BOXED(0x3f999999,32,FLEN)
NAN_BOXED(0x7d7685d7,32,FLEN)
NAN_BOXED(0x184ebb6,32,FLEN)
NAN_BOXED(0x3fa49249,32,FLEN)
NAN_BOXED(0x7d7685d7,32,FLEN)
NAN_BOXED(0x184ebb6,32,FLEN)
NAN_BOXED(0x3fb33333,32,FLEN)
NAN_BOXED(0x7d7685d7,32,FLEN)
NAN_BOXED(0x184ebb6,32,FLEN)
NAN_BOXED(0x3fb6db6d,32,FLEN)
NAN_BOXED(0x7d7685d7,32,FLEN)
NAN_BOXED(0x184ebb6,32,FLEN)
NAN_BOXED(0x3fbbbbbb,32,FLEN)
NAN_BOXED(0x7d7685d7,32,FLEN)
NAN_BOXED(0x184ebb6,32,FLEN)
NAN_BOXED(0x3fc44444,32,FLEN)
NAN_BOXED(0x7d7685d7,32,FLEN)
NAN_BOXED(0x184ebb6,32,FLEN)
NAN_BOXED(0x3fcccccc,32,FLEN)
NAN_BOXED(0x7d7685d7,32,FLEN)
NAN_BOXED(0x184ebb6,32,FLEN)
NAN_BOXED(0x3fdb6db6,32,FLEN)
NAN_BOXED(0x7d7685d7,32,FLEN)
NAN_BOXED(0x184ebb6,32,FLEN)
NAN_BOXED(0x3fe66666,32,FLEN)
NAN_BOXED(0x7d7685d7,32,FLEN)
NAN_BOXED(0x184ebb6,32,FLEN)
NAN_BOXED(0x3fedb6db,32,FLEN)
NAN_BOXED(0x7d7685d7,32,FLEN)
NAN_BOXED(0x184ebb6,32,FLEN)
NAN_BOXED(0x3ffffff8,32,FLEN)
NAN_BOXED(0x7d7685d7,32,FLEN)
NAN_BOXED(0x184ebb6,32,FLEN)
NAN_BOXED(0x3ffffffc,32,FLEN)
NAN_BOXED(0x7d7685d7,32,FLEN)
NAN_BOXED(0x184ebb6,32,FLEN)
NAN_BOXED(0x3ffffffe,32,FLEN)
NAN_BOXED(0x7d772129,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x80000001,32,FLEN)
NAN_BOXED(0x7d772129,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x80000003,32,FLEN)
NAN_BOXED(0x7d772129,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x80000007,32,FLEN)
NAN_BOXED(0x7d772129,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x80199999,32,FLEN)
NAN_BOXED(0x7d772129,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x80249249,32,FLEN)
NAN_BOXED(0x7d772129,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x80333333,32,FLEN)
NAN_BOXED(0x7d772129,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x8036db6d,32,FLEN)
NAN_BOXED(0x7d772129,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x803bbbbb,32,FLEN)
NAN_BOXED(0x7d772129,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x80444444,32,FLEN)
NAN_BOXED(0x7d772129,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x804ccccc,32,FLEN)
NAN_BOXED(0x7d772129,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x805b6db6,32,FLEN)
NAN_BOXED(0x7d772129,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x80666666,32,FLEN)
NAN_BOXED(0x7d772129,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x806db6db,32,FLEN)
NAN_BOXED(0x7d772129,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x807ffff8,32,FLEN)
NAN_BOXED(0x7d772129,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x807ffffc,32,FLEN)
NAN_BOXED(0x7d772129,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x807ffffe,32,FLEN)
NAN_BOXED(0x7d772129,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x87000000,32,FLEN)
NAN_BOXED(0x7d772129,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x87000001,32,FLEN)
NAN_BOXED(0x7d772129,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x87000003,32,FLEN)
NAN_BOXED(0x7d772129,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x87000007,32,FLEN)
NAN_BOXED(0x7d772129,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x8700000f,32,FLEN)
NAN_BOXED(0x7d772129,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x8700001f,32,FLEN)
NAN_BOXED(0x7d772129,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x8700003f,32,FLEN)
NAN_BOXED(0x7d772129,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x8700007f,32,FLEN)
NAN_BOXED(0x7d772129,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x870000ff,32,FLEN)
NAN_BOXED(0x7d772129,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x870001ff,32,FLEN)
NAN_BOXED(0x7d772129,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x870003ff,32,FLEN)
NAN_BOXED(0x7d772129,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x870007ff,32,FLEN)
NAN_BOXED(0x7d772129,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x87000fff,32,FLEN)
NAN_BOXED(0x7d772129,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x87001fff,32,FLEN)
NAN_BOXED(0x7d772129,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x87003fff,32,FLEN)
NAN_BOXED(0x7d772129,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x87007fff,32,FLEN)
NAN_BOXED(0x7d772129,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x8700ffff,32,FLEN)
NAN_BOXED(0x7d772129,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x8701ffff,32,FLEN)
NAN_BOXED(0x7d772129,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x8703ffff,32,FLEN)
NAN_BOXED(0x7d772129,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x8707ffff,32,FLEN)
NAN_BOXED(0x7d772129,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x870fffff,32,FLEN)
NAN_BOXED(0x7d772129,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x871fffff,32,FLEN)
NAN_BOXED(0x7d772129,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x873fffff,32,FLEN)
NAN_BOXED(0x7d772129,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x87400000,32,FLEN)
NAN_BOXED(0x7d772129,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x87600000,32,FLEN)
NAN_BOXED(0x7d772129,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x87700000,32,FLEN)
NAN_BOXED(0x7d772129,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x87780000,32,FLEN)
NAN_BOXED(0x7d772129,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x877c0000,32,FLEN)
NAN_BOXED(0x7d772129,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x877e0000,32,FLEN)
NAN_BOXED(0x7d772129,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x877f0000,32,FLEN)
NAN_BOXED(0x7d772129,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x877f8000,32,FLEN)
NAN_BOXED(0x7d772129,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x877fc000,32,FLEN)
NAN_BOXED(0x7d772129,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x877fe000,32,FLEN)
NAN_BOXED(0x7d772129,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x877ff000,32,FLEN)
NAN_BOXED(0x7d772129,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x877ff800,32,FLEN)
NAN_BOXED(0x7d772129,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x877ffc00,32,FLEN)
NAN_BOXED(0x7d772129,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x877ffe00,32,FLEN)
NAN_BOXED(0x7d772129,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x877fff00,32,FLEN)
NAN_BOXED(0x7d772129,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x877fff80,32,FLEN)
NAN_BOXED(0x7d772129,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x877fffc0,32,FLEN)
NAN_BOXED(0x7d772129,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x877fffe0,32,FLEN)
NAN_BOXED(0x7d772129,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x877ffff0,32,FLEN)
NAN_BOXED(0x7d772129,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x877ffff8,32,FLEN)
NAN_BOXED(0x7d772129,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x877ffffc,32,FLEN)
NAN_BOXED(0x7d772129,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x877ffffe,32,FLEN)
NAN_BOXED(0x7d772129,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x877fffff,32,FLEN)
NAN_BOXED(0x7d77fb3b,32,FLEN)
NAN_BOXED(0x81842392,32,FLEN)
NAN_BOXED(0xa4000000,32,FLEN)
NAN_BOXED(0x7d77fb3b,32,FLEN)
NAN_BOXED(0x81842392,32,FLEN)
NAN_BOXED(0xa4000001,32,FLEN)
NAN_BOXED(0x7d77fb3b,32,FLEN)
NAN_BOXED(0x81842392,32,FLEN)
NAN_BOXED(0xa4000003,32,FLEN)
NAN_BOXED(0x7d77fb3b,32,FLEN)
NAN_BOXED(0x81842392,32,FLEN)
NAN_BOXED(0xa4000007,32,FLEN)
NAN_BOXED(0x7d77fb3b,32,FLEN)
NAN_BOXED(0x81842392,32,FLEN)
NAN_BOXED(0xa400000f,32,FLEN)
NAN_BOXED(0x7d77fb3b,32,FLEN)
NAN_BOXED(0x81842392,32,FLEN)
NAN_BOXED(0xa400001f,32,FLEN)
NAN_BOXED(0x7d77fb3b,32,FLEN)
NAN_BOXED(0x81842392,32,FLEN)
NAN_BOXED(0xa400003f,32,FLEN)
NAN_BOXED(0x7d77fb3b,32,FLEN)
NAN_BOXED(0x81842392,32,FLEN)
NAN_BOXED(0xa400007f,32,FLEN)
NAN_BOXED(0x7d77fb3b,32,FLEN)
NAN_BOXED(0x81842392,32,FLEN)
NAN_BOXED(0xa40000ff,32,FLEN)
NAN_BOXED(0x7d77fb3b,32,FLEN)
NAN_BOXED(0x81842392,32,FLEN)
NAN_BOXED(0xa40001ff,32,FLEN)
NAN_BOXED(0x7d77fb3b,32,FLEN)
NAN_BOXED(0x81842392,32,FLEN)
NAN_BOXED(0xa40003ff,32,FLEN)
NAN_BOXED(0x7d77fb3b,32,FLEN)
NAN_BOXED(0x81842392,32,FLEN)
NAN_BOXED(0xa40007ff,32,FLEN)
NAN_BOXED(0x7d77fb3b,32,FLEN)
NAN_BOXED(0x81842392,32,FLEN)
NAN_BOXED(0xa4000fff,32,FLEN)
NAN_BOXED(0x7d77fb3b,32,FLEN)
NAN_BOXED(0x81842392,32,FLEN)
NAN_BOXED(0xa4001fff,32,FLEN)
NAN_BOXED(0x7d77fb3b,32,FLEN)
NAN_BOXED(0x81842392,32,FLEN)
NAN_BOXED(0xa4003fff,32,FLEN)
NAN_BOXED(0x7d77fb3b,32,FLEN)
NAN_BOXED(0x81842392,32,FLEN)
NAN_BOXED(0xa4007fff,32,FLEN)
NAN_BOXED(0x7d77fb3b,32,FLEN)
NAN_BOXED(0x81842392,32,FLEN)
NAN_BOXED(0xa400ffff,32,FLEN)
NAN_BOXED(0x7d77fb3b,32,FLEN)
NAN_BOXED(0x81842392,32,FLEN)
NAN_BOXED(0xa401ffff,32,FLEN)
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NAN_BOXED(0x81842392,32,FLEN)
NAN_BOXED(0xa403ffff,32,FLEN)
NAN_BOXED(0x7d77fb3b,32,FLEN)
NAN_BOXED(0x81842392,32,FLEN)
NAN_BOXED(0xa407ffff,32,FLEN)
NAN_BOXED(0x7d77fb3b,32,FLEN)
NAN_BOXED(0x81842392,32,FLEN)
NAN_BOXED(0xa40fffff,32,FLEN)
NAN_BOXED(0x7d77fb3b,32,FLEN)
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NAN_BOXED(0xa41fffff,32,FLEN)
NAN_BOXED(0x7d77fb3b,32,FLEN)
NAN_BOXED(0x81842392,32,FLEN)
NAN_BOXED(0xa43fffff,32,FLEN)
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NAN_BOXED(0x81842392,32,FLEN)
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NAN_BOXED(0x81842392,32,FLEN)
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NAN_BOXED(0x81842392,32,FLEN)
NAN_BOXED(0xbfe66666,32,FLEN)
NAN_BOXED(0x7d77fb3b,32,FLEN)
NAN_BOXED(0x81842392,32,FLEN)
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NAN_BOXED(0x7d77fb3b,32,FLEN)
NAN_BOXED(0x81842392,32,FLEN)
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NAN_BOXED(0x7d77fb3b,32,FLEN)
NAN_BOXED(0x81842392,32,FLEN)
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NAN_BOXED(0x7d77fb3b,32,FLEN)
NAN_BOXED(0x81842392,32,FLEN)
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NAN_BOXED(0x4183ff9c,32,FLEN)
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NAN_BOXED(0x72000003,32,FLEN)
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NAN_BOXED(0x7d783eca,32,FLEN)
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NAN_BOXED(0x7d783eca,32,FLEN)
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NAN_BOXED(0x72001fff,32,FLEN)
NAN_BOXED(0x7d783eca,32,FLEN)
NAN_BOXED(0x4183ff9c,32,FLEN)
NAN_BOXED(0x72003fff,32,FLEN)
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NAN_BOXED(0x7d783eca,32,FLEN)
NAN_BOXED(0x4183ff9c,32,FLEN)
NAN_BOXED(0x7200ffff,32,FLEN)
NAN_BOXED(0x7d783eca,32,FLEN)
NAN_BOXED(0x4183ff9c,32,FLEN)
NAN_BOXED(0x7201ffff,32,FLEN)
NAN_BOXED(0x7d783eca,32,FLEN)
NAN_BOXED(0x4183ff9c,32,FLEN)
NAN_BOXED(0x7203ffff,32,FLEN)
NAN_BOXED(0x7d783eca,32,FLEN)
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NAN_BOXED(0x7207ffff,32,FLEN)
NAN_BOXED(0x7d783eca,32,FLEN)
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NAN_BOXED(0x721fffff,32,FLEN)
NAN_BOXED(0x7d783eca,32,FLEN)
NAN_BOXED(0x4183ff9c,32,FLEN)
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NAN_BOXED(0x7d783eca,32,FLEN)
NAN_BOXED(0x4183ff9c,32,FLEN)
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NAN_BOXED(0x7d783eca,32,FLEN)
NAN_BOXED(0x4183ff9c,32,FLEN)
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NAN_BOXED(0x7d783eca,32,FLEN)
NAN_BOXED(0x4183ff9c,32,FLEN)
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NAN_BOXED(0x4183ff9c,32,FLEN)
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NAN_BOXED(0x7d8081b9,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x83000fff,32,FLEN)
NAN_BOXED(0x7d8081b9,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x83001fff,32,FLEN)
NAN_BOXED(0x7d8081b9,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x83003fff,32,FLEN)
NAN_BOXED(0x7d8081b9,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x83007fff,32,FLEN)
NAN_BOXED(0x7d8081b9,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x8300ffff,32,FLEN)
NAN_BOXED(0x7d8081b9,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x8301ffff,32,FLEN)
NAN_BOXED(0x7d8081b9,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x8303ffff,32,FLEN)
NAN_BOXED(0x7d8081b9,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x8307ffff,32,FLEN)
NAN_BOXED(0x7d8081b9,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x830fffff,32,FLEN)
NAN_BOXED(0x7d8081b9,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x831fffff,32,FLEN)
NAN_BOXED(0x7d8081b9,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x833fffff,32,FLEN)
NAN_BOXED(0x7d8081b9,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x83400000,32,FLEN)
NAN_BOXED(0x7d8081b9,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x83600000,32,FLEN)
NAN_BOXED(0x7d8081b9,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x83700000,32,FLEN)
NAN_BOXED(0x7d8081b9,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x83780000,32,FLEN)
NAN_BOXED(0x7d8081b9,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x837c0000,32,FLEN)
NAN_BOXED(0x7d8081b9,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x837e0000,32,FLEN)
NAN_BOXED(0x7d8081b9,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x837f0000,32,FLEN)
NAN_BOXED(0x7d8081b9,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x837f8000,32,FLEN)
NAN_BOXED(0x7d8081b9,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x837fc000,32,FLEN)
NAN_BOXED(0x7d8081b9,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x837fe000,32,FLEN)
NAN_BOXED(0x7d8081b9,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x837ff000,32,FLEN)
NAN_BOXED(0x7d8081b9,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x837ff800,32,FLEN)
NAN_BOXED(0x7d8081b9,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x837ffc00,32,FLEN)
NAN_BOXED(0x7d8081b9,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x837ffe00,32,FLEN)
NAN_BOXED(0x7d8081b9,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x837fff00,32,FLEN)
NAN_BOXED(0x7d8081b9,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x837fff80,32,FLEN)
NAN_BOXED(0x7d8081b9,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x837fffc0,32,FLEN)
NAN_BOXED(0x7d8081b9,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x837fffe0,32,FLEN)
NAN_BOXED(0x7d8081b9,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x837ffff0,32,FLEN)
NAN_BOXED(0x7d8081b9,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x837ffff8,32,FLEN)
NAN_BOXED(0x7d8081b9,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x837ffffc,32,FLEN)
NAN_BOXED(0x7d8081b9,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x837ffffe,32,FLEN)
NAN_BOXED(0x7d8081b9,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x837fffff,32,FLEN)
NAN_BOXED(0x7d820308,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x1,32,FLEN)
NAN_BOXED(0x7d820308,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x3,32,FLEN)
NAN_BOXED(0x7d820308,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x7,32,FLEN)
NAN_BOXED(0x7d820308,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x199999,32,FLEN)
NAN_BOXED(0x7d820308,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x249249,32,FLEN)
NAN_BOXED(0x7d820308,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x333333,32,FLEN)
NAN_BOXED(0x7d820308,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x36db6d,32,FLEN)
NAN_BOXED(0x7d820308,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x3bbbbb,32,FLEN)
NAN_BOXED(0x7d820308,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x444444,32,FLEN)
NAN_BOXED(0x7d820308,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x4ccccc,32,FLEN)
NAN_BOXED(0x7d820308,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x5b6db6,32,FLEN)
NAN_BOXED(0x7d820308,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x666666,32,FLEN)
NAN_BOXED(0x7d820308,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x6db6db,32,FLEN)
NAN_BOXED(0x7d820308,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x7ffff8,32,FLEN)
NAN_BOXED(0x7d820308,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x7ffffc,32,FLEN)
NAN_BOXED(0x7d820308,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x7ffffe,32,FLEN)
NAN_BOXED(0x7d820308,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xb000000,32,FLEN)
NAN_BOXED(0x7d820308,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xb000001,32,FLEN)
NAN_BOXED(0x7d820308,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xb000003,32,FLEN)
NAN_BOXED(0x7d820308,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xb000007,32,FLEN)
NAN_BOXED(0x7d820308,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xb00000f,32,FLEN)
NAN_BOXED(0x7d820308,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xb00001f,32,FLEN)
NAN_BOXED(0x7d820308,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xb00003f,32,FLEN)
NAN_BOXED(0x7d820308,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xb00007f,32,FLEN)
NAN_BOXED(0x7d820308,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xb0000ff,32,FLEN)
NAN_BOXED(0x7d820308,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xb0001ff,32,FLEN)
NAN_BOXED(0x7d820308,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xb0003ff,32,FLEN)
NAN_BOXED(0x7d820308,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xb0007ff,32,FLEN)
NAN_BOXED(0x7d820308,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xb000fff,32,FLEN)
NAN_BOXED(0x7d820308,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xb001fff,32,FLEN)
NAN_BOXED(0x7d820308,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xb003fff,32,FLEN)
NAN_BOXED(0x7d820308,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xb007fff,32,FLEN)
NAN_BOXED(0x7d820308,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xb00ffff,32,FLEN)
NAN_BOXED(0x7d820308,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xb01ffff,32,FLEN)
NAN_BOXED(0x7d820308,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xb03ffff,32,FLEN)
NAN_BOXED(0x7d820308,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xb07ffff,32,FLEN)
NAN_BOXED(0x7d820308,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xb0fffff,32,FLEN)
NAN_BOXED(0x7d820308,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xb1fffff,32,FLEN)
NAN_BOXED(0x7d820308,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xb3fffff,32,FLEN)
NAN_BOXED(0x7d820308,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xb400000,32,FLEN)
NAN_BOXED(0x7d820308,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xb600000,32,FLEN)
NAN_BOXED(0x7d820308,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xb700000,32,FLEN)
NAN_BOXED(0x7d820308,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xb780000,32,FLEN)
NAN_BOXED(0x7d820308,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xb7c0000,32,FLEN)
NAN_BOXED(0x7d820308,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xb7e0000,32,FLEN)
NAN_BOXED(0x7d820308,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xb7f0000,32,FLEN)
NAN_BOXED(0x7d820308,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xb7f8000,32,FLEN)
NAN_BOXED(0x7d820308,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xb7fc000,32,FLEN)
NAN_BOXED(0x7d820308,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xb7fe000,32,FLEN)
NAN_BOXED(0x7d820308,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xb7ff000,32,FLEN)
NAN_BOXED(0x7d820308,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xb7ff800,32,FLEN)
NAN_BOXED(0x7d820308,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xb7ffc00,32,FLEN)
NAN_BOXED(0x7d820308,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xb7ffe00,32,FLEN)
NAN_BOXED(0x7d820308,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xb7fff00,32,FLEN)
NAN_BOXED(0x7d820308,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xb7fff80,32,FLEN)
NAN_BOXED(0x7d820308,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xb7fffc0,32,FLEN)
NAN_BOXED(0x7d820308,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xb7fffe0,32,FLEN)
NAN_BOXED(0x7d820308,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xb7ffff0,32,FLEN)
NAN_BOXED(0x7d820308,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xb7ffff8,32,FLEN)
NAN_BOXED(0x7d820308,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xb7ffffc,32,FLEN)
NAN_BOXED(0x7d820308,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xb7ffffe,32,FLEN)
NAN_BOXED(0x7d820308,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xb7fffff,32,FLEN)
NAN_BOXED(0x7d820d6d,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x1,32,FLEN)
NAN_BOXED(0x7d820d6d,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x3,32,FLEN)
NAN_BOXED(0x7d820d6d,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x7,32,FLEN)
NAN_BOXED(0x7d820d6d,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x199999,32,FLEN)
NAN_BOXED(0x7d820d6d,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x249249,32,FLEN)
NAN_BOXED(0x7d820d6d,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x333333,32,FLEN)
NAN_BOXED(0x7d820d6d,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x36db6d,32,FLEN)
NAN_BOXED(0x7d820d6d,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x3bbbbb,32,FLEN)
NAN_BOXED(0x7d820d6d,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x444444,32,FLEN)
NAN_BOXED(0x7d820d6d,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x4ccccc,32,FLEN)
NAN_BOXED(0x7d820d6d,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x5b6db6,32,FLEN)
NAN_BOXED(0x7d820d6d,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x666666,32,FLEN)
NAN_BOXED(0x7d820d6d,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x6db6db,32,FLEN)
NAN_BOXED(0x7d820d6d,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x7ffff8,32,FLEN)
NAN_BOXED(0x7d820d6d,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x7ffffc,32,FLEN)
NAN_BOXED(0x7d820d6d,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x7ffffe,32,FLEN)
NAN_BOXED(0x7d820d6d,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xf800000,32,FLEN)
NAN_BOXED(0x7d820d6d,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xf800001,32,FLEN)
NAN_BOXED(0x7d820d6d,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xf800003,32,FLEN)
NAN_BOXED(0x7d820d6d,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xf800007,32,FLEN)
NAN_BOXED(0x7d820d6d,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xf80000f,32,FLEN)
NAN_BOXED(0x7d820d6d,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xf80001f,32,FLEN)
NAN_BOXED(0x7d820d6d,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xf80003f,32,FLEN)
NAN_BOXED(0x7d820d6d,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xf80007f,32,FLEN)
NAN_BOXED(0x7d820d6d,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xf8000ff,32,FLEN)
NAN_BOXED(0x7d820d6d,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xf8001ff,32,FLEN)
NAN_BOXED(0x7d820d6d,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xf8003ff,32,FLEN)
NAN_BOXED(0x7d820d6d,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xf8007ff,32,FLEN)
NAN_BOXED(0x7d820d6d,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xf800fff,32,FLEN)
NAN_BOXED(0x7d820d6d,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xf801fff,32,FLEN)
NAN_BOXED(0x7d820d6d,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xf803fff,32,FLEN)
NAN_BOXED(0x7d820d6d,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xf807fff,32,FLEN)
NAN_BOXED(0x7d820d6d,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xf80ffff,32,FLEN)
NAN_BOXED(0x7d820d6d,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xf81ffff,32,FLEN)
NAN_BOXED(0x7d820d6d,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xf83ffff,32,FLEN)
NAN_BOXED(0x7d820d6d,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xf87ffff,32,FLEN)
NAN_BOXED(0x7d820d6d,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xf8fffff,32,FLEN)
NAN_BOXED(0x7d820d6d,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xf9fffff,32,FLEN)
NAN_BOXED(0x7d820d6d,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xfbfffff,32,FLEN)
NAN_BOXED(0x7d820d6d,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xfc00000,32,FLEN)
NAN_BOXED(0x7d820d6d,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xfe00000,32,FLEN)
NAN_BOXED(0x7d820d6d,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xff00000,32,FLEN)
NAN_BOXED(0x7d820d6d,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xff80000,32,FLEN)
NAN_BOXED(0x7d820d6d,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xffc0000,32,FLEN)
NAN_BOXED(0x7d820d6d,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xffe0000,32,FLEN)
NAN_BOXED(0x7d820d6d,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xfff0000,32,FLEN)
NAN_BOXED(0x7d820d6d,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xfff8000,32,FLEN)
NAN_BOXED(0x7d820d6d,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xfffc000,32,FLEN)
NAN_BOXED(0x7d820d6d,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xfffe000,32,FLEN)
NAN_BOXED(0x7d820d6d,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xffff000,32,FLEN)
NAN_BOXED(0x7d820d6d,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xffff800,32,FLEN)
NAN_BOXED(0x7d820d6d,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xffffc00,32,FLEN)
NAN_BOXED(0x7d820d6d,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xffffe00,32,FLEN)
NAN_BOXED(0x7d820d6d,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xfffff00,32,FLEN)
NAN_BOXED(0x7d820d6d,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xfffff80,32,FLEN)
NAN_BOXED(0x7d820d6d,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xfffffc0,32,FLEN)
NAN_BOXED(0x7d820d6d,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xfffffe0,32,FLEN)
NAN_BOXED(0x7d820d6d,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xffffff0,32,FLEN)
NAN_BOXED(0x7d820d6d,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xffffff8,32,FLEN)
NAN_BOXED(0x7d820d6d,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xffffffc,32,FLEN)
NAN_BOXED(0x7d820d6d,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xffffffe,32,FLEN)
NAN_BOXED(0x7d820d6d,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xfffffff,32,FLEN)
NAN_BOXED(0x7d8b3bce,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x80000001,32,FLEN)
NAN_BOXED(0x7d8b3bce,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x80000003,32,FLEN)
NAN_BOXED(0x7d8b3bce,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x80000007,32,FLEN)
NAN_BOXED(0x7d8b3bce,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x80199999,32,FLEN)
NAN_BOXED(0x7d8b3bce,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x80249249,32,FLEN)
NAN_BOXED(0x7d8b3bce,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x80333333,32,FLEN)
NAN_BOXED(0x7d8b3bce,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x8036db6d,32,FLEN)
NAN_BOXED(0x7d8b3bce,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x803bbbbb,32,FLEN)
NAN_BOXED(0x7d8b3bce,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x80444444,32,FLEN)
NAN_BOXED(0x7d8b3bce,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x804ccccc,32,FLEN)
NAN_BOXED(0x7d8b3bce,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x805b6db6,32,FLEN)
NAN_BOXED(0x7d8b3bce,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x80666666,32,FLEN)
NAN_BOXED(0x7d8b3bce,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x806db6db,32,FLEN)
NAN_BOXED(0x7d8b3bce,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x807ffff8,32,FLEN)
NAN_BOXED(0x7d8b3bce,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x807ffffc,32,FLEN)
NAN_BOXED(0x7d8b3bce,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x807ffffe,32,FLEN)
NAN_BOXED(0x7d8b3bce,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x81000000,32,FLEN)
NAN_BOXED(0x7d8b3bce,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x81000001,32,FLEN)
NAN_BOXED(0x7d8b3bce,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x81000003,32,FLEN)
NAN_BOXED(0x7d8b3bce,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x81000007,32,FLEN)
NAN_BOXED(0x7d8b3bce,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x8100000f,32,FLEN)
NAN_BOXED(0x7d8b3bce,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x8100001f,32,FLEN)
NAN_BOXED(0x7d8b3bce,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x8100003f,32,FLEN)
NAN_BOXED(0x7d8b3bce,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x8100007f,32,FLEN)
NAN_BOXED(0x7d8b3bce,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x810000ff,32,FLEN)
NAN_BOXED(0x7d8b3bce,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x810001ff,32,FLEN)
NAN_BOXED(0x7d8b3bce,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x810003ff,32,FLEN)
NAN_BOXED(0x7d8b3bce,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x810007ff,32,FLEN)
NAN_BOXED(0x7d8b3bce,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x81000fff,32,FLEN)
NAN_BOXED(0x7d8b3bce,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x81001fff,32,FLEN)
NAN_BOXED(0x7d8b3bce,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x81003fff,32,FLEN)
NAN_BOXED(0x7d8b3bce,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x81007fff,32,FLEN)
NAN_BOXED(0x7d8b3bce,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x8100ffff,32,FLEN)
NAN_BOXED(0x7d8b3bce,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x8101ffff,32,FLEN)
NAN_BOXED(0x7d8b3bce,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x8103ffff,32,FLEN)
NAN_BOXED(0x7d8b3bce,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x8107ffff,32,FLEN)
NAN_BOXED(0x7d8b3bce,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x810fffff,32,FLEN)
NAN_BOXED(0x7d8b3bce,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x811fffff,32,FLEN)
NAN_BOXED(0x7d8b3bce,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x813fffff,32,FLEN)
NAN_BOXED(0x7d8b3bce,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x81400000,32,FLEN)
NAN_BOXED(0x7d8b3bce,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x81600000,32,FLEN)
NAN_BOXED(0x7d8b3bce,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x81700000,32,FLEN)
NAN_BOXED(0x7d8b3bce,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x81780000,32,FLEN)
NAN_BOXED(0x7d8b3bce,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x817c0000,32,FLEN)
NAN_BOXED(0x7d8b3bce,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x817e0000,32,FLEN)
NAN_BOXED(0x7d8b3bce,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x817f0000,32,FLEN)
NAN_BOXED(0x7d8b3bce,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x817f8000,32,FLEN)
NAN_BOXED(0x7d8b3bce,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x817fc000,32,FLEN)
NAN_BOXED(0x7d8b3bce,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x817fe000,32,FLEN)
NAN_BOXED(0x7d8b3bce,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x817ff000,32,FLEN)
NAN_BOXED(0x7d8b3bce,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x817ff800,32,FLEN)
NAN_BOXED(0x7d8b3bce,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x817ffc00,32,FLEN)
NAN_BOXED(0x7d8b3bce,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x817ffe00,32,FLEN)
NAN_BOXED(0x7d8b3bce,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x817fff00,32,FLEN)
NAN_BOXED(0x7d8b3bce,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x817fff80,32,FLEN)
NAN_BOXED(0x7d8b3bce,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x817fffc0,32,FLEN)
NAN_BOXED(0x7d8b3bce,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x817fffe0,32,FLEN)
NAN_BOXED(0x7d8b3bce,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x817ffff0,32,FLEN)
NAN_BOXED(0x7d8b3bce,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x817ffff8,32,FLEN)
NAN_BOXED(0x7d8b3bce,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x817ffffc,32,FLEN)
NAN_BOXED(0x7d8b3bce,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x817ffffe,32,FLEN)
NAN_BOXED(0x7d8b3bce,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x817fffff,32,FLEN)
NAN_BOXED(0x7d8c97c9,32,FLEN)
NAN_BOXED(0x16911ef,32,FLEN)
NAN_BOXED(0x36800000,32,FLEN)
NAN_BOXED(0x7d8c97c9,32,FLEN)
NAN_BOXED(0x16911ef,32,FLEN)
NAN_BOXED(0x36800001,32,FLEN)
NAN_BOXED(0x7d8c97c9,32,FLEN)
NAN_BOXED(0x16911ef,32,FLEN)
NAN_BOXED(0x36800003,32,FLEN)
NAN_BOXED(0x7d8c97c9,32,FLEN)
NAN_BOXED(0x16911ef,32,FLEN)
NAN_BOXED(0x36800007,32,FLEN)
NAN_BOXED(0x7d8c97c9,32,FLEN)
NAN_BOXED(0x16911ef,32,FLEN)
NAN_BOXED(0x3680000f,32,FLEN)
NAN_BOXED(0x7d8c97c9,32,FLEN)
NAN_BOXED(0x16911ef,32,FLEN)
NAN_BOXED(0x3680001f,32,FLEN)
NAN_BOXED(0x7d8c97c9,32,FLEN)
NAN_BOXED(0x16911ef,32,FLEN)
NAN_BOXED(0x3680003f,32,FLEN)
NAN_BOXED(0x7d8c97c9,32,FLEN)
NAN_BOXED(0x16911ef,32,FLEN)
NAN_BOXED(0x3680007f,32,FLEN)
NAN_BOXED(0x7d8c97c9,32,FLEN)
NAN_BOXED(0x16911ef,32,FLEN)
NAN_BOXED(0x368000ff,32,FLEN)
NAN_BOXED(0x7d8c97c9,32,FLEN)
NAN_BOXED(0x16911ef,32,FLEN)
NAN_BOXED(0x368001ff,32,FLEN)
NAN_BOXED(0x7d8c97c9,32,FLEN)
NAN_BOXED(0x16911ef,32,FLEN)
NAN_BOXED(0x368003ff,32,FLEN)
NAN_BOXED(0x7d8c97c9,32,FLEN)
NAN_BOXED(0x16911ef,32,FLEN)
NAN_BOXED(0x368007ff,32,FLEN)
NAN_BOXED(0x7d8c97c9,32,FLEN)
NAN_BOXED(0x16911ef,32,FLEN)
NAN_BOXED(0x36800fff,32,FLEN)
NAN_BOXED(0x7d8c97c9,32,FLEN)
NAN_BOXED(0x16911ef,32,FLEN)
NAN_BOXED(0x36801fff,32,FLEN)
NAN_BOXED(0x7d8c97c9,32,FLEN)
NAN_BOXED(0x16911ef,32,FLEN)
NAN_BOXED(0x36803fff,32,FLEN)
NAN_BOXED(0x7d8c97c9,32,FLEN)
NAN_BOXED(0x16911ef,32,FLEN)
NAN_BOXED(0x36807fff,32,FLEN)
NAN_BOXED(0x7d8c97c9,32,FLEN)
NAN_BOXED(0x16911ef,32,FLEN)
NAN_BOXED(0x3680ffff,32,FLEN)
NAN_BOXED(0x7d8c97c9,32,FLEN)
NAN_BOXED(0x16911ef,32,FLEN)
NAN_BOXED(0x3681ffff,32,FLEN)
NAN_BOXED(0x7d8c97c9,32,FLEN)
NAN_BOXED(0x16911ef,32,FLEN)
NAN_BOXED(0x3683ffff,32,FLEN)
NAN_BOXED(0x7d8c97c9,32,FLEN)
NAN_BOXED(0x16911ef,32,FLEN)
NAN_BOXED(0x3687ffff,32,FLEN)
NAN_BOXED(0x7d8c97c9,32,FLEN)
NAN_BOXED(0x16911ef,32,FLEN)
NAN_BOXED(0x368fffff,32,FLEN)
NAN_BOXED(0x7d8c97c9,32,FLEN)
NAN_BOXED(0x16911ef,32,FLEN)
NAN_BOXED(0x369fffff,32,FLEN)
NAN_BOXED(0x7d8c97c9,32,FLEN)
NAN_BOXED(0x16911ef,32,FLEN)
NAN_BOXED(0x36bfffff,32,FLEN)
NAN_BOXED(0x7d8c97c9,32,FLEN)
NAN_BOXED(0x16911ef,32,FLEN)
NAN_BOXED(0x36c00000,32,FLEN)
NAN_BOXED(0x7d8c97c9,32,FLEN)
NAN_BOXED(0x16911ef,32,FLEN)
NAN_BOXED(0x36e00000,32,FLEN)
NAN_BOXED(0x7d8c97c9,32,FLEN)
NAN_BOXED(0x16911ef,32,FLEN)
NAN_BOXED(0x36f00000,32,FLEN)
NAN_BOXED(0x7d8c97c9,32,FLEN)
NAN_BOXED(0x16911ef,32,FLEN)
NAN_BOXED(0x36f80000,32,FLEN)
NAN_BOXED(0x7d8c97c9,32,FLEN)
NAN_BOXED(0x16911ef,32,FLEN)
NAN_BOXED(0x36fc0000,32,FLEN)
NAN_BOXED(0x7d8c97c9,32,FLEN)
NAN_BOXED(0x16911ef,32,FLEN)
NAN_BOXED(0x36fe0000,32,FLEN)
NAN_BOXED(0x7d8c97c9,32,FLEN)
NAN_BOXED(0x16911ef,32,FLEN)
NAN_BOXED(0x36ff0000,32,FLEN)
NAN_BOXED(0x7d8c97c9,32,FLEN)
NAN_BOXED(0x16911ef,32,FLEN)
NAN_BOXED(0x36ff8000,32,FLEN)
NAN_BOXED(0x7d8c97c9,32,FLEN)
NAN_BOXED(0x16911ef,32,FLEN)
NAN_BOXED(0x36ffc000,32,FLEN)
NAN_BOXED(0x7d8c97c9,32,FLEN)
NAN_BOXED(0x16911ef,32,FLEN)
NAN_BOXED(0x36ffe000,32,FLEN)
NAN_BOXED(0x7d8c97c9,32,FLEN)
NAN_BOXED(0x16911ef,32,FLEN)
NAN_BOXED(0x36fff000,32,FLEN)
NAN_BOXED(0x7d8c97c9,32,FLEN)
NAN_BOXED(0x16911ef,32,FLEN)
NAN_BOXED(0x36fff800,32,FLEN)
NAN_BOXED(0x7d8c97c9,32,FLEN)
NAN_BOXED(0x16911ef,32,FLEN)
NAN_BOXED(0x36fffc00,32,FLEN)
NAN_BOXED(0x7d8c97c9,32,FLEN)
NAN_BOXED(0x16911ef,32,FLEN)
NAN_BOXED(0x36fffe00,32,FLEN)
NAN_BOXED(0x7d8c97c9,32,FLEN)
NAN_BOXED(0x16911ef,32,FLEN)
NAN_BOXED(0x36ffff00,32,FLEN)
NAN_BOXED(0x7d8c97c9,32,FLEN)
NAN_BOXED(0x16911ef,32,FLEN)
NAN_BOXED(0x36ffff80,32,FLEN)
NAN_BOXED(0x7d8c97c9,32,FLEN)
NAN_BOXED(0x16911ef,32,FLEN)
NAN_BOXED(0x36ffffc0,32,FLEN)
NAN_BOXED(0x7d8c97c9,32,FLEN)
NAN_BOXED(0x16911ef,32,FLEN)
NAN_BOXED(0x36ffffe0,32,FLEN)
NAN_BOXED(0x7d8c97c9,32,FLEN)
NAN_BOXED(0x16911ef,32,FLEN)
NAN_BOXED(0x36fffff0,32,FLEN)
NAN_BOXED(0x7d8c97c9,32,FLEN)
NAN_BOXED(0x16911ef,32,FLEN)
NAN_BOXED(0x36fffff8,32,FLEN)
NAN_BOXED(0x7d8c97c9,32,FLEN)
NAN_BOXED(0x16911ef,32,FLEN)
NAN_BOXED(0x36fffffc,32,FLEN)
NAN_BOXED(0x7d8c97c9,32,FLEN)
NAN_BOXED(0x16911ef,32,FLEN)
NAN_BOXED(0x36fffffe,32,FLEN)
NAN_BOXED(0x7d8c97c9,32,FLEN)
NAN_BOXED(0x16911ef,32,FLEN)
NAN_BOXED(0x36ffffff,32,FLEN)
NAN_BOXED(0x7d8c97c9,32,FLEN)
NAN_BOXED(0x16911ef,32,FLEN)
NAN_BOXED(0x3f800001,32,FLEN)
NAN_BOXED(0x7d8c97c9,32,FLEN)
NAN_BOXED(0x16911ef,32,FLEN)
NAN_BOXED(0x3f800003,32,FLEN)
NAN_BOXED(0x7d8c97c9,32,FLEN)
NAN_BOXED(0x16911ef,32,FLEN)
NAN_BOXED(0x3f800007,32,FLEN)
NAN_BOXED(0x7d8c97c9,32,FLEN)
NAN_BOXED(0x16911ef,32,FLEN)
NAN_BOXED(0x3f999999,32,FLEN)
NAN_BOXED(0x7d8c97c9,32,FLEN)
NAN_BOXED(0x16911ef,32,FLEN)
NAN_BOXED(0x3fa49249,32,FLEN)
NAN_BOXED(0x7d8c97c9,32,FLEN)
NAN_BOXED(0x16911ef,32,FLEN)
NAN_BOXED(0x3fb33333,32,FLEN)
NAN_BOXED(0x7d8c97c9,32,FLEN)
NAN_BOXED(0x16911ef,32,FLEN)
NAN_BOXED(0x3fb6db6d,32,FLEN)
NAN_BOXED(0x7d8c97c9,32,FLEN)
NAN_BOXED(0x16911ef,32,FLEN)
NAN_BOXED(0x3fbbbbbb,32,FLEN)
NAN_BOXED(0x7d8c97c9,32,FLEN)
NAN_BOXED(0x16911ef,32,FLEN)
NAN_BOXED(0x3fc44444,32,FLEN)
NAN_BOXED(0x7d8c97c9,32,FLEN)
NAN_BOXED(0x16911ef,32,FLEN)
NAN_BOXED(0x3fcccccc,32,FLEN)
NAN_BOXED(0x7d8c97c9,32,FLEN)
NAN_BOXED(0x16911ef,32,FLEN)
NAN_BOXED(0x3fdb6db6,32,FLEN)
NAN_BOXED(0x7d8c97c9,32,FLEN)
NAN_BOXED(0x16911ef,32,FLEN)
NAN_BOXED(0x3fe66666,32,FLEN)
NAN_BOXED(0x7d8c97c9,32,FLEN)
NAN_BOXED(0x16911ef,32,FLEN)
NAN_BOXED(0x3fedb6db,32,FLEN)
NAN_BOXED(0x7d8c97c9,32,FLEN)
NAN_BOXED(0x16911ef,32,FLEN)
NAN_BOXED(0x3ffffff8,32,FLEN)
NAN_BOXED(0x7d8c97c9,32,FLEN)
NAN_BOXED(0x16911ef,32,FLEN)
NAN_BOXED(0x3ffffffc,32,FLEN)
NAN_BOXED(0x7d8c97c9,32,FLEN)
NAN_BOXED(0x16911ef,32,FLEN)
NAN_BOXED(0x3ffffffe,32,FLEN)
NAN_BOXED(0x7d8f43fc,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x7d8f43fc,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x80000001,32,FLEN)
NAN_BOXED(0x7d8f43fc,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x80000003,32,FLEN)
NAN_BOXED(0x7d8f43fc,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x80000007,32,FLEN)
NAN_BOXED(0x7d8f43fc,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x8000000f,32,FLEN)
NAN_BOXED(0x7d8f43fc,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x8000001f,32,FLEN)
NAN_BOXED(0x7d8f43fc,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x8000003f,32,FLEN)
NAN_BOXED(0x7d8f43fc,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x8000007f,32,FLEN)
NAN_BOXED(0x7d8f43fc,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x800000ff,32,FLEN)
NAN_BOXED(0x7d8f43fc,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x800001ff,32,FLEN)
NAN_BOXED(0x7d8f43fc,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x800003ff,32,FLEN)
NAN_BOXED(0x7d8f43fc,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x800007ff,32,FLEN)
NAN_BOXED(0x7d8f43fc,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x80000fff,32,FLEN)
NAN_BOXED(0x7d8f43fc,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x80001fff,32,FLEN)
NAN_BOXED(0x7d8f43fc,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x80003fff,32,FLEN)
NAN_BOXED(0x7d8f43fc,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x80007fff,32,FLEN)
NAN_BOXED(0x7d8f43fc,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x8000ffff,32,FLEN)
NAN_BOXED(0x7d8f43fc,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x8001ffff,32,FLEN)
NAN_BOXED(0x7d8f43fc,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x8003ffff,32,FLEN)
NAN_BOXED(0x7d8f43fc,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x8007ffff,32,FLEN)
NAN_BOXED(0x7d8f43fc,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x800fffff,32,FLEN)
NAN_BOXED(0x7d8f43fc,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x80199999,32,FLEN)
NAN_BOXED(0x7d8f43fc,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x801fffff,32,FLEN)
NAN_BOXED(0x7d8f43fc,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x80249249,32,FLEN)
NAN_BOXED(0x7d8f43fc,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x80333333,32,FLEN)
NAN_BOXED(0x7d8f43fc,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x8036db6d,32,FLEN)
NAN_BOXED(0x7d8f43fc,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x803bbbbb,32,FLEN)
NAN_BOXED(0x7d8f43fc,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x803fffff,32,FLEN)
NAN_BOXED(0x7d8f43fc,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x80400000,32,FLEN)
NAN_BOXED(0x7d8f43fc,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x80444444,32,FLEN)
NAN_BOXED(0x7d8f43fc,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x804ccccc,32,FLEN)
NAN_BOXED(0x7d8f43fc,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x805b6db6,32,FLEN)
NAN_BOXED(0x7d8f43fc,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x80600000,32,FLEN)
NAN_BOXED(0x7d8f43fc,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x80666666,32,FLEN)
NAN_BOXED(0x7d8f43fc,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x806db6db,32,FLEN)
NAN_BOXED(0x7d8f43fc,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x80700000,32,FLEN)
NAN_BOXED(0x7d8f43fc,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x80780000,32,FLEN)
NAN_BOXED(0x7d8f43fc,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x807c0000,32,FLEN)
NAN_BOXED(0x7d8f43fc,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x807e0000,32,FLEN)
NAN_BOXED(0x7d8f43fc,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x807f0000,32,FLEN)
NAN_BOXED(0x7d8f43fc,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x807f8000,32,FLEN)
NAN_BOXED(0x7d8f43fc,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x807fc000,32,FLEN)
NAN_BOXED(0x7d8f43fc,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x807fe000,32,FLEN)
NAN_BOXED(0x7d8f43fc,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x807ff000,32,FLEN)
NAN_BOXED(0x7d8f43fc,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x807ff800,32,FLEN)
NAN_BOXED(0x7d8f43fc,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x807ffc00,32,FLEN)
NAN_BOXED(0x7d8f43fc,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x807ffe00,32,FLEN)
NAN_BOXED(0x7d8f43fc,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x807fff00,32,FLEN)
NAN_BOXED(0x7d8f43fc,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x807fff80,32,FLEN)
NAN_BOXED(0x7d8f43fc,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x807fffc0,32,FLEN)
NAN_BOXED(0x7d8f43fc,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x807fffe0,32,FLEN)
NAN_BOXED(0x7d8f43fc,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x807ffff0,32,FLEN)
NAN_BOXED(0x7d8f43fc,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x807ffff8,32,FLEN)
NAN_BOXED(0x7d8f43fc,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x807ffffc,32,FLEN)
NAN_BOXED(0x7d8f43fc,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x807ffffe,32,FLEN)
NAN_BOXED(0x7d8f43fc,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x807fffff,32,FLEN)
NAN_BOXED(0x7d8f9457,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x80800001,32,FLEN)
NAN_BOXED(0x7d8f9457,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x80800003,32,FLEN)
NAN_BOXED(0x7d8f9457,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x80800007,32,FLEN)
NAN_BOXED(0x7d8f9457,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x80999999,32,FLEN)
NAN_BOXED(0x7d8f9457,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x80a49249,32,FLEN)
NAN_BOXED(0x7d8f9457,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x80b33333,32,FLEN)
NAN_BOXED(0x7d8f9457,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x80b6db6d,32,FLEN)
NAN_BOXED(0x7d8f9457,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x80bbbbbb,32,FLEN)
NAN_BOXED(0x7d8f9457,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x80c44444,32,FLEN)
NAN_BOXED(0x7d8f9457,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x80cccccc,32,FLEN)
NAN_BOXED(0x7d8f9457,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x80db6db6,32,FLEN)
NAN_BOXED(0x7d8f9457,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x80e66666,32,FLEN)
NAN_BOXED(0x7d8f9457,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x80edb6db,32,FLEN)
NAN_BOXED(0x7d8f9457,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x80fffff8,32,FLEN)
NAN_BOXED(0x7d8f9457,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x80fffffc,32,FLEN)
NAN_BOXED(0x7d8f9457,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x80fffffe,32,FLEN)
NAN_BOXED(0x7d8f9457,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x89800000,32,FLEN)
NAN_BOXED(0x7d8f9457,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x89800001,32,FLEN)
NAN_BOXED(0x7d8f9457,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x89800003,32,FLEN)
NAN_BOXED(0x7d8f9457,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x89800007,32,FLEN)
RVTEST_DATA_END

RVMODEL_DATA_BEGIN
rvtest_sig_begin:
sig_begin_canary:
CANARY;


signature_x1_0:
    .fill 0*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_1:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_2:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_3:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_4:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_5:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_6:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef

#ifdef rvtest_mtrap_routine

tsig_begin_canary:
CANARY;
tsig_begin_canary:
CANARY;
mtrap_sigptr:
    .fill 64*(XLEN/32),4,0xdeadbeef
tsig_end_canary:
CANARY;
tsig_end_canary:
CANARY;

#endif

#ifdef rvtest_gpr_save

gpr_save:
    .fill 32*XLEN/32,4,0xdeadbeef

#endif

sig_end_canary:
CANARY;
rvtest_sig_end:
RVMODEL_DATA_END
