
// -----------
// This file was generated by riscv_ctg (https://github.com/riscv-software-src/riscv-ctg)
// version   : 0.7.1
// timestamp : Thu Jun 30 09:50:01 2022 GMT
// usage     : riscv_ctg \
//                  -- cgf //                  --cgf /scratch/pawan/work/normalised/RV32F/fmv.x.w.cgf \
 \
//                  -- xlen 32  \
//                  --randomize \
// -----------
//
// -----------
// Copyright (c) 2020. RISC-V International. All rights reserved.
// SPDX-License-Identifier: BSD-3-Clause
// -----------
//
// This assembly file tests the fmv.x.w instruction of the RISC-V RV32F_Zicsr,RV32FD_Zicsr,RV64F_Zicsr,RV64FD_Zicsr extension for the fmv.x.w_b29 covergroup.
// 
#include "model_test.h"
#include "arch_test.h"
RVTEST_ISA("RV32IF_Zicsr,RV32IFD_Zicsr,RV64IF_Zicsr,RV64IFD_Zicsr")

.section .text.init
.globl rvtest_entry_point
rvtest_entry_point:
RVMODEL_BOOT
RVTEST_CODE_BEGIN

#ifdef TEST_CASE_1

RVTEST_CASE(0,"//check ISA:=regex(.*I.*F.*);def TEST_CASE_1=True;",fmv.x.w_b29)

RVTEST_FP_ENABLE()
RVTEST_VALBASEUPD(x17,test_dataset_0)
RVTEST_SIGBASE(x14,signature_x14_1)

inst_0:// rs1==f15, rd==x2,fs1 == 0 and fe1 == 0x7c and fm1 == 0x4923b8 and  fcsr == 0  
/* opcode: fmv.x.w ; op1:f15; dest:x2; op1val:0x3e4923b8; valaddr_reg:x17;
val_offset:0*FLEN/8; correctval:??; testreg:x18;
fcsr_val:0*/
TEST_FPID_OP_NRM(fmv.x.w, x2, f15, 0, 0, x17, 0*FLEN/8, x20, x14, x18)

inst_1:// rs1==f13, rd==x5,fs1 == 0 and fe1 == 0x7c and fm1 == 0x4923b9 and  fcsr == 0  
/* opcode: fmv.x.w ; op1:f13; dest:x5; op1val:0x3e4923b9; valaddr_reg:x17;
val_offset:1*FLEN/8; correctval:??; testreg:x18;
fcsr_val:0*/
TEST_FPID_OP_NRM(fmv.x.w, x5, f13, 0, 0, x17, 1*FLEN/8, x20, x14, x18)

inst_2:// rs1==f9, rd==x12,fs1 == 0 and fe1 == 0x7c and fm1 == 0x4923ba and  fcsr == 0  
/* opcode: fmv.x.w ; op1:f9; dest:x12; op1val:0x3e4923ba; valaddr_reg:x17;
val_offset:2*FLEN/8; correctval:??; testreg:x18;
fcsr_val:0*/
TEST_FPID_OP_NRM(fmv.x.w, x12, f9, 0, 0, x17, 2*FLEN/8, x20, x14, x18)

inst_3:// rs1==f31, rd==x16,fs1 == 0 and fe1 == 0x7c and fm1 == 0x4923bb and  fcsr == 0  
/* opcode: fmv.x.w ; op1:f31; dest:x16; op1val:0x3e4923bb; valaddr_reg:x17;
val_offset:3*FLEN/8; correctval:??; testreg:x18;
fcsr_val:0*/
TEST_FPID_OP_NRM(fmv.x.w, x16, f31, 0, 0, x17, 3*FLEN/8, x20, x14, x18)

inst_4:// rs1==f30, rd==x28,fs1 == 0 and fe1 == 0x7c and fm1 == 0x4923bc and  fcsr == 0  
/* opcode: fmv.x.w ; op1:f30; dest:x28; op1val:0x3e4923bc; valaddr_reg:x17;
val_offset:4*FLEN/8; correctval:??; testreg:x18;
fcsr_val:0*/
TEST_FPID_OP_NRM(fmv.x.w, x28, f30, 0, 0, x17, 4*FLEN/8, x20, x14, x18)

inst_5:// rs1==f12, rd==x21,fs1 == 0 and fe1 == 0x7c and fm1 == 0x4923bd and  fcsr == 0  
/* opcode: fmv.x.w ; op1:f12; dest:x21; op1val:0x3e4923bd; valaddr_reg:x17;
val_offset:5*FLEN/8; correctval:??; testreg:x18;
fcsr_val:0*/
TEST_FPID_OP_NRM(fmv.x.w, x21, f12, 0, 0, x17, 5*FLEN/8, x20, x14, x18)

inst_6:// rs1==f4, rd==x4,fs1 == 0 and fe1 == 0x7c and fm1 == 0x4923be and  fcsr == 0  
/* opcode: fmv.x.w ; op1:f4; dest:x4; op1val:0x3e4923be; valaddr_reg:x17;
val_offset:6*FLEN/8; correctval:??; testreg:x18;
fcsr_val:0*/
TEST_FPID_OP_NRM(fmv.x.w, x4, f4, 0, 0, x17, 6*FLEN/8, x20, x14, x18)

inst_7:// rs1==f1, rd==x22,fs1 == 0 and fe1 == 0x7c and fm1 == 0x4923bf and  fcsr == 0  
/* opcode: fmv.x.w ; op1:f1; dest:x22; op1val:0x3e4923bf; valaddr_reg:x17;
val_offset:7*FLEN/8; correctval:??; testreg:x18;
fcsr_val:0*/
TEST_FPID_OP_NRM(fmv.x.w, x22, f1, 0, 0, x17, 7*FLEN/8, x20, x14, x18)

inst_8:// rs1==f0, rd==x29,fs1 == 1 and fe1 == 0x7c and fm1 == 0x4923b8 and  fcsr == 0  
/* opcode: fmv.x.w ; op1:f0; dest:x29; op1val:0xbe4923b8; valaddr_reg:x17;
val_offset:8*FLEN/8; correctval:??; testreg:x18;
fcsr_val:0*/
TEST_FPID_OP_NRM(fmv.x.w, x29, f0, 0, 0, x17, 8*FLEN/8, x20, x14, x18)

inst_9:// rs1==f18, rd==x0,fs1 == 1 and fe1 == 0x7c and fm1 == 0x4923b9 and  fcsr == 0  
/* opcode: fmv.x.w ; op1:f18; dest:x0; op1val:0xbe4923b9; valaddr_reg:x17;
val_offset:9*FLEN/8; correctval:??; testreg:x18;
fcsr_val:0*/
TEST_FPID_OP_NRM(fmv.x.w, x0, f18, 0, 0, x17, 9*FLEN/8, x20, x14, x18)

inst_10:// rs1==f25, rd==x1,fs1 == 1 and fe1 == 0x7c and fm1 == 0x4923ba and  fcsr == 0  
/* opcode: fmv.x.w ; op1:f25; dest:x1; op1val:0xbe4923ba; valaddr_reg:x17;
val_offset:10*FLEN/8; correctval:??; testreg:x18;
fcsr_val:0*/
TEST_FPID_OP_NRM(fmv.x.w, x1, f25, 0, 0, x17, 10*FLEN/8, x20, x14, x18)

inst_11:// rs1==f14, rd==x26,fs1 == 1 and fe1 == 0x7c and fm1 == 0x4923bb and  fcsr == 0  
/* opcode: fmv.x.w ; op1:f14; dest:x26; op1val:0xbe4923bb; valaddr_reg:x17;
val_offset:11*FLEN/8; correctval:??; testreg:x18;
fcsr_val:0*/
TEST_FPID_OP_NRM(fmv.x.w, x26, f14, 0, 0, x17, 11*FLEN/8, x20, x14, x18)

inst_12:// rs1==f17, rd==x8,fs1 == 1 and fe1 == 0x7c and fm1 == 0x4923bc and  fcsr == 0  
/* opcode: fmv.x.w ; op1:f17; dest:x8; op1val:0xbe4923bc; valaddr_reg:x17;
val_offset:12*FLEN/8; correctval:??; testreg:x18;
fcsr_val:0*/
TEST_FPID_OP_NRM(fmv.x.w, x8, f17, 0, 0, x17, 12*FLEN/8, x20, x14, x18)

inst_13:// rs1==f10, rd==x31,fs1 == 1 and fe1 == 0x7c and fm1 == 0x4923bd and  fcsr == 0  
/* opcode: fmv.x.w ; op1:f10; dest:x31; op1val:0xbe4923bd; valaddr_reg:x17;
val_offset:13*FLEN/8; correctval:??; testreg:x18;
fcsr_val:0*/
TEST_FPID_OP_NRM(fmv.x.w, x31, f10, 0, 0, x17, 13*FLEN/8, x20, x14, x18)

inst_14:// rs1==f11, rd==x15,fs1 == 1 and fe1 == 0x7c and fm1 == 0x4923be and  fcsr == 0  
/* opcode: fmv.x.w ; op1:f11; dest:x15; op1val:0xbe4923be; valaddr_reg:x17;
val_offset:14*FLEN/8; correctval:??; testreg:x18;
fcsr_val:0*/
TEST_FPID_OP_NRM(fmv.x.w, x15, f11, 0, 0, x17, 14*FLEN/8, x20, x14, x18)

inst_15:// rs1==f29, rd==x6,fs1 == 1 and fe1 == 0x7c and fm1 == 0x4923bf and  fcsr == 0  
/* opcode: fmv.x.w ; op1:f29; dest:x6; op1val:0xbe4923bf; valaddr_reg:x17;
val_offset:15*FLEN/8; correctval:??; testreg:x18;
fcsr_val:0*/
TEST_FPID_OP_NRM(fmv.x.w, x6, f29, 0, 0, x17, 15*FLEN/8, x20, x14, x18)

inst_16:// rs1==f2, rd==x25,
/* opcode: fmv.x.w ; op1:f2; dest:x25; op1val:0x0; valaddr_reg:x17;
val_offset:16*FLEN/8; correctval:??; testreg:x18;
fcsr_val:0*/
TEST_FPID_OP_NRM(fmv.x.w, x25, f2, 0, 0, x17, 16*FLEN/8, x20, x14, x18)

inst_17:// rs1==f26, rd==x13,
/* opcode: fmv.x.w ; op1:f26; dest:x13; op1val:0x0; valaddr_reg:x17;
val_offset:17*FLEN/8; correctval:??; testreg:x18;
fcsr_val:0*/
TEST_FPID_OP_NRM(fmv.x.w, x13, f26, 0, 0, x17, 17*FLEN/8, x20, x14, x18)

inst_18:// rs1==f19, rd==x23,
/* opcode: fmv.x.w ; op1:f19; dest:x23; op1val:0x0; valaddr_reg:x17;
val_offset:18*FLEN/8; correctval:??; testreg:x18;
fcsr_val:0*/
TEST_FPID_OP_NRM(fmv.x.w, x23, f19, 0, 0, x17, 18*FLEN/8, x20, x14, x18)

inst_19:// rs1==f21, rd==x9,
/* opcode: fmv.x.w ; op1:f21; dest:x9; op1val:0x0; valaddr_reg:x17;
val_offset:19*FLEN/8; correctval:??; testreg:x18;
fcsr_val:0*/
TEST_FPID_OP_NRM(fmv.x.w, x9, f21, 0, 0, x17, 19*FLEN/8, x20, x14, x18)

inst_20:// rs1==f7, rd==x3,
/* opcode: fmv.x.w ; op1:f7; dest:x3; op1val:0x0; valaddr_reg:x17;
val_offset:20*FLEN/8; correctval:??; testreg:x18;
fcsr_val:0*/
TEST_FPID_OP_NRM(fmv.x.w, x3, f7, 0, 0, x17, 20*FLEN/8, x20, x14, x18)

inst_21:// rs1==f22, rd==x11,
/* opcode: fmv.x.w ; op1:f22; dest:x11; op1val:0x0; valaddr_reg:x17;
val_offset:21*FLEN/8; correctval:??; testreg:x18;
fcsr_val:0*/
TEST_FPID_OP_NRM(fmv.x.w, x11, f22, 0, 0, x17, 21*FLEN/8, x20, x14, x18)

inst_22:// rs1==f16, rd==x7,
/* opcode: fmv.x.w ; op1:f16; dest:x7; op1val:0x0; valaddr_reg:x17;
val_offset:22*FLEN/8; correctval:??; testreg:x18;
fcsr_val:0*/
TEST_FPID_OP_NRM(fmv.x.w, x7, f16, 0, 0, x17, 22*FLEN/8, x20, x14, x18)

inst_23:// rs1==f5, rd==x10,
/* opcode: fmv.x.w ; op1:f5; dest:x10; op1val:0x0; valaddr_reg:x17;
val_offset:23*FLEN/8; correctval:??; testreg:x18;
fcsr_val:0*/
TEST_FPID_OP_NRM(fmv.x.w, x10, f5, 0, 0, x17, 23*FLEN/8, x20, x14, x18)

inst_24:// rs1==f8, rd==x19,
/* opcode: fmv.x.w ; op1:f8; dest:x19; op1val:0x0; valaddr_reg:x17;
val_offset:24*FLEN/8; correctval:??; testreg:x18;
fcsr_val:0*/
TEST_FPID_OP_NRM(fmv.x.w, x19, f8, 0, 0, x17, 24*FLEN/8, x20, x14, x18)
RVTEST_VALBASEUPD(x3,test_dataset_1)

inst_25:// rs1==f28, rd==x20,
/* opcode: fmv.x.w ; op1:f28; dest:x20; op1val:0x0; valaddr_reg:x3;
val_offset:0*FLEN/8; correctval:??; testreg:x18;
fcsr_val:0*/
TEST_FPID_OP_NRM(fmv.x.w, x20, f28, 0, 0, x3, 0*FLEN/8, x4, x14, x18)

inst_26:// rs1==f6, rd==x17,
/* opcode: fmv.x.w ; op1:f6; dest:x17; op1val:0x0; valaddr_reg:x3;
val_offset:1*FLEN/8; correctval:??; testreg:x18;
fcsr_val:0*/
TEST_FPID_OP_NRM(fmv.x.w, x17, f6, 0, 0, x3, 1*FLEN/8, x4, x14, x18)

inst_27:// rs1==f3, rd==x27,
/* opcode: fmv.x.w ; op1:f3; dest:x27; op1val:0x0; valaddr_reg:x3;
val_offset:2*FLEN/8; correctval:??; testreg:x2;
fcsr_val:0*/
TEST_FPID_OP_NRM(fmv.x.w, x27, f3, 0, 0, x3, 2*FLEN/8, x4, x14, x2)
RVTEST_SIGBASE(x1,signature_x1_0)

inst_28:// rs1==f23, rd==x14,
/* opcode: fmv.x.w ; op1:f23; dest:x14; op1val:0x0; valaddr_reg:x3;
val_offset:3*FLEN/8; correctval:??; testreg:x2;
fcsr_val:0*/
TEST_FPID_OP_NRM(fmv.x.w, x14, f23, 0, 0, x3, 3*FLEN/8, x4, x1, x2)

inst_29:// rs1==f24, rd==x18,
/* opcode: fmv.x.w ; op1:f24; dest:x18; op1val:0x0; valaddr_reg:x3;
val_offset:4*FLEN/8; correctval:??; testreg:x2;
fcsr_val:0*/
TEST_FPID_OP_NRM(fmv.x.w, x18, f24, 0, 0, x3, 4*FLEN/8, x4, x1, x2)

inst_30:// rs1==f20, rd==x24,
/* opcode: fmv.x.w ; op1:f20; dest:x24; op1val:0x0; valaddr_reg:x3;
val_offset:5*FLEN/8; correctval:??; testreg:x2;
fcsr_val:0*/
TEST_FPID_OP_NRM(fmv.x.w, x24, f20, 0, 0, x3, 5*FLEN/8, x4, x1, x2)

inst_31:// rs1==f27, rd==x30,
/* opcode: fmv.x.w ; op1:f27; dest:x30; op1val:0x0; valaddr_reg:x3;
val_offset:6*FLEN/8; correctval:??; testreg:x2;
fcsr_val:0*/
TEST_FPID_OP_NRM(fmv.x.w, x30, f27, 0, 0, x3, 6*FLEN/8, x4, x1, x2)

inst_32:// fs1 == 1 and fe1 == 0x7c and fm1 == 0x4923b9 and  fcsr == 0  
/* opcode: fmv.x.w ; op1:f31; dest:x31; op1val:0xbe4923b9; valaddr_reg:x3;
val_offset:7*FLEN/8; correctval:??; testreg:x2;
fcsr_val:0*/
TEST_FPID_OP_NRM(fmv.x.w, x31, f31, 0, 0, x3, 7*FLEN/8, x4, x1, x2)
#endif


RVTEST_CODE_END
RVMODEL_HALT

RVTEST_DATA_BEGIN
.align 4
rvtest_data:
.word 0xbabecafe
.word 0xabecafeb
.word 0xbecafeba
.word 0xecafebab
test_dataset_0:
NAN_BOXED(0x3e4923b8,32,FLEN)
NAN_BOXED(0x3e4923b9,32,FLEN)
NAN_BOXED(0x3e4923ba,32,FLEN)
NAN_BOXED(0x3e4923bb,32,FLEN)
NAN_BOXED(0x3e4923bc,32,FLEN)
NAN_BOXED(0x3e4923bd,32,FLEN)
NAN_BOXED(0x3e4923be,32,FLEN)
NAN_BOXED(0x3e4923bf,32,FLEN)
NAN_BOXED(0xbe4923b8,32,FLEN)
NAN_BOXED(0xbe4923b9,32,FLEN)
NAN_BOXED(0xbe4923ba,32,FLEN)
NAN_BOXED(0xbe4923bb,32,FLEN)
NAN_BOXED(0xbe4923bc,32,FLEN)
NAN_BOXED(0xbe4923bd,32,FLEN)
NAN_BOXED(0xbe4923be,32,FLEN)
NAN_BOXED(0xbe4923bf,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
test_dataset_1:
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xbe4923b9,32,FLEN)
RVTEST_DATA_END

RVMODEL_DATA_BEGIN
rvtest_sig_begin:
sig_begin_canary:
CANARY;


signature_x14_0:
    .fill 0*((SIGALIGN)/4),4,0xdeadbeef


signature_x14_1:
    .fill 56*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_0:
    .fill 10*((SIGALIGN)/4),4,0xdeadbeef

#ifdef rvtest_mtrap_routine

tsig_begin_canary:
CANARY;
tsig_begin_canary:
CANARY;
mtrap_sigptr:
    .fill 64*(XLEN/32),4,0xdeadbeef
tsig_end_canary:
CANARY;
tsig_end_canary:
CANARY;

#endif

#ifdef rvtest_gpr_save

gpr_save:
    .fill 32*XLEN/32,4,0xdeadbeef

#endif

sig_end_canary:
CANARY;
rvtest_sig_end:
RVMODEL_DATA_END
