
// -----------
// This file was generated by riscv_ctg (https://github.com/riscv-software-src/riscv-ctg)
// version   : 0.11.0
// timestamp : Tue Jan 30 08:43:40 2024 GMT
// usage     : riscv_ctg \
//                  -- cgf //                  --cgf /home/riscv/riscv-ctg/sample_cgfs/dataset.cgf \
//                  --cgf /home/riscv/riscv-ctg/sample_cgfs/sample_cgfs_fext/RV32H/rv32h_fmadd.cgf \
 \
//                  -- xlen 32  \
// -----------
//
// -----------
// Copyright (c) 2020. RISC-V International. All rights reserved.
// SPDX-License-Identifier: BSD-3-Clause
// -----------
//
// This assembly file tests the fmadd.h instruction of the RISC-V RV32F_Zicsr_Zfh,RV64F_Zicsr_Zfh extension for the fmadd_b1 covergroup.
// 
#include "model_test.h"
#include "arch_test.h"
RVTEST_ISA("RV32IF_Zicsr_Zfh,RV64IF_Zicsr_Zfh")

.section .text.init
.globl rvtest_entry_point
rvtest_entry_point:
RVMODEL_BOOT
RVTEST_CODE_BEGIN

#ifdef TEST_CASE_1

RVTEST_CASE(0,"//check ISA:=regex(.*I.*F.*Zfh.*);def TEST_CASE_1=True;",fmadd_b1)

RVTEST_FP_ENABLE()
RVTEST_VALBASEUPD(x3,test_dataset_0)
RVTEST_SIGBASE(x1,signature_x1_1)

inst_3835:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x255 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3ff; op2val:0xfc00;
op3val:0xfe55; valaddr_reg:x3; val_offset:11505*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 11505*FLEN/8, x4, x1, x2)

inst_3836:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3ff; op2val:0xfc00;
op3val:0x7c01; valaddr_reg:x3; val_offset:11508*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 11508*FLEN/8, x4, x1, x2)

inst_3837:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x155 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3ff; op2val:0xfc00;
op3val:0xfd55; valaddr_reg:x3; val_offset:11511*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 11511*FLEN/8, x4, x1, x2)

inst_3838:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3ff; op2val:0xfc00;
op3val:0x3c00; valaddr_reg:x3; val_offset:11514*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 11514*FLEN/8, x4, x1, x2)

inst_3839:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3ff; op2val:0xfc00;
op3val:0xbc00; valaddr_reg:x3; val_offset:11517*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 11517*FLEN/8, x4, x1, x2)

RVTEST_SIGBASE(x1,signature_x1_31)
inst_3840:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3ff; op2val:0x7e00;
op3val:0x0; valaddr_reg:x3; val_offset:11520*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 11520*FLEN/8, x4, x1, x2)

inst_3841:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3ff; op2val:0x7e00;
op3val:0x8000; valaddr_reg:x3; val_offset:11523*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 11523*FLEN/8, x4, x1, x2)

inst_3842:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3ff; op2val:0x7e00;
op3val:0x1; valaddr_reg:x3; val_offset:11526*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 11526*FLEN/8, x4, x1, x2)

inst_3843:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3ff; op2val:0x7e00;
op3val:0x8001; valaddr_reg:x3; val_offset:11529*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 11529*FLEN/8, x4, x1, x2)

inst_3844:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x002 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3ff; op2val:0x7e00;
op3val:0x2; valaddr_reg:x3; val_offset:11532*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 11532*FLEN/8, x4, x1, x2)

inst_3845:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3fe and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3ff; op2val:0x7e00;
op3val:0x83fe; valaddr_reg:x3; val_offset:11535*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 11535*FLEN/8, x4, x1, x2)

inst_3846:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3ff; op2val:0x7e00;
op3val:0x3ff; valaddr_reg:x3; val_offset:11538*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 11538*FLEN/8, x4, x1, x2)

inst_3847:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3ff; op2val:0x7e00;
op3val:0x83ff; valaddr_reg:x3; val_offset:11541*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 11541*FLEN/8, x4, x1, x2)

inst_3848:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3ff; op2val:0x7e00;
op3val:0x400; valaddr_reg:x3; val_offset:11544*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 11544*FLEN/8, x4, x1, x2)

inst_3849:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3ff; op2val:0x7e00;
op3val:0x8400; valaddr_reg:x3; val_offset:11547*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 11547*FLEN/8, x4, x1, x2)

inst_3850:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3ff; op2val:0x7e00;
op3val:0x401; valaddr_reg:x3; val_offset:11550*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 11550*FLEN/8, x4, x1, x2)

inst_3851:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3ff; op2val:0x7e00;
op3val:0x8455; valaddr_reg:x3; val_offset:11553*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 11553*FLEN/8, x4, x1, x2)

inst_3852:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3ff; op2val:0x7e00;
op3val:0x7bff; valaddr_reg:x3; val_offset:11556*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 11556*FLEN/8, x4, x1, x2)

inst_3853:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3ff; op2val:0x7e00;
op3val:0xfbff; valaddr_reg:x3; val_offset:11559*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 11559*FLEN/8, x4, x1, x2)

inst_3854:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3ff; op2val:0x7e00;
op3val:0x7c00; valaddr_reg:x3; val_offset:11562*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 11562*FLEN/8, x4, x1, x2)

inst_3855:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3ff; op2val:0x7e00;
op3val:0xfc00; valaddr_reg:x3; val_offset:11565*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 11565*FLEN/8, x4, x1, x2)

inst_3856:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3ff; op2val:0x7e00;
op3val:0x7e00; valaddr_reg:x3; val_offset:11568*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 11568*FLEN/8, x4, x1, x2)

inst_3857:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3ff; op2val:0x7e00;
op3val:0xfe00; valaddr_reg:x3; val_offset:11571*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 11571*FLEN/8, x4, x1, x2)

inst_3858:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x201 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3ff; op2val:0x7e00;
op3val:0x7e01; valaddr_reg:x3; val_offset:11574*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 11574*FLEN/8, x4, x1, x2)

inst_3859:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x255 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3ff; op2val:0x7e00;
op3val:0xfe55; valaddr_reg:x3; val_offset:11577*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 11577*FLEN/8, x4, x1, x2)

inst_3860:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3ff; op2val:0x7e00;
op3val:0x7c01; valaddr_reg:x3; val_offset:11580*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 11580*FLEN/8, x4, x1, x2)

inst_3861:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x155 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3ff; op2val:0x7e00;
op3val:0xfd55; valaddr_reg:x3; val_offset:11583*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 11583*FLEN/8, x4, x1, x2)

inst_3862:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 0 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3ff; op2val:0x7e00;
op3val:0x3c00; valaddr_reg:x3; val_offset:11586*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 11586*FLEN/8, x4, x1, x2)

inst_3863:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 1 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3ff; op2val:0x7e00;
op3val:0xbc00; valaddr_reg:x3; val_offset:11589*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 11589*FLEN/8, x4, x1, x2)

inst_3864:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3ff; op2val:0xfe00;
op3val:0x0; valaddr_reg:x3; val_offset:11592*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 11592*FLEN/8, x4, x1, x2)

inst_3865:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3ff; op2val:0xfe00;
op3val:0x8000; valaddr_reg:x3; val_offset:11595*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 11595*FLEN/8, x4, x1, x2)

inst_3866:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3ff; op2val:0xfe00;
op3val:0x1; valaddr_reg:x3; val_offset:11598*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 11598*FLEN/8, x4, x1, x2)

inst_3867:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3ff; op2val:0xfe00;
op3val:0x8001; valaddr_reg:x3; val_offset:11601*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 11601*FLEN/8, x4, x1, x2)

inst_3868:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x002 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3ff; op2val:0xfe00;
op3val:0x2; valaddr_reg:x3; val_offset:11604*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 11604*FLEN/8, x4, x1, x2)

inst_3869:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3fe and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3ff; op2val:0xfe00;
op3val:0x83fe; valaddr_reg:x3; val_offset:11607*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 11607*FLEN/8, x4, x1, x2)

inst_3870:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3ff; op2val:0xfe00;
op3val:0x3ff; valaddr_reg:x3; val_offset:11610*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 11610*FLEN/8, x4, x1, x2)

inst_3871:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3ff; op2val:0xfe00;
op3val:0x83ff; valaddr_reg:x3; val_offset:11613*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 11613*FLEN/8, x4, x1, x2)

inst_3872:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3ff; op2val:0xfe00;
op3val:0x400; valaddr_reg:x3; val_offset:11616*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 11616*FLEN/8, x4, x1, x2)

inst_3873:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3ff; op2val:0xfe00;
op3val:0x8400; valaddr_reg:x3; val_offset:11619*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 11619*FLEN/8, x4, x1, x2)

inst_3874:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3ff; op2val:0xfe00;
op3val:0x401; valaddr_reg:x3; val_offset:11622*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 11622*FLEN/8, x4, x1, x2)

inst_3875:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3ff; op2val:0xfe00;
op3val:0x8455; valaddr_reg:x3; val_offset:11625*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 11625*FLEN/8, x4, x1, x2)

inst_3876:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3ff; op2val:0xfe00;
op3val:0x7bff; valaddr_reg:x3; val_offset:11628*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 11628*FLEN/8, x4, x1, x2)

inst_3877:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3ff; op2val:0xfe00;
op3val:0xfbff; valaddr_reg:x3; val_offset:11631*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 11631*FLEN/8, x4, x1, x2)

inst_3878:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3ff; op2val:0xfe00;
op3val:0x7c00; valaddr_reg:x3; val_offset:11634*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 11634*FLEN/8, x4, x1, x2)

inst_3879:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3ff; op2val:0xfe00;
op3val:0xfc00; valaddr_reg:x3; val_offset:11637*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 11637*FLEN/8, x4, x1, x2)

inst_3880:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3ff; op2val:0xfe00;
op3val:0x7e00; valaddr_reg:x3; val_offset:11640*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 11640*FLEN/8, x4, x1, x2)

inst_3881:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3ff; op2val:0xfe00;
op3val:0xfe00; valaddr_reg:x3; val_offset:11643*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 11643*FLEN/8, x4, x1, x2)

inst_3882:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x201 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3ff; op2val:0xfe00;
op3val:0x7e01; valaddr_reg:x3; val_offset:11646*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 11646*FLEN/8, x4, x1, x2)

inst_3883:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x255 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3ff; op2val:0xfe00;
op3val:0xfe55; valaddr_reg:x3; val_offset:11649*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 11649*FLEN/8, x4, x1, x2)

inst_3884:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3ff; op2val:0xfe00;
op3val:0x7c01; valaddr_reg:x3; val_offset:11652*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 11652*FLEN/8, x4, x1, x2)

inst_3885:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x155 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3ff; op2val:0xfe00;
op3val:0xfd55; valaddr_reg:x3; val_offset:11655*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 11655*FLEN/8, x4, x1, x2)

inst_3886:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 0 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3ff; op2val:0xfe00;
op3val:0x3c00; valaddr_reg:x3; val_offset:11658*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 11658*FLEN/8, x4, x1, x2)

inst_3887:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 1 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3ff; op2val:0xfe00;
op3val:0xbc00; valaddr_reg:x3; val_offset:11661*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 11661*FLEN/8, x4, x1, x2)

inst_3888:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3ff; op2val:0x7e01;
op3val:0x0; valaddr_reg:x3; val_offset:11664*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 11664*FLEN/8, x4, x1, x2)

inst_3889:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3ff; op2val:0x7e01;
op3val:0x8000; valaddr_reg:x3; val_offset:11667*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 11667*FLEN/8, x4, x1, x2)

inst_3890:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3ff; op2val:0x7e01;
op3val:0x1; valaddr_reg:x3; val_offset:11670*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 11670*FLEN/8, x4, x1, x2)

inst_3891:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3ff; op2val:0x7e01;
op3val:0x8001; valaddr_reg:x3; val_offset:11673*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 11673*FLEN/8, x4, x1, x2)

inst_3892:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x002 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3ff; op2val:0x7e01;
op3val:0x2; valaddr_reg:x3; val_offset:11676*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 11676*FLEN/8, x4, x1, x2)

inst_3893:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3fe and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3ff; op2val:0x7e01;
op3val:0x83fe; valaddr_reg:x3; val_offset:11679*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 11679*FLEN/8, x4, x1, x2)

inst_3894:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3ff; op2val:0x7e01;
op3val:0x3ff; valaddr_reg:x3; val_offset:11682*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 11682*FLEN/8, x4, x1, x2)

inst_3895:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3ff; op2val:0x7e01;
op3val:0x83ff; valaddr_reg:x3; val_offset:11685*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 11685*FLEN/8, x4, x1, x2)

inst_3896:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3ff; op2val:0x7e01;
op3val:0x400; valaddr_reg:x3; val_offset:11688*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 11688*FLEN/8, x4, x1, x2)

inst_3897:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3ff; op2val:0x7e01;
op3val:0x8400; valaddr_reg:x3; val_offset:11691*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 11691*FLEN/8, x4, x1, x2)

inst_3898:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3ff; op2val:0x7e01;
op3val:0x401; valaddr_reg:x3; val_offset:11694*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 11694*FLEN/8, x4, x1, x2)

inst_3899:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3ff; op2val:0x7e01;
op3val:0x8455; valaddr_reg:x3; val_offset:11697*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 11697*FLEN/8, x4, x1, x2)

inst_3900:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3ff; op2val:0x7e01;
op3val:0x7bff; valaddr_reg:x3; val_offset:11700*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 11700*FLEN/8, x4, x1, x2)

inst_3901:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3ff; op2val:0x7e01;
op3val:0xfbff; valaddr_reg:x3; val_offset:11703*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 11703*FLEN/8, x4, x1, x2)

inst_3902:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3ff; op2val:0x7e01;
op3val:0x7c00; valaddr_reg:x3; val_offset:11706*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 11706*FLEN/8, x4, x1, x2)

inst_3903:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3ff; op2val:0x7e01;
op3val:0xfc00; valaddr_reg:x3; val_offset:11709*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 11709*FLEN/8, x4, x1, x2)

inst_3904:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3ff; op2val:0x7e01;
op3val:0x7e00; valaddr_reg:x3; val_offset:11712*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 11712*FLEN/8, x4, x1, x2)

inst_3905:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3ff; op2val:0x7e01;
op3val:0xfe00; valaddr_reg:x3; val_offset:11715*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 11715*FLEN/8, x4, x1, x2)

inst_3906:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x201 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3ff; op2val:0x7e01;
op3val:0x7e01; valaddr_reg:x3; val_offset:11718*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 11718*FLEN/8, x4, x1, x2)

inst_3907:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x255 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3ff; op2val:0x7e01;
op3val:0xfe55; valaddr_reg:x3; val_offset:11721*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 11721*FLEN/8, x4, x1, x2)

inst_3908:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3ff; op2val:0x7e01;
op3val:0x7c01; valaddr_reg:x3; val_offset:11724*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 11724*FLEN/8, x4, x1, x2)

inst_3909:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x155 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3ff; op2val:0x7e01;
op3val:0xfd55; valaddr_reg:x3; val_offset:11727*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 11727*FLEN/8, x4, x1, x2)

inst_3910:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fs3 == 0 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3ff; op2val:0x7e01;
op3val:0x3c00; valaddr_reg:x3; val_offset:11730*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 11730*FLEN/8, x4, x1, x2)

inst_3911:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fs3 == 1 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3ff; op2val:0x7e01;
op3val:0xbc00; valaddr_reg:x3; val_offset:11733*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 11733*FLEN/8, x4, x1, x2)

inst_3912:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3ff; op2val:0xfe55;
op3val:0x0; valaddr_reg:x3; val_offset:11736*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 11736*FLEN/8, x4, x1, x2)

inst_3913:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3ff; op2val:0xfe55;
op3val:0x8000; valaddr_reg:x3; val_offset:11739*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 11739*FLEN/8, x4, x1, x2)

inst_3914:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3ff; op2val:0xfe55;
op3val:0x1; valaddr_reg:x3; val_offset:11742*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 11742*FLEN/8, x4, x1, x2)

inst_3915:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3ff; op2val:0xfe55;
op3val:0x8001; valaddr_reg:x3; val_offset:11745*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 11745*FLEN/8, x4, x1, x2)

inst_3916:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x002 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3ff; op2val:0xfe55;
op3val:0x2; valaddr_reg:x3; val_offset:11748*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 11748*FLEN/8, x4, x1, x2)

inst_3917:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3fe and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3ff; op2val:0xfe55;
op3val:0x83fe; valaddr_reg:x3; val_offset:11751*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 11751*FLEN/8, x4, x1, x2)

inst_3918:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3ff; op2val:0xfe55;
op3val:0x3ff; valaddr_reg:x3; val_offset:11754*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 11754*FLEN/8, x4, x1, x2)

inst_3919:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3ff; op2val:0xfe55;
op3val:0x83ff; valaddr_reg:x3; val_offset:11757*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 11757*FLEN/8, x4, x1, x2)

inst_3920:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3ff; op2val:0xfe55;
op3val:0x400; valaddr_reg:x3; val_offset:11760*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 11760*FLEN/8, x4, x1, x2)

inst_3921:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3ff; op2val:0xfe55;
op3val:0x8400; valaddr_reg:x3; val_offset:11763*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 11763*FLEN/8, x4, x1, x2)

inst_3922:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3ff; op2val:0xfe55;
op3val:0x401; valaddr_reg:x3; val_offset:11766*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 11766*FLEN/8, x4, x1, x2)

inst_3923:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3ff; op2val:0xfe55;
op3val:0x8455; valaddr_reg:x3; val_offset:11769*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 11769*FLEN/8, x4, x1, x2)

inst_3924:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3ff; op2val:0xfe55;
op3val:0x7bff; valaddr_reg:x3; val_offset:11772*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 11772*FLEN/8, x4, x1, x2)

inst_3925:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3ff; op2val:0xfe55;
op3val:0xfbff; valaddr_reg:x3; val_offset:11775*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 11775*FLEN/8, x4, x1, x2)

inst_3926:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3ff; op2val:0xfe55;
op3val:0x7c00; valaddr_reg:x3; val_offset:11778*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 11778*FLEN/8, x4, x1, x2)

inst_3927:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3ff; op2val:0xfe55;
op3val:0xfc00; valaddr_reg:x3; val_offset:11781*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 11781*FLEN/8, x4, x1, x2)

inst_3928:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3ff; op2val:0xfe55;
op3val:0x7e00; valaddr_reg:x3; val_offset:11784*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 11784*FLEN/8, x4, x1, x2)

inst_3929:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3ff; op2val:0xfe55;
op3val:0xfe00; valaddr_reg:x3; val_offset:11787*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 11787*FLEN/8, x4, x1, x2)

inst_3930:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x201 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3ff; op2val:0xfe55;
op3val:0x7e01; valaddr_reg:x3; val_offset:11790*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 11790*FLEN/8, x4, x1, x2)

inst_3931:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x255 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3ff; op2val:0xfe55;
op3val:0xfe55; valaddr_reg:x3; val_offset:11793*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 11793*FLEN/8, x4, x1, x2)

inst_3932:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3ff; op2val:0xfe55;
op3val:0x7c01; valaddr_reg:x3; val_offset:11796*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 11796*FLEN/8, x4, x1, x2)

inst_3933:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x155 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3ff; op2val:0xfe55;
op3val:0xfd55; valaddr_reg:x3; val_offset:11799*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 11799*FLEN/8, x4, x1, x2)

inst_3934:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fs3 == 0 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3ff; op2val:0xfe55;
op3val:0x3c00; valaddr_reg:x3; val_offset:11802*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 11802*FLEN/8, x4, x1, x2)

inst_3935:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fs3 == 1 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3ff; op2val:0xfe55;
op3val:0xbc00; valaddr_reg:x3; val_offset:11805*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 11805*FLEN/8, x4, x1, x2)

inst_3936:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3ff; op2val:0x7c01;
op3val:0x0; valaddr_reg:x3; val_offset:11808*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 11808*FLEN/8, x4, x1, x2)

inst_3937:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3ff; op2val:0x7c01;
op3val:0x8000; valaddr_reg:x3; val_offset:11811*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 11811*FLEN/8, x4, x1, x2)

inst_3938:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3ff; op2val:0x7c01;
op3val:0x1; valaddr_reg:x3; val_offset:11814*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 11814*FLEN/8, x4, x1, x2)

inst_3939:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3ff; op2val:0x7c01;
op3val:0x8001; valaddr_reg:x3; val_offset:11817*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 11817*FLEN/8, x4, x1, x2)

inst_3940:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x002 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3ff; op2val:0x7c01;
op3val:0x2; valaddr_reg:x3; val_offset:11820*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 11820*FLEN/8, x4, x1, x2)

inst_3941:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3fe and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3ff; op2val:0x7c01;
op3val:0x83fe; valaddr_reg:x3; val_offset:11823*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 11823*FLEN/8, x4, x1, x2)

inst_3942:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3ff; op2val:0x7c01;
op3val:0x3ff; valaddr_reg:x3; val_offset:11826*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 11826*FLEN/8, x4, x1, x2)

inst_3943:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3ff; op2val:0x7c01;
op3val:0x83ff; valaddr_reg:x3; val_offset:11829*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 11829*FLEN/8, x4, x1, x2)

inst_3944:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3ff; op2val:0x7c01;
op3val:0x400; valaddr_reg:x3; val_offset:11832*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 11832*FLEN/8, x4, x1, x2)

inst_3945:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3ff; op2val:0x7c01;
op3val:0x8400; valaddr_reg:x3; val_offset:11835*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 11835*FLEN/8, x4, x1, x2)

inst_3946:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3ff; op2val:0x7c01;
op3val:0x401; valaddr_reg:x3; val_offset:11838*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 11838*FLEN/8, x4, x1, x2)

inst_3947:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3ff; op2val:0x7c01;
op3val:0x8455; valaddr_reg:x3; val_offset:11841*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 11841*FLEN/8, x4, x1, x2)

inst_3948:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3ff; op2val:0x7c01;
op3val:0x7bff; valaddr_reg:x3; val_offset:11844*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 11844*FLEN/8, x4, x1, x2)

inst_3949:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3ff; op2val:0x7c01;
op3val:0xfbff; valaddr_reg:x3; val_offset:11847*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 11847*FLEN/8, x4, x1, x2)

inst_3950:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3ff; op2val:0x7c01;
op3val:0x7c00; valaddr_reg:x3; val_offset:11850*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 11850*FLEN/8, x4, x1, x2)

inst_3951:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3ff; op2val:0x7c01;
op3val:0xfc00; valaddr_reg:x3; val_offset:11853*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 11853*FLEN/8, x4, x1, x2)

inst_3952:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3ff; op2val:0x7c01;
op3val:0x7e00; valaddr_reg:x3; val_offset:11856*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 11856*FLEN/8, x4, x1, x2)

inst_3953:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3ff; op2val:0x7c01;
op3val:0xfe00; valaddr_reg:x3; val_offset:11859*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 11859*FLEN/8, x4, x1, x2)

inst_3954:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x201 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3ff; op2val:0x7c01;
op3val:0x7e01; valaddr_reg:x3; val_offset:11862*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 11862*FLEN/8, x4, x1, x2)

inst_3955:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x255 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3ff; op2val:0x7c01;
op3val:0xfe55; valaddr_reg:x3; val_offset:11865*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 11865*FLEN/8, x4, x1, x2)

inst_3956:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3ff; op2val:0x7c01;
op3val:0x7c01; valaddr_reg:x3; val_offset:11868*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 11868*FLEN/8, x4, x1, x2)

inst_3957:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x155 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3ff; op2val:0x7c01;
op3val:0xfd55; valaddr_reg:x3; val_offset:11871*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 11871*FLEN/8, x4, x1, x2)

inst_3958:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fs3 == 0 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3ff; op2val:0x7c01;
op3val:0x3c00; valaddr_reg:x3; val_offset:11874*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 11874*FLEN/8, x4, x1, x2)

inst_3959:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fs3 == 1 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3ff; op2val:0x7c01;
op3val:0xbc00; valaddr_reg:x3; val_offset:11877*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 11877*FLEN/8, x4, x1, x2)

inst_3960:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3ff; op2val:0xfd55;
op3val:0x0; valaddr_reg:x3; val_offset:11880*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 11880*FLEN/8, x4, x1, x2)

inst_3961:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3ff; op2val:0xfd55;
op3val:0x8000; valaddr_reg:x3; val_offset:11883*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 11883*FLEN/8, x4, x1, x2)

inst_3962:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3ff; op2val:0xfd55;
op3val:0x1; valaddr_reg:x3; val_offset:11886*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 11886*FLEN/8, x4, x1, x2)

inst_3963:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3ff; op2val:0xfd55;
op3val:0x8001; valaddr_reg:x3; val_offset:11889*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 11889*FLEN/8, x4, x1, x2)

inst_3964:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x002 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3ff; op2val:0xfd55;
op3val:0x2; valaddr_reg:x3; val_offset:11892*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 11892*FLEN/8, x4, x1, x2)

inst_3965:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3fe and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3ff; op2val:0xfd55;
op3val:0x83fe; valaddr_reg:x3; val_offset:11895*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 11895*FLEN/8, x4, x1, x2)

inst_3966:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3ff; op2val:0xfd55;
op3val:0x3ff; valaddr_reg:x3; val_offset:11898*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 11898*FLEN/8, x4, x1, x2)

inst_3967:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3ff; op2val:0xfd55;
op3val:0x83ff; valaddr_reg:x3; val_offset:11901*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 11901*FLEN/8, x4, x1, x2)

RVTEST_SIGBASE(x1,signature_x1_32)
inst_3968:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3ff; op2val:0xfd55;
op3val:0x400; valaddr_reg:x3; val_offset:11904*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 11904*FLEN/8, x4, x1, x2)

inst_3969:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3ff; op2val:0xfd55;
op3val:0x8400; valaddr_reg:x3; val_offset:11907*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 11907*FLEN/8, x4, x1, x2)

inst_3970:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3ff; op2val:0xfd55;
op3val:0x401; valaddr_reg:x3; val_offset:11910*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 11910*FLEN/8, x4, x1, x2)

inst_3971:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3ff; op2val:0xfd55;
op3val:0x8455; valaddr_reg:x3; val_offset:11913*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 11913*FLEN/8, x4, x1, x2)

inst_3972:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3ff; op2val:0xfd55;
op3val:0x7bff; valaddr_reg:x3; val_offset:11916*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 11916*FLEN/8, x4, x1, x2)

inst_3973:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3ff; op2val:0xfd55;
op3val:0xfbff; valaddr_reg:x3; val_offset:11919*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 11919*FLEN/8, x4, x1, x2)

inst_3974:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3ff; op2val:0xfd55;
op3val:0x7c00; valaddr_reg:x3; val_offset:11922*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 11922*FLEN/8, x4, x1, x2)

inst_3975:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3ff; op2val:0xfd55;
op3val:0xfc00; valaddr_reg:x3; val_offset:11925*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 11925*FLEN/8, x4, x1, x2)

inst_3976:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3ff; op2val:0xfd55;
op3val:0x7e00; valaddr_reg:x3; val_offset:11928*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 11928*FLEN/8, x4, x1, x2)

inst_3977:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3ff; op2val:0xfd55;
op3val:0xfe00; valaddr_reg:x3; val_offset:11931*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 11931*FLEN/8, x4, x1, x2)

inst_3978:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x201 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3ff; op2val:0xfd55;
op3val:0x7e01; valaddr_reg:x3; val_offset:11934*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 11934*FLEN/8, x4, x1, x2)

inst_3979:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x255 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3ff; op2val:0xfd55;
op3val:0xfe55; valaddr_reg:x3; val_offset:11937*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 11937*FLEN/8, x4, x1, x2)

inst_3980:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3ff; op2val:0xfd55;
op3val:0x7c01; valaddr_reg:x3; val_offset:11940*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 11940*FLEN/8, x4, x1, x2)

inst_3981:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x155 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3ff; op2val:0xfd55;
op3val:0xfd55; valaddr_reg:x3; val_offset:11943*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 11943*FLEN/8, x4, x1, x2)

inst_3982:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fs3 == 0 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3ff; op2val:0xfd55;
op3val:0x3c00; valaddr_reg:x3; val_offset:11946*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 11946*FLEN/8, x4, x1, x2)

inst_3983:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fs3 == 1 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3ff; op2val:0xfd55;
op3val:0xbc00; valaddr_reg:x3; val_offset:11949*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 11949*FLEN/8, x4, x1, x2)

inst_3984:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3ff; op2val:0x3c00;
op3val:0x0; valaddr_reg:x3; val_offset:11952*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 11952*FLEN/8, x4, x1, x2)

inst_3985:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3ff; op2val:0x3c00;
op3val:0x8000; valaddr_reg:x3; val_offset:11955*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 11955*FLEN/8, x4, x1, x2)

inst_3986:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3ff; op2val:0x3c00;
op3val:0x1; valaddr_reg:x3; val_offset:11958*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 11958*FLEN/8, x4, x1, x2)

inst_3987:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3ff; op2val:0x3c00;
op3val:0x8001; valaddr_reg:x3; val_offset:11961*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 11961*FLEN/8, x4, x1, x2)

inst_3988:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x002 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3ff; op2val:0x3c00;
op3val:0x2; valaddr_reg:x3; val_offset:11964*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 11964*FLEN/8, x4, x1, x2)

inst_3989:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3fe and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3ff; op2val:0x3c00;
op3val:0x83fe; valaddr_reg:x3; val_offset:11967*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 11967*FLEN/8, x4, x1, x2)

inst_3990:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3ff; op2val:0x3c00;
op3val:0x3ff; valaddr_reg:x3; val_offset:11970*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 11970*FLEN/8, x4, x1, x2)

inst_3991:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3ff; op2val:0x3c00;
op3val:0x83ff; valaddr_reg:x3; val_offset:11973*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 11973*FLEN/8, x4, x1, x2)

inst_3992:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3ff; op2val:0x3c00;
op3val:0x400; valaddr_reg:x3; val_offset:11976*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 11976*FLEN/8, x4, x1, x2)

inst_3993:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3ff; op2val:0x3c00;
op3val:0x8400; valaddr_reg:x3; val_offset:11979*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 11979*FLEN/8, x4, x1, x2)

inst_3994:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3ff; op2val:0x3c00;
op3val:0x401; valaddr_reg:x3; val_offset:11982*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 11982*FLEN/8, x4, x1, x2)

inst_3995:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3ff; op2val:0x3c00;
op3val:0x8455; valaddr_reg:x3; val_offset:11985*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 11985*FLEN/8, x4, x1, x2)

inst_3996:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3ff; op2val:0x3c00;
op3val:0x7bff; valaddr_reg:x3; val_offset:11988*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 11988*FLEN/8, x4, x1, x2)

inst_3997:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3ff; op2val:0x3c00;
op3val:0xfbff; valaddr_reg:x3; val_offset:11991*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 11991*FLEN/8, x4, x1, x2)

inst_3998:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3ff; op2val:0x3c00;
op3val:0x7c00; valaddr_reg:x3; val_offset:11994*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 11994*FLEN/8, x4, x1, x2)

inst_3999:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3ff; op2val:0x3c00;
op3val:0xfc00; valaddr_reg:x3; val_offset:11997*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 11997*FLEN/8, x4, x1, x2)

inst_4000:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3ff; op2val:0x3c00;
op3val:0x7e00; valaddr_reg:x3; val_offset:12000*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 12000*FLEN/8, x4, x1, x2)

inst_4001:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3ff; op2val:0x3c00;
op3val:0xfe00; valaddr_reg:x3; val_offset:12003*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 12003*FLEN/8, x4, x1, x2)

inst_4002:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x201 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3ff; op2val:0x3c00;
op3val:0x7e01; valaddr_reg:x3; val_offset:12006*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 12006*FLEN/8, x4, x1, x2)

inst_4003:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x255 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3ff; op2val:0x3c00;
op3val:0xfe55; valaddr_reg:x3; val_offset:12009*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 12009*FLEN/8, x4, x1, x2)

inst_4004:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3ff; op2val:0x3c00;
op3val:0x7c01; valaddr_reg:x3; val_offset:12012*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 12012*FLEN/8, x4, x1, x2)

inst_4005:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x155 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3ff; op2val:0x3c00;
op3val:0xfd55; valaddr_reg:x3; val_offset:12015*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 12015*FLEN/8, x4, x1, x2)

inst_4006:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3ff; op2val:0x3c00;
op3val:0x3c00; valaddr_reg:x3; val_offset:12018*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 12018*FLEN/8, x4, x1, x2)

inst_4007:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3ff; op2val:0x3c00;
op3val:0xbc00; valaddr_reg:x3; val_offset:12021*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 12021*FLEN/8, x4, x1, x2)

inst_4008:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3ff; op2val:0xbc00;
op3val:0x0; valaddr_reg:x3; val_offset:12024*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 12024*FLEN/8, x4, x1, x2)

inst_4009:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3ff; op2val:0xbc00;
op3val:0x8000; valaddr_reg:x3; val_offset:12027*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 12027*FLEN/8, x4, x1, x2)

inst_4010:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3ff; op2val:0xbc00;
op3val:0x1; valaddr_reg:x3; val_offset:12030*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 12030*FLEN/8, x4, x1, x2)

inst_4011:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3ff; op2val:0xbc00;
op3val:0x8001; valaddr_reg:x3; val_offset:12033*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 12033*FLEN/8, x4, x1, x2)

inst_4012:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x002 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3ff; op2val:0xbc00;
op3val:0x2; valaddr_reg:x3; val_offset:12036*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 12036*FLEN/8, x4, x1, x2)

inst_4013:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3fe and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3ff; op2val:0xbc00;
op3val:0x83fe; valaddr_reg:x3; val_offset:12039*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 12039*FLEN/8, x4, x1, x2)

inst_4014:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3ff; op2val:0xbc00;
op3val:0x3ff; valaddr_reg:x3; val_offset:12042*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 12042*FLEN/8, x4, x1, x2)

inst_4015:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3ff; op2val:0xbc00;
op3val:0x83ff; valaddr_reg:x3; val_offset:12045*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 12045*FLEN/8, x4, x1, x2)

inst_4016:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3ff; op2val:0xbc00;
op3val:0x400; valaddr_reg:x3; val_offset:12048*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 12048*FLEN/8, x4, x1, x2)

inst_4017:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3ff; op2val:0xbc00;
op3val:0x8400; valaddr_reg:x3; val_offset:12051*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 12051*FLEN/8, x4, x1, x2)

inst_4018:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3ff; op2val:0xbc00;
op3val:0x401; valaddr_reg:x3; val_offset:12054*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 12054*FLEN/8, x4, x1, x2)

inst_4019:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3ff; op2val:0xbc00;
op3val:0x8455; valaddr_reg:x3; val_offset:12057*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 12057*FLEN/8, x4, x1, x2)

inst_4020:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3ff; op2val:0xbc00;
op3val:0x7bff; valaddr_reg:x3; val_offset:12060*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 12060*FLEN/8, x4, x1, x2)

inst_4021:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3ff; op2val:0xbc00;
op3val:0xfbff; valaddr_reg:x3; val_offset:12063*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 12063*FLEN/8, x4, x1, x2)

inst_4022:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3ff; op2val:0xbc00;
op3val:0x7c00; valaddr_reg:x3; val_offset:12066*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 12066*FLEN/8, x4, x1, x2)

inst_4023:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3ff; op2val:0xbc00;
op3val:0xfc00; valaddr_reg:x3; val_offset:12069*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 12069*FLEN/8, x4, x1, x2)

inst_4024:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3ff; op2val:0xbc00;
op3val:0x7e00; valaddr_reg:x3; val_offset:12072*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 12072*FLEN/8, x4, x1, x2)

inst_4025:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3ff; op2val:0xbc00;
op3val:0xfe00; valaddr_reg:x3; val_offset:12075*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 12075*FLEN/8, x4, x1, x2)

inst_4026:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x201 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3ff; op2val:0xbc00;
op3val:0x7e01; valaddr_reg:x3; val_offset:12078*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 12078*FLEN/8, x4, x1, x2)

inst_4027:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x255 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3ff; op2val:0xbc00;
op3val:0xfe55; valaddr_reg:x3; val_offset:12081*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 12081*FLEN/8, x4, x1, x2)

inst_4028:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3ff; op2val:0xbc00;
op3val:0x7c01; valaddr_reg:x3; val_offset:12084*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 12084*FLEN/8, x4, x1, x2)

inst_4029:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x155 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3ff; op2val:0xbc00;
op3val:0xfd55; valaddr_reg:x3; val_offset:12087*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 12087*FLEN/8, x4, x1, x2)

inst_4030:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3ff; op2val:0xbc00;
op3val:0x3c00; valaddr_reg:x3; val_offset:12090*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 12090*FLEN/8, x4, x1, x2)

inst_4031:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3ff; op2val:0xbc00;
op3val:0xbc00; valaddr_reg:x3; val_offset:12093*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 12093*FLEN/8, x4, x1, x2)

inst_4032:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83ff; op2val:0x0;
op3val:0x0; valaddr_reg:x3; val_offset:12096*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 12096*FLEN/8, x4, x1, x2)

inst_4033:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83ff; op2val:0x0;
op3val:0x8000; valaddr_reg:x3; val_offset:12099*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 12099*FLEN/8, x4, x1, x2)

inst_4034:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83ff; op2val:0x0;
op3val:0x1; valaddr_reg:x3; val_offset:12102*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 12102*FLEN/8, x4, x1, x2)

inst_4035:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83ff; op2val:0x0;
op3val:0x8001; valaddr_reg:x3; val_offset:12105*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 12105*FLEN/8, x4, x1, x2)

inst_4036:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x002 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83ff; op2val:0x0;
op3val:0x2; valaddr_reg:x3; val_offset:12108*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 12108*FLEN/8, x4, x1, x2)

inst_4037:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3fe and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83ff; op2val:0x0;
op3val:0x83fe; valaddr_reg:x3; val_offset:12111*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 12111*FLEN/8, x4, x1, x2)

inst_4038:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83ff; op2val:0x0;
op3val:0x3ff; valaddr_reg:x3; val_offset:12114*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 12114*FLEN/8, x4, x1, x2)

inst_4039:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83ff; op2val:0x0;
op3val:0x83ff; valaddr_reg:x3; val_offset:12117*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 12117*FLEN/8, x4, x1, x2)

inst_4040:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83ff; op2val:0x0;
op3val:0x400; valaddr_reg:x3; val_offset:12120*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 12120*FLEN/8, x4, x1, x2)

inst_4041:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83ff; op2val:0x0;
op3val:0x8400; valaddr_reg:x3; val_offset:12123*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 12123*FLEN/8, x4, x1, x2)

inst_4042:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83ff; op2val:0x0;
op3val:0x401; valaddr_reg:x3; val_offset:12126*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 12126*FLEN/8, x4, x1, x2)

inst_4043:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83ff; op2val:0x0;
op3val:0x8455; valaddr_reg:x3; val_offset:12129*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 12129*FLEN/8, x4, x1, x2)

inst_4044:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83ff; op2val:0x0;
op3val:0x7bff; valaddr_reg:x3; val_offset:12132*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 12132*FLEN/8, x4, x1, x2)

inst_4045:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83ff; op2val:0x0;
op3val:0xfbff; valaddr_reg:x3; val_offset:12135*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 12135*FLEN/8, x4, x1, x2)

inst_4046:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83ff; op2val:0x0;
op3val:0x7c00; valaddr_reg:x3; val_offset:12138*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 12138*FLEN/8, x4, x1, x2)

inst_4047:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83ff; op2val:0x0;
op3val:0xfc00; valaddr_reg:x3; val_offset:12141*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 12141*FLEN/8, x4, x1, x2)

inst_4048:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83ff; op2val:0x0;
op3val:0x7e00; valaddr_reg:x3; val_offset:12144*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 12144*FLEN/8, x4, x1, x2)

inst_4049:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83ff; op2val:0x0;
op3val:0xfe00; valaddr_reg:x3; val_offset:12147*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 12147*FLEN/8, x4, x1, x2)

inst_4050:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x201 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83ff; op2val:0x0;
op3val:0x7e01; valaddr_reg:x3; val_offset:12150*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 12150*FLEN/8, x4, x1, x2)

inst_4051:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x255 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83ff; op2val:0x0;
op3val:0xfe55; valaddr_reg:x3; val_offset:12153*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 12153*FLEN/8, x4, x1, x2)

inst_4052:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83ff; op2val:0x0;
op3val:0x7c01; valaddr_reg:x3; val_offset:12156*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 12156*FLEN/8, x4, x1, x2)

inst_4053:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x155 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83ff; op2val:0x0;
op3val:0xfd55; valaddr_reg:x3; val_offset:12159*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 12159*FLEN/8, x4, x1, x2)

inst_4054:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83ff; op2val:0x0;
op3val:0x3c00; valaddr_reg:x3; val_offset:12162*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 12162*FLEN/8, x4, x1, x2)

inst_4055:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83ff; op2val:0x0;
op3val:0xbc00; valaddr_reg:x3; val_offset:12165*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 12165*FLEN/8, x4, x1, x2)

inst_4056:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83ff; op2val:0x8000;
op3val:0x0; valaddr_reg:x3; val_offset:12168*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 12168*FLEN/8, x4, x1, x2)

inst_4057:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83ff; op2val:0x8000;
op3val:0x8000; valaddr_reg:x3; val_offset:12171*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 12171*FLEN/8, x4, x1, x2)

inst_4058:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83ff; op2val:0x8000;
op3val:0x1; valaddr_reg:x3; val_offset:12174*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 12174*FLEN/8, x4, x1, x2)

inst_4059:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83ff; op2val:0x8000;
op3val:0x8001; valaddr_reg:x3; val_offset:12177*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 12177*FLEN/8, x4, x1, x2)

inst_4060:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x002 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83ff; op2val:0x8000;
op3val:0x2; valaddr_reg:x3; val_offset:12180*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 12180*FLEN/8, x4, x1, x2)

inst_4061:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3fe and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83ff; op2val:0x8000;
op3val:0x83fe; valaddr_reg:x3; val_offset:12183*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 12183*FLEN/8, x4, x1, x2)

inst_4062:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83ff; op2val:0x8000;
op3val:0x3ff; valaddr_reg:x3; val_offset:12186*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 12186*FLEN/8, x4, x1, x2)

inst_4063:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83ff; op2val:0x8000;
op3val:0x83ff; valaddr_reg:x3; val_offset:12189*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 12189*FLEN/8, x4, x1, x2)

inst_4064:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83ff; op2val:0x8000;
op3val:0x400; valaddr_reg:x3; val_offset:12192*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 12192*FLEN/8, x4, x1, x2)

inst_4065:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83ff; op2val:0x8000;
op3val:0x8400; valaddr_reg:x3; val_offset:12195*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 12195*FLEN/8, x4, x1, x2)

inst_4066:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83ff; op2val:0x8000;
op3val:0x401; valaddr_reg:x3; val_offset:12198*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 12198*FLEN/8, x4, x1, x2)

inst_4067:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83ff; op2val:0x8000;
op3val:0x8455; valaddr_reg:x3; val_offset:12201*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 12201*FLEN/8, x4, x1, x2)

inst_4068:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83ff; op2val:0x8000;
op3val:0x7bff; valaddr_reg:x3; val_offset:12204*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 12204*FLEN/8, x4, x1, x2)

inst_4069:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83ff; op2val:0x8000;
op3val:0xfbff; valaddr_reg:x3; val_offset:12207*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 12207*FLEN/8, x4, x1, x2)

inst_4070:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83ff; op2val:0x8000;
op3val:0x7c00; valaddr_reg:x3; val_offset:12210*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 12210*FLEN/8, x4, x1, x2)

inst_4071:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83ff; op2val:0x8000;
op3val:0xfc00; valaddr_reg:x3; val_offset:12213*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 12213*FLEN/8, x4, x1, x2)

inst_4072:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83ff; op2val:0x8000;
op3val:0x7e00; valaddr_reg:x3; val_offset:12216*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 12216*FLEN/8, x4, x1, x2)

inst_4073:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83ff; op2val:0x8000;
op3val:0xfe00; valaddr_reg:x3; val_offset:12219*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 12219*FLEN/8, x4, x1, x2)

inst_4074:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x201 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83ff; op2val:0x8000;
op3val:0x7e01; valaddr_reg:x3; val_offset:12222*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 12222*FLEN/8, x4, x1, x2)

inst_4075:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x255 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83ff; op2val:0x8000;
op3val:0xfe55; valaddr_reg:x3; val_offset:12225*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 12225*FLEN/8, x4, x1, x2)

inst_4076:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83ff; op2val:0x8000;
op3val:0x7c01; valaddr_reg:x3; val_offset:12228*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 12228*FLEN/8, x4, x1, x2)

inst_4077:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x155 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83ff; op2val:0x8000;
op3val:0xfd55; valaddr_reg:x3; val_offset:12231*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 12231*FLEN/8, x4, x1, x2)

inst_4078:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83ff; op2val:0x8000;
op3val:0x3c00; valaddr_reg:x3; val_offset:12234*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 12234*FLEN/8, x4, x1, x2)

inst_4079:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83ff; op2val:0x8000;
op3val:0xbc00; valaddr_reg:x3; val_offset:12237*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 12237*FLEN/8, x4, x1, x2)

inst_4080:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83ff; op2val:0x1;
op3val:0x0; valaddr_reg:x3; val_offset:12240*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 12240*FLEN/8, x4, x1, x2)

inst_4081:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83ff; op2val:0x1;
op3val:0x8000; valaddr_reg:x3; val_offset:12243*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 12243*FLEN/8, x4, x1, x2)

inst_4082:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83ff; op2val:0x1;
op3val:0x1; valaddr_reg:x3; val_offset:12246*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 12246*FLEN/8, x4, x1, x2)

inst_4083:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83ff; op2val:0x1;
op3val:0x8001; valaddr_reg:x3; val_offset:12249*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 12249*FLEN/8, x4, x1, x2)

inst_4084:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x002 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83ff; op2val:0x1;
op3val:0x2; valaddr_reg:x3; val_offset:12252*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 12252*FLEN/8, x4, x1, x2)

inst_4085:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3fe and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83ff; op2val:0x1;
op3val:0x83fe; valaddr_reg:x3; val_offset:12255*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 12255*FLEN/8, x4, x1, x2)

inst_4086:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83ff; op2val:0x1;
op3val:0x3ff; valaddr_reg:x3; val_offset:12258*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 12258*FLEN/8, x4, x1, x2)

inst_4087:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83ff; op2val:0x1;
op3val:0x83ff; valaddr_reg:x3; val_offset:12261*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 12261*FLEN/8, x4, x1, x2)

inst_4088:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83ff; op2val:0x1;
op3val:0x400; valaddr_reg:x3; val_offset:12264*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 12264*FLEN/8, x4, x1, x2)

inst_4089:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83ff; op2val:0x1;
op3val:0x8400; valaddr_reg:x3; val_offset:12267*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 12267*FLEN/8, x4, x1, x2)

inst_4090:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83ff; op2val:0x1;
op3val:0x401; valaddr_reg:x3; val_offset:12270*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 12270*FLEN/8, x4, x1, x2)

inst_4091:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83ff; op2val:0x1;
op3val:0x8455; valaddr_reg:x3; val_offset:12273*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 12273*FLEN/8, x4, x1, x2)

inst_4092:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83ff; op2val:0x1;
op3val:0x7bff; valaddr_reg:x3; val_offset:12276*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 12276*FLEN/8, x4, x1, x2)

inst_4093:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83ff; op2val:0x1;
op3val:0xfbff; valaddr_reg:x3; val_offset:12279*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 12279*FLEN/8, x4, x1, x2)

inst_4094:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83ff; op2val:0x1;
op3val:0x7c00; valaddr_reg:x3; val_offset:12282*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 12282*FLEN/8, x4, x1, x2)

inst_4095:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83ff; op2val:0x1;
op3val:0xfc00; valaddr_reg:x3; val_offset:12285*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 12285*FLEN/8, x4, x1, x2)

RVTEST_SIGBASE(x1,signature_x1_33)
inst_4096:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83ff; op2val:0x1;
op3val:0x7e00; valaddr_reg:x3; val_offset:12288*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 12288*FLEN/8, x4, x1, x2)

inst_4097:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83ff; op2val:0x1;
op3val:0xfe00; valaddr_reg:x3; val_offset:12291*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 12291*FLEN/8, x4, x1, x2)

inst_4098:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x201 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83ff; op2val:0x1;
op3val:0x7e01; valaddr_reg:x3; val_offset:12294*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 12294*FLEN/8, x4, x1, x2)

inst_4099:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x255 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83ff; op2val:0x1;
op3val:0xfe55; valaddr_reg:x3; val_offset:12297*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 12297*FLEN/8, x4, x1, x2)

inst_4100:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83ff; op2val:0x1;
op3val:0x7c01; valaddr_reg:x3; val_offset:12300*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 12300*FLEN/8, x4, x1, x2)

inst_4101:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x155 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83ff; op2val:0x1;
op3val:0xfd55; valaddr_reg:x3; val_offset:12303*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 12303*FLEN/8, x4, x1, x2)

inst_4102:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83ff; op2val:0x1;
op3val:0x3c00; valaddr_reg:x3; val_offset:12306*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 12306*FLEN/8, x4, x1, x2)

inst_4103:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83ff; op2val:0x1;
op3val:0xbc00; valaddr_reg:x3; val_offset:12309*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 12309*FLEN/8, x4, x1, x2)

inst_4104:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83ff; op2val:0x8001;
op3val:0x0; valaddr_reg:x3; val_offset:12312*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 12312*FLEN/8, x4, x1, x2)

inst_4105:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83ff; op2val:0x8001;
op3val:0x8000; valaddr_reg:x3; val_offset:12315*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 12315*FLEN/8, x4, x1, x2)

inst_4106:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83ff; op2val:0x8001;
op3val:0x1; valaddr_reg:x3; val_offset:12318*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 12318*FLEN/8, x4, x1, x2)

inst_4107:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83ff; op2val:0x8001;
op3val:0x8001; valaddr_reg:x3; val_offset:12321*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 12321*FLEN/8, x4, x1, x2)

inst_4108:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x002 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83ff; op2val:0x8001;
op3val:0x2; valaddr_reg:x3; val_offset:12324*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 12324*FLEN/8, x4, x1, x2)

inst_4109:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3fe and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83ff; op2val:0x8001;
op3val:0x83fe; valaddr_reg:x3; val_offset:12327*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 12327*FLEN/8, x4, x1, x2)

inst_4110:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83ff; op2val:0x8001;
op3val:0x3ff; valaddr_reg:x3; val_offset:12330*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 12330*FLEN/8, x4, x1, x2)

inst_4111:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83ff; op2val:0x8001;
op3val:0x83ff; valaddr_reg:x3; val_offset:12333*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 12333*FLEN/8, x4, x1, x2)

inst_4112:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83ff; op2val:0x8001;
op3val:0x400; valaddr_reg:x3; val_offset:12336*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 12336*FLEN/8, x4, x1, x2)

inst_4113:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83ff; op2val:0x8001;
op3val:0x8400; valaddr_reg:x3; val_offset:12339*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 12339*FLEN/8, x4, x1, x2)

inst_4114:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83ff; op2val:0x8001;
op3val:0x401; valaddr_reg:x3; val_offset:12342*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 12342*FLEN/8, x4, x1, x2)

inst_4115:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83ff; op2val:0x8001;
op3val:0x8455; valaddr_reg:x3; val_offset:12345*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 12345*FLEN/8, x4, x1, x2)

inst_4116:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83ff; op2val:0x8001;
op3val:0x7bff; valaddr_reg:x3; val_offset:12348*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 12348*FLEN/8, x4, x1, x2)

inst_4117:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83ff; op2val:0x8001;
op3val:0xfbff; valaddr_reg:x3; val_offset:12351*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 12351*FLEN/8, x4, x1, x2)

inst_4118:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83ff; op2val:0x8001;
op3val:0x7c00; valaddr_reg:x3; val_offset:12354*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 12354*FLEN/8, x4, x1, x2)

inst_4119:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83ff; op2val:0x8001;
op3val:0xfc00; valaddr_reg:x3; val_offset:12357*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 12357*FLEN/8, x4, x1, x2)

inst_4120:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83ff; op2val:0x8001;
op3val:0x7e00; valaddr_reg:x3; val_offset:12360*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 12360*FLEN/8, x4, x1, x2)

inst_4121:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83ff; op2val:0x8001;
op3val:0xfe00; valaddr_reg:x3; val_offset:12363*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 12363*FLEN/8, x4, x1, x2)

inst_4122:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x201 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83ff; op2val:0x8001;
op3val:0x7e01; valaddr_reg:x3; val_offset:12366*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 12366*FLEN/8, x4, x1, x2)

inst_4123:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x255 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83ff; op2val:0x8001;
op3val:0xfe55; valaddr_reg:x3; val_offset:12369*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 12369*FLEN/8, x4, x1, x2)

inst_4124:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83ff; op2val:0x8001;
op3val:0x7c01; valaddr_reg:x3; val_offset:12372*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 12372*FLEN/8, x4, x1, x2)

inst_4125:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x155 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83ff; op2val:0x8001;
op3val:0xfd55; valaddr_reg:x3; val_offset:12375*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 12375*FLEN/8, x4, x1, x2)

inst_4126:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83ff; op2val:0x8001;
op3val:0x3c00; valaddr_reg:x3; val_offset:12378*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 12378*FLEN/8, x4, x1, x2)

inst_4127:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83ff; op2val:0x8001;
op3val:0xbc00; valaddr_reg:x3; val_offset:12381*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 12381*FLEN/8, x4, x1, x2)

inst_4128:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83ff; op2val:0x2;
op3val:0x0; valaddr_reg:x3; val_offset:12384*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 12384*FLEN/8, x4, x1, x2)

inst_4129:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83ff; op2val:0x2;
op3val:0x8000; valaddr_reg:x3; val_offset:12387*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 12387*FLEN/8, x4, x1, x2)

inst_4130:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83ff; op2val:0x2;
op3val:0x1; valaddr_reg:x3; val_offset:12390*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 12390*FLEN/8, x4, x1, x2)

inst_4131:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83ff; op2val:0x2;
op3val:0x8001; valaddr_reg:x3; val_offset:12393*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 12393*FLEN/8, x4, x1, x2)

inst_4132:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x002 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83ff; op2val:0x2;
op3val:0x2; valaddr_reg:x3; val_offset:12396*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 12396*FLEN/8, x4, x1, x2)

inst_4133:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3fe and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83ff; op2val:0x2;
op3val:0x83fe; valaddr_reg:x3; val_offset:12399*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 12399*FLEN/8, x4, x1, x2)

inst_4134:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83ff; op2val:0x2;
op3val:0x3ff; valaddr_reg:x3; val_offset:12402*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 12402*FLEN/8, x4, x1, x2)

inst_4135:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83ff; op2val:0x2;
op3val:0x83ff; valaddr_reg:x3; val_offset:12405*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 12405*FLEN/8, x4, x1, x2)

inst_4136:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83ff; op2val:0x2;
op3val:0x400; valaddr_reg:x3; val_offset:12408*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 12408*FLEN/8, x4, x1, x2)

inst_4137:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83ff; op2val:0x2;
op3val:0x8400; valaddr_reg:x3; val_offset:12411*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 12411*FLEN/8, x4, x1, x2)

inst_4138:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83ff; op2val:0x2;
op3val:0x401; valaddr_reg:x3; val_offset:12414*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 12414*FLEN/8, x4, x1, x2)

inst_4139:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83ff; op2val:0x2;
op3val:0x8455; valaddr_reg:x3; val_offset:12417*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 12417*FLEN/8, x4, x1, x2)

inst_4140:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83ff; op2val:0x2;
op3val:0x7bff; valaddr_reg:x3; val_offset:12420*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 12420*FLEN/8, x4, x1, x2)

inst_4141:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83ff; op2val:0x2;
op3val:0xfbff; valaddr_reg:x3; val_offset:12423*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 12423*FLEN/8, x4, x1, x2)

inst_4142:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83ff; op2val:0x2;
op3val:0x7c00; valaddr_reg:x3; val_offset:12426*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 12426*FLEN/8, x4, x1, x2)

inst_4143:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83ff; op2val:0x2;
op3val:0xfc00; valaddr_reg:x3; val_offset:12429*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 12429*FLEN/8, x4, x1, x2)

inst_4144:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83ff; op2val:0x2;
op3val:0x7e00; valaddr_reg:x3; val_offset:12432*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 12432*FLEN/8, x4, x1, x2)

inst_4145:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83ff; op2val:0x2;
op3val:0xfe00; valaddr_reg:x3; val_offset:12435*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 12435*FLEN/8, x4, x1, x2)

inst_4146:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x201 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83ff; op2val:0x2;
op3val:0x7e01; valaddr_reg:x3; val_offset:12438*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 12438*FLEN/8, x4, x1, x2)

inst_4147:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x255 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83ff; op2val:0x2;
op3val:0xfe55; valaddr_reg:x3; val_offset:12441*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 12441*FLEN/8, x4, x1, x2)

inst_4148:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83ff; op2val:0x2;
op3val:0x7c01; valaddr_reg:x3; val_offset:12444*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 12444*FLEN/8, x4, x1, x2)

inst_4149:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x155 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83ff; op2val:0x2;
op3val:0xfd55; valaddr_reg:x3; val_offset:12447*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 12447*FLEN/8, x4, x1, x2)

inst_4150:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fs3 == 0 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83ff; op2val:0x2;
op3val:0x3c00; valaddr_reg:x3; val_offset:12450*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 12450*FLEN/8, x4, x1, x2)

inst_4151:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fs3 == 1 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83ff; op2val:0x2;
op3val:0xbc00; valaddr_reg:x3; val_offset:12453*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 12453*FLEN/8, x4, x1, x2)

inst_4152:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83ff; op2val:0x83fe;
op3val:0x0; valaddr_reg:x3; val_offset:12456*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 12456*FLEN/8, x4, x1, x2)

inst_4153:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83ff; op2val:0x83fe;
op3val:0x8000; valaddr_reg:x3; val_offset:12459*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 12459*FLEN/8, x4, x1, x2)

inst_4154:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fs3 == 0 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83ff; op2val:0x83fe;
op3val:0x1; valaddr_reg:x3; val_offset:12462*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 12462*FLEN/8, x4, x1, x2)

inst_4155:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fs3 == 1 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83ff; op2val:0x83fe;
op3val:0x8001; valaddr_reg:x3; val_offset:12465*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 12465*FLEN/8, x4, x1, x2)

inst_4156:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fs3 == 0 and fe3 == 0x00 and fm3 == 0x002 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83ff; op2val:0x83fe;
op3val:0x2; valaddr_reg:x3; val_offset:12468*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 12468*FLEN/8, x4, x1, x2)

inst_4157:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3fe and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83ff; op2val:0x83fe;
op3val:0x83fe; valaddr_reg:x3; val_offset:12471*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 12471*FLEN/8, x4, x1, x2)

inst_4158:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fs3 == 0 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83ff; op2val:0x83fe;
op3val:0x3ff; valaddr_reg:x3; val_offset:12474*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 12474*FLEN/8, x4, x1, x2)

inst_4159:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83ff; op2val:0x83fe;
op3val:0x83ff; valaddr_reg:x3; val_offset:12477*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 12477*FLEN/8, x4, x1, x2)

inst_4160:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83ff; op2val:0x83fe;
op3val:0x400; valaddr_reg:x3; val_offset:12480*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 12480*FLEN/8, x4, x1, x2)

inst_4161:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83ff; op2val:0x83fe;
op3val:0x8400; valaddr_reg:x3; val_offset:12483*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 12483*FLEN/8, x4, x1, x2)

inst_4162:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fs3 == 0 and fe3 == 0x01 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83ff; op2val:0x83fe;
op3val:0x401; valaddr_reg:x3; val_offset:12486*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 12486*FLEN/8, x4, x1, x2)

inst_4163:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83ff; op2val:0x83fe;
op3val:0x8455; valaddr_reg:x3; val_offset:12489*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 12489*FLEN/8, x4, x1, x2)

inst_4164:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83ff; op2val:0x83fe;
op3val:0x7bff; valaddr_reg:x3; val_offset:12492*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 12492*FLEN/8, x4, x1, x2)

inst_4165:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83ff; op2val:0x83fe;
op3val:0xfbff; valaddr_reg:x3; val_offset:12495*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 12495*FLEN/8, x4, x1, x2)

inst_4166:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fs3 == 0 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83ff; op2val:0x83fe;
op3val:0x7c00; valaddr_reg:x3; val_offset:12498*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 12498*FLEN/8, x4, x1, x2)

inst_4167:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fs3 == 1 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83ff; op2val:0x83fe;
op3val:0xfc00; valaddr_reg:x3; val_offset:12501*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 12501*FLEN/8, x4, x1, x2)

inst_4168:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fs3 == 0 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83ff; op2val:0x83fe;
op3val:0x7e00; valaddr_reg:x3; val_offset:12504*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 12504*FLEN/8, x4, x1, x2)

inst_4169:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fs3 == 1 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83ff; op2val:0x83fe;
op3val:0xfe00; valaddr_reg:x3; val_offset:12507*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 12507*FLEN/8, x4, x1, x2)

inst_4170:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fs3 == 0 and fe3 == 0x1f and fm3 == 0x201 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83ff; op2val:0x83fe;
op3val:0x7e01; valaddr_reg:x3; val_offset:12510*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 12510*FLEN/8, x4, x1, x2)

inst_4171:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fs3 == 1 and fe3 == 0x1f and fm3 == 0x255 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83ff; op2val:0x83fe;
op3val:0xfe55; valaddr_reg:x3; val_offset:12513*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 12513*FLEN/8, x4, x1, x2)

inst_4172:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fs3 == 0 and fe3 == 0x1f and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83ff; op2val:0x83fe;
op3val:0x7c01; valaddr_reg:x3; val_offset:12516*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 12516*FLEN/8, x4, x1, x2)

inst_4173:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fs3 == 1 and fe3 == 0x1f and fm3 == 0x155 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83ff; op2val:0x83fe;
op3val:0xfd55; valaddr_reg:x3; val_offset:12519*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 12519*FLEN/8, x4, x1, x2)

inst_4174:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fs3 == 0 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83ff; op2val:0x83fe;
op3val:0x3c00; valaddr_reg:x3; val_offset:12522*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 12522*FLEN/8, x4, x1, x2)

inst_4175:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fs3 == 1 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83ff; op2val:0x83fe;
op3val:0xbc00; valaddr_reg:x3; val_offset:12525*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 12525*FLEN/8, x4, x1, x2)

inst_4176:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83ff; op2val:0x3ff;
op3val:0x0; valaddr_reg:x3; val_offset:12528*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 12528*FLEN/8, x4, x1, x2)

inst_4177:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83ff; op2val:0x3ff;
op3val:0x8000; valaddr_reg:x3; val_offset:12531*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 12531*FLEN/8, x4, x1, x2)

inst_4178:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83ff; op2val:0x3ff;
op3val:0x1; valaddr_reg:x3; val_offset:12534*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 12534*FLEN/8, x4, x1, x2)

inst_4179:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83ff; op2val:0x3ff;
op3val:0x8001; valaddr_reg:x3; val_offset:12537*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 12537*FLEN/8, x4, x1, x2)

inst_4180:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x002 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83ff; op2val:0x3ff;
op3val:0x2; valaddr_reg:x3; val_offset:12540*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 12540*FLEN/8, x4, x1, x2)

inst_4181:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3fe and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83ff; op2val:0x3ff;
op3val:0x83fe; valaddr_reg:x3; val_offset:12543*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 12543*FLEN/8, x4, x1, x2)

inst_4182:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83ff; op2val:0x3ff;
op3val:0x3ff; valaddr_reg:x3; val_offset:12546*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 12546*FLEN/8, x4, x1, x2)

inst_4183:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83ff; op2val:0x3ff;
op3val:0x83ff; valaddr_reg:x3; val_offset:12549*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 12549*FLEN/8, x4, x1, x2)

inst_4184:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83ff; op2val:0x3ff;
op3val:0x400; valaddr_reg:x3; val_offset:12552*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 12552*FLEN/8, x4, x1, x2)

inst_4185:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83ff; op2val:0x3ff;
op3val:0x8400; valaddr_reg:x3; val_offset:12555*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 12555*FLEN/8, x4, x1, x2)

inst_4186:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x01 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83ff; op2val:0x3ff;
op3val:0x401; valaddr_reg:x3; val_offset:12558*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 12558*FLEN/8, x4, x1, x2)

inst_4187:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83ff; op2val:0x3ff;
op3val:0x8455; valaddr_reg:x3; val_offset:12561*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 12561*FLEN/8, x4, x1, x2)

inst_4188:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83ff; op2val:0x3ff;
op3val:0x7bff; valaddr_reg:x3; val_offset:12564*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 12564*FLEN/8, x4, x1, x2)

inst_4189:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83ff; op2val:0x3ff;
op3val:0xfbff; valaddr_reg:x3; val_offset:12567*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 12567*FLEN/8, x4, x1, x2)

inst_4190:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83ff; op2val:0x3ff;
op3val:0x7c00; valaddr_reg:x3; val_offset:12570*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 12570*FLEN/8, x4, x1, x2)

inst_4191:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83ff; op2val:0x3ff;
op3val:0xfc00; valaddr_reg:x3; val_offset:12573*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 12573*FLEN/8, x4, x1, x2)

inst_4192:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83ff; op2val:0x3ff;
op3val:0x7e00; valaddr_reg:x3; val_offset:12576*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 12576*FLEN/8, x4, x1, x2)

inst_4193:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83ff; op2val:0x3ff;
op3val:0xfe00; valaddr_reg:x3; val_offset:12579*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 12579*FLEN/8, x4, x1, x2)

inst_4194:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x1f and fm3 == 0x201 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83ff; op2val:0x3ff;
op3val:0x7e01; valaddr_reg:x3; val_offset:12582*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 12582*FLEN/8, x4, x1, x2)

inst_4195:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x1f and fm3 == 0x255 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83ff; op2val:0x3ff;
op3val:0xfe55; valaddr_reg:x3; val_offset:12585*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 12585*FLEN/8, x4, x1, x2)

inst_4196:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x1f and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83ff; op2val:0x3ff;
op3val:0x7c01; valaddr_reg:x3; val_offset:12588*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 12588*FLEN/8, x4, x1, x2)

inst_4197:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x1f and fm3 == 0x155 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83ff; op2val:0x3ff;
op3val:0xfd55; valaddr_reg:x3; val_offset:12591*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 12591*FLEN/8, x4, x1, x2)

inst_4198:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83ff; op2val:0x3ff;
op3val:0x3c00; valaddr_reg:x3; val_offset:12594*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 12594*FLEN/8, x4, x1, x2)

inst_4199:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83ff; op2val:0x3ff;
op3val:0xbc00; valaddr_reg:x3; val_offset:12597*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 12597*FLEN/8, x4, x1, x2)

inst_4200:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83ff; op2val:0x83ff;
op3val:0x0; valaddr_reg:x3; val_offset:12600*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 12600*FLEN/8, x4, x1, x2)

inst_4201:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83ff; op2val:0x83ff;
op3val:0x8000; valaddr_reg:x3; val_offset:12603*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 12603*FLEN/8, x4, x1, x2)

inst_4202:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83ff; op2val:0x83ff;
op3val:0x1; valaddr_reg:x3; val_offset:12606*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 12606*FLEN/8, x4, x1, x2)

inst_4203:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83ff; op2val:0x83ff;
op3val:0x8001; valaddr_reg:x3; val_offset:12609*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 12609*FLEN/8, x4, x1, x2)

inst_4204:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x002 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83ff; op2val:0x83ff;
op3val:0x2; valaddr_reg:x3; val_offset:12612*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 12612*FLEN/8, x4, x1, x2)

inst_4205:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3fe and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83ff; op2val:0x83ff;
op3val:0x83fe; valaddr_reg:x3; val_offset:12615*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 12615*FLEN/8, x4, x1, x2)

inst_4206:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83ff; op2val:0x83ff;
op3val:0x3ff; valaddr_reg:x3; val_offset:12618*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 12618*FLEN/8, x4, x1, x2)

inst_4207:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83ff; op2val:0x83ff;
op3val:0x83ff; valaddr_reg:x3; val_offset:12621*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 12621*FLEN/8, x4, x1, x2)

inst_4208:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83ff; op2val:0x83ff;
op3val:0x400; valaddr_reg:x3; val_offset:12624*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 12624*FLEN/8, x4, x1, x2)

inst_4209:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83ff; op2val:0x83ff;
op3val:0x8400; valaddr_reg:x3; val_offset:12627*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 12627*FLEN/8, x4, x1, x2)

inst_4210:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x01 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83ff; op2val:0x83ff;
op3val:0x401; valaddr_reg:x3; val_offset:12630*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 12630*FLEN/8, x4, x1, x2)

inst_4211:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83ff; op2val:0x83ff;
op3val:0x8455; valaddr_reg:x3; val_offset:12633*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 12633*FLEN/8, x4, x1, x2)

inst_4212:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83ff; op2val:0x83ff;
op3val:0x7bff; valaddr_reg:x3; val_offset:12636*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 12636*FLEN/8, x4, x1, x2)

inst_4213:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83ff; op2val:0x83ff;
op3val:0xfbff; valaddr_reg:x3; val_offset:12639*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 12639*FLEN/8, x4, x1, x2)

inst_4214:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83ff; op2val:0x83ff;
op3val:0x7c00; valaddr_reg:x3; val_offset:12642*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 12642*FLEN/8, x4, x1, x2)

inst_4215:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83ff; op2val:0x83ff;
op3val:0xfc00; valaddr_reg:x3; val_offset:12645*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 12645*FLEN/8, x4, x1, x2)

inst_4216:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83ff; op2val:0x83ff;
op3val:0x7e00; valaddr_reg:x3; val_offset:12648*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 12648*FLEN/8, x4, x1, x2)

inst_4217:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83ff; op2val:0x83ff;
op3val:0xfe00; valaddr_reg:x3; val_offset:12651*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 12651*FLEN/8, x4, x1, x2)

inst_4218:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x1f and fm3 == 0x201 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83ff; op2val:0x83ff;
op3val:0x7e01; valaddr_reg:x3; val_offset:12654*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 12654*FLEN/8, x4, x1, x2)

inst_4219:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x1f and fm3 == 0x255 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83ff; op2val:0x83ff;
op3val:0xfe55; valaddr_reg:x3; val_offset:12657*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 12657*FLEN/8, x4, x1, x2)

inst_4220:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x1f and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83ff; op2val:0x83ff;
op3val:0x7c01; valaddr_reg:x3; val_offset:12660*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 12660*FLEN/8, x4, x1, x2)

inst_4221:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x1f and fm3 == 0x155 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83ff; op2val:0x83ff;
op3val:0xfd55; valaddr_reg:x3; val_offset:12663*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 12663*FLEN/8, x4, x1, x2)

inst_4222:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83ff; op2val:0x83ff;
op3val:0x3c00; valaddr_reg:x3; val_offset:12666*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 12666*FLEN/8, x4, x1, x2)

inst_4223:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83ff; op2val:0x83ff;
op3val:0xbc00; valaddr_reg:x3; val_offset:12669*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 12669*FLEN/8, x4, x1, x2)

RVTEST_SIGBASE(x1,signature_x1_34)
inst_4224:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83ff; op2val:0x400;
op3val:0x0; valaddr_reg:x3; val_offset:12672*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 12672*FLEN/8, x4, x1, x2)

inst_4225:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83ff; op2val:0x400;
op3val:0x8000; valaddr_reg:x3; val_offset:12675*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 12675*FLEN/8, x4, x1, x2)

inst_4226:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83ff; op2val:0x400;
op3val:0x1; valaddr_reg:x3; val_offset:12678*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 12678*FLEN/8, x4, x1, x2)

inst_4227:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83ff; op2val:0x400;
op3val:0x8001; valaddr_reg:x3; val_offset:12681*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 12681*FLEN/8, x4, x1, x2)

inst_4228:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x002 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83ff; op2val:0x400;
op3val:0x2; valaddr_reg:x3; val_offset:12684*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 12684*FLEN/8, x4, x1, x2)

inst_4229:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3fe and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83ff; op2val:0x400;
op3val:0x83fe; valaddr_reg:x3; val_offset:12687*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 12687*FLEN/8, x4, x1, x2)

inst_4230:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83ff; op2val:0x400;
op3val:0x3ff; valaddr_reg:x3; val_offset:12690*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 12690*FLEN/8, x4, x1, x2)

inst_4231:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83ff; op2val:0x400;
op3val:0x83ff; valaddr_reg:x3; val_offset:12693*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 12693*FLEN/8, x4, x1, x2)

inst_4232:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83ff; op2val:0x400;
op3val:0x400; valaddr_reg:x3; val_offset:12696*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 12696*FLEN/8, x4, x1, x2)

inst_4233:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83ff; op2val:0x400;
op3val:0x8400; valaddr_reg:x3; val_offset:12699*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 12699*FLEN/8, x4, x1, x2)

inst_4234:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83ff; op2val:0x400;
op3val:0x401; valaddr_reg:x3; val_offset:12702*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 12702*FLEN/8, x4, x1, x2)

inst_4235:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83ff; op2val:0x400;
op3val:0x8455; valaddr_reg:x3; val_offset:12705*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 12705*FLEN/8, x4, x1, x2)

inst_4236:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83ff; op2val:0x400;
op3val:0x7bff; valaddr_reg:x3; val_offset:12708*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 12708*FLEN/8, x4, x1, x2)

inst_4237:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83ff; op2val:0x400;
op3val:0xfbff; valaddr_reg:x3; val_offset:12711*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 12711*FLEN/8, x4, x1, x2)

inst_4238:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83ff; op2val:0x400;
op3val:0x7c00; valaddr_reg:x3; val_offset:12714*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 12714*FLEN/8, x4, x1, x2)

inst_4239:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83ff; op2val:0x400;
op3val:0xfc00; valaddr_reg:x3; val_offset:12717*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 12717*FLEN/8, x4, x1, x2)

inst_4240:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83ff; op2val:0x400;
op3val:0x7e00; valaddr_reg:x3; val_offset:12720*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 12720*FLEN/8, x4, x1, x2)

inst_4241:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83ff; op2val:0x400;
op3val:0xfe00; valaddr_reg:x3; val_offset:12723*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 12723*FLEN/8, x4, x1, x2)

inst_4242:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x201 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83ff; op2val:0x400;
op3val:0x7e01; valaddr_reg:x3; val_offset:12726*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 12726*FLEN/8, x4, x1, x2)

inst_4243:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x255 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83ff; op2val:0x400;
op3val:0xfe55; valaddr_reg:x3; val_offset:12729*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 12729*FLEN/8, x4, x1, x2)

inst_4244:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83ff; op2val:0x400;
op3val:0x7c01; valaddr_reg:x3; val_offset:12732*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 12732*FLEN/8, x4, x1, x2)

inst_4245:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x155 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83ff; op2val:0x400;
op3val:0xfd55; valaddr_reg:x3; val_offset:12735*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 12735*FLEN/8, x4, x1, x2)

inst_4246:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83ff; op2val:0x400;
op3val:0x3c00; valaddr_reg:x3; val_offset:12738*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 12738*FLEN/8, x4, x1, x2)

inst_4247:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83ff; op2val:0x400;
op3val:0xbc00; valaddr_reg:x3; val_offset:12741*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 12741*FLEN/8, x4, x1, x2)

inst_4248:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83ff; op2val:0x8400;
op3val:0x0; valaddr_reg:x3; val_offset:12744*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 12744*FLEN/8, x4, x1, x2)

inst_4249:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83ff; op2val:0x8400;
op3val:0x8000; valaddr_reg:x3; val_offset:12747*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 12747*FLEN/8, x4, x1, x2)

inst_4250:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83ff; op2val:0x8400;
op3val:0x1; valaddr_reg:x3; val_offset:12750*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 12750*FLEN/8, x4, x1, x2)

inst_4251:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83ff; op2val:0x8400;
op3val:0x8001; valaddr_reg:x3; val_offset:12753*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 12753*FLEN/8, x4, x1, x2)

inst_4252:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x002 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83ff; op2val:0x8400;
op3val:0x2; valaddr_reg:x3; val_offset:12756*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 12756*FLEN/8, x4, x1, x2)

inst_4253:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3fe and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83ff; op2val:0x8400;
op3val:0x83fe; valaddr_reg:x3; val_offset:12759*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 12759*FLEN/8, x4, x1, x2)

inst_4254:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83ff; op2val:0x8400;
op3val:0x3ff; valaddr_reg:x3; val_offset:12762*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 12762*FLEN/8, x4, x1, x2)

inst_4255:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83ff; op2val:0x8400;
op3val:0x83ff; valaddr_reg:x3; val_offset:12765*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 12765*FLEN/8, x4, x1, x2)

inst_4256:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83ff; op2val:0x8400;
op3val:0x400; valaddr_reg:x3; val_offset:12768*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 12768*FLEN/8, x4, x1, x2)

inst_4257:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83ff; op2val:0x8400;
op3val:0x8400; valaddr_reg:x3; val_offset:12771*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 12771*FLEN/8, x4, x1, x2)

inst_4258:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83ff; op2val:0x8400;
op3val:0x401; valaddr_reg:x3; val_offset:12774*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 12774*FLEN/8, x4, x1, x2)

inst_4259:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83ff; op2val:0x8400;
op3val:0x8455; valaddr_reg:x3; val_offset:12777*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 12777*FLEN/8, x4, x1, x2)

inst_4260:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83ff; op2val:0x8400;
op3val:0x7bff; valaddr_reg:x3; val_offset:12780*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 12780*FLEN/8, x4, x1, x2)

inst_4261:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83ff; op2val:0x8400;
op3val:0xfbff; valaddr_reg:x3; val_offset:12783*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 12783*FLEN/8, x4, x1, x2)

inst_4262:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83ff; op2val:0x8400;
op3val:0x7c00; valaddr_reg:x3; val_offset:12786*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 12786*FLEN/8, x4, x1, x2)

inst_4263:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83ff; op2val:0x8400;
op3val:0xfc00; valaddr_reg:x3; val_offset:12789*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 12789*FLEN/8, x4, x1, x2)

inst_4264:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83ff; op2val:0x8400;
op3val:0x7e00; valaddr_reg:x3; val_offset:12792*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 12792*FLEN/8, x4, x1, x2)

inst_4265:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83ff; op2val:0x8400;
op3val:0xfe00; valaddr_reg:x3; val_offset:12795*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 12795*FLEN/8, x4, x1, x2)

inst_4266:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x201 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83ff; op2val:0x8400;
op3val:0x7e01; valaddr_reg:x3; val_offset:12798*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 12798*FLEN/8, x4, x1, x2)

inst_4267:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x255 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83ff; op2val:0x8400;
op3val:0xfe55; valaddr_reg:x3; val_offset:12801*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 12801*FLEN/8, x4, x1, x2)

inst_4268:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83ff; op2val:0x8400;
op3val:0x7c01; valaddr_reg:x3; val_offset:12804*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 12804*FLEN/8, x4, x1, x2)

inst_4269:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x155 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83ff; op2val:0x8400;
op3val:0xfd55; valaddr_reg:x3; val_offset:12807*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 12807*FLEN/8, x4, x1, x2)

inst_4270:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83ff; op2val:0x8400;
op3val:0x3c00; valaddr_reg:x3; val_offset:12810*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 12810*FLEN/8, x4, x1, x2)

inst_4271:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83ff; op2val:0x8400;
op3val:0xbc00; valaddr_reg:x3; val_offset:12813*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 12813*FLEN/8, x4, x1, x2)

inst_4272:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83ff; op2val:0x401;
op3val:0x0; valaddr_reg:x3; val_offset:12816*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 12816*FLEN/8, x4, x1, x2)

inst_4273:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83ff; op2val:0x401;
op3val:0x8000; valaddr_reg:x3; val_offset:12819*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 12819*FLEN/8, x4, x1, x2)

inst_4274:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83ff; op2val:0x401;
op3val:0x1; valaddr_reg:x3; val_offset:12822*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 12822*FLEN/8, x4, x1, x2)

inst_4275:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83ff; op2val:0x401;
op3val:0x8001; valaddr_reg:x3; val_offset:12825*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 12825*FLEN/8, x4, x1, x2)

inst_4276:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x002 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83ff; op2val:0x401;
op3val:0x2; valaddr_reg:x3; val_offset:12828*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 12828*FLEN/8, x4, x1, x2)

inst_4277:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3fe and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83ff; op2val:0x401;
op3val:0x83fe; valaddr_reg:x3; val_offset:12831*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 12831*FLEN/8, x4, x1, x2)

inst_4278:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83ff; op2val:0x401;
op3val:0x3ff; valaddr_reg:x3; val_offset:12834*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 12834*FLEN/8, x4, x1, x2)

inst_4279:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83ff; op2val:0x401;
op3val:0x83ff; valaddr_reg:x3; val_offset:12837*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 12837*FLEN/8, x4, x1, x2)

inst_4280:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83ff; op2val:0x401;
op3val:0x400; valaddr_reg:x3; val_offset:12840*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 12840*FLEN/8, x4, x1, x2)

inst_4281:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83ff; op2val:0x401;
op3val:0x8400; valaddr_reg:x3; val_offset:12843*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 12843*FLEN/8, x4, x1, x2)

inst_4282:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83ff; op2val:0x401;
op3val:0x401; valaddr_reg:x3; val_offset:12846*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 12846*FLEN/8, x4, x1, x2)

inst_4283:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83ff; op2val:0x401;
op3val:0x8455; valaddr_reg:x3; val_offset:12849*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 12849*FLEN/8, x4, x1, x2)

inst_4284:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83ff; op2val:0x401;
op3val:0x7bff; valaddr_reg:x3; val_offset:12852*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 12852*FLEN/8, x4, x1, x2)

inst_4285:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83ff; op2val:0x401;
op3val:0xfbff; valaddr_reg:x3; val_offset:12855*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 12855*FLEN/8, x4, x1, x2)

inst_4286:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83ff; op2val:0x401;
op3val:0x7c00; valaddr_reg:x3; val_offset:12858*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 12858*FLEN/8, x4, x1, x2)

inst_4287:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83ff; op2val:0x401;
op3val:0xfc00; valaddr_reg:x3; val_offset:12861*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 12861*FLEN/8, x4, x1, x2)

inst_4288:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83ff; op2val:0x401;
op3val:0x7e00; valaddr_reg:x3; val_offset:12864*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 12864*FLEN/8, x4, x1, x2)

inst_4289:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83ff; op2val:0x401;
op3val:0xfe00; valaddr_reg:x3; val_offset:12867*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 12867*FLEN/8, x4, x1, x2)

inst_4290:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x201 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83ff; op2val:0x401;
op3val:0x7e01; valaddr_reg:x3; val_offset:12870*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 12870*FLEN/8, x4, x1, x2)

inst_4291:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x255 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83ff; op2val:0x401;
op3val:0xfe55; valaddr_reg:x3; val_offset:12873*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 12873*FLEN/8, x4, x1, x2)

inst_4292:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83ff; op2val:0x401;
op3val:0x7c01; valaddr_reg:x3; val_offset:12876*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 12876*FLEN/8, x4, x1, x2)

inst_4293:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x155 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83ff; op2val:0x401;
op3val:0xfd55; valaddr_reg:x3; val_offset:12879*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 12879*FLEN/8, x4, x1, x2)

inst_4294:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83ff; op2val:0x401;
op3val:0x3c00; valaddr_reg:x3; val_offset:12882*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 12882*FLEN/8, x4, x1, x2)

inst_4295:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83ff; op2val:0x401;
op3val:0xbc00; valaddr_reg:x3; val_offset:12885*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 12885*FLEN/8, x4, x1, x2)

inst_4296:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83ff; op2val:0x8455;
op3val:0x0; valaddr_reg:x3; val_offset:12888*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 12888*FLEN/8, x4, x1, x2)

inst_4297:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83ff; op2val:0x8455;
op3val:0x8000; valaddr_reg:x3; val_offset:12891*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 12891*FLEN/8, x4, x1, x2)

inst_4298:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83ff; op2val:0x8455;
op3val:0x1; valaddr_reg:x3; val_offset:12894*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 12894*FLEN/8, x4, x1, x2)

inst_4299:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83ff; op2val:0x8455;
op3val:0x8001; valaddr_reg:x3; val_offset:12897*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 12897*FLEN/8, x4, x1, x2)

inst_4300:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x002 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83ff; op2val:0x8455;
op3val:0x2; valaddr_reg:x3; val_offset:12900*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 12900*FLEN/8, x4, x1, x2)

inst_4301:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3fe and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83ff; op2val:0x8455;
op3val:0x83fe; valaddr_reg:x3; val_offset:12903*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 12903*FLEN/8, x4, x1, x2)

inst_4302:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83ff; op2val:0x8455;
op3val:0x3ff; valaddr_reg:x3; val_offset:12906*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 12906*FLEN/8, x4, x1, x2)

inst_4303:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83ff; op2val:0x8455;
op3val:0x83ff; valaddr_reg:x3; val_offset:12909*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 12909*FLEN/8, x4, x1, x2)

inst_4304:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83ff; op2val:0x8455;
op3val:0x400; valaddr_reg:x3; val_offset:12912*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 12912*FLEN/8, x4, x1, x2)

inst_4305:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83ff; op2val:0x8455;
op3val:0x8400; valaddr_reg:x3; val_offset:12915*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 12915*FLEN/8, x4, x1, x2)

inst_4306:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83ff; op2val:0x8455;
op3val:0x401; valaddr_reg:x3; val_offset:12918*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 12918*FLEN/8, x4, x1, x2)

inst_4307:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83ff; op2val:0x8455;
op3val:0x8455; valaddr_reg:x3; val_offset:12921*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 12921*FLEN/8, x4, x1, x2)

inst_4308:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83ff; op2val:0x8455;
op3val:0x7bff; valaddr_reg:x3; val_offset:12924*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 12924*FLEN/8, x4, x1, x2)

inst_4309:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83ff; op2val:0x8455;
op3val:0xfbff; valaddr_reg:x3; val_offset:12927*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 12927*FLEN/8, x4, x1, x2)

inst_4310:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83ff; op2val:0x8455;
op3val:0x7c00; valaddr_reg:x3; val_offset:12930*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 12930*FLEN/8, x4, x1, x2)

inst_4311:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83ff; op2val:0x8455;
op3val:0xfc00; valaddr_reg:x3; val_offset:12933*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 12933*FLEN/8, x4, x1, x2)

inst_4312:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83ff; op2val:0x8455;
op3val:0x7e00; valaddr_reg:x3; val_offset:12936*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 12936*FLEN/8, x4, x1, x2)

inst_4313:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83ff; op2val:0x8455;
op3val:0xfe00; valaddr_reg:x3; val_offset:12939*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 12939*FLEN/8, x4, x1, x2)

inst_4314:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x201 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83ff; op2val:0x8455;
op3val:0x7e01; valaddr_reg:x3; val_offset:12942*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 12942*FLEN/8, x4, x1, x2)

inst_4315:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x255 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83ff; op2val:0x8455;
op3val:0xfe55; valaddr_reg:x3; val_offset:12945*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 12945*FLEN/8, x4, x1, x2)

inst_4316:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83ff; op2val:0x8455;
op3val:0x7c01; valaddr_reg:x3; val_offset:12948*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 12948*FLEN/8, x4, x1, x2)

inst_4317:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x155 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83ff; op2val:0x8455;
op3val:0xfd55; valaddr_reg:x3; val_offset:12951*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 12951*FLEN/8, x4, x1, x2)

inst_4318:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fs3 == 0 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83ff; op2val:0x8455;
op3val:0x3c00; valaddr_reg:x3; val_offset:12954*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 12954*FLEN/8, x4, x1, x2)

inst_4319:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fs3 == 1 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83ff; op2val:0x8455;
op3val:0xbc00; valaddr_reg:x3; val_offset:12957*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 12957*FLEN/8, x4, x1, x2)

inst_4320:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83ff; op2val:0x7bff;
op3val:0x0; valaddr_reg:x3; val_offset:12960*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 12960*FLEN/8, x4, x1, x2)

inst_4321:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83ff; op2val:0x7bff;
op3val:0x8000; valaddr_reg:x3; val_offset:12963*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 12963*FLEN/8, x4, x1, x2)

inst_4322:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83ff; op2val:0x7bff;
op3val:0x1; valaddr_reg:x3; val_offset:12966*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 12966*FLEN/8, x4, x1, x2)

inst_4323:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83ff; op2val:0x7bff;
op3val:0x8001; valaddr_reg:x3; val_offset:12969*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 12969*FLEN/8, x4, x1, x2)

inst_4324:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x002 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83ff; op2val:0x7bff;
op3val:0x2; valaddr_reg:x3; val_offset:12972*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 12972*FLEN/8, x4, x1, x2)

inst_4325:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3fe and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83ff; op2val:0x7bff;
op3val:0x83fe; valaddr_reg:x3; val_offset:12975*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 12975*FLEN/8, x4, x1, x2)

inst_4326:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83ff; op2val:0x7bff;
op3val:0x3ff; valaddr_reg:x3; val_offset:12978*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 12978*FLEN/8, x4, x1, x2)

inst_4327:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83ff; op2val:0x7bff;
op3val:0x83ff; valaddr_reg:x3; val_offset:12981*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 12981*FLEN/8, x4, x1, x2)

inst_4328:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83ff; op2val:0x7bff;
op3val:0x400; valaddr_reg:x3; val_offset:12984*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 12984*FLEN/8, x4, x1, x2)

inst_4329:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83ff; op2val:0x7bff;
op3val:0x8400; valaddr_reg:x3; val_offset:12987*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 12987*FLEN/8, x4, x1, x2)

inst_4330:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x01 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83ff; op2val:0x7bff;
op3val:0x401; valaddr_reg:x3; val_offset:12990*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 12990*FLEN/8, x4, x1, x2)

inst_4331:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83ff; op2val:0x7bff;
op3val:0x8455; valaddr_reg:x3; val_offset:12993*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 12993*FLEN/8, x4, x1, x2)

inst_4332:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83ff; op2val:0x7bff;
op3val:0x7bff; valaddr_reg:x3; val_offset:12996*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 12996*FLEN/8, x4, x1, x2)

inst_4333:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83ff; op2val:0x7bff;
op3val:0xfbff; valaddr_reg:x3; val_offset:12999*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 12999*FLEN/8, x4, x1, x2)

inst_4334:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83ff; op2val:0x7bff;
op3val:0x7c00; valaddr_reg:x3; val_offset:13002*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 13002*FLEN/8, x4, x1, x2)

inst_4335:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83ff; op2val:0x7bff;
op3val:0xfc00; valaddr_reg:x3; val_offset:13005*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 13005*FLEN/8, x4, x1, x2)

inst_4336:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83ff; op2val:0x7bff;
op3val:0x7e00; valaddr_reg:x3; val_offset:13008*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 13008*FLEN/8, x4, x1, x2)

inst_4337:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83ff; op2val:0x7bff;
op3val:0xfe00; valaddr_reg:x3; val_offset:13011*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 13011*FLEN/8, x4, x1, x2)

inst_4338:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x1f and fm3 == 0x201 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83ff; op2val:0x7bff;
op3val:0x7e01; valaddr_reg:x3; val_offset:13014*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 13014*FLEN/8, x4, x1, x2)

inst_4339:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x1f and fm3 == 0x255 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83ff; op2val:0x7bff;
op3val:0xfe55; valaddr_reg:x3; val_offset:13017*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 13017*FLEN/8, x4, x1, x2)

inst_4340:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x1f and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83ff; op2val:0x7bff;
op3val:0x7c01; valaddr_reg:x3; val_offset:13020*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 13020*FLEN/8, x4, x1, x2)

inst_4341:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x1f and fm3 == 0x155 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83ff; op2val:0x7bff;
op3val:0xfd55; valaddr_reg:x3; val_offset:13023*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 13023*FLEN/8, x4, x1, x2)

inst_4342:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83ff; op2val:0x7bff;
op3val:0x3c00; valaddr_reg:x3; val_offset:13026*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 13026*FLEN/8, x4, x1, x2)

inst_4343:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83ff; op2val:0x7bff;
op3val:0xbc00; valaddr_reg:x3; val_offset:13029*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 13029*FLEN/8, x4, x1, x2)

inst_4344:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83ff; op2val:0xfbff;
op3val:0x0; valaddr_reg:x3; val_offset:13032*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 13032*FLEN/8, x4, x1, x2)

inst_4345:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83ff; op2val:0xfbff;
op3val:0x8000; valaddr_reg:x3; val_offset:13035*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 13035*FLEN/8, x4, x1, x2)

inst_4346:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83ff; op2val:0xfbff;
op3val:0x1; valaddr_reg:x3; val_offset:13038*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 13038*FLEN/8, x4, x1, x2)

inst_4347:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83ff; op2val:0xfbff;
op3val:0x8001; valaddr_reg:x3; val_offset:13041*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 13041*FLEN/8, x4, x1, x2)

inst_4348:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x002 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83ff; op2val:0xfbff;
op3val:0x2; valaddr_reg:x3; val_offset:13044*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 13044*FLEN/8, x4, x1, x2)

inst_4349:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3fe and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83ff; op2val:0xfbff;
op3val:0x83fe; valaddr_reg:x3; val_offset:13047*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 13047*FLEN/8, x4, x1, x2)

inst_4350:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83ff; op2val:0xfbff;
op3val:0x3ff; valaddr_reg:x3; val_offset:13050*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 13050*FLEN/8, x4, x1, x2)

inst_4351:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83ff; op2val:0xfbff;
op3val:0x83ff; valaddr_reg:x3; val_offset:13053*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 13053*FLEN/8, x4, x1, x2)

RVTEST_SIGBASE(x1,signature_x1_35)
inst_4352:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83ff; op2val:0xfbff;
op3val:0x400; valaddr_reg:x3; val_offset:13056*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 13056*FLEN/8, x4, x1, x2)

inst_4353:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83ff; op2val:0xfbff;
op3val:0x8400; valaddr_reg:x3; val_offset:13059*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 13059*FLEN/8, x4, x1, x2)

inst_4354:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x01 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83ff; op2val:0xfbff;
op3val:0x401; valaddr_reg:x3; val_offset:13062*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 13062*FLEN/8, x4, x1, x2)

inst_4355:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83ff; op2val:0xfbff;
op3val:0x8455; valaddr_reg:x3; val_offset:13065*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 13065*FLEN/8, x4, x1, x2)

inst_4356:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83ff; op2val:0xfbff;
op3val:0x7bff; valaddr_reg:x3; val_offset:13068*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 13068*FLEN/8, x4, x1, x2)

inst_4357:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83ff; op2val:0xfbff;
op3val:0xfbff; valaddr_reg:x3; val_offset:13071*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 13071*FLEN/8, x4, x1, x2)

inst_4358:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83ff; op2val:0xfbff;
op3val:0x7c00; valaddr_reg:x3; val_offset:13074*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 13074*FLEN/8, x4, x1, x2)

inst_4359:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83ff; op2val:0xfbff;
op3val:0xfc00; valaddr_reg:x3; val_offset:13077*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 13077*FLEN/8, x4, x1, x2)

inst_4360:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83ff; op2val:0xfbff;
op3val:0x7e00; valaddr_reg:x3; val_offset:13080*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 13080*FLEN/8, x4, x1, x2)

inst_4361:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83ff; op2val:0xfbff;
op3val:0xfe00; valaddr_reg:x3; val_offset:13083*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 13083*FLEN/8, x4, x1, x2)

inst_4362:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x1f and fm3 == 0x201 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83ff; op2val:0xfbff;
op3val:0x7e01; valaddr_reg:x3; val_offset:13086*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 13086*FLEN/8, x4, x1, x2)

inst_4363:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x1f and fm3 == 0x255 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83ff; op2val:0xfbff;
op3val:0xfe55; valaddr_reg:x3; val_offset:13089*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 13089*FLEN/8, x4, x1, x2)

inst_4364:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x1f and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83ff; op2val:0xfbff;
op3val:0x7c01; valaddr_reg:x3; val_offset:13092*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 13092*FLEN/8, x4, x1, x2)

inst_4365:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x1f and fm3 == 0x155 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83ff; op2val:0xfbff;
op3val:0xfd55; valaddr_reg:x3; val_offset:13095*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 13095*FLEN/8, x4, x1, x2)

inst_4366:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83ff; op2val:0xfbff;
op3val:0x3c00; valaddr_reg:x3; val_offset:13098*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 13098*FLEN/8, x4, x1, x2)

inst_4367:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83ff; op2val:0xfbff;
op3val:0xbc00; valaddr_reg:x3; val_offset:13101*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 13101*FLEN/8, x4, x1, x2)

inst_4368:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83ff; op2val:0x7c00;
op3val:0x0; valaddr_reg:x3; val_offset:13104*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 13104*FLEN/8, x4, x1, x2)

inst_4369:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83ff; op2val:0x7c00;
op3val:0x8000; valaddr_reg:x3; val_offset:13107*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 13107*FLEN/8, x4, x1, x2)

inst_4370:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83ff; op2val:0x7c00;
op3val:0x1; valaddr_reg:x3; val_offset:13110*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 13110*FLEN/8, x4, x1, x2)

inst_4371:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83ff; op2val:0x7c00;
op3val:0x8001; valaddr_reg:x3; val_offset:13113*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 13113*FLEN/8, x4, x1, x2)

inst_4372:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x002 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83ff; op2val:0x7c00;
op3val:0x2; valaddr_reg:x3; val_offset:13116*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 13116*FLEN/8, x4, x1, x2)

inst_4373:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3fe and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83ff; op2val:0x7c00;
op3val:0x83fe; valaddr_reg:x3; val_offset:13119*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 13119*FLEN/8, x4, x1, x2)

inst_4374:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83ff; op2val:0x7c00;
op3val:0x3ff; valaddr_reg:x3; val_offset:13122*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 13122*FLEN/8, x4, x1, x2)

inst_4375:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83ff; op2val:0x7c00;
op3val:0x83ff; valaddr_reg:x3; val_offset:13125*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 13125*FLEN/8, x4, x1, x2)

inst_4376:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83ff; op2val:0x7c00;
op3val:0x400; valaddr_reg:x3; val_offset:13128*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 13128*FLEN/8, x4, x1, x2)

inst_4377:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83ff; op2val:0x7c00;
op3val:0x8400; valaddr_reg:x3; val_offset:13131*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 13131*FLEN/8, x4, x1, x2)

inst_4378:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83ff; op2val:0x7c00;
op3val:0x401; valaddr_reg:x3; val_offset:13134*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 13134*FLEN/8, x4, x1, x2)

inst_4379:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83ff; op2val:0x7c00;
op3val:0x8455; valaddr_reg:x3; val_offset:13137*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 13137*FLEN/8, x4, x1, x2)

inst_4380:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83ff; op2val:0x7c00;
op3val:0x7bff; valaddr_reg:x3; val_offset:13140*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 13140*FLEN/8, x4, x1, x2)

inst_4381:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83ff; op2val:0x7c00;
op3val:0xfbff; valaddr_reg:x3; val_offset:13143*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 13143*FLEN/8, x4, x1, x2)

inst_4382:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83ff; op2val:0x7c00;
op3val:0x7c00; valaddr_reg:x3; val_offset:13146*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 13146*FLEN/8, x4, x1, x2)

inst_4383:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83ff; op2val:0x7c00;
op3val:0xfc00; valaddr_reg:x3; val_offset:13149*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 13149*FLEN/8, x4, x1, x2)

inst_4384:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83ff; op2val:0x7c00;
op3val:0x7e00; valaddr_reg:x3; val_offset:13152*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 13152*FLEN/8, x4, x1, x2)

inst_4385:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83ff; op2val:0x7c00;
op3val:0xfe00; valaddr_reg:x3; val_offset:13155*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 13155*FLEN/8, x4, x1, x2)

inst_4386:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x201 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83ff; op2val:0x7c00;
op3val:0x7e01; valaddr_reg:x3; val_offset:13158*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 13158*FLEN/8, x4, x1, x2)

inst_4387:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x255 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83ff; op2val:0x7c00;
op3val:0xfe55; valaddr_reg:x3; val_offset:13161*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 13161*FLEN/8, x4, x1, x2)

inst_4388:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83ff; op2val:0x7c00;
op3val:0x7c01; valaddr_reg:x3; val_offset:13164*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 13164*FLEN/8, x4, x1, x2)

inst_4389:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x155 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83ff; op2val:0x7c00;
op3val:0xfd55; valaddr_reg:x3; val_offset:13167*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 13167*FLEN/8, x4, x1, x2)

inst_4390:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83ff; op2val:0x7c00;
op3val:0x3c00; valaddr_reg:x3; val_offset:13170*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 13170*FLEN/8, x4, x1, x2)

inst_4391:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83ff; op2val:0x7c00;
op3val:0xbc00; valaddr_reg:x3; val_offset:13173*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 13173*FLEN/8, x4, x1, x2)

inst_4392:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83ff; op2val:0xfc00;
op3val:0x0; valaddr_reg:x3; val_offset:13176*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 13176*FLEN/8, x4, x1, x2)

inst_4393:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83ff; op2val:0xfc00;
op3val:0x8000; valaddr_reg:x3; val_offset:13179*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 13179*FLEN/8, x4, x1, x2)

inst_4394:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83ff; op2val:0xfc00;
op3val:0x1; valaddr_reg:x3; val_offset:13182*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 13182*FLEN/8, x4, x1, x2)

inst_4395:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83ff; op2val:0xfc00;
op3val:0x8001; valaddr_reg:x3; val_offset:13185*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 13185*FLEN/8, x4, x1, x2)

inst_4396:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x002 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83ff; op2val:0xfc00;
op3val:0x2; valaddr_reg:x3; val_offset:13188*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 13188*FLEN/8, x4, x1, x2)

inst_4397:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3fe and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83ff; op2val:0xfc00;
op3val:0x83fe; valaddr_reg:x3; val_offset:13191*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 13191*FLEN/8, x4, x1, x2)

inst_4398:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83ff; op2val:0xfc00;
op3val:0x3ff; valaddr_reg:x3; val_offset:13194*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 13194*FLEN/8, x4, x1, x2)

inst_4399:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83ff; op2val:0xfc00;
op3val:0x83ff; valaddr_reg:x3; val_offset:13197*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 13197*FLEN/8, x4, x1, x2)

inst_4400:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83ff; op2val:0xfc00;
op3val:0x400; valaddr_reg:x3; val_offset:13200*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 13200*FLEN/8, x4, x1, x2)

inst_4401:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83ff; op2val:0xfc00;
op3val:0x8400; valaddr_reg:x3; val_offset:13203*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 13203*FLEN/8, x4, x1, x2)

inst_4402:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83ff; op2val:0xfc00;
op3val:0x401; valaddr_reg:x3; val_offset:13206*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 13206*FLEN/8, x4, x1, x2)

inst_4403:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83ff; op2val:0xfc00;
op3val:0x8455; valaddr_reg:x3; val_offset:13209*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 13209*FLEN/8, x4, x1, x2)

inst_4404:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83ff; op2val:0xfc00;
op3val:0x7bff; valaddr_reg:x3; val_offset:13212*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 13212*FLEN/8, x4, x1, x2)

inst_4405:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83ff; op2val:0xfc00;
op3val:0xfbff; valaddr_reg:x3; val_offset:13215*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 13215*FLEN/8, x4, x1, x2)

inst_4406:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83ff; op2val:0xfc00;
op3val:0x7c00; valaddr_reg:x3; val_offset:13218*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 13218*FLEN/8, x4, x1, x2)

inst_4407:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83ff; op2val:0xfc00;
op3val:0xfc00; valaddr_reg:x3; val_offset:13221*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 13221*FLEN/8, x4, x1, x2)

inst_4408:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83ff; op2val:0xfc00;
op3val:0x7e00; valaddr_reg:x3; val_offset:13224*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 13224*FLEN/8, x4, x1, x2)

inst_4409:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83ff; op2val:0xfc00;
op3val:0xfe00; valaddr_reg:x3; val_offset:13227*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 13227*FLEN/8, x4, x1, x2)

inst_4410:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x201 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83ff; op2val:0xfc00;
op3val:0x7e01; valaddr_reg:x3; val_offset:13230*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 13230*FLEN/8, x4, x1, x2)

inst_4411:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x255 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83ff; op2val:0xfc00;
op3val:0xfe55; valaddr_reg:x3; val_offset:13233*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 13233*FLEN/8, x4, x1, x2)

inst_4412:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83ff; op2val:0xfc00;
op3val:0x7c01; valaddr_reg:x3; val_offset:13236*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 13236*FLEN/8, x4, x1, x2)

inst_4413:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x155 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83ff; op2val:0xfc00;
op3val:0xfd55; valaddr_reg:x3; val_offset:13239*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 13239*FLEN/8, x4, x1, x2)

inst_4414:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83ff; op2val:0xfc00;
op3val:0x3c00; valaddr_reg:x3; val_offset:13242*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 13242*FLEN/8, x4, x1, x2)

inst_4415:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83ff; op2val:0xfc00;
op3val:0xbc00; valaddr_reg:x3; val_offset:13245*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 13245*FLEN/8, x4, x1, x2)

inst_4416:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83ff; op2val:0x7e00;
op3val:0x0; valaddr_reg:x3; val_offset:13248*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 13248*FLEN/8, x4, x1, x2)

inst_4417:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83ff; op2val:0x7e00;
op3val:0x8000; valaddr_reg:x3; val_offset:13251*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 13251*FLEN/8, x4, x1, x2)

inst_4418:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83ff; op2val:0x7e00;
op3val:0x1; valaddr_reg:x3; val_offset:13254*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 13254*FLEN/8, x4, x1, x2)

inst_4419:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83ff; op2val:0x7e00;
op3val:0x8001; valaddr_reg:x3; val_offset:13257*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 13257*FLEN/8, x4, x1, x2)

inst_4420:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x002 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83ff; op2val:0x7e00;
op3val:0x2; valaddr_reg:x3; val_offset:13260*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 13260*FLEN/8, x4, x1, x2)

inst_4421:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3fe and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83ff; op2val:0x7e00;
op3val:0x83fe; valaddr_reg:x3; val_offset:13263*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 13263*FLEN/8, x4, x1, x2)

inst_4422:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83ff; op2val:0x7e00;
op3val:0x3ff; valaddr_reg:x3; val_offset:13266*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 13266*FLEN/8, x4, x1, x2)

inst_4423:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83ff; op2val:0x7e00;
op3val:0x83ff; valaddr_reg:x3; val_offset:13269*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 13269*FLEN/8, x4, x1, x2)

inst_4424:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83ff; op2val:0x7e00;
op3val:0x400; valaddr_reg:x3; val_offset:13272*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 13272*FLEN/8, x4, x1, x2)

inst_4425:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83ff; op2val:0x7e00;
op3val:0x8400; valaddr_reg:x3; val_offset:13275*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 13275*FLEN/8, x4, x1, x2)

inst_4426:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83ff; op2val:0x7e00;
op3val:0x401; valaddr_reg:x3; val_offset:13278*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 13278*FLEN/8, x4, x1, x2)

inst_4427:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83ff; op2val:0x7e00;
op3val:0x8455; valaddr_reg:x3; val_offset:13281*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 13281*FLEN/8, x4, x1, x2)

inst_4428:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83ff; op2val:0x7e00;
op3val:0x7bff; valaddr_reg:x3; val_offset:13284*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 13284*FLEN/8, x4, x1, x2)

inst_4429:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83ff; op2val:0x7e00;
op3val:0xfbff; valaddr_reg:x3; val_offset:13287*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 13287*FLEN/8, x4, x1, x2)

inst_4430:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83ff; op2val:0x7e00;
op3val:0x7c00; valaddr_reg:x3; val_offset:13290*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 13290*FLEN/8, x4, x1, x2)

inst_4431:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83ff; op2val:0x7e00;
op3val:0xfc00; valaddr_reg:x3; val_offset:13293*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 13293*FLEN/8, x4, x1, x2)

inst_4432:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83ff; op2val:0x7e00;
op3val:0x7e00; valaddr_reg:x3; val_offset:13296*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 13296*FLEN/8, x4, x1, x2)

inst_4433:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83ff; op2val:0x7e00;
op3val:0xfe00; valaddr_reg:x3; val_offset:13299*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 13299*FLEN/8, x4, x1, x2)

inst_4434:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x201 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83ff; op2val:0x7e00;
op3val:0x7e01; valaddr_reg:x3; val_offset:13302*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 13302*FLEN/8, x4, x1, x2)

inst_4435:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x255 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83ff; op2val:0x7e00;
op3val:0xfe55; valaddr_reg:x3; val_offset:13305*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 13305*FLEN/8, x4, x1, x2)

inst_4436:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83ff; op2val:0x7e00;
op3val:0x7c01; valaddr_reg:x3; val_offset:13308*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 13308*FLEN/8, x4, x1, x2)

inst_4437:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x155 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83ff; op2val:0x7e00;
op3val:0xfd55; valaddr_reg:x3; val_offset:13311*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 13311*FLEN/8, x4, x1, x2)

inst_4438:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 0 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83ff; op2val:0x7e00;
op3val:0x3c00; valaddr_reg:x3; val_offset:13314*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 13314*FLEN/8, x4, x1, x2)

inst_4439:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 1 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83ff; op2val:0x7e00;
op3val:0xbc00; valaddr_reg:x3; val_offset:13317*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 13317*FLEN/8, x4, x1, x2)

inst_4440:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83ff; op2val:0xfe00;
op3val:0x0; valaddr_reg:x3; val_offset:13320*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 13320*FLEN/8, x4, x1, x2)

inst_4441:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83ff; op2val:0xfe00;
op3val:0x8000; valaddr_reg:x3; val_offset:13323*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 13323*FLEN/8, x4, x1, x2)

inst_4442:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83ff; op2val:0xfe00;
op3val:0x1; valaddr_reg:x3; val_offset:13326*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 13326*FLEN/8, x4, x1, x2)

inst_4443:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83ff; op2val:0xfe00;
op3val:0x8001; valaddr_reg:x3; val_offset:13329*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 13329*FLEN/8, x4, x1, x2)

inst_4444:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x002 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83ff; op2val:0xfe00;
op3val:0x2; valaddr_reg:x3; val_offset:13332*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 13332*FLEN/8, x4, x1, x2)

inst_4445:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3fe and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83ff; op2val:0xfe00;
op3val:0x83fe; valaddr_reg:x3; val_offset:13335*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 13335*FLEN/8, x4, x1, x2)

inst_4446:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83ff; op2val:0xfe00;
op3val:0x3ff; valaddr_reg:x3; val_offset:13338*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 13338*FLEN/8, x4, x1, x2)

inst_4447:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83ff; op2val:0xfe00;
op3val:0x83ff; valaddr_reg:x3; val_offset:13341*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 13341*FLEN/8, x4, x1, x2)

inst_4448:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83ff; op2val:0xfe00;
op3val:0x400; valaddr_reg:x3; val_offset:13344*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 13344*FLEN/8, x4, x1, x2)

inst_4449:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83ff; op2val:0xfe00;
op3val:0x8400; valaddr_reg:x3; val_offset:13347*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 13347*FLEN/8, x4, x1, x2)

inst_4450:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83ff; op2val:0xfe00;
op3val:0x401; valaddr_reg:x3; val_offset:13350*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 13350*FLEN/8, x4, x1, x2)

inst_4451:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83ff; op2val:0xfe00;
op3val:0x8455; valaddr_reg:x3; val_offset:13353*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 13353*FLEN/8, x4, x1, x2)

inst_4452:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83ff; op2val:0xfe00;
op3val:0x7bff; valaddr_reg:x3; val_offset:13356*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 13356*FLEN/8, x4, x1, x2)

inst_4453:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83ff; op2val:0xfe00;
op3val:0xfbff; valaddr_reg:x3; val_offset:13359*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 13359*FLEN/8, x4, x1, x2)

inst_4454:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83ff; op2val:0xfe00;
op3val:0x7c00; valaddr_reg:x3; val_offset:13362*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 13362*FLEN/8, x4, x1, x2)

inst_4455:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83ff; op2val:0xfe00;
op3val:0xfc00; valaddr_reg:x3; val_offset:13365*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 13365*FLEN/8, x4, x1, x2)

inst_4456:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83ff; op2val:0xfe00;
op3val:0x7e00; valaddr_reg:x3; val_offset:13368*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 13368*FLEN/8, x4, x1, x2)

inst_4457:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83ff; op2val:0xfe00;
op3val:0xfe00; valaddr_reg:x3; val_offset:13371*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 13371*FLEN/8, x4, x1, x2)

inst_4458:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x201 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83ff; op2val:0xfe00;
op3val:0x7e01; valaddr_reg:x3; val_offset:13374*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 13374*FLEN/8, x4, x1, x2)

inst_4459:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x255 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83ff; op2val:0xfe00;
op3val:0xfe55; valaddr_reg:x3; val_offset:13377*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 13377*FLEN/8, x4, x1, x2)

inst_4460:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83ff; op2val:0xfe00;
op3val:0x7c01; valaddr_reg:x3; val_offset:13380*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 13380*FLEN/8, x4, x1, x2)

inst_4461:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x155 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83ff; op2val:0xfe00;
op3val:0xfd55; valaddr_reg:x3; val_offset:13383*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 13383*FLEN/8, x4, x1, x2)

inst_4462:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 0 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83ff; op2val:0xfe00;
op3val:0x3c00; valaddr_reg:x3; val_offset:13386*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 13386*FLEN/8, x4, x1, x2)

inst_4463:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 1 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83ff; op2val:0xfe00;
op3val:0xbc00; valaddr_reg:x3; val_offset:13389*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 13389*FLEN/8, x4, x1, x2)

inst_4464:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83ff; op2val:0x7e01;
op3val:0x0; valaddr_reg:x3; val_offset:13392*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 13392*FLEN/8, x4, x1, x2)

inst_4465:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83ff; op2val:0x7e01;
op3val:0x8000; valaddr_reg:x3; val_offset:13395*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 13395*FLEN/8, x4, x1, x2)

inst_4466:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83ff; op2val:0x7e01;
op3val:0x1; valaddr_reg:x3; val_offset:13398*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 13398*FLEN/8, x4, x1, x2)

inst_4467:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83ff; op2val:0x7e01;
op3val:0x8001; valaddr_reg:x3; val_offset:13401*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 13401*FLEN/8, x4, x1, x2)

inst_4468:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x002 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83ff; op2val:0x7e01;
op3val:0x2; valaddr_reg:x3; val_offset:13404*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 13404*FLEN/8, x4, x1, x2)

inst_4469:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3fe and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83ff; op2val:0x7e01;
op3val:0x83fe; valaddr_reg:x3; val_offset:13407*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 13407*FLEN/8, x4, x1, x2)

inst_4470:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83ff; op2val:0x7e01;
op3val:0x3ff; valaddr_reg:x3; val_offset:13410*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 13410*FLEN/8, x4, x1, x2)

inst_4471:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83ff; op2val:0x7e01;
op3val:0x83ff; valaddr_reg:x3; val_offset:13413*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 13413*FLEN/8, x4, x1, x2)

inst_4472:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83ff; op2val:0x7e01;
op3val:0x400; valaddr_reg:x3; val_offset:13416*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 13416*FLEN/8, x4, x1, x2)

inst_4473:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83ff; op2val:0x7e01;
op3val:0x8400; valaddr_reg:x3; val_offset:13419*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 13419*FLEN/8, x4, x1, x2)

inst_4474:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83ff; op2val:0x7e01;
op3val:0x401; valaddr_reg:x3; val_offset:13422*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 13422*FLEN/8, x4, x1, x2)

inst_4475:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83ff; op2val:0x7e01;
op3val:0x8455; valaddr_reg:x3; val_offset:13425*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 13425*FLEN/8, x4, x1, x2)

inst_4476:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83ff; op2val:0x7e01;
op3val:0x7bff; valaddr_reg:x3; val_offset:13428*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 13428*FLEN/8, x4, x1, x2)

inst_4477:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83ff; op2val:0x7e01;
op3val:0xfbff; valaddr_reg:x3; val_offset:13431*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 13431*FLEN/8, x4, x1, x2)

inst_4478:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83ff; op2val:0x7e01;
op3val:0x7c00; valaddr_reg:x3; val_offset:13434*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 13434*FLEN/8, x4, x1, x2)

inst_4479:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83ff; op2val:0x7e01;
op3val:0xfc00; valaddr_reg:x3; val_offset:13437*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 13437*FLEN/8, x4, x1, x2)

RVTEST_SIGBASE(x1,signature_x1_36)
inst_4480:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83ff; op2val:0x7e01;
op3val:0x7e00; valaddr_reg:x3; val_offset:13440*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 13440*FLEN/8, x4, x1, x2)

inst_4481:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83ff; op2val:0x7e01;
op3val:0xfe00; valaddr_reg:x3; val_offset:13443*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 13443*FLEN/8, x4, x1, x2)

inst_4482:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x201 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83ff; op2val:0x7e01;
op3val:0x7e01; valaddr_reg:x3; val_offset:13446*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 13446*FLEN/8, x4, x1, x2)

inst_4483:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x255 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83ff; op2val:0x7e01;
op3val:0xfe55; valaddr_reg:x3; val_offset:13449*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 13449*FLEN/8, x4, x1, x2)

inst_4484:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83ff; op2val:0x7e01;
op3val:0x7c01; valaddr_reg:x3; val_offset:13452*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 13452*FLEN/8, x4, x1, x2)

inst_4485:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x155 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83ff; op2val:0x7e01;
op3val:0xfd55; valaddr_reg:x3; val_offset:13455*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 13455*FLEN/8, x4, x1, x2)

inst_4486:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fs3 == 0 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83ff; op2val:0x7e01;
op3val:0x3c00; valaddr_reg:x3; val_offset:13458*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 13458*FLEN/8, x4, x1, x2)

inst_4487:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fs3 == 1 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83ff; op2val:0x7e01;
op3val:0xbc00; valaddr_reg:x3; val_offset:13461*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 13461*FLEN/8, x4, x1, x2)

inst_4488:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83ff; op2val:0xfe55;
op3val:0x0; valaddr_reg:x3; val_offset:13464*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 13464*FLEN/8, x4, x1, x2)

inst_4489:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83ff; op2val:0xfe55;
op3val:0x8000; valaddr_reg:x3; val_offset:13467*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 13467*FLEN/8, x4, x1, x2)

inst_4490:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83ff; op2val:0xfe55;
op3val:0x1; valaddr_reg:x3; val_offset:13470*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 13470*FLEN/8, x4, x1, x2)

inst_4491:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83ff; op2val:0xfe55;
op3val:0x8001; valaddr_reg:x3; val_offset:13473*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 13473*FLEN/8, x4, x1, x2)

inst_4492:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x002 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83ff; op2val:0xfe55;
op3val:0x2; valaddr_reg:x3; val_offset:13476*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 13476*FLEN/8, x4, x1, x2)

inst_4493:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3fe and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83ff; op2val:0xfe55;
op3val:0x83fe; valaddr_reg:x3; val_offset:13479*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 13479*FLEN/8, x4, x1, x2)

inst_4494:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83ff; op2val:0xfe55;
op3val:0x3ff; valaddr_reg:x3; val_offset:13482*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 13482*FLEN/8, x4, x1, x2)

inst_4495:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83ff; op2val:0xfe55;
op3val:0x83ff; valaddr_reg:x3; val_offset:13485*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 13485*FLEN/8, x4, x1, x2)

inst_4496:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83ff; op2val:0xfe55;
op3val:0x400; valaddr_reg:x3; val_offset:13488*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 13488*FLEN/8, x4, x1, x2)

inst_4497:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83ff; op2val:0xfe55;
op3val:0x8400; valaddr_reg:x3; val_offset:13491*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 13491*FLEN/8, x4, x1, x2)

inst_4498:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83ff; op2val:0xfe55;
op3val:0x401; valaddr_reg:x3; val_offset:13494*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 13494*FLEN/8, x4, x1, x2)

inst_4499:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83ff; op2val:0xfe55;
op3val:0x8455; valaddr_reg:x3; val_offset:13497*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 13497*FLEN/8, x4, x1, x2)

inst_4500:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83ff; op2val:0xfe55;
op3val:0x7bff; valaddr_reg:x3; val_offset:13500*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 13500*FLEN/8, x4, x1, x2)

inst_4501:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83ff; op2val:0xfe55;
op3val:0xfbff; valaddr_reg:x3; val_offset:13503*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 13503*FLEN/8, x4, x1, x2)

inst_4502:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83ff; op2val:0xfe55;
op3val:0x7c00; valaddr_reg:x3; val_offset:13506*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 13506*FLEN/8, x4, x1, x2)

inst_4503:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83ff; op2val:0xfe55;
op3val:0xfc00; valaddr_reg:x3; val_offset:13509*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 13509*FLEN/8, x4, x1, x2)

inst_4504:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83ff; op2val:0xfe55;
op3val:0x7e00; valaddr_reg:x3; val_offset:13512*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 13512*FLEN/8, x4, x1, x2)

inst_4505:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83ff; op2val:0xfe55;
op3val:0xfe00; valaddr_reg:x3; val_offset:13515*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 13515*FLEN/8, x4, x1, x2)

inst_4506:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x201 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83ff; op2val:0xfe55;
op3val:0x7e01; valaddr_reg:x3; val_offset:13518*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 13518*FLEN/8, x4, x1, x2)

inst_4507:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x255 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83ff; op2val:0xfe55;
op3val:0xfe55; valaddr_reg:x3; val_offset:13521*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 13521*FLEN/8, x4, x1, x2)

inst_4508:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83ff; op2val:0xfe55;
op3val:0x7c01; valaddr_reg:x3; val_offset:13524*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 13524*FLEN/8, x4, x1, x2)

inst_4509:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x155 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83ff; op2val:0xfe55;
op3val:0xfd55; valaddr_reg:x3; val_offset:13527*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 13527*FLEN/8, x4, x1, x2)

inst_4510:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fs3 == 0 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83ff; op2val:0xfe55;
op3val:0x3c00; valaddr_reg:x3; val_offset:13530*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 13530*FLEN/8, x4, x1, x2)

inst_4511:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fs3 == 1 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83ff; op2val:0xfe55;
op3val:0xbc00; valaddr_reg:x3; val_offset:13533*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 13533*FLEN/8, x4, x1, x2)

inst_4512:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83ff; op2val:0x7c01;
op3val:0x0; valaddr_reg:x3; val_offset:13536*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 13536*FLEN/8, x4, x1, x2)

inst_4513:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83ff; op2val:0x7c01;
op3val:0x8000; valaddr_reg:x3; val_offset:13539*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 13539*FLEN/8, x4, x1, x2)

inst_4514:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83ff; op2val:0x7c01;
op3val:0x1; valaddr_reg:x3; val_offset:13542*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 13542*FLEN/8, x4, x1, x2)

inst_4515:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83ff; op2val:0x7c01;
op3val:0x8001; valaddr_reg:x3; val_offset:13545*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 13545*FLEN/8, x4, x1, x2)

inst_4516:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x002 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83ff; op2val:0x7c01;
op3val:0x2; valaddr_reg:x3; val_offset:13548*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 13548*FLEN/8, x4, x1, x2)

inst_4517:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3fe and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83ff; op2val:0x7c01;
op3val:0x83fe; valaddr_reg:x3; val_offset:13551*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 13551*FLEN/8, x4, x1, x2)

inst_4518:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83ff; op2val:0x7c01;
op3val:0x3ff; valaddr_reg:x3; val_offset:13554*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 13554*FLEN/8, x4, x1, x2)

inst_4519:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83ff; op2val:0x7c01;
op3val:0x83ff; valaddr_reg:x3; val_offset:13557*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 13557*FLEN/8, x4, x1, x2)

inst_4520:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83ff; op2val:0x7c01;
op3val:0x400; valaddr_reg:x3; val_offset:13560*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 13560*FLEN/8, x4, x1, x2)

inst_4521:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83ff; op2val:0x7c01;
op3val:0x8400; valaddr_reg:x3; val_offset:13563*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 13563*FLEN/8, x4, x1, x2)

inst_4522:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83ff; op2val:0x7c01;
op3val:0x401; valaddr_reg:x3; val_offset:13566*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 13566*FLEN/8, x4, x1, x2)

inst_4523:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83ff; op2val:0x7c01;
op3val:0x8455; valaddr_reg:x3; val_offset:13569*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 13569*FLEN/8, x4, x1, x2)

inst_4524:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83ff; op2val:0x7c01;
op3val:0x7bff; valaddr_reg:x3; val_offset:13572*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 13572*FLEN/8, x4, x1, x2)

inst_4525:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83ff; op2val:0x7c01;
op3val:0xfbff; valaddr_reg:x3; val_offset:13575*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 13575*FLEN/8, x4, x1, x2)

inst_4526:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83ff; op2val:0x7c01;
op3val:0x7c00; valaddr_reg:x3; val_offset:13578*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 13578*FLEN/8, x4, x1, x2)

inst_4527:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83ff; op2val:0x7c01;
op3val:0xfc00; valaddr_reg:x3; val_offset:13581*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 13581*FLEN/8, x4, x1, x2)

inst_4528:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83ff; op2val:0x7c01;
op3val:0x7e00; valaddr_reg:x3; val_offset:13584*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 13584*FLEN/8, x4, x1, x2)

inst_4529:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83ff; op2val:0x7c01;
op3val:0xfe00; valaddr_reg:x3; val_offset:13587*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 13587*FLEN/8, x4, x1, x2)

inst_4530:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x201 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83ff; op2val:0x7c01;
op3val:0x7e01; valaddr_reg:x3; val_offset:13590*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 13590*FLEN/8, x4, x1, x2)

inst_4531:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x255 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83ff; op2val:0x7c01;
op3val:0xfe55; valaddr_reg:x3; val_offset:13593*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 13593*FLEN/8, x4, x1, x2)

inst_4532:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83ff; op2val:0x7c01;
op3val:0x7c01; valaddr_reg:x3; val_offset:13596*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 13596*FLEN/8, x4, x1, x2)

inst_4533:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x155 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83ff; op2val:0x7c01;
op3val:0xfd55; valaddr_reg:x3; val_offset:13599*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 13599*FLEN/8, x4, x1, x2)

inst_4534:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fs3 == 0 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83ff; op2val:0x7c01;
op3val:0x3c00; valaddr_reg:x3; val_offset:13602*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 13602*FLEN/8, x4, x1, x2)

inst_4535:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fs3 == 1 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83ff; op2val:0x7c01;
op3val:0xbc00; valaddr_reg:x3; val_offset:13605*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 13605*FLEN/8, x4, x1, x2)

inst_4536:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83ff; op2val:0xfd55;
op3val:0x0; valaddr_reg:x3; val_offset:13608*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 13608*FLEN/8, x4, x1, x2)

inst_4537:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83ff; op2val:0xfd55;
op3val:0x8000; valaddr_reg:x3; val_offset:13611*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 13611*FLEN/8, x4, x1, x2)

inst_4538:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83ff; op2val:0xfd55;
op3val:0x1; valaddr_reg:x3; val_offset:13614*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 13614*FLEN/8, x4, x1, x2)

inst_4539:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83ff; op2val:0xfd55;
op3val:0x8001; valaddr_reg:x3; val_offset:13617*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 13617*FLEN/8, x4, x1, x2)

inst_4540:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x002 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83ff; op2val:0xfd55;
op3val:0x2; valaddr_reg:x3; val_offset:13620*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 13620*FLEN/8, x4, x1, x2)

inst_4541:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3fe and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83ff; op2val:0xfd55;
op3val:0x83fe; valaddr_reg:x3; val_offset:13623*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 13623*FLEN/8, x4, x1, x2)

inst_4542:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83ff; op2val:0xfd55;
op3val:0x3ff; valaddr_reg:x3; val_offset:13626*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 13626*FLEN/8, x4, x1, x2)

inst_4543:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83ff; op2val:0xfd55;
op3val:0x83ff; valaddr_reg:x3; val_offset:13629*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 13629*FLEN/8, x4, x1, x2)

inst_4544:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83ff; op2val:0xfd55;
op3val:0x400; valaddr_reg:x3; val_offset:13632*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 13632*FLEN/8, x4, x1, x2)

inst_4545:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83ff; op2val:0xfd55;
op3val:0x8400; valaddr_reg:x3; val_offset:13635*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 13635*FLEN/8, x4, x1, x2)

inst_4546:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83ff; op2val:0xfd55;
op3val:0x401; valaddr_reg:x3; val_offset:13638*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 13638*FLEN/8, x4, x1, x2)

inst_4547:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83ff; op2val:0xfd55;
op3val:0x8455; valaddr_reg:x3; val_offset:13641*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 13641*FLEN/8, x4, x1, x2)

inst_4548:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83ff; op2val:0xfd55;
op3val:0x7bff; valaddr_reg:x3; val_offset:13644*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 13644*FLEN/8, x4, x1, x2)

inst_4549:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83ff; op2val:0xfd55;
op3val:0xfbff; valaddr_reg:x3; val_offset:13647*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 13647*FLEN/8, x4, x1, x2)

inst_4550:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83ff; op2val:0xfd55;
op3val:0x7c00; valaddr_reg:x3; val_offset:13650*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 13650*FLEN/8, x4, x1, x2)

inst_4551:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83ff; op2val:0xfd55;
op3val:0xfc00; valaddr_reg:x3; val_offset:13653*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 13653*FLEN/8, x4, x1, x2)

inst_4552:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83ff; op2val:0xfd55;
op3val:0x7e00; valaddr_reg:x3; val_offset:13656*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 13656*FLEN/8, x4, x1, x2)

inst_4553:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83ff; op2val:0xfd55;
op3val:0xfe00; valaddr_reg:x3; val_offset:13659*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 13659*FLEN/8, x4, x1, x2)

inst_4554:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x201 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83ff; op2val:0xfd55;
op3val:0x7e01; valaddr_reg:x3; val_offset:13662*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 13662*FLEN/8, x4, x1, x2)

inst_4555:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x255 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83ff; op2val:0xfd55;
op3val:0xfe55; valaddr_reg:x3; val_offset:13665*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 13665*FLEN/8, x4, x1, x2)

inst_4556:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83ff; op2val:0xfd55;
op3val:0x7c01; valaddr_reg:x3; val_offset:13668*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 13668*FLEN/8, x4, x1, x2)

inst_4557:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x155 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83ff; op2val:0xfd55;
op3val:0xfd55; valaddr_reg:x3; val_offset:13671*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 13671*FLEN/8, x4, x1, x2)

inst_4558:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fs3 == 0 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83ff; op2val:0xfd55;
op3val:0x3c00; valaddr_reg:x3; val_offset:13674*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 13674*FLEN/8, x4, x1, x2)

inst_4559:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fs3 == 1 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83ff; op2val:0xfd55;
op3val:0xbc00; valaddr_reg:x3; val_offset:13677*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 13677*FLEN/8, x4, x1, x2)

inst_4560:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83ff; op2val:0x3c00;
op3val:0x0; valaddr_reg:x3; val_offset:13680*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 13680*FLEN/8, x4, x1, x2)

#endif
RVTEST_CODE_END
RVMODEL_HALT
RVTEST_DATA_BEGIN
.align 4
rvtest_data:
.word 0xbabecafe
.word 0xabecafeb
.word 0xbecafeba
.word 0xecafebab
test_dataset_0:
NAN_BOXED(64512,16,FLEN)
NAN_BOXED(15360,16,FLEN)
NAN_BOXED(1023,16,FLEN)
NAN_BOXED(64512,16,FLEN)
NAN_BOXED(48128,16,FLEN)
NAN_BOXED(1023,16,FLEN)
NAN_BOXED(32256,16,FLEN)
NAN_BOXED(0,16,FLEN)
NAN_BOXED(1023,16,FLEN)
NAN_BOXED(32256,16,FLEN)
NAN_BOXED(32768,16,FLEN)
NAN_BOXED(1023,16,FLEN)
NAN_BOXED(32256,16,FLEN)
NAN_BOXED(1,16,FLEN)
NAN_BOXED(1023,16,FLEN)
NAN_BOXED(32256,16,FLEN)
NAN_BOXED(32769,16,FLEN)
NAN_BOXED(1023,16,FLEN)
NAN_BOXED(32256,16,FLEN)
NAN_BOXED(2,16,FLEN)
NAN_BOXED(1023,16,FLEN)
NAN_BOXED(32256,16,FLEN)
NAN_BOXED(33790,16,FLEN)
NAN_BOXED(1023,16,FLEN)
NAN_BOXED(32256,16,FLEN)
NAN_BOXED(1023,16,FLEN)
NAN_BOXED(1023,16,FLEN)
NAN_BOXED(32256,16,FLEN)
NAN_BOXED(33791,16,FLEN)
NAN_BOXED(1023,16,FLEN)
NAN_BOXED(32256,16,FLEN)
NAN_BOXED(1024,16,FLEN)
NAN_BOXED(1023,16,FLEN)
NAN_BOXED(32256,16,FLEN)
NAN_BOXED(33792,16,FLEN)
NAN_BOXED(1023,16,FLEN)
NAN_BOXED(32256,16,FLEN)
NAN_BOXED(1025,16,FLEN)
NAN_BOXED(1023,16,FLEN)
NAN_BOXED(32256,16,FLEN)
NAN_BOXED(33877,16,FLEN)
NAN_BOXED(1023,16,FLEN)
NAN_BOXED(32256,16,FLEN)
NAN_BOXED(31743,16,FLEN)
NAN_BOXED(1023,16,FLEN)
NAN_BOXED(32256,16,FLEN)
NAN_BOXED(64511,16,FLEN)
NAN_BOXED(1023,16,FLEN)
NAN_BOXED(32256,16,FLEN)
NAN_BOXED(31744,16,FLEN)
NAN_BOXED(1023,16,FLEN)
NAN_BOXED(32256,16,FLEN)
NAN_BOXED(64512,16,FLEN)
NAN_BOXED(1023,16,FLEN)
NAN_BOXED(32256,16,FLEN)
NAN_BOXED(32256,16,FLEN)
NAN_BOXED(1023,16,FLEN)
NAN_BOXED(32256,16,FLEN)
NAN_BOXED(65024,16,FLEN)
NAN_BOXED(1023,16,FLEN)
NAN_BOXED(32256,16,FLEN)
NAN_BOXED(32257,16,FLEN)
NAN_BOXED(1023,16,FLEN)
NAN_BOXED(32256,16,FLEN)
NAN_BOXED(65109,16,FLEN)
NAN_BOXED(1023,16,FLEN)
NAN_BOXED(32256,16,FLEN)
NAN_BOXED(31745,16,FLEN)
NAN_BOXED(1023,16,FLEN)
NAN_BOXED(32256,16,FLEN)
NAN_BOXED(64853,16,FLEN)
NAN_BOXED(1023,16,FLEN)
NAN_BOXED(32256,16,FLEN)
NAN_BOXED(15360,16,FLEN)
NAN_BOXED(1023,16,FLEN)
NAN_BOXED(32256,16,FLEN)
NAN_BOXED(48128,16,FLEN)
NAN_BOXED(1023,16,FLEN)
NAN_BOXED(65024,16,FLEN)
NAN_BOXED(0,16,FLEN)
NAN_BOXED(1023,16,FLEN)
NAN_BOXED(65024,16,FLEN)
NAN_BOXED(32768,16,FLEN)
NAN_BOXED(1023,16,FLEN)
NAN_BOXED(65024,16,FLEN)
NAN_BOXED(1,16,FLEN)
NAN_BOXED(1023,16,FLEN)
NAN_BOXED(65024,16,FLEN)
NAN_BOXED(32769,16,FLEN)
NAN_BOXED(1023,16,FLEN)
NAN_BOXED(65024,16,FLEN)
NAN_BOXED(2,16,FLEN)
NAN_BOXED(1023,16,FLEN)
NAN_BOXED(65024,16,FLEN)
NAN_BOXED(33790,16,FLEN)
NAN_BOXED(1023,16,FLEN)
NAN_BOXED(65024,16,FLEN)
NAN_BOXED(1023,16,FLEN)
NAN_BOXED(1023,16,FLEN)
NAN_BOXED(65024,16,FLEN)
NAN_BOXED(33791,16,FLEN)
NAN_BOXED(1023,16,FLEN)
NAN_BOXED(65024,16,FLEN)
NAN_BOXED(1024,16,FLEN)
NAN_BOXED(1023,16,FLEN)
NAN_BOXED(65024,16,FLEN)
NAN_BOXED(33792,16,FLEN)
NAN_BOXED(1023,16,FLEN)
NAN_BOXED(65024,16,FLEN)
NAN_BOXED(1025,16,FLEN)
NAN_BOXED(1023,16,FLEN)
NAN_BOXED(65024,16,FLEN)
NAN_BOXED(33877,16,FLEN)
NAN_BOXED(1023,16,FLEN)
NAN_BOXED(65024,16,FLEN)
NAN_BOXED(31743,16,FLEN)
NAN_BOXED(1023,16,FLEN)
NAN_BOXED(65024,16,FLEN)
NAN_BOXED(64511,16,FLEN)
NAN_BOXED(1023,16,FLEN)
NAN_BOXED(65024,16,FLEN)
NAN_BOXED(31744,16,FLEN)
NAN_BOXED(1023,16,FLEN)
NAN_BOXED(65024,16,FLEN)
NAN_BOXED(64512,16,FLEN)
NAN_BOXED(1023,16,FLEN)
NAN_BOXED(65024,16,FLEN)
NAN_BOXED(32256,16,FLEN)
NAN_BOXED(1023,16,FLEN)
NAN_BOXED(65024,16,FLEN)
NAN_BOXED(65024,16,FLEN)
NAN_BOXED(1023,16,FLEN)
NAN_BOXED(65024,16,FLEN)
NAN_BOXED(32257,16,FLEN)
NAN_BOXED(1023,16,FLEN)
NAN_BOXED(65024,16,FLEN)
NAN_BOXED(65109,16,FLEN)
NAN_BOXED(1023,16,FLEN)
NAN_BOXED(65024,16,FLEN)
NAN_BOXED(31745,16,FLEN)
NAN_BOXED(1023,16,FLEN)
NAN_BOXED(65024,16,FLEN)
NAN_BOXED(64853,16,FLEN)
NAN_BOXED(1023,16,FLEN)
NAN_BOXED(65024,16,FLEN)
NAN_BOXED(15360,16,FLEN)
NAN_BOXED(1023,16,FLEN)
NAN_BOXED(65024,16,FLEN)
NAN_BOXED(48128,16,FLEN)
NAN_BOXED(1023,16,FLEN)
NAN_BOXED(32257,16,FLEN)
NAN_BOXED(0,16,FLEN)
NAN_BOXED(1023,16,FLEN)
NAN_BOXED(32257,16,FLEN)
NAN_BOXED(32768,16,FLEN)
NAN_BOXED(1023,16,FLEN)
NAN_BOXED(32257,16,FLEN)
NAN_BOXED(1,16,FLEN)
NAN_BOXED(1023,16,FLEN)
NAN_BOXED(32257,16,FLEN)
NAN_BOXED(32769,16,FLEN)
NAN_BOXED(1023,16,FLEN)
NAN_BOXED(32257,16,FLEN)
NAN_BOXED(2,16,FLEN)
NAN_BOXED(1023,16,FLEN)
NAN_BOXED(32257,16,FLEN)
NAN_BOXED(33790,16,FLEN)
NAN_BOXED(1023,16,FLEN)
NAN_BOXED(32257,16,FLEN)
NAN_BOXED(1023,16,FLEN)
NAN_BOXED(1023,16,FLEN)
NAN_BOXED(32257,16,FLEN)
NAN_BOXED(33791,16,FLEN)
NAN_BOXED(1023,16,FLEN)
NAN_BOXED(32257,16,FLEN)
NAN_BOXED(1024,16,FLEN)
NAN_BOXED(1023,16,FLEN)
NAN_BOXED(32257,16,FLEN)
NAN_BOXED(33792,16,FLEN)
NAN_BOXED(1023,16,FLEN)
NAN_BOXED(32257,16,FLEN)
NAN_BOXED(1025,16,FLEN)
NAN_BOXED(1023,16,FLEN)
NAN_BOXED(32257,16,FLEN)
NAN_BOXED(33877,16,FLEN)
NAN_BOXED(1023,16,FLEN)
NAN_BOXED(32257,16,FLEN)
NAN_BOXED(31743,16,FLEN)
NAN_BOXED(1023,16,FLEN)
NAN_BOXED(32257,16,FLEN)
NAN_BOXED(64511,16,FLEN)
NAN_BOXED(1023,16,FLEN)
NAN_BOXED(32257,16,FLEN)
NAN_BOXED(31744,16,FLEN)
NAN_BOXED(1023,16,FLEN)
NAN_BOXED(32257,16,FLEN)
NAN_BOXED(64512,16,FLEN)
NAN_BOXED(1023,16,FLEN)
NAN_BOXED(32257,16,FLEN)
NAN_BOXED(32256,16,FLEN)
NAN_BOXED(1023,16,FLEN)
NAN_BOXED(32257,16,FLEN)
NAN_BOXED(65024,16,FLEN)
NAN_BOXED(1023,16,FLEN)
NAN_BOXED(32257,16,FLEN)
NAN_BOXED(32257,16,FLEN)
NAN_BOXED(1023,16,FLEN)
NAN_BOXED(32257,16,FLEN)
NAN_BOXED(65109,16,FLEN)
NAN_BOXED(1023,16,FLEN)
NAN_BOXED(32257,16,FLEN)
NAN_BOXED(31745,16,FLEN)
NAN_BOXED(1023,16,FLEN)
NAN_BOXED(32257,16,FLEN)
NAN_BOXED(64853,16,FLEN)
NAN_BOXED(1023,16,FLEN)
NAN_BOXED(32257,16,FLEN)
NAN_BOXED(15360,16,FLEN)
NAN_BOXED(1023,16,FLEN)
NAN_BOXED(32257,16,FLEN)
NAN_BOXED(48128,16,FLEN)
NAN_BOXED(1023,16,FLEN)
NAN_BOXED(65109,16,FLEN)
NAN_BOXED(0,16,FLEN)
NAN_BOXED(1023,16,FLEN)
NAN_BOXED(65109,16,FLEN)
NAN_BOXED(32768,16,FLEN)
NAN_BOXED(1023,16,FLEN)
NAN_BOXED(65109,16,FLEN)
NAN_BOXED(1,16,FLEN)
NAN_BOXED(1023,16,FLEN)
NAN_BOXED(65109,16,FLEN)
NAN_BOXED(32769,16,FLEN)
NAN_BOXED(1023,16,FLEN)
NAN_BOXED(65109,16,FLEN)
NAN_BOXED(2,16,FLEN)
NAN_BOXED(1023,16,FLEN)
NAN_BOXED(65109,16,FLEN)
NAN_BOXED(33790,16,FLEN)
NAN_BOXED(1023,16,FLEN)
NAN_BOXED(65109,16,FLEN)
NAN_BOXED(1023,16,FLEN)
NAN_BOXED(1023,16,FLEN)
NAN_BOXED(65109,16,FLEN)
NAN_BOXED(33791,16,FLEN)
NAN_BOXED(1023,16,FLEN)
NAN_BOXED(65109,16,FLEN)
NAN_BOXED(1024,16,FLEN)
NAN_BOXED(1023,16,FLEN)
NAN_BOXED(65109,16,FLEN)
NAN_BOXED(33792,16,FLEN)
NAN_BOXED(1023,16,FLEN)
NAN_BOXED(65109,16,FLEN)
NAN_BOXED(1025,16,FLEN)
NAN_BOXED(1023,16,FLEN)
NAN_BOXED(65109,16,FLEN)
NAN_BOXED(33877,16,FLEN)
NAN_BOXED(1023,16,FLEN)
NAN_BOXED(65109,16,FLEN)
NAN_BOXED(31743,16,FLEN)
NAN_BOXED(1023,16,FLEN)
NAN_BOXED(65109,16,FLEN)
NAN_BOXED(64511,16,FLEN)
NAN_BOXED(1023,16,FLEN)
NAN_BOXED(65109,16,FLEN)
NAN_BOXED(31744,16,FLEN)
NAN_BOXED(1023,16,FLEN)
NAN_BOXED(65109,16,FLEN)
NAN_BOXED(64512,16,FLEN)
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NAN_BOXED(65024,16,FLEN)
NAN_BOXED(0,16,FLEN)
NAN_BOXED(33791,16,FLEN)
NAN_BOXED(65024,16,FLEN)
NAN_BOXED(32768,16,FLEN)
NAN_BOXED(33791,16,FLEN)
NAN_BOXED(65024,16,FLEN)
NAN_BOXED(1,16,FLEN)
NAN_BOXED(33791,16,FLEN)
NAN_BOXED(65024,16,FLEN)
NAN_BOXED(32769,16,FLEN)
NAN_BOXED(33791,16,FLEN)
NAN_BOXED(65024,16,FLEN)
NAN_BOXED(2,16,FLEN)
NAN_BOXED(33791,16,FLEN)
NAN_BOXED(65024,16,FLEN)
NAN_BOXED(33790,16,FLEN)
NAN_BOXED(33791,16,FLEN)
NAN_BOXED(65024,16,FLEN)
NAN_BOXED(1023,16,FLEN)
NAN_BOXED(33791,16,FLEN)
NAN_BOXED(65024,16,FLEN)
NAN_BOXED(33791,16,FLEN)
NAN_BOXED(33791,16,FLEN)
NAN_BOXED(65024,16,FLEN)
NAN_BOXED(1024,16,FLEN)
NAN_BOXED(33791,16,FLEN)
NAN_BOXED(65024,16,FLEN)
NAN_BOXED(33792,16,FLEN)
NAN_BOXED(33791,16,FLEN)
NAN_BOXED(65024,16,FLEN)
NAN_BOXED(1025,16,FLEN)
NAN_BOXED(33791,16,FLEN)
NAN_BOXED(65024,16,FLEN)
NAN_BOXED(33877,16,FLEN)
NAN_BOXED(33791,16,FLEN)
NAN_BOXED(65024,16,FLEN)
NAN_BOXED(31743,16,FLEN)
NAN_BOXED(33791,16,FLEN)
NAN_BOXED(65024,16,FLEN)
NAN_BOXED(64511,16,FLEN)
NAN_BOXED(33791,16,FLEN)
NAN_BOXED(65024,16,FLEN)
NAN_BOXED(31744,16,FLEN)
NAN_BOXED(33791,16,FLEN)
NAN_BOXED(65024,16,FLEN)
NAN_BOXED(64512,16,FLEN)
NAN_BOXED(33791,16,FLEN)
NAN_BOXED(65024,16,FLEN)
NAN_BOXED(32256,16,FLEN)
NAN_BOXED(33791,16,FLEN)
NAN_BOXED(65024,16,FLEN)
NAN_BOXED(65024,16,FLEN)
NAN_BOXED(33791,16,FLEN)
NAN_BOXED(65024,16,FLEN)
NAN_BOXED(32257,16,FLEN)
NAN_BOXED(33791,16,FLEN)
NAN_BOXED(65024,16,FLEN)
NAN_BOXED(65109,16,FLEN)
NAN_BOXED(33791,16,FLEN)
NAN_BOXED(65024,16,FLEN)
NAN_BOXED(31745,16,FLEN)
NAN_BOXED(33791,16,FLEN)
NAN_BOXED(65024,16,FLEN)
NAN_BOXED(64853,16,FLEN)
NAN_BOXED(33791,16,FLEN)
NAN_BOXED(65024,16,FLEN)
NAN_BOXED(15360,16,FLEN)
NAN_BOXED(33791,16,FLEN)
NAN_BOXED(65024,16,FLEN)
NAN_BOXED(48128,16,FLEN)
NAN_BOXED(33791,16,FLEN)
NAN_BOXED(32257,16,FLEN)
NAN_BOXED(0,16,FLEN)
NAN_BOXED(33791,16,FLEN)
NAN_BOXED(32257,16,FLEN)
NAN_BOXED(32768,16,FLEN)
NAN_BOXED(33791,16,FLEN)
NAN_BOXED(32257,16,FLEN)
NAN_BOXED(1,16,FLEN)
NAN_BOXED(33791,16,FLEN)
NAN_BOXED(32257,16,FLEN)
NAN_BOXED(32769,16,FLEN)
NAN_BOXED(33791,16,FLEN)
NAN_BOXED(32257,16,FLEN)
NAN_BOXED(2,16,FLEN)
NAN_BOXED(33791,16,FLEN)
NAN_BOXED(32257,16,FLEN)
NAN_BOXED(33790,16,FLEN)
NAN_BOXED(33791,16,FLEN)
NAN_BOXED(32257,16,FLEN)
NAN_BOXED(1023,16,FLEN)
NAN_BOXED(33791,16,FLEN)
NAN_BOXED(32257,16,FLEN)
NAN_BOXED(33791,16,FLEN)
NAN_BOXED(33791,16,FLEN)
NAN_BOXED(32257,16,FLEN)
NAN_BOXED(1024,16,FLEN)
NAN_BOXED(33791,16,FLEN)
NAN_BOXED(32257,16,FLEN)
NAN_BOXED(33792,16,FLEN)
NAN_BOXED(33791,16,FLEN)
NAN_BOXED(32257,16,FLEN)
NAN_BOXED(1025,16,FLEN)
NAN_BOXED(33791,16,FLEN)
NAN_BOXED(32257,16,FLEN)
NAN_BOXED(33877,16,FLEN)
NAN_BOXED(33791,16,FLEN)
NAN_BOXED(32257,16,FLEN)
NAN_BOXED(31743,16,FLEN)
NAN_BOXED(33791,16,FLEN)
NAN_BOXED(32257,16,FLEN)
NAN_BOXED(64511,16,FLEN)
NAN_BOXED(33791,16,FLEN)
NAN_BOXED(32257,16,FLEN)
NAN_BOXED(31744,16,FLEN)
NAN_BOXED(33791,16,FLEN)
NAN_BOXED(32257,16,FLEN)
NAN_BOXED(64512,16,FLEN)
NAN_BOXED(33791,16,FLEN)
NAN_BOXED(32257,16,FLEN)
NAN_BOXED(32256,16,FLEN)
NAN_BOXED(33791,16,FLEN)
NAN_BOXED(32257,16,FLEN)
NAN_BOXED(65024,16,FLEN)
NAN_BOXED(33791,16,FLEN)
NAN_BOXED(32257,16,FLEN)
NAN_BOXED(32257,16,FLEN)
NAN_BOXED(33791,16,FLEN)
NAN_BOXED(32257,16,FLEN)
NAN_BOXED(65109,16,FLEN)
NAN_BOXED(33791,16,FLEN)
NAN_BOXED(32257,16,FLEN)
NAN_BOXED(31745,16,FLEN)
NAN_BOXED(33791,16,FLEN)
NAN_BOXED(32257,16,FLEN)
NAN_BOXED(64853,16,FLEN)
NAN_BOXED(33791,16,FLEN)
NAN_BOXED(32257,16,FLEN)
NAN_BOXED(15360,16,FLEN)
NAN_BOXED(33791,16,FLEN)
NAN_BOXED(32257,16,FLEN)
NAN_BOXED(48128,16,FLEN)
NAN_BOXED(33791,16,FLEN)
NAN_BOXED(65109,16,FLEN)
NAN_BOXED(0,16,FLEN)
NAN_BOXED(33791,16,FLEN)
NAN_BOXED(65109,16,FLEN)
NAN_BOXED(32768,16,FLEN)
NAN_BOXED(33791,16,FLEN)
NAN_BOXED(65109,16,FLEN)
NAN_BOXED(1,16,FLEN)
NAN_BOXED(33791,16,FLEN)
NAN_BOXED(65109,16,FLEN)
NAN_BOXED(32769,16,FLEN)
NAN_BOXED(33791,16,FLEN)
NAN_BOXED(65109,16,FLEN)
NAN_BOXED(2,16,FLEN)
NAN_BOXED(33791,16,FLEN)
NAN_BOXED(65109,16,FLEN)
NAN_BOXED(33790,16,FLEN)
NAN_BOXED(33791,16,FLEN)
NAN_BOXED(65109,16,FLEN)
NAN_BOXED(1023,16,FLEN)
NAN_BOXED(33791,16,FLEN)
NAN_BOXED(65109,16,FLEN)
NAN_BOXED(33791,16,FLEN)
NAN_BOXED(33791,16,FLEN)
NAN_BOXED(65109,16,FLEN)
NAN_BOXED(1024,16,FLEN)
NAN_BOXED(33791,16,FLEN)
NAN_BOXED(65109,16,FLEN)
NAN_BOXED(33792,16,FLEN)
NAN_BOXED(33791,16,FLEN)
NAN_BOXED(65109,16,FLEN)
NAN_BOXED(1025,16,FLEN)
NAN_BOXED(33791,16,FLEN)
NAN_BOXED(65109,16,FLEN)
NAN_BOXED(33877,16,FLEN)
NAN_BOXED(33791,16,FLEN)
NAN_BOXED(65109,16,FLEN)
NAN_BOXED(31743,16,FLEN)
NAN_BOXED(33791,16,FLEN)
NAN_BOXED(65109,16,FLEN)
NAN_BOXED(64511,16,FLEN)
NAN_BOXED(33791,16,FLEN)
NAN_BOXED(65109,16,FLEN)
NAN_BOXED(31744,16,FLEN)
NAN_BOXED(33791,16,FLEN)
NAN_BOXED(65109,16,FLEN)
NAN_BOXED(64512,16,FLEN)
NAN_BOXED(33791,16,FLEN)
NAN_BOXED(65109,16,FLEN)
NAN_BOXED(32256,16,FLEN)
NAN_BOXED(33791,16,FLEN)
NAN_BOXED(65109,16,FLEN)
NAN_BOXED(65024,16,FLEN)
NAN_BOXED(33791,16,FLEN)
NAN_BOXED(65109,16,FLEN)
NAN_BOXED(32257,16,FLEN)
NAN_BOXED(33791,16,FLEN)
NAN_BOXED(65109,16,FLEN)
NAN_BOXED(65109,16,FLEN)
NAN_BOXED(33791,16,FLEN)
NAN_BOXED(65109,16,FLEN)
NAN_BOXED(31745,16,FLEN)
NAN_BOXED(33791,16,FLEN)
NAN_BOXED(65109,16,FLEN)
NAN_BOXED(64853,16,FLEN)
NAN_BOXED(33791,16,FLEN)
NAN_BOXED(65109,16,FLEN)
NAN_BOXED(15360,16,FLEN)
NAN_BOXED(33791,16,FLEN)
NAN_BOXED(65109,16,FLEN)
NAN_BOXED(48128,16,FLEN)
NAN_BOXED(33791,16,FLEN)
NAN_BOXED(31745,16,FLEN)
NAN_BOXED(0,16,FLEN)
NAN_BOXED(33791,16,FLEN)
NAN_BOXED(31745,16,FLEN)
NAN_BOXED(32768,16,FLEN)
NAN_BOXED(33791,16,FLEN)
NAN_BOXED(31745,16,FLEN)
NAN_BOXED(1,16,FLEN)
NAN_BOXED(33791,16,FLEN)
NAN_BOXED(31745,16,FLEN)
NAN_BOXED(32769,16,FLEN)
NAN_BOXED(33791,16,FLEN)
NAN_BOXED(31745,16,FLEN)
NAN_BOXED(2,16,FLEN)
NAN_BOXED(33791,16,FLEN)
NAN_BOXED(31745,16,FLEN)
NAN_BOXED(33790,16,FLEN)
NAN_BOXED(33791,16,FLEN)
NAN_BOXED(31745,16,FLEN)
NAN_BOXED(1023,16,FLEN)
NAN_BOXED(33791,16,FLEN)
NAN_BOXED(31745,16,FLEN)
NAN_BOXED(33791,16,FLEN)
NAN_BOXED(33791,16,FLEN)
NAN_BOXED(31745,16,FLEN)
NAN_BOXED(1024,16,FLEN)
NAN_BOXED(33791,16,FLEN)
NAN_BOXED(31745,16,FLEN)
NAN_BOXED(33792,16,FLEN)
NAN_BOXED(33791,16,FLEN)
NAN_BOXED(31745,16,FLEN)
NAN_BOXED(1025,16,FLEN)
NAN_BOXED(33791,16,FLEN)
NAN_BOXED(31745,16,FLEN)
NAN_BOXED(33877,16,FLEN)
NAN_BOXED(33791,16,FLEN)
NAN_BOXED(31745,16,FLEN)
NAN_BOXED(31743,16,FLEN)
NAN_BOXED(33791,16,FLEN)
NAN_BOXED(31745,16,FLEN)
NAN_BOXED(64511,16,FLEN)
NAN_BOXED(33791,16,FLEN)
NAN_BOXED(31745,16,FLEN)
NAN_BOXED(31744,16,FLEN)
NAN_BOXED(33791,16,FLEN)
NAN_BOXED(31745,16,FLEN)
NAN_BOXED(64512,16,FLEN)
NAN_BOXED(33791,16,FLEN)
NAN_BOXED(31745,16,FLEN)
NAN_BOXED(32256,16,FLEN)
NAN_BOXED(33791,16,FLEN)
NAN_BOXED(31745,16,FLEN)
NAN_BOXED(65024,16,FLEN)
NAN_BOXED(33791,16,FLEN)
NAN_BOXED(31745,16,FLEN)
NAN_BOXED(32257,16,FLEN)
NAN_BOXED(33791,16,FLEN)
NAN_BOXED(31745,16,FLEN)
NAN_BOXED(65109,16,FLEN)
NAN_BOXED(33791,16,FLEN)
NAN_BOXED(31745,16,FLEN)
NAN_BOXED(31745,16,FLEN)
NAN_BOXED(33791,16,FLEN)
NAN_BOXED(31745,16,FLEN)
NAN_BOXED(64853,16,FLEN)
NAN_BOXED(33791,16,FLEN)
NAN_BOXED(31745,16,FLEN)
NAN_BOXED(15360,16,FLEN)
NAN_BOXED(33791,16,FLEN)
NAN_BOXED(31745,16,FLEN)
NAN_BOXED(48128,16,FLEN)
NAN_BOXED(33791,16,FLEN)
NAN_BOXED(64853,16,FLEN)
NAN_BOXED(0,16,FLEN)
NAN_BOXED(33791,16,FLEN)
NAN_BOXED(64853,16,FLEN)
NAN_BOXED(32768,16,FLEN)
NAN_BOXED(33791,16,FLEN)
NAN_BOXED(64853,16,FLEN)
NAN_BOXED(1,16,FLEN)
NAN_BOXED(33791,16,FLEN)
NAN_BOXED(64853,16,FLEN)
NAN_BOXED(32769,16,FLEN)
NAN_BOXED(33791,16,FLEN)
NAN_BOXED(64853,16,FLEN)
NAN_BOXED(2,16,FLEN)
NAN_BOXED(33791,16,FLEN)
NAN_BOXED(64853,16,FLEN)
NAN_BOXED(33790,16,FLEN)
NAN_BOXED(33791,16,FLEN)
NAN_BOXED(64853,16,FLEN)
NAN_BOXED(1023,16,FLEN)
NAN_BOXED(33791,16,FLEN)
NAN_BOXED(64853,16,FLEN)
NAN_BOXED(33791,16,FLEN)
NAN_BOXED(33791,16,FLEN)
NAN_BOXED(64853,16,FLEN)
NAN_BOXED(1024,16,FLEN)
NAN_BOXED(33791,16,FLEN)
NAN_BOXED(64853,16,FLEN)
NAN_BOXED(33792,16,FLEN)
NAN_BOXED(33791,16,FLEN)
NAN_BOXED(64853,16,FLEN)
NAN_BOXED(1025,16,FLEN)
NAN_BOXED(33791,16,FLEN)
NAN_BOXED(64853,16,FLEN)
NAN_BOXED(33877,16,FLEN)
NAN_BOXED(33791,16,FLEN)
NAN_BOXED(64853,16,FLEN)
NAN_BOXED(31743,16,FLEN)
NAN_BOXED(33791,16,FLEN)
NAN_BOXED(64853,16,FLEN)
NAN_BOXED(64511,16,FLEN)
NAN_BOXED(33791,16,FLEN)
NAN_BOXED(64853,16,FLEN)
NAN_BOXED(31744,16,FLEN)
NAN_BOXED(33791,16,FLEN)
NAN_BOXED(64853,16,FLEN)
NAN_BOXED(64512,16,FLEN)
NAN_BOXED(33791,16,FLEN)
NAN_BOXED(64853,16,FLEN)
NAN_BOXED(32256,16,FLEN)
NAN_BOXED(33791,16,FLEN)
NAN_BOXED(64853,16,FLEN)
NAN_BOXED(65024,16,FLEN)
NAN_BOXED(33791,16,FLEN)
NAN_BOXED(64853,16,FLEN)
NAN_BOXED(32257,16,FLEN)
NAN_BOXED(33791,16,FLEN)
NAN_BOXED(64853,16,FLEN)
NAN_BOXED(65109,16,FLEN)
NAN_BOXED(33791,16,FLEN)
NAN_BOXED(64853,16,FLEN)
NAN_BOXED(31745,16,FLEN)
NAN_BOXED(33791,16,FLEN)
NAN_BOXED(64853,16,FLEN)
NAN_BOXED(64853,16,FLEN)
NAN_BOXED(33791,16,FLEN)
NAN_BOXED(64853,16,FLEN)
NAN_BOXED(15360,16,FLEN)
NAN_BOXED(33791,16,FLEN)
NAN_BOXED(64853,16,FLEN)
NAN_BOXED(48128,16,FLEN)
NAN_BOXED(33791,16,FLEN)
NAN_BOXED(15360,16,FLEN)
NAN_BOXED(0,16,FLEN)
NAN_BOXED(33791,16,FLEN)
NAN_BOXED(15360,16,FLEN)
NAN_BOXED(32768,16,FLEN)
NAN_BOXED(33791,16,FLEN)
NAN_BOXED(15360,16,FLEN)
NAN_BOXED(1,16,FLEN)
NAN_BOXED(33791,16,FLEN)
NAN_BOXED(15360,16,FLEN)
NAN_BOXED(32769,16,FLEN)
NAN_BOXED(33791,16,FLEN)
NAN_BOXED(15360,16,FLEN)
NAN_BOXED(2,16,FLEN)
NAN_BOXED(33791,16,FLEN)
NAN_BOXED(15360,16,FLEN)
NAN_BOXED(33790,16,FLEN)
NAN_BOXED(33791,16,FLEN)
NAN_BOXED(15360,16,FLEN)
NAN_BOXED(1023,16,FLEN)
NAN_BOXED(33791,16,FLEN)
NAN_BOXED(15360,16,FLEN)
NAN_BOXED(33791,16,FLEN)
NAN_BOXED(33791,16,FLEN)
NAN_BOXED(15360,16,FLEN)
NAN_BOXED(1024,16,FLEN)
NAN_BOXED(33791,16,FLEN)
NAN_BOXED(15360,16,FLEN)
NAN_BOXED(33792,16,FLEN)
NAN_BOXED(33791,16,FLEN)
NAN_BOXED(15360,16,FLEN)
NAN_BOXED(1025,16,FLEN)
NAN_BOXED(33791,16,FLEN)
NAN_BOXED(15360,16,FLEN)
NAN_BOXED(33877,16,FLEN)
NAN_BOXED(33791,16,FLEN)
NAN_BOXED(15360,16,FLEN)
NAN_BOXED(31743,16,FLEN)
NAN_BOXED(33791,16,FLEN)
NAN_BOXED(15360,16,FLEN)
NAN_BOXED(64511,16,FLEN)
NAN_BOXED(33791,16,FLEN)
NAN_BOXED(15360,16,FLEN)
NAN_BOXED(31744,16,FLEN)
NAN_BOXED(33791,16,FLEN)
NAN_BOXED(15360,16,FLEN)
NAN_BOXED(64512,16,FLEN)
NAN_BOXED(33791,16,FLEN)
NAN_BOXED(15360,16,FLEN)
NAN_BOXED(32256,16,FLEN)
NAN_BOXED(33791,16,FLEN)
NAN_BOXED(15360,16,FLEN)
NAN_BOXED(65024,16,FLEN)
NAN_BOXED(33791,16,FLEN)
NAN_BOXED(15360,16,FLEN)
NAN_BOXED(32257,16,FLEN)
NAN_BOXED(33791,16,FLEN)
NAN_BOXED(15360,16,FLEN)
NAN_BOXED(65109,16,FLEN)
NAN_BOXED(33791,16,FLEN)
NAN_BOXED(15360,16,FLEN)
NAN_BOXED(31745,16,FLEN)
NAN_BOXED(33791,16,FLEN)
NAN_BOXED(15360,16,FLEN)
NAN_BOXED(64853,16,FLEN)
NAN_BOXED(33791,16,FLEN)
NAN_BOXED(15360,16,FLEN)
NAN_BOXED(15360,16,FLEN)
NAN_BOXED(33791,16,FLEN)
NAN_BOXED(15360,16,FLEN)
NAN_BOXED(48128,16,FLEN)
NAN_BOXED(33791,16,FLEN)
NAN_BOXED(48128,16,FLEN)
NAN_BOXED(0,16,FLEN)
NAN_BOXED(33791,16,FLEN)
NAN_BOXED(48128,16,FLEN)
NAN_BOXED(32768,16,FLEN)
NAN_BOXED(33791,16,FLEN)
NAN_BOXED(48128,16,FLEN)
NAN_BOXED(1,16,FLEN)
NAN_BOXED(33791,16,FLEN)
NAN_BOXED(48128,16,FLEN)
NAN_BOXED(32769,16,FLEN)
NAN_BOXED(33791,16,FLEN)
NAN_BOXED(48128,16,FLEN)
NAN_BOXED(2,16,FLEN)
NAN_BOXED(33791,16,FLEN)
NAN_BOXED(48128,16,FLEN)
NAN_BOXED(33790,16,FLEN)
NAN_BOXED(33791,16,FLEN)
NAN_BOXED(48128,16,FLEN)
NAN_BOXED(1023,16,FLEN)
NAN_BOXED(33791,16,FLEN)
NAN_BOXED(48128,16,FLEN)
NAN_BOXED(33791,16,FLEN)
NAN_BOXED(33791,16,FLEN)
NAN_BOXED(48128,16,FLEN)
NAN_BOXED(1024,16,FLEN)
NAN_BOXED(33791,16,FLEN)
NAN_BOXED(48128,16,FLEN)
NAN_BOXED(33792,16,FLEN)
NAN_BOXED(33791,16,FLEN)
NAN_BOXED(48128,16,FLEN)
NAN_BOXED(1025,16,FLEN)
NAN_BOXED(33791,16,FLEN)
NAN_BOXED(48128,16,FLEN)
NAN_BOXED(33877,16,FLEN)
NAN_BOXED(33791,16,FLEN)
NAN_BOXED(48128,16,FLEN)
NAN_BOXED(31743,16,FLEN)
NAN_BOXED(33791,16,FLEN)
NAN_BOXED(48128,16,FLEN)
NAN_BOXED(64511,16,FLEN)
NAN_BOXED(33791,16,FLEN)
NAN_BOXED(48128,16,FLEN)
NAN_BOXED(31744,16,FLEN)
NAN_BOXED(33791,16,FLEN)
NAN_BOXED(48128,16,FLEN)
NAN_BOXED(64512,16,FLEN)
NAN_BOXED(33791,16,FLEN)
NAN_BOXED(48128,16,FLEN)
NAN_BOXED(32256,16,FLEN)
NAN_BOXED(33791,16,FLEN)
NAN_BOXED(48128,16,FLEN)
NAN_BOXED(65024,16,FLEN)
NAN_BOXED(33791,16,FLEN)
NAN_BOXED(48128,16,FLEN)
NAN_BOXED(32257,16,FLEN)
NAN_BOXED(33791,16,FLEN)
NAN_BOXED(48128,16,FLEN)
NAN_BOXED(65109,16,FLEN)
NAN_BOXED(33791,16,FLEN)
NAN_BOXED(48128,16,FLEN)
NAN_BOXED(31745,16,FLEN)
NAN_BOXED(33791,16,FLEN)
NAN_BOXED(48128,16,FLEN)
NAN_BOXED(64853,16,FLEN)
NAN_BOXED(33791,16,FLEN)
RVTEST_DATA_END

RVMODEL_DATA_BEGIN
rvtest_sig_begin:
sig_begin_canary:
CANARY;



signature_x1_0:
    .fill 0*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_1:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_2:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_3:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_4:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_5:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_6:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_7:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_8:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_9:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_10:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_11:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_12:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_13:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_14:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_15:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_16:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_17:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_18:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_19:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_20:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_21:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_22:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_23:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_24:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_25:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_26:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_27:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_28:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_29:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_30:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_31:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_32:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_33:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_34:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_35:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_36:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_37:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_38:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_39:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_40:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_41:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_42:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_43:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_44:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_45:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_46:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_47:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_48:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_49:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_50:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_51:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_52:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_53:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_54:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_55:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_56:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_57:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_58:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_59:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_60:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_61:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_62:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_63:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_64:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_65:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_66:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_67:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_68:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_69:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_70:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_71:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_72:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_73:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_74:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_75:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_76:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_77:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_78:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_79:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_80:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_81:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_82:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_83:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_84:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_85:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_86:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_87:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_88:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_89:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_90:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_91:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_92:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_93:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_94:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_95:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_96:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_97:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_98:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_99:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_100:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_101:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_102:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_103:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_104:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_105:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_106:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_107:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_108:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_109:
    .fill 14*((SIGALIGN)/4),4,0xdeadbeef

#ifdef rvtest_mtrap_routine
tsig_begin_canary:
CANARY;

mtrap_sigptr:
    .fill 64*XLEN/32,4,0xdeadbeef

tsig_end_canary:
CANARY;
#endif

#ifdef rvtest_gpr_save

gpr_save:
    .fill 32*XLEN/32,4,0xdeadbeef

#endif


sig_end_canary:
CANARY;
rvtest_sig_end:
RVMODEL_DATA_END
