
// -----------
// This file was generated by riscv_ctg (https://github.com/riscv-software-src/riscv-ctg)
// version   : 0.12.2
// timestamp : Wed Sep 25 06:02:02 2024 GMT
// usage     : riscv_ctg \
//                  -- cgf //                  --cgf /home/riscv/testing/riscv-ctg/sample_cgfs/dataset.cgf \
//                  --cgf /home/riscv/testing/riscv-ctg/sample_cgfs/sample_cgfs_fext/RV32Zhinx/rv32h_fsub.cgf \
 \
//                  -- xlen 32  \
//                  --randomize \
// -----------
//
// -----------
// Copyright (c) 2020. RISC-V International. All rights reserved.
// SPDX-License-Identifier: BSD-3-Clause
// -----------
//
// This assembly file tests the fsub.h instruction of the RISC-V RV32_Zfinx_Zhinx,RV64_Zfinx_Zhinx extension for the fsub_b7 covergroup.
// 
#include "model_test.h"
#include "arch_test.h"
RVTEST_ISA("RV32I_Zfinx_Zhinx,RV64I_Zfinx_Zhinx")

.section .text.init
.globl rvtest_entry_point
rvtest_entry_point:
RVMODEL_BOOT
RVTEST_CODE_BEGIN

#ifdef TEST_CASE_1

RVTEST_CASE(0,"//check ISA:=regex(.*I.*Zfinx.*Zhinx.*);def TEST_CASE_1=True;",fsub_b7)

RVTEST_FP_ENABLE()
RVTEST_VALBASEUPD(x3,test_dataset_0)
RVTEST_SIGBASE(x2,signature_x2_1)

inst_0:
// rs1 == rs2 == rd, rs1==x8, rs2==x8, rd==x8,fs1 == 0 and fe1 == 0x1c and fm1 == 0x04c and fs2 == 0 and fe2 == 0x1c and fm2 == 0x04c and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x8; op2:x8; dest:x8; op1val:0x704c; op2val:0x704c;
   valaddr_reg:x3; val_offset:0*FLEN/8; rmval:dyn; fcsr: 96;
   correctval:??; testreg:x1*/
TEST_FPRR_OP(fsub.h, x8, x8, x8, dyn, 96, 0, x3, 0*FLEN/8, x5, x2, x1)

inst_1:
// rs2 == rd != rs1, rs1==x26, rs2==x9, rd==x9,fs1 == 0 and fe1 == 0x1e and fm1 == 0x21b and fs2 == 0 and fe2 == 0x1e and fm2 == 0x21b and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x26; op2:x9; dest:x9; op1val:0x7a1b; op2val:0x7a1b;
   valaddr_reg:x3; val_offset:2*FLEN/8; rmval:dyn; fcsr: 96;
   correctval:??; testreg:x1*/
TEST_FPRR_OP(fsub.h, x9, x26, x9, dyn, 96, 0, x3, 2*FLEN/8, x5, x2, x1)

inst_2:
// rs1 == rd != rs2, rs1==x24, rs2==x13, rd==x24,fs1 == 0 and fe1 == 0x1d and fm1 == 0x3ec and fs2 == 0 and fe2 == 0x1d and fm2 == 0x3ec and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x24; op2:x13; dest:x24; op1val:0x77ec; op2val:0x77ec;
   valaddr_reg:x3; val_offset:4*FLEN/8; rmval:dyn; fcsr: 96;
   correctval:??; testreg:x1*/
TEST_FPRR_OP(fsub.h, x24, x24, x13, dyn, 96, 0, x3, 4*FLEN/8, x5, x2, x1)

inst_3:
// rs1 != rs2  and rs1 != rd and rs2 != rd, rs1==x10, rs2==x11, rd==x16,fs1 == 0 and fe1 == 0x1e and fm1 == 0x135 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x135 and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x10; op2:x11; dest:x16; op1val:0x7935; op2val:0x7935;
   valaddr_reg:x3; val_offset:6*FLEN/8; rmval:dyn; fcsr: 96;
   correctval:??; testreg:x1*/
TEST_FPRR_OP(fsub.h, x16, x10, x11, dyn, 96, 0, x3, 6*FLEN/8, x5, x2, x1)

inst_4:
// rs1 == rs2 != rd, rs1==x27, rs2==x27, rd==x20,fs1 == 0 and fe1 == 0x1b and fm1 == 0x201 and fs2 == 0 and fe2 == 0x1b and fm2 == 0x201 and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x27; op2:x27; dest:x20; op1val:0x6e01; op2val:0x6e01;
   valaddr_reg:x3; val_offset:8*FLEN/8; rmval:dyn; fcsr: 96;
   correctval:??; testreg:x1*/
TEST_FPRR_OP(fsub.h, x20, x27, x27, dyn, 96, 0, x3, 8*FLEN/8, x5, x2, x1)

inst_5:
// rs1==x30, rs2==x16, rd==x29,fs1 == 0 and fe1 == 0x1e and fm1 == 0x2ae and fs2 == 0 and fe2 == 0x1e and fm2 == 0x2ae and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x16; dest:x29; op1val:0x7aae; op2val:0x7aae;
   valaddr_reg:x3; val_offset:10*FLEN/8; rmval:dyn; fcsr: 96;
   correctval:??; testreg:x1*/
TEST_FPRR_OP(fsub.h, x29, x30, x16, dyn, 96, 0, x3, 10*FLEN/8, x5, x2, x1)

inst_6:
// rs1==x23, rs2==x29, rd==x10,fs1 == 0 and fe1 == 0x1e and fm1 == 0x218 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x218 and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x23; op2:x29; dest:x10; op1val:0x7a18; op2val:0x7a18;
   valaddr_reg:x3; val_offset:12*FLEN/8; rmval:dyn; fcsr: 96;
   correctval:??; testreg:x1*/
TEST_FPRR_OP(fsub.h, x10, x23, x29, dyn, 96, 0, x3, 12*FLEN/8, x5, x2, x1)

inst_7:
// rs1==x12, rs2==x18, rd==x15,fs1 == 0 and fe1 == 0x1d and fm1 == 0x31f and fs2 == 0 and fe2 == 0x1d and fm2 == 0x31f and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x12; op2:x18; dest:x15; op1val:0x771f; op2val:0x771f;
   valaddr_reg:x3; val_offset:14*FLEN/8; rmval:dyn; fcsr: 96;
   correctval:??; testreg:x1*/
TEST_FPRR_OP(fsub.h, x15, x12, x18, dyn, 96, 0, x3, 14*FLEN/8, x5, x2, x1)

inst_8:
// rs1==x21, rs2==x0, rd==x30,fs1 == 0 and fe1 == 0x1c and fm1 == 0x351 and fs2 == 0 and fe2 == 0x1c and fm2 == 0x351 and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x21; op2:x0; dest:x30; op1val:0x7351; op2val:0x0;
   valaddr_reg:x3; val_offset:16*FLEN/8; rmval:dyn; fcsr: 96;
   correctval:??; testreg:x1*/
TEST_FPRR_OP(fsub.h, x30, x21, x0, dyn, 96, 0, x3, 16*FLEN/8, x5, x2, x1)

inst_9:
// rs1==x17, rs2==x7, rd==x4,fs1 == 0 and fe1 == 0x1e and fm1 == 0x335 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x335 and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x17; op2:x7; dest:x4; op1val:0x7b35; op2val:0x7b35;
   valaddr_reg:x3; val_offset:18*FLEN/8; rmval:dyn; fcsr: 96;
   correctval:??; testreg:x1*/
TEST_FPRR_OP(fsub.h, x4, x17, x7, dyn, 96, 0, x3, 18*FLEN/8, x5, x2, x1)

inst_10:
// rs1==x6, rs2==x23, rd==x26,fs1 == 0 and fe1 == 0x19 and fm1 == 0x283 and fs2 == 0 and fe2 == 0x19 and fm2 == 0x283 and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x6; op2:x23; dest:x26; op1val:0x6683; op2val:0x6683;
   valaddr_reg:x3; val_offset:20*FLEN/8; rmval:dyn; fcsr: 96;
   correctval:??; testreg:x1*/
TEST_FPRR_OP(fsub.h, x26, x6, x23, dyn, 96, 0, x3, 20*FLEN/8, x5, x2, x1)

inst_11:
// rs1==x15, rs2==x4, rd==x12,fs1 == 0 and fe1 == 0x1e and fm1 == 0x382 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x382 and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x15; op2:x4; dest:x12; op1val:0x7b82; op2val:0x7b82;
   valaddr_reg:x3; val_offset:22*FLEN/8; rmval:dyn; fcsr: 96;
   correctval:??; testreg:x1*/
TEST_FPRR_OP(fsub.h, x12, x15, x4, dyn, 96, 0, x3, 22*FLEN/8, x5, x2, x1)

inst_12:
// rs1==x28, rs2==x14, rd==x7,fs1 == 0 and fe1 == 0x1c and fm1 == 0x2ed and fs2 == 0 and fe2 == 0x1c and fm2 == 0x2ed and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x28; op2:x14; dest:x7; op1val:0x72ed; op2val:0x72ed;
   valaddr_reg:x3; val_offset:24*FLEN/8; rmval:dyn; fcsr: 96;
   correctval:??; testreg:x1*/
TEST_FPRR_OP(fsub.h, x7, x28, x14, dyn, 96, 0, x3, 24*FLEN/8, x5, x2, x1)
RVTEST_VALBASEUPD(x16,test_dataset_1)

inst_13:
// rs1==x19, rs2==x10, rd==x22,fs1 == 0 and fe1 == 0x19 and fm1 == 0x36f and fs2 == 0 and fe2 == 0x19 and fm2 == 0x36f and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x19; op2:x10; dest:x22; op1val:0x676f; op2val:0x676f;
   valaddr_reg:x16; val_offset:0*FLEN/8; rmval:dyn; fcsr: 96;
   correctval:??; testreg:x1*/
TEST_FPRR_OP(fsub.h, x22, x19, x10, dyn, 96, 0, x16, 0*FLEN/8, x20, x2, x1)

inst_14:
// rs1==x25, rs2==x3, rd==x1,fs1 == 0 and fe1 == 0x1d and fm1 == 0x300 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x300 and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x25; op2:x3; dest:x1; op1val:0x7700; op2val:0x7700;
   valaddr_reg:x16; val_offset:2*FLEN/8; rmval:dyn; fcsr: 96;
   correctval:??; testreg:x10*/
TEST_FPRR_OP(fsub.h, x1, x25, x3, dyn, 96, 0, x16, 2*FLEN/8, x20, x2, x10)
RVTEST_SIGBASE(x8,signature_x8_0)

inst_15:
// rs1==x7, rs2==x1, rd==x14,fs1 == 0 and fe1 == 0x1c and fm1 == 0x374 and fs2 == 0 and fe2 == 0x1c and fm2 == 0x374 and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x7; op2:x1; dest:x14; op1val:0x7374; op2val:0x7374;
   valaddr_reg:x16; val_offset:4*FLEN/8; rmval:dyn; fcsr: 96;
   correctval:??; testreg:x10*/
TEST_FPRR_OP(fsub.h, x14, x7, x1, dyn, 96, 0, x16, 4*FLEN/8, x20, x8, x10)

inst_16:
// rs1==x2, rs2==x31, rd==x6,fs1 == 0 and fe1 == 0x1c and fm1 == 0x2ff and fs2 == 0 and fe2 == 0x1c and fm2 == 0x2ff and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x2; op2:x31; dest:x6; op1val:0x72ff; op2val:0x72ff;
   valaddr_reg:x16; val_offset:6*FLEN/8; rmval:dyn; fcsr: 96;
   correctval:??; testreg:x10*/
TEST_FPRR_OP(fsub.h, x6, x2, x31, dyn, 96, 0, x16, 6*FLEN/8, x20, x8, x10)

inst_17:
// rs1==x9, rs2==x2, rd==x11,fs1 == 0 and fe1 == 0x1d and fm1 == 0x0a2 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x0a2 and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x9; op2:x2; dest:x11; op1val:0x74a2; op2val:0x74a2;
   valaddr_reg:x16; val_offset:8*FLEN/8; rmval:dyn; fcsr: 96;
   correctval:??; testreg:x10*/
TEST_FPRR_OP(fsub.h, x11, x9, x2, dyn, 96, 0, x16, 8*FLEN/8, x20, x8, x10)

inst_18:
// rs1==x31, rs2==x6, rd==x2,fs1 == 0 and fe1 == 0x1e and fm1 == 0x2b2 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x2b2 and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x31; op2:x6; dest:x2; op1val:0x7ab2; op2val:0x7ab2;
   valaddr_reg:x16; val_offset:10*FLEN/8; rmval:dyn; fcsr: 96;
   correctval:??; testreg:x10*/
TEST_FPRR_OP(fsub.h, x2, x31, x6, dyn, 96, 0, x16, 10*FLEN/8, x20, x8, x10)

inst_19:
// rs1==x4, rs2==x5, rd==x3,fs1 == 0 and fe1 == 0x1e and fm1 == 0x122 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x122 and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x4; op2:x5; dest:x3; op1val:0x7922; op2val:0x7922;
   valaddr_reg:x16; val_offset:12*FLEN/8; rmval:dyn; fcsr: 96;
   correctval:??; testreg:x10*/
TEST_FPRR_OP(fsub.h, x3, x4, x5, dyn, 96, 0, x16, 12*FLEN/8, x20, x8, x10)

inst_20:
// rs1==x14, rs2==x15, rd==x13,fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ef and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ef and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x14; op2:x15; dest:x13; op1val:0x7bef; op2val:0x7bef;
   valaddr_reg:x16; val_offset:14*FLEN/8; rmval:dyn; fcsr: 96;
   correctval:??; testreg:x10*/
TEST_FPRR_OP(fsub.h, x13, x14, x15, dyn, 96, 0, x16, 14*FLEN/8, x20, x8, x10)

inst_21:
// rs1==x29, rs2==x12, rd==x27,fs1 == 0 and fe1 == 0x1b and fm1 == 0x3bb and fs2 == 0 and fe2 == 0x1b and fm2 == 0x3bb and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x29; op2:x12; dest:x27; op1val:0x6fbb; op2val:0x6fbb;
   valaddr_reg:x16; val_offset:16*FLEN/8; rmval:dyn; fcsr: 96;
   correctval:??; testreg:x10*/
TEST_FPRR_OP(fsub.h, x27, x29, x12, dyn, 96, 0, x16, 16*FLEN/8, x20, x8, x10)

inst_22:
// rs1==x18, rs2==x26, rd==x23,fs1 == 0 and fe1 == 0x1e and fm1 == 0x1c4 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x1c4 and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x18; op2:x26; dest:x23; op1val:0x79c4; op2val:0x79c4;
   valaddr_reg:x16; val_offset:18*FLEN/8; rmval:dyn; fcsr: 96;
   correctval:??; testreg:x10*/
TEST_FPRR_OP(fsub.h, x23, x18, x26, dyn, 96, 0, x16, 18*FLEN/8, x20, x8, x10)

inst_23:
// rs1==x22, rs2==x30, rd==x17,fs1 == 0 and fe1 == 0x1e and fm1 == 0x37c and fs2 == 0 and fe2 == 0x1e and fm2 == 0x37c and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x22; op2:x30; dest:x17; op1val:0x7b7c; op2val:0x7b7c;
   valaddr_reg:x16; val_offset:20*FLEN/8; rmval:dyn; fcsr: 96;
   correctval:??; testreg:x10*/
TEST_FPRR_OP(fsub.h, x17, x22, x30, dyn, 96, 0, x16, 20*FLEN/8, x20, x8, x10)
RVTEST_VALBASEUPD(x6,test_dataset_2)

inst_24:
// rs1==x20, rs2==x22, rd==x19,fs1 == 0 and fe1 == 0x1e and fm1 == 0x2a3 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x2a3 and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x20; op2:x22; dest:x19; op1val:0x7aa3; op2val:0x7aa3;
   valaddr_reg:x6; val_offset:0*FLEN/8; rmval:dyn; fcsr: 96;
   correctval:??; testreg:x10*/
TEST_FPRR_OP(fsub.h, x19, x20, x22, dyn, 96, 0, x6, 0*FLEN/8, x7, x8, x10)

inst_25:
// rs1==x11, rs2==x24, rd==x28,fs1 == 0 and fe1 == 0x1d and fm1 == 0x0da and fs2 == 0 and fe2 == 0x1d and fm2 == 0x0da and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x11; op2:x24; dest:x28; op1val:0x74da; op2val:0x74da;
   valaddr_reg:x6; val_offset:2*FLEN/8; rmval:dyn; fcsr: 96;
   correctval:??; testreg:x4*/
TEST_FPRR_OP(fsub.h, x28, x11, x24, dyn, 96, 0, x6, 2*FLEN/8, x7, x8, x4)
RVTEST_SIGBASE(x2,signature_x2_2)

inst_26:
// rs1==x0, rs2==x17, rd==x31,fs1 == 0 and fe1 == 0x1e and fm1 == 0x30e and fs2 == 0 and fe2 == 0x1e and fm2 == 0x30e and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x0; op2:x17; dest:x31; op1val:0x0; op2val:0x7b0e;
   valaddr_reg:x6; val_offset:4*FLEN/8; rmval:dyn; fcsr: 96;
   correctval:??; testreg:x4*/
TEST_FPRR_OP(fsub.h, x31, x0, x17, dyn, 96, 0, x6, 4*FLEN/8, x7, x2, x4)

inst_27:
// rs1==x3, rs2==x28, rd==x18,fs1 == 0 and fe1 == 0x1e and fm1 == 0x00a and fs2 == 0 and fe2 == 0x1e and fm2 == 0x00a and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x3; op2:x28; dest:x18; op1val:0x780a; op2val:0x780a;
   valaddr_reg:x6; val_offset:6*FLEN/8; rmval:dyn; fcsr: 96;
   correctval:??; testreg:x4*/
TEST_FPRR_OP(fsub.h, x18, x3, x28, dyn, 96, 0, x6, 6*FLEN/8, x7, x2, x4)

inst_28:
// rs1==x5, rs2==x21, rd==x0,fs1 == 0 and fe1 == 0x1a and fm1 == 0x06b and fs2 == 0 and fe2 == 0x1a and fm2 == 0x06b and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x5; op2:x21; dest:x0; op1val:0x686b; op2val:0x686b;
   valaddr_reg:x6; val_offset:8*FLEN/8; rmval:dyn; fcsr: 96;
   correctval:??; testreg:x4*/
TEST_FPRR_OP(fsub.h, x0, x5, x21, dyn, 96, 0, x6, 8*FLEN/8, x7, x2, x4)

inst_29:
// rs1==x16, rs2==x25, rd==x5,fs1 == 0 and fe1 == 0x1e and fm1 == 0x260 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x260 and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x16; op2:x25; dest:x5; op1val:0x7a60; op2val:0x7a60;
   valaddr_reg:x6; val_offset:10*FLEN/8; rmval:dyn; fcsr: 96;
   correctval:??; testreg:x4*/
TEST_FPRR_OP(fsub.h, x5, x16, x25, dyn, 96, 0, x6, 10*FLEN/8, x7, x2, x4)

inst_30:
// rs1==x13, rs2==x20, rd==x25,fs1 == 0 and fe1 == 0x1c and fm1 == 0x188 and fs2 == 0 and fe2 == 0x1c and fm2 == 0x188 and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x13; op2:x20; dest:x25; op1val:0x7188; op2val:0x7188;
   valaddr_reg:x6; val_offset:12*FLEN/8; rmval:dyn; fcsr: 96;
   correctval:??; testreg:x4*/
TEST_FPRR_OP(fsub.h, x25, x13, x20, dyn, 96, 0, x6, 12*FLEN/8, x7, x2, x4)

inst_31:
// rs1==x1, rs2==x19, rd==x21,fs1 == 0 and fe1 == 0x1e and fm1 == 0x19f and fs2 == 0 and fe2 == 0x1e and fm2 == 0x19f and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x1; op2:x19; dest:x21; op1val:0x799f; op2val:0x799f;
   valaddr_reg:x6; val_offset:14*FLEN/8; rmval:dyn; fcsr: 96;
   correctval:??; testreg:x4*/
TEST_FPRR_OP(fsub.h, x21, x1, x19, dyn, 96, 0, x6, 14*FLEN/8, x7, x2, x4)

inst_32:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x1fe and fs2 == 0 and fe2 == 0x1d and fm2 == 0x1fe and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x75fe; op2val:0x75fe;
   valaddr_reg:x6; val_offset:16*FLEN/8; rmval:dyn; fcsr: 96;
   correctval:??; testreg:x4*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 96, 0, x6, 16*FLEN/8, x7, x2, x4)

inst_33:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x010 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x010 and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7810; op2val:0x7810;
   valaddr_reg:x6; val_offset:18*FLEN/8; rmval:dyn; fcsr: 96;
   correctval:??; testreg:x4*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 96, 0, x6, 18*FLEN/8, x7, x2, x4)

inst_34:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x02a and fs2 == 0 and fe2 == 0x1e and fm2 == 0x02a and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x782a; op2val:0x782a;
   valaddr_reg:x6; val_offset:20*FLEN/8; rmval:dyn; fcsr: 96;
   correctval:??; testreg:x4*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 96, 0, x6, 20*FLEN/8, x7, x2, x4)

inst_35:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x3d4 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x3d4 and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x77d4; op2val:0x77d4;
   valaddr_reg:x6; val_offset:22*FLEN/8; rmval:dyn; fcsr: 96;
   correctval:??; testreg:x4*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 96, 0, x6, 22*FLEN/8, x7, x2, x4)

inst_36:
// fs1 == 0 and fe1 == 0x1a and fm1 == 0x190 and fs2 == 0 and fe2 == 0x1a and fm2 == 0x190 and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x6990; op2val:0x6990;
   valaddr_reg:x6; val_offset:24*FLEN/8; rmval:dyn; fcsr: 96;
   correctval:??; testreg:x4*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 96, 0, x6, 24*FLEN/8, x7, x2, x4)

inst_37:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3dc and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3dc and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bdc; op2val:0x7bdc;
   valaddr_reg:x6; val_offset:26*FLEN/8; rmval:dyn; fcsr: 96;
   correctval:??; testreg:x4*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 96, 0, x6, 26*FLEN/8, x7, x2, x4)

inst_38:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x24b and fs2 == 0 and fe2 == 0x1d and fm2 == 0x24b and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x764b; op2val:0x764b;
   valaddr_reg:x6; val_offset:28*FLEN/8; rmval:dyn; fcsr: 96;
   correctval:??; testreg:x4*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 96, 0, x6, 28*FLEN/8, x7, x2, x4)

inst_39:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x004 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x004 and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7804; op2val:0x7804;
   valaddr_reg:x6; val_offset:30*FLEN/8; rmval:dyn; fcsr: 96;
   correctval:??; testreg:x4*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 96, 0, x6, 30*FLEN/8, x7, x2, x4)

inst_40:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x229 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x229 and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7a29; op2val:0x7a29;
   valaddr_reg:x6; val_offset:32*FLEN/8; rmval:dyn; fcsr: 96;
   correctval:??; testreg:x4*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 96, 0, x6, 32*FLEN/8, x7, x2, x4)

inst_41:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2e1 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x2e1 and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7ae1; op2val:0x7ae1;
   valaddr_reg:x6; val_offset:34*FLEN/8; rmval:dyn; fcsr: 96;
   correctval:??; testreg:x4*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 96, 0, x6, 34*FLEN/8, x7, x2, x4)

inst_42:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x01b and fs2 == 0 and fe2 == 0x1e and fm2 == 0x019 and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x781b; op2val:0x7819;
   valaddr_reg:x6; val_offset:36*FLEN/8; rmval:dyn; fcsr: 96;
   correctval:??; testreg:x4*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 96, 0, x6, 36*FLEN/8, x7, x2, x4)

inst_43:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x09e and fs2 == 0 and fe2 == 0x1e and fm2 == 0x09c and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x789e; op2val:0x789c;
   valaddr_reg:x6; val_offset:38*FLEN/8; rmval:dyn; fcsr: 96;
   correctval:??; testreg:x4*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 96, 0, x6, 38*FLEN/8, x7, x2, x4)

inst_44:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x04e and fs2 == 0 and fe2 == 0x1d and fm2 == 0x04a and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x744e; op2val:0x744a;
   valaddr_reg:x6; val_offset:40*FLEN/8; rmval:dyn; fcsr: 96;
   correctval:??; testreg:x4*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 96, 0, x6, 40*FLEN/8, x7, x2, x4)

inst_45:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3a7 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3a5 and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7ba7; op2val:0x7ba5;
   valaddr_reg:x6; val_offset:42*FLEN/8; rmval:dyn; fcsr: 96;
   correctval:??; testreg:x4*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 96, 0, x6, 42*FLEN/8, x7, x2, x4)

inst_46:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x244 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x242 and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7a44; op2val:0x7a42;
   valaddr_reg:x6; val_offset:44*FLEN/8; rmval:dyn; fcsr: 96;
   correctval:??; testreg:x4*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 96, 0, x6, 44*FLEN/8, x7, x2, x4)

inst_47:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x316 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x314 and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7b16; op2val:0x7b14;
   valaddr_reg:x6; val_offset:46*FLEN/8; rmval:dyn; fcsr: 96;
   correctval:??; testreg:x4*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 96, 0, x6, 46*FLEN/8, x7, x2, x4)

inst_48:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x278 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x276 and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7a78; op2val:0x7a76;
   valaddr_reg:x6; val_offset:48*FLEN/8; rmval:dyn; fcsr: 96;
   correctval:??; testreg:x4*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 96, 0, x6, 48*FLEN/8, x7, x2, x4)

inst_49:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x07d and fs2 == 0 and fe2 == 0x1e and fm2 == 0x07d and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x787d; op2val:0x787d;
   valaddr_reg:x6; val_offset:50*FLEN/8; rmval:dyn; fcsr: 96;
   correctval:??; testreg:x4*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 96, 0, x6, 50*FLEN/8, x7, x2, x4)

inst_50:
// fs1 == 0 and fe1 == 0x1a and fm1 == 0x32e and fs2 == 0 and fe2 == 0x1a and fm2 == 0x32e and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x6b2e; op2val:0x6b2e;
   valaddr_reg:x6; val_offset:52*FLEN/8; rmval:dyn; fcsr: 96;
   correctval:??; testreg:x4*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 96, 0, x6, 52*FLEN/8, x7, x2, x4)

inst_51:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x08e and fs2 == 0 and fe2 == 0x1e and fm2 == 0x08e and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x788e; op2val:0x788e;
   valaddr_reg:x6; val_offset:54*FLEN/8; rmval:dyn; fcsr: 96;
   correctval:??; testreg:x4*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 96, 0, x6, 54*FLEN/8, x7, x2, x4)

inst_52:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x009 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x009 and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7809; op2val:0x7809;
   valaddr_reg:x6; val_offset:56*FLEN/8; rmval:dyn; fcsr: 96;
   correctval:??; testreg:x4*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 96, 0, x6, 56*FLEN/8, x7, x2, x4)

inst_53:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x1b4 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x1b4 and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x75b4; op2val:0x75b4;
   valaddr_reg:x6; val_offset:58*FLEN/8; rmval:dyn; fcsr: 96;
   correctval:??; testreg:x4*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 96, 0, x6, 58*FLEN/8, x7, x2, x4)

inst_54:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x04e and fs2 == 0 and fe2 == 0x1e and fm2 == 0x04e and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x784e; op2val:0x784e;
   valaddr_reg:x6; val_offset:60*FLEN/8; rmval:dyn; fcsr: 96;
   correctval:??; testreg:x4*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 96, 0, x6, 60*FLEN/8, x7, x2, x4)

inst_55:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0e5 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x0e5 and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x78e5; op2val:0x78e5;
   valaddr_reg:x6; val_offset:62*FLEN/8; rmval:dyn; fcsr: 96;
   correctval:??; testreg:x4*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 96, 0, x6, 62*FLEN/8, x7, x2, x4)

inst_56:
// fs1 == 0 and fe1 == 0x1c and fm1 == 0x04c and fs2 == 0 and fe2 == 0x1c and fm2 == 0x04c and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x704c; op2val:0x704c;
   valaddr_reg:x6; val_offset:64*FLEN/8; rmval:dyn; fcsr: 96;
   correctval:??; testreg:x4*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 96, 0, x6, 64*FLEN/8, x7, x2, x4)

inst_57:
// fs1 == 0 and fe1 == 0x1b and fm1 == 0x201 and fs2 == 0 and fe2 == 0x1b and fm2 == 0x201 and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x6e01; op2val:0x6e01;
   valaddr_reg:x6; val_offset:66*FLEN/8; rmval:dyn; fcsr: 96;
   correctval:??; testreg:x4*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 96, 0, x6, 66*FLEN/8, x7, x2, x4)

inst_58:
// fs1 == 0 and fe1 == 0x1c and fm1 == 0x351 and fs2 == 0 and fe2 == 0x1c and fm2 == 0x351 and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7351; op2val:0x7351;
   valaddr_reg:x6; val_offset:68*FLEN/8; rmval:dyn; fcsr: 96;
   correctval:??; testreg:x4*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 96, 0, x6, 68*FLEN/8, x7, x2, x4)

inst_59:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x30e and fs2 == 0 and fe2 == 0x1e and fm2 == 0x30e and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7b0e; op2val:0x7b0e;
   valaddr_reg:x6; val_offset:70*FLEN/8; rmval:dyn; fcsr: 96;
   correctval:??; testreg:x4*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 96, 0, x6, 70*FLEN/8, x7, x2, x4)

inst_60:
// fs1 == 0 and fe1 == 0x1a and fm1 == 0x06b and fs2 == 0 and fe2 == 0x1a and fm2 == 0x06b and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x686b; op2val:0x686b;
   valaddr_reg:x6; val_offset:72*FLEN/8; rmval:dyn; fcsr: 96;
   correctval:??; testreg:x4*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 96, 0, x6, 72*FLEN/8, x7, x2, x4)
#endif


RVTEST_CODE_END
RVMODEL_HALT

RVTEST_DATA_BEGIN
.align 4
rvtest_data:
.word 0xbabecafe
.word 0xabecafeb
.word 0xbecafeba
.word 0xecafebab
test_dataset_0:
NAN_BOXED(28748,32,FLEN)
NAN_BOXED(28748,32,FLEN)
NAN_BOXED(31259,32,FLEN)
NAN_BOXED(31259,32,FLEN)
NAN_BOXED(30700,32,FLEN)
NAN_BOXED(30700,32,FLEN)
NAN_BOXED(31029,32,FLEN)
NAN_BOXED(31029,32,FLEN)
NAN_BOXED(28161,32,FLEN)
NAN_BOXED(28161,32,FLEN)
NAN_BOXED(31406,32,FLEN)
NAN_BOXED(31406,32,FLEN)
NAN_BOXED(31256,32,FLEN)
NAN_BOXED(31256,32,FLEN)
NAN_BOXED(30495,32,FLEN)
NAN_BOXED(30495,32,FLEN)
NAN_BOXED(29521,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(31541,32,FLEN)
NAN_BOXED(31541,32,FLEN)
NAN_BOXED(26243,32,FLEN)
NAN_BOXED(26243,32,FLEN)
NAN_BOXED(31618,32,FLEN)
NAN_BOXED(31618,32,FLEN)
NAN_BOXED(29421,32,FLEN)
NAN_BOXED(29421,32,FLEN)
test_dataset_1:
NAN_BOXED(26479,32,FLEN)
NAN_BOXED(26479,32,FLEN)
NAN_BOXED(30464,32,FLEN)
NAN_BOXED(30464,32,FLEN)
NAN_BOXED(29556,32,FLEN)
NAN_BOXED(29556,32,FLEN)
NAN_BOXED(29439,32,FLEN)
NAN_BOXED(29439,32,FLEN)
NAN_BOXED(29858,32,FLEN)
NAN_BOXED(29858,32,FLEN)
NAN_BOXED(31410,32,FLEN)
NAN_BOXED(31410,32,FLEN)
NAN_BOXED(31010,32,FLEN)
NAN_BOXED(31010,32,FLEN)
NAN_BOXED(31727,32,FLEN)
NAN_BOXED(31727,32,FLEN)
NAN_BOXED(28603,32,FLEN)
NAN_BOXED(28603,32,FLEN)
NAN_BOXED(31172,32,FLEN)
NAN_BOXED(31172,32,FLEN)
NAN_BOXED(31612,32,FLEN)
NAN_BOXED(31612,32,FLEN)
test_dataset_2:
NAN_BOXED(31395,16,FLEN)
NAN_BOXED(31395,16,FLEN)
NAN_BOXED(29914,16,FLEN)
NAN_BOXED(29914,16,FLEN)
NAN_BOXED(0,16,FLEN)
NAN_BOXED(31502,16,FLEN)
NAN_BOXED(30730,16,FLEN)
NAN_BOXED(30730,16,FLEN)
NAN_BOXED(26731,16,FLEN)
NAN_BOXED(26731,16,FLEN)
NAN_BOXED(31328,16,FLEN)
NAN_BOXED(31328,16,FLEN)
NAN_BOXED(29064,16,FLEN)
NAN_BOXED(29064,16,FLEN)
NAN_BOXED(31135,16,FLEN)
NAN_BOXED(31135,16,FLEN)
NAN_BOXED(30206,16,FLEN)
NAN_BOXED(30206,16,FLEN)
NAN_BOXED(30736,16,FLEN)
NAN_BOXED(30736,16,FLEN)
NAN_BOXED(30762,16,FLEN)
NAN_BOXED(30762,16,FLEN)
NAN_BOXED(30676,16,FLEN)
NAN_BOXED(30676,16,FLEN)
NAN_BOXED(27024,16,FLEN)
NAN_BOXED(27024,16,FLEN)
NAN_BOXED(31708,16,FLEN)
NAN_BOXED(31708,16,FLEN)
NAN_BOXED(30283,16,FLEN)
NAN_BOXED(30283,16,FLEN)
NAN_BOXED(30724,16,FLEN)
NAN_BOXED(30724,16,FLEN)
NAN_BOXED(31273,16,FLEN)
NAN_BOXED(31273,16,FLEN)
NAN_BOXED(31457,16,FLEN)
NAN_BOXED(31457,16,FLEN)
NAN_BOXED(30747,16,FLEN)
NAN_BOXED(30745,16,FLEN)
NAN_BOXED(30878,16,FLEN)
NAN_BOXED(30876,16,FLEN)
NAN_BOXED(29774,16,FLEN)
NAN_BOXED(29770,16,FLEN)
NAN_BOXED(31655,16,FLEN)
NAN_BOXED(31653,16,FLEN)
NAN_BOXED(31300,16,FLEN)
NAN_BOXED(31298,16,FLEN)
NAN_BOXED(31510,16,FLEN)
NAN_BOXED(31508,16,FLEN)
NAN_BOXED(31352,16,FLEN)
NAN_BOXED(31350,16,FLEN)
NAN_BOXED(30845,16,FLEN)
NAN_BOXED(30845,16,FLEN)
NAN_BOXED(27438,16,FLEN)
NAN_BOXED(27438,16,FLEN)
NAN_BOXED(30862,16,FLEN)
NAN_BOXED(30862,16,FLEN)
NAN_BOXED(30729,16,FLEN)
NAN_BOXED(30729,16,FLEN)
NAN_BOXED(30132,16,FLEN)
NAN_BOXED(30132,16,FLEN)
NAN_BOXED(30798,16,FLEN)
NAN_BOXED(30798,16,FLEN)
NAN_BOXED(30949,16,FLEN)
NAN_BOXED(30949,16,FLEN)
NAN_BOXED(28748,16,FLEN)
NAN_BOXED(28748,16,FLEN)
NAN_BOXED(28161,16,FLEN)
NAN_BOXED(28161,16,FLEN)
NAN_BOXED(29521,16,FLEN)
NAN_BOXED(29521,16,FLEN)
NAN_BOXED(31502,16,FLEN)
NAN_BOXED(31502,16,FLEN)
NAN_BOXED(26731,16,FLEN)
NAN_BOXED(26731,16,FLEN)
RVTEST_DATA_END

RVMODEL_DATA_BEGIN
rvtest_sig_begin:
sig_begin_canary:
CANARY;



signature_x2_0:
    .fill 0*((SIGALIGN)/4),4,0xdeadbeef


signature_x2_1:
    .fill 30*((SIGALIGN)/4),4,0xdeadbeef


signature_x8_0:
    .fill 22*((SIGALIGN)/4),4,0xdeadbeef


signature_x2_2:
    .fill 70*((SIGALIGN)/4),4,0xdeadbeef

#ifdef rvtest_mtrap_routine
tsig_begin_canary:
CANARY;

mtrap_sigptr:
    .fill 64*XLEN/32,4,0xdeadbeef

tsig_end_canary:
CANARY;
#endif

#ifdef rvtest_gpr_save

gpr_save:
    .fill 32*XLEN/32,4,0xdeadbeef

#endif


sig_end_canary:
CANARY;
rvtest_sig_end:
RVMODEL_DATA_END
