//
// Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24)
//
//
//
//
// Ports:
// Name                         I/O  size props
// master0_awvalid                O     1 reg
// master0_awid                   O     4 reg
// master0_awaddr                 O    64 reg
// master0_awlen                  O     8 reg
// master0_awsize                 O     3 reg
// master0_awburst                O     2 reg
// master0_awlock                 O     1 reg
// master0_awcache                O     4 reg
// master0_awprot                 O     3 reg
// master0_awqos                  O     4 reg
// master0_awregion               O     4 reg
// master0_wvalid                 O     1 reg
// master0_wdata                  O    64 reg
// master0_wstrb                  O     8 reg
// master0_wlast                  O     1 reg
// master0_bready                 O     1 reg
// master0_arvalid                O     1 reg
// master0_arid                   O     4 reg
// master0_araddr                 O    64 reg
// master0_arlen                  O     8 reg
// master0_arsize                 O     3 reg
// master0_arburst                O     2 reg
// master0_arlock                 O     1 reg
// master0_arcache                O     4 reg
// master0_arprot                 O     3 reg
// master0_arqos                  O     4 reg
// master0_arregion               O     4 reg
// master0_rready                 O     1 reg
// master1_awvalid                O     1 reg
// master1_awid                   O     4 reg
// master1_awaddr                 O    64 reg
// master1_awlen                  O     8 reg
// master1_awsize                 O     3 reg
// master1_awburst                O     2 reg
// master1_awlock                 O     1 reg
// master1_awcache                O     4 reg
// master1_awprot                 O     3 reg
// master1_awqos                  O     4 reg
// master1_awregion               O     4 reg
// master1_wvalid                 O     1 reg
// master1_wdata                  O    64 reg
// master1_wstrb                  O     8 reg
// master1_wlast                  O     1 reg
// master1_bready                 O     1 reg
// master1_arvalid                O     1 reg
// master1_arid                   O     4 reg
// master1_araddr                 O    64 reg
// master1_arlen                  O     8 reg
// master1_arsize                 O     3 reg
// master1_arburst                O     2 reg
// master1_arlock                 O     1 reg
// master1_arcache                O     4 reg
// master1_arprot                 O     3 reg
// master1_arqos                  O     4 reg
// master1_arregion               O     4 reg
// master1_rready                 O     1 reg
// tv_verifier_info_tx_tvalid     O     1 reg
// tv_verifier_info_tx_tdata      O   608 reg
// tv_verifier_info_tx_tstrb      O    76 reg
// tv_verifier_info_tx_tkeep      O    76 reg
// tv_verifier_info_tx_tlast      O     1 reg
// jtag_tdo                       O     1
// CLK_jtag_tclk_out              O     1 clock
// CLK_GATE_jtag_tclk_out         O     1 const
// CLK                            I     1 clock
// RST_N                          I     1 reset
// master0_awready                I     1
// master0_wready                 I     1
// master0_bvalid                 I     1
// master0_bid                    I     4 reg
// master0_bresp                  I     2 reg
// master0_arready                I     1
// master0_rvalid                 I     1
// master0_rid                    I     4 reg
// master0_rdata                  I    64 reg
// master0_rresp                  I     2 reg
// master0_rlast                  I     1 reg
// master1_awready                I     1
// master1_wready                 I     1
// master1_bvalid                 I     1
// master1_bid                    I     4 reg
// master1_bresp                  I     2 reg
// master1_arready                I     1
// master1_rvalid                 I     1
// master1_rid                    I     4 reg
// master1_rdata                  I    64 reg
// master1_rresp                  I     2 reg
// master1_rlast                  I     1 reg
// cpu_external_interrupt_req     I    16
// tv_verifier_info_tx_tready     I     1
// jtag_tdi                       I     1
// jtag_tms                       I     1
// jtag_tclk                      I     1
//
// No combinational paths from inputs to outputs
//
//

`ifdef BSV_ASSIGNMENT_DELAY
`else
  `define BSV_ASSIGNMENT_DELAY
`endif

`ifdef BSV_POSITIVE_RESET
  `define BSV_RESET_VALUE 1'b1
  `define BSV_RESET_EDGE posedge
`else
  `define BSV_RESET_VALUE 1'b0
  `define BSV_RESET_EDGE negedge
`endif

module mkP1_Core(CLK,
		 RST_N,

		 master0_awvalid,

		 master0_awid,

		 master0_awaddr,

		 master0_awlen,

		 master0_awsize,

		 master0_awburst,

		 master0_awlock,

		 master0_awcache,

		 master0_awprot,

		 master0_awqos,

		 master0_awregion,

		 master0_awready,

		 master0_wvalid,

		 master0_wdata,

		 master0_wstrb,

		 master0_wlast,

		 master0_wready,

		 master0_bvalid,
		 master0_bid,
		 master0_bresp,

		 master0_bready,

		 master0_arvalid,

		 master0_arid,

		 master0_araddr,

		 master0_arlen,

		 master0_arsize,

		 master0_arburst,

		 master0_arlock,

		 master0_arcache,

		 master0_arprot,

		 master0_arqos,

		 master0_arregion,

		 master0_arready,

		 master0_rvalid,
		 master0_rid,
		 master0_rdata,
		 master0_rresp,
		 master0_rlast,

		 master0_rready,

		 master1_awvalid,

		 master1_awid,

		 master1_awaddr,

		 master1_awlen,

		 master1_awsize,

		 master1_awburst,

		 master1_awlock,

		 master1_awcache,

		 master1_awprot,

		 master1_awqos,

		 master1_awregion,

		 master1_awready,

		 master1_wvalid,

		 master1_wdata,

		 master1_wstrb,

		 master1_wlast,

		 master1_wready,

		 master1_bvalid,
		 master1_bid,
		 master1_bresp,

		 master1_bready,

		 master1_arvalid,

		 master1_arid,

		 master1_araddr,

		 master1_arlen,

		 master1_arsize,

		 master1_arburst,

		 master1_arlock,

		 master1_arcache,

		 master1_arprot,

		 master1_arqos,

		 master1_arregion,

		 master1_arready,

		 master1_rvalid,
		 master1_rid,
		 master1_rdata,
		 master1_rresp,
		 master1_rlast,

		 master1_rready,

		 cpu_external_interrupt_req,

		 tv_verifier_info_tx_tvalid,

		 tv_verifier_info_tx_tdata,

		 tv_verifier_info_tx_tstrb,

		 tv_verifier_info_tx_tkeep,

		 tv_verifier_info_tx_tlast,

		 tv_verifier_info_tx_tready,

		 jtag_tdi,

		 jtag_tms,

		 jtag_tclk,

		 jtag_tdo,

		 CLK_jtag_tclk_out,
		 CLK_GATE_jtag_tclk_out);
  input  CLK;
  input  RST_N;

  // value method master0_m_awvalid
  output master0_awvalid;

  // value method master0_m_awid
  output [3 : 0] master0_awid;

  // value method master0_m_awaddr
  output [63 : 0] master0_awaddr;

  // value method master0_m_awlen
  output [7 : 0] master0_awlen;

  // value method master0_m_awsize
  output [2 : 0] master0_awsize;

  // value method master0_m_awburst
  output [1 : 0] master0_awburst;

  // value method master0_m_awlock
  output master0_awlock;

  // value method master0_m_awcache
  output [3 : 0] master0_awcache;

  // value method master0_m_awprot
  output [2 : 0] master0_awprot;

  // value method master0_m_awqos
  output [3 : 0] master0_awqos;

  // value method master0_m_awregion
  output [3 : 0] master0_awregion;

  // value method master0_m_awuser

  // action method master0_m_awready
  input  master0_awready;

  // value method master0_m_wvalid
  output master0_wvalid;

  // value method master0_m_wdata
  output [63 : 0] master0_wdata;

  // value method master0_m_wstrb
  output [7 : 0] master0_wstrb;

  // value method master0_m_wlast
  output master0_wlast;

  // value method master0_m_wuser

  // action method master0_m_wready
  input  master0_wready;

  // action method master0_m_bvalid
  input  master0_bvalid;
  input  [3 : 0] master0_bid;
  input  [1 : 0] master0_bresp;

  // value method master0_m_bready
  output master0_bready;

  // value method master0_m_arvalid
  output master0_arvalid;

  // value method master0_m_arid
  output [3 : 0] master0_arid;

  // value method master0_m_araddr
  output [63 : 0] master0_araddr;

  // value method master0_m_arlen
  output [7 : 0] master0_arlen;

  // value method master0_m_arsize
  output [2 : 0] master0_arsize;

  // value method master0_m_arburst
  output [1 : 0] master0_arburst;

  // value method master0_m_arlock
  output master0_arlock;

  // value method master0_m_arcache
  output [3 : 0] master0_arcache;

  // value method master0_m_arprot
  output [2 : 0] master0_arprot;

  // value method master0_m_arqos
  output [3 : 0] master0_arqos;

  // value method master0_m_arregion
  output [3 : 0] master0_arregion;

  // value method master0_m_aruser

  // action method master0_m_arready
  input  master0_arready;

  // action method master0_m_rvalid
  input  master0_rvalid;
  input  [3 : 0] master0_rid;
  input  [63 : 0] master0_rdata;
  input  [1 : 0] master0_rresp;
  input  master0_rlast;

  // value method master0_m_rready
  output master0_rready;

  // value method master1_m_awvalid
  output master1_awvalid;

  // value method master1_m_awid
  output [3 : 0] master1_awid;

  // value method master1_m_awaddr
  output [63 : 0] master1_awaddr;

  // value method master1_m_awlen
  output [7 : 0] master1_awlen;

  // value method master1_m_awsize
  output [2 : 0] master1_awsize;

  // value method master1_m_awburst
  output [1 : 0] master1_awburst;

  // value method master1_m_awlock
  output master1_awlock;

  // value method master1_m_awcache
  output [3 : 0] master1_awcache;

  // value method master1_m_awprot
  output [2 : 0] master1_awprot;

  // value method master1_m_awqos
  output [3 : 0] master1_awqos;

  // value method master1_m_awregion
  output [3 : 0] master1_awregion;

  // value method master1_m_awuser

  // action method master1_m_awready
  input  master1_awready;

  // value method master1_m_wvalid
  output master1_wvalid;

  // value method master1_m_wdata
  output [63 : 0] master1_wdata;

  // value method master1_m_wstrb
  output [7 : 0] master1_wstrb;

  // value method master1_m_wlast
  output master1_wlast;

  // value method master1_m_wuser

  // action method master1_m_wready
  input  master1_wready;

  // action method master1_m_bvalid
  input  master1_bvalid;
  input  [3 : 0] master1_bid;
  input  [1 : 0] master1_bresp;

  // value method master1_m_bready
  output master1_bready;

  // value method master1_m_arvalid
  output master1_arvalid;

  // value method master1_m_arid
  output [3 : 0] master1_arid;

  // value method master1_m_araddr
  output [63 : 0] master1_araddr;

  // value method master1_m_arlen
  output [7 : 0] master1_arlen;

  // value method master1_m_arsize
  output [2 : 0] master1_arsize;

  // value method master1_m_arburst
  output [1 : 0] master1_arburst;

  // value method master1_m_arlock
  output master1_arlock;

  // value method master1_m_arcache
  output [3 : 0] master1_arcache;

  // value method master1_m_arprot
  output [2 : 0] master1_arprot;

  // value method master1_m_arqos
  output [3 : 0] master1_arqos;

  // value method master1_m_arregion
  output [3 : 0] master1_arregion;

  // value method master1_m_aruser

  // action method master1_m_arready
  input  master1_arready;

  // action method master1_m_rvalid
  input  master1_rvalid;
  input  [3 : 0] master1_rid;
  input  [63 : 0] master1_rdata;
  input  [1 : 0] master1_rresp;
  input  master1_rlast;

  // value method master1_m_rready
  output master1_rready;

  // action method interrupt_reqs
  input  [15 : 0] cpu_external_interrupt_req;

  // value method tv_verifier_info_tx_m_tvalid
  output tv_verifier_info_tx_tvalid;

  // value method tv_verifier_info_tx_m_tid

  // value method tv_verifier_info_tx_m_tdata
  output [607 : 0] tv_verifier_info_tx_tdata;

  // value method tv_verifier_info_tx_m_tstrb
  output [75 : 0] tv_verifier_info_tx_tstrb;

  // value method tv_verifier_info_tx_m_tkeep
  output [75 : 0] tv_verifier_info_tx_tkeep;

  // value method tv_verifier_info_tx_m_tlast
  output tv_verifier_info_tx_tlast;

  // value method tv_verifier_info_tx_m_tdest

  // value method tv_verifier_info_tx_m_tuser

  // action method tv_verifier_info_tx_m_tready
  input  tv_verifier_info_tx_tready;

  // action method jtag_tdi
  input  jtag_tdi;

  // action method jtag_tms
  input  jtag_tms;

  // action method jtag_tclk
  input  jtag_tclk;

  // value method jtag_tdo
  output jtag_tdo;

  // oscillator and gates for output clock CLK_jtag_tclk_out
  output CLK_jtag_tclk_out;
  output CLK_GATE_jtag_tclk_out;

  // signals for module outputs
  wire [607 : 0] tv_verifier_info_tx_tdata;
  wire [75 : 0] tv_verifier_info_tx_tkeep, tv_verifier_info_tx_tstrb;
  wire [63 : 0] master0_araddr,
		master0_awaddr,
		master0_wdata,
		master1_araddr,
		master1_awaddr,
		master1_wdata;
  wire [7 : 0] master0_arlen,
	       master0_awlen,
	       master0_wstrb,
	       master1_arlen,
	       master1_awlen,
	       master1_wstrb;
  wire [3 : 0] master0_arcache,
	       master0_arid,
	       master0_arqos,
	       master0_arregion,
	       master0_awcache,
	       master0_awid,
	       master0_awqos,
	       master0_awregion,
	       master1_arcache,
	       master1_arid,
	       master1_arqos,
	       master1_arregion,
	       master1_awcache,
	       master1_awid,
	       master1_awqos,
	       master1_awregion;
  wire [2 : 0] master0_arprot,
	       master0_arsize,
	       master0_awprot,
	       master0_awsize,
	       master1_arprot,
	       master1_arsize,
	       master1_awprot,
	       master1_awsize;
  wire [1 : 0] master0_arburst,
	       master0_awburst,
	       master1_arburst,
	       master1_awburst;
  wire CLK_GATE_jtag_tclk_out,
       CLK_jtag_tclk_out,
       jtag_tdo,
       master0_arlock,
       master0_arvalid,
       master0_awlock,
       master0_awvalid,
       master0_bready,
       master0_rready,
       master0_wlast,
       master0_wvalid,
       master1_arlock,
       master1_arvalid,
       master1_awlock,
       master1_awvalid,
       master1_bready,
       master1_rready,
       master1_wlast,
       master1_wvalid,
       tv_verifier_info_tx_tlast,
       tv_verifier_info_tx_tvalid;

  // inlined wires
  wire [40 : 0] bus_dmi_req_data_wire$wget;
  wire bus_dmi_rsp_fifof_enqueueing$whas;

  // register bus_dmi_rsp_fifof_cntr_r
  reg [1 : 0] bus_dmi_rsp_fifof_cntr_r;
  wire [1 : 0] bus_dmi_rsp_fifof_cntr_r$D_IN;
  wire bus_dmi_rsp_fifof_cntr_r$EN;

  // register bus_dmi_rsp_fifof_q_0
  reg [33 : 0] bus_dmi_rsp_fifof_q_0;
  reg [33 : 0] bus_dmi_rsp_fifof_q_0$D_IN;
  wire bus_dmi_rsp_fifof_q_0$EN;

  // register bus_dmi_rsp_fifof_q_1
  reg [33 : 0] bus_dmi_rsp_fifof_q_1;
  reg [33 : 0] bus_dmi_rsp_fifof_q_1$D_IN;
  wire bus_dmi_rsp_fifof_q_1$EN;

  // register rg_ndm_reset
  reg [1 : 0] rg_ndm_reset;
  wire [1 : 0] rg_ndm_reset$D_IN;
  wire rg_ndm_reset$EN;

  // register rg_once
  reg rg_once;
  wire rg_once$D_IN, rg_once$EN;

  // ports of submodule bus_dmi_req_fifof
  wire [40 : 0] bus_dmi_req_fifof$D_IN, bus_dmi_req_fifof$D_OUT;
  wire bus_dmi_req_fifof$CLR,
       bus_dmi_req_fifof$DEQ,
       bus_dmi_req_fifof$EMPTY_N,
       bus_dmi_req_fifof$ENQ,
       bus_dmi_req_fifof$FULL_N;

  // ports of submodule core
  wire [607 : 0] core$tv_verifier_info_get_get;
  wire [63 : 0] core$cpu_dmem_master_araddr,
		core$cpu_dmem_master_awaddr,
		core$cpu_dmem_master_rdata,
		core$cpu_dmem_master_wdata,
		core$cpu_imem_master_araddr,
		core$cpu_imem_master_awaddr,
		core$cpu_imem_master_rdata,
		core$cpu_imem_master_wdata,
		core$set_verbosity_logdelay;
  wire [31 : 0] core$dm_dmi_read_data, core$dm_dmi_write_dm_word;
  wire [7 : 0] core$cpu_dmem_master_arlen,
	       core$cpu_dmem_master_awlen,
	       core$cpu_dmem_master_wstrb,
	       core$cpu_imem_master_arlen,
	       core$cpu_imem_master_awlen,
	       core$cpu_imem_master_wstrb;
  wire [6 : 0] core$dm_dmi_read_addr_dm_addr, core$dm_dmi_write_dm_addr;
  wire [3 : 0] core$cpu_dmem_master_arcache,
	       core$cpu_dmem_master_arid,
	       core$cpu_dmem_master_arqos,
	       core$cpu_dmem_master_arregion,
	       core$cpu_dmem_master_awcache,
	       core$cpu_dmem_master_awid,
	       core$cpu_dmem_master_awqos,
	       core$cpu_dmem_master_awregion,
	       core$cpu_dmem_master_bid,
	       core$cpu_dmem_master_rid,
	       core$cpu_imem_master_arcache,
	       core$cpu_imem_master_arid,
	       core$cpu_imem_master_arqos,
	       core$cpu_imem_master_arregion,
	       core$cpu_imem_master_awcache,
	       core$cpu_imem_master_awid,
	       core$cpu_imem_master_awqos,
	       core$cpu_imem_master_awregion,
	       core$cpu_imem_master_bid,
	       core$cpu_imem_master_rid,
	       core$set_verbosity_verbosity;
  wire [2 : 0] core$cpu_dmem_master_arprot,
	       core$cpu_dmem_master_arsize,
	       core$cpu_dmem_master_awprot,
	       core$cpu_dmem_master_awsize,
	       core$cpu_imem_master_arprot,
	       core$cpu_imem_master_arsize,
	       core$cpu_imem_master_awprot,
	       core$cpu_imem_master_awsize;
  wire [1 : 0] core$cpu_dmem_master_arburst,
	       core$cpu_dmem_master_awburst,
	       core$cpu_dmem_master_bresp,
	       core$cpu_dmem_master_rresp,
	       core$cpu_imem_master_arburst,
	       core$cpu_imem_master_awburst,
	       core$cpu_imem_master_bresp,
	       core$cpu_imem_master_rresp;
  wire core$EN_cpu_reset_server_request_put,
       core$EN_cpu_reset_server_response_get,
       core$EN_dm_dmi_read_addr,
       core$EN_dm_dmi_read_data,
       core$EN_dm_dmi_write,
       core$EN_ndm_reset_client_request_get,
       core$EN_ndm_reset_client_response_put,
       core$EN_set_verbosity,
       core$EN_tv_verifier_info_get_get,
       core$RDY_cpu_reset_server_request_put,
       core$RDY_cpu_reset_server_response_get,
       core$RDY_dm_dmi_read_addr,
       core$RDY_dm_dmi_read_data,
       core$RDY_dm_dmi_write,
       core$RDY_ndm_reset_client_request_get,
       core$RDY_ndm_reset_client_response_put,
       core$RDY_tv_verifier_info_get_get,
       core$core_external_interrupt_sources_0_m_interrupt_req_set_not_clear,
       core$core_external_interrupt_sources_10_m_interrupt_req_set_not_clear,
       core$core_external_interrupt_sources_11_m_interrupt_req_set_not_clear,
       core$core_external_interrupt_sources_12_m_interrupt_req_set_not_clear,
       core$core_external_interrupt_sources_13_m_interrupt_req_set_not_clear,
       core$core_external_interrupt_sources_14_m_interrupt_req_set_not_clear,
       core$core_external_interrupt_sources_15_m_interrupt_req_set_not_clear,
       core$core_external_interrupt_sources_1_m_interrupt_req_set_not_clear,
       core$core_external_interrupt_sources_2_m_interrupt_req_set_not_clear,
       core$core_external_interrupt_sources_3_m_interrupt_req_set_not_clear,
       core$core_external_interrupt_sources_4_m_interrupt_req_set_not_clear,
       core$core_external_interrupt_sources_5_m_interrupt_req_set_not_clear,
       core$core_external_interrupt_sources_6_m_interrupt_req_set_not_clear,
       core$core_external_interrupt_sources_7_m_interrupt_req_set_not_clear,
       core$core_external_interrupt_sources_8_m_interrupt_req_set_not_clear,
       core$core_external_interrupt_sources_9_m_interrupt_req_set_not_clear,
       core$cpu_dmem_master_arlock,
       core$cpu_dmem_master_arready,
       core$cpu_dmem_master_arvalid,
       core$cpu_dmem_master_awlock,
       core$cpu_dmem_master_awready,
       core$cpu_dmem_master_awvalid,
       core$cpu_dmem_master_bready,
       core$cpu_dmem_master_bvalid,
       core$cpu_dmem_master_rlast,
       core$cpu_dmem_master_rready,
       core$cpu_dmem_master_rvalid,
       core$cpu_dmem_master_wlast,
       core$cpu_dmem_master_wready,
       core$cpu_dmem_master_wvalid,
       core$cpu_imem_master_arlock,
       core$cpu_imem_master_arready,
       core$cpu_imem_master_arvalid,
       core$cpu_imem_master_awlock,
       core$cpu_imem_master_awready,
       core$cpu_imem_master_awvalid,
       core$cpu_imem_master_bready,
       core$cpu_imem_master_bvalid,
       core$cpu_imem_master_rlast,
       core$cpu_imem_master_rready,
       core$cpu_imem_master_rvalid,
       core$cpu_imem_master_wlast,
       core$cpu_imem_master_wready,
       core$cpu_imem_master_wvalid,
       core$cpu_reset_server_request_put,
       core$cpu_reset_server_response_get,
       core$ndm_reset_client_request_get,
       core$ndm_reset_client_response_put,
       core$nmi_req_set_not_clear;

  // ports of submodule jtagtap
  wire [31 : 0] jtagtap$dmi_req_data, jtagtap$dmi_rsp_data;
  wire [6 : 0] jtagtap$dmi_req_addr;
  wire [1 : 0] jtagtap$dmi_req_op, jtagtap$dmi_rsp_response;
  wire jtagtap$CLK_jtag_tclk_out,
       jtagtap$dmi_req_ready,
       jtagtap$dmi_req_valid,
       jtagtap$dmi_rsp_ready,
       jtagtap$dmi_rsp_valid,
       jtagtap$jtag_tclk,
       jtagtap$jtag_tdi,
       jtagtap$jtag_tdo,
       jtagtap$jtag_tms;

  // ports of submodule tv_xactor
  wire [607 : 0] tv_xactor$axi_out_tdata, tv_xactor$tv_in_put;
  wire [75 : 0] tv_xactor$axi_out_tkeep, tv_xactor$axi_out_tstrb;
  wire tv_xactor$EN_tv_in_put,
       tv_xactor$RDY_tv_in_put,
       tv_xactor$axi_out_tlast,
       tv_xactor$axi_out_tready,
       tv_xactor$axi_out_tvalid;

  // rule scheduling signals
  wire CAN_FIRE_RL_bus_dmi_req_do_enq,
       CAN_FIRE_RL_bus_dmi_rsp_do_deq,
       CAN_FIRE_RL_bus_dmi_rsp_fifof_both,
       CAN_FIRE_RL_bus_dmi_rsp_fifof_decCtr,
       CAN_FIRE_RL_bus_dmi_rsp_fifof_incCtr,
       CAN_FIRE_RL_mkConnectionGetPut,
       CAN_FIRE_RL_mkConnectionVtoAf,
       CAN_FIRE_RL_mkConnectionVtoAf_1,
       CAN_FIRE_RL_mkConnectionVtoAf_2,
       CAN_FIRE_RL_mkConnectionVtoAf_3,
       CAN_FIRE_RL_mkConnectionVtoAf_4,
       CAN_FIRE_RL_mkConnectionVtoAf_5,
       CAN_FIRE_RL_mkConnectionVtoAf_6,
       CAN_FIRE_RL_mkConnectionVtoAf_7,
       CAN_FIRE_RL_mkConnectionVtoAf_8,
       CAN_FIRE_RL_rl_always,
       CAN_FIRE_RL_rl_dmi_req,
       CAN_FIRE_RL_rl_dmi_req_cpu,
       CAN_FIRE_RL_rl_dmi_rsp,
       CAN_FIRE_RL_rl_dmi_rsp_cpu,
       CAN_FIRE_RL_rl_ndmreset,
       CAN_FIRE_RL_rl_once,
       CAN_FIRE_RL_rl_reset_response,
       CAN_FIRE_interrupt_reqs,
       CAN_FIRE_jtag_tclk,
       CAN_FIRE_jtag_tdi,
       CAN_FIRE_jtag_tms,
       CAN_FIRE_master0_m_arready,
       CAN_FIRE_master0_m_awready,
       CAN_FIRE_master0_m_bvalid,
       CAN_FIRE_master0_m_rvalid,
       CAN_FIRE_master0_m_wready,
       CAN_FIRE_master1_m_arready,
       CAN_FIRE_master1_m_awready,
       CAN_FIRE_master1_m_bvalid,
       CAN_FIRE_master1_m_rvalid,
       CAN_FIRE_master1_m_wready,
       CAN_FIRE_tv_verifier_info_tx_m_tready,
       WILL_FIRE_RL_bus_dmi_req_do_enq,
       WILL_FIRE_RL_bus_dmi_rsp_do_deq,
       WILL_FIRE_RL_bus_dmi_rsp_fifof_both,
       WILL_FIRE_RL_bus_dmi_rsp_fifof_decCtr,
       WILL_FIRE_RL_bus_dmi_rsp_fifof_incCtr,
       WILL_FIRE_RL_mkConnectionGetPut,
       WILL_FIRE_RL_mkConnectionVtoAf,
       WILL_FIRE_RL_mkConnectionVtoAf_1,
       WILL_FIRE_RL_mkConnectionVtoAf_2,
       WILL_FIRE_RL_mkConnectionVtoAf_3,
       WILL_FIRE_RL_mkConnectionVtoAf_4,
       WILL_FIRE_RL_mkConnectionVtoAf_5,
       WILL_FIRE_RL_mkConnectionVtoAf_6,
       WILL_FIRE_RL_mkConnectionVtoAf_7,
       WILL_FIRE_RL_mkConnectionVtoAf_8,
       WILL_FIRE_RL_rl_always,
       WILL_FIRE_RL_rl_dmi_req,
       WILL_FIRE_RL_rl_dmi_req_cpu,
       WILL_FIRE_RL_rl_dmi_rsp,
       WILL_FIRE_RL_rl_dmi_rsp_cpu,
       WILL_FIRE_RL_rl_ndmreset,
       WILL_FIRE_RL_rl_once,
       WILL_FIRE_RL_rl_reset_response,
       WILL_FIRE_interrupt_reqs,
       WILL_FIRE_jtag_tclk,
       WILL_FIRE_jtag_tdi,
       WILL_FIRE_jtag_tms,
       WILL_FIRE_master0_m_arready,
       WILL_FIRE_master0_m_awready,
       WILL_FIRE_master0_m_bvalid,
       WILL_FIRE_master0_m_rvalid,
       WILL_FIRE_master0_m_wready,
       WILL_FIRE_master1_m_arready,
       WILL_FIRE_master1_m_awready,
       WILL_FIRE_master1_m_bvalid,
       WILL_FIRE_master1_m_rvalid,
       WILL_FIRE_master1_m_wready,
       WILL_FIRE_tv_verifier_info_tx_m_tready;

  // inputs to muxes for submodule ports
  wire [33 : 0] MUX_bus_dmi_rsp_fifof_q_0$write_1__VAL_1,
		MUX_bus_dmi_rsp_fifof_q_0$write_1__VAL_2,
		MUX_bus_dmi_rsp_fifof_q_1$write_1__VAL_1,
		MUX_bus_dmi_rsp_fifof_x_wire$wset_1__VAL_1,
		MUX_bus_dmi_rsp_fifof_x_wire$wset_1__VAL_2;
  wire [1 : 0] MUX_bus_dmi_rsp_fifof_cntr_r$write_1__VAL_2,
	       MUX_rg_ndm_reset$write_1__VAL_1;
  wire MUX_bus_dmi_rsp_fifof_q_0$write_1__SEL_1,
       MUX_bus_dmi_rsp_fifof_q_0$write_1__SEL_2,
       MUX_bus_dmi_rsp_fifof_q_1$write_1__SEL_1,
       MUX_bus_dmi_rsp_fifof_q_1$write_1__SEL_2,
       MUX_bus_dmi_rsp_fifof_x_wire$wset_1__SEL_1;

  // remaining internal signals
  wire [1 : 0] bus_dmi_rsp_fifof_cntr_r_2_MINUS_1___d40;
  wire IF_bus_dmi_req_fifof_first__9_BITS_1_TO_0_0_EQ_ETC___d90,
       _dfoo1,
       _dfoo3;

  // oscillator and gates for output clock CLK_jtag_tclk_out
  assign CLK_jtag_tclk_out = jtagtap$CLK_jtag_tclk_out ;
  assign CLK_GATE_jtag_tclk_out = 1'b1 ;

  // value method master0_m_awvalid
  assign master0_awvalid = core$cpu_imem_master_awvalid ;

  // value method master0_m_awid
  assign master0_awid = core$cpu_imem_master_awid ;

  // value method master0_m_awaddr
  assign master0_awaddr = core$cpu_imem_master_awaddr ;

  // value method master0_m_awlen
  assign master0_awlen = core$cpu_imem_master_awlen ;

  // value method master0_m_awsize
  assign master0_awsize = core$cpu_imem_master_awsize ;

  // value method master0_m_awburst
  assign master0_awburst = core$cpu_imem_master_awburst ;

  // value method master0_m_awlock
  assign master0_awlock = core$cpu_imem_master_awlock ;

  // value method master0_m_awcache
  assign master0_awcache = core$cpu_imem_master_awcache ;

  // value method master0_m_awprot
  assign master0_awprot = core$cpu_imem_master_awprot ;

  // value method master0_m_awqos
  assign master0_awqos = core$cpu_imem_master_awqos ;

  // value method master0_m_awregion
  assign master0_awregion = core$cpu_imem_master_awregion ;

  // action method master0_m_awready
  assign CAN_FIRE_master0_m_awready = 1'd1 ;
  assign WILL_FIRE_master0_m_awready = 1'd1 ;

  // value method master0_m_wvalid
  assign master0_wvalid = core$cpu_imem_master_wvalid ;

  // value method master0_m_wdata
  assign master0_wdata = core$cpu_imem_master_wdata ;

  // value method master0_m_wstrb
  assign master0_wstrb = core$cpu_imem_master_wstrb ;

  // value method master0_m_wlast
  assign master0_wlast = core$cpu_imem_master_wlast ;

  // action method master0_m_wready
  assign CAN_FIRE_master0_m_wready = 1'd1 ;
  assign WILL_FIRE_master0_m_wready = 1'd1 ;

  // action method master0_m_bvalid
  assign CAN_FIRE_master0_m_bvalid = 1'd1 ;
  assign WILL_FIRE_master0_m_bvalid = 1'd1 ;

  // value method master0_m_bready
  assign master0_bready = core$cpu_imem_master_bready ;

  // value method master0_m_arvalid
  assign master0_arvalid = core$cpu_imem_master_arvalid ;

  // value method master0_m_arid
  assign master0_arid = core$cpu_imem_master_arid ;

  // value method master0_m_araddr
  assign master0_araddr = core$cpu_imem_master_araddr ;

  // value method master0_m_arlen
  assign master0_arlen = core$cpu_imem_master_arlen ;

  // value method master0_m_arsize
  assign master0_arsize = core$cpu_imem_master_arsize ;

  // value method master0_m_arburst
  assign master0_arburst = core$cpu_imem_master_arburst ;

  // value method master0_m_arlock
  assign master0_arlock = core$cpu_imem_master_arlock ;

  // value method master0_m_arcache
  assign master0_arcache = core$cpu_imem_master_arcache ;

  // value method master0_m_arprot
  assign master0_arprot = core$cpu_imem_master_arprot ;

  // value method master0_m_arqos
  assign master0_arqos = core$cpu_imem_master_arqos ;

  // value method master0_m_arregion
  assign master0_arregion = core$cpu_imem_master_arregion ;

  // action method master0_m_arready
  assign CAN_FIRE_master0_m_arready = 1'd1 ;
  assign WILL_FIRE_master0_m_arready = 1'd1 ;

  // action method master0_m_rvalid
  assign CAN_FIRE_master0_m_rvalid = 1'd1 ;
  assign WILL_FIRE_master0_m_rvalid = 1'd1 ;

  // value method master0_m_rready
  assign master0_rready = core$cpu_imem_master_rready ;

  // value method master1_m_awvalid
  assign master1_awvalid = core$cpu_dmem_master_awvalid ;

  // value method master1_m_awid
  assign master1_awid = core$cpu_dmem_master_awid ;

  // value method master1_m_awaddr
  assign master1_awaddr = core$cpu_dmem_master_awaddr ;

  // value method master1_m_awlen
  assign master1_awlen = core$cpu_dmem_master_awlen ;

  // value method master1_m_awsize
  assign master1_awsize = core$cpu_dmem_master_awsize ;

  // value method master1_m_awburst
  assign master1_awburst = core$cpu_dmem_master_awburst ;

  // value method master1_m_awlock
  assign master1_awlock = core$cpu_dmem_master_awlock ;

  // value method master1_m_awcache
  assign master1_awcache = core$cpu_dmem_master_awcache ;

  // value method master1_m_awprot
  assign master1_awprot = core$cpu_dmem_master_awprot ;

  // value method master1_m_awqos
  assign master1_awqos = core$cpu_dmem_master_awqos ;

  // value method master1_m_awregion
  assign master1_awregion = core$cpu_dmem_master_awregion ;

  // action method master1_m_awready
  assign CAN_FIRE_master1_m_awready = 1'd1 ;
  assign WILL_FIRE_master1_m_awready = 1'd1 ;

  // value method master1_m_wvalid
  assign master1_wvalid = core$cpu_dmem_master_wvalid ;

  // value method master1_m_wdata
  assign master1_wdata = core$cpu_dmem_master_wdata ;

  // value method master1_m_wstrb
  assign master1_wstrb = core$cpu_dmem_master_wstrb ;

  // value method master1_m_wlast
  assign master1_wlast = core$cpu_dmem_master_wlast ;

  // action method master1_m_wready
  assign CAN_FIRE_master1_m_wready = 1'd1 ;
  assign WILL_FIRE_master1_m_wready = 1'd1 ;

  // action method master1_m_bvalid
  assign CAN_FIRE_master1_m_bvalid = 1'd1 ;
  assign WILL_FIRE_master1_m_bvalid = 1'd1 ;

  // value method master1_m_bready
  assign master1_bready = core$cpu_dmem_master_bready ;

  // value method master1_m_arvalid
  assign master1_arvalid = core$cpu_dmem_master_arvalid ;

  // value method master1_m_arid
  assign master1_arid = core$cpu_dmem_master_arid ;

  // value method master1_m_araddr
  assign master1_araddr = core$cpu_dmem_master_araddr ;

  // value method master1_m_arlen
  assign master1_arlen = core$cpu_dmem_master_arlen ;

  // value method master1_m_arsize
  assign master1_arsize = core$cpu_dmem_master_arsize ;

  // value method master1_m_arburst
  assign master1_arburst = core$cpu_dmem_master_arburst ;

  // value method master1_m_arlock
  assign master1_arlock = core$cpu_dmem_master_arlock ;

  // value method master1_m_arcache
  assign master1_arcache = core$cpu_dmem_master_arcache ;

  // value method master1_m_arprot
  assign master1_arprot = core$cpu_dmem_master_arprot ;

  // value method master1_m_arqos
  assign master1_arqos = core$cpu_dmem_master_arqos ;

  // value method master1_m_arregion
  assign master1_arregion = core$cpu_dmem_master_arregion ;

  // action method master1_m_arready
  assign CAN_FIRE_master1_m_arready = 1'd1 ;
  assign WILL_FIRE_master1_m_arready = 1'd1 ;

  // action method master1_m_rvalid
  assign CAN_FIRE_master1_m_rvalid = 1'd1 ;
  assign WILL_FIRE_master1_m_rvalid = 1'd1 ;

  // value method master1_m_rready
  assign master1_rready = core$cpu_dmem_master_rready ;

  // action method interrupt_reqs
  assign CAN_FIRE_interrupt_reqs = 1'd1 ;
  assign WILL_FIRE_interrupt_reqs = 1'd1 ;

  // value method tv_verifier_info_tx_m_tvalid
  assign tv_verifier_info_tx_tvalid = tv_xactor$axi_out_tvalid ;

  // value method tv_verifier_info_tx_m_tdata
  assign tv_verifier_info_tx_tdata = tv_xactor$axi_out_tdata ;

  // value method tv_verifier_info_tx_m_tstrb
  assign tv_verifier_info_tx_tstrb = tv_xactor$axi_out_tstrb ;

  // value method tv_verifier_info_tx_m_tkeep
  assign tv_verifier_info_tx_tkeep = tv_xactor$axi_out_tkeep ;

  // value method tv_verifier_info_tx_m_tlast
  assign tv_verifier_info_tx_tlast = tv_xactor$axi_out_tlast ;

  // action method tv_verifier_info_tx_m_tready
  assign CAN_FIRE_tv_verifier_info_tx_m_tready = 1'd1 ;
  assign WILL_FIRE_tv_verifier_info_tx_m_tready = 1'd1 ;

  // action method jtag_tdi
  assign CAN_FIRE_jtag_tdi = 1'd1 ;
  assign WILL_FIRE_jtag_tdi = 1'd1 ;

  // action method jtag_tms
  assign CAN_FIRE_jtag_tms = 1'd1 ;
  assign WILL_FIRE_jtag_tms = 1'd1 ;

  // action method jtag_tclk
  assign CAN_FIRE_jtag_tclk = 1'd1 ;
  assign WILL_FIRE_jtag_tclk = 1'd1 ;

  // value method jtag_tdo
  assign jtag_tdo = jtagtap$jtag_tdo ;

  // submodule bus_dmi_req_fifof
  FIFO2 #(.width(32'd41), .guarded(32'd1)) bus_dmi_req_fifof(.RST(RST_N),
							     .CLK(CLK),
							     .D_IN(bus_dmi_req_fifof$D_IN),
							     .ENQ(bus_dmi_req_fifof$ENQ),
							     .DEQ(bus_dmi_req_fifof$DEQ),
							     .CLR(bus_dmi_req_fifof$CLR),
							     .D_OUT(bus_dmi_req_fifof$D_OUT),
							     .FULL_N(bus_dmi_req_fifof$FULL_N),
							     .EMPTY_N(bus_dmi_req_fifof$EMPTY_N));

  // submodule core
  mkCore core(.CLK(CLK),
	      .RST_N(RST_N),
	      .core_external_interrupt_sources_0_m_interrupt_req_set_not_clear(core$core_external_interrupt_sources_0_m_interrupt_req_set_not_clear),
	      .core_external_interrupt_sources_10_m_interrupt_req_set_not_clear(core$core_external_interrupt_sources_10_m_interrupt_req_set_not_clear),
	      .core_external_interrupt_sources_11_m_interrupt_req_set_not_clear(core$core_external_interrupt_sources_11_m_interrupt_req_set_not_clear),
	      .core_external_interrupt_sources_12_m_interrupt_req_set_not_clear(core$core_external_interrupt_sources_12_m_interrupt_req_set_not_clear),
	      .core_external_interrupt_sources_13_m_interrupt_req_set_not_clear(core$core_external_interrupt_sources_13_m_interrupt_req_set_not_clear),
	      .core_external_interrupt_sources_14_m_interrupt_req_set_not_clear(core$core_external_interrupt_sources_14_m_interrupt_req_set_not_clear),
	      .core_external_interrupt_sources_15_m_interrupt_req_set_not_clear(core$core_external_interrupt_sources_15_m_interrupt_req_set_not_clear),
	      .core_external_interrupt_sources_1_m_interrupt_req_set_not_clear(core$core_external_interrupt_sources_1_m_interrupt_req_set_not_clear),
	      .core_external_interrupt_sources_2_m_interrupt_req_set_not_clear(core$core_external_interrupt_sources_2_m_interrupt_req_set_not_clear),
	      .core_external_interrupt_sources_3_m_interrupt_req_set_not_clear(core$core_external_interrupt_sources_3_m_interrupt_req_set_not_clear),
	      .core_external_interrupt_sources_4_m_interrupt_req_set_not_clear(core$core_external_interrupt_sources_4_m_interrupt_req_set_not_clear),
	      .core_external_interrupt_sources_5_m_interrupt_req_set_not_clear(core$core_external_interrupt_sources_5_m_interrupt_req_set_not_clear),
	      .core_external_interrupt_sources_6_m_interrupt_req_set_not_clear(core$core_external_interrupt_sources_6_m_interrupt_req_set_not_clear),
	      .core_external_interrupt_sources_7_m_interrupt_req_set_not_clear(core$core_external_interrupt_sources_7_m_interrupt_req_set_not_clear),
	      .core_external_interrupt_sources_8_m_interrupt_req_set_not_clear(core$core_external_interrupt_sources_8_m_interrupt_req_set_not_clear),
	      .core_external_interrupt_sources_9_m_interrupt_req_set_not_clear(core$core_external_interrupt_sources_9_m_interrupt_req_set_not_clear),
	      .cpu_dmem_master_arready(core$cpu_dmem_master_arready),
	      .cpu_dmem_master_awready(core$cpu_dmem_master_awready),
	      .cpu_dmem_master_bid(core$cpu_dmem_master_bid),
	      .cpu_dmem_master_bresp(core$cpu_dmem_master_bresp),
	      .cpu_dmem_master_bvalid(core$cpu_dmem_master_bvalid),
	      .cpu_dmem_master_rdata(core$cpu_dmem_master_rdata),
	      .cpu_dmem_master_rid(core$cpu_dmem_master_rid),
	      .cpu_dmem_master_rlast(core$cpu_dmem_master_rlast),
	      .cpu_dmem_master_rresp(core$cpu_dmem_master_rresp),
	      .cpu_dmem_master_rvalid(core$cpu_dmem_master_rvalid),
	      .cpu_dmem_master_wready(core$cpu_dmem_master_wready),
	      .cpu_imem_master_arready(core$cpu_imem_master_arready),
	      .cpu_imem_master_awready(core$cpu_imem_master_awready),
	      .cpu_imem_master_bid(core$cpu_imem_master_bid),
	      .cpu_imem_master_bresp(core$cpu_imem_master_bresp),
	      .cpu_imem_master_bvalid(core$cpu_imem_master_bvalid),
	      .cpu_imem_master_rdata(core$cpu_imem_master_rdata),
	      .cpu_imem_master_rid(core$cpu_imem_master_rid),
	      .cpu_imem_master_rlast(core$cpu_imem_master_rlast),
	      .cpu_imem_master_rresp(core$cpu_imem_master_rresp),
	      .cpu_imem_master_rvalid(core$cpu_imem_master_rvalid),
	      .cpu_imem_master_wready(core$cpu_imem_master_wready),
	      .cpu_reset_server_request_put(core$cpu_reset_server_request_put),
	      .dm_dmi_read_addr_dm_addr(core$dm_dmi_read_addr_dm_addr),
	      .dm_dmi_write_dm_addr(core$dm_dmi_write_dm_addr),
	      .dm_dmi_write_dm_word(core$dm_dmi_write_dm_word),
	      .ndm_reset_client_response_put(core$ndm_reset_client_response_put),
	      .nmi_req_set_not_clear(core$nmi_req_set_not_clear),
	      .set_verbosity_logdelay(core$set_verbosity_logdelay),
	      .set_verbosity_verbosity(core$set_verbosity_verbosity),
	      .EN_set_verbosity(core$EN_set_verbosity),
	      .EN_cpu_reset_server_request_put(core$EN_cpu_reset_server_request_put),
	      .EN_cpu_reset_server_response_get(core$EN_cpu_reset_server_response_get),
	      .EN_tv_verifier_info_get_get(core$EN_tv_verifier_info_get_get),
	      .EN_dm_dmi_read_addr(core$EN_dm_dmi_read_addr),
	      .EN_dm_dmi_read_data(core$EN_dm_dmi_read_data),
	      .EN_dm_dmi_write(core$EN_dm_dmi_write),
	      .EN_ndm_reset_client_request_get(core$EN_ndm_reset_client_request_get),
	      .EN_ndm_reset_client_response_put(core$EN_ndm_reset_client_response_put),
	      .RDY_set_verbosity(),
	      .RDY_cpu_reset_server_request_put(core$RDY_cpu_reset_server_request_put),
	      .cpu_reset_server_response_get(core$cpu_reset_server_response_get),
	      .RDY_cpu_reset_server_response_get(core$RDY_cpu_reset_server_response_get),
	      .cpu_imem_master_awvalid(core$cpu_imem_master_awvalid),
	      .cpu_imem_master_awid(core$cpu_imem_master_awid),
	      .cpu_imem_master_awaddr(core$cpu_imem_master_awaddr),
	      .cpu_imem_master_awlen(core$cpu_imem_master_awlen),
	      .cpu_imem_master_awsize(core$cpu_imem_master_awsize),
	      .cpu_imem_master_awburst(core$cpu_imem_master_awburst),
	      .cpu_imem_master_awlock(core$cpu_imem_master_awlock),
	      .cpu_imem_master_awcache(core$cpu_imem_master_awcache),
	      .cpu_imem_master_awprot(core$cpu_imem_master_awprot),
	      .cpu_imem_master_awqos(core$cpu_imem_master_awqos),
	      .cpu_imem_master_awregion(core$cpu_imem_master_awregion),
	      .cpu_imem_master_wvalid(core$cpu_imem_master_wvalid),
	      .cpu_imem_master_wdata(core$cpu_imem_master_wdata),
	      .cpu_imem_master_wstrb(core$cpu_imem_master_wstrb),
	      .cpu_imem_master_wlast(core$cpu_imem_master_wlast),
	      .cpu_imem_master_bready(core$cpu_imem_master_bready),
	      .cpu_imem_master_arvalid(core$cpu_imem_master_arvalid),
	      .cpu_imem_master_arid(core$cpu_imem_master_arid),
	      .cpu_imem_master_araddr(core$cpu_imem_master_araddr),
	      .cpu_imem_master_arlen(core$cpu_imem_master_arlen),
	      .cpu_imem_master_arsize(core$cpu_imem_master_arsize),
	      .cpu_imem_master_arburst(core$cpu_imem_master_arburst),
	      .cpu_imem_master_arlock(core$cpu_imem_master_arlock),
	      .cpu_imem_master_arcache(core$cpu_imem_master_arcache),
	      .cpu_imem_master_arprot(core$cpu_imem_master_arprot),
	      .cpu_imem_master_arqos(core$cpu_imem_master_arqos),
	      .cpu_imem_master_arregion(core$cpu_imem_master_arregion),
	      .cpu_imem_master_rready(core$cpu_imem_master_rready),
	      .cpu_dmem_master_awvalid(core$cpu_dmem_master_awvalid),
	      .cpu_dmem_master_awid(core$cpu_dmem_master_awid),
	      .cpu_dmem_master_awaddr(core$cpu_dmem_master_awaddr),
	      .cpu_dmem_master_awlen(core$cpu_dmem_master_awlen),
	      .cpu_dmem_master_awsize(core$cpu_dmem_master_awsize),
	      .cpu_dmem_master_awburst(core$cpu_dmem_master_awburst),
	      .cpu_dmem_master_awlock(core$cpu_dmem_master_awlock),
	      .cpu_dmem_master_awcache(core$cpu_dmem_master_awcache),
	      .cpu_dmem_master_awprot(core$cpu_dmem_master_awprot),
	      .cpu_dmem_master_awqos(core$cpu_dmem_master_awqos),
	      .cpu_dmem_master_awregion(core$cpu_dmem_master_awregion),
	      .cpu_dmem_master_wvalid(core$cpu_dmem_master_wvalid),
	      .cpu_dmem_master_wdata(core$cpu_dmem_master_wdata),
	      .cpu_dmem_master_wstrb(core$cpu_dmem_master_wstrb),
	      .cpu_dmem_master_wlast(core$cpu_dmem_master_wlast),
	      .cpu_dmem_master_bready(core$cpu_dmem_master_bready),
	      .cpu_dmem_master_arvalid(core$cpu_dmem_master_arvalid),
	      .cpu_dmem_master_arid(core$cpu_dmem_master_arid),
	      .cpu_dmem_master_araddr(core$cpu_dmem_master_araddr),
	      .cpu_dmem_master_arlen(core$cpu_dmem_master_arlen),
	      .cpu_dmem_master_arsize(core$cpu_dmem_master_arsize),
	      .cpu_dmem_master_arburst(core$cpu_dmem_master_arburst),
	      .cpu_dmem_master_arlock(core$cpu_dmem_master_arlock),
	      .cpu_dmem_master_arcache(core$cpu_dmem_master_arcache),
	      .cpu_dmem_master_arprot(core$cpu_dmem_master_arprot),
	      .cpu_dmem_master_arqos(core$cpu_dmem_master_arqos),
	      .cpu_dmem_master_arregion(core$cpu_dmem_master_arregion),
	      .cpu_dmem_master_rready(core$cpu_dmem_master_rready),
	      .tv_verifier_info_get_get(core$tv_verifier_info_get_get),
	      .RDY_tv_verifier_info_get_get(core$RDY_tv_verifier_info_get_get),
	      .RDY_dm_dmi_read_addr(core$RDY_dm_dmi_read_addr),
	      .dm_dmi_read_data(core$dm_dmi_read_data),
	      .RDY_dm_dmi_read_data(core$RDY_dm_dmi_read_data),
	      .RDY_dm_dmi_write(core$RDY_dm_dmi_write),
	      .ndm_reset_client_request_get(core$ndm_reset_client_request_get),
	      .RDY_ndm_reset_client_request_get(core$RDY_ndm_reset_client_request_get),
	      .RDY_ndm_reset_client_response_put(core$RDY_ndm_reset_client_response_put));

  // submodule jtagtap
  mkJtagTap jtagtap(.CLK(CLK),
		    .RST_N(RST_N),
		    .dmi_req_ready(jtagtap$dmi_req_ready),
		    .dmi_rsp_data(jtagtap$dmi_rsp_data),
		    .dmi_rsp_response(jtagtap$dmi_rsp_response),
		    .dmi_rsp_valid(jtagtap$dmi_rsp_valid),
		    .jtag_tclk(jtagtap$jtag_tclk),
		    .jtag_tdi(jtagtap$jtag_tdi),
		    .jtag_tms(jtagtap$jtag_tms),
		    .jtag_tdo(jtagtap$jtag_tdo),
		    .dmi_req_valid(jtagtap$dmi_req_valid),
		    .dmi_req_addr(jtagtap$dmi_req_addr),
		    .dmi_req_data(jtagtap$dmi_req_data),
		    .dmi_req_op(jtagtap$dmi_req_op),
		    .dmi_rsp_ready(jtagtap$dmi_rsp_ready),
		    .CLK_jtag_tclk_out(jtagtap$CLK_jtag_tclk_out),
		    .CLK_GATE_jtag_tclk_out());

  // submodule tv_xactor
  mkTV_Xactor tv_xactor(.CLK(CLK),
			.RST_N(RST_N),
			.axi_out_tready(tv_xactor$axi_out_tready),
			.tv_in_put(tv_xactor$tv_in_put),
			.EN_tv_in_put(tv_xactor$EN_tv_in_put),
			.RDY_tv_in_put(tv_xactor$RDY_tv_in_put),
			.axi_out_tvalid(tv_xactor$axi_out_tvalid),
			.axi_out_tdata(tv_xactor$axi_out_tdata),
			.axi_out_tstrb(tv_xactor$axi_out_tstrb),
			.axi_out_tkeep(tv_xactor$axi_out_tkeep),
			.axi_out_tlast(tv_xactor$axi_out_tlast));

  // rule RL_rl_always
  assign CAN_FIRE_RL_rl_always = 1'd1 ;
  assign WILL_FIRE_RL_rl_always = 1'd1 ;

  // rule RL_rl_once
  assign CAN_FIRE_RL_rl_once =
	     core$RDY_cpu_reset_server_request_put && !rg_once ;
  assign WILL_FIRE_RL_rl_once = CAN_FIRE_RL_rl_once ;

  // rule RL_mkConnectionVtoAf
  assign CAN_FIRE_RL_mkConnectionVtoAf = 1'd1 ;
  assign WILL_FIRE_RL_mkConnectionVtoAf = 1'd1 ;

  // rule RL_mkConnectionVtoAf_1
  assign CAN_FIRE_RL_mkConnectionVtoAf_1 = 1'd1 ;
  assign WILL_FIRE_RL_mkConnectionVtoAf_1 = 1'd1 ;

  // rule RL_mkConnectionVtoAf_2
  assign CAN_FIRE_RL_mkConnectionVtoAf_2 = 1'd1 ;
  assign WILL_FIRE_RL_mkConnectionVtoAf_2 = 1'd1 ;

  // rule RL_mkConnectionVtoAf_3
  assign CAN_FIRE_RL_mkConnectionVtoAf_3 = 1'd1 ;
  assign WILL_FIRE_RL_mkConnectionVtoAf_3 = 1'd1 ;

  // rule RL_mkConnectionVtoAf_4
  assign CAN_FIRE_RL_mkConnectionVtoAf_4 = 1'd1 ;
  assign WILL_FIRE_RL_mkConnectionVtoAf_4 = 1'd1 ;

  // rule RL_mkConnectionVtoAf_5
  assign CAN_FIRE_RL_mkConnectionVtoAf_5 = 1'd1 ;
  assign WILL_FIRE_RL_mkConnectionVtoAf_5 = 1'd1 ;

  // rule RL_mkConnectionVtoAf_6
  assign CAN_FIRE_RL_mkConnectionVtoAf_6 = 1'd1 ;
  assign WILL_FIRE_RL_mkConnectionVtoAf_6 = 1'd1 ;

  // rule RL_rl_dmi_req
  assign CAN_FIRE_RL_rl_dmi_req = 1'd1 ;
  assign WILL_FIRE_RL_rl_dmi_req = 1'd1 ;

  // rule RL_rl_dmi_rsp
  assign CAN_FIRE_RL_rl_dmi_rsp = 1'd1 ;
  assign WILL_FIRE_RL_rl_dmi_rsp = 1'd1 ;

  // rule RL_mkConnectionVtoAf_7
  assign CAN_FIRE_RL_mkConnectionVtoAf_7 = 1'd1 ;
  assign WILL_FIRE_RL_mkConnectionVtoAf_7 = 1'd1 ;

  // rule RL_mkConnectionVtoAf_8
  assign CAN_FIRE_RL_mkConnectionVtoAf_8 = 1'd1 ;
  assign WILL_FIRE_RL_mkConnectionVtoAf_8 = 1'd1 ;

  // rule RL_rl_dmi_req_cpu
  assign CAN_FIRE_RL_rl_dmi_req_cpu =
	     bus_dmi_req_fifof$EMPTY_N &&
	     IF_bus_dmi_req_fifof_first__9_BITS_1_TO_0_0_EQ_ETC___d90 ;
  assign WILL_FIRE_RL_rl_dmi_req_cpu = CAN_FIRE_RL_rl_dmi_req_cpu ;

  // rule RL_rl_dmi_rsp_cpu
  assign CAN_FIRE_RL_rl_dmi_rsp_cpu =
	     bus_dmi_rsp_fifof_cntr_r != 2'd2 && core$RDY_dm_dmi_read_data ;
  assign WILL_FIRE_RL_rl_dmi_rsp_cpu =
	     CAN_FIRE_RL_rl_dmi_rsp_cpu && !WILL_FIRE_RL_rl_dmi_req_cpu ;

  // rule RL_rl_reset_response
  assign CAN_FIRE_RL_rl_reset_response =
	     core$RDY_cpu_reset_server_response_get &&
	     (!rg_ndm_reset[1] || core$RDY_ndm_reset_client_response_put) ;
  assign WILL_FIRE_RL_rl_reset_response = CAN_FIRE_RL_rl_reset_response ;

  // rule RL_rl_ndmreset
  assign CAN_FIRE_RL_rl_ndmreset =
	     core$RDY_ndm_reset_client_request_get && rg_once ;
  assign WILL_FIRE_RL_rl_ndmreset = CAN_FIRE_RL_rl_ndmreset ;

  // rule RL_mkConnectionGetPut
  assign CAN_FIRE_RL_mkConnectionGetPut =
	     core$RDY_tv_verifier_info_get_get && tv_xactor$RDY_tv_in_put ;
  assign WILL_FIRE_RL_mkConnectionGetPut = CAN_FIRE_RL_mkConnectionGetPut ;

  // rule RL_bus_dmi_req_do_enq
  assign CAN_FIRE_RL_bus_dmi_req_do_enq =
	     bus_dmi_req_fifof$FULL_N && jtagtap$dmi_req_valid ;
  assign WILL_FIRE_RL_bus_dmi_req_do_enq = CAN_FIRE_RL_bus_dmi_req_do_enq ;

  // rule RL_bus_dmi_rsp_do_deq
  assign CAN_FIRE_RL_bus_dmi_rsp_do_deq =
	     bus_dmi_rsp_fifof_cntr_r != 2'd0 && jtagtap$dmi_rsp_ready ;
  assign WILL_FIRE_RL_bus_dmi_rsp_do_deq = CAN_FIRE_RL_bus_dmi_rsp_do_deq ;

  // rule RL_bus_dmi_rsp_fifof_incCtr
  assign CAN_FIRE_RL_bus_dmi_rsp_fifof_incCtr =
	     bus_dmi_rsp_fifof_enqueueing$whas &&
	     bus_dmi_rsp_fifof_enqueueing$whas &&
	     !CAN_FIRE_RL_bus_dmi_rsp_do_deq ;
  assign WILL_FIRE_RL_bus_dmi_rsp_fifof_incCtr =
	     CAN_FIRE_RL_bus_dmi_rsp_fifof_incCtr ;

  // rule RL_bus_dmi_rsp_fifof_decCtr
  assign CAN_FIRE_RL_bus_dmi_rsp_fifof_decCtr =
	     CAN_FIRE_RL_bus_dmi_rsp_do_deq &&
	     !bus_dmi_rsp_fifof_enqueueing$whas ;
  assign WILL_FIRE_RL_bus_dmi_rsp_fifof_decCtr =
	     CAN_FIRE_RL_bus_dmi_rsp_fifof_decCtr ;

  // rule RL_bus_dmi_rsp_fifof_both
  assign CAN_FIRE_RL_bus_dmi_rsp_fifof_both =
	     bus_dmi_rsp_fifof_enqueueing$whas &&
	     CAN_FIRE_RL_bus_dmi_rsp_do_deq &&
	     bus_dmi_rsp_fifof_enqueueing$whas ;
  assign WILL_FIRE_RL_bus_dmi_rsp_fifof_both =
	     CAN_FIRE_RL_bus_dmi_rsp_fifof_both ;

  // inputs to muxes for submodule ports
  assign MUX_bus_dmi_rsp_fifof_q_0$write_1__SEL_1 =
	     WILL_FIRE_RL_bus_dmi_rsp_fifof_both && _dfoo3 ;
  assign MUX_bus_dmi_rsp_fifof_q_0$write_1__SEL_2 =
	     WILL_FIRE_RL_bus_dmi_rsp_fifof_incCtr &&
	     bus_dmi_rsp_fifof_cntr_r == 2'd0 ;
  assign MUX_bus_dmi_rsp_fifof_q_1$write_1__SEL_1 =
	     WILL_FIRE_RL_bus_dmi_rsp_fifof_both && _dfoo1 ;
  assign MUX_bus_dmi_rsp_fifof_q_1$write_1__SEL_2 =
	     WILL_FIRE_RL_bus_dmi_rsp_fifof_incCtr &&
	     bus_dmi_rsp_fifof_cntr_r == 2'd1 ;
  assign MUX_bus_dmi_rsp_fifof_x_wire$wset_1__SEL_1 =
	     WILL_FIRE_RL_rl_dmi_req_cpu &&
	     bus_dmi_req_fifof$D_OUT[1:0] != 2'd1 ;
  assign MUX_bus_dmi_rsp_fifof_cntr_r$write_1__VAL_2 =
	     bus_dmi_rsp_fifof_cntr_r + 2'd1 ;
  assign MUX_bus_dmi_rsp_fifof_q_0$write_1__VAL_1 =
	     (bus_dmi_rsp_fifof_cntr_r == 2'd1) ?
	       MUX_bus_dmi_rsp_fifof_q_0$write_1__VAL_2 :
	       bus_dmi_rsp_fifof_q_1 ;
  assign MUX_bus_dmi_rsp_fifof_q_0$write_1__VAL_2 =
	     MUX_bus_dmi_rsp_fifof_x_wire$wset_1__SEL_1 ?
	       MUX_bus_dmi_rsp_fifof_x_wire$wset_1__VAL_1 :
	       MUX_bus_dmi_rsp_fifof_x_wire$wset_1__VAL_2 ;
  assign MUX_bus_dmi_rsp_fifof_q_1$write_1__VAL_1 =
	     (bus_dmi_rsp_fifof_cntr_r == 2'd2) ?
	       MUX_bus_dmi_rsp_fifof_q_0$write_1__VAL_2 :
	       34'd0 ;
  assign MUX_bus_dmi_rsp_fifof_x_wire$wset_1__VAL_1 =
	     { 32'hAAAAAAAA,
	       (bus_dmi_req_fifof$D_OUT[1:0] == 2'd2) ? 2'd0 : 2'd2 } ;
  assign MUX_bus_dmi_rsp_fifof_x_wire$wset_1__VAL_2 =
	     { core$dm_dmi_read_data, 2'd0 } ;
  assign MUX_rg_ndm_reset$write_1__VAL_1 =
	     { 1'd1, core$ndm_reset_client_request_get } ;

  // inlined wires
  assign bus_dmi_rsp_fifof_enqueueing$whas =
	     WILL_FIRE_RL_rl_dmi_req_cpu &&
	     bus_dmi_req_fifof$D_OUT[1:0] != 2'd1 ||
	     WILL_FIRE_RL_rl_dmi_rsp_cpu ;
  assign bus_dmi_req_data_wire$wget =
	     { jtagtap$dmi_req_addr,
	       jtagtap$dmi_req_data,
	       jtagtap$dmi_req_op } ;

  // register bus_dmi_rsp_fifof_cntr_r
  assign bus_dmi_rsp_fifof_cntr_r$D_IN =
	     WILL_FIRE_RL_bus_dmi_rsp_fifof_decCtr ?
	       bus_dmi_rsp_fifof_cntr_r_2_MINUS_1___d40 :
	       MUX_bus_dmi_rsp_fifof_cntr_r$write_1__VAL_2 ;
  assign bus_dmi_rsp_fifof_cntr_r$EN =
	     WILL_FIRE_RL_bus_dmi_rsp_fifof_decCtr ||
	     WILL_FIRE_RL_bus_dmi_rsp_fifof_incCtr ;

  // register bus_dmi_rsp_fifof_q_0
  always@(MUX_bus_dmi_rsp_fifof_q_0$write_1__SEL_1 or
	  MUX_bus_dmi_rsp_fifof_q_0$write_1__VAL_1 or
	  MUX_bus_dmi_rsp_fifof_q_0$write_1__SEL_2 or
	  MUX_bus_dmi_rsp_fifof_q_0$write_1__VAL_2 or
	  WILL_FIRE_RL_bus_dmi_rsp_fifof_decCtr or bus_dmi_rsp_fifof_q_1)
  begin
    case (1'b1) // synopsys parallel_case
      MUX_bus_dmi_rsp_fifof_q_0$write_1__SEL_1:
	  bus_dmi_rsp_fifof_q_0$D_IN =
	      MUX_bus_dmi_rsp_fifof_q_0$write_1__VAL_1;
      MUX_bus_dmi_rsp_fifof_q_0$write_1__SEL_2:
	  bus_dmi_rsp_fifof_q_0$D_IN =
	      MUX_bus_dmi_rsp_fifof_q_0$write_1__VAL_2;
      WILL_FIRE_RL_bus_dmi_rsp_fifof_decCtr:
	  bus_dmi_rsp_fifof_q_0$D_IN = bus_dmi_rsp_fifof_q_1;
      default: bus_dmi_rsp_fifof_q_0$D_IN =
		   34'h2AAAAAAAA /* unspecified value */ ;
    endcase
  end
  assign bus_dmi_rsp_fifof_q_0$EN =
	     WILL_FIRE_RL_bus_dmi_rsp_fifof_both && _dfoo3 ||
	     WILL_FIRE_RL_bus_dmi_rsp_fifof_incCtr &&
	     bus_dmi_rsp_fifof_cntr_r == 2'd0 ||
	     WILL_FIRE_RL_bus_dmi_rsp_fifof_decCtr ;

  // register bus_dmi_rsp_fifof_q_1
  always@(MUX_bus_dmi_rsp_fifof_q_1$write_1__SEL_1 or
	  MUX_bus_dmi_rsp_fifof_q_1$write_1__VAL_1 or
	  MUX_bus_dmi_rsp_fifof_q_1$write_1__SEL_2 or
	  MUX_bus_dmi_rsp_fifof_q_0$write_1__VAL_2 or
	  WILL_FIRE_RL_bus_dmi_rsp_fifof_decCtr)
  begin
    case (1'b1) // synopsys parallel_case
      MUX_bus_dmi_rsp_fifof_q_1$write_1__SEL_1:
	  bus_dmi_rsp_fifof_q_1$D_IN =
	      MUX_bus_dmi_rsp_fifof_q_1$write_1__VAL_1;
      MUX_bus_dmi_rsp_fifof_q_1$write_1__SEL_2:
	  bus_dmi_rsp_fifof_q_1$D_IN =
	      MUX_bus_dmi_rsp_fifof_q_0$write_1__VAL_2;
      WILL_FIRE_RL_bus_dmi_rsp_fifof_decCtr:
	  bus_dmi_rsp_fifof_q_1$D_IN = 34'd0;
      default: bus_dmi_rsp_fifof_q_1$D_IN =
		   34'h2AAAAAAAA /* unspecified value */ ;
    endcase
  end
  assign bus_dmi_rsp_fifof_q_1$EN =
	     WILL_FIRE_RL_bus_dmi_rsp_fifof_both && _dfoo1 ||
	     WILL_FIRE_RL_bus_dmi_rsp_fifof_incCtr &&
	     bus_dmi_rsp_fifof_cntr_r == 2'd1 ||
	     WILL_FIRE_RL_bus_dmi_rsp_fifof_decCtr ;

  // register rg_ndm_reset
  assign rg_ndm_reset$D_IN =
	     WILL_FIRE_RL_rl_ndmreset ?
	       MUX_rg_ndm_reset$write_1__VAL_1 :
	       2'd0 ;
  assign rg_ndm_reset$EN =
	     WILL_FIRE_RL_rl_reset_response || WILL_FIRE_RL_rl_ndmreset ;

  // register rg_once
  assign rg_once$D_IN = !WILL_FIRE_RL_rl_ndmreset ;
  assign rg_once$EN = WILL_FIRE_RL_rl_ndmreset || WILL_FIRE_RL_rl_once ;

  // submodule bus_dmi_req_fifof
  assign bus_dmi_req_fifof$D_IN = bus_dmi_req_data_wire$wget ;
  assign bus_dmi_req_fifof$ENQ = CAN_FIRE_RL_bus_dmi_req_do_enq ;
  assign bus_dmi_req_fifof$DEQ = CAN_FIRE_RL_rl_dmi_req_cpu ;
  assign bus_dmi_req_fifof$CLR = 1'b0 ;

  // submodule core
  assign core$core_external_interrupt_sources_0_m_interrupt_req_set_not_clear =
	     cpu_external_interrupt_req[0] ;
  assign core$core_external_interrupt_sources_10_m_interrupt_req_set_not_clear =
	     cpu_external_interrupt_req[10] ;
  assign core$core_external_interrupt_sources_11_m_interrupt_req_set_not_clear =
	     cpu_external_interrupt_req[11] ;
  assign core$core_external_interrupt_sources_12_m_interrupt_req_set_not_clear =
	     cpu_external_interrupt_req[12] ;
  assign core$core_external_interrupt_sources_13_m_interrupt_req_set_not_clear =
	     cpu_external_interrupt_req[13] ;
  assign core$core_external_interrupt_sources_14_m_interrupt_req_set_not_clear =
	     cpu_external_interrupt_req[14] ;
  assign core$core_external_interrupt_sources_15_m_interrupt_req_set_not_clear =
	     cpu_external_interrupt_req[15] ;
  assign core$core_external_interrupt_sources_1_m_interrupt_req_set_not_clear =
	     cpu_external_interrupt_req[1] ;
  assign core$core_external_interrupt_sources_2_m_interrupt_req_set_not_clear =
	     cpu_external_interrupt_req[2] ;
  assign core$core_external_interrupt_sources_3_m_interrupt_req_set_not_clear =
	     cpu_external_interrupt_req[3] ;
  assign core$core_external_interrupt_sources_4_m_interrupt_req_set_not_clear =
	     cpu_external_interrupt_req[4] ;
  assign core$core_external_interrupt_sources_5_m_interrupt_req_set_not_clear =
	     cpu_external_interrupt_req[5] ;
  assign core$core_external_interrupt_sources_6_m_interrupt_req_set_not_clear =
	     cpu_external_interrupt_req[6] ;
  assign core$core_external_interrupt_sources_7_m_interrupt_req_set_not_clear =
	     cpu_external_interrupt_req[7] ;
  assign core$core_external_interrupt_sources_8_m_interrupt_req_set_not_clear =
	     cpu_external_interrupt_req[8] ;
  assign core$core_external_interrupt_sources_9_m_interrupt_req_set_not_clear =
	     cpu_external_interrupt_req[9] ;
  assign core$cpu_dmem_master_arready = master1_arready ;
  assign core$cpu_dmem_master_awready = master1_awready ;
  assign core$cpu_dmem_master_bid = master1_bid ;
  assign core$cpu_dmem_master_bresp = master1_bresp ;
  assign core$cpu_dmem_master_bvalid = master1_bvalid ;
  assign core$cpu_dmem_master_rdata = master1_rdata ;
  assign core$cpu_dmem_master_rid = master1_rid ;
  assign core$cpu_dmem_master_rlast = master1_rlast ;
  assign core$cpu_dmem_master_rresp = master1_rresp ;
  assign core$cpu_dmem_master_rvalid = master1_rvalid ;
  assign core$cpu_dmem_master_wready = master1_wready ;
  assign core$cpu_imem_master_arready = master0_arready ;
  assign core$cpu_imem_master_awready = master0_awready ;
  assign core$cpu_imem_master_bid = master0_bid ;
  assign core$cpu_imem_master_bresp = master0_bresp ;
  assign core$cpu_imem_master_bvalid = master0_bvalid ;
  assign core$cpu_imem_master_rdata = master0_rdata ;
  assign core$cpu_imem_master_rid = master0_rid ;
  assign core$cpu_imem_master_rlast = master0_rlast ;
  assign core$cpu_imem_master_rresp = master0_rresp ;
  assign core$cpu_imem_master_rvalid = master0_rvalid ;
  assign core$cpu_imem_master_wready = master0_wready ;
  assign core$cpu_reset_server_request_put =
	     !rg_ndm_reset[1] || rg_ndm_reset[0] ;
  assign core$dm_dmi_read_addr_dm_addr = bus_dmi_req_fifof$D_OUT[40:34] ;
  assign core$dm_dmi_write_dm_addr = bus_dmi_req_fifof$D_OUT[40:34] ;
  assign core$dm_dmi_write_dm_word = bus_dmi_req_fifof$D_OUT[33:2] ;
  assign core$ndm_reset_client_response_put =
	     core$cpu_reset_server_response_get ;
  assign core$nmi_req_set_not_clear = 1'd0 ;
  assign core$set_verbosity_logdelay = 64'h0 ;
  assign core$set_verbosity_verbosity = 4'h0 ;
  assign core$EN_set_verbosity = 1'b0 ;
  assign core$EN_cpu_reset_server_request_put = CAN_FIRE_RL_rl_once ;
  assign core$EN_cpu_reset_server_response_get =
	     CAN_FIRE_RL_rl_reset_response ;
  assign core$EN_tv_verifier_info_get_get = CAN_FIRE_RL_mkConnectionGetPut ;
  assign core$EN_dm_dmi_read_addr =
	     WILL_FIRE_RL_rl_dmi_req_cpu &&
	     bus_dmi_req_fifof$D_OUT[1:0] == 2'd1 ;
  assign core$EN_dm_dmi_read_data = WILL_FIRE_RL_rl_dmi_rsp_cpu ;
  assign core$EN_dm_dmi_write =
	     WILL_FIRE_RL_rl_dmi_req_cpu &&
	     bus_dmi_req_fifof$D_OUT[1:0] == 2'd2 ;
  assign core$EN_ndm_reset_client_request_get = CAN_FIRE_RL_rl_ndmreset ;
  assign core$EN_ndm_reset_client_response_put =
	     WILL_FIRE_RL_rl_reset_response && rg_ndm_reset[1] ;

  // submodule jtagtap
  assign jtagtap$dmi_req_ready = bus_dmi_req_fifof$FULL_N ;
  assign jtagtap$dmi_rsp_data = bus_dmi_rsp_fifof_q_0[33:2] ;
  assign jtagtap$dmi_rsp_response = bus_dmi_rsp_fifof_q_0[1:0] ;
  assign jtagtap$dmi_rsp_valid = bus_dmi_rsp_fifof_cntr_r != 2'd0 ;
  assign jtagtap$jtag_tclk = jtag_tclk ;
  assign jtagtap$jtag_tdi = jtag_tdi ;
  assign jtagtap$jtag_tms = jtag_tms ;

  // submodule tv_xactor
  assign tv_xactor$axi_out_tready = tv_verifier_info_tx_tready ;
  assign tv_xactor$tv_in_put = core$tv_verifier_info_get_get ;
  assign tv_xactor$EN_tv_in_put = CAN_FIRE_RL_mkConnectionGetPut ;

  // remaining internal signals
  assign IF_bus_dmi_req_fifof_first__9_BITS_1_TO_0_0_EQ_ETC___d90 =
	     (bus_dmi_req_fifof$D_OUT[1:0] == 2'd1) ?
	       core$RDY_dm_dmi_read_addr :
	       (bus_dmi_req_fifof$D_OUT[1:0] == 2'd2 ||
		bus_dmi_rsp_fifof_cntr_r != 2'd2) &&
	       (bus_dmi_req_fifof$D_OUT[1:0] != 2'd2 ||
		bus_dmi_rsp_fifof_cntr_r != 2'd2 && core$RDY_dm_dmi_write) ;
  assign _dfoo1 =
	     bus_dmi_rsp_fifof_cntr_r != 2'd2 ||
	     bus_dmi_rsp_fifof_cntr_r_2_MINUS_1___d40 == 2'd1 ;
  assign _dfoo3 =
	     bus_dmi_rsp_fifof_cntr_r != 2'd1 ||
	     bus_dmi_rsp_fifof_cntr_r_2_MINUS_1___d40 == 2'd0 ;
  assign bus_dmi_rsp_fifof_cntr_r_2_MINUS_1___d40 =
	     bus_dmi_rsp_fifof_cntr_r - 2'd1 ;

  // handling of inlined registers

  always@(posedge CLK)
  begin
    if (RST_N == `BSV_RESET_VALUE)
      begin
        bus_dmi_rsp_fifof_cntr_r <= `BSV_ASSIGNMENT_DELAY 2'd0;
	bus_dmi_rsp_fifof_q_0 <= `BSV_ASSIGNMENT_DELAY 34'd0;
	bus_dmi_rsp_fifof_q_1 <= `BSV_ASSIGNMENT_DELAY 34'd0;
	rg_ndm_reset <= `BSV_ASSIGNMENT_DELAY 2'd0;
	rg_once <= `BSV_ASSIGNMENT_DELAY 1'd0;
      end
    else
      begin
        if (bus_dmi_rsp_fifof_cntr_r$EN)
	  bus_dmi_rsp_fifof_cntr_r <= `BSV_ASSIGNMENT_DELAY
	      bus_dmi_rsp_fifof_cntr_r$D_IN;
	if (bus_dmi_rsp_fifof_q_0$EN)
	  bus_dmi_rsp_fifof_q_0 <= `BSV_ASSIGNMENT_DELAY
	      bus_dmi_rsp_fifof_q_0$D_IN;
	if (bus_dmi_rsp_fifof_q_1$EN)
	  bus_dmi_rsp_fifof_q_1 <= `BSV_ASSIGNMENT_DELAY
	      bus_dmi_rsp_fifof_q_1$D_IN;
	if (rg_ndm_reset$EN)
	  rg_ndm_reset <= `BSV_ASSIGNMENT_DELAY rg_ndm_reset$D_IN;
	if (rg_once$EN) rg_once <= `BSV_ASSIGNMENT_DELAY rg_once$D_IN;
      end
  end

  // synopsys translate_off
  `ifdef BSV_NO_INITIAL_BLOCKS
  `else // not BSV_NO_INITIAL_BLOCKS
  initial
  begin
    bus_dmi_rsp_fifof_cntr_r = 2'h2;
    bus_dmi_rsp_fifof_q_0 = 34'h2AAAAAAAA;
    bus_dmi_rsp_fifof_q_1 = 34'h2AAAAAAAA;
    rg_ndm_reset = 2'h2;
    rg_once = 1'h0;
  end
  `endif // BSV_NO_INITIAL_BLOCKS
  // synopsys translate_on
endmodule  // mkP1_Core

