//
// Generated by Bluespec Compiler (build 0fccbb13)
//
//
// Ports:
// Name                         I/O  size props
// RDY_hart0_server_reset_request_put  O     1 reg
// hart0_server_reset_response_get  O     1 reg
// RDY_hart0_server_reset_response_get  O     1 reg
// imem_master_awvalid            O     1 reg
// imem_master_awid               O     4 reg
// imem_master_awaddr             O    64 reg
// imem_master_awlen              O     8 reg
// imem_master_awsize             O     3 reg
// imem_master_awburst            O     2 reg
// imem_master_awlock             O     1 reg
// imem_master_awcache            O     4 reg
// imem_master_awprot             O     3 reg
// imem_master_awqos              O     4 reg
// imem_master_awregion           O     4 reg
// imem_master_wvalid             O     1 reg
// imem_master_wdata              O    64 reg
// imem_master_wstrb              O     8 reg
// imem_master_wlast              O     1 reg
// imem_master_bready             O     1 reg
// imem_master_arvalid            O     1 reg
// imem_master_arid               O     4 reg
// imem_master_araddr             O    64 reg
// imem_master_arlen              O     8 reg
// imem_master_arsize             O     3 reg
// imem_master_arburst            O     2 reg
// imem_master_arlock             O     1 reg
// imem_master_arcache            O     4 reg
// imem_master_arprot             O     3 reg
// imem_master_arqos              O     4 reg
// imem_master_arregion           O     4 reg
// imem_master_rready             O     1 reg
// dmem_master_awvalid            O     1 reg
// dmem_master_awid               O     4 reg
// dmem_master_awaddr             O    64 reg
// dmem_master_awlen              O     8 reg
// dmem_master_awsize             O     3 reg
// dmem_master_awburst            O     2 reg
// dmem_master_awlock             O     1 reg
// dmem_master_awcache            O     4 reg
// dmem_master_awprot             O     3 reg
// dmem_master_awqos              O     4 reg
// dmem_master_awregion           O     4 reg
// dmem_master_wvalid             O     1 reg
// dmem_master_wdata              O    64 reg
// dmem_master_wstrb              O     8 reg
// dmem_master_wlast              O     1 reg
// dmem_master_bready             O     1 reg
// dmem_master_arvalid            O     1 reg
// dmem_master_arid               O     4 reg
// dmem_master_araddr             O    64 reg
// dmem_master_arlen              O     8 reg
// dmem_master_arsize             O     3 reg
// dmem_master_arburst            O     2 reg
// dmem_master_arlock             O     1 reg
// dmem_master_arcache            O     4 reg
// dmem_master_arprot             O     3 reg
// dmem_master_arqos              O     4 reg
// dmem_master_arregion           O     4 reg
// dmem_master_rready             O     1 reg
// RDY_set_verbosity              O     1 const
// CLK                            I     1 clock
// RST_N                          I     1 reset
// hart0_server_reset_request_put  I     1 reg
// imem_master_awready            I     1
// imem_master_wready             I     1
// imem_master_bvalid             I     1
// imem_master_bid                I     4 reg
// imem_master_bresp              I     2 reg
// imem_master_arready            I     1
// imem_master_rvalid             I     1
// imem_master_rid                I     4 reg
// imem_master_rdata              I    64 reg
// imem_master_rresp              I     2 reg
// imem_master_rlast              I     1 reg
// dmem_master_awready            I     1
// dmem_master_wready             I     1
// dmem_master_bvalid             I     1
// dmem_master_bid                I     4 reg
// dmem_master_bresp              I     2 reg
// dmem_master_arready            I     1
// dmem_master_rvalid             I     1
// dmem_master_rid                I     4 reg
// dmem_master_rdata              I    64 reg
// dmem_master_rresp              I     2 reg
// dmem_master_rlast              I     1 reg
// m_external_interrupt_req_set_not_clear  I     1 reg
// s_external_interrupt_req_set_not_clear  I     1 reg
// software_interrupt_req_set_not_clear  I     1 reg
// timer_interrupt_req_set_not_clear  I     1 reg
// nmi_req_set_not_clear          I     1
// set_verbosity_verbosity        I     4 reg
// set_verbosity_logdelay         I    64 reg
// EN_hart0_server_reset_request_put  I     1
// EN_set_verbosity               I     1
// EN_hart0_server_reset_response_get  I     1
//
// No combinational paths from inputs to outputs
//
//

`ifdef BSV_ASSIGNMENT_DELAY
`else
  `define BSV_ASSIGNMENT_DELAY
`endif

`ifdef BSV_POSITIVE_RESET
  `define BSV_RESET_VALUE 1'b1
  `define BSV_RESET_EDGE posedge
`else
  `define BSV_RESET_VALUE 1'b0
  `define BSV_RESET_EDGE negedge
`endif

module mkCPU(CLK,
	     RST_N,

	     hart0_server_reset_request_put,
	     EN_hart0_server_reset_request_put,
	     RDY_hart0_server_reset_request_put,

	     EN_hart0_server_reset_response_get,
	     hart0_server_reset_response_get,
	     RDY_hart0_server_reset_response_get,

	     imem_master_awvalid,

	     imem_master_awid,

	     imem_master_awaddr,

	     imem_master_awlen,

	     imem_master_awsize,

	     imem_master_awburst,

	     imem_master_awlock,

	     imem_master_awcache,

	     imem_master_awprot,

	     imem_master_awqos,

	     imem_master_awregion,

	     imem_master_awready,

	     imem_master_wvalid,

	     imem_master_wdata,

	     imem_master_wstrb,

	     imem_master_wlast,

	     imem_master_wready,

	     imem_master_bvalid,
	     imem_master_bid,
	     imem_master_bresp,

	     imem_master_bready,

	     imem_master_arvalid,

	     imem_master_arid,

	     imem_master_araddr,

	     imem_master_arlen,

	     imem_master_arsize,

	     imem_master_arburst,

	     imem_master_arlock,

	     imem_master_arcache,

	     imem_master_arprot,

	     imem_master_arqos,

	     imem_master_arregion,

	     imem_master_arready,

	     imem_master_rvalid,
	     imem_master_rid,
	     imem_master_rdata,
	     imem_master_rresp,
	     imem_master_rlast,

	     imem_master_rready,

	     dmem_master_awvalid,

	     dmem_master_awid,

	     dmem_master_awaddr,

	     dmem_master_awlen,

	     dmem_master_awsize,

	     dmem_master_awburst,

	     dmem_master_awlock,

	     dmem_master_awcache,

	     dmem_master_awprot,

	     dmem_master_awqos,

	     dmem_master_awregion,

	     dmem_master_awready,

	     dmem_master_wvalid,

	     dmem_master_wdata,

	     dmem_master_wstrb,

	     dmem_master_wlast,

	     dmem_master_wready,

	     dmem_master_bvalid,
	     dmem_master_bid,
	     dmem_master_bresp,

	     dmem_master_bready,

	     dmem_master_arvalid,

	     dmem_master_arid,

	     dmem_master_araddr,

	     dmem_master_arlen,

	     dmem_master_arsize,

	     dmem_master_arburst,

	     dmem_master_arlock,

	     dmem_master_arcache,

	     dmem_master_arprot,

	     dmem_master_arqos,

	     dmem_master_arregion,

	     dmem_master_arready,

	     dmem_master_rvalid,
	     dmem_master_rid,
	     dmem_master_rdata,
	     dmem_master_rresp,
	     dmem_master_rlast,

	     dmem_master_rready,

	     m_external_interrupt_req_set_not_clear,

	     s_external_interrupt_req_set_not_clear,

	     software_interrupt_req_set_not_clear,

	     timer_interrupt_req_set_not_clear,

	     nmi_req_set_not_clear,

	     set_verbosity_verbosity,
	     set_verbosity_logdelay,
	     EN_set_verbosity,
	     RDY_set_verbosity);
  input  CLK;
  input  RST_N;

  // action method hart0_server_reset_request_put
  input  hart0_server_reset_request_put;
  input  EN_hart0_server_reset_request_put;
  output RDY_hart0_server_reset_request_put;

  // actionvalue method hart0_server_reset_response_get
  input  EN_hart0_server_reset_response_get;
  output hart0_server_reset_response_get;
  output RDY_hart0_server_reset_response_get;

  // value method imem_master_m_awvalid
  output imem_master_awvalid;

  // value method imem_master_m_awid
  output [3 : 0] imem_master_awid;

  // value method imem_master_m_awaddr
  output [63 : 0] imem_master_awaddr;

  // value method imem_master_m_awlen
  output [7 : 0] imem_master_awlen;

  // value method imem_master_m_awsize
  output [2 : 0] imem_master_awsize;

  // value method imem_master_m_awburst
  output [1 : 0] imem_master_awburst;

  // value method imem_master_m_awlock
  output imem_master_awlock;

  // value method imem_master_m_awcache
  output [3 : 0] imem_master_awcache;

  // value method imem_master_m_awprot
  output [2 : 0] imem_master_awprot;

  // value method imem_master_m_awqos
  output [3 : 0] imem_master_awqos;

  // value method imem_master_m_awregion
  output [3 : 0] imem_master_awregion;

  // value method imem_master_m_awuser

  // action method imem_master_m_awready
  input  imem_master_awready;

  // value method imem_master_m_wvalid
  output imem_master_wvalid;

  // value method imem_master_m_wdata
  output [63 : 0] imem_master_wdata;

  // value method imem_master_m_wstrb
  output [7 : 0] imem_master_wstrb;

  // value method imem_master_m_wlast
  output imem_master_wlast;

  // value method imem_master_m_wuser

  // action method imem_master_m_wready
  input  imem_master_wready;

  // action method imem_master_m_bvalid
  input  imem_master_bvalid;
  input  [3 : 0] imem_master_bid;
  input  [1 : 0] imem_master_bresp;

  // value method imem_master_m_bready
  output imem_master_bready;

  // value method imem_master_m_arvalid
  output imem_master_arvalid;

  // value method imem_master_m_arid
  output [3 : 0] imem_master_arid;

  // value method imem_master_m_araddr
  output [63 : 0] imem_master_araddr;

  // value method imem_master_m_arlen
  output [7 : 0] imem_master_arlen;

  // value method imem_master_m_arsize
  output [2 : 0] imem_master_arsize;

  // value method imem_master_m_arburst
  output [1 : 0] imem_master_arburst;

  // value method imem_master_m_arlock
  output imem_master_arlock;

  // value method imem_master_m_arcache
  output [3 : 0] imem_master_arcache;

  // value method imem_master_m_arprot
  output [2 : 0] imem_master_arprot;

  // value method imem_master_m_arqos
  output [3 : 0] imem_master_arqos;

  // value method imem_master_m_arregion
  output [3 : 0] imem_master_arregion;

  // value method imem_master_m_aruser

  // action method imem_master_m_arready
  input  imem_master_arready;

  // action method imem_master_m_rvalid
  input  imem_master_rvalid;
  input  [3 : 0] imem_master_rid;
  input  [63 : 0] imem_master_rdata;
  input  [1 : 0] imem_master_rresp;
  input  imem_master_rlast;

  // value method imem_master_m_rready
  output imem_master_rready;

  // value method dmem_master_m_awvalid
  output dmem_master_awvalid;

  // value method dmem_master_m_awid
  output [3 : 0] dmem_master_awid;

  // value method dmem_master_m_awaddr
  output [63 : 0] dmem_master_awaddr;

  // value method dmem_master_m_awlen
  output [7 : 0] dmem_master_awlen;

  // value method dmem_master_m_awsize
  output [2 : 0] dmem_master_awsize;

  // value method dmem_master_m_awburst
  output [1 : 0] dmem_master_awburst;

  // value method dmem_master_m_awlock
  output dmem_master_awlock;

  // value method dmem_master_m_awcache
  output [3 : 0] dmem_master_awcache;

  // value method dmem_master_m_awprot
  output [2 : 0] dmem_master_awprot;

  // value method dmem_master_m_awqos
  output [3 : 0] dmem_master_awqos;

  // value method dmem_master_m_awregion
  output [3 : 0] dmem_master_awregion;

  // value method dmem_master_m_awuser

  // action method dmem_master_m_awready
  input  dmem_master_awready;

  // value method dmem_master_m_wvalid
  output dmem_master_wvalid;

  // value method dmem_master_m_wdata
  output [63 : 0] dmem_master_wdata;

  // value method dmem_master_m_wstrb
  output [7 : 0] dmem_master_wstrb;

  // value method dmem_master_m_wlast
  output dmem_master_wlast;

  // value method dmem_master_m_wuser

  // action method dmem_master_m_wready
  input  dmem_master_wready;

  // action method dmem_master_m_bvalid
  input  dmem_master_bvalid;
  input  [3 : 0] dmem_master_bid;
  input  [1 : 0] dmem_master_bresp;

  // value method dmem_master_m_bready
  output dmem_master_bready;

  // value method dmem_master_m_arvalid
  output dmem_master_arvalid;

  // value method dmem_master_m_arid
  output [3 : 0] dmem_master_arid;

  // value method dmem_master_m_araddr
  output [63 : 0] dmem_master_araddr;

  // value method dmem_master_m_arlen
  output [7 : 0] dmem_master_arlen;

  // value method dmem_master_m_arsize
  output [2 : 0] dmem_master_arsize;

  // value method dmem_master_m_arburst
  output [1 : 0] dmem_master_arburst;

  // value method dmem_master_m_arlock
  output dmem_master_arlock;

  // value method dmem_master_m_arcache
  output [3 : 0] dmem_master_arcache;

  // value method dmem_master_m_arprot
  output [2 : 0] dmem_master_arprot;

  // value method dmem_master_m_arqos
  output [3 : 0] dmem_master_arqos;

  // value method dmem_master_m_arregion
  output [3 : 0] dmem_master_arregion;

  // value method dmem_master_m_aruser

  // action method dmem_master_m_arready
  input  dmem_master_arready;

  // action method dmem_master_m_rvalid
  input  dmem_master_rvalid;
  input  [3 : 0] dmem_master_rid;
  input  [63 : 0] dmem_master_rdata;
  input  [1 : 0] dmem_master_rresp;
  input  dmem_master_rlast;

  // value method dmem_master_m_rready
  output dmem_master_rready;

  // action method m_external_interrupt_req
  input  m_external_interrupt_req_set_not_clear;

  // action method s_external_interrupt_req
  input  s_external_interrupt_req_set_not_clear;

  // action method software_interrupt_req
  input  software_interrupt_req_set_not_clear;

  // action method timer_interrupt_req
  input  timer_interrupt_req_set_not_clear;

  // action method nmi_req
  input  nmi_req_set_not_clear;

  // action method set_verbosity
  input  [3 : 0] set_verbosity_verbosity;
  input  [63 : 0] set_verbosity_logdelay;
  input  EN_set_verbosity;
  output RDY_set_verbosity;

  // signals for module outputs
  wire [63 : 0] dmem_master_araddr,
		dmem_master_awaddr,
		dmem_master_wdata,
		imem_master_araddr,
		imem_master_awaddr,
		imem_master_wdata;
  wire [7 : 0] dmem_master_arlen,
	       dmem_master_awlen,
	       dmem_master_wstrb,
	       imem_master_arlen,
	       imem_master_awlen,
	       imem_master_wstrb;
  wire [3 : 0] dmem_master_arcache,
	       dmem_master_arid,
	       dmem_master_arqos,
	       dmem_master_arregion,
	       dmem_master_awcache,
	       dmem_master_awid,
	       dmem_master_awqos,
	       dmem_master_awregion,
	       imem_master_arcache,
	       imem_master_arid,
	       imem_master_arqos,
	       imem_master_arregion,
	       imem_master_awcache,
	       imem_master_awid,
	       imem_master_awqos,
	       imem_master_awregion;
  wire [2 : 0] dmem_master_arprot,
	       dmem_master_arsize,
	       dmem_master_awprot,
	       dmem_master_awsize,
	       imem_master_arprot,
	       imem_master_arsize,
	       imem_master_awprot,
	       imem_master_awsize;
  wire [1 : 0] dmem_master_arburst,
	       dmem_master_awburst,
	       imem_master_arburst,
	       imem_master_awburst;
  wire RDY_hart0_server_reset_request_put,
       RDY_hart0_server_reset_response_get,
       RDY_set_verbosity,
       dmem_master_arlock,
       dmem_master_arvalid,
       dmem_master_awlock,
       dmem_master_awvalid,
       dmem_master_bready,
       dmem_master_rready,
       dmem_master_wlast,
       dmem_master_wvalid,
       hart0_server_reset_response_get,
       imem_master_arlock,
       imem_master_arvalid,
       imem_master_awlock,
       imem_master_awvalid,
       imem_master_bready,
       imem_master_rready,
       imem_master_wlast,
       imem_master_wvalid;

  // register cfg_logdelay
  reg [63 : 0] cfg_logdelay;
  wire [63 : 0] cfg_logdelay$D_IN;
  wire cfg_logdelay$EN;

  // register cfg_verbosity
  reg [3 : 0] cfg_verbosity;
  wire [3 : 0] cfg_verbosity$D_IN;
  wire cfg_verbosity$EN;

  // register imem_c_rg_cache_addr
  reg [31 : 0] imem_c_rg_cache_addr;
  wire [31 : 0] imem_c_rg_cache_addr$D_IN;
  wire imem_c_rg_cache_addr$EN;

  // register imem_c_rg_cache_b16
  reg [16 : 0] imem_c_rg_cache_b16;
  reg [16 : 0] imem_c_rg_cache_b16$D_IN;
  wire imem_c_rg_cache_b16$EN;

  // register imem_c_rg_f3
  reg [2 : 0] imem_c_rg_f3;
  wire [2 : 0] imem_c_rg_f3$D_IN;
  wire imem_c_rg_f3$EN;

  // register imem_c_rg_mstatus_MXR
  reg imem_c_rg_mstatus_MXR;
  wire imem_c_rg_mstatus_MXR$D_IN, imem_c_rg_mstatus_MXR$EN;

  // register imem_c_rg_pc
  reg [31 : 0] imem_c_rg_pc;
  reg [31 : 0] imem_c_rg_pc$D_IN;
  wire imem_c_rg_pc$EN;

  // register imem_c_rg_priv
  reg [1 : 0] imem_c_rg_priv;
  wire [1 : 0] imem_c_rg_priv$D_IN;
  wire imem_c_rg_priv$EN;

  // register imem_c_rg_satp
  reg [31 : 0] imem_c_rg_satp;
  wire [31 : 0] imem_c_rg_satp$D_IN;
  wire imem_c_rg_satp$EN;

  // register imem_c_rg_sstatus_SUM
  reg imem_c_rg_sstatus_SUM;
  wire imem_c_rg_sstatus_SUM$D_IN, imem_c_rg_sstatus_SUM$EN;

  // register imem_c_rg_tval
  reg [31 : 0] imem_c_rg_tval;
  reg [31 : 0] imem_c_rg_tval$D_IN;
  wire imem_c_rg_tval$EN;

  // register rg_csr_pc
  reg [31 : 0] rg_csr_pc;
  wire [31 : 0] rg_csr_pc$D_IN;
  wire rg_csr_pc$EN;

  // register rg_csr_val1
  reg [31 : 0] rg_csr_val1;
  wire [31 : 0] rg_csr_val1$D_IN;
  wire rg_csr_val1$EN;

  // register rg_cur_priv
  reg [1 : 0] rg_cur_priv;
  reg [1 : 0] rg_cur_priv$D_IN;
  wire rg_cur_priv$EN;

  // register rg_mstatus_MXR
  reg rg_mstatus_MXR;
  wire rg_mstatus_MXR$D_IN, rg_mstatus_MXR$EN;

  // register rg_next_pc
  reg [31 : 0] rg_next_pc;
  reg [31 : 0] rg_next_pc$D_IN;
  wire rg_next_pc$EN;

  // register rg_run_on_reset
  reg rg_run_on_reset;
  wire rg_run_on_reset$D_IN, rg_run_on_reset$EN;

  // register rg_sstatus_SUM
  reg rg_sstatus_SUM;
  wire rg_sstatus_SUM$D_IN, rg_sstatus_SUM$EN;

  // register rg_start_CPI_cycles
  reg [63 : 0] rg_start_CPI_cycles;
  wire [63 : 0] rg_start_CPI_cycles$D_IN;
  wire rg_start_CPI_cycles$EN;

  // register rg_start_CPI_instrs
  reg [63 : 0] rg_start_CPI_instrs;
  wire [63 : 0] rg_start_CPI_instrs$D_IN;
  wire rg_start_CPI_instrs$EN;

  // register rg_state
  reg [3 : 0] rg_state;
  reg [3 : 0] rg_state$D_IN;
  wire rg_state$EN;

  // register rg_trap_info
  reg [67 : 0] rg_trap_info;
  reg [67 : 0] rg_trap_info$D_IN;
  wire rg_trap_info$EN;

  // register rg_trap_instr
  reg [31 : 0] rg_trap_instr;
  wire [31 : 0] rg_trap_instr$D_IN;
  wire rg_trap_instr$EN;

  // register rg_trap_interrupt
  reg rg_trap_interrupt;
  wire rg_trap_interrupt$D_IN, rg_trap_interrupt$EN;

  // register stage1_rg_full
  reg stage1_rg_full;
  reg stage1_rg_full$D_IN;
  wire stage1_rg_full$EN;

  // register stage2_rg_full
  reg stage2_rg_full;
  reg stage2_rg_full$D_IN;
  wire stage2_rg_full$EN;

  // register stage2_rg_resetting
  reg stage2_rg_resetting;
  wire stage2_rg_resetting$D_IN, stage2_rg_resetting$EN;

  // register stage2_rg_stage2
  reg [169 : 0] stage2_rg_stage2;
  wire [169 : 0] stage2_rg_stage2$D_IN;
  wire stage2_rg_stage2$EN;

  // register stage3_rg_full
  reg stage3_rg_full;
  reg stage3_rg_full$D_IN;
  wire stage3_rg_full$EN;

  // register stage3_rg_stage3
  reg [103 : 0] stage3_rg_stage3;
  wire [103 : 0] stage3_rg_stage3$D_IN;
  wire stage3_rg_stage3$EN;

  // ports of submodule csr_regfile
  wire [97 : 0] csr_regfile$csr_trap_actions;
  wire [65 : 0] csr_regfile$csr_ret_actions;
  wire [63 : 0] csr_regfile$read_csr_mcycle, csr_regfile$read_csr_minstret;
  wire [32 : 0] csr_regfile$read_csr;
  wire [31 : 0] csr_regfile$csr_trap_actions_pc,
		csr_regfile$csr_trap_actions_xtval,
		csr_regfile$mav_csr_write_word,
		csr_regfile$read_mstatus,
		csr_regfile$read_satp;
  wire [27 : 0] csr_regfile$read_misa;
  wire [11 : 0] csr_regfile$access_permitted_1_csr_addr,
		csr_regfile$access_permitted_2_csr_addr,
		csr_regfile$csr_counter_read_fault_csr_addr,
		csr_regfile$mav_csr_write_csr_addr,
		csr_regfile$mav_read_csr_csr_addr,
		csr_regfile$read_csr_csr_addr,
		csr_regfile$read_csr_port2_csr_addr;
  wire [4 : 0] csr_regfile$interrupt_pending;
  wire [3 : 0] csr_regfile$csr_trap_actions_exc_code;
  wire [1 : 0] csr_regfile$access_permitted_1_priv,
	       csr_regfile$access_permitted_2_priv,
	       csr_regfile$csr_counter_read_fault_priv,
	       csr_regfile$csr_ret_actions_from_priv,
	       csr_regfile$csr_trap_actions_from_priv,
	       csr_regfile$interrupt_pending_cur_priv;
  wire csr_regfile$EN_csr_minstret_incr,
       csr_regfile$EN_csr_ret_actions,
       csr_regfile$EN_csr_trap_actions,
       csr_regfile$EN_debug,
       csr_regfile$EN_mav_csr_write,
       csr_regfile$EN_mav_read_csr,
       csr_regfile$EN_server_reset_request_put,
       csr_regfile$EN_server_reset_response_get,
       csr_regfile$RDY_server_reset_request_put,
       csr_regfile$RDY_server_reset_response_get,
       csr_regfile$access_permitted_1,
       csr_regfile$access_permitted_1_read_not_write,
       csr_regfile$access_permitted_2,
       csr_regfile$access_permitted_2_read_not_write,
       csr_regfile$csr_trap_actions_interrupt,
       csr_regfile$csr_trap_actions_nmi,
       csr_regfile$m_external_interrupt_req_set_not_clear,
       csr_regfile$nmi_pending,
       csr_regfile$nmi_req_set_not_clear,
       csr_regfile$s_external_interrupt_req_set_not_clear,
       csr_regfile$software_interrupt_req_set_not_clear,
       csr_regfile$timer_interrupt_req_set_not_clear,
       csr_regfile$wfi_resume;

  // ports of submodule f_reset_reqs
  wire f_reset_reqs$CLR,
       f_reset_reqs$DEQ,
       f_reset_reqs$D_IN,
       f_reset_reqs$D_OUT,
       f_reset_reqs$EMPTY_N,
       f_reset_reqs$ENQ,
       f_reset_reqs$FULL_N;

  // ports of submodule f_reset_rsps
  wire f_reset_rsps$CLR,
       f_reset_rsps$DEQ,
       f_reset_rsps$D_IN,
       f_reset_rsps$D_OUT,
       f_reset_rsps$EMPTY_N,
       f_reset_rsps$ENQ,
       f_reset_rsps$FULL_N;

  // ports of submodule gpr_regfile
  wire [31 : 0] gpr_regfile$read_rs1,
		gpr_regfile$read_rs2,
		gpr_regfile$write_rd_rd_val;
  wire [4 : 0] gpr_regfile$read_rs1_port2_rs1,
	       gpr_regfile$read_rs1_rs1,
	       gpr_regfile$read_rs2_rs2,
	       gpr_regfile$write_rd_rd;
  wire gpr_regfile$EN_server_reset_request_put,
       gpr_regfile$EN_server_reset_response_get,
       gpr_regfile$EN_write_rd,
       gpr_regfile$RDY_server_reset_request_put,
       gpr_regfile$RDY_server_reset_response_get;

  // ports of submodule near_mem
  reg [31 : 0] near_mem$imem_req_addr;
  reg [1 : 0] near_mem$dmem_req_op;
  reg near_mem$imem_req_mstatus_MXR, near_mem$imem_req_sstatus_SUM;
  wire [63 : 0] near_mem$dmem_master_araddr,
		near_mem$dmem_master_awaddr,
		near_mem$dmem_master_rdata,
		near_mem$dmem_master_wdata,
		near_mem$dmem_req_store_value,
		near_mem$dmem_word64,
		near_mem$imem_master_araddr,
		near_mem$imem_master_awaddr,
		near_mem$imem_master_rdata,
		near_mem$imem_master_wdata;
  wire [31 : 0] near_mem$dmem_req_addr,
		near_mem$dmem_req_satp,
		near_mem$imem_instr,
		near_mem$imem_pc,
		near_mem$imem_req_satp;
  wire [7 : 0] near_mem$dmem_master_arlen,
	       near_mem$dmem_master_awlen,
	       near_mem$dmem_master_wstrb,
	       near_mem$imem_master_arlen,
	       near_mem$imem_master_awlen,
	       near_mem$imem_master_wstrb,
	       near_mem$server_fence_request_put;
  wire [6 : 0] near_mem$dmem_req_amo_funct7;
  wire [3 : 0] near_mem$dmem_exc_code,
	       near_mem$dmem_master_arcache,
	       near_mem$dmem_master_arid,
	       near_mem$dmem_master_arqos,
	       near_mem$dmem_master_arregion,
	       near_mem$dmem_master_awcache,
	       near_mem$dmem_master_awid,
	       near_mem$dmem_master_awqos,
	       near_mem$dmem_master_awregion,
	       near_mem$dmem_master_bid,
	       near_mem$dmem_master_rid,
	       near_mem$imem_exc_code,
	       near_mem$imem_master_arcache,
	       near_mem$imem_master_arid,
	       near_mem$imem_master_arqos,
	       near_mem$imem_master_arregion,
	       near_mem$imem_master_awcache,
	       near_mem$imem_master_awid,
	       near_mem$imem_master_awqos,
	       near_mem$imem_master_awregion,
	       near_mem$imem_master_bid,
	       near_mem$imem_master_rid;
  wire [2 : 0] near_mem$dmem_master_arprot,
	       near_mem$dmem_master_arsize,
	       near_mem$dmem_master_awprot,
	       near_mem$dmem_master_awsize,
	       near_mem$dmem_req_f3,
	       near_mem$imem_master_arprot,
	       near_mem$imem_master_arsize,
	       near_mem$imem_master_awprot,
	       near_mem$imem_master_awsize,
	       near_mem$imem_req_f3;
  wire [1 : 0] near_mem$dmem_master_arburst,
	       near_mem$dmem_master_awburst,
	       near_mem$dmem_master_bresp,
	       near_mem$dmem_master_rresp,
	       near_mem$dmem_req_priv,
	       near_mem$imem_master_arburst,
	       near_mem$imem_master_awburst,
	       near_mem$imem_master_bresp,
	       near_mem$imem_master_rresp,
	       near_mem$imem_req_priv;
  wire near_mem$EN_dmem_req,
       near_mem$EN_imem_req,
       near_mem$EN_server_fence_i_request_put,
       near_mem$EN_server_fence_i_response_get,
       near_mem$EN_server_fence_request_put,
       near_mem$EN_server_fence_response_get,
       near_mem$EN_server_reset_request_put,
       near_mem$EN_server_reset_response_get,
       near_mem$EN_sfence_vma,
       near_mem$RDY_server_fence_i_request_put,
       near_mem$RDY_server_fence_i_response_get,
       near_mem$RDY_server_fence_request_put,
       near_mem$RDY_server_fence_response_get,
       near_mem$RDY_server_reset_request_put,
       near_mem$RDY_server_reset_response_get,
       near_mem$dmem_exc,
       near_mem$dmem_master_arlock,
       near_mem$dmem_master_arready,
       near_mem$dmem_master_arvalid,
       near_mem$dmem_master_awlock,
       near_mem$dmem_master_awready,
       near_mem$dmem_master_awvalid,
       near_mem$dmem_master_bready,
       near_mem$dmem_master_bvalid,
       near_mem$dmem_master_rlast,
       near_mem$dmem_master_rready,
       near_mem$dmem_master_rvalid,
       near_mem$dmem_master_wlast,
       near_mem$dmem_master_wready,
       near_mem$dmem_master_wvalid,
       near_mem$dmem_req_mstatus_MXR,
       near_mem$dmem_req_sstatus_SUM,
       near_mem$dmem_valid,
       near_mem$imem_exc,
       near_mem$imem_is_i32_not_i16,
       near_mem$imem_master_arlock,
       near_mem$imem_master_arready,
       near_mem$imem_master_arvalid,
       near_mem$imem_master_awlock,
       near_mem$imem_master_awready,
       near_mem$imem_master_awvalid,
       near_mem$imem_master_bready,
       near_mem$imem_master_bvalid,
       near_mem$imem_master_rlast,
       near_mem$imem_master_rready,
       near_mem$imem_master_rvalid,
       near_mem$imem_master_wlast,
       near_mem$imem_master_wready,
       near_mem$imem_master_wvalid,
       near_mem$imem_valid;

  // ports of submodule soc_map
  wire [63 : 0] soc_map$m_is_IO_addr_addr,
		soc_map$m_is_mem_addr_addr,
		soc_map$m_is_near_mem_IO_addr_addr,
		soc_map$m_pc_reset_value;

  // ports of submodule stage1_f_reset_reqs
  wire stage1_f_reset_reqs$CLR,
       stage1_f_reset_reqs$DEQ,
       stage1_f_reset_reqs$EMPTY_N,
       stage1_f_reset_reqs$ENQ,
       stage1_f_reset_reqs$FULL_N;

  // ports of submodule stage1_f_reset_rsps
  wire stage1_f_reset_rsps$CLR,
       stage1_f_reset_rsps$DEQ,
       stage1_f_reset_rsps$EMPTY_N,
       stage1_f_reset_rsps$ENQ,
       stage1_f_reset_rsps$FULL_N;

  // ports of submodule stage2_f_reset_reqs
  wire stage2_f_reset_reqs$CLR,
       stage2_f_reset_reqs$DEQ,
       stage2_f_reset_reqs$EMPTY_N,
       stage2_f_reset_reqs$ENQ,
       stage2_f_reset_reqs$FULL_N;

  // ports of submodule stage2_f_reset_rsps
  wire stage2_f_reset_rsps$CLR,
       stage2_f_reset_rsps$DEQ,
       stage2_f_reset_rsps$EMPTY_N,
       stage2_f_reset_rsps$ENQ,
       stage2_f_reset_rsps$FULL_N;

  // ports of submodule stage2_mbox
  wire [31 : 0] stage2_mbox$req_v1, stage2_mbox$req_v2, stage2_mbox$word;
  wire [3 : 0] stage2_mbox$set_verbosity_verbosity;
  wire [2 : 0] stage2_mbox$req_f3;
  wire stage2_mbox$EN_req,
       stage2_mbox$EN_req_reset,
       stage2_mbox$EN_rsp_reset,
       stage2_mbox$EN_set_verbosity,
       stage2_mbox$req_is_OP_not_OP_32,
       stage2_mbox$valid;

  // ports of submodule stage3_f_reset_reqs
  wire stage3_f_reset_reqs$CLR,
       stage3_f_reset_reqs$DEQ,
       stage3_f_reset_reqs$EMPTY_N,
       stage3_f_reset_reqs$ENQ,
       stage3_f_reset_reqs$FULL_N;

  // ports of submodule stage3_f_reset_rsps
  wire stage3_f_reset_rsps$CLR,
       stage3_f_reset_rsps$DEQ,
       stage3_f_reset_rsps$EMPTY_N,
       stage3_f_reset_rsps$ENQ,
       stage3_f_reset_rsps$FULL_N;

  // rule scheduling signals
  wire CAN_FIRE_RL_imem_c_rl_assert_fail,
       CAN_FIRE_RL_imem_c_rl_fetch_next_32b,
       CAN_FIRE_RL_rl_WFI_resume,
       CAN_FIRE_RL_rl_finish_FENCE,
       CAN_FIRE_RL_rl_finish_FENCE_I,
       CAN_FIRE_RL_rl_finish_SFENCE_VMA,
       CAN_FIRE_RL_rl_pipe,
       CAN_FIRE_RL_rl_reset_complete,
       CAN_FIRE_RL_rl_reset_from_WFI,
       CAN_FIRE_RL_rl_reset_start,
       CAN_FIRE_RL_rl_show_pipe,
       CAN_FIRE_RL_rl_stage1_CSRR_S_or_C,
       CAN_FIRE_RL_rl_stage1_CSRR_S_or_C_2,
       CAN_FIRE_RL_rl_stage1_CSRR_W,
       CAN_FIRE_RL_rl_stage1_CSRR_W_2,
       CAN_FIRE_RL_rl_stage1_FENCE,
       CAN_FIRE_RL_rl_stage1_FENCE_I,
       CAN_FIRE_RL_rl_stage1_WFI,
       CAN_FIRE_RL_rl_stage1_interrupt,
       CAN_FIRE_RL_rl_stage1_restart_after_csrrx,
       CAN_FIRE_RL_rl_stage1_trap,
       CAN_FIRE_RL_rl_stage1_xRET,
       CAN_FIRE_RL_rl_stage2_nonpipe,
       CAN_FIRE_RL_rl_trap,
       CAN_FIRE_RL_rl_trap_fetch,
       CAN_FIRE_RL_stage1_rl_reset,
       CAN_FIRE_RL_stage2_rl_reset_begin,
       CAN_FIRE_RL_stage2_rl_reset_end,
       CAN_FIRE_RL_stage3_rl_reset,
       CAN_FIRE_dmem_master_m_arready,
       CAN_FIRE_dmem_master_m_awready,
       CAN_FIRE_dmem_master_m_bvalid,
       CAN_FIRE_dmem_master_m_rvalid,
       CAN_FIRE_dmem_master_m_wready,
       CAN_FIRE_hart0_server_reset_request_put,
       CAN_FIRE_hart0_server_reset_response_get,
       CAN_FIRE_imem_master_m_arready,
       CAN_FIRE_imem_master_m_awready,
       CAN_FIRE_imem_master_m_bvalid,
       CAN_FIRE_imem_master_m_rvalid,
       CAN_FIRE_imem_master_m_wready,
       CAN_FIRE_m_external_interrupt_req,
       CAN_FIRE_nmi_req,
       CAN_FIRE_s_external_interrupt_req,
       CAN_FIRE_set_verbosity,
       CAN_FIRE_software_interrupt_req,
       CAN_FIRE_timer_interrupt_req,
       WILL_FIRE_RL_imem_c_rl_assert_fail,
       WILL_FIRE_RL_imem_c_rl_fetch_next_32b,
       WILL_FIRE_RL_rl_WFI_resume,
       WILL_FIRE_RL_rl_finish_FENCE,
       WILL_FIRE_RL_rl_finish_FENCE_I,
       WILL_FIRE_RL_rl_finish_SFENCE_VMA,
       WILL_FIRE_RL_rl_pipe,
       WILL_FIRE_RL_rl_reset_complete,
       WILL_FIRE_RL_rl_reset_from_WFI,
       WILL_FIRE_RL_rl_reset_start,
       WILL_FIRE_RL_rl_show_pipe,
       WILL_FIRE_RL_rl_stage1_CSRR_S_or_C,
       WILL_FIRE_RL_rl_stage1_CSRR_S_or_C_2,
       WILL_FIRE_RL_rl_stage1_CSRR_W,
       WILL_FIRE_RL_rl_stage1_CSRR_W_2,
       WILL_FIRE_RL_rl_stage1_FENCE,
       WILL_FIRE_RL_rl_stage1_FENCE_I,
       WILL_FIRE_RL_rl_stage1_WFI,
       WILL_FIRE_RL_rl_stage1_interrupt,
       WILL_FIRE_RL_rl_stage1_restart_after_csrrx,
       WILL_FIRE_RL_rl_stage1_trap,
       WILL_FIRE_RL_rl_stage1_xRET,
       WILL_FIRE_RL_rl_stage2_nonpipe,
       WILL_FIRE_RL_rl_trap,
       WILL_FIRE_RL_rl_trap_fetch,
       WILL_FIRE_RL_stage1_rl_reset,
       WILL_FIRE_RL_stage2_rl_reset_begin,
       WILL_FIRE_RL_stage2_rl_reset_end,
       WILL_FIRE_RL_stage3_rl_reset,
       WILL_FIRE_dmem_master_m_arready,
       WILL_FIRE_dmem_master_m_awready,
       WILL_FIRE_dmem_master_m_bvalid,
       WILL_FIRE_dmem_master_m_rvalid,
       WILL_FIRE_dmem_master_m_wready,
       WILL_FIRE_hart0_server_reset_request_put,
       WILL_FIRE_hart0_server_reset_response_get,
       WILL_FIRE_imem_master_m_arready,
       WILL_FIRE_imem_master_m_awready,
       WILL_FIRE_imem_master_m_bvalid,
       WILL_FIRE_imem_master_m_rvalid,
       WILL_FIRE_imem_master_m_wready,
       WILL_FIRE_m_external_interrupt_req,
       WILL_FIRE_nmi_req,
       WILL_FIRE_s_external_interrupt_req,
       WILL_FIRE_set_verbosity,
       WILL_FIRE_software_interrupt_req,
       WILL_FIRE_timer_interrupt_req;

  // inputs to muxes for submodule ports
  reg [31 : 0] MUX_csr_regfile$mav_csr_write_2__VAL_2;
  wire [67 : 0] MUX_rg_trap_info$write_1__VAL_1,
		MUX_rg_trap_info$write_1__VAL_2,
		MUX_rg_trap_info$write_1__VAL_3,
		MUX_rg_trap_info$write_1__VAL_4;
  wire [31 : 0] MUX_imem_c_rg_tval$write_1__VAL_5,
		MUX_near_mem$imem_req_2__VAL_1,
		MUX_near_mem$imem_req_2__VAL_2,
		MUX_near_mem$imem_req_2__VAL_5;
  wire [16 : 0] MUX_imem_c_rg_cache_b16$write_1__VAL_1;
  wire [3 : 0] MUX_rg_state$write_1__VAL_1,
	       MUX_rg_state$write_1__VAL_2,
	       MUX_rg_state$write_1__VAL_3;
  wire MUX_csr_regfile$mav_csr_write_1__SEL_1,
       MUX_gpr_regfile$write_rd_1__SEL_3,
       MUX_imem_c_rg_cache_addr$write_1__SEL_2,
       MUX_imem_c_rg_cache_addr$write_1__SEL_3,
       MUX_imem_c_rg_cache_b16$write_1__SEL_10,
       MUX_imem_c_rg_cache_b16$write_1__SEL_5,
       MUX_imem_c_rg_cache_b16$write_1__SEL_6,
       MUX_imem_c_rg_cache_b16$write_1__SEL_7,
       MUX_imem_c_rg_cache_b16$write_1__SEL_8,
       MUX_imem_c_rg_cache_b16$write_1__SEL_9,
       MUX_imem_c_rg_f3$write_1__SEL_1,
       MUX_imem_c_rg_f3$write_1__SEL_2,
       MUX_imem_c_rg_mstatus_MXR$write_1__SEL_4,
       MUX_imem_c_rg_pc$write_1__SEL_4,
       MUX_near_mem$imem_req_1__SEL_6,
       MUX_rg_next_pc$write_1__SEL_1,
       MUX_rg_state$write_1__SEL_1,
       MUX_rg_state$write_1__SEL_10,
       MUX_rg_state$write_1__SEL_11,
       MUX_rg_state$write_1__SEL_12,
       MUX_rg_state$write_1__SEL_13,
       MUX_rg_state$write_1__SEL_4,
       MUX_rg_state$write_1__SEL_5,
       MUX_rg_state$write_1__SEL_6,
       MUX_rg_state$write_1__SEL_7,
       MUX_rg_state$write_1__SEL_8,
       MUX_rg_state$write_1__SEL_9,
       MUX_rg_trap_info$write_1__SEL_1,
       MUX_rg_trap_instr$write_1__SEL_1,
       MUX_rg_trap_interrupt$write_1__SEL_1,
       MUX_stage1_rg_full$write_1__VAL_2,
       MUX_stage2_rg_full$write_1__VAL_2,
       MUX_stage3_rg_full$write_1__VAL_2;

  // declarations used by system tasks
  // synopsys translate_off
  reg [31 : 0] v__h2079;
  reg [31 : 0] v__h2073;
  // synopsys translate_on

  // remaining internal signals
  reg [31 : 0] IF_IF_imem_c_rg_pc_BITS_1_TO_0_EQ_0b0_OR_NOT_i_ETC___d1011,
	       IF_IF_imem_c_rg_pc_BITS_1_TO_0_EQ_0b0_OR_NOT_i_ETC___d1085,
	       _theResult_____1_fst__h14028,
	       rs1_val__h21423,
	       x_out_bypass_rd_val__h7055,
	       x_out_data_to_stage2_addr__h12927,
	       x_out_data_to_stage2_val1__h12928,
	       x_out_data_to_stage3_rd_val__h6402;
  reg [4 : 0] x_out_bypass_rd__h7054, x_out_data_to_stage3_rd__h6401;
  reg [3 : 0] CASE_rg_cur_priv_0b0_8_0b1_9_11__q4,
	      CASE_theResult__859_BITS_31_TO_20_0b0_CASE_rg__ETC__q5,
	      alu_outputs_exc_code__h13589;
  reg [2 : 0] CASE_theResult__859_BITS_6_TO_0_0b1100011_0_0b_ETC__q14,
	      CASE_theResult__859_BITS_6_TO_0_0b11_1_0b10011_ETC__q13;
  reg CASE_stage2_rg_stage2_BITS_103_TO_101_1_NOT_ne_ETC__q15,
      CASE_theResult__859_BITS_6_TO_0_0b10011_IF_ime_ETC__q10,
      CASE_theResult__859_BITS_6_TO_0_0b10011_NOT_IF_ETC__q12,
      CASE_theResult__859_BITS_6_TO_0_0b10011_NOT_IF_ETC__q8,
      CASE_theResult__859_BITS_6_TO_0_0b11_NOT_theRe_ETC__q7,
      CASE_theResult__859_BITS_6_TO_0_0b11_theResult_ETC__q9,
      IF_IF_imem_c_rg_pc_BITS_1_TO_0_EQ_0b0_OR_NOT_i_ETC___d1344,
      IF_IF_imem_c_rg_pc_BITS_1_TO_0_EQ_0b0_OR_NOT_i_ETC___d581,
      IF_IF_imem_c_rg_pc_BITS_1_TO_0_EQ_0b0_OR_NOT_i_ETC___d675,
      IF_stage2_rg_stage2_1_BITS_103_TO_101_2_EQ_1_4_ETC___d1159,
      IF_stage2_rg_stage2_1_BITS_103_TO_101_2_EQ_1_4_ETC___d1196,
      IF_stage2_rg_stage2_1_BITS_103_TO_101_2_EQ_1_4_ETC___d122,
      IF_stage2_rg_stage2_1_BITS_103_TO_101_2_EQ_1_4_ETC___d144,
      IF_stage2_rg_stage2_1_BITS_103_TO_101_2_EQ_1_4_ETC___d152,
      IF_stage2_rg_stage2_1_BITS_103_TO_101_2_EQ_1_4_ETC___d183,
      IF_stage2_rg_stage2_1_BITS_103_TO_101_2_EQ_1_4_ETC___d188,
      IF_stage2_rg_stage2_1_BITS_103_TO_101_2_EQ_1_4_ETC___d196,
      IF_stage2_rg_stage2_1_BITS_103_TO_101_2_EQ_1_4_ETC___d200;
  wire [135 : 0] IF_imem_c_rg_pc_BITS_1_TO_0_EQ_0b0_OR_NOT_imem_ETC___d1227;
  wire [127 : 0] csr_regfile_read_csr_mcycle__5_MINUS_rg_start__ETC___d1374;
  wire [63 : 0] _theResult____h20140,
		cpi__h20142,
		cpifrac__h20143,
		delta_CPI_cycles__h20138,
		delta_CPI_instrs___1__h20184,
		delta_CPI_instrs__h20139,
		x__h20141;
  wire [35 : 0] IF_near_mem_imem_exc__29_THEN_near_mem_imem_ex_ETC___d1355;
  wire [31 : 0] IF_IF_imem_c_rg_pc_BITS_1_TO_0_EQ_0b0_OR_NOT_i_ETC___d1012,
		IF_IF_imem_c_rg_pc_BITS_1_TO_0_EQ_0b0_OR_NOT_i_ETC___d1013,
		IF_NOT_imem_c_rg_pc_BITS_1_TO_0_EQ_0b0_AND_ime_ETC___d265,
		IF_csr_regfile_read_csr_rg_trap_instr_371_BITS_ETC___d1429,
		IF_csr_regfile_read_misa__3_BIT_2_46_AND_IF_NO_ETC___d480,
		IF_csr_regfile_read_misa__3_BIT_2_46_AND_IF_NO_ETC___d482,
		IF_csr_regfile_read_misa__3_BIT_2_46_AND_IF_NO_ETC___d484,
		IF_csr_regfile_read_misa__3_BIT_2_46_AND_IF_NO_ETC___d485,
		IF_csr_regfile_read_misa__3_BIT_2_46_AND_IF_NO_ETC___d487,
		IF_csr_regfile_read_misa__3_BIT_2_46_AND_IF_NO_ETC___d488,
		IF_csr_regfile_read_misa__3_BIT_2_46_AND_IF_NO_ETC___d489,
		IF_csr_regfile_read_misa__3_BIT_2_46_AND_IF_NO_ETC___d491,
		IF_csr_regfile_read_misa__3_BIT_2_46_AND_IF_NO_ETC___d492,
		IF_csr_regfile_read_misa__3_BIT_2_46_AND_IF_NO_ETC___d493,
		IF_csr_regfile_read_misa__3_BIT_2_46_AND_IF_NO_ETC___d495,
		IF_csr_regfile_read_misa__3_BIT_2_46_AND_IF_NO_ETC___d496,
		IF_csr_regfile_read_misa__3_BIT_2_46_AND_IF_NO_ETC___d497,
		IF_csr_regfile_read_misa__3_BIT_2_46_AND_IF_NO_ETC___d498,
		IF_csr_regfile_read_misa__3_BIT_2_46_AND_IF_NO_ETC___d499,
		IF_csr_regfile_read_misa__3_BIT_2_46_AND_IF_NO_ETC___d500,
		IF_csr_regfile_read_misa__3_BIT_2_46_AND_IF_NO_ETC___d501,
		IF_csr_regfile_read_misa__3_BIT_2_46_AND_IF_NO_ETC___d502,
		IF_csr_regfile_read_misa__3_BIT_2_46_AND_IF_NO_ETC___d503,
		IF_imem_c_rg_pc_BITS_1_TO_0_EQ_0b0_AND_imem_c__ETC___d266,
		IF_imem_c_rg_pc_BITS_1_TO_0_EQ_0b0_OR_NOT_imem_ETC___d943,
		SEXT_IF_imem_c_rg_pc_BITS_1_TO_0_EQ_0b0_OR_NOT_ETC___d952,
		_theResult_____1_fst__h14021,
		_theResult_____1_fst__h14056,
		_theResult____h4859,
		_theResult___snd__h15372,
		addr_of_b32___1__h16950,
		addr_of_b32___1__h19177,
		addr_of_b32___1__h27508,
		addr_of_b32__h16844,
		addr_of_b32__h19071,
		addr_of_b32__h27402,
		alu_outputs___1_addr__h13103,
		alu_outputs___1_addr__h13124,
		alu_outputs___1_addr__h13150,
		alu_outputs___1_addr__h13353,
		alu_outputs___1_val1__h13250,
		alu_outputs___1_val1__h13286,
		alu_outputs___1_val1__h13552,
		alu_outputs___1_val1__h13572,
		branch_target__h13080,
		data_to_stage2_addr__h12919,
		data_to_stage2_val2__h12921,
		eaddr__h13323,
		fall_through_pc__h12722,
		instr___1__h7261,
		instr__h10078,
		instr__h10207,
		instr__h10644,
		instr__h10816,
		instr__h10989,
		instr__h11182,
		instr__h11375,
		instr__h11492,
		instr__h11670,
		instr__h11789,
		instr__h11884,
		instr__h12020,
		instr__h12156,
		instr__h12292,
		instr__h12630,
		instr__h4857,
		instr__h7564,
		instr__h7709,
		instr__h7901,
		instr__h8096,
		instr__h8325,
		instr__h8668,
		instr__h9058,
		instr__h9174,
		instr__h9239,
		instr__h9556,
		instr__h9894,
		instr_out___1__h7399,
		instr_out___1__h7431,
		next_pc___1__h14698,
		next_pc__h14696,
		rd_val___1__h14009,
		rd_val___1__h14017,
		rd_val___1__h14024,
		rd_val___1__h14031,
		rd_val___1__h14038,
		rd_val___1__h14045,
		rd_val__h12672,
		rd_val__h13293,
		rd_val__h13307,
		rd_val__h15268,
		rd_val__h15320,
		rd_val__h15342,
		rd_val__h7206,
		rs1_val__h20670,
		rs1_val_bypassed__h4867,
		rs2_val_bypassed__h4873,
		trap_info_tval__h14518,
		val__h12674,
		val__h7208,
		value__h14581,
		x_out_data_to_stage2_instr__h12924,
		x_out_data_to_stage2_val2__h12929,
		x_out_next_pc__h12736,
		y__h21701;
  wire [20 : 0] SEXT_IF_NOT_imem_c_rg_pc_BITS_1_TO_0_EQ_0b0_AN_ETC___d331,
		theResult__859_BIT_31_CONCAT_theResult__859_BI_ETC__q3;
  wire [19 : 0] imm20__h9946;
  wire [15 : 0] IF_imem_c_rg_pc_BITS_31_TO_2_0_EQ_near_mem_ime_ETC___d263,
		imem_c_rg_cache_b16_BITS_15_TO_0__q1;
  wire [12 : 0] SEXT_IF_NOT_imem_c_rg_pc_BITS_1_TO_0_EQ_0b0_AN_ETC___d360,
		theResult__859_BIT_31_CONCAT_theResult__859_BI_ETC__q2;
  wire [11 : 0] imm12__h10442,
		imm12__h10657,
		imm12__h10853,
		imm12__h11198,
		imm12__h7565,
		imm12__h7902,
		imm12__h9818,
		offset__h8272,
		theResult__859_BITS_31_TO_20__q11,
		theResult__859_BITS_31_TO_25_CONCAT_theResult__ETC__q6;
  wire [9 : 0] nzimm10__h10440, nzimm10__h10655;
  wire [8 : 0] offset__h9183;
  wire [7 : 0] offset__h7299;
  wire [6 : 0] offset__h7844;
  wire [5 : 0] imm6__h9816;
  wire [4 : 0] data_to_stage2_rd__h12918,
	       offset_BITS_4_TO_0___h7833,
	       offset_BITS_4_TO_0___h8264,
	       rd__h7904,
	       rs1__h7903,
	       shamt__h13237,
	       x_out_data_to_stage2_rd__h12926;
  wire [3 : 0] alu_outputs___1_exc_code__h13548,
	       cur_verbosity__h3469,
	       x_exc_code__h27688,
	       x_out_trap_info_exc_code__h14521;
  wire IF_IF_imem_c_rg_pc_BITS_1_TO_0_EQ_0b0_OR_NOT_i_ETC___d1153,
       IF_IF_imem_c_rg_pc_BITS_1_TO_0_EQ_0b0_OR_NOT_i_ETC___d1340,
       IF_IF_imem_c_rg_pc_BITS_1_TO_0_EQ_0b0_OR_NOT_i_ETC___d1347,
       IF_IF_imem_c_rg_pc_BITS_1_TO_0_EQ_0b0_OR_NOT_i_ETC___d570,
       IF_IF_imem_c_rg_pc_BITS_1_TO_0_EQ_0b0_OR_NOT_i_ETC___d572,
       IF_IF_imem_c_rg_pc_BITS_1_TO_0_EQ_0b0_OR_NOT_i_ETC___d574,
       IF_IF_imem_c_rg_pc_BITS_1_TO_0_EQ_0b0_OR_NOT_i_ETC___d666,
       IF_IF_imem_c_rg_pc_BITS_1_TO_0_EQ_0b0_OR_NOT_i_ETC___d669,
       IF_IF_imem_c_rg_pc_BITS_1_TO_0_EQ_0b0_OR_NOT_i_ETC___d680,
       IF_IF_imem_c_rg_pc_BITS_1_TO_0_EQ_0b0_OR_NOT_i_ETC___d727,
       IF_IF_imem_c_rg_pc_BITS_1_TO_0_EQ_0b0_OR_NOT_i_ETC___d729,
       IF_imem_c_rg_pc_BITS_1_TO_0_EQ_0b0_OR_NOT_imem_ETC___d700,
       IF_imem_c_rg_pc_BITS_1_TO_0_EQ_0b0_OR_NOT_imem_ETC___d801,
       IF_imem_c_rg_pc_BITS_1_TO_0_EQ_0b0_OR_NOT_imem_ETC___d821,
       IF_stage2_rg_full_0_THEN_IF_stage2_rg_stage2_1_ETC___d507,
       IF_stage2_rg_full_0_THEN_IF_stage2_rg_stage2_1_ETC___d509,
       NOT_IF_NOT_stage1_rg_full_06_07_OR_NOT_near_me_ETC___d1302,
       NOT_IF_csr_regfile_read_csr_minstret__8_ULT_cf_ETC___d44,
       NOT_IF_imem_c_rg_pc_BITS_1_TO_0_EQ_0b0_OR_NOT__ETC___d611,
       NOT_IF_imem_c_rg_pc_BITS_1_TO_0_EQ_0b0_OR_NOT__ETC___d661,
       NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d1189,
       NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d1213,
       NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d1238,
       NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d1256,
       NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d1258,
       NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d1260,
       NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d1262,
       NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d1264,
       NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d1266,
       NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d1272,
       NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d1275,
       NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d1287,
       NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d1292,
       NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d1318,
       NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d1327,
       NOT_imem_c_rg_pc_BITS_1_TO_0_EQ_0b0_AND_imem_c_ETC___d1289,
       NOT_imem_c_rg_pc_BITS_1_TO_0_EQ_0b0_AND_imem_c_ETC___d250,
       NOT_imem_c_rg_pc_BITS_1_TO_0_EQ_0b0_AND_imem_c_ETC___d519,
       NOT_imem_c_rg_pc_BITS_1_TO_0_EQ_0b0_AND_imem_c_ETC___d521,
       NOT_imem_c_rg_pc_BITS_31_TO_2_0_EQ_imem_c_rg_c_ETC___d1167,
       NOT_near_mem_imem_exc__29_85_AND_IF_imem_c_rg__ETC___d755,
       NOT_near_mem_imem_exc__29_85_AND_IF_imem_c_rg__ETC___d769,
       NOT_near_mem_imem_valid_08_OR_imem_c_rg_pc_BIT_ETC___d1178,
       NOT_near_mem_imem_valid_08_OR_imem_c_rg_pc_BIT_ETC___d1186,
       NOT_near_mem_imem_valid_08_OR_imem_c_rg_pc_BIT_ETC___d1267,
       NOT_near_mem_imem_valid_08_OR_imem_c_rg_pc_BIT_ETC___d1269,
       NOT_rg_cur_priv_6_EQ_0b11_96_53_AND_NOT_rg_cur_ETC___d869,
       NOT_rg_next_pc_453_BITS_1_TO_0_454_EQ_0b0_455__ETC___d1462,
       NOT_soc_map_m_pc_reset_value__129_BITS_1_TO_0__ETC___d1141,
       NOT_stage1_rg_full_06_07_OR_near_mem_imem_vali_ETC___d1358,
       NOT_stage2_rg_full_0_41_OR_stage2_rg_stage2_1__ETC___d527,
       NOT_stage2_rg_full_0_41_OR_stage2_rg_stage2_1__ETC___d735,
       NOT_stage2_rg_full_0_41_OR_stage2_rg_stage2_1__ETC___d736,
       NOT_stage2_rg_full_0_41_OR_stage2_rg_stage2_1__ETC___d804,
       NOT_stage2_rg_full_0_41_OR_stage2_rg_stage2_1__ETC___d824,
       NOT_stage2_rg_full_0_41_OR_stage2_rg_stage2_1__ETC___d890,
       NOT_stage2_rg_stage2_1_BITS_103_TO_101_2_EQ_0__ETC___d126,
       NOT_stage2_rg_stage2_1_BITS_103_TO_101_2_EQ_1__ETC___d146,
       csr_regfile_RDY_server_reset_response_get__109_ETC___d1124,
       csr_regfile_interrupt_pending_rg_cur_priv_6_14_ETC___d1158,
       csr_regfile_interrupt_pending_rg_cur_priv_6_14_ETC___d1162,
       csr_regfile_interrupt_pending_rg_cur_priv_6_14_ETC___d1170,
       csr_regfile_read_misa__3_BIT_2_46_AND_IF_NOT_i_ETC___d345,
       csr_regfile_read_misa__3_BIT_2_46_AND_IF_NOT_i_ETC___d351,
       gpr_regfile_RDY_server_reset_request_put__089__ETC___d1101,
       imem_c_rg_pc_BITS_1_TO_0_EQ_0b0_OR_NOT_imem_c__ETC___d1282,
       imem_c_rg_pc_BITS_1_TO_0_EQ_0b0_OR_NOT_imem_c__ETC___d1284,
       imem_c_rg_pc_BITS_1_TO_0_EQ_0b0_OR_NOT_imem_c__ETC___d235,
       imem_c_rg_pc_BITS_1_TO_0_EQ_0b0_OR_NOT_imem_c__ETC___d243,
       imem_c_rg_pc_BITS_1_TO_0_EQ_0b0_OR_NOT_near_me_ETC___d1118,
       imem_c_rg_pc_BITS_31_TO_2_0_EQ_imem_c_rg_cache_ETC___d211,
       imem_c_rg_pc_BITS_31_TO_2_0_EQ_near_mem_imem_p_ETC___d13,
       imem_c_rg_pc_BITS_31_TO_2_0_EQ_near_mem_imem_p_ETC___d260,
       near_mem_imem_exc__29_OR_IF_IF_imem_c_rg_pc_BI_ETC___d1024,
       near_mem_imem_exc__29_OR_IF_IF_imem_c_rg_pc_BI_ETC___d1027,
       near_mem_imem_exc__29_OR_IF_IF_imem_c_rg_pc_BI_ETC___d1030,
       near_mem_imem_exc__29_OR_IF_IF_imem_c_rg_pc_BI_ETC___d1033,
       near_mem_imem_exc__29_OR_IF_IF_imem_c_rg_pc_BI_ETC___d1036,
       near_mem_imem_exc__29_OR_IF_IF_imem_c_rg_pc_BI_ETC___d1039,
       near_mem_imem_exc__29_OR_IF_IF_imem_c_rg_pc_BI_ETC___d1042,
       near_mem_imem_exc__29_OR_IF_IF_imem_c_rg_pc_BI_ETC___d1045,
       near_mem_imem_exc__29_OR_IF_IF_imem_c_rg_pc_BI_ETC___d1048,
       near_mem_imem_pc__1_EQ_imem_c_rg_pc_PLUS_2_14___d215,
       near_mem_imem_valid_AND_NOT_imem_c_rg_pc_BITS__ETC___d1214,
       near_mem_imem_valid_AND_NOT_imem_c_rg_pc_BITS__ETC___d1331,
       near_mem_imem_valid_AND_NOT_imem_c_rg_pc_BITS__ETC___d683,
       near_mem_imem_valid_AND_NOT_imem_c_rg_pc_BITS__ETC___d733,
       near_mem_imem_valid_AND_NOT_imem_c_rg_pc_BITS__ETC___d740,
       near_mem_imem_valid_AND_NOT_imem_c_rg_pc_BITS__ETC___d760,
       near_mem_imem_valid_AND_NOT_imem_c_rg_pc_BITS__ETC___d774,
       near_mem_imem_valid_AND_NOT_imem_c_rg_pc_BITS__ETC___d783,
       near_mem_imem_valid_AND_NOT_imem_c_rg_pc_BITS__ETC___d791,
       near_mem_imem_valid_AND_NOT_imem_c_rg_pc_BITS__ETC___d808,
       near_mem_imem_valid_AND_NOT_imem_c_rg_pc_BITS__ETC___d828,
       near_mem_imem_valid_AND_NOT_imem_c_rg_pc_BITS__ETC___d883,
       near_mem_imem_valid_AND_NOT_imem_c_rg_pc_BITS__ETC___d892,
       near_mem_imem_valid_AND_NOT_imem_c_rg_pc_BITS__ETC___d896,
       near_mem_imem_valid_AND_NOT_imem_c_rg_pc_BITS__ETC___d900,
       near_mem_imem_valid_AND_NOT_imem_c_rg_pc_BITS__ETC___d904,
       near_mem_imem_valid_AND_NOT_imem_c_rg_pc_BITS__ETC___d924,
       rg_cur_priv_6_EQ_0b11_96_OR_rg_cur_priv_6_EQ_0_ETC___d819,
       rg_state_5_EQ_3_172_AND_NOT_csr_regfile_interr_ETC___d1330,
       rg_state_5_EQ_3_172_AND_NOT_csr_regfile_interr_ETC___d1387,
       rg_state_5_EQ_3_172_AND_NOT_csr_regfile_interr_ETC___d1390,
       rg_state_5_EQ_3_172_AND_stage3_rg_full_1_OR_st_ETC___d1192,
       rg_trap_info_360_BITS_67_TO_36_361_EQ_csr_regf_ETC___d1370,
       stage1_rg_full_06_AND_NOT_near_mem_imem_valid__ETC___d517,
       stage1_rg_full_06_AND_imem_c_rg_pc_BITS_31_TO__ETC___d1155,
       stage2_rg_full_0_AND_IF_stage2_rg_stage2_1_BIT_ETC___d1205,
       stage2_rg_full_0_AND_NOT_stage2_rg_stage2_1_BI_ETC___d120,
       stage2_rg_full_0_AND_NOT_stage2_rg_stage2_1_BI_ETC___d511,
       stage2_rg_full_0_AND_NOT_stage2_rg_stage2_1_BI_ETC___d732,
       stage2_rg_full_0_AND_NOT_stage2_rg_stage2_1_BI_ETC___d746,
       stage2_rg_full_0_AND_NOT_stage2_rg_stage2_1_BI_ETC___d757,
       stage2_rg_full_0_AND_NOT_stage2_rg_stage2_1_BI_ETC___d758,
       stage2_rg_full_0_AND_NOT_stage2_rg_stage2_1_BI_ETC___d771,
       stage2_rg_full_0_AND_NOT_stage2_rg_stage2_1_BI_ETC___d772,
       stage2_rg_full_0_AND_NOT_stage2_rg_stage2_1_BI_ETC___d780,
       stage2_rg_full_0_AND_NOT_stage2_rg_stage2_1_BI_ETC___d781,
       stage2_rg_full_0_AND_NOT_stage2_rg_stage2_1_BI_ETC___d788,
       stage2_rg_full_0_AND_NOT_stage2_rg_stage2_1_BI_ETC___d789,
       stage2_rg_full_0_AND_NOT_stage2_rg_stage2_1_BI_ETC___d806,
       stage2_rg_full_0_AND_NOT_stage2_rg_stage2_1_BI_ETC___d826,
       stage2_rg_full_0_AND_NOT_stage2_rg_stage2_1_BI_ETC___d860,
       stage2_rg_full_0_AND_NOT_stage2_rg_stage2_1_BI_ETC___d874,
       stage2_rg_full_0_AND_NOT_stage2_rg_stage2_1_BI_ETC___d877,
       stage2_rg_full_0_AND_NOT_stage2_rg_stage2_1_BI_ETC___d879,
       stage2_rg_full_0_AND_NOT_stage2_rg_stage2_1_BI_ETC___d881,
       stage2_rg_full_0_AND_NOT_stage2_rg_stage2_1_BI_ETC___d914,
       stage2_rg_full_0_AND_NOT_stage2_rg_stage2_1_BI_ETC___d921,
       stage2_rg_full_0_AND_stage2_rg_stage2_1_BITS_1_ETC___d1202,
       stage2_rg_full_0_AND_stage2_rg_stage2_1_BITS_1_ETC___d1207,
       stage2_rg_full_0_AND_stage2_rg_stage2_1_BITS_1_ETC___d140,
       stage2_rg_full_0_AND_stage2_rg_stage2_1_BITS_1_ETC___d554,
       stage2_rg_stage2_1_BITS_103_TO_101_2_EQ_0_3_OR_ETC___d138,
       stage3_rg_full_1_OR_NOT_stage2_rg_full_0_41_OR_ETC___d1181;

  // action method hart0_server_reset_request_put
  assign RDY_hart0_server_reset_request_put = f_reset_reqs$FULL_N ;
  assign CAN_FIRE_hart0_server_reset_request_put = f_reset_reqs$FULL_N ;
  assign WILL_FIRE_hart0_server_reset_request_put =
	     EN_hart0_server_reset_request_put ;

  // actionvalue method hart0_server_reset_response_get
  assign hart0_server_reset_response_get = f_reset_rsps$D_OUT ;
  assign RDY_hart0_server_reset_response_get = f_reset_rsps$EMPTY_N ;
  assign CAN_FIRE_hart0_server_reset_response_get = f_reset_rsps$EMPTY_N ;
  assign WILL_FIRE_hart0_server_reset_response_get =
	     EN_hart0_server_reset_response_get ;

  // value method imem_master_m_awvalid
  assign imem_master_awvalid = near_mem$imem_master_awvalid ;

  // value method imem_master_m_awid
  assign imem_master_awid = near_mem$imem_master_awid ;

  // value method imem_master_m_awaddr
  assign imem_master_awaddr = near_mem$imem_master_awaddr ;

  // value method imem_master_m_awlen
  assign imem_master_awlen = near_mem$imem_master_awlen ;

  // value method imem_master_m_awsize
  assign imem_master_awsize = near_mem$imem_master_awsize ;

  // value method imem_master_m_awburst
  assign imem_master_awburst = near_mem$imem_master_awburst ;

  // value method imem_master_m_awlock
  assign imem_master_awlock = near_mem$imem_master_awlock ;

  // value method imem_master_m_awcache
  assign imem_master_awcache = near_mem$imem_master_awcache ;

  // value method imem_master_m_awprot
  assign imem_master_awprot = near_mem$imem_master_awprot ;

  // value method imem_master_m_awqos
  assign imem_master_awqos = near_mem$imem_master_awqos ;

  // value method imem_master_m_awregion
  assign imem_master_awregion = near_mem$imem_master_awregion ;

  // action method imem_master_m_awready
  assign CAN_FIRE_imem_master_m_awready = 1'd1 ;
  assign WILL_FIRE_imem_master_m_awready = 1'd1 ;

  // value method imem_master_m_wvalid
  assign imem_master_wvalid = near_mem$imem_master_wvalid ;

  // value method imem_master_m_wdata
  assign imem_master_wdata = near_mem$imem_master_wdata ;

  // value method imem_master_m_wstrb
  assign imem_master_wstrb = near_mem$imem_master_wstrb ;

  // value method imem_master_m_wlast
  assign imem_master_wlast = near_mem$imem_master_wlast ;

  // action method imem_master_m_wready
  assign CAN_FIRE_imem_master_m_wready = 1'd1 ;
  assign WILL_FIRE_imem_master_m_wready = 1'd1 ;

  // action method imem_master_m_bvalid
  assign CAN_FIRE_imem_master_m_bvalid = 1'd1 ;
  assign WILL_FIRE_imem_master_m_bvalid = 1'd1 ;

  // value method imem_master_m_bready
  assign imem_master_bready = near_mem$imem_master_bready ;

  // value method imem_master_m_arvalid
  assign imem_master_arvalid = near_mem$imem_master_arvalid ;

  // value method imem_master_m_arid
  assign imem_master_arid = near_mem$imem_master_arid ;

  // value method imem_master_m_araddr
  assign imem_master_araddr = near_mem$imem_master_araddr ;

  // value method imem_master_m_arlen
  assign imem_master_arlen = near_mem$imem_master_arlen ;

  // value method imem_master_m_arsize
  assign imem_master_arsize = near_mem$imem_master_arsize ;

  // value method imem_master_m_arburst
  assign imem_master_arburst = near_mem$imem_master_arburst ;

  // value method imem_master_m_arlock
  assign imem_master_arlock = near_mem$imem_master_arlock ;

  // value method imem_master_m_arcache
  assign imem_master_arcache = near_mem$imem_master_arcache ;

  // value method imem_master_m_arprot
  assign imem_master_arprot = near_mem$imem_master_arprot ;

  // value method imem_master_m_arqos
  assign imem_master_arqos = near_mem$imem_master_arqos ;

  // value method imem_master_m_arregion
  assign imem_master_arregion = near_mem$imem_master_arregion ;

  // action method imem_master_m_arready
  assign CAN_FIRE_imem_master_m_arready = 1'd1 ;
  assign WILL_FIRE_imem_master_m_arready = 1'd1 ;

  // action method imem_master_m_rvalid
  assign CAN_FIRE_imem_master_m_rvalid = 1'd1 ;
  assign WILL_FIRE_imem_master_m_rvalid = 1'd1 ;

  // value method imem_master_m_rready
  assign imem_master_rready = near_mem$imem_master_rready ;

  // value method dmem_master_m_awvalid
  assign dmem_master_awvalid = near_mem$dmem_master_awvalid ;

  // value method dmem_master_m_awid
  assign dmem_master_awid = near_mem$dmem_master_awid ;

  // value method dmem_master_m_awaddr
  assign dmem_master_awaddr = near_mem$dmem_master_awaddr ;

  // value method dmem_master_m_awlen
  assign dmem_master_awlen = near_mem$dmem_master_awlen ;

  // value method dmem_master_m_awsize
  assign dmem_master_awsize = near_mem$dmem_master_awsize ;

  // value method dmem_master_m_awburst
  assign dmem_master_awburst = near_mem$dmem_master_awburst ;

  // value method dmem_master_m_awlock
  assign dmem_master_awlock = near_mem$dmem_master_awlock ;

  // value method dmem_master_m_awcache
  assign dmem_master_awcache = near_mem$dmem_master_awcache ;

  // value method dmem_master_m_awprot
  assign dmem_master_awprot = near_mem$dmem_master_awprot ;

  // value method dmem_master_m_awqos
  assign dmem_master_awqos = near_mem$dmem_master_awqos ;

  // value method dmem_master_m_awregion
  assign dmem_master_awregion = near_mem$dmem_master_awregion ;

  // action method dmem_master_m_awready
  assign CAN_FIRE_dmem_master_m_awready = 1'd1 ;
  assign WILL_FIRE_dmem_master_m_awready = 1'd1 ;

  // value method dmem_master_m_wvalid
  assign dmem_master_wvalid = near_mem$dmem_master_wvalid ;

  // value method dmem_master_m_wdata
  assign dmem_master_wdata = near_mem$dmem_master_wdata ;

  // value method dmem_master_m_wstrb
  assign dmem_master_wstrb = near_mem$dmem_master_wstrb ;

  // value method dmem_master_m_wlast
  assign dmem_master_wlast = near_mem$dmem_master_wlast ;

  // action method dmem_master_m_wready
  assign CAN_FIRE_dmem_master_m_wready = 1'd1 ;
  assign WILL_FIRE_dmem_master_m_wready = 1'd1 ;

  // action method dmem_master_m_bvalid
  assign CAN_FIRE_dmem_master_m_bvalid = 1'd1 ;
  assign WILL_FIRE_dmem_master_m_bvalid = 1'd1 ;

  // value method dmem_master_m_bready
  assign dmem_master_bready = near_mem$dmem_master_bready ;

  // value method dmem_master_m_arvalid
  assign dmem_master_arvalid = near_mem$dmem_master_arvalid ;

  // value method dmem_master_m_arid
  assign dmem_master_arid = near_mem$dmem_master_arid ;

  // value method dmem_master_m_araddr
  assign dmem_master_araddr = near_mem$dmem_master_araddr ;

  // value method dmem_master_m_arlen
  assign dmem_master_arlen = near_mem$dmem_master_arlen ;

  // value method dmem_master_m_arsize
  assign dmem_master_arsize = near_mem$dmem_master_arsize ;

  // value method dmem_master_m_arburst
  assign dmem_master_arburst = near_mem$dmem_master_arburst ;

  // value method dmem_master_m_arlock
  assign dmem_master_arlock = near_mem$dmem_master_arlock ;

  // value method dmem_master_m_arcache
  assign dmem_master_arcache = near_mem$dmem_master_arcache ;

  // value method dmem_master_m_arprot
  assign dmem_master_arprot = near_mem$dmem_master_arprot ;

  // value method dmem_master_m_arqos
  assign dmem_master_arqos = near_mem$dmem_master_arqos ;

  // value method dmem_master_m_arregion
  assign dmem_master_arregion = near_mem$dmem_master_arregion ;

  // action method dmem_master_m_arready
  assign CAN_FIRE_dmem_master_m_arready = 1'd1 ;
  assign WILL_FIRE_dmem_master_m_arready = 1'd1 ;

  // action method dmem_master_m_rvalid
  assign CAN_FIRE_dmem_master_m_rvalid = 1'd1 ;
  assign WILL_FIRE_dmem_master_m_rvalid = 1'd1 ;

  // value method dmem_master_m_rready
  assign dmem_master_rready = near_mem$dmem_master_rready ;

  // action method m_external_interrupt_req
  assign CAN_FIRE_m_external_interrupt_req = 1'd1 ;
  assign WILL_FIRE_m_external_interrupt_req = 1'd1 ;

  // action method s_external_interrupt_req
  assign CAN_FIRE_s_external_interrupt_req = 1'd1 ;
  assign WILL_FIRE_s_external_interrupt_req = 1'd1 ;

  // action method software_interrupt_req
  assign CAN_FIRE_software_interrupt_req = 1'd1 ;
  assign WILL_FIRE_software_interrupt_req = 1'd1 ;

  // action method timer_interrupt_req
  assign CAN_FIRE_timer_interrupt_req = 1'd1 ;
  assign WILL_FIRE_timer_interrupt_req = 1'd1 ;

  // action method nmi_req
  assign CAN_FIRE_nmi_req = 1'd1 ;
  assign WILL_FIRE_nmi_req = 1'd1 ;

  // action method set_verbosity
  assign RDY_set_verbosity = 1'd1 ;
  assign CAN_FIRE_set_verbosity = 1'd1 ;
  assign WILL_FIRE_set_verbosity = EN_set_verbosity ;

  // submodule csr_regfile
  mkCSR_RegFile csr_regfile(.CLK(CLK),
			    .RST_N(RST_N),
			    .access_permitted_1_csr_addr(csr_regfile$access_permitted_1_csr_addr),
			    .access_permitted_1_priv(csr_regfile$access_permitted_1_priv),
			    .access_permitted_1_read_not_write(csr_regfile$access_permitted_1_read_not_write),
			    .access_permitted_2_csr_addr(csr_regfile$access_permitted_2_csr_addr),
			    .access_permitted_2_priv(csr_regfile$access_permitted_2_priv),
			    .access_permitted_2_read_not_write(csr_regfile$access_permitted_2_read_not_write),
			    .csr_counter_read_fault_csr_addr(csr_regfile$csr_counter_read_fault_csr_addr),
			    .csr_counter_read_fault_priv(csr_regfile$csr_counter_read_fault_priv),
			    .csr_ret_actions_from_priv(csr_regfile$csr_ret_actions_from_priv),
			    .csr_trap_actions_exc_code(csr_regfile$csr_trap_actions_exc_code),
			    .csr_trap_actions_from_priv(csr_regfile$csr_trap_actions_from_priv),
			    .csr_trap_actions_interrupt(csr_regfile$csr_trap_actions_interrupt),
			    .csr_trap_actions_nmi(csr_regfile$csr_trap_actions_nmi),
			    .csr_trap_actions_pc(csr_regfile$csr_trap_actions_pc),
			    .csr_trap_actions_xtval(csr_regfile$csr_trap_actions_xtval),
			    .interrupt_pending_cur_priv(csr_regfile$interrupt_pending_cur_priv),
			    .m_external_interrupt_req_set_not_clear(csr_regfile$m_external_interrupt_req_set_not_clear),
			    .mav_csr_write_csr_addr(csr_regfile$mav_csr_write_csr_addr),
			    .mav_csr_write_word(csr_regfile$mav_csr_write_word),
			    .mav_read_csr_csr_addr(csr_regfile$mav_read_csr_csr_addr),
			    .nmi_req_set_not_clear(csr_regfile$nmi_req_set_not_clear),
			    .read_csr_csr_addr(csr_regfile$read_csr_csr_addr),
			    .read_csr_port2_csr_addr(csr_regfile$read_csr_port2_csr_addr),
			    .s_external_interrupt_req_set_not_clear(csr_regfile$s_external_interrupt_req_set_not_clear),
			    .software_interrupt_req_set_not_clear(csr_regfile$software_interrupt_req_set_not_clear),
			    .timer_interrupt_req_set_not_clear(csr_regfile$timer_interrupt_req_set_not_clear),
			    .EN_server_reset_request_put(csr_regfile$EN_server_reset_request_put),
			    .EN_server_reset_response_get(csr_regfile$EN_server_reset_response_get),
			    .EN_mav_read_csr(csr_regfile$EN_mav_read_csr),
			    .EN_mav_csr_write(csr_regfile$EN_mav_csr_write),
			    .EN_csr_trap_actions(csr_regfile$EN_csr_trap_actions),
			    .EN_csr_ret_actions(csr_regfile$EN_csr_ret_actions),
			    .EN_csr_minstret_incr(csr_regfile$EN_csr_minstret_incr),
			    .EN_debug(csr_regfile$EN_debug),
			    .RDY_server_reset_request_put(csr_regfile$RDY_server_reset_request_put),
			    .RDY_server_reset_response_get(csr_regfile$RDY_server_reset_response_get),
			    .read_csr(csr_regfile$read_csr),
			    .read_csr_port2(),
			    .mav_read_csr(),
			    .mav_csr_write(),
			    .read_misa(csr_regfile$read_misa),
			    .read_mstatus(csr_regfile$read_mstatus),
			    .read_ustatus(),
			    .read_satp(csr_regfile$read_satp),
			    .csr_trap_actions(csr_regfile$csr_trap_actions),
			    .RDY_csr_trap_actions(),
			    .csr_ret_actions(csr_regfile$csr_ret_actions),
			    .RDY_csr_ret_actions(),
			    .read_csr_minstret(csr_regfile$read_csr_minstret),
			    .read_csr_mcycle(csr_regfile$read_csr_mcycle),
			    .read_csr_mtime(),
			    .access_permitted_1(csr_regfile$access_permitted_1),
			    .access_permitted_2(csr_regfile$access_permitted_2),
			    .csr_counter_read_fault(),
			    .csr_mip_read(),
			    .interrupt_pending(csr_regfile$interrupt_pending),
			    .wfi_resume(csr_regfile$wfi_resume),
			    .nmi_pending(csr_regfile$nmi_pending),
			    .RDY_debug());

  // submodule f_reset_reqs
  FIFO2 #(.width(32'd1), .guarded(1'd1)) f_reset_reqs(.RST(RST_N),
						      .CLK(CLK),
						      .D_IN(f_reset_reqs$D_IN),
						      .ENQ(f_reset_reqs$ENQ),
						      .DEQ(f_reset_reqs$DEQ),
						      .CLR(f_reset_reqs$CLR),
						      .D_OUT(f_reset_reqs$D_OUT),
						      .FULL_N(f_reset_reqs$FULL_N),
						      .EMPTY_N(f_reset_reqs$EMPTY_N));

  // submodule f_reset_rsps
  FIFO2 #(.width(32'd1), .guarded(1'd1)) f_reset_rsps(.RST(RST_N),
						      .CLK(CLK),
						      .D_IN(f_reset_rsps$D_IN),
						      .ENQ(f_reset_rsps$ENQ),
						      .DEQ(f_reset_rsps$DEQ),
						      .CLR(f_reset_rsps$CLR),
						      .D_OUT(f_reset_rsps$D_OUT),
						      .FULL_N(f_reset_rsps$FULL_N),
						      .EMPTY_N(f_reset_rsps$EMPTY_N));

  // submodule gpr_regfile
  mkGPR_RegFile gpr_regfile(.CLK(CLK),
			    .RST_N(RST_N),
			    .read_rs1_port2_rs1(gpr_regfile$read_rs1_port2_rs1),
			    .read_rs1_rs1(gpr_regfile$read_rs1_rs1),
			    .read_rs2_rs2(gpr_regfile$read_rs2_rs2),
			    .write_rd_rd(gpr_regfile$write_rd_rd),
			    .write_rd_rd_val(gpr_regfile$write_rd_rd_val),
			    .EN_server_reset_request_put(gpr_regfile$EN_server_reset_request_put),
			    .EN_server_reset_response_get(gpr_regfile$EN_server_reset_response_get),
			    .EN_write_rd(gpr_regfile$EN_write_rd),
			    .RDY_server_reset_request_put(gpr_regfile$RDY_server_reset_request_put),
			    .RDY_server_reset_response_get(gpr_regfile$RDY_server_reset_response_get),
			    .read_rs1(gpr_regfile$read_rs1),
			    .read_rs1_port2(),
			    .read_rs2(gpr_regfile$read_rs2));

  // submodule near_mem
  mkNear_Mem near_mem(.CLK(CLK),
		      .RST_N(RST_N),
		      .dmem_master_arready(near_mem$dmem_master_arready),
		      .dmem_master_awready(near_mem$dmem_master_awready),
		      .dmem_master_bid(near_mem$dmem_master_bid),
		      .dmem_master_bresp(near_mem$dmem_master_bresp),
		      .dmem_master_bvalid(near_mem$dmem_master_bvalid),
		      .dmem_master_rdata(near_mem$dmem_master_rdata),
		      .dmem_master_rid(near_mem$dmem_master_rid),
		      .dmem_master_rlast(near_mem$dmem_master_rlast),
		      .dmem_master_rresp(near_mem$dmem_master_rresp),
		      .dmem_master_rvalid(near_mem$dmem_master_rvalid),
		      .dmem_master_wready(near_mem$dmem_master_wready),
		      .dmem_req_addr(near_mem$dmem_req_addr),
		      .dmem_req_amo_funct7(near_mem$dmem_req_amo_funct7),
		      .dmem_req_f3(near_mem$dmem_req_f3),
		      .dmem_req_mstatus_MXR(near_mem$dmem_req_mstatus_MXR),
		      .dmem_req_op(near_mem$dmem_req_op),
		      .dmem_req_priv(near_mem$dmem_req_priv),
		      .dmem_req_satp(near_mem$dmem_req_satp),
		      .dmem_req_sstatus_SUM(near_mem$dmem_req_sstatus_SUM),
		      .dmem_req_store_value(near_mem$dmem_req_store_value),
		      .imem_master_arready(near_mem$imem_master_arready),
		      .imem_master_awready(near_mem$imem_master_awready),
		      .imem_master_bid(near_mem$imem_master_bid),
		      .imem_master_bresp(near_mem$imem_master_bresp),
		      .imem_master_bvalid(near_mem$imem_master_bvalid),
		      .imem_master_rdata(near_mem$imem_master_rdata),
		      .imem_master_rid(near_mem$imem_master_rid),
		      .imem_master_rlast(near_mem$imem_master_rlast),
		      .imem_master_rresp(near_mem$imem_master_rresp),
		      .imem_master_rvalid(near_mem$imem_master_rvalid),
		      .imem_master_wready(near_mem$imem_master_wready),
		      .imem_req_addr(near_mem$imem_req_addr),
		      .imem_req_f3(near_mem$imem_req_f3),
		      .imem_req_mstatus_MXR(near_mem$imem_req_mstatus_MXR),
		      .imem_req_priv(near_mem$imem_req_priv),
		      .imem_req_satp(near_mem$imem_req_satp),
		      .imem_req_sstatus_SUM(near_mem$imem_req_sstatus_SUM),
		      .server_fence_request_put(near_mem$server_fence_request_put),
		      .EN_server_reset_request_put(near_mem$EN_server_reset_request_put),
		      .EN_server_reset_response_get(near_mem$EN_server_reset_response_get),
		      .EN_imem_req(near_mem$EN_imem_req),
		      .EN_dmem_req(near_mem$EN_dmem_req),
		      .EN_server_fence_i_request_put(near_mem$EN_server_fence_i_request_put),
		      .EN_server_fence_i_response_get(near_mem$EN_server_fence_i_response_get),
		      .EN_server_fence_request_put(near_mem$EN_server_fence_request_put),
		      .EN_server_fence_response_get(near_mem$EN_server_fence_response_get),
		      .EN_sfence_vma(near_mem$EN_sfence_vma),
		      .RDY_server_reset_request_put(near_mem$RDY_server_reset_request_put),
		      .RDY_server_reset_response_get(near_mem$RDY_server_reset_response_get),
		      .imem_valid(near_mem$imem_valid),
		      .imem_is_i32_not_i16(near_mem$imem_is_i32_not_i16),
		      .imem_pc(near_mem$imem_pc),
		      .imem_instr(near_mem$imem_instr),
		      .imem_exc(near_mem$imem_exc),
		      .imem_exc_code(near_mem$imem_exc_code),
		      .imem_tval(),
		      .imem_master_awvalid(near_mem$imem_master_awvalid),
		      .imem_master_awid(near_mem$imem_master_awid),
		      .imem_master_awaddr(near_mem$imem_master_awaddr),
		      .imem_master_awlen(near_mem$imem_master_awlen),
		      .imem_master_awsize(near_mem$imem_master_awsize),
		      .imem_master_awburst(near_mem$imem_master_awburst),
		      .imem_master_awlock(near_mem$imem_master_awlock),
		      .imem_master_awcache(near_mem$imem_master_awcache),
		      .imem_master_awprot(near_mem$imem_master_awprot),
		      .imem_master_awqos(near_mem$imem_master_awqos),
		      .imem_master_awregion(near_mem$imem_master_awregion),
		      .imem_master_wvalid(near_mem$imem_master_wvalid),
		      .imem_master_wdata(near_mem$imem_master_wdata),
		      .imem_master_wstrb(near_mem$imem_master_wstrb),
		      .imem_master_wlast(near_mem$imem_master_wlast),
		      .imem_master_bready(near_mem$imem_master_bready),
		      .imem_master_arvalid(near_mem$imem_master_arvalid),
		      .imem_master_arid(near_mem$imem_master_arid),
		      .imem_master_araddr(near_mem$imem_master_araddr),
		      .imem_master_arlen(near_mem$imem_master_arlen),
		      .imem_master_arsize(near_mem$imem_master_arsize),
		      .imem_master_arburst(near_mem$imem_master_arburst),
		      .imem_master_arlock(near_mem$imem_master_arlock),
		      .imem_master_arcache(near_mem$imem_master_arcache),
		      .imem_master_arprot(near_mem$imem_master_arprot),
		      .imem_master_arqos(near_mem$imem_master_arqos),
		      .imem_master_arregion(near_mem$imem_master_arregion),
		      .imem_master_rready(near_mem$imem_master_rready),
		      .dmem_valid(near_mem$dmem_valid),
		      .dmem_word64(near_mem$dmem_word64),
		      .dmem_st_amo_val(),
		      .dmem_exc(near_mem$dmem_exc),
		      .dmem_exc_code(near_mem$dmem_exc_code),
		      .dmem_master_awvalid(near_mem$dmem_master_awvalid),
		      .dmem_master_awid(near_mem$dmem_master_awid),
		      .dmem_master_awaddr(near_mem$dmem_master_awaddr),
		      .dmem_master_awlen(near_mem$dmem_master_awlen),
		      .dmem_master_awsize(near_mem$dmem_master_awsize),
		      .dmem_master_awburst(near_mem$dmem_master_awburst),
		      .dmem_master_awlock(near_mem$dmem_master_awlock),
		      .dmem_master_awcache(near_mem$dmem_master_awcache),
		      .dmem_master_awprot(near_mem$dmem_master_awprot),
		      .dmem_master_awqos(near_mem$dmem_master_awqos),
		      .dmem_master_awregion(near_mem$dmem_master_awregion),
		      .dmem_master_wvalid(near_mem$dmem_master_wvalid),
		      .dmem_master_wdata(near_mem$dmem_master_wdata),
		      .dmem_master_wstrb(near_mem$dmem_master_wstrb),
		      .dmem_master_wlast(near_mem$dmem_master_wlast),
		      .dmem_master_bready(near_mem$dmem_master_bready),
		      .dmem_master_arvalid(near_mem$dmem_master_arvalid),
		      .dmem_master_arid(near_mem$dmem_master_arid),
		      .dmem_master_araddr(near_mem$dmem_master_araddr),
		      .dmem_master_arlen(near_mem$dmem_master_arlen),
		      .dmem_master_arsize(near_mem$dmem_master_arsize),
		      .dmem_master_arburst(near_mem$dmem_master_arburst),
		      .dmem_master_arlock(near_mem$dmem_master_arlock),
		      .dmem_master_arcache(near_mem$dmem_master_arcache),
		      .dmem_master_arprot(near_mem$dmem_master_arprot),
		      .dmem_master_arqos(near_mem$dmem_master_arqos),
		      .dmem_master_arregion(near_mem$dmem_master_arregion),
		      .dmem_master_rready(near_mem$dmem_master_rready),
		      .RDY_server_fence_i_request_put(near_mem$RDY_server_fence_i_request_put),
		      .RDY_server_fence_i_response_get(near_mem$RDY_server_fence_i_response_get),
		      .RDY_server_fence_request_put(near_mem$RDY_server_fence_request_put),
		      .RDY_server_fence_response_get(near_mem$RDY_server_fence_response_get),
		      .RDY_sfence_vma());

  // submodule soc_map
  mkSoC_Map soc_map(.CLK(CLK),
		    .RST_N(RST_N),
		    .m_is_IO_addr_addr(soc_map$m_is_IO_addr_addr),
		    .m_is_mem_addr_addr(soc_map$m_is_mem_addr_addr),
		    .m_is_near_mem_IO_addr_addr(soc_map$m_is_near_mem_IO_addr_addr),
		    .m_near_mem_io_addr_base(),
		    .m_near_mem_io_addr_size(),
		    .m_near_mem_io_addr_lim(),
		    .m_plic_addr_base(),
		    .m_plic_addr_size(),
		    .m_plic_addr_lim(),
		    .m_uart0_addr_base(),
		    .m_uart0_addr_size(),
		    .m_uart0_addr_lim(),
		    .m_boot_rom_addr_base(),
		    .m_boot_rom_addr_size(),
		    .m_boot_rom_addr_lim(),
		    .m_mem0_controller_addr_base(),
		    .m_mem0_controller_addr_size(),
		    .m_mem0_controller_addr_lim(),
		    .m_tcm_addr_base(),
		    .m_tcm_addr_size(),
		    .m_tcm_addr_lim(),
		    .m_is_mem_addr(),
		    .m_is_IO_addr(),
		    .m_is_near_mem_IO_addr(),
		    .m_pc_reset_value(soc_map$m_pc_reset_value),
		    .m_mtvec_reset_value(),
		    .m_nmivec_reset_value());

  // submodule stage1_f_reset_reqs
  FIFO20 #(.guarded(1'd1)) stage1_f_reset_reqs(.RST(RST_N),
					       .CLK(CLK),
					       .ENQ(stage1_f_reset_reqs$ENQ),
					       .DEQ(stage1_f_reset_reqs$DEQ),
					       .CLR(stage1_f_reset_reqs$CLR),
					       .FULL_N(stage1_f_reset_reqs$FULL_N),
					       .EMPTY_N(stage1_f_reset_reqs$EMPTY_N));

  // submodule stage1_f_reset_rsps
  FIFO20 #(.guarded(1'd1)) stage1_f_reset_rsps(.RST(RST_N),
					       .CLK(CLK),
					       .ENQ(stage1_f_reset_rsps$ENQ),
					       .DEQ(stage1_f_reset_rsps$DEQ),
					       .CLR(stage1_f_reset_rsps$CLR),
					       .FULL_N(stage1_f_reset_rsps$FULL_N),
					       .EMPTY_N(stage1_f_reset_rsps$EMPTY_N));

  // submodule stage2_f_reset_reqs
  FIFO20 #(.guarded(1'd1)) stage2_f_reset_reqs(.RST(RST_N),
					       .CLK(CLK),
					       .ENQ(stage2_f_reset_reqs$ENQ),
					       .DEQ(stage2_f_reset_reqs$DEQ),
					       .CLR(stage2_f_reset_reqs$CLR),
					       .FULL_N(stage2_f_reset_reqs$FULL_N),
					       .EMPTY_N(stage2_f_reset_reqs$EMPTY_N));

  // submodule stage2_f_reset_rsps
  FIFO20 #(.guarded(1'd1)) stage2_f_reset_rsps(.RST(RST_N),
					       .CLK(CLK),
					       .ENQ(stage2_f_reset_rsps$ENQ),
					       .DEQ(stage2_f_reset_rsps$DEQ),
					       .CLR(stage2_f_reset_rsps$CLR),
					       .FULL_N(stage2_f_reset_rsps$FULL_N),
					       .EMPTY_N(stage2_f_reset_rsps$EMPTY_N));

  // submodule stage2_mbox
  mkRISCV_MBox stage2_mbox(.CLK(CLK),
			   .RST_N(RST_N),
			   .req_f3(stage2_mbox$req_f3),
			   .req_is_OP_not_OP_32(stage2_mbox$req_is_OP_not_OP_32),
			   .req_v1(stage2_mbox$req_v1),
			   .req_v2(stage2_mbox$req_v2),
			   .set_verbosity_verbosity(stage2_mbox$set_verbosity_verbosity),
			   .EN_set_verbosity(stage2_mbox$EN_set_verbosity),
			   .EN_req_reset(stage2_mbox$EN_req_reset),
			   .EN_rsp_reset(stage2_mbox$EN_rsp_reset),
			   .EN_req(stage2_mbox$EN_req),
			   .RDY_set_verbosity(),
			   .RDY_req_reset(),
			   .RDY_rsp_reset(),
			   .valid(stage2_mbox$valid),
			   .word(stage2_mbox$word));

  // submodule stage3_f_reset_reqs
  FIFO20 #(.guarded(1'd1)) stage3_f_reset_reqs(.RST(RST_N),
					       .CLK(CLK),
					       .ENQ(stage3_f_reset_reqs$ENQ),
					       .DEQ(stage3_f_reset_reqs$DEQ),
					       .CLR(stage3_f_reset_reqs$CLR),
					       .FULL_N(stage3_f_reset_reqs$FULL_N),
					       .EMPTY_N(stage3_f_reset_reqs$EMPTY_N));

  // submodule stage3_f_reset_rsps
  FIFO20 #(.guarded(1'd1)) stage3_f_reset_rsps(.RST(RST_N),
					       .CLK(CLK),
					       .ENQ(stage3_f_reset_rsps$ENQ),
					       .DEQ(stage3_f_reset_rsps$DEQ),
					       .CLR(stage3_f_reset_rsps$CLR),
					       .FULL_N(stage3_f_reset_rsps$FULL_N),
					       .EMPTY_N(stage3_f_reset_rsps$EMPTY_N));

  // rule RL_rl_show_pipe
  assign CAN_FIRE_RL_rl_show_pipe =
	     NOT_IF_csr_regfile_read_csr_minstret__8_ULT_cf_ETC___d44 &&
	     rg_state != 4'd0 &&
	     rg_state != 4'd1 &&
	     rg_state != 4'd12 ;
  assign WILL_FIRE_RL_rl_show_pipe = CAN_FIRE_RL_rl_show_pipe ;

  // rule RL_rl_stage2_nonpipe
  assign CAN_FIRE_RL_rl_stage2_nonpipe =
	     rg_state == 4'd3 && !stage3_rg_full && stage2_rg_full &&
	     NOT_stage2_rg_stage2_1_BITS_103_TO_101_2_EQ_0__ETC___d126 ;
  assign WILL_FIRE_RL_rl_stage2_nonpipe = CAN_FIRE_RL_rl_stage2_nonpipe ;

  // rule RL_rl_stage1_trap
  assign CAN_FIRE_RL_rl_stage1_trap =
	     rg_state_5_EQ_3_172_AND_NOT_csr_regfile_interr_ETC___d1330 &&
	     stage1_rg_full &&
	     near_mem_imem_valid_AND_NOT_imem_c_rg_pc_BITS__ETC___d1331 &&
	     (near_mem$imem_exc ||
	      ((_theResult____h4859[6:0] == 7'b1100011) ?
		 _theResult____h4859[14:12] != 3'b0 &&
		 _theResult____h4859[14:12] != 3'b001 &&
		 _theResult____h4859[14:12] != 3'b100 &&
		 _theResult____h4859[14:12] != 3'b101 &&
		 _theResult____h4859[14:12] != 3'b110 &&
		 _theResult____h4859[14:12] != 3'b111 :
		 _theResult____h4859[6:0] != 7'b1101111 &&
		 _theResult____h4859[6:0] != 7'b1100111 &&
		 (_theResult____h4859[6:0] != 7'b0110011 ||
		  _theResult____h4859[31:25] != 7'b0000001) &&
		 IF_IF_imem_c_rg_pc_BITS_1_TO_0_EQ_0b0_OR_NOT_i_ETC___d1347)) ;
  assign WILL_FIRE_RL_rl_stage1_trap = CAN_FIRE_RL_rl_stage1_trap ;

  // rule RL_rl_trap
  assign CAN_FIRE_RL_rl_trap =
	     rg_state == 4'd4 &&
	     NOT_stage1_rg_full_06_07_OR_near_mem_imem_vali_ETC___d1358 ;
  assign WILL_FIRE_RL_rl_trap = CAN_FIRE_RL_rl_trap ;

  // rule RL_rl_stage1_CSRR_W
  assign CAN_FIRE_RL_rl_stage1_CSRR_W = MUX_rg_state$write_1__SEL_9 ;
  assign WILL_FIRE_RL_rl_stage1_CSRR_W = MUX_rg_state$write_1__SEL_9 ;

  // rule RL_rl_stage1_CSRR_W_2
  assign CAN_FIRE_RL_rl_stage1_CSRR_W_2 = rg_state == 4'd6 ;
  assign WILL_FIRE_RL_rl_stage1_CSRR_W_2 = rg_state == 4'd6 ;

  // rule RL_rl_stage1_CSRR_S_or_C
  assign CAN_FIRE_RL_rl_stage1_CSRR_S_or_C = MUX_rg_state$write_1__SEL_10 ;
  assign WILL_FIRE_RL_rl_stage1_CSRR_S_or_C = MUX_rg_state$write_1__SEL_10 ;

  // rule RL_rl_stage1_CSRR_S_or_C_2
  assign CAN_FIRE_RL_rl_stage1_CSRR_S_or_C_2 = rg_state == 4'd7 ;
  assign WILL_FIRE_RL_rl_stage1_CSRR_S_or_C_2 = rg_state == 4'd7 ;

  // rule RL_rl_stage1_restart_after_csrrx
  assign CAN_FIRE_RL_rl_stage1_restart_after_csrrx =
	     imem_c_rg_pc_BITS_1_TO_0_EQ_0b0_OR_NOT_near_me_ETC___d1118 &&
	     rg_state == 4'd8 ;
  assign WILL_FIRE_RL_rl_stage1_restart_after_csrrx =
	     CAN_FIRE_RL_rl_stage1_restart_after_csrrx ;

  // rule RL_rl_stage1_xRET
  assign CAN_FIRE_RL_rl_stage1_xRET =
	     rg_state_5_EQ_3_172_AND_NOT_csr_regfile_interr_ETC___d1330 &&
	     stage1_rg_full &&
	     near_mem_imem_valid_AND_NOT_imem_c_rg_pc_BITS__ETC___d1331 &&
	     !near_mem$imem_exc &&
	     _theResult____h4859[6:0] == 7'b1110011 &&
	     IF_imem_c_rg_pc_BITS_1_TO_0_EQ_0b0_OR_NOT_imem_ETC___d801 ;
  assign WILL_FIRE_RL_rl_stage1_xRET = CAN_FIRE_RL_rl_stage1_xRET ;

  // rule RL_rl_stage1_FENCE_I
  assign CAN_FIRE_RL_rl_stage1_FENCE_I = MUX_rg_state$write_1__SEL_11 ;
  assign WILL_FIRE_RL_rl_stage1_FENCE_I = MUX_rg_state$write_1__SEL_11 ;

  // rule RL_rl_finish_FENCE_I
  assign CAN_FIRE_RL_rl_finish_FENCE_I =
	     imem_c_rg_pc_BITS_1_TO_0_EQ_0b0_OR_NOT_near_me_ETC___d1118 &&
	     near_mem$RDY_server_fence_i_response_get &&
	     rg_state == 4'd9 ;
  assign WILL_FIRE_RL_rl_finish_FENCE_I = CAN_FIRE_RL_rl_finish_FENCE_I ;

  // rule RL_rl_stage1_FENCE
  assign CAN_FIRE_RL_rl_stage1_FENCE = MUX_rg_state$write_1__SEL_12 ;
  assign WILL_FIRE_RL_rl_stage1_FENCE = MUX_rg_state$write_1__SEL_12 ;

  // rule RL_rl_finish_FENCE
  assign CAN_FIRE_RL_rl_finish_FENCE =
	     imem_c_rg_pc_BITS_1_TO_0_EQ_0b0_OR_NOT_near_me_ETC___d1118 &&
	     near_mem$RDY_server_fence_response_get &&
	     rg_state == 4'd10 ;
  assign WILL_FIRE_RL_rl_finish_FENCE = CAN_FIRE_RL_rl_finish_FENCE ;

  // rule RL_rl_finish_SFENCE_VMA
  assign CAN_FIRE_RL_rl_finish_SFENCE_VMA =
	     imem_c_rg_pc_BITS_1_TO_0_EQ_0b0_OR_NOT_near_me_ETC___d1118 &&
	     rg_state == 4'd11 ;
  assign WILL_FIRE_RL_rl_finish_SFENCE_VMA =
	     CAN_FIRE_RL_rl_finish_SFENCE_VMA ;

  // rule RL_rl_stage1_WFI
  assign CAN_FIRE_RL_rl_stage1_WFI = MUX_rg_state$write_1__SEL_13 ;
  assign WILL_FIRE_RL_rl_stage1_WFI = MUX_rg_state$write_1__SEL_13 ;

  // rule RL_rl_WFI_resume
  assign CAN_FIRE_RL_rl_WFI_resume =
	     imem_c_rg_pc_BITS_1_TO_0_EQ_0b0_OR_NOT_near_me_ETC___d1118 &&
	     rg_state == 4'd12 &&
	     csr_regfile$wfi_resume &&
	     NOT_stage1_rg_full_06_07_OR_near_mem_imem_vali_ETC___d1358 ;
  assign WILL_FIRE_RL_rl_WFI_resume = CAN_FIRE_RL_rl_WFI_resume ;

  // rule RL_rl_reset_from_WFI
  assign CAN_FIRE_RL_rl_reset_from_WFI =
	     rg_state == 4'd12 && f_reset_reqs$EMPTY_N ;
  assign WILL_FIRE_RL_rl_reset_from_WFI = MUX_rg_state$write_1__SEL_4 ;

  // rule RL_rl_trap_fetch
  assign CAN_FIRE_RL_rl_trap_fetch =
	     imem_c_rg_pc_BITS_1_TO_0_EQ_0b0_OR_NOT_near_me_ETC___d1118 &&
	     rg_state == 4'd5 ;
  assign WILL_FIRE_RL_rl_trap_fetch = CAN_FIRE_RL_rl_trap_fetch ;

  // rule RL_rl_stage1_interrupt
  assign CAN_FIRE_RL_rl_stage1_interrupt =
	     (csr_regfile$interrupt_pending[4] || csr_regfile$nmi_pending) &&
	     rg_state == 4'd3 &&
	     stage1_rg_full &&
	     near_mem$imem_valid &&
	     NOT_imem_c_rg_pc_BITS_1_TO_0_EQ_0b0_AND_imem_c_ETC___d521 &&
	     IF_IF_imem_c_rg_pc_BITS_1_TO_0_EQ_0b0_OR_NOT_i_ETC___d1153 &&
	     !stage2_rg_full &&
	     !stage3_rg_full ;
  assign WILL_FIRE_RL_rl_stage1_interrupt = CAN_FIRE_RL_rl_stage1_interrupt ;

  // rule RL_imem_c_rl_assert_fail
  assign CAN_FIRE_RL_imem_c_rl_assert_fail = !near_mem$imem_is_i32_not_i16 ;
  assign WILL_FIRE_RL_imem_c_rl_assert_fail =
	     CAN_FIRE_RL_imem_c_rl_assert_fail ;

  // rule RL_rl_reset_complete
  assign CAN_FIRE_RL_rl_reset_complete =
	     gpr_regfile$RDY_server_reset_response_get &&
	     near_mem$RDY_server_reset_response_get &&
	     csr_regfile_RDY_server_reset_response_get__109_ETC___d1124 &&
	     rg_state == 4'd1 ;
  assign WILL_FIRE_RL_rl_reset_complete = MUX_rg_state$write_1__SEL_1 ;

  // rule RL_rl_pipe
  assign CAN_FIRE_RL_rl_pipe =
	     (csr_regfile_interrupt_pending_rg_cur_priv_6_14_ETC___d1170 ||
	      imem_c_rg_pc_BITS_1_TO_0_EQ_0b0_OR_NOT_near_me_ETC___d1118) &&
	     rg_state_5_EQ_3_172_AND_stage3_rg_full_1_OR_st_ETC___d1192 ;
  assign WILL_FIRE_RL_rl_pipe =
	     CAN_FIRE_RL_rl_pipe && !WILL_FIRE_RL_imem_c_rl_fetch_next_32b ;

  // rule RL_rl_reset_start
  assign CAN_FIRE_RL_rl_reset_start = MUX_rg_state$write_1__SEL_5 ;
  assign WILL_FIRE_RL_rl_reset_start = MUX_rg_state$write_1__SEL_5 ;

  // rule RL_imem_c_rl_fetch_next_32b
  assign CAN_FIRE_RL_imem_c_rl_fetch_next_32b =
	     near_mem$imem_valid && imem_c_rg_pc[1:0] != 2'b0 &&
	     imem_c_rg_pc_BITS_31_TO_2_0_EQ_near_mem_imem_p_ETC___d13 &&
	     near_mem$imem_instr[17:16] == 2'b11 ;
  assign WILL_FIRE_RL_imem_c_rl_fetch_next_32b =
	     CAN_FIRE_RL_imem_c_rl_fetch_next_32b ;

  // rule RL_stage3_rl_reset
  assign CAN_FIRE_RL_stage3_rl_reset =
	     stage3_f_reset_reqs$EMPTY_N && stage3_f_reset_rsps$FULL_N ;
  assign WILL_FIRE_RL_stage3_rl_reset = CAN_FIRE_RL_stage3_rl_reset ;

  // rule RL_stage2_rl_reset_end
  assign CAN_FIRE_RL_stage2_rl_reset_end =
	     stage2_f_reset_rsps$FULL_N && stage2_rg_resetting ;
  assign WILL_FIRE_RL_stage2_rl_reset_end = CAN_FIRE_RL_stage2_rl_reset_end ;

  // rule RL_stage2_rl_reset_begin
  assign CAN_FIRE_RL_stage2_rl_reset_begin = stage2_f_reset_reqs$EMPTY_N ;
  assign WILL_FIRE_RL_stage2_rl_reset_begin = stage2_f_reset_reqs$EMPTY_N ;

  // rule RL_stage1_rl_reset
  assign CAN_FIRE_RL_stage1_rl_reset =
	     stage1_f_reset_reqs$EMPTY_N && stage1_f_reset_rsps$FULL_N ;
  assign WILL_FIRE_RL_stage1_rl_reset = CAN_FIRE_RL_stage1_rl_reset ;

  // inputs to muxes for submodule ports
  assign MUX_csr_regfile$mav_csr_write_1__SEL_1 =
	     WILL_FIRE_RL_rl_stage1_CSRR_W_2 &&
	     csr_regfile$access_permitted_1 ;
  assign MUX_gpr_regfile$write_rd_1__SEL_3 =
	     WILL_FIRE_RL_rl_stage1_CSRR_S_or_C_2 &&
	     csr_regfile$access_permitted_2 ;
  assign MUX_imem_c_rg_cache_addr$write_1__SEL_2 =
	     WILL_FIRE_RL_rl_reset_complete && rg_run_on_reset &&
	     near_mem$imem_valid ;
  assign MUX_imem_c_rg_cache_addr$write_1__SEL_3 =
	     WILL_FIRE_RL_rl_pipe &&
	     NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d1292 &&
	     near_mem$imem_valid ;
  assign MUX_imem_c_rg_cache_b16$write_1__SEL_5 =
	     WILL_FIRE_RL_rl_trap_fetch && near_mem$imem_valid ;
  assign MUX_imem_c_rg_cache_b16$write_1__SEL_6 =
	     WILL_FIRE_RL_rl_WFI_resume && near_mem$imem_valid ;
  assign MUX_imem_c_rg_cache_b16$write_1__SEL_7 =
	     WILL_FIRE_RL_rl_finish_SFENCE_VMA && near_mem$imem_valid ;
  assign MUX_imem_c_rg_cache_b16$write_1__SEL_8 =
	     WILL_FIRE_RL_rl_finish_FENCE && near_mem$imem_valid ;
  assign MUX_imem_c_rg_cache_b16$write_1__SEL_9 =
	     WILL_FIRE_RL_rl_finish_FENCE_I && near_mem$imem_valid ;
  assign MUX_imem_c_rg_cache_b16$write_1__SEL_10 =
	     WILL_FIRE_RL_rl_stage1_restart_after_csrrx &&
	     near_mem$imem_valid ;
  assign MUX_imem_c_rg_f3$write_1__SEL_1 =
	     WILL_FIRE_RL_rl_reset_complete && rg_run_on_reset ;
  assign MUX_imem_c_rg_f3$write_1__SEL_2 =
	     WILL_FIRE_RL_rl_pipe &&
	     NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d1275 ;
  assign MUX_imem_c_rg_mstatus_MXR$write_1__SEL_4 =
	     WILL_FIRE_RL_rl_WFI_resume ||
	     WILL_FIRE_RL_rl_finish_SFENCE_VMA ||
	     WILL_FIRE_RL_rl_finish_FENCE ||
	     WILL_FIRE_RL_rl_finish_FENCE_I ||
	     WILL_FIRE_RL_rl_stage1_restart_after_csrrx ;
  assign MUX_imem_c_rg_pc$write_1__SEL_4 =
	     WILL_FIRE_RL_rl_trap_fetch || WILL_FIRE_RL_rl_WFI_resume ||
	     WILL_FIRE_RL_rl_finish_SFENCE_VMA ||
	     WILL_FIRE_RL_rl_finish_FENCE ||
	     WILL_FIRE_RL_rl_finish_FENCE_I ;
  assign MUX_near_mem$imem_req_1__SEL_6 =
	     WILL_FIRE_RL_rl_WFI_resume ||
	     WILL_FIRE_RL_rl_finish_SFENCE_VMA ||
	     WILL_FIRE_RL_rl_finish_FENCE ||
	     WILL_FIRE_RL_rl_finish_FENCE_I ;
  assign MUX_rg_next_pc$write_1__SEL_1 =
	     WILL_FIRE_RL_rl_stage1_WFI || WILL_FIRE_RL_rl_stage1_FENCE ||
	     WILL_FIRE_RL_rl_stage1_FENCE_I ||
	     WILL_FIRE_RL_rl_stage1_CSRR_S_or_C ||
	     WILL_FIRE_RL_rl_stage1_CSRR_W ;
  assign MUX_rg_state$write_1__SEL_1 =
	     CAN_FIRE_RL_rl_reset_complete &&
	     !WILL_FIRE_RL_imem_c_rl_fetch_next_32b ;
  assign MUX_rg_state$write_1__SEL_4 =
	     CAN_FIRE_RL_rl_reset_from_WFI && !WILL_FIRE_RL_rl_WFI_resume ;
  assign MUX_rg_state$write_1__SEL_5 =
	     gpr_regfile_RDY_server_reset_request_put__089__ETC___d1101 &&
	     rg_state == 4'd0 ;
  assign MUX_rg_state$write_1__SEL_6 =
	     WILL_FIRE_RL_rl_trap_fetch || WILL_FIRE_RL_rl_WFI_resume ||
	     WILL_FIRE_RL_rl_finish_SFENCE_VMA ||
	     WILL_FIRE_RL_rl_finish_FENCE ||
	     WILL_FIRE_RL_rl_finish_FENCE_I ||
	     WILL_FIRE_RL_rl_stage1_restart_after_csrrx ;
  assign MUX_rg_state$write_1__SEL_7 =
	     WILL_FIRE_RL_rl_stage1_interrupt ||
	     WILL_FIRE_RL_rl_stage1_trap ||
	     WILL_FIRE_RL_rl_stage2_nonpipe ;
  assign MUX_rg_state$write_1__SEL_8 =
	     WILL_FIRE_RL_rl_stage1_xRET || WILL_FIRE_RL_rl_trap ;
  assign MUX_rg_state$write_1__SEL_9 =
	     rg_state_5_EQ_3_172_AND_NOT_csr_regfile_interr_ETC___d1390 &&
	     NOT_near_mem_imem_exc__29_85_AND_IF_imem_c_rg__ETC___d755 ;
  assign MUX_rg_state$write_1__SEL_10 =
	     rg_state_5_EQ_3_172_AND_NOT_csr_regfile_interr_ETC___d1390 &&
	     NOT_near_mem_imem_exc__29_85_AND_IF_imem_c_rg__ETC___d769 ;
  assign MUX_rg_state$write_1__SEL_11 =
	     near_mem$RDY_server_fence_i_request_put &&
	     rg_state_5_EQ_3_172_AND_NOT_csr_regfile_interr_ETC___d1390 &&
	     !near_mem$imem_exc &&
	     _theResult____h4859[6:0] == 7'b0001111 &&
	     _theResult____h4859[14:12] == 3'b001 ;
  assign MUX_rg_state$write_1__SEL_12 =
	     near_mem$RDY_server_fence_request_put &&
	     rg_state_5_EQ_3_172_AND_NOT_csr_regfile_interr_ETC___d1390 &&
	     !near_mem$imem_exc &&
	     _theResult____h4859[6:0] == 7'b0001111 &&
	     _theResult____h4859[14:12] == 3'b0 ;
  assign MUX_rg_state$write_1__SEL_13 =
	     rg_state_5_EQ_3_172_AND_NOT_csr_regfile_interr_ETC___d1390 &&
	     !near_mem$imem_exc &&
	     _theResult____h4859[6:0] == 7'b1110011 &&
	     IF_imem_c_rg_pc_BITS_1_TO_0_EQ_0b0_OR_NOT_imem_ETC___d821 ;
  assign MUX_rg_trap_info$write_1__SEL_1 =
	     WILL_FIRE_RL_rl_stage1_CSRR_S_or_C ||
	     WILL_FIRE_RL_rl_stage1_CSRR_W ;
  assign MUX_rg_trap_instr$write_1__SEL_1 =
	     WILL_FIRE_RL_rl_stage1_interrupt ||
	     WILL_FIRE_RL_rl_stage1_CSRR_S_or_C ||
	     WILL_FIRE_RL_rl_stage1_CSRR_W ||
	     WILL_FIRE_RL_rl_stage1_trap ;
  assign MUX_rg_trap_interrupt$write_1__SEL_1 =
	     WILL_FIRE_RL_rl_stage1_CSRR_S_or_C ||
	     WILL_FIRE_RL_rl_stage1_CSRR_W ||
	     WILL_FIRE_RL_rl_stage1_trap ||
	     WILL_FIRE_RL_rl_stage2_nonpipe ;
  always@(rg_trap_instr or
	  csr_regfile$read_csr or
	  y__h21701 or
	  IF_csr_regfile_read_csr_rg_trap_instr_371_BITS_ETC___d1429)
  begin
    case (rg_trap_instr[14:12])
      3'b010, 3'b110:
	  MUX_csr_regfile$mav_csr_write_2__VAL_2 =
	      IF_csr_regfile_read_csr_rg_trap_instr_371_BITS_ETC___d1429;
      default: MUX_csr_regfile$mav_csr_write_2__VAL_2 =
		   csr_regfile$read_csr[31:0] & y__h21701;
    endcase
  end
  assign MUX_imem_c_rg_cache_b16$write_1__VAL_1 =
	     { 1'd1, near_mem$imem_instr[31:16] } ;
  assign MUX_imem_c_rg_tval$write_1__VAL_5 = near_mem$imem_pc + 32'd4 ;
  assign MUX_near_mem$imem_req_2__VAL_1 =
	     NOT_soc_map_m_pc_reset_value__129_BITS_1_TO_0__ETC___d1141 ?
	       addr_of_b32___1__h16950 :
	       addr_of_b32__h16844 ;
  assign MUX_near_mem$imem_req_2__VAL_2 =
	     NOT_IF_NOT_stage1_rg_full_06_07_OR_NOT_near_me_ETC___d1302 ?
	       addr_of_b32___1__h19177 :
	       addr_of_b32__h19071 ;
  assign MUX_near_mem$imem_req_2__VAL_5 =
	     NOT_rg_next_pc_453_BITS_1_TO_0_454_EQ_0b0_455__ETC___d1462 ?
	       addr_of_b32___1__h27508 :
	       addr_of_b32__h27402 ;
  assign MUX_rg_state$write_1__VAL_1 = rg_run_on_reset ? 4'd3 : 4'd2 ;
  assign MUX_rg_state$write_1__VAL_2 =
	     csr_regfile$access_permitted_1 ? 4'd8 : 4'd4 ;
  assign MUX_rg_state$write_1__VAL_3 =
	     csr_regfile$access_permitted_2 ? 4'd8 : 4'd4 ;
  assign MUX_rg_trap_info$write_1__VAL_1 =
	     { imem_c_rg_pc,
	       4'd2,
	       near_mem$imem_exc ? imem_c_rg_tval : trap_info_tval__h14518 } ;
  assign MUX_rg_trap_info$write_1__VAL_2 =
	     { stage2_rg_stage2[167:136],
	       near_mem$dmem_exc_code,
	       stage2_rg_stage2[95:64] } ;
  assign MUX_rg_trap_info$write_1__VAL_3 =
	     { imem_c_rg_pc,
	       IF_near_mem_imem_exc__29_THEN_near_mem_imem_ex_ETC___d1355 } ;
  assign MUX_rg_trap_info$write_1__VAL_4 =
	     { imem_c_rg_pc, x_exc_code__h27688, 32'd0 } ;
  assign MUX_stage1_rg_full$write_1__VAL_2 =
	     NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d1318 ||
	     (csr_regfile_interrupt_pending_rg_cur_priv_6_14_ETC___d1162 ||
	      NOT_near_mem_imem_valid_08_OR_imem_c_rg_pc_BIT_ETC___d1267) &&
	     stage1_rg_full ;
  assign MUX_stage2_rg_full$write_1__VAL_2 =
	     NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d1213 &&
	     stage1_rg_full &&
	     near_mem_imem_valid_AND_NOT_imem_c_rg_pc_BITS__ETC___d1214 ||
	     stage2_rg_stage2[103:101] != 3'd0 &&
	     IF_stage2_rg_stage2_1_BITS_103_TO_101_2_EQ_1_4_ETC___d1159 &&
	     stage2_rg_full ;
  assign MUX_stage3_rg_full$write_1__VAL_2 =
	     stage2_rg_full &&
	     (stage2_rg_stage2[103:101] == 3'd0 ||
	      IF_stage2_rg_stage2_1_BITS_103_TO_101_2_EQ_1_4_ETC___d1196) ;

  // register cfg_logdelay
  assign cfg_logdelay$D_IN = set_verbosity_logdelay ;
  assign cfg_logdelay$EN = EN_set_verbosity ;

  // register cfg_verbosity
  assign cfg_verbosity$D_IN = set_verbosity_verbosity ;
  assign cfg_verbosity$EN = EN_set_verbosity ;

  // register imem_c_rg_cache_addr
  assign imem_c_rg_cache_addr$D_IN = near_mem$imem_pc ;
  assign imem_c_rg_cache_addr$EN =
	     MUX_rg_state$write_1__SEL_6 && near_mem$imem_valid ||
	     WILL_FIRE_RL_rl_reset_complete && rg_run_on_reset &&
	     near_mem$imem_valid ||
	     WILL_FIRE_RL_rl_pipe &&
	     NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d1292 &&
	     near_mem$imem_valid ||
	     WILL_FIRE_RL_imem_c_rl_fetch_next_32b ;

  // register imem_c_rg_cache_b16
  always@(WILL_FIRE_RL_imem_c_rl_fetch_next_32b or
	  MUX_imem_c_rg_cache_b16$write_1__VAL_1 or
	  WILL_FIRE_RL_rl_reset_start or
	  MUX_imem_c_rg_cache_addr$write_1__SEL_3 or
	  MUX_imem_c_rg_cache_addr$write_1__SEL_2 or
	  MUX_imem_c_rg_cache_b16$write_1__SEL_5 or
	  MUX_imem_c_rg_cache_b16$write_1__SEL_6 or
	  MUX_imem_c_rg_cache_b16$write_1__SEL_7 or
	  MUX_imem_c_rg_cache_b16$write_1__SEL_8 or
	  MUX_imem_c_rg_cache_b16$write_1__SEL_9 or
	  MUX_imem_c_rg_cache_b16$write_1__SEL_10)
  case (1'b1)
    WILL_FIRE_RL_imem_c_rl_fetch_next_32b:
	imem_c_rg_cache_b16$D_IN = MUX_imem_c_rg_cache_b16$write_1__VAL_1;
    WILL_FIRE_RL_rl_reset_start: imem_c_rg_cache_b16$D_IN = 17'd43690;
    MUX_imem_c_rg_cache_addr$write_1__SEL_3:
	imem_c_rg_cache_b16$D_IN = MUX_imem_c_rg_cache_b16$write_1__VAL_1;
    MUX_imem_c_rg_cache_addr$write_1__SEL_2:
	imem_c_rg_cache_b16$D_IN = MUX_imem_c_rg_cache_b16$write_1__VAL_1;
    MUX_imem_c_rg_cache_b16$write_1__SEL_5:
	imem_c_rg_cache_b16$D_IN = MUX_imem_c_rg_cache_b16$write_1__VAL_1;
    MUX_imem_c_rg_cache_b16$write_1__SEL_6:
	imem_c_rg_cache_b16$D_IN = MUX_imem_c_rg_cache_b16$write_1__VAL_1;
    MUX_imem_c_rg_cache_b16$write_1__SEL_7:
	imem_c_rg_cache_b16$D_IN = MUX_imem_c_rg_cache_b16$write_1__VAL_1;
    MUX_imem_c_rg_cache_b16$write_1__SEL_8:
	imem_c_rg_cache_b16$D_IN = MUX_imem_c_rg_cache_b16$write_1__VAL_1;
    MUX_imem_c_rg_cache_b16$write_1__SEL_9:
	imem_c_rg_cache_b16$D_IN = MUX_imem_c_rg_cache_b16$write_1__VAL_1;
    MUX_imem_c_rg_cache_b16$write_1__SEL_10:
	imem_c_rg_cache_b16$D_IN = MUX_imem_c_rg_cache_b16$write_1__VAL_1;
    default: imem_c_rg_cache_b16$D_IN =
		 17'b01010101010101010 /* unspecified value */ ;
  endcase
  assign imem_c_rg_cache_b16$EN =
	     MUX_rg_state$write_1__SEL_6 && near_mem$imem_valid ||
	     WILL_FIRE_RL_rl_reset_complete && rg_run_on_reset &&
	     near_mem$imem_valid ||
	     WILL_FIRE_RL_rl_pipe &&
	     NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d1292 &&
	     near_mem$imem_valid ||
	     WILL_FIRE_RL_imem_c_rl_fetch_next_32b ||
	     WILL_FIRE_RL_rl_reset_start ;

  // register imem_c_rg_f3
  assign imem_c_rg_f3$D_IN = 3'b010 ;
  assign imem_c_rg_f3$EN =
	     WILL_FIRE_RL_rl_reset_complete && rg_run_on_reset ||
	     WILL_FIRE_RL_rl_pipe &&
	     NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d1275 ||
	     WILL_FIRE_RL_rl_trap_fetch ||
	     WILL_FIRE_RL_rl_WFI_resume ||
	     WILL_FIRE_RL_rl_finish_SFENCE_VMA ||
	     WILL_FIRE_RL_rl_finish_FENCE ||
	     WILL_FIRE_RL_rl_finish_FENCE_I ||
	     WILL_FIRE_RL_rl_stage1_restart_after_csrrx ;

  // register imem_c_rg_mstatus_MXR
  assign imem_c_rg_mstatus_MXR$D_IN =
	     (MUX_imem_c_rg_f3$write_1__SEL_1 ||
	      MUX_imem_c_rg_f3$write_1__SEL_2 ||
	      MUX_imem_c_rg_mstatus_MXR$write_1__SEL_4) ?
	       csr_regfile$read_mstatus[19] :
	       rg_mstatus_MXR ;
  assign imem_c_rg_mstatus_MXR$EN =
	     WILL_FIRE_RL_rl_reset_complete && rg_run_on_reset ||
	     WILL_FIRE_RL_rl_pipe &&
	     NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d1275 ||
	     WILL_FIRE_RL_rl_trap_fetch ||
	     WILL_FIRE_RL_rl_WFI_resume ||
	     WILL_FIRE_RL_rl_finish_SFENCE_VMA ||
	     WILL_FIRE_RL_rl_finish_FENCE ||
	     WILL_FIRE_RL_rl_finish_FENCE_I ||
	     WILL_FIRE_RL_rl_stage1_restart_after_csrrx ;

  // register imem_c_rg_pc
  always@(MUX_imem_c_rg_f3$write_1__SEL_1 or
	  soc_map$m_pc_reset_value or
	  MUX_imem_c_rg_f3$write_1__SEL_2 or
	  x_out_next_pc__h12736 or
	  WILL_FIRE_RL_rl_stage1_restart_after_csrrx or
	  MUX_imem_c_rg_pc$write_1__SEL_4 or rg_next_pc)
  begin
    case (1'b1) // synopsys parallel_case
      MUX_imem_c_rg_f3$write_1__SEL_1:
	  imem_c_rg_pc$D_IN = soc_map$m_pc_reset_value[31:0];
      MUX_imem_c_rg_f3$write_1__SEL_2:
	  imem_c_rg_pc$D_IN = x_out_next_pc__h12736;
      WILL_FIRE_RL_rl_stage1_restart_after_csrrx:
	  imem_c_rg_pc$D_IN = x_out_next_pc__h12736;
      MUX_imem_c_rg_pc$write_1__SEL_4: imem_c_rg_pc$D_IN = rg_next_pc;
      default: imem_c_rg_pc$D_IN = 32'hAAAAAAAA /* unspecified value */ ;
    endcase
  end
  assign imem_c_rg_pc$EN =
	     WILL_FIRE_RL_rl_reset_complete && rg_run_on_reset ||
	     WILL_FIRE_RL_rl_pipe &&
	     NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d1275 ||
	     WILL_FIRE_RL_rl_stage1_restart_after_csrrx ||
	     WILL_FIRE_RL_rl_trap_fetch ||
	     WILL_FIRE_RL_rl_WFI_resume ||
	     WILL_FIRE_RL_rl_finish_SFENCE_VMA ||
	     WILL_FIRE_RL_rl_finish_FENCE ||
	     WILL_FIRE_RL_rl_finish_FENCE_I ;

  // register imem_c_rg_priv
  assign imem_c_rg_priv$D_IN = rg_cur_priv ;
  assign imem_c_rg_priv$EN =
	     WILL_FIRE_RL_rl_reset_complete && rg_run_on_reset ||
	     WILL_FIRE_RL_rl_pipe &&
	     NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d1275 ||
	     WILL_FIRE_RL_rl_trap_fetch ||
	     WILL_FIRE_RL_rl_WFI_resume ||
	     WILL_FIRE_RL_rl_finish_SFENCE_VMA ||
	     WILL_FIRE_RL_rl_finish_FENCE ||
	     WILL_FIRE_RL_rl_finish_FENCE_I ||
	     WILL_FIRE_RL_rl_stage1_restart_after_csrrx ;

  // register imem_c_rg_satp
  assign imem_c_rg_satp$D_IN = csr_regfile$read_satp ;
  assign imem_c_rg_satp$EN =
	     WILL_FIRE_RL_rl_reset_complete && rg_run_on_reset ||
	     WILL_FIRE_RL_rl_pipe &&
	     NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d1275 ||
	     WILL_FIRE_RL_rl_trap_fetch ||
	     WILL_FIRE_RL_rl_WFI_resume ||
	     WILL_FIRE_RL_rl_finish_SFENCE_VMA ||
	     WILL_FIRE_RL_rl_finish_FENCE ||
	     WILL_FIRE_RL_rl_finish_FENCE_I ||
	     WILL_FIRE_RL_rl_stage1_restart_after_csrrx ;

  // register imem_c_rg_sstatus_SUM
  assign imem_c_rg_sstatus_SUM$D_IN =
	     WILL_FIRE_RL_rl_trap_fetch && rg_sstatus_SUM ;
  assign imem_c_rg_sstatus_SUM$EN =
	     WILL_FIRE_RL_rl_reset_complete && rg_run_on_reset ||
	     WILL_FIRE_RL_rl_pipe &&
	     NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d1275 ||
	     WILL_FIRE_RL_rl_trap_fetch ||
	     WILL_FIRE_RL_rl_WFI_resume ||
	     WILL_FIRE_RL_rl_finish_SFENCE_VMA ||
	     WILL_FIRE_RL_rl_finish_FENCE ||
	     WILL_FIRE_RL_rl_finish_FENCE_I ||
	     WILL_FIRE_RL_rl_stage1_restart_after_csrrx ;

  // register imem_c_rg_tval
  always@(MUX_imem_c_rg_f3$write_1__SEL_1 or
	  soc_map$m_pc_reset_value or
	  MUX_imem_c_rg_f3$write_1__SEL_2 or
	  x_out_next_pc__h12736 or
	  WILL_FIRE_RL_rl_stage1_restart_after_csrrx or
	  MUX_imem_c_rg_pc$write_1__SEL_4 or
	  rg_next_pc or
	  WILL_FIRE_RL_imem_c_rl_fetch_next_32b or
	  MUX_imem_c_rg_tval$write_1__VAL_5)
  begin
    case (1'b1) // synopsys parallel_case
      MUX_imem_c_rg_f3$write_1__SEL_1:
	  imem_c_rg_tval$D_IN = soc_map$m_pc_reset_value[31:0];
      MUX_imem_c_rg_f3$write_1__SEL_2:
	  imem_c_rg_tval$D_IN = x_out_next_pc__h12736;
      WILL_FIRE_RL_rl_stage1_restart_after_csrrx:
	  imem_c_rg_tval$D_IN = x_out_next_pc__h12736;
      MUX_imem_c_rg_pc$write_1__SEL_4: imem_c_rg_tval$D_IN = rg_next_pc;
      WILL_FIRE_RL_imem_c_rl_fetch_next_32b:
	  imem_c_rg_tval$D_IN = MUX_imem_c_rg_tval$write_1__VAL_5;
      default: imem_c_rg_tval$D_IN = 32'hAAAAAAAA /* unspecified value */ ;
    endcase
  end
  assign imem_c_rg_tval$EN =
	     WILL_FIRE_RL_rl_reset_complete && rg_run_on_reset ||
	     WILL_FIRE_RL_rl_pipe &&
	     NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d1275 ||
	     WILL_FIRE_RL_rl_stage1_restart_after_csrrx ||
	     WILL_FIRE_RL_rl_trap_fetch ||
	     WILL_FIRE_RL_rl_WFI_resume ||
	     WILL_FIRE_RL_rl_finish_SFENCE_VMA ||
	     WILL_FIRE_RL_rl_finish_FENCE ||
	     WILL_FIRE_RL_rl_finish_FENCE_I ||
	     WILL_FIRE_RL_imem_c_rl_fetch_next_32b ;

  // register rg_csr_pc
  assign rg_csr_pc$D_IN = imem_c_rg_pc ;
  assign rg_csr_pc$EN = MUX_rg_trap_info$write_1__SEL_1 ;

  // register rg_csr_val1
  assign rg_csr_val1$D_IN = x_out_data_to_stage2_val1__h12928 ;
  assign rg_csr_val1$EN = MUX_rg_trap_info$write_1__SEL_1 ;

  // register rg_cur_priv
  always@(WILL_FIRE_RL_rl_trap or
	  csr_regfile$csr_trap_actions or
	  WILL_FIRE_RL_rl_stage1_xRET or
	  csr_regfile$csr_ret_actions or WILL_FIRE_RL_rl_reset_start)
  begin
    case (1'b1) // synopsys parallel_case
      WILL_FIRE_RL_rl_trap:
	  rg_cur_priv$D_IN = csr_regfile$csr_trap_actions[1:0];
      WILL_FIRE_RL_rl_stage1_xRET:
	  rg_cur_priv$D_IN = csr_regfile$csr_ret_actions[33:32];
      WILL_FIRE_RL_rl_reset_start: rg_cur_priv$D_IN = 2'b11;
      default: rg_cur_priv$D_IN = 2'b10 /* unspecified value */ ;
    endcase
  end
  assign rg_cur_priv$EN =
	     WILL_FIRE_RL_rl_trap || WILL_FIRE_RL_rl_stage1_xRET ||
	     WILL_FIRE_RL_rl_reset_start ;

  // register rg_mstatus_MXR
  assign rg_mstatus_MXR$D_IN = csr_regfile$read_mstatus[19] ;
  assign rg_mstatus_MXR$EN = MUX_rg_state$write_1__SEL_8 ;

  // register rg_next_pc
  always@(MUX_rg_next_pc$write_1__SEL_1 or
	  x_out_next_pc__h12736 or
	  WILL_FIRE_RL_rl_trap or
	  csr_regfile$csr_trap_actions or
	  WILL_FIRE_RL_rl_stage1_xRET or csr_regfile$csr_ret_actions)
  begin
    case (1'b1) // synopsys parallel_case
      MUX_rg_next_pc$write_1__SEL_1: rg_next_pc$D_IN = x_out_next_pc__h12736;
      WILL_FIRE_RL_rl_trap:
	  rg_next_pc$D_IN = csr_regfile$csr_trap_actions[97:66];
      WILL_FIRE_RL_rl_stage1_xRET:
	  rg_next_pc$D_IN = csr_regfile$csr_ret_actions[65:34];
      default: rg_next_pc$D_IN = 32'hAAAAAAAA /* unspecified value */ ;
    endcase
  end
  assign rg_next_pc$EN =
	     WILL_FIRE_RL_rl_stage1_WFI || WILL_FIRE_RL_rl_stage1_FENCE ||
	     WILL_FIRE_RL_rl_stage1_FENCE_I ||
	     WILL_FIRE_RL_rl_stage1_CSRR_S_or_C ||
	     WILL_FIRE_RL_rl_stage1_CSRR_W ||
	     WILL_FIRE_RL_rl_trap ||
	     WILL_FIRE_RL_rl_stage1_xRET ;

  // register rg_run_on_reset
  assign rg_run_on_reset$D_IN = f_reset_reqs$D_OUT ;
  assign rg_run_on_reset$EN = MUX_rg_state$write_1__SEL_5 ;

  // register rg_sstatus_SUM
  assign rg_sstatus_SUM$D_IN = 1'd0 ;
  assign rg_sstatus_SUM$EN = MUX_rg_state$write_1__SEL_8 ;

  // register rg_start_CPI_cycles
  assign rg_start_CPI_cycles$D_IN = csr_regfile$read_csr_mcycle ;
  assign rg_start_CPI_cycles$EN = MUX_imem_c_rg_f3$write_1__SEL_1 ;

  // register rg_start_CPI_instrs
  assign rg_start_CPI_instrs$D_IN = csr_regfile$read_csr_minstret ;
  assign rg_start_CPI_instrs$EN = MUX_imem_c_rg_f3$write_1__SEL_1 ;

  // register rg_state
  always@(WILL_FIRE_RL_rl_reset_complete or
	  MUX_rg_state$write_1__VAL_1 or
	  WILL_FIRE_RL_rl_stage1_CSRR_W_2 or
	  MUX_rg_state$write_1__VAL_2 or
	  WILL_FIRE_RL_rl_stage1_CSRR_S_or_C_2 or
	  MUX_rg_state$write_1__VAL_3 or
	  WILL_FIRE_RL_rl_reset_from_WFI or
	  WILL_FIRE_RL_rl_reset_start or
	  MUX_rg_state$write_1__SEL_6 or
	  MUX_rg_state$write_1__SEL_7 or
	  MUX_rg_state$write_1__SEL_8 or
	  WILL_FIRE_RL_rl_stage1_CSRR_W or
	  WILL_FIRE_RL_rl_stage1_CSRR_S_or_C or
	  WILL_FIRE_RL_rl_stage1_FENCE_I or
	  WILL_FIRE_RL_rl_stage1_FENCE or WILL_FIRE_RL_rl_stage1_WFI)
  begin
    case (1'b1) // synopsys parallel_case
      WILL_FIRE_RL_rl_reset_complete:
	  rg_state$D_IN = MUX_rg_state$write_1__VAL_1;
      WILL_FIRE_RL_rl_stage1_CSRR_W_2:
	  rg_state$D_IN = MUX_rg_state$write_1__VAL_2;
      WILL_FIRE_RL_rl_stage1_CSRR_S_or_C_2:
	  rg_state$D_IN = MUX_rg_state$write_1__VAL_3;
      WILL_FIRE_RL_rl_reset_from_WFI: rg_state$D_IN = 4'd0;
      WILL_FIRE_RL_rl_reset_start: rg_state$D_IN = 4'd1;
      MUX_rg_state$write_1__SEL_6: rg_state$D_IN = 4'd3;
      MUX_rg_state$write_1__SEL_7: rg_state$D_IN = 4'd4;
      MUX_rg_state$write_1__SEL_8: rg_state$D_IN = 4'd5;
      WILL_FIRE_RL_rl_stage1_CSRR_W: rg_state$D_IN = 4'd6;
      WILL_FIRE_RL_rl_stage1_CSRR_S_or_C: rg_state$D_IN = 4'd7;
      WILL_FIRE_RL_rl_stage1_FENCE_I: rg_state$D_IN = 4'd9;
      WILL_FIRE_RL_rl_stage1_FENCE: rg_state$D_IN = 4'd10;
      WILL_FIRE_RL_rl_stage1_WFI: rg_state$D_IN = 4'd12;
      default: rg_state$D_IN = 4'b1010 /* unspecified value */ ;
    endcase
  end
  assign rg_state$EN =
	     WILL_FIRE_RL_rl_reset_complete ||
	     WILL_FIRE_RL_rl_stage1_CSRR_W_2 ||
	     WILL_FIRE_RL_rl_stage1_CSRR_S_or_C_2 ||
	     WILL_FIRE_RL_rl_reset_from_WFI ||
	     WILL_FIRE_RL_rl_reset_start ||
	     WILL_FIRE_RL_rl_trap_fetch ||
	     WILL_FIRE_RL_rl_WFI_resume ||
	     WILL_FIRE_RL_rl_finish_SFENCE_VMA ||
	     WILL_FIRE_RL_rl_finish_FENCE ||
	     WILL_FIRE_RL_rl_finish_FENCE_I ||
	     WILL_FIRE_RL_rl_stage1_restart_after_csrrx ||
	     WILL_FIRE_RL_rl_stage1_interrupt ||
	     WILL_FIRE_RL_rl_stage1_trap ||
	     WILL_FIRE_RL_rl_stage2_nonpipe ||
	     WILL_FIRE_RL_rl_stage1_xRET ||
	     WILL_FIRE_RL_rl_trap ||
	     WILL_FIRE_RL_rl_stage1_CSRR_W ||
	     WILL_FIRE_RL_rl_stage1_CSRR_S_or_C ||
	     WILL_FIRE_RL_rl_stage1_FENCE_I ||
	     WILL_FIRE_RL_rl_stage1_FENCE ||
	     WILL_FIRE_RL_rl_stage1_WFI ;

  // register rg_trap_info
  always@(MUX_rg_trap_info$write_1__SEL_1 or
	  MUX_rg_trap_info$write_1__VAL_1 or
	  WILL_FIRE_RL_rl_stage2_nonpipe or
	  MUX_rg_trap_info$write_1__VAL_2 or
	  WILL_FIRE_RL_rl_stage1_trap or
	  MUX_rg_trap_info$write_1__VAL_3 or
	  WILL_FIRE_RL_rl_stage1_interrupt or MUX_rg_trap_info$write_1__VAL_4)
  begin
    case (1'b1) // synopsys parallel_case
      MUX_rg_trap_info$write_1__SEL_1:
	  rg_trap_info$D_IN = MUX_rg_trap_info$write_1__VAL_1;
      WILL_FIRE_RL_rl_stage2_nonpipe:
	  rg_trap_info$D_IN = MUX_rg_trap_info$write_1__VAL_2;
      WILL_FIRE_RL_rl_stage1_trap:
	  rg_trap_info$D_IN = MUX_rg_trap_info$write_1__VAL_3;
      WILL_FIRE_RL_rl_stage1_interrupt:
	  rg_trap_info$D_IN = MUX_rg_trap_info$write_1__VAL_4;
      default: rg_trap_info$D_IN =
		   68'hAAAAAAAAAAAAAAAAA /* unspecified value */ ;
    endcase
  end
  assign rg_trap_info$EN =
	     WILL_FIRE_RL_rl_stage1_CSRR_S_or_C ||
	     WILL_FIRE_RL_rl_stage1_CSRR_W ||
	     WILL_FIRE_RL_rl_stage2_nonpipe ||
	     WILL_FIRE_RL_rl_stage1_trap ||
	     WILL_FIRE_RL_rl_stage1_interrupt ;

  // register rg_trap_instr
  assign rg_trap_instr$D_IN =
	     MUX_rg_trap_instr$write_1__SEL_1 ?
	       x_out_data_to_stage2_instr__h12924 :
	       stage2_rg_stage2[135:104] ;
  assign rg_trap_instr$EN =
	     WILL_FIRE_RL_rl_stage1_interrupt ||
	     WILL_FIRE_RL_rl_stage1_CSRR_S_or_C ||
	     WILL_FIRE_RL_rl_stage1_CSRR_W ||
	     WILL_FIRE_RL_rl_stage1_trap ||
	     WILL_FIRE_RL_rl_stage2_nonpipe ;

  // register rg_trap_interrupt
  assign rg_trap_interrupt$D_IN = !MUX_rg_trap_interrupt$write_1__SEL_1 ;
  assign rg_trap_interrupt$EN =
	     WILL_FIRE_RL_rl_stage1_CSRR_S_or_C ||
	     WILL_FIRE_RL_rl_stage1_CSRR_W ||
	     WILL_FIRE_RL_rl_stage1_trap ||
	     WILL_FIRE_RL_rl_stage2_nonpipe ||
	     WILL_FIRE_RL_rl_stage1_interrupt ;

  // register stage1_rg_full
  always@(WILL_FIRE_RL_stage1_rl_reset or
	  WILL_FIRE_RL_rl_pipe or
	  MUX_stage1_rg_full$write_1__VAL_2 or
	  MUX_imem_c_rg_f3$write_1__SEL_1 or
	  WILL_FIRE_RL_rl_trap_fetch or
	  WILL_FIRE_RL_rl_WFI_resume or
	  WILL_FIRE_RL_rl_stage1_WFI or
	  WILL_FIRE_RL_rl_finish_SFENCE_VMA or
	  WILL_FIRE_RL_rl_finish_FENCE or
	  WILL_FIRE_RL_rl_finish_FENCE_I or
	  WILL_FIRE_RL_rl_stage1_xRET or
	  WILL_FIRE_RL_rl_stage1_restart_after_csrrx or WILL_FIRE_RL_rl_trap)
  case (1'b1)
    WILL_FIRE_RL_stage1_rl_reset: stage1_rg_full$D_IN = 1'd0;
    WILL_FIRE_RL_rl_pipe:
	stage1_rg_full$D_IN = MUX_stage1_rg_full$write_1__VAL_2;
    MUX_imem_c_rg_f3$write_1__SEL_1 || WILL_FIRE_RL_rl_trap_fetch ||
    WILL_FIRE_RL_rl_WFI_resume:
	stage1_rg_full$D_IN = 1'd1;
    WILL_FIRE_RL_rl_stage1_WFI: stage1_rg_full$D_IN = 1'd0;
    WILL_FIRE_RL_rl_finish_SFENCE_VMA || WILL_FIRE_RL_rl_finish_FENCE ||
    WILL_FIRE_RL_rl_finish_FENCE_I:
	stage1_rg_full$D_IN = 1'd1;
    WILL_FIRE_RL_rl_stage1_xRET: stage1_rg_full$D_IN = 1'd0;
    WILL_FIRE_RL_rl_stage1_restart_after_csrrx: stage1_rg_full$D_IN = 1'd1;
    WILL_FIRE_RL_rl_trap: stage1_rg_full$D_IN = 1'd0;
    default: stage1_rg_full$D_IN = 1'b0 /* unspecified value */ ;
  endcase
  assign stage1_rg_full$EN =
	     WILL_FIRE_RL_rl_reset_complete && rg_run_on_reset ||
	     WILL_FIRE_RL_rl_pipe ||
	     WILL_FIRE_RL_rl_stage1_WFI ||
	     WILL_FIRE_RL_rl_stage1_xRET ||
	     WILL_FIRE_RL_rl_trap ||
	     WILL_FIRE_RL_stage1_rl_reset ||
	     WILL_FIRE_RL_rl_trap_fetch ||
	     WILL_FIRE_RL_rl_WFI_resume ||
	     WILL_FIRE_RL_rl_finish_SFENCE_VMA ||
	     WILL_FIRE_RL_rl_finish_FENCE ||
	     WILL_FIRE_RL_rl_finish_FENCE_I ||
	     WILL_FIRE_RL_rl_stage1_restart_after_csrrx ;

  // register stage2_rg_full
  always@(stage2_f_reset_reqs$EMPTY_N or
	  WILL_FIRE_RL_rl_pipe or
	  MUX_stage2_rg_full$write_1__VAL_2 or
	  MUX_imem_c_rg_f3$write_1__SEL_1 or WILL_FIRE_RL_rl_trap)
  case (1'b1)
    stage2_f_reset_reqs$EMPTY_N: stage2_rg_full$D_IN = 1'd0;
    WILL_FIRE_RL_rl_pipe:
	stage2_rg_full$D_IN = MUX_stage2_rg_full$write_1__VAL_2;
    MUX_imem_c_rg_f3$write_1__SEL_1 || WILL_FIRE_RL_rl_trap:
	stage2_rg_full$D_IN = 1'd0;
    default: stage2_rg_full$D_IN = 1'b0 /* unspecified value */ ;
  endcase
  assign stage2_rg_full$EN =
	     WILL_FIRE_RL_rl_reset_complete && rg_run_on_reset ||
	     WILL_FIRE_RL_rl_pipe ||
	     WILL_FIRE_RL_rl_trap ||
	     stage2_f_reset_reqs$EMPTY_N ;

  // register stage2_rg_resetting
  assign stage2_rg_resetting$D_IN = stage2_f_reset_reqs$EMPTY_N ;
  assign stage2_rg_resetting$EN =
	     WILL_FIRE_RL_stage2_rl_reset_end || stage2_f_reset_reqs$EMPTY_N ;

  // register stage2_rg_stage2
  assign stage2_rg_stage2$D_IN =
	     { rg_cur_priv,
	       imem_c_rg_pc,
	       IF_imem_c_rg_pc_BITS_1_TO_0_EQ_0b0_OR_NOT_imem_ETC___d1227 } ;
  assign stage2_rg_stage2$EN =
	     WILL_FIRE_RL_rl_pipe &&
	     NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d1213 &&
	     stage1_rg_full &&
	     near_mem_imem_valid_AND_NOT_imem_c_rg_pc_BITS__ETC___d1214 ;

  // register stage3_rg_full
  always@(WILL_FIRE_RL_stage3_rl_reset or
	  WILL_FIRE_RL_rl_pipe or
	  MUX_stage3_rg_full$write_1__VAL_2 or
	  MUX_imem_c_rg_f3$write_1__SEL_1)
  case (1'b1)
    WILL_FIRE_RL_stage3_rl_reset: stage3_rg_full$D_IN = 1'd0;
    WILL_FIRE_RL_rl_pipe:
	stage3_rg_full$D_IN = MUX_stage3_rg_full$write_1__VAL_2;
    MUX_imem_c_rg_f3$write_1__SEL_1: stage3_rg_full$D_IN = 1'd0;
    default: stage3_rg_full$D_IN = 1'b0 /* unspecified value */ ;
  endcase
  assign stage3_rg_full$EN =
	     WILL_FIRE_RL_rl_reset_complete && rg_run_on_reset ||
	     WILL_FIRE_RL_rl_pipe ||
	     WILL_FIRE_RL_stage3_rl_reset ;

  // register stage3_rg_stage3
  assign stage3_rg_stage3$D_IN =
	     { stage2_rg_stage2[167:104],
	       stage2_rg_stage2[169:168],
	       1'd1,
	       x_out_data_to_stage3_rd__h6401,
	       x_out_data_to_stage3_rd_val__h6402 } ;
  assign stage3_rg_stage3$EN =
	     WILL_FIRE_RL_rl_pipe && stage2_rg_full &&
	     (stage2_rg_stage2[103:101] == 3'd0 ||
	      IF_stage2_rg_stage2_1_BITS_103_TO_101_2_EQ_1_4_ETC___d1196) ;

  // submodule csr_regfile
  assign csr_regfile$access_permitted_1_csr_addr = rg_trap_instr[31:20] ;
  assign csr_regfile$access_permitted_1_priv = rg_cur_priv ;
  assign csr_regfile$access_permitted_1_read_not_write = 1'd0 ;
  assign csr_regfile$access_permitted_2_csr_addr = rg_trap_instr[31:20] ;
  assign csr_regfile$access_permitted_2_priv = rg_cur_priv ;
  assign csr_regfile$access_permitted_2_read_not_write =
	     rs1_val__h21423 == 32'd0 ;
  assign csr_regfile$csr_counter_read_fault_csr_addr = 12'h0 ;
  assign csr_regfile$csr_counter_read_fault_priv = 2'h0 ;
  assign csr_regfile$csr_ret_actions_from_priv =
	     (!near_mem$imem_exc && _theResult____h4859[6:0] == 7'b1110011 &&
	      IF_imem_c_rg_pc_BITS_1_TO_0_EQ_0b0_OR_NOT_imem_ETC___d801) ?
	       2'b11 :
	       2'b0 ;
  assign csr_regfile$csr_trap_actions_exc_code = rg_trap_info[35:32] ;
  assign csr_regfile$csr_trap_actions_from_priv = rg_cur_priv ;
  assign csr_regfile$csr_trap_actions_interrupt =
	     rg_trap_interrupt && !csr_regfile$nmi_pending ;
  assign csr_regfile$csr_trap_actions_nmi =
	     rg_trap_interrupt && csr_regfile$nmi_pending ;
  assign csr_regfile$csr_trap_actions_pc = rg_trap_info[67:36] ;
  assign csr_regfile$csr_trap_actions_xtval = rg_trap_info[31:0] ;
  assign csr_regfile$interrupt_pending_cur_priv = rg_cur_priv ;
  assign csr_regfile$m_external_interrupt_req_set_not_clear =
	     m_external_interrupt_req_set_not_clear ;
  assign csr_regfile$mav_csr_write_csr_addr = rg_trap_instr[31:20] ;
  assign csr_regfile$mav_csr_write_word =
	     MUX_csr_regfile$mav_csr_write_1__SEL_1 ?
	       rs1_val__h20670 :
	       MUX_csr_regfile$mav_csr_write_2__VAL_2 ;
  assign csr_regfile$mav_read_csr_csr_addr = 12'h0 ;
  assign csr_regfile$nmi_req_set_not_clear = nmi_req_set_not_clear ;
  assign csr_regfile$read_csr_csr_addr = rg_trap_instr[31:20] ;
  assign csr_regfile$read_csr_port2_csr_addr = 12'h0 ;
  assign csr_regfile$s_external_interrupt_req_set_not_clear =
	     s_external_interrupt_req_set_not_clear ;
  assign csr_regfile$software_interrupt_req_set_not_clear =
	     software_interrupt_req_set_not_clear ;
  assign csr_regfile$timer_interrupt_req_set_not_clear =
	     timer_interrupt_req_set_not_clear ;
  assign csr_regfile$EN_server_reset_request_put =
	     MUX_rg_state$write_1__SEL_5 ;
  assign csr_regfile$EN_server_reset_response_get =
	     MUX_rg_state$write_1__SEL_1 ;
  assign csr_regfile$EN_mav_read_csr = 1'b0 ;
  assign csr_regfile$EN_mav_csr_write =
	     WILL_FIRE_RL_rl_stage1_CSRR_W_2 &&
	     csr_regfile$access_permitted_1 ||
	     WILL_FIRE_RL_rl_stage1_CSRR_S_or_C_2 &&
	     csr_regfile$access_permitted_2 &&
	     rg_trap_instr[19:15] != 5'd0 ;
  assign csr_regfile$EN_csr_trap_actions = CAN_FIRE_RL_rl_trap ;
  assign csr_regfile$EN_csr_ret_actions = CAN_FIRE_RL_rl_stage1_xRET ;
  assign csr_regfile$EN_csr_minstret_incr =
	     WILL_FIRE_RL_rl_pipe && stage2_rg_full &&
	     (stage2_rg_stage2[103:101] == 3'd0 ||
	      IF_stage2_rg_stage2_1_BITS_103_TO_101_2_EQ_1_4_ETC___d1196) ||
	     WILL_FIRE_RL_rl_stage1_CSRR_W_2 &&
	     csr_regfile$access_permitted_1 ||
	     WILL_FIRE_RL_rl_stage1_CSRR_S_or_C_2 &&
	     csr_regfile$access_permitted_2 ||
	     WILL_FIRE_RL_rl_stage1_WFI ||
	     WILL_FIRE_RL_rl_stage1_FENCE ||
	     WILL_FIRE_RL_rl_stage1_FENCE_I ||
	     WILL_FIRE_RL_rl_stage1_xRET ;
  assign csr_regfile$EN_debug = 1'b0 ;

  // submodule f_reset_reqs
  assign f_reset_reqs$D_IN = hart0_server_reset_request_put ;
  assign f_reset_reqs$ENQ = EN_hart0_server_reset_request_put ;
  assign f_reset_reqs$DEQ =
	     gpr_regfile_RDY_server_reset_request_put__089__ETC___d1101 &&
	     rg_state == 4'd0 ;
  assign f_reset_reqs$CLR = 1'b0 ;

  // submodule f_reset_rsps
  assign f_reset_rsps$D_IN = rg_run_on_reset ;
  assign f_reset_rsps$ENQ = MUX_rg_state$write_1__SEL_1 ;
  assign f_reset_rsps$DEQ = EN_hart0_server_reset_response_get ;
  assign f_reset_rsps$CLR = 1'b0 ;

  // submodule gpr_regfile
  assign gpr_regfile$read_rs1_port2_rs1 = 5'h0 ;
  assign gpr_regfile$read_rs1_rs1 = _theResult____h4859[19:15] ;
  assign gpr_regfile$read_rs2_rs2 = _theResult____h4859[24:20] ;
  assign gpr_regfile$write_rd_rd =
	     (MUX_csr_regfile$mav_csr_write_1__SEL_1 ||
	      MUX_gpr_regfile$write_rd_1__SEL_3) ?
	       rg_trap_instr[11:7] :
	       stage3_rg_stage3[36:32] ;
  assign gpr_regfile$write_rd_rd_val =
	     (MUX_csr_regfile$mav_csr_write_1__SEL_1 ||
	      MUX_gpr_regfile$write_rd_1__SEL_3) ?
	       csr_regfile$read_csr[31:0] :
	       stage3_rg_stage3[31:0] ;
  assign gpr_regfile$EN_server_reset_request_put =
	     MUX_rg_state$write_1__SEL_5 ;
  assign gpr_regfile$EN_server_reset_response_get =
	     MUX_rg_state$write_1__SEL_1 ;
  assign gpr_regfile$EN_write_rd =
	     WILL_FIRE_RL_rl_pipe && stage3_rg_full && stage3_rg_stage3[37] ||
	     WILL_FIRE_RL_rl_stage1_CSRR_W_2 &&
	     csr_regfile$access_permitted_1 ||
	     WILL_FIRE_RL_rl_stage1_CSRR_S_or_C_2 &&
	     csr_regfile$access_permitted_2 ;

  // submodule near_mem
  assign near_mem$dmem_master_arready = dmem_master_arready ;
  assign near_mem$dmem_master_awready = dmem_master_awready ;
  assign near_mem$dmem_master_bid = dmem_master_bid ;
  assign near_mem$dmem_master_bresp = dmem_master_bresp ;
  assign near_mem$dmem_master_bvalid = dmem_master_bvalid ;
  assign near_mem$dmem_master_rdata = dmem_master_rdata ;
  assign near_mem$dmem_master_rid = dmem_master_rid ;
  assign near_mem$dmem_master_rlast = dmem_master_rlast ;
  assign near_mem$dmem_master_rresp = dmem_master_rresp ;
  assign near_mem$dmem_master_rvalid = dmem_master_rvalid ;
  assign near_mem$dmem_master_wready = dmem_master_wready ;
  assign near_mem$dmem_req_addr = x_out_data_to_stage2_addr__h12927 ;
  assign near_mem$dmem_req_amo_funct7 =
	     x_out_data_to_stage2_val1__h12928[6:0] ;
  assign near_mem$dmem_req_f3 = x_out_data_to_stage2_instr__h12924[14:12] ;
  assign near_mem$dmem_req_mstatus_MXR = csr_regfile$read_mstatus[19] ;
  always@(_theResult____h4859)
  begin
    case (_theResult____h4859[6:0])
      7'b0000011: near_mem$dmem_req_op = 2'd0;
      7'b0100011: near_mem$dmem_req_op = 2'd1;
      default: near_mem$dmem_req_op = 2'd2;
    endcase
  end
  assign near_mem$dmem_req_priv =
	     csr_regfile$read_mstatus[17] ?
	       csr_regfile$read_mstatus[12:11] :
	       rg_cur_priv ;
  assign near_mem$dmem_req_satp = csr_regfile$read_satp ;
  assign near_mem$dmem_req_sstatus_SUM = 1'd0 ;
  assign near_mem$dmem_req_store_value =
	     { 32'd0, data_to_stage2_val2__h12921 } ;
  assign near_mem$imem_master_arready = imem_master_arready ;
  assign near_mem$imem_master_awready = imem_master_awready ;
  assign near_mem$imem_master_bid = imem_master_bid ;
  assign near_mem$imem_master_bresp = imem_master_bresp ;
  assign near_mem$imem_master_bvalid = imem_master_bvalid ;
  assign near_mem$imem_master_rdata = imem_master_rdata ;
  assign near_mem$imem_master_rid = imem_master_rid ;
  assign near_mem$imem_master_rlast = imem_master_rlast ;
  assign near_mem$imem_master_rresp = imem_master_rresp ;
  assign near_mem$imem_master_rvalid = imem_master_rvalid ;
  assign near_mem$imem_master_wready = imem_master_wready ;
  always@(MUX_imem_c_rg_f3$write_1__SEL_1 or
	  MUX_near_mem$imem_req_2__VAL_1 or
	  MUX_imem_c_rg_f3$write_1__SEL_2 or
	  MUX_near_mem$imem_req_2__VAL_2 or
	  WILL_FIRE_RL_imem_c_rl_fetch_next_32b or
	  MUX_imem_c_rg_tval$write_1__VAL_5 or
	  WILL_FIRE_RL_rl_stage1_restart_after_csrrx or
	  WILL_FIRE_RL_rl_trap_fetch or
	  MUX_near_mem$imem_req_2__VAL_5 or MUX_near_mem$imem_req_1__SEL_6)
  begin
    case (1'b1) // synopsys parallel_case
      MUX_imem_c_rg_f3$write_1__SEL_1:
	  near_mem$imem_req_addr = MUX_near_mem$imem_req_2__VAL_1;
      MUX_imem_c_rg_f3$write_1__SEL_2:
	  near_mem$imem_req_addr = MUX_near_mem$imem_req_2__VAL_2;
      WILL_FIRE_RL_imem_c_rl_fetch_next_32b:
	  near_mem$imem_req_addr = MUX_imem_c_rg_tval$write_1__VAL_5;
      WILL_FIRE_RL_rl_stage1_restart_after_csrrx:
	  near_mem$imem_req_addr = MUX_near_mem$imem_req_2__VAL_2;
      WILL_FIRE_RL_rl_trap_fetch:
	  near_mem$imem_req_addr = MUX_near_mem$imem_req_2__VAL_5;
      MUX_near_mem$imem_req_1__SEL_6:
	  near_mem$imem_req_addr = MUX_near_mem$imem_req_2__VAL_5;
      default: near_mem$imem_req_addr = 32'hAAAAAAAA /* unspecified value */ ;
    endcase
  end
  assign near_mem$imem_req_f3 =
	     WILL_FIRE_RL_imem_c_rl_fetch_next_32b ? imem_c_rg_f3 : 3'b010 ;
  always@(MUX_imem_c_rg_f3$write_1__SEL_1 or
	  MUX_imem_c_rg_f3$write_1__SEL_2 or
	  WILL_FIRE_RL_rl_stage1_restart_after_csrrx or
	  MUX_near_mem$imem_req_1__SEL_6 or
	  csr_regfile$read_mstatus or
	  WILL_FIRE_RL_rl_trap_fetch or
	  rg_mstatus_MXR or
	  WILL_FIRE_RL_imem_c_rl_fetch_next_32b or imem_c_rg_mstatus_MXR)
  begin
    case (1'b1) // synopsys parallel_case
      MUX_imem_c_rg_f3$write_1__SEL_1 || MUX_imem_c_rg_f3$write_1__SEL_2 ||
      WILL_FIRE_RL_rl_stage1_restart_after_csrrx ||
      MUX_near_mem$imem_req_1__SEL_6:
	  near_mem$imem_req_mstatus_MXR = csr_regfile$read_mstatus[19];
      WILL_FIRE_RL_rl_trap_fetch:
	  near_mem$imem_req_mstatus_MXR = rg_mstatus_MXR;
      WILL_FIRE_RL_imem_c_rl_fetch_next_32b:
	  near_mem$imem_req_mstatus_MXR = imem_c_rg_mstatus_MXR;
      default: near_mem$imem_req_mstatus_MXR = 1'b0 /* unspecified value */ ;
    endcase
  end
  assign near_mem$imem_req_priv =
	     (MUX_imem_c_rg_f3$write_1__SEL_1 ||
	      MUX_imem_c_rg_f3$write_1__SEL_2 ||
	      WILL_FIRE_RL_rl_stage1_restart_after_csrrx ||
	      WILL_FIRE_RL_rl_trap_fetch ||
	      MUX_near_mem$imem_req_1__SEL_6) ?
	       rg_cur_priv :
	       imem_c_rg_priv ;
  assign near_mem$imem_req_satp =
	     WILL_FIRE_RL_imem_c_rl_fetch_next_32b ?
	       imem_c_rg_satp :
	       csr_regfile$read_satp ;
  always@(WILL_FIRE_RL_rl_trap_fetch or
	  rg_sstatus_SUM or
	  WILL_FIRE_RL_imem_c_rl_fetch_next_32b or
	  imem_c_rg_sstatus_SUM or
	  MUX_imem_c_rg_f3$write_1__SEL_1 or
	  MUX_imem_c_rg_f3$write_1__SEL_2 or
	  WILL_FIRE_RL_rl_stage1_restart_after_csrrx or
	  MUX_near_mem$imem_req_1__SEL_6)
  begin
    case (1'b1) // synopsys parallel_case
      WILL_FIRE_RL_rl_trap_fetch:
	  near_mem$imem_req_sstatus_SUM = rg_sstatus_SUM;
      WILL_FIRE_RL_imem_c_rl_fetch_next_32b:
	  near_mem$imem_req_sstatus_SUM = imem_c_rg_sstatus_SUM;
      MUX_imem_c_rg_f3$write_1__SEL_1 || MUX_imem_c_rg_f3$write_1__SEL_2 ||
      WILL_FIRE_RL_rl_stage1_restart_after_csrrx ||
      MUX_near_mem$imem_req_1__SEL_6:
	  near_mem$imem_req_sstatus_SUM = 1'd0;
      default: near_mem$imem_req_sstatus_SUM = 1'b0 /* unspecified value */ ;
    endcase
  end
  assign near_mem$server_fence_request_put =
	     8'b10101010 /* unspecified value */  ;
  assign near_mem$EN_server_reset_request_put = MUX_rg_state$write_1__SEL_5 ;
  assign near_mem$EN_server_reset_response_get = MUX_rg_state$write_1__SEL_1 ;
  assign near_mem$EN_imem_req =
	     WILL_FIRE_RL_rl_reset_complete && rg_run_on_reset ||
	     WILL_FIRE_RL_rl_pipe &&
	     NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d1275 ||
	     WILL_FIRE_RL_imem_c_rl_fetch_next_32b ||
	     WILL_FIRE_RL_rl_stage1_restart_after_csrrx ||
	     WILL_FIRE_RL_rl_trap_fetch ||
	     WILL_FIRE_RL_rl_WFI_resume ||
	     WILL_FIRE_RL_rl_finish_SFENCE_VMA ||
	     WILL_FIRE_RL_rl_finish_FENCE ||
	     WILL_FIRE_RL_rl_finish_FENCE_I ;
  assign near_mem$EN_dmem_req =
	     WILL_FIRE_RL_rl_pipe &&
	     NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d1238 ;
  assign near_mem$EN_server_fence_i_request_put =
	     MUX_rg_state$write_1__SEL_11 ;
  assign near_mem$EN_server_fence_i_response_get =
	     CAN_FIRE_RL_rl_finish_FENCE_I ;
  assign near_mem$EN_server_fence_request_put = MUX_rg_state$write_1__SEL_12 ;
  assign near_mem$EN_server_fence_response_get = CAN_FIRE_RL_rl_finish_FENCE ;
  assign near_mem$EN_sfence_vma = 1'b0 ;

  // submodule soc_map
  assign soc_map$m_is_IO_addr_addr = 64'h0 ;
  assign soc_map$m_is_mem_addr_addr = 64'h0 ;
  assign soc_map$m_is_near_mem_IO_addr_addr = 64'h0 ;

  // submodule stage1_f_reset_reqs
  assign stage1_f_reset_reqs$ENQ = MUX_rg_state$write_1__SEL_5 ;
  assign stage1_f_reset_reqs$DEQ = CAN_FIRE_RL_stage1_rl_reset ;
  assign stage1_f_reset_reqs$CLR = 1'b0 ;

  // submodule stage1_f_reset_rsps
  assign stage1_f_reset_rsps$ENQ = CAN_FIRE_RL_stage1_rl_reset ;
  assign stage1_f_reset_rsps$DEQ = MUX_rg_state$write_1__SEL_1 ;
  assign stage1_f_reset_rsps$CLR = 1'b0 ;

  // submodule stage2_f_reset_reqs
  assign stage2_f_reset_reqs$ENQ = MUX_rg_state$write_1__SEL_5 ;
  assign stage2_f_reset_reqs$DEQ = stage2_f_reset_reqs$EMPTY_N ;
  assign stage2_f_reset_reqs$CLR = 1'b0 ;

  // submodule stage2_f_reset_rsps
  assign stage2_f_reset_rsps$ENQ = CAN_FIRE_RL_stage2_rl_reset_end ;
  assign stage2_f_reset_rsps$DEQ = MUX_rg_state$write_1__SEL_1 ;
  assign stage2_f_reset_rsps$CLR = 1'b0 ;

  // submodule stage2_mbox
  assign stage2_mbox$req_f3 = x_out_data_to_stage2_instr__h12924[14:12] ;
  assign stage2_mbox$req_is_OP_not_OP_32 = !_theResult____h4859[3] ;
  assign stage2_mbox$req_v1 = x_out_data_to_stage2_val1__h12928 ;
  assign stage2_mbox$req_v2 = x_out_data_to_stage2_val2__h12929 ;
  assign stage2_mbox$set_verbosity_verbosity = 4'h0 ;
  assign stage2_mbox$EN_set_verbosity = 1'b0 ;
  assign stage2_mbox$EN_req_reset = 1'b0 ;
  assign stage2_mbox$EN_rsp_reset = 1'b0 ;
  assign stage2_mbox$EN_req =
	     WILL_FIRE_RL_rl_pipe &&
	     NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d1213 &&
	     stage1_rg_full &&
	     near_mem_imem_valid_AND_NOT_imem_c_rg_pc_BITS__ETC___d1214 &&
	     _theResult____h4859[6:0] == 7'b0110011 &&
	     _theResult____h4859[31:25] == 7'b0000001 ;

  // submodule stage3_f_reset_reqs
  assign stage3_f_reset_reqs$ENQ = MUX_rg_state$write_1__SEL_5 ;
  assign stage3_f_reset_reqs$DEQ = CAN_FIRE_RL_stage3_rl_reset ;
  assign stage3_f_reset_reqs$CLR = 1'b0 ;

  // submodule stage3_f_reset_rsps
  assign stage3_f_reset_rsps$ENQ = CAN_FIRE_RL_stage3_rl_reset ;
  assign stage3_f_reset_rsps$DEQ = MUX_rg_state$write_1__SEL_1 ;
  assign stage3_f_reset_rsps$CLR = 1'b0 ;

  // remaining internal signals
  assign IF_IF_imem_c_rg_pc_BITS_1_TO_0_EQ_0b0_OR_NOT_i_ETC___d1012 =
	     ((_theResult____h4859[6:0] == 7'b0010011 ||
	       _theResult____h4859[6:0] == 7'b0110011) &&
	      (_theResult____h4859[14:12] == 3'b001 ||
	       _theResult____h4859[14:12] == 3'b101)) ?
	       alu_outputs___1_val1__h13250 :
	       IF_IF_imem_c_rg_pc_BITS_1_TO_0_EQ_0b0_OR_NOT_i_ETC___d1011 ;
  assign IF_IF_imem_c_rg_pc_BITS_1_TO_0_EQ_0b0_OR_NOT_i_ETC___d1013 =
	     (_theResult____h4859[6:0] == 7'b0110011 &&
	      _theResult____h4859[31:25] == 7'b0000001) ?
	       rs1_val_bypassed__h4867 :
	       IF_IF_imem_c_rg_pc_BITS_1_TO_0_EQ_0b0_OR_NOT_i_ETC___d1012 ;
  assign IF_IF_imem_c_rg_pc_BITS_1_TO_0_EQ_0b0_OR_NOT_i_ETC___d1153 =
	     IF_IF_imem_c_rg_pc_BITS_1_TO_0_EQ_0b0_OR_NOT_i_ETC___d727 ||
	     IF_IF_imem_c_rg_pc_BITS_1_TO_0_EQ_0b0_OR_NOT_i_ETC___d729 ||
	     near_mem$imem_exc ||
	     IF_IF_imem_c_rg_pc_BITS_1_TO_0_EQ_0b0_OR_NOT_i_ETC___d669 &&
	     IF_IF_imem_c_rg_pc_BITS_1_TO_0_EQ_0b0_OR_NOT_i_ETC___d680 ;
  assign IF_IF_imem_c_rg_pc_BITS_1_TO_0_EQ_0b0_OR_NOT_i_ETC___d1340 =
	     (_theResult____h4859[14:12] == 3'b0) ?
	       _theResult____h4859[11:7] != 5'd0 ||
	       _theResult____h4859[19:15] != 5'd0 ||
	       _theResult____h4859[31:20] == 12'b0 ||
	       _theResult____h4859[31:20] == 12'b000000000001 ||
	       (rg_cur_priv != 2'b11 ||
		_theResult____h4859[31:20] != 12'b001100000010) &&
	       NOT_rg_cur_priv_6_EQ_0b11_96_53_AND_NOT_rg_cur_ETC___d869 :
	       _theResult____h4859[14:12] != 3'b001 &&
	       _theResult____h4859[14:12] != 3'b101 &&
	       _theResult____h4859[14:12] != 3'b010 &&
	       _theResult____h4859[14:12] != 3'b110 &&
	       _theResult____h4859[14:12] != 3'b011 &&
	       _theResult____h4859[14:12] != 3'b111 ;
  assign IF_IF_imem_c_rg_pc_BITS_1_TO_0_EQ_0b0_OR_NOT_i_ETC___d1347 =
	     ((_theResult____h4859[6:0] == 7'b0010011 ||
	       _theResult____h4859[6:0] == 7'b0110011) &&
	      (_theResult____h4859[14:12] == 3'b001 ||
	       _theResult____h4859[14:12] == 3'b101)) ?
	       _theResult____h4859[25] :
	       CASE_theResult__859_BITS_6_TO_0_0b10011_NOT_IF_ETC__q12 ;
  assign IF_IF_imem_c_rg_pc_BITS_1_TO_0_EQ_0b0_OR_NOT_i_ETC___d570 =
	     rs1_val_bypassed__h4867 == rs2_val_bypassed__h4873 ;
  assign IF_IF_imem_c_rg_pc_BITS_1_TO_0_EQ_0b0_OR_NOT_i_ETC___d572 =
	     (rs1_val_bypassed__h4867 ^ 32'h80000000) <
	     (rs2_val_bypassed__h4873 ^ 32'h80000000) ;
  assign IF_IF_imem_c_rg_pc_BITS_1_TO_0_EQ_0b0_OR_NOT_i_ETC___d574 =
	     rs1_val_bypassed__h4867 < rs2_val_bypassed__h4873 ;
  assign IF_IF_imem_c_rg_pc_BITS_1_TO_0_EQ_0b0_OR_NOT_i_ETC___d666 =
	     ((_theResult____h4859[6:0] == 7'b0010011 ||
	       _theResult____h4859[6:0] == 7'b0110011) &&
	      (_theResult____h4859[14:12] == 3'b001 ||
	       _theResult____h4859[14:12] == 3'b101)) ?
	       _theResult____h4859[25] :
	       CASE_theResult__859_BITS_6_TO_0_0b10011_NOT_IF_ETC__q8 ;
  assign IF_IF_imem_c_rg_pc_BITS_1_TO_0_EQ_0b0_OR_NOT_i_ETC___d669 =
	     (_theResult____h4859[6:0] == 7'b1100011) ?
	       _theResult____h4859[14:12] != 3'b0 &&
	       _theResult____h4859[14:12] != 3'b001 &&
	       _theResult____h4859[14:12] != 3'b100 &&
	       _theResult____h4859[14:12] != 3'b101 &&
	       _theResult____h4859[14:12] != 3'b110 &&
	       _theResult____h4859[14:12] != 3'b111 ||
	       IF_IF_imem_c_rg_pc_BITS_1_TO_0_EQ_0b0_OR_NOT_i_ETC___d581 :
	       _theResult____h4859[6:0] == 7'b1101111 ||
	       _theResult____h4859[6:0] == 7'b1100111 ||
	       (_theResult____h4859[6:0] != 7'b0110011 ||
		_theResult____h4859[31:25] != 7'b0000001) &&
	       IF_IF_imem_c_rg_pc_BITS_1_TO_0_EQ_0b0_OR_NOT_i_ETC___d666 ;
  assign IF_IF_imem_c_rg_pc_BITS_1_TO_0_EQ_0b0_OR_NOT_i_ETC___d680 =
	     (_theResult____h4859[6:0] == 7'b1100011) ?
	       _theResult____h4859[14:12] != 3'b0 &&
	       _theResult____h4859[14:12] != 3'b001 &&
	       _theResult____h4859[14:12] != 3'b100 &&
	       _theResult____h4859[14:12] != 3'b101 &&
	       _theResult____h4859[14:12] != 3'b110 &&
	       _theResult____h4859[14:12] != 3'b111 ||
	       IF_IF_imem_c_rg_pc_BITS_1_TO_0_EQ_0b0_OR_NOT_i_ETC___d675 :
	       _theResult____h4859[6:0] != 7'b1101111 &&
	       _theResult____h4859[6:0] != 7'b1100111 ;
  assign IF_IF_imem_c_rg_pc_BITS_1_TO_0_EQ_0b0_OR_NOT_i_ETC___d727 =
	     (_theResult____h4859[6:0] == 7'b1100011) ?
	       (_theResult____h4859[14:12] == 3'b0 ||
		_theResult____h4859[14:12] == 3'b001 ||
		_theResult____h4859[14:12] == 3'b100 ||
		_theResult____h4859[14:12] == 3'b101 ||
		_theResult____h4859[14:12] == 3'b110 ||
		_theResult____h4859[14:12] == 3'b111) &&
	       IF_IF_imem_c_rg_pc_BITS_1_TO_0_EQ_0b0_OR_NOT_i_ETC___d675 :
	       _theResult____h4859[6:0] == 7'b0110011 &&
	       _theResult____h4859[31:25] == 7'b0000001 ||
	       (((_theResult____h4859[6:0] == 7'b0010011 ||
		  _theResult____h4859[6:0] == 7'b0110011) &&
		 (_theResult____h4859[14:12] == 3'b001 ||
		  _theResult____h4859[14:12] == 3'b101)) ?
		  !_theResult____h4859[25] :
		  CASE_theResult__859_BITS_6_TO_0_0b10011_IF_ime_ETC__q10) ;
  assign IF_IF_imem_c_rg_pc_BITS_1_TO_0_EQ_0b0_OR_NOT_i_ETC___d729 =
	     (_theResult____h4859[6:0] == 7'b1100011) ?
	       (_theResult____h4859[14:12] == 3'b0 ||
		_theResult____h4859[14:12] == 3'b001 ||
		_theResult____h4859[14:12] == 3'b100 ||
		_theResult____h4859[14:12] == 3'b101 ||
		_theResult____h4859[14:12] == 3'b110 ||
		_theResult____h4859[14:12] == 3'b111) &&
	       IF_IF_imem_c_rg_pc_BITS_1_TO_0_EQ_0b0_OR_NOT_i_ETC___d581 :
	       _theResult____h4859[6:0] == 7'b1101111 ||
	       _theResult____h4859[6:0] == 7'b1100111 ;
  assign IF_NOT_imem_c_rg_pc_BITS_1_TO_0_EQ_0b0_AND_ime_ETC___d265 =
	     (imem_c_rg_pc[1:0] != 2'b0 &&
	      imem_c_rg_pc_BITS_31_TO_2_0_EQ_near_mem_imem_p_ETC___d260) ?
	       { 16'b0,
		 IF_imem_c_rg_pc_BITS_31_TO_2_0_EQ_near_mem_ime_ETC___d263 } :
	       near_mem$imem_instr ;
  assign IF_csr_regfile_read_csr_rg_trap_instr_371_BITS_ETC___d1429 =
	     csr_regfile$read_csr[31:0] | rs1_val__h21423 ;
  assign IF_csr_regfile_read_misa__3_BIT_2_46_AND_IF_NO_ETC___d480 =
	     (csr_regfile$read_misa[2] && instr__h4857[1:0] == 2'b01 &&
	      instr__h4857[15:10] == 6'b100011 &&
	      instr__h4857[6:5] == 2'b0) ?
	       instr__h12292 :
	       ((csr_regfile$read_misa[2] && instr__h4857[1:0] == 2'b10 &&
		 instr__h4857[15:12] == 4'b1001 &&
		 instr__h4857[11:7] == 5'd0 &&
		 instr__h4857[6:2] == 5'd0) ?
		  instr__h12630 :
		  32'h0) ;
  assign IF_csr_regfile_read_misa__3_BIT_2_46_AND_IF_NO_ETC___d482 =
	     (csr_regfile$read_misa[2] && instr__h4857[1:0] == 2'b01 &&
	      instr__h4857[15:10] == 6'b100011 &&
	      instr__h4857[6:5] == 2'b10) ?
	       instr__h12020 :
	       ((csr_regfile$read_misa[2] && instr__h4857[1:0] == 2'b01 &&
		 instr__h4857[15:10] == 6'b100011 &&
		 instr__h4857[6:5] == 2'b01) ?
		  instr__h12156 :
		  IF_csr_regfile_read_misa__3_BIT_2_46_AND_IF_NO_ETC___d480) ;
  assign IF_csr_regfile_read_misa__3_BIT_2_46_AND_IF_NO_ETC___d484 =
	     (csr_regfile_read_misa__3_BIT_2_46_AND_IF_NOT_i_ETC___d351 &&
	      instr__h4857[6:2] != 5'd0) ?
	       instr__h11789 :
	       ((csr_regfile$read_misa[2] && instr__h4857[1:0] == 2'b01 &&
		 instr__h4857[15:10] == 6'b100011 &&
		 instr__h4857[6:5] == 2'b11) ?
		  instr__h11884 :
		  IF_csr_regfile_read_misa__3_BIT_2_46_AND_IF_NO_ETC___d482) ;
  assign IF_csr_regfile_read_misa__3_BIT_2_46_AND_IF_NO_ETC___d485 =
	     (csr_regfile_read_misa__3_BIT_2_46_AND_IF_NOT_i_ETC___d345 &&
	      instr__h4857[6:2] != 5'd0) ?
	       instr__h11670 :
	       IF_csr_regfile_read_misa__3_BIT_2_46_AND_IF_NO_ETC___d484 ;
  assign IF_csr_regfile_read_misa__3_BIT_2_46_AND_IF_NO_ETC___d487 =
	     (csr_regfile$read_misa[2] && instr__h4857[1:0] == 2'b01 &&
	      instr__h4857[15:13] == 3'b100 &&
	      instr__h4857[11:10] == 2'b01 &&
	      imm6__h9816 != 6'd0 &&
	      !instr__h4857[12]) ?
	       instr__h11375 :
	       ((csr_regfile$read_misa[2] && instr__h4857[1:0] == 2'b01 &&
		 instr__h4857[15:13] == 3'b100 &&
		 instr__h4857[11:10] == 2'b10) ?
		  instr__h11492 :
		  IF_csr_regfile_read_misa__3_BIT_2_46_AND_IF_NO_ETC___d485) ;
  assign IF_csr_regfile_read_misa__3_BIT_2_46_AND_IF_NO_ETC___d488 =
	     (csr_regfile$read_misa[2] && instr__h4857[1:0] == 2'b01 &&
	      instr__h4857[15:13] == 3'b100 &&
	      instr__h4857[11:10] == 2'b0 &&
	      imm6__h9816 != 6'd0 &&
	      !instr__h4857[12]) ?
	       instr__h11182 :
	       IF_csr_regfile_read_misa__3_BIT_2_46_AND_IF_NO_ETC___d487 ;
  assign IF_csr_regfile_read_misa__3_BIT_2_46_AND_IF_NO_ETC___d489 =
	     (csr_regfile$read_misa[2] && instr__h4857[1:0] == 2'b10 &&
	      instr__h4857[15:13] == 3'b0 &&
	      instr__h4857[11:7] != 5'd0 &&
	      imm6__h9816 != 6'd0 &&
	      !instr__h4857[12]) ?
	       instr__h10989 :
	       IF_csr_regfile_read_misa__3_BIT_2_46_AND_IF_NO_ETC___d488 ;
  assign IF_csr_regfile_read_misa__3_BIT_2_46_AND_IF_NO_ETC___d491 =
	     (csr_regfile$read_misa[2] && instr__h4857[1:0] == 2'b01 &&
	      instr__h4857[15:13] == 3'b011 &&
	      instr__h4857[11:7] == 5'd2 &&
	      nzimm10__h10440 != 10'd0) ?
	       instr__h10644 :
	       ((csr_regfile$read_misa[2] && instr__h4857[1:0] == 2'b0 &&
		 instr__h4857[15:13] == 3'b0 &&
		 nzimm10__h10655 != 10'd0) ?
		  instr__h10816 :
		  IF_csr_regfile_read_misa__3_BIT_2_46_AND_IF_NO_ETC___d489) ;
  assign IF_csr_regfile_read_misa__3_BIT_2_46_AND_IF_NO_ETC___d492 =
	     (csr_regfile$read_misa[2] && instr__h4857[1:0] == 2'b01 &&
	      instr__h4857[15:13] == 3'b0 &&
	      instr__h4857[11:7] != 5'd0 &&
	      imm6__h9816 != 6'd0 ||
	      csr_regfile$read_misa[2] && instr__h4857[1:0] == 2'b01 &&
	      instr__h4857[15:13] == 3'b0 &&
	      instr__h4857[11:7] == 5'd0 &&
	      imm6__h9816 == 6'd0) ?
	       instr__h10207 :
	       IF_csr_regfile_read_misa__3_BIT_2_46_AND_IF_NO_ETC___d491 ;
  assign IF_csr_regfile_read_misa__3_BIT_2_46_AND_IF_NO_ETC___d493 =
	     (csr_regfile$read_misa[2] && instr__h4857[1:0] == 2'b01 &&
	      instr__h4857[15:13] == 3'b011 &&
	      instr__h4857[11:7] != 5'd0 &&
	      instr__h4857[11:7] != 5'd2 &&
	      imm6__h9816 != 6'd0) ?
	       instr__h10078 :
	       IF_csr_regfile_read_misa__3_BIT_2_46_AND_IF_NO_ETC___d492 ;
  assign IF_csr_regfile_read_misa__3_BIT_2_46_AND_IF_NO_ETC___d495 =
	     (csr_regfile$read_misa[2] && instr__h4857[1:0] == 2'b01 &&
	      instr__h4857[15:13] == 3'b111) ?
	       instr__h9556 :
	       ((csr_regfile$read_misa[2] && instr__h4857[1:0] == 2'b01 &&
		 instr__h4857[15:13] == 3'b010 &&
		 instr__h4857[11:7] != 5'd0) ?
		  instr__h9894 :
		  IF_csr_regfile_read_misa__3_BIT_2_46_AND_IF_NO_ETC___d493) ;
  assign IF_csr_regfile_read_misa__3_BIT_2_46_AND_IF_NO_ETC___d496 =
	     (csr_regfile$read_misa[2] && instr__h4857[1:0] == 2'b01 &&
	      instr__h4857[15:13] == 3'b110) ?
	       instr__h9239 :
	       IF_csr_regfile_read_misa__3_BIT_2_46_AND_IF_NO_ETC___d495 ;
  assign IF_csr_regfile_read_misa__3_BIT_2_46_AND_IF_NO_ETC___d497 =
	     (csr_regfile_read_misa__3_BIT_2_46_AND_IF_NOT_i_ETC___d351 &&
	      instr__h4857[6:2] == 5'd0) ?
	       instr__h9174 :
	       IF_csr_regfile_read_misa__3_BIT_2_46_AND_IF_NO_ETC___d496 ;
  assign IF_csr_regfile_read_misa__3_BIT_2_46_AND_IF_NO_ETC___d498 =
	     (csr_regfile_read_misa__3_BIT_2_46_AND_IF_NOT_i_ETC___d345 &&
	      instr__h4857[6:2] == 5'd0) ?
	       instr__h9058 :
	       IF_csr_regfile_read_misa__3_BIT_2_46_AND_IF_NO_ETC___d497 ;
  assign IF_csr_regfile_read_misa__3_BIT_2_46_AND_IF_NO_ETC___d499 =
	     (csr_regfile$read_misa[2] && instr__h4857[1:0] == 2'b01 &&
	      instr__h4857[15:13] == 3'b001) ?
	       instr__h8668 :
	       IF_csr_regfile_read_misa__3_BIT_2_46_AND_IF_NO_ETC___d498 ;
  assign IF_csr_regfile_read_misa__3_BIT_2_46_AND_IF_NO_ETC___d500 =
	     (csr_regfile$read_misa[2] && instr__h4857[1:0] == 2'b01 &&
	      instr__h4857[15:13] == 3'b101) ?
	       instr__h8325 :
	       IF_csr_regfile_read_misa__3_BIT_2_46_AND_IF_NO_ETC___d499 ;
  assign IF_csr_regfile_read_misa__3_BIT_2_46_AND_IF_NO_ETC___d501 =
	     (csr_regfile$read_misa[2] && instr__h4857[1:0] == 2'b0 &&
	      instr__h4857[15:13] == 3'b110) ?
	       instr__h8096 :
	       IF_csr_regfile_read_misa__3_BIT_2_46_AND_IF_NO_ETC___d500 ;
  assign IF_csr_regfile_read_misa__3_BIT_2_46_AND_IF_NO_ETC___d502 =
	     (csr_regfile$read_misa[2] && instr__h4857[1:0] == 2'b0 &&
	      instr__h4857[15:13] == 3'b010) ?
	       instr__h7901 :
	       IF_csr_regfile_read_misa__3_BIT_2_46_AND_IF_NO_ETC___d501 ;
  assign IF_csr_regfile_read_misa__3_BIT_2_46_AND_IF_NO_ETC___d503 =
	     (csr_regfile$read_misa[2] && instr__h4857[1:0] == 2'b10 &&
	      instr__h4857[15:13] == 3'b110) ?
	       instr__h7709 :
	       IF_csr_regfile_read_misa__3_BIT_2_46_AND_IF_NO_ETC___d502 ;
  assign IF_imem_c_rg_pc_BITS_1_TO_0_EQ_0b0_AND_imem_c__ETC___d266 =
	     (imem_c_rg_pc[1:0] == 2'b0 &&
	      imem_c_rg_pc_BITS_31_TO_2_0_EQ_near_mem_imem_p_ETC___d13 &&
	      near_mem$imem_instr[1:0] != 2'b11) ?
	       instr_out___1__h7431 :
	       IF_NOT_imem_c_rg_pc_BITS_1_TO_0_EQ_0b0_AND_ime_ETC___d265 ;
  assign IF_imem_c_rg_pc_BITS_1_TO_0_EQ_0b0_OR_NOT_imem_ETC___d1227 =
	     { _theResult____h4859,
	       CASE_theResult__859_BITS_6_TO_0_0b1100011_0_0b_ETC__q14,
	       data_to_stage2_rd__h12918,
	       data_to_stage2_addr__h12919,
	       x_out_data_to_stage2_val1__h12928,
	       data_to_stage2_val2__h12921 } ;
  assign IF_imem_c_rg_pc_BITS_1_TO_0_EQ_0b0_OR_NOT_imem_ETC___d700 =
	     _theResult____h4859[14:12] == 3'b0 &&
	     (_theResult____h4859[6:0] != 7'b0110011 ||
	      !_theResult____h4859[30]) ||
	     _theResult____h4859[14:12] == 3'b0 &&
	     _theResult____h4859[6:0] == 7'b0110011 &&
	     _theResult____h4859[30] ||
	     _theResult____h4859[14:12] == 3'b010 ||
	     _theResult____h4859[14:12] == 3'b011 ||
	     _theResult____h4859[14:12] == 3'b100 ||
	     _theResult____h4859[14:12] == 3'b110 ||
	     _theResult____h4859[14:12] == 3'b111 ;
  assign IF_imem_c_rg_pc_BITS_1_TO_0_EQ_0b0_OR_NOT_imem_ETC___d801 =
	     _theResult____h4859[14:12] == 3'b0 &&
	     _theResult____h4859[11:7] == 5'd0 &&
	     _theResult____h4859[19:15] == 5'd0 &&
	     rg_cur_priv == 2'b11 &&
	     _theResult____h4859[31:20] == 12'b001100000010 ;
  assign IF_imem_c_rg_pc_BITS_1_TO_0_EQ_0b0_OR_NOT_imem_ETC___d821 =
	     _theResult____h4859[14:12] == 3'b0 &&
	     _theResult____h4859[11:7] == 5'd0 &&
	     _theResult____h4859[19:15] == 5'd0 &&
	     rg_cur_priv_6_EQ_0b11_96_OR_rg_cur_priv_6_EQ_0_ETC___d819 ;
  assign IF_imem_c_rg_pc_BITS_1_TO_0_EQ_0b0_OR_NOT_imem_ETC___d943 =
	     imem_c_rg_pc_BITS_1_TO_0_EQ_0b0_OR_NOT_imem_c__ETC___d235 ?
	       next_pc___1__h14698 :
	       next_pc__h14696 ;
  assign IF_imem_c_rg_pc_BITS_31_TO_2_0_EQ_near_mem_ime_ETC___d263 =
	     imem_c_rg_pc_BITS_31_TO_2_0_EQ_near_mem_imem_p_ETC___d13 ?
	       near_mem$imem_instr[31:16] :
	       (imem_c_rg_cache_b16[16] ? imem_c_rg_cache_b16[15:0] : 16'd0) ;
  assign IF_near_mem_imem_exc__29_THEN_near_mem_imem_ex_ETC___d1355 =
	     near_mem$imem_exc ?
	       { near_mem$imem_exc_code, imem_c_rg_tval } :
	       { alu_outputs_exc_code__h13589, trap_info_tval__h14518 } ;
  assign IF_stage2_rg_full_0_THEN_IF_stage2_rg_stage2_1_ETC___d507 =
	     x_out_bypass_rd__h7054 == _theResult____h4859[19:15] ;
  assign IF_stage2_rg_full_0_THEN_IF_stage2_rg_stage2_1_ETC___d509 =
	     x_out_bypass_rd__h7054 == _theResult____h4859[24:20] ;
  assign NOT_IF_NOT_stage1_rg_full_06_07_OR_NOT_near_me_ETC___d1302 =
	     x_out_next_pc__h12736[1:0] != 2'b0 && near_mem$imem_valid &&
	     addr_of_b32__h19071 == near_mem$imem_pc &&
	     near_mem$imem_instr[17:16] == 2'b11 ;
  assign NOT_IF_csr_regfile_read_csr_minstret__8_ULT_cf_ETC___d44 =
	     cur_verbosity__h3469 > 4'd1 ;
  assign NOT_IF_imem_c_rg_pc_BITS_1_TO_0_EQ_0b0_OR_NOT__ETC___d611 =
	     (_theResult____h4859[14:12] != 3'b0 ||
	      _theResult____h4859[6:0] == 7'b0110011 &&
	      _theResult____h4859[30]) &&
	     (_theResult____h4859[14:12] != 3'b0 ||
	      _theResult____h4859[6:0] != 7'b0110011 ||
	      !_theResult____h4859[30]) &&
	     _theResult____h4859[14:12] != 3'b010 &&
	     _theResult____h4859[14:12] != 3'b011 &&
	     _theResult____h4859[14:12] != 3'b100 &&
	     _theResult____h4859[14:12] != 3'b110 &&
	     _theResult____h4859[14:12] != 3'b111 ;
  assign NOT_IF_imem_c_rg_pc_BITS_1_TO_0_EQ_0b0_OR_NOT__ETC___d661 =
	     _theResult____h4859[6:0] != 7'b0101111 ||
	     _theResult____h4859[31:27] != 5'b00010 &&
	     _theResult____h4859[31:27] != 5'b00011 &&
	     _theResult____h4859[31:27] != 5'b0 &&
	     _theResult____h4859[31:27] != 5'b00001 &&
	     _theResult____h4859[31:27] != 5'b01100 &&
	     _theResult____h4859[31:27] != 5'b01000 &&
	     _theResult____h4859[31:27] != 5'b00100 &&
	     _theResult____h4859[31:27] != 5'b10000 &&
	     _theResult____h4859[31:27] != 5'b11000 &&
	     _theResult____h4859[31:27] != 5'b10100 &&
	     _theResult____h4859[31:27] != 5'b11100 ||
	     _theResult____h4859[14:12] != 3'b010 ;
  assign NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d1189 =
	     !csr_regfile$interrupt_pending[4] && !csr_regfile$nmi_pending ||
	     (!stage1_rg_full ||
	      NOT_near_mem_imem_valid_08_OR_imem_c_rg_pc_BIT_ETC___d1186) &&
	     (!stage1_rg_full ||
	      NOT_near_mem_imem_valid_08_OR_imem_c_rg_pc_BIT_ETC___d1178) ;
  assign NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d1213 =
	     (!csr_regfile$interrupt_pending[4] && !csr_regfile$nmi_pending ||
	      stage2_rg_full_0_AND_NOT_stage2_rg_stage2_1_BI_ETC___d511 ||
	      near_mem$imem_exc ||
	      IF_IF_imem_c_rg_pc_BITS_1_TO_0_EQ_0b0_OR_NOT_i_ETC___d669 &&
	      IF_IF_imem_c_rg_pc_BITS_1_TO_0_EQ_0b0_OR_NOT_i_ETC___d680) &&
	     (stage2_rg_stage2[103:101] == 3'd0 ||
	      IF_stage2_rg_stage2_1_BITS_103_TO_101_2_EQ_1_4_ETC___d1196 ||
	      !stage2_rg_full) ;
  assign NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d1238 =
	     NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d1213 &&
	     stage1_rg_full &&
	     near_mem_imem_valid_AND_NOT_imem_c_rg_pc_BITS__ETC___d1214 &&
	     _theResult____h4859[6:0] != 7'b1100011 &&
	     _theResult____h4859[6:0] != 7'b1101111 &&
	     _theResult____h4859[6:0] != 7'b1100111 &&
	     _theResult____h4859[6:0] != 7'b0010011 &&
	     _theResult____h4859[6:0] != 7'b0110011 &&
	     _theResult____h4859[6:0] != 7'b0110111 &&
	     _theResult____h4859[6:0] != 7'b0010111 ;
  assign NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d1256 =
	     NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d1213 &&
	     stage1_rg_full &&
	     near_mem_imem_valid_AND_NOT_imem_c_rg_pc_BITS__ETC___d1214 &&
	     NOT_IF_csr_regfile_read_csr_minstret__8_ULT_cf_ETC___d44 ;
  assign NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d1258 =
	     NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d1213 &&
	     stage1_rg_full &&
	     near_mem_imem_valid_AND_NOT_imem_c_rg_pc_BITS__ETC___d1214 &&
	     NOT_IF_csr_regfile_read_csr_minstret__8_ULT_cf_ETC___d44 &&
	     NOT_stage2_rg_full_0_41_OR_stage2_rg_stage2_1__ETC___d890 ;
  assign NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d1260 =
	     NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d1213 &&
	     stage1_rg_full &&
	     near_mem_imem_valid_AND_NOT_imem_c_rg_pc_BITS__ETC___d1214 &&
	     NOT_IF_csr_regfile_read_csr_minstret__8_ULT_cf_ETC___d44 &&
	     NOT_stage2_rg_full_0_41_OR_stage2_rg_stage2_1__ETC___d735 &&
	     NOT_stage2_rg_full_0_41_OR_stage2_rg_stage2_1__ETC___d736 &&
	     _theResult____h4859[6:0] == 7'b0000011 ;
  assign NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d1262 =
	     NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d1213 &&
	     stage1_rg_full &&
	     near_mem_imem_valid_AND_NOT_imem_c_rg_pc_BITS__ETC___d1214 &&
	     NOT_IF_csr_regfile_read_csr_minstret__8_ULT_cf_ETC___d44 &&
	     NOT_stage2_rg_full_0_41_OR_stage2_rg_stage2_1__ETC___d735 &&
	     NOT_stage2_rg_full_0_41_OR_stage2_rg_stage2_1__ETC___d736 &&
	     _theResult____h4859[6:0] == 7'b0100011 ;
  assign NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d1264 =
	     NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d1213 &&
	     stage1_rg_full &&
	     near_mem_imem_valid_AND_NOT_imem_c_rg_pc_BITS__ETC___d1214 &&
	     NOT_IF_csr_regfile_read_csr_minstret__8_ULT_cf_ETC___d44 &&
	     NOT_stage2_rg_full_0_41_OR_stage2_rg_stage2_1__ETC___d735 &&
	     NOT_stage2_rg_full_0_41_OR_stage2_rg_stage2_1__ETC___d736 &&
	     _theResult____h4859[6:0] == 7'b0110011 &&
	     _theResult____h4859[31:25] == 7'b0000001 ;
  assign NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d1266 =
	     NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d1213 &&
	     stage1_rg_full &&
	     near_mem_imem_valid_AND_NOT_imem_c_rg_pc_BITS__ETC___d1214 &&
	     NOT_IF_csr_regfile_read_csr_minstret__8_ULT_cf_ETC___d44 &&
	     stage2_rg_full_0_AND_NOT_stage2_rg_stage2_1_BI_ETC___d914 &&
	     stage2_rg_full_0_AND_NOT_stage2_rg_stage2_1_BI_ETC___d921 ;
  assign NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d1272 =
	     !csr_regfile$interrupt_pending[4] && !csr_regfile$nmi_pending ||
	     (!stage1_rg_full ||
	      NOT_near_mem_imem_valid_08_OR_imem_c_rg_pc_BIT_ETC___d1267) &&
	     (!stage1_rg_full ||
	      NOT_near_mem_imem_valid_08_OR_imem_c_rg_pc_BIT_ETC___d1269) ;
  assign NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d1275 =
	     NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d1272 &&
	     (NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d1213 &&
	      near_mem_imem_valid_AND_NOT_imem_c_rg_pc_BITS__ETC___d1214 ||
	      !stage1_rg_full) ;
  assign NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d1287 =
	     !csr_regfile$interrupt_pending[4] && !csr_regfile$nmi_pending ||
	     (!stage1_rg_full ||
	      imem_c_rg_pc_BITS_1_TO_0_EQ_0b0_OR_NOT_imem_c__ETC___d1282) &&
	     (!stage1_rg_full ||
	      imem_c_rg_pc_BITS_1_TO_0_EQ_0b0_OR_NOT_imem_c__ETC___d1284) ;
  assign NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d1292 =
	     NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d1287 &&
	     (NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d1213 &&
	      NOT_imem_c_rg_pc_BITS_1_TO_0_EQ_0b0_AND_imem_c_ETC___d1289 ||
	      !stage1_rg_full) ;
  assign NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d1318 =
	     NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d1272 &&
	     (NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d1213 &&
	      near_mem_imem_valid_AND_NOT_imem_c_rg_pc_BITS__ETC___d1214 ||
	      !stage1_rg_full) ;
  assign NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d1327 =
	     !csr_regfile$interrupt_pending[4] && !csr_regfile$nmi_pending ||
	     !near_mem$imem_exc &&
	     (IF_IF_imem_c_rg_pc_BITS_1_TO_0_EQ_0b0_OR_NOT_i_ETC___d727 ||
	      IF_IF_imem_c_rg_pc_BITS_1_TO_0_EQ_0b0_OR_NOT_i_ETC___d729) ;
  assign NOT_imem_c_rg_pc_BITS_1_TO_0_EQ_0b0_AND_imem_c_ETC___d1289 =
	     NOT_imem_c_rg_pc_BITS_1_TO_0_EQ_0b0_AND_imem_c_ETC___d521 &&
	     NOT_stage2_rg_full_0_41_OR_stage2_rg_stage2_1__ETC___d527 &&
	     !near_mem$imem_exc &&
	     (IF_IF_imem_c_rg_pc_BITS_1_TO_0_EQ_0b0_OR_NOT_i_ETC___d727 ||
	      IF_IF_imem_c_rg_pc_BITS_1_TO_0_EQ_0b0_OR_NOT_i_ETC___d729) ;
  assign NOT_imem_c_rg_pc_BITS_1_TO_0_EQ_0b0_AND_imem_c_ETC___d250 =
	     imem_c_rg_pc[1:0] != 2'b0 &&
	     imem_c_rg_pc_BITS_31_TO_2_0_EQ_imem_c_rg_cache_ETC___d211 &&
	     near_mem_imem_pc__1_EQ_imem_c_rg_pc_PLUS_2_14___d215 &&
	     imem_c_rg_cache_b16[16] &&
	     imem_c_rg_cache_b16_BITS_15_TO_0__q1[1:0] == 2'b11 ;
  assign NOT_imem_c_rg_pc_BITS_1_TO_0_EQ_0b0_AND_imem_c_ETC___d519 =
	     NOT_imem_c_rg_pc_BITS_1_TO_0_EQ_0b0_AND_imem_c_ETC___d250 ||
	     imem_c_rg_pc[1:0] == 2'b0 &&
	     imem_c_rg_pc_BITS_31_TO_2_0_EQ_near_mem_imem_p_ETC___d13 &&
	     near_mem$imem_instr[1:0] == 2'b11 ;
  assign NOT_imem_c_rg_pc_BITS_1_TO_0_EQ_0b0_AND_imem_c_ETC___d521 =
	     NOT_imem_c_rg_pc_BITS_1_TO_0_EQ_0b0_AND_imem_c_ETC___d519 ||
	     imem_c_rg_pc[1:0] != 2'b0 &&
	     imem_c_rg_pc_BITS_31_TO_2_0_EQ_near_mem_imem_p_ETC___d260 ||
	     imem_c_rg_pc[1:0] == 2'b0 &&
	     imem_c_rg_pc_BITS_31_TO_2_0_EQ_near_mem_imem_p_ETC___d13 &&
	     near_mem$imem_instr[1:0] != 2'b11 ;
  assign NOT_imem_c_rg_pc_BITS_31_TO_2_0_EQ_imem_c_rg_c_ETC___d1167 =
	     (!imem_c_rg_pc_BITS_31_TO_2_0_EQ_imem_c_rg_cache_ETC___d211 ||
	      !near_mem_imem_pc__1_EQ_imem_c_rg_pc_PLUS_2_14___d215 ||
	      !imem_c_rg_cache_b16[16] ||
	      imem_c_rg_cache_b16_BITS_15_TO_0__q1[1:0] != 2'b11) &&
	     (!imem_c_rg_pc_BITS_31_TO_2_0_EQ_imem_c_rg_cache_ETC___d211 ||
	      !imem_c_rg_cache_b16[16] ||
	      imem_c_rg_cache_b16_BITS_15_TO_0__q1[1:0] == 2'b11) ||
	     stage2_rg_full_0_AND_NOT_stage2_rg_stage2_1_BI_ETC___d511 ||
	     near_mem$imem_exc ||
	     IF_IF_imem_c_rg_pc_BITS_1_TO_0_EQ_0b0_OR_NOT_i_ETC___d669 &&
	     IF_IF_imem_c_rg_pc_BITS_1_TO_0_EQ_0b0_OR_NOT_i_ETC___d680 ;
  assign NOT_near_mem_imem_exc__29_85_AND_IF_imem_c_rg__ETC___d755 =
	     !near_mem$imem_exc && _theResult____h4859[6:0] == 7'b1110011 &&
	     (_theResult____h4859[14:12] == 3'b001 ||
	      _theResult____h4859[14:12] == 3'b101) ;
  assign NOT_near_mem_imem_exc__29_85_AND_IF_imem_c_rg__ETC___d769 =
	     !near_mem$imem_exc && _theResult____h4859[6:0] == 7'b1110011 &&
	     (_theResult____h4859[14:12] == 3'b010 ||
	      _theResult____h4859[14:12] == 3'b110 ||
	      _theResult____h4859[14:12] == 3'b011 ||
	      _theResult____h4859[14:12] == 3'b111) ;
  assign NOT_near_mem_imem_valid_08_OR_imem_c_rg_pc_BIT_ETC___d1178 =
	     !near_mem$imem_valid ||
	     imem_c_rg_pc_BITS_1_TO_0_EQ_0b0_OR_NOT_imem_c__ETC___d243 ||
	     !near_mem$imem_exc &&
	     (IF_IF_imem_c_rg_pc_BITS_1_TO_0_EQ_0b0_OR_NOT_i_ETC___d727 ||
	      IF_IF_imem_c_rg_pc_BITS_1_TO_0_EQ_0b0_OR_NOT_i_ETC___d729) ;
  assign NOT_near_mem_imem_valid_08_OR_imem_c_rg_pc_BIT_ETC___d1186 =
	     !near_mem$imem_valid ||
	     imem_c_rg_pc_BITS_1_TO_0_EQ_0b0_OR_NOT_imem_c__ETC___d243 ||
	     near_mem$imem_exc ||
	     IF_IF_imem_c_rg_pc_BITS_1_TO_0_EQ_0b0_OR_NOT_i_ETC___d669 &&
	     IF_IF_imem_c_rg_pc_BITS_1_TO_0_EQ_0b0_OR_NOT_i_ETC___d680 ;
  assign NOT_near_mem_imem_valid_08_OR_imem_c_rg_pc_BIT_ETC___d1267 =
	     !near_mem$imem_valid ||
	     imem_c_rg_pc_BITS_1_TO_0_EQ_0b0_OR_NOT_imem_c__ETC___d243 ||
	     stage2_rg_full_0_AND_NOT_stage2_rg_stage2_1_BI_ETC___d511 ||
	     near_mem$imem_exc ||
	     IF_IF_imem_c_rg_pc_BITS_1_TO_0_EQ_0b0_OR_NOT_i_ETC___d669 &&
	     IF_IF_imem_c_rg_pc_BITS_1_TO_0_EQ_0b0_OR_NOT_i_ETC___d680 ;
  assign NOT_near_mem_imem_valid_08_OR_imem_c_rg_pc_BIT_ETC___d1269 =
	     !near_mem$imem_valid ||
	     imem_c_rg_pc_BITS_1_TO_0_EQ_0b0_OR_NOT_imem_c__ETC___d243 ||
	     stage2_rg_full_0_AND_NOT_stage2_rg_stage2_1_BI_ETC___d511 ||
	     !near_mem$imem_exc &&
	     (IF_IF_imem_c_rg_pc_BITS_1_TO_0_EQ_0b0_OR_NOT_i_ETC___d727 ||
	      IF_IF_imem_c_rg_pc_BITS_1_TO_0_EQ_0b0_OR_NOT_i_ETC___d729) ;
  assign NOT_rg_cur_priv_6_EQ_0b11_96_53_AND_NOT_rg_cur_ETC___d869 =
	     rg_cur_priv != 2'b11 &&
	     (rg_cur_priv != 2'b01 || csr_regfile$read_mstatus[21]) &&
	     (rg_cur_priv != 2'b0 || !csr_regfile$read_misa[13]) ||
	     _theResult____h4859[31:20] != 12'b000100000101 ;
  assign NOT_rg_next_pc_453_BITS_1_TO_0_454_EQ_0b0_455__ETC___d1462 =
	     rg_next_pc[1:0] != 2'b0 && near_mem$imem_valid &&
	     addr_of_b32__h27402 == near_mem$imem_pc &&
	     near_mem$imem_instr[17:16] == 2'b11 ;
  assign NOT_soc_map_m_pc_reset_value__129_BITS_1_TO_0__ETC___d1141 =
	     soc_map$m_pc_reset_value[1:0] != 2'b0 && near_mem$imem_valid &&
	     addr_of_b32__h16844 == near_mem$imem_pc &&
	     near_mem$imem_instr[17:16] == 2'b11 ;
  assign NOT_stage1_rg_full_06_07_OR_near_mem_imem_vali_ETC___d1358 =
	     !stage1_rg_full ||
	     near_mem$imem_valid &&
	     NOT_imem_c_rg_pc_BITS_1_TO_0_EQ_0b0_AND_imem_c_ETC___d521 &&
	     NOT_stage2_rg_full_0_41_OR_stage2_rg_stage2_1__ETC___d527 ;
  assign NOT_stage2_rg_full_0_41_OR_stage2_rg_stage2_1__ETC___d527 =
	     !stage2_rg_full || stage2_rg_stage2[103:101] == 3'd0 ||
	     IF_stage2_rg_stage2_1_BITS_103_TO_101_2_EQ_1_4_ETC___d200 ||
	     !IF_stage2_rg_full_0_THEN_IF_stage2_rg_stage2_1_ETC___d507 &&
	     !IF_stage2_rg_full_0_THEN_IF_stage2_rg_stage2_1_ETC___d509 ;
  assign NOT_stage2_rg_full_0_41_OR_stage2_rg_stage2_1__ETC___d735 =
	     !stage2_rg_full || stage2_rg_stage2[103:101] == 3'd0 ||
	     IF_stage2_rg_stage2_1_BITS_103_TO_101_2_EQ_1_4_ETC___d200 ||
	     !IF_stage2_rg_full_0_THEN_IF_stage2_rg_stage2_1_ETC___d507 ;
  assign NOT_stage2_rg_full_0_41_OR_stage2_rg_stage2_1__ETC___d736 =
	     !stage2_rg_full || stage2_rg_stage2[103:101] == 3'd0 ||
	     IF_stage2_rg_stage2_1_BITS_103_TO_101_2_EQ_1_4_ETC___d200 ||
	     !IF_stage2_rg_full_0_THEN_IF_stage2_rg_stage2_1_ETC___d509 ;
  assign NOT_stage2_rg_full_0_41_OR_stage2_rg_stage2_1__ETC___d804 =
	     NOT_stage2_rg_full_0_41_OR_stage2_rg_stage2_1__ETC___d735 &&
	     NOT_stage2_rg_full_0_41_OR_stage2_rg_stage2_1__ETC___d736 &&
	     !near_mem$imem_exc &&
	     _theResult____h4859[6:0] == 7'b1110011 &&
	     IF_imem_c_rg_pc_BITS_1_TO_0_EQ_0b0_OR_NOT_imem_ETC___d801 ;
  assign NOT_stage2_rg_full_0_41_OR_stage2_rg_stage2_1__ETC___d824 =
	     NOT_stage2_rg_full_0_41_OR_stage2_rg_stage2_1__ETC___d735 &&
	     NOT_stage2_rg_full_0_41_OR_stage2_rg_stage2_1__ETC___d736 &&
	     !near_mem$imem_exc &&
	     _theResult____h4859[6:0] == 7'b1110011 &&
	     IF_imem_c_rg_pc_BITS_1_TO_0_EQ_0b0_OR_NOT_imem_ETC___d821 ;
  assign NOT_stage2_rg_full_0_41_OR_stage2_rg_stage2_1__ETC___d890 =
	     NOT_stage2_rg_full_0_41_OR_stage2_rg_stage2_1__ETC___d735 &&
	     NOT_stage2_rg_full_0_41_OR_stage2_rg_stage2_1__ETC___d736 &&
	     (_theResult____h4859[6:0] == 7'b1100011 ||
	      _theResult____h4859[6:0] == 7'b1101111 ||
	      _theResult____h4859[6:0] == 7'b1100111 ||
	      (_theResult____h4859[6:0] != 7'b0110011 ||
	       _theResult____h4859[31:25] != 7'b0000001) &&
	      (_theResult____h4859[6:0] == 7'b0010011 ||
	       _theResult____h4859[6:0] == 7'b0110011 ||
	       _theResult____h4859[6:0] == 7'b0110111 ||
	       _theResult____h4859[6:0] == 7'b0010111)) ;
  assign NOT_stage2_rg_stage2_1_BITS_103_TO_101_2_EQ_0__ETC___d126 =
	     (stage2_rg_stage2[103:101] == 3'd1 ||
	      stage2_rg_stage2[103:101] == 3'd4 ||
	      stage2_rg_stage2[103:101] == 3'd2) &&
	     near_mem$dmem_valid &&
	     near_mem$dmem_exc ;
  assign NOT_stage2_rg_stage2_1_BITS_103_TO_101_2_EQ_1__ETC___d146 =
	     (stage2_rg_stage2[103:101] != 3'd1 &&
	      stage2_rg_stage2[103:101] != 3'd4 &&
	      stage2_rg_stage2[103:101] != 3'd2 ||
	      !near_mem$dmem_valid ||
	      !near_mem$dmem_exc) &&
	     stage2_rg_stage2[103:101] != 3'd0 &&
	     IF_stage2_rg_stage2_1_BITS_103_TO_101_2_EQ_1_4_ETC___d144 ;
  assign SEXT_IF_NOT_imem_c_rg_pc_BITS_1_TO_0_EQ_0b0_AN_ETC___d331 =
	     { {9{offset__h8272[11]}}, offset__h8272 } ;
  assign SEXT_IF_NOT_imem_c_rg_pc_BITS_1_TO_0_EQ_0b0_AN_ETC___d360 =
	     { {4{offset__h9183[8]}}, offset__h9183 } ;
  assign SEXT_IF_imem_c_rg_pc_BITS_1_TO_0_EQ_0b0_OR_NOT_ETC___d952 =
	     { {20{theResult__859_BITS_31_TO_20__q11[11]}},
	       theResult__859_BITS_31_TO_20__q11 } ;
  assign _theResult_____1_fst__h14021 =
	     (_theResult____h4859[14:12] == 3'b0 &&
	      _theResult____h4859[6:0] == 7'b0110011 &&
	      _theResult____h4859[30]) ?
	       rd_val___1__h14017 :
	       _theResult_____1_fst__h14028 ;
  assign _theResult_____1_fst__h14056 =
	     rs1_val_bypassed__h4867 & _theResult___snd__h15372 ;
  assign _theResult____h20140 =
	     (delta_CPI_instrs__h20139 == 64'd0) ?
	       delta_CPI_instrs___1__h20184 :
	       delta_CPI_instrs__h20139 ;
  assign _theResult____h4859 = x_out_data_to_stage2_instr__h12924 ;
  assign _theResult___snd__h15372 =
	     (_theResult____h4859[6:0] == 7'b0010011) ?
	       SEXT_IF_imem_c_rg_pc_BITS_1_TO_0_EQ_0b0_OR_NOT_ETC___d952 :
	       rs2_val_bypassed__h4873 ;
  assign addr_of_b32___1__h16950 = addr_of_b32__h16844 + 32'd4 ;
  assign addr_of_b32___1__h19177 = addr_of_b32__h19071 + 32'd4 ;
  assign addr_of_b32___1__h27508 = addr_of_b32__h27402 + 32'd4 ;
  assign addr_of_b32__h16844 = { soc_map$m_pc_reset_value[31:2], 2'd0 } ;
  assign addr_of_b32__h19071 = { x_out_next_pc__h12736[31:2], 2'd0 } ;
  assign addr_of_b32__h27402 = { rg_next_pc[31:2], 2'd0 } ;
  assign alu_outputs___1_addr__h13103 =
	     IF_IF_imem_c_rg_pc_BITS_1_TO_0_EQ_0b0_OR_NOT_i_ETC___d581 ?
	       branch_target__h13080 :
	       IF_imem_c_rg_pc_BITS_1_TO_0_EQ_0b0_OR_NOT_imem_ETC___d943 ;
  assign alu_outputs___1_addr__h13124 =
	     imem_c_rg_pc +
	     { {11{theResult__859_BIT_31_CONCAT_theResult__859_BI_ETC__q3[20]}},
	       theResult__859_BIT_31_CONCAT_theResult__859_BI_ETC__q3 } ;
  assign alu_outputs___1_addr__h13150 = { eaddr__h13323[31:1], 1'd0 } ;
  assign alu_outputs___1_addr__h13353 =
	     rs1_val_bypassed__h4867 +
	     { {20{theResult__859_BITS_31_TO_25_CONCAT_theResult__ETC__q6[11]}},
	       theResult__859_BITS_31_TO_25_CONCAT_theResult__ETC__q6 } ;
  assign alu_outputs___1_exc_code__h13548 =
	     (_theResult____h4859[14:12] == 3'b0) ?
	       ((_theResult____h4859[11:7] == 5'd0 &&
		 _theResult____h4859[19:15] == 5'd0) ?
		  CASE_theResult__859_BITS_31_TO_20_0b0_CASE_rg__ETC__q5 :
		  4'd2) :
	       4'd2 ;
  assign alu_outputs___1_val1__h13250 =
	     (_theResult____h4859[14:12] == 3'b001) ?
	       rd_val__h15268 :
	       (_theResult____h4859[30] ? rd_val__h15342 : rd_val__h15320) ;
  assign alu_outputs___1_val1__h13286 =
	     (_theResult____h4859[14:12] == 3'b0 &&
	      (_theResult____h4859[6:0] != 7'b0110011 ||
	       !_theResult____h4859[30])) ?
	       rd_val___1__h14009 :
	       _theResult_____1_fst__h14021 ;
  assign alu_outputs___1_val1__h13552 =
	     _theResult____h4859[14] ?
	       { 27'd0, _theResult____h4859[19:15] } :
	       rs1_val_bypassed__h4867 ;
  assign alu_outputs___1_val1__h13572 =
	     { 25'd0, _theResult____h4859[31:25] } ;
  assign branch_target__h13080 =
	     imem_c_rg_pc +
	     { {19{theResult__859_BIT_31_CONCAT_theResult__859_BI_ETC__q2[12]}},
	       theResult__859_BIT_31_CONCAT_theResult__859_BI_ETC__q2 } ;
  assign cpi__h20142 = x__h20141 / 64'd10 ;
  assign cpifrac__h20143 = x__h20141 % 64'd10 ;
  assign csr_regfile_RDY_server_reset_response_get__109_ETC___d1124 =
	     csr_regfile$RDY_server_reset_response_get &&
	     stage1_f_reset_rsps$EMPTY_N &&
	     stage2_f_reset_rsps$EMPTY_N &&
	     stage3_f_reset_rsps$EMPTY_N &&
	     f_reset_rsps$FULL_N &&
	     (!rg_run_on_reset ||
	      imem_c_rg_pc_BITS_1_TO_0_EQ_0b0_OR_NOT_near_me_ETC___d1118) ;
  assign csr_regfile_interrupt_pending_rg_cur_priv_6_14_ETC___d1158 =
	     (csr_regfile$interrupt_pending[4] || csr_regfile$nmi_pending) &&
	     NOT_stage2_rg_full_0_41_OR_stage2_rg_stage2_1__ETC___d527 &&
	     (IF_IF_imem_c_rg_pc_BITS_1_TO_0_EQ_0b0_OR_NOT_i_ETC___d727 ||
	      IF_IF_imem_c_rg_pc_BITS_1_TO_0_EQ_0b0_OR_NOT_i_ETC___d729) ;
  assign csr_regfile_interrupt_pending_rg_cur_priv_6_14_ETC___d1162 =
	     csr_regfile_interrupt_pending_rg_cur_priv_6_14_ETC___d1158 ||
	     stage2_rg_stage2[103:101] != 3'd0 &&
	     IF_stage2_rg_stage2_1_BITS_103_TO_101_2_EQ_1_4_ETC___d1159 &&
	     stage2_rg_full ;
  assign csr_regfile_interrupt_pending_rg_cur_priv_6_14_ETC___d1170 =
	     (csr_regfile$interrupt_pending[4] || csr_regfile$nmi_pending) &&
	     stage1_rg_full_06_AND_imem_c_rg_pc_BITS_31_TO__ETC___d1155 ||
	     (csr_regfile_interrupt_pending_rg_cur_priv_6_14_ETC___d1162 ||
	      NOT_imem_c_rg_pc_BITS_31_TO_2_0_EQ_imem_c_rg_c_ETC___d1167) &&
	     stage1_rg_full ;
  assign csr_regfile_read_csr_mcycle__5_MINUS_rg_start__ETC___d1374 =
	     delta_CPI_cycles__h20138 * 64'd10 ;
  assign csr_regfile_read_misa__3_BIT_2_46_AND_IF_NOT_i_ETC___d345 =
	     csr_regfile$read_misa[2] && instr__h4857[1:0] == 2'b10 &&
	     instr__h4857[15:12] == 4'b1000 &&
	     instr__h4857[11:7] != 5'd0 ;
  assign csr_regfile_read_misa__3_BIT_2_46_AND_IF_NOT_i_ETC___d351 =
	     csr_regfile$read_misa[2] && instr__h4857[1:0] == 2'b10 &&
	     instr__h4857[15:12] == 4'b1001 &&
	     instr__h4857[11:7] != 5'd0 ;
  assign cur_verbosity__h3469 =
	     (csr_regfile$read_csr_minstret < cfg_logdelay) ?
	       4'd0 :
	       cfg_verbosity ;
  assign data_to_stage2_addr__h12919 = x_out_data_to_stage2_addr__h12927 ;
  assign data_to_stage2_rd__h12918 = x_out_data_to_stage2_rd__h12926 ;
  assign data_to_stage2_val2__h12921 = x_out_data_to_stage2_val2__h12929 ;
  assign delta_CPI_cycles__h20138 =
	     csr_regfile$read_csr_mcycle - rg_start_CPI_cycles ;
  assign delta_CPI_instrs___1__h20184 = delta_CPI_instrs__h20139 + 64'd1 ;
  assign delta_CPI_instrs__h20139 =
	     csr_regfile$read_csr_minstret - rg_start_CPI_instrs ;
  assign eaddr__h13323 =
	     rs1_val_bypassed__h4867 +
	     SEXT_IF_imem_c_rg_pc_BITS_1_TO_0_EQ_0b0_OR_NOT_ETC___d952 ;
  assign fall_through_pc__h12722 =
	     imem_c_rg_pc +
	     (NOT_imem_c_rg_pc_BITS_1_TO_0_EQ_0b0_AND_imem_c_ETC___d519 ?
		32'd4 :
		32'd2) ;
  assign gpr_regfile_RDY_server_reset_request_put__089__ETC___d1101 =
	     gpr_regfile$RDY_server_reset_request_put &&
	     near_mem$RDY_server_reset_request_put &&
	     csr_regfile$RDY_server_reset_request_put &&
	     f_reset_reqs$EMPTY_N &&
	     stage1_f_reset_reqs$FULL_N &&
	     stage2_f_reset_reqs$FULL_N &&
	     stage3_f_reset_reqs$FULL_N ;
  assign imem_c_rg_cache_b16_BITS_15_TO_0__q1 = imem_c_rg_cache_b16[15:0] ;
  assign imem_c_rg_pc_BITS_1_TO_0_EQ_0b0_OR_NOT_imem_c__ETC___d1282 =
	     imem_c_rg_pc_BITS_1_TO_0_EQ_0b0_OR_NOT_imem_c__ETC___d243 ||
	     stage2_rg_full_0_AND_NOT_stage2_rg_stage2_1_BI_ETC___d511 ||
	     near_mem$imem_exc ||
	     IF_IF_imem_c_rg_pc_BITS_1_TO_0_EQ_0b0_OR_NOT_i_ETC___d669 &&
	     IF_IF_imem_c_rg_pc_BITS_1_TO_0_EQ_0b0_OR_NOT_i_ETC___d680 ;
  assign imem_c_rg_pc_BITS_1_TO_0_EQ_0b0_OR_NOT_imem_c__ETC___d1284 =
	     imem_c_rg_pc_BITS_1_TO_0_EQ_0b0_OR_NOT_imem_c__ETC___d243 ||
	     stage2_rg_full_0_AND_NOT_stage2_rg_stage2_1_BI_ETC___d511 ||
	     !near_mem$imem_exc &&
	     (IF_IF_imem_c_rg_pc_BITS_1_TO_0_EQ_0b0_OR_NOT_i_ETC___d727 ||
	      IF_IF_imem_c_rg_pc_BITS_1_TO_0_EQ_0b0_OR_NOT_i_ETC___d729) ;
  assign imem_c_rg_pc_BITS_1_TO_0_EQ_0b0_OR_NOT_imem_c__ETC___d235 =
	     (imem_c_rg_pc[1:0] == 2'b0 ||
	      !imem_c_rg_pc_BITS_31_TO_2_0_EQ_imem_c_rg_cache_ETC___d211 ||
	      !near_mem_imem_pc__1_EQ_imem_c_rg_pc_PLUS_2_14___d215 ||
	      !imem_c_rg_cache_b16[16] ||
	      imem_c_rg_cache_b16_BITS_15_TO_0__q1[1:0] != 2'b11) &&
	     (imem_c_rg_pc[1:0] != 2'b0 ||
	      !imem_c_rg_pc_BITS_31_TO_2_0_EQ_near_mem_imem_p_ETC___d13 ||
	      near_mem$imem_instr[1:0] != 2'b11) ;
  assign imem_c_rg_pc_BITS_1_TO_0_EQ_0b0_OR_NOT_imem_c__ETC___d243 =
	     imem_c_rg_pc_BITS_1_TO_0_EQ_0b0_OR_NOT_imem_c__ETC___d235 &&
	     (imem_c_rg_pc[1:0] == 2'b0 ||
	      (!imem_c_rg_pc_BITS_31_TO_2_0_EQ_near_mem_imem_p_ETC___d13 ||
	       near_mem$imem_instr[17:16] == 2'b11) &&
	      (!imem_c_rg_pc_BITS_31_TO_2_0_EQ_imem_c_rg_cache_ETC___d211 ||
	       !imem_c_rg_cache_b16[16] ||
	       imem_c_rg_cache_b16_BITS_15_TO_0__q1[1:0] == 2'b11)) &&
	     (imem_c_rg_pc[1:0] != 2'b0 ||
	      !imem_c_rg_pc_BITS_31_TO_2_0_EQ_near_mem_imem_p_ETC___d13 ||
	      near_mem$imem_instr[1:0] == 2'b11) ;
  assign imem_c_rg_pc_BITS_1_TO_0_EQ_0b0_OR_NOT_near_me_ETC___d1118 =
	     imem_c_rg_pc[1:0] == 2'b0 || !near_mem$imem_valid ||
	     !imem_c_rg_pc_BITS_31_TO_2_0_EQ_near_mem_imem_p_ETC___d13 ||
	     near_mem$imem_instr[17:16] != 2'b11 ;
  assign imem_c_rg_pc_BITS_31_TO_2_0_EQ_imem_c_rg_cache_ETC___d211 =
	     imem_c_rg_pc[31:2] == imem_c_rg_cache_addr[31:2] ;
  assign imem_c_rg_pc_BITS_31_TO_2_0_EQ_near_mem_imem_p_ETC___d13 =
	     imem_c_rg_pc[31:2] == near_mem$imem_pc[31:2] ;
  assign imem_c_rg_pc_BITS_31_TO_2_0_EQ_near_mem_imem_p_ETC___d260 =
	     imem_c_rg_pc_BITS_31_TO_2_0_EQ_near_mem_imem_p_ETC___d13 &&
	     near_mem$imem_instr[17:16] != 2'b11 ||
	     imem_c_rg_pc_BITS_31_TO_2_0_EQ_imem_c_rg_cache_ETC___d211 &&
	     imem_c_rg_cache_b16[16] &&
	     imem_c_rg_cache_b16_BITS_15_TO_0__q1[1:0] != 2'b11 ;
  assign imm12__h10442 = { {2{nzimm10__h10440[9]}}, nzimm10__h10440 } ;
  assign imm12__h10657 = { 2'd0, nzimm10__h10655 } ;
  assign imm12__h10853 = { 7'b0, instr__h4857[6:2] } ;
  assign imm12__h11198 = { 7'b0100000, instr__h4857[6:2] } ;
  assign imm12__h7565 = { 4'd0, offset__h7299 } ;
  assign imm12__h7902 = { 5'd0, offset__h7844 } ;
  assign imm12__h9818 = { {6{imm6__h9816[5]}}, imm6__h9816 } ;
  assign imm20__h9946 = { {14{imm6__h9816[5]}}, imm6__h9816 } ;
  assign imm6__h9816 = { instr__h4857[12], instr__h4857[6:2] } ;
  assign instr___1__h7261 =
	     (csr_regfile$read_misa[2] && instr__h4857[1:0] == 2'b10 &&
	      instr__h4857[11:7] != 5'd0 &&
	      instr__h4857[15:13] == 3'b010) ?
	       instr__h7564 :
	       IF_csr_regfile_read_misa__3_BIT_2_46_AND_IF_NO_ETC___d503 ;
  assign instr__h10078 = { imm20__h9946, instr__h4857[11:7], 7'b0110111 } ;
  assign instr__h10207 =
	     { imm12__h9818,
	       instr__h4857[11:7],
	       3'b0,
	       instr__h4857[11:7],
	       7'b0010011 } ;
  assign instr__h10644 =
	     { imm12__h10442,
	       instr__h4857[11:7],
	       3'b0,
	       instr__h4857[11:7],
	       7'b0010011 } ;
  assign instr__h10816 = { imm12__h10657, 8'd16, rd__h7904, 7'b0010011 } ;
  assign instr__h10989 =
	     { imm12__h10853,
	       instr__h4857[11:7],
	       3'b001,
	       instr__h4857[11:7],
	       7'b0010011 } ;
  assign instr__h11182 =
	     { imm12__h10853, rs1__h7903, 3'b101, rs1__h7903, 7'b0010011 } ;
  assign instr__h11375 =
	     { imm12__h11198, rs1__h7903, 3'b101, rs1__h7903, 7'b0010011 } ;
  assign instr__h11492 =
	     { imm12__h9818, rs1__h7903, 3'b111, rs1__h7903, 7'b0010011 } ;
  assign instr__h11670 =
	     { 7'b0,
	       instr__h4857[6:2],
	       8'd0,
	       instr__h4857[11:7],
	       7'b0110011 } ;
  assign instr__h11789 =
	     { 7'b0,
	       instr__h4857[6:2],
	       instr__h4857[11:7],
	       3'b0,
	       instr__h4857[11:7],
	       7'b0110011 } ;
  assign instr__h11884 =
	     { 7'b0, rd__h7904, rs1__h7903, 3'b111, rs1__h7903, 7'b0110011 } ;
  assign instr__h12020 =
	     { 7'b0, rd__h7904, rs1__h7903, 3'b110, rs1__h7903, 7'b0110011 } ;
  assign instr__h12156 =
	     { 7'b0, rd__h7904, rs1__h7903, 3'b100, rs1__h7903, 7'b0110011 } ;
  assign instr__h12292 =
	     { 7'b0100000,
	       rd__h7904,
	       rs1__h7903,
	       3'b0,
	       rs1__h7903,
	       7'b0110011 } ;
  assign instr__h12630 =
	     { 12'b000000000001,
	       instr__h4857[11:7],
	       3'b0,
	       instr__h4857[11:7],
	       7'b1110011 } ;
  assign instr__h4857 =
	     NOT_imem_c_rg_pc_BITS_1_TO_0_EQ_0b0_AND_imem_c_ETC___d250 ?
	       instr_out___1__h7399 :
	       IF_imem_c_rg_pc_BITS_1_TO_0_EQ_0b0_AND_imem_c__ETC___d266 ;
  assign instr__h7564 =
	     { imm12__h7565, 8'd18, instr__h4857[11:7], 7'b0000011 } ;
  assign instr__h7709 =
	     { 4'd0,
	       instr__h4857[8:7],
	       instr__h4857[12],
	       instr__h4857[6:2],
	       8'd18,
	       offset_BITS_4_TO_0___h7833,
	       7'b0100011 } ;
  assign instr__h7901 =
	     { imm12__h7902, rs1__h7903, 3'b010, rd__h7904, 7'b0000011 } ;
  assign instr__h8096 =
	     { 5'd0,
	       instr__h4857[5],
	       instr__h4857[12],
	       rd__h7904,
	       rs1__h7903,
	       3'b010,
	       offset_BITS_4_TO_0___h8264,
	       7'b0100011 } ;
  assign instr__h8325 =
	     { SEXT_IF_NOT_imem_c_rg_pc_BITS_1_TO_0_EQ_0b0_AN_ETC___d331[20],
	       SEXT_IF_NOT_imem_c_rg_pc_BITS_1_TO_0_EQ_0b0_AN_ETC___d331[10:1],
	       SEXT_IF_NOT_imem_c_rg_pc_BITS_1_TO_0_EQ_0b0_AN_ETC___d331[11],
	       SEXT_IF_NOT_imem_c_rg_pc_BITS_1_TO_0_EQ_0b0_AN_ETC___d331[19:12],
	       12'd111 } ;
  assign instr__h8668 =
	     { SEXT_IF_NOT_imem_c_rg_pc_BITS_1_TO_0_EQ_0b0_AN_ETC___d331[20],
	       SEXT_IF_NOT_imem_c_rg_pc_BITS_1_TO_0_EQ_0b0_AN_ETC___d331[10:1],
	       SEXT_IF_NOT_imem_c_rg_pc_BITS_1_TO_0_EQ_0b0_AN_ETC___d331[11],
	       SEXT_IF_NOT_imem_c_rg_pc_BITS_1_TO_0_EQ_0b0_AN_ETC___d331[19:12],
	       12'd239 } ;
  assign instr__h9058 = { 12'd0, instr__h4857[11:7], 15'd103 } ;
  assign instr__h9174 = { 12'd0, instr__h4857[11:7], 15'd231 } ;
  assign instr__h9239 =
	     { SEXT_IF_NOT_imem_c_rg_pc_BITS_1_TO_0_EQ_0b0_AN_ETC___d360[12],
	       SEXT_IF_NOT_imem_c_rg_pc_BITS_1_TO_0_EQ_0b0_AN_ETC___d360[10:5],
	       5'd0,
	       rs1__h7903,
	       3'b0,
	       SEXT_IF_NOT_imem_c_rg_pc_BITS_1_TO_0_EQ_0b0_AN_ETC___d360[4:1],
	       SEXT_IF_NOT_imem_c_rg_pc_BITS_1_TO_0_EQ_0b0_AN_ETC___d360[11],
	       7'b1100011 } ;
  assign instr__h9556 =
	     { SEXT_IF_NOT_imem_c_rg_pc_BITS_1_TO_0_EQ_0b0_AN_ETC___d360[12],
	       SEXT_IF_NOT_imem_c_rg_pc_BITS_1_TO_0_EQ_0b0_AN_ETC___d360[10:5],
	       5'd0,
	       rs1__h7903,
	       3'b001,
	       SEXT_IF_NOT_imem_c_rg_pc_BITS_1_TO_0_EQ_0b0_AN_ETC___d360[4:1],
	       SEXT_IF_NOT_imem_c_rg_pc_BITS_1_TO_0_EQ_0b0_AN_ETC___d360[11],
	       7'b1100011 } ;
  assign instr__h9894 =
	     { imm12__h9818, 8'd0, instr__h4857[11:7], 7'b0010011 } ;
  assign instr_out___1__h7399 =
	     { near_mem$imem_instr[15:0], imem_c_rg_cache_b16[15:0] } ;
  assign instr_out___1__h7431 = { 16'b0, near_mem$imem_instr[15:0] } ;
  assign near_mem_imem_exc__29_OR_IF_IF_imem_c_rg_pc_BI_ETC___d1024 =
	     IF_IF_imem_c_rg_pc_BITS_1_TO_0_EQ_0b0_OR_NOT_i_ETC___d669 &&
	     IF_IF_imem_c_rg_pc_BITS_1_TO_0_EQ_0b0_OR_NOT_i_ETC___d680 &&
	     NOT_stage2_rg_full_0_41_OR_stage2_rg_stage2_1__ETC___d735 &&
	     NOT_stage2_rg_full_0_41_OR_stage2_rg_stage2_1__ETC___d736 &&
	     !near_mem$imem_exc &&
	     IF_IF_imem_c_rg_pc_BITS_1_TO_0_EQ_0b0_OR_NOT_i_ETC___d727 ;
  assign near_mem_imem_exc__29_OR_IF_IF_imem_c_rg_pc_BI_ETC___d1027 =
	     (near_mem$imem_exc ||
	      IF_IF_imem_c_rg_pc_BITS_1_TO_0_EQ_0b0_OR_NOT_i_ETC___d669 &&
	      IF_IF_imem_c_rg_pc_BITS_1_TO_0_EQ_0b0_OR_NOT_i_ETC___d680) &&
	     stage2_rg_full_0_AND_NOT_stage2_rg_stage2_1_BI_ETC___d746 ;
  assign near_mem_imem_exc__29_OR_IF_IF_imem_c_rg_pc_BI_ETC___d1030 =
	     (near_mem$imem_exc ||
	      IF_IF_imem_c_rg_pc_BITS_1_TO_0_EQ_0b0_OR_NOT_i_ETC___d669 &&
	      IF_IF_imem_c_rg_pc_BITS_1_TO_0_EQ_0b0_OR_NOT_i_ETC___d680) &&
	     stage2_rg_full_0_AND_NOT_stage2_rg_stage2_1_BI_ETC___d758 ;
  assign near_mem_imem_exc__29_OR_IF_IF_imem_c_rg_pc_BI_ETC___d1033 =
	     (near_mem$imem_exc ||
	      IF_IF_imem_c_rg_pc_BITS_1_TO_0_EQ_0b0_OR_NOT_i_ETC___d669 &&
	      IF_IF_imem_c_rg_pc_BITS_1_TO_0_EQ_0b0_OR_NOT_i_ETC___d680) &&
	     stage2_rg_full_0_AND_NOT_stage2_rg_stage2_1_BI_ETC___d772 ;
  assign near_mem_imem_exc__29_OR_IF_IF_imem_c_rg_pc_BI_ETC___d1036 =
	     (near_mem$imem_exc ||
	      IF_IF_imem_c_rg_pc_BITS_1_TO_0_EQ_0b0_OR_NOT_i_ETC___d669 &&
	      IF_IF_imem_c_rg_pc_BITS_1_TO_0_EQ_0b0_OR_NOT_i_ETC___d680) &&
	     stage2_rg_full_0_AND_NOT_stage2_rg_stage2_1_BI_ETC___d781 ;
  assign near_mem_imem_exc__29_OR_IF_IF_imem_c_rg_pc_BI_ETC___d1039 =
	     (near_mem$imem_exc ||
	      IF_IF_imem_c_rg_pc_BITS_1_TO_0_EQ_0b0_OR_NOT_i_ETC___d669 &&
	      IF_IF_imem_c_rg_pc_BITS_1_TO_0_EQ_0b0_OR_NOT_i_ETC___d680) &&
	     stage2_rg_full_0_AND_NOT_stage2_rg_stage2_1_BI_ETC___d789 ;
  assign near_mem_imem_exc__29_OR_IF_IF_imem_c_rg_pc_BI_ETC___d1042 =
	     (near_mem$imem_exc ||
	      IF_IF_imem_c_rg_pc_BITS_1_TO_0_EQ_0b0_OR_NOT_i_ETC___d669 &&
	      IF_IF_imem_c_rg_pc_BITS_1_TO_0_EQ_0b0_OR_NOT_i_ETC___d680) &&
	     stage2_rg_full_0_AND_NOT_stage2_rg_stage2_1_BI_ETC___d806 ;
  assign near_mem_imem_exc__29_OR_IF_IF_imem_c_rg_pc_BI_ETC___d1045 =
	     (near_mem$imem_exc ||
	      IF_IF_imem_c_rg_pc_BITS_1_TO_0_EQ_0b0_OR_NOT_i_ETC___d669 &&
	      IF_IF_imem_c_rg_pc_BITS_1_TO_0_EQ_0b0_OR_NOT_i_ETC___d680) &&
	     stage2_rg_full_0_AND_NOT_stage2_rg_stage2_1_BI_ETC___d826 ;
  assign near_mem_imem_exc__29_OR_IF_IF_imem_c_rg_pc_BI_ETC___d1048 =
	     (near_mem$imem_exc ||
	      IF_IF_imem_c_rg_pc_BITS_1_TO_0_EQ_0b0_OR_NOT_i_ETC___d669 &&
	      IF_IF_imem_c_rg_pc_BITS_1_TO_0_EQ_0b0_OR_NOT_i_ETC___d680) &&
	     stage2_rg_full_0_AND_NOT_stage2_rg_stage2_1_BI_ETC___d881 ;
  assign near_mem_imem_pc__1_EQ_imem_c_rg_pc_PLUS_2_14___d215 =
	     near_mem$imem_pc == next_pc___1__h14698 ;
  assign near_mem_imem_valid_AND_NOT_imem_c_rg_pc_BITS__ETC___d1214 =
	     near_mem$imem_valid &&
	     NOT_imem_c_rg_pc_BITS_1_TO_0_EQ_0b0_AND_imem_c_ETC___d521 &&
	     NOT_stage2_rg_full_0_41_OR_stage2_rg_stage2_1__ETC___d527 &&
	     !near_mem$imem_exc &&
	     (IF_IF_imem_c_rg_pc_BITS_1_TO_0_EQ_0b0_OR_NOT_i_ETC___d727 ||
	      IF_IF_imem_c_rg_pc_BITS_1_TO_0_EQ_0b0_OR_NOT_i_ETC___d729) ;
  assign near_mem_imem_valid_AND_NOT_imem_c_rg_pc_BITS__ETC___d1331 =
	     near_mem$imem_valid &&
	     NOT_imem_c_rg_pc_BITS_1_TO_0_EQ_0b0_AND_imem_c_ETC___d521 &&
	     (near_mem$imem_exc ||
	      IF_IF_imem_c_rg_pc_BITS_1_TO_0_EQ_0b0_OR_NOT_i_ETC___d669 &&
	      IF_IF_imem_c_rg_pc_BITS_1_TO_0_EQ_0b0_OR_NOT_i_ETC___d680) ;
  assign near_mem_imem_valid_AND_NOT_imem_c_rg_pc_BITS__ETC___d683 =
	     near_mem$imem_valid &&
	     NOT_imem_c_rg_pc_BITS_1_TO_0_EQ_0b0_AND_imem_c_ETC___d521 &&
	     NOT_stage2_rg_full_0_41_OR_stage2_rg_stage2_1__ETC___d527 &&
	     (near_mem$imem_exc ||
	      IF_IF_imem_c_rg_pc_BITS_1_TO_0_EQ_0b0_OR_NOT_i_ETC___d669 &&
	      IF_IF_imem_c_rg_pc_BITS_1_TO_0_EQ_0b0_OR_NOT_i_ETC___d680) ;
  assign near_mem_imem_valid_AND_NOT_imem_c_rg_pc_BITS__ETC___d733 =
	     near_mem$imem_valid &&
	     NOT_imem_c_rg_pc_BITS_1_TO_0_EQ_0b0_AND_imem_c_ETC___d521 &&
	     NOT_stage2_rg_full_0_41_OR_stage2_rg_stage2_1__ETC___d527 &&
	     stage2_rg_full_0_AND_NOT_stage2_rg_stage2_1_BI_ETC___d732 ;
  assign near_mem_imem_valid_AND_NOT_imem_c_rg_pc_BITS__ETC___d740 =
	     near_mem$imem_valid &&
	     NOT_imem_c_rg_pc_BITS_1_TO_0_EQ_0b0_AND_imem_c_ETC___d521 &&
	     NOT_stage2_rg_full_0_41_OR_stage2_rg_stage2_1__ETC___d527 &&
	     NOT_stage2_rg_full_0_41_OR_stage2_rg_stage2_1__ETC___d735 &&
	     NOT_stage2_rg_full_0_41_OR_stage2_rg_stage2_1__ETC___d736 &&
	     !near_mem$imem_exc &&
	     IF_IF_imem_c_rg_pc_BITS_1_TO_0_EQ_0b0_OR_NOT_i_ETC___d727 ;
  assign near_mem_imem_valid_AND_NOT_imem_c_rg_pc_BITS__ETC___d760 =
	     near_mem$imem_valid &&
	     NOT_imem_c_rg_pc_BITS_1_TO_0_EQ_0b0_AND_imem_c_ETC___d521 &&
	     NOT_stage2_rg_full_0_41_OR_stage2_rg_stage2_1__ETC___d527 &&
	     (stage2_rg_full_0_AND_NOT_stage2_rg_stage2_1_BI_ETC___d511 ||
	      IF_IF_imem_c_rg_pc_BITS_1_TO_0_EQ_0b0_OR_NOT_i_ETC___d727 ||
	      IF_IF_imem_c_rg_pc_BITS_1_TO_0_EQ_0b0_OR_NOT_i_ETC___d729) &&
	     stage2_rg_full_0_AND_NOT_stage2_rg_stage2_1_BI_ETC___d758 ;
  assign near_mem_imem_valid_AND_NOT_imem_c_rg_pc_BITS__ETC___d774 =
	     near_mem$imem_valid &&
	     NOT_imem_c_rg_pc_BITS_1_TO_0_EQ_0b0_AND_imem_c_ETC___d521 &&
	     NOT_stage2_rg_full_0_41_OR_stage2_rg_stage2_1__ETC___d527 &&
	     (stage2_rg_full_0_AND_NOT_stage2_rg_stage2_1_BI_ETC___d511 ||
	      IF_IF_imem_c_rg_pc_BITS_1_TO_0_EQ_0b0_OR_NOT_i_ETC___d727 ||
	      IF_IF_imem_c_rg_pc_BITS_1_TO_0_EQ_0b0_OR_NOT_i_ETC___d729) &&
	     stage2_rg_full_0_AND_NOT_stage2_rg_stage2_1_BI_ETC___d772 ;
  assign near_mem_imem_valid_AND_NOT_imem_c_rg_pc_BITS__ETC___d783 =
	     near_mem$imem_valid &&
	     NOT_imem_c_rg_pc_BITS_1_TO_0_EQ_0b0_AND_imem_c_ETC___d521 &&
	     NOT_stage2_rg_full_0_41_OR_stage2_rg_stage2_1__ETC___d527 &&
	     (stage2_rg_full_0_AND_NOT_stage2_rg_stage2_1_BI_ETC___d511 ||
	      IF_IF_imem_c_rg_pc_BITS_1_TO_0_EQ_0b0_OR_NOT_i_ETC___d727 ||
	      IF_IF_imem_c_rg_pc_BITS_1_TO_0_EQ_0b0_OR_NOT_i_ETC___d729) &&
	     stage2_rg_full_0_AND_NOT_stage2_rg_stage2_1_BI_ETC___d781 ;
  assign near_mem_imem_valid_AND_NOT_imem_c_rg_pc_BITS__ETC___d791 =
	     near_mem$imem_valid &&
	     NOT_imem_c_rg_pc_BITS_1_TO_0_EQ_0b0_AND_imem_c_ETC___d521 &&
	     NOT_stage2_rg_full_0_41_OR_stage2_rg_stage2_1__ETC___d527 &&
	     (stage2_rg_full_0_AND_NOT_stage2_rg_stage2_1_BI_ETC___d511 ||
	      IF_IF_imem_c_rg_pc_BITS_1_TO_0_EQ_0b0_OR_NOT_i_ETC___d727 ||
	      IF_IF_imem_c_rg_pc_BITS_1_TO_0_EQ_0b0_OR_NOT_i_ETC___d729) &&
	     stage2_rg_full_0_AND_NOT_stage2_rg_stage2_1_BI_ETC___d789 ;
  assign near_mem_imem_valid_AND_NOT_imem_c_rg_pc_BITS__ETC___d808 =
	     near_mem$imem_valid &&
	     NOT_imem_c_rg_pc_BITS_1_TO_0_EQ_0b0_AND_imem_c_ETC___d521 &&
	     NOT_stage2_rg_full_0_41_OR_stage2_rg_stage2_1__ETC___d527 &&
	     (stage2_rg_full_0_AND_NOT_stage2_rg_stage2_1_BI_ETC___d511 ||
	      IF_IF_imem_c_rg_pc_BITS_1_TO_0_EQ_0b0_OR_NOT_i_ETC___d727 ||
	      IF_IF_imem_c_rg_pc_BITS_1_TO_0_EQ_0b0_OR_NOT_i_ETC___d729) &&
	     stage2_rg_full_0_AND_NOT_stage2_rg_stage2_1_BI_ETC___d806 ;
  assign near_mem_imem_valid_AND_NOT_imem_c_rg_pc_BITS__ETC___d828 =
	     near_mem$imem_valid &&
	     NOT_imem_c_rg_pc_BITS_1_TO_0_EQ_0b0_AND_imem_c_ETC___d521 &&
	     NOT_stage2_rg_full_0_41_OR_stage2_rg_stage2_1__ETC___d527 &&
	     (stage2_rg_full_0_AND_NOT_stage2_rg_stage2_1_BI_ETC___d511 ||
	      IF_IF_imem_c_rg_pc_BITS_1_TO_0_EQ_0b0_OR_NOT_i_ETC___d727 ||
	      IF_IF_imem_c_rg_pc_BITS_1_TO_0_EQ_0b0_OR_NOT_i_ETC___d729) &&
	     stage2_rg_full_0_AND_NOT_stage2_rg_stage2_1_BI_ETC___d826 ;
  assign near_mem_imem_valid_AND_NOT_imem_c_rg_pc_BITS__ETC___d883 =
	     near_mem$imem_valid &&
	     NOT_imem_c_rg_pc_BITS_1_TO_0_EQ_0b0_AND_imem_c_ETC___d521 &&
	     NOT_stage2_rg_full_0_41_OR_stage2_rg_stage2_1__ETC___d527 &&
	     stage2_rg_full_0_AND_NOT_stage2_rg_stage2_1_BI_ETC___d732 &&
	     stage2_rg_full_0_AND_NOT_stage2_rg_stage2_1_BI_ETC___d881 ;
  assign near_mem_imem_valid_AND_NOT_imem_c_rg_pc_BITS__ETC___d892 =
	     near_mem$imem_valid &&
	     NOT_imem_c_rg_pc_BITS_1_TO_0_EQ_0b0_AND_imem_c_ETC___d521 &&
	     NOT_stage2_rg_full_0_41_OR_stage2_rg_stage2_1__ETC___d527 &&
	     stage2_rg_full_0_AND_NOT_stage2_rg_stage2_1_BI_ETC___d732 &&
	     NOT_stage2_rg_full_0_41_OR_stage2_rg_stage2_1__ETC___d890 ;
  assign near_mem_imem_valid_AND_NOT_imem_c_rg_pc_BITS__ETC___d896 =
	     near_mem$imem_valid &&
	     NOT_imem_c_rg_pc_BITS_1_TO_0_EQ_0b0_AND_imem_c_ETC___d521 &&
	     NOT_stage2_rg_full_0_41_OR_stage2_rg_stage2_1__ETC___d527 &&
	     stage2_rg_full_0_AND_NOT_stage2_rg_stage2_1_BI_ETC___d732 &&
	     NOT_stage2_rg_full_0_41_OR_stage2_rg_stage2_1__ETC___d735 &&
	     NOT_stage2_rg_full_0_41_OR_stage2_rg_stage2_1__ETC___d736 &&
	     _theResult____h4859[6:0] == 7'b0000011 ;
  assign near_mem_imem_valid_AND_NOT_imem_c_rg_pc_BITS__ETC___d900 =
	     near_mem$imem_valid &&
	     NOT_imem_c_rg_pc_BITS_1_TO_0_EQ_0b0_AND_imem_c_ETC___d521 &&
	     NOT_stage2_rg_full_0_41_OR_stage2_rg_stage2_1__ETC___d527 &&
	     stage2_rg_full_0_AND_NOT_stage2_rg_stage2_1_BI_ETC___d732 &&
	     NOT_stage2_rg_full_0_41_OR_stage2_rg_stage2_1__ETC___d735 &&
	     NOT_stage2_rg_full_0_41_OR_stage2_rg_stage2_1__ETC___d736 &&
	     _theResult____h4859[6:0] == 7'b0100011 ;
  assign near_mem_imem_valid_AND_NOT_imem_c_rg_pc_BITS__ETC___d904 =
	     near_mem$imem_valid &&
	     NOT_imem_c_rg_pc_BITS_1_TO_0_EQ_0b0_AND_imem_c_ETC___d521 &&
	     NOT_stage2_rg_full_0_41_OR_stage2_rg_stage2_1__ETC___d527 &&
	     stage2_rg_full_0_AND_NOT_stage2_rg_stage2_1_BI_ETC___d732 &&
	     NOT_stage2_rg_full_0_41_OR_stage2_rg_stage2_1__ETC___d735 &&
	     NOT_stage2_rg_full_0_41_OR_stage2_rg_stage2_1__ETC___d736 &&
	     _theResult____h4859[6:0] == 7'b0110011 &&
	     _theResult____h4859[31:25] == 7'b0000001 ;
  assign near_mem_imem_valid_AND_NOT_imem_c_rg_pc_BITS__ETC___d924 =
	     near_mem$imem_valid &&
	     NOT_imem_c_rg_pc_BITS_1_TO_0_EQ_0b0_AND_imem_c_ETC___d521 &&
	     NOT_stage2_rg_full_0_41_OR_stage2_rg_stage2_1__ETC___d527 &&
	     stage2_rg_full_0_AND_NOT_stage2_rg_stage2_1_BI_ETC___d732 &&
	     stage2_rg_full_0_AND_NOT_stage2_rg_stage2_1_BI_ETC___d914 &&
	     stage2_rg_full_0_AND_NOT_stage2_rg_stage2_1_BI_ETC___d921 ;
  assign next_pc___1__h14698 = imem_c_rg_pc + 32'd2 ;
  assign next_pc__h14696 = imem_c_rg_pc + 32'd4 ;
  assign nzimm10__h10440 =
	     { instr__h4857[12],
	       instr__h4857[4:3],
	       instr__h4857[5],
	       instr__h4857[2],
	       instr__h4857[6],
	       4'b0 } ;
  assign nzimm10__h10655 =
	     { instr__h4857[10:7],
	       instr__h4857[12:11],
	       instr__h4857[5],
	       instr__h4857[6],
	       2'b0 } ;
  assign offset_BITS_4_TO_0___h7833 = { instr__h4857[11:9], 2'b0 } ;
  assign offset_BITS_4_TO_0___h8264 =
	     { instr__h4857[11:10], instr__h4857[6], 2'b0 } ;
  assign offset__h7299 =
	     { instr__h4857[3:2],
	       instr__h4857[12],
	       instr__h4857[6:4],
	       2'b0 } ;
  assign offset__h7844 =
	     { instr__h4857[5], instr__h4857[12:10], instr__h4857[6], 2'b0 } ;
  assign offset__h8272 =
	     { instr__h4857[12],
	       instr__h4857[8],
	       instr__h4857[10:9],
	       instr__h4857[6],
	       instr__h4857[7],
	       instr__h4857[2],
	       instr__h4857[11],
	       instr__h4857[5:3],
	       1'b0 } ;
  assign offset__h9183 =
	     { instr__h4857[12],
	       instr__h4857[6:5],
	       instr__h4857[2],
	       instr__h4857[11:10],
	       instr__h4857[4:3],
	       1'b0 } ;
  assign rd__h7904 = { 2'b01, instr__h4857[4:2] } ;
  assign rd_val___1__h14009 =
	     rs1_val_bypassed__h4867 + _theResult___snd__h15372 ;
  assign rd_val___1__h14017 =
	     rs1_val_bypassed__h4867 - _theResult___snd__h15372 ;
  assign rd_val___1__h14024 =
	     ((rs1_val_bypassed__h4867 ^ 32'h80000000) <
	      (_theResult___snd__h15372 ^ 32'h80000000)) ?
	       32'd1 :
	       32'd0 ;
  assign rd_val___1__h14031 =
	     (rs1_val_bypassed__h4867 < _theResult___snd__h15372) ?
	       32'd1 :
	       32'd0 ;
  assign rd_val___1__h14038 =
	     rs1_val_bypassed__h4867 ^ _theResult___snd__h15372 ;
  assign rd_val___1__h14045 =
	     rs1_val_bypassed__h4867 | _theResult___snd__h15372 ;
  assign rd_val__h12672 =
	     (stage3_rg_full && stage3_rg_stage3[37] &&
	      stage3_rg_stage3[36:32] == _theResult____h4859[24:20]) ?
	       stage3_rg_stage3[31:0] :
	       gpr_regfile$read_rs2 ;
  assign rd_val__h13293 = { _theResult____h4859[31:12], 12'h0 } ;
  assign rd_val__h13307 = imem_c_rg_pc + rd_val__h13293 ;
  assign rd_val__h15268 = rs1_val_bypassed__h4867 << shamt__h13237 ;
  assign rd_val__h15320 = rs1_val_bypassed__h4867 >> shamt__h13237 ;
  assign rd_val__h15342 =
	     rs1_val_bypassed__h4867 >> shamt__h13237 |
	     ~(32'hFFFFFFFF >> shamt__h13237) &
	     {32{rs1_val_bypassed__h4867[31]}} ;
  assign rd_val__h7206 =
	     (stage3_rg_full && stage3_rg_stage3[37] &&
	      stage3_rg_stage3[36:32] == _theResult____h4859[19:15]) ?
	       stage3_rg_stage3[31:0] :
	       gpr_regfile$read_rs1 ;
  assign rg_cur_priv_6_EQ_0b11_96_OR_rg_cur_priv_6_EQ_0_ETC___d819 =
	     (rg_cur_priv == 2'b11 ||
	      rg_cur_priv == 2'b01 && !csr_regfile$read_mstatus[21] ||
	      rg_cur_priv == 2'b0 && csr_regfile$read_misa[13]) &&
	     _theResult____h4859[31:20] == 12'b000100000101 ;
  assign rg_state_5_EQ_3_172_AND_NOT_csr_regfile_interr_ETC___d1330 =
	     rg_state == 4'd3 &&
	     NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d1327 &&
	     !stage3_rg_full &&
	     !stage2_rg_full ;
  assign rg_state_5_EQ_3_172_AND_NOT_csr_regfile_interr_ETC___d1387 =
	     rg_state == 4'd3 &&
	     (!csr_regfile$interrupt_pending[4] && !csr_regfile$nmi_pending ||
	      IF_IF_imem_c_rg_pc_BITS_1_TO_0_EQ_0b0_OR_NOT_i_ETC___d727 ||
	      IF_IF_imem_c_rg_pc_BITS_1_TO_0_EQ_0b0_OR_NOT_i_ETC___d729) ;
  assign rg_state_5_EQ_3_172_AND_NOT_csr_regfile_interr_ETC___d1390 =
	     rg_state_5_EQ_3_172_AND_NOT_csr_regfile_interr_ETC___d1387 &&
	     !stage3_rg_full &&
	     !stage2_rg_full &&
	     stage1_rg_full &&
	     near_mem_imem_valid_AND_NOT_imem_c_rg_pc_BITS__ETC___d1331 ;
  assign rg_state_5_EQ_3_172_AND_stage3_rg_full_1_OR_st_ETC___d1192 =
	     rg_state == 4'd3 &&
	     (stage3_rg_full || stage2_rg_full || stage1_rg_full) &&
	     stage3_rg_full_1_OR_NOT_stage2_rg_full_0_41_OR_ETC___d1181 &&
	     (NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d1189 ||
	      stage2_rg_full ||
	      stage3_rg_full) ;
  assign rg_trap_info_360_BITS_67_TO_36_361_EQ_csr_regf_ETC___d1370 =
	     rg_trap_info[67:36] == csr_regfile$csr_trap_actions[97:66] ;
  assign rs1__h7903 = { 2'b01, instr__h4857[9:7] } ;
  assign rs1_val__h20670 =
	     (rg_trap_instr[14:12] == 3'b001) ?
	       rg_csr_val1 :
	       { 27'd0, rg_trap_instr[19:15] } ;
  assign rs1_val_bypassed__h4867 =
	     (_theResult____h4859[19:15] == 5'd0) ? 32'd0 : val__h7208 ;
  assign rs2_val_bypassed__h4873 =
	     (_theResult____h4859[24:20] == 5'd0) ? 32'd0 : val__h12674 ;
  assign shamt__h13237 =
	     (_theResult____h4859[6:0] == 7'b0010011) ?
	       _theResult____h4859[24:20] :
	       rs2_val_bypassed__h4873[4:0] ;
  assign stage1_rg_full_06_AND_NOT_near_mem_imem_valid__ETC___d517 =
	     stage1_rg_full &&
	     (!near_mem$imem_valid ||
	      imem_c_rg_pc_BITS_1_TO_0_EQ_0b0_OR_NOT_imem_c__ETC___d243 ||
	      stage2_rg_full_0_AND_NOT_stage2_rg_stage2_1_BI_ETC___d511) ;
  assign stage1_rg_full_06_AND_imem_c_rg_pc_BITS_31_TO__ETC___d1155 =
	     stage1_rg_full &&
	     imem_c_rg_pc_BITS_31_TO_2_0_EQ_imem_c_rg_cache_ETC___d211 &&
	     (near_mem_imem_pc__1_EQ_imem_c_rg_pc_PLUS_2_14___d215 &&
	      imem_c_rg_cache_b16[16] &&
	      imem_c_rg_cache_b16_BITS_15_TO_0__q1[1:0] == 2'b11 ||
	      imem_c_rg_cache_b16[16] &&
	      imem_c_rg_cache_b16_BITS_15_TO_0__q1[1:0] != 2'b11) &&
	     NOT_stage2_rg_full_0_41_OR_stage2_rg_stage2_1__ETC___d527 &&
	     IF_IF_imem_c_rg_pc_BITS_1_TO_0_EQ_0b0_OR_NOT_i_ETC___d1153 ;
  assign stage2_rg_full_0_AND_IF_stage2_rg_stage2_1_BIT_ETC___d1205 =
	     stage2_rg_full &&
	     IF_stage2_rg_stage2_1_BITS_103_TO_101_2_EQ_1_4_ETC___d1196 &&
	     NOT_IF_csr_regfile_read_csr_minstret__8_ULT_cf_ETC___d44 &&
	     stage2_rg_stage2[103:101] != 3'd0 &&
	     IF_stage2_rg_stage2_1_BITS_103_TO_101_2_EQ_1_4_ETC___d144 ;
  assign stage2_rg_full_0_AND_NOT_stage2_rg_stage2_1_BI_ETC___d120 =
	     stage2_rg_full && stage2_rg_stage2[103:101] != 3'd0 &&
	     CASE_stage2_rg_stage2_BITS_103_TO_101_1_NOT_ne_ETC__q15 ;
  assign stage2_rg_full_0_AND_NOT_stage2_rg_stage2_1_BI_ETC___d511 =
	     stage2_rg_full && stage2_rg_stage2[103:101] != 3'd0 &&
	     IF_stage2_rg_stage2_1_BITS_103_TO_101_2_EQ_1_4_ETC___d196 &&
	     (IF_stage2_rg_full_0_THEN_IF_stage2_rg_stage2_1_ETC___d507 ||
	      IF_stage2_rg_full_0_THEN_IF_stage2_rg_stage2_1_ETC___d509) ;
  assign stage2_rg_full_0_AND_NOT_stage2_rg_stage2_1_BI_ETC___d732 =
	     stage2_rg_full_0_AND_NOT_stage2_rg_stage2_1_BI_ETC___d511 ||
	     !near_mem$imem_exc &&
	     (IF_IF_imem_c_rg_pc_BITS_1_TO_0_EQ_0b0_OR_NOT_i_ETC___d727 ||
	      IF_IF_imem_c_rg_pc_BITS_1_TO_0_EQ_0b0_OR_NOT_i_ETC___d729) ;
  assign stage2_rg_full_0_AND_NOT_stage2_rg_stage2_1_BI_ETC___d746 =
	     (stage2_rg_full_0_AND_NOT_stage2_rg_stage2_1_BI_ETC___d511 ||
	      IF_IF_imem_c_rg_pc_BITS_1_TO_0_EQ_0b0_OR_NOT_i_ETC___d669) &&
	     NOT_stage2_rg_full_0_41_OR_stage2_rg_stage2_1__ETC___d735 &&
	     NOT_stage2_rg_full_0_41_OR_stage2_rg_stage2_1__ETC___d736 &&
	     !near_mem$imem_exc &&
	     IF_IF_imem_c_rg_pc_BITS_1_TO_0_EQ_0b0_OR_NOT_i_ETC___d729 ;
  assign stage2_rg_full_0_AND_NOT_stage2_rg_stage2_1_BI_ETC___d757 =
	     (stage2_rg_full_0_AND_NOT_stage2_rg_stage2_1_BI_ETC___d511 ||
	      near_mem$imem_exc ||
	      IF_IF_imem_c_rg_pc_BITS_1_TO_0_EQ_0b0_OR_NOT_i_ETC___d680) &&
	     NOT_stage2_rg_full_0_41_OR_stage2_rg_stage2_1__ETC___d735 &&
	     NOT_stage2_rg_full_0_41_OR_stage2_rg_stage2_1__ETC___d736 &&
	     NOT_near_mem_imem_exc__29_85_AND_IF_imem_c_rg__ETC___d755 ;
  assign stage2_rg_full_0_AND_NOT_stage2_rg_stage2_1_BI_ETC___d758 =
	     (stage2_rg_full_0_AND_NOT_stage2_rg_stage2_1_BI_ETC___d511 ||
	      near_mem$imem_exc ||
	      IF_IF_imem_c_rg_pc_BITS_1_TO_0_EQ_0b0_OR_NOT_i_ETC___d669) &&
	     stage2_rg_full_0_AND_NOT_stage2_rg_stage2_1_BI_ETC___d757 ;
  assign stage2_rg_full_0_AND_NOT_stage2_rg_stage2_1_BI_ETC___d771 =
	     (stage2_rg_full_0_AND_NOT_stage2_rg_stage2_1_BI_ETC___d511 ||
	      near_mem$imem_exc ||
	      IF_IF_imem_c_rg_pc_BITS_1_TO_0_EQ_0b0_OR_NOT_i_ETC___d680) &&
	     NOT_stage2_rg_full_0_41_OR_stage2_rg_stage2_1__ETC___d735 &&
	     NOT_stage2_rg_full_0_41_OR_stage2_rg_stage2_1__ETC___d736 &&
	     NOT_near_mem_imem_exc__29_85_AND_IF_imem_c_rg__ETC___d769 ;
  assign stage2_rg_full_0_AND_NOT_stage2_rg_stage2_1_BI_ETC___d772 =
	     (stage2_rg_full_0_AND_NOT_stage2_rg_stage2_1_BI_ETC___d511 ||
	      near_mem$imem_exc ||
	      IF_IF_imem_c_rg_pc_BITS_1_TO_0_EQ_0b0_OR_NOT_i_ETC___d669) &&
	     stage2_rg_full_0_AND_NOT_stage2_rg_stage2_1_BI_ETC___d771 ;
  assign stage2_rg_full_0_AND_NOT_stage2_rg_stage2_1_BI_ETC___d780 =
	     (stage2_rg_full_0_AND_NOT_stage2_rg_stage2_1_BI_ETC___d511 ||
	      near_mem$imem_exc ||
	      IF_IF_imem_c_rg_pc_BITS_1_TO_0_EQ_0b0_OR_NOT_i_ETC___d680) &&
	     NOT_stage2_rg_full_0_41_OR_stage2_rg_stage2_1__ETC___d735 &&
	     NOT_stage2_rg_full_0_41_OR_stage2_rg_stage2_1__ETC___d736 &&
	     !near_mem$imem_exc &&
	     _theResult____h4859[6:0] == 7'b0001111 &&
	     _theResult____h4859[14:12] == 3'b0 ;
  assign stage2_rg_full_0_AND_NOT_stage2_rg_stage2_1_BI_ETC___d781 =
	     (stage2_rg_full_0_AND_NOT_stage2_rg_stage2_1_BI_ETC___d511 ||
	      near_mem$imem_exc ||
	      IF_IF_imem_c_rg_pc_BITS_1_TO_0_EQ_0b0_OR_NOT_i_ETC___d669) &&
	     stage2_rg_full_0_AND_NOT_stage2_rg_stage2_1_BI_ETC___d780 ;
  assign stage2_rg_full_0_AND_NOT_stage2_rg_stage2_1_BI_ETC___d788 =
	     (stage2_rg_full_0_AND_NOT_stage2_rg_stage2_1_BI_ETC___d511 ||
	      near_mem$imem_exc ||
	      IF_IF_imem_c_rg_pc_BITS_1_TO_0_EQ_0b0_OR_NOT_i_ETC___d680) &&
	     NOT_stage2_rg_full_0_41_OR_stage2_rg_stage2_1__ETC___d735 &&
	     NOT_stage2_rg_full_0_41_OR_stage2_rg_stage2_1__ETC___d736 &&
	     !near_mem$imem_exc &&
	     _theResult____h4859[6:0] == 7'b0001111 &&
	     _theResult____h4859[14:12] == 3'b001 ;
  assign stage2_rg_full_0_AND_NOT_stage2_rg_stage2_1_BI_ETC___d789 =
	     (stage2_rg_full_0_AND_NOT_stage2_rg_stage2_1_BI_ETC___d511 ||
	      near_mem$imem_exc ||
	      IF_IF_imem_c_rg_pc_BITS_1_TO_0_EQ_0b0_OR_NOT_i_ETC___d669) &&
	     stage2_rg_full_0_AND_NOT_stage2_rg_stage2_1_BI_ETC___d788 ;
  assign stage2_rg_full_0_AND_NOT_stage2_rg_stage2_1_BI_ETC___d806 =
	     (stage2_rg_full_0_AND_NOT_stage2_rg_stage2_1_BI_ETC___d511 ||
	      near_mem$imem_exc ||
	      IF_IF_imem_c_rg_pc_BITS_1_TO_0_EQ_0b0_OR_NOT_i_ETC___d669) &&
	     (stage2_rg_full_0_AND_NOT_stage2_rg_stage2_1_BI_ETC___d511 ||
	      near_mem$imem_exc ||
	      IF_IF_imem_c_rg_pc_BITS_1_TO_0_EQ_0b0_OR_NOT_i_ETC___d680) &&
	     NOT_stage2_rg_full_0_41_OR_stage2_rg_stage2_1__ETC___d804 ;
  assign stage2_rg_full_0_AND_NOT_stage2_rg_stage2_1_BI_ETC___d826 =
	     (stage2_rg_full_0_AND_NOT_stage2_rg_stage2_1_BI_ETC___d511 ||
	      near_mem$imem_exc ||
	      IF_IF_imem_c_rg_pc_BITS_1_TO_0_EQ_0b0_OR_NOT_i_ETC___d669) &&
	     (stage2_rg_full_0_AND_NOT_stage2_rg_stage2_1_BI_ETC___d511 ||
	      near_mem$imem_exc ||
	      IF_IF_imem_c_rg_pc_BITS_1_TO_0_EQ_0b0_OR_NOT_i_ETC___d680) &&
	     NOT_stage2_rg_full_0_41_OR_stage2_rg_stage2_1__ETC___d824 ;
  assign stage2_rg_full_0_AND_NOT_stage2_rg_stage2_1_BI_ETC___d860 =
	     stage2_rg_full_0_AND_NOT_stage2_rg_stage2_1_BI_ETC___d511 ||
	     near_mem$imem_exc ||
	     _theResult____h4859[6:0] != 7'b1110011 ||
	     _theResult____h4859[14:12] != 3'b0 ||
	     _theResult____h4859[11:7] != 5'd0 ||
	     _theResult____h4859[19:15] != 5'd0 ||
	     rg_cur_priv != 2'b11 ||
	     _theResult____h4859[31:20] != 12'b001100000010 ;
  assign stage2_rg_full_0_AND_NOT_stage2_rg_stage2_1_BI_ETC___d874 =
	     stage2_rg_full_0_AND_NOT_stage2_rg_stage2_1_BI_ETC___d511 ||
	     near_mem$imem_exc ||
	     _theResult____h4859[6:0] != 7'b1110011 ||
	     _theResult____h4859[14:12] != 3'b0 ||
	     _theResult____h4859[11:7] != 5'd0 ||
	     _theResult____h4859[19:15] != 5'd0 ||
	     NOT_rg_cur_priv_6_EQ_0b11_96_53_AND_NOT_rg_cur_ETC___d869 ;
  assign stage2_rg_full_0_AND_NOT_stage2_rg_stage2_1_BI_ETC___d877 =
	     (stage2_rg_full_0_AND_NOT_stage2_rg_stage2_1_BI_ETC___d511 ||
	      near_mem$imem_exc ||
	      _theResult____h4859[6:0] != 7'b0001111 ||
	      _theResult____h4859[14:12] != 3'b0) &&
	     (stage2_rg_full_0_AND_NOT_stage2_rg_stage2_1_BI_ETC___d511 ||
	      near_mem$imem_exc ||
	      _theResult____h4859[6:0] != 7'b0001111 ||
	      _theResult____h4859[14:12] != 3'b001) &&
	     stage2_rg_full_0_AND_NOT_stage2_rg_stage2_1_BI_ETC___d860 &&
	     stage2_rg_full_0_AND_NOT_stage2_rg_stage2_1_BI_ETC___d874 ;
  assign stage2_rg_full_0_AND_NOT_stage2_rg_stage2_1_BI_ETC___d879 =
	     (stage2_rg_full_0_AND_NOT_stage2_rg_stage2_1_BI_ETC___d511 ||
	      near_mem$imem_exc ||
	      _theResult____h4859[6:0] != 7'b1110011 ||
	      _theResult____h4859[14:12] != 3'b001 &&
	      _theResult____h4859[14:12] != 3'b101) &&
	     (stage2_rg_full_0_AND_NOT_stage2_rg_stage2_1_BI_ETC___d511 ||
	      near_mem$imem_exc ||
	      _theResult____h4859[6:0] != 7'b1110011 ||
	      _theResult____h4859[14:12] != 3'b010 &&
	      _theResult____h4859[14:12] != 3'b110 &&
	      _theResult____h4859[14:12] != 3'b011 &&
	      _theResult____h4859[14:12] != 3'b111) &&
	     stage2_rg_full_0_AND_NOT_stage2_rg_stage2_1_BI_ETC___d877 ;
  assign stage2_rg_full_0_AND_NOT_stage2_rg_stage2_1_BI_ETC___d881 =
	     (stage2_rg_full_0_AND_NOT_stage2_rg_stage2_1_BI_ETC___d511 ||
	      near_mem$imem_exc ||
	      IF_IF_imem_c_rg_pc_BITS_1_TO_0_EQ_0b0_OR_NOT_i_ETC___d669) &&
	     (stage2_rg_full_0_AND_NOT_stage2_rg_stage2_1_BI_ETC___d511 ||
	      near_mem$imem_exc ||
	      IF_IF_imem_c_rg_pc_BITS_1_TO_0_EQ_0b0_OR_NOT_i_ETC___d680) &&
	     stage2_rg_full_0_AND_NOT_stage2_rg_stage2_1_BI_ETC___d879 ;
  assign stage2_rg_full_0_AND_NOT_stage2_rg_stage2_1_BI_ETC___d914 =
	     stage2_rg_full_0_AND_NOT_stage2_rg_stage2_1_BI_ETC___d511 ||
	     _theResult____h4859[6:0] != 7'b1100011 &&
	     _theResult____h4859[6:0] != 7'b1101111 &&
	     _theResult____h4859[6:0] != 7'b1100111 &&
	     (_theResult____h4859[6:0] == 7'b0110011 &&
	      _theResult____h4859[31:25] == 7'b0000001 ||
	      _theResult____h4859[6:0] != 7'b0010011 &&
	      _theResult____h4859[6:0] != 7'b0110011 &&
	      _theResult____h4859[6:0] != 7'b0110111 &&
	      _theResult____h4859[6:0] != 7'b0010111) ;
  assign stage2_rg_full_0_AND_NOT_stage2_rg_stage2_1_BI_ETC___d921 =
	     (stage2_rg_full_0_AND_NOT_stage2_rg_stage2_1_BI_ETC___d511 ||
	      _theResult____h4859[6:0] != 7'b0000011) &&
	     (stage2_rg_full_0_AND_NOT_stage2_rg_stage2_1_BI_ETC___d511 ||
	      _theResult____h4859[6:0] != 7'b0100011) &&
	     (stage2_rg_full_0_AND_NOT_stage2_rg_stage2_1_BI_ETC___d511 ||
	      _theResult____h4859[6:0] != 7'b0110011 ||
	      _theResult____h4859[31:25] != 7'b0000001) ;
  assign stage2_rg_full_0_AND_stage2_rg_stage2_1_BITS_1_ETC___d1202 =
	     stage2_rg_full &&
	     (stage2_rg_stage2[103:101] == 3'd0 ||
	      IF_stage2_rg_stage2_1_BITS_103_TO_101_2_EQ_1_4_ETC___d1196) &&
	     NOT_IF_csr_regfile_read_csr_minstret__8_ULT_cf_ETC___d44 ;
  assign stage2_rg_full_0_AND_stage2_rg_stage2_1_BITS_1_ETC___d1207 =
	     stage2_rg_full &&
	     (stage2_rg_stage2[103:101] == 3'd0 ||
	      IF_stage2_rg_stage2_1_BITS_103_TO_101_2_EQ_1_4_ETC___d1196) &&
	     NOT_IF_csr_regfile_read_csr_minstret__8_ULT_cf_ETC___d44 &&
	     (stage2_rg_stage2[103:101] == 3'd0 ||
	      IF_stage2_rg_stage2_1_BITS_103_TO_101_2_EQ_1_4_ETC___d152) ;
  assign stage2_rg_full_0_AND_stage2_rg_stage2_1_BITS_1_ETC___d140 =
	     stage2_rg_full &&
	     (stage2_rg_stage2[103:101] == 3'd0 ||
	      IF_stage2_rg_stage2_1_BITS_103_TO_101_2_EQ_1_4_ETC___d122) &&
	     stage2_rg_stage2_1_BITS_103_TO_101_2_EQ_0_3_OR_ETC___d138 ;
  assign stage2_rg_full_0_AND_stage2_rg_stage2_1_BITS_1_ETC___d554 =
	     stage2_rg_full &&
	     (stage2_rg_stage2[103:101] == 3'd0 ||
	      stage2_rg_stage2[103:101] != 3'd1 &&
	      stage2_rg_stage2[103:101] != 3'd4 &&
	      stage2_rg_stage2[103:101] != 3'd2 &&
	      stage2_mbox$valid) ;
  assign stage2_rg_stage2_1_BITS_103_TO_101_2_EQ_0_3_OR_ETC___d138 =
	     stage2_rg_stage2[103:101] != 3'd1 &&
	     stage2_rg_stage2[103:101] != 3'd4 &&
	     stage2_rg_stage2[103:101] != 3'd2 ||
	     !near_mem$dmem_valid ||
	     !near_mem$dmem_exc ;
  assign stage3_rg_full_1_OR_NOT_stage2_rg_full_0_41_OR_ETC___d1181 =
	     (stage3_rg_full || !stage2_rg_full ||
	      stage2_rg_stage2_1_BITS_103_TO_101_2_EQ_0_3_OR_ETC___d138) &&
	     (stage3_rg_full || stage2_rg_full || !stage1_rg_full ||
	      NOT_near_mem_imem_valid_08_OR_imem_c_rg_pc_BIT_ETC___d1178) ;
  assign theResult__859_BITS_31_TO_20__q11 = _theResult____h4859[31:20] ;
  assign theResult__859_BITS_31_TO_25_CONCAT_theResult__ETC__q6 =
	     { _theResult____h4859[31:25], _theResult____h4859[11:7] } ;
  assign theResult__859_BIT_31_CONCAT_theResult__859_BI_ETC__q2 =
	     { _theResult____h4859[31],
	       _theResult____h4859[7],
	       _theResult____h4859[30:25],
	       _theResult____h4859[11:8],
	       1'b0 } ;
  assign theResult__859_BIT_31_CONCAT_theResult__859_BI_ETC__q3 =
	     { _theResult____h4859[31],
	       _theResult____h4859[19:12],
	       _theResult____h4859[20],
	       _theResult____h4859[30:21],
	       1'b0 } ;
  assign trap_info_tval__h14518 =
	     (_theResult____h4859[6:0] != 7'b1101111 &&
	      _theResult____h4859[6:0] != 7'b1100111 &&
	      (_theResult____h4859[6:0] != 7'b1110011 ||
	       _theResult____h4859[14:12] != 3'b0 ||
	       _theResult____h4859[11:7] != 5'd0 ||
	       _theResult____h4859[19:15] != 5'd0 ||
	       _theResult____h4859[31:20] != 12'b0 &&
	       _theResult____h4859[31:20] != 12'b000000000001)) ?
	       (NOT_imem_c_rg_pc_BITS_1_TO_0_EQ_0b0_AND_imem_c_ETC___d519 ?
		  _theResult____h4859 :
		  { 16'd0, instr__h4857[15:0] }) :
	       IF_IF_imem_c_rg_pc_BITS_1_TO_0_EQ_0b0_OR_NOT_i_ETC___d1085 ;
  assign val__h12674 =
	     (stage2_rg_full_0_AND_stage2_rg_stage2_1_BITS_1_ETC___d554 &&
	      IF_stage2_rg_full_0_THEN_IF_stage2_rg_stage2_1_ETC___d509) ?
	       x_out_bypass_rd_val__h7055 :
	       rd_val__h12672 ;
  assign val__h7208 =
	     (stage2_rg_full_0_AND_stage2_rg_stage2_1_BITS_1_ETC___d554 &&
	      IF_stage2_rg_full_0_THEN_IF_stage2_rg_stage2_1_ETC___d507) ?
	       x_out_bypass_rd_val__h7055 :
	       rd_val__h7206 ;
  assign value__h14581 =
	     near_mem$imem_exc ? imem_c_rg_tval : trap_info_tval__h14518 ;
  assign x__h20141 =
	     csr_regfile_read_csr_mcycle__5_MINUS_rg_start__ETC___d1374[63:0] /
	     _theResult____h20140 ;
  assign x_exc_code__h27688 =
	     (csr_regfile$interrupt_pending[4] && !csr_regfile$nmi_pending) ?
	       csr_regfile$interrupt_pending[3:0] :
	       4'd0 ;
  assign x_out_data_to_stage2_instr__h12924 =
	     imem_c_rg_pc_BITS_1_TO_0_EQ_0b0_OR_NOT_imem_c__ETC___d235 ?
	       instr___1__h7261 :
	       instr__h4857 ;
  assign x_out_data_to_stage2_rd__h12926 =
	     (_theResult____h4859[6:0] == 7'b1100011) ?
	       5'd0 :
	       _theResult____h4859[11:7] ;
  assign x_out_data_to_stage2_val2__h12929 =
	     (_theResult____h4859[6:0] == 7'b1100011) ?
	       branch_target__h13080 :
	       rs2_val_bypassed__h4873 ;
  assign x_out_next_pc__h12736 =
	     IF_IF_imem_c_rg_pc_BITS_1_TO_0_EQ_0b0_OR_NOT_i_ETC___d729 ?
	       data_to_stage2_addr__h12919 :
	       fall_through_pc__h12722 ;
  assign x_out_trap_info_exc_code__h14521 =
	     near_mem$imem_exc ?
	       near_mem$imem_exc_code :
	       alu_outputs_exc_code__h13589 ;
  assign y__h21701 = ~rs1_val__h21423 ;
  always@(stage2_rg_stage2)
  begin
    case (stage2_rg_stage2[103:101])
      3'd0, 3'd1, 3'd4:
	  x_out_data_to_stage3_rd__h6401 = stage2_rg_stage2[100:96];
      3'd2: x_out_data_to_stage3_rd__h6401 = 5'd0;
      default: x_out_data_to_stage3_rd__h6401 = stage2_rg_stage2[100:96];
    endcase
  end
  always@(stage2_rg_stage2 or stage2_mbox$word or near_mem$dmem_word64)
  begin
    case (stage2_rg_stage2[103:101])
      3'd0, 3'd2:
	  x_out_data_to_stage3_rd_val__h6402 = stage2_rg_stage2[63:32];
      3'd1, 3'd4:
	  x_out_data_to_stage3_rd_val__h6402 = near_mem$dmem_word64[31:0];
      default: x_out_data_to_stage3_rd_val__h6402 = stage2_mbox$word;
    endcase
  end
  always@(stage2_rg_stage2)
  begin
    case (stage2_rg_stage2[103:101])
      3'd0, 3'd1, 3'd4: x_out_bypass_rd__h7054 = stage2_rg_stage2[100:96];
      default: x_out_bypass_rd__h7054 = stage2_rg_stage2[100:96];
    endcase
  end
  always@(stage2_rg_stage2 or stage2_mbox$word)
  begin
    case (stage2_rg_stage2[103:101])
      3'd0, 3'd1, 3'd4: x_out_bypass_rd_val__h7055 = stage2_rg_stage2[63:32];
      default: x_out_bypass_rd_val__h7055 = stage2_mbox$word;
    endcase
  end
  always@(rg_trap_instr or rg_csr_val1)
  begin
    case (rg_trap_instr[14:12])
      3'b010, 3'b011: rs1_val__h21423 = rg_csr_val1;
      default: rs1_val__h21423 = { 27'd0, rg_trap_instr[19:15] };
    endcase
  end
  always@(stage2_rg_stage2 or stage2_mbox$valid or near_mem$dmem_valid)
  begin
    case (stage2_rg_stage2[103:101])
      3'd1, 3'd2, 3'd4:
	  IF_stage2_rg_stage2_1_BITS_103_TO_101_2_EQ_1_4_ETC___d122 =
	      near_mem$dmem_valid;
      default: IF_stage2_rg_stage2_1_BITS_103_TO_101_2_EQ_1_4_ETC___d122 =
		   stage2_mbox$valid;
    endcase
  end
  always@(stage2_rg_stage2 or
	  stage2_mbox$valid or near_mem$dmem_valid or near_mem$dmem_exc)
  begin
    case (stage2_rg_stage2[103:101])
      3'd1, 3'd2, 3'd4:
	  IF_stage2_rg_stage2_1_BITS_103_TO_101_2_EQ_1_4_ETC___d144 =
	      !near_mem$dmem_valid || near_mem$dmem_exc;
      default: IF_stage2_rg_stage2_1_BITS_103_TO_101_2_EQ_1_4_ETC___d144 =
		   stage2_rg_stage2[103:101] == 3'd3 && !stage2_mbox$valid;
    endcase
  end
  always@(stage2_rg_stage2 or
	  stage2_mbox$valid or near_mem$dmem_valid or near_mem$dmem_exc)
  begin
    case (stage2_rg_stage2[103:101])
      3'd1, 3'd2, 3'd4:
	  IF_stage2_rg_stage2_1_BITS_103_TO_101_2_EQ_1_4_ETC___d152 =
	      near_mem$dmem_valid && !near_mem$dmem_exc;
      default: IF_stage2_rg_stage2_1_BITS_103_TO_101_2_EQ_1_4_ETC___d152 =
		   stage2_rg_stage2[103:101] != 3'd3 || stage2_mbox$valid;
    endcase
  end
  always@(stage2_rg_stage2 or near_mem$dmem_valid or near_mem$dmem_exc)
  begin
    case (stage2_rg_stage2[103:101])
      3'd1, 3'd4:
	  IF_stage2_rg_stage2_1_BITS_103_TO_101_2_EQ_1_4_ETC___d183 =
	      near_mem$dmem_valid && near_mem$dmem_exc ||
	      stage2_rg_stage2[100:96] == 5'd0;
      default: IF_stage2_rg_stage2_1_BITS_103_TO_101_2_EQ_1_4_ETC___d183 =
		   stage2_rg_stage2[103:101] == 3'd2;
    endcase
  end
  always@(stage2_rg_stage2 or near_mem$dmem_valid or near_mem$dmem_exc)
  begin
    case (stage2_rg_stage2[103:101])
      3'd1, 3'd4:
	  IF_stage2_rg_stage2_1_BITS_103_TO_101_2_EQ_1_4_ETC___d188 =
	      (!near_mem$dmem_valid || !near_mem$dmem_exc) &&
	      stage2_rg_stage2[100:96] != 5'd0;
      default: IF_stage2_rg_stage2_1_BITS_103_TO_101_2_EQ_1_4_ETC___d188 =
		   stage2_rg_stage2[103:101] != 3'd2;
    endcase
  end
  always@(stage2_rg_stage2 or
	  stage2_mbox$valid or near_mem$dmem_valid or near_mem$dmem_exc)
  begin
    case (stage2_rg_stage2[103:101])
      3'd1, 3'd4:
	  IF_stage2_rg_stage2_1_BITS_103_TO_101_2_EQ_1_4_ETC___d196 =
	      (!near_mem$dmem_valid || !near_mem$dmem_exc) &&
	      stage2_rg_stage2[100:96] != 5'd0;
      default: IF_stage2_rg_stage2_1_BITS_103_TO_101_2_EQ_1_4_ETC___d196 =
		   stage2_rg_stage2[103:101] != 3'd2 && !stage2_mbox$valid;
    endcase
  end
  always@(stage2_rg_stage2 or
	  stage2_mbox$valid or near_mem$dmem_valid or near_mem$dmem_exc)
  begin
    case (stage2_rg_stage2[103:101])
      3'd1, 3'd4:
	  IF_stage2_rg_stage2_1_BITS_103_TO_101_2_EQ_1_4_ETC___d200 =
	      near_mem$dmem_valid && near_mem$dmem_exc ||
	      stage2_rg_stage2[100:96] == 5'd0;
      default: IF_stage2_rg_stage2_1_BITS_103_TO_101_2_EQ_1_4_ETC___d200 =
		   stage2_rg_stage2[103:101] == 3'd2 || stage2_mbox$valid;
    endcase
  end
  always@(rg_cur_priv)
  begin
    case (rg_cur_priv)
      2'b0: CASE_rg_cur_priv_0b0_8_0b1_9_11__q4 = 4'd8;
      2'b01: CASE_rg_cur_priv_0b0_8_0b1_9_11__q4 = 4'd9;
      default: CASE_rg_cur_priv_0b0_8_0b1_9_11__q4 = 4'd11;
    endcase
  end
  always@(_theResult____h4859 or CASE_rg_cur_priv_0b0_8_0b1_9_11__q4)
  begin
    case (_theResult____h4859[31:20])
      12'b0:
	  CASE_theResult__859_BITS_31_TO_20_0b0_CASE_rg__ETC__q5 =
	      CASE_rg_cur_priv_0b0_8_0b1_9_11__q4;
      12'b000000000001:
	  CASE_theResult__859_BITS_31_TO_20_0b0_CASE_rg__ETC__q5 = 4'd3;
      default: CASE_theResult__859_BITS_31_TO_20_0b0_CASE_rg__ETC__q5 = 4'd2;
    endcase
  end
  always@(_theResult____h4859 or alu_outputs___1_exc_code__h13548)
  begin
    case (_theResult____h4859[6:0])
      7'b0000011,
      7'b0001111,
      7'b0010011,
      7'b0010111,
      7'b0100011,
      7'b0110011,
      7'b0110111,
      7'b1100011:
	  alu_outputs_exc_code__h13589 = 4'd2;
      7'b1100111, 7'b1101111: alu_outputs_exc_code__h13589 = 4'd0;
      7'b1110011:
	  alu_outputs_exc_code__h13589 = alu_outputs___1_exc_code__h13548;
      default: alu_outputs_exc_code__h13589 = 4'd2;
    endcase
  end
  always@(_theResult____h4859 or
	  IF_IF_imem_c_rg_pc_BITS_1_TO_0_EQ_0b0_OR_NOT_i_ETC___d574 or
	  IF_IF_imem_c_rg_pc_BITS_1_TO_0_EQ_0b0_OR_NOT_i_ETC___d570 or
	  IF_IF_imem_c_rg_pc_BITS_1_TO_0_EQ_0b0_OR_NOT_i_ETC___d572)
  begin
    case (_theResult____h4859[14:12])
      3'b0:
	  IF_IF_imem_c_rg_pc_BITS_1_TO_0_EQ_0b0_OR_NOT_i_ETC___d675 =
	      !IF_IF_imem_c_rg_pc_BITS_1_TO_0_EQ_0b0_OR_NOT_i_ETC___d570;
      3'b001:
	  IF_IF_imem_c_rg_pc_BITS_1_TO_0_EQ_0b0_OR_NOT_i_ETC___d675 =
	      IF_IF_imem_c_rg_pc_BITS_1_TO_0_EQ_0b0_OR_NOT_i_ETC___d570;
      3'b100:
	  IF_IF_imem_c_rg_pc_BITS_1_TO_0_EQ_0b0_OR_NOT_i_ETC___d675 =
	      !IF_IF_imem_c_rg_pc_BITS_1_TO_0_EQ_0b0_OR_NOT_i_ETC___d572;
      3'b101:
	  IF_IF_imem_c_rg_pc_BITS_1_TO_0_EQ_0b0_OR_NOT_i_ETC___d675 =
	      IF_IF_imem_c_rg_pc_BITS_1_TO_0_EQ_0b0_OR_NOT_i_ETC___d572;
      3'b110:
	  IF_IF_imem_c_rg_pc_BITS_1_TO_0_EQ_0b0_OR_NOT_i_ETC___d675 =
	      !IF_IF_imem_c_rg_pc_BITS_1_TO_0_EQ_0b0_OR_NOT_i_ETC___d574;
      default: IF_IF_imem_c_rg_pc_BITS_1_TO_0_EQ_0b0_OR_NOT_i_ETC___d675 =
		   _theResult____h4859[14:12] != 3'b111 ||
		   IF_IF_imem_c_rg_pc_BITS_1_TO_0_EQ_0b0_OR_NOT_i_ETC___d574;
    endcase
  end
  always@(_theResult____h4859 or
	  IF_IF_imem_c_rg_pc_BITS_1_TO_0_EQ_0b0_OR_NOT_i_ETC___d574 or
	  IF_IF_imem_c_rg_pc_BITS_1_TO_0_EQ_0b0_OR_NOT_i_ETC___d570 or
	  IF_IF_imem_c_rg_pc_BITS_1_TO_0_EQ_0b0_OR_NOT_i_ETC___d572)
  begin
    case (_theResult____h4859[14:12])
      3'b0:
	  IF_IF_imem_c_rg_pc_BITS_1_TO_0_EQ_0b0_OR_NOT_i_ETC___d581 =
	      IF_IF_imem_c_rg_pc_BITS_1_TO_0_EQ_0b0_OR_NOT_i_ETC___d570;
      3'b001:
	  IF_IF_imem_c_rg_pc_BITS_1_TO_0_EQ_0b0_OR_NOT_i_ETC___d581 =
	      !IF_IF_imem_c_rg_pc_BITS_1_TO_0_EQ_0b0_OR_NOT_i_ETC___d570;
      3'b100:
	  IF_IF_imem_c_rg_pc_BITS_1_TO_0_EQ_0b0_OR_NOT_i_ETC___d581 =
	      IF_IF_imem_c_rg_pc_BITS_1_TO_0_EQ_0b0_OR_NOT_i_ETC___d572;
      3'b101:
	  IF_IF_imem_c_rg_pc_BITS_1_TO_0_EQ_0b0_OR_NOT_i_ETC___d581 =
	      !IF_IF_imem_c_rg_pc_BITS_1_TO_0_EQ_0b0_OR_NOT_i_ETC___d572;
      3'b110:
	  IF_IF_imem_c_rg_pc_BITS_1_TO_0_EQ_0b0_OR_NOT_i_ETC___d581 =
	      IF_IF_imem_c_rg_pc_BITS_1_TO_0_EQ_0b0_OR_NOT_i_ETC___d574;
      default: IF_IF_imem_c_rg_pc_BITS_1_TO_0_EQ_0b0_OR_NOT_i_ETC___d581 =
		   _theResult____h4859[14:12] == 3'b111 &&
		   !IF_IF_imem_c_rg_pc_BITS_1_TO_0_EQ_0b0_OR_NOT_i_ETC___d574;
    endcase
  end
  always@(_theResult____h4859 or
	  NOT_IF_imem_c_rg_pc_BITS_1_TO_0_EQ_0b0_OR_NOT__ETC___d661)
  begin
    case (_theResult____h4859[6:0])
      7'b0000011:
	  CASE_theResult__859_BITS_6_TO_0_0b11_NOT_theRe_ETC__q7 =
	      _theResult____h4859[14:12] != 3'b0 &&
	      _theResult____h4859[14:12] != 3'b100 &&
	      _theResult____h4859[14:12] != 3'b001 &&
	      _theResult____h4859[14:12] != 3'b101 &&
	      _theResult____h4859[14:12] != 3'b010;
      7'b0100011:
	  CASE_theResult__859_BITS_6_TO_0_0b11_NOT_theRe_ETC__q7 =
	      _theResult____h4859[14:12] != 3'b0 &&
	      _theResult____h4859[14:12] != 3'b001 &&
	      _theResult____h4859[14:12] != 3'b010;
      default: CASE_theResult__859_BITS_6_TO_0_0b11_NOT_theRe_ETC__q7 =
		   NOT_IF_imem_c_rg_pc_BITS_1_TO_0_EQ_0b0_OR_NOT__ETC___d661;
    endcase
  end
  always@(_theResult____h4859 or
	  CASE_theResult__859_BITS_6_TO_0_0b11_NOT_theRe_ETC__q7 or
	  NOT_IF_imem_c_rg_pc_BITS_1_TO_0_EQ_0b0_OR_NOT__ETC___d611)
  begin
    case (_theResult____h4859[6:0])
      7'b0010011, 7'b0110011:
	  CASE_theResult__859_BITS_6_TO_0_0b10011_NOT_IF_ETC__q8 =
	      NOT_IF_imem_c_rg_pc_BITS_1_TO_0_EQ_0b0_OR_NOT__ETC___d611;
      default: CASE_theResult__859_BITS_6_TO_0_0b10011_NOT_IF_ETC__q8 =
		   _theResult____h4859[6:0] != 7'b0110111 &&
		   _theResult____h4859[6:0] != 7'b0010111 &&
		   CASE_theResult__859_BITS_6_TO_0_0b11_NOT_theRe_ETC__q7;
    endcase
  end
  always@(_theResult____h4859)
  begin
    case (_theResult____h4859[6:0])
      7'b0000011:
	  CASE_theResult__859_BITS_6_TO_0_0b11_theResult_ETC__q9 =
	      _theResult____h4859[14:12] == 3'b0 ||
	      _theResult____h4859[14:12] == 3'b100 ||
	      _theResult____h4859[14:12] == 3'b001 ||
	      _theResult____h4859[14:12] == 3'b101 ||
	      _theResult____h4859[14:12] == 3'b010;
      7'b0100011:
	  CASE_theResult__859_BITS_6_TO_0_0b11_theResult_ETC__q9 =
	      _theResult____h4859[14:12] == 3'b0 ||
	      _theResult____h4859[14:12] == 3'b001 ||
	      _theResult____h4859[14:12] == 3'b010;
      default: CASE_theResult__859_BITS_6_TO_0_0b11_theResult_ETC__q9 =
		   _theResult____h4859[6:0] == 7'b0101111 &&
		   (_theResult____h4859[31:27] == 5'b00010 ||
		    _theResult____h4859[31:27] == 5'b00011 ||
		    _theResult____h4859[31:27] == 5'b0 ||
		    _theResult____h4859[31:27] == 5'b00001 ||
		    _theResult____h4859[31:27] == 5'b01100 ||
		    _theResult____h4859[31:27] == 5'b01000 ||
		    _theResult____h4859[31:27] == 5'b00100 ||
		    _theResult____h4859[31:27] == 5'b10000 ||
		    _theResult____h4859[31:27] == 5'b11000 ||
		    _theResult____h4859[31:27] == 5'b10100 ||
		    _theResult____h4859[31:27] == 5'b11100) &&
		   _theResult____h4859[14:12] == 3'b010;
    endcase
  end
  always@(_theResult____h4859 or
	  CASE_theResult__859_BITS_6_TO_0_0b11_theResult_ETC__q9 or
	  IF_imem_c_rg_pc_BITS_1_TO_0_EQ_0b0_OR_NOT_imem_ETC___d700)
  begin
    case (_theResult____h4859[6:0])
      7'b0010011, 7'b0110011:
	  CASE_theResult__859_BITS_6_TO_0_0b10011_IF_ime_ETC__q10 =
	      IF_imem_c_rg_pc_BITS_1_TO_0_EQ_0b0_OR_NOT_imem_ETC___d700;
      default: CASE_theResult__859_BITS_6_TO_0_0b10011_IF_ime_ETC__q10 =
		   _theResult____h4859[6:0] == 7'b0110111 ||
		   _theResult____h4859[6:0] == 7'b0010111 ||
		   CASE_theResult__859_BITS_6_TO_0_0b11_theResult_ETC__q9;
    endcase
  end
  always@(_theResult____h4859 or
	  _theResult_____1_fst__h14056 or
	  rd_val___1__h14024 or
	  rd_val___1__h14031 or rd_val___1__h14038 or rd_val___1__h14045)
  begin
    case (_theResult____h4859[14:12])
      3'b010: _theResult_____1_fst__h14028 = rd_val___1__h14024;
      3'b011: _theResult_____1_fst__h14028 = rd_val___1__h14031;
      3'b100: _theResult_____1_fst__h14028 = rd_val___1__h14038;
      3'b110: _theResult_____1_fst__h14028 = rd_val___1__h14045;
      default: _theResult_____1_fst__h14028 = _theResult_____1_fst__h14056;
    endcase
  end
  always@(_theResult____h4859 or
	  rs1_val_bypassed__h4867 or
	  eaddr__h13323 or
	  alu_outputs___1_addr__h13353 or
	  alu_outputs___1_addr__h13103 or
	  alu_outputs___1_addr__h13150 or alu_outputs___1_addr__h13124)
  begin
    case (_theResult____h4859[6:0])
      7'b0000011: x_out_data_to_stage2_addr__h12927 = eaddr__h13323;
      7'b0100011:
	  x_out_data_to_stage2_addr__h12927 = alu_outputs___1_addr__h13353;
      7'b1100011:
	  x_out_data_to_stage2_addr__h12927 = alu_outputs___1_addr__h13103;
      7'b1100111:
	  x_out_data_to_stage2_addr__h12927 = alu_outputs___1_addr__h13150;
      7'b1101111:
	  x_out_data_to_stage2_addr__h12927 = alu_outputs___1_addr__h13124;
      default: x_out_data_to_stage2_addr__h12927 = rs1_val_bypassed__h4867;
    endcase
  end
  always@(_theResult____h4859 or imem_c_rg_pc or data_to_stage2_addr__h12919)
  begin
    case (_theResult____h4859[6:0])
      7'b1100111, 7'b1101111:
	  IF_IF_imem_c_rg_pc_BITS_1_TO_0_EQ_0b0_OR_NOT_i_ETC___d1085 =
	      data_to_stage2_addr__h12919;
      default: IF_IF_imem_c_rg_pc_BITS_1_TO_0_EQ_0b0_OR_NOT_i_ETC___d1085 =
		   (_theResult____h4859[6:0] == 7'b1110011 &&
		    _theResult____h4859[14:12] == 3'b0 &&
		    _theResult____h4859[11:7] == 5'd0 &&
		    _theResult____h4859[19:15] == 5'd0 &&
		    _theResult____h4859[31:20] == 12'b000000000001) ?
		     imem_c_rg_pc :
		     32'd0;
    endcase
  end
  always@(stage2_rg_stage2 or
	  stage2_mbox$valid or near_mem$dmem_valid or near_mem$dmem_exc)
  begin
    case (stage2_rg_stage2[103:101])
      3'd1, 3'd2, 3'd4:
	  IF_stage2_rg_stage2_1_BITS_103_TO_101_2_EQ_1_4_ETC___d1159 =
	      !near_mem$dmem_valid || near_mem$dmem_exc;
      default: IF_stage2_rg_stage2_1_BITS_103_TO_101_2_EQ_1_4_ETC___d1159 =
		   !stage2_mbox$valid;
    endcase
  end
  always@(stage2_rg_stage2 or
	  stage2_mbox$valid or near_mem$dmem_valid or near_mem$dmem_exc)
  begin
    case (stage2_rg_stage2[103:101])
      3'd1, 3'd2, 3'd4:
	  IF_stage2_rg_stage2_1_BITS_103_TO_101_2_EQ_1_4_ETC___d1196 =
	      near_mem$dmem_valid && !near_mem$dmem_exc;
      default: IF_stage2_rg_stage2_1_BITS_103_TO_101_2_EQ_1_4_ETC___d1196 =
		   stage2_mbox$valid;
    endcase
  end
  always@(_theResult____h4859 or
	  alu_outputs___1_val1__h13572 or
	  alu_outputs___1_val1__h13286 or
	  rd_val__h13307 or rd_val__h13293 or alu_outputs___1_val1__h13552)
  begin
    case (_theResult____h4859[6:0])
      7'b0010011, 7'b0110011:
	  IF_IF_imem_c_rg_pc_BITS_1_TO_0_EQ_0b0_OR_NOT_i_ETC___d1011 =
	      alu_outputs___1_val1__h13286;
      7'b0010111:
	  IF_IF_imem_c_rg_pc_BITS_1_TO_0_EQ_0b0_OR_NOT_i_ETC___d1011 =
	      rd_val__h13307;
      7'b0110111:
	  IF_IF_imem_c_rg_pc_BITS_1_TO_0_EQ_0b0_OR_NOT_i_ETC___d1011 =
	      rd_val__h13293;
      7'b1110011:
	  IF_IF_imem_c_rg_pc_BITS_1_TO_0_EQ_0b0_OR_NOT_i_ETC___d1011 =
	      alu_outputs___1_val1__h13552;
      default: IF_IF_imem_c_rg_pc_BITS_1_TO_0_EQ_0b0_OR_NOT_i_ETC___d1011 =
		   alu_outputs___1_val1__h13572;
    endcase
  end
  always@(_theResult____h4859 or
	  IF_IF_imem_c_rg_pc_BITS_1_TO_0_EQ_0b0_OR_NOT_i_ETC___d1013 or
	  IF_imem_c_rg_pc_BITS_1_TO_0_EQ_0b0_OR_NOT_imem_ETC___d943)
  begin
    case (_theResult____h4859[6:0])
      7'b1100111, 7'b1101111:
	  x_out_data_to_stage2_val1__h12928 =
	      IF_imem_c_rg_pc_BITS_1_TO_0_EQ_0b0_OR_NOT_imem_ETC___d943;
      default: x_out_data_to_stage2_val1__h12928 =
		   IF_IF_imem_c_rg_pc_BITS_1_TO_0_EQ_0b0_OR_NOT_i_ETC___d1013;
    endcase
  end
  always@(_theResult____h4859 or
	  NOT_IF_imem_c_rg_pc_BITS_1_TO_0_EQ_0b0_OR_NOT__ETC___d661 or
	  IF_IF_imem_c_rg_pc_BITS_1_TO_0_EQ_0b0_OR_NOT_i_ETC___d1340)
  begin
    case (_theResult____h4859[6:0])
      7'b0000011:
	  IF_IF_imem_c_rg_pc_BITS_1_TO_0_EQ_0b0_OR_NOT_i_ETC___d1344 =
	      _theResult____h4859[14:12] != 3'b0 &&
	      _theResult____h4859[14:12] != 3'b100 &&
	      _theResult____h4859[14:12] != 3'b001 &&
	      _theResult____h4859[14:12] != 3'b101 &&
	      _theResult____h4859[14:12] != 3'b010;
      7'b0001111:
	  IF_IF_imem_c_rg_pc_BITS_1_TO_0_EQ_0b0_OR_NOT_i_ETC___d1344 =
	      _theResult____h4859[14:12] != 3'b001 &&
	      _theResult____h4859[14:12] != 3'b0;
      7'b0100011:
	  IF_IF_imem_c_rg_pc_BITS_1_TO_0_EQ_0b0_OR_NOT_i_ETC___d1344 =
	      _theResult____h4859[14:12] != 3'b0 &&
	      _theResult____h4859[14:12] != 3'b001 &&
	      _theResult____h4859[14:12] != 3'b010;
      7'b1110011:
	  IF_IF_imem_c_rg_pc_BITS_1_TO_0_EQ_0b0_OR_NOT_i_ETC___d1344 =
	      IF_IF_imem_c_rg_pc_BITS_1_TO_0_EQ_0b0_OR_NOT_i_ETC___d1340;
      default: IF_IF_imem_c_rg_pc_BITS_1_TO_0_EQ_0b0_OR_NOT_i_ETC___d1344 =
		   NOT_IF_imem_c_rg_pc_BITS_1_TO_0_EQ_0b0_OR_NOT__ETC___d661;
    endcase
  end
  always@(_theResult____h4859 or
	  IF_IF_imem_c_rg_pc_BITS_1_TO_0_EQ_0b0_OR_NOT_i_ETC___d1344 or
	  NOT_IF_imem_c_rg_pc_BITS_1_TO_0_EQ_0b0_OR_NOT__ETC___d611)
  begin
    case (_theResult____h4859[6:0])
      7'b0010011, 7'b0110011:
	  CASE_theResult__859_BITS_6_TO_0_0b10011_NOT_IF_ETC__q12 =
	      NOT_IF_imem_c_rg_pc_BITS_1_TO_0_EQ_0b0_OR_NOT__ETC___d611;
      default: CASE_theResult__859_BITS_6_TO_0_0b10011_NOT_IF_ETC__q12 =
		   _theResult____h4859[6:0] != 7'b0110111 &&
		   _theResult____h4859[6:0] != 7'b0010111 &&
		   IF_IF_imem_c_rg_pc_BITS_1_TO_0_EQ_0b0_OR_NOT_i_ETC___d1344;
    endcase
  end
  always@(_theResult____h4859)
  begin
    case (_theResult____h4859[6:0])
      7'b0000011:
	  CASE_theResult__859_BITS_6_TO_0_0b11_1_0b10011_ETC__q13 = 3'd1;
      7'b0010011, 7'b0010111, 7'b0110011, 7'b0110111:
	  CASE_theResult__859_BITS_6_TO_0_0b11_1_0b10011_ETC__q13 = 3'd0;
      7'b0100011:
	  CASE_theResult__859_BITS_6_TO_0_0b11_1_0b10011_ETC__q13 = 3'd2;
      default: CASE_theResult__859_BITS_6_TO_0_0b11_1_0b10011_ETC__q13 = 3'd4;
    endcase
  end
  always@(_theResult____h4859 or
	  CASE_theResult__859_BITS_6_TO_0_0b11_1_0b10011_ETC__q13)
  begin
    case (_theResult____h4859[6:0])
      7'b1100011, 7'b1100111, 7'b1101111:
	  CASE_theResult__859_BITS_6_TO_0_0b1100011_0_0b_ETC__q14 = 3'd0;
      default: CASE_theResult__859_BITS_6_TO_0_0b1100011_0_0b_ETC__q14 =
		   (_theResult____h4859[6:0] == 7'b0110011 &&
		    _theResult____h4859[31:25] == 7'b0000001) ?
		     3'd3 :
		     CASE_theResult__859_BITS_6_TO_0_0b11_1_0b10011_ETC__q13;
    endcase
  end
  always@(stage2_rg_stage2 or stage2_mbox$valid or near_mem$dmem_valid)
  begin
    case (stage2_rg_stage2[103:101])
      3'd1, 3'd2, 3'd4:
	  CASE_stage2_rg_stage2_BITS_103_TO_101_1_NOT_ne_ETC__q15 =
	      !near_mem$dmem_valid;
      default: CASE_stage2_rg_stage2_BITS_103_TO_101_1_NOT_ne_ETC__q15 =
		   !stage2_mbox$valid;
    endcase
  end

  // handling of inlined registers

  always@(posedge CLK)
  begin
    if (RST_N == `BSV_RESET_VALUE)
      begin
        cfg_logdelay <= `BSV_ASSIGNMENT_DELAY 64'd0;
	cfg_verbosity <= `BSV_ASSIGNMENT_DELAY 4'd0;
	imem_c_rg_cache_addr <= `BSV_ASSIGNMENT_DELAY 32'hFFFFFFFF;
	rg_cur_priv <= `BSV_ASSIGNMENT_DELAY 2'b11;
	rg_run_on_reset <= `BSV_ASSIGNMENT_DELAY 1'd0;
	rg_state <= `BSV_ASSIGNMENT_DELAY 4'd0;
	stage1_rg_full <= `BSV_ASSIGNMENT_DELAY 1'd0;
	stage2_rg_full <= `BSV_ASSIGNMENT_DELAY 1'd0;
	stage2_rg_resetting <= `BSV_ASSIGNMENT_DELAY 1'd0;
	stage3_rg_full <= `BSV_ASSIGNMENT_DELAY 1'd0;
      end
    else
      begin
        if (cfg_logdelay$EN)
	  cfg_logdelay <= `BSV_ASSIGNMENT_DELAY cfg_logdelay$D_IN;
	if (cfg_verbosity$EN)
	  cfg_verbosity <= `BSV_ASSIGNMENT_DELAY cfg_verbosity$D_IN;
	if (imem_c_rg_cache_addr$EN)
	  imem_c_rg_cache_addr <= `BSV_ASSIGNMENT_DELAY
	      imem_c_rg_cache_addr$D_IN;
	if (rg_cur_priv$EN)
	  rg_cur_priv <= `BSV_ASSIGNMENT_DELAY rg_cur_priv$D_IN;
	if (rg_run_on_reset$EN)
	  rg_run_on_reset <= `BSV_ASSIGNMENT_DELAY rg_run_on_reset$D_IN;
	if (rg_state$EN) rg_state <= `BSV_ASSIGNMENT_DELAY rg_state$D_IN;
	if (stage1_rg_full$EN)
	  stage1_rg_full <= `BSV_ASSIGNMENT_DELAY stage1_rg_full$D_IN;
	if (stage2_rg_full$EN)
	  stage2_rg_full <= `BSV_ASSIGNMENT_DELAY stage2_rg_full$D_IN;
	if (stage2_rg_resetting$EN)
	  stage2_rg_resetting <= `BSV_ASSIGNMENT_DELAY
	      stage2_rg_resetting$D_IN;
	if (stage3_rg_full$EN)
	  stage3_rg_full <= `BSV_ASSIGNMENT_DELAY stage3_rg_full$D_IN;
      end
    if (imem_c_rg_cache_b16$EN)
      imem_c_rg_cache_b16 <= `BSV_ASSIGNMENT_DELAY imem_c_rg_cache_b16$D_IN;
    if (imem_c_rg_f3$EN)
      imem_c_rg_f3 <= `BSV_ASSIGNMENT_DELAY imem_c_rg_f3$D_IN;
    if (imem_c_rg_mstatus_MXR$EN)
      imem_c_rg_mstatus_MXR <= `BSV_ASSIGNMENT_DELAY
	  imem_c_rg_mstatus_MXR$D_IN;
    if (imem_c_rg_pc$EN)
      imem_c_rg_pc <= `BSV_ASSIGNMENT_DELAY imem_c_rg_pc$D_IN;
    if (imem_c_rg_priv$EN)
      imem_c_rg_priv <= `BSV_ASSIGNMENT_DELAY imem_c_rg_priv$D_IN;
    if (imem_c_rg_satp$EN)
      imem_c_rg_satp <= `BSV_ASSIGNMENT_DELAY imem_c_rg_satp$D_IN;
    if (imem_c_rg_sstatus_SUM$EN)
      imem_c_rg_sstatus_SUM <= `BSV_ASSIGNMENT_DELAY
	  imem_c_rg_sstatus_SUM$D_IN;
    if (imem_c_rg_tval$EN)
      imem_c_rg_tval <= `BSV_ASSIGNMENT_DELAY imem_c_rg_tval$D_IN;
    if (rg_csr_pc$EN) rg_csr_pc <= `BSV_ASSIGNMENT_DELAY rg_csr_pc$D_IN;
    if (rg_csr_val1$EN) rg_csr_val1 <= `BSV_ASSIGNMENT_DELAY rg_csr_val1$D_IN;
    if (rg_mstatus_MXR$EN)
      rg_mstatus_MXR <= `BSV_ASSIGNMENT_DELAY rg_mstatus_MXR$D_IN;
    if (rg_next_pc$EN) rg_next_pc <= `BSV_ASSIGNMENT_DELAY rg_next_pc$D_IN;
    if (rg_sstatus_SUM$EN)
      rg_sstatus_SUM <= `BSV_ASSIGNMENT_DELAY rg_sstatus_SUM$D_IN;
    if (rg_start_CPI_cycles$EN)
      rg_start_CPI_cycles <= `BSV_ASSIGNMENT_DELAY rg_start_CPI_cycles$D_IN;
    if (rg_start_CPI_instrs$EN)
      rg_start_CPI_instrs <= `BSV_ASSIGNMENT_DELAY rg_start_CPI_instrs$D_IN;
    if (rg_trap_info$EN)
      rg_trap_info <= `BSV_ASSIGNMENT_DELAY rg_trap_info$D_IN;
    if (rg_trap_instr$EN)
      rg_trap_instr <= `BSV_ASSIGNMENT_DELAY rg_trap_instr$D_IN;
    if (rg_trap_interrupt$EN)
      rg_trap_interrupt <= `BSV_ASSIGNMENT_DELAY rg_trap_interrupt$D_IN;
    if (stage2_rg_stage2$EN)
      stage2_rg_stage2 <= `BSV_ASSIGNMENT_DELAY stage2_rg_stage2$D_IN;
    if (stage3_rg_stage3$EN)
      stage3_rg_stage3 <= `BSV_ASSIGNMENT_DELAY stage3_rg_stage3$D_IN;
  end

  // synopsys translate_off
  `ifdef BSV_NO_INITIAL_BLOCKS
  `else // not BSV_NO_INITIAL_BLOCKS
  initial
  begin
    cfg_logdelay = 64'hAAAAAAAAAAAAAAAA;
    cfg_verbosity = 4'hA;
    imem_c_rg_cache_addr = 32'hAAAAAAAA;
    imem_c_rg_cache_b16 = 17'h0AAAA;
    imem_c_rg_f3 = 3'h2;
    imem_c_rg_mstatus_MXR = 1'h0;
    imem_c_rg_pc = 32'hAAAAAAAA;
    imem_c_rg_priv = 2'h2;
    imem_c_rg_satp = 32'hAAAAAAAA;
    imem_c_rg_sstatus_SUM = 1'h0;
    imem_c_rg_tval = 32'hAAAAAAAA;
    rg_csr_pc = 32'hAAAAAAAA;
    rg_csr_val1 = 32'hAAAAAAAA;
    rg_cur_priv = 2'h2;
    rg_mstatus_MXR = 1'h0;
    rg_next_pc = 32'hAAAAAAAA;
    rg_run_on_reset = 1'h0;
    rg_sstatus_SUM = 1'h0;
    rg_start_CPI_cycles = 64'hAAAAAAAAAAAAAAAA;
    rg_start_CPI_instrs = 64'hAAAAAAAAAAAAAAAA;
    rg_state = 4'hA;
    rg_trap_info = 68'hAAAAAAAAAAAAAAAAA;
    rg_trap_instr = 32'hAAAAAAAA;
    rg_trap_interrupt = 1'h0;
    stage1_rg_full = 1'h0;
    stage2_rg_full = 1'h0;
    stage2_rg_resetting = 1'h0;
    stage2_rg_stage2 = 170'h2AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA;
    stage3_rg_full = 1'h0;
    stage3_rg_stage3 = 104'hAAAAAAAAAAAAAAAAAAAAAAAAAA;
  end
  `endif // BSV_NO_INITIAL_BLOCKS
  // synopsys translate_on

  // handling of system tasks

  // synopsys translate_off
  always@(negedge CLK)
  begin
    #0;
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe)
	$display("================================================================");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe)
	$display("%0d: Pipeline State:  minstret:%0d  cur_priv:%0d  mstatus:%0x",
		 csr_regfile$read_csr_mcycle,
		 csr_regfile$read_csr_minstret,
		 rg_cur_priv,
		 csr_regfile$read_mstatus);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe) $write("    ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe)
	$write("MStatus{",
	       "sd:%0d",
	       csr_regfile$read_mstatus[14:13] == 2'h3 ||
	       csr_regfile$read_mstatus[16:15] == 2'h3);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe && csr_regfile$read_misa[27:26] == 2'd2)
	$write(" sxl:%0d uxl:%0d", 2'd0, 2'd0);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe && csr_regfile$read_misa[27:26] != 2'd2)
	$write("");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe)
	$write(" tsr:%0d", csr_regfile$read_mstatus[22]);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe)
	$write(" tw:%0d", csr_regfile$read_mstatus[21]);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe)
	$write(" tvm:%0d", csr_regfile$read_mstatus[20]);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe)
	$write(" mxr:%0d", csr_regfile$read_mstatus[19]);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe)
	$write(" sum:%0d", csr_regfile$read_mstatus[18]);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe)
	$write(" mprv:%0d", csr_regfile$read_mstatus[17]);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe)
	$write(" xs:%0d", csr_regfile$read_mstatus[16:15]);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe)
	$write(" fs:%0d", csr_regfile$read_mstatus[14:13]);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe)
	$write(" mpp:%0d", csr_regfile$read_mstatus[12:11]);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe)
	$write(" spp:%0d", csr_regfile$read_mstatus[8]);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe)
	$write(" pies:%0d_%0d%0d",
	       csr_regfile$read_mstatus[7],
	       csr_regfile$read_mstatus[5],
	       csr_regfile$read_mstatus[4]);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe)
	$write(" ies:%0d_%0d%0d",
	       csr_regfile$read_mstatus[3],
	       csr_regfile$read_mstatus[1],
	       csr_regfile$read_mstatus[0]);
    if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_show_pipe) $write("}");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe) $write("\n");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe) $write("    Stage3: ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe) $write("Output_Stage3");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe && stage3_rg_full) $write(" PIPE");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe && !stage3_rg_full) $write(" EMPTY");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe) $write("\n");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe) $write("        Bypass  to Stage1: ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe) $write("Bypass {");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe &&
	  (!stage3_rg_full || !stage3_rg_stage3[37]))
	$write("Rd -");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe && stage3_rg_full && stage3_rg_stage3[37])
	$write("Rd %0d ",
	       stage3_rg_stage3[36:32],
	       "rd_val:%h",
	       stage3_rg_stage3[31:0]);
    if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_show_pipe) $write("}");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe) $write("\n");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe)
	$display("    Stage2: pc 0x%08h instr 0x%08h priv %0d",
		 stage2_rg_stage2[167:136],
		 stage2_rg_stage2[135:104],
		 stage2_rg_stage2[169:168]);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe) $write("        ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe &&
	  stage2_rg_full_0_AND_NOT_stage2_rg_stage2_1_BI_ETC___d120)
	$write("Output_Stage2", " BUSY: pc:%0h", stage2_rg_stage2[167:136]);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe && stage2_rg_full &&
	  IF_stage2_rg_stage2_1_BITS_103_TO_101_2_EQ_1_4_ETC___d122 &&
	  NOT_stage2_rg_stage2_1_BITS_103_TO_101_2_EQ_0__ETC___d126)
	$write("Output_Stage2", " NONPIPE: ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe &&
	  stage2_rg_full_0_AND_stage2_rg_stage2_1_BITS_1_ETC___d140)
	$write("Output_Stage2", " PIPE: ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe && !stage2_rg_full)
	$write("Output_Stage2", " EMPTY");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe &&
	  stage2_rg_full_0_AND_NOT_stage2_rg_stage2_1_BI_ETC___d120)
	$write("");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe && stage2_rg_full &&
	  IF_stage2_rg_stage2_1_BITS_103_TO_101_2_EQ_1_4_ETC___d122 &&
	  NOT_stage2_rg_stage2_1_BITS_103_TO_101_2_EQ_0__ETC___d126)
	$write("");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe &&
	  stage2_rg_full_0_AND_stage2_rg_stage2_1_BITS_1_ETC___d140)
	$write("data_to_Stage3 {pc:%h  instr:%h  priv:%0d\n",
	       stage2_rg_stage2[167:136],
	       stage2_rg_stage2[135:104],
	       stage2_rg_stage2[169:168]);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe && !stage2_rg_full) $write("");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe &&
	  stage2_rg_full_0_AND_NOT_stage2_rg_stage2_1_BI_ETC___d120)
	$write("");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe && stage2_rg_full &&
	  IF_stage2_rg_stage2_1_BITS_103_TO_101_2_EQ_1_4_ETC___d122 &&
	  NOT_stage2_rg_stage2_1_BITS_103_TO_101_2_EQ_0__ETC___d126)
	$write("");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe &&
	  stage2_rg_full_0_AND_stage2_rg_stage2_1_BITS_1_ETC___d140)
	$write("        rd_valid:");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe && !stage2_rg_full) $write("");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe &&
	  stage2_rg_full_0_AND_NOT_stage2_rg_stage2_1_BI_ETC___d120)
	$write("");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe && stage2_rg_full &&
	  IF_stage2_rg_stage2_1_BITS_103_TO_101_2_EQ_1_4_ETC___d122 &&
	  NOT_stage2_rg_stage2_1_BITS_103_TO_101_2_EQ_0__ETC___d126)
	$write("");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe && stage2_rg_full &&
	  IF_stage2_rg_stage2_1_BITS_103_TO_101_2_EQ_1_4_ETC___d122 &&
	  NOT_stage2_rg_stage2_1_BITS_103_TO_101_2_EQ_1__ETC___d146)
	$write("False");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe && stage2_rg_full &&
	  (stage2_rg_stage2[103:101] == 3'd0 ||
	   IF_stage2_rg_stage2_1_BITS_103_TO_101_2_EQ_1_4_ETC___d122) &&
	  stage2_rg_stage2_1_BITS_103_TO_101_2_EQ_0_3_OR_ETC___d138 &&
	  (stage2_rg_stage2[103:101] == 3'd0 ||
	   IF_stage2_rg_stage2_1_BITS_103_TO_101_2_EQ_1_4_ETC___d152))
	$write("True");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe && !stage2_rg_full) $write("");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe &&
	  stage2_rg_full_0_AND_NOT_stage2_rg_stage2_1_BI_ETC___d120)
	$write("");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe && stage2_rg_full &&
	  IF_stage2_rg_stage2_1_BITS_103_TO_101_2_EQ_1_4_ETC___d122 &&
	  NOT_stage2_rg_stage2_1_BITS_103_TO_101_2_EQ_0__ETC___d126)
	$write("");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe &&
	  stage2_rg_full_0_AND_stage2_rg_stage2_1_BITS_1_ETC___d140)
	$write("  grd:%0d  rd_val:%h\n",
	       x_out_data_to_stage3_rd__h6401,
	       x_out_data_to_stage3_rd_val__h6402);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe && !stage2_rg_full) $write("");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe &&
	  stage2_rg_full_0_AND_NOT_stage2_rg_stage2_1_BI_ETC___d120)
	$write("");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe && stage2_rg_full &&
	  IF_stage2_rg_stage2_1_BITS_103_TO_101_2_EQ_1_4_ETC___d122 &&
	  NOT_stage2_rg_stage2_1_BITS_103_TO_101_2_EQ_0__ETC___d126)
	$write("Trap_Info { ", "epc: ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe &&
	  stage2_rg_full_0_AND_stage2_rg_stage2_1_BITS_1_ETC___d140)
	$write("");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe && !stage2_rg_full) $write("");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe &&
	  stage2_rg_full_0_AND_NOT_stage2_rg_stage2_1_BI_ETC___d120)
	$write("");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe && stage2_rg_full &&
	  IF_stage2_rg_stage2_1_BITS_103_TO_101_2_EQ_1_4_ETC___d122 &&
	  NOT_stage2_rg_stage2_1_BITS_103_TO_101_2_EQ_0__ETC___d126)
	$write("'h%h", stage2_rg_stage2[167:136]);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe &&
	  stage2_rg_full_0_AND_stage2_rg_stage2_1_BITS_1_ETC___d140)
	$write("");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe && !stage2_rg_full) $write("");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe &&
	  stage2_rg_full_0_AND_NOT_stage2_rg_stage2_1_BI_ETC___d120)
	$write("");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe && stage2_rg_full &&
	  IF_stage2_rg_stage2_1_BITS_103_TO_101_2_EQ_1_4_ETC___d122 &&
	  NOT_stage2_rg_stage2_1_BITS_103_TO_101_2_EQ_0__ETC___d126)
	$write(", ", "exc_code: ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe &&
	  stage2_rg_full_0_AND_stage2_rg_stage2_1_BITS_1_ETC___d140)
	$write("");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe && !stage2_rg_full) $write("");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe &&
	  stage2_rg_full_0_AND_NOT_stage2_rg_stage2_1_BI_ETC___d120)
	$write("");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe && stage2_rg_full &&
	  IF_stage2_rg_stage2_1_BITS_103_TO_101_2_EQ_1_4_ETC___d122 &&
	  NOT_stage2_rg_stage2_1_BITS_103_TO_101_2_EQ_0__ETC___d126)
	$write("'h%h", near_mem$dmem_exc_code);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe &&
	  stage2_rg_full_0_AND_stage2_rg_stage2_1_BITS_1_ETC___d140)
	$write("");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe && !stage2_rg_full) $write("");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe &&
	  stage2_rg_full_0_AND_NOT_stage2_rg_stage2_1_BI_ETC___d120)
	$write("");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe && stage2_rg_full &&
	  IF_stage2_rg_stage2_1_BITS_103_TO_101_2_EQ_1_4_ETC___d122 &&
	  NOT_stage2_rg_stage2_1_BITS_103_TO_101_2_EQ_0__ETC___d126)
	$write(", ", "tval: ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe &&
	  stage2_rg_full_0_AND_stage2_rg_stage2_1_BITS_1_ETC___d140)
	$write("");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe && !stage2_rg_full) $write("");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe &&
	  stage2_rg_full_0_AND_NOT_stage2_rg_stage2_1_BI_ETC___d120)
	$write("");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe && stage2_rg_full &&
	  IF_stage2_rg_stage2_1_BITS_103_TO_101_2_EQ_1_4_ETC___d122 &&
	  NOT_stage2_rg_stage2_1_BITS_103_TO_101_2_EQ_0__ETC___d126)
	$write("'h%h", stage2_rg_stage2[95:64], " }");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe &&
	  stage2_rg_full_0_AND_stage2_rg_stage2_1_BITS_1_ETC___d140)
	$write("");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe && !stage2_rg_full) $write("");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe &&
	  stage2_rg_full_0_AND_NOT_stage2_rg_stage2_1_BI_ETC___d120)
	$write("");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe && stage2_rg_full &&
	  IF_stage2_rg_stage2_1_BITS_103_TO_101_2_EQ_1_4_ETC___d122 &&
	  NOT_stage2_rg_stage2_1_BITS_103_TO_101_2_EQ_0__ETC___d126)
	$write(" ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe &&
	  stage2_rg_full_0_AND_stage2_rg_stage2_1_BITS_1_ETC___d140)
	$write("");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe && !stage2_rg_full) $write("");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe &&
	  stage2_rg_full_0_AND_NOT_stage2_rg_stage2_1_BI_ETC___d120)
	$write("");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe && stage2_rg_full &&
	  IF_stage2_rg_stage2_1_BITS_103_TO_101_2_EQ_1_4_ETC___d122 &&
	  NOT_stage2_rg_stage2_1_BITS_103_TO_101_2_EQ_0__ETC___d126)
	$write("Trap_Info { ", "epc: ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe &&
	  stage2_rg_full_0_AND_stage2_rg_stage2_1_BITS_1_ETC___d140)
	$write("");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe && !stage2_rg_full) $write("");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe &&
	  stage2_rg_full_0_AND_NOT_stage2_rg_stage2_1_BI_ETC___d120)
	$write("");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe && stage2_rg_full &&
	  IF_stage2_rg_stage2_1_BITS_103_TO_101_2_EQ_1_4_ETC___d122 &&
	  NOT_stage2_rg_stage2_1_BITS_103_TO_101_2_EQ_0__ETC___d126)
	$write("'h%h", stage2_rg_stage2[167:136]);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe &&
	  stage2_rg_full_0_AND_stage2_rg_stage2_1_BITS_1_ETC___d140)
	$write("");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe && !stage2_rg_full) $write("");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe &&
	  stage2_rg_full_0_AND_NOT_stage2_rg_stage2_1_BI_ETC___d120)
	$write("");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe && stage2_rg_full &&
	  IF_stage2_rg_stage2_1_BITS_103_TO_101_2_EQ_1_4_ETC___d122 &&
	  NOT_stage2_rg_stage2_1_BITS_103_TO_101_2_EQ_0__ETC___d126)
	$write(", ", "exc_code: ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe &&
	  stage2_rg_full_0_AND_stage2_rg_stage2_1_BITS_1_ETC___d140)
	$write("");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe && !stage2_rg_full) $write("");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe &&
	  stage2_rg_full_0_AND_NOT_stage2_rg_stage2_1_BI_ETC___d120)
	$write("");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe && stage2_rg_full &&
	  IF_stage2_rg_stage2_1_BITS_103_TO_101_2_EQ_1_4_ETC___d122 &&
	  NOT_stage2_rg_stage2_1_BITS_103_TO_101_2_EQ_0__ETC___d126)
	$write("'h%h", near_mem$dmem_exc_code);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe &&
	  stage2_rg_full_0_AND_stage2_rg_stage2_1_BITS_1_ETC___d140)
	$write("");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe && !stage2_rg_full) $write("");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe &&
	  stage2_rg_full_0_AND_NOT_stage2_rg_stage2_1_BI_ETC___d120)
	$write("");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe && stage2_rg_full &&
	  IF_stage2_rg_stage2_1_BITS_103_TO_101_2_EQ_1_4_ETC___d122 &&
	  NOT_stage2_rg_stage2_1_BITS_103_TO_101_2_EQ_0__ETC___d126)
	$write(", ", "tval: ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe &&
	  stage2_rg_full_0_AND_stage2_rg_stage2_1_BITS_1_ETC___d140)
	$write("");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe && !stage2_rg_full) $write("");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe &&
	  stage2_rg_full_0_AND_NOT_stage2_rg_stage2_1_BI_ETC___d120)
	$write("");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe && stage2_rg_full &&
	  IF_stage2_rg_stage2_1_BITS_103_TO_101_2_EQ_1_4_ETC___d122 &&
	  NOT_stage2_rg_stage2_1_BITS_103_TO_101_2_EQ_0__ETC___d126)
	$write("'h%h", stage2_rg_stage2[95:64], " }");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe &&
	  stage2_rg_full_0_AND_stage2_rg_stage2_1_BITS_1_ETC___d140)
	$write("");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe && !stage2_rg_full) $write("");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe) $write("\n");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe) $write("        Bypass  to Stage1: ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe) $write("Bypass {");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe &&
	  (!stage2_rg_full ||
	   stage2_rg_stage2[103:101] != 3'd0 &&
	   IF_stage2_rg_stage2_1_BITS_103_TO_101_2_EQ_1_4_ETC___d183))
	$write("Rd -");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe && stage2_rg_full &&
	  (stage2_rg_stage2[103:101] == 3'd0 ||
	   IF_stage2_rg_stage2_1_BITS_103_TO_101_2_EQ_1_4_ETC___d188))
	$write("Rd %0d ", x_out_bypass_rd__h7054);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe &&
	  (!stage2_rg_full ||
	   stage2_rg_stage2[103:101] != 3'd0 &&
	   IF_stage2_rg_stage2_1_BITS_103_TO_101_2_EQ_1_4_ETC___d183))
	$write("");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe && stage2_rg_full &&
	  IF_stage2_rg_stage2_1_BITS_103_TO_101_2_EQ_1_4_ETC___d188 &&
	  stage2_rg_stage2[103:101] != 3'd0 &&
	  IF_stage2_rg_stage2_1_BITS_103_TO_101_2_EQ_1_4_ETC___d196)
	$write("-");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe && stage2_rg_full &&
	  (stage2_rg_stage2[103:101] == 3'd0 ||
	   IF_stage2_rg_stage2_1_BITS_103_TO_101_2_EQ_1_4_ETC___d188) &&
	  (stage2_rg_stage2[103:101] == 3'd0 ||
	   IF_stage2_rg_stage2_1_BITS_103_TO_101_2_EQ_1_4_ETC___d200))
	$write("rd_val:%h", x_out_bypass_rd_val__h7055);
    if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_show_pipe) $write("}");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe) $write("\n");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe)
	$display("    Stage1: pc 0x%08h instr 0x%08h priv %0d",
		 imem_c_rg_pc,
		 x_out_data_to_stage2_instr__h12924,
		 rg_cur_priv);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe) $write("        ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe &&
	  stage1_rg_full_06_AND_NOT_near_mem_imem_valid__ETC___d517)
	$write("Output_Stage1", " BUSY pc:%h", imem_c_rg_pc);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full &&
	  near_mem_imem_valid_AND_NOT_imem_c_rg_pc_BITS__ETC___d683)
	$write("Output_Stage1", " NONPIPE: pc:%h", imem_c_rg_pc);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full &&
	  near_mem_imem_valid_AND_NOT_imem_c_rg_pc_BITS__ETC___d733)
	$write("Output_Stage1");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe && !stage1_rg_full)
	$write("Output_Stage1", " EMPTY");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe &&
	  stage1_rg_full_06_AND_NOT_near_mem_imem_valid__ETC___d517)
	$write("");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full &&
	  near_mem_imem_valid_AND_NOT_imem_c_rg_pc_BITS__ETC___d683)
	$write("");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full &&
	  near_mem_imem_valid_AND_NOT_imem_c_rg_pc_BITS__ETC___d733)
	$write(" PIPE: ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe && !stage1_rg_full) $write("");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe &&
	  stage1_rg_full_06_AND_NOT_near_mem_imem_valid__ETC___d517)
	$write("");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full &&
	  near_mem_imem_valid_AND_NOT_imem_c_rg_pc_BITS__ETC___d683)
	$write("");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full &&
	  near_mem_imem_valid_AND_NOT_imem_c_rg_pc_BITS__ETC___d740)
	$write("CONTROL_STRAIGHT");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full &&
	  near_mem$imem_valid &&
	  NOT_imem_c_rg_pc_BITS_1_TO_0_EQ_0b0_AND_imem_c_ETC___d521 &&
	  NOT_stage2_rg_full_0_41_OR_stage2_rg_stage2_1__ETC___d527 &&
	  stage2_rg_full_0_AND_NOT_stage2_rg_stage2_1_BI_ETC___d746)
	$write("CONTROL_BRANCH");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full &&
	  near_mem_imem_valid_AND_NOT_imem_c_rg_pc_BITS__ETC___d760)
	$write("CONTROL_CSRR_W");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full &&
	  near_mem_imem_valid_AND_NOT_imem_c_rg_pc_BITS__ETC___d774)
	$write("CONTROL_CSRR_S_or_C");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full &&
	  near_mem_imem_valid_AND_NOT_imem_c_rg_pc_BITS__ETC___d783)
	$write("CONTROL_FENCE");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full &&
	  near_mem_imem_valid_AND_NOT_imem_c_rg_pc_BITS__ETC___d791)
	$write("CONTROL_FENCE_I");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full &&
	  near_mem_imem_valid_AND_NOT_imem_c_rg_pc_BITS__ETC___d808)
	$write("CONTROL_MRET");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full &&
	  near_mem_imem_valid_AND_NOT_imem_c_rg_pc_BITS__ETC___d828)
	$write("CONTROL_WFI");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full &&
	  near_mem_imem_valid_AND_NOT_imem_c_rg_pc_BITS__ETC___d883)
	$write("CONTROL_TRAP");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe && !stage1_rg_full) $write("");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe &&
	  stage1_rg_full_06_AND_NOT_near_mem_imem_valid__ETC___d517)
	$write("");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full &&
	  near_mem_imem_valid_AND_NOT_imem_c_rg_pc_BITS__ETC___d683)
	$write("");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full &&
	  near_mem_imem_valid_AND_NOT_imem_c_rg_pc_BITS__ETC___d733)
	$write(" ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe && !stage1_rg_full) $write("");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe &&
	  stage1_rg_full_06_AND_NOT_near_mem_imem_valid__ETC___d517)
	$write("");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full &&
	  near_mem_imem_valid_AND_NOT_imem_c_rg_pc_BITS__ETC___d683)
	$write("");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe && !stage1_rg_full) $write("");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe &&
	  stage1_rg_full_06_AND_NOT_near_mem_imem_valid__ETC___d517)
	$write("");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full &&
	  near_mem_imem_valid_AND_NOT_imem_c_rg_pc_BITS__ETC___d683)
	$write("");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe && !stage1_rg_full) $write("");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe &&
	  stage1_rg_full_06_AND_NOT_near_mem_imem_valid__ETC___d517)
	$write("");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full &&
	  near_mem_imem_valid_AND_NOT_imem_c_rg_pc_BITS__ETC___d683)
	$write("");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe && !stage1_rg_full) $write("");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe &&
	  stage1_rg_full_06_AND_NOT_near_mem_imem_valid__ETC___d517)
	$write("");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full &&
	  near_mem_imem_valid_AND_NOT_imem_c_rg_pc_BITS__ETC___d683)
	$write("");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe && !stage1_rg_full) $write("");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe &&
	  stage1_rg_full_06_AND_NOT_near_mem_imem_valid__ETC___d517)
	$write("");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full &&
	  near_mem_imem_valid_AND_NOT_imem_c_rg_pc_BITS__ETC___d683)
	$write("");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full &&
	  near_mem_imem_valid_AND_NOT_imem_c_rg_pc_BITS__ETC___d733)
	$write("}");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe && !stage1_rg_full) $write("");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe &&
	  stage1_rg_full_06_AND_NOT_near_mem_imem_valid__ETC___d517)
	$write("");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full &&
	  near_mem_imem_valid_AND_NOT_imem_c_rg_pc_BITS__ETC___d683)
	$write("");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full &&
	  near_mem_imem_valid_AND_NOT_imem_c_rg_pc_BITS__ETC___d733)
	$write("data_to_Stage 2 {pc:%h  instr:%h  priv:%0d\n",
	       imem_c_rg_pc,
	       x_out_data_to_stage2_instr__h12924,
	       rg_cur_priv);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe && !stage1_rg_full) $write("");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe &&
	  stage1_rg_full_06_AND_NOT_near_mem_imem_valid__ETC___d517)
	$write("");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full &&
	  near_mem_imem_valid_AND_NOT_imem_c_rg_pc_BITS__ETC___d683)
	$write("");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full &&
	  near_mem_imem_valid_AND_NOT_imem_c_rg_pc_BITS__ETC___d733)
	$write("            op_stage2:");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe && !stage1_rg_full) $write("");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe &&
	  stage1_rg_full_06_AND_NOT_near_mem_imem_valid__ETC___d517)
	$write("");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full &&
	  near_mem_imem_valid_AND_NOT_imem_c_rg_pc_BITS__ETC___d683)
	$write("");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full &&
	  near_mem_imem_valid_AND_NOT_imem_c_rg_pc_BITS__ETC___d892)
	$write("OP_Stage2_ALU");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full &&
	  near_mem_imem_valid_AND_NOT_imem_c_rg_pc_BITS__ETC___d896)
	$write("OP_Stage2_LD");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full &&
	  near_mem_imem_valid_AND_NOT_imem_c_rg_pc_BITS__ETC___d900)
	$write("OP_Stage2_ST");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full &&
	  near_mem_imem_valid_AND_NOT_imem_c_rg_pc_BITS__ETC___d904)
	$write("OP_Stage2_M");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full &&
	  near_mem_imem_valid_AND_NOT_imem_c_rg_pc_BITS__ETC___d924)
	$write("OP_Stage2_AMO");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe && !stage1_rg_full) $write("");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe &&
	  stage1_rg_full_06_AND_NOT_near_mem_imem_valid__ETC___d517)
	$write("");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full &&
	  near_mem_imem_valid_AND_NOT_imem_c_rg_pc_BITS__ETC___d683)
	$write("");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full &&
	  near_mem_imem_valid_AND_NOT_imem_c_rg_pc_BITS__ETC___d733)
	$write("  rd:%0d\n", x_out_data_to_stage2_rd__h12926);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe && !stage1_rg_full) $write("");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe &&
	  stage1_rg_full_06_AND_NOT_near_mem_imem_valid__ETC___d517)
	$write("");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full &&
	  near_mem_imem_valid_AND_NOT_imem_c_rg_pc_BITS__ETC___d683)
	$write("");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full &&
	  near_mem_imem_valid_AND_NOT_imem_c_rg_pc_BITS__ETC___d733)
	$write("            addr:%h  val1:%h  val2:%h}",
	       x_out_data_to_stage2_addr__h12927,
	       x_out_data_to_stage2_val1__h12928,
	       x_out_data_to_stage2_val2__h12929);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe && !stage1_rg_full) $write("");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe &&
	  stage1_rg_full_06_AND_NOT_near_mem_imem_valid__ETC___d517)
	$write("");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full &&
	  near_mem_imem_valid_AND_NOT_imem_c_rg_pc_BITS__ETC___d683)
	$write(" ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full &&
	  near_mem_imem_valid_AND_NOT_imem_c_rg_pc_BITS__ETC___d733)
	$write("");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe && !stage1_rg_full) $write("");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe &&
	  stage1_rg_full_06_AND_NOT_near_mem_imem_valid__ETC___d517)
	$write("");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full &&
	  near_mem$imem_valid &&
	  NOT_imem_c_rg_pc_BITS_1_TO_0_EQ_0b0_AND_imem_c_ETC___d521 &&
	  NOT_stage2_rg_full_0_41_OR_stage2_rg_stage2_1__ETC___d527 &&
	  near_mem_imem_exc__29_OR_IF_IF_imem_c_rg_pc_BI_ETC___d1024)
	$write("CONTROL_STRAIGHT");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full &&
	  near_mem$imem_valid &&
	  NOT_imem_c_rg_pc_BITS_1_TO_0_EQ_0b0_AND_imem_c_ETC___d521 &&
	  NOT_stage2_rg_full_0_41_OR_stage2_rg_stage2_1__ETC___d527 &&
	  near_mem_imem_exc__29_OR_IF_IF_imem_c_rg_pc_BI_ETC___d1027)
	$write("CONTROL_BRANCH");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full &&
	  near_mem$imem_valid &&
	  NOT_imem_c_rg_pc_BITS_1_TO_0_EQ_0b0_AND_imem_c_ETC___d521 &&
	  NOT_stage2_rg_full_0_41_OR_stage2_rg_stage2_1__ETC___d527 &&
	  near_mem_imem_exc__29_OR_IF_IF_imem_c_rg_pc_BI_ETC___d1030)
	$write("CONTROL_CSRR_W");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full &&
	  near_mem$imem_valid &&
	  NOT_imem_c_rg_pc_BITS_1_TO_0_EQ_0b0_AND_imem_c_ETC___d521 &&
	  NOT_stage2_rg_full_0_41_OR_stage2_rg_stage2_1__ETC___d527 &&
	  near_mem_imem_exc__29_OR_IF_IF_imem_c_rg_pc_BI_ETC___d1033)
	$write("CONTROL_CSRR_S_or_C");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full &&
	  near_mem$imem_valid &&
	  NOT_imem_c_rg_pc_BITS_1_TO_0_EQ_0b0_AND_imem_c_ETC___d521 &&
	  NOT_stage2_rg_full_0_41_OR_stage2_rg_stage2_1__ETC___d527 &&
	  near_mem_imem_exc__29_OR_IF_IF_imem_c_rg_pc_BI_ETC___d1036)
	$write("CONTROL_FENCE");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full &&
	  near_mem$imem_valid &&
	  NOT_imem_c_rg_pc_BITS_1_TO_0_EQ_0b0_AND_imem_c_ETC___d521 &&
	  NOT_stage2_rg_full_0_41_OR_stage2_rg_stage2_1__ETC___d527 &&
	  near_mem_imem_exc__29_OR_IF_IF_imem_c_rg_pc_BI_ETC___d1039)
	$write("CONTROL_FENCE_I");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full &&
	  near_mem$imem_valid &&
	  NOT_imem_c_rg_pc_BITS_1_TO_0_EQ_0b0_AND_imem_c_ETC___d521 &&
	  NOT_stage2_rg_full_0_41_OR_stage2_rg_stage2_1__ETC___d527 &&
	  near_mem_imem_exc__29_OR_IF_IF_imem_c_rg_pc_BI_ETC___d1042)
	$write("CONTROL_MRET");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full &&
	  near_mem$imem_valid &&
	  NOT_imem_c_rg_pc_BITS_1_TO_0_EQ_0b0_AND_imem_c_ETC___d521 &&
	  NOT_stage2_rg_full_0_41_OR_stage2_rg_stage2_1__ETC___d527 &&
	  near_mem_imem_exc__29_OR_IF_IF_imem_c_rg_pc_BI_ETC___d1045)
	$write("CONTROL_WFI");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full &&
	  near_mem$imem_valid &&
	  NOT_imem_c_rg_pc_BITS_1_TO_0_EQ_0b0_AND_imem_c_ETC___d521 &&
	  NOT_stage2_rg_full_0_41_OR_stage2_rg_stage2_1__ETC___d527 &&
	  near_mem_imem_exc__29_OR_IF_IF_imem_c_rg_pc_BI_ETC___d1048)
	$write("CONTROL_TRAP");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full &&
	  near_mem_imem_valid_AND_NOT_imem_c_rg_pc_BITS__ETC___d733)
	$write("");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe && !stage1_rg_full) $write("");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe &&
	  stage1_rg_full_06_AND_NOT_near_mem_imem_valid__ETC___d517)
	$write("");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full &&
	  near_mem_imem_valid_AND_NOT_imem_c_rg_pc_BITS__ETC___d683)
	$write(" ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full &&
	  near_mem_imem_valid_AND_NOT_imem_c_rg_pc_BITS__ETC___d733)
	$write("");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe && !stage1_rg_full) $write("");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe &&
	  stage1_rg_full_06_AND_NOT_near_mem_imem_valid__ETC___d517)
	$write("");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full &&
	  near_mem_imem_valid_AND_NOT_imem_c_rg_pc_BITS__ETC___d683)
	$write("Trap_Info { ", "epc: ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full &&
	  near_mem_imem_valid_AND_NOT_imem_c_rg_pc_BITS__ETC___d733)
	$write("");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe && !stage1_rg_full) $write("");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe &&
	  stage1_rg_full_06_AND_NOT_near_mem_imem_valid__ETC___d517)
	$write("");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full &&
	  near_mem_imem_valid_AND_NOT_imem_c_rg_pc_BITS__ETC___d683)
	$write("'h%h", imem_c_rg_pc);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full &&
	  near_mem_imem_valid_AND_NOT_imem_c_rg_pc_BITS__ETC___d733)
	$write("");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe && !stage1_rg_full) $write("");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe &&
	  stage1_rg_full_06_AND_NOT_near_mem_imem_valid__ETC___d517)
	$write("");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full &&
	  near_mem_imem_valid_AND_NOT_imem_c_rg_pc_BITS__ETC___d683)
	$write(", ", "exc_code: ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full &&
	  near_mem_imem_valid_AND_NOT_imem_c_rg_pc_BITS__ETC___d733)
	$write("");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe && !stage1_rg_full) $write("");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe &&
	  stage1_rg_full_06_AND_NOT_near_mem_imem_valid__ETC___d517)
	$write("");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full &&
	  near_mem_imem_valid_AND_NOT_imem_c_rg_pc_BITS__ETC___d683)
	$write("'h%h", x_out_trap_info_exc_code__h14521);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full &&
	  near_mem_imem_valid_AND_NOT_imem_c_rg_pc_BITS__ETC___d733)
	$write("");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe && !stage1_rg_full) $write("");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe &&
	  stage1_rg_full_06_AND_NOT_near_mem_imem_valid__ETC___d517)
	$write("");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full &&
	  near_mem_imem_valid_AND_NOT_imem_c_rg_pc_BITS__ETC___d683)
	$write(", ", "tval: ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full &&
	  near_mem_imem_valid_AND_NOT_imem_c_rg_pc_BITS__ETC___d733)
	$write("");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe && !stage1_rg_full) $write("");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe &&
	  stage1_rg_full_06_AND_NOT_near_mem_imem_valid__ETC___d517)
	$write("");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full &&
	  near_mem_imem_valid_AND_NOT_imem_c_rg_pc_BITS__ETC___d683)
	$write("'h%h", value__h14581, " }");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full &&
	  near_mem_imem_valid_AND_NOT_imem_c_rg_pc_BITS__ETC___d733)
	$write("");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe && !stage1_rg_full) $write("");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe &&
	  stage1_rg_full_06_AND_NOT_near_mem_imem_valid__ETC___d517)
	$write("");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe && !stage1_rg_full) $write("");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe) $write("\n");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe) $display("----------------");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_stage2_nonpipe &&
	  NOT_IF_csr_regfile_read_csr_minstret__8_ULT_cf_ETC___d44)
	$display("%0d: %m.rl_stage2_nonpipe", csr_regfile$read_csr_mcycle);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_stage1_trap &&
	  NOT_IF_csr_regfile_read_csr_minstret__8_ULT_cf_ETC___d44)
	$display("%0d: %m.rl_stage1_trap", csr_regfile$read_csr_mcycle);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_trap &&
	  rg_trap_info_360_BITS_67_TO_36_361_EQ_csr_regf_ETC___d1370)
	$display("%0d: %m.rl_stage1_trap: Tight infinite trap loop: pc 0x%0x instr 0x%08x",
		 csr_regfile$read_csr_mcycle,
		 csr_regfile$csr_trap_actions[97:66],
		 rg_trap_instr);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_trap &&
	  rg_trap_info_360_BITS_67_TO_36_361_EQ_csr_regf_ETC___d1370)
	$display("CPI: %0d.%0d = (%0d/%0d) since last 'continue'",
		 cpi__h20142,
		 cpifrac__h20143,
		 delta_CPI_cycles__h20138,
		 _theResult____h20140);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_trap &&
	  rg_trap_info_360_BITS_67_TO_36_361_EQ_csr_regf_ETC___d1370)
	$finish(32'd0);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_trap && cur_verbosity__h3469 == 4'd1)
	$display("instret:%0d  PC:0x%0h  instr:0x%0h  priv:%0d",
		 csr_regfile$read_csr_minstret,
		 rg_trap_info[67:36],
		 rg_trap_instr,
		 rg_cur_priv);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_trap && cur_verbosity__h3469 != 4'd0)
	$display("    mcause:0x%0h  epc 0x%0h  tval:0x%0h  next_pc 0x%0h, new_priv %0d new_mstatus 0x%0h",
		 csr_regfile$csr_trap_actions[33:2],
		 rg_trap_info[67:36],
		 rg_trap_info[31:0],
		 csr_regfile$csr_trap_actions[97:66],
		 csr_regfile$csr_trap_actions[1:0],
		 csr_regfile$csr_trap_actions[65:34]);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_stage1_CSRR_W &&
	  NOT_IF_csr_regfile_read_csr_minstret__8_ULT_cf_ETC___d44)
	$display("%0d: %m.rl_stage1_CSRR_W", csr_regfile$read_csr_mcycle);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_stage1_CSRR_W_2 &&
	  NOT_IF_csr_regfile_read_csr_minstret__8_ULT_cf_ETC___d44)
	$display("%0d: %m.rl_stage1_CSRR_W_2", csr_regfile$read_csr_mcycle);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_stage1_CSRR_W_2 && csr_regfile$access_permitted_1 &&
	  cur_verbosity__h3469 == 4'd1)
	$display("instret:%0d  PC:0x%0h  instr:0x%0h  priv:%0d",
		 csr_regfile$read_csr_minstret,
		 rg_csr_pc,
		 rg_trap_instr,
		 rg_cur_priv);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_stage1_CSRR_W_2 && csr_regfile$access_permitted_1 &&
	  NOT_IF_csr_regfile_read_csr_minstret__8_ULT_cf_ETC___d44)
	$display("    S1: write CSRRW/CSRRWI Rs1 %0d Rs1_val 0x%0h csr 0x%0h csr_val 0x%0h Rd %0d",
		 rg_trap_instr[19:15],
		 rs1_val__h20670,
		 rg_trap_instr[31:20],
		 csr_regfile$read_csr[31:0],
		 rg_trap_instr[11:7]);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_stage1_CSRR_W_2 &&
	  !csr_regfile$access_permitted_1 &&
	  NOT_IF_csr_regfile_read_csr_minstret__8_ULT_cf_ETC___d44)
	$display("    Trap on CSR permissions: Rs1 %0d Rs1_val 0x%0h csr 0x%0h Rd %0d",
		 rg_trap_instr[19:15],
		 rs1_val__h20670,
		 rg_trap_instr[31:20],
		 rg_trap_instr[11:7]);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_stage1_CSRR_S_or_C &&
	  NOT_IF_csr_regfile_read_csr_minstret__8_ULT_cf_ETC___d44)
	$display("%0d: %m.rl_stage1_CSRR_S_or_C",
		 csr_regfile$read_csr_mcycle);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_stage1_CSRR_S_or_C_2 &&
	  NOT_IF_csr_regfile_read_csr_minstret__8_ULT_cf_ETC___d44)
	$display("%0d: %m.rl_stage1_CSRR_S_or_C_2",
		 csr_regfile$read_csr_mcycle);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_stage1_CSRR_S_or_C_2 &&
	  csr_regfile$access_permitted_2 &&
	  cur_verbosity__h3469 == 4'd1)
	$display("instret:%0d  PC:0x%0h  instr:0x%0h  priv:%0d",
		 csr_regfile$read_csr_minstret,
		 rg_csr_pc,
		 rg_trap_instr,
		 rg_cur_priv);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_stage1_CSRR_S_or_C_2 &&
	  csr_regfile$access_permitted_2 &&
	  NOT_IF_csr_regfile_read_csr_minstret__8_ULT_cf_ETC___d44)
	$display("    S1: write CSRR_S_or_C: Rs1 %0d Rs1_val 0x%0h csr 0x%0h csr_val 0x%0h Rd %0d",
		 rg_trap_instr[19:15],
		 rs1_val__h21423,
		 rg_trap_instr[31:20],
		 csr_regfile$read_csr[31:0],
		 rg_trap_instr[11:7]);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_stage1_CSRR_S_or_C_2 &&
	  !csr_regfile$access_permitted_2 &&
	  NOT_IF_csr_regfile_read_csr_minstret__8_ULT_cf_ETC___d44)
	$display("    Trap on CSR permissions: Rs1 %0d Rs1_val 0x%0h csr 0x%0h Rd %0d",
		 rg_trap_instr[19:15],
		 rs1_val__h21423,
		 rg_trap_instr[31:20],
		 rg_trap_instr[11:7]);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_stage1_restart_after_csrrx &&
	  NOT_IF_csr_regfile_read_csr_minstret__8_ULT_cf_ETC___d44)
	$display("%0d: %m.rl_stage1_restart_after_csrrx",
		 csr_regfile$read_csr_mcycle);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_stage1_restart_after_csrrx &&
	  NOT_IF_csr_regfile_read_csr_minstret__8_ULT_cf_ETC___d44)
	$display("    CPU_Stage1.enq: 0x%08h", x_out_next_pc__h12736);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_stage1_xRET &&
	  NOT_IF_csr_regfile_read_csr_minstret__8_ULT_cf_ETC___d44)
	$display("%0d: %m.rl_stage1_xRET", csr_regfile$read_csr_mcycle);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_stage1_xRET && cur_verbosity__h3469 == 4'd1)
	$display("instret:%0d  PC:0x%0h  instr:0x%0h  priv:%0d",
		 csr_regfile$read_csr_minstret,
		 imem_c_rg_pc,
		 x_out_data_to_stage2_instr__h12924,
		 rg_cur_priv);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_stage1_xRET && cur_verbosity__h3469 != 4'd0)
	$display("    xRET: next_pc:0x%0h  new mstatus:0x%0h  new priv:%0d",
		 csr_regfile$csr_ret_actions[65:34],
		 csr_regfile$csr_ret_actions[31:0],
		 csr_regfile$csr_ret_actions[33:32]);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_stage1_FENCE_I &&
	  NOT_IF_csr_regfile_read_csr_minstret__8_ULT_cf_ETC___d44)
	$display("%0d: %m.rl_stage1_FENCE_I", csr_regfile$read_csr_mcycle);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_stage1_FENCE_I && cur_verbosity__h3469 == 4'd1)
	$display("instret:%0d  PC:0x%0h  instr:0x%0h  priv:%0d",
		 csr_regfile$read_csr_minstret,
		 imem_c_rg_pc,
		 x_out_data_to_stage2_instr__h12924,
		 rg_cur_priv);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_stage1_FENCE_I &&
	  NOT_IF_csr_regfile_read_csr_minstret__8_ULT_cf_ETC___d44)
	$display("%0d: %m.rl_stage1_FENCE_I", csr_regfile$read_csr_mcycle);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_finish_FENCE_I &&
	  NOT_IF_csr_regfile_read_csr_minstret__8_ULT_cf_ETC___d44)
	$display("%0d: %m.rl_finish_FENCE_I", csr_regfile$read_csr_mcycle);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_finish_FENCE_I &&
	  NOT_IF_csr_regfile_read_csr_minstret__8_ULT_cf_ETC___d44)
	$display("    CPU_Stage1.enq: 0x%08h", rg_next_pc);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_finish_FENCE_I &&
	  NOT_IF_csr_regfile_read_csr_minstret__8_ULT_cf_ETC___d44)
	$display("    CPU.rl_finish_FENCE_I");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_stage1_FENCE &&
	  NOT_IF_csr_regfile_read_csr_minstret__8_ULT_cf_ETC___d44)
	$display("%0d: %m.rl_stage1_FENCE", csr_regfile$read_csr_mcycle);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_stage1_FENCE && cur_verbosity__h3469 == 4'd1)
	$display("instret:%0d  PC:0x%0h  instr:0x%0h  priv:%0d",
		 csr_regfile$read_csr_minstret,
		 imem_c_rg_pc,
		 x_out_data_to_stage2_instr__h12924,
		 rg_cur_priv);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_stage1_FENCE &&
	  NOT_IF_csr_regfile_read_csr_minstret__8_ULT_cf_ETC___d44)
	$display("%0d: %m.rl_stage1_FENCE", csr_regfile$read_csr_mcycle);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_finish_FENCE &&
	  NOT_IF_csr_regfile_read_csr_minstret__8_ULT_cf_ETC___d44)
	$display("%0d: %m.rl_finish_FENCE", csr_regfile$read_csr_mcycle);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_finish_FENCE &&
	  NOT_IF_csr_regfile_read_csr_minstret__8_ULT_cf_ETC___d44)
	$display("    CPU_Stage1.enq: 0x%08h", rg_next_pc);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_finish_FENCE &&
	  NOT_IF_csr_regfile_read_csr_minstret__8_ULT_cf_ETC___d44)
	$display("    CPU.rl_finish_FENCE");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_finish_SFENCE_VMA &&
	  NOT_IF_csr_regfile_read_csr_minstret__8_ULT_cf_ETC___d44)
	$display("%0d: %m.rl_finish_SFENCE_VMA", csr_regfile$read_csr_mcycle);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_finish_SFENCE_VMA &&
	  NOT_IF_csr_regfile_read_csr_minstret__8_ULT_cf_ETC___d44)
	$display("    CPU_Stage1.enq: 0x%08h", rg_next_pc);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_finish_SFENCE_VMA &&
	  NOT_IF_csr_regfile_read_csr_minstret__8_ULT_cf_ETC___d44)
	$display("    CPU.rl_finish_SFENCE_VMA");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_stage1_WFI &&
	  NOT_IF_csr_regfile_read_csr_minstret__8_ULT_cf_ETC___d44)
	$display("%0d: %m.rl_stage1_WFI", csr_regfile$read_csr_mcycle);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_stage1_WFI && cur_verbosity__h3469 == 4'd1)
	$display("instret:%0d  PC:0x%0h  instr:0x%0h  priv:%0d",
		 csr_regfile$read_csr_minstret,
		 imem_c_rg_pc,
		 x_out_data_to_stage2_instr__h12924,
		 rg_cur_priv);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_stage1_WFI &&
	  NOT_IF_csr_regfile_read_csr_minstret__8_ULT_cf_ETC___d44)
	$display("    CPU.rl_stage1_WFI");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_WFI_resume &&
	  NOT_IF_csr_regfile_read_csr_minstret__8_ULT_cf_ETC___d44)
	$display("%0d: %m.rl_WFI_resume", csr_regfile$read_csr_mcycle);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_WFI_resume &&
	  NOT_IF_csr_regfile_read_csr_minstret__8_ULT_cf_ETC___d44)
	$display("    CPU_Stage1.enq: 0x%08h", rg_next_pc);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_reset_from_WFI &&
	  NOT_IF_csr_regfile_read_csr_minstret__8_ULT_cf_ETC___d44)
	$display("%0d: %m.rl_reset_from_WFI", csr_regfile$read_csr_mcycle);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_trap_fetch &&
	  NOT_IF_csr_regfile_read_csr_minstret__8_ULT_cf_ETC___d44)
	$display("    CPU_Stage1.enq: 0x%08h", rg_next_pc);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_stage1_interrupt &&
	  NOT_IF_csr_regfile_read_csr_minstret__8_ULT_cf_ETC___d44)
	$display("%0d: %m.rl_stage1_interrupt", csr_regfile$read_csr_mcycle);
    if (WILL_FIRE_RL_imem_c_rl_assert_fail)
      begin
        v__h2079 = $stime;
	#0;
      end
    v__h2073 = v__h2079 / 32'd10;
    if (WILL_FIRE_RL_imem_c_rl_assert_fail)
      $display("%0d: ERROR: CPU_Fetch_C: imem32.is_i32_not_i16 is False",
	       v__h2073);
    if (WILL_FIRE_RL_imem_c_rl_assert_fail) $finish(32'd1);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_reset_complete && rg_run_on_reset)
	$display("%0d: %m.rl_reset_complete: restart at PC = 0x%0h",
		 csr_regfile$read_csr_mcycle,
		 soc_map$m_pc_reset_value[31:0]);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_reset_complete && rg_run_on_reset &&
	  NOT_IF_csr_regfile_read_csr_minstret__8_ULT_cf_ETC___d44)
	$display("    CPU_Stage1.enq: 0x%08h",
		 soc_map$m_pc_reset_value[31:0]);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_reset_complete && !rg_run_on_reset)
	$display("%0d: %m.rl_reset_complete: entering DEBUG_MODE",
		 csr_regfile$read_csr_mcycle);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_pipe &&
	  NOT_IF_csr_regfile_read_csr_minstret__8_ULT_cf_ETC___d44)
	$display("%0d: %m.rl_pipe", csr_regfile$read_csr_mcycle);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_pipe && stage3_rg_full && stage3_rg_stage3[37] &&
	  NOT_IF_csr_regfile_read_csr_minstret__8_ULT_cf_ETC___d44)
	$display("    S3.fa_deq: write GRd 0x%0h, rd_val 0x%0h",
		 stage3_rg_stage3[36:32],
		 stage3_rg_stage3[31:0]);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_pipe &&
	  stage2_rg_full_0_AND_stage2_rg_stage2_1_BITS_1_ETC___d1202)
	$write("    S3.enq: ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_pipe &&
	  stage2_rg_full_0_AND_stage2_rg_stage2_1_BITS_1_ETC___d1202)
	$write("data_to_Stage3 {pc:%h  instr:%h  priv:%0d\n",
	       stage2_rg_stage2[167:136],
	       stage2_rg_stage2[135:104],
	       stage2_rg_stage2[169:168]);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_pipe &&
	  stage2_rg_full_0_AND_stage2_rg_stage2_1_BITS_1_ETC___d1202)
	$write("        rd_valid:");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_pipe &&
	  stage2_rg_full_0_AND_IF_stage2_rg_stage2_1_BIT_ETC___d1205)
	$write("False");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_pipe &&
	  stage2_rg_full_0_AND_stage2_rg_stage2_1_BITS_1_ETC___d1207)
	$write("True");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_pipe &&
	  stage2_rg_full_0_AND_stage2_rg_stage2_1_BITS_1_ETC___d1202)
	$write("  grd:%0d  rd_val:%h\n",
	       x_out_data_to_stage3_rd__h6401,
	       x_out_data_to_stage3_rd_val__h6402);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_pipe &&
	  stage2_rg_full_0_AND_stage2_rg_stage2_1_BITS_1_ETC___d1202)
	$write("\n");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_pipe && stage2_rg_full &&
	  (stage2_rg_stage2[103:101] == 3'd0 ||
	   IF_stage2_rg_stage2_1_BITS_103_TO_101_2_EQ_1_4_ETC___d1196) &&
	  cur_verbosity__h3469 == 4'd1)
	$display("instret:%0d  PC:0x%0h  instr:0x%0h  priv:%0d",
		 csr_regfile$read_csr_minstret,
		 stage2_rg_stage2[167:136],
		 stage2_rg_stage2[135:104],
		 rg_cur_priv);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_pipe &&
	  NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d1256)
	$write("    CPU_Stage2.enq (Data_Stage1_to_Stage2) ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_pipe &&
	  NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d1256)
	$write("data_to_Stage 2 {pc:%h  instr:%h  priv:%0d\n",
	       imem_c_rg_pc,
	       x_out_data_to_stage2_instr__h12924,
	       rg_cur_priv);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_pipe &&
	  NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d1256)
	$write("            op_stage2:");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_pipe &&
	  NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d1258)
	$write("OP_Stage2_ALU");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_pipe &&
	  NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d1260)
	$write("OP_Stage2_LD");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_pipe &&
	  NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d1262)
	$write("OP_Stage2_ST");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_pipe &&
	  NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d1264)
	$write("OP_Stage2_M");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_pipe &&
	  NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d1266)
	$write("OP_Stage2_AMO");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_pipe &&
	  NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d1256)
	$write("  rd:%0d\n", x_out_data_to_stage2_rd__h12926);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_pipe &&
	  NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d1256)
	$write("            addr:%h  val1:%h  val2:%h}",
	       x_out_data_to_stage2_addr__h12927,
	       x_out_data_to_stage2_val1__h12928,
	       x_out_data_to_stage2_val2__h12929);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_pipe &&
	  NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d1256)
	$write("\n");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_pipe &&
	  NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d1275 &&
	  NOT_IF_csr_regfile_read_csr_minstret__8_ULT_cf_ETC___d44)
	$display("    CPU_Stage1.enq: 0x%08h", x_out_next_pc__h12736);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_reset_start)
	$display("================================================================");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_reset_start)
	$write("CPU: Bluespec  RISC-V  Piccolo  v3.0");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_reset_start) $display(" (RV32)");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_reset_start)
	$display("Copyright (c) 2016-2020 Bluespec, Inc. All Rights Reserved.");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_reset_start)
	$display("================================================================");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_reset_start && cur_verbosity__h3469 != 4'd0)
	$display("%0d: %m.rl_reset_start", csr_regfile$read_csr_mcycle);
  end
  // synopsys translate_on
endmodule  // mkCPU

