//
// Generated by Bluespec Compiler, version 2018.10.beta1 (build e1df8052c, 2018-10-17)
//
//
//
//
// Ports:
// Name                         I/O  size props
// RDY_server_reset_request_put   O     1 reg
// RDY_server_reset_response_get  O     1
// read_csr                       O    33
// read_csr_port2                 O    33
// mav_read_csr                   O    33
// mav_csr_write                  O    32
// read_frm                       O     3 reg
// read_misa                      O    28 const
// read_mstatus                   O    32 reg
// read_sstatus                   O    32
// read_ustatus                   O    32
// read_satp                      O    32 reg
// csr_trap_actions               O    98
// RDY_csr_trap_actions           O     1 const
// csr_ret_actions                O    66
// RDY_csr_ret_actions            O     1 const
// read_csr_minstret              O    64 reg
// read_csr_mcycle                O    64 reg
// read_csr_mtime                 O    64 reg
// access_permitted_1             O     1
// access_permitted_2             O     1
// csr_counter_read_fault         O     1
// csr_mip_read                   O    32
// interrupt_pending              O     5
// wfi_resume                     O     1
// nmi_pending                    O     1 reg
// RDY_debug                      O     1 const
// CLK                            I     1 clock
// RST_N                          I     1 reset
// read_csr_csr_addr              I    12
// read_csr_port2_csr_addr        I    12
// mav_read_csr_csr_addr          I    12
// mav_csr_write_csr_addr         I    12
// mav_csr_write_word             I    32
// ma_update_fcsr_fflags_flags    I     5
// ma_update_mstatus_fs_fs        I     2
// csr_trap_actions_from_priv     I     2
// csr_trap_actions_pc            I    32
// csr_trap_actions_nmi           I     1
// csr_trap_actions_interrupt     I     1
// csr_trap_actions_exc_code      I     4
// csr_trap_actions_xtval         I    32
// csr_ret_actions_from_priv      I     2
// access_permitted_1_priv        I     2
// access_permitted_1_csr_addr    I    12
// access_permitted_1_read_not_write  I     1
// access_permitted_2_priv        I     2
// access_permitted_2_csr_addr    I    12
// access_permitted_2_read_not_write  I     1
// csr_counter_read_fault_priv    I     2
// csr_counter_read_fault_csr_addr  I    12
// m_external_interrupt_req_set_not_clear  I     1 reg
// s_external_interrupt_req_set_not_clear  I     1 reg
// timer_interrupt_req_set_not_clear  I     1 reg
// software_interrupt_req_set_not_clear  I     1 reg
// interrupt_pending_cur_priv     I     2
// nmi_req_set_not_clear          I     1
// EN_server_reset_request_put    I     1
// EN_server_reset_response_get   I     1
// EN_ma_update_fcsr_fflags       I     1
// EN_ma_update_mstatus_fs        I     1
// EN_csr_minstret_incr           I     1
// EN_debug                       I     1 unused
// EN_mav_read_csr                I     1 unused
// EN_mav_csr_write               I     1
// EN_csr_trap_actions            I     1
// EN_csr_ret_actions             I     1
//
// Combinational paths from inputs to outputs:
//   read_csr_csr_addr -> read_csr
//   read_csr_port2_csr_addr -> read_csr_port2
//   (access_permitted_1_priv,
//    access_permitted_1_csr_addr,
//    access_permitted_1_read_not_write) -> access_permitted_1
//   (access_permitted_2_priv,
//    access_permitted_2_csr_addr,
//    access_permitted_2_read_not_write) -> access_permitted_2
//   (csr_counter_read_fault_priv,
//    csr_counter_read_fault_csr_addr) -> csr_counter_read_fault
//   interrupt_pending_cur_priv -> interrupt_pending
//   mav_read_csr_csr_addr -> mav_read_csr
//   (mav_csr_write_csr_addr,
//    mav_csr_write_word,
//    EN_mav_csr_write) -> mav_csr_write
//   (csr_trap_actions_from_priv,
//    csr_trap_actions_nmi,
//    csr_trap_actions_interrupt,
//    csr_trap_actions_exc_code) -> csr_trap_actions
//   csr_ret_actions_from_priv -> csr_ret_actions
//
//

`ifdef BSV_ASSIGNMENT_DELAY
`else
  `define BSV_ASSIGNMENT_DELAY
`endif

`ifdef BSV_POSITIVE_RESET
  `define BSV_RESET_VALUE 1'b1
  `define BSV_RESET_EDGE posedge
`else
  `define BSV_RESET_VALUE 1'b0
  `define BSV_RESET_EDGE negedge
`endif

module mkCSR_RegFile(CLK,
		     RST_N,

		     EN_server_reset_request_put,
		     RDY_server_reset_request_put,

		     EN_server_reset_response_get,
		     RDY_server_reset_response_get,

		     read_csr_csr_addr,
		     read_csr,

		     read_csr_port2_csr_addr,
		     read_csr_port2,

		     mav_read_csr_csr_addr,
		     EN_mav_read_csr,
		     mav_read_csr,

		     mav_csr_write_csr_addr,
		     mav_csr_write_word,
		     EN_mav_csr_write,
		     mav_csr_write,

		     read_frm,

		     ma_update_fcsr_fflags_flags,
		     EN_ma_update_fcsr_fflags,

		     ma_update_mstatus_fs_fs,
		     EN_ma_update_mstatus_fs,

		     read_misa,

		     read_mstatus,

		     read_sstatus,

		     read_ustatus,

		     read_satp,

		     csr_trap_actions_from_priv,
		     csr_trap_actions_pc,
		     csr_trap_actions_nmi,
		     csr_trap_actions_interrupt,
		     csr_trap_actions_exc_code,
		     csr_trap_actions_xtval,
		     EN_csr_trap_actions,
		     csr_trap_actions,
		     RDY_csr_trap_actions,

		     csr_ret_actions_from_priv,
		     EN_csr_ret_actions,
		     csr_ret_actions,
		     RDY_csr_ret_actions,

		     read_csr_minstret,

		     EN_csr_minstret_incr,

		     read_csr_mcycle,

		     read_csr_mtime,

		     access_permitted_1_priv,
		     access_permitted_1_csr_addr,
		     access_permitted_1_read_not_write,
		     access_permitted_1,

		     access_permitted_2_priv,
		     access_permitted_2_csr_addr,
		     access_permitted_2_read_not_write,
		     access_permitted_2,

		     csr_counter_read_fault_priv,
		     csr_counter_read_fault_csr_addr,
		     csr_counter_read_fault,

		     csr_mip_read,

		     m_external_interrupt_req_set_not_clear,

		     s_external_interrupt_req_set_not_clear,

		     timer_interrupt_req_set_not_clear,

		     software_interrupt_req_set_not_clear,

		     interrupt_pending_cur_priv,
		     interrupt_pending,

		     wfi_resume,

		     nmi_req_set_not_clear,

		     nmi_pending,

		     EN_debug,
		     RDY_debug);
  input  CLK;
  input  RST_N;

  // action method server_reset_request_put
  input  EN_server_reset_request_put;
  output RDY_server_reset_request_put;

  // action method server_reset_response_get
  input  EN_server_reset_response_get;
  output RDY_server_reset_response_get;

  // value method read_csr
  input  [11 : 0] read_csr_csr_addr;
  output [32 : 0] read_csr;

  // value method read_csr_port2
  input  [11 : 0] read_csr_port2_csr_addr;
  output [32 : 0] read_csr_port2;

  // actionvalue method mav_read_csr
  input  [11 : 0] mav_read_csr_csr_addr;
  input  EN_mav_read_csr;
  output [32 : 0] mav_read_csr;

  // actionvalue method mav_csr_write
  input  [11 : 0] mav_csr_write_csr_addr;
  input  [31 : 0] mav_csr_write_word;
  input  EN_mav_csr_write;
  output [31 : 0] mav_csr_write;

  // value method read_frm
  output [2 : 0] read_frm;

  // action method ma_update_fcsr_fflags
  input  [4 : 0] ma_update_fcsr_fflags_flags;
  input  EN_ma_update_fcsr_fflags;

  // action method ma_update_mstatus_fs
  input  [1 : 0] ma_update_mstatus_fs_fs;
  input  EN_ma_update_mstatus_fs;

  // value method read_misa
  output [27 : 0] read_misa;

  // value method read_mstatus
  output [31 : 0] read_mstatus;

  // value method read_sstatus
  output [31 : 0] read_sstatus;

  // value method read_ustatus
  output [31 : 0] read_ustatus;

  // value method read_satp
  output [31 : 0] read_satp;

  // actionvalue method csr_trap_actions
  input  [1 : 0] csr_trap_actions_from_priv;
  input  [31 : 0] csr_trap_actions_pc;
  input  csr_trap_actions_nmi;
  input  csr_trap_actions_interrupt;
  input  [3 : 0] csr_trap_actions_exc_code;
  input  [31 : 0] csr_trap_actions_xtval;
  input  EN_csr_trap_actions;
  output [97 : 0] csr_trap_actions;
  output RDY_csr_trap_actions;

  // actionvalue method csr_ret_actions
  input  [1 : 0] csr_ret_actions_from_priv;
  input  EN_csr_ret_actions;
  output [65 : 0] csr_ret_actions;
  output RDY_csr_ret_actions;

  // value method read_csr_minstret
  output [63 : 0] read_csr_minstret;

  // action method csr_minstret_incr
  input  EN_csr_minstret_incr;

  // value method read_csr_mcycle
  output [63 : 0] read_csr_mcycle;

  // value method read_csr_mtime
  output [63 : 0] read_csr_mtime;

  // value method access_permitted_1
  input  [1 : 0] access_permitted_1_priv;
  input  [11 : 0] access_permitted_1_csr_addr;
  input  access_permitted_1_read_not_write;
  output access_permitted_1;

  // value method access_permitted_2
  input  [1 : 0] access_permitted_2_priv;
  input  [11 : 0] access_permitted_2_csr_addr;
  input  access_permitted_2_read_not_write;
  output access_permitted_2;

  // value method csr_counter_read_fault
  input  [1 : 0] csr_counter_read_fault_priv;
  input  [11 : 0] csr_counter_read_fault_csr_addr;
  output csr_counter_read_fault;

  // value method csr_mip_read
  output [31 : 0] csr_mip_read;

  // action method m_external_interrupt_req
  input  m_external_interrupt_req_set_not_clear;

  // action method s_external_interrupt_req
  input  s_external_interrupt_req_set_not_clear;

  // action method timer_interrupt_req
  input  timer_interrupt_req_set_not_clear;

  // action method software_interrupt_req
  input  software_interrupt_req_set_not_clear;

  // value method interrupt_pending
  input  [1 : 0] interrupt_pending_cur_priv;
  output [4 : 0] interrupt_pending;

  // value method wfi_resume
  output wfi_resume;

  // action method nmi_req
  input  nmi_req_set_not_clear;

  // value method nmi_pending
  output nmi_pending;

  // action method debug
  input  EN_debug;
  output RDY_debug;

  // signals for module outputs
  wire [97 : 0] csr_trap_actions;
  wire [65 : 0] csr_ret_actions;
  wire [63 : 0] read_csr_mcycle, read_csr_minstret, read_csr_mtime;
  wire [32 : 0] mav_read_csr, read_csr, read_csr_port2;
  wire [31 : 0] csr_mip_read,
		mav_csr_write,
		read_mstatus,
		read_satp,
		read_sstatus,
		read_ustatus;
  wire [27 : 0] read_misa;
  wire [4 : 0] interrupt_pending;
  wire [2 : 0] read_frm;
  wire RDY_csr_ret_actions,
       RDY_csr_trap_actions,
       RDY_debug,
       RDY_server_reset_request_put,
       RDY_server_reset_response_get,
       access_permitted_1,
       access_permitted_2,
       csr_counter_read_fault,
       nmi_pending,
       wfi_resume;

  // register cfg_verbosity
  reg [3 : 0] cfg_verbosity;
  wire [3 : 0] cfg_verbosity$D_IN;
  wire cfg_verbosity$EN;

  // register csr_mstatus_rg_mstatus
  reg [31 : 0] csr_mstatus_rg_mstatus;
  reg [31 : 0] csr_mstatus_rg_mstatus$D_IN;
  wire csr_mstatus_rg_mstatus$EN;

  // register rg_dcsr
  reg [31 : 0] rg_dcsr;
  wire [31 : 0] rg_dcsr$D_IN;
  wire rg_dcsr$EN;

  // register rg_dpc
  reg [31 : 0] rg_dpc;
  wire [31 : 0] rg_dpc$D_IN;
  wire rg_dpc$EN;

  // register rg_dscratch0
  reg [31 : 0] rg_dscratch0;
  wire [31 : 0] rg_dscratch0$D_IN;
  wire rg_dscratch0$EN;

  // register rg_dscratch1
  reg [31 : 0] rg_dscratch1;
  wire [31 : 0] rg_dscratch1$D_IN;
  wire rg_dscratch1$EN;

  // register rg_fflags
  reg [4 : 0] rg_fflags;
  reg [4 : 0] rg_fflags$D_IN;
  wire rg_fflags$EN;

  // register rg_frm
  reg [2 : 0] rg_frm;
  wire [2 : 0] rg_frm$D_IN;
  wire rg_frm$EN;

  // register rg_mcause
  reg [4 : 0] rg_mcause;
  reg [4 : 0] rg_mcause$D_IN;
  wire rg_mcause$EN;

  // register rg_mcounteren
  reg [2 : 0] rg_mcounteren;
  wire [2 : 0] rg_mcounteren$D_IN;
  wire rg_mcounteren$EN;

  // register rg_mcycle
  reg [63 : 0] rg_mcycle;
  wire [63 : 0] rg_mcycle$D_IN;
  wire rg_mcycle$EN;

  // register rg_medeleg
  reg [15 : 0] rg_medeleg;
  wire [15 : 0] rg_medeleg$D_IN;
  wire rg_medeleg$EN;

  // register rg_mepc
  reg [31 : 0] rg_mepc;
  wire [31 : 0] rg_mepc$D_IN;
  wire rg_mepc$EN;

  // register rg_mideleg
  reg [11 : 0] rg_mideleg;
  wire [11 : 0] rg_mideleg$D_IN;
  wire rg_mideleg$EN;

  // register rg_minstret
  reg [63 : 0] rg_minstret;
  wire [63 : 0] rg_minstret$D_IN;
  wire rg_minstret$EN;

  // register rg_mscratch
  reg [31 : 0] rg_mscratch;
  wire [31 : 0] rg_mscratch$D_IN;
  wire rg_mscratch$EN;

  // register rg_mtval
  reg [31 : 0] rg_mtval;
  wire [31 : 0] rg_mtval$D_IN;
  wire rg_mtval$EN;

  // register rg_mtvec
  reg [30 : 0] rg_mtvec;
  wire [30 : 0] rg_mtvec$D_IN;
  wire rg_mtvec$EN;

  // register rg_nmi
  reg rg_nmi;
  wire rg_nmi$D_IN, rg_nmi$EN;

  // register rg_nmi_vector
  reg [31 : 0] rg_nmi_vector;
  wire [31 : 0] rg_nmi_vector$D_IN;
  wire rg_nmi_vector$EN;

  // register rg_satp
  reg [31 : 0] rg_satp;
  wire [31 : 0] rg_satp$D_IN;
  wire rg_satp$EN;

  // register rg_scause
  reg [4 : 0] rg_scause;
  reg [4 : 0] rg_scause$D_IN;
  wire rg_scause$EN;

  // register rg_sepc
  reg [31 : 0] rg_sepc;
  wire [31 : 0] rg_sepc$D_IN;
  wire rg_sepc$EN;

  // register rg_sscratch
  reg [31 : 0] rg_sscratch;
  wire [31 : 0] rg_sscratch$D_IN;
  wire rg_sscratch$EN;

  // register rg_state
  reg rg_state;
  wire rg_state$D_IN, rg_state$EN;

  // register rg_stval
  reg [31 : 0] rg_stval;
  wire [31 : 0] rg_stval$D_IN;
  wire rg_stval$EN;

  // register rg_stvec
  reg [30 : 0] rg_stvec;
  wire [30 : 0] rg_stvec$D_IN;
  wire rg_stvec$EN;

  // register rg_tdata1
  reg [31 : 0] rg_tdata1;
  wire [31 : 0] rg_tdata1$D_IN;
  wire rg_tdata1$EN;

  // register rg_tdata2
  reg [31 : 0] rg_tdata2;
  wire [31 : 0] rg_tdata2$D_IN;
  wire rg_tdata2$EN;

  // register rg_tdata3
  reg [31 : 0] rg_tdata3;
  wire [31 : 0] rg_tdata3$D_IN;
  wire rg_tdata3$EN;

  // register rg_tselect
  reg [31 : 0] rg_tselect;
  wire [31 : 0] rg_tselect$D_IN;
  wire rg_tselect$EN;

  // ports of submodule csr_mie
  wire [31 : 0] csr_mie$fav_sie_write,
		csr_mie$fav_sie_write_wordxl,
		csr_mie$fav_write,
		csr_mie$fav_write_wordxl,
		csr_mie$fv_read,
		csr_mie$fv_sie_read;
  wire [27 : 0] csr_mie$fav_sie_write_misa, csr_mie$fav_write_misa;
  wire csr_mie$EN_fav_sie_write, csr_mie$EN_fav_write, csr_mie$EN_reset;

  // ports of submodule csr_mip
  wire [31 : 0] csr_mip$fav_sip_write,
		csr_mip$fav_sip_write_wordxl,
		csr_mip$fav_write,
		csr_mip$fav_write_wordxl,
		csr_mip$fv_read,
		csr_mip$fv_sip_read;
  wire [27 : 0] csr_mip$fav_sip_write_misa, csr_mip$fav_write_misa;
  wire csr_mip$EN_fav_sip_write,
       csr_mip$EN_fav_write,
       csr_mip$EN_reset,
       csr_mip$m_external_interrupt_req_req,
       csr_mip$s_external_interrupt_req_req,
       csr_mip$software_interrupt_req_req,
       csr_mip$timer_interrupt_req_req;

  // ports of submodule f_reset_rsps
  wire f_reset_rsps$CLR,
       f_reset_rsps$DEQ,
       f_reset_rsps$EMPTY_N,
       f_reset_rsps$ENQ,
       f_reset_rsps$FULL_N;

  // ports of submodule soc_map
  wire [63 : 0] soc_map$m_is_IO_addr_addr,
		soc_map$m_is_mem_addr_addr,
		soc_map$m_is_near_mem_IO_addr_addr,
		soc_map$m_mtvec_reset_value,
		soc_map$m_nmivec_reset_value;

  // rule scheduling signals
  wire CAN_FIRE_RL_rl_mcycle_incr,
       CAN_FIRE_RL_rl_reset_start,
       CAN_FIRE_RL_rl_upd_minstret_csrrx,
       CAN_FIRE_RL_rl_upd_minstret_incr,
       CAN_FIRE_csr_minstret_incr,
       CAN_FIRE_csr_ret_actions,
       CAN_FIRE_csr_trap_actions,
       CAN_FIRE_debug,
       CAN_FIRE_m_external_interrupt_req,
       CAN_FIRE_ma_update_fcsr_fflags,
       CAN_FIRE_ma_update_mstatus_fs,
       CAN_FIRE_mav_csr_write,
       CAN_FIRE_mav_read_csr,
       CAN_FIRE_nmi_req,
       CAN_FIRE_s_external_interrupt_req,
       CAN_FIRE_server_reset_request_put,
       CAN_FIRE_server_reset_response_get,
       CAN_FIRE_software_interrupt_req,
       CAN_FIRE_timer_interrupt_req,
       WILL_FIRE_RL_rl_mcycle_incr,
       WILL_FIRE_RL_rl_reset_start,
       WILL_FIRE_RL_rl_upd_minstret_csrrx,
       WILL_FIRE_RL_rl_upd_minstret_incr,
       WILL_FIRE_csr_minstret_incr,
       WILL_FIRE_csr_ret_actions,
       WILL_FIRE_csr_trap_actions,
       WILL_FIRE_debug,
       WILL_FIRE_m_external_interrupt_req,
       WILL_FIRE_ma_update_fcsr_fflags,
       WILL_FIRE_ma_update_mstatus_fs,
       WILL_FIRE_mav_csr_write,
       WILL_FIRE_mav_read_csr,
       WILL_FIRE_nmi_req,
       WILL_FIRE_s_external_interrupt_req,
       WILL_FIRE_server_reset_request_put,
       WILL_FIRE_server_reset_response_get,
       WILL_FIRE_software_interrupt_req,
       WILL_FIRE_timer_interrupt_req;

  // inputs to muxes for submodule ports
  wire [63 : 0] MUX_rg_minstret$write_1__VAL_1,
		MUX_rg_minstret$write_1__VAL_2,
		MUX_rw_minstret$wset_1__VAL_1;
  wire [31 : 0] MUX_csr_mstatus_rg_mstatus$write_1__VAL_2,
		MUX_csr_mstatus_rg_mstatus$write_1__VAL_4,
		MUX_csr_mstatus_rg_mstatus$write_1__VAL_5;
  wire [30 : 0] MUX_rg_mtvec$write_1__VAL_1, MUX_rg_mtvec$write_1__VAL_2;
  wire [15 : 0] MUX_rg_medeleg$write_1__VAL_1;
  wire [4 : 0] MUX_rg_fflags$write_1__VAL_3,
	       MUX_rg_mcause$write_1__VAL_2,
	       MUX_rg_mcause$write_1__VAL_3;
  wire [2 : 0] MUX_rg_frm$write_1__VAL_1;
  wire MUX_csr_mstatus_rg_mstatus$write_1__SEL_5,
       MUX_rg_fflags$write_1__SEL_2,
       MUX_rg_frm$write_1__SEL_1,
       MUX_rg_mcause$write_1__SEL_2,
       MUX_rg_mcause$write_1__SEL_3,
       MUX_rg_mcounteren$write_1__SEL_1,
       MUX_rg_medeleg$write_1__SEL_1,
       MUX_rg_mideleg$write_1__SEL_1,
       MUX_rg_mtvec$write_1__SEL_1,
       MUX_rg_satp$write_1__SEL_1,
       MUX_rg_scause$write_1__SEL_2,
       MUX_rg_scause$write_1__SEL_3,
       MUX_rg_sepc$write_1__SEL_1,
       MUX_rg_state$write_1__SEL_2,
       MUX_rg_stval$write_1__SEL_1,
       MUX_rg_stvec$write_1__SEL_1,
       MUX_rg_tdata1$write_1__SEL_1,
       MUX_rw_minstret$wset_1__SEL_1;

  // remaining internal signals
  reg [31 : 0] IF_mav_read_csr_csr_addr_EQ_0x1_21_THEN_0_CONC_ETC___d860,
	       IF_read_csr_csr_addr_EQ_0x1_9_THEN_0_CONCAT_rg_ETC___d336,
	       IF_read_csr_port2_csr_addr_EQ_0x1_59_THEN_0_CO_ETC___d598,
	       y_avValue_fst__h8976;
  reg [29 : 0] CASE_new_priv0791_0b1_rg_stvec_BITS_30_TO_1_0b_ETC__q1;
  reg CASE_new_priv0791_0b1_rg_stvec_BIT_0_0b11_rg_m_ETC__q2,
      IF_interrupt_pending_cur_priv_EQ_0b0_983_THEN__ETC___d1990,
      IF_interrupt_pending_cur_priv_EQ_0b0_983_THEN__ETC___d2093;
  wire [63 : 0] x__h8408, x__h8516;
  wire [31 : 0] IF_IF_csr_trap_actions_nmi_THEN_0b11_ELSE_IF_c_ETC___d1484,
		IF_csr_ret_actions_from_priv_EQ_0b11_661_THEN__ETC___d1682,
		_theResult___fst__h12935,
		_theResult___fst__h13136,
		csr_mstatus_rg_mstatus_46_AND_INV_1_SL_0_CONCA_ETC___d1675,
		csr_mstatus_rg_mstatus_46_AND_INV_1_SL_1_CONCA_ETC___d1476,
		exc_pc___1__h12025,
		exc_pc__h11951,
		mask__h10973,
		mask__h10990,
		mask__h12956,
		mask__h12973,
		result__h8591,
		v__h10796,
		v__h5698,
		v__h5842,
		v__h5956,
		v__h7081,
		v__h7117,
		v__h7758,
		v__h7820,
		v__h7976,
		val__h10974,
		val__h10991,
		val__h12974,
		vector_offset__h11952,
		wordxl1__h7212,
		x__h10972,
		x__h10985,
		x__h11002,
		x__h12806,
		x__h12807,
		x__h12955,
		x__h12968,
		x__h12985,
		x__h9768,
		y__h10986,
		y__h11003,
		y__h12969,
		y__h12986,
		y_avValue_fst__h11908,
		y_avValue_fst__h11925,
		y_avValue_snd_snd__h11998;
  wire [22 : 0] fixed_up_val_23__h10840,
		fixed_up_val_23__h12869,
		fixed_up_val_23__h6007,
		fixed_up_val_23__h7253,
		fixed_up_val_23__h9209;
  wire [5 : 0] ie_from_x__h12919,
	       ie_to_x__h10890,
	       pie_from_x__h12920,
	       pie_to_x__h10891;
  wire [3 : 0] IF_NOT_csr_mip_fv_read__94_BIT_11_976_082_OR_N_ETC___d2171,
	       IF_NOT_csr_mip_fv_read__94_BIT_11_976_082_OR_N_ETC___d2173,
	       IF_NOT_csr_mip_fv_read__94_BIT_11_976_082_OR_N_ETC___d2174,
	       IF_NOT_csr_mip_fv_read__94_BIT_11_976_082_OR_N_ETC___d2176,
	       exc_code__h12648;
  wire [1 : 0] IF_csr_mstatus_rg_mstatus_46_BITS_12_TO_11_04__ETC___d906,
	       _theResult____h14614,
	       _theResult____h14826,
	       _theResult____h15038,
	       _theResult____h15250,
	       _theResult____h15462,
	       _theResult____h15674,
	       _theResult____h15886,
	       _theResult____h16098,
	       _theResult____h16310,
	       _theResult___fst__h10902,
	       new_priv__h10791,
	       to_y__h13135;
  wire NOT_access_permitted_1_csr_addr_ULT_0xC03_701__ETC___d1821,
       NOT_access_permitted_2_csr_addr_ULT_0xC03_826__ETC___d1944,
       NOT_cfg_verbosity_read__148_ULE_1_149___d1150,
       NOT_csr_mip_fv_read__94_BIT_0_060_151_OR_NOT_c_ETC___d2158,
       NOT_csr_mip_fv_read__94_BIT_11_976_082_OR_NOT__ETC___d2096,
       NOT_csr_mip_fv_read__94_BIT_11_976_082_OR_NOT__ETC___d2123,
       NOT_csr_mip_fv_read__94_BIT_11_976_082_OR_NOT__ETC___d2150,
       NOT_csr_mip_fv_read__94_BIT_1_027_124_OR_NOT_c_ETC___d2131,
       NOT_csr_mip_fv_read__94_BIT_3_994_097_OR_NOT_c_ETC___d2104,
       NOT_csr_mip_fv_read__94_BIT_5_038_133_OR_NOT_c_ETC___d2140,
       NOT_csr_mip_fv_read__94_BIT_7_005_106_OR_NOT_c_ETC___d2113,
       NOT_csr_mip_fv_read__94_BIT_8_049_142_OR_NOT_c_ETC___d2149,
       NOT_csr_mip_fv_read__94_BIT_9_016_115_OR_NOT_c_ETC___d2122,
       NOT_csr_trap_actions_nmi_499_AND_csr_trap_acti_ETC___d1606,
       NOT_mav_csr_write_csr_addr_ULT_0xB03_63_152_AN_ETC___d1159,
       b__h10989,
       b__h12972,
       csr_mip_fv_read__94_BIT_0_060_AND_csr_mie_fv_r_ETC___d2069,
       csr_mip_fv_read__94_BIT_11_976_AND_csr_mie_fv__ETC___d1993,
       csr_mip_fv_read__94_BIT_11_976_AND_csr_mie_fv__ETC___d2059,
       csr_mip_fv_read__94_BIT_1_027_AND_csr_mie_fv_r_ETC___d2036,
       csr_mip_fv_read__94_BIT_3_994_AND_csr_mie_fv_r_ETC___d2003,
       csr_mip_fv_read__94_BIT_4_071_AND_csr_mie_fv_r_ETC___d2080,
       csr_mip_fv_read__94_BIT_5_038_AND_csr_mie_fv_r_ETC___d2047,
       csr_mip_fv_read__94_BIT_7_005_AND_csr_mie_fv_r_ETC___d2014,
       csr_mip_fv_read__94_BIT_8_049_AND_csr_mie_fv_r_ETC___d2058,
       csr_mip_fv_read__94_BIT_9_016_AND_csr_mie_fv_r_ETC___d2025,
       csr_trap_actions_interrupt_AND_NOT_csr_trap_ac_ETC___d1508,
       csr_trap_actions_nmi_OR_NOT_csr_trap_actions_i_ETC___d1657,
       deleg_bit___1__h10911,
       deleg_bit___1__h10926,
       interrupt_pending_cur_priv_EQ_IF_rg_mideleg_75_ETC___d1982,
       interrupt_pending_cur_priv_EQ_IF_rg_mideleg_75_ETC___d2000,
       interrupt_pending_cur_priv_EQ_IF_rg_mideleg_75_ETC___d2011,
       interrupt_pending_cur_priv_EQ_IF_rg_mideleg_75_ETC___d2022,
       interrupt_pending_cur_priv_EQ_IF_rg_mideleg_75_ETC___d2033,
       interrupt_pending_cur_priv_EQ_IF_rg_mideleg_75_ETC___d2044,
       interrupt_pending_cur_priv_EQ_IF_rg_mideleg_75_ETC___d2055,
       interrupt_pending_cur_priv_EQ_IF_rg_mideleg_75_ETC___d2066,
       interrupt_pending_cur_priv_ULT_IF_rg_mideleg_7_ETC___d1981,
       interrupt_pending_cur_priv_ULT_IF_rg_mideleg_7_ETC___d1999,
       interrupt_pending_cur_priv_ULT_IF_rg_mideleg_7_ETC___d2010,
       interrupt_pending_cur_priv_ULT_IF_rg_mideleg_7_ETC___d2021,
       interrupt_pending_cur_priv_ULT_IF_rg_mideleg_7_ETC___d2032,
       interrupt_pending_cur_priv_ULT_IF_rg_mideleg_7_ETC___d2043,
       interrupt_pending_cur_priv_ULT_IF_rg_mideleg_7_ETC___d2054,
       interrupt_pending_cur_priv_ULT_IF_rg_mideleg_7_ETC___d2065,
       mav_csr_write_csr_addr_ULE_0x33F___d872,
       mav_csr_write_csr_addr_ULE_0xB1F___d864,
       mav_csr_write_csr_addr_ULE_0xB9F___d868,
       mav_csr_write_csr_addr_ULT_0x323_71_OR_NOT_mav_ETC___d1145,
       mav_csr_write_csr_addr_ULT_0x323___d871,
       mav_csr_write_csr_addr_ULT_0xB03_63_OR_NOT_mav_ETC___d1147,
       mav_csr_write_csr_addr_ULT_0xB03_63_OR_NOT_mav_ETC___d876,
       mav_csr_write_csr_addr_ULT_0xB03___d863,
       mav_csr_write_csr_addr_ULT_0xB83___d867,
       sd__h10839,
       sd__h12868,
       sd__h7252,
       sd__h9208;

  // action method server_reset_request_put
  assign RDY_server_reset_request_put = f_reset_rsps$FULL_N ;
  assign CAN_FIRE_server_reset_request_put = f_reset_rsps$FULL_N ;
  assign WILL_FIRE_server_reset_request_put = EN_server_reset_request_put ;

  // action method server_reset_response_get
  assign RDY_server_reset_response_get = rg_state && f_reset_rsps$EMPTY_N ;
  assign CAN_FIRE_server_reset_response_get =
	     rg_state && f_reset_rsps$EMPTY_N ;
  assign WILL_FIRE_server_reset_response_get = EN_server_reset_response_get ;

  // value method read_csr
  assign read_csr =
	     { read_csr_csr_addr >= 12'hC03 && read_csr_csr_addr <= 12'hC1F ||
	       read_csr_csr_addr >= 12'hC83 && read_csr_csr_addr <= 12'hC9F ||
	       read_csr_csr_addr >= 12'hB03 && read_csr_csr_addr <= 12'hB1F ||
	       read_csr_csr_addr >= 12'hB83 && read_csr_csr_addr <= 12'hB9F ||
	       read_csr_csr_addr >= 12'h323 && read_csr_csr_addr <= 12'h33F ||
	       read_csr_csr_addr == 12'h001 ||
	       read_csr_csr_addr == 12'h002 ||
	       read_csr_csr_addr == 12'h003 ||
	       read_csr_csr_addr == 12'hC00 ||
	       read_csr_csr_addr == 12'hC02 ||
	       read_csr_csr_addr == 12'hC80 ||
	       read_csr_csr_addr == 12'hC82 ||
	       read_csr_csr_addr == 12'h100 ||
	       read_csr_csr_addr == 12'h102 ||
	       read_csr_csr_addr == 12'h103 ||
	       read_csr_csr_addr == 12'h104 ||
	       read_csr_csr_addr == 12'h105 ||
	       read_csr_csr_addr == 12'h106 ||
	       read_csr_csr_addr == 12'h140 ||
	       read_csr_csr_addr == 12'h141 ||
	       read_csr_csr_addr == 12'h142 ||
	       read_csr_csr_addr == 12'h143 ||
	       read_csr_csr_addr == 12'h144 ||
	       read_csr_csr_addr == 12'h180 ||
	       read_csr_csr_addr == 12'h302 ||
	       read_csr_csr_addr == 12'h303 ||
	       read_csr_csr_addr == 12'hF11 ||
	       read_csr_csr_addr == 12'hF12 ||
	       read_csr_csr_addr == 12'hF13 ||
	       read_csr_csr_addr == 12'hF14 ||
	       read_csr_csr_addr == 12'h300 ||
	       read_csr_csr_addr == 12'h301 ||
	       read_csr_csr_addr == 12'h304 ||
	       read_csr_csr_addr == 12'h305 ||
	       read_csr_csr_addr == 12'h306 ||
	       read_csr_csr_addr == 12'h340 ||
	       read_csr_csr_addr == 12'h341 ||
	       read_csr_csr_addr == 12'h342 ||
	       read_csr_csr_addr == 12'h343 ||
	       read_csr_csr_addr == 12'h344 ||
	       read_csr_csr_addr == 12'hB00 ||
	       read_csr_csr_addr == 12'hB02 ||
	       read_csr_csr_addr == 12'hB80 ||
	       read_csr_csr_addr == 12'hB82 ||
	       read_csr_csr_addr == 12'h7A0 ||
	       read_csr_csr_addr == 12'h7A1 ||
	       read_csr_csr_addr == 12'h7A2 ||
	       read_csr_csr_addr == 12'h7A3,
	       (read_csr_csr_addr >= 12'hC03 &&
		read_csr_csr_addr <= 12'hC1F ||
		read_csr_csr_addr >= 12'hC83 &&
		read_csr_csr_addr <= 12'hC9F ||
		read_csr_csr_addr >= 12'hB03 &&
		read_csr_csr_addr <= 12'hB1F ||
		read_csr_csr_addr >= 12'hB83 &&
		read_csr_csr_addr <= 12'hB9F ||
		read_csr_csr_addr >= 12'h323 &&
		read_csr_csr_addr <= 12'h33F) ?
		 32'd0 :
		 IF_read_csr_csr_addr_EQ_0x1_9_THEN_0_CONCAT_rg_ETC___d336 } ;

  // value method read_csr_port2
  assign read_csr_port2 =
	     { read_csr_port2_csr_addr >= 12'hC03 &&
	       read_csr_port2_csr_addr <= 12'hC1F ||
	       read_csr_port2_csr_addr >= 12'hC83 &&
	       read_csr_port2_csr_addr <= 12'hC9F ||
	       read_csr_port2_csr_addr >= 12'hB03 &&
	       read_csr_port2_csr_addr <= 12'hB1F ||
	       read_csr_port2_csr_addr >= 12'hB83 &&
	       read_csr_port2_csr_addr <= 12'hB9F ||
	       read_csr_port2_csr_addr >= 12'h323 &&
	       read_csr_port2_csr_addr <= 12'h33F ||
	       read_csr_port2_csr_addr == 12'h001 ||
	       read_csr_port2_csr_addr == 12'h002 ||
	       read_csr_port2_csr_addr == 12'h003 ||
	       read_csr_port2_csr_addr == 12'hC00 ||
	       read_csr_port2_csr_addr == 12'hC02 ||
	       read_csr_port2_csr_addr == 12'hC80 ||
	       read_csr_port2_csr_addr == 12'hC82 ||
	       read_csr_port2_csr_addr == 12'h100 ||
	       read_csr_port2_csr_addr == 12'h102 ||
	       read_csr_port2_csr_addr == 12'h103 ||
	       read_csr_port2_csr_addr == 12'h104 ||
	       read_csr_port2_csr_addr == 12'h105 ||
	       read_csr_port2_csr_addr == 12'h106 ||
	       read_csr_port2_csr_addr == 12'h140 ||
	       read_csr_port2_csr_addr == 12'h141 ||
	       read_csr_port2_csr_addr == 12'h142 ||
	       read_csr_port2_csr_addr == 12'h143 ||
	       read_csr_port2_csr_addr == 12'h144 ||
	       read_csr_port2_csr_addr == 12'h180 ||
	       read_csr_port2_csr_addr == 12'h302 ||
	       read_csr_port2_csr_addr == 12'h303 ||
	       read_csr_port2_csr_addr == 12'hF11 ||
	       read_csr_port2_csr_addr == 12'hF12 ||
	       read_csr_port2_csr_addr == 12'hF13 ||
	       read_csr_port2_csr_addr == 12'hF14 ||
	       read_csr_port2_csr_addr == 12'h300 ||
	       read_csr_port2_csr_addr == 12'h301 ||
	       read_csr_port2_csr_addr == 12'h304 ||
	       read_csr_port2_csr_addr == 12'h305 ||
	       read_csr_port2_csr_addr == 12'h306 ||
	       read_csr_port2_csr_addr == 12'h340 ||
	       read_csr_port2_csr_addr == 12'h341 ||
	       read_csr_port2_csr_addr == 12'h342 ||
	       read_csr_port2_csr_addr == 12'h343 ||
	       read_csr_port2_csr_addr == 12'h344 ||
	       read_csr_port2_csr_addr == 12'hB00 ||
	       read_csr_port2_csr_addr == 12'hB02 ||
	       read_csr_port2_csr_addr == 12'hB80 ||
	       read_csr_port2_csr_addr == 12'hB82 ||
	       read_csr_port2_csr_addr == 12'h7A0 ||
	       read_csr_port2_csr_addr == 12'h7A1 ||
	       read_csr_port2_csr_addr == 12'h7A2 ||
	       read_csr_port2_csr_addr == 12'h7A3,
	       (read_csr_port2_csr_addr >= 12'hC03 &&
		read_csr_port2_csr_addr <= 12'hC1F ||
		read_csr_port2_csr_addr >= 12'hC83 &&
		read_csr_port2_csr_addr <= 12'hC9F ||
		read_csr_port2_csr_addr >= 12'hB03 &&
		read_csr_port2_csr_addr <= 12'hB1F ||
		read_csr_port2_csr_addr >= 12'hB83 &&
		read_csr_port2_csr_addr <= 12'hB9F ||
		read_csr_port2_csr_addr >= 12'h323 &&
		read_csr_port2_csr_addr <= 12'h33F) ?
		 32'd0 :
		 IF_read_csr_port2_csr_addr_EQ_0x1_59_THEN_0_CO_ETC___d598 } ;

  // actionvalue method mav_read_csr
  assign mav_read_csr =
	     { mav_read_csr_csr_addr >= 12'hC03 &&
	       mav_read_csr_csr_addr <= 12'hC1F ||
	       mav_read_csr_csr_addr >= 12'hC83 &&
	       mav_read_csr_csr_addr <= 12'hC9F ||
	       mav_read_csr_csr_addr >= 12'hB03 &&
	       mav_read_csr_csr_addr <= 12'hB1F ||
	       mav_read_csr_csr_addr >= 12'hB83 &&
	       mav_read_csr_csr_addr <= 12'hB9F ||
	       mav_read_csr_csr_addr >= 12'h323 &&
	       mav_read_csr_csr_addr <= 12'h33F ||
	       mav_read_csr_csr_addr == 12'h001 ||
	       mav_read_csr_csr_addr == 12'h002 ||
	       mav_read_csr_csr_addr == 12'h003 ||
	       mav_read_csr_csr_addr == 12'hC00 ||
	       mav_read_csr_csr_addr == 12'hC02 ||
	       mav_read_csr_csr_addr == 12'hC80 ||
	       mav_read_csr_csr_addr == 12'hC82 ||
	       mav_read_csr_csr_addr == 12'h100 ||
	       mav_read_csr_csr_addr == 12'h102 ||
	       mav_read_csr_csr_addr == 12'h103 ||
	       mav_read_csr_csr_addr == 12'h104 ||
	       mav_read_csr_csr_addr == 12'h105 ||
	       mav_read_csr_csr_addr == 12'h106 ||
	       mav_read_csr_csr_addr == 12'h140 ||
	       mav_read_csr_csr_addr == 12'h141 ||
	       mav_read_csr_csr_addr == 12'h142 ||
	       mav_read_csr_csr_addr == 12'h143 ||
	       mav_read_csr_csr_addr == 12'h144 ||
	       mav_read_csr_csr_addr == 12'h180 ||
	       mav_read_csr_csr_addr == 12'h302 ||
	       mav_read_csr_csr_addr == 12'h303 ||
	       mav_read_csr_csr_addr == 12'hF11 ||
	       mav_read_csr_csr_addr == 12'hF12 ||
	       mav_read_csr_csr_addr == 12'hF13 ||
	       mav_read_csr_csr_addr == 12'hF14 ||
	       mav_read_csr_csr_addr == 12'h300 ||
	       mav_read_csr_csr_addr == 12'h301 ||
	       mav_read_csr_csr_addr == 12'h304 ||
	       mav_read_csr_csr_addr == 12'h305 ||
	       mav_read_csr_csr_addr == 12'h306 ||
	       mav_read_csr_csr_addr == 12'h340 ||
	       mav_read_csr_csr_addr == 12'h341 ||
	       mav_read_csr_csr_addr == 12'h342 ||
	       mav_read_csr_csr_addr == 12'h343 ||
	       mav_read_csr_csr_addr == 12'h344 ||
	       mav_read_csr_csr_addr == 12'hB00 ||
	       mav_read_csr_csr_addr == 12'hB02 ||
	       mav_read_csr_csr_addr == 12'hB80 ||
	       mav_read_csr_csr_addr == 12'hB82 ||
	       mav_read_csr_csr_addr == 12'h7A0 ||
	       mav_read_csr_csr_addr == 12'h7A1 ||
	       mav_read_csr_csr_addr == 12'h7A2 ||
	       mav_read_csr_csr_addr == 12'h7A3,
	       (mav_read_csr_csr_addr >= 12'hC03 &&
		mav_read_csr_csr_addr <= 12'hC1F ||
		mav_read_csr_csr_addr >= 12'hC83 &&
		mav_read_csr_csr_addr <= 12'hC9F ||
		mav_read_csr_csr_addr >= 12'hB03 &&
		mav_read_csr_csr_addr <= 12'hB1F ||
		mav_read_csr_csr_addr >= 12'hB83 &&
		mav_read_csr_csr_addr <= 12'hB9F ||
		mav_read_csr_csr_addr >= 12'h323 &&
		mav_read_csr_csr_addr <= 12'h33F) ?
		 32'd0 :
		 IF_mav_read_csr_csr_addr_EQ_0x1_21_THEN_0_CONC_ETC___d860 } ;
  assign CAN_FIRE_mav_read_csr = 1'd1 ;
  assign WILL_FIRE_mav_read_csr = EN_mav_read_csr ;

  // actionvalue method mav_csr_write
  assign mav_csr_write =
	     NOT_mav_csr_write_csr_addr_ULT_0xB03_63_152_AN_ETC___d1159 ?
	       32'd0 :
	       y_avValue_fst__h8976 ;
  assign CAN_FIRE_mav_csr_write = 1'd1 ;
  assign WILL_FIRE_mav_csr_write = EN_mav_csr_write ;

  // value method read_frm
  assign read_frm = rg_frm ;

  // action method ma_update_fcsr_fflags
  assign CAN_FIRE_ma_update_fcsr_fflags = 1'd1 ;
  assign WILL_FIRE_ma_update_fcsr_fflags = EN_ma_update_fcsr_fflags ;

  // action method ma_update_mstatus_fs
  assign CAN_FIRE_ma_update_mstatus_fs = 1'd1 ;
  assign WILL_FIRE_ma_update_mstatus_fs = EN_ma_update_mstatus_fs ;

  // value method read_misa
  assign read_misa = 28'd68423981 ;

  // value method read_mstatus
  assign read_mstatus = csr_mstatus_rg_mstatus ;

  // value method read_sstatus
  assign read_sstatus =
	     { csr_mstatus_rg_mstatus[31],
	       11'd0,
	       csr_mstatus_rg_mstatus[19:18],
	       1'd0,
	       csr_mstatus_rg_mstatus[16:13],
	       4'd0,
	       csr_mstatus_rg_mstatus[8],
	       2'd0,
	       csr_mstatus_rg_mstatus[5:4],
	       2'd0,
	       csr_mstatus_rg_mstatus[1:0] } ;

  // value method read_ustatus
  assign read_ustatus =
	     { 27'd0,
	       csr_mstatus_rg_mstatus[4],
	       3'd0,
	       csr_mstatus_rg_mstatus[0] } ;

  // value method read_satp
  assign read_satp = rg_satp ;

  // actionvalue method csr_trap_actions
  assign csr_trap_actions =
	     { x__h9768, x__h12806, x__h12807, new_priv__h10791 } ;
  assign RDY_csr_trap_actions = 1'd1 ;
  assign CAN_FIRE_csr_trap_actions = 1'd1 ;
  assign WILL_FIRE_csr_trap_actions = EN_csr_trap_actions ;

  // actionvalue method csr_ret_actions
  assign csr_ret_actions =
	     (csr_ret_actions_from_priv == 2'b11) ?
	       { rg_mepc,
		 csr_mstatus_rg_mstatus_46_AND_INV_1_SL_0_CONCA_ETC___d1675[12:11],
		 _theResult___fst__h12935 } :
	       { rg_sepc, to_y__h13135, _theResult___fst__h13136 } ;
  assign RDY_csr_ret_actions = 1'd1 ;
  assign CAN_FIRE_csr_ret_actions = 1'd1 ;
  assign WILL_FIRE_csr_ret_actions = EN_csr_ret_actions ;

  // value method read_csr_minstret
  assign read_csr_minstret = rg_minstret ;

  // action method csr_minstret_incr
  assign CAN_FIRE_csr_minstret_incr = 1'd1 ;
  assign WILL_FIRE_csr_minstret_incr = EN_csr_minstret_incr ;

  // value method read_csr_mcycle
  assign read_csr_mcycle = rg_mcycle ;

  // value method read_csr_mtime
  assign read_csr_mtime = rg_mcycle ;

  // value method access_permitted_1
  assign access_permitted_1 =
	     NOT_access_permitted_1_csr_addr_ULT_0xC03_701__ETC___d1821 &&
	     (access_permitted_1_read_not_write ||
	      access_permitted_1_csr_addr[11:10] != 2'b11) ;

  // value method access_permitted_2
  assign access_permitted_2 =
	     NOT_access_permitted_2_csr_addr_ULT_0xC03_826__ETC___d1944 &&
	     (access_permitted_2_read_not_write ||
	      access_permitted_2_csr_addr[11:10] != 2'b11) ;

  // value method csr_counter_read_fault
  assign csr_counter_read_fault =
	     (csr_counter_read_fault_priv == 2'b01 ||
	      csr_counter_read_fault_priv == 2'b0) &&
	     (csr_counter_read_fault_csr_addr == 12'hC00 &&
	      !rg_mcounteren[0] ||
	      csr_counter_read_fault_csr_addr == 12'hC01 &&
	      !rg_mcounteren[1] ||
	      csr_counter_read_fault_csr_addr == 12'hC02 &&
	      !rg_mcounteren[2] ||
	      csr_counter_read_fault_csr_addr >= 12'hC03 &&
	      csr_counter_read_fault_csr_addr <= 12'hC1F ||
	      csr_counter_read_fault_csr_addr >= 12'hC83 &&
	      csr_counter_read_fault_csr_addr <= 12'hC9F) ;

  // value method csr_mip_read
  assign csr_mip_read = csr_mip$fv_read ;

  // action method m_external_interrupt_req
  assign CAN_FIRE_m_external_interrupt_req = 1'd1 ;
  assign WILL_FIRE_m_external_interrupt_req = 1'd1 ;

  // action method s_external_interrupt_req
  assign CAN_FIRE_s_external_interrupt_req = 1'd1 ;
  assign WILL_FIRE_s_external_interrupt_req = 1'd1 ;

  // action method timer_interrupt_req
  assign CAN_FIRE_timer_interrupt_req = 1'd1 ;
  assign WILL_FIRE_timer_interrupt_req = 1'd1 ;

  // action method software_interrupt_req
  assign CAN_FIRE_software_interrupt_req = 1'd1 ;
  assign WILL_FIRE_software_interrupt_req = 1'd1 ;

  // value method interrupt_pending
  assign interrupt_pending =
	     { csr_mip_fv_read__94_BIT_11_976_AND_csr_mie_fv__ETC___d2059 ||
	       csr_mip_fv_read__94_BIT_0_060_AND_csr_mie_fv_r_ETC___d2069 ||
	       csr_mip_fv_read__94_BIT_4_071_AND_csr_mie_fv_r_ETC___d2080,
	       IF_NOT_csr_mip_fv_read__94_BIT_11_976_082_OR_N_ETC___d2176 } ;

  // value method wfi_resume
  assign wfi_resume = (csr_mip$fv_read & csr_mie$fv_read) != 32'd0 ;

  // action method nmi_req
  assign CAN_FIRE_nmi_req = 1'd1 ;
  assign WILL_FIRE_nmi_req = 1'd1 ;

  // value method nmi_pending
  assign nmi_pending = rg_nmi ;

  // action method debug
  assign RDY_debug = 1'd1 ;
  assign CAN_FIRE_debug = 1'd1 ;
  assign WILL_FIRE_debug = EN_debug ;

  // submodule csr_mie
  mkCSR_MIE csr_mie(.CLK(CLK),
		    .RST_N(RST_N),
		    .fav_sie_write_misa(csr_mie$fav_sie_write_misa),
		    .fav_sie_write_wordxl(csr_mie$fav_sie_write_wordxl),
		    .fav_write_misa(csr_mie$fav_write_misa),
		    .fav_write_wordxl(csr_mie$fav_write_wordxl),
		    .EN_reset(csr_mie$EN_reset),
		    .EN_fav_write(csr_mie$EN_fav_write),
		    .EN_fav_sie_write(csr_mie$EN_fav_sie_write),
		    .fv_read(csr_mie$fv_read),
		    .fav_write(csr_mie$fav_write),
		    .fv_sie_read(csr_mie$fv_sie_read),
		    .fav_sie_write(csr_mie$fav_sie_write));

  // submodule csr_mip
  mkCSR_MIP csr_mip(.CLK(CLK),
		    .RST_N(RST_N),
		    .fav_sip_write_misa(csr_mip$fav_sip_write_misa),
		    .fav_sip_write_wordxl(csr_mip$fav_sip_write_wordxl),
		    .fav_write_misa(csr_mip$fav_write_misa),
		    .fav_write_wordxl(csr_mip$fav_write_wordxl),
		    .m_external_interrupt_req_req(csr_mip$m_external_interrupt_req_req),
		    .s_external_interrupt_req_req(csr_mip$s_external_interrupt_req_req),
		    .software_interrupt_req_req(csr_mip$software_interrupt_req_req),
		    .timer_interrupt_req_req(csr_mip$timer_interrupt_req_req),
		    .EN_reset(csr_mip$EN_reset),
		    .EN_fav_write(csr_mip$EN_fav_write),
		    .EN_fav_sip_write(csr_mip$EN_fav_sip_write),
		    .fv_read(csr_mip$fv_read),
		    .fav_write(csr_mip$fav_write),
		    .fv_sip_read(csr_mip$fv_sip_read),
		    .fav_sip_write(csr_mip$fav_sip_write));

  // submodule f_reset_rsps
  FIFO20 #(.guarded(32'd1)) f_reset_rsps(.RST(RST_N),
					 .CLK(CLK),
					 .ENQ(f_reset_rsps$ENQ),
					 .DEQ(f_reset_rsps$DEQ),
					 .CLR(f_reset_rsps$CLR),
					 .FULL_N(f_reset_rsps$FULL_N),
					 .EMPTY_N(f_reset_rsps$EMPTY_N));

  // submodule soc_map
  mkSoC_Map soc_map(.CLK(CLK),
		    .RST_N(RST_N),
		    .m_is_IO_addr_addr(soc_map$m_is_IO_addr_addr),
		    .m_is_mem_addr_addr(soc_map$m_is_mem_addr_addr),
		    .m_is_near_mem_IO_addr_addr(soc_map$m_is_near_mem_IO_addr_addr),
		    .m_near_mem_io_addr_base(),
		    .m_near_mem_io_addr_size(),
		    .m_near_mem_io_addr_lim(),
		    .m_plic_addr_base(),
		    .m_plic_addr_size(),
		    .m_plic_addr_lim(),
		    .m_uart0_addr_base(),
		    .m_uart0_addr_size(),
		    .m_uart0_addr_lim(),
		    .m_boot_rom_addr_base(),
		    .m_boot_rom_addr_size(),
		    .m_boot_rom_addr_lim(),
		    .m_mem0_controller_addr_base(),
		    .m_mem0_controller_addr_size(),
		    .m_mem0_controller_addr_lim(),
		    .m_tcm_addr_base(),
		    .m_tcm_addr_size(),
		    .m_tcm_addr_lim(),
		    .m_is_mem_addr(),
		    .m_is_IO_addr(),
		    .m_is_near_mem_IO_addr(),
		    .m_pc_reset_value(),
		    .m_mtvec_reset_value(soc_map$m_mtvec_reset_value),
		    .m_nmivec_reset_value(soc_map$m_nmivec_reset_value));

  // rule RL_rl_reset_start
  assign CAN_FIRE_RL_rl_reset_start = !rg_state ;
  assign WILL_FIRE_RL_rl_reset_start = MUX_rg_state$write_1__SEL_2 ;

  // rule RL_rl_mcycle_incr
  assign CAN_FIRE_RL_rl_mcycle_incr = 1'd1 ;
  assign WILL_FIRE_RL_rl_mcycle_incr = 1'd1 ;

  // rule RL_rl_upd_minstret_csrrx
  assign CAN_FIRE_RL_rl_upd_minstret_csrrx =
	     MUX_rw_minstret$wset_1__SEL_1 || WILL_FIRE_RL_rl_reset_start ;
  assign WILL_FIRE_RL_rl_upd_minstret_csrrx =
	     CAN_FIRE_RL_rl_upd_minstret_csrrx ;

  // rule RL_rl_upd_minstret_incr
  assign CAN_FIRE_RL_rl_upd_minstret_incr =
	     !CAN_FIRE_RL_rl_upd_minstret_csrrx && EN_csr_minstret_incr ;
  assign WILL_FIRE_RL_rl_upd_minstret_incr =
	     CAN_FIRE_RL_rl_upd_minstret_incr ;

  // inputs to muxes for submodule ports
  assign MUX_csr_mstatus_rg_mstatus$write_1__SEL_5 =
	     EN_mav_csr_write &&
	     mav_csr_write_csr_addr_ULT_0xB03_63_OR_NOT_mav_ETC___d876 &&
	     (mav_csr_write_csr_addr == 12'h100 ||
	      mav_csr_write_csr_addr == 12'h300) ;
  assign MUX_rg_fflags$write_1__SEL_2 =
	     EN_mav_csr_write &&
	     mav_csr_write_csr_addr_ULT_0xB03_63_OR_NOT_mav_ETC___d876 &&
	     (mav_csr_write_csr_addr == 12'h001 ||
	      mav_csr_write_csr_addr == 12'h003) ;
  assign MUX_rg_frm$write_1__SEL_1 =
	     EN_mav_csr_write &&
	     mav_csr_write_csr_addr_ULT_0xB03_63_OR_NOT_mav_ETC___d876 &&
	     (mav_csr_write_csr_addr == 12'h002 ||
	      mav_csr_write_csr_addr == 12'h003) ;
  assign MUX_rg_mcause$write_1__SEL_2 =
	     EN_csr_trap_actions &&
	     (csr_trap_actions_nmi || new_priv__h10791 == 2'b11) ;
  assign MUX_rg_mcause$write_1__SEL_3 =
	     EN_mav_csr_write &&
	     mav_csr_write_csr_addr_ULT_0xB03_63_OR_NOT_mav_ETC___d876 &&
	     mav_csr_write_csr_addr == 12'h342 ;
  assign MUX_rg_mcounteren$write_1__SEL_1 =
	     EN_mav_csr_write &&
	     mav_csr_write_csr_addr_ULT_0xB03_63_OR_NOT_mav_ETC___d876 &&
	     mav_csr_write_csr_addr == 12'h306 ;
  assign MUX_rg_medeleg$write_1__SEL_1 =
	     EN_mav_csr_write &&
	     mav_csr_write_csr_addr_ULT_0xB03_63_OR_NOT_mav_ETC___d876 &&
	     mav_csr_write_csr_addr == 12'h302 ;
  assign MUX_rg_mideleg$write_1__SEL_1 =
	     EN_mav_csr_write &&
	     mav_csr_write_csr_addr_ULT_0xB03_63_OR_NOT_mav_ETC___d876 &&
	     mav_csr_write_csr_addr == 12'h303 ;
  assign MUX_rg_mtvec$write_1__SEL_1 =
	     EN_mav_csr_write &&
	     mav_csr_write_csr_addr_ULT_0xB03_63_OR_NOT_mav_ETC___d876 &&
	     mav_csr_write_csr_addr == 12'h305 ;
  assign MUX_rg_satp$write_1__SEL_1 =
	     EN_mav_csr_write &&
	     mav_csr_write_csr_addr_ULT_0xB03_63_OR_NOT_mav_ETC___d876 &&
	     mav_csr_write_csr_addr == 12'h180 ;
  assign MUX_rg_scause$write_1__SEL_2 =
	     EN_csr_trap_actions && !csr_trap_actions_nmi &&
	     new_priv__h10791 == 2'b01 ;
  assign MUX_rg_scause$write_1__SEL_3 =
	     EN_mav_csr_write &&
	     mav_csr_write_csr_addr_ULT_0xB03_63_OR_NOT_mav_ETC___d876 &&
	     mav_csr_write_csr_addr == 12'h142 ;
  assign MUX_rg_sepc$write_1__SEL_1 =
	     EN_mav_csr_write &&
	     mav_csr_write_csr_addr_ULT_0xB03_63_OR_NOT_mav_ETC___d876 &&
	     mav_csr_write_csr_addr == 12'h141 ;
  assign MUX_rg_state$write_1__SEL_2 =
	     CAN_FIRE_RL_rl_reset_start && !EN_mav_csr_write ;
  assign MUX_rg_stval$write_1__SEL_1 =
	     EN_mav_csr_write &&
	     mav_csr_write_csr_addr_ULT_0xB03_63_OR_NOT_mav_ETC___d876 &&
	     mav_csr_write_csr_addr == 12'h143 ;
  assign MUX_rg_stvec$write_1__SEL_1 =
	     EN_mav_csr_write &&
	     mav_csr_write_csr_addr_ULT_0xB03_63_OR_NOT_mav_ETC___d876 &&
	     mav_csr_write_csr_addr == 12'h105 ;
  assign MUX_rg_tdata1$write_1__SEL_1 =
	     EN_mav_csr_write &&
	     mav_csr_write_csr_addr_ULT_0xB03_63_OR_NOT_mav_ETC___d876 &&
	     mav_csr_write_csr_addr == 12'h7A1 ;
  assign MUX_rw_minstret$wset_1__SEL_1 =
	     EN_mav_csr_write &&
	     mav_csr_write_csr_addr_ULT_0xB03_63_OR_NOT_mav_ETC___d876 &&
	     (mav_csr_write_csr_addr == 12'hB02 ||
	      mav_csr_write_csr_addr == 12'hB82) ;
  assign MUX_csr_mstatus_rg_mstatus$write_1__VAL_2 =
	     { sd__h12868, 8'd0, fixed_up_val_23__h12869 } ;
  assign MUX_csr_mstatus_rg_mstatus$write_1__VAL_4 =
	     { sd__h9208, 8'd0, fixed_up_val_23__h9209 } ;
  assign MUX_csr_mstatus_rg_mstatus$write_1__VAL_5 =
	     { sd__h7252,
	       8'd0,
	       (mav_csr_write_csr_addr == 12'h100) ?
		 fixed_up_val_23__h6007 :
		 fixed_up_val_23__h7253 } ;
  assign MUX_rg_fflags$write_1__VAL_3 =
	     rg_fflags | ma_update_fcsr_fflags_flags ;
  assign MUX_rg_frm$write_1__VAL_1 =
	     (mav_csr_write_csr_addr == 12'h002) ?
	       mav_csr_write_word[2:0] :
	       mav_csr_write_word[7:5] ;
  assign MUX_rg_mcause$write_1__VAL_2 =
	     { !csr_trap_actions_nmi && csr_trap_actions_interrupt,
	       exc_code__h12648 } ;
  assign MUX_rg_mcause$write_1__VAL_3 =
	     { mav_csr_write_word[31], mav_csr_write_word[3:0] } ;
  assign MUX_rg_medeleg$write_1__VAL_1 =
	     { mav_csr_write_word[15],
	       1'd0,
	       mav_csr_write_word[13:12],
	       2'd0,
	       mav_csr_write_word[9:0] } ;
  assign MUX_rg_minstret$write_1__VAL_1 =
	     MUX_rw_minstret$wset_1__SEL_1 ?
	       MUX_rw_minstret$wset_1__VAL_1 :
	       64'd0 ;
  assign MUX_rg_minstret$write_1__VAL_2 = rg_minstret + 64'd1 ;
  assign MUX_rg_mtvec$write_1__VAL_1 =
	     { mav_csr_write_word[31:2], mav_csr_write_word[0] } ;
  assign MUX_rg_mtvec$write_1__VAL_2 =
	     { soc_map$m_mtvec_reset_value[31:2],
	       soc_map$m_mtvec_reset_value[0] } ;
  assign MUX_rw_minstret$wset_1__VAL_1 =
	     (mav_csr_write_csr_addr == 12'hB02) ? x__h8408 : x__h8516 ;

  // register cfg_verbosity
  assign cfg_verbosity$D_IN = 4'h0 ;
  assign cfg_verbosity$EN = 1'b0 ;

  // register csr_mstatus_rg_mstatus
  always@(WILL_FIRE_RL_rl_reset_start or
	  EN_csr_ret_actions or
	  MUX_csr_mstatus_rg_mstatus$write_1__VAL_2 or
	  EN_csr_trap_actions or
	  v__h10796 or
	  EN_ma_update_mstatus_fs or
	  MUX_csr_mstatus_rg_mstatus$write_1__VAL_4 or
	  MUX_csr_mstatus_rg_mstatus$write_1__SEL_5 or
	  MUX_csr_mstatus_rg_mstatus$write_1__VAL_5)
  case (1'b1)
    WILL_FIRE_RL_rl_reset_start: csr_mstatus_rg_mstatus$D_IN = 32'd8192;
    EN_csr_ret_actions:
	csr_mstatus_rg_mstatus$D_IN =
	    MUX_csr_mstatus_rg_mstatus$write_1__VAL_2;
    EN_csr_trap_actions: csr_mstatus_rg_mstatus$D_IN = v__h10796;
    EN_ma_update_mstatus_fs:
	csr_mstatus_rg_mstatus$D_IN =
	    MUX_csr_mstatus_rg_mstatus$write_1__VAL_4;
    MUX_csr_mstatus_rg_mstatus$write_1__SEL_5:
	csr_mstatus_rg_mstatus$D_IN =
	    MUX_csr_mstatus_rg_mstatus$write_1__VAL_5;
    default: csr_mstatus_rg_mstatus$D_IN =
		 32'hAAAAAAAA /* unspecified value */ ;
  endcase
  assign csr_mstatus_rg_mstatus$EN =
	     EN_mav_csr_write &&
	     mav_csr_write_csr_addr_ULT_0xB03_63_OR_NOT_mav_ETC___d876 &&
	     (mav_csr_write_csr_addr == 12'h100 ||
	      mav_csr_write_csr_addr == 12'h300) ||
	     EN_csr_trap_actions ||
	     EN_ma_update_mstatus_fs ||
	     EN_csr_ret_actions ||
	     WILL_FIRE_RL_rl_reset_start ;

  // register rg_dcsr
  assign rg_dcsr$D_IN = 32'h0 ;
  assign rg_dcsr$EN = 1'b0 ;

  // register rg_dpc
  assign rg_dpc$D_IN = 32'h0 ;
  assign rg_dpc$EN = 1'b0 ;

  // register rg_dscratch0
  assign rg_dscratch0$D_IN = 32'h0 ;
  assign rg_dscratch0$EN = 1'b0 ;

  // register rg_dscratch1
  assign rg_dscratch1$D_IN = 32'h0 ;
  assign rg_dscratch1$EN = 1'b0 ;

  // register rg_fflags
  always@(WILL_FIRE_RL_rl_reset_start or
	  MUX_rg_fflags$write_1__SEL_2 or
	  mav_csr_write_word or
	  EN_ma_update_fcsr_fflags or MUX_rg_fflags$write_1__VAL_3)
  case (1'b1)
    WILL_FIRE_RL_rl_reset_start: rg_fflags$D_IN = 5'd0;
    MUX_rg_fflags$write_1__SEL_2: rg_fflags$D_IN = mav_csr_write_word[4:0];
    EN_ma_update_fcsr_fflags: rg_fflags$D_IN = MUX_rg_fflags$write_1__VAL_3;
    default: rg_fflags$D_IN = 5'b01010 /* unspecified value */ ;
  endcase
  assign rg_fflags$EN =
	     EN_mav_csr_write &&
	     mav_csr_write_csr_addr_ULT_0xB03_63_OR_NOT_mav_ETC___d876 &&
	     (mav_csr_write_csr_addr == 12'h001 ||
	      mav_csr_write_csr_addr == 12'h003) ||
	     EN_ma_update_fcsr_fflags ||
	     WILL_FIRE_RL_rl_reset_start ;

  // register rg_frm
  assign rg_frm$D_IN =
	     MUX_rg_frm$write_1__SEL_1 ? MUX_rg_frm$write_1__VAL_1 : 3'd0 ;
  assign rg_frm$EN =
	     EN_mav_csr_write &&
	     mav_csr_write_csr_addr_ULT_0xB03_63_OR_NOT_mav_ETC___d876 &&
	     (mav_csr_write_csr_addr == 12'h002 ||
	      mav_csr_write_csr_addr == 12'h003) ||
	     WILL_FIRE_RL_rl_reset_start ;

  // register rg_mcause
  always@(WILL_FIRE_RL_rl_reset_start or
	  MUX_rg_mcause$write_1__SEL_2 or
	  MUX_rg_mcause$write_1__VAL_2 or
	  MUX_rg_mcause$write_1__SEL_3 or MUX_rg_mcause$write_1__VAL_3)
  case (1'b1)
    WILL_FIRE_RL_rl_reset_start: rg_mcause$D_IN = 5'd0;
    MUX_rg_mcause$write_1__SEL_2:
	rg_mcause$D_IN = MUX_rg_mcause$write_1__VAL_2;
    MUX_rg_mcause$write_1__SEL_3:
	rg_mcause$D_IN = MUX_rg_mcause$write_1__VAL_3;
    default: rg_mcause$D_IN = 5'b01010 /* unspecified value */ ;
  endcase
  assign rg_mcause$EN =
	     EN_csr_trap_actions &&
	     (csr_trap_actions_nmi || new_priv__h10791 == 2'b11) ||
	     EN_mav_csr_write &&
	     mav_csr_write_csr_addr_ULT_0xB03_63_OR_NOT_mav_ETC___d876 &&
	     mav_csr_write_csr_addr == 12'h342 ||
	     WILL_FIRE_RL_rl_reset_start ;

  // register rg_mcounteren
  assign rg_mcounteren$D_IN =
	     MUX_rg_mcounteren$write_1__SEL_1 ?
	       mav_csr_write_word[2:0] :
	       3'd0 ;
  assign rg_mcounteren$EN =
	     EN_mav_csr_write &&
	     mav_csr_write_csr_addr_ULT_0xB03_63_OR_NOT_mav_ETC___d876 &&
	     mav_csr_write_csr_addr == 12'h306 ||
	     WILL_FIRE_RL_rl_reset_start ;

  // register rg_mcycle
  assign rg_mcycle$D_IN = rg_mcycle + 64'd1 ;
  assign rg_mcycle$EN = 1'd1 ;

  // register rg_medeleg
  assign rg_medeleg$D_IN =
	     MUX_rg_medeleg$write_1__SEL_1 ?
	       MUX_rg_medeleg$write_1__VAL_1 :
	       16'd0 ;
  assign rg_medeleg$EN =
	     EN_mav_csr_write &&
	     mav_csr_write_csr_addr_ULT_0xB03_63_OR_NOT_mav_ETC___d876 &&
	     mav_csr_write_csr_addr == 12'h302 ||
	     WILL_FIRE_RL_rl_reset_start ;

  // register rg_mepc
  assign rg_mepc$D_IN =
	     MUX_rg_mcause$write_1__SEL_2 ?
	       csr_trap_actions_pc :
	       mav_csr_write_word ;
  assign rg_mepc$EN =
	     EN_csr_trap_actions &&
	     (csr_trap_actions_nmi || new_priv__h10791 == 2'b11) ||
	     EN_mav_csr_write &&
	     mav_csr_write_csr_addr_ULT_0xB03_63_OR_NOT_mav_ETC___d876 &&
	     mav_csr_write_csr_addr == 12'h341 ;

  // register rg_mideleg
  assign rg_mideleg$D_IN =
	     MUX_rg_mideleg$write_1__SEL_1 ?
	       mav_csr_write_word[11:0] :
	       12'd0 ;
  assign rg_mideleg$EN =
	     EN_mav_csr_write &&
	     mav_csr_write_csr_addr_ULT_0xB03_63_OR_NOT_mav_ETC___d876 &&
	     mav_csr_write_csr_addr == 12'h303 ||
	     WILL_FIRE_RL_rl_reset_start ;

  // register rg_minstret
  assign rg_minstret$D_IN =
	     WILL_FIRE_RL_rl_upd_minstret_csrrx ?
	       MUX_rg_minstret$write_1__VAL_1 :
	       MUX_rg_minstret$write_1__VAL_2 ;
  assign rg_minstret$EN =
	     WILL_FIRE_RL_rl_upd_minstret_csrrx ||
	     WILL_FIRE_RL_rl_upd_minstret_incr ;

  // register rg_mscratch
  assign rg_mscratch$D_IN = mav_csr_write_word ;
  assign rg_mscratch$EN =
	     EN_mav_csr_write &&
	     mav_csr_write_csr_addr_ULT_0xB03_63_OR_NOT_mav_ETC___d876 &&
	     mav_csr_write_csr_addr == 12'h340 ;

  // register rg_mtval
  assign rg_mtval$D_IN =
	     MUX_rg_mcause$write_1__SEL_2 ?
	       csr_trap_actions_xtval :
	       mav_csr_write_word ;
  assign rg_mtval$EN =
	     EN_csr_trap_actions &&
	     (csr_trap_actions_nmi || new_priv__h10791 == 2'b11) ||
	     EN_mav_csr_write &&
	     mav_csr_write_csr_addr_ULT_0xB03_63_OR_NOT_mav_ETC___d876 &&
	     mav_csr_write_csr_addr == 12'h343 ;

  // register rg_mtvec
  assign rg_mtvec$D_IN =
	     MUX_rg_mtvec$write_1__SEL_1 ?
	       MUX_rg_mtvec$write_1__VAL_1 :
	       MUX_rg_mtvec$write_1__VAL_2 ;
  assign rg_mtvec$EN =
	     EN_mav_csr_write &&
	     mav_csr_write_csr_addr_ULT_0xB03_63_OR_NOT_mav_ETC___d876 &&
	     mav_csr_write_csr_addr == 12'h305 ||
	     WILL_FIRE_RL_rl_reset_start ;

  // register rg_nmi
  assign rg_nmi$D_IN = !WILL_FIRE_RL_rl_reset_start && nmi_req_set_not_clear ;
  assign rg_nmi$EN = 1'b1 ;

  // register rg_nmi_vector
  assign rg_nmi_vector$D_IN = soc_map$m_nmivec_reset_value[31:0] ;
  assign rg_nmi_vector$EN = MUX_rg_state$write_1__SEL_2 ;

  // register rg_satp
  assign rg_satp$D_IN =
	     MUX_rg_satp$write_1__SEL_1 ? mav_csr_write_word : 32'd0 ;
  assign rg_satp$EN =
	     EN_mav_csr_write &&
	     mav_csr_write_csr_addr_ULT_0xB03_63_OR_NOT_mav_ETC___d876 &&
	     mav_csr_write_csr_addr == 12'h180 ||
	     WILL_FIRE_RL_rl_reset_start ;

  // register rg_scause
  always@(WILL_FIRE_RL_rl_reset_start or
	  MUX_rg_scause$write_1__SEL_2 or
	  MUX_rg_mcause$write_1__VAL_2 or
	  MUX_rg_scause$write_1__SEL_3 or MUX_rg_mcause$write_1__VAL_3)
  case (1'b1)
    WILL_FIRE_RL_rl_reset_start: rg_scause$D_IN = 5'd0;
    MUX_rg_scause$write_1__SEL_2:
	rg_scause$D_IN = MUX_rg_mcause$write_1__VAL_2;
    MUX_rg_scause$write_1__SEL_3:
	rg_scause$D_IN = MUX_rg_mcause$write_1__VAL_3;
    default: rg_scause$D_IN = 5'b01010 /* unspecified value */ ;
  endcase
  assign rg_scause$EN =
	     EN_mav_csr_write &&
	     mav_csr_write_csr_addr_ULT_0xB03_63_OR_NOT_mav_ETC___d876 &&
	     mav_csr_write_csr_addr == 12'h142 ||
	     EN_csr_trap_actions && !csr_trap_actions_nmi &&
	     new_priv__h10791 == 2'b01 ||
	     WILL_FIRE_RL_rl_reset_start ;

  // register rg_sepc
  assign rg_sepc$D_IN =
	     MUX_rg_sepc$write_1__SEL_1 ?
	       mav_csr_write_word :
	       csr_trap_actions_pc ;
  assign rg_sepc$EN =
	     EN_mav_csr_write &&
	     mav_csr_write_csr_addr_ULT_0xB03_63_OR_NOT_mav_ETC___d876 &&
	     mav_csr_write_csr_addr == 12'h141 ||
	     EN_csr_trap_actions && !csr_trap_actions_nmi &&
	     new_priv__h10791 == 2'b01 ;

  // register rg_sscratch
  assign rg_sscratch$D_IN = mav_csr_write_word ;
  assign rg_sscratch$EN =
	     EN_mav_csr_write &&
	     mav_csr_write_csr_addr_ULT_0xB03_63_OR_NOT_mav_ETC___d876 &&
	     mav_csr_write_csr_addr == 12'h140 ;

  // register rg_state
  assign rg_state$D_IN = !EN_server_reset_request_put ;
  assign rg_state$EN =
	     EN_server_reset_request_put || WILL_FIRE_RL_rl_reset_start ;

  // register rg_stval
  assign rg_stval$D_IN =
	     MUX_rg_stval$write_1__SEL_1 ?
	       mav_csr_write_word :
	       csr_trap_actions_xtval ;
  assign rg_stval$EN =
	     EN_mav_csr_write &&
	     mav_csr_write_csr_addr_ULT_0xB03_63_OR_NOT_mav_ETC___d876 &&
	     mav_csr_write_csr_addr == 12'h143 ||
	     EN_csr_trap_actions && !csr_trap_actions_nmi &&
	     new_priv__h10791 == 2'b01 ;

  // register rg_stvec
  assign rg_stvec$D_IN =
	     MUX_rg_stvec$write_1__SEL_1 ?
	       MUX_rg_mtvec$write_1__VAL_1 :
	       MUX_rg_mtvec$write_1__VAL_2 ;
  assign rg_stvec$EN =
	     EN_mav_csr_write &&
	     mav_csr_write_csr_addr_ULT_0xB03_63_OR_NOT_mav_ETC___d876 &&
	     mav_csr_write_csr_addr == 12'h105 ||
	     WILL_FIRE_RL_rl_reset_start ;

  // register rg_tdata1
  assign rg_tdata1$D_IN =
	     MUX_rg_tdata1$write_1__SEL_1 ? result__h8591 : 32'd0 ;
  assign rg_tdata1$EN =
	     EN_mav_csr_write &&
	     mav_csr_write_csr_addr_ULT_0xB03_63_OR_NOT_mav_ETC___d876 &&
	     mav_csr_write_csr_addr == 12'h7A1 ||
	     WILL_FIRE_RL_rl_reset_start ;

  // register rg_tdata2
  assign rg_tdata2$D_IN = mav_csr_write_word ;
  assign rg_tdata2$EN =
	     EN_mav_csr_write &&
	     mav_csr_write_csr_addr_ULT_0xB03_63_OR_NOT_mav_ETC___d876 &&
	     mav_csr_write_csr_addr == 12'h7A2 ;

  // register rg_tdata3
  assign rg_tdata3$D_IN = mav_csr_write_word ;
  assign rg_tdata3$EN =
	     EN_mav_csr_write &&
	     mav_csr_write_csr_addr_ULT_0xB03_63_OR_NOT_mav_ETC___d876 &&
	     mav_csr_write_csr_addr == 12'h7A3 ;

  // register rg_tselect
  assign rg_tselect$D_IN = 32'd0 ;
  assign rg_tselect$EN =
	     EN_mav_csr_write &&
	     mav_csr_write_csr_addr_ULT_0xB03_63_OR_NOT_mav_ETC___d876 &&
	     mav_csr_write_csr_addr == 12'h7A0 ||
	     WILL_FIRE_RL_rl_reset_start ;

  // submodule csr_mie
  assign csr_mie$fav_sie_write_misa = 28'd68423981 ;
  assign csr_mie$fav_sie_write_wordxl = mav_csr_write_word ;
  assign csr_mie$fav_write_misa = 28'd68423981 ;
  assign csr_mie$fav_write_wordxl = mav_csr_write_word ;
  assign csr_mie$EN_reset = MUX_rg_state$write_1__SEL_2 ;
  assign csr_mie$EN_fav_write =
	     EN_mav_csr_write &&
	     mav_csr_write_csr_addr_ULT_0xB03_63_OR_NOT_mav_ETC___d876 &&
	     mav_csr_write_csr_addr == 12'h304 ;
  assign csr_mie$EN_fav_sie_write =
	     EN_mav_csr_write &&
	     mav_csr_write_csr_addr_ULT_0xB03_63_OR_NOT_mav_ETC___d876 &&
	     mav_csr_write_csr_addr == 12'h104 ;

  // submodule csr_mip
  assign csr_mip$fav_sip_write_misa = 28'd68423981 ;
  assign csr_mip$fav_sip_write_wordxl = mav_csr_write_word ;
  assign csr_mip$fav_write_misa = 28'd68423981 ;
  assign csr_mip$fav_write_wordxl = mav_csr_write_word ;
  assign csr_mip$m_external_interrupt_req_req =
	     m_external_interrupt_req_set_not_clear ;
  assign csr_mip$s_external_interrupt_req_req =
	     s_external_interrupt_req_set_not_clear ;
  assign csr_mip$software_interrupt_req_req =
	     software_interrupt_req_set_not_clear ;
  assign csr_mip$timer_interrupt_req_req = timer_interrupt_req_set_not_clear ;
  assign csr_mip$EN_reset = MUX_rg_state$write_1__SEL_2 ;
  assign csr_mip$EN_fav_write =
	     EN_mav_csr_write &&
	     mav_csr_write_csr_addr_ULT_0xB03_63_OR_NOT_mav_ETC___d876 &&
	     mav_csr_write_csr_addr == 12'h344 ;
  assign csr_mip$EN_fav_sip_write =
	     EN_mav_csr_write &&
	     mav_csr_write_csr_addr_ULT_0xB03_63_OR_NOT_mav_ETC___d876 &&
	     mav_csr_write_csr_addr == 12'h144 ;

  // submodule f_reset_rsps
  assign f_reset_rsps$ENQ = EN_server_reset_request_put ;
  assign f_reset_rsps$DEQ = EN_server_reset_response_get ;
  assign f_reset_rsps$CLR = 1'b0 ;

  // submodule soc_map
  assign soc_map$m_is_IO_addr_addr = 64'h0 ;
  assign soc_map$m_is_mem_addr_addr = 64'h0 ;
  assign soc_map$m_is_near_mem_IO_addr_addr = 64'h0 ;

  // remaining internal signals
  assign IF_IF_csr_trap_actions_nmi_THEN_0b11_ELSE_IF_c_ETC___d1484 =
	     (new_priv__h10791 == 2'b11) ?
	       { csr_mstatus_rg_mstatus_46_AND_INV_1_SL_1_CONCA_ETC___d1476[31:13],
		 csr_trap_actions_from_priv,
		 csr_mstatus_rg_mstatus_46_AND_INV_1_SL_1_CONCA_ETC___d1476[10:0] } :
	       { csr_mstatus_rg_mstatus_46_AND_INV_1_SL_1_CONCA_ETC___d1476[31:9],
		 csr_trap_actions_from_priv[0],
		 csr_mstatus_rg_mstatus_46_AND_INV_1_SL_1_CONCA_ETC___d1476[7:0] } ;
  assign IF_NOT_csr_mip_fv_read__94_BIT_11_976_082_OR_N_ETC___d2171 =
	     (NOT_csr_mip_fv_read__94_BIT_11_976_082_OR_NOT__ETC___d2096 &&
	      NOT_csr_mip_fv_read__94_BIT_3_994_097_OR_NOT_c_ETC___d2104 &&
	      NOT_csr_mip_fv_read__94_BIT_7_005_106_OR_NOT_c_ETC___d2113) ?
	       4'd9 :
	       ((NOT_csr_mip_fv_read__94_BIT_11_976_082_OR_NOT__ETC___d2096 &&
		 NOT_csr_mip_fv_read__94_BIT_3_994_097_OR_NOT_c_ETC___d2104) ?
		  4'd7 :
		  (NOT_csr_mip_fv_read__94_BIT_11_976_082_OR_NOT__ETC___d2096 ?
		     4'd3 :
		     4'd11)) ;
  assign IF_NOT_csr_mip_fv_read__94_BIT_11_976_082_OR_N_ETC___d2173 =
	     (NOT_csr_mip_fv_read__94_BIT_11_976_082_OR_NOT__ETC___d2123 &&
	      NOT_csr_mip_fv_read__94_BIT_1_027_124_OR_NOT_c_ETC___d2131) ?
	       4'd5 :
	       (NOT_csr_mip_fv_read__94_BIT_11_976_082_OR_NOT__ETC___d2123 ?
		  4'd1 :
		  IF_NOT_csr_mip_fv_read__94_BIT_11_976_082_OR_N_ETC___d2171) ;
  assign IF_NOT_csr_mip_fv_read__94_BIT_11_976_082_OR_N_ETC___d2174 =
	     (NOT_csr_mip_fv_read__94_BIT_11_976_082_OR_NOT__ETC___d2123 &&
	      NOT_csr_mip_fv_read__94_BIT_1_027_124_OR_NOT_c_ETC___d2131 &&
	      NOT_csr_mip_fv_read__94_BIT_5_038_133_OR_NOT_c_ETC___d2140) ?
	       4'd8 :
	       IF_NOT_csr_mip_fv_read__94_BIT_11_976_082_OR_N_ETC___d2173 ;
  assign IF_NOT_csr_mip_fv_read__94_BIT_11_976_082_OR_N_ETC___d2176 =
	     (NOT_csr_mip_fv_read__94_BIT_11_976_082_OR_NOT__ETC___d2150 &&
	      NOT_csr_mip_fv_read__94_BIT_0_060_151_OR_NOT_c_ETC___d2158) ?
	       4'd4 :
	       (NOT_csr_mip_fv_read__94_BIT_11_976_082_OR_NOT__ETC___d2150 ?
		  4'd0 :
		  IF_NOT_csr_mip_fv_read__94_BIT_11_976_082_OR_N_ETC___d2174) ;
  assign IF_csr_mstatus_rg_mstatus_46_BITS_12_TO_11_04__ETC___d906 =
	     (csr_mstatus_rg_mstatus[12:11] == 2'b10) ?
	       2'b01 :
	       csr_mstatus_rg_mstatus[12:11] ;
  assign IF_csr_ret_actions_from_priv_EQ_0b11_661_THEN__ETC___d1682 =
	     (csr_ret_actions_from_priv == 2'b11) ?
	       _theResult___fst__h12935 :
	       _theResult___fst__h13136 ;
  assign NOT_access_permitted_1_csr_addr_ULT_0xC03_701__ETC___d1821 =
	     (access_permitted_1_csr_addr >= 12'hC03 &&
	      access_permitted_1_csr_addr <= 12'hC1F ||
	      access_permitted_1_csr_addr >= 12'hB03 &&
	      access_permitted_1_csr_addr <= 12'hB1F ||
	      access_permitted_1_csr_addr >= 12'hC83 &&
	      access_permitted_1_csr_addr <= 12'hC9F ||
	      access_permitted_1_csr_addr >= 12'hB83 &&
	      access_permitted_1_csr_addr <= 12'hB9F ||
	      access_permitted_1_csr_addr >= 12'h323 &&
	      access_permitted_1_csr_addr <= 12'h33F ||
	      access_permitted_1_csr_addr == 12'h001 ||
	      access_permitted_1_csr_addr == 12'h002 ||
	      access_permitted_1_csr_addr == 12'h003 ||
	      access_permitted_1_csr_addr == 12'hC00 ||
	      access_permitted_1_csr_addr == 12'hC02 ||
	      access_permitted_1_csr_addr == 12'hC80 ||
	      access_permitted_1_csr_addr == 12'hC81 ||
	      access_permitted_1_csr_addr == 12'hC82 ||
	      access_permitted_1_csr_addr == 12'h100 ||
	      access_permitted_1_csr_addr == 12'h102 ||
	      access_permitted_1_csr_addr == 12'h103 ||
	      access_permitted_1_csr_addr == 12'h104 ||
	      access_permitted_1_csr_addr == 12'h105 ||
	      access_permitted_1_csr_addr == 12'h106 ||
	      access_permitted_1_csr_addr == 12'h140 ||
	      access_permitted_1_csr_addr == 12'h141 ||
	      access_permitted_1_csr_addr == 12'h142 ||
	      access_permitted_1_csr_addr == 12'h143 ||
	      access_permitted_1_csr_addr == 12'h144 ||
	      access_permitted_1_csr_addr == 12'h180 ||
	      access_permitted_1_csr_addr == 12'h302 ||
	      access_permitted_1_csr_addr == 12'h303 ||
	      access_permitted_1_csr_addr == 12'hF11 ||
	      access_permitted_1_csr_addr == 12'hF12 ||
	      access_permitted_1_csr_addr == 12'hF13 ||
	      access_permitted_1_csr_addr == 12'hF14 ||
	      access_permitted_1_csr_addr == 12'h300 ||
	      access_permitted_1_csr_addr == 12'h301 ||
	      access_permitted_1_csr_addr == 12'h304 ||
	      access_permitted_1_csr_addr == 12'h305 ||
	      access_permitted_1_csr_addr == 12'h306 ||
	      access_permitted_1_csr_addr == 12'h340 ||
	      access_permitted_1_csr_addr == 12'h341 ||
	      access_permitted_1_csr_addr == 12'h342 ||
	      access_permitted_1_csr_addr == 12'h343 ||
	      access_permitted_1_csr_addr == 12'h344 ||
	      access_permitted_1_csr_addr == 12'hB00 ||
	      access_permitted_1_csr_addr == 12'hB02 ||
	      access_permitted_1_csr_addr == 12'hB80 ||
	      access_permitted_1_csr_addr == 12'hB82 ||
	      access_permitted_1_csr_addr == 12'h7A0 ||
	      access_permitted_1_csr_addr == 12'h7A1 ||
	      access_permitted_1_csr_addr == 12'h7A2 ||
	      access_permitted_1_csr_addr == 12'h7A3) &&
	     access_permitted_1_priv >= access_permitted_1_csr_addr[9:8] &&
	     (access_permitted_1_csr_addr != 12'h180 ||
	      !csr_mstatus_rg_mstatus[20]) ;
  assign NOT_access_permitted_2_csr_addr_ULT_0xC03_826__ETC___d1944 =
	     (access_permitted_2_csr_addr >= 12'hC03 &&
	      access_permitted_2_csr_addr <= 12'hC1F ||
	      access_permitted_2_csr_addr >= 12'hB03 &&
	      access_permitted_2_csr_addr <= 12'hB1F ||
	      access_permitted_2_csr_addr >= 12'hC83 &&
	      access_permitted_2_csr_addr <= 12'hC9F ||
	      access_permitted_2_csr_addr >= 12'hB83 &&
	      access_permitted_2_csr_addr <= 12'hB9F ||
	      access_permitted_2_csr_addr >= 12'h323 &&
	      access_permitted_2_csr_addr <= 12'h33F ||
	      access_permitted_2_csr_addr == 12'h001 ||
	      access_permitted_2_csr_addr == 12'h002 ||
	      access_permitted_2_csr_addr == 12'h003 ||
	      access_permitted_2_csr_addr == 12'hC00 ||
	      access_permitted_2_csr_addr == 12'hC02 ||
	      access_permitted_2_csr_addr == 12'hC80 ||
	      access_permitted_2_csr_addr == 12'hC81 ||
	      access_permitted_2_csr_addr == 12'hC82 ||
	      access_permitted_2_csr_addr == 12'h100 ||
	      access_permitted_2_csr_addr == 12'h102 ||
	      access_permitted_2_csr_addr == 12'h103 ||
	      access_permitted_2_csr_addr == 12'h104 ||
	      access_permitted_2_csr_addr == 12'h105 ||
	      access_permitted_2_csr_addr == 12'h106 ||
	      access_permitted_2_csr_addr == 12'h140 ||
	      access_permitted_2_csr_addr == 12'h141 ||
	      access_permitted_2_csr_addr == 12'h142 ||
	      access_permitted_2_csr_addr == 12'h143 ||
	      access_permitted_2_csr_addr == 12'h144 ||
	      access_permitted_2_csr_addr == 12'h180 ||
	      access_permitted_2_csr_addr == 12'h302 ||
	      access_permitted_2_csr_addr == 12'h303 ||
	      access_permitted_2_csr_addr == 12'hF11 ||
	      access_permitted_2_csr_addr == 12'hF12 ||
	      access_permitted_2_csr_addr == 12'hF13 ||
	      access_permitted_2_csr_addr == 12'hF14 ||
	      access_permitted_2_csr_addr == 12'h300 ||
	      access_permitted_2_csr_addr == 12'h301 ||
	      access_permitted_2_csr_addr == 12'h304 ||
	      access_permitted_2_csr_addr == 12'h305 ||
	      access_permitted_2_csr_addr == 12'h306 ||
	      access_permitted_2_csr_addr == 12'h340 ||
	      access_permitted_2_csr_addr == 12'h341 ||
	      access_permitted_2_csr_addr == 12'h342 ||
	      access_permitted_2_csr_addr == 12'h343 ||
	      access_permitted_2_csr_addr == 12'h344 ||
	      access_permitted_2_csr_addr == 12'hB00 ||
	      access_permitted_2_csr_addr == 12'hB02 ||
	      access_permitted_2_csr_addr == 12'hB80 ||
	      access_permitted_2_csr_addr == 12'hB82 ||
	      access_permitted_2_csr_addr == 12'h7A0 ||
	      access_permitted_2_csr_addr == 12'h7A1 ||
	      access_permitted_2_csr_addr == 12'h7A2 ||
	      access_permitted_2_csr_addr == 12'h7A3) &&
	     access_permitted_2_priv >= access_permitted_2_csr_addr[9:8] &&
	     (access_permitted_2_csr_addr != 12'h180 ||
	      !csr_mstatus_rg_mstatus[20]) ;
  assign NOT_cfg_verbosity_read__148_ULE_1_149___d1150 =
	     cfg_verbosity > 4'd1 ;
  assign NOT_csr_mip_fv_read__94_BIT_0_060_151_OR_NOT_c_ETC___d2158 =
	     !csr_mip$fv_read[0] || !csr_mie$fv_read[0] ||
	     !interrupt_pending_cur_priv_ULT_IF_rg_mideleg_7_ETC___d2065 &&
	     (!interrupt_pending_cur_priv_EQ_IF_rg_mideleg_75_ETC___d2066 ||
	      IF_interrupt_pending_cur_priv_EQ_0b0_983_THEN__ETC___d2093) ;
  assign NOT_csr_mip_fv_read__94_BIT_11_976_082_OR_NOT__ETC___d2096 =
	     !csr_mip$fv_read[11] || !csr_mie$fv_read[11] ||
	     !interrupt_pending_cur_priv_ULT_IF_rg_mideleg_7_ETC___d1981 &&
	     (!interrupt_pending_cur_priv_EQ_IF_rg_mideleg_75_ETC___d1982 ||
	      IF_interrupt_pending_cur_priv_EQ_0b0_983_THEN__ETC___d2093) ;
  assign NOT_csr_mip_fv_read__94_BIT_11_976_082_OR_NOT__ETC___d2123 =
	     NOT_csr_mip_fv_read__94_BIT_11_976_082_OR_NOT__ETC___d2096 &&
	     NOT_csr_mip_fv_read__94_BIT_3_994_097_OR_NOT_c_ETC___d2104 &&
	     NOT_csr_mip_fv_read__94_BIT_7_005_106_OR_NOT_c_ETC___d2113 &&
	     NOT_csr_mip_fv_read__94_BIT_9_016_115_OR_NOT_c_ETC___d2122 ;
  assign NOT_csr_mip_fv_read__94_BIT_11_976_082_OR_NOT__ETC___d2150 =
	     NOT_csr_mip_fv_read__94_BIT_11_976_082_OR_NOT__ETC___d2123 &&
	     NOT_csr_mip_fv_read__94_BIT_1_027_124_OR_NOT_c_ETC___d2131 &&
	     NOT_csr_mip_fv_read__94_BIT_5_038_133_OR_NOT_c_ETC___d2140 &&
	     NOT_csr_mip_fv_read__94_BIT_8_049_142_OR_NOT_c_ETC___d2149 ;
  assign NOT_csr_mip_fv_read__94_BIT_1_027_124_OR_NOT_c_ETC___d2131 =
	     !csr_mip$fv_read[1] || !csr_mie$fv_read[1] ||
	     !interrupt_pending_cur_priv_ULT_IF_rg_mideleg_7_ETC___d2032 &&
	     (!interrupt_pending_cur_priv_EQ_IF_rg_mideleg_75_ETC___d2033 ||
	      IF_interrupt_pending_cur_priv_EQ_0b0_983_THEN__ETC___d2093) ;
  assign NOT_csr_mip_fv_read__94_BIT_3_994_097_OR_NOT_c_ETC___d2104 =
	     !csr_mip$fv_read[3] || !csr_mie$fv_read[3] ||
	     !interrupt_pending_cur_priv_ULT_IF_rg_mideleg_7_ETC___d1999 &&
	     (!interrupt_pending_cur_priv_EQ_IF_rg_mideleg_75_ETC___d2000 ||
	      IF_interrupt_pending_cur_priv_EQ_0b0_983_THEN__ETC___d2093) ;
  assign NOT_csr_mip_fv_read__94_BIT_5_038_133_OR_NOT_c_ETC___d2140 =
	     !csr_mip$fv_read[5] || !csr_mie$fv_read[5] ||
	     !interrupt_pending_cur_priv_ULT_IF_rg_mideleg_7_ETC___d2043 &&
	     (!interrupt_pending_cur_priv_EQ_IF_rg_mideleg_75_ETC___d2044 ||
	      IF_interrupt_pending_cur_priv_EQ_0b0_983_THEN__ETC___d2093) ;
  assign NOT_csr_mip_fv_read__94_BIT_7_005_106_OR_NOT_c_ETC___d2113 =
	     !csr_mip$fv_read[7] || !csr_mie$fv_read[7] ||
	     !interrupt_pending_cur_priv_ULT_IF_rg_mideleg_7_ETC___d2010 &&
	     (!interrupt_pending_cur_priv_EQ_IF_rg_mideleg_75_ETC___d2011 ||
	      IF_interrupt_pending_cur_priv_EQ_0b0_983_THEN__ETC___d2093) ;
  assign NOT_csr_mip_fv_read__94_BIT_8_049_142_OR_NOT_c_ETC___d2149 =
	     !csr_mip$fv_read[8] || !csr_mie$fv_read[8] ||
	     !interrupt_pending_cur_priv_ULT_IF_rg_mideleg_7_ETC___d2054 &&
	     (!interrupt_pending_cur_priv_EQ_IF_rg_mideleg_75_ETC___d2055 ||
	      IF_interrupt_pending_cur_priv_EQ_0b0_983_THEN__ETC___d2093) ;
  assign NOT_csr_mip_fv_read__94_BIT_9_016_115_OR_NOT_c_ETC___d2122 =
	     !csr_mip$fv_read[9] || !csr_mie$fv_read[9] ||
	     !interrupt_pending_cur_priv_ULT_IF_rg_mideleg_7_ETC___d2021 &&
	     (!interrupt_pending_cur_priv_EQ_IF_rg_mideleg_75_ETC___d2022 ||
	      IF_interrupt_pending_cur_priv_EQ_0b0_983_THEN__ETC___d2093) ;
  assign NOT_csr_trap_actions_nmi_499_AND_csr_trap_acti_ETC___d1606 =
	     !csr_trap_actions_nmi && csr_trap_actions_interrupt &&
	     exc_code__h12648 != 4'd0 &&
	     exc_code__h12648 != 4'd1 &&
	     exc_code__h12648 != 4'd2 &&
	     exc_code__h12648 != 4'd3 &&
	     exc_code__h12648 != 4'd4 &&
	     exc_code__h12648 != 4'd5 &&
	     exc_code__h12648 != 4'd6 &&
	     exc_code__h12648 != 4'd7 &&
	     exc_code__h12648 != 4'd8 &&
	     exc_code__h12648 != 4'd9 &&
	     exc_code__h12648 != 4'd10 &&
	     exc_code__h12648 != 4'd11 ;
  assign NOT_mav_csr_write_csr_addr_ULT_0xB03_63_152_AN_ETC___d1159 =
	     !mav_csr_write_csr_addr_ULT_0xB03___d863 &&
	     mav_csr_write_csr_addr_ULE_0xB1F___d864 ||
	     !mav_csr_write_csr_addr_ULT_0xB83___d867 &&
	     mav_csr_write_csr_addr_ULE_0xB9F___d868 ||
	     !mav_csr_write_csr_addr_ULT_0x323___d871 &&
	     mav_csr_write_csr_addr_ULE_0x33F___d872 ;
  assign _theResult____h14614 = rg_mideleg[11] ? 2'b01 : 2'b11 ;
  assign _theResult____h14826 = rg_mideleg[3] ? 2'b01 : 2'b11 ;
  assign _theResult____h15038 = rg_mideleg[7] ? 2'b01 : 2'b11 ;
  assign _theResult____h15250 = rg_mideleg[9] ? 2'b01 : 2'b11 ;
  assign _theResult____h15462 = rg_mideleg[1] ? 2'b01 : 2'b11 ;
  assign _theResult____h15674 = rg_mideleg[5] ? 2'b01 : 2'b11 ;
  assign _theResult____h15886 = rg_mideleg[8] ? 2'b01 : 2'b11 ;
  assign _theResult____h16098 = rg_mideleg[0] ? 2'b01 : 2'b11 ;
  assign _theResult____h16310 = rg_mideleg[4] ? 2'b01 : 2'b11 ;
  assign _theResult___fst__h10902 =
	     (csr_trap_actions_interrupt ?
		deleg_bit___1__h10911 :
		deleg_bit___1__h10926) ?
	       2'b01 :
	       2'b11 ;
  assign _theResult___fst__h12935 =
	     { csr_mstatus_rg_mstatus_46_AND_INV_1_SL_0_CONCA_ETC___d1675[31:13],
	       2'd0,
	       csr_mstatus_rg_mstatus_46_AND_INV_1_SL_0_CONCA_ETC___d1675[10:0] } ;
  assign _theResult___fst__h13136 =
	     { csr_mstatus_rg_mstatus_46_AND_INV_1_SL_0_CONCA_ETC___d1675[31:9],
	       1'd0,
	       csr_mstatus_rg_mstatus_46_AND_INV_1_SL_0_CONCA_ETC___d1675[7:0] } ;
  assign b__h10989 = csr_mstatus_rg_mstatus[new_priv__h10791] ;
  assign b__h12972 =
	     csr_mstatus_rg_mstatus[{ 3'd1, csr_ret_actions_from_priv }] ;
  assign csr_mip_fv_read__94_BIT_0_060_AND_csr_mie_fv_r_ETC___d2069 =
	     csr_mip$fv_read[0] && csr_mie$fv_read[0] &&
	     (interrupt_pending_cur_priv_ULT_IF_rg_mideleg_7_ETC___d2065 ||
	      interrupt_pending_cur_priv_EQ_IF_rg_mideleg_75_ETC___d2066 &&
	      IF_interrupt_pending_cur_priv_EQ_0b0_983_THEN__ETC___d1990) ;
  assign csr_mip_fv_read__94_BIT_11_976_AND_csr_mie_fv__ETC___d1993 =
	     csr_mip$fv_read[11] && csr_mie$fv_read[11] &&
	     (interrupt_pending_cur_priv_ULT_IF_rg_mideleg_7_ETC___d1981 ||
	      interrupt_pending_cur_priv_EQ_IF_rg_mideleg_75_ETC___d1982 &&
	      IF_interrupt_pending_cur_priv_EQ_0b0_983_THEN__ETC___d1990) ;
  assign csr_mip_fv_read__94_BIT_11_976_AND_csr_mie_fv__ETC___d2059 =
	     csr_mip_fv_read__94_BIT_11_976_AND_csr_mie_fv__ETC___d1993 ||
	     csr_mip_fv_read__94_BIT_3_994_AND_csr_mie_fv_r_ETC___d2003 ||
	     csr_mip_fv_read__94_BIT_7_005_AND_csr_mie_fv_r_ETC___d2014 ||
	     csr_mip_fv_read__94_BIT_9_016_AND_csr_mie_fv_r_ETC___d2025 ||
	     csr_mip_fv_read__94_BIT_1_027_AND_csr_mie_fv_r_ETC___d2036 ||
	     csr_mip_fv_read__94_BIT_5_038_AND_csr_mie_fv_r_ETC___d2047 ||
	     csr_mip_fv_read__94_BIT_8_049_AND_csr_mie_fv_r_ETC___d2058 ;
  assign csr_mip_fv_read__94_BIT_1_027_AND_csr_mie_fv_r_ETC___d2036 =
	     csr_mip$fv_read[1] && csr_mie$fv_read[1] &&
	     (interrupt_pending_cur_priv_ULT_IF_rg_mideleg_7_ETC___d2032 ||
	      interrupt_pending_cur_priv_EQ_IF_rg_mideleg_75_ETC___d2033 &&
	      IF_interrupt_pending_cur_priv_EQ_0b0_983_THEN__ETC___d1990) ;
  assign csr_mip_fv_read__94_BIT_3_994_AND_csr_mie_fv_r_ETC___d2003 =
	     csr_mip$fv_read[3] && csr_mie$fv_read[3] &&
	     (interrupt_pending_cur_priv_ULT_IF_rg_mideleg_7_ETC___d1999 ||
	      interrupt_pending_cur_priv_EQ_IF_rg_mideleg_75_ETC___d2000 &&
	      IF_interrupt_pending_cur_priv_EQ_0b0_983_THEN__ETC___d1990) ;
  assign csr_mip_fv_read__94_BIT_4_071_AND_csr_mie_fv_r_ETC___d2080 =
	     csr_mip$fv_read[4] && csr_mie$fv_read[4] &&
	     (interrupt_pending_cur_priv < _theResult____h16310 ||
	      interrupt_pending_cur_priv == _theResult____h16310 &&
	      IF_interrupt_pending_cur_priv_EQ_0b0_983_THEN__ETC___d1990) ;
  assign csr_mip_fv_read__94_BIT_5_038_AND_csr_mie_fv_r_ETC___d2047 =
	     csr_mip$fv_read[5] && csr_mie$fv_read[5] &&
	     (interrupt_pending_cur_priv_ULT_IF_rg_mideleg_7_ETC___d2043 ||
	      interrupt_pending_cur_priv_EQ_IF_rg_mideleg_75_ETC___d2044 &&
	      IF_interrupt_pending_cur_priv_EQ_0b0_983_THEN__ETC___d1990) ;
  assign csr_mip_fv_read__94_BIT_7_005_AND_csr_mie_fv_r_ETC___d2014 =
	     csr_mip$fv_read[7] && csr_mie$fv_read[7] &&
	     (interrupt_pending_cur_priv_ULT_IF_rg_mideleg_7_ETC___d2010 ||
	      interrupt_pending_cur_priv_EQ_IF_rg_mideleg_75_ETC___d2011 &&
	      IF_interrupt_pending_cur_priv_EQ_0b0_983_THEN__ETC___d1990) ;
  assign csr_mip_fv_read__94_BIT_8_049_AND_csr_mie_fv_r_ETC___d2058 =
	     csr_mip$fv_read[8] && csr_mie$fv_read[8] &&
	     (interrupt_pending_cur_priv_ULT_IF_rg_mideleg_7_ETC___d2054 ||
	      interrupt_pending_cur_priv_EQ_IF_rg_mideleg_75_ETC___d2055 &&
	      IF_interrupt_pending_cur_priv_EQ_0b0_983_THEN__ETC___d1990) ;
  assign csr_mip_fv_read__94_BIT_9_016_AND_csr_mie_fv_r_ETC___d2025 =
	     csr_mip$fv_read[9] && csr_mie$fv_read[9] &&
	     (interrupt_pending_cur_priv_ULT_IF_rg_mideleg_7_ETC___d2021 ||
	      interrupt_pending_cur_priv_EQ_IF_rg_mideleg_75_ETC___d2022 &&
	      IF_interrupt_pending_cur_priv_EQ_0b0_983_THEN__ETC___d1990) ;
  assign csr_mstatus_rg_mstatus_46_AND_INV_1_SL_0_CONCA_ETC___d1675 =
	     x__h12968 | mask__h12956 ;
  assign csr_mstatus_rg_mstatus_46_AND_INV_1_SL_1_CONCA_ETC___d1476 =
	     x__h10985 | val__h10974 ;
  assign csr_trap_actions_interrupt_AND_NOT_csr_trap_ac_ETC___d1508 =
	     csr_trap_actions_interrupt && !csr_trap_actions_nmi &&
	     CASE_new_priv0791_0b1_rg_stvec_BIT_0_0b11_rg_m_ETC__q2 ;
  assign csr_trap_actions_nmi_OR_NOT_csr_trap_actions_i_ETC___d1657 =
	     (csr_trap_actions_nmi || !csr_trap_actions_interrupt) &&
	     exc_code__h12648 != 4'd0 &&
	     exc_code__h12648 != 4'd1 &&
	     exc_code__h12648 != 4'd2 &&
	     exc_code__h12648 != 4'd3 &&
	     exc_code__h12648 != 4'd4 &&
	     exc_code__h12648 != 4'd5 &&
	     exc_code__h12648 != 4'd6 &&
	     exc_code__h12648 != 4'd7 &&
	     exc_code__h12648 != 4'd8 &&
	     exc_code__h12648 != 4'd9 &&
	     exc_code__h12648 != 4'd11 &&
	     exc_code__h12648 != 4'd12 &&
	     exc_code__h12648 != 4'd13 &&
	     exc_code__h12648 != 4'd15 ;
  assign deleg_bit___1__h10911 = rg_mideleg[csr_trap_actions_exc_code] ;
  assign deleg_bit___1__h10926 = rg_medeleg[csr_trap_actions_exc_code] ;
  assign exc_code__h12648 =
	     csr_trap_actions_nmi ? 4'd0 : csr_trap_actions_exc_code ;
  assign exc_pc___1__h12025 = exc_pc__h11951 + vector_offset__h11952 ;
  assign exc_pc__h11951 =
	     csr_trap_actions_nmi ?
	       rg_nmi_vector :
	       y_avValue_snd_snd__h11998 ;
  assign fixed_up_val_23__h10840 =
	     { IF_IF_csr_trap_actions_nmi_THEN_0b11_ELSE_IF_c_ETC___d1484[22:17],
	       2'd0,
	       IF_IF_csr_trap_actions_nmi_THEN_0b11_ELSE_IF_c_ETC___d1484[14:13],
	       (IF_IF_csr_trap_actions_nmi_THEN_0b11_ELSE_IF_c_ETC___d1484[12:11] ==
		2'b10) ?
		 2'b01 :
		 IF_IF_csr_trap_actions_nmi_THEN_0b11_ELSE_IF_c_ETC___d1484[12:11],
	       IF_IF_csr_trap_actions_nmi_THEN_0b11_ELSE_IF_c_ETC___d1484[10:5],
	       1'd0,
	       IF_IF_csr_trap_actions_nmi_THEN_0b11_ELSE_IF_c_ETC___d1484[3:1],
	       1'd0 } ;
  assign fixed_up_val_23__h12869 =
	     { IF_csr_ret_actions_from_priv_EQ_0b11_661_THEN__ETC___d1682[22:17],
	       2'd0,
	       IF_csr_ret_actions_from_priv_EQ_0b11_661_THEN__ETC___d1682[14:13],
	       (IF_csr_ret_actions_from_priv_EQ_0b11_661_THEN__ETC___d1682[12:11] ==
		2'b10) ?
		 2'b01 :
		 IF_csr_ret_actions_from_priv_EQ_0b11_661_THEN__ETC___d1682[12:11],
	       IF_csr_ret_actions_from_priv_EQ_0b11_661_THEN__ETC___d1682[10:5],
	       1'd0,
	       IF_csr_ret_actions_from_priv_EQ_0b11_661_THEN__ETC___d1682[3:1],
	       1'd0 } ;
  assign fixed_up_val_23__h6007 =
	     { csr_mstatus_rg_mstatus[22:20],
	       mav_csr_write_word[19:18],
	       csr_mstatus_rg_mstatus[17],
	       2'd0,
	       mav_csr_write_word[14:13],
	       IF_csr_mstatus_rg_mstatus_46_BITS_12_TO_11_04__ETC___d906,
	       csr_mstatus_rg_mstatus[10:9],
	       mav_csr_write_word[8],
	       csr_mstatus_rg_mstatus[7:6],
	       mav_csr_write_word[5],
	       1'd0,
	       csr_mstatus_rg_mstatus[3:2],
	       mav_csr_write_word[1],
	       1'd0 } ;
  assign fixed_up_val_23__h7253 =
	     { mav_csr_write_word[22:17],
	       2'd0,
	       mav_csr_write_word[14:13],
	       (mav_csr_write_word[12:11] == 2'b10) ?
		 2'b01 :
		 mav_csr_write_word[12:11],
	       mav_csr_write_word[10:5],
	       1'd0,
	       mav_csr_write_word[3:1],
	       1'd0 } ;
  assign fixed_up_val_23__h9209 =
	     { csr_mstatus_rg_mstatus[22:17],
	       2'd0,
	       ma_update_mstatus_fs_fs,
	       IF_csr_mstatus_rg_mstatus_46_BITS_12_TO_11_04__ETC___d906,
	       csr_mstatus_rg_mstatus[10:5],
	       1'd0,
	       csr_mstatus_rg_mstatus[3:1],
	       1'd0 } ;
  assign ie_from_x__h12919 = { 4'd0, csr_ret_actions_from_priv } ;
  assign ie_to_x__h10890 = { 4'd0, new_priv__h10791 } ;
  assign interrupt_pending_cur_priv_EQ_IF_rg_mideleg_75_ETC___d1982 =
	     interrupt_pending_cur_priv == _theResult____h14614 ;
  assign interrupt_pending_cur_priv_EQ_IF_rg_mideleg_75_ETC___d2000 =
	     interrupt_pending_cur_priv == _theResult____h14826 ;
  assign interrupt_pending_cur_priv_EQ_IF_rg_mideleg_75_ETC___d2011 =
	     interrupt_pending_cur_priv == _theResult____h15038 ;
  assign interrupt_pending_cur_priv_EQ_IF_rg_mideleg_75_ETC___d2022 =
	     interrupt_pending_cur_priv == _theResult____h15250 ;
  assign interrupt_pending_cur_priv_EQ_IF_rg_mideleg_75_ETC___d2033 =
	     interrupt_pending_cur_priv == _theResult____h15462 ;
  assign interrupt_pending_cur_priv_EQ_IF_rg_mideleg_75_ETC___d2044 =
	     interrupt_pending_cur_priv == _theResult____h15674 ;
  assign interrupt_pending_cur_priv_EQ_IF_rg_mideleg_75_ETC___d2055 =
	     interrupt_pending_cur_priv == _theResult____h15886 ;
  assign interrupt_pending_cur_priv_EQ_IF_rg_mideleg_75_ETC___d2066 =
	     interrupt_pending_cur_priv == _theResult____h16098 ;
  assign interrupt_pending_cur_priv_ULT_IF_rg_mideleg_7_ETC___d1981 =
	     interrupt_pending_cur_priv < _theResult____h14614 ;
  assign interrupt_pending_cur_priv_ULT_IF_rg_mideleg_7_ETC___d1999 =
	     interrupt_pending_cur_priv < _theResult____h14826 ;
  assign interrupt_pending_cur_priv_ULT_IF_rg_mideleg_7_ETC___d2010 =
	     interrupt_pending_cur_priv < _theResult____h15038 ;
  assign interrupt_pending_cur_priv_ULT_IF_rg_mideleg_7_ETC___d2021 =
	     interrupt_pending_cur_priv < _theResult____h15250 ;
  assign interrupt_pending_cur_priv_ULT_IF_rg_mideleg_7_ETC___d2032 =
	     interrupt_pending_cur_priv < _theResult____h15462 ;
  assign interrupt_pending_cur_priv_ULT_IF_rg_mideleg_7_ETC___d2043 =
	     interrupt_pending_cur_priv < _theResult____h15674 ;
  assign interrupt_pending_cur_priv_ULT_IF_rg_mideleg_7_ETC___d2054 =
	     interrupt_pending_cur_priv < _theResult____h15886 ;
  assign interrupt_pending_cur_priv_ULT_IF_rg_mideleg_7_ETC___d2065 =
	     interrupt_pending_cur_priv < _theResult____h16098 ;
  assign mask__h10973 = 32'd1 << ie_to_x__h10890 ;
  assign mask__h10990 = 32'd1 << pie_to_x__h10891 ;
  assign mask__h12956 = 32'd1 << pie_from_x__h12920 ;
  assign mask__h12973 = 32'd1 << ie_from_x__h12919 ;
  assign mav_csr_write_csr_addr_ULE_0x33F___d872 =
	     mav_csr_write_csr_addr <= 12'h33F ;
  assign mav_csr_write_csr_addr_ULE_0xB1F___d864 =
	     mav_csr_write_csr_addr <= 12'hB1F ;
  assign mav_csr_write_csr_addr_ULE_0xB9F___d868 =
	     mav_csr_write_csr_addr <= 12'hB9F ;
  assign mav_csr_write_csr_addr_ULT_0x323_71_OR_NOT_mav_ETC___d1145 =
	     (mav_csr_write_csr_addr_ULT_0x323___d871 ||
	      !mav_csr_write_csr_addr_ULE_0x33F___d872) &&
	     mav_csr_write_csr_addr != 12'h001 &&
	     mav_csr_write_csr_addr != 12'h002 &&
	     mav_csr_write_csr_addr != 12'h003 &&
	     mav_csr_write_csr_addr != 12'h100 &&
	     mav_csr_write_csr_addr != 12'h102 &&
	     mav_csr_write_csr_addr != 12'h103 &&
	     mav_csr_write_csr_addr != 12'h104 &&
	     mav_csr_write_csr_addr != 12'h105 &&
	     mav_csr_write_csr_addr != 12'h106 &&
	     mav_csr_write_csr_addr != 12'h140 &&
	     mav_csr_write_csr_addr != 12'h141 &&
	     mav_csr_write_csr_addr != 12'h142 &&
	     mav_csr_write_csr_addr != 12'h143 &&
	     mav_csr_write_csr_addr != 12'h144 &&
	     mav_csr_write_csr_addr != 12'h180 &&
	     mav_csr_write_csr_addr != 12'h302 &&
	     mav_csr_write_csr_addr != 12'h303 &&
	     mav_csr_write_csr_addr != 12'hF11 &&
	     mav_csr_write_csr_addr != 12'hF12 &&
	     mav_csr_write_csr_addr != 12'hF13 &&
	     mav_csr_write_csr_addr != 12'hF14 &&
	     mav_csr_write_csr_addr != 12'h300 &&
	     mav_csr_write_csr_addr != 12'h301 &&
	     mav_csr_write_csr_addr != 12'h304 &&
	     mav_csr_write_csr_addr != 12'h305 &&
	     mav_csr_write_csr_addr != 12'h306 &&
	     mav_csr_write_csr_addr != 12'h340 &&
	     mav_csr_write_csr_addr != 12'h341 &&
	     mav_csr_write_csr_addr != 12'h342 &&
	     mav_csr_write_csr_addr != 12'h343 &&
	     mav_csr_write_csr_addr != 12'h344 &&
	     mav_csr_write_csr_addr != 12'hB00 &&
	     mav_csr_write_csr_addr != 12'hB02 &&
	     mav_csr_write_csr_addr != 12'hB80 &&
	     mav_csr_write_csr_addr != 12'hB82 &&
	     mav_csr_write_csr_addr != 12'h7A0 &&
	     mav_csr_write_csr_addr != 12'h7A1 &&
	     mav_csr_write_csr_addr != 12'h7A2 &&
	     mav_csr_write_csr_addr != 12'h7A3 ;
  assign mav_csr_write_csr_addr_ULT_0x323___d871 =
	     mav_csr_write_csr_addr < 12'h323 ;
  assign mav_csr_write_csr_addr_ULT_0xB03_63_OR_NOT_mav_ETC___d1147 =
	     (mav_csr_write_csr_addr_ULT_0xB03___d863 ||
	      !mav_csr_write_csr_addr_ULE_0xB1F___d864) &&
	     (mav_csr_write_csr_addr_ULT_0xB83___d867 ||
	      !mav_csr_write_csr_addr_ULE_0xB9F___d868) &&
	     mav_csr_write_csr_addr_ULT_0x323_71_OR_NOT_mav_ETC___d1145 ;
  assign mav_csr_write_csr_addr_ULT_0xB03_63_OR_NOT_mav_ETC___d876 =
	     (mav_csr_write_csr_addr_ULT_0xB03___d863 ||
	      !mav_csr_write_csr_addr_ULE_0xB1F___d864) &&
	     (mav_csr_write_csr_addr_ULT_0xB83___d867 ||
	      !mav_csr_write_csr_addr_ULE_0xB9F___d868) &&
	     (mav_csr_write_csr_addr_ULT_0x323___d871 ||
	      !mav_csr_write_csr_addr_ULE_0x33F___d872) ;
  assign mav_csr_write_csr_addr_ULT_0xB03___d863 =
	     mav_csr_write_csr_addr < 12'hB03 ;
  assign mav_csr_write_csr_addr_ULT_0xB83___d867 =
	     mav_csr_write_csr_addr < 12'hB83 ;
  assign new_priv__h10791 =
	     csr_trap_actions_nmi ?
	       2'b11 :
	       ((csr_trap_actions_from_priv == 2'b11) ?
		  csr_trap_actions_from_priv :
		  _theResult___fst__h10902) ;
  assign pie_from_x__h12920 = { 4'd1, csr_ret_actions_from_priv } ;
  assign pie_to_x__h10891 = { 4'd1, new_priv__h10791 } ;
  assign result__h8591 = { 4'd0, mav_csr_write_word[27:0] } ;
  assign sd__h10839 =
	     IF_IF_csr_trap_actions_nmi_THEN_0b11_ELSE_IF_c_ETC___d1484[14:13] ==
	     2'h3 ;
  assign sd__h12868 =
	     IF_csr_ret_actions_from_priv_EQ_0b11_661_THEN__ETC___d1682[14:13] ==
	     2'h3 ;
  assign sd__h7252 = mav_csr_write_word[14:13] == 2'h3 ;
  assign sd__h9208 = ma_update_mstatus_fs_fs == 2'h3 ;
  assign to_y__h13135 =
	     { 1'b0,
	       csr_mstatus_rg_mstatus_46_AND_INV_1_SL_0_CONCA_ETC___d1675[8] } ;
  assign v__h10796 = { sd__h10839, 8'd0, fixed_up_val_23__h10840 } ;
  assign v__h5698 = { 27'd0, mav_csr_write_word[4:0] } ;
  assign v__h5842 = { 24'd0, mav_csr_write_word[7:0] } ;
  assign v__h5956 =
	     { sd__h7252,
	       11'd0,
	       mav_csr_write_word[19:18],
	       3'd0,
	       mav_csr_write_word[14:13],
	       4'd0,
	       mav_csr_write_word[8],
	       2'd0,
	       mav_csr_write_word[5],
	       3'd0,
	       mav_csr_write_word[1],
	       1'd0 } ;
  assign v__h7081 =
	     { 16'd0,
	       mav_csr_write_word[15],
	       1'd0,
	       mav_csr_write_word[13:12],
	       2'd0,
	       mav_csr_write_word[9:0] } ;
  assign v__h7117 = { 20'd0, mav_csr_write_word[11:0] } ;
  assign v__h7758 =
	     { mav_csr_write_word[31:2], 1'b0, mav_csr_write_word[0] } ;
  assign v__h7820 = { 29'd0, mav_csr_write_word[2:0] } ;
  assign v__h7976 =
	     { mav_csr_write_word[31], 27'd0, mav_csr_write_word[3:0] } ;
  assign val__h10974 = 32'd0 << ie_to_x__h10890 ;
  assign val__h10991 = { 31'd0, b__h10989 } << pie_to_x__h10891 ;
  assign val__h12974 = { 31'd0, b__h12972 } << ie_from_x__h12919 ;
  assign vector_offset__h11952 = { 26'd0, csr_trap_actions_exc_code, 2'd0 } ;
  assign wordxl1__h7212 = { sd__h7252, 8'd0, fixed_up_val_23__h7253 } ;
  assign x__h10972 = x__h11002 | val__h10991 ;
  assign x__h10985 = x__h10972 & y__h10986 ;
  assign x__h11002 = csr_mstatus_rg_mstatus & y__h11003 ;
  assign x__h12806 =
	     (csr_trap_actions_nmi || new_priv__h10791 == 2'b11) ?
	       v__h10796 :
	       y_avValue_fst__h11925 ;
  assign x__h12807 =
	     { !csr_trap_actions_nmi && csr_trap_actions_interrupt,
	       27'd0,
	       exc_code__h12648 } ;
  assign x__h12955 = x__h12985 | val__h12974 ;
  assign x__h12968 = x__h12955 & y__h12969 ;
  assign x__h12985 = csr_mstatus_rg_mstatus & y__h12986 ;
  assign x__h8408 = { rg_minstret[63:32], mav_csr_write_word } ;
  assign x__h8516 = { mav_csr_write_word, rg_minstret[31:0] } ;
  assign x__h9768 =
	     csr_trap_actions_interrupt_AND_NOT_csr_trap_ac_ETC___d1508 ?
	       exc_pc___1__h12025 :
	       exc_pc__h11951 ;
  assign y__h10986 = ~mask__h10973 ;
  assign y__h11003 = ~mask__h10990 ;
  assign y__h12969 = ~mask__h12956 ;
  assign y__h12986 = ~mask__h12973 ;
  assign y_avValue_fst__h11908 =
	     { sd__h10839,
	       11'd0,
	       IF_IF_csr_trap_actions_nmi_THEN_0b11_ELSE_IF_c_ETC___d1484[19:18],
	       3'd0,
	       IF_IF_csr_trap_actions_nmi_THEN_0b11_ELSE_IF_c_ETC___d1484[14:13],
	       4'd0,
	       IF_IF_csr_trap_actions_nmi_THEN_0b11_ELSE_IF_c_ETC___d1484[8],
	       2'd0,
	       IF_IF_csr_trap_actions_nmi_THEN_0b11_ELSE_IF_c_ETC___d1484[5],
	       3'd0,
	       IF_IF_csr_trap_actions_nmi_THEN_0b11_ELSE_IF_c_ETC___d1484[1],
	       1'd0 } ;
  assign y_avValue_fst__h11925 =
	     (new_priv__h10791 == 2'b01) ? y_avValue_fst__h11908 : v__h10796 ;
  assign y_avValue_snd_snd__h11998 =
	     { CASE_new_priv0791_0b1_rg_stvec_BITS_30_TO_1_0b_ETC__q1,
	       2'd0 } ;
  always@(mav_csr_write_csr_addr or
	  v__h5698 or
	  v__h7820 or
	  v__h5842 or
	  v__h5956 or
	  csr_mie$fav_sie_write or
	  v__h7758 or
	  mav_csr_write_word or
	  v__h7976 or
	  csr_mip$fav_sip_write or
	  wordxl1__h7212 or
	  v__h7081 or
	  v__h7117 or csr_mie$fav_write or csr_mip$fav_write or result__h8591)
  begin
    case (mav_csr_write_csr_addr)
      12'h001: y_avValue_fst__h8976 = v__h5698;
      12'h002, 12'h306: y_avValue_fst__h8976 = v__h7820;
      12'h003: y_avValue_fst__h8976 = v__h5842;
      12'h100: y_avValue_fst__h8976 = v__h5956;
      12'h102,
      12'h103,
      12'h106,
      12'h301,
      12'h7A0,
      12'hF11,
      12'hF12,
      12'hF13,
      12'hF14:
	  y_avValue_fst__h8976 = 32'd0;
      12'h104: y_avValue_fst__h8976 = csr_mie$fav_sie_write;
      12'h105, 12'h305: y_avValue_fst__h8976 = v__h7758;
      12'h140,
      12'h141,
      12'h143,
      12'h180,
      12'h340,
      12'h341,
      12'h343,
      12'h7A2,
      12'h7A3,
      12'hB00,
      12'hB02,
      12'hB80,
      12'hB82:
	  y_avValue_fst__h8976 = mav_csr_write_word;
      12'h142, 12'h342: y_avValue_fst__h8976 = v__h7976;
      12'h144: y_avValue_fst__h8976 = csr_mip$fav_sip_write;
      12'h300: y_avValue_fst__h8976 = wordxl1__h7212;
      12'h302: y_avValue_fst__h8976 = v__h7081;
      12'h303: y_avValue_fst__h8976 = v__h7117;
      12'h304: y_avValue_fst__h8976 = csr_mie$fav_write;
      12'h344: y_avValue_fst__h8976 = csr_mip$fav_write;
      12'h7A1: y_avValue_fst__h8976 = result__h8591;
      default: y_avValue_fst__h8976 = 32'd0;
    endcase
  end
  always@(new_priv__h10791 or rg_mtvec or rg_stvec)
  begin
    case (new_priv__h10791)
      2'b01:
	  CASE_new_priv0791_0b1_rg_stvec_BITS_30_TO_1_0b_ETC__q1 =
	      rg_stvec[30:1];
      2'b11:
	  CASE_new_priv0791_0b1_rg_stvec_BITS_30_TO_1_0b_ETC__q1 =
	      rg_mtvec[30:1];
      default: CASE_new_priv0791_0b1_rg_stvec_BITS_30_TO_1_0b_ETC__q1 =
		   rg_mtvec[30:1];
    endcase
  end
  always@(new_priv__h10791 or rg_mtvec or rg_stvec)
  begin
    case (new_priv__h10791)
      2'b01:
	  CASE_new_priv0791_0b1_rg_stvec_BIT_0_0b11_rg_m_ETC__q2 =
	      rg_stvec[0];
      2'b11:
	  CASE_new_priv0791_0b1_rg_stvec_BIT_0_0b11_rg_m_ETC__q2 =
	      rg_mtvec[0];
      default: CASE_new_priv0791_0b1_rg_stvec_BIT_0_0b11_rg_m_ETC__q2 =
		   rg_mtvec[0];
    endcase
  end
  always@(interrupt_pending_cur_priv or csr_mstatus_rg_mstatus)
  begin
    case (interrupt_pending_cur_priv)
      2'b0:
	  IF_interrupt_pending_cur_priv_EQ_0b0_983_THEN__ETC___d1990 =
	      csr_mstatus_rg_mstatus[0];
      2'b01:
	  IF_interrupt_pending_cur_priv_EQ_0b0_983_THEN__ETC___d1990 =
	      csr_mstatus_rg_mstatus[1];
      default: IF_interrupt_pending_cur_priv_EQ_0b0_983_THEN__ETC___d1990 =
		   interrupt_pending_cur_priv == 2'b11 &&
		   csr_mstatus_rg_mstatus[3];
    endcase
  end
  always@(interrupt_pending_cur_priv or csr_mstatus_rg_mstatus)
  begin
    case (interrupt_pending_cur_priv)
      2'b0:
	  IF_interrupt_pending_cur_priv_EQ_0b0_983_THEN__ETC___d2093 =
	      !csr_mstatus_rg_mstatus[0];
      2'b01:
	  IF_interrupt_pending_cur_priv_EQ_0b0_983_THEN__ETC___d2093 =
	      !csr_mstatus_rg_mstatus[1];
      default: IF_interrupt_pending_cur_priv_EQ_0b0_983_THEN__ETC___d2093 =
		   interrupt_pending_cur_priv != 2'b11 ||
		   !csr_mstatus_rg_mstatus[3];
    endcase
  end
  always@(read_csr_csr_addr or
	  rg_tdata3 or
	  rg_fflags or
	  rg_frm or
	  csr_mstatus_rg_mstatus or
	  csr_mie$fv_sie_read or
	  rg_stvec or
	  rg_sscratch or
	  rg_sepc or
	  rg_scause or
	  rg_stval or
	  csr_mip$fv_sip_read or
	  rg_satp or
	  rg_medeleg or
	  rg_mideleg or
	  csr_mie$fv_read or
	  rg_mtvec or
	  rg_mcounteren or
	  rg_mscratch or
	  rg_mepc or
	  rg_mcause or
	  rg_mtval or
	  csr_mip$fv_read or
	  rg_tselect or rg_tdata1 or rg_tdata2 or rg_mcycle or rg_minstret)
  begin
    case (read_csr_csr_addr)
      12'h001:
	  IF_read_csr_csr_addr_EQ_0x1_9_THEN_0_CONCAT_rg_ETC___d336 =
	      { 27'd0, rg_fflags };
      12'h002:
	  IF_read_csr_csr_addr_EQ_0x1_9_THEN_0_CONCAT_rg_ETC___d336 =
	      { 29'd0, rg_frm };
      12'h003:
	  IF_read_csr_csr_addr_EQ_0x1_9_THEN_0_CONCAT_rg_ETC___d336 =
	      { 24'd0, rg_frm, rg_fflags };
      12'h100:
	  IF_read_csr_csr_addr_EQ_0x1_9_THEN_0_CONCAT_rg_ETC___d336 =
	      { csr_mstatus_rg_mstatus[31],
		11'd0,
		csr_mstatus_rg_mstatus[19:18],
		1'd0,
		csr_mstatus_rg_mstatus[16:13],
		4'd0,
		csr_mstatus_rg_mstatus[8],
		2'd0,
		csr_mstatus_rg_mstatus[5:4],
		2'd0,
		csr_mstatus_rg_mstatus[1:0] };
      12'h102, 12'h103, 12'h106, 12'hF11, 12'hF12, 12'hF13, 12'hF14:
	  IF_read_csr_csr_addr_EQ_0x1_9_THEN_0_CONCAT_rg_ETC___d336 = 32'd0;
      12'h104:
	  IF_read_csr_csr_addr_EQ_0x1_9_THEN_0_CONCAT_rg_ETC___d336 =
	      csr_mie$fv_sie_read;
      12'h105:
	  IF_read_csr_csr_addr_EQ_0x1_9_THEN_0_CONCAT_rg_ETC___d336 =
	      { rg_stvec[30:1], 1'b0, rg_stvec[0] };
      12'h140:
	  IF_read_csr_csr_addr_EQ_0x1_9_THEN_0_CONCAT_rg_ETC___d336 =
	      rg_sscratch;
      12'h141:
	  IF_read_csr_csr_addr_EQ_0x1_9_THEN_0_CONCAT_rg_ETC___d336 = rg_sepc;
      12'h142:
	  IF_read_csr_csr_addr_EQ_0x1_9_THEN_0_CONCAT_rg_ETC___d336 =
	      { rg_scause[4], 27'd0, rg_scause[3:0] };
      12'h143:
	  IF_read_csr_csr_addr_EQ_0x1_9_THEN_0_CONCAT_rg_ETC___d336 =
	      rg_stval;
      12'h144:
	  IF_read_csr_csr_addr_EQ_0x1_9_THEN_0_CONCAT_rg_ETC___d336 =
	      csr_mip$fv_sip_read;
      12'h180:
	  IF_read_csr_csr_addr_EQ_0x1_9_THEN_0_CONCAT_rg_ETC___d336 = rg_satp;
      12'h300:
	  IF_read_csr_csr_addr_EQ_0x1_9_THEN_0_CONCAT_rg_ETC___d336 =
	      csr_mstatus_rg_mstatus;
      12'h301:
	  IF_read_csr_csr_addr_EQ_0x1_9_THEN_0_CONCAT_rg_ETC___d336 =
	      32'd1075056941;
      12'h302:
	  IF_read_csr_csr_addr_EQ_0x1_9_THEN_0_CONCAT_rg_ETC___d336 =
	      { 16'd0, rg_medeleg };
      12'h303:
	  IF_read_csr_csr_addr_EQ_0x1_9_THEN_0_CONCAT_rg_ETC___d336 =
	      { 20'd0, rg_mideleg };
      12'h304:
	  IF_read_csr_csr_addr_EQ_0x1_9_THEN_0_CONCAT_rg_ETC___d336 =
	      csr_mie$fv_read;
      12'h305:
	  IF_read_csr_csr_addr_EQ_0x1_9_THEN_0_CONCAT_rg_ETC___d336 =
	      { rg_mtvec[30:1], 1'b0, rg_mtvec[0] };
      12'h306:
	  IF_read_csr_csr_addr_EQ_0x1_9_THEN_0_CONCAT_rg_ETC___d336 =
	      { 29'd0, rg_mcounteren };
      12'h340:
	  IF_read_csr_csr_addr_EQ_0x1_9_THEN_0_CONCAT_rg_ETC___d336 =
	      rg_mscratch;
      12'h341:
	  IF_read_csr_csr_addr_EQ_0x1_9_THEN_0_CONCAT_rg_ETC___d336 = rg_mepc;
      12'h342:
	  IF_read_csr_csr_addr_EQ_0x1_9_THEN_0_CONCAT_rg_ETC___d336 =
	      { rg_mcause[4], 27'd0, rg_mcause[3:0] };
      12'h343:
	  IF_read_csr_csr_addr_EQ_0x1_9_THEN_0_CONCAT_rg_ETC___d336 =
	      rg_mtval;
      12'h344:
	  IF_read_csr_csr_addr_EQ_0x1_9_THEN_0_CONCAT_rg_ETC___d336 =
	      csr_mip$fv_read;
      12'h7A0:
	  IF_read_csr_csr_addr_EQ_0x1_9_THEN_0_CONCAT_rg_ETC___d336 =
	      rg_tselect;
      12'h7A1:
	  IF_read_csr_csr_addr_EQ_0x1_9_THEN_0_CONCAT_rg_ETC___d336 =
	      rg_tdata1;
      12'h7A2:
	  IF_read_csr_csr_addr_EQ_0x1_9_THEN_0_CONCAT_rg_ETC___d336 =
	      rg_tdata2;
      12'hB00, 12'hC00:
	  IF_read_csr_csr_addr_EQ_0x1_9_THEN_0_CONCAT_rg_ETC___d336 =
	      rg_mcycle[31:0];
      12'hB02, 12'hC02:
	  IF_read_csr_csr_addr_EQ_0x1_9_THEN_0_CONCAT_rg_ETC___d336 =
	      rg_minstret[31:0];
      12'hB80, 12'hC80:
	  IF_read_csr_csr_addr_EQ_0x1_9_THEN_0_CONCAT_rg_ETC___d336 =
	      rg_mcycle[63:32];
      12'hB82, 12'hC82:
	  IF_read_csr_csr_addr_EQ_0x1_9_THEN_0_CONCAT_rg_ETC___d336 =
	      rg_minstret[63:32];
      default: IF_read_csr_csr_addr_EQ_0x1_9_THEN_0_CONCAT_rg_ETC___d336 =
		   rg_tdata3;
    endcase
  end
  always@(read_csr_port2_csr_addr or
	  rg_tdata3 or
	  rg_fflags or
	  rg_frm or
	  csr_mstatus_rg_mstatus or
	  csr_mie$fv_sie_read or
	  rg_stvec or
	  rg_sscratch or
	  rg_sepc or
	  rg_scause or
	  rg_stval or
	  csr_mip$fv_sip_read or
	  rg_satp or
	  rg_medeleg or
	  rg_mideleg or
	  csr_mie$fv_read or
	  rg_mtvec or
	  rg_mcounteren or
	  rg_mscratch or
	  rg_mepc or
	  rg_mcause or
	  rg_mtval or
	  csr_mip$fv_read or
	  rg_tselect or rg_tdata1 or rg_tdata2 or rg_mcycle or rg_minstret)
  begin
    case (read_csr_port2_csr_addr)
      12'h001:
	  IF_read_csr_port2_csr_addr_EQ_0x1_59_THEN_0_CO_ETC___d598 =
	      { 27'd0, rg_fflags };
      12'h002:
	  IF_read_csr_port2_csr_addr_EQ_0x1_59_THEN_0_CO_ETC___d598 =
	      { 29'd0, rg_frm };
      12'h003:
	  IF_read_csr_port2_csr_addr_EQ_0x1_59_THEN_0_CO_ETC___d598 =
	      { 24'd0, rg_frm, rg_fflags };
      12'h100:
	  IF_read_csr_port2_csr_addr_EQ_0x1_59_THEN_0_CO_ETC___d598 =
	      { csr_mstatus_rg_mstatus[31],
		11'd0,
		csr_mstatus_rg_mstatus[19:18],
		1'd0,
		csr_mstatus_rg_mstatus[16:13],
		4'd0,
		csr_mstatus_rg_mstatus[8],
		2'd0,
		csr_mstatus_rg_mstatus[5:4],
		2'd0,
		csr_mstatus_rg_mstatus[1:0] };
      12'h102, 12'h103, 12'h106, 12'hF11, 12'hF12, 12'hF13, 12'hF14:
	  IF_read_csr_port2_csr_addr_EQ_0x1_59_THEN_0_CO_ETC___d598 = 32'd0;
      12'h104:
	  IF_read_csr_port2_csr_addr_EQ_0x1_59_THEN_0_CO_ETC___d598 =
	      csr_mie$fv_sie_read;
      12'h105:
	  IF_read_csr_port2_csr_addr_EQ_0x1_59_THEN_0_CO_ETC___d598 =
	      { rg_stvec[30:1], 1'b0, rg_stvec[0] };
      12'h140:
	  IF_read_csr_port2_csr_addr_EQ_0x1_59_THEN_0_CO_ETC___d598 =
	      rg_sscratch;
      12'h141:
	  IF_read_csr_port2_csr_addr_EQ_0x1_59_THEN_0_CO_ETC___d598 = rg_sepc;
      12'h142:
	  IF_read_csr_port2_csr_addr_EQ_0x1_59_THEN_0_CO_ETC___d598 =
	      { rg_scause[4], 27'd0, rg_scause[3:0] };
      12'h143:
	  IF_read_csr_port2_csr_addr_EQ_0x1_59_THEN_0_CO_ETC___d598 =
	      rg_stval;
      12'h144:
	  IF_read_csr_port2_csr_addr_EQ_0x1_59_THEN_0_CO_ETC___d598 =
	      csr_mip$fv_sip_read;
      12'h180:
	  IF_read_csr_port2_csr_addr_EQ_0x1_59_THEN_0_CO_ETC___d598 = rg_satp;
      12'h300:
	  IF_read_csr_port2_csr_addr_EQ_0x1_59_THEN_0_CO_ETC___d598 =
	      csr_mstatus_rg_mstatus;
      12'h301:
	  IF_read_csr_port2_csr_addr_EQ_0x1_59_THEN_0_CO_ETC___d598 =
	      32'd1075056941;
      12'h302:
	  IF_read_csr_port2_csr_addr_EQ_0x1_59_THEN_0_CO_ETC___d598 =
	      { 16'd0, rg_medeleg };
      12'h303:
	  IF_read_csr_port2_csr_addr_EQ_0x1_59_THEN_0_CO_ETC___d598 =
	      { 20'd0, rg_mideleg };
      12'h304:
	  IF_read_csr_port2_csr_addr_EQ_0x1_59_THEN_0_CO_ETC___d598 =
	      csr_mie$fv_read;
      12'h305:
	  IF_read_csr_port2_csr_addr_EQ_0x1_59_THEN_0_CO_ETC___d598 =
	      { rg_mtvec[30:1], 1'b0, rg_mtvec[0] };
      12'h306:
	  IF_read_csr_port2_csr_addr_EQ_0x1_59_THEN_0_CO_ETC___d598 =
	      { 29'd0, rg_mcounteren };
      12'h340:
	  IF_read_csr_port2_csr_addr_EQ_0x1_59_THEN_0_CO_ETC___d598 =
	      rg_mscratch;
      12'h341:
	  IF_read_csr_port2_csr_addr_EQ_0x1_59_THEN_0_CO_ETC___d598 = rg_mepc;
      12'h342:
	  IF_read_csr_port2_csr_addr_EQ_0x1_59_THEN_0_CO_ETC___d598 =
	      { rg_mcause[4], 27'd0, rg_mcause[3:0] };
      12'h343:
	  IF_read_csr_port2_csr_addr_EQ_0x1_59_THEN_0_CO_ETC___d598 =
	      rg_mtval;
      12'h344:
	  IF_read_csr_port2_csr_addr_EQ_0x1_59_THEN_0_CO_ETC___d598 =
	      csr_mip$fv_read;
      12'h7A0:
	  IF_read_csr_port2_csr_addr_EQ_0x1_59_THEN_0_CO_ETC___d598 =
	      rg_tselect;
      12'h7A1:
	  IF_read_csr_port2_csr_addr_EQ_0x1_59_THEN_0_CO_ETC___d598 =
	      rg_tdata1;
      12'h7A2:
	  IF_read_csr_port2_csr_addr_EQ_0x1_59_THEN_0_CO_ETC___d598 =
	      rg_tdata2;
      12'hB00, 12'hC00:
	  IF_read_csr_port2_csr_addr_EQ_0x1_59_THEN_0_CO_ETC___d598 =
	      rg_mcycle[31:0];
      12'hB02, 12'hC02:
	  IF_read_csr_port2_csr_addr_EQ_0x1_59_THEN_0_CO_ETC___d598 =
	      rg_minstret[31:0];
      12'hB80, 12'hC80:
	  IF_read_csr_port2_csr_addr_EQ_0x1_59_THEN_0_CO_ETC___d598 =
	      rg_mcycle[63:32];
      12'hB82, 12'hC82:
	  IF_read_csr_port2_csr_addr_EQ_0x1_59_THEN_0_CO_ETC___d598 =
	      rg_minstret[63:32];
      default: IF_read_csr_port2_csr_addr_EQ_0x1_59_THEN_0_CO_ETC___d598 =
		   rg_tdata3;
    endcase
  end
  always@(mav_read_csr_csr_addr or
	  rg_tdata3 or
	  rg_fflags or
	  rg_frm or
	  csr_mstatus_rg_mstatus or
	  csr_mie$fv_sie_read or
	  rg_stvec or
	  rg_sscratch or
	  rg_sepc or
	  rg_scause or
	  rg_stval or
	  csr_mip$fv_sip_read or
	  rg_satp or
	  rg_medeleg or
	  rg_mideleg or
	  csr_mie$fv_read or
	  rg_mtvec or
	  rg_mcounteren or
	  rg_mscratch or
	  rg_mepc or
	  rg_mcause or
	  rg_mtval or
	  csr_mip$fv_read or
	  rg_tselect or rg_tdata1 or rg_tdata2 or rg_mcycle or rg_minstret)
  begin
    case (mav_read_csr_csr_addr)
      12'h001:
	  IF_mav_read_csr_csr_addr_EQ_0x1_21_THEN_0_CONC_ETC___d860 =
	      { 27'd0, rg_fflags };
      12'h002:
	  IF_mav_read_csr_csr_addr_EQ_0x1_21_THEN_0_CONC_ETC___d860 =
	      { 29'd0, rg_frm };
      12'h003:
	  IF_mav_read_csr_csr_addr_EQ_0x1_21_THEN_0_CONC_ETC___d860 =
	      { 24'd0, rg_frm, rg_fflags };
      12'h100:
	  IF_mav_read_csr_csr_addr_EQ_0x1_21_THEN_0_CONC_ETC___d860 =
	      { csr_mstatus_rg_mstatus[31],
		11'd0,
		csr_mstatus_rg_mstatus[19:18],
		1'd0,
		csr_mstatus_rg_mstatus[16:13],
		4'd0,
		csr_mstatus_rg_mstatus[8],
		2'd0,
		csr_mstatus_rg_mstatus[5:4],
		2'd0,
		csr_mstatus_rg_mstatus[1:0] };
      12'h102, 12'h103, 12'h106, 12'hF11, 12'hF12, 12'hF13, 12'hF14:
	  IF_mav_read_csr_csr_addr_EQ_0x1_21_THEN_0_CONC_ETC___d860 = 32'd0;
      12'h104:
	  IF_mav_read_csr_csr_addr_EQ_0x1_21_THEN_0_CONC_ETC___d860 =
	      csr_mie$fv_sie_read;
      12'h105:
	  IF_mav_read_csr_csr_addr_EQ_0x1_21_THEN_0_CONC_ETC___d860 =
	      { rg_stvec[30:1], 1'b0, rg_stvec[0] };
      12'h140:
	  IF_mav_read_csr_csr_addr_EQ_0x1_21_THEN_0_CONC_ETC___d860 =
	      rg_sscratch;
      12'h141:
	  IF_mav_read_csr_csr_addr_EQ_0x1_21_THEN_0_CONC_ETC___d860 = rg_sepc;
      12'h142:
	  IF_mav_read_csr_csr_addr_EQ_0x1_21_THEN_0_CONC_ETC___d860 =
	      { rg_scause[4], 27'd0, rg_scause[3:0] };
      12'h143:
	  IF_mav_read_csr_csr_addr_EQ_0x1_21_THEN_0_CONC_ETC___d860 =
	      rg_stval;
      12'h144:
	  IF_mav_read_csr_csr_addr_EQ_0x1_21_THEN_0_CONC_ETC___d860 =
	      csr_mip$fv_sip_read;
      12'h180:
	  IF_mav_read_csr_csr_addr_EQ_0x1_21_THEN_0_CONC_ETC___d860 = rg_satp;
      12'h300:
	  IF_mav_read_csr_csr_addr_EQ_0x1_21_THEN_0_CONC_ETC___d860 =
	      csr_mstatus_rg_mstatus;
      12'h301:
	  IF_mav_read_csr_csr_addr_EQ_0x1_21_THEN_0_CONC_ETC___d860 =
	      32'd1075056941;
      12'h302:
	  IF_mav_read_csr_csr_addr_EQ_0x1_21_THEN_0_CONC_ETC___d860 =
	      { 16'd0, rg_medeleg };
      12'h303:
	  IF_mav_read_csr_csr_addr_EQ_0x1_21_THEN_0_CONC_ETC___d860 =
	      { 20'd0, rg_mideleg };
      12'h304:
	  IF_mav_read_csr_csr_addr_EQ_0x1_21_THEN_0_CONC_ETC___d860 =
	      csr_mie$fv_read;
      12'h305:
	  IF_mav_read_csr_csr_addr_EQ_0x1_21_THEN_0_CONC_ETC___d860 =
	      { rg_mtvec[30:1], 1'b0, rg_mtvec[0] };
      12'h306:
	  IF_mav_read_csr_csr_addr_EQ_0x1_21_THEN_0_CONC_ETC___d860 =
	      { 29'd0, rg_mcounteren };
      12'h340:
	  IF_mav_read_csr_csr_addr_EQ_0x1_21_THEN_0_CONC_ETC___d860 =
	      rg_mscratch;
      12'h341:
	  IF_mav_read_csr_csr_addr_EQ_0x1_21_THEN_0_CONC_ETC___d860 = rg_mepc;
      12'h342:
	  IF_mav_read_csr_csr_addr_EQ_0x1_21_THEN_0_CONC_ETC___d860 =
	      { rg_mcause[4], 27'd0, rg_mcause[3:0] };
      12'h343:
	  IF_mav_read_csr_csr_addr_EQ_0x1_21_THEN_0_CONC_ETC___d860 =
	      rg_mtval;
      12'h344:
	  IF_mav_read_csr_csr_addr_EQ_0x1_21_THEN_0_CONC_ETC___d860 =
	      csr_mip$fv_read;
      12'h7A0:
	  IF_mav_read_csr_csr_addr_EQ_0x1_21_THEN_0_CONC_ETC___d860 =
	      rg_tselect;
      12'h7A1:
	  IF_mav_read_csr_csr_addr_EQ_0x1_21_THEN_0_CONC_ETC___d860 =
	      rg_tdata1;
      12'h7A2:
	  IF_mav_read_csr_csr_addr_EQ_0x1_21_THEN_0_CONC_ETC___d860 =
	      rg_tdata2;
      12'hB00, 12'hC00:
	  IF_mav_read_csr_csr_addr_EQ_0x1_21_THEN_0_CONC_ETC___d860 =
	      rg_mcycle[31:0];
      12'hB02, 12'hC02:
	  IF_mav_read_csr_csr_addr_EQ_0x1_21_THEN_0_CONC_ETC___d860 =
	      rg_minstret[31:0];
      12'hB80, 12'hC80:
	  IF_mav_read_csr_csr_addr_EQ_0x1_21_THEN_0_CONC_ETC___d860 =
	      rg_mcycle[63:32];
      12'hB82, 12'hC82:
	  IF_mav_read_csr_csr_addr_EQ_0x1_21_THEN_0_CONC_ETC___d860 =
	      rg_minstret[63:32];
      default: IF_mav_read_csr_csr_addr_EQ_0x1_21_THEN_0_CONC_ETC___d860 =
		   rg_tdata3;
    endcase
  end

  // handling of inlined registers

  always@(posedge CLK)
  begin
    if (RST_N == `BSV_RESET_VALUE)
      begin
        cfg_verbosity <= `BSV_ASSIGNMENT_DELAY 4'd0;
	csr_mstatus_rg_mstatus <= `BSV_ASSIGNMENT_DELAY 32'd8192;
	rg_mcycle <= `BSV_ASSIGNMENT_DELAY 64'd0;
	rg_minstret <= `BSV_ASSIGNMENT_DELAY 64'd0;
	rg_nmi <= `BSV_ASSIGNMENT_DELAY 1'd0;
	rg_state <= `BSV_ASSIGNMENT_DELAY 1'd0;
      end
    else
      begin
        if (cfg_verbosity$EN)
	  cfg_verbosity <= `BSV_ASSIGNMENT_DELAY cfg_verbosity$D_IN;
	if (csr_mstatus_rg_mstatus$EN)
	  csr_mstatus_rg_mstatus <= `BSV_ASSIGNMENT_DELAY
	      csr_mstatus_rg_mstatus$D_IN;
	if (rg_mcycle$EN) rg_mcycle <= `BSV_ASSIGNMENT_DELAY rg_mcycle$D_IN;
	if (rg_minstret$EN)
	  rg_minstret <= `BSV_ASSIGNMENT_DELAY rg_minstret$D_IN;
	if (rg_nmi$EN) rg_nmi <= `BSV_ASSIGNMENT_DELAY rg_nmi$D_IN;
	if (rg_state$EN) rg_state <= `BSV_ASSIGNMENT_DELAY rg_state$D_IN;
      end
    if (rg_dcsr$EN) rg_dcsr <= `BSV_ASSIGNMENT_DELAY rg_dcsr$D_IN;
    if (rg_dpc$EN) rg_dpc <= `BSV_ASSIGNMENT_DELAY rg_dpc$D_IN;
    if (rg_dscratch0$EN)
      rg_dscratch0 <= `BSV_ASSIGNMENT_DELAY rg_dscratch0$D_IN;
    if (rg_dscratch1$EN)
      rg_dscratch1 <= `BSV_ASSIGNMENT_DELAY rg_dscratch1$D_IN;
    if (rg_fflags$EN) rg_fflags <= `BSV_ASSIGNMENT_DELAY rg_fflags$D_IN;
    if (rg_frm$EN) rg_frm <= `BSV_ASSIGNMENT_DELAY rg_frm$D_IN;
    if (rg_mcause$EN) rg_mcause <= `BSV_ASSIGNMENT_DELAY rg_mcause$D_IN;
    if (rg_mcounteren$EN)
      rg_mcounteren <= `BSV_ASSIGNMENT_DELAY rg_mcounteren$D_IN;
    if (rg_medeleg$EN) rg_medeleg <= `BSV_ASSIGNMENT_DELAY rg_medeleg$D_IN;
    if (rg_mepc$EN) rg_mepc <= `BSV_ASSIGNMENT_DELAY rg_mepc$D_IN;
    if (rg_mideleg$EN) rg_mideleg <= `BSV_ASSIGNMENT_DELAY rg_mideleg$D_IN;
    if (rg_mscratch$EN) rg_mscratch <= `BSV_ASSIGNMENT_DELAY rg_mscratch$D_IN;
    if (rg_mtval$EN) rg_mtval <= `BSV_ASSIGNMENT_DELAY rg_mtval$D_IN;
    if (rg_mtvec$EN) rg_mtvec <= `BSV_ASSIGNMENT_DELAY rg_mtvec$D_IN;
    if (rg_nmi_vector$EN)
      rg_nmi_vector <= `BSV_ASSIGNMENT_DELAY rg_nmi_vector$D_IN;
    if (rg_satp$EN) rg_satp <= `BSV_ASSIGNMENT_DELAY rg_satp$D_IN;
    if (rg_scause$EN) rg_scause <= `BSV_ASSIGNMENT_DELAY rg_scause$D_IN;
    if (rg_sepc$EN) rg_sepc <= `BSV_ASSIGNMENT_DELAY rg_sepc$D_IN;
    if (rg_sscratch$EN) rg_sscratch <= `BSV_ASSIGNMENT_DELAY rg_sscratch$D_IN;
    if (rg_stval$EN) rg_stval <= `BSV_ASSIGNMENT_DELAY rg_stval$D_IN;
    if (rg_stvec$EN) rg_stvec <= `BSV_ASSIGNMENT_DELAY rg_stvec$D_IN;
    if (rg_tdata1$EN) rg_tdata1 <= `BSV_ASSIGNMENT_DELAY rg_tdata1$D_IN;
    if (rg_tdata2$EN) rg_tdata2 <= `BSV_ASSIGNMENT_DELAY rg_tdata2$D_IN;
    if (rg_tdata3$EN) rg_tdata3 <= `BSV_ASSIGNMENT_DELAY rg_tdata3$D_IN;
    if (rg_tselect$EN) rg_tselect <= `BSV_ASSIGNMENT_DELAY rg_tselect$D_IN;
  end

  // synopsys translate_off
  `ifdef BSV_NO_INITIAL_BLOCKS
  `else // not BSV_NO_INITIAL_BLOCKS
  initial
  begin
    cfg_verbosity = 4'hA;
    csr_mstatus_rg_mstatus = 32'hAAAAAAAA;
    rg_dcsr = 32'hAAAAAAAA;
    rg_dpc = 32'hAAAAAAAA;
    rg_dscratch0 = 32'hAAAAAAAA;
    rg_dscratch1 = 32'hAAAAAAAA;
    rg_fflags = 5'h0A;
    rg_frm = 3'h2;
    rg_mcause = 5'h0A;
    rg_mcounteren = 3'h2;
    rg_mcycle = 64'hAAAAAAAAAAAAAAAA;
    rg_medeleg = 16'hAAAA;
    rg_mepc = 32'hAAAAAAAA;
    rg_mideleg = 12'hAAA;
    rg_minstret = 64'hAAAAAAAAAAAAAAAA;
    rg_mscratch = 32'hAAAAAAAA;
    rg_mtval = 32'hAAAAAAAA;
    rg_mtvec = 31'h2AAAAAAA;
    rg_nmi = 1'h0;
    rg_nmi_vector = 32'hAAAAAAAA;
    rg_satp = 32'hAAAAAAAA;
    rg_scause = 5'h0A;
    rg_sepc = 32'hAAAAAAAA;
    rg_sscratch = 32'hAAAAAAAA;
    rg_state = 1'h0;
    rg_stval = 32'hAAAAAAAA;
    rg_stvec = 31'h2AAAAAAA;
    rg_tdata1 = 32'hAAAAAAAA;
    rg_tdata2 = 32'hAAAAAAAA;
    rg_tdata3 = 32'hAAAAAAAA;
    rg_tselect = 32'hAAAAAAAA;
  end
  `endif // BSV_NO_INITIAL_BLOCKS
  // synopsys translate_on

  // handling of system tasks

  // synopsys translate_off
  always@(negedge CLK)
  begin
    #0;
    if (RST_N != `BSV_RESET_VALUE)
      if (EN_debug) $display("mstatus = 0x%0h", csr_mstatus_rg_mstatus);
    if (RST_N != `BSV_RESET_VALUE)
      if (EN_debug)
	$display("sstatus = 0x%0h",
		 { csr_mstatus_rg_mstatus[31],
		   11'd0,
		   csr_mstatus_rg_mstatus[19:18],
		   1'd0,
		   csr_mstatus_rg_mstatus[16:13],
		   4'd0,
		   csr_mstatus_rg_mstatus[8],
		   2'd0,
		   csr_mstatus_rg_mstatus[5:4],
		   2'd0,
		   csr_mstatus_rg_mstatus[1:0] });
    if (RST_N != `BSV_RESET_VALUE)
      if (EN_debug) $display("mip     = 0x%0h", csr_mip$fv_read);
    if (RST_N != `BSV_RESET_VALUE)
      if (EN_debug) $display("sip     = 0x%0h", csr_mip$fv_sip_read);
    if (RST_N != `BSV_RESET_VALUE)
      if (EN_debug) $display("mie     = 0x%0h", csr_mie$fv_read);
    if (RST_N != `BSV_RESET_VALUE)
      if (EN_debug) $display("sie     = 0x%0h", csr_mie$fv_sie_read);
    if (RST_N != `BSV_RESET_VALUE)
      if (EN_mav_csr_write &&
	  mav_csr_write_csr_addr_ULT_0xB03_63_OR_NOT_mav_ETC___d1147 &&
	  NOT_cfg_verbosity_read__148_ULE_1_149___d1150)
	$display("%0d: ERROR: CSR-write addr 0x%0h val 0x%0h not successful",
		 rg_mcycle,
		 mav_csr_write_csr_addr,
		 mav_csr_write_word);
    if (RST_N != `BSV_RESET_VALUE)
      if (EN_csr_trap_actions &&
	  NOT_cfg_verbosity_read__148_ULE_1_149___d1150)
	$display("%0d: CSR_Regfile.csr_trap_actions:", rg_mcycle);
    if (RST_N != `BSV_RESET_VALUE)
      if (EN_csr_trap_actions &&
	  NOT_cfg_verbosity_read__148_ULE_1_149___d1150)
	$display("    from priv %0d  pc 0x%0h  interrupt %0d  exc_code %0d  xtval 0x%0h",
		 csr_trap_actions_from_priv,
		 csr_trap_actions_pc,
		 csr_trap_actions_interrupt,
		 csr_trap_actions_exc_code,
		 csr_trap_actions_xtval);
    if (RST_N != `BSV_RESET_VALUE)
      if (EN_csr_trap_actions &&
	  NOT_cfg_verbosity_read__148_ULE_1_149___d1150)
	$write("    priv %0d: ", 2'b01);
    if (RST_N != `BSV_RESET_VALUE)
      if (EN_csr_trap_actions &&
	  NOT_cfg_verbosity_read__148_ULE_1_149___d1150)
	$write(" ip: 0x%0h", csr_mip$fv_read);
    if (RST_N != `BSV_RESET_VALUE)
      if (EN_csr_trap_actions &&
	  NOT_cfg_verbosity_read__148_ULE_1_149___d1150)
	$write(" ie: 0x%0h", csr_mie$fv_read);
    if (RST_N != `BSV_RESET_VALUE)
      if (EN_csr_trap_actions &&
	  NOT_cfg_verbosity_read__148_ULE_1_149___d1150)
	$write(" edeleg: 0x%0h", 16'd0);
    if (RST_N != `BSV_RESET_VALUE)
      if (EN_csr_trap_actions &&
	  NOT_cfg_verbosity_read__148_ULE_1_149___d1150)
	$write(" ideleg: 0x%0h", 12'd0);
    if (RST_N != `BSV_RESET_VALUE)
      if (EN_csr_trap_actions &&
	  NOT_cfg_verbosity_read__148_ULE_1_149___d1150)
	$write(" cause:");
    if (RST_N != `BSV_RESET_VALUE)
      if (EN_csr_trap_actions &&
	  NOT_cfg_verbosity_read__148_ULE_1_149___d1150 &&
	  rg_scause[4] &&
	  rg_scause[3:0] == 4'd0)
	$write("USER_SW_INTERRUPT");
    if (RST_N != `BSV_RESET_VALUE)
      if (EN_csr_trap_actions &&
	  NOT_cfg_verbosity_read__148_ULE_1_149___d1150 &&
	  rg_scause[4] &&
	  rg_scause[3:0] == 4'd1)
	$write("SUPERVISOR_SW_INTERRUPT");
    if (RST_N != `BSV_RESET_VALUE)
      if (EN_csr_trap_actions &&
	  NOT_cfg_verbosity_read__148_ULE_1_149___d1150 &&
	  rg_scause[4] &&
	  rg_scause[3:0] == 4'd2)
	$write("HYPERVISOR_SW_INTERRUPT");
    if (RST_N != `BSV_RESET_VALUE)
      if (EN_csr_trap_actions &&
	  NOT_cfg_verbosity_read__148_ULE_1_149___d1150 &&
	  rg_scause[4] &&
	  rg_scause[3:0] == 4'd3)
	$write("MACHINE_SW_INTERRUPT");
    if (RST_N != `BSV_RESET_VALUE)
      if (EN_csr_trap_actions &&
	  NOT_cfg_verbosity_read__148_ULE_1_149___d1150 &&
	  rg_scause[4] &&
	  rg_scause[3:0] == 4'd4)
	$write("USER_TIMER_INTERRUPT");
    if (RST_N != `BSV_RESET_VALUE)
      if (EN_csr_trap_actions &&
	  NOT_cfg_verbosity_read__148_ULE_1_149___d1150 &&
	  rg_scause[4] &&
	  rg_scause[3:0] == 4'd5)
	$write("SUPERVISOR_TIMER_INTERRUPT");
    if (RST_N != `BSV_RESET_VALUE)
      if (EN_csr_trap_actions &&
	  NOT_cfg_verbosity_read__148_ULE_1_149___d1150 &&
	  rg_scause[4] &&
	  rg_scause[3:0] == 4'd6)
	$write("HYPERVISOR_TIMER_INTERRUPT");
    if (RST_N != `BSV_RESET_VALUE)
      if (EN_csr_trap_actions &&
	  NOT_cfg_verbosity_read__148_ULE_1_149___d1150 &&
	  rg_scause[4] &&
	  rg_scause[3:0] == 4'd7)
	$write("MACHINE_TIMER_INTERRUPT");
    if (RST_N != `BSV_RESET_VALUE)
      if (EN_csr_trap_actions &&
	  NOT_cfg_verbosity_read__148_ULE_1_149___d1150 &&
	  rg_scause[4] &&
	  rg_scause[3:0] == 4'd8)
	$write("USER_EXTERNAL_INTERRUPT");
    if (RST_N != `BSV_RESET_VALUE)
      if (EN_csr_trap_actions &&
	  NOT_cfg_verbosity_read__148_ULE_1_149___d1150 &&
	  rg_scause[4] &&
	  rg_scause[3:0] == 4'd9)
	$write("SUPERVISOR_EXTERNAL_INTERRUPT");
    if (RST_N != `BSV_RESET_VALUE)
      if (EN_csr_trap_actions &&
	  NOT_cfg_verbosity_read__148_ULE_1_149___d1150 &&
	  rg_scause[4] &&
	  rg_scause[3:0] == 4'd10)
	$write("HYPERVISOR_EXTERNAL_INTERRUPT");
    if (RST_N != `BSV_RESET_VALUE)
      if (EN_csr_trap_actions &&
	  NOT_cfg_verbosity_read__148_ULE_1_149___d1150 &&
	  rg_scause[4] &&
	  rg_scause[3:0] == 4'd11)
	$write("MACHINE_EXTERNAL_INTERRUPT");
    if (RST_N != `BSV_RESET_VALUE)
      if (EN_csr_trap_actions &&
	  NOT_cfg_verbosity_read__148_ULE_1_149___d1150 &&
	  rg_scause[4] &&
	  rg_scause[3:0] != 4'd0 &&
	  rg_scause[3:0] != 4'd1 &&
	  rg_scause[3:0] != 4'd2 &&
	  rg_scause[3:0] != 4'd3 &&
	  rg_scause[3:0] != 4'd4 &&
	  rg_scause[3:0] != 4'd5 &&
	  rg_scause[3:0] != 4'd6 &&
	  rg_scause[3:0] != 4'd7 &&
	  rg_scause[3:0] != 4'd8 &&
	  rg_scause[3:0] != 4'd9 &&
	  rg_scause[3:0] != 4'd10 &&
	  rg_scause[3:0] != 4'd11)
	$write("unknown interrupt Exc_Code %d", rg_scause[3:0]);
    if (RST_N != `BSV_RESET_VALUE)
      if (EN_csr_trap_actions &&
	  NOT_cfg_verbosity_read__148_ULE_1_149___d1150 &&
	  !rg_scause[4] &&
	  rg_scause[3:0] == 4'd0)
	$write("INSTRUCTION_ADDR_MISALIGNED");
    if (RST_N != `BSV_RESET_VALUE)
      if (EN_csr_trap_actions &&
	  NOT_cfg_verbosity_read__148_ULE_1_149___d1150 &&
	  !rg_scause[4] &&
	  rg_scause[3:0] == 4'd1)
	$write("INSTRUCTION_ACCESS_FAULT");
    if (RST_N != `BSV_RESET_VALUE)
      if (EN_csr_trap_actions &&
	  NOT_cfg_verbosity_read__148_ULE_1_149___d1150 &&
	  !rg_scause[4] &&
	  rg_scause[3:0] == 4'd2)
	$write("ILLEGAL_INSTRUCTION");
    if (RST_N != `BSV_RESET_VALUE)
      if (EN_csr_trap_actions &&
	  NOT_cfg_verbosity_read__148_ULE_1_149___d1150 &&
	  !rg_scause[4] &&
	  rg_scause[3:0] == 4'd3)
	$write("BREAKPOINT");
    if (RST_N != `BSV_RESET_VALUE)
      if (EN_csr_trap_actions &&
	  NOT_cfg_verbosity_read__148_ULE_1_149___d1150 &&
	  !rg_scause[4] &&
	  rg_scause[3:0] == 4'd4)
	$write("LOAD_ADDR_MISALIGNED");
    if (RST_N != `BSV_RESET_VALUE)
      if (EN_csr_trap_actions &&
	  NOT_cfg_verbosity_read__148_ULE_1_149___d1150 &&
	  !rg_scause[4] &&
	  rg_scause[3:0] == 4'd5)
	$write("LOAD_ACCESS_FAULT");
    if (RST_N != `BSV_RESET_VALUE)
      if (EN_csr_trap_actions &&
	  NOT_cfg_verbosity_read__148_ULE_1_149___d1150 &&
	  !rg_scause[4] &&
	  rg_scause[3:0] == 4'd6)
	$write("STORE_AMO_ADDR_MISALIGNED");
    if (RST_N != `BSV_RESET_VALUE)
      if (EN_csr_trap_actions &&
	  NOT_cfg_verbosity_read__148_ULE_1_149___d1150 &&
	  !rg_scause[4] &&
	  rg_scause[3:0] == 4'd7)
	$write("STORE_AMO_ACCESS_FAULT");
    if (RST_N != `BSV_RESET_VALUE)
      if (EN_csr_trap_actions &&
	  NOT_cfg_verbosity_read__148_ULE_1_149___d1150 &&
	  !rg_scause[4] &&
	  rg_scause[3:0] == 4'd8)
	$write("ECALL_FROM_U");
    if (RST_N != `BSV_RESET_VALUE)
      if (EN_csr_trap_actions &&
	  NOT_cfg_verbosity_read__148_ULE_1_149___d1150 &&
	  !rg_scause[4] &&
	  rg_scause[3:0] == 4'd9)
	$write("ECALL_FROM_S");
    if (RST_N != `BSV_RESET_VALUE)
      if (EN_csr_trap_actions &&
	  NOT_cfg_verbosity_read__148_ULE_1_149___d1150 &&
	  !rg_scause[4] &&
	  rg_scause[3:0] == 4'd11)
	$write("ECALL_FROM_M");
    if (RST_N != `BSV_RESET_VALUE)
      if (EN_csr_trap_actions &&
	  NOT_cfg_verbosity_read__148_ULE_1_149___d1150 &&
	  !rg_scause[4] &&
	  rg_scause[3:0] == 4'd12)
	$write("INSTRUCTION_PAGE_FAULT");
    if (RST_N != `BSV_RESET_VALUE)
      if (EN_csr_trap_actions &&
	  NOT_cfg_verbosity_read__148_ULE_1_149___d1150 &&
	  !rg_scause[4] &&
	  rg_scause[3:0] == 4'd13)
	$write("LOAD_PAGE_FAULT");
    if (RST_N != `BSV_RESET_VALUE)
      if (EN_csr_trap_actions &&
	  NOT_cfg_verbosity_read__148_ULE_1_149___d1150 &&
	  !rg_scause[4] &&
	  rg_scause[3:0] == 4'd15)
	$write("STORE_AMO_PAGE_FAULT");
    if (RST_N != `BSV_RESET_VALUE)
      if (EN_csr_trap_actions &&
	  NOT_cfg_verbosity_read__148_ULE_1_149___d1150 &&
	  !rg_scause[4] &&
	  rg_scause[3:0] != 4'd0 &&
	  rg_scause[3:0] != 4'd1 &&
	  rg_scause[3:0] != 4'd2 &&
	  rg_scause[3:0] != 4'd3 &&
	  rg_scause[3:0] != 4'd4 &&
	  rg_scause[3:0] != 4'd5 &&
	  rg_scause[3:0] != 4'd6 &&
	  rg_scause[3:0] != 4'd7 &&
	  rg_scause[3:0] != 4'd8 &&
	  rg_scause[3:0] != 4'd9 &&
	  rg_scause[3:0] != 4'd11 &&
	  rg_scause[3:0] != 4'd12 &&
	  rg_scause[3:0] != 4'd13 &&
	  rg_scause[3:0] != 4'd15)
	$write("unknown trap Exc_Code %d", rg_scause[3:0]);
    if (RST_N != `BSV_RESET_VALUE)
      if (EN_csr_trap_actions &&
	  NOT_cfg_verbosity_read__148_ULE_1_149___d1150)
	$display("");
    if (RST_N != `BSV_RESET_VALUE)
      if (EN_csr_trap_actions &&
	  NOT_cfg_verbosity_read__148_ULE_1_149___d1150)
	$write("        ");
    if (RST_N != `BSV_RESET_VALUE)
      if (EN_csr_trap_actions &&
	  NOT_cfg_verbosity_read__148_ULE_1_149___d1150)
	$write(" status: 0x%0h",
	       { csr_mstatus_rg_mstatus[31],
		 11'd0,
		 csr_mstatus_rg_mstatus[19:18],
		 1'd0,
		 csr_mstatus_rg_mstatus[16:13],
		 4'd0,
		 csr_mstatus_rg_mstatus[8],
		 2'd0,
		 csr_mstatus_rg_mstatus[5:4],
		 2'd0,
		 csr_mstatus_rg_mstatus[1:0] });
    if (RST_N != `BSV_RESET_VALUE)
      if (EN_csr_trap_actions &&
	  NOT_cfg_verbosity_read__148_ULE_1_149___d1150)
	$write(" tvec: 0x%0h", { rg_stvec[30:1], 1'b0, rg_stvec[0] });
    if (RST_N != `BSV_RESET_VALUE)
      if (EN_csr_trap_actions &&
	  NOT_cfg_verbosity_read__148_ULE_1_149___d1150)
	$write(" epc: 0x%0h", rg_sepc);
    if (RST_N != `BSV_RESET_VALUE)
      if (EN_csr_trap_actions &&
	  NOT_cfg_verbosity_read__148_ULE_1_149___d1150)
	$write(" tval: 0x%0h", rg_stval);
    if (RST_N != `BSV_RESET_VALUE)
      if (EN_csr_trap_actions &&
	  NOT_cfg_verbosity_read__148_ULE_1_149___d1150)
	$display("");
    if (RST_N != `BSV_RESET_VALUE)
      if (EN_csr_trap_actions &&
	  NOT_cfg_verbosity_read__148_ULE_1_149___d1150)
	$write("    priv %0d: ", 2'b11);
    if (RST_N != `BSV_RESET_VALUE)
      if (EN_csr_trap_actions &&
	  NOT_cfg_verbosity_read__148_ULE_1_149___d1150)
	$write(" ip: 0x%0h", csr_mip$fv_read);
    if (RST_N != `BSV_RESET_VALUE)
      if (EN_csr_trap_actions &&
	  NOT_cfg_verbosity_read__148_ULE_1_149___d1150)
	$write(" ie: 0x%0h", csr_mie$fv_read);
    if (RST_N != `BSV_RESET_VALUE)
      if (EN_csr_trap_actions &&
	  NOT_cfg_verbosity_read__148_ULE_1_149___d1150)
	$write(" edeleg: 0x%0h", rg_medeleg);
    if (RST_N != `BSV_RESET_VALUE)
      if (EN_csr_trap_actions &&
	  NOT_cfg_verbosity_read__148_ULE_1_149___d1150)
	$write(" ideleg: 0x%0h", rg_mideleg);
    if (RST_N != `BSV_RESET_VALUE)
      if (EN_csr_trap_actions &&
	  NOT_cfg_verbosity_read__148_ULE_1_149___d1150)
	$write(" cause:");
    if (RST_N != `BSV_RESET_VALUE)
      if (EN_csr_trap_actions &&
	  NOT_cfg_verbosity_read__148_ULE_1_149___d1150 &&
	  rg_mcause[4] &&
	  rg_mcause[3:0] == 4'd0)
	$write("USER_SW_INTERRUPT");
    if (RST_N != `BSV_RESET_VALUE)
      if (EN_csr_trap_actions &&
	  NOT_cfg_verbosity_read__148_ULE_1_149___d1150 &&
	  rg_mcause[4] &&
	  rg_mcause[3:0] == 4'd1)
	$write("SUPERVISOR_SW_INTERRUPT");
    if (RST_N != `BSV_RESET_VALUE)
      if (EN_csr_trap_actions &&
	  NOT_cfg_verbosity_read__148_ULE_1_149___d1150 &&
	  rg_mcause[4] &&
	  rg_mcause[3:0] == 4'd2)
	$write("HYPERVISOR_SW_INTERRUPT");
    if (RST_N != `BSV_RESET_VALUE)
      if (EN_csr_trap_actions &&
	  NOT_cfg_verbosity_read__148_ULE_1_149___d1150 &&
	  rg_mcause[4] &&
	  rg_mcause[3:0] == 4'd3)
	$write("MACHINE_SW_INTERRUPT");
    if (RST_N != `BSV_RESET_VALUE)
      if (EN_csr_trap_actions &&
	  NOT_cfg_verbosity_read__148_ULE_1_149___d1150 &&
	  rg_mcause[4] &&
	  rg_mcause[3:0] == 4'd4)
	$write("USER_TIMER_INTERRUPT");
    if (RST_N != `BSV_RESET_VALUE)
      if (EN_csr_trap_actions &&
	  NOT_cfg_verbosity_read__148_ULE_1_149___d1150 &&
	  rg_mcause[4] &&
	  rg_mcause[3:0] == 4'd5)
	$write("SUPERVISOR_TIMER_INTERRUPT");
    if (RST_N != `BSV_RESET_VALUE)
      if (EN_csr_trap_actions &&
	  NOT_cfg_verbosity_read__148_ULE_1_149___d1150 &&
	  rg_mcause[4] &&
	  rg_mcause[3:0] == 4'd6)
	$write("HYPERVISOR_TIMER_INTERRUPT");
    if (RST_N != `BSV_RESET_VALUE)
      if (EN_csr_trap_actions &&
	  NOT_cfg_verbosity_read__148_ULE_1_149___d1150 &&
	  rg_mcause[4] &&
	  rg_mcause[3:0] == 4'd7)
	$write("MACHINE_TIMER_INTERRUPT");
    if (RST_N != `BSV_RESET_VALUE)
      if (EN_csr_trap_actions &&
	  NOT_cfg_verbosity_read__148_ULE_1_149___d1150 &&
	  rg_mcause[4] &&
	  rg_mcause[3:0] == 4'd8)
	$write("USER_EXTERNAL_INTERRUPT");
    if (RST_N != `BSV_RESET_VALUE)
      if (EN_csr_trap_actions &&
	  NOT_cfg_verbosity_read__148_ULE_1_149___d1150 &&
	  rg_mcause[4] &&
	  rg_mcause[3:0] == 4'd9)
	$write("SUPERVISOR_EXTERNAL_INTERRUPT");
    if (RST_N != `BSV_RESET_VALUE)
      if (EN_csr_trap_actions &&
	  NOT_cfg_verbosity_read__148_ULE_1_149___d1150 &&
	  rg_mcause[4] &&
	  rg_mcause[3:0] == 4'd10)
	$write("HYPERVISOR_EXTERNAL_INTERRUPT");
    if (RST_N != `BSV_RESET_VALUE)
      if (EN_csr_trap_actions &&
	  NOT_cfg_verbosity_read__148_ULE_1_149___d1150 &&
	  rg_mcause[4] &&
	  rg_mcause[3:0] == 4'd11)
	$write("MACHINE_EXTERNAL_INTERRUPT");
    if (RST_N != `BSV_RESET_VALUE)
      if (EN_csr_trap_actions &&
	  NOT_cfg_verbosity_read__148_ULE_1_149___d1150 &&
	  rg_mcause[4] &&
	  rg_mcause[3:0] != 4'd0 &&
	  rg_mcause[3:0] != 4'd1 &&
	  rg_mcause[3:0] != 4'd2 &&
	  rg_mcause[3:0] != 4'd3 &&
	  rg_mcause[3:0] != 4'd4 &&
	  rg_mcause[3:0] != 4'd5 &&
	  rg_mcause[3:0] != 4'd6 &&
	  rg_mcause[3:0] != 4'd7 &&
	  rg_mcause[3:0] != 4'd8 &&
	  rg_mcause[3:0] != 4'd9 &&
	  rg_mcause[3:0] != 4'd10 &&
	  rg_mcause[3:0] != 4'd11)
	$write("unknown interrupt Exc_Code %d", rg_mcause[3:0]);
    if (RST_N != `BSV_RESET_VALUE)
      if (EN_csr_trap_actions &&
	  NOT_cfg_verbosity_read__148_ULE_1_149___d1150 &&
	  !rg_mcause[4] &&
	  rg_mcause[3:0] == 4'd0)
	$write("INSTRUCTION_ADDR_MISALIGNED");
    if (RST_N != `BSV_RESET_VALUE)
      if (EN_csr_trap_actions &&
	  NOT_cfg_verbosity_read__148_ULE_1_149___d1150 &&
	  !rg_mcause[4] &&
	  rg_mcause[3:0] == 4'd1)
	$write("INSTRUCTION_ACCESS_FAULT");
    if (RST_N != `BSV_RESET_VALUE)
      if (EN_csr_trap_actions &&
	  NOT_cfg_verbosity_read__148_ULE_1_149___d1150 &&
	  !rg_mcause[4] &&
	  rg_mcause[3:0] == 4'd2)
	$write("ILLEGAL_INSTRUCTION");
    if (RST_N != `BSV_RESET_VALUE)
      if (EN_csr_trap_actions &&
	  NOT_cfg_verbosity_read__148_ULE_1_149___d1150 &&
	  !rg_mcause[4] &&
	  rg_mcause[3:0] == 4'd3)
	$write("BREAKPOINT");
    if (RST_N != `BSV_RESET_VALUE)
      if (EN_csr_trap_actions &&
	  NOT_cfg_verbosity_read__148_ULE_1_149___d1150 &&
	  !rg_mcause[4] &&
	  rg_mcause[3:0] == 4'd4)
	$write("LOAD_ADDR_MISALIGNED");
    if (RST_N != `BSV_RESET_VALUE)
      if (EN_csr_trap_actions &&
	  NOT_cfg_verbosity_read__148_ULE_1_149___d1150 &&
	  !rg_mcause[4] &&
	  rg_mcause[3:0] == 4'd5)
	$write("LOAD_ACCESS_FAULT");
    if (RST_N != `BSV_RESET_VALUE)
      if (EN_csr_trap_actions &&
	  NOT_cfg_verbosity_read__148_ULE_1_149___d1150 &&
	  !rg_mcause[4] &&
	  rg_mcause[3:0] == 4'd6)
	$write("STORE_AMO_ADDR_MISALIGNED");
    if (RST_N != `BSV_RESET_VALUE)
      if (EN_csr_trap_actions &&
	  NOT_cfg_verbosity_read__148_ULE_1_149___d1150 &&
	  !rg_mcause[4] &&
	  rg_mcause[3:0] == 4'd7)
	$write("STORE_AMO_ACCESS_FAULT");
    if (RST_N != `BSV_RESET_VALUE)
      if (EN_csr_trap_actions &&
	  NOT_cfg_verbosity_read__148_ULE_1_149___d1150 &&
	  !rg_mcause[4] &&
	  rg_mcause[3:0] == 4'd8)
	$write("ECALL_FROM_U");
    if (RST_N != `BSV_RESET_VALUE)
      if (EN_csr_trap_actions &&
	  NOT_cfg_verbosity_read__148_ULE_1_149___d1150 &&
	  !rg_mcause[4] &&
	  rg_mcause[3:0] == 4'd9)
	$write("ECALL_FROM_S");
    if (RST_N != `BSV_RESET_VALUE)
      if (EN_csr_trap_actions &&
	  NOT_cfg_verbosity_read__148_ULE_1_149___d1150 &&
	  !rg_mcause[4] &&
	  rg_mcause[3:0] == 4'd11)
	$write("ECALL_FROM_M");
    if (RST_N != `BSV_RESET_VALUE)
      if (EN_csr_trap_actions &&
	  NOT_cfg_verbosity_read__148_ULE_1_149___d1150 &&
	  !rg_mcause[4] &&
	  rg_mcause[3:0] == 4'd12)
	$write("INSTRUCTION_PAGE_FAULT");
    if (RST_N != `BSV_RESET_VALUE)
      if (EN_csr_trap_actions &&
	  NOT_cfg_verbosity_read__148_ULE_1_149___d1150 &&
	  !rg_mcause[4] &&
	  rg_mcause[3:0] == 4'd13)
	$write("LOAD_PAGE_FAULT");
    if (RST_N != `BSV_RESET_VALUE)
      if (EN_csr_trap_actions &&
	  NOT_cfg_verbosity_read__148_ULE_1_149___d1150 &&
	  !rg_mcause[4] &&
	  rg_mcause[3:0] == 4'd15)
	$write("STORE_AMO_PAGE_FAULT");
    if (RST_N != `BSV_RESET_VALUE)
      if (EN_csr_trap_actions &&
	  NOT_cfg_verbosity_read__148_ULE_1_149___d1150 &&
	  !rg_mcause[4] &&
	  rg_mcause[3:0] != 4'd0 &&
	  rg_mcause[3:0] != 4'd1 &&
	  rg_mcause[3:0] != 4'd2 &&
	  rg_mcause[3:0] != 4'd3 &&
	  rg_mcause[3:0] != 4'd4 &&
	  rg_mcause[3:0] != 4'd5 &&
	  rg_mcause[3:0] != 4'd6 &&
	  rg_mcause[3:0] != 4'd7 &&
	  rg_mcause[3:0] != 4'd8 &&
	  rg_mcause[3:0] != 4'd9 &&
	  rg_mcause[3:0] != 4'd11 &&
	  rg_mcause[3:0] != 4'd12 &&
	  rg_mcause[3:0] != 4'd13 &&
	  rg_mcause[3:0] != 4'd15)
	$write("unknown trap Exc_Code %d", rg_mcause[3:0]);
    if (RST_N != `BSV_RESET_VALUE)
      if (EN_csr_trap_actions &&
	  NOT_cfg_verbosity_read__148_ULE_1_149___d1150)
	$display("");
    if (RST_N != `BSV_RESET_VALUE)
      if (EN_csr_trap_actions &&
	  NOT_cfg_verbosity_read__148_ULE_1_149___d1150)
	$write("        ");
    if (RST_N != `BSV_RESET_VALUE)
      if (EN_csr_trap_actions &&
	  NOT_cfg_verbosity_read__148_ULE_1_149___d1150)
	$write(" status: 0x%0h", csr_mstatus_rg_mstatus);
    if (RST_N != `BSV_RESET_VALUE)
      if (EN_csr_trap_actions &&
	  NOT_cfg_verbosity_read__148_ULE_1_149___d1150)
	$write(" tvec: 0x%0h", { rg_mtvec[30:1], 1'b0, rg_mtvec[0] });
    if (RST_N != `BSV_RESET_VALUE)
      if (EN_csr_trap_actions &&
	  NOT_cfg_verbosity_read__148_ULE_1_149___d1150)
	$write(" epc: 0x%0h", rg_mepc);
    if (RST_N != `BSV_RESET_VALUE)
      if (EN_csr_trap_actions &&
	  NOT_cfg_verbosity_read__148_ULE_1_149___d1150)
	$write(" tval: 0x%0h", rg_mtval);
    if (RST_N != `BSV_RESET_VALUE)
      if (EN_csr_trap_actions &&
	  NOT_cfg_verbosity_read__148_ULE_1_149___d1150)
	$display("");
    if (RST_N != `BSV_RESET_VALUE)
      if (EN_csr_trap_actions &&
	  NOT_cfg_verbosity_read__148_ULE_1_149___d1150)
	$write("    Return: new pc 0x%0h  ", x__h9768);
    if (RST_N != `BSV_RESET_VALUE)
      if (EN_csr_trap_actions &&
	  NOT_cfg_verbosity_read__148_ULE_1_149___d1150)
	$write(" new mstatus:");
    if (RST_N != `BSV_RESET_VALUE)
      if (EN_csr_trap_actions &&
	  NOT_cfg_verbosity_read__148_ULE_1_149___d1150)
	$write("MStatus{",
	       "sd:%0d",
	       x__h12806[14:13] == 2'h3 || x__h12806[16:15] == 2'h3);
    if (RST_N != `BSV_RESET_VALUE)
      if (EN_csr_trap_actions &&
	  NOT_cfg_verbosity_read__148_ULE_1_149___d1150)
	$write("");
    if (RST_N != `BSV_RESET_VALUE)
      if (EN_csr_trap_actions &&
	  NOT_cfg_verbosity_read__148_ULE_1_149___d1150)
	$write(" tsr:%0d", x__h12806[22]);
    if (RST_N != `BSV_RESET_VALUE)
      if (EN_csr_trap_actions &&
	  NOT_cfg_verbosity_read__148_ULE_1_149___d1150)
	$write(" tw:%0d", x__h12806[21]);
    if (RST_N != `BSV_RESET_VALUE)
      if (EN_csr_trap_actions &&
	  NOT_cfg_verbosity_read__148_ULE_1_149___d1150)
	$write(" tvm:%0d", x__h12806[20]);
    if (RST_N != `BSV_RESET_VALUE)
      if (EN_csr_trap_actions &&
	  NOT_cfg_verbosity_read__148_ULE_1_149___d1150)
	$write(" mxr:%0d", x__h12806[19]);
    if (RST_N != `BSV_RESET_VALUE)
      if (EN_csr_trap_actions &&
	  NOT_cfg_verbosity_read__148_ULE_1_149___d1150)
	$write(" sum:%0d", x__h12806[18]);
    if (RST_N != `BSV_RESET_VALUE)
      if (EN_csr_trap_actions &&
	  NOT_cfg_verbosity_read__148_ULE_1_149___d1150)
	$write(" mprv:%0d", x__h12806[17]);
    if (RST_N != `BSV_RESET_VALUE)
      if (EN_csr_trap_actions &&
	  NOT_cfg_verbosity_read__148_ULE_1_149___d1150)
	$write(" xs:%0d", x__h12806[16:15]);
    if (RST_N != `BSV_RESET_VALUE)
      if (EN_csr_trap_actions &&
	  NOT_cfg_verbosity_read__148_ULE_1_149___d1150)
	$write(" fs:%0d", x__h12806[14:13]);
    if (RST_N != `BSV_RESET_VALUE)
      if (EN_csr_trap_actions &&
	  NOT_cfg_verbosity_read__148_ULE_1_149___d1150)
	$write(" mpp:%0d", x__h12806[12:11]);
    if (RST_N != `BSV_RESET_VALUE)
      if (EN_csr_trap_actions &&
	  NOT_cfg_verbosity_read__148_ULE_1_149___d1150)
	$write(" spp:%0d", x__h12806[8]);
    if (RST_N != `BSV_RESET_VALUE)
      if (EN_csr_trap_actions &&
	  NOT_cfg_verbosity_read__148_ULE_1_149___d1150)
	$write(" pies:%0d_%0d%0d", x__h12806[7], x__h12806[5], x__h12806[4]);
    if (RST_N != `BSV_RESET_VALUE)
      if (EN_csr_trap_actions &&
	  NOT_cfg_verbosity_read__148_ULE_1_149___d1150)
	$write(" ies:%0d_%0d%0d", x__h12806[3], x__h12806[1], x__h12806[0]);
    if (RST_N != `BSV_RESET_VALUE)
      if (EN_csr_trap_actions &&
	  NOT_cfg_verbosity_read__148_ULE_1_149___d1150)
	$write("}");
    if (RST_N != `BSV_RESET_VALUE)
      if (EN_csr_trap_actions &&
	  NOT_cfg_verbosity_read__148_ULE_1_149___d1150)
	$write(" new xcause:");
    if (RST_N != `BSV_RESET_VALUE)
      if (EN_csr_trap_actions &&
	  NOT_cfg_verbosity_read__148_ULE_1_149___d1150 &&
	  !csr_trap_actions_nmi &&
	  csr_trap_actions_interrupt &&
	  exc_code__h12648 == 4'd0)
	$write("USER_SW_INTERRUPT");
    if (RST_N != `BSV_RESET_VALUE)
      if (EN_csr_trap_actions &&
	  NOT_cfg_verbosity_read__148_ULE_1_149___d1150 &&
	  !csr_trap_actions_nmi &&
	  csr_trap_actions_interrupt &&
	  exc_code__h12648 == 4'd1)
	$write("SUPERVISOR_SW_INTERRUPT");
    if (RST_N != `BSV_RESET_VALUE)
      if (EN_csr_trap_actions &&
	  NOT_cfg_verbosity_read__148_ULE_1_149___d1150 &&
	  !csr_trap_actions_nmi &&
	  csr_trap_actions_interrupt &&
	  exc_code__h12648 == 4'd2)
	$write("HYPERVISOR_SW_INTERRUPT");
    if (RST_N != `BSV_RESET_VALUE)
      if (EN_csr_trap_actions &&
	  NOT_cfg_verbosity_read__148_ULE_1_149___d1150 &&
	  !csr_trap_actions_nmi &&
	  csr_trap_actions_interrupt &&
	  exc_code__h12648 == 4'd3)
	$write("MACHINE_SW_INTERRUPT");
    if (RST_N != `BSV_RESET_VALUE)
      if (EN_csr_trap_actions &&
	  NOT_cfg_verbosity_read__148_ULE_1_149___d1150 &&
	  !csr_trap_actions_nmi &&
	  csr_trap_actions_interrupt &&
	  exc_code__h12648 == 4'd4)
	$write("USER_TIMER_INTERRUPT");
    if (RST_N != `BSV_RESET_VALUE)
      if (EN_csr_trap_actions &&
	  NOT_cfg_verbosity_read__148_ULE_1_149___d1150 &&
	  !csr_trap_actions_nmi &&
	  csr_trap_actions_interrupt &&
	  exc_code__h12648 == 4'd5)
	$write("SUPERVISOR_TIMER_INTERRUPT");
    if (RST_N != `BSV_RESET_VALUE)
      if (EN_csr_trap_actions &&
	  NOT_cfg_verbosity_read__148_ULE_1_149___d1150 &&
	  !csr_trap_actions_nmi &&
	  csr_trap_actions_interrupt &&
	  exc_code__h12648 == 4'd6)
	$write("HYPERVISOR_TIMER_INTERRUPT");
    if (RST_N != `BSV_RESET_VALUE)
      if (EN_csr_trap_actions &&
	  NOT_cfg_verbosity_read__148_ULE_1_149___d1150 &&
	  !csr_trap_actions_nmi &&
	  csr_trap_actions_interrupt &&
	  exc_code__h12648 == 4'd7)
	$write("MACHINE_TIMER_INTERRUPT");
    if (RST_N != `BSV_RESET_VALUE)
      if (EN_csr_trap_actions &&
	  NOT_cfg_verbosity_read__148_ULE_1_149___d1150 &&
	  !csr_trap_actions_nmi &&
	  csr_trap_actions_interrupt &&
	  exc_code__h12648 == 4'd8)
	$write("USER_EXTERNAL_INTERRUPT");
    if (RST_N != `BSV_RESET_VALUE)
      if (EN_csr_trap_actions &&
	  NOT_cfg_verbosity_read__148_ULE_1_149___d1150 &&
	  !csr_trap_actions_nmi &&
	  csr_trap_actions_interrupt &&
	  exc_code__h12648 == 4'd9)
	$write("SUPERVISOR_EXTERNAL_INTERRUPT");
    if (RST_N != `BSV_RESET_VALUE)
      if (EN_csr_trap_actions &&
	  NOT_cfg_verbosity_read__148_ULE_1_149___d1150 &&
	  !csr_trap_actions_nmi &&
	  csr_trap_actions_interrupt &&
	  exc_code__h12648 == 4'd10)
	$write("HYPERVISOR_EXTERNAL_INTERRUPT");
    if (RST_N != `BSV_RESET_VALUE)
      if (EN_csr_trap_actions &&
	  NOT_cfg_verbosity_read__148_ULE_1_149___d1150 &&
	  !csr_trap_actions_nmi &&
	  csr_trap_actions_interrupt &&
	  exc_code__h12648 == 4'd11)
	$write("MACHINE_EXTERNAL_INTERRUPT");
    if (RST_N != `BSV_RESET_VALUE)
      if (EN_csr_trap_actions &&
	  NOT_cfg_verbosity_read__148_ULE_1_149___d1150 &&
	  NOT_csr_trap_actions_nmi_499_AND_csr_trap_acti_ETC___d1606)
	$write("unknown interrupt Exc_Code %d", exc_code__h12648);
    if (RST_N != `BSV_RESET_VALUE)
      if (EN_csr_trap_actions &&
	  NOT_cfg_verbosity_read__148_ULE_1_149___d1150 &&
	  (csr_trap_actions_nmi || !csr_trap_actions_interrupt) &&
	  exc_code__h12648 == 4'd0)
	$write("INSTRUCTION_ADDR_MISALIGNED");
    if (RST_N != `BSV_RESET_VALUE)
      if (EN_csr_trap_actions &&
	  NOT_cfg_verbosity_read__148_ULE_1_149___d1150 &&
	  (csr_trap_actions_nmi || !csr_trap_actions_interrupt) &&
	  exc_code__h12648 == 4'd1)
	$write("INSTRUCTION_ACCESS_FAULT");
    if (RST_N != `BSV_RESET_VALUE)
      if (EN_csr_trap_actions &&
	  NOT_cfg_verbosity_read__148_ULE_1_149___d1150 &&
	  (csr_trap_actions_nmi || !csr_trap_actions_interrupt) &&
	  exc_code__h12648 == 4'd2)
	$write("ILLEGAL_INSTRUCTION");
    if (RST_N != `BSV_RESET_VALUE)
      if (EN_csr_trap_actions &&
	  NOT_cfg_verbosity_read__148_ULE_1_149___d1150 &&
	  (csr_trap_actions_nmi || !csr_trap_actions_interrupt) &&
	  exc_code__h12648 == 4'd3)
	$write("BREAKPOINT");
    if (RST_N != `BSV_RESET_VALUE)
      if (EN_csr_trap_actions &&
	  NOT_cfg_verbosity_read__148_ULE_1_149___d1150 &&
	  (csr_trap_actions_nmi || !csr_trap_actions_interrupt) &&
	  exc_code__h12648 == 4'd4)
	$write("LOAD_ADDR_MISALIGNED");
    if (RST_N != `BSV_RESET_VALUE)
      if (EN_csr_trap_actions &&
	  NOT_cfg_verbosity_read__148_ULE_1_149___d1150 &&
	  (csr_trap_actions_nmi || !csr_trap_actions_interrupt) &&
	  exc_code__h12648 == 4'd5)
	$write("LOAD_ACCESS_FAULT");
    if (RST_N != `BSV_RESET_VALUE)
      if (EN_csr_trap_actions &&
	  NOT_cfg_verbosity_read__148_ULE_1_149___d1150 &&
	  (csr_trap_actions_nmi || !csr_trap_actions_interrupt) &&
	  exc_code__h12648 == 4'd6)
	$write("STORE_AMO_ADDR_MISALIGNED");
    if (RST_N != `BSV_RESET_VALUE)
      if (EN_csr_trap_actions &&
	  NOT_cfg_verbosity_read__148_ULE_1_149___d1150 &&
	  (csr_trap_actions_nmi || !csr_trap_actions_interrupt) &&
	  exc_code__h12648 == 4'd7)
	$write("STORE_AMO_ACCESS_FAULT");
    if (RST_N != `BSV_RESET_VALUE)
      if (EN_csr_trap_actions &&
	  NOT_cfg_verbosity_read__148_ULE_1_149___d1150 &&
	  (csr_trap_actions_nmi || !csr_trap_actions_interrupt) &&
	  exc_code__h12648 == 4'd8)
	$write("ECALL_FROM_U");
    if (RST_N != `BSV_RESET_VALUE)
      if (EN_csr_trap_actions &&
	  NOT_cfg_verbosity_read__148_ULE_1_149___d1150 &&
	  (csr_trap_actions_nmi || !csr_trap_actions_interrupt) &&
	  exc_code__h12648 == 4'd9)
	$write("ECALL_FROM_S");
    if (RST_N != `BSV_RESET_VALUE)
      if (EN_csr_trap_actions &&
	  NOT_cfg_verbosity_read__148_ULE_1_149___d1150 &&
	  (csr_trap_actions_nmi || !csr_trap_actions_interrupt) &&
	  exc_code__h12648 == 4'd11)
	$write("ECALL_FROM_M");
    if (RST_N != `BSV_RESET_VALUE)
      if (EN_csr_trap_actions &&
	  NOT_cfg_verbosity_read__148_ULE_1_149___d1150 &&
	  (csr_trap_actions_nmi || !csr_trap_actions_interrupt) &&
	  exc_code__h12648 == 4'd12)
	$write("INSTRUCTION_PAGE_FAULT");
    if (RST_N != `BSV_RESET_VALUE)
      if (EN_csr_trap_actions &&
	  NOT_cfg_verbosity_read__148_ULE_1_149___d1150 &&
	  (csr_trap_actions_nmi || !csr_trap_actions_interrupt) &&
	  exc_code__h12648 == 4'd13)
	$write("LOAD_PAGE_FAULT");
    if (RST_N != `BSV_RESET_VALUE)
      if (EN_csr_trap_actions &&
	  NOT_cfg_verbosity_read__148_ULE_1_149___d1150 &&
	  (csr_trap_actions_nmi || !csr_trap_actions_interrupt) &&
	  exc_code__h12648 == 4'd15)
	$write("STORE_AMO_PAGE_FAULT");
    if (RST_N != `BSV_RESET_VALUE)
      if (EN_csr_trap_actions &&
	  NOT_cfg_verbosity_read__148_ULE_1_149___d1150 &&
	  csr_trap_actions_nmi_OR_NOT_csr_trap_actions_i_ETC___d1657)
	$write("unknown trap Exc_Code %d", exc_code__h12648);
    if (RST_N != `BSV_RESET_VALUE)
      if (EN_csr_trap_actions &&
	  NOT_cfg_verbosity_read__148_ULE_1_149___d1150)
	$write(" new priv %0d", new_priv__h10791);
    if (RST_N != `BSV_RESET_VALUE)
      if (EN_csr_trap_actions &&
	  NOT_cfg_verbosity_read__148_ULE_1_149___d1150)
	$display("");
    if (RST_N != `BSV_RESET_VALUE)
      if (NOT_cfg_verbosity_read__148_ULE_1_149___d1150)
	$display("%0d: CSR_RegFile: m_external_interrupt_req: %x",
		 rg_mcycle,
		 m_external_interrupt_req_set_not_clear);
    if (RST_N != `BSV_RESET_VALUE)
      if (NOT_cfg_verbosity_read__148_ULE_1_149___d1150)
	$display("%0d: CSR_RegFile: s_external_interrupt_req: %x",
		 rg_mcycle,
		 s_external_interrupt_req_set_not_clear);
    if (RST_N != `BSV_RESET_VALUE)
      if (NOT_cfg_verbosity_read__148_ULE_1_149___d1150)
	$display("%0d: CSR_RegFile: timer_interrupt_req: %x",
		 rg_mcycle,
		 timer_interrupt_req_set_not_clear);
    if (RST_N != `BSV_RESET_VALUE)
      if (NOT_cfg_verbosity_read__148_ULE_1_149___d1150)
	$display("%0d: CSR_RegFile: software_interrupt_req: %x",
		 rg_mcycle,
		 software_interrupt_req_set_not_clear);
  end
  // synopsys translate_on
endmodule  // mkCSR_RegFile

