//
// Generated by Bluespec Compiler, version 2018.10.beta1 (build e1df8052c, 2018-10-17)
//
//
//
//
// Ports:
// Name                         I/O  size props
// RDY_set_verbosity              O     1 const
// RDY_server_reset_request_put   O     1 reg
// RDY_server_reset_response_get  O     1
// valid                          O     1
// addr                           O    64 reg
// word64                         O    64
// st_amo_val                     O    64
// exc                            O     1
// exc_code                       O     4 reg
// RDY_server_flush_request_put   O     1 reg
// RDY_server_flush_response_get  O     1
// RDY_tlb_flush                  O     1 const
// mem_master_awvalid             O     1
// mem_master_awid                O     4 reg
// mem_master_awaddr              O    64 reg
// mem_master_awlen               O     8 reg
// mem_master_awsize              O     3 reg
// mem_master_awburst             O     2 reg
// mem_master_awlock              O     1 reg
// mem_master_awcache             O     4 reg
// mem_master_awprot              O     3 reg
// mem_master_awqos               O     4 reg
// mem_master_awregion            O     4 reg
// mem_master_wvalid              O     1
// mem_master_wid                 O     4 reg
// mem_master_wdata               O    64 reg
// mem_master_wstrb               O     8 reg
// mem_master_wlast               O     1 reg
// mem_master_bready              O     1
// mem_master_arvalid             O     1
// mem_master_arid                O     4 reg
// mem_master_araddr              O    64 reg
// mem_master_arlen               O     8 reg
// mem_master_arsize              O     3 reg
// mem_master_arburst             O     2 reg
// mem_master_arlock              O     1 reg
// mem_master_arcache             O     4 reg
// mem_master_arprot              O     3 reg
// mem_master_arqos               O     4 reg
// mem_master_arregion            O     4 reg
// mem_master_rready              O     1
// CLK                            I     1 clock
// RST_N                          I     1 reset
// set_verbosity_verbosity        I     4 reg
// req_op                         I     2
// req_f3                         I     3
// req_amo_funct7                 I     7 reg
// req_addr                       I    64
// req_st_value                   I    64
// req_priv                       I     2 unused
// req_sstatus_SUM                I     1 unused
// req_mstatus_MXR                I     1 unused
// req_satp                       I    64 unused
// mem_master_awready             I     1
// mem_master_wready              I     1
// mem_master_bvalid              I     1
// mem_master_bid                 I     4 reg
// mem_master_bresp               I     2 reg
// mem_master_arready             I     1
// mem_master_rvalid              I     1
// mem_master_rid                 I     4 reg
// mem_master_rdata               I    64 reg
// mem_master_rresp               I     2 reg
// mem_master_rlast               I     1 reg
// EN_set_verbosity               I     1
// EN_server_reset_request_put    I     1
// EN_server_reset_response_get   I     1
// EN_req                         I     1
// EN_server_flush_request_put    I     1
// EN_server_flush_response_get   I     1
// EN_tlb_flush                   I     1 unused
//
// Combinational paths from inputs to outputs:
//   (mem_master_awready, mem_master_wready) -> valid
//   (mem_master_awready, mem_master_wready) -> word64
//   (mem_master_awready, mem_master_wready) -> st_amo_val
//   (mem_master_awready, mem_master_wready) -> mem_master_bready
//   (mem_master_awready, mem_master_wready, EN_req) -> mem_master_rready
//
//

`ifdef BSV_ASSIGNMENT_DELAY
`else
  `define BSV_ASSIGNMENT_DELAY
`endif

`ifdef BSV_POSITIVE_RESET
  `define BSV_RESET_VALUE 1'b1
  `define BSV_RESET_EDGE posedge
`else
  `define BSV_RESET_VALUE 1'b0
  `define BSV_RESET_EDGE negedge
`endif

module mkMMU_Cache(CLK,
		   RST_N,

		   set_verbosity_verbosity,
		   EN_set_verbosity,
		   RDY_set_verbosity,

		   EN_server_reset_request_put,
		   RDY_server_reset_request_put,

		   EN_server_reset_response_get,
		   RDY_server_reset_response_get,

		   req_op,
		   req_f3,
		   req_amo_funct7,
		   req_addr,
		   req_st_value,
		   req_priv,
		   req_sstatus_SUM,
		   req_mstatus_MXR,
		   req_satp,
		   EN_req,

		   valid,

		   addr,

		   word64,

		   st_amo_val,

		   exc,

		   exc_code,

		   EN_server_flush_request_put,
		   RDY_server_flush_request_put,

		   EN_server_flush_response_get,
		   RDY_server_flush_response_get,

		   EN_tlb_flush,
		   RDY_tlb_flush,

		   mem_master_awvalid,

		   mem_master_awid,

		   mem_master_awaddr,

		   mem_master_awlen,

		   mem_master_awsize,

		   mem_master_awburst,

		   mem_master_awlock,

		   mem_master_awcache,

		   mem_master_awprot,

		   mem_master_awqos,

		   mem_master_awregion,

		   mem_master_awready,

		   mem_master_wvalid,

		   mem_master_wid,

		   mem_master_wdata,

		   mem_master_wstrb,

		   mem_master_wlast,

		   mem_master_wready,

		   mem_master_bvalid,
		   mem_master_bid,
		   mem_master_bresp,

		   mem_master_bready,

		   mem_master_arvalid,

		   mem_master_arid,

		   mem_master_araddr,

		   mem_master_arlen,

		   mem_master_arsize,

		   mem_master_arburst,

		   mem_master_arlock,

		   mem_master_arcache,

		   mem_master_arprot,

		   mem_master_arqos,

		   mem_master_arregion,

		   mem_master_arready,

		   mem_master_rvalid,
		   mem_master_rid,
		   mem_master_rdata,
		   mem_master_rresp,
		   mem_master_rlast,

		   mem_master_rready);
  parameter [0 : 0] dmem_not_imem = 1'b0;
  input  CLK;
  input  RST_N;

  // action method set_verbosity
  input  [3 : 0] set_verbosity_verbosity;
  input  EN_set_verbosity;
  output RDY_set_verbosity;

  // action method server_reset_request_put
  input  EN_server_reset_request_put;
  output RDY_server_reset_request_put;

  // action method server_reset_response_get
  input  EN_server_reset_response_get;
  output RDY_server_reset_response_get;

  // action method req
  input  [1 : 0] req_op;
  input  [2 : 0] req_f3;
  input  [6 : 0] req_amo_funct7;
  input  [63 : 0] req_addr;
  input  [63 : 0] req_st_value;
  input  [1 : 0] req_priv;
  input  req_sstatus_SUM;
  input  req_mstatus_MXR;
  input  [63 : 0] req_satp;
  input  EN_req;

  // value method valid
  output valid;

  // value method addr
  output [63 : 0] addr;

  // value method word64
  output [63 : 0] word64;

  // value method st_amo_val
  output [63 : 0] st_amo_val;

  // value method exc
  output exc;

  // value method exc_code
  output [3 : 0] exc_code;

  // action method server_flush_request_put
  input  EN_server_flush_request_put;
  output RDY_server_flush_request_put;

  // action method server_flush_response_get
  input  EN_server_flush_response_get;
  output RDY_server_flush_response_get;

  // action method tlb_flush
  input  EN_tlb_flush;
  output RDY_tlb_flush;

  // value method mem_master_m_awvalid
  output mem_master_awvalid;

  // value method mem_master_m_awid
  output [3 : 0] mem_master_awid;

  // value method mem_master_m_awaddr
  output [63 : 0] mem_master_awaddr;

  // value method mem_master_m_awlen
  output [7 : 0] mem_master_awlen;

  // value method mem_master_m_awsize
  output [2 : 0] mem_master_awsize;

  // value method mem_master_m_awburst
  output [1 : 0] mem_master_awburst;

  // value method mem_master_m_awlock
  output mem_master_awlock;

  // value method mem_master_m_awcache
  output [3 : 0] mem_master_awcache;

  // value method mem_master_m_awprot
  output [2 : 0] mem_master_awprot;

  // value method mem_master_m_awqos
  output [3 : 0] mem_master_awqos;

  // value method mem_master_m_awregion
  output [3 : 0] mem_master_awregion;

  // value method mem_master_m_awuser

  // action method mem_master_m_awready
  input  mem_master_awready;

  // value method mem_master_m_wvalid
  output mem_master_wvalid;

  // value method mem_master_m_wid
  output [3 : 0] mem_master_wid;

  // value method mem_master_m_wdata
  output [63 : 0] mem_master_wdata;

  // value method mem_master_m_wstrb
  output [7 : 0] mem_master_wstrb;

  // value method mem_master_m_wlast
  output mem_master_wlast;

  // value method mem_master_m_wuser

  // action method mem_master_m_wready
  input  mem_master_wready;

  // action method mem_master_m_bvalid
  input  mem_master_bvalid;
  input  [3 : 0] mem_master_bid;
  input  [1 : 0] mem_master_bresp;

  // value method mem_master_m_bready
  output mem_master_bready;

  // value method mem_master_m_arvalid
  output mem_master_arvalid;

  // value method mem_master_m_arid
  output [3 : 0] mem_master_arid;

  // value method mem_master_m_araddr
  output [63 : 0] mem_master_araddr;

  // value method mem_master_m_arlen
  output [7 : 0] mem_master_arlen;

  // value method mem_master_m_arsize
  output [2 : 0] mem_master_arsize;

  // value method mem_master_m_arburst
  output [1 : 0] mem_master_arburst;

  // value method mem_master_m_arlock
  output mem_master_arlock;

  // value method mem_master_m_arcache
  output [3 : 0] mem_master_arcache;

  // value method mem_master_m_arprot
  output [2 : 0] mem_master_arprot;

  // value method mem_master_m_arqos
  output [3 : 0] mem_master_arqos;

  // value method mem_master_m_arregion
  output [3 : 0] mem_master_arregion;

  // value method mem_master_m_aruser

  // action method mem_master_m_arready
  input  mem_master_arready;

  // action method mem_master_m_rvalid
  input  mem_master_rvalid;
  input  [3 : 0] mem_master_rid;
  input  [63 : 0] mem_master_rdata;
  input  [1 : 0] mem_master_rresp;
  input  mem_master_rlast;

  // value method mem_master_m_rready
  output mem_master_rready;

  // signals for module outputs
  reg [63 : 0] word64;
  wire [63 : 0] addr,
		mem_master_araddr,
		mem_master_awaddr,
		mem_master_wdata,
		st_amo_val;
  wire [7 : 0] mem_master_arlen, mem_master_awlen, mem_master_wstrb;
  wire [3 : 0] exc_code,
	       mem_master_arcache,
	       mem_master_arid,
	       mem_master_arqos,
	       mem_master_arregion,
	       mem_master_awcache,
	       mem_master_awid,
	       mem_master_awqos,
	       mem_master_awregion,
	       mem_master_wid;
  wire [2 : 0] mem_master_arprot,
	       mem_master_arsize,
	       mem_master_awprot,
	       mem_master_awsize;
  wire [1 : 0] mem_master_arburst, mem_master_awburst;
  wire RDY_server_flush_request_put,
       RDY_server_flush_response_get,
       RDY_server_reset_request_put,
       RDY_server_reset_response_get,
       RDY_set_verbosity,
       RDY_tlb_flush,
       exc,
       mem_master_arlock,
       mem_master_arvalid,
       mem_master_awlock,
       mem_master_awvalid,
       mem_master_bready,
       mem_master_rready,
       mem_master_wlast,
       mem_master_wvalid,
       valid;

  // inlined wires
  reg [3 : 0] ctr_wr_rsps_pending_crg$port0__write_1;
  wire [10 : 0] crg_sb_to_load_delay$port0__write_1,
		crg_sb_to_load_delay$port2__read;
  wire [3 : 0] ctr_wr_rsps_pending_crg$port1__write_1,
	       ctr_wr_rsps_pending_crg$port2__read,
	       ctr_wr_rsps_pending_crg$port3__read;
  wire crg_sb_to_load_delay$EN_port1__write,
       ctr_wr_rsps_pending_crg$EN_port0__write,
       ctr_wr_rsps_pending_crg$EN_port2__write,
       dw_valid$whas,
       master_xactor_crg_rd_addr_full$EN_port0__write,
       master_xactor_crg_rd_addr_full$EN_port1__write,
       master_xactor_crg_rd_addr_full$EN_port2__write,
       master_xactor_crg_rd_addr_full$port1__read,
       master_xactor_crg_rd_addr_full$port2__read,
       master_xactor_crg_rd_addr_full$port3__read,
       master_xactor_crg_rd_data_full$EN_port0__write,
       master_xactor_crg_rd_data_full$EN_port1__write,
       master_xactor_crg_rd_data_full$EN_port2__write,
       master_xactor_crg_rd_data_full$port1__read,
       master_xactor_crg_rd_data_full$port2__read,
       master_xactor_crg_rd_data_full$port3__read,
       master_xactor_crg_wr_addr_full$EN_port0__write,
       master_xactor_crg_wr_addr_full$EN_port1__write,
       master_xactor_crg_wr_addr_full$EN_port2__write,
       master_xactor_crg_wr_addr_full$port1__read,
       master_xactor_crg_wr_addr_full$port2__read,
       master_xactor_crg_wr_addr_full$port3__read,
       master_xactor_crg_wr_data_full$EN_port0__write,
       master_xactor_crg_wr_data_full$EN_port1__write,
       master_xactor_crg_wr_data_full$EN_port2__write,
       master_xactor_crg_wr_data_full$port1__read,
       master_xactor_crg_wr_data_full$port2__read,
       master_xactor_crg_wr_data_full$port3__read,
       master_xactor_crg_wr_resp_full$EN_port0__write,
       master_xactor_crg_wr_resp_full$EN_port2__write,
       master_xactor_crg_wr_resp_full$port1__read,
       master_xactor_crg_wr_resp_full$port2__read,
       master_xactor_crg_wr_resp_full$port3__read;

  // register cfg_verbosity
  reg [3 : 0] cfg_verbosity;
  wire [3 : 0] cfg_verbosity$D_IN;
  wire cfg_verbosity$EN;

  // register crg_sb_to_load_delay
  reg [10 : 0] crg_sb_to_load_delay;
  wire [10 : 0] crg_sb_to_load_delay$D_IN;
  wire crg_sb_to_load_delay$EN;

  // register ctr_wr_rsps_pending_crg
  reg [3 : 0] ctr_wr_rsps_pending_crg;
  wire [3 : 0] ctr_wr_rsps_pending_crg$D_IN;
  wire ctr_wr_rsps_pending_crg$EN;

  // register master_xactor_crg_rd_addr_full
  reg master_xactor_crg_rd_addr_full;
  wire master_xactor_crg_rd_addr_full$D_IN, master_xactor_crg_rd_addr_full$EN;

  // register master_xactor_crg_rd_data_full
  reg master_xactor_crg_rd_data_full;
  wire master_xactor_crg_rd_data_full$D_IN, master_xactor_crg_rd_data_full$EN;

  // register master_xactor_crg_wr_addr_full
  reg master_xactor_crg_wr_addr_full;
  wire master_xactor_crg_wr_addr_full$D_IN, master_xactor_crg_wr_addr_full$EN;

  // register master_xactor_crg_wr_data_full
  reg master_xactor_crg_wr_data_full;
  wire master_xactor_crg_wr_data_full$D_IN, master_xactor_crg_wr_data_full$EN;

  // register master_xactor_crg_wr_resp_full
  reg master_xactor_crg_wr_resp_full;
  wire master_xactor_crg_wr_resp_full$D_IN, master_xactor_crg_wr_resp_full$EN;

  // register master_xactor_rg_rd_addr
  reg [96 : 0] master_xactor_rg_rd_addr;
  wire [96 : 0] master_xactor_rg_rd_addr$D_IN;
  wire master_xactor_rg_rd_addr$EN;

  // register master_xactor_rg_rd_data
  reg [70 : 0] master_xactor_rg_rd_data;
  wire [70 : 0] master_xactor_rg_rd_data$D_IN;
  wire master_xactor_rg_rd_data$EN;

  // register master_xactor_rg_wr_addr
  reg [96 : 0] master_xactor_rg_wr_addr;
  reg [96 : 0] master_xactor_rg_wr_addr$D_IN;
  wire master_xactor_rg_wr_addr$EN;

  // register master_xactor_rg_wr_data
  reg [76 : 0] master_xactor_rg_wr_data;
  reg [76 : 0] master_xactor_rg_wr_data$D_IN;
  wire master_xactor_rg_wr_data$EN;

  // register master_xactor_rg_wr_resp
  reg [5 : 0] master_xactor_rg_wr_resp;
  wire [5 : 0] master_xactor_rg_wr_resp$D_IN;
  wire master_xactor_rg_wr_resp$EN;

  // register rg_addr
  reg [63 : 0] rg_addr;
  wire [63 : 0] rg_addr$D_IN;
  wire rg_addr$EN;

  // register rg_amo_funct7
  reg [6 : 0] rg_amo_funct7;
  wire [6 : 0] rg_amo_funct7$D_IN;
  wire rg_amo_funct7$EN;

  // register rg_cset_in_cache
  reg [5 : 0] rg_cset_in_cache;
  wire [5 : 0] rg_cset_in_cache$D_IN;
  wire rg_cset_in_cache$EN;

  // register rg_error_during_refill
  reg rg_error_during_refill;
  wire rg_error_during_refill$D_IN, rg_error_during_refill$EN;

  // register rg_exc_code
  reg [3 : 0] rg_exc_code;
  reg [3 : 0] rg_exc_code$D_IN;
  wire rg_exc_code$EN;

  // register rg_f3
  reg [2 : 0] rg_f3;
  wire [2 : 0] rg_f3$D_IN;
  wire rg_f3$EN;

  // register rg_ld_val
  reg [63 : 0] rg_ld_val;
  reg [63 : 0] rg_ld_val$D_IN;
  wire rg_ld_val$EN;

  // register rg_lower_word32
  reg [31 : 0] rg_lower_word32;
  wire [31 : 0] rg_lower_word32$D_IN;
  wire rg_lower_word32$EN;

  // register rg_lower_word32_full
  reg rg_lower_word32_full;
  wire rg_lower_word32_full$D_IN, rg_lower_word32_full$EN;

  // register rg_lrsc_pa
  reg [63 : 0] rg_lrsc_pa;
  wire [63 : 0] rg_lrsc_pa$D_IN;
  wire rg_lrsc_pa$EN;

  // register rg_lrsc_valid
  reg rg_lrsc_valid;
  wire rg_lrsc_valid$D_IN, rg_lrsc_valid$EN;

  // register rg_op
  reg [1 : 0] rg_op;
  wire [1 : 0] rg_op$D_IN;
  wire rg_op$EN;

  // register rg_pa
  reg [63 : 0] rg_pa;
  wire [63 : 0] rg_pa$D_IN;
  wire rg_pa$EN;

  // register rg_pte_pa
  reg [63 : 0] rg_pte_pa;
  wire [63 : 0] rg_pte_pa$D_IN;
  wire rg_pte_pa$EN;

  // register rg_st_amo_val
  reg [63 : 0] rg_st_amo_val;
  wire [63 : 0] rg_st_amo_val$D_IN;
  wire rg_st_amo_val$EN;

  // register rg_state
  reg [4 : 0] rg_state;
  reg [4 : 0] rg_state$D_IN;
  wire rg_state$EN;

  // register rg_word64_set_in_cache
  reg [8 : 0] rg_word64_set_in_cache;
  wire [8 : 0] rg_word64_set_in_cache$D_IN;
  wire rg_word64_set_in_cache$EN;

  // ports of submodule f_reset_reqs
  wire f_reset_reqs$CLR,
       f_reset_reqs$DEQ,
       f_reset_reqs$D_IN,
       f_reset_reqs$D_OUT,
       f_reset_reqs$EMPTY_N,
       f_reset_reqs$ENQ,
       f_reset_reqs$FULL_N;

  // ports of submodule f_reset_rsps
  wire f_reset_rsps$CLR,
       f_reset_rsps$DEQ,
       f_reset_rsps$D_IN,
       f_reset_rsps$D_OUT,
       f_reset_rsps$EMPTY_N,
       f_reset_rsps$ENQ,
       f_reset_rsps$FULL_N;

  // ports of submodule ram_state_and_ctag_cset
  wire [52 : 0] ram_state_and_ctag_cset$DIA,
		ram_state_and_ctag_cset$DIB,
		ram_state_and_ctag_cset$DOB;
  wire [5 : 0] ram_state_and_ctag_cset$ADDRA, ram_state_and_ctag_cset$ADDRB;
  wire ram_state_and_ctag_cset$ENA,
       ram_state_and_ctag_cset$ENB,
       ram_state_and_ctag_cset$WEA,
       ram_state_and_ctag_cset$WEB;

  // ports of submodule ram_word64_set
  reg [63 : 0] ram_word64_set$DIB;
  reg [8 : 0] ram_word64_set$ADDRB;
  wire [63 : 0] ram_word64_set$DIA, ram_word64_set$DOB;
  wire [8 : 0] ram_word64_set$ADDRA;
  wire ram_word64_set$ENA,
       ram_word64_set$ENB,
       ram_word64_set$WEA,
       ram_word64_set$WEB;

  // ports of submodule soc_map
  wire [63 : 0] soc_map$m_is_IO_addr_addr,
		soc_map$m_is_mem_addr_addr,
		soc_map$m_is_near_mem_IO_addr_addr;
  wire soc_map$m_is_mem_addr;

  // rule scheduling signals
  wire CAN_FIRE_RL_rl_ST_AMO_response,
       CAN_FIRE_RL_rl_cache_refill_rsps_loop,
       CAN_FIRE_RL_rl_discard_write_rsp,
       CAN_FIRE_RL_rl_drive_exception_rsp,
       CAN_FIRE_RL_rl_io_AMO_SC_req,
       CAN_FIRE_RL_rl_io_AMO_op_req,
       CAN_FIRE_RL_rl_io_AMO_read_rsp,
       CAN_FIRE_RL_rl_io_read_req,
       CAN_FIRE_RL_rl_io_read_rsp,
       CAN_FIRE_RL_rl_io_write_req,
       CAN_FIRE_RL_rl_maintain_io_read_rsp,
       CAN_FIRE_RL_rl_probe_and_immed_rsp,
       CAN_FIRE_RL_rl_rereq,
       CAN_FIRE_RL_rl_reset,
       CAN_FIRE_RL_rl_shift_sb_to_load_delay,
       CAN_FIRE_RL_rl_start_cache_refill,
       CAN_FIRE_RL_rl_start_reset,
       CAN_FIRE_mem_master_m_arready,
       CAN_FIRE_mem_master_m_awready,
       CAN_FIRE_mem_master_m_bvalid,
       CAN_FIRE_mem_master_m_rvalid,
       CAN_FIRE_mem_master_m_wready,
       CAN_FIRE_req,
       CAN_FIRE_server_flush_request_put,
       CAN_FIRE_server_flush_response_get,
       CAN_FIRE_server_reset_request_put,
       CAN_FIRE_server_reset_response_get,
       CAN_FIRE_set_verbosity,
       CAN_FIRE_tlb_flush,
       WILL_FIRE_RL_rl_ST_AMO_response,
       WILL_FIRE_RL_rl_cache_refill_rsps_loop,
       WILL_FIRE_RL_rl_discard_write_rsp,
       WILL_FIRE_RL_rl_drive_exception_rsp,
       WILL_FIRE_RL_rl_io_AMO_SC_req,
       WILL_FIRE_RL_rl_io_AMO_op_req,
       WILL_FIRE_RL_rl_io_AMO_read_rsp,
       WILL_FIRE_RL_rl_io_read_req,
       WILL_FIRE_RL_rl_io_read_rsp,
       WILL_FIRE_RL_rl_io_write_req,
       WILL_FIRE_RL_rl_maintain_io_read_rsp,
       WILL_FIRE_RL_rl_probe_and_immed_rsp,
       WILL_FIRE_RL_rl_rereq,
       WILL_FIRE_RL_rl_reset,
       WILL_FIRE_RL_rl_shift_sb_to_load_delay,
       WILL_FIRE_RL_rl_start_cache_refill,
       WILL_FIRE_RL_rl_start_reset,
       WILL_FIRE_mem_master_m_arready,
       WILL_FIRE_mem_master_m_awready,
       WILL_FIRE_mem_master_m_bvalid,
       WILL_FIRE_mem_master_m_rvalid,
       WILL_FIRE_mem_master_m_wready,
       WILL_FIRE_req,
       WILL_FIRE_server_flush_request_put,
       WILL_FIRE_server_flush_response_get,
       WILL_FIRE_server_reset_request_put,
       WILL_FIRE_server_reset_response_get,
       WILL_FIRE_set_verbosity,
       WILL_FIRE_tlb_flush;

  // inputs to muxes for submodule ports
  wire [96 : 0] MUX_master_xactor_rg_rd_addr$write_1__VAL_1,
		MUX_master_xactor_rg_rd_addr$write_1__VAL_2,
		MUX_master_xactor_rg_wr_addr$write_1__VAL_1,
		MUX_master_xactor_rg_wr_addr$write_1__VAL_2;
  wire [76 : 0] MUX_master_xactor_rg_wr_data$write_1__VAL_1,
		MUX_master_xactor_rg_wr_data$write_1__VAL_2,
		MUX_master_xactor_rg_wr_data$write_1__VAL_3;
  wire [63 : 0] MUX_dw_output_ld_val$wset_1__VAL_3,
		MUX_ram_word64_set$a_put_3__VAL_2,
		MUX_rg_ld_val$write_1__VAL_2;
  wire [52 : 0] MUX_ram_state_and_ctag_cset$a_put_3__VAL_1;
  wire [8 : 0] MUX_ram_word64_set$b_put_2__VAL_2,
	       MUX_ram_word64_set$b_put_2__VAL_4;
  wire [5 : 0] MUX_rg_cset_in_cache$write_1__VAL_1;
  wire [4 : 0] MUX_rg_state$write_1__VAL_1,
	       MUX_rg_state$write_1__VAL_4,
	       MUX_rg_state$write_1__VAL_8,
	       MUX_rg_state$write_1__VAL_9;
  wire [3 : 0] MUX_ctr_wr_rsps_pending_crg$port0__write_1__VAL_1,
	       MUX_rg_exc_code$write_1__VAL_1;
  wire MUX_ctr_wr_rsps_pending_crg$port0__write_1__SEL_1,
       MUX_ctr_wr_rsps_pending_crg$port0__write_1__SEL_2,
       MUX_dw_output_ld_val$wset_1__SEL_1,
       MUX_dw_output_ld_val$wset_1__SEL_3,
       MUX_dw_output_ld_val$wset_1__SEL_4,
       MUX_master_xactor_rg_rd_addr$write_1__SEL_1,
       MUX_ram_state_and_ctag_cset$b_put_1__SEL_1,
       MUX_ram_word64_set$a_put_1__SEL_1,
       MUX_ram_word64_set$b_put_1__SEL_2,
       MUX_rg_error_during_refill$write_1__SEL_1,
       MUX_rg_exc_code$write_1__SEL_1,
       MUX_rg_exc_code$write_1__SEL_2,
       MUX_rg_exc_code$write_1__SEL_3,
       MUX_rg_ld_val$write_1__SEL_2,
       MUX_rg_lrsc_valid$write_1__SEL_2,
       MUX_rg_state$write_1__SEL_13,
       MUX_rg_state$write_1__SEL_2,
       MUX_rg_state$write_1__SEL_3,
       MUX_rg_state$write_1__SEL_8,
       MUX_rg_state$write_1__SEL_9;

  // declarations used by system tasks
  // synopsys translate_off
  reg [31 : 0] v__h3732;
  reg [31 : 0] v__h3833;
  reg [31 : 0] v__h25363;
  reg [31 : 0] v__h26261;
  reg [31 : 0] v__h3369;
  reg [31 : 0] v__h4286;
  reg [31 : 0] v__h12754;
  reg [31 : 0] v__h17070;
  reg [31 : 0] v__h16398;
  reg [31 : 0] v__h20536;
  reg [31 : 0] v__h21830;
  reg [31 : 0] v__h22071;
  reg [31 : 0] v__h24049;
  reg [31 : 0] v__h25151;
  reg [31 : 0] v__h25258;
  reg [31 : 0] v__h25443;
  reg [31 : 0] v__h25965;
  reg [31 : 0] v__h26379;
  reg [31 : 0] v__h26697;
  reg [31 : 0] v__h26872;
  reg [31 : 0] v__h29485;
  reg [31 : 0] v__h29737;
  reg [31 : 0] v__h26968;
  reg [31 : 0] v__h20981;
  reg [31 : 0] v__h23675;
  reg [31 : 0] v__h30707;
  reg [31 : 0] v__h30357;
  reg [31 : 0] v__h30318;
  reg [31 : 0] v__h26962;
  reg [31 : 0] v__h3363;
  reg [31 : 0] v__h3726;
  reg [31 : 0] v__h3827;
  reg [31 : 0] v__h4280;
  reg [31 : 0] v__h12748;
  reg [31 : 0] v__h16392;
  reg [31 : 0] v__h17064;
  reg [31 : 0] v__h20530;
  reg [31 : 0] v__h20975;
  reg [31 : 0] v__h21824;
  reg [31 : 0] v__h22065;
  reg [31 : 0] v__h23669;
  reg [31 : 0] v__h24043;
  reg [31 : 0] v__h25145;
  reg [31 : 0] v__h25252;
  reg [31 : 0] v__h25357;
  reg [31 : 0] v__h25437;
  reg [31 : 0] v__h25959;
  reg [31 : 0] v__h26255;
  reg [31 : 0] v__h26373;
  reg [31 : 0] v__h26691;
  reg [31 : 0] v__h26866;
  reg [31 : 0] v__h29479;
  reg [31 : 0] v__h29731;
  reg [31 : 0] v__h30312;
  reg [31 : 0] v__h30351;
  reg [31 : 0] v__h30701;
  // synopsys translate_on

  // remaining internal signals
  reg [63 : 0] CASE_rg_addr_BITS_2_TO_0_0x0_ram_word64_setDO_ETC__q32,
	       CASE_rg_addr_BITS_2_TO_0_0x0_ram_word64_setDO_ETC__q51,
	       CASE_rg_addr_BITS_2_TO_0_0x0_result2575_0x4_re_ETC__q29,
	       CASE_rg_addr_BITS_2_TO_0_0x0_result4929_0x4_re_ETC__q33,
	       CASE_rg_addr_BITS_2_TO_0_0x0_result4994_0x4_re_ETC__q34,
	       CASE_rg_addr_BITS_2_TO_0_0x0_result9085_0x4_re_ETC__q49,
	       IF_rg_addr_0_BITS_2_TO_0_6_EQ_0x0_40_THEN_0_CO_ETC___d221,
	       IF_rg_addr_0_BITS_2_TO_0_6_EQ_0x0_40_THEN_0_CO_ETC___d243,
	       IF_rg_addr_0_BITS_2_TO_0_6_EQ_0x0_40_THEN_0_CO_ETC___d255,
	       IF_rg_addr_0_BITS_2_TO_0_6_EQ_0x0_40_THEN_0_CO_ETC___d646,
	       IF_rg_addr_0_BITS_2_TO_0_6_EQ_0x0_40_THEN_0_CO_ETC___d666,
	       IF_rg_addr_0_BITS_2_TO_0_6_EQ_0x0_40_THEN_0_CO_ETC___d769,
	       IF_rg_addr_0_BITS_2_TO_0_6_EQ_0x0_40_THEN_0_CO_ETC___d789,
	       IF_rg_addr_0_BITS_2_TO_0_6_EQ_0x0_40_THEN_0_CO_ETC___d799,
	       IF_rg_addr_0_BITS_2_TO_0_6_EQ_0x0_40_THEN_SEXT_ETC___d204,
	       IF_rg_addr_0_BITS_2_TO_0_6_EQ_0x0_40_THEN_SEXT_ETC___d234,
	       IF_rg_addr_0_BITS_2_TO_0_6_EQ_0x0_40_THEN_SEXT_ETC___d630,
	       IF_rg_addr_0_BITS_2_TO_0_6_EQ_0x0_40_THEN_SEXT_ETC___d658,
	       IF_rg_addr_0_BITS_2_TO_0_6_EQ_0x0_40_THEN_SEXT_ETC___d753,
	       IF_rg_addr_0_BITS_2_TO_0_6_EQ_0x0_40_THEN_SEXT_ETC___d781,
	       IF_rg_addr_0_BITS_2_TO_0_6_EQ_0x0_40_THEN_ram__ETC___d342,
	       IF_rg_addr_0_BITS_2_TO_0_6_EQ_0x0_40_THEN_ram__ETC___d351,
	       IF_rg_addr_0_BITS_2_TO_0_6_EQ_0x0_40_THEN_ram__ETC___d416,
	       IF_rg_addr_0_BITS_2_TO_0_6_EQ_0x0_40_THEN_ram__ETC___d425,
	       IF_rg_f3_38_EQ_0b0_39_THEN_IF_rg_addr_0_BITS_2_ETC___d360,
	       IF_rg_f3_38_EQ_0b0_39_THEN_IF_rg_addr_0_BITS_2_ETC___d434,
	       IF_rg_f3_38_EQ_0b10_44_THEN_SEXT_IF_rg_f3_38_E_ETC___d302,
	       _theResult_____2__h17629,
	       _theResult_____2__h27290,
	       ld_val__h24158,
	       mem_req_wr_data_wdata__h16835,
	       mem_req_wr_data_wdata__h20332,
	       mem_req_wr_data_wdata__h25761,
	       mem_req_wr_data_wdata__h27265,
	       new_ld_val__h26998,
	       new_value__h15489,
	       new_value__h5462,
	       w1__h17621,
	       w1__h27278,
	       w1__h27282;
  reg [7 : 0] mem_req_wr_data_wstrb__h20333, mem_req_wr_data_wstrb__h27266;
  reg [2 : 0] value__h26583, value__h29609;
  wire [63 : 0] IF_rg_addr_0_BITS_2_TO_0_6_EQ_0x0_40_THEN_1_EL_ETC___d271,
		IF_rg_addr_0_BITS_2_TO_0_6_EQ_0x0_40_THEN_IF_r_ETC___d800,
		IF_rg_addr_0_BITS_2_TO_0_6_EQ_0x0_40_THEN_ram__ETC___d257,
		IF_rg_f3_38_EQ_0b10_44_THEN_SEXT_rg_st_amo_val_ETC___d366,
		IF_rg_op_4_EQ_1_2_OR_rg_op_4_EQ_2_6_AND_rg_amo_ETC___d466,
		_theResult___snd_fst__h16843,
		_theResult___snd_fst__h20340,
		_theResult___snd_fst__h25769,
		_theResult___snd_fst__h27273,
		cline_fabric_addr__h21034,
		new_st_val__h17351,
		new_st_val__h17633,
		new_st_val__h17724,
		new_st_val__h18704,
		new_st_val__h18708,
		new_st_val__h18712,
		new_st_val__h18716,
		new_st_val__h18721,
		new_st_val__h18727,
		new_st_val__h18732,
		new_st_val__h27294,
		new_st_val__h27385,
		new_st_val__h29245,
		new_st_val__h29249,
		new_st_val__h29253,
		new_st_val__h29257,
		new_st_val__h29262,
		new_st_val__h29268,
		new_st_val__h29273,
		result__h11871,
		result__h11899,
		result__h11927,
		result__h11955,
		result__h11983,
		result__h12011,
		result__h12039,
		result__h12084,
		result__h12112,
		result__h12140,
		result__h12168,
		result__h12196,
		result__h12224,
		result__h12252,
		result__h12280,
		result__h12325,
		result__h12353,
		result__h12381,
		result__h12409,
		result__h12450,
		result__h12478,
		result__h12506,
		result__h12534,
		result__h12575,
		result__h12603,
		result__h12642,
		result__h12670,
		result__h24218,
		result__h24248,
		result__h24275,
		result__h24302,
		result__h24329,
		result__h24356,
		result__h24383,
		result__h24410,
		result__h24454,
		result__h24481,
		result__h24508,
		result__h24535,
		result__h24562,
		result__h24589,
		result__h24616,
		result__h24643,
		result__h24687,
		result__h24714,
		result__h24741,
		result__h24768,
		result__h24808,
		result__h24835,
		result__h24862,
		result__h24889,
		result__h24929,
		result__h24956,
		result__h24994,
		result__h25021,
		result__h27473,
		result__h28381,
		result__h28409,
		result__h28437,
		result__h28465,
		result__h28493,
		result__h28521,
		result__h28549,
		result__h28594,
		result__h28622,
		result__h28650,
		result__h28678,
		result__h28706,
		result__h28734,
		result__h28762,
		result__h28790,
		result__h28835,
		result__h28863,
		result__h28891,
		result__h28919,
		result__h28960,
		result__h28988,
		result__h29016,
		result__h29044,
		result__h29085,
		result__h29113,
		result__h29152,
		result__h29180,
		result__h5515,
		st_val__h27010,
		w1___1__h17692,
		w1___1__h27353,
		w2___1__h27354,
		w2__h27284,
		word64__h5281,
		x__h13141,
		y__h5551;
  wire [31 : 0] ld_val4158_BITS_31_TO_0__q37,
		ld_val4158_BITS_63_TO_32__q44,
		master_xactor_rg_rd_data_BITS_34_TO_3__q3,
		master_xactor_rg_rd_data_BITS_66_TO_35__q10,
		new_value462_BITS_31_TO_0__q30,
		rg_st_amo_val_BITS_31_TO_0__q31,
		w17278_BITS_31_TO_0__q50,
		word64281_BITS_31_TO_0__q17,
		word64281_BITS_63_TO_32__q24;
  wire [15 : 0] ld_val4158_BITS_15_TO_0__q36,
		ld_val4158_BITS_31_TO_16__q40,
		ld_val4158_BITS_47_TO_32__q43,
		ld_val4158_BITS_63_TO_48__q47,
		master_xactor_rg_rd_data_BITS_18_TO_3__q2,
		master_xactor_rg_rd_data_BITS_34_TO_19__q6,
		master_xactor_rg_rd_data_BITS_50_TO_35__q9,
		master_xactor_rg_rd_data_BITS_66_TO_51__q13,
		word64281_BITS_15_TO_0__q16,
		word64281_BITS_31_TO_16__q20,
		word64281_BITS_47_TO_32__q23,
		word64281_BITS_63_TO_48__q27;
  wire [7 : 0] ld_val4158_BITS_15_TO_8__q38,
	       ld_val4158_BITS_23_TO_16__q39,
	       ld_val4158_BITS_31_TO_24__q41,
	       ld_val4158_BITS_39_TO_32__q42,
	       ld_val4158_BITS_47_TO_40__q45,
	       ld_val4158_BITS_55_TO_48__q46,
	       ld_val4158_BITS_63_TO_56__q48,
	       ld_val4158_BITS_7_TO_0__q35,
	       master_xactor_rg_rd_data_BITS_10_TO_3__q1,
	       master_xactor_rg_rd_data_BITS_18_TO_11__q4,
	       master_xactor_rg_rd_data_BITS_26_TO_19__q5,
	       master_xactor_rg_rd_data_BITS_34_TO_27__q7,
	       master_xactor_rg_rd_data_BITS_42_TO_35__q8,
	       master_xactor_rg_rd_data_BITS_50_TO_43__q11,
	       master_xactor_rg_rd_data_BITS_58_TO_51__q12,
	       master_xactor_rg_rd_data_BITS_66_TO_59__q14,
	       strobe64__h20266,
	       strobe64__h20268,
	       strobe64__h20270,
	       strobe64__h27199,
	       strobe64__h27201,
	       strobe64__h27203,
	       word64281_BITS_15_TO_8__q18,
	       word64281_BITS_23_TO_16__q19,
	       word64281_BITS_31_TO_24__q21,
	       word64281_BITS_39_TO_32__q22,
	       word64281_BITS_47_TO_40__q25,
	       word64281_BITS_55_TO_48__q26,
	       word64281_BITS_63_TO_56__q28,
	       word64281_BITS_7_TO_0__q15;
  wire [5 : 0] shift_bits__h20133, shift_bits__h27066;
  wire [4 : 0] IF_rg_op_4_EQ_0_5_OR_rg_op_4_EQ_2_6_AND_rg_amo_ETC___d110,
	       IF_rg_op_4_EQ_1_2_OR_rg_op_4_EQ_2_6_AND_rg_amo_ETC___d109;
  wire [3 : 0] access_exc_code__h2925, b__h20935;
  wire IF_rg_op_4_EQ_1_2_OR_rg_op_4_EQ_2_6_AND_rg_amo_ETC___d78,
       NOT_cfg_verbosity_read__0_ULE_1_1___d12,
       NOT_cfg_verbosity_read__0_ULE_2_54___d555,
       NOT_dmem_not_imem_13_OR_soc_map_m_is_mem_addr__ETC___d298,
       NOT_dmem_not_imem_13_OR_soc_map_m_is_mem_addr__ETC___d309,
       NOT_dmem_not_imem_13_OR_soc_map_m_is_mem_addr__ETC___d443,
       NOT_dmem_not_imem_13_OR_soc_map_m_is_mem_addr__ETC___d479,
       NOT_dmem_not_imem_13_OR_soc_map_m_is_mem_addr__ETC___d491,
       NOT_dmem_not_imem_13_OR_soc_map_m_is_mem_addr__ETC___d519,
       NOT_dmem_not_imem_13_OR_soc_map_m_is_mem_addr__ETC___d522,
       NOT_dmem_not_imem_13_OR_soc_map_m_is_mem_addr__ETC___d526,
       NOT_dmem_not_imem_13_OR_soc_map_m_is_mem_addr__ETC___d532,
       NOT_dmem_not_imem_13_OR_soc_map_m_is_mem_addr__ETC___d534,
       NOT_ram_state_and_ctag_cset_b_read__9_BIT_52_0_ETC___d119,
       NOT_req_f3_BITS_1_TO_0_90_EQ_0b0_91_92_AND_NOT_ETC___d911,
       NOT_rg_op_4_EQ_0_5_2_AND_NOT_rg_op_4_EQ_2_6_3__ETC___d105,
       NOT_rg_op_4_EQ_0_5_2_AND_NOT_rg_op_4_EQ_2_6_3__ETC___d446,
       NOT_rg_op_4_EQ_0_5_2_AND_NOT_rg_op_4_EQ_2_6_3__ETC___d494,
       NOT_rg_op_4_EQ_0_5_2_AND_NOT_rg_op_4_EQ_2_6_3__ETC___d502,
       NOT_rg_op_4_EQ_0_5_2_AND_NOT_rg_op_4_EQ_2_6_3__ETC___d507,
       NOT_rg_op_4_EQ_1_2_25_AND_NOT_rg_op_4_EQ_2_6_3_ETC___d128,
       NOT_rg_op_4_EQ_1_2_25_AND_NOT_rg_op_4_EQ_2_6_3_ETC___d306,
       NOT_rg_op_4_EQ_1_2_25_AND_NOT_rg_op_4_EQ_2_6_3_ETC___d440,
       NOT_rg_op_4_EQ_1_2_25_AND_NOT_rg_op_4_EQ_2_6_3_ETC___d517,
       NOT_rg_op_4_EQ_1_2_25_AND_NOT_rg_op_4_EQ_2_6_3_ETC___d520,
       NOT_rg_op_4_EQ_1_2_25_AND_NOT_rg_op_4_EQ_2_6_3_ETC___d524,
       NOT_rg_op_4_EQ_1_2_25_AND_NOT_rg_op_4_EQ_2_6_3_ETC___d530,
       NOT_rg_op_4_EQ_2_6_3_OR_NOT_rg_amo_funct7_7_BI_ETC___d304,
       NOT_rg_op_4_EQ_2_6_3_OR_NOT_rg_amo_funct7_7_BI_ETC___d438,
       NOT_rg_op_4_EQ_2_6_3_OR_NOT_rg_amo_funct7_7_BI_ETC___d492,
       NOT_rg_op_4_EQ_2_6_3_OR_NOT_rg_amo_funct7_7_BI_ETC___d496,
       NOT_rg_op_4_EQ_2_6_3_OR_NOT_rg_amo_funct7_7_BI_ETC___d500,
       NOT_rg_op_4_EQ_2_6_3_OR_NOT_rg_amo_funct7_7_BI_ETC___d505,
       dmem_not_imem_AND_NOT_soc_map_m_is_mem_addr_rg_ETC___d80,
       lrsc_result__h13131,
       master_xactor_crg_rd_data_full_port1__read__51_ETC___d723,
       ram_state_and_ctag_cset_b_read__9_BITS_51_TO_0_ETC___d74,
       ram_state_and_ctag_cset_b_read__9_BIT_52_0_AND_ETC___d120,
       req_f3_BITS_1_TO_0_90_EQ_0b0_91_OR_req_f3_BITS_ETC___d920,
       rg_addr_0_EQ_rg_lrsc_pa_8___d117,
       rg_amo_funct7_7_BITS_6_TO_2_8_EQ_0b10_9_AND_NO_ETC___d292,
       rg_lrsc_pa_8_EQ_rg_addr_0___d59,
       rg_op_4_EQ_0_5_OR_rg_op_4_EQ_2_6_AND_rg_amo_fu_ETC___d100,
       rg_op_4_EQ_0_5_OR_rg_op_4_EQ_2_6_AND_rg_amo_fu_ETC___d131,
       rg_op_4_EQ_0_5_OR_rg_op_4_EQ_2_6_AND_rg_amo_fu_ETC___d133,
       rg_op_4_EQ_0_5_OR_rg_op_4_EQ_2_6_AND_rg_amo_fu_ETC___d136,
       rg_op_4_EQ_0_5_OR_rg_op_4_EQ_2_6_AND_rg_amo_fu_ETC___d275,
       rg_op_4_EQ_0_5_OR_rg_op_4_EQ_2_6_AND_rg_amo_fu_ETC___d288,
       rg_op_4_EQ_1_2_OR_rg_op_4_EQ_2_6_AND_rg_amo_fu_ETC___d129,
       rg_op_4_EQ_1_2_OR_rg_op_4_EQ_2_6_AND_rg_amo_fu_ETC___d307,
       rg_op_4_EQ_1_2_OR_rg_op_4_EQ_2_6_AND_rg_amo_fu_ETC___d441,
       rg_op_4_EQ_1_2_OR_rg_op_4_EQ_2_6_AND_rg_amo_fu_ETC___d444,
       rg_op_4_EQ_2_6_AND_rg_amo_funct7_7_BITS_6_TO_2_ETC___d513,
       rg_op_4_EQ_2_6_AND_rg_amo_funct7_7_BITS_6_TO_2_ETC___d68,
       rg_state_EQ_13_90_AND_rg_op_4_EQ_0_5_OR_rg_op__ETC___d592,
       rg_state_EQ_3_1_AND_NOT_rg_op_4_EQ_0_5_2_AND_N_ETC___d90;

  // action method set_verbosity
  assign RDY_set_verbosity = 1'd1 ;
  assign CAN_FIRE_set_verbosity = 1'd1 ;
  assign WILL_FIRE_set_verbosity = EN_set_verbosity ;

  // action method server_reset_request_put
  assign RDY_server_reset_request_put = f_reset_reqs$FULL_N ;
  assign CAN_FIRE_server_reset_request_put = f_reset_reqs$FULL_N ;
  assign WILL_FIRE_server_reset_request_put = EN_server_reset_request_put ;

  // action method server_reset_response_get
  assign RDY_server_reset_response_get =
	     !f_reset_rsps$D_OUT && f_reset_rsps$EMPTY_N ;
  assign CAN_FIRE_server_reset_response_get =
	     !f_reset_rsps$D_OUT && f_reset_rsps$EMPTY_N ;
  assign WILL_FIRE_server_reset_response_get = EN_server_reset_response_get ;

  // action method req
  assign CAN_FIRE_req = 1'd1 ;
  assign WILL_FIRE_req = EN_req ;

  // value method valid
  assign valid = dw_valid$whas ;

  // value method addr
  assign addr = rg_addr ;

  // value method word64
  always@(MUX_dw_output_ld_val$wset_1__SEL_1 or
	  ld_val__h24158 or
	  MUX_ctr_wr_rsps_pending_crg$port0__write_1__SEL_1 or
	  new_ld_val__h26998 or
	  MUX_dw_output_ld_val$wset_1__SEL_3 or
	  MUX_dw_output_ld_val$wset_1__VAL_3 or
	  MUX_dw_output_ld_val$wset_1__SEL_4 or rg_ld_val)
  begin
    case (1'b1) // synopsys parallel_case
      MUX_dw_output_ld_val$wset_1__SEL_1: word64 = ld_val__h24158;
      MUX_ctr_wr_rsps_pending_crg$port0__write_1__SEL_1:
	  word64 = new_ld_val__h26998;
      MUX_dw_output_ld_val$wset_1__SEL_3:
	  word64 = MUX_dw_output_ld_val$wset_1__VAL_3;
      MUX_dw_output_ld_val$wset_1__SEL_4: word64 = rg_ld_val;
      default: word64 = 64'hAAAAAAAAAAAAAAAA /* unspecified value */ ;
    endcase
  end

  // value method st_amo_val
  assign st_amo_val =
	     MUX_dw_output_ld_val$wset_1__SEL_3 ? 64'd0 : rg_st_amo_val ;

  // value method exc
  assign exc = rg_state == 5'd4 ;

  // value method exc_code
  assign exc_code = rg_exc_code ;

  // action method server_flush_request_put
  assign RDY_server_flush_request_put = f_reset_reqs$FULL_N ;
  assign CAN_FIRE_server_flush_request_put = f_reset_reqs$FULL_N ;
  assign WILL_FIRE_server_flush_request_put = EN_server_flush_request_put ;

  // action method server_flush_response_get
  assign RDY_server_flush_response_get =
	     f_reset_rsps$D_OUT && f_reset_rsps$EMPTY_N ;
  assign CAN_FIRE_server_flush_response_get =
	     f_reset_rsps$D_OUT && f_reset_rsps$EMPTY_N ;
  assign WILL_FIRE_server_flush_response_get = EN_server_flush_response_get ;

  // action method tlb_flush
  assign RDY_tlb_flush = 1'd1 ;
  assign CAN_FIRE_tlb_flush = 1'd1 ;
  assign WILL_FIRE_tlb_flush = EN_tlb_flush ;

  // value method mem_master_m_awvalid
  assign mem_master_awvalid =
	     !master_xactor_crg_wr_addr_full$EN_port0__write &&
	     master_xactor_crg_wr_addr_full ;

  // value method mem_master_m_awid
  assign mem_master_awid = master_xactor_rg_wr_addr[96:93] ;

  // value method mem_master_m_awaddr
  assign mem_master_awaddr = master_xactor_rg_wr_addr[92:29] ;

  // value method mem_master_m_awlen
  assign mem_master_awlen = master_xactor_rg_wr_addr[28:21] ;

  // value method mem_master_m_awsize
  assign mem_master_awsize = master_xactor_rg_wr_addr[20:18] ;

  // value method mem_master_m_awburst
  assign mem_master_awburst = master_xactor_rg_wr_addr[17:16] ;

  // value method mem_master_m_awlock
  assign mem_master_awlock = master_xactor_rg_wr_addr[15] ;

  // value method mem_master_m_awcache
  assign mem_master_awcache = master_xactor_rg_wr_addr[14:11] ;

  // value method mem_master_m_awprot
  assign mem_master_awprot = master_xactor_rg_wr_addr[10:8] ;

  // value method mem_master_m_awqos
  assign mem_master_awqos = master_xactor_rg_wr_addr[7:4] ;

  // value method mem_master_m_awregion
  assign mem_master_awregion = master_xactor_rg_wr_addr[3:0] ;

  // action method mem_master_m_awready
  assign CAN_FIRE_mem_master_m_awready = 1'd1 ;
  assign WILL_FIRE_mem_master_m_awready = 1'd1 ;

  // value method mem_master_m_wvalid
  assign mem_master_wvalid =
	     !master_xactor_crg_wr_data_full$EN_port0__write &&
	     master_xactor_crg_wr_data_full ;

  // value method mem_master_m_wid
  assign mem_master_wid = master_xactor_rg_wr_data[76:73] ;

  // value method mem_master_m_wdata
  assign mem_master_wdata = master_xactor_rg_wr_data[72:9] ;

  // value method mem_master_m_wstrb
  assign mem_master_wstrb = master_xactor_rg_wr_data[8:1] ;

  // value method mem_master_m_wlast
  assign mem_master_wlast = master_xactor_rg_wr_data[0] ;

  // action method mem_master_m_wready
  assign CAN_FIRE_mem_master_m_wready = 1'd1 ;
  assign WILL_FIRE_mem_master_m_wready = 1'd1 ;

  // action method mem_master_m_bvalid
  assign CAN_FIRE_mem_master_m_bvalid = 1'd1 ;
  assign WILL_FIRE_mem_master_m_bvalid = 1'd1 ;

  // value method mem_master_m_bready
  assign mem_master_bready = !master_xactor_crg_wr_resp_full$port2__read ;

  // value method mem_master_m_arvalid
  assign mem_master_arvalid =
	     !master_xactor_crg_rd_addr_full$EN_port0__write &&
	     master_xactor_crg_rd_addr_full ;

  // value method mem_master_m_arid
  assign mem_master_arid = master_xactor_rg_rd_addr[96:93] ;

  // value method mem_master_m_araddr
  assign mem_master_araddr = master_xactor_rg_rd_addr[92:29] ;

  // value method mem_master_m_arlen
  assign mem_master_arlen = master_xactor_rg_rd_addr[28:21] ;

  // value method mem_master_m_arsize
  assign mem_master_arsize = master_xactor_rg_rd_addr[20:18] ;

  // value method mem_master_m_arburst
  assign mem_master_arburst = master_xactor_rg_rd_addr[17:16] ;

  // value method mem_master_m_arlock
  assign mem_master_arlock = master_xactor_rg_rd_addr[15] ;

  // value method mem_master_m_arcache
  assign mem_master_arcache = master_xactor_rg_rd_addr[14:11] ;

  // value method mem_master_m_arprot
  assign mem_master_arprot = master_xactor_rg_rd_addr[10:8] ;

  // value method mem_master_m_arqos
  assign mem_master_arqos = master_xactor_rg_rd_addr[7:4] ;

  // value method mem_master_m_arregion
  assign mem_master_arregion = master_xactor_rg_rd_addr[3:0] ;

  // action method mem_master_m_arready
  assign CAN_FIRE_mem_master_m_arready = 1'd1 ;
  assign WILL_FIRE_mem_master_m_arready = 1'd1 ;

  // action method mem_master_m_rvalid
  assign CAN_FIRE_mem_master_m_rvalid = 1'd1 ;
  assign WILL_FIRE_mem_master_m_rvalid = 1'd1 ;

  // value method mem_master_m_rready
  assign mem_master_rready = !master_xactor_crg_rd_data_full$port2__read ;

  // submodule f_reset_reqs
  FIFO2 #(.width(32'd1), .guarded(32'd1)) f_reset_reqs(.RST(RST_N),
						       .CLK(CLK),
						       .D_IN(f_reset_reqs$D_IN),
						       .ENQ(f_reset_reqs$ENQ),
						       .DEQ(f_reset_reqs$DEQ),
						       .CLR(f_reset_reqs$CLR),
						       .D_OUT(f_reset_reqs$D_OUT),
						       .FULL_N(f_reset_reqs$FULL_N),
						       .EMPTY_N(f_reset_reqs$EMPTY_N));

  // submodule f_reset_rsps
  FIFO2 #(.width(32'd1), .guarded(32'd1)) f_reset_rsps(.RST(RST_N),
						       .CLK(CLK),
						       .D_IN(f_reset_rsps$D_IN),
						       .ENQ(f_reset_rsps$ENQ),
						       .DEQ(f_reset_rsps$DEQ),
						       .CLR(f_reset_rsps$CLR),
						       .D_OUT(f_reset_rsps$D_OUT),
						       .FULL_N(f_reset_rsps$FULL_N),
						       .EMPTY_N(f_reset_rsps$EMPTY_N));

  // submodule ram_state_and_ctag_cset
  BRAM2 #(.PIPELINED(1'd0),
	  .ADDR_WIDTH(32'd6),
	  .DATA_WIDTH(32'd53),
	  .MEMSIZE(7'd64)) ram_state_and_ctag_cset(.CLKA(CLK),
						   .CLKB(CLK),
						   .ADDRA(ram_state_and_ctag_cset$ADDRA),
						   .ADDRB(ram_state_and_ctag_cset$ADDRB),
						   .DIA(ram_state_and_ctag_cset$DIA),
						   .DIB(ram_state_and_ctag_cset$DIB),
						   .WEA(ram_state_and_ctag_cset$WEA),
						   .WEB(ram_state_and_ctag_cset$WEB),
						   .ENA(ram_state_and_ctag_cset$ENA),
						   .ENB(ram_state_and_ctag_cset$ENB),
						   .DOA(),
						   .DOB(ram_state_and_ctag_cset$DOB));

  // submodule ram_word64_set
  BRAM2 #(.PIPELINED(1'd0),
	  .ADDR_WIDTH(32'd9),
	  .DATA_WIDTH(32'd64),
	  .MEMSIZE(10'd512)) ram_word64_set(.CLKA(CLK),
					    .CLKB(CLK),
					    .ADDRA(ram_word64_set$ADDRA),
					    .ADDRB(ram_word64_set$ADDRB),
					    .DIA(ram_word64_set$DIA),
					    .DIB(ram_word64_set$DIB),
					    .WEA(ram_word64_set$WEA),
					    .WEB(ram_word64_set$WEB),
					    .ENA(ram_word64_set$ENA),
					    .ENB(ram_word64_set$ENB),
					    .DOA(),
					    .DOB(ram_word64_set$DOB));

  // submodule soc_map
  mkSoC_Map soc_map(.CLK(CLK),
		    .RST_N(RST_N),
		    .m_is_IO_addr_addr(soc_map$m_is_IO_addr_addr),
		    .m_is_mem_addr_addr(soc_map$m_is_mem_addr_addr),
		    .m_is_near_mem_IO_addr_addr(soc_map$m_is_near_mem_IO_addr_addr),
		    .m_near_mem_io_addr_base(),
		    .m_near_mem_io_addr_size(),
		    .m_near_mem_io_addr_lim(),
		    .m_plic_addr_base(),
		    .m_plic_addr_size(),
		    .m_plic_addr_lim(),
		    .m_uart0_addr_base(),
		    .m_uart0_addr_size(),
		    .m_uart0_addr_lim(),
		    .m_boot_rom_addr_base(),
		    .m_boot_rom_addr_size(),
		    .m_boot_rom_addr_lim(),
		    .m_mem0_controller_addr_base(),
		    .m_mem0_controller_addr_size(),
		    .m_mem0_controller_addr_lim(),
		    .m_tcm_addr_base(),
		    .m_tcm_addr_size(),
		    .m_tcm_addr_lim(),
		    .m_is_mem_addr(soc_map$m_is_mem_addr),
		    .m_is_IO_addr(),
		    .m_is_near_mem_IO_addr(),
		    .m_pc_reset_value(),
		    .m_mtvec_reset_value(),
		    .m_nmivec_reset_value());

  // rule RL_rl_reset
  assign CAN_FIRE_RL_rl_reset =
	     (rg_cset_in_cache != 6'd63 ||
	      f_reset_reqs$EMPTY_N && f_reset_rsps$FULL_N) &&
	     rg_state == 5'd1 ;
  assign WILL_FIRE_RL_rl_reset = CAN_FIRE_RL_rl_reset ;

  // rule RL_rl_shift_sb_to_load_delay
  assign CAN_FIRE_RL_rl_shift_sb_to_load_delay = 1'd1 ;
  assign WILL_FIRE_RL_rl_shift_sb_to_load_delay = 1'd1 ;

  // rule RL_rl_rereq
  assign CAN_FIRE_RL_rl_rereq = rg_state == 5'd11 ;
  assign WILL_FIRE_RL_rl_rereq =
	     CAN_FIRE_RL_rl_rereq && !WILL_FIRE_RL_rl_start_reset && !EN_req ;

  // rule RL_rl_ST_AMO_response
  assign CAN_FIRE_RL_rl_ST_AMO_response = rg_state == 5'd12 ;
  assign WILL_FIRE_RL_rl_ST_AMO_response = CAN_FIRE_RL_rl_ST_AMO_response ;

  // rule RL_rl_maintain_io_read_rsp
  assign CAN_FIRE_RL_rl_maintain_io_read_rsp = rg_state == 5'd15 ;
  assign WILL_FIRE_RL_rl_maintain_io_read_rsp =
	     CAN_FIRE_RL_rl_maintain_io_read_rsp ;

  // rule RL_rl_io_AMO_SC_req
  assign CAN_FIRE_RL_rl_io_AMO_SC_req =
	     rg_state == 5'd13 && rg_op == 2'd2 &&
	     rg_amo_funct7[6:2] == 5'b00011 ;
  assign WILL_FIRE_RL_rl_io_AMO_SC_req =
	     CAN_FIRE_RL_rl_io_AMO_SC_req && !WILL_FIRE_RL_rl_start_reset ;

  // rule RL_rl_drive_exception_rsp
  assign CAN_FIRE_RL_rl_drive_exception_rsp = rg_state == 5'd4 ;
  assign WILL_FIRE_RL_rl_drive_exception_rsp = rg_state == 5'd4 ;

  // rule RL_rl_start_reset
  assign CAN_FIRE_RL_rl_start_reset =
	     f_reset_reqs$EMPTY_N && rg_state != 5'd1 ;
  assign WILL_FIRE_RL_rl_start_reset = CAN_FIRE_RL_rl_start_reset ;

  // rule RL_rl_probe_and_immed_rsp
  assign CAN_FIRE_RL_rl_probe_and_immed_rsp =
	     dmem_not_imem_AND_NOT_soc_map_m_is_mem_addr_rg_ETC___d80 &&
	     rg_state_EQ_3_1_AND_NOT_rg_op_4_EQ_0_5_2_AND_N_ETC___d90 ;
  assign WILL_FIRE_RL_rl_probe_and_immed_rsp =
	     CAN_FIRE_RL_rl_probe_and_immed_rsp &&
	     !WILL_FIRE_RL_rl_start_reset ;

  // rule RL_rl_cache_refill_rsps_loop
  assign CAN_FIRE_RL_rl_cache_refill_rsps_loop =
	     master_xactor_crg_rd_data_full$port1__read && rg_state == 5'd10 ;
  assign WILL_FIRE_RL_rl_cache_refill_rsps_loop =
	     CAN_FIRE_RL_rl_cache_refill_rsps_loop &&
	     !WILL_FIRE_RL_rl_start_reset &&
	     !EN_req ;

  // rule RL_rl_io_read_rsp
  assign CAN_FIRE_RL_rl_io_read_rsp =
	     master_xactor_crg_rd_data_full$port1__read && rg_state == 5'd14 ;
  assign WILL_FIRE_RL_rl_io_read_rsp =
	     CAN_FIRE_RL_rl_io_read_rsp && !WILL_FIRE_RL_rl_start_reset ;

  // rule RL_rl_io_write_req
  assign CAN_FIRE_RL_rl_io_write_req =
	     !master_xactor_crg_wr_addr_full$port2__read &&
	     !master_xactor_crg_wr_data_full$port2__read &&
	     rg_state == 5'd13 &&
	     rg_op == 2'd1 ;
  assign WILL_FIRE_RL_rl_io_write_req =
	     CAN_FIRE_RL_rl_io_write_req && !WILL_FIRE_RL_rl_start_reset ;

  // rule RL_rl_io_AMO_op_req
  assign CAN_FIRE_RL_rl_io_AMO_op_req =
	     !master_xactor_crg_rd_addr_full$port2__read &&
	     rg_state == 5'd13 &&
	     rg_op == 2'd2 &&
	     rg_amo_funct7[6:2] != 5'b00010 &&
	     rg_amo_funct7[6:2] != 5'b00011 ;
  assign WILL_FIRE_RL_rl_io_AMO_op_req =
	     CAN_FIRE_RL_rl_io_AMO_op_req && !WILL_FIRE_RL_rl_start_reset ;

  // rule RL_rl_io_AMO_read_rsp
  assign CAN_FIRE_RL_rl_io_AMO_read_rsp =
	     master_xactor_crg_rd_data_full_port1__read__51_ETC___d723 &&
	     rg_state == 5'd16 ;
  assign WILL_FIRE_RL_rl_io_AMO_read_rsp =
	     CAN_FIRE_RL_rl_io_AMO_read_rsp && !WILL_FIRE_RL_rl_start_reset ;

  // rule RL_rl_start_cache_refill
  assign CAN_FIRE_RL_rl_start_cache_refill =
	     !master_xactor_crg_rd_addr_full$port2__read &&
	     rg_state == 5'd9 &&
	     b__h20935 == 4'd0 ;
  assign WILL_FIRE_RL_rl_start_cache_refill = MUX_rg_state$write_1__SEL_3 ;

  // rule RL_rl_io_read_req
  assign CAN_FIRE_RL_rl_io_read_req =
	     !master_xactor_crg_rd_addr_full$port2__read &&
	     rg_state_EQ_13_90_AND_rg_op_4_EQ_0_5_OR_rg_op__ETC___d592 ;
  assign WILL_FIRE_RL_rl_io_read_req = MUX_rg_state$write_1__SEL_2 ;

  // rule RL_rl_discard_write_rsp
  assign CAN_FIRE_RL_rl_discard_write_rsp =
	     b__h20935 != 4'd0 && master_xactor_crg_wr_resp_full$port1__read ;
  assign WILL_FIRE_RL_rl_discard_write_rsp =
	     CAN_FIRE_RL_rl_discard_write_rsp &&
	     !WILL_FIRE_RL_rl_start_reset ;

  // inputs to muxes for submodule ports
  assign MUX_ctr_wr_rsps_pending_crg$port0__write_1__SEL_1 =
	     WILL_FIRE_RL_rl_io_AMO_read_rsp &&
	     master_xactor_rg_rd_data[2:1] == 2'b0 ;
  assign MUX_ctr_wr_rsps_pending_crg$port0__write_1__SEL_2 =
	     WILL_FIRE_RL_rl_probe_and_immed_rsp &&
	     (!dmem_not_imem || soc_map$m_is_mem_addr) &&
	     NOT_rg_op_4_EQ_0_5_2_AND_NOT_rg_op_4_EQ_2_6_3__ETC___d446 ;
  assign MUX_dw_output_ld_val$wset_1__SEL_1 =
	     WILL_FIRE_RL_rl_io_read_rsp &&
	     master_xactor_rg_rd_data[2:1] == 2'b0 ;
  assign MUX_dw_output_ld_val$wset_1__SEL_3 =
	     WILL_FIRE_RL_rl_probe_and_immed_rsp &&
	     (!dmem_not_imem || soc_map$m_is_mem_addr) &&
	     rg_op_4_EQ_0_5_OR_rg_op_4_EQ_2_6_AND_rg_amo_fu_ETC___d136 ;
  assign MUX_dw_output_ld_val$wset_1__SEL_4 =
	     WILL_FIRE_RL_rl_maintain_io_read_rsp ||
	     WILL_FIRE_RL_rl_ST_AMO_response ;
  assign MUX_master_xactor_rg_rd_addr$write_1__SEL_1 =
	     WILL_FIRE_RL_rl_io_AMO_op_req || WILL_FIRE_RL_rl_io_read_req ;
  assign MUX_ram_state_and_ctag_cset$b_put_1__SEL_1 =
	     EN_req &&
	     req_f3_BITS_1_TO_0_90_EQ_0b0_91_OR_req_f3_BITS_ETC___d920 ;
  assign MUX_ram_word64_set$a_put_1__SEL_1 =
	     WILL_FIRE_RL_rl_cache_refill_rsps_loop &&
	     master_xactor_rg_rd_data[2:1] == 2'b0 ;
  assign MUX_ram_word64_set$b_put_1__SEL_2 =
	     WILL_FIRE_RL_rl_cache_refill_rsps_loop &&
	     rg_word64_set_in_cache[2:0] != 3'd7 ;
  assign MUX_rg_error_during_refill$write_1__SEL_1 =
	     WILL_FIRE_RL_rl_cache_refill_rsps_loop &&
	     master_xactor_rg_rd_data[2:1] != 2'b0 ;
  assign MUX_rg_exc_code$write_1__SEL_1 =
	     EN_req &&
	     NOT_req_f3_BITS_1_TO_0_90_EQ_0b0_91_92_AND_NOT_ETC___d911 ;
  assign MUX_rg_exc_code$write_1__SEL_2 =
	     WILL_FIRE_RL_rl_io_AMO_read_rsp &&
	     master_xactor_rg_rd_data[2:1] != 2'b0 ;
  assign MUX_rg_exc_code$write_1__SEL_3 =
	     WILL_FIRE_RL_rl_io_read_rsp &&
	     master_xactor_rg_rd_data[2:1] != 2'b0 ;
  assign MUX_rg_ld_val$write_1__SEL_2 =
	     WILL_FIRE_RL_rl_probe_and_immed_rsp &&
	     NOT_dmem_not_imem_13_OR_soc_map_m_is_mem_addr__ETC___d298 ;
  assign MUX_rg_lrsc_valid$write_1__SEL_2 =
	     WILL_FIRE_RL_rl_probe_and_immed_rsp &&
	     (!dmem_not_imem || soc_map$m_is_mem_addr) &&
	     rg_op_4_EQ_0_5_OR_rg_op_4_EQ_2_6_AND_rg_amo_fu_ETC___d131 ;
  assign MUX_rg_state$write_1__SEL_2 =
	     CAN_FIRE_RL_rl_io_read_req && !WILL_FIRE_RL_rl_start_reset ;
  assign MUX_rg_state$write_1__SEL_3 =
	     CAN_FIRE_RL_rl_start_cache_refill &&
	     !WILL_FIRE_RL_rl_start_reset &&
	     !EN_req ;
  assign MUX_rg_state$write_1__SEL_8 =
	     WILL_FIRE_RL_rl_cache_refill_rsps_loop &&
	     rg_word64_set_in_cache[2:0] == 3'd7 ;
  assign MUX_rg_state$write_1__SEL_9 =
	     WILL_FIRE_RL_rl_probe_and_immed_rsp &&
	     (dmem_not_imem && !soc_map$m_is_mem_addr ||
	      rg_op_4_EQ_0_5_OR_rg_op_4_EQ_2_6_AND_rg_amo_fu_ETC___d100 ||
	      NOT_rg_op_4_EQ_0_5_2_AND_NOT_rg_op_4_EQ_2_6_3__ETC___d105) ;
  assign MUX_rg_state$write_1__SEL_13 =
	     WILL_FIRE_RL_rl_reset && rg_cset_in_cache == 6'd63 ;
  assign MUX_ctr_wr_rsps_pending_crg$port0__write_1__VAL_1 =
	     ctr_wr_rsps_pending_crg + 4'd1 ;
  assign MUX_dw_output_ld_val$wset_1__VAL_3 =
	     (rg_op == 2'd0 ||
	      rg_op == 2'd2 && rg_amo_funct7[6:2] == 5'b00010) ?
	       new_value__h5462 :
	       new_value__h15489 ;
  assign MUX_master_xactor_rg_rd_addr$write_1__VAL_1 =
	     { 4'd0, rg_pa, 8'd0, value__h26583, 18'd65536 } ;
  assign MUX_master_xactor_rg_rd_addr$write_1__VAL_2 =
	     { 4'd0, cline_fabric_addr__h21034, 29'd15532032 } ;
  assign MUX_master_xactor_rg_wr_addr$write_1__VAL_1 =
	     { 4'd0, rg_pa, 8'd0, value__h29609, 18'd65536 } ;
  assign MUX_master_xactor_rg_wr_addr$write_1__VAL_2 =
	     { 4'd0, rg_addr, 8'd0, value__h29609, 18'd65536 } ;
  assign MUX_master_xactor_rg_wr_data$write_1__VAL_1 =
	     { 4'd0,
	       mem_req_wr_data_wdata__h27265,
	       mem_req_wr_data_wstrb__h27266,
	       1'd1 } ;
  assign MUX_master_xactor_rg_wr_data$write_1__VAL_2 =
	     { 4'd0,
	       IF_rg_op_4_EQ_1_2_OR_rg_op_4_EQ_2_6_AND_rg_amo_ETC___d466,
	       mem_req_wr_data_wstrb__h20333,
	       1'd1 } ;
  assign MUX_master_xactor_rg_wr_data$write_1__VAL_3 =
	     { 4'd0,
	       mem_req_wr_data_wdata__h25761,
	       mem_req_wr_data_wstrb__h27266,
	       1'd1 } ;
  assign MUX_ram_state_and_ctag_cset$a_put_3__VAL_1 = { 1'd1, rg_pa[63:12] } ;
  assign MUX_ram_word64_set$a_put_3__VAL_2 =
	     (rg_op == 2'd1 ||
	      rg_op == 2'd2 && rg_amo_funct7[6:2] == 5'b00011) ?
	       IF_rg_f3_38_EQ_0b0_39_THEN_IF_rg_addr_0_BITS_2_ETC___d360 :
	       IF_rg_f3_38_EQ_0b0_39_THEN_IF_rg_addr_0_BITS_2_ETC___d434 ;
  assign MUX_ram_word64_set$b_put_2__VAL_2 = rg_word64_set_in_cache + 9'd1 ;
  assign MUX_ram_word64_set$b_put_2__VAL_4 = { rg_addr[11:6], 3'd0 } ;
  assign MUX_rg_cset_in_cache$write_1__VAL_1 = rg_cset_in_cache + 6'd1 ;
  assign MUX_rg_exc_code$write_1__VAL_1 = (req_op == 2'd0) ? 4'd4 : 4'd6 ;
  assign MUX_rg_ld_val$write_1__VAL_2 =
	     (rg_op == 2'd1 ||
	      rg_op == 2'd2 && rg_amo_funct7[6:2] == 5'b00011) ?
	       x__h13141 :
	       IF_rg_f3_38_EQ_0b10_44_THEN_SEXT_IF_rg_f3_38_E_ETC___d302 ;
  assign MUX_rg_state$write_1__VAL_1 =
	     NOT_req_f3_BITS_1_TO_0_90_EQ_0b0_91_92_AND_NOT_ETC___d911 ?
	       5'd4 :
	       5'd3 ;
  assign MUX_rg_state$write_1__VAL_4 =
	     (master_xactor_rg_rd_data[2:1] == 2'b0) ? 5'd15 : 5'd4 ;
  assign MUX_rg_state$write_1__VAL_8 =
	     (master_xactor_rg_rd_data[2:1] != 2'b0 ||
	      rg_error_during_refill) ?
	       5'd4 :
	       5'd11 ;
  assign MUX_rg_state$write_1__VAL_9 =
	     (dmem_not_imem && !soc_map$m_is_mem_addr) ?
	       5'd13 :
	       IF_rg_op_4_EQ_0_5_OR_rg_op_4_EQ_2_6_AND_rg_amo_ETC___d110 ;

  // inlined wires
  assign dw_valid$whas =
	     (WILL_FIRE_RL_rl_io_AMO_read_rsp ||
	      WILL_FIRE_RL_rl_io_read_rsp) &&
	     master_xactor_rg_rd_data[2:1] == 2'b0 ||
	     WILL_FIRE_RL_rl_probe_and_immed_rsp &&
	     (!dmem_not_imem || soc_map$m_is_mem_addr) &&
	     rg_op_4_EQ_0_5_OR_rg_op_4_EQ_2_6_AND_rg_amo_fu_ETC___d136 ||
	     WILL_FIRE_RL_rl_drive_exception_rsp ||
	     WILL_FIRE_RL_rl_maintain_io_read_rsp ||
	     WILL_FIRE_RL_rl_ST_AMO_response ;
  assign master_xactor_crg_wr_addr_full$EN_port0__write =
	     WILL_FIRE_RL_rl_start_reset && !f_reset_reqs$D_OUT ;
  assign master_xactor_crg_wr_addr_full$port1__read =
	     !master_xactor_crg_wr_addr_full$EN_port0__write &&
	     master_xactor_crg_wr_addr_full ;
  assign master_xactor_crg_wr_addr_full$EN_port1__write =
	     master_xactor_crg_wr_addr_full$port1__read &&
	     mem_master_awready ;
  assign master_xactor_crg_wr_addr_full$port2__read =
	     !master_xactor_crg_wr_addr_full$EN_port1__write &&
	     master_xactor_crg_wr_addr_full$port1__read ;
  assign master_xactor_crg_wr_addr_full$EN_port2__write =
	     WILL_FIRE_RL_rl_io_AMO_read_rsp &&
	     master_xactor_rg_rd_data[2:1] == 2'b0 ||
	     WILL_FIRE_RL_rl_probe_and_immed_rsp &&
	     (!dmem_not_imem || soc_map$m_is_mem_addr) &&
	     NOT_rg_op_4_EQ_0_5_2_AND_NOT_rg_op_4_EQ_2_6_3__ETC___d446 ||
	     WILL_FIRE_RL_rl_io_write_req ;
  assign master_xactor_crg_wr_addr_full$port3__read =
	     master_xactor_crg_wr_addr_full$EN_port2__write ?
	       1'd1 :
	       master_xactor_crg_wr_addr_full$port2__read ;
  assign master_xactor_crg_wr_data_full$EN_port0__write =
	     WILL_FIRE_RL_rl_start_reset && !f_reset_reqs$D_OUT ;
  assign master_xactor_crg_wr_data_full$port1__read =
	     !master_xactor_crg_wr_data_full$EN_port0__write &&
	     master_xactor_crg_wr_data_full ;
  assign master_xactor_crg_wr_data_full$EN_port1__write =
	     master_xactor_crg_wr_data_full$port1__read && mem_master_wready ;
  assign master_xactor_crg_wr_data_full$port2__read =
	     !master_xactor_crg_wr_data_full$EN_port1__write &&
	     master_xactor_crg_wr_data_full$port1__read ;
  assign master_xactor_crg_wr_data_full$EN_port2__write =
	     WILL_FIRE_RL_rl_io_AMO_read_rsp &&
	     master_xactor_rg_rd_data[2:1] == 2'b0 ||
	     WILL_FIRE_RL_rl_probe_and_immed_rsp &&
	     (!dmem_not_imem || soc_map$m_is_mem_addr) &&
	     NOT_rg_op_4_EQ_0_5_2_AND_NOT_rg_op_4_EQ_2_6_3__ETC___d446 ||
	     WILL_FIRE_RL_rl_io_write_req ;
  assign master_xactor_crg_wr_data_full$port3__read =
	     master_xactor_crg_wr_data_full$EN_port2__write ?
	       1'd1 :
	       master_xactor_crg_wr_data_full$port2__read ;
  assign master_xactor_crg_wr_resp_full$EN_port0__write =
	     WILL_FIRE_RL_rl_start_reset && !f_reset_reqs$D_OUT ;
  assign master_xactor_crg_wr_resp_full$port1__read =
	     !master_xactor_crg_wr_resp_full$EN_port0__write &&
	     master_xactor_crg_wr_resp_full ;
  assign master_xactor_crg_wr_resp_full$port2__read =
	     !WILL_FIRE_RL_rl_discard_write_rsp &&
	     master_xactor_crg_wr_resp_full$port1__read ;
  assign master_xactor_crg_wr_resp_full$EN_port2__write =
	     mem_master_bvalid &&
	     !master_xactor_crg_wr_resp_full$port2__read ;
  assign master_xactor_crg_wr_resp_full$port3__read =
	     master_xactor_crg_wr_resp_full$EN_port2__write ||
	     master_xactor_crg_wr_resp_full$port2__read ;
  assign master_xactor_crg_rd_addr_full$EN_port0__write =
	     WILL_FIRE_RL_rl_start_reset && !f_reset_reqs$D_OUT ;
  assign master_xactor_crg_rd_addr_full$port1__read =
	     !master_xactor_crg_rd_addr_full$EN_port0__write &&
	     master_xactor_crg_rd_addr_full ;
  assign master_xactor_crg_rd_addr_full$EN_port1__write =
	     master_xactor_crg_rd_addr_full$port1__read &&
	     mem_master_arready ;
  assign master_xactor_crg_rd_addr_full$port2__read =
	     !master_xactor_crg_rd_addr_full$EN_port1__write &&
	     master_xactor_crg_rd_addr_full$port1__read ;
  assign master_xactor_crg_rd_addr_full$EN_port2__write =
	     WILL_FIRE_RL_rl_io_AMO_op_req || WILL_FIRE_RL_rl_io_read_req ||
	     WILL_FIRE_RL_rl_start_cache_refill ;
  assign master_xactor_crg_rd_addr_full$port3__read =
	     master_xactor_crg_rd_addr_full$EN_port2__write ||
	     master_xactor_crg_rd_addr_full$port2__read ;
  assign master_xactor_crg_rd_data_full$EN_port0__write =
	     WILL_FIRE_RL_rl_start_reset && !f_reset_reqs$D_OUT ;
  assign master_xactor_crg_rd_data_full$port1__read =
	     !master_xactor_crg_rd_data_full$EN_port0__write &&
	     master_xactor_crg_rd_data_full ;
  assign master_xactor_crg_rd_data_full$EN_port1__write =
	     WILL_FIRE_RL_rl_io_AMO_read_rsp || WILL_FIRE_RL_rl_io_read_rsp ||
	     WILL_FIRE_RL_rl_cache_refill_rsps_loop ;
  assign master_xactor_crg_rd_data_full$port2__read =
	     !master_xactor_crg_rd_data_full$EN_port1__write &&
	     master_xactor_crg_rd_data_full$port1__read ;
  assign master_xactor_crg_rd_data_full$EN_port2__write =
	     mem_master_rvalid &&
	     !master_xactor_crg_rd_data_full$port2__read ;
  assign master_xactor_crg_rd_data_full$port3__read =
	     master_xactor_crg_rd_data_full$EN_port2__write ||
	     master_xactor_crg_rd_data_full$port2__read ;
  assign ctr_wr_rsps_pending_crg$EN_port0__write =
	     WILL_FIRE_RL_rl_io_AMO_read_rsp &&
	     master_xactor_rg_rd_data[2:1] == 2'b0 ||
	     WILL_FIRE_RL_rl_probe_and_immed_rsp &&
	     (!dmem_not_imem || soc_map$m_is_mem_addr) &&
	     NOT_rg_op_4_EQ_0_5_2_AND_NOT_rg_op_4_EQ_2_6_3__ETC___d446 ||
	     WILL_FIRE_RL_rl_io_write_req ;
  always@(MUX_ctr_wr_rsps_pending_crg$port0__write_1__SEL_1 or
	  MUX_ctr_wr_rsps_pending_crg$port0__write_1__VAL_1 or
	  MUX_ctr_wr_rsps_pending_crg$port0__write_1__SEL_2 or
	  WILL_FIRE_RL_rl_io_write_req)
  begin
    case (1'b1) // synopsys parallel_case
      MUX_ctr_wr_rsps_pending_crg$port0__write_1__SEL_1:
	  ctr_wr_rsps_pending_crg$port0__write_1 =
	      MUX_ctr_wr_rsps_pending_crg$port0__write_1__VAL_1;
      MUX_ctr_wr_rsps_pending_crg$port0__write_1__SEL_2:
	  ctr_wr_rsps_pending_crg$port0__write_1 =
	      MUX_ctr_wr_rsps_pending_crg$port0__write_1__VAL_1;
      WILL_FIRE_RL_rl_io_write_req:
	  ctr_wr_rsps_pending_crg$port0__write_1 =
	      MUX_ctr_wr_rsps_pending_crg$port0__write_1__VAL_1;
      default: ctr_wr_rsps_pending_crg$port0__write_1 =
		   4'b1010 /* unspecified value */ ;
    endcase
  end
  assign ctr_wr_rsps_pending_crg$port1__write_1 = b__h20935 - 4'd1 ;
  assign ctr_wr_rsps_pending_crg$port2__read =
	     WILL_FIRE_RL_rl_discard_write_rsp ?
	       ctr_wr_rsps_pending_crg$port1__write_1 :
	       b__h20935 ;
  assign ctr_wr_rsps_pending_crg$EN_port2__write =
	     WILL_FIRE_RL_rl_start_reset && !f_reset_reqs$D_OUT ;
  assign ctr_wr_rsps_pending_crg$port3__read =
	     ctr_wr_rsps_pending_crg$EN_port2__write ?
	       4'd0 :
	       ctr_wr_rsps_pending_crg$port2__read ;
  assign crg_sb_to_load_delay$port0__write_1 =
	     { 1'd0, crg_sb_to_load_delay[10:1] } ;
  assign crg_sb_to_load_delay$EN_port1__write =
	     WILL_FIRE_RL_rl_probe_and_immed_rsp &&
	     NOT_dmem_not_imem_13_OR_soc_map_m_is_mem_addr__ETC___d443 ;
  assign crg_sb_to_load_delay$port2__read =
	     crg_sb_to_load_delay$EN_port1__write ?
	       11'd2047 :
	       crg_sb_to_load_delay$port0__write_1 ;

  // register cfg_verbosity
  assign cfg_verbosity$D_IN = set_verbosity_verbosity ;
  assign cfg_verbosity$EN = EN_set_verbosity ;

  // register crg_sb_to_load_delay
  assign crg_sb_to_load_delay$D_IN = crg_sb_to_load_delay$port2__read ;
  assign crg_sb_to_load_delay$EN = 1'b1 ;

  // register ctr_wr_rsps_pending_crg
  assign ctr_wr_rsps_pending_crg$D_IN = ctr_wr_rsps_pending_crg$port3__read ;
  assign ctr_wr_rsps_pending_crg$EN = 1'b1 ;

  // register master_xactor_crg_rd_addr_full
  assign master_xactor_crg_rd_addr_full$D_IN =
	     master_xactor_crg_rd_addr_full$port3__read ;
  assign master_xactor_crg_rd_addr_full$EN = 1'b1 ;

  // register master_xactor_crg_rd_data_full
  assign master_xactor_crg_rd_data_full$D_IN =
	     master_xactor_crg_rd_data_full$port3__read ;
  assign master_xactor_crg_rd_data_full$EN = 1'b1 ;

  // register master_xactor_crg_wr_addr_full
  assign master_xactor_crg_wr_addr_full$D_IN =
	     master_xactor_crg_wr_addr_full$port3__read ;
  assign master_xactor_crg_wr_addr_full$EN = 1'b1 ;

  // register master_xactor_crg_wr_data_full
  assign master_xactor_crg_wr_data_full$D_IN =
	     master_xactor_crg_wr_data_full$port3__read ;
  assign master_xactor_crg_wr_data_full$EN = 1'b1 ;

  // register master_xactor_crg_wr_resp_full
  assign master_xactor_crg_wr_resp_full$D_IN =
	     master_xactor_crg_wr_resp_full$port3__read ;
  assign master_xactor_crg_wr_resp_full$EN = 1'b1 ;

  // register master_xactor_rg_rd_addr
  assign master_xactor_rg_rd_addr$D_IN =
	     MUX_master_xactor_rg_rd_addr$write_1__SEL_1 ?
	       MUX_master_xactor_rg_rd_addr$write_1__VAL_1 :
	       MUX_master_xactor_rg_rd_addr$write_1__VAL_2 ;
  assign master_xactor_rg_rd_addr$EN =
	     WILL_FIRE_RL_rl_io_AMO_op_req || WILL_FIRE_RL_rl_io_read_req ||
	     WILL_FIRE_RL_rl_start_cache_refill ;

  // register master_xactor_rg_rd_data
  assign master_xactor_rg_rd_data$D_IN =
	     { mem_master_rid,
	       mem_master_rdata,
	       mem_master_rresp,
	       mem_master_rlast } ;
  assign master_xactor_rg_rd_data$EN = 1'd1 ;

  // register master_xactor_rg_wr_addr
  always@(MUX_ctr_wr_rsps_pending_crg$port0__write_1__SEL_1 or
	  MUX_master_xactor_rg_wr_addr$write_1__VAL_1 or
	  MUX_ctr_wr_rsps_pending_crg$port0__write_1__SEL_2 or
	  MUX_master_xactor_rg_wr_addr$write_1__VAL_2 or
	  WILL_FIRE_RL_rl_io_write_req)
  begin
    case (1'b1) // synopsys parallel_case
      MUX_ctr_wr_rsps_pending_crg$port0__write_1__SEL_1:
	  master_xactor_rg_wr_addr$D_IN =
	      MUX_master_xactor_rg_wr_addr$write_1__VAL_1;
      MUX_ctr_wr_rsps_pending_crg$port0__write_1__SEL_2:
	  master_xactor_rg_wr_addr$D_IN =
	      MUX_master_xactor_rg_wr_addr$write_1__VAL_2;
      WILL_FIRE_RL_rl_io_write_req:
	  master_xactor_rg_wr_addr$D_IN =
	      MUX_master_xactor_rg_wr_addr$write_1__VAL_1;
      default: master_xactor_rg_wr_addr$D_IN =
		   97'h0AAAAAAAAAAAAAAAAAAAAAAAA /* unspecified value */ ;
    endcase
  end
  assign master_xactor_rg_wr_addr$EN =
	     WILL_FIRE_RL_rl_io_AMO_read_rsp &&
	     master_xactor_rg_rd_data[2:1] == 2'b0 ||
	     WILL_FIRE_RL_rl_probe_and_immed_rsp &&
	     (!dmem_not_imem || soc_map$m_is_mem_addr) &&
	     NOT_rg_op_4_EQ_0_5_2_AND_NOT_rg_op_4_EQ_2_6_3__ETC___d446 ||
	     WILL_FIRE_RL_rl_io_write_req ;

  // register master_xactor_rg_wr_data
  always@(MUX_ctr_wr_rsps_pending_crg$port0__write_1__SEL_1 or
	  MUX_master_xactor_rg_wr_data$write_1__VAL_1 or
	  MUX_ctr_wr_rsps_pending_crg$port0__write_1__SEL_2 or
	  MUX_master_xactor_rg_wr_data$write_1__VAL_2 or
	  WILL_FIRE_RL_rl_io_write_req or
	  MUX_master_xactor_rg_wr_data$write_1__VAL_3)
  begin
    case (1'b1) // synopsys parallel_case
      MUX_ctr_wr_rsps_pending_crg$port0__write_1__SEL_1:
	  master_xactor_rg_wr_data$D_IN =
	      MUX_master_xactor_rg_wr_data$write_1__VAL_1;
      MUX_ctr_wr_rsps_pending_crg$port0__write_1__SEL_2:
	  master_xactor_rg_wr_data$D_IN =
	      MUX_master_xactor_rg_wr_data$write_1__VAL_2;
      WILL_FIRE_RL_rl_io_write_req:
	  master_xactor_rg_wr_data$D_IN =
	      MUX_master_xactor_rg_wr_data$write_1__VAL_3;
      default: master_xactor_rg_wr_data$D_IN =
		   77'h0AAAAAAAAAAAAAAAAAAA /* unspecified value */ ;
    endcase
  end
  assign master_xactor_rg_wr_data$EN =
	     WILL_FIRE_RL_rl_io_AMO_read_rsp &&
	     master_xactor_rg_rd_data[2:1] == 2'b0 ||
	     WILL_FIRE_RL_rl_probe_and_immed_rsp &&
	     (!dmem_not_imem || soc_map$m_is_mem_addr) &&
	     NOT_rg_op_4_EQ_0_5_2_AND_NOT_rg_op_4_EQ_2_6_3__ETC___d446 ||
	     WILL_FIRE_RL_rl_io_write_req ;

  // register master_xactor_rg_wr_resp
  assign master_xactor_rg_wr_resp$D_IN =
	     { mem_master_bid, mem_master_bresp } ;
  assign master_xactor_rg_wr_resp$EN =
	     mem_master_bvalid &&
	     !master_xactor_crg_wr_resp_full$port2__read ;

  // register rg_addr
  assign rg_addr$D_IN = req_addr ;
  assign rg_addr$EN = EN_req ;

  // register rg_amo_funct7
  assign rg_amo_funct7$D_IN = req_amo_funct7 ;
  assign rg_amo_funct7$EN = EN_req ;

  // register rg_cset_in_cache
  assign rg_cset_in_cache$D_IN =
	     WILL_FIRE_RL_rl_reset ?
	       MUX_rg_cset_in_cache$write_1__VAL_1 :
	       6'd0 ;
  assign rg_cset_in_cache$EN =
	     WILL_FIRE_RL_rl_reset || WILL_FIRE_RL_rl_start_reset ;

  // register rg_error_during_refill
  assign rg_error_during_refill$D_IN =
	     MUX_rg_error_during_refill$write_1__SEL_1 ;
  assign rg_error_during_refill$EN =
	     WILL_FIRE_RL_rl_cache_refill_rsps_loop &&
	     master_xactor_rg_rd_data[2:1] != 2'b0 ||
	     WILL_FIRE_RL_rl_start_cache_refill ;

  // register rg_exc_code
  always@(MUX_rg_exc_code$write_1__SEL_1 or
	  MUX_rg_exc_code$write_1__VAL_1 or
	  MUX_rg_exc_code$write_1__SEL_2 or
	  MUX_rg_exc_code$write_1__SEL_3 or
	  MUX_rg_error_during_refill$write_1__SEL_1 or access_exc_code__h2925)
  case (1'b1)
    MUX_rg_exc_code$write_1__SEL_1:
	rg_exc_code$D_IN = MUX_rg_exc_code$write_1__VAL_1;
    MUX_rg_exc_code$write_1__SEL_2: rg_exc_code$D_IN = 4'd7;
    MUX_rg_exc_code$write_1__SEL_3: rg_exc_code$D_IN = 4'd5;
    MUX_rg_error_during_refill$write_1__SEL_1:
	rg_exc_code$D_IN = access_exc_code__h2925;
    default: rg_exc_code$D_IN = 4'b1010 /* unspecified value */ ;
  endcase
  assign rg_exc_code$EN =
	     WILL_FIRE_RL_rl_cache_refill_rsps_loop &&
	     master_xactor_rg_rd_data[2:1] != 2'b0 ||
	     WILL_FIRE_RL_rl_io_read_rsp &&
	     master_xactor_rg_rd_data[2:1] != 2'b0 ||
	     WILL_FIRE_RL_rl_io_AMO_read_rsp &&
	     master_xactor_rg_rd_data[2:1] != 2'b0 ||
	     EN_req &&
	     NOT_req_f3_BITS_1_TO_0_90_EQ_0b0_91_92_AND_NOT_ETC___d911 ;

  // register rg_f3
  assign rg_f3$D_IN = req_f3 ;
  assign rg_f3$EN = EN_req ;

  // register rg_ld_val
  always@(MUX_ctr_wr_rsps_pending_crg$port0__write_1__SEL_1 or
	  new_ld_val__h26998 or
	  MUX_rg_ld_val$write_1__SEL_2 or
	  MUX_rg_ld_val$write_1__VAL_2 or
	  WILL_FIRE_RL_rl_io_read_rsp or
	  ld_val__h24158 or WILL_FIRE_RL_rl_io_AMO_SC_req)
  begin
    case (1'b1) // synopsys parallel_case
      MUX_ctr_wr_rsps_pending_crg$port0__write_1__SEL_1:
	  rg_ld_val$D_IN = new_ld_val__h26998;
      MUX_rg_ld_val$write_1__SEL_2:
	  rg_ld_val$D_IN = MUX_rg_ld_val$write_1__VAL_2;
      WILL_FIRE_RL_rl_io_read_rsp: rg_ld_val$D_IN = ld_val__h24158;
      WILL_FIRE_RL_rl_io_AMO_SC_req: rg_ld_val$D_IN = 64'd1;
      default: rg_ld_val$D_IN = 64'hAAAAAAAAAAAAAAAA /* unspecified value */ ;
    endcase
  end
  assign rg_ld_val$EN =
	     WILL_FIRE_RL_rl_io_AMO_read_rsp &&
	     master_xactor_rg_rd_data[2:1] == 2'b0 ||
	     WILL_FIRE_RL_rl_probe_and_immed_rsp &&
	     NOT_dmem_not_imem_13_OR_soc_map_m_is_mem_addr__ETC___d298 ||
	     WILL_FIRE_RL_rl_io_read_rsp ||
	     WILL_FIRE_RL_rl_io_AMO_SC_req ;

  // register rg_lower_word32
  assign rg_lower_word32$D_IN = 32'h0 ;
  assign rg_lower_word32$EN = 1'b0 ;

  // register rg_lower_word32_full
  assign rg_lower_word32_full$D_IN = 1'd0 ;
  assign rg_lower_word32_full$EN =
	     WILL_FIRE_RL_rl_start_cache_refill ||
	     WILL_FIRE_RL_rl_start_reset ;

  // register rg_lrsc_pa
  assign rg_lrsc_pa$D_IN = rg_addr ;
  assign rg_lrsc_pa$EN =
	     WILL_FIRE_RL_rl_probe_and_immed_rsp &&
	     (!dmem_not_imem || soc_map$m_is_mem_addr) &&
	     rg_op == 2'd2 &&
	     rg_amo_funct7[6:2] == 5'b00010 &&
	     ram_state_and_ctag_cset$DOB[52] &&
	     ram_state_and_ctag_cset_b_read__9_BITS_51_TO_0_ETC___d74 ;

  // register rg_lrsc_valid
  assign rg_lrsc_valid$D_IN =
	     MUX_rg_lrsc_valid$write_1__SEL_2 &&
	     rg_op_4_EQ_0_5_OR_rg_op_4_EQ_2_6_AND_rg_amo_fu_ETC___d133 ;
  assign rg_lrsc_valid$EN =
	     WILL_FIRE_RL_rl_io_read_req && rg_op == 2'd2 &&
	     rg_amo_funct7[6:2] == 5'b00010 ||
	     WILL_FIRE_RL_rl_probe_and_immed_rsp &&
	     (!dmem_not_imem || soc_map$m_is_mem_addr) &&
	     rg_op_4_EQ_0_5_OR_rg_op_4_EQ_2_6_AND_rg_amo_fu_ETC___d131 ||
	     WILL_FIRE_RL_rl_start_reset ;

  // register rg_op
  assign rg_op$D_IN = req_op ;
  assign rg_op$EN = EN_req ;

  // register rg_pa
  assign rg_pa$D_IN = EN_req ? req_addr : rg_addr ;
  assign rg_pa$EN = EN_req || WILL_FIRE_RL_rl_probe_and_immed_rsp ;

  // register rg_pte_pa
  assign rg_pte_pa$D_IN = 64'h0 ;
  assign rg_pte_pa$EN = 1'b0 ;

  // register rg_st_amo_val
  assign rg_st_amo_val$D_IN = EN_req ? req_st_value : new_st_val__h17351 ;
  assign rg_st_amo_val$EN =
	     WILL_FIRE_RL_rl_probe_and_immed_rsp &&
	     NOT_dmem_not_imem_13_OR_soc_map_m_is_mem_addr__ETC___d534 ||
	     EN_req ;

  // register rg_state
  always@(EN_req or
	  MUX_rg_state$write_1__VAL_1 or
	  WILL_FIRE_RL_rl_io_read_req or
	  WILL_FIRE_RL_rl_start_cache_refill or
	  WILL_FIRE_RL_rl_io_AMO_read_rsp or
	  MUX_rg_state$write_1__VAL_4 or
	  WILL_FIRE_RL_rl_io_AMO_op_req or
	  WILL_FIRE_RL_rl_io_write_req or
	  WILL_FIRE_RL_rl_io_read_rsp or
	  MUX_rg_state$write_1__SEL_8 or
	  MUX_rg_state$write_1__VAL_8 or
	  MUX_rg_state$write_1__SEL_9 or
	  MUX_rg_state$write_1__VAL_9 or
	  WILL_FIRE_RL_rl_start_reset or
	  WILL_FIRE_RL_rl_io_AMO_SC_req or
	  WILL_FIRE_RL_rl_rereq or MUX_rg_state$write_1__SEL_13)
  case (1'b1)
    EN_req: rg_state$D_IN = MUX_rg_state$write_1__VAL_1;
    WILL_FIRE_RL_rl_io_read_req: rg_state$D_IN = 5'd14;
    WILL_FIRE_RL_rl_start_cache_refill: rg_state$D_IN = 5'd10;
    WILL_FIRE_RL_rl_io_AMO_read_rsp:
	rg_state$D_IN = MUX_rg_state$write_1__VAL_4;
    WILL_FIRE_RL_rl_io_AMO_op_req: rg_state$D_IN = 5'd16;
    WILL_FIRE_RL_rl_io_write_req: rg_state$D_IN = 5'd12;
    WILL_FIRE_RL_rl_io_read_rsp: rg_state$D_IN = MUX_rg_state$write_1__VAL_4;
    MUX_rg_state$write_1__SEL_8: rg_state$D_IN = MUX_rg_state$write_1__VAL_8;
    MUX_rg_state$write_1__SEL_9: rg_state$D_IN = MUX_rg_state$write_1__VAL_9;
    WILL_FIRE_RL_rl_start_reset: rg_state$D_IN = 5'd1;
    WILL_FIRE_RL_rl_io_AMO_SC_req: rg_state$D_IN = 5'd12;
    WILL_FIRE_RL_rl_rereq: rg_state$D_IN = 5'd3;
    MUX_rg_state$write_1__SEL_13: rg_state$D_IN = 5'd2;
    default: rg_state$D_IN = 5'b01010 /* unspecified value */ ;
  endcase
  assign rg_state$EN =
	     WILL_FIRE_RL_rl_reset && rg_cset_in_cache == 6'd63 ||
	     WILL_FIRE_RL_rl_cache_refill_rsps_loop &&
	     rg_word64_set_in_cache[2:0] == 3'd7 ||
	     MUX_rg_state$write_1__SEL_9 ||
	     WILL_FIRE_RL_rl_io_AMO_read_rsp ||
	     WILL_FIRE_RL_rl_io_read_rsp ||
	     EN_req ||
	     WILL_FIRE_RL_rl_start_reset ||
	     WILL_FIRE_RL_rl_rereq ||
	     WILL_FIRE_RL_rl_start_cache_refill ||
	     WILL_FIRE_RL_rl_io_AMO_SC_req ||
	     WILL_FIRE_RL_rl_io_write_req ||
	     WILL_FIRE_RL_rl_io_read_req ||
	     WILL_FIRE_RL_rl_io_AMO_op_req ;

  // register rg_word64_set_in_cache
  assign rg_word64_set_in_cache$D_IN =
	     MUX_ram_word64_set$b_put_1__SEL_2 ?
	       MUX_ram_word64_set$b_put_2__VAL_2 :
	       MUX_ram_word64_set$b_put_2__VAL_4 ;
  assign rg_word64_set_in_cache$EN =
	     WILL_FIRE_RL_rl_cache_refill_rsps_loop &&
	     rg_word64_set_in_cache[2:0] != 3'd7 ||
	     WILL_FIRE_RL_rl_start_cache_refill ;

  // submodule f_reset_reqs
  assign f_reset_reqs$D_IN = !EN_server_reset_request_put ;
  assign f_reset_reqs$ENQ =
	     EN_server_reset_request_put || EN_server_flush_request_put ;
  assign f_reset_reqs$DEQ =
	     WILL_FIRE_RL_rl_reset && rg_cset_in_cache == 6'd63 ;
  assign f_reset_reqs$CLR = 1'b0 ;

  // submodule f_reset_rsps
  assign f_reset_rsps$D_IN = f_reset_reqs$D_OUT ;
  assign f_reset_rsps$ENQ =
	     WILL_FIRE_RL_rl_reset && rg_cset_in_cache == 6'd63 ;
  assign f_reset_rsps$DEQ =
	     EN_server_flush_response_get || EN_server_reset_response_get ;
  assign f_reset_rsps$CLR = 1'b0 ;

  // submodule ram_state_and_ctag_cset
  assign ram_state_and_ctag_cset$ADDRA =
	     WILL_FIRE_RL_rl_start_cache_refill ?
	       rg_addr[11:6] :
	       rg_cset_in_cache ;
  assign ram_state_and_ctag_cset$ADDRB =
	     MUX_ram_state_and_ctag_cset$b_put_1__SEL_1 ?
	       req_addr[11:6] :
	       rg_addr[11:6] ;
  assign ram_state_and_ctag_cset$DIA =
	     WILL_FIRE_RL_rl_start_cache_refill ?
	       MUX_ram_state_and_ctag_cset$a_put_3__VAL_1 :
	       53'h0AAAAAAAAAAAAA ;
  assign ram_state_and_ctag_cset$DIB =
	     MUX_ram_state_and_ctag_cset$b_put_1__SEL_1 ?
	       53'h0AAAAAAAAAAAAA /* unspecified value */  :
	       53'h0AAAAAAAAAAAAA /* unspecified value */  ;
  assign ram_state_and_ctag_cset$WEA = 1'd1 ;
  assign ram_state_and_ctag_cset$WEB = 1'd0 ;
  assign ram_state_and_ctag_cset$ENA =
	     WILL_FIRE_RL_rl_start_cache_refill || WILL_FIRE_RL_rl_reset ;
  assign ram_state_and_ctag_cset$ENB =
	     EN_req &&
	     req_f3_BITS_1_TO_0_90_EQ_0b0_91_OR_req_f3_BITS_ETC___d920 ||
	     WILL_FIRE_RL_rl_rereq ;

  // submodule ram_word64_set
  assign ram_word64_set$ADDRA =
	     MUX_ram_word64_set$a_put_1__SEL_1 ?
	       rg_word64_set_in_cache :
	       rg_addr[11:3] ;
  always@(MUX_ram_state_and_ctag_cset$b_put_1__SEL_1 or
	  req_addr or
	  MUX_ram_word64_set$b_put_1__SEL_2 or
	  MUX_ram_word64_set$b_put_2__VAL_2 or
	  WILL_FIRE_RL_rl_rereq or
	  rg_addr or
	  WILL_FIRE_RL_rl_start_cache_refill or
	  MUX_ram_word64_set$b_put_2__VAL_4)
  begin
    case (1'b1) // synopsys parallel_case
      MUX_ram_state_and_ctag_cset$b_put_1__SEL_1:
	  ram_word64_set$ADDRB = req_addr[11:3];
      MUX_ram_word64_set$b_put_1__SEL_2:
	  ram_word64_set$ADDRB = MUX_ram_word64_set$b_put_2__VAL_2;
      WILL_FIRE_RL_rl_rereq: ram_word64_set$ADDRB = rg_addr[11:3];
      WILL_FIRE_RL_rl_start_cache_refill:
	  ram_word64_set$ADDRB = MUX_ram_word64_set$b_put_2__VAL_4;
      default: ram_word64_set$ADDRB = 9'b010101010 /* unspecified value */ ;
    endcase
  end
  assign ram_word64_set$DIA =
	     MUX_ram_word64_set$a_put_1__SEL_1 ?
	       master_xactor_rg_rd_data[66:3] :
	       MUX_ram_word64_set$a_put_3__VAL_2 ;
  always@(MUX_ram_state_and_ctag_cset$b_put_1__SEL_1 or
	  MUX_ram_word64_set$b_put_1__SEL_2 or
	  WILL_FIRE_RL_rl_rereq or WILL_FIRE_RL_rl_start_cache_refill)
  begin
    case (1'b1) // synopsys parallel_case
      MUX_ram_state_and_ctag_cset$b_put_1__SEL_1:
	  ram_word64_set$DIB = 64'hAAAAAAAAAAAAAAAA /* unspecified value */ ;
      MUX_ram_word64_set$b_put_1__SEL_2:
	  ram_word64_set$DIB = 64'hAAAAAAAAAAAAAAAA /* unspecified value */ ;
      WILL_FIRE_RL_rl_rereq:
	  ram_word64_set$DIB = 64'hAAAAAAAAAAAAAAAA /* unspecified value */ ;
      WILL_FIRE_RL_rl_start_cache_refill:
	  ram_word64_set$DIB = 64'hAAAAAAAAAAAAAAAA /* unspecified value */ ;
      default: ram_word64_set$DIB =
		   64'hAAAAAAAAAAAAAAAA /* unspecified value */ ;
    endcase
  end
  assign ram_word64_set$WEA = 1'd1 ;
  assign ram_word64_set$WEB = 1'd0 ;
  assign ram_word64_set$ENA =
	     WILL_FIRE_RL_rl_cache_refill_rsps_loop &&
	     master_xactor_rg_rd_data[2:1] == 2'b0 ||
	     WILL_FIRE_RL_rl_probe_and_immed_rsp &&
	     NOT_dmem_not_imem_13_OR_soc_map_m_is_mem_addr__ETC___d309 ;
  assign ram_word64_set$ENB =
	     EN_req &&
	     req_f3_BITS_1_TO_0_90_EQ_0b0_91_OR_req_f3_BITS_ETC___d920 ||
	     WILL_FIRE_RL_rl_cache_refill_rsps_loop &&
	     rg_word64_set_in_cache[2:0] != 3'd7 ||
	     WILL_FIRE_RL_rl_rereq ||
	     WILL_FIRE_RL_rl_start_cache_refill ;

  // submodule soc_map
  assign soc_map$m_is_IO_addr_addr = 64'h0 ;
  assign soc_map$m_is_mem_addr_addr = rg_addr ;
  assign soc_map$m_is_near_mem_IO_addr_addr = 64'h0 ;

  // remaining internal signals
  assign IF_rg_addr_0_BITS_2_TO_0_6_EQ_0x0_40_THEN_1_EL_ETC___d271 =
	     (rg_addr[2:0] == 3'h0) ? 64'd1 : 64'd0 ;
  assign IF_rg_addr_0_BITS_2_TO_0_6_EQ_0x0_40_THEN_IF_r_ETC___d800 =
	     (rg_addr[2:0] == 3'h0) ? ld_val__h24158 : 64'd0 ;
  assign IF_rg_addr_0_BITS_2_TO_0_6_EQ_0x0_40_THEN_ram__ETC___d257 =
	     (rg_addr[2:0] == 3'h0) ? word64__h5281 : 64'd0 ;
  assign IF_rg_f3_38_EQ_0b10_44_THEN_SEXT_rg_st_amo_val_ETC___d366 =
	     (rg_f3 == 3'b010) ?
	       { {32{rg_st_amo_val_BITS_31_TO_0__q31[31]}},
		 rg_st_amo_val_BITS_31_TO_0__q31 } :
	       rg_st_amo_val ;
  assign IF_rg_op_4_EQ_0_5_OR_rg_op_4_EQ_2_6_AND_rg_amo_ETC___d110 =
	     (rg_op == 2'd0 ||
	      rg_op == 2'd2 && rg_amo_funct7[6:2] == 5'b00010) ?
	       5'd9 :
	       IF_rg_op_4_EQ_1_2_OR_rg_op_4_EQ_2_6_AND_rg_amo_ETC___d109 ;
  assign IF_rg_op_4_EQ_1_2_OR_rg_op_4_EQ_2_6_AND_rg_amo_ETC___d109 =
	     (rg_op == 2'd1 ||
	      rg_op == 2'd2 && rg_amo_funct7[6:2] == 5'b00011) ?
	       5'd12 :
	       ((!ram_state_and_ctag_cset$DOB[52] ||
		 !ram_state_and_ctag_cset_b_read__9_BITS_51_TO_0_ETC___d74) ?
		  5'd9 :
		  5'd12) ;
  assign IF_rg_op_4_EQ_1_2_OR_rg_op_4_EQ_2_6_AND_rg_amo_ETC___d466 =
	     (rg_op == 2'd1 ||
	      rg_op == 2'd2 && rg_amo_funct7[6:2] == 5'b00011) ?
	       mem_req_wr_data_wdata__h16835 :
	       mem_req_wr_data_wdata__h20332 ;
  assign IF_rg_op_4_EQ_1_2_OR_rg_op_4_EQ_2_6_AND_rg_amo_ETC___d78 =
	     (rg_op == 2'd1 ||
	      rg_op == 2'd2 && rg_amo_funct7[6:2] == 5'b00011) ?
	       rg_op_4_EQ_2_6_AND_rg_amo_funct7_7_BITS_6_TO_2_ETC___d68 :
	       !ram_state_and_ctag_cset$DOB[52] ||
	       !ram_state_and_ctag_cset_b_read__9_BITS_51_TO_0_ETC___d74 ||
	       !master_xactor_crg_wr_addr_full$port2__read &&
	       !master_xactor_crg_wr_data_full$port2__read ;
  assign NOT_cfg_verbosity_read__0_ULE_1_1___d12 = cfg_verbosity > 4'd1 ;
  assign NOT_cfg_verbosity_read__0_ULE_2_54___d555 = cfg_verbosity > 4'd2 ;
  assign NOT_dmem_not_imem_13_OR_soc_map_m_is_mem_addr__ETC___d298 =
	     (!dmem_not_imem || soc_map$m_is_mem_addr) && rg_op != 2'd0 &&
	     (rg_op != 2'd2 || rg_amo_funct7[6:2] != 5'b00010) &&
	     (rg_op == 2'd2 && rg_amo_funct7[6:2] == 5'b00011 ||
	      rg_op != 2'd1 && ram_state_and_ctag_cset$DOB[52] &&
	      ram_state_and_ctag_cset_b_read__9_BITS_51_TO_0_ETC___d74) ;
  assign NOT_dmem_not_imem_13_OR_soc_map_m_is_mem_addr__ETC___d309 =
	     (!dmem_not_imem || soc_map$m_is_mem_addr) && rg_op != 2'd0 &&
	     (rg_op != 2'd2 || rg_amo_funct7[6:2] != 5'b00010) &&
	     rg_op_4_EQ_1_2_OR_rg_op_4_EQ_2_6_AND_rg_amo_fu_ETC___d307 ;
  assign NOT_dmem_not_imem_13_OR_soc_map_m_is_mem_addr__ETC___d443 =
	     (!dmem_not_imem || soc_map$m_is_mem_addr) && rg_op != 2'd0 &&
	     (rg_op != 2'd2 || rg_amo_funct7[6:2] != 5'b00010) &&
	     rg_op_4_EQ_1_2_OR_rg_op_4_EQ_2_6_AND_rg_amo_fu_ETC___d441 ;
  assign NOT_dmem_not_imem_13_OR_soc_map_m_is_mem_addr__ETC___d479 =
	     (!dmem_not_imem || soc_map$m_is_mem_addr) && rg_op == 2'd1 &&
	     rg_addr_0_EQ_rg_lrsc_pa_8___d117 &&
	     NOT_cfg_verbosity_read__0_ULE_1_1___d12 ;
  assign NOT_dmem_not_imem_13_OR_soc_map_m_is_mem_addr__ETC___d491 =
	     (!dmem_not_imem || soc_map$m_is_mem_addr) && rg_op == 2'd2 &&
	     rg_amo_funct7[6:2] == 5'b00011 &&
	     NOT_cfg_verbosity_read__0_ULE_1_1___d12 ;
  assign NOT_dmem_not_imem_13_OR_soc_map_m_is_mem_addr__ETC___d519 =
	     (!dmem_not_imem || soc_map$m_is_mem_addr) && rg_op != 2'd0 &&
	     (rg_op != 2'd2 || rg_amo_funct7[6:2] != 5'b00010) &&
	     NOT_rg_op_4_EQ_1_2_25_AND_NOT_rg_op_4_EQ_2_6_3_ETC___d517 ;
  assign NOT_dmem_not_imem_13_OR_soc_map_m_is_mem_addr__ETC___d522 =
	     (!dmem_not_imem || soc_map$m_is_mem_addr) && rg_op != 2'd0 &&
	     (rg_op != 2'd2 || rg_amo_funct7[6:2] != 5'b00010) &&
	     NOT_rg_op_4_EQ_1_2_25_AND_NOT_rg_op_4_EQ_2_6_3_ETC___d520 ;
  assign NOT_dmem_not_imem_13_OR_soc_map_m_is_mem_addr__ETC___d526 =
	     (!dmem_not_imem || soc_map$m_is_mem_addr) && rg_op != 2'd0 &&
	     (rg_op != 2'd2 || rg_amo_funct7[6:2] != 5'b00010) &&
	     NOT_rg_op_4_EQ_1_2_25_AND_NOT_rg_op_4_EQ_2_6_3_ETC___d524 ;
  assign NOT_dmem_not_imem_13_OR_soc_map_m_is_mem_addr__ETC___d532 =
	     (!dmem_not_imem || soc_map$m_is_mem_addr) && rg_op != 2'd0 &&
	     (rg_op != 2'd2 || rg_amo_funct7[6:2] != 5'b00010) &&
	     NOT_rg_op_4_EQ_1_2_25_AND_NOT_rg_op_4_EQ_2_6_3_ETC___d530 ;
  assign NOT_dmem_not_imem_13_OR_soc_map_m_is_mem_addr__ETC___d534 =
	     (!dmem_not_imem || soc_map$m_is_mem_addr) && rg_op != 2'd0 &&
	     (rg_op != 2'd2 || rg_amo_funct7[6:2] != 5'b00010) &&
	     NOT_rg_op_4_EQ_1_2_25_AND_NOT_rg_op_4_EQ_2_6_3_ETC___d306 ;
  assign NOT_ram_state_and_ctag_cset_b_read__9_BIT_52_0_ETC___d119 =
	     (!ram_state_and_ctag_cset$DOB[52] ||
	      !ram_state_and_ctag_cset_b_read__9_BITS_51_TO_0_ETC___d74) &&
	     rg_op == 2'd2 &&
	     rg_amo_funct7[6:2] == 5'b00010 &&
	     rg_addr_0_EQ_rg_lrsc_pa_8___d117 ;
  assign NOT_req_f3_BITS_1_TO_0_90_EQ_0b0_91_92_AND_NOT_ETC___d911 =
	     req_f3[1:0] != 2'b0 && (req_f3[1:0] != 2'b01 || req_addr[0]) &&
	     (req_f3[1:0] != 2'b10 || req_addr[1:0] != 2'b0) &&
	     (req_f3[1:0] != 2'b11 || req_addr[2:0] != 3'b0) ;
  assign NOT_rg_op_4_EQ_0_5_2_AND_NOT_rg_op_4_EQ_2_6_3__ETC___d105 =
	     rg_op != 2'd0 &&
	     (rg_op != 2'd2 || rg_amo_funct7[6:2] != 5'b00010) &&
	     (rg_op != 2'd2 || rg_amo_funct7[6:2] != 5'b00011 ||
	      rg_lrsc_valid && rg_lrsc_pa_8_EQ_rg_addr_0___d59) ;
  assign NOT_rg_op_4_EQ_0_5_2_AND_NOT_rg_op_4_EQ_2_6_3__ETC___d446 =
	     rg_op != 2'd0 &&
	     (rg_op != 2'd2 || rg_amo_funct7[6:2] != 5'b00010) &&
	     (rg_op_4_EQ_1_2_OR_rg_op_4_EQ_2_6_AND_rg_amo_fu_ETC___d444 ||
	      NOT_rg_op_4_EQ_1_2_25_AND_NOT_rg_op_4_EQ_2_6_3_ETC___d306) ;
  assign NOT_rg_op_4_EQ_0_5_2_AND_NOT_rg_op_4_EQ_2_6_3__ETC___d494 =
	     (rg_op == 2'd1 ||
	      rg_op == 2'd2 && rg_amo_funct7[6:2] == 5'b00011) &&
	     NOT_rg_op_4_EQ_2_6_3_OR_NOT_rg_amo_funct7_7_BI_ETC___d492 ;
  assign NOT_rg_op_4_EQ_0_5_2_AND_NOT_rg_op_4_EQ_2_6_3__ETC___d502 =
	     (rg_op == 2'd1 ||
	      rg_op == 2'd2 && rg_amo_funct7[6:2] == 5'b00011) &&
	     NOT_rg_op_4_EQ_2_6_3_OR_NOT_rg_amo_funct7_7_BI_ETC___d500 ;
  assign NOT_rg_op_4_EQ_0_5_2_AND_NOT_rg_op_4_EQ_2_6_3__ETC___d507 =
	     (rg_op == 2'd1 ||
	      rg_op == 2'd2 && rg_amo_funct7[6:2] == 5'b00011) &&
	     NOT_rg_op_4_EQ_2_6_3_OR_NOT_rg_amo_funct7_7_BI_ETC___d505 ;
  assign NOT_rg_op_4_EQ_1_2_25_AND_NOT_rg_op_4_EQ_2_6_3_ETC___d128 =
	     rg_op != 2'd1 &&
	     (rg_op != 2'd2 || rg_amo_funct7[6:2] != 5'b00011) &&
	     ram_state_and_ctag_cset$DOB[52] &&
	     ram_state_and_ctag_cset_b_read__9_BITS_51_TO_0_ETC___d74 &&
	     rg_addr_0_EQ_rg_lrsc_pa_8___d117 ;
  assign NOT_rg_op_4_EQ_1_2_25_AND_NOT_rg_op_4_EQ_2_6_3_ETC___d306 =
	     rg_op != 2'd1 &&
	     (rg_op != 2'd2 || rg_amo_funct7[6:2] != 5'b00011) &&
	     ram_state_and_ctag_cset$DOB[52] &&
	     ram_state_and_ctag_cset_b_read__9_BITS_51_TO_0_ETC___d74 ;
  assign NOT_rg_op_4_EQ_1_2_25_AND_NOT_rg_op_4_EQ_2_6_3_ETC___d440 =
	     rg_op != 2'd1 &&
	     (rg_op != 2'd2 || rg_amo_funct7[6:2] != 5'b00011) &&
	     ram_state_and_ctag_cset$DOB[52] &&
	     ram_state_and_ctag_cset_b_read__9_BITS_51_TO_0_ETC___d74 &&
	     (rg_f3 == 3'b0 || rg_f3 == 3'b001) ;
  assign NOT_rg_op_4_EQ_1_2_25_AND_NOT_rg_op_4_EQ_2_6_3_ETC___d517 =
	     rg_op != 2'd1 &&
	     (rg_op != 2'd2 || rg_amo_funct7[6:2] != 5'b00011) &&
	     (!ram_state_and_ctag_cset$DOB[52] ||
	      !ram_state_and_ctag_cset_b_read__9_BITS_51_TO_0_ETC___d74) &&
	     NOT_cfg_verbosity_read__0_ULE_1_1___d12 ;
  assign NOT_rg_op_4_EQ_1_2_25_AND_NOT_rg_op_4_EQ_2_6_3_ETC___d520 =
	     rg_op != 2'd1 &&
	     (rg_op != 2'd2 || rg_amo_funct7[6:2] != 5'b00011) &&
	     ram_state_and_ctag_cset$DOB[52] &&
	     ram_state_and_ctag_cset_b_read__9_BITS_51_TO_0_ETC___d74 &&
	     NOT_cfg_verbosity_read__0_ULE_1_1___d12 ;
  assign NOT_rg_op_4_EQ_1_2_25_AND_NOT_rg_op_4_EQ_2_6_3_ETC___d524 =
	     rg_op != 2'd1 &&
	     (rg_op != 2'd2 || rg_amo_funct7[6:2] != 5'b00011) &&
	     ram_state_and_ctag_cset$DOB[52] &&
	     ram_state_and_ctag_cset_b_read__9_BITS_51_TO_0_ETC___d74 &&
	     ctr_wr_rsps_pending_crg == 4'd15 ;
  assign NOT_rg_op_4_EQ_1_2_25_AND_NOT_rg_op_4_EQ_2_6_3_ETC___d530 =
	     rg_op != 2'd1 &&
	     (rg_op != 2'd2 || rg_amo_funct7[6:2] != 5'b00011) &&
	     ram_state_and_ctag_cset$DOB[52] &&
	     ram_state_and_ctag_cset_b_read__9_BITS_51_TO_0_ETC___d74 &&
	     rg_addr_0_EQ_rg_lrsc_pa_8___d117 &&
	     NOT_cfg_verbosity_read__0_ULE_1_1___d12 ;
  assign NOT_rg_op_4_EQ_2_6_3_OR_NOT_rg_amo_funct7_7_BI_ETC___d304 =
	     (rg_op != 2'd2 || rg_amo_funct7[6:2] != 5'b00011 ||
	      rg_lrsc_valid && rg_lrsc_pa_8_EQ_rg_addr_0___d59) &&
	     ram_state_and_ctag_cset$DOB[52] &&
	     ram_state_and_ctag_cset_b_read__9_BITS_51_TO_0_ETC___d74 ;
  assign NOT_rg_op_4_EQ_2_6_3_OR_NOT_rg_amo_funct7_7_BI_ETC___d438 =
	     (rg_op != 2'd2 || rg_amo_funct7[6:2] != 5'b00011 ||
	      rg_lrsc_valid && rg_lrsc_pa_8_EQ_rg_addr_0___d59) &&
	     ram_state_and_ctag_cset$DOB[52] &&
	     ram_state_and_ctag_cset_b_read__9_BITS_51_TO_0_ETC___d74 &&
	     (rg_f3 == 3'b0 || rg_f3 == 3'b001) ;
  assign NOT_rg_op_4_EQ_2_6_3_OR_NOT_rg_amo_funct7_7_BI_ETC___d492 =
	     (rg_op != 2'd2 || rg_amo_funct7[6:2] != 5'b00011 ||
	      rg_lrsc_valid && rg_lrsc_pa_8_EQ_rg_addr_0___d59) &&
	     ram_state_and_ctag_cset$DOB[52] &&
	     ram_state_and_ctag_cset_b_read__9_BITS_51_TO_0_ETC___d74 &&
	     NOT_cfg_verbosity_read__0_ULE_1_1___d12 ;
  assign NOT_rg_op_4_EQ_2_6_3_OR_NOT_rg_amo_funct7_7_BI_ETC___d496 =
	     (rg_op != 2'd2 || rg_amo_funct7[6:2] != 5'b00011 ||
	      rg_lrsc_valid && rg_lrsc_pa_8_EQ_rg_addr_0___d59) &&
	     (!ram_state_and_ctag_cset$DOB[52] ||
	      !ram_state_and_ctag_cset_b_read__9_BITS_51_TO_0_ETC___d74) &&
	     NOT_cfg_verbosity_read__0_ULE_1_1___d12 ;
  assign NOT_rg_op_4_EQ_2_6_3_OR_NOT_rg_amo_funct7_7_BI_ETC___d500 =
	     (rg_op != 2'd2 || rg_amo_funct7[6:2] != 5'b00011 ||
	      rg_lrsc_valid && rg_lrsc_pa_8_EQ_rg_addr_0___d59) &&
	     NOT_cfg_verbosity_read__0_ULE_1_1___d12 ;
  assign NOT_rg_op_4_EQ_2_6_3_OR_NOT_rg_amo_funct7_7_BI_ETC___d505 =
	     (rg_op != 2'd2 || rg_amo_funct7[6:2] != 5'b00011 ||
	      rg_lrsc_valid && rg_lrsc_pa_8_EQ_rg_addr_0___d59) &&
	     ctr_wr_rsps_pending_crg == 4'd15 ;
  assign _theResult___snd_fst__h16843 = rg_st_amo_val << shift_bits__h20133 ;
  assign _theResult___snd_fst__h20340 =
	     new_st_val__h17351 << shift_bits__h20133 ;
  assign _theResult___snd_fst__h25769 = rg_st_amo_val << shift_bits__h27066 ;
  assign _theResult___snd_fst__h27273 = st_val__h27010 << shift_bits__h27066 ;
  assign access_exc_code__h2925 =
	     dmem_not_imem ?
	       ((rg_op == 2'd0 ||
		 rg_op == 2'd2 && rg_amo_funct7[6:2] == 5'b00010) ?
		  4'd5 :
		  4'd7) :
	       4'd1 ;
  assign b__h20935 =
	     ctr_wr_rsps_pending_crg$EN_port0__write ?
	       ctr_wr_rsps_pending_crg$port0__write_1 :
	       ctr_wr_rsps_pending_crg ;
  assign cline_fabric_addr__h21034 = { rg_pa[63:6], 6'd0 } ;
  assign dmem_not_imem_AND_NOT_soc_map_m_is_mem_addr_rg_ETC___d80 =
	     dmem_not_imem && !soc_map$m_is_mem_addr || rg_op == 2'd0 ||
	     rg_op == 2'd2 && rg_amo_funct7[6:2] == 5'b00010 ||
	     IF_rg_op_4_EQ_1_2_OR_rg_op_4_EQ_2_6_AND_rg_amo_ETC___d78 ;
  assign ld_val4158_BITS_15_TO_0__q36 = ld_val__h24158[15:0] ;
  assign ld_val4158_BITS_15_TO_8__q38 = ld_val__h24158[15:8] ;
  assign ld_val4158_BITS_23_TO_16__q39 = ld_val__h24158[23:16] ;
  assign ld_val4158_BITS_31_TO_0__q37 = ld_val__h24158[31:0] ;
  assign ld_val4158_BITS_31_TO_16__q40 = ld_val__h24158[31:16] ;
  assign ld_val4158_BITS_31_TO_24__q41 = ld_val__h24158[31:24] ;
  assign ld_val4158_BITS_39_TO_32__q42 = ld_val__h24158[39:32] ;
  assign ld_val4158_BITS_47_TO_32__q43 = ld_val__h24158[47:32] ;
  assign ld_val4158_BITS_47_TO_40__q45 = ld_val__h24158[47:40] ;
  assign ld_val4158_BITS_55_TO_48__q46 = ld_val__h24158[55:48] ;
  assign ld_val4158_BITS_63_TO_32__q44 = ld_val__h24158[63:32] ;
  assign ld_val4158_BITS_63_TO_48__q47 = ld_val__h24158[63:48] ;
  assign ld_val4158_BITS_63_TO_56__q48 = ld_val__h24158[63:56] ;
  assign ld_val4158_BITS_7_TO_0__q35 = ld_val__h24158[7:0] ;
  assign lrsc_result__h13131 =
	     !rg_lrsc_valid || !rg_lrsc_pa_8_EQ_rg_addr_0___d59 ;
  assign master_xactor_crg_rd_data_full_port1__read__51_ETC___d723 =
	     master_xactor_crg_rd_data_full$port1__read &&
	     (master_xactor_rg_rd_data[2:1] != 2'b0 ||
	      !master_xactor_crg_wr_addr_full$port2__read &&
	      !master_xactor_crg_wr_data_full$port2__read) ;
  assign master_xactor_rg_rd_data_BITS_10_TO_3__q1 =
	     master_xactor_rg_rd_data[10:3] ;
  assign master_xactor_rg_rd_data_BITS_18_TO_11__q4 =
	     master_xactor_rg_rd_data[18:11] ;
  assign master_xactor_rg_rd_data_BITS_18_TO_3__q2 =
	     master_xactor_rg_rd_data[18:3] ;
  assign master_xactor_rg_rd_data_BITS_26_TO_19__q5 =
	     master_xactor_rg_rd_data[26:19] ;
  assign master_xactor_rg_rd_data_BITS_34_TO_19__q6 =
	     master_xactor_rg_rd_data[34:19] ;
  assign master_xactor_rg_rd_data_BITS_34_TO_27__q7 =
	     master_xactor_rg_rd_data[34:27] ;
  assign master_xactor_rg_rd_data_BITS_34_TO_3__q3 =
	     master_xactor_rg_rd_data[34:3] ;
  assign master_xactor_rg_rd_data_BITS_42_TO_35__q8 =
	     master_xactor_rg_rd_data[42:35] ;
  assign master_xactor_rg_rd_data_BITS_50_TO_35__q9 =
	     master_xactor_rg_rd_data[50:35] ;
  assign master_xactor_rg_rd_data_BITS_50_TO_43__q11 =
	     master_xactor_rg_rd_data[50:43] ;
  assign master_xactor_rg_rd_data_BITS_58_TO_51__q12 =
	     master_xactor_rg_rd_data[58:51] ;
  assign master_xactor_rg_rd_data_BITS_66_TO_35__q10 =
	     master_xactor_rg_rd_data[66:35] ;
  assign master_xactor_rg_rd_data_BITS_66_TO_51__q13 =
	     master_xactor_rg_rd_data[66:51] ;
  assign master_xactor_rg_rd_data_BITS_66_TO_59__q14 =
	     master_xactor_rg_rd_data[66:59] ;
  assign new_st_val__h17351 =
	     (rg_f3 == 3'b010) ?
	       new_st_val__h17633 :
	       _theResult_____2__h17629 ;
  assign new_st_val__h17633 = { 32'd0, _theResult_____2__h17629[31:0] } ;
  assign new_st_val__h17724 =
	     IF_rg_f3_38_EQ_0b10_44_THEN_SEXT_IF_rg_f3_38_E_ETC___d302 +
	     IF_rg_f3_38_EQ_0b10_44_THEN_SEXT_rg_st_amo_val_ETC___d366 ;
  assign new_st_val__h18704 = w1__h17621 ^ w2__h27284 ;
  assign new_st_val__h18708 = w1__h17621 & w2__h27284 ;
  assign new_st_val__h18712 = w1__h17621 | w2__h27284 ;
  assign new_st_val__h18716 =
	     (w1__h17621 < w2__h27284) ? w1__h17621 : w2__h27284 ;
  assign new_st_val__h18721 =
	     (w1__h17621 <= w2__h27284) ? w2__h27284 : w1__h17621 ;
  assign new_st_val__h18727 =
	     ((IF_rg_f3_38_EQ_0b10_44_THEN_SEXT_IF_rg_f3_38_E_ETC___d302 ^
	       64'h8000000000000000) <
	      (IF_rg_f3_38_EQ_0b10_44_THEN_SEXT_rg_st_amo_val_ETC___d366 ^
	       64'h8000000000000000)) ?
	       w1__h17621 :
	       w2__h27284 ;
  assign new_st_val__h18732 =
	     ((IF_rg_f3_38_EQ_0b10_44_THEN_SEXT_IF_rg_f3_38_E_ETC___d302 ^
	       64'h8000000000000000) <=
	      (IF_rg_f3_38_EQ_0b10_44_THEN_SEXT_rg_st_amo_val_ETC___d366 ^
	       64'h8000000000000000)) ?
	       w2__h27284 :
	       w1__h17621 ;
  assign new_st_val__h27294 = { 32'd0, _theResult_____2__h27290[31:0] } ;
  assign new_st_val__h27385 =
	     new_ld_val__h26998 +
	     IF_rg_f3_38_EQ_0b10_44_THEN_SEXT_rg_st_amo_val_ETC___d366 ;
  assign new_st_val__h29245 = w1__h27282 ^ w2__h27284 ;
  assign new_st_val__h29249 = w1__h27282 & w2__h27284 ;
  assign new_st_val__h29253 = w1__h27282 | w2__h27284 ;
  assign new_st_val__h29257 =
	     (w1__h27282 < w2__h27284) ? w1__h27282 : w2__h27284 ;
  assign new_st_val__h29262 =
	     (w1__h27282 <= w2__h27284) ? w2__h27284 : w1__h27282 ;
  assign new_st_val__h29268 =
	     ((new_ld_val__h26998 ^ 64'h8000000000000000) <
	      (IF_rg_f3_38_EQ_0b10_44_THEN_SEXT_rg_st_amo_val_ETC___d366 ^
	       64'h8000000000000000)) ?
	       w1__h27282 :
	       w2__h27284 ;
  assign new_st_val__h29273 =
	     ((new_ld_val__h26998 ^ 64'h8000000000000000) <=
	      (IF_rg_f3_38_EQ_0b10_44_THEN_SEXT_rg_st_amo_val_ETC___d366 ^
	       64'h8000000000000000)) ?
	       w2__h27284 :
	       w1__h27282 ;
  assign new_value462_BITS_31_TO_0__q30 = new_value__h5462[31:0] ;
  assign ram_state_and_ctag_cset_b_read__9_BITS_51_TO_0_ETC___d74 =
	     ram_state_and_ctag_cset$DOB[51:0] == rg_addr[63:12] ;
  assign ram_state_and_ctag_cset_b_read__9_BIT_52_0_AND_ETC___d120 =
	     ram_state_and_ctag_cset$DOB[52] &&
	     ram_state_and_ctag_cset_b_read__9_BITS_51_TO_0_ETC___d74 &&
	     rg_op == 2'd2 &&
	     rg_amo_funct7[6:2] == 5'b00010 ||
	     NOT_ram_state_and_ctag_cset_b_read__9_BIT_52_0_ETC___d119 ;
  assign req_f3_BITS_1_TO_0_90_EQ_0b0_91_OR_req_f3_BITS_ETC___d920 =
	     req_f3[1:0] == 2'b0 || req_f3[1:0] == 2'b01 && !req_addr[0] ||
	     req_f3[1:0] == 2'b10 && req_addr[1:0] == 2'b0 ||
	     req_f3[1:0] == 2'b11 && req_addr[2:0] == 3'b0 ;
  assign result__h11871 =
	     { {56{word64281_BITS_15_TO_8__q18[7]}},
	       word64281_BITS_15_TO_8__q18 } ;
  assign result__h11899 =
	     { {56{word64281_BITS_23_TO_16__q19[7]}},
	       word64281_BITS_23_TO_16__q19 } ;
  assign result__h11927 =
	     { {56{word64281_BITS_31_TO_24__q21[7]}},
	       word64281_BITS_31_TO_24__q21 } ;
  assign result__h11955 =
	     { {56{word64281_BITS_39_TO_32__q22[7]}},
	       word64281_BITS_39_TO_32__q22 } ;
  assign result__h11983 =
	     { {56{word64281_BITS_47_TO_40__q25[7]}},
	       word64281_BITS_47_TO_40__q25 } ;
  assign result__h12011 =
	     { {56{word64281_BITS_55_TO_48__q26[7]}},
	       word64281_BITS_55_TO_48__q26 } ;
  assign result__h12039 =
	     { {56{word64281_BITS_63_TO_56__q28[7]}},
	       word64281_BITS_63_TO_56__q28 } ;
  assign result__h12084 = { 56'd0, word64__h5281[7:0] } ;
  assign result__h12112 = { 56'd0, word64__h5281[15:8] } ;
  assign result__h12140 = { 56'd0, word64__h5281[23:16] } ;
  assign result__h12168 = { 56'd0, word64__h5281[31:24] } ;
  assign result__h12196 = { 56'd0, word64__h5281[39:32] } ;
  assign result__h12224 = { 56'd0, word64__h5281[47:40] } ;
  assign result__h12252 = { 56'd0, word64__h5281[55:48] } ;
  assign result__h12280 = { 56'd0, word64__h5281[63:56] } ;
  assign result__h12325 =
	     { {48{word64281_BITS_15_TO_0__q16[15]}},
	       word64281_BITS_15_TO_0__q16 } ;
  assign result__h12353 =
	     { {48{word64281_BITS_31_TO_16__q20[15]}},
	       word64281_BITS_31_TO_16__q20 } ;
  assign result__h12381 =
	     { {48{word64281_BITS_47_TO_32__q23[15]}},
	       word64281_BITS_47_TO_32__q23 } ;
  assign result__h12409 =
	     { {48{word64281_BITS_63_TO_48__q27[15]}},
	       word64281_BITS_63_TO_48__q27 } ;
  assign result__h12450 = { 48'd0, word64__h5281[15:0] } ;
  assign result__h12478 = { 48'd0, word64__h5281[31:16] } ;
  assign result__h12506 = { 48'd0, word64__h5281[47:32] } ;
  assign result__h12534 = { 48'd0, word64__h5281[63:48] } ;
  assign result__h12575 =
	     { {32{word64281_BITS_31_TO_0__q17[31]}},
	       word64281_BITS_31_TO_0__q17 } ;
  assign result__h12603 =
	     { {32{word64281_BITS_63_TO_32__q24[31]}},
	       word64281_BITS_63_TO_32__q24 } ;
  assign result__h12642 = { 32'd0, word64__h5281[31:0] } ;
  assign result__h12670 = { 32'd0, word64__h5281[63:32] } ;
  assign result__h24218 =
	     { {56{master_xactor_rg_rd_data_BITS_10_TO_3__q1[7]}},
	       master_xactor_rg_rd_data_BITS_10_TO_3__q1 } ;
  assign result__h24248 =
	     { {56{master_xactor_rg_rd_data_BITS_18_TO_11__q4[7]}},
	       master_xactor_rg_rd_data_BITS_18_TO_11__q4 } ;
  assign result__h24275 =
	     { {56{master_xactor_rg_rd_data_BITS_26_TO_19__q5[7]}},
	       master_xactor_rg_rd_data_BITS_26_TO_19__q5 } ;
  assign result__h24302 =
	     { {56{master_xactor_rg_rd_data_BITS_34_TO_27__q7[7]}},
	       master_xactor_rg_rd_data_BITS_34_TO_27__q7 } ;
  assign result__h24329 =
	     { {56{master_xactor_rg_rd_data_BITS_42_TO_35__q8[7]}},
	       master_xactor_rg_rd_data_BITS_42_TO_35__q8 } ;
  assign result__h24356 =
	     { {56{master_xactor_rg_rd_data_BITS_50_TO_43__q11[7]}},
	       master_xactor_rg_rd_data_BITS_50_TO_43__q11 } ;
  assign result__h24383 =
	     { {56{master_xactor_rg_rd_data_BITS_58_TO_51__q12[7]}},
	       master_xactor_rg_rd_data_BITS_58_TO_51__q12 } ;
  assign result__h24410 =
	     { {56{master_xactor_rg_rd_data_BITS_66_TO_59__q14[7]}},
	       master_xactor_rg_rd_data_BITS_66_TO_59__q14 } ;
  assign result__h24454 = { 56'd0, master_xactor_rg_rd_data[10:3] } ;
  assign result__h24481 = { 56'd0, master_xactor_rg_rd_data[18:11] } ;
  assign result__h24508 = { 56'd0, master_xactor_rg_rd_data[26:19] } ;
  assign result__h24535 = { 56'd0, master_xactor_rg_rd_data[34:27] } ;
  assign result__h24562 = { 56'd0, master_xactor_rg_rd_data[42:35] } ;
  assign result__h24589 = { 56'd0, master_xactor_rg_rd_data[50:43] } ;
  assign result__h24616 = { 56'd0, master_xactor_rg_rd_data[58:51] } ;
  assign result__h24643 = { 56'd0, master_xactor_rg_rd_data[66:59] } ;
  assign result__h24687 =
	     { {48{master_xactor_rg_rd_data_BITS_18_TO_3__q2[15]}},
	       master_xactor_rg_rd_data_BITS_18_TO_3__q2 } ;
  assign result__h24714 =
	     { {48{master_xactor_rg_rd_data_BITS_34_TO_19__q6[15]}},
	       master_xactor_rg_rd_data_BITS_34_TO_19__q6 } ;
  assign result__h24741 =
	     { {48{master_xactor_rg_rd_data_BITS_50_TO_35__q9[15]}},
	       master_xactor_rg_rd_data_BITS_50_TO_35__q9 } ;
  assign result__h24768 =
	     { {48{master_xactor_rg_rd_data_BITS_66_TO_51__q13[15]}},
	       master_xactor_rg_rd_data_BITS_66_TO_51__q13 } ;
  assign result__h24808 = { 48'd0, master_xactor_rg_rd_data[18:3] } ;
  assign result__h24835 = { 48'd0, master_xactor_rg_rd_data[34:19] } ;
  assign result__h24862 = { 48'd0, master_xactor_rg_rd_data[50:35] } ;
  assign result__h24889 = { 48'd0, master_xactor_rg_rd_data[66:51] } ;
  assign result__h24929 =
	     { {32{master_xactor_rg_rd_data_BITS_34_TO_3__q3[31]}},
	       master_xactor_rg_rd_data_BITS_34_TO_3__q3 } ;
  assign result__h24956 =
	     { {32{master_xactor_rg_rd_data_BITS_66_TO_35__q10[31]}},
	       master_xactor_rg_rd_data_BITS_66_TO_35__q10 } ;
  assign result__h24994 = { 32'd0, master_xactor_rg_rd_data[34:3] } ;
  assign result__h25021 = { 32'd0, master_xactor_rg_rd_data[66:35] } ;
  assign result__h27473 =
	     { {56{ld_val4158_BITS_7_TO_0__q35[7]}},
	       ld_val4158_BITS_7_TO_0__q35 } ;
  assign result__h28381 =
	     { {56{ld_val4158_BITS_15_TO_8__q38[7]}},
	       ld_val4158_BITS_15_TO_8__q38 } ;
  assign result__h28409 =
	     { {56{ld_val4158_BITS_23_TO_16__q39[7]}},
	       ld_val4158_BITS_23_TO_16__q39 } ;
  assign result__h28437 =
	     { {56{ld_val4158_BITS_31_TO_24__q41[7]}},
	       ld_val4158_BITS_31_TO_24__q41 } ;
  assign result__h28465 =
	     { {56{ld_val4158_BITS_39_TO_32__q42[7]}},
	       ld_val4158_BITS_39_TO_32__q42 } ;
  assign result__h28493 =
	     { {56{ld_val4158_BITS_47_TO_40__q45[7]}},
	       ld_val4158_BITS_47_TO_40__q45 } ;
  assign result__h28521 =
	     { {56{ld_val4158_BITS_55_TO_48__q46[7]}},
	       ld_val4158_BITS_55_TO_48__q46 } ;
  assign result__h28549 =
	     { {56{ld_val4158_BITS_63_TO_56__q48[7]}},
	       ld_val4158_BITS_63_TO_56__q48 } ;
  assign result__h28594 = { 56'd0, ld_val__h24158[7:0] } ;
  assign result__h28622 = { 56'd0, ld_val__h24158[15:8] } ;
  assign result__h28650 = { 56'd0, ld_val__h24158[23:16] } ;
  assign result__h28678 = { 56'd0, ld_val__h24158[31:24] } ;
  assign result__h28706 = { 56'd0, ld_val__h24158[39:32] } ;
  assign result__h28734 = { 56'd0, ld_val__h24158[47:40] } ;
  assign result__h28762 = { 56'd0, ld_val__h24158[55:48] } ;
  assign result__h28790 = { 56'd0, ld_val__h24158[63:56] } ;
  assign result__h28835 =
	     { {48{ld_val4158_BITS_15_TO_0__q36[15]}},
	       ld_val4158_BITS_15_TO_0__q36 } ;
  assign result__h28863 =
	     { {48{ld_val4158_BITS_31_TO_16__q40[15]}},
	       ld_val4158_BITS_31_TO_16__q40 } ;
  assign result__h28891 =
	     { {48{ld_val4158_BITS_47_TO_32__q43[15]}},
	       ld_val4158_BITS_47_TO_32__q43 } ;
  assign result__h28919 =
	     { {48{ld_val4158_BITS_63_TO_48__q47[15]}},
	       ld_val4158_BITS_63_TO_48__q47 } ;
  assign result__h28960 = { 48'd0, ld_val__h24158[15:0] } ;
  assign result__h28988 = { 48'd0, ld_val__h24158[31:16] } ;
  assign result__h29016 = { 48'd0, ld_val__h24158[47:32] } ;
  assign result__h29044 = { 48'd0, ld_val__h24158[63:48] } ;
  assign result__h29085 =
	     { {32{ld_val4158_BITS_31_TO_0__q37[31]}},
	       ld_val4158_BITS_31_TO_0__q37 } ;
  assign result__h29113 =
	     { {32{ld_val4158_BITS_63_TO_32__q44[31]}},
	       ld_val4158_BITS_63_TO_32__q44 } ;
  assign result__h29152 = { 32'd0, ld_val__h24158[31:0] } ;
  assign result__h29180 = { 32'd0, ld_val__h24158[63:32] } ;
  assign result__h5515 =
	     { {56{word64281_BITS_7_TO_0__q15[7]}},
	       word64281_BITS_7_TO_0__q15 } ;
  assign rg_addr_0_EQ_rg_lrsc_pa_8___d117 = rg_addr == rg_lrsc_pa ;
  assign rg_amo_funct7_7_BITS_6_TO_2_8_EQ_0b10_9_AND_NO_ETC___d292 =
	     rg_amo_funct7[6:2] == 5'b00010 &&
	     (!ram_state_and_ctag_cset$DOB[52] ||
	      !ram_state_and_ctag_cset_b_read__9_BITS_51_TO_0_ETC___d74) &&
	     rg_addr_0_EQ_rg_lrsc_pa_8___d117 &&
	     NOT_cfg_verbosity_read__0_ULE_1_1___d12 ;
  assign rg_lrsc_pa_8_EQ_rg_addr_0___d59 = rg_lrsc_pa == rg_addr ;
  assign rg_op_4_EQ_0_5_OR_rg_op_4_EQ_2_6_AND_rg_amo_fu_ETC___d100 =
	     (rg_op == 2'd0 ||
	      rg_op == 2'd2 && rg_amo_funct7[6:2] == 5'b00010) &&
	     (!ram_state_and_ctag_cset$DOB[52] ||
	      !ram_state_and_ctag_cset_b_read__9_BITS_51_TO_0_ETC___d74) ;
  assign rg_op_4_EQ_0_5_OR_rg_op_4_EQ_2_6_AND_rg_amo_fu_ETC___d131 =
	     (rg_op == 2'd0 ||
	      rg_op == 2'd2 && rg_amo_funct7[6:2] == 5'b00010) &&
	     ram_state_and_ctag_cset_b_read__9_BIT_52_0_AND_ETC___d120 ||
	     rg_op != 2'd0 &&
	     (rg_op != 2'd2 || rg_amo_funct7[6:2] != 5'b00010) &&
	     rg_op_4_EQ_1_2_OR_rg_op_4_EQ_2_6_AND_rg_amo_fu_ETC___d129 ;
  assign rg_op_4_EQ_0_5_OR_rg_op_4_EQ_2_6_AND_rg_amo_fu_ETC___d133 =
	     (rg_op == 2'd0 ||
	      rg_op == 2'd2 && rg_amo_funct7[6:2] == 5'b00010) &&
	     ram_state_and_ctag_cset$DOB[52] &&
	     ram_state_and_ctag_cset_b_read__9_BITS_51_TO_0_ETC___d74 ;
  assign rg_op_4_EQ_0_5_OR_rg_op_4_EQ_2_6_AND_rg_amo_fu_ETC___d136 =
	     rg_op_4_EQ_0_5_OR_rg_op_4_EQ_2_6_AND_rg_amo_fu_ETC___d133 ||
	     rg_op == 2'd2 && rg_amo_funct7[6:2] == 5'b00011 &&
	     lrsc_result__h13131 ;
  assign rg_op_4_EQ_0_5_OR_rg_op_4_EQ_2_6_AND_rg_amo_fu_ETC___d275 =
	     (rg_op == 2'd0 ||
	      rg_op == 2'd2 && rg_amo_funct7[6:2] == 5'b00010) &&
	     ram_state_and_ctag_cset$DOB[52] &&
	     ram_state_and_ctag_cset_b_read__9_BITS_51_TO_0_ETC___d74 &&
	     NOT_cfg_verbosity_read__0_ULE_1_1___d12 ;
  assign rg_op_4_EQ_0_5_OR_rg_op_4_EQ_2_6_AND_rg_amo_fu_ETC___d288 =
	     (rg_op == 2'd0 ||
	      rg_op == 2'd2 && rg_amo_funct7[6:2] == 5'b00010) &&
	     (!ram_state_and_ctag_cset$DOB[52] ||
	      !ram_state_and_ctag_cset_b_read__9_BITS_51_TO_0_ETC___d74) &&
	     NOT_cfg_verbosity_read__0_ULE_1_1___d12 ;
  assign rg_op_4_EQ_1_2_OR_rg_op_4_EQ_2_6_AND_rg_amo_fu_ETC___d129 =
	     rg_op == 2'd1 && rg_addr_0_EQ_rg_lrsc_pa_8___d117 ||
	     rg_op == 2'd2 && rg_amo_funct7[6:2] == 5'b00011 ||
	     NOT_rg_op_4_EQ_1_2_25_AND_NOT_rg_op_4_EQ_2_6_3_ETC___d128 ;
  assign rg_op_4_EQ_1_2_OR_rg_op_4_EQ_2_6_AND_rg_amo_fu_ETC___d307 =
	     (rg_op == 2'd1 ||
	      rg_op == 2'd2 && rg_amo_funct7[6:2] == 5'b00011) &&
	     NOT_rg_op_4_EQ_2_6_3_OR_NOT_rg_amo_funct7_7_BI_ETC___d304 ||
	     NOT_rg_op_4_EQ_1_2_25_AND_NOT_rg_op_4_EQ_2_6_3_ETC___d306 ;
  assign rg_op_4_EQ_1_2_OR_rg_op_4_EQ_2_6_AND_rg_amo_fu_ETC___d441 =
	     (rg_op == 2'd1 ||
	      rg_op == 2'd2 && rg_amo_funct7[6:2] == 5'b00011) &&
	     NOT_rg_op_4_EQ_2_6_3_OR_NOT_rg_amo_funct7_7_BI_ETC___d438 ||
	     NOT_rg_op_4_EQ_1_2_25_AND_NOT_rg_op_4_EQ_2_6_3_ETC___d440 ;
  assign rg_op_4_EQ_1_2_OR_rg_op_4_EQ_2_6_AND_rg_amo_fu_ETC___d444 =
	     (rg_op == 2'd1 ||
	      rg_op == 2'd2 && rg_amo_funct7[6:2] == 5'b00011) &&
	     (rg_op != 2'd2 || rg_amo_funct7[6:2] != 5'b00011 ||
	      rg_lrsc_valid && rg_lrsc_pa_8_EQ_rg_addr_0___d59) ;
  assign rg_op_4_EQ_2_6_AND_rg_amo_funct7_7_BITS_6_TO_2_ETC___d513 =
	     rg_op == 2'd2 && rg_amo_funct7[6:2] == 5'b00011 &&
	     lrsc_result__h13131 &&
	     NOT_cfg_verbosity_read__0_ULE_1_1___d12 ;
  assign rg_op_4_EQ_2_6_AND_rg_amo_funct7_7_BITS_6_TO_2_ETC___d68 =
	     rg_op == 2'd2 && rg_amo_funct7[6:2] == 5'b00011 &&
	     lrsc_result__h13131 ||
	     !master_xactor_crg_wr_addr_full$port2__read &&
	     !master_xactor_crg_wr_data_full$port2__read ;
  assign rg_st_amo_val_BITS_31_TO_0__q31 = rg_st_amo_val[31:0] ;
  assign rg_state_EQ_13_90_AND_rg_op_4_EQ_0_5_OR_rg_op__ETC___d592 =
	     rg_state == 5'd13 &&
	     (rg_op == 2'd0 ||
	      rg_op == 2'd2 && rg_amo_funct7[6:2] == 5'b00010) &&
	     b__h20935 == 4'd0 ;
  assign rg_state_EQ_3_1_AND_NOT_rg_op_4_EQ_0_5_2_AND_N_ETC___d90 =
	     rg_state == 5'd3 &&
	     (rg_op != 2'd0 &&
	      (rg_op != 2'd2 || rg_amo_funct7[6:2] != 5'b00010) ||
	      crg_sb_to_load_delay$port0__write_1 == 11'd0) ;
  assign shift_bits__h20133 = { rg_addr[2:0], 3'b0 } ;
  assign shift_bits__h27066 = { rg_pa[2:0], 3'b0 } ;
  assign st_val__h27010 =
	     (rg_f3 == 3'b010) ?
	       new_st_val__h27294 :
	       _theResult_____2__h27290 ;
  assign strobe64__h20266 = 8'b00000001 << rg_addr[2:0] ;
  assign strobe64__h20268 = 8'b00000011 << rg_addr[2:0] ;
  assign strobe64__h20270 = 8'b00001111 << rg_addr[2:0] ;
  assign strobe64__h27199 = 8'b00000001 << rg_pa[2:0] ;
  assign strobe64__h27201 = 8'b00000011 << rg_pa[2:0] ;
  assign strobe64__h27203 = 8'b00001111 << rg_pa[2:0] ;
  assign w17278_BITS_31_TO_0__q50 = w1__h27278[31:0] ;
  assign w1___1__h17692 = { 32'd0, new_value__h5462[31:0] } ;
  assign w1___1__h27353 = { 32'd0, w1__h27278[31:0] } ;
  assign w2___1__h27354 = { 32'd0, rg_st_amo_val[31:0] } ;
  assign w2__h27284 = (rg_f3 == 3'b010) ? w2___1__h27354 : rg_st_amo_val ;
  assign word64281_BITS_15_TO_0__q16 = word64__h5281[15:0] ;
  assign word64281_BITS_15_TO_8__q18 = word64__h5281[15:8] ;
  assign word64281_BITS_23_TO_16__q19 = word64__h5281[23:16] ;
  assign word64281_BITS_31_TO_0__q17 = word64__h5281[31:0] ;
  assign word64281_BITS_31_TO_16__q20 = word64__h5281[31:16] ;
  assign word64281_BITS_31_TO_24__q21 = word64__h5281[31:24] ;
  assign word64281_BITS_39_TO_32__q22 = word64__h5281[39:32] ;
  assign word64281_BITS_47_TO_32__q23 = word64__h5281[47:32] ;
  assign word64281_BITS_47_TO_40__q25 = word64__h5281[47:40] ;
  assign word64281_BITS_55_TO_48__q26 = word64__h5281[55:48] ;
  assign word64281_BITS_63_TO_32__q24 = word64__h5281[63:32] ;
  assign word64281_BITS_63_TO_48__q27 = word64__h5281[63:48] ;
  assign word64281_BITS_63_TO_56__q28 = word64__h5281[63:56] ;
  assign word64281_BITS_7_TO_0__q15 = word64__h5281[7:0] ;
  assign word64__h5281 = ram_word64_set$DOB & y__h5551 ;
  assign x__h13141 = { 63'd0, lrsc_result__h13131 } ;
  assign y__h5551 =
	     {64{ram_state_and_ctag_cset$DOB[52] &&
		 ram_state_and_ctag_cset_b_read__9_BITS_51_TO_0_ETC___d74}} ;
  always@(rg_f3)
  begin
    case (rg_f3[1:0])
      2'b0: value__h26583 = 3'b0;
      2'b01: value__h26583 = 3'b001;
      2'b10: value__h26583 = 3'b010;
      2'd3: value__h26583 = 3'b011;
    endcase
  end
  always@(rg_f3)
  begin
    case (rg_f3[1:0])
      2'b0: value__h29609 = 3'b0;
      2'b01: value__h29609 = 3'b001;
      2'b10: value__h29609 = 3'b010;
      2'b11: value__h29609 = 3'b011;
    endcase
  end
  always@(rg_f3 or strobe64__h20266 or strobe64__h20268 or strobe64__h20270)
  begin
    case (rg_f3[1:0])
      2'b0: mem_req_wr_data_wstrb__h20333 = strobe64__h20266;
      2'b01: mem_req_wr_data_wstrb__h20333 = strobe64__h20268;
      2'b10: mem_req_wr_data_wstrb__h20333 = strobe64__h20270;
      2'b11: mem_req_wr_data_wstrb__h20333 = 8'b11111111;
    endcase
  end
  always@(rg_f3 or strobe64__h27199 or strobe64__h27201 or strobe64__h27203)
  begin
    case (rg_f3[1:0])
      2'b0: mem_req_wr_data_wstrb__h27266 = strobe64__h27199;
      2'b01: mem_req_wr_data_wstrb__h27266 = strobe64__h27201;
      2'b10: mem_req_wr_data_wstrb__h27266 = strobe64__h27203;
      2'b11: mem_req_wr_data_wstrb__h27266 = 8'b11111111;
    endcase
  end
  always@(rg_f3 or rg_st_amo_val or _theResult___snd_fst__h16843)
  begin
    case (rg_f3[1:0])
      2'b0, 2'b01, 2'b10:
	  mem_req_wr_data_wdata__h16835 = _theResult___snd_fst__h16843;
      2'd3: mem_req_wr_data_wdata__h16835 = rg_st_amo_val;
    endcase
  end
  always@(rg_f3 or rg_st_amo_val or _theResult___snd_fst__h25769)
  begin
    case (rg_f3[1:0])
      2'b0, 2'b01, 2'b10:
	  mem_req_wr_data_wdata__h25761 = _theResult___snd_fst__h25769;
      2'd3: mem_req_wr_data_wdata__h25761 = rg_st_amo_val;
    endcase
  end
  always@(rg_addr or
	  result__h5515 or
	  result__h11871 or
	  result__h11899 or
	  result__h11927 or
	  result__h11955 or
	  result__h11983 or result__h12011 or result__h12039)
  begin
    case (rg_addr[2:0])
      3'h0:
	  IF_rg_addr_0_BITS_2_TO_0_6_EQ_0x0_40_THEN_SEXT_ETC___d204 =
	      result__h5515;
      3'h1:
	  IF_rg_addr_0_BITS_2_TO_0_6_EQ_0x0_40_THEN_SEXT_ETC___d204 =
	      result__h11871;
      3'h2:
	  IF_rg_addr_0_BITS_2_TO_0_6_EQ_0x0_40_THEN_SEXT_ETC___d204 =
	      result__h11899;
      3'h3:
	  IF_rg_addr_0_BITS_2_TO_0_6_EQ_0x0_40_THEN_SEXT_ETC___d204 =
	      result__h11927;
      3'h4:
	  IF_rg_addr_0_BITS_2_TO_0_6_EQ_0x0_40_THEN_SEXT_ETC___d204 =
	      result__h11955;
      3'h5:
	  IF_rg_addr_0_BITS_2_TO_0_6_EQ_0x0_40_THEN_SEXT_ETC___d204 =
	      result__h11983;
      3'h6:
	  IF_rg_addr_0_BITS_2_TO_0_6_EQ_0x0_40_THEN_SEXT_ETC___d204 =
	      result__h12011;
      3'h7:
	  IF_rg_addr_0_BITS_2_TO_0_6_EQ_0x0_40_THEN_SEXT_ETC___d204 =
	      result__h12039;
    endcase
  end
  always@(rg_addr or
	  result__h12084 or
	  result__h12112 or
	  result__h12140 or
	  result__h12168 or
	  result__h12196 or
	  result__h12224 or result__h12252 or result__h12280)
  begin
    case (rg_addr[2:0])
      3'h0:
	  IF_rg_addr_0_BITS_2_TO_0_6_EQ_0x0_40_THEN_0_CO_ETC___d221 =
	      result__h12084;
      3'h1:
	  IF_rg_addr_0_BITS_2_TO_0_6_EQ_0x0_40_THEN_0_CO_ETC___d221 =
	      result__h12112;
      3'h2:
	  IF_rg_addr_0_BITS_2_TO_0_6_EQ_0x0_40_THEN_0_CO_ETC___d221 =
	      result__h12140;
      3'h3:
	  IF_rg_addr_0_BITS_2_TO_0_6_EQ_0x0_40_THEN_0_CO_ETC___d221 =
	      result__h12168;
      3'h4:
	  IF_rg_addr_0_BITS_2_TO_0_6_EQ_0x0_40_THEN_0_CO_ETC___d221 =
	      result__h12196;
      3'h5:
	  IF_rg_addr_0_BITS_2_TO_0_6_EQ_0x0_40_THEN_0_CO_ETC___d221 =
	      result__h12224;
      3'h6:
	  IF_rg_addr_0_BITS_2_TO_0_6_EQ_0x0_40_THEN_0_CO_ETC___d221 =
	      result__h12252;
      3'h7:
	  IF_rg_addr_0_BITS_2_TO_0_6_EQ_0x0_40_THEN_0_CO_ETC___d221 =
	      result__h12280;
    endcase
  end
  always@(rg_addr or
	  result__h12450 or
	  result__h12478 or result__h12506 or result__h12534)
  begin
    case (rg_addr[2:0])
      3'h0:
	  IF_rg_addr_0_BITS_2_TO_0_6_EQ_0x0_40_THEN_0_CO_ETC___d243 =
	      result__h12450;
      3'h2:
	  IF_rg_addr_0_BITS_2_TO_0_6_EQ_0x0_40_THEN_0_CO_ETC___d243 =
	      result__h12478;
      3'h4:
	  IF_rg_addr_0_BITS_2_TO_0_6_EQ_0x0_40_THEN_0_CO_ETC___d243 =
	      result__h12506;
      3'h6:
	  IF_rg_addr_0_BITS_2_TO_0_6_EQ_0x0_40_THEN_0_CO_ETC___d243 =
	      result__h12534;
      default: IF_rg_addr_0_BITS_2_TO_0_6_EQ_0x0_40_THEN_0_CO_ETC___d243 =
		   64'd0;
    endcase
  end
  always@(rg_addr or
	  result__h12325 or
	  result__h12353 or result__h12381 or result__h12409)
  begin
    case (rg_addr[2:0])
      3'h0:
	  IF_rg_addr_0_BITS_2_TO_0_6_EQ_0x0_40_THEN_SEXT_ETC___d234 =
	      result__h12325;
      3'h2:
	  IF_rg_addr_0_BITS_2_TO_0_6_EQ_0x0_40_THEN_SEXT_ETC___d234 =
	      result__h12353;
      3'h4:
	  IF_rg_addr_0_BITS_2_TO_0_6_EQ_0x0_40_THEN_SEXT_ETC___d234 =
	      result__h12381;
      3'h6:
	  IF_rg_addr_0_BITS_2_TO_0_6_EQ_0x0_40_THEN_SEXT_ETC___d234 =
	      result__h12409;
      default: IF_rg_addr_0_BITS_2_TO_0_6_EQ_0x0_40_THEN_SEXT_ETC___d234 =
		   64'd0;
    endcase
  end
  always@(rg_addr or result__h12642 or result__h12670)
  begin
    case (rg_addr[2:0])
      3'h0:
	  IF_rg_addr_0_BITS_2_TO_0_6_EQ_0x0_40_THEN_0_CO_ETC___d255 =
	      result__h12642;
      3'h4:
	  IF_rg_addr_0_BITS_2_TO_0_6_EQ_0x0_40_THEN_0_CO_ETC___d255 =
	      result__h12670;
      default: IF_rg_addr_0_BITS_2_TO_0_6_EQ_0x0_40_THEN_0_CO_ETC___d255 =
		   64'd0;
    endcase
  end
  always@(rg_addr or result__h12575 or result__h12603)
  begin
    case (rg_addr[2:0])
      3'h0:
	  CASE_rg_addr_BITS_2_TO_0_0x0_result2575_0x4_re_ETC__q29 =
	      result__h12575;
      3'h4:
	  CASE_rg_addr_BITS_2_TO_0_0x0_result2575_0x4_re_ETC__q29 =
	      result__h12603;
      default: CASE_rg_addr_BITS_2_TO_0_0x0_result2575_0x4_re_ETC__q29 =
		   64'd0;
    endcase
  end
  always@(rg_f3 or
	  IF_rg_addr_0_BITS_2_TO_0_6_EQ_0x0_40_THEN_SEXT_ETC___d204 or
	  IF_rg_addr_0_BITS_2_TO_0_6_EQ_0x0_40_THEN_SEXT_ETC___d234 or
	  CASE_rg_addr_BITS_2_TO_0_0x0_result2575_0x4_re_ETC__q29 or
	  IF_rg_addr_0_BITS_2_TO_0_6_EQ_0x0_40_THEN_ram__ETC___d257 or
	  IF_rg_addr_0_BITS_2_TO_0_6_EQ_0x0_40_THEN_0_CO_ETC___d221 or
	  IF_rg_addr_0_BITS_2_TO_0_6_EQ_0x0_40_THEN_0_CO_ETC___d243 or
	  IF_rg_addr_0_BITS_2_TO_0_6_EQ_0x0_40_THEN_0_CO_ETC___d255)
  begin
    case (rg_f3)
      3'b0:
	  new_value__h5462 =
	      IF_rg_addr_0_BITS_2_TO_0_6_EQ_0x0_40_THEN_SEXT_ETC___d204;
      3'b001:
	  new_value__h5462 =
	      IF_rg_addr_0_BITS_2_TO_0_6_EQ_0x0_40_THEN_SEXT_ETC___d234;
      3'b010:
	  new_value__h5462 =
	      CASE_rg_addr_BITS_2_TO_0_0x0_result2575_0x4_re_ETC__q29;
      3'b011:
	  new_value__h5462 =
	      IF_rg_addr_0_BITS_2_TO_0_6_EQ_0x0_40_THEN_ram__ETC___d257;
      3'b100:
	  new_value__h5462 =
	      IF_rg_addr_0_BITS_2_TO_0_6_EQ_0x0_40_THEN_0_CO_ETC___d221;
      3'b101:
	  new_value__h5462 =
	      IF_rg_addr_0_BITS_2_TO_0_6_EQ_0x0_40_THEN_0_CO_ETC___d243;
      3'b110:
	  new_value__h5462 =
	      IF_rg_addr_0_BITS_2_TO_0_6_EQ_0x0_40_THEN_0_CO_ETC___d255;
      3'd7: new_value__h5462 = 64'd0;
    endcase
  end
  always@(rg_f3 or
	  IF_rg_addr_0_BITS_2_TO_0_6_EQ_0x0_40_THEN_SEXT_ETC___d204 or
	  IF_rg_addr_0_BITS_2_TO_0_6_EQ_0x0_40_THEN_SEXT_ETC___d234 or
	  w1___1__h17692 or
	  IF_rg_addr_0_BITS_2_TO_0_6_EQ_0x0_40_THEN_ram__ETC___d257 or
	  IF_rg_addr_0_BITS_2_TO_0_6_EQ_0x0_40_THEN_0_CO_ETC___d221 or
	  IF_rg_addr_0_BITS_2_TO_0_6_EQ_0x0_40_THEN_0_CO_ETC___d243 or
	  IF_rg_addr_0_BITS_2_TO_0_6_EQ_0x0_40_THEN_0_CO_ETC___d255)
  begin
    case (rg_f3)
      3'b0:
	  w1__h17621 =
	      IF_rg_addr_0_BITS_2_TO_0_6_EQ_0x0_40_THEN_SEXT_ETC___d204;
      3'b001:
	  w1__h17621 =
	      IF_rg_addr_0_BITS_2_TO_0_6_EQ_0x0_40_THEN_SEXT_ETC___d234;
      3'b010: w1__h17621 = w1___1__h17692;
      3'b011:
	  w1__h17621 =
	      IF_rg_addr_0_BITS_2_TO_0_6_EQ_0x0_40_THEN_ram__ETC___d257;
      3'b100:
	  w1__h17621 =
	      IF_rg_addr_0_BITS_2_TO_0_6_EQ_0x0_40_THEN_0_CO_ETC___d221;
      3'b101:
	  w1__h17621 =
	      IF_rg_addr_0_BITS_2_TO_0_6_EQ_0x0_40_THEN_0_CO_ETC___d243;
      3'b110:
	  w1__h17621 =
	      IF_rg_addr_0_BITS_2_TO_0_6_EQ_0x0_40_THEN_0_CO_ETC___d255;
      3'd7: w1__h17621 = 64'd0;
    endcase
  end
  always@(rg_addr or ram_word64_set$DOB or rg_st_amo_val)
  begin
    case (rg_addr[2:0])
      3'h0:
	  IF_rg_addr_0_BITS_2_TO_0_6_EQ_0x0_40_THEN_ram__ETC___d351 =
	      { ram_word64_set$DOB[63:16], rg_st_amo_val[15:0] };
      3'h2:
	  IF_rg_addr_0_BITS_2_TO_0_6_EQ_0x0_40_THEN_ram__ETC___d351 =
	      { ram_word64_set$DOB[63:32],
		rg_st_amo_val[15:0],
		ram_word64_set$DOB[15:0] };
      3'h4:
	  IF_rg_addr_0_BITS_2_TO_0_6_EQ_0x0_40_THEN_ram__ETC___d351 =
	      { ram_word64_set$DOB[63:48],
		rg_st_amo_val[15:0],
		ram_word64_set$DOB[31:0] };
      3'h6:
	  IF_rg_addr_0_BITS_2_TO_0_6_EQ_0x0_40_THEN_ram__ETC___d351 =
	      { rg_st_amo_val[15:0], ram_word64_set$DOB[47:0] };
      default: IF_rg_addr_0_BITS_2_TO_0_6_EQ_0x0_40_THEN_ram__ETC___d351 =
		   ram_word64_set$DOB;
    endcase
  end
  always@(rg_addr or ram_word64_set$DOB or rg_st_amo_val)
  begin
    case (rg_addr[2:0])
      3'h0:
	  IF_rg_addr_0_BITS_2_TO_0_6_EQ_0x0_40_THEN_ram__ETC___d342 =
	      { ram_word64_set$DOB[63:8], rg_st_amo_val[7:0] };
      3'h1:
	  IF_rg_addr_0_BITS_2_TO_0_6_EQ_0x0_40_THEN_ram__ETC___d342 =
	      { ram_word64_set$DOB[63:16],
		rg_st_amo_val[7:0],
		ram_word64_set$DOB[7:0] };
      3'h2:
	  IF_rg_addr_0_BITS_2_TO_0_6_EQ_0x0_40_THEN_ram__ETC___d342 =
	      { ram_word64_set$DOB[63:24],
		rg_st_amo_val[7:0],
		ram_word64_set$DOB[15:0] };
      3'h3:
	  IF_rg_addr_0_BITS_2_TO_0_6_EQ_0x0_40_THEN_ram__ETC___d342 =
	      { ram_word64_set$DOB[63:32],
		rg_st_amo_val[7:0],
		ram_word64_set$DOB[23:0] };
      3'h4:
	  IF_rg_addr_0_BITS_2_TO_0_6_EQ_0x0_40_THEN_ram__ETC___d342 =
	      { ram_word64_set$DOB[63:40],
		rg_st_amo_val[7:0],
		ram_word64_set$DOB[31:0] };
      3'h5:
	  IF_rg_addr_0_BITS_2_TO_0_6_EQ_0x0_40_THEN_ram__ETC___d342 =
	      { ram_word64_set$DOB[63:48],
		rg_st_amo_val[7:0],
		ram_word64_set$DOB[39:0] };
      3'h6:
	  IF_rg_addr_0_BITS_2_TO_0_6_EQ_0x0_40_THEN_ram__ETC___d342 =
	      { ram_word64_set$DOB[63:56],
		rg_st_amo_val[7:0],
		ram_word64_set$DOB[47:0] };
      3'h7:
	  IF_rg_addr_0_BITS_2_TO_0_6_EQ_0x0_40_THEN_ram__ETC___d342 =
	      { rg_st_amo_val[7:0], ram_word64_set$DOB[55:0] };
    endcase
  end
  always@(rg_f3 or
	  IF_rg_addr_0_BITS_2_TO_0_6_EQ_0x0_40_THEN_SEXT_ETC___d204 or
	  IF_rg_addr_0_BITS_2_TO_0_6_EQ_0x0_40_THEN_SEXT_ETC___d234 or
	  new_value462_BITS_31_TO_0__q30 or
	  IF_rg_addr_0_BITS_2_TO_0_6_EQ_0x0_40_THEN_ram__ETC___d257 or
	  IF_rg_addr_0_BITS_2_TO_0_6_EQ_0x0_40_THEN_0_CO_ETC___d221 or
	  IF_rg_addr_0_BITS_2_TO_0_6_EQ_0x0_40_THEN_0_CO_ETC___d243 or
	  IF_rg_addr_0_BITS_2_TO_0_6_EQ_0x0_40_THEN_0_CO_ETC___d255)
  begin
    case (rg_f3)
      3'b0:
	  IF_rg_f3_38_EQ_0b10_44_THEN_SEXT_IF_rg_f3_38_E_ETC___d302 =
	      IF_rg_addr_0_BITS_2_TO_0_6_EQ_0x0_40_THEN_SEXT_ETC___d204;
      3'b001:
	  IF_rg_f3_38_EQ_0b10_44_THEN_SEXT_IF_rg_f3_38_E_ETC___d302 =
	      IF_rg_addr_0_BITS_2_TO_0_6_EQ_0x0_40_THEN_SEXT_ETC___d234;
      3'b010:
	  IF_rg_f3_38_EQ_0b10_44_THEN_SEXT_IF_rg_f3_38_E_ETC___d302 =
	      { {32{new_value462_BITS_31_TO_0__q30[31]}},
		new_value462_BITS_31_TO_0__q30 };
      3'b011:
	  IF_rg_f3_38_EQ_0b10_44_THEN_SEXT_IF_rg_f3_38_E_ETC___d302 =
	      IF_rg_addr_0_BITS_2_TO_0_6_EQ_0x0_40_THEN_ram__ETC___d257;
      3'b100:
	  IF_rg_f3_38_EQ_0b10_44_THEN_SEXT_IF_rg_f3_38_E_ETC___d302 =
	      IF_rg_addr_0_BITS_2_TO_0_6_EQ_0x0_40_THEN_0_CO_ETC___d221;
      3'b101:
	  IF_rg_f3_38_EQ_0b10_44_THEN_SEXT_IF_rg_f3_38_E_ETC___d302 =
	      IF_rg_addr_0_BITS_2_TO_0_6_EQ_0x0_40_THEN_0_CO_ETC___d243;
      3'b110:
	  IF_rg_f3_38_EQ_0b10_44_THEN_SEXT_IF_rg_f3_38_E_ETC___d302 =
	      IF_rg_addr_0_BITS_2_TO_0_6_EQ_0x0_40_THEN_0_CO_ETC___d255;
      3'd7: IF_rg_f3_38_EQ_0b10_44_THEN_SEXT_IF_rg_f3_38_E_ETC___d302 = 64'd0;
    endcase
  end
  always@(rg_amo_funct7 or
	  new_st_val__h18732 or
	  new_st_val__h17724 or
	  w2__h27284 or
	  new_st_val__h18704 or
	  new_st_val__h18712 or
	  new_st_val__h18708 or
	  new_st_val__h18727 or new_st_val__h18716 or new_st_val__h18721)
  begin
    case (rg_amo_funct7[6:2])
      5'b0: _theResult_____2__h17629 = new_st_val__h17724;
      5'b00001: _theResult_____2__h17629 = w2__h27284;
      5'b00100: _theResult_____2__h17629 = new_st_val__h18704;
      5'b01000: _theResult_____2__h17629 = new_st_val__h18712;
      5'b01100: _theResult_____2__h17629 = new_st_val__h18708;
      5'b10000: _theResult_____2__h17629 = new_st_val__h18727;
      5'b11000: _theResult_____2__h17629 = new_st_val__h18716;
      5'b11100: _theResult_____2__h17629 = new_st_val__h18721;
      default: _theResult_____2__h17629 = new_st_val__h18732;
    endcase
  end
  always@(rg_f3 or new_st_val__h17351 or _theResult___snd_fst__h20340)
  begin
    case (rg_f3[1:0])
      2'b0, 2'b01, 2'b10:
	  mem_req_wr_data_wdata__h20332 = _theResult___snd_fst__h20340;
      2'd3: mem_req_wr_data_wdata__h20332 = new_st_val__h17351;
    endcase
  end
  always@(rg_addr or ram_word64_set$DOB or new_st_val__h17351)
  begin
    case (rg_addr[2:0])
      3'h0:
	  IF_rg_addr_0_BITS_2_TO_0_6_EQ_0x0_40_THEN_ram__ETC___d425 =
	      { ram_word64_set$DOB[63:16], new_st_val__h17351[15:0] };
      3'h2:
	  IF_rg_addr_0_BITS_2_TO_0_6_EQ_0x0_40_THEN_ram__ETC___d425 =
	      { ram_word64_set$DOB[63:32],
		new_st_val__h17351[15:0],
		ram_word64_set$DOB[15:0] };
      3'h4:
	  IF_rg_addr_0_BITS_2_TO_0_6_EQ_0x0_40_THEN_ram__ETC___d425 =
	      { ram_word64_set$DOB[63:48],
		new_st_val__h17351[15:0],
		ram_word64_set$DOB[31:0] };
      3'h6:
	  IF_rg_addr_0_BITS_2_TO_0_6_EQ_0x0_40_THEN_ram__ETC___d425 =
	      { new_st_val__h17351[15:0], ram_word64_set$DOB[47:0] };
      default: IF_rg_addr_0_BITS_2_TO_0_6_EQ_0x0_40_THEN_ram__ETC___d425 =
		   ram_word64_set$DOB;
    endcase
  end
  always@(rg_addr or ram_word64_set$DOB or new_st_val__h17351)
  begin
    case (rg_addr[2:0])
      3'h0:
	  IF_rg_addr_0_BITS_2_TO_0_6_EQ_0x0_40_THEN_ram__ETC___d416 =
	      { ram_word64_set$DOB[63:8], new_st_val__h17351[7:0] };
      3'h1:
	  IF_rg_addr_0_BITS_2_TO_0_6_EQ_0x0_40_THEN_ram__ETC___d416 =
	      { ram_word64_set$DOB[63:16],
		new_st_val__h17351[7:0],
		ram_word64_set$DOB[7:0] };
      3'h2:
	  IF_rg_addr_0_BITS_2_TO_0_6_EQ_0x0_40_THEN_ram__ETC___d416 =
	      { ram_word64_set$DOB[63:24],
		new_st_val__h17351[7:0],
		ram_word64_set$DOB[15:0] };
      3'h3:
	  IF_rg_addr_0_BITS_2_TO_0_6_EQ_0x0_40_THEN_ram__ETC___d416 =
	      { ram_word64_set$DOB[63:32],
		new_st_val__h17351[7:0],
		ram_word64_set$DOB[23:0] };
      3'h4:
	  IF_rg_addr_0_BITS_2_TO_0_6_EQ_0x0_40_THEN_ram__ETC___d416 =
	      { ram_word64_set$DOB[63:40],
		new_st_val__h17351[7:0],
		ram_word64_set$DOB[31:0] };
      3'h5:
	  IF_rg_addr_0_BITS_2_TO_0_6_EQ_0x0_40_THEN_ram__ETC___d416 =
	      { ram_word64_set$DOB[63:48],
		new_st_val__h17351[7:0],
		ram_word64_set$DOB[39:0] };
      3'h6:
	  IF_rg_addr_0_BITS_2_TO_0_6_EQ_0x0_40_THEN_ram__ETC___d416 =
	      { ram_word64_set$DOB[63:56],
		new_st_val__h17351[7:0],
		ram_word64_set$DOB[47:0] };
      3'h7:
	  IF_rg_addr_0_BITS_2_TO_0_6_EQ_0x0_40_THEN_ram__ETC___d416 =
	      { new_st_val__h17351[7:0], ram_word64_set$DOB[55:0] };
    endcase
  end
  always@(rg_addr or ram_word64_set$DOB or rg_st_amo_val)
  begin
    case (rg_addr[2:0])
      3'h0:
	  CASE_rg_addr_BITS_2_TO_0_0x0_ram_word64_setDO_ETC__q32 =
	      { ram_word64_set$DOB[63:32], rg_st_amo_val[31:0] };
      3'h4:
	  CASE_rg_addr_BITS_2_TO_0_0x0_ram_word64_setDO_ETC__q32 =
	      { rg_st_amo_val[31:0], ram_word64_set$DOB[31:0] };
      default: CASE_rg_addr_BITS_2_TO_0_0x0_ram_word64_setDO_ETC__q32 =
		   ram_word64_set$DOB;
    endcase
  end
  always@(rg_f3 or
	  ram_word64_set$DOB or
	  IF_rg_addr_0_BITS_2_TO_0_6_EQ_0x0_40_THEN_ram__ETC___d342 or
	  IF_rg_addr_0_BITS_2_TO_0_6_EQ_0x0_40_THEN_ram__ETC___d351 or
	  CASE_rg_addr_BITS_2_TO_0_0x0_ram_word64_setDO_ETC__q32 or
	  rg_st_amo_val)
  begin
    case (rg_f3)
      3'b0:
	  IF_rg_f3_38_EQ_0b0_39_THEN_IF_rg_addr_0_BITS_2_ETC___d360 =
	      IF_rg_addr_0_BITS_2_TO_0_6_EQ_0x0_40_THEN_ram__ETC___d342;
      3'b001:
	  IF_rg_f3_38_EQ_0b0_39_THEN_IF_rg_addr_0_BITS_2_ETC___d360 =
	      IF_rg_addr_0_BITS_2_TO_0_6_EQ_0x0_40_THEN_ram__ETC___d351;
      3'b010:
	  IF_rg_f3_38_EQ_0b0_39_THEN_IF_rg_addr_0_BITS_2_ETC___d360 =
	      CASE_rg_addr_BITS_2_TO_0_0x0_ram_word64_setDO_ETC__q32;
      3'b011:
	  IF_rg_f3_38_EQ_0b0_39_THEN_IF_rg_addr_0_BITS_2_ETC___d360 =
	      rg_st_amo_val;
      default: IF_rg_f3_38_EQ_0b0_39_THEN_IF_rg_addr_0_BITS_2_ETC___d360 =
		   ram_word64_set$DOB;
    endcase
  end
  always@(rg_addr or
	  result__h24808 or
	  result__h24835 or result__h24862 or result__h24889)
  begin
    case (rg_addr[2:0])
      3'h0:
	  IF_rg_addr_0_BITS_2_TO_0_6_EQ_0x0_40_THEN_0_CO_ETC___d666 =
	      result__h24808;
      3'h2:
	  IF_rg_addr_0_BITS_2_TO_0_6_EQ_0x0_40_THEN_0_CO_ETC___d666 =
	      result__h24835;
      3'h4:
	  IF_rg_addr_0_BITS_2_TO_0_6_EQ_0x0_40_THEN_0_CO_ETC___d666 =
	      result__h24862;
      3'h6:
	  IF_rg_addr_0_BITS_2_TO_0_6_EQ_0x0_40_THEN_0_CO_ETC___d666 =
	      result__h24889;
      default: IF_rg_addr_0_BITS_2_TO_0_6_EQ_0x0_40_THEN_0_CO_ETC___d666 =
		   64'd0;
    endcase
  end
  always@(rg_addr or
	  result__h24687 or
	  result__h24714 or result__h24741 or result__h24768)
  begin
    case (rg_addr[2:0])
      3'h0:
	  IF_rg_addr_0_BITS_2_TO_0_6_EQ_0x0_40_THEN_SEXT_ETC___d658 =
	      result__h24687;
      3'h2:
	  IF_rg_addr_0_BITS_2_TO_0_6_EQ_0x0_40_THEN_SEXT_ETC___d658 =
	      result__h24714;
      3'h4:
	  IF_rg_addr_0_BITS_2_TO_0_6_EQ_0x0_40_THEN_SEXT_ETC___d658 =
	      result__h24741;
      3'h6:
	  IF_rg_addr_0_BITS_2_TO_0_6_EQ_0x0_40_THEN_SEXT_ETC___d658 =
	      result__h24768;
      default: IF_rg_addr_0_BITS_2_TO_0_6_EQ_0x0_40_THEN_SEXT_ETC___d658 =
		   64'd0;
    endcase
  end
  always@(rg_addr or
	  result__h24454 or
	  result__h24481 or
	  result__h24508 or
	  result__h24535 or
	  result__h24562 or
	  result__h24589 or result__h24616 or result__h24643)
  begin
    case (rg_addr[2:0])
      3'h0:
	  IF_rg_addr_0_BITS_2_TO_0_6_EQ_0x0_40_THEN_0_CO_ETC___d646 =
	      result__h24454;
      3'h1:
	  IF_rg_addr_0_BITS_2_TO_0_6_EQ_0x0_40_THEN_0_CO_ETC___d646 =
	      result__h24481;
      3'h2:
	  IF_rg_addr_0_BITS_2_TO_0_6_EQ_0x0_40_THEN_0_CO_ETC___d646 =
	      result__h24508;
      3'h3:
	  IF_rg_addr_0_BITS_2_TO_0_6_EQ_0x0_40_THEN_0_CO_ETC___d646 =
	      result__h24535;
      3'h4:
	  IF_rg_addr_0_BITS_2_TO_0_6_EQ_0x0_40_THEN_0_CO_ETC___d646 =
	      result__h24562;
      3'h5:
	  IF_rg_addr_0_BITS_2_TO_0_6_EQ_0x0_40_THEN_0_CO_ETC___d646 =
	      result__h24589;
      3'h6:
	  IF_rg_addr_0_BITS_2_TO_0_6_EQ_0x0_40_THEN_0_CO_ETC___d646 =
	      result__h24616;
      3'h7:
	  IF_rg_addr_0_BITS_2_TO_0_6_EQ_0x0_40_THEN_0_CO_ETC___d646 =
	      result__h24643;
    endcase
  end
  always@(rg_addr or
	  result__h24218 or
	  result__h24248 or
	  result__h24275 or
	  result__h24302 or
	  result__h24329 or
	  result__h24356 or result__h24383 or result__h24410)
  begin
    case (rg_addr[2:0])
      3'h0:
	  IF_rg_addr_0_BITS_2_TO_0_6_EQ_0x0_40_THEN_SEXT_ETC___d630 =
	      result__h24218;
      3'h1:
	  IF_rg_addr_0_BITS_2_TO_0_6_EQ_0x0_40_THEN_SEXT_ETC___d630 =
	      result__h24248;
      3'h2:
	  IF_rg_addr_0_BITS_2_TO_0_6_EQ_0x0_40_THEN_SEXT_ETC___d630 =
	      result__h24275;
      3'h3:
	  IF_rg_addr_0_BITS_2_TO_0_6_EQ_0x0_40_THEN_SEXT_ETC___d630 =
	      result__h24302;
      3'h4:
	  IF_rg_addr_0_BITS_2_TO_0_6_EQ_0x0_40_THEN_SEXT_ETC___d630 =
	      result__h24329;
      3'h5:
	  IF_rg_addr_0_BITS_2_TO_0_6_EQ_0x0_40_THEN_SEXT_ETC___d630 =
	      result__h24356;
      3'h6:
	  IF_rg_addr_0_BITS_2_TO_0_6_EQ_0x0_40_THEN_SEXT_ETC___d630 =
	      result__h24383;
      3'h7:
	  IF_rg_addr_0_BITS_2_TO_0_6_EQ_0x0_40_THEN_SEXT_ETC___d630 =
	      result__h24410;
    endcase
  end
  always@(rg_addr or result__h24929 or result__h24956)
  begin
    case (rg_addr[2:0])
      3'h0:
	  CASE_rg_addr_BITS_2_TO_0_0x0_result4929_0x4_re_ETC__q33 =
	      result__h24929;
      3'h4:
	  CASE_rg_addr_BITS_2_TO_0_0x0_result4929_0x4_re_ETC__q33 =
	      result__h24956;
      default: CASE_rg_addr_BITS_2_TO_0_0x0_result4929_0x4_re_ETC__q33 =
		   64'd0;
    endcase
  end
  always@(rg_addr or result__h24994 or result__h25021)
  begin
    case (rg_addr[2:0])
      3'h0:
	  CASE_rg_addr_BITS_2_TO_0_0x0_result4994_0x4_re_ETC__q34 =
	      result__h24994;
      3'h4:
	  CASE_rg_addr_BITS_2_TO_0_0x0_result4994_0x4_re_ETC__q34 =
	      result__h25021;
      default: CASE_rg_addr_BITS_2_TO_0_0x0_result4994_0x4_re_ETC__q34 =
		   64'd0;
    endcase
  end
  always@(rg_f3 or
	  IF_rg_addr_0_BITS_2_TO_0_6_EQ_0x0_40_THEN_SEXT_ETC___d630 or
	  IF_rg_addr_0_BITS_2_TO_0_6_EQ_0x0_40_THEN_SEXT_ETC___d658 or
	  CASE_rg_addr_BITS_2_TO_0_0x0_result4929_0x4_re_ETC__q33 or
	  rg_addr or
	  master_xactor_rg_rd_data or
	  IF_rg_addr_0_BITS_2_TO_0_6_EQ_0x0_40_THEN_0_CO_ETC___d646 or
	  IF_rg_addr_0_BITS_2_TO_0_6_EQ_0x0_40_THEN_0_CO_ETC___d666 or
	  CASE_rg_addr_BITS_2_TO_0_0x0_result4994_0x4_re_ETC__q34)
  begin
    case (rg_f3)
      3'b0:
	  ld_val__h24158 =
	      IF_rg_addr_0_BITS_2_TO_0_6_EQ_0x0_40_THEN_SEXT_ETC___d630;
      3'b001:
	  ld_val__h24158 =
	      IF_rg_addr_0_BITS_2_TO_0_6_EQ_0x0_40_THEN_SEXT_ETC___d658;
      3'b010:
	  ld_val__h24158 =
	      CASE_rg_addr_BITS_2_TO_0_0x0_result4929_0x4_re_ETC__q33;
      3'b011:
	  ld_val__h24158 =
	      (rg_addr[2:0] == 3'h0) ? master_xactor_rg_rd_data[66:3] : 64'd0;
      3'b100:
	  ld_val__h24158 =
	      IF_rg_addr_0_BITS_2_TO_0_6_EQ_0x0_40_THEN_0_CO_ETC___d646;
      3'b101:
	  ld_val__h24158 =
	      IF_rg_addr_0_BITS_2_TO_0_6_EQ_0x0_40_THEN_0_CO_ETC___d666;
      3'b110:
	  ld_val__h24158 =
	      CASE_rg_addr_BITS_2_TO_0_0x0_result4994_0x4_re_ETC__q34;
      3'd7: ld_val__h24158 = 64'd0;
    endcase
  end
  always@(rg_addr or
	  result__h28960 or
	  result__h28988 or result__h29016 or result__h29044)
  begin
    case (rg_addr[2:0])
      3'h0:
	  IF_rg_addr_0_BITS_2_TO_0_6_EQ_0x0_40_THEN_0_CO_ETC___d789 =
	      result__h28960;
      3'h2:
	  IF_rg_addr_0_BITS_2_TO_0_6_EQ_0x0_40_THEN_0_CO_ETC___d789 =
	      result__h28988;
      3'h4:
	  IF_rg_addr_0_BITS_2_TO_0_6_EQ_0x0_40_THEN_0_CO_ETC___d789 =
	      result__h29016;
      3'h6:
	  IF_rg_addr_0_BITS_2_TO_0_6_EQ_0x0_40_THEN_0_CO_ETC___d789 =
	      result__h29044;
      default: IF_rg_addr_0_BITS_2_TO_0_6_EQ_0x0_40_THEN_0_CO_ETC___d789 =
		   64'd0;
    endcase
  end
  always@(rg_addr or result__h29152 or result__h29180)
  begin
    case (rg_addr[2:0])
      3'h0:
	  IF_rg_addr_0_BITS_2_TO_0_6_EQ_0x0_40_THEN_0_CO_ETC___d799 =
	      result__h29152;
      3'h4:
	  IF_rg_addr_0_BITS_2_TO_0_6_EQ_0x0_40_THEN_0_CO_ETC___d799 =
	      result__h29180;
      default: IF_rg_addr_0_BITS_2_TO_0_6_EQ_0x0_40_THEN_0_CO_ETC___d799 =
		   64'd0;
    endcase
  end
  always@(rg_addr or
	  result__h28835 or
	  result__h28863 or result__h28891 or result__h28919)
  begin
    case (rg_addr[2:0])
      3'h0:
	  IF_rg_addr_0_BITS_2_TO_0_6_EQ_0x0_40_THEN_SEXT_ETC___d781 =
	      result__h28835;
      3'h2:
	  IF_rg_addr_0_BITS_2_TO_0_6_EQ_0x0_40_THEN_SEXT_ETC___d781 =
	      result__h28863;
      3'h4:
	  IF_rg_addr_0_BITS_2_TO_0_6_EQ_0x0_40_THEN_SEXT_ETC___d781 =
	      result__h28891;
      3'h6:
	  IF_rg_addr_0_BITS_2_TO_0_6_EQ_0x0_40_THEN_SEXT_ETC___d781 =
	      result__h28919;
      default: IF_rg_addr_0_BITS_2_TO_0_6_EQ_0x0_40_THEN_SEXT_ETC___d781 =
		   64'd0;
    endcase
  end
  always@(rg_addr or
	  result__h28594 or
	  result__h28622 or
	  result__h28650 or
	  result__h28678 or
	  result__h28706 or
	  result__h28734 or result__h28762 or result__h28790)
  begin
    case (rg_addr[2:0])
      3'h0:
	  IF_rg_addr_0_BITS_2_TO_0_6_EQ_0x0_40_THEN_0_CO_ETC___d769 =
	      result__h28594;
      3'h1:
	  IF_rg_addr_0_BITS_2_TO_0_6_EQ_0x0_40_THEN_0_CO_ETC___d769 =
	      result__h28622;
      3'h2:
	  IF_rg_addr_0_BITS_2_TO_0_6_EQ_0x0_40_THEN_0_CO_ETC___d769 =
	      result__h28650;
      3'h3:
	  IF_rg_addr_0_BITS_2_TO_0_6_EQ_0x0_40_THEN_0_CO_ETC___d769 =
	      result__h28678;
      3'h4:
	  IF_rg_addr_0_BITS_2_TO_0_6_EQ_0x0_40_THEN_0_CO_ETC___d769 =
	      result__h28706;
      3'h5:
	  IF_rg_addr_0_BITS_2_TO_0_6_EQ_0x0_40_THEN_0_CO_ETC___d769 =
	      result__h28734;
      3'h6:
	  IF_rg_addr_0_BITS_2_TO_0_6_EQ_0x0_40_THEN_0_CO_ETC___d769 =
	      result__h28762;
      3'h7:
	  IF_rg_addr_0_BITS_2_TO_0_6_EQ_0x0_40_THEN_0_CO_ETC___d769 =
	      result__h28790;
    endcase
  end
  always@(rg_addr or
	  result__h27473 or
	  result__h28381 or
	  result__h28409 or
	  result__h28437 or
	  result__h28465 or
	  result__h28493 or result__h28521 or result__h28549)
  begin
    case (rg_addr[2:0])
      3'h0:
	  IF_rg_addr_0_BITS_2_TO_0_6_EQ_0x0_40_THEN_SEXT_ETC___d753 =
	      result__h27473;
      3'h1:
	  IF_rg_addr_0_BITS_2_TO_0_6_EQ_0x0_40_THEN_SEXT_ETC___d753 =
	      result__h28381;
      3'h2:
	  IF_rg_addr_0_BITS_2_TO_0_6_EQ_0x0_40_THEN_SEXT_ETC___d753 =
	      result__h28409;
      3'h3:
	  IF_rg_addr_0_BITS_2_TO_0_6_EQ_0x0_40_THEN_SEXT_ETC___d753 =
	      result__h28437;
      3'h4:
	  IF_rg_addr_0_BITS_2_TO_0_6_EQ_0x0_40_THEN_SEXT_ETC___d753 =
	      result__h28465;
      3'h5:
	  IF_rg_addr_0_BITS_2_TO_0_6_EQ_0x0_40_THEN_SEXT_ETC___d753 =
	      result__h28493;
      3'h6:
	  IF_rg_addr_0_BITS_2_TO_0_6_EQ_0x0_40_THEN_SEXT_ETC___d753 =
	      result__h28521;
      3'h7:
	  IF_rg_addr_0_BITS_2_TO_0_6_EQ_0x0_40_THEN_SEXT_ETC___d753 =
	      result__h28549;
    endcase
  end
  always@(rg_addr or result__h29085 or result__h29113)
  begin
    case (rg_addr[2:0])
      3'h0:
	  CASE_rg_addr_BITS_2_TO_0_0x0_result9085_0x4_re_ETC__q49 =
	      result__h29085;
      3'h4:
	  CASE_rg_addr_BITS_2_TO_0_0x0_result9085_0x4_re_ETC__q49 =
	      result__h29113;
      default: CASE_rg_addr_BITS_2_TO_0_0x0_result9085_0x4_re_ETC__q49 =
		   64'd0;
    endcase
  end
  always@(rg_f3 or
	  IF_rg_addr_0_BITS_2_TO_0_6_EQ_0x0_40_THEN_SEXT_ETC___d753 or
	  IF_rg_addr_0_BITS_2_TO_0_6_EQ_0x0_40_THEN_SEXT_ETC___d781 or
	  CASE_rg_addr_BITS_2_TO_0_0x0_result9085_0x4_re_ETC__q49 or
	  IF_rg_addr_0_BITS_2_TO_0_6_EQ_0x0_40_THEN_IF_r_ETC___d800 or
	  IF_rg_addr_0_BITS_2_TO_0_6_EQ_0x0_40_THEN_0_CO_ETC___d769 or
	  IF_rg_addr_0_BITS_2_TO_0_6_EQ_0x0_40_THEN_0_CO_ETC___d789 or
	  IF_rg_addr_0_BITS_2_TO_0_6_EQ_0x0_40_THEN_0_CO_ETC___d799)
  begin
    case (rg_f3)
      3'b0:
	  w1__h27278 =
	      IF_rg_addr_0_BITS_2_TO_0_6_EQ_0x0_40_THEN_SEXT_ETC___d753;
      3'b001:
	  w1__h27278 =
	      IF_rg_addr_0_BITS_2_TO_0_6_EQ_0x0_40_THEN_SEXT_ETC___d781;
      3'b010:
	  w1__h27278 =
	      CASE_rg_addr_BITS_2_TO_0_0x0_result9085_0x4_re_ETC__q49;
      3'b011:
	  w1__h27278 =
	      IF_rg_addr_0_BITS_2_TO_0_6_EQ_0x0_40_THEN_IF_r_ETC___d800;
      3'b100:
	  w1__h27278 =
	      IF_rg_addr_0_BITS_2_TO_0_6_EQ_0x0_40_THEN_0_CO_ETC___d769;
      3'b101:
	  w1__h27278 =
	      IF_rg_addr_0_BITS_2_TO_0_6_EQ_0x0_40_THEN_0_CO_ETC___d789;
      3'b110:
	  w1__h27278 =
	      IF_rg_addr_0_BITS_2_TO_0_6_EQ_0x0_40_THEN_0_CO_ETC___d799;
      3'd7: w1__h27278 = 64'd0;
    endcase
  end
  always@(rg_f3 or
	  IF_rg_addr_0_BITS_2_TO_0_6_EQ_0x0_40_THEN_SEXT_ETC___d753 or
	  IF_rg_addr_0_BITS_2_TO_0_6_EQ_0x0_40_THEN_SEXT_ETC___d781 or
	  w1___1__h27353 or
	  IF_rg_addr_0_BITS_2_TO_0_6_EQ_0x0_40_THEN_IF_r_ETC___d800 or
	  IF_rg_addr_0_BITS_2_TO_0_6_EQ_0x0_40_THEN_0_CO_ETC___d769 or
	  IF_rg_addr_0_BITS_2_TO_0_6_EQ_0x0_40_THEN_0_CO_ETC___d789 or
	  IF_rg_addr_0_BITS_2_TO_0_6_EQ_0x0_40_THEN_0_CO_ETC___d799)
  begin
    case (rg_f3)
      3'b0:
	  w1__h27282 =
	      IF_rg_addr_0_BITS_2_TO_0_6_EQ_0x0_40_THEN_SEXT_ETC___d753;
      3'b001:
	  w1__h27282 =
	      IF_rg_addr_0_BITS_2_TO_0_6_EQ_0x0_40_THEN_SEXT_ETC___d781;
      3'b010: w1__h27282 = w1___1__h27353;
      3'b011:
	  w1__h27282 =
	      IF_rg_addr_0_BITS_2_TO_0_6_EQ_0x0_40_THEN_IF_r_ETC___d800;
      3'b100:
	  w1__h27282 =
	      IF_rg_addr_0_BITS_2_TO_0_6_EQ_0x0_40_THEN_0_CO_ETC___d769;
      3'b101:
	  w1__h27282 =
	      IF_rg_addr_0_BITS_2_TO_0_6_EQ_0x0_40_THEN_0_CO_ETC___d789;
      3'b110:
	  w1__h27282 =
	      IF_rg_addr_0_BITS_2_TO_0_6_EQ_0x0_40_THEN_0_CO_ETC___d799;
      3'd7: w1__h27282 = 64'd0;
    endcase
  end
  always@(rg_f3 or
	  IF_rg_addr_0_BITS_2_TO_0_6_EQ_0x0_40_THEN_SEXT_ETC___d753 or
	  IF_rg_addr_0_BITS_2_TO_0_6_EQ_0x0_40_THEN_SEXT_ETC___d781 or
	  w17278_BITS_31_TO_0__q50 or
	  IF_rg_addr_0_BITS_2_TO_0_6_EQ_0x0_40_THEN_IF_r_ETC___d800 or
	  IF_rg_addr_0_BITS_2_TO_0_6_EQ_0x0_40_THEN_0_CO_ETC___d769 or
	  IF_rg_addr_0_BITS_2_TO_0_6_EQ_0x0_40_THEN_0_CO_ETC___d789 or
	  IF_rg_addr_0_BITS_2_TO_0_6_EQ_0x0_40_THEN_0_CO_ETC___d799)
  begin
    case (rg_f3)
      3'b0:
	  new_ld_val__h26998 =
	      IF_rg_addr_0_BITS_2_TO_0_6_EQ_0x0_40_THEN_SEXT_ETC___d753;
      3'b001:
	  new_ld_val__h26998 =
	      IF_rg_addr_0_BITS_2_TO_0_6_EQ_0x0_40_THEN_SEXT_ETC___d781;
      3'b010:
	  new_ld_val__h26998 =
	      { {32{w17278_BITS_31_TO_0__q50[31]}},
		w17278_BITS_31_TO_0__q50 };
      3'b011:
	  new_ld_val__h26998 =
	      IF_rg_addr_0_BITS_2_TO_0_6_EQ_0x0_40_THEN_IF_r_ETC___d800;
      3'b100:
	  new_ld_val__h26998 =
	      IF_rg_addr_0_BITS_2_TO_0_6_EQ_0x0_40_THEN_0_CO_ETC___d769;
      3'b101:
	  new_ld_val__h26998 =
	      IF_rg_addr_0_BITS_2_TO_0_6_EQ_0x0_40_THEN_0_CO_ETC___d789;
      3'b110:
	  new_ld_val__h26998 =
	      IF_rg_addr_0_BITS_2_TO_0_6_EQ_0x0_40_THEN_0_CO_ETC___d799;
      3'd7: new_ld_val__h26998 = 64'd0;
    endcase
  end
  always@(rg_amo_funct7 or
	  new_st_val__h29273 or
	  new_st_val__h27385 or
	  w2__h27284 or
	  new_st_val__h29245 or
	  new_st_val__h29253 or
	  new_st_val__h29249 or
	  new_st_val__h29268 or new_st_val__h29257 or new_st_val__h29262)
  begin
    case (rg_amo_funct7[6:2])
      5'b0: _theResult_____2__h27290 = new_st_val__h27385;
      5'b00001: _theResult_____2__h27290 = w2__h27284;
      5'b00100: _theResult_____2__h27290 = new_st_val__h29245;
      5'b01000: _theResult_____2__h27290 = new_st_val__h29253;
      5'b01100: _theResult_____2__h27290 = new_st_val__h29249;
      5'b10000: _theResult_____2__h27290 = new_st_val__h29268;
      5'b11000: _theResult_____2__h27290 = new_st_val__h29257;
      5'b11100: _theResult_____2__h27290 = new_st_val__h29262;
      default: _theResult_____2__h27290 = new_st_val__h29273;
    endcase
  end
  always@(rg_f3 or st_val__h27010 or _theResult___snd_fst__h27273)
  begin
    case (rg_f3[1:0])
      2'b0, 2'b01, 2'b10:
	  mem_req_wr_data_wdata__h27265 = _theResult___snd_fst__h27273;
      2'd3: mem_req_wr_data_wdata__h27265 = st_val__h27010;
    endcase
  end
  always@(rg_addr or ram_word64_set$DOB or new_st_val__h17351)
  begin
    case (rg_addr[2:0])
      3'h0:
	  CASE_rg_addr_BITS_2_TO_0_0x0_ram_word64_setDO_ETC__q51 =
	      { ram_word64_set$DOB[63:32], new_st_val__h17351[31:0] };
      3'h4:
	  CASE_rg_addr_BITS_2_TO_0_0x0_ram_word64_setDO_ETC__q51 =
	      { new_st_val__h17351[31:0], ram_word64_set$DOB[31:0] };
      default: CASE_rg_addr_BITS_2_TO_0_0x0_ram_word64_setDO_ETC__q51 =
		   ram_word64_set$DOB;
    endcase
  end
  always@(rg_f3 or
	  ram_word64_set$DOB or
	  IF_rg_addr_0_BITS_2_TO_0_6_EQ_0x0_40_THEN_ram__ETC___d416 or
	  IF_rg_addr_0_BITS_2_TO_0_6_EQ_0x0_40_THEN_ram__ETC___d425 or
	  CASE_rg_addr_BITS_2_TO_0_0x0_ram_word64_setDO_ETC__q51 or
	  new_st_val__h17351)
  begin
    case (rg_f3)
      3'b0:
	  IF_rg_f3_38_EQ_0b0_39_THEN_IF_rg_addr_0_BITS_2_ETC___d434 =
	      IF_rg_addr_0_BITS_2_TO_0_6_EQ_0x0_40_THEN_ram__ETC___d416;
      3'b001:
	  IF_rg_f3_38_EQ_0b0_39_THEN_IF_rg_addr_0_BITS_2_ETC___d434 =
	      IF_rg_addr_0_BITS_2_TO_0_6_EQ_0x0_40_THEN_ram__ETC___d425;
      3'b010:
	  IF_rg_f3_38_EQ_0b0_39_THEN_IF_rg_addr_0_BITS_2_ETC___d434 =
	      CASE_rg_addr_BITS_2_TO_0_0x0_ram_word64_setDO_ETC__q51;
      3'b011:
	  IF_rg_f3_38_EQ_0b0_39_THEN_IF_rg_addr_0_BITS_2_ETC___d434 =
	      new_st_val__h17351;
      default: IF_rg_f3_38_EQ_0b0_39_THEN_IF_rg_addr_0_BITS_2_ETC___d434 =
		   ram_word64_set$DOB;
    endcase
  end
  always@(rg_f3 or IF_rg_addr_0_BITS_2_TO_0_6_EQ_0x0_40_THEN_1_EL_ETC___d271)
  begin
    case (rg_f3)
      3'b0, 3'b001, 3'b010, 3'b011, 3'b100, 3'b101, 3'b110:
	  new_value__h15489 =
	      IF_rg_addr_0_BITS_2_TO_0_6_EQ_0x0_40_THEN_1_EL_ETC___d271;
      3'd7: new_value__h15489 = 64'd0;
    endcase
  end

  // handling of inlined registers

  always@(posedge CLK)
  begin
    if (RST_N == `BSV_RESET_VALUE)
      begin
        cfg_verbosity <= `BSV_ASSIGNMENT_DELAY 4'd0;
	crg_sb_to_load_delay <= `BSV_ASSIGNMENT_DELAY 11'd0;
	ctr_wr_rsps_pending_crg <= `BSV_ASSIGNMENT_DELAY 4'd0;
	master_xactor_crg_rd_addr_full <= `BSV_ASSIGNMENT_DELAY 1'd0;
	master_xactor_crg_rd_data_full <= `BSV_ASSIGNMENT_DELAY 1'd0;
	master_xactor_crg_wr_addr_full <= `BSV_ASSIGNMENT_DELAY 1'd0;
	master_xactor_crg_wr_data_full <= `BSV_ASSIGNMENT_DELAY 1'd0;
	master_xactor_crg_wr_resp_full <= `BSV_ASSIGNMENT_DELAY 1'd0;
	rg_cset_in_cache <= `BSV_ASSIGNMENT_DELAY 6'd0;
	rg_lower_word32_full <= `BSV_ASSIGNMENT_DELAY 1'd0;
	rg_lrsc_valid <= `BSV_ASSIGNMENT_DELAY 1'd0;
	rg_state <= `BSV_ASSIGNMENT_DELAY 5'd0;
      end
    else
      begin
        if (cfg_verbosity$EN)
	  cfg_verbosity <= `BSV_ASSIGNMENT_DELAY cfg_verbosity$D_IN;
	if (crg_sb_to_load_delay$EN)
	  crg_sb_to_load_delay <= `BSV_ASSIGNMENT_DELAY
	      crg_sb_to_load_delay$D_IN;
	if (ctr_wr_rsps_pending_crg$EN)
	  ctr_wr_rsps_pending_crg <= `BSV_ASSIGNMENT_DELAY
	      ctr_wr_rsps_pending_crg$D_IN;
	if (master_xactor_crg_rd_addr_full$EN)
	  master_xactor_crg_rd_addr_full <= `BSV_ASSIGNMENT_DELAY
	      master_xactor_crg_rd_addr_full$D_IN;
	if (master_xactor_crg_rd_data_full$EN)
	  master_xactor_crg_rd_data_full <= `BSV_ASSIGNMENT_DELAY
	      master_xactor_crg_rd_data_full$D_IN;
	if (master_xactor_crg_wr_addr_full$EN)
	  master_xactor_crg_wr_addr_full <= `BSV_ASSIGNMENT_DELAY
	      master_xactor_crg_wr_addr_full$D_IN;
	if (master_xactor_crg_wr_data_full$EN)
	  master_xactor_crg_wr_data_full <= `BSV_ASSIGNMENT_DELAY
	      master_xactor_crg_wr_data_full$D_IN;
	if (master_xactor_crg_wr_resp_full$EN)
	  master_xactor_crg_wr_resp_full <= `BSV_ASSIGNMENT_DELAY
	      master_xactor_crg_wr_resp_full$D_IN;
	if (rg_cset_in_cache$EN)
	  rg_cset_in_cache <= `BSV_ASSIGNMENT_DELAY rg_cset_in_cache$D_IN;
	if (rg_lower_word32_full$EN)
	  rg_lower_word32_full <= `BSV_ASSIGNMENT_DELAY
	      rg_lower_word32_full$D_IN;
	if (rg_lrsc_valid$EN)
	  rg_lrsc_valid <= `BSV_ASSIGNMENT_DELAY rg_lrsc_valid$D_IN;
	if (rg_state$EN) rg_state <= `BSV_ASSIGNMENT_DELAY rg_state$D_IN;
      end
    if (master_xactor_rg_rd_addr$EN)
      master_xactor_rg_rd_addr <= `BSV_ASSIGNMENT_DELAY
	  master_xactor_rg_rd_addr$D_IN;
    if (master_xactor_rg_rd_data$EN)
      master_xactor_rg_rd_data <= `BSV_ASSIGNMENT_DELAY
	  master_xactor_rg_rd_data$D_IN;
    if (master_xactor_rg_wr_addr$EN)
      master_xactor_rg_wr_addr <= `BSV_ASSIGNMENT_DELAY
	  master_xactor_rg_wr_addr$D_IN;
    if (master_xactor_rg_wr_data$EN)
      master_xactor_rg_wr_data <= `BSV_ASSIGNMENT_DELAY
	  master_xactor_rg_wr_data$D_IN;
    if (master_xactor_rg_wr_resp$EN)
      master_xactor_rg_wr_resp <= `BSV_ASSIGNMENT_DELAY
	  master_xactor_rg_wr_resp$D_IN;
    if (rg_addr$EN) rg_addr <= `BSV_ASSIGNMENT_DELAY rg_addr$D_IN;
    if (rg_amo_funct7$EN)
      rg_amo_funct7 <= `BSV_ASSIGNMENT_DELAY rg_amo_funct7$D_IN;
    if (rg_error_during_refill$EN)
      rg_error_during_refill <= `BSV_ASSIGNMENT_DELAY
	  rg_error_during_refill$D_IN;
    if (rg_exc_code$EN) rg_exc_code <= `BSV_ASSIGNMENT_DELAY rg_exc_code$D_IN;
    if (rg_f3$EN) rg_f3 <= `BSV_ASSIGNMENT_DELAY rg_f3$D_IN;
    if (rg_ld_val$EN) rg_ld_val <= `BSV_ASSIGNMENT_DELAY rg_ld_val$D_IN;
    if (rg_lower_word32$EN)
      rg_lower_word32 <= `BSV_ASSIGNMENT_DELAY rg_lower_word32$D_IN;
    if (rg_lrsc_pa$EN) rg_lrsc_pa <= `BSV_ASSIGNMENT_DELAY rg_lrsc_pa$D_IN;
    if (rg_op$EN) rg_op <= `BSV_ASSIGNMENT_DELAY rg_op$D_IN;
    if (rg_pa$EN) rg_pa <= `BSV_ASSIGNMENT_DELAY rg_pa$D_IN;
    if (rg_pte_pa$EN) rg_pte_pa <= `BSV_ASSIGNMENT_DELAY rg_pte_pa$D_IN;
    if (rg_st_amo_val$EN)
      rg_st_amo_val <= `BSV_ASSIGNMENT_DELAY rg_st_amo_val$D_IN;
    if (rg_word64_set_in_cache$EN)
      rg_word64_set_in_cache <= `BSV_ASSIGNMENT_DELAY
	  rg_word64_set_in_cache$D_IN;
  end

  // synopsys translate_off
  `ifdef BSV_NO_INITIAL_BLOCKS
  `else // not BSV_NO_INITIAL_BLOCKS
  initial
  begin
    cfg_verbosity = 4'hA;
    crg_sb_to_load_delay = 11'h2AA;
    ctr_wr_rsps_pending_crg = 4'hA;
    master_xactor_crg_rd_addr_full = 1'h0;
    master_xactor_crg_rd_data_full = 1'h0;
    master_xactor_crg_wr_addr_full = 1'h0;
    master_xactor_crg_wr_data_full = 1'h0;
    master_xactor_crg_wr_resp_full = 1'h0;
    master_xactor_rg_rd_addr = 97'h0AAAAAAAAAAAAAAAAAAAAAAAA;
    master_xactor_rg_rd_data = 71'h2AAAAAAAAAAAAAAAAA;
    master_xactor_rg_wr_addr = 97'h0AAAAAAAAAAAAAAAAAAAAAAAA;
    master_xactor_rg_wr_data = 77'h0AAAAAAAAAAAAAAAAAAA;
    master_xactor_rg_wr_resp = 6'h2A;
    rg_addr = 64'hAAAAAAAAAAAAAAAA;
    rg_amo_funct7 = 7'h2A;
    rg_cset_in_cache = 6'h2A;
    rg_error_during_refill = 1'h0;
    rg_exc_code = 4'hA;
    rg_f3 = 3'h2;
    rg_ld_val = 64'hAAAAAAAAAAAAAAAA;
    rg_lower_word32 = 32'hAAAAAAAA;
    rg_lower_word32_full = 1'h0;
    rg_lrsc_pa = 64'hAAAAAAAAAAAAAAAA;
    rg_lrsc_valid = 1'h0;
    rg_op = 2'h2;
    rg_pa = 64'hAAAAAAAAAAAAAAAA;
    rg_pte_pa = 64'hAAAAAAAAAAAAAAAA;
    rg_st_amo_val = 64'hAAAAAAAAAAAAAAAA;
    rg_state = 5'h0A;
    rg_word64_set_in_cache = 9'h0AA;
  end
  `endif // BSV_NO_INITIAL_BLOCKS
  // synopsys translate_on

  // handling of system tasks

  // synopsys translate_off
  always@(negedge CLK)
  begin
    #0;
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_reset && rg_cset_in_cache == 6'd63 &&
	  cfg_verbosity != 4'd0 &&
	  !f_reset_reqs$D_OUT)
	begin
	  v__h3732 = $stime;
	  #0;
	end
    v__h3726 = v__h3732 / 32'd10;
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_reset && rg_cset_in_cache == 6'd63 &&
	  cfg_verbosity != 4'd0 &&
	  !f_reset_reqs$D_OUT)
	if (dmem_not_imem)
	  $display("%0d: %s.rl_reset: %0d sets x %0d ways: all tag states reset to CTAG_EMPTY",
		   v__h3726,
		   "D_MMU_Cache",
		   $signed(32'd64),
		   $signed(32'd1));
	else
	  $display("%0d: %s.rl_reset: %0d sets x %0d ways: all tag states reset to CTAG_EMPTY",
		   v__h3726,
		   "I_MMU_Cache",
		   $signed(32'd64),
		   $signed(32'd1));
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_reset && rg_cset_in_cache == 6'd63 &&
	  NOT_cfg_verbosity_read__0_ULE_1_1___d12 &&
	  f_reset_reqs$D_OUT)
	begin
	  v__h3833 = $stime;
	  #0;
	end
    v__h3827 = v__h3833 / 32'd10;
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_reset && rg_cset_in_cache == 6'd63 &&
	  NOT_cfg_verbosity_read__0_ULE_1_1___d12 &&
	  f_reset_reqs$D_OUT)
	if (dmem_not_imem)
	  $display("%0d: %s.rl_reset: Flushed", v__h3827, "D_MMU_Cache");
	else
	  $display("%0d: %s.rl_reset: Flushed", v__h3827, "I_MMU_Cache");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_rereq && NOT_cfg_verbosity_read__0_ULE_1_1___d12)
	$display("    fa_req_ram_B tagCSet [0x%0x] word64_set [0x%0d]",
		 rg_addr[11:6],
		 rg_addr[11:3]);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_maintain_io_read_rsp &&
	  NOT_cfg_verbosity_read__0_ULE_1_1___d12)
	begin
	  v__h25363 = $stime;
	  #0;
	end
    v__h25357 = v__h25363 / 32'd10;
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_maintain_io_read_rsp &&
	  NOT_cfg_verbosity_read__0_ULE_1_1___d12)
	if (dmem_not_imem)
	  $display("%0d: %s.drive_IO_read_rsp: addr 0x%0h ld_val 0x%0h",
		   v__h25357,
		   "D_MMU_Cache",
		   rg_addr,
		   rg_ld_val);
	else
	  $display("%0d: %s.drive_IO_read_rsp: addr 0x%0h ld_val 0x%0h",
		   v__h25357,
		   "I_MMU_Cache",
		   rg_addr,
		   rg_ld_val);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_io_AMO_SC_req &&
	  NOT_cfg_verbosity_read__0_ULE_1_1___d12)
	begin
	  v__h26261 = $stime;
	  #0;
	end
    v__h26255 = v__h26261 / 32'd10;
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_io_AMO_SC_req &&
	  NOT_cfg_verbosity_read__0_ULE_1_1___d12)
	if (dmem_not_imem)
	  $display("%0d: %s: rl_io_AMO_SC_req; f3 0x%0h  vaddr %0h  paddr %0h  word64 0x%0h",
		   v__h26255,
		   "D_MMU_Cache",
		   rg_f3,
		   rg_addr,
		   rg_pa,
		   rg_st_amo_val);
	else
	  $display("%0d: %s: rl_io_AMO_SC_req; f3 0x%0h  vaddr %0h  paddr %0h  word64 0x%0h",
		   v__h26255,
		   "I_MMU_Cache",
		   rg_f3,
		   rg_addr,
		   rg_pa,
		   rg_st_amo_val);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_io_AMO_SC_req &&
	  NOT_cfg_verbosity_read__0_ULE_1_1___d12)
	$display("    FAIL due to I/O address.");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_io_AMO_SC_req &&
	  NOT_cfg_verbosity_read__0_ULE_1_1___d12)
	$display("    => rl_ST_AMO_response");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_start_reset &&
	  NOT_cfg_verbosity_read__0_ULE_1_1___d12)
	begin
	  v__h3369 = $stime;
	  #0;
	end
    v__h3363 = v__h3369 / 32'd10;
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_start_reset &&
	  NOT_cfg_verbosity_read__0_ULE_1_1___d12)
	if (dmem_not_imem)
	  $display("%0d: %s.rl_start_reset", v__h3363, "D_MMU_Cache");
	else
	  $display("%0d: %s.rl_start_reset", v__h3363, "I_MMU_Cache");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
	  NOT_cfg_verbosity_read__0_ULE_1_1___d12)
	begin
	  v__h4286 = $stime;
	  #0;
	end
    v__h4280 = v__h4286 / 32'd10;
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
	  NOT_cfg_verbosity_read__0_ULE_1_1___d12)
	if (dmem_not_imem)
	  $display("%0d: %s: rl_probe_and_immed_rsp; eaddr %0h",
		   v__h4280,
		   "D_MMU_Cache",
		   rg_addr);
	else
	  $display("%0d: %s: rl_probe_and_immed_rsp; eaddr %0h",
		   v__h4280,
		   "I_MMU_Cache",
		   rg_addr);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
	  NOT_cfg_verbosity_read__0_ULE_1_1___d12)
	$display("        eaddr = {CTag 0x%0h  CSet 0x%0h  Word64 0x%0h  Byte 0x%0h}",
		 rg_addr[63:12],
		 rg_addr[11:6],
		 rg_addr[5:3],
		 rg_addr[2:0]);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
	  NOT_cfg_verbosity_read__0_ULE_1_1___d12)
	$write("        CSet 0x%0x: (state, tag):", rg_addr[11:6]);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
	  NOT_cfg_verbosity_read__0_ULE_1_1___d12)
	$write(" (");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
	  NOT_cfg_verbosity_read__0_ULE_1_1___d12 &&
	  ram_state_and_ctag_cset$DOB[52])
	$write("CTAG_CLEAN");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
	  NOT_cfg_verbosity_read__0_ULE_1_1___d12 &&
	  !ram_state_and_ctag_cset$DOB[52])
	$write("CTAG_EMPTY");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
	  NOT_cfg_verbosity_read__0_ULE_1_1___d12 &&
	  ram_state_and_ctag_cset$DOB[52])
	$write(", 0x%0x", ram_state_and_ctag_cset$DOB[51:0]);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
	  NOT_cfg_verbosity_read__0_ULE_1_1___d12 &&
	  !ram_state_and_ctag_cset$DOB[52])
	$write(", --");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
	  NOT_cfg_verbosity_read__0_ULE_1_1___d12)
	$write(")");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
	  NOT_cfg_verbosity_read__0_ULE_1_1___d12)
	$write("\n");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
	  NOT_cfg_verbosity_read__0_ULE_1_1___d12)
	$write("        CSet 0x%0x, Word64 0x%0x: ",
	       rg_addr[11:6],
	       rg_addr[5:3]);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
	  NOT_cfg_verbosity_read__0_ULE_1_1___d12)
	$write(" 0x%0x", ram_word64_set$DOB);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
	  NOT_cfg_verbosity_read__0_ULE_1_1___d12)
	$write("\n");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
	  NOT_cfg_verbosity_read__0_ULE_1_1___d12)
	$write("    TLB result: ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
	  NOT_cfg_verbosity_read__0_ULE_1_1___d12)
	$write("VM_Xlate_Result { ", "outcome: ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
	  NOT_cfg_verbosity_read__0_ULE_1_1___d12)
	$write("VM_XLATE_OK");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
	  NOT_cfg_verbosity_read__0_ULE_1_1___d12)
	$write(", ", "pa: ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
	  NOT_cfg_verbosity_read__0_ULE_1_1___d12)
	$write("'h%h", rg_addr);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
	  NOT_cfg_verbosity_read__0_ULE_1_1___d12)
	$write(", ", "exc_code: ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
	  NOT_cfg_verbosity_read__0_ULE_1_1___d12)
	$write("'h%h", 4'hA, " }");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
	  NOT_cfg_verbosity_read__0_ULE_1_1___d12)
	$write("\n");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_probe_and_immed_rsp && dmem_not_imem &&
	  !soc_map$m_is_mem_addr &&
	  NOT_cfg_verbosity_read__0_ULE_1_1___d12)
	$display("    => IO_REQ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
	  (!dmem_not_imem || soc_map$m_is_mem_addr) &&
	  rg_op_4_EQ_0_5_OR_rg_op_4_EQ_2_6_AND_rg_amo_fu_ETC___d275)
	begin
	  v__h12754 = $stime;
	  #0;
	end
    v__h12748 = v__h12754 / 32'd10;
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
	  (!dmem_not_imem || soc_map$m_is_mem_addr) &&
	  rg_op_4_EQ_0_5_OR_rg_op_4_EQ_2_6_AND_rg_amo_fu_ETC___d275)
	if (dmem_not_imem)
	  $display("%0d: %s.drive_mem_rsp: addr 0x%0h ld_val 0x%0h st_amo_val 0x%0h",
		   v__h12748,
		   "D_MMU_Cache",
		   rg_addr,
		   word64__h5281,
		   64'd0);
	else
	  $display("%0d: %s.drive_mem_rsp: addr 0x%0h ld_val 0x%0h st_amo_val 0x%0h",
		   v__h12748,
		   "I_MMU_Cache",
		   rg_addr,
		   word64__h5281,
		   64'd0);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
	  (!dmem_not_imem || soc_map$m_is_mem_addr) &&
	  rg_op == 2'd2 &&
	  rg_amo_funct7[6:2] == 5'b00010 &&
	  ram_state_and_ctag_cset$DOB[52] &&
	  ram_state_and_ctag_cset_b_read__9_BITS_51_TO_0_ETC___d74 &&
	  NOT_cfg_verbosity_read__0_ULE_1_1___d12)
	$display("        AMO LR: reserving PA 0x%0h", rg_addr);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
	  (!dmem_not_imem || soc_map$m_is_mem_addr) &&
	  rg_op_4_EQ_0_5_OR_rg_op_4_EQ_2_6_AND_rg_amo_fu_ETC___d275)
	$display("        Read-hit: addr 0x%0h word64 0x%0h",
		 rg_addr,
		 word64__h5281);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
	  (!dmem_not_imem || soc_map$m_is_mem_addr) &&
	  rg_op_4_EQ_0_5_OR_rg_op_4_EQ_2_6_AND_rg_amo_fu_ETC___d288)
	$display("        Read Miss: -> CACHE_START_REFILL.");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
	  (!dmem_not_imem || soc_map$m_is_mem_addr) &&
	  rg_op == 2'd2 &&
	  rg_amo_funct7_7_BITS_6_TO_2_8_EQ_0b10_9_AND_NO_ETC___d292)
	$display("        AMO LR: cache refill: cancelling LR/SC reservation for PA 0x%0h",
		 rg_lrsc_pa);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
	  NOT_dmem_not_imem_13_OR_soc_map_m_is_mem_addr__ETC___d479)
	$display("        ST: cancelling LR/SC reservation for PA", rg_addr);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
	  (!dmem_not_imem || soc_map$m_is_mem_addr) &&
	  rg_op == 2'd2 &&
	  rg_amo_funct7[6:2] == 5'b00011 &&
	  rg_lrsc_valid &&
	  !rg_lrsc_pa_8_EQ_rg_addr_0___d59 &&
	  NOT_cfg_verbosity_read__0_ULE_1_1___d12)
	$display("        AMO SC: fail: reserved addr 0x%0h, this address 0x%0h",
		 rg_lrsc_pa,
		 rg_addr);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
	  (!dmem_not_imem || soc_map$m_is_mem_addr) &&
	  rg_op == 2'd2 &&
	  rg_amo_funct7[6:2] == 5'b00011 &&
	  !rg_lrsc_valid &&
	  NOT_cfg_verbosity_read__0_ULE_1_1___d12)
	$display("        AMO SC: fail due to invalid LR/SC reservation");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
	  NOT_dmem_not_imem_13_OR_soc_map_m_is_mem_addr__ETC___d491)
	$display("        AMO SC result = %0d", lrsc_result__h13131);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
	  (!dmem_not_imem || soc_map$m_is_mem_addr) &&
	  NOT_rg_op_4_EQ_0_5_2_AND_NOT_rg_op_4_EQ_2_6_3__ETC___d494)
	$display("        Write-Cache-Hit: pa 0x%0h word64 0x%0h",
		 rg_addr,
		 rg_st_amo_val);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
	  (!dmem_not_imem || soc_map$m_is_mem_addr) &&
	  NOT_rg_op_4_EQ_0_5_2_AND_NOT_rg_op_4_EQ_2_6_3__ETC___d494)
	$write("        New Word64_Set:");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
	  (!dmem_not_imem || soc_map$m_is_mem_addr) &&
	  NOT_rg_op_4_EQ_0_5_2_AND_NOT_rg_op_4_EQ_2_6_3__ETC___d494)
	$write("        CSet 0x%0x, Word64 0x%0x: ",
	       rg_addr[11:6],
	       rg_addr[5:3]);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
	  (!dmem_not_imem || soc_map$m_is_mem_addr) &&
	  NOT_rg_op_4_EQ_0_5_2_AND_NOT_rg_op_4_EQ_2_6_3__ETC___d494)
	$write(" 0x%0x",
	       IF_rg_f3_38_EQ_0b0_39_THEN_IF_rg_addr_0_BITS_2_ETC___d360);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
	  (!dmem_not_imem || soc_map$m_is_mem_addr) &&
	  NOT_rg_op_4_EQ_0_5_2_AND_NOT_rg_op_4_EQ_2_6_3__ETC___d494)
	$write("\n");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
	  (!dmem_not_imem || soc_map$m_is_mem_addr) &&
	  rg_op != 2'd0 &&
	  (rg_op != 2'd2 || rg_amo_funct7[6:2] != 5'b00010) &&
	  (rg_op == 2'd1 ||
	   rg_op == 2'd2 && rg_amo_funct7[6:2] == 5'b00011) &&
	  NOT_rg_op_4_EQ_2_6_3_OR_NOT_rg_amo_funct7_7_BI_ETC___d496)
	$display("        Write-Cache-Miss: pa 0x%0h word64 0x%0h",
		 rg_addr,
		 rg_st_amo_val);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
	  (!dmem_not_imem || soc_map$m_is_mem_addr) &&
	  NOT_rg_op_4_EQ_0_5_2_AND_NOT_rg_op_4_EQ_2_6_3__ETC___d502)
	$display("        Write-Cache-Hit/Miss: eaddr 0x%0h word64 0x%0h",
		 rg_addr,
		 rg_st_amo_val);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
	  (!dmem_not_imem || soc_map$m_is_mem_addr) &&
	  NOT_rg_op_4_EQ_0_5_2_AND_NOT_rg_op_4_EQ_2_6_3__ETC___d507)
	begin
	  v__h17070 = $stime;
	  #0;
	end
    v__h17064 = v__h17070 / 32'd10;
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
	  (!dmem_not_imem || soc_map$m_is_mem_addr) &&
	  NOT_rg_op_4_EQ_0_5_2_AND_NOT_rg_op_4_EQ_2_6_3__ETC___d507)
	$display("%0d: ERROR: CreditCounter: overflow", v__h17064);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
	  (!dmem_not_imem || soc_map$m_is_mem_addr) &&
	  NOT_rg_op_4_EQ_0_5_2_AND_NOT_rg_op_4_EQ_2_6_3__ETC___d507)
	$finish(32'd1);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
	  (!dmem_not_imem || soc_map$m_is_mem_addr) &&
	  NOT_rg_op_4_EQ_0_5_2_AND_NOT_rg_op_4_EQ_2_6_3__ETC___d502)
	$write("            To fabric: ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
	  (!dmem_not_imem || soc_map$m_is_mem_addr) &&
	  NOT_rg_op_4_EQ_0_5_2_AND_NOT_rg_op_4_EQ_2_6_3__ETC___d502)
	$write("AXI4_Wr_Addr { ", "awid: ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
	  (!dmem_not_imem || soc_map$m_is_mem_addr) &&
	  NOT_rg_op_4_EQ_0_5_2_AND_NOT_rg_op_4_EQ_2_6_3__ETC___d502)
	$write("'h%h", 4'd0);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
	  (!dmem_not_imem || soc_map$m_is_mem_addr) &&
	  NOT_rg_op_4_EQ_0_5_2_AND_NOT_rg_op_4_EQ_2_6_3__ETC___d502)
	$write(", ", "awaddr: ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
	  (!dmem_not_imem || soc_map$m_is_mem_addr) &&
	  NOT_rg_op_4_EQ_0_5_2_AND_NOT_rg_op_4_EQ_2_6_3__ETC___d502)
	$write("'h%h", rg_addr);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
	  (!dmem_not_imem || soc_map$m_is_mem_addr) &&
	  NOT_rg_op_4_EQ_0_5_2_AND_NOT_rg_op_4_EQ_2_6_3__ETC___d502)
	$write(", ", "awlen: ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
	  (!dmem_not_imem || soc_map$m_is_mem_addr) &&
	  NOT_rg_op_4_EQ_0_5_2_AND_NOT_rg_op_4_EQ_2_6_3__ETC___d502)
	$write("'h%h", 8'd0);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
	  (!dmem_not_imem || soc_map$m_is_mem_addr) &&
	  NOT_rg_op_4_EQ_0_5_2_AND_NOT_rg_op_4_EQ_2_6_3__ETC___d502)
	$write(", ", "awsize: ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
	  (!dmem_not_imem || soc_map$m_is_mem_addr) &&
	  NOT_rg_op_4_EQ_0_5_2_AND_NOT_rg_op_4_EQ_2_6_3__ETC___d502)
	$write("'h%h", value__h29609);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
	  (!dmem_not_imem || soc_map$m_is_mem_addr) &&
	  NOT_rg_op_4_EQ_0_5_2_AND_NOT_rg_op_4_EQ_2_6_3__ETC___d502)
	$write(", ", "awburst: ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
	  (!dmem_not_imem || soc_map$m_is_mem_addr) &&
	  NOT_rg_op_4_EQ_0_5_2_AND_NOT_rg_op_4_EQ_2_6_3__ETC___d502)
	$write("'h%h", 2'b01);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
	  (!dmem_not_imem || soc_map$m_is_mem_addr) &&
	  NOT_rg_op_4_EQ_0_5_2_AND_NOT_rg_op_4_EQ_2_6_3__ETC___d502)
	$write(", ", "awlock: ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
	  (!dmem_not_imem || soc_map$m_is_mem_addr) &&
	  NOT_rg_op_4_EQ_0_5_2_AND_NOT_rg_op_4_EQ_2_6_3__ETC___d502)
	$write("'h%h", 1'b0);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
	  (!dmem_not_imem || soc_map$m_is_mem_addr) &&
	  NOT_rg_op_4_EQ_0_5_2_AND_NOT_rg_op_4_EQ_2_6_3__ETC___d502)
	$write(", ", "awcache: ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
	  (!dmem_not_imem || soc_map$m_is_mem_addr) &&
	  NOT_rg_op_4_EQ_0_5_2_AND_NOT_rg_op_4_EQ_2_6_3__ETC___d502)
	$write("'h%h", 4'b0);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
	  (!dmem_not_imem || soc_map$m_is_mem_addr) &&
	  NOT_rg_op_4_EQ_0_5_2_AND_NOT_rg_op_4_EQ_2_6_3__ETC___d502)
	$write(", ", "awprot: ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
	  (!dmem_not_imem || soc_map$m_is_mem_addr) &&
	  NOT_rg_op_4_EQ_0_5_2_AND_NOT_rg_op_4_EQ_2_6_3__ETC___d502)
	$write("'h%h", 3'd0);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
	  (!dmem_not_imem || soc_map$m_is_mem_addr) &&
	  NOT_rg_op_4_EQ_0_5_2_AND_NOT_rg_op_4_EQ_2_6_3__ETC___d502)
	$write(", ", "awqos: ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
	  (!dmem_not_imem || soc_map$m_is_mem_addr) &&
	  NOT_rg_op_4_EQ_0_5_2_AND_NOT_rg_op_4_EQ_2_6_3__ETC___d502)
	$write("'h%h", 4'd0);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
	  (!dmem_not_imem || soc_map$m_is_mem_addr) &&
	  NOT_rg_op_4_EQ_0_5_2_AND_NOT_rg_op_4_EQ_2_6_3__ETC___d502)
	$write(", ", "awregion: ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
	  (!dmem_not_imem || soc_map$m_is_mem_addr) &&
	  NOT_rg_op_4_EQ_0_5_2_AND_NOT_rg_op_4_EQ_2_6_3__ETC___d502)
	$write("'h%h", 4'd0);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
	  (!dmem_not_imem || soc_map$m_is_mem_addr) &&
	  NOT_rg_op_4_EQ_0_5_2_AND_NOT_rg_op_4_EQ_2_6_3__ETC___d502)
	$write(", ", "awuser: ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
	  (!dmem_not_imem || soc_map$m_is_mem_addr) &&
	  NOT_rg_op_4_EQ_0_5_2_AND_NOT_rg_op_4_EQ_2_6_3__ETC___d502)
	$write("'h%h", 1'h0, " }");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
	  (!dmem_not_imem || soc_map$m_is_mem_addr) &&
	  NOT_rg_op_4_EQ_0_5_2_AND_NOT_rg_op_4_EQ_2_6_3__ETC___d502)
	$write("\n");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
	  (!dmem_not_imem || soc_map$m_is_mem_addr) &&
	  NOT_rg_op_4_EQ_0_5_2_AND_NOT_rg_op_4_EQ_2_6_3__ETC___d502)
	$write("                       ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
	  (!dmem_not_imem || soc_map$m_is_mem_addr) &&
	  NOT_rg_op_4_EQ_0_5_2_AND_NOT_rg_op_4_EQ_2_6_3__ETC___d502)
	$write("AXI4_Wr_Data { ", "wid: ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
	  (!dmem_not_imem || soc_map$m_is_mem_addr) &&
	  NOT_rg_op_4_EQ_0_5_2_AND_NOT_rg_op_4_EQ_2_6_3__ETC___d502)
	$write("'h%h", 4'd0);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
	  (!dmem_not_imem || soc_map$m_is_mem_addr) &&
	  NOT_rg_op_4_EQ_0_5_2_AND_NOT_rg_op_4_EQ_2_6_3__ETC___d502)
	$write(", ", "wdata: ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
	  (!dmem_not_imem || soc_map$m_is_mem_addr) &&
	  NOT_rg_op_4_EQ_0_5_2_AND_NOT_rg_op_4_EQ_2_6_3__ETC___d502)
	$write("'h%h", mem_req_wr_data_wdata__h16835);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
	  (!dmem_not_imem || soc_map$m_is_mem_addr) &&
	  NOT_rg_op_4_EQ_0_5_2_AND_NOT_rg_op_4_EQ_2_6_3__ETC___d502)
	$write(", ", "wstrb: ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
	  (!dmem_not_imem || soc_map$m_is_mem_addr) &&
	  NOT_rg_op_4_EQ_0_5_2_AND_NOT_rg_op_4_EQ_2_6_3__ETC___d502)
	$write("'h%h", mem_req_wr_data_wstrb__h20333);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
	  (!dmem_not_imem || soc_map$m_is_mem_addr) &&
	  NOT_rg_op_4_EQ_0_5_2_AND_NOT_rg_op_4_EQ_2_6_3__ETC___d502)
	$write(", ", "wlast: ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
	  (!dmem_not_imem || soc_map$m_is_mem_addr) &&
	  NOT_rg_op_4_EQ_0_5_2_AND_NOT_rg_op_4_EQ_2_6_3__ETC___d502)
	$write("True");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
	  (!dmem_not_imem || soc_map$m_is_mem_addr) &&
	  NOT_rg_op_4_EQ_0_5_2_AND_NOT_rg_op_4_EQ_2_6_3__ETC___d502)
	$write(", ", "wuser: ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
	  (!dmem_not_imem || soc_map$m_is_mem_addr) &&
	  NOT_rg_op_4_EQ_0_5_2_AND_NOT_rg_op_4_EQ_2_6_3__ETC___d502)
	$write("'h%h", 1'h0, " }");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
	  (!dmem_not_imem || soc_map$m_is_mem_addr) &&
	  NOT_rg_op_4_EQ_0_5_2_AND_NOT_rg_op_4_EQ_2_6_3__ETC___d502)
	$write("\n");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
	  (!dmem_not_imem || soc_map$m_is_mem_addr) &&
	  NOT_rg_op_4_EQ_0_5_2_AND_NOT_rg_op_4_EQ_2_6_3__ETC___d502)
	$display("        => rl_write_response");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
	  (!dmem_not_imem || soc_map$m_is_mem_addr) &&
	  rg_op_4_EQ_2_6_AND_rg_amo_funct7_7_BITS_6_TO_2_ETC___d513)
	begin
	  v__h16398 = $stime;
	  #0;
	end
    v__h16392 = v__h16398 / 32'd10;
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
	  (!dmem_not_imem || soc_map$m_is_mem_addr) &&
	  rg_op_4_EQ_2_6_AND_rg_amo_funct7_7_BITS_6_TO_2_ETC___d513)
	if (dmem_not_imem)
	  $display("%0d: %s.drive_mem_rsp: addr 0x%0h ld_val 0x%0h st_amo_val 0x%0h",
		   v__h16392,
		   "D_MMU_Cache",
		   rg_addr,
		   64'd1,
		   64'd0);
	else
	  $display("%0d: %s.drive_mem_rsp: addr 0x%0h ld_val 0x%0h st_amo_val 0x%0h",
		   v__h16392,
		   "I_MMU_Cache",
		   rg_addr,
		   64'd1,
		   64'd0);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
	  (!dmem_not_imem || soc_map$m_is_mem_addr) &&
	  rg_op_4_EQ_2_6_AND_rg_amo_funct7_7_BITS_6_TO_2_ETC___d513)
	$display("        AMO SC: Fail response for addr 0x%0h", rg_addr);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
	  NOT_dmem_not_imem_13_OR_soc_map_m_is_mem_addr__ETC___d519)
	$display("        AMO Miss: -> CACHE_START_REFILL.");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
	  NOT_dmem_not_imem_13_OR_soc_map_m_is_mem_addr__ETC___d522)
	$display("        AMO: addr 0x%0h amo_f7 0x%0h f3 %0d rs2_val 0x%0h",
		 rg_addr,
		 rg_amo_funct7,
		 rg_f3,
		 rg_st_amo_val);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
	  NOT_dmem_not_imem_13_OR_soc_map_m_is_mem_addr__ETC___d522)
	$display("          PA 0x%0h ", rg_addr);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
	  NOT_dmem_not_imem_13_OR_soc_map_m_is_mem_addr__ETC___d522)
	$display("          Cache word64 0x%0h, load-result 0x%0h",
		 word64__h5281,
		 word64__h5281);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
	  NOT_dmem_not_imem_13_OR_soc_map_m_is_mem_addr__ETC___d522)
	$display("          0x%0h  op  0x%0h -> 0x%0h",
		 word64__h5281,
		 word64__h5281,
		 new_st_val__h17351);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
	  NOT_dmem_not_imem_13_OR_soc_map_m_is_mem_addr__ETC___d522)
	$write("          New Word64_Set:");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
	  NOT_dmem_not_imem_13_OR_soc_map_m_is_mem_addr__ETC___d522)
	$write("        CSet 0x%0x, Word64 0x%0x: ",
	       rg_addr[11:6],
	       rg_addr[5:3]);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
	  NOT_dmem_not_imem_13_OR_soc_map_m_is_mem_addr__ETC___d522)
	$write(" 0x%0x",
	       IF_rg_f3_38_EQ_0b0_39_THEN_IF_rg_addr_0_BITS_2_ETC___d434);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
	  NOT_dmem_not_imem_13_OR_soc_map_m_is_mem_addr__ETC___d522)
	$write("\n");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
	  NOT_dmem_not_imem_13_OR_soc_map_m_is_mem_addr__ETC___d526)
	begin
	  v__h20536 = $stime;
	  #0;
	end
    v__h20530 = v__h20536 / 32'd10;
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
	  NOT_dmem_not_imem_13_OR_soc_map_m_is_mem_addr__ETC___d526)
	$display("%0d: ERROR: CreditCounter: overflow", v__h20530);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
	  NOT_dmem_not_imem_13_OR_soc_map_m_is_mem_addr__ETC___d526)
	$finish(32'd1);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
	  NOT_dmem_not_imem_13_OR_soc_map_m_is_mem_addr__ETC___d522)
	$write("            To fabric: ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
	  NOT_dmem_not_imem_13_OR_soc_map_m_is_mem_addr__ETC___d522)
	$write("AXI4_Wr_Addr { ", "awid: ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
	  NOT_dmem_not_imem_13_OR_soc_map_m_is_mem_addr__ETC___d522)
	$write("'h%h", 4'd0);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
	  NOT_dmem_not_imem_13_OR_soc_map_m_is_mem_addr__ETC___d522)
	$write(", ", "awaddr: ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
	  NOT_dmem_not_imem_13_OR_soc_map_m_is_mem_addr__ETC___d522)
	$write("'h%h", rg_addr);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
	  NOT_dmem_not_imem_13_OR_soc_map_m_is_mem_addr__ETC___d522)
	$write(", ", "awlen: ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
	  NOT_dmem_not_imem_13_OR_soc_map_m_is_mem_addr__ETC___d522)
	$write("'h%h", 8'd0);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
	  NOT_dmem_not_imem_13_OR_soc_map_m_is_mem_addr__ETC___d522)
	$write(", ", "awsize: ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
	  NOT_dmem_not_imem_13_OR_soc_map_m_is_mem_addr__ETC___d522)
	$write("'h%h", value__h29609);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
	  NOT_dmem_not_imem_13_OR_soc_map_m_is_mem_addr__ETC___d522)
	$write(", ", "awburst: ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
	  NOT_dmem_not_imem_13_OR_soc_map_m_is_mem_addr__ETC___d522)
	$write("'h%h", 2'b01);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
	  NOT_dmem_not_imem_13_OR_soc_map_m_is_mem_addr__ETC___d522)
	$write(", ", "awlock: ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
	  NOT_dmem_not_imem_13_OR_soc_map_m_is_mem_addr__ETC___d522)
	$write("'h%h", 1'b0);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
	  NOT_dmem_not_imem_13_OR_soc_map_m_is_mem_addr__ETC___d522)
	$write(", ", "awcache: ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
	  NOT_dmem_not_imem_13_OR_soc_map_m_is_mem_addr__ETC___d522)
	$write("'h%h", 4'b0);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
	  NOT_dmem_not_imem_13_OR_soc_map_m_is_mem_addr__ETC___d522)
	$write(", ", "awprot: ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
	  NOT_dmem_not_imem_13_OR_soc_map_m_is_mem_addr__ETC___d522)
	$write("'h%h", 3'd0);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
	  NOT_dmem_not_imem_13_OR_soc_map_m_is_mem_addr__ETC___d522)
	$write(", ", "awqos: ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
	  NOT_dmem_not_imem_13_OR_soc_map_m_is_mem_addr__ETC___d522)
	$write("'h%h", 4'd0);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
	  NOT_dmem_not_imem_13_OR_soc_map_m_is_mem_addr__ETC___d522)
	$write(", ", "awregion: ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
	  NOT_dmem_not_imem_13_OR_soc_map_m_is_mem_addr__ETC___d522)
	$write("'h%h", 4'd0);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
	  NOT_dmem_not_imem_13_OR_soc_map_m_is_mem_addr__ETC___d522)
	$write(", ", "awuser: ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
	  NOT_dmem_not_imem_13_OR_soc_map_m_is_mem_addr__ETC___d522)
	$write("'h%h", 1'h0, " }");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
	  NOT_dmem_not_imem_13_OR_soc_map_m_is_mem_addr__ETC___d522)
	$write("\n");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
	  NOT_dmem_not_imem_13_OR_soc_map_m_is_mem_addr__ETC___d522)
	$write("                       ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
	  NOT_dmem_not_imem_13_OR_soc_map_m_is_mem_addr__ETC___d522)
	$write("AXI4_Wr_Data { ", "wid: ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
	  NOT_dmem_not_imem_13_OR_soc_map_m_is_mem_addr__ETC___d522)
	$write("'h%h", 4'd0);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
	  NOT_dmem_not_imem_13_OR_soc_map_m_is_mem_addr__ETC___d522)
	$write(", ", "wdata: ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
	  NOT_dmem_not_imem_13_OR_soc_map_m_is_mem_addr__ETC___d522)
	$write("'h%h", mem_req_wr_data_wdata__h20332);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
	  NOT_dmem_not_imem_13_OR_soc_map_m_is_mem_addr__ETC___d522)
	$write(", ", "wstrb: ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
	  NOT_dmem_not_imem_13_OR_soc_map_m_is_mem_addr__ETC___d522)
	$write("'h%h", mem_req_wr_data_wstrb__h20333);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
	  NOT_dmem_not_imem_13_OR_soc_map_m_is_mem_addr__ETC___d522)
	$write(", ", "wlast: ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
	  NOT_dmem_not_imem_13_OR_soc_map_m_is_mem_addr__ETC___d522)
	$write("True");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
	  NOT_dmem_not_imem_13_OR_soc_map_m_is_mem_addr__ETC___d522)
	$write(", ", "wuser: ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
	  NOT_dmem_not_imem_13_OR_soc_map_m_is_mem_addr__ETC___d522)
	$write("'h%h", 1'h0, " }");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
	  NOT_dmem_not_imem_13_OR_soc_map_m_is_mem_addr__ETC___d522)
	$write("\n");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
	  NOT_dmem_not_imem_13_OR_soc_map_m_is_mem_addr__ETC___d532)
	$display("        AMO_op: cancelling LR/SC reservation for PA",
		 rg_addr);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_cache_refill_rsps_loop &&
	  NOT_cfg_verbosity_read__0_ULE_2_54___d555)
	begin
	  v__h21830 = $stime;
	  #0;
	end
    v__h21824 = v__h21830 / 32'd10;
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_cache_refill_rsps_loop &&
	  NOT_cfg_verbosity_read__0_ULE_2_54___d555)
	if (dmem_not_imem)
	  $display("%0d: %s.rl_cache_refill_rsps_loop:",
		   v__h21824,
		   "D_MMU_Cache");
	else
	  $display("%0d: %s.rl_cache_refill_rsps_loop:",
		   v__h21824,
		   "I_MMU_Cache");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_cache_refill_rsps_loop &&
	  NOT_cfg_verbosity_read__0_ULE_2_54___d555)
	$write("        ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_cache_refill_rsps_loop &&
	  NOT_cfg_verbosity_read__0_ULE_2_54___d555)
	$write("AXI4_Rd_Data { ", "rid: ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_cache_refill_rsps_loop &&
	  NOT_cfg_verbosity_read__0_ULE_2_54___d555)
	$write("'h%h", master_xactor_rg_rd_data[70:67]);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_cache_refill_rsps_loop &&
	  NOT_cfg_verbosity_read__0_ULE_2_54___d555)
	$write(", ", "rdata: ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_cache_refill_rsps_loop &&
	  NOT_cfg_verbosity_read__0_ULE_2_54___d555)
	$write("'h%h", master_xactor_rg_rd_data[66:3]);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_cache_refill_rsps_loop &&
	  NOT_cfg_verbosity_read__0_ULE_2_54___d555)
	$write(", ", "rresp: ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_cache_refill_rsps_loop &&
	  NOT_cfg_verbosity_read__0_ULE_2_54___d555)
	$write("'h%h", master_xactor_rg_rd_data[2:1]);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_cache_refill_rsps_loop &&
	  NOT_cfg_verbosity_read__0_ULE_2_54___d555)
	$write(", ", "rlast: ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_cache_refill_rsps_loop &&
	  NOT_cfg_verbosity_read__0_ULE_2_54___d555 &&
	  master_xactor_rg_rd_data[0])
	$write("True");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_cache_refill_rsps_loop &&
	  NOT_cfg_verbosity_read__0_ULE_2_54___d555 &&
	  !master_xactor_rg_rd_data[0])
	$write("False");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_cache_refill_rsps_loop &&
	  NOT_cfg_verbosity_read__0_ULE_2_54___d555)
	$write(", ", "ruser: ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_cache_refill_rsps_loop &&
	  NOT_cfg_verbosity_read__0_ULE_2_54___d555)
	$write("'h%h", 1'd0, " }");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_cache_refill_rsps_loop &&
	  NOT_cfg_verbosity_read__0_ULE_2_54___d555)
	$write("\n");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_cache_refill_rsps_loop &&
	  master_xactor_rg_rd_data[2:1] != 2'b0 &&
	  NOT_cfg_verbosity_read__0_ULE_1_1___d12)
	begin
	  v__h22071 = $stime;
	  #0;
	end
    v__h22065 = v__h22071 / 32'd10;
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_cache_refill_rsps_loop &&
	  master_xactor_rg_rd_data[2:1] != 2'b0 &&
	  NOT_cfg_verbosity_read__0_ULE_1_1___d12)
	if (dmem_not_imem)
	  $display("%0d: %s.rl_cache_refill_rsps_loop: FABRIC_RSP_ERR: raising access exception %0d",
		   v__h22065,
		   "D_MMU_Cache",
		   access_exc_code__h2925);
	else
	  $display("%0d: %s.rl_cache_refill_rsps_loop: FABRIC_RSP_ERR: raising access exception %0d",
		   v__h22065,
		   "I_MMU_Cache",
		   access_exc_code__h2925);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_cache_refill_rsps_loop &&
	  rg_word64_set_in_cache[2:0] == 3'd7 &&
	  (master_xactor_rg_rd_data[2:1] != 2'b0 || rg_error_during_refill) &&
	  NOT_cfg_verbosity_read__0_ULE_1_1___d12)
	$display("    => MODULE_EXCEPTION_RSP");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_cache_refill_rsps_loop &&
	  rg_word64_set_in_cache[2:0] == 3'd7 &&
	  master_xactor_rg_rd_data[2:1] == 2'b0 &&
	  !rg_error_during_refill &&
	  NOT_cfg_verbosity_read__0_ULE_1_1___d12)
	$display("    => CACHE_REREQ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_cache_refill_rsps_loop &&
	  NOT_cfg_verbosity_read__0_ULE_2_54___d555)
	$display("        Updating Cache word64_set 0x%0h, word64_in_cline %0d) old => new",
		 rg_word64_set_in_cache,
		 rg_word64_set_in_cache[2:0]);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_cache_refill_rsps_loop &&
	  NOT_cfg_verbosity_read__0_ULE_2_54___d555)
	$write("        CSet 0x%0x, Word64 0x%0x: ",
	       rg_addr[11:6],
	       rg_word64_set_in_cache[2:0]);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_cache_refill_rsps_loop &&
	  NOT_cfg_verbosity_read__0_ULE_2_54___d555)
	$write(" 0x%0x", ram_word64_set$DOB);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_cache_refill_rsps_loop &&
	  NOT_cfg_verbosity_read__0_ULE_2_54___d555)
	$write("\n");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_cache_refill_rsps_loop &&
	  NOT_cfg_verbosity_read__0_ULE_2_54___d555)
	$write("        CSet 0x%0x, Word64 0x%0x: ",
	       rg_addr[11:6],
	       rg_word64_set_in_cache[2:0]);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_cache_refill_rsps_loop &&
	  NOT_cfg_verbosity_read__0_ULE_2_54___d555)
	$write(" 0x%0x", master_xactor_rg_rd_data[66:3]);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_cache_refill_rsps_loop &&
	  NOT_cfg_verbosity_read__0_ULE_2_54___d555)
	$write("\n");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_io_read_rsp &&
	  NOT_cfg_verbosity_read__0_ULE_1_1___d12)
	begin
	  v__h24049 = $stime;
	  #0;
	end
    v__h24043 = v__h24049 / 32'd10;
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_io_read_rsp &&
	  NOT_cfg_verbosity_read__0_ULE_1_1___d12)
	if (dmem_not_imem)
	  $display("%0d: %s.rl_io_read_rsp: vaddr 0x%0h  paddr 0x%0h",
		   v__h24043,
		   "D_MMU_Cache",
		   rg_addr,
		   rg_pa);
	else
	  $display("%0d: %s.rl_io_read_rsp: vaddr 0x%0h  paddr 0x%0h",
		   v__h24043,
		   "I_MMU_Cache",
		   rg_addr,
		   rg_pa);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_io_read_rsp &&
	  NOT_cfg_verbosity_read__0_ULE_1_1___d12)
	$write("    ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_io_read_rsp &&
	  NOT_cfg_verbosity_read__0_ULE_1_1___d12)
	$write("AXI4_Rd_Data { ", "rid: ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_io_read_rsp &&
	  NOT_cfg_verbosity_read__0_ULE_1_1___d12)
	$write("'h%h", master_xactor_rg_rd_data[70:67]);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_io_read_rsp &&
	  NOT_cfg_verbosity_read__0_ULE_1_1___d12)
	$write(", ", "rdata: ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_io_read_rsp &&
	  NOT_cfg_verbosity_read__0_ULE_1_1___d12)
	$write("'h%h", master_xactor_rg_rd_data[66:3]);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_io_read_rsp &&
	  NOT_cfg_verbosity_read__0_ULE_1_1___d12)
	$write(", ", "rresp: ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_io_read_rsp &&
	  NOT_cfg_verbosity_read__0_ULE_1_1___d12)
	$write("'h%h", master_xactor_rg_rd_data[2:1]);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_io_read_rsp &&
	  NOT_cfg_verbosity_read__0_ULE_1_1___d12)
	$write(", ", "rlast: ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_io_read_rsp &&
	  NOT_cfg_verbosity_read__0_ULE_1_1___d12 &&
	  master_xactor_rg_rd_data[0])
	$write("True");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_io_read_rsp &&
	  NOT_cfg_verbosity_read__0_ULE_1_1___d12 &&
	  !master_xactor_rg_rd_data[0])
	$write("False");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_io_read_rsp &&
	  NOT_cfg_verbosity_read__0_ULE_1_1___d12)
	$write(", ", "ruser: ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_io_read_rsp &&
	  NOT_cfg_verbosity_read__0_ULE_1_1___d12)
	$write("'h%h", 1'd0, " }");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_io_read_rsp &&
	  NOT_cfg_verbosity_read__0_ULE_1_1___d12)
	$write("\n");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_io_read_rsp &&
	  master_xactor_rg_rd_data[2:1] == 2'b0 &&
	  NOT_cfg_verbosity_read__0_ULE_1_1___d12)
	begin
	  v__h25151 = $stime;
	  #0;
	end
    v__h25145 = v__h25151 / 32'd10;
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_io_read_rsp &&
	  master_xactor_rg_rd_data[2:1] == 2'b0 &&
	  NOT_cfg_verbosity_read__0_ULE_1_1___d12)
	if (dmem_not_imem)
	  $display("%0d: %s.drive_IO_read_rsp: addr 0x%0h ld_val 0x%0h",
		   v__h25145,
		   "D_MMU_Cache",
		   rg_addr,
		   ld_val__h24158);
	else
	  $display("%0d: %s.drive_IO_read_rsp: addr 0x%0h ld_val 0x%0h",
		   v__h25145,
		   "I_MMU_Cache",
		   rg_addr,
		   ld_val__h24158);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_io_read_rsp &&
	  master_xactor_rg_rd_data[2:1] != 2'b0 &&
	  NOT_cfg_verbosity_read__0_ULE_1_1___d12)
	begin
	  v__h25258 = $stime;
	  #0;
	end
    v__h25252 = v__h25258 / 32'd10;
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_io_read_rsp &&
	  master_xactor_rg_rd_data[2:1] != 2'b0 &&
	  NOT_cfg_verbosity_read__0_ULE_1_1___d12)
	if (dmem_not_imem)
	  $display("%0d: %s.rl_io_read_rsp: FABRIC_RSP_ERR: raising trap LOAD_ACCESS_FAULT",
		   v__h25252,
		   "D_MMU_Cache");
	else
	  $display("%0d: %s.rl_io_read_rsp: FABRIC_RSP_ERR: raising trap LOAD_ACCESS_FAULT",
		   v__h25252,
		   "I_MMU_Cache");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_io_write_req &&
	  NOT_cfg_verbosity_read__0_ULE_1_1___d12)
	begin
	  v__h25443 = $stime;
	  #0;
	end
    v__h25437 = v__h25443 / 32'd10;
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_io_write_req &&
	  NOT_cfg_verbosity_read__0_ULE_1_1___d12)
	if (dmem_not_imem)
	  $display("%0d: %s: rl_io_write_req; f3 0x%0h  vaddr %0h  paddr %0h  word64 0x%0h",
		   v__h25437,
		   "D_MMU_Cache",
		   rg_f3,
		   rg_addr,
		   rg_pa,
		   rg_st_amo_val);
	else
	  $display("%0d: %s: rl_io_write_req; f3 0x%0h  vaddr %0h  paddr %0h  word64 0x%0h",
		   v__h25437,
		   "I_MMU_Cache",
		   rg_f3,
		   rg_addr,
		   rg_pa,
		   rg_st_amo_val);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_io_write_req && ctr_wr_rsps_pending_crg == 4'd15)
	begin
	  v__h25965 = $stime;
	  #0;
	end
    v__h25959 = v__h25965 / 32'd10;
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_io_write_req && ctr_wr_rsps_pending_crg == 4'd15)
	$display("%0d: ERROR: CreditCounter: overflow", v__h25959);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_io_write_req && ctr_wr_rsps_pending_crg == 4'd15)
	$finish(32'd1);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_io_write_req &&
	  NOT_cfg_verbosity_read__0_ULE_1_1___d12)
	$write("            To fabric: ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_io_write_req &&
	  NOT_cfg_verbosity_read__0_ULE_1_1___d12)
	$write("AXI4_Wr_Addr { ", "awid: ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_io_write_req &&
	  NOT_cfg_verbosity_read__0_ULE_1_1___d12)
	$write("'h%h", 4'd0);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_io_write_req &&
	  NOT_cfg_verbosity_read__0_ULE_1_1___d12)
	$write(", ", "awaddr: ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_io_write_req &&
	  NOT_cfg_verbosity_read__0_ULE_1_1___d12)
	$write("'h%h", rg_pa);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_io_write_req &&
	  NOT_cfg_verbosity_read__0_ULE_1_1___d12)
	$write(", ", "awlen: ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_io_write_req &&
	  NOT_cfg_verbosity_read__0_ULE_1_1___d12)
	$write("'h%h", 8'd0);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_io_write_req &&
	  NOT_cfg_verbosity_read__0_ULE_1_1___d12)
	$write(", ", "awsize: ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_io_write_req &&
	  NOT_cfg_verbosity_read__0_ULE_1_1___d12)
	$write("'h%h", value__h29609);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_io_write_req &&
	  NOT_cfg_verbosity_read__0_ULE_1_1___d12)
	$write(", ", "awburst: ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_io_write_req &&
	  NOT_cfg_verbosity_read__0_ULE_1_1___d12)
	$write("'h%h", 2'b01);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_io_write_req &&
	  NOT_cfg_verbosity_read__0_ULE_1_1___d12)
	$write(", ", "awlock: ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_io_write_req &&
	  NOT_cfg_verbosity_read__0_ULE_1_1___d12)
	$write("'h%h", 1'b0);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_io_write_req &&
	  NOT_cfg_verbosity_read__0_ULE_1_1___d12)
	$write(", ", "awcache: ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_io_write_req &&
	  NOT_cfg_verbosity_read__0_ULE_1_1___d12)
	$write("'h%h", 4'b0);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_io_write_req &&
	  NOT_cfg_verbosity_read__0_ULE_1_1___d12)
	$write(", ", "awprot: ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_io_write_req &&
	  NOT_cfg_verbosity_read__0_ULE_1_1___d12)
	$write("'h%h", 3'd0);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_io_write_req &&
	  NOT_cfg_verbosity_read__0_ULE_1_1___d12)
	$write(", ", "awqos: ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_io_write_req &&
	  NOT_cfg_verbosity_read__0_ULE_1_1___d12)
	$write("'h%h", 4'd0);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_io_write_req &&
	  NOT_cfg_verbosity_read__0_ULE_1_1___d12)
	$write(", ", "awregion: ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_io_write_req &&
	  NOT_cfg_verbosity_read__0_ULE_1_1___d12)
	$write("'h%h", 4'd0);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_io_write_req &&
	  NOT_cfg_verbosity_read__0_ULE_1_1___d12)
	$write(", ", "awuser: ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_io_write_req &&
	  NOT_cfg_verbosity_read__0_ULE_1_1___d12)
	$write("'h%h", 1'h0, " }");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_io_write_req &&
	  NOT_cfg_verbosity_read__0_ULE_1_1___d12)
	$write("\n");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_io_write_req &&
	  NOT_cfg_verbosity_read__0_ULE_1_1___d12)
	$write("                       ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_io_write_req &&
	  NOT_cfg_verbosity_read__0_ULE_1_1___d12)
	$write("AXI4_Wr_Data { ", "wid: ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_io_write_req &&
	  NOT_cfg_verbosity_read__0_ULE_1_1___d12)
	$write("'h%h", 4'd0);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_io_write_req &&
	  NOT_cfg_verbosity_read__0_ULE_1_1___d12)
	$write(", ", "wdata: ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_io_write_req &&
	  NOT_cfg_verbosity_read__0_ULE_1_1___d12)
	$write("'h%h", mem_req_wr_data_wdata__h25761);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_io_write_req &&
	  NOT_cfg_verbosity_read__0_ULE_1_1___d12)
	$write(", ", "wstrb: ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_io_write_req &&
	  NOT_cfg_verbosity_read__0_ULE_1_1___d12)
	$write("'h%h", mem_req_wr_data_wstrb__h27266);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_io_write_req &&
	  NOT_cfg_verbosity_read__0_ULE_1_1___d12)
	$write(", ", "wlast: ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_io_write_req &&
	  NOT_cfg_verbosity_read__0_ULE_1_1___d12)
	$write("True");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_io_write_req &&
	  NOT_cfg_verbosity_read__0_ULE_1_1___d12)
	$write(", ", "wuser: ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_io_write_req &&
	  NOT_cfg_verbosity_read__0_ULE_1_1___d12)
	$write("'h%h", 1'h0, " }");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_io_write_req &&
	  NOT_cfg_verbosity_read__0_ULE_1_1___d12)
	$write("\n");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_io_write_req &&
	  NOT_cfg_verbosity_read__0_ULE_1_1___d12)
	$display("    => rl_ST_AMO_response");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_io_AMO_op_req &&
	  NOT_cfg_verbosity_read__0_ULE_1_1___d12)
	begin
	  v__h26379 = $stime;
	  #0;
	end
    v__h26373 = v__h26379 / 32'd10;
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_io_AMO_op_req &&
	  NOT_cfg_verbosity_read__0_ULE_1_1___d12)
	if (dmem_not_imem)
	  $display("%0d: %s.rl_io_AMO_op_req; f3 0x%0h vaddr %0h  paddr %0h",
		   v__h26373,
		   "D_MMU_Cache",
		   rg_f3,
		   rg_addr,
		   rg_pa);
	else
	  $display("%0d: %s.rl_io_AMO_op_req; f3 0x%0h vaddr %0h  paddr %0h",
		   v__h26373,
		   "I_MMU_Cache",
		   rg_f3,
		   rg_addr,
		   rg_pa);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_io_AMO_op_req &&
	  NOT_cfg_verbosity_read__0_ULE_1_1___d12)
	$write("            To fabric: ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_io_AMO_op_req &&
	  NOT_cfg_verbosity_read__0_ULE_1_1___d12)
	$write("AXI4_Rd_Addr { ", "arid: ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_io_AMO_op_req &&
	  NOT_cfg_verbosity_read__0_ULE_1_1___d12)
	$write("'h%h", 4'd0);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_io_AMO_op_req &&
	  NOT_cfg_verbosity_read__0_ULE_1_1___d12)
	$write(", ", "araddr: ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_io_AMO_op_req &&
	  NOT_cfg_verbosity_read__0_ULE_1_1___d12)
	$write("'h%h", rg_pa);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_io_AMO_op_req &&
	  NOT_cfg_verbosity_read__0_ULE_1_1___d12)
	$write(", ", "arlen: ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_io_AMO_op_req &&
	  NOT_cfg_verbosity_read__0_ULE_1_1___d12)
	$write("'h%h", 8'd0);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_io_AMO_op_req &&
	  NOT_cfg_verbosity_read__0_ULE_1_1___d12)
	$write(", ", "arsize: ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_io_AMO_op_req &&
	  NOT_cfg_verbosity_read__0_ULE_1_1___d12)
	$write("'h%h", value__h26583);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_io_AMO_op_req &&
	  NOT_cfg_verbosity_read__0_ULE_1_1___d12)
	$write(", ", "arburst: ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_io_AMO_op_req &&
	  NOT_cfg_verbosity_read__0_ULE_1_1___d12)
	$write("'h%h", 2'b01);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_io_AMO_op_req &&
	  NOT_cfg_verbosity_read__0_ULE_1_1___d12)
	$write(", ", "arlock: ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_io_AMO_op_req &&
	  NOT_cfg_verbosity_read__0_ULE_1_1___d12)
	$write("'h%h", 1'b0);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_io_AMO_op_req &&
	  NOT_cfg_verbosity_read__0_ULE_1_1___d12)
	$write(", ", "arcache: ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_io_AMO_op_req &&
	  NOT_cfg_verbosity_read__0_ULE_1_1___d12)
	$write("'h%h", 4'b0);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_io_AMO_op_req &&
	  NOT_cfg_verbosity_read__0_ULE_1_1___d12)
	$write(", ", "arprot: ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_io_AMO_op_req &&
	  NOT_cfg_verbosity_read__0_ULE_1_1___d12)
	$write("'h%h", 3'd0);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_io_AMO_op_req &&
	  NOT_cfg_verbosity_read__0_ULE_1_1___d12)
	$write(", ", "arqos: ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_io_AMO_op_req &&
	  NOT_cfg_verbosity_read__0_ULE_1_1___d12)
	$write("'h%h", 4'd0);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_io_AMO_op_req &&
	  NOT_cfg_verbosity_read__0_ULE_1_1___d12)
	$write(", ", "arregion: ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_io_AMO_op_req &&
	  NOT_cfg_verbosity_read__0_ULE_1_1___d12)
	$write("'h%h", 4'd0);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_io_AMO_op_req &&
	  NOT_cfg_verbosity_read__0_ULE_1_1___d12)
	$write(", ", "aruser: ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_io_AMO_op_req &&
	  NOT_cfg_verbosity_read__0_ULE_1_1___d12)
	$write("'h%h", 1'h0, " }");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_io_AMO_op_req &&
	  NOT_cfg_verbosity_read__0_ULE_1_1___d12)
	$write("\n");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_io_AMO_read_rsp &&
	  NOT_cfg_verbosity_read__0_ULE_1_1___d12)
	begin
	  v__h26697 = $stime;
	  #0;
	end
    v__h26691 = v__h26697 / 32'd10;
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_io_AMO_read_rsp &&
	  NOT_cfg_verbosity_read__0_ULE_1_1___d12)
	if (dmem_not_imem)
	  $display("%0d: %s.rl_io_AMO_read_rsp: vaddr 0x%0h  paddr 0x%0h",
		   v__h26691,
		   "D_MMU_Cache",
		   rg_addr,
		   rg_pa);
	else
	  $display("%0d: %s.rl_io_AMO_read_rsp: vaddr 0x%0h  paddr 0x%0h",
		   v__h26691,
		   "I_MMU_Cache",
		   rg_addr,
		   rg_pa);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_io_AMO_read_rsp &&
	  NOT_cfg_verbosity_read__0_ULE_1_1___d12)
	$write("    ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_io_AMO_read_rsp &&
	  NOT_cfg_verbosity_read__0_ULE_1_1___d12)
	$write("AXI4_Rd_Data { ", "rid: ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_io_AMO_read_rsp &&
	  NOT_cfg_verbosity_read__0_ULE_1_1___d12)
	$write("'h%h", master_xactor_rg_rd_data[70:67]);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_io_AMO_read_rsp &&
	  NOT_cfg_verbosity_read__0_ULE_1_1___d12)
	$write(", ", "rdata: ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_io_AMO_read_rsp &&
	  NOT_cfg_verbosity_read__0_ULE_1_1___d12)
	$write("'h%h", master_xactor_rg_rd_data[66:3]);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_io_AMO_read_rsp &&
	  NOT_cfg_verbosity_read__0_ULE_1_1___d12)
	$write(", ", "rresp: ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_io_AMO_read_rsp &&
	  NOT_cfg_verbosity_read__0_ULE_1_1___d12)
	$write("'h%h", master_xactor_rg_rd_data[2:1]);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_io_AMO_read_rsp &&
	  NOT_cfg_verbosity_read__0_ULE_1_1___d12)
	$write(", ", "rlast: ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_io_AMO_read_rsp &&
	  NOT_cfg_verbosity_read__0_ULE_1_1___d12 &&
	  master_xactor_rg_rd_data[0])
	$write("True");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_io_AMO_read_rsp &&
	  NOT_cfg_verbosity_read__0_ULE_1_1___d12 &&
	  !master_xactor_rg_rd_data[0])
	$write("False");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_io_AMO_read_rsp &&
	  NOT_cfg_verbosity_read__0_ULE_1_1___d12)
	$write(", ", "ruser: ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_io_AMO_read_rsp &&
	  NOT_cfg_verbosity_read__0_ULE_1_1___d12)
	$write("'h%h", 1'd0, " }");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_io_AMO_read_rsp &&
	  NOT_cfg_verbosity_read__0_ULE_1_1___d12)
	$write("\n");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_io_AMO_read_rsp &&
	  master_xactor_rg_rd_data[2:1] == 2'b0 &&
	  NOT_cfg_verbosity_read__0_ULE_1_1___d12)
	begin
	  v__h26872 = $stime;
	  #0;
	end
    v__h26866 = v__h26872 / 32'd10;
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_io_AMO_read_rsp &&
	  master_xactor_rg_rd_data[2:1] == 2'b0 &&
	  NOT_cfg_verbosity_read__0_ULE_1_1___d12)
	if (dmem_not_imem)
	  $display("%0d: %s: rl_io_AMO_read_rsp; f3 0x%0h  vaddr %0h  paddr %0h  word64 0x%0h",
		   v__h26866,
		   "D_MMU_Cache",
		   rg_f3,
		   rg_addr,
		   rg_pa,
		   rg_st_amo_val);
	else
	  $display("%0d: %s: rl_io_AMO_read_rsp; f3 0x%0h  vaddr %0h  paddr %0h  word64 0x%0h",
		   v__h26866,
		   "I_MMU_Cache",
		   rg_f3,
		   rg_addr,
		   rg_pa,
		   rg_st_amo_val);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_io_AMO_read_rsp &&
	  master_xactor_rg_rd_data[2:1] == 2'b0 &&
	  ctr_wr_rsps_pending_crg == 4'd15)
	begin
	  v__h29485 = $stime;
	  #0;
	end
    v__h29479 = v__h29485 / 32'd10;
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_io_AMO_read_rsp &&
	  master_xactor_rg_rd_data[2:1] == 2'b0 &&
	  ctr_wr_rsps_pending_crg == 4'd15)
	$display("%0d: ERROR: CreditCounter: overflow", v__h29479);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_io_AMO_read_rsp &&
	  master_xactor_rg_rd_data[2:1] == 2'b0 &&
	  ctr_wr_rsps_pending_crg == 4'd15)
	$finish(32'd1);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_io_AMO_read_rsp &&
	  master_xactor_rg_rd_data[2:1] == 2'b0 &&
	  NOT_cfg_verbosity_read__0_ULE_1_1___d12)
	$write("            To fabric: ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_io_AMO_read_rsp &&
	  master_xactor_rg_rd_data[2:1] == 2'b0 &&
	  NOT_cfg_verbosity_read__0_ULE_1_1___d12)
	$write("AXI4_Wr_Addr { ", "awid: ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_io_AMO_read_rsp &&
	  master_xactor_rg_rd_data[2:1] == 2'b0 &&
	  NOT_cfg_verbosity_read__0_ULE_1_1___d12)
	$write("'h%h", 4'd0);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_io_AMO_read_rsp &&
	  master_xactor_rg_rd_data[2:1] == 2'b0 &&
	  NOT_cfg_verbosity_read__0_ULE_1_1___d12)
	$write(", ", "awaddr: ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_io_AMO_read_rsp &&
	  master_xactor_rg_rd_data[2:1] == 2'b0 &&
	  NOT_cfg_verbosity_read__0_ULE_1_1___d12)
	$write("'h%h", rg_pa);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_io_AMO_read_rsp &&
	  master_xactor_rg_rd_data[2:1] == 2'b0 &&
	  NOT_cfg_verbosity_read__0_ULE_1_1___d12)
	$write(", ", "awlen: ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_io_AMO_read_rsp &&
	  master_xactor_rg_rd_data[2:1] == 2'b0 &&
	  NOT_cfg_verbosity_read__0_ULE_1_1___d12)
	$write("'h%h", 8'd0);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_io_AMO_read_rsp &&
	  master_xactor_rg_rd_data[2:1] == 2'b0 &&
	  NOT_cfg_verbosity_read__0_ULE_1_1___d12)
	$write(", ", "awsize: ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_io_AMO_read_rsp &&
	  master_xactor_rg_rd_data[2:1] == 2'b0 &&
	  NOT_cfg_verbosity_read__0_ULE_1_1___d12)
	$write("'h%h", value__h29609);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_io_AMO_read_rsp &&
	  master_xactor_rg_rd_data[2:1] == 2'b0 &&
	  NOT_cfg_verbosity_read__0_ULE_1_1___d12)
	$write(", ", "awburst: ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_io_AMO_read_rsp &&
	  master_xactor_rg_rd_data[2:1] == 2'b0 &&
	  NOT_cfg_verbosity_read__0_ULE_1_1___d12)
	$write("'h%h", 2'b01);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_io_AMO_read_rsp &&
	  master_xactor_rg_rd_data[2:1] == 2'b0 &&
	  NOT_cfg_verbosity_read__0_ULE_1_1___d12)
	$write(", ", "awlock: ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_io_AMO_read_rsp &&
	  master_xactor_rg_rd_data[2:1] == 2'b0 &&
	  NOT_cfg_verbosity_read__0_ULE_1_1___d12)
	$write("'h%h", 1'b0);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_io_AMO_read_rsp &&
	  master_xactor_rg_rd_data[2:1] == 2'b0 &&
	  NOT_cfg_verbosity_read__0_ULE_1_1___d12)
	$write(", ", "awcache: ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_io_AMO_read_rsp &&
	  master_xactor_rg_rd_data[2:1] == 2'b0 &&
	  NOT_cfg_verbosity_read__0_ULE_1_1___d12)
	$write("'h%h", 4'b0);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_io_AMO_read_rsp &&
	  master_xactor_rg_rd_data[2:1] == 2'b0 &&
	  NOT_cfg_verbosity_read__0_ULE_1_1___d12)
	$write(", ", "awprot: ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_io_AMO_read_rsp &&
	  master_xactor_rg_rd_data[2:1] == 2'b0 &&
	  NOT_cfg_verbosity_read__0_ULE_1_1___d12)
	$write("'h%h", 3'd0);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_io_AMO_read_rsp &&
	  master_xactor_rg_rd_data[2:1] == 2'b0 &&
	  NOT_cfg_verbosity_read__0_ULE_1_1___d12)
	$write(", ", "awqos: ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_io_AMO_read_rsp &&
	  master_xactor_rg_rd_data[2:1] == 2'b0 &&
	  NOT_cfg_verbosity_read__0_ULE_1_1___d12)
	$write("'h%h", 4'd0);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_io_AMO_read_rsp &&
	  master_xactor_rg_rd_data[2:1] == 2'b0 &&
	  NOT_cfg_verbosity_read__0_ULE_1_1___d12)
	$write(", ", "awregion: ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_io_AMO_read_rsp &&
	  master_xactor_rg_rd_data[2:1] == 2'b0 &&
	  NOT_cfg_verbosity_read__0_ULE_1_1___d12)
	$write("'h%h", 4'd0);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_io_AMO_read_rsp &&
	  master_xactor_rg_rd_data[2:1] == 2'b0 &&
	  NOT_cfg_verbosity_read__0_ULE_1_1___d12)
	$write(", ", "awuser: ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_io_AMO_read_rsp &&
	  master_xactor_rg_rd_data[2:1] == 2'b0 &&
	  NOT_cfg_verbosity_read__0_ULE_1_1___d12)
	$write("'h%h", 1'h0, " }");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_io_AMO_read_rsp &&
	  master_xactor_rg_rd_data[2:1] == 2'b0 &&
	  NOT_cfg_verbosity_read__0_ULE_1_1___d12)
	$write("\n");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_io_AMO_read_rsp &&
	  master_xactor_rg_rd_data[2:1] == 2'b0 &&
	  NOT_cfg_verbosity_read__0_ULE_1_1___d12)
	$write("                       ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_io_AMO_read_rsp &&
	  master_xactor_rg_rd_data[2:1] == 2'b0 &&
	  NOT_cfg_verbosity_read__0_ULE_1_1___d12)
	$write("AXI4_Wr_Data { ", "wid: ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_io_AMO_read_rsp &&
	  master_xactor_rg_rd_data[2:1] == 2'b0 &&
	  NOT_cfg_verbosity_read__0_ULE_1_1___d12)
	$write("'h%h", 4'd0);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_io_AMO_read_rsp &&
	  master_xactor_rg_rd_data[2:1] == 2'b0 &&
	  NOT_cfg_verbosity_read__0_ULE_1_1___d12)
	$write(", ", "wdata: ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_io_AMO_read_rsp &&
	  master_xactor_rg_rd_data[2:1] == 2'b0 &&
	  NOT_cfg_verbosity_read__0_ULE_1_1___d12)
	$write("'h%h", mem_req_wr_data_wdata__h27265);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_io_AMO_read_rsp &&
	  master_xactor_rg_rd_data[2:1] == 2'b0 &&
	  NOT_cfg_verbosity_read__0_ULE_1_1___d12)
	$write(", ", "wstrb: ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_io_AMO_read_rsp &&
	  master_xactor_rg_rd_data[2:1] == 2'b0 &&
	  NOT_cfg_verbosity_read__0_ULE_1_1___d12)
	$write("'h%h", mem_req_wr_data_wstrb__h27266);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_io_AMO_read_rsp &&
	  master_xactor_rg_rd_data[2:1] == 2'b0 &&
	  NOT_cfg_verbosity_read__0_ULE_1_1___d12)
	$write(", ", "wlast: ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_io_AMO_read_rsp &&
	  master_xactor_rg_rd_data[2:1] == 2'b0 &&
	  NOT_cfg_verbosity_read__0_ULE_1_1___d12)
	$write("True");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_io_AMO_read_rsp &&
	  master_xactor_rg_rd_data[2:1] == 2'b0 &&
	  NOT_cfg_verbosity_read__0_ULE_1_1___d12)
	$write(", ", "wuser: ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_io_AMO_read_rsp &&
	  master_xactor_rg_rd_data[2:1] == 2'b0 &&
	  NOT_cfg_verbosity_read__0_ULE_1_1___d12)
	$write("'h%h", 1'h0, " }");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_io_AMO_read_rsp &&
	  master_xactor_rg_rd_data[2:1] == 2'b0 &&
	  NOT_cfg_verbosity_read__0_ULE_1_1___d12)
	$write("\n");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_io_AMO_read_rsp &&
	  master_xactor_rg_rd_data[2:1] == 2'b0 &&
	  NOT_cfg_verbosity_read__0_ULE_1_1___d12)
	begin
	  v__h29737 = $stime;
	  #0;
	end
    v__h29731 = v__h29737 / 32'd10;
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_io_AMO_read_rsp &&
	  master_xactor_rg_rd_data[2:1] == 2'b0 &&
	  NOT_cfg_verbosity_read__0_ULE_1_1___d12)
	if (dmem_not_imem)
	  $display("%0d: %s.drive_IO_read_rsp: addr 0x%0h ld_val 0x%0h",
		   v__h29731,
		   "D_MMU_Cache",
		   rg_addr,
		   new_ld_val__h26998);
	else
	  $display("%0d: %s.drive_IO_read_rsp: addr 0x%0h ld_val 0x%0h",
		   v__h29731,
		   "I_MMU_Cache",
		   rg_addr,
		   new_ld_val__h26998);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_io_AMO_read_rsp &&
	  master_xactor_rg_rd_data[2:1] == 2'b0 &&
	  NOT_cfg_verbosity_read__0_ULE_1_1___d12)
	$display("    => rl_ST_AMO_response");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_io_AMO_read_rsp &&
	  master_xactor_rg_rd_data[2:1] != 2'b0 &&
	  NOT_cfg_verbosity_read__0_ULE_1_1___d12)
	begin
	  v__h26968 = $stime;
	  #0;
	end
    v__h26962 = v__h26968 / 32'd10;
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_io_AMO_read_rsp &&
	  master_xactor_rg_rd_data[2:1] != 2'b0 &&
	  NOT_cfg_verbosity_read__0_ULE_1_1___d12)
	if (dmem_not_imem)
	  $display("%0d: %s.rl_io_AMO_read_rsp: FABRIC_RSP_ERR: raising trap STORE_AMO_ACCESS_FAULT",
		   v__h26962,
		   "D_MMU_Cache");
	else
	  $display("%0d: %s.rl_io_AMO_read_rsp: FABRIC_RSP_ERR: raising trap STORE_AMO_ACCESS_FAULT",
		   v__h26962,
		   "I_MMU_Cache");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_start_cache_refill &&
	  NOT_cfg_verbosity_read__0_ULE_1_1___d12)
	begin
	  v__h20981 = $stime;
	  #0;
	end
    v__h20975 = v__h20981 / 32'd10;
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_start_cache_refill &&
	  NOT_cfg_verbosity_read__0_ULE_1_1___d12)
	if (dmem_not_imem)
	  $display("%0d: %s.rl_start_cache_refill: ",
		   v__h20975,
		   "D_MMU_Cache");
	else
	  $display("%0d: %s.rl_start_cache_refill: ",
		   v__h20975,
		   "I_MMU_Cache");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_start_cache_refill &&
	  NOT_cfg_verbosity_read__0_ULE_1_1___d12)
	$write("    To fabric: ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_start_cache_refill &&
	  NOT_cfg_verbosity_read__0_ULE_1_1___d12)
	$write("AXI4_Rd_Addr { ", "arid: ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_start_cache_refill &&
	  NOT_cfg_verbosity_read__0_ULE_1_1___d12)
	$write("'h%h", 4'd0);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_start_cache_refill &&
	  NOT_cfg_verbosity_read__0_ULE_1_1___d12)
	$write(", ", "araddr: ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_start_cache_refill &&
	  NOT_cfg_verbosity_read__0_ULE_1_1___d12)
	$write("'h%h", cline_fabric_addr__h21034);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_start_cache_refill &&
	  NOT_cfg_verbosity_read__0_ULE_1_1___d12)
	$write(", ", "arlen: ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_start_cache_refill &&
	  NOT_cfg_verbosity_read__0_ULE_1_1___d12)
	$write("'h%h", 8'd7);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_start_cache_refill &&
	  NOT_cfg_verbosity_read__0_ULE_1_1___d12)
	$write(", ", "arsize: ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_start_cache_refill &&
	  NOT_cfg_verbosity_read__0_ULE_1_1___d12)
	$write("'h%h", 3'b011);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_start_cache_refill &&
	  NOT_cfg_verbosity_read__0_ULE_1_1___d12)
	$write(", ", "arburst: ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_start_cache_refill &&
	  NOT_cfg_verbosity_read__0_ULE_1_1___d12)
	$write("'h%h", 2'b01);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_start_cache_refill &&
	  NOT_cfg_verbosity_read__0_ULE_1_1___d12)
	$write(", ", "arlock: ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_start_cache_refill &&
	  NOT_cfg_verbosity_read__0_ULE_1_1___d12)
	$write("'h%h", 1'b0);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_start_cache_refill &&
	  NOT_cfg_verbosity_read__0_ULE_1_1___d12)
	$write(", ", "arcache: ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_start_cache_refill &&
	  NOT_cfg_verbosity_read__0_ULE_1_1___d12)
	$write("'h%h", 4'b0);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_start_cache_refill &&
	  NOT_cfg_verbosity_read__0_ULE_1_1___d12)
	$write(", ", "arprot: ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_start_cache_refill &&
	  NOT_cfg_verbosity_read__0_ULE_1_1___d12)
	$write("'h%h", 3'd0);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_start_cache_refill &&
	  NOT_cfg_verbosity_read__0_ULE_1_1___d12)
	$write(", ", "arqos: ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_start_cache_refill &&
	  NOT_cfg_verbosity_read__0_ULE_1_1___d12)
	$write("'h%h", 4'd0);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_start_cache_refill &&
	  NOT_cfg_verbosity_read__0_ULE_1_1___d12)
	$write(", ", "arregion: ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_start_cache_refill &&
	  NOT_cfg_verbosity_read__0_ULE_1_1___d12)
	$write("'h%h", 4'd0);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_start_cache_refill &&
	  NOT_cfg_verbosity_read__0_ULE_1_1___d12)
	$write(", ", "aruser: ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_start_cache_refill &&
	  NOT_cfg_verbosity_read__0_ULE_1_1___d12)
	$write("'h%h", 1'h0, " }");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_start_cache_refill &&
	  NOT_cfg_verbosity_read__0_ULE_1_1___d12)
	$write("\n");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_start_cache_refill &&
	  NOT_cfg_verbosity_read__0_ULE_1_1___d12)
	$display("    Victim way %0d; => CACHE_REFILL", 1'd0);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_io_read_req &&
	  NOT_cfg_verbosity_read__0_ULE_1_1___d12)
	begin
	  v__h23675 = $stime;
	  #0;
	end
    v__h23669 = v__h23675 / 32'd10;
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_io_read_req &&
	  NOT_cfg_verbosity_read__0_ULE_1_1___d12)
	if (dmem_not_imem)
	  $display("%0d: %s.rl_io_read_req; f3 0x%0h vaddr %0h  paddr %0h",
		   v__h23669,
		   "D_MMU_Cache",
		   rg_f3,
		   rg_addr,
		   rg_pa);
	else
	  $display("%0d: %s.rl_io_read_req; f3 0x%0h vaddr %0h  paddr %0h",
		   v__h23669,
		   "I_MMU_Cache",
		   rg_f3,
		   rg_addr,
		   rg_pa);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_io_read_req &&
	  NOT_cfg_verbosity_read__0_ULE_1_1___d12)
	$write("            To fabric: ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_io_read_req &&
	  NOT_cfg_verbosity_read__0_ULE_1_1___d12)
	$write("AXI4_Rd_Addr { ", "arid: ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_io_read_req &&
	  NOT_cfg_verbosity_read__0_ULE_1_1___d12)
	$write("'h%h", 4'd0);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_io_read_req &&
	  NOT_cfg_verbosity_read__0_ULE_1_1___d12)
	$write(", ", "araddr: ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_io_read_req &&
	  NOT_cfg_verbosity_read__0_ULE_1_1___d12)
	$write("'h%h", rg_pa);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_io_read_req &&
	  NOT_cfg_verbosity_read__0_ULE_1_1___d12)
	$write(", ", "arlen: ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_io_read_req &&
	  NOT_cfg_verbosity_read__0_ULE_1_1___d12)
	$write("'h%h", 8'd0);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_io_read_req &&
	  NOT_cfg_verbosity_read__0_ULE_1_1___d12)
	$write(", ", "arsize: ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_io_read_req &&
	  NOT_cfg_verbosity_read__0_ULE_1_1___d12)
	$write("'h%h", value__h26583);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_io_read_req &&
	  NOT_cfg_verbosity_read__0_ULE_1_1___d12)
	$write(", ", "arburst: ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_io_read_req &&
	  NOT_cfg_verbosity_read__0_ULE_1_1___d12)
	$write("'h%h", 2'b01);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_io_read_req &&
	  NOT_cfg_verbosity_read__0_ULE_1_1___d12)
	$write(", ", "arlock: ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_io_read_req &&
	  NOT_cfg_verbosity_read__0_ULE_1_1___d12)
	$write("'h%h", 1'b0);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_io_read_req &&
	  NOT_cfg_verbosity_read__0_ULE_1_1___d12)
	$write(", ", "arcache: ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_io_read_req &&
	  NOT_cfg_verbosity_read__0_ULE_1_1___d12)
	$write("'h%h", 4'b0);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_io_read_req &&
	  NOT_cfg_verbosity_read__0_ULE_1_1___d12)
	$write(", ", "arprot: ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_io_read_req &&
	  NOT_cfg_verbosity_read__0_ULE_1_1___d12)
	$write("'h%h", 3'd0);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_io_read_req &&
	  NOT_cfg_verbosity_read__0_ULE_1_1___d12)
	$write(", ", "arqos: ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_io_read_req &&
	  NOT_cfg_verbosity_read__0_ULE_1_1___d12)
	$write("'h%h", 4'd0);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_io_read_req &&
	  NOT_cfg_verbosity_read__0_ULE_1_1___d12)
	$write(", ", "arregion: ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_io_read_req &&
	  NOT_cfg_verbosity_read__0_ULE_1_1___d12)
	$write("'h%h", 4'd0);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_io_read_req &&
	  NOT_cfg_verbosity_read__0_ULE_1_1___d12)
	$write(", ", "aruser: ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_io_read_req &&
	  NOT_cfg_verbosity_read__0_ULE_1_1___d12)
	$write("'h%h", 1'h0, " }");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_io_read_req &&
	  NOT_cfg_verbosity_read__0_ULE_1_1___d12)
	$write("\n");
    if (RST_N != `BSV_RESET_VALUE)
      if (EN_req && NOT_cfg_verbosity_read__0_ULE_1_1___d12)
	begin
	  v__h30707 = $stime;
	  #0;
	end
    v__h30701 = v__h30707 / 32'd10;
    if (RST_N != `BSV_RESET_VALUE)
      if (EN_req && NOT_cfg_verbosity_read__0_ULE_1_1___d12)
	if (dmem_not_imem)
	  $write("%0d: %s.req: op:", v__h30701, "D_MMU_Cache");
	else
	  $write("%0d: %s.req: op:", v__h30701, "I_MMU_Cache");
    if (RST_N != `BSV_RESET_VALUE)
      if (EN_req && NOT_cfg_verbosity_read__0_ULE_1_1___d12 && req_op == 2'd0)
	$write("CACHE_LD");
    if (RST_N != `BSV_RESET_VALUE)
      if (EN_req && NOT_cfg_verbosity_read__0_ULE_1_1___d12 && req_op == 2'd1)
	$write("CACHE_ST");
    if (RST_N != `BSV_RESET_VALUE)
      if (EN_req && NOT_cfg_verbosity_read__0_ULE_1_1___d12 &&
	  req_op != 2'd0 &&
	  req_op != 2'd1)
	$write("CACHE_AMO");
    if (RST_N != `BSV_RESET_VALUE)
      if (EN_req && NOT_cfg_verbosity_read__0_ULE_1_1___d12)
	$write(" f3:%0d addr:0x%0h st_value:0x%0h priv:",
	       req_f3,
	       req_addr,
	       req_st_value);
    if (RST_N != `BSV_RESET_VALUE)
      if (EN_req && NOT_cfg_verbosity_read__0_ULE_1_1___d12 &&
	  req_priv == 2'b0)
	$write("U");
    if (RST_N != `BSV_RESET_VALUE)
      if (EN_req && NOT_cfg_verbosity_read__0_ULE_1_1___d12 &&
	  req_priv == 2'b01)
	$write("S");
    if (RST_N != `BSV_RESET_VALUE)
      if (EN_req && NOT_cfg_verbosity_read__0_ULE_1_1___d12 &&
	  req_priv == 2'b11)
	$write("M");
    if (RST_N != `BSV_RESET_VALUE)
      if (EN_req && NOT_cfg_verbosity_read__0_ULE_1_1___d12 &&
	  req_priv != 2'b0 &&
	  req_priv != 2'b01 &&
	  req_priv != 2'b11)
	$write("RESERVED");
    if (RST_N != `BSV_RESET_VALUE)
      if (EN_req && NOT_cfg_verbosity_read__0_ULE_1_1___d12)
	$write(" sstatus_SUM:%0d mstatus_MXR:%0d satp:0x%0h",
	       req_sstatus_SUM,
	       req_mstatus_MXR,
	       req_satp,
	       "\n");
    if (RST_N != `BSV_RESET_VALUE)
      if (EN_req && NOT_cfg_verbosity_read__0_ULE_1_1___d12)
	$display("    amo_funct7 = 0x%0h", req_amo_funct7);
    if (RST_N != `BSV_RESET_VALUE)
      if (EN_req &&
	  req_f3_BITS_1_TO_0_90_EQ_0b0_91_OR_req_f3_BITS_ETC___d920 &&
	  NOT_cfg_verbosity_read__0_ULE_1_1___d12)
	$display("    fa_req_ram_B tagCSet [0x%0x] word64_set [0x%0d]",
		 req_addr[11:6],
		 req_addr[11:3]);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_discard_write_rsp &&
	  master_xactor_rg_wr_resp[1:0] == 2'b0 &&
	  NOT_cfg_verbosity_read__0_ULE_1_1___d12)
	begin
	  v__h30357 = $stime;
	  #0;
	end
    v__h30351 = v__h30357 / 32'd10;
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_discard_write_rsp &&
	  master_xactor_rg_wr_resp[1:0] == 2'b0 &&
	  NOT_cfg_verbosity_read__0_ULE_1_1___d12)
	if (dmem_not_imem)
	  $write("%0d: %s.rl_discard_write_rsp: pending %0d ",
		 v__h30351,
		 "D_MMU_Cache",
		 $unsigned(b__h20935));
	else
	  $write("%0d: %s.rl_discard_write_rsp: pending %0d ",
		 v__h30351,
		 "I_MMU_Cache",
		 $unsigned(b__h20935));
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_discard_write_rsp &&
	  master_xactor_rg_wr_resp[1:0] == 2'b0 &&
	  NOT_cfg_verbosity_read__0_ULE_1_1___d12)
	$write("AXI4_Wr_Resp { ", "bid: ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_discard_write_rsp &&
	  master_xactor_rg_wr_resp[1:0] == 2'b0 &&
	  NOT_cfg_verbosity_read__0_ULE_1_1___d12)
	$write("'h%h", master_xactor_rg_wr_resp[5:2]);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_discard_write_rsp &&
	  master_xactor_rg_wr_resp[1:0] == 2'b0 &&
	  NOT_cfg_verbosity_read__0_ULE_1_1___d12)
	$write(", ", "bresp: ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_discard_write_rsp &&
	  master_xactor_rg_wr_resp[1:0] == 2'b0 &&
	  NOT_cfg_verbosity_read__0_ULE_1_1___d12)
	$write("'h%h", master_xactor_rg_wr_resp[1:0]);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_discard_write_rsp &&
	  master_xactor_rg_wr_resp[1:0] == 2'b0 &&
	  NOT_cfg_verbosity_read__0_ULE_1_1___d12)
	$write(", ", "buser: ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_discard_write_rsp &&
	  master_xactor_rg_wr_resp[1:0] == 2'b0 &&
	  NOT_cfg_verbosity_read__0_ULE_1_1___d12)
	$write("'h%h", 1'd0, " }");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_discard_write_rsp &&
	  master_xactor_rg_wr_resp[1:0] == 2'b0 &&
	  NOT_cfg_verbosity_read__0_ULE_1_1___d12)
	$write("\n");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_discard_write_rsp &&
	  master_xactor_rg_wr_resp[1:0] != 2'b0)
	begin
	  v__h30318 = $stime;
	  #0;
	end
    v__h30312 = v__h30318 / 32'd10;
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_discard_write_rsp &&
	  master_xactor_rg_wr_resp[1:0] != 2'b0)
	if (dmem_not_imem)
	  $display("%0d: %s.rl_discard_write_rsp: fabric response error: exit",
		   v__h30312,
		   "D_MMU_Cache");
	else
	  $display("%0d: %s.rl_discard_write_rsp: fabric response error: exit",
		   v__h30312,
		   "I_MMU_Cache");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_discard_write_rsp &&
	  master_xactor_rg_wr_resp[1:0] != 2'b0)
	$write("    ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_discard_write_rsp &&
	  master_xactor_rg_wr_resp[1:0] != 2'b0)
	$write("AXI4_Wr_Resp { ", "bid: ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_discard_write_rsp &&
	  master_xactor_rg_wr_resp[1:0] != 2'b0)
	$write("'h%h", master_xactor_rg_wr_resp[5:2]);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_discard_write_rsp &&
	  master_xactor_rg_wr_resp[1:0] != 2'b0)
	$write(", ", "bresp: ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_discard_write_rsp &&
	  master_xactor_rg_wr_resp[1:0] != 2'b0)
	$write("'h%h", master_xactor_rg_wr_resp[1:0]);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_discard_write_rsp &&
	  master_xactor_rg_wr_resp[1:0] != 2'b0)
	$write(", ", "buser: ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_discard_write_rsp &&
	  master_xactor_rg_wr_resp[1:0] != 2'b0)
	$write("'h%h", 1'd0, " }");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_discard_write_rsp &&
	  master_xactor_rg_wr_resp[1:0] != 2'b0)
	$write("\n");
  end
  // synopsys translate_on
endmodule  // mkMMU_Cache

