//
// Generated by Bluespec Compiler, version 2018.10.beta1 (build e1df8052c, 2018-10-17)
//
//
//
//
// Ports:
// Name                         I/O  size props
// RDY_hart0_server_reset_request_put  O     1 reg
// hart0_server_reset_response_get  O     1 reg
// RDY_hart0_server_reset_response_get  O     1 reg
// imem_master_awvalid            O     1
// imem_master_awid               O     4 reg
// imem_master_awaddr             O    64 reg
// imem_master_awlen              O     8 reg
// imem_master_awsize             O     3 reg
// imem_master_awburst            O     2 reg
// imem_master_awlock             O     1 reg
// imem_master_awcache            O     4 reg
// imem_master_awprot             O     3 reg
// imem_master_awqos              O     4 reg
// imem_master_awregion           O     4 reg
// imem_master_wvalid             O     1
// imem_master_wid                O     4 reg
// imem_master_wdata              O    64 reg
// imem_master_wstrb              O     8 reg
// imem_master_wlast              O     1 reg
// imem_master_bready             O     1
// imem_master_arvalid            O     1
// imem_master_arid               O     4 reg
// imem_master_araddr             O    64 reg
// imem_master_arlen              O     8 reg
// imem_master_arsize             O     3 reg
// imem_master_arburst            O     2 reg
// imem_master_arlock             O     1 reg
// imem_master_arcache            O     4 reg
// imem_master_arprot             O     3 reg
// imem_master_arqos              O     4 reg
// imem_master_arregion           O     4 reg
// imem_master_rready             O     1
// dmem_master_awvalid            O     1
// dmem_master_awid               O     4 reg
// dmem_master_awaddr             O    64 reg
// dmem_master_awlen              O     8 reg
// dmem_master_awsize             O     3 reg
// dmem_master_awburst            O     2 reg
// dmem_master_awlock             O     1 reg
// dmem_master_awcache            O     4 reg
// dmem_master_awprot             O     3 reg
// dmem_master_awqos              O     4 reg
// dmem_master_awregion           O     4 reg
// dmem_master_wvalid             O     1
// dmem_master_wid                O     4 reg
// dmem_master_wdata              O    64 reg
// dmem_master_wstrb              O     8 reg
// dmem_master_wlast              O     1 reg
// dmem_master_bready             O     1
// dmem_master_arvalid            O     1
// dmem_master_arid               O     4 reg
// dmem_master_araddr             O    64 reg
// dmem_master_arlen              O     8 reg
// dmem_master_arsize             O     3 reg
// dmem_master_arburst            O     2 reg
// dmem_master_arlock             O     1 reg
// dmem_master_arcache            O     4 reg
// dmem_master_arprot             O     3 reg
// dmem_master_arqos              O     4 reg
// dmem_master_arregion           O     4 reg
// dmem_master_rready             O     1
// RDY_set_verbosity              O     1 const
// CLK                            I     1 clock
// RST_N                          I     1 reset
// hart0_server_reset_request_put  I     1 reg
// imem_master_awready            I     1
// imem_master_wready             I     1
// imem_master_bvalid             I     1
// imem_master_bid                I     4 reg
// imem_master_bresp              I     2 reg
// imem_master_arready            I     1
// imem_master_rvalid             I     1
// imem_master_rid                I     4 reg
// imem_master_rdata              I    64 reg
// imem_master_rresp              I     2 reg
// imem_master_rlast              I     1 reg
// dmem_master_awready            I     1
// dmem_master_wready             I     1
// dmem_master_bvalid             I     1
// dmem_master_bid                I     4 reg
// dmem_master_bresp              I     2 reg
// dmem_master_arready            I     1
// dmem_master_rvalid             I     1
// dmem_master_rid                I     4 reg
// dmem_master_rdata              I    64 reg
// dmem_master_rresp              I     2 reg
// dmem_master_rlast              I     1 reg
// m_external_interrupt_req_set_not_clear  I     1 reg
// s_external_interrupt_req_set_not_clear  I     1 reg
// software_interrupt_req_set_not_clear  I     1 reg
// timer_interrupt_req_set_not_clear  I     1 reg
// nmi_req_set_not_clear          I     1
// set_verbosity_verbosity        I     4 reg
// set_verbosity_logdelay         I    64 reg
// EN_hart0_server_reset_request_put  I     1
// EN_set_verbosity               I     1
// EN_hart0_server_reset_response_get  I     1
//
// Combinational paths from inputs to outputs:
//   (imem_master_awready, imem_master_wready) -> imem_master_bready
//   (imem_master_awready,
//    imem_master_wready,
//    dmem_master_awready,
//    dmem_master_wready) -> imem_master_rready
//   (imem_master_awready,
//    imem_master_wready,
//    dmem_master_awready,
//    dmem_master_wready) -> dmem_master_rready
//   (dmem_master_awready, dmem_master_wready) -> dmem_master_bready
//
//

`ifdef BSV_ASSIGNMENT_DELAY
`else
  `define BSV_ASSIGNMENT_DELAY
`endif

`ifdef BSV_POSITIVE_RESET
  `define BSV_RESET_VALUE 1'b1
  `define BSV_RESET_EDGE posedge
`else
  `define BSV_RESET_VALUE 1'b0
  `define BSV_RESET_EDGE negedge
`endif

module mkCPU(CLK,
	     RST_N,

	     hart0_server_reset_request_put,
	     EN_hart0_server_reset_request_put,
	     RDY_hart0_server_reset_request_put,

	     EN_hart0_server_reset_response_get,
	     hart0_server_reset_response_get,
	     RDY_hart0_server_reset_response_get,

	     imem_master_awvalid,

	     imem_master_awid,

	     imem_master_awaddr,

	     imem_master_awlen,

	     imem_master_awsize,

	     imem_master_awburst,

	     imem_master_awlock,

	     imem_master_awcache,

	     imem_master_awprot,

	     imem_master_awqos,

	     imem_master_awregion,

	     imem_master_awready,

	     imem_master_wvalid,

	     imem_master_wid,

	     imem_master_wdata,

	     imem_master_wstrb,

	     imem_master_wlast,

	     imem_master_wready,

	     imem_master_bvalid,
	     imem_master_bid,
	     imem_master_bresp,

	     imem_master_bready,

	     imem_master_arvalid,

	     imem_master_arid,

	     imem_master_araddr,

	     imem_master_arlen,

	     imem_master_arsize,

	     imem_master_arburst,

	     imem_master_arlock,

	     imem_master_arcache,

	     imem_master_arprot,

	     imem_master_arqos,

	     imem_master_arregion,

	     imem_master_arready,

	     imem_master_rvalid,
	     imem_master_rid,
	     imem_master_rdata,
	     imem_master_rresp,
	     imem_master_rlast,

	     imem_master_rready,

	     dmem_master_awvalid,

	     dmem_master_awid,

	     dmem_master_awaddr,

	     dmem_master_awlen,

	     dmem_master_awsize,

	     dmem_master_awburst,

	     dmem_master_awlock,

	     dmem_master_awcache,

	     dmem_master_awprot,

	     dmem_master_awqos,

	     dmem_master_awregion,

	     dmem_master_awready,

	     dmem_master_wvalid,

	     dmem_master_wid,

	     dmem_master_wdata,

	     dmem_master_wstrb,

	     dmem_master_wlast,

	     dmem_master_wready,

	     dmem_master_bvalid,
	     dmem_master_bid,
	     dmem_master_bresp,

	     dmem_master_bready,

	     dmem_master_arvalid,

	     dmem_master_arid,

	     dmem_master_araddr,

	     dmem_master_arlen,

	     dmem_master_arsize,

	     dmem_master_arburst,

	     dmem_master_arlock,

	     dmem_master_arcache,

	     dmem_master_arprot,

	     dmem_master_arqos,

	     dmem_master_arregion,

	     dmem_master_arready,

	     dmem_master_rvalid,
	     dmem_master_rid,
	     dmem_master_rdata,
	     dmem_master_rresp,
	     dmem_master_rlast,

	     dmem_master_rready,

	     m_external_interrupt_req_set_not_clear,

	     s_external_interrupt_req_set_not_clear,

	     software_interrupt_req_set_not_clear,

	     timer_interrupt_req_set_not_clear,

	     nmi_req_set_not_clear,

	     set_verbosity_verbosity,
	     set_verbosity_logdelay,
	     EN_set_verbosity,
	     RDY_set_verbosity);
  input  CLK;
  input  RST_N;

  // action method hart0_server_reset_request_put
  input  hart0_server_reset_request_put;
  input  EN_hart0_server_reset_request_put;
  output RDY_hart0_server_reset_request_put;

  // actionvalue method hart0_server_reset_response_get
  input  EN_hart0_server_reset_response_get;
  output hart0_server_reset_response_get;
  output RDY_hart0_server_reset_response_get;

  // value method imem_master_m_awvalid
  output imem_master_awvalid;

  // value method imem_master_m_awid
  output [3 : 0] imem_master_awid;

  // value method imem_master_m_awaddr
  output [63 : 0] imem_master_awaddr;

  // value method imem_master_m_awlen
  output [7 : 0] imem_master_awlen;

  // value method imem_master_m_awsize
  output [2 : 0] imem_master_awsize;

  // value method imem_master_m_awburst
  output [1 : 0] imem_master_awburst;

  // value method imem_master_m_awlock
  output imem_master_awlock;

  // value method imem_master_m_awcache
  output [3 : 0] imem_master_awcache;

  // value method imem_master_m_awprot
  output [2 : 0] imem_master_awprot;

  // value method imem_master_m_awqos
  output [3 : 0] imem_master_awqos;

  // value method imem_master_m_awregion
  output [3 : 0] imem_master_awregion;

  // value method imem_master_m_awuser

  // action method imem_master_m_awready
  input  imem_master_awready;

  // value method imem_master_m_wvalid
  output imem_master_wvalid;

  // value method imem_master_m_wid
  output [3 : 0] imem_master_wid;

  // value method imem_master_m_wdata
  output [63 : 0] imem_master_wdata;

  // value method imem_master_m_wstrb
  output [7 : 0] imem_master_wstrb;

  // value method imem_master_m_wlast
  output imem_master_wlast;

  // value method imem_master_m_wuser

  // action method imem_master_m_wready
  input  imem_master_wready;

  // action method imem_master_m_bvalid
  input  imem_master_bvalid;
  input  [3 : 0] imem_master_bid;
  input  [1 : 0] imem_master_bresp;

  // value method imem_master_m_bready
  output imem_master_bready;

  // value method imem_master_m_arvalid
  output imem_master_arvalid;

  // value method imem_master_m_arid
  output [3 : 0] imem_master_arid;

  // value method imem_master_m_araddr
  output [63 : 0] imem_master_araddr;

  // value method imem_master_m_arlen
  output [7 : 0] imem_master_arlen;

  // value method imem_master_m_arsize
  output [2 : 0] imem_master_arsize;

  // value method imem_master_m_arburst
  output [1 : 0] imem_master_arburst;

  // value method imem_master_m_arlock
  output imem_master_arlock;

  // value method imem_master_m_arcache
  output [3 : 0] imem_master_arcache;

  // value method imem_master_m_arprot
  output [2 : 0] imem_master_arprot;

  // value method imem_master_m_arqos
  output [3 : 0] imem_master_arqos;

  // value method imem_master_m_arregion
  output [3 : 0] imem_master_arregion;

  // value method imem_master_m_aruser

  // action method imem_master_m_arready
  input  imem_master_arready;

  // action method imem_master_m_rvalid
  input  imem_master_rvalid;
  input  [3 : 0] imem_master_rid;
  input  [63 : 0] imem_master_rdata;
  input  [1 : 0] imem_master_rresp;
  input  imem_master_rlast;

  // value method imem_master_m_rready
  output imem_master_rready;

  // value method dmem_master_m_awvalid
  output dmem_master_awvalid;

  // value method dmem_master_m_awid
  output [3 : 0] dmem_master_awid;

  // value method dmem_master_m_awaddr
  output [63 : 0] dmem_master_awaddr;

  // value method dmem_master_m_awlen
  output [7 : 0] dmem_master_awlen;

  // value method dmem_master_m_awsize
  output [2 : 0] dmem_master_awsize;

  // value method dmem_master_m_awburst
  output [1 : 0] dmem_master_awburst;

  // value method dmem_master_m_awlock
  output dmem_master_awlock;

  // value method dmem_master_m_awcache
  output [3 : 0] dmem_master_awcache;

  // value method dmem_master_m_awprot
  output [2 : 0] dmem_master_awprot;

  // value method dmem_master_m_awqos
  output [3 : 0] dmem_master_awqos;

  // value method dmem_master_m_awregion
  output [3 : 0] dmem_master_awregion;

  // value method dmem_master_m_awuser

  // action method dmem_master_m_awready
  input  dmem_master_awready;

  // value method dmem_master_m_wvalid
  output dmem_master_wvalid;

  // value method dmem_master_m_wid
  output [3 : 0] dmem_master_wid;

  // value method dmem_master_m_wdata
  output [63 : 0] dmem_master_wdata;

  // value method dmem_master_m_wstrb
  output [7 : 0] dmem_master_wstrb;

  // value method dmem_master_m_wlast
  output dmem_master_wlast;

  // value method dmem_master_m_wuser

  // action method dmem_master_m_wready
  input  dmem_master_wready;

  // action method dmem_master_m_bvalid
  input  dmem_master_bvalid;
  input  [3 : 0] dmem_master_bid;
  input  [1 : 0] dmem_master_bresp;

  // value method dmem_master_m_bready
  output dmem_master_bready;

  // value method dmem_master_m_arvalid
  output dmem_master_arvalid;

  // value method dmem_master_m_arid
  output [3 : 0] dmem_master_arid;

  // value method dmem_master_m_araddr
  output [63 : 0] dmem_master_araddr;

  // value method dmem_master_m_arlen
  output [7 : 0] dmem_master_arlen;

  // value method dmem_master_m_arsize
  output [2 : 0] dmem_master_arsize;

  // value method dmem_master_m_arburst
  output [1 : 0] dmem_master_arburst;

  // value method dmem_master_m_arlock
  output dmem_master_arlock;

  // value method dmem_master_m_arcache
  output [3 : 0] dmem_master_arcache;

  // value method dmem_master_m_arprot
  output [2 : 0] dmem_master_arprot;

  // value method dmem_master_m_arqos
  output [3 : 0] dmem_master_arqos;

  // value method dmem_master_m_arregion
  output [3 : 0] dmem_master_arregion;

  // value method dmem_master_m_aruser

  // action method dmem_master_m_arready
  input  dmem_master_arready;

  // action method dmem_master_m_rvalid
  input  dmem_master_rvalid;
  input  [3 : 0] dmem_master_rid;
  input  [63 : 0] dmem_master_rdata;
  input  [1 : 0] dmem_master_rresp;
  input  dmem_master_rlast;

  // value method dmem_master_m_rready
  output dmem_master_rready;

  // action method m_external_interrupt_req
  input  m_external_interrupt_req_set_not_clear;

  // action method s_external_interrupt_req
  input  s_external_interrupt_req_set_not_clear;

  // action method software_interrupt_req
  input  software_interrupt_req_set_not_clear;

  // action method timer_interrupt_req
  input  timer_interrupt_req_set_not_clear;

  // action method nmi_req
  input  nmi_req_set_not_clear;

  // action method set_verbosity
  input  [3 : 0] set_verbosity_verbosity;
  input  [63 : 0] set_verbosity_logdelay;
  input  EN_set_verbosity;
  output RDY_set_verbosity;

  // signals for module outputs
  wire [63 : 0] dmem_master_araddr,
		dmem_master_awaddr,
		dmem_master_wdata,
		imem_master_araddr,
		imem_master_awaddr,
		imem_master_wdata;
  wire [7 : 0] dmem_master_arlen,
	       dmem_master_awlen,
	       dmem_master_wstrb,
	       imem_master_arlen,
	       imem_master_awlen,
	       imem_master_wstrb;
  wire [3 : 0] dmem_master_arcache,
	       dmem_master_arid,
	       dmem_master_arqos,
	       dmem_master_arregion,
	       dmem_master_awcache,
	       dmem_master_awid,
	       dmem_master_awqos,
	       dmem_master_awregion,
	       dmem_master_wid,
	       imem_master_arcache,
	       imem_master_arid,
	       imem_master_arqos,
	       imem_master_arregion,
	       imem_master_awcache,
	       imem_master_awid,
	       imem_master_awqos,
	       imem_master_awregion,
	       imem_master_wid;
  wire [2 : 0] dmem_master_arprot,
	       dmem_master_arsize,
	       dmem_master_awprot,
	       dmem_master_awsize,
	       imem_master_arprot,
	       imem_master_arsize,
	       imem_master_awprot,
	       imem_master_awsize;
  wire [1 : 0] dmem_master_arburst,
	       dmem_master_awburst,
	       imem_master_arburst,
	       imem_master_awburst;
  wire RDY_hart0_server_reset_request_put,
       RDY_hart0_server_reset_response_get,
       RDY_set_verbosity,
       dmem_master_arlock,
       dmem_master_arvalid,
       dmem_master_awlock,
       dmem_master_awvalid,
       dmem_master_bready,
       dmem_master_rready,
       dmem_master_wlast,
       dmem_master_wvalid,
       hart0_server_reset_response_get,
       imem_master_arlock,
       imem_master_arvalid,
       imem_master_awlock,
       imem_master_awvalid,
       imem_master_bready,
       imem_master_rready,
       imem_master_wlast,
       imem_master_wvalid;

  // register cfg_logdelay
  reg [63 : 0] cfg_logdelay;
  wire [63 : 0] cfg_logdelay$D_IN;
  wire cfg_logdelay$EN;

  // register cfg_verbosity
  reg [3 : 0] cfg_verbosity;
  wire [3 : 0] cfg_verbosity$D_IN;
  wire cfg_verbosity$EN;

  // register imem_rg_f3
  reg [2 : 0] imem_rg_f3;
  wire [2 : 0] imem_rg_f3$D_IN;
  wire imem_rg_f3$EN;

  // register imem_rg_instr_15_0
  reg [15 : 0] imem_rg_instr_15_0;
  wire [15 : 0] imem_rg_instr_15_0$D_IN;
  wire imem_rg_instr_15_0$EN;

  // register imem_rg_mstatus_MXR
  reg imem_rg_mstatus_MXR;
  wire imem_rg_mstatus_MXR$D_IN, imem_rg_mstatus_MXR$EN;

  // register imem_rg_pc
  reg [31 : 0] imem_rg_pc;
  reg [31 : 0] imem_rg_pc$D_IN;
  wire imem_rg_pc$EN;

  // register imem_rg_priv
  reg [1 : 0] imem_rg_priv;
  wire [1 : 0] imem_rg_priv$D_IN;
  wire imem_rg_priv$EN;

  // register imem_rg_satp
  reg [31 : 0] imem_rg_satp;
  wire [31 : 0] imem_rg_satp$D_IN;
  wire imem_rg_satp$EN;

  // register imem_rg_sstatus_SUM
  reg imem_rg_sstatus_SUM;
  wire imem_rg_sstatus_SUM$D_IN, imem_rg_sstatus_SUM$EN;

  // register imem_rg_tval
  reg [31 : 0] imem_rg_tval;
  reg [31 : 0] imem_rg_tval$D_IN;
  wire imem_rg_tval$EN;

  // register rg_cur_priv
  reg [1 : 0] rg_cur_priv;
  reg [1 : 0] rg_cur_priv$D_IN;
  wire rg_cur_priv$EN;

  // register rg_mstatus_MXR
  reg rg_mstatus_MXR;
  wire rg_mstatus_MXR$D_IN, rg_mstatus_MXR$EN;

  // register rg_next_pc
  reg [31 : 0] rg_next_pc;
  reg [31 : 0] rg_next_pc$D_IN;
  wire rg_next_pc$EN;

  // register rg_run_on_reset
  reg rg_run_on_reset;
  wire rg_run_on_reset$D_IN, rg_run_on_reset$EN;

  // register rg_sstatus_SUM
  reg rg_sstatus_SUM;
  wire rg_sstatus_SUM$D_IN, rg_sstatus_SUM$EN;

  // register rg_start_CPI_cycles
  reg [63 : 0] rg_start_CPI_cycles;
  wire [63 : 0] rg_start_CPI_cycles$D_IN;
  wire rg_start_CPI_cycles$EN;

  // register rg_start_CPI_instrs
  reg [63 : 0] rg_start_CPI_instrs;
  wire [63 : 0] rg_start_CPI_instrs$D_IN;
  wire rg_start_CPI_instrs$EN;

  // register rg_state
  reg [3 : 0] rg_state;
  reg [3 : 0] rg_state$D_IN;
  wire rg_state$EN;

  // register stage1_rg_full
  reg stage1_rg_full;
  reg stage1_rg_full$D_IN;
  wire stage1_rg_full$EN;

  // register stage2_rg_full
  reg stage2_rg_full;
  reg stage2_rg_full$D_IN;
  wire stage2_rg_full$EN;

  // register stage2_rg_resetting
  reg stage2_rg_resetting;
  wire stage2_rg_resetting$D_IN, stage2_rg_resetting$EN;

  // register stage2_rg_stage2
  reg [169 : 0] stage2_rg_stage2;
  wire [169 : 0] stage2_rg_stage2$D_IN;
  wire stage2_rg_stage2$EN;

  // register stage3_rg_full
  reg stage3_rg_full;
  reg stage3_rg_full$D_IN;
  wire stage3_rg_full$EN;

  // register stage3_rg_stage3
  reg [103 : 0] stage3_rg_stage3;
  wire [103 : 0] stage3_rg_stage3$D_IN;
  wire stage3_rg_stage3$EN;

  // ports of submodule csr_regfile
  reg [31 : 0] csr_regfile$csr_trap_actions_xtval;
  reg [3 : 0] csr_regfile$csr_trap_actions_exc_code;
  reg [1 : 0] csr_regfile$csr_ret_actions_from_priv;
  wire [97 : 0] csr_regfile$csr_trap_actions;
  wire [65 : 0] csr_regfile$csr_ret_actions;
  wire [63 : 0] csr_regfile$read_csr_mcycle, csr_regfile$read_csr_minstret;
  wire [32 : 0] csr_regfile$read_csr;
  wire [31 : 0] csr_regfile$csr_trap_actions_pc,
		csr_regfile$mav_csr_write_word,
		csr_regfile$read_mstatus,
		csr_regfile$read_satp;
  wire [27 : 0] csr_regfile$read_misa;
  wire [11 : 0] csr_regfile$access_permitted_1_csr_addr,
		csr_regfile$access_permitted_2_csr_addr,
		csr_regfile$csr_counter_read_fault_csr_addr,
		csr_regfile$mav_csr_write_csr_addr,
		csr_regfile$mav_read_csr_csr_addr,
		csr_regfile$read_csr_csr_addr,
		csr_regfile$read_csr_port2_csr_addr;
  wire [4 : 0] csr_regfile$interrupt_pending;
  wire [1 : 0] csr_regfile$access_permitted_1_priv,
	       csr_regfile$access_permitted_2_priv,
	       csr_regfile$csr_counter_read_fault_priv,
	       csr_regfile$csr_trap_actions_from_priv,
	       csr_regfile$interrupt_pending_cur_priv;
  wire csr_regfile$EN_csr_minstret_incr,
       csr_regfile$EN_csr_ret_actions,
       csr_regfile$EN_csr_trap_actions,
       csr_regfile$EN_debug,
       csr_regfile$EN_mav_csr_write,
       csr_regfile$EN_mav_read_csr,
       csr_regfile$EN_server_reset_request_put,
       csr_regfile$EN_server_reset_response_get,
       csr_regfile$RDY_server_reset_request_put,
       csr_regfile$RDY_server_reset_response_get,
       csr_regfile$access_permitted_1,
       csr_regfile$access_permitted_1_read_not_write,
       csr_regfile$access_permitted_2,
       csr_regfile$access_permitted_2_read_not_write,
       csr_regfile$csr_trap_actions_interrupt,
       csr_regfile$csr_trap_actions_nmi,
       csr_regfile$m_external_interrupt_req_set_not_clear,
       csr_regfile$nmi_pending,
       csr_regfile$nmi_req_set_not_clear,
       csr_regfile$s_external_interrupt_req_set_not_clear,
       csr_regfile$software_interrupt_req_set_not_clear,
       csr_regfile$timer_interrupt_req_set_not_clear,
       csr_regfile$wfi_resume;

  // ports of submodule f_reset_reqs
  wire f_reset_reqs$CLR,
       f_reset_reqs$DEQ,
       f_reset_reqs$D_IN,
       f_reset_reqs$D_OUT,
       f_reset_reqs$EMPTY_N,
       f_reset_reqs$ENQ,
       f_reset_reqs$FULL_N;

  // ports of submodule f_reset_rsps
  wire f_reset_rsps$CLR,
       f_reset_rsps$DEQ,
       f_reset_rsps$D_IN,
       f_reset_rsps$D_OUT,
       f_reset_rsps$EMPTY_N,
       f_reset_rsps$ENQ,
       f_reset_rsps$FULL_N;

  // ports of submodule gpr_regfile
  wire [31 : 0] gpr_regfile$read_rs1,
		gpr_regfile$read_rs2,
		gpr_regfile$write_rd_rd_val;
  wire [4 : 0] gpr_regfile$read_rs1_port2_rs1,
	       gpr_regfile$read_rs1_rs1,
	       gpr_regfile$read_rs2_rs2,
	       gpr_regfile$write_rd_rd;
  wire gpr_regfile$EN_server_reset_request_put,
       gpr_regfile$EN_server_reset_response_get,
       gpr_regfile$EN_write_rd,
       gpr_regfile$RDY_server_reset_request_put,
       gpr_regfile$RDY_server_reset_response_get;

  // ports of submodule near_mem
  reg [31 : 0] near_mem$imem_req_addr;
  reg [1 : 0] near_mem$dmem_req_op;
  reg near_mem$imem_req_mstatus_MXR, near_mem$imem_req_sstatus_SUM;
  wire [63 : 0] near_mem$dmem_master_araddr,
		near_mem$dmem_master_awaddr,
		near_mem$dmem_master_rdata,
		near_mem$dmem_master_wdata,
		near_mem$dmem_req_store_value,
		near_mem$dmem_word64,
		near_mem$imem_master_araddr,
		near_mem$imem_master_awaddr,
		near_mem$imem_master_rdata,
		near_mem$imem_master_wdata;
  wire [31 : 0] near_mem$dmem_req_addr,
		near_mem$dmem_req_satp,
		near_mem$imem_instr,
		near_mem$imem_pc,
		near_mem$imem_req_satp;
  wire [7 : 0] near_mem$dmem_master_arlen,
	       near_mem$dmem_master_awlen,
	       near_mem$dmem_master_wstrb,
	       near_mem$imem_master_arlen,
	       near_mem$imem_master_awlen,
	       near_mem$imem_master_wstrb,
	       near_mem$server_fence_request_put;
  wire [6 : 0] near_mem$dmem_req_amo_funct7;
  wire [3 : 0] near_mem$dmem_exc_code,
	       near_mem$dmem_master_arcache,
	       near_mem$dmem_master_arid,
	       near_mem$dmem_master_arqos,
	       near_mem$dmem_master_arregion,
	       near_mem$dmem_master_awcache,
	       near_mem$dmem_master_awid,
	       near_mem$dmem_master_awqos,
	       near_mem$dmem_master_awregion,
	       near_mem$dmem_master_bid,
	       near_mem$dmem_master_rid,
	       near_mem$dmem_master_wid,
	       near_mem$imem_exc_code,
	       near_mem$imem_master_arcache,
	       near_mem$imem_master_arid,
	       near_mem$imem_master_arqos,
	       near_mem$imem_master_arregion,
	       near_mem$imem_master_awcache,
	       near_mem$imem_master_awid,
	       near_mem$imem_master_awqos,
	       near_mem$imem_master_awregion,
	       near_mem$imem_master_bid,
	       near_mem$imem_master_rid,
	       near_mem$imem_master_wid;
  wire [2 : 0] near_mem$dmem_master_arprot,
	       near_mem$dmem_master_arsize,
	       near_mem$dmem_master_awprot,
	       near_mem$dmem_master_awsize,
	       near_mem$dmem_req_f3,
	       near_mem$imem_master_arprot,
	       near_mem$imem_master_arsize,
	       near_mem$imem_master_awprot,
	       near_mem$imem_master_awsize,
	       near_mem$imem_req_f3;
  wire [1 : 0] near_mem$dmem_master_arburst,
	       near_mem$dmem_master_awburst,
	       near_mem$dmem_master_bresp,
	       near_mem$dmem_master_rresp,
	       near_mem$dmem_req_priv,
	       near_mem$imem_master_arburst,
	       near_mem$imem_master_awburst,
	       near_mem$imem_master_bresp,
	       near_mem$imem_master_rresp,
	       near_mem$imem_req_priv;
  wire near_mem$EN_dmem_req,
       near_mem$EN_imem_req,
       near_mem$EN_server_fence_i_request_put,
       near_mem$EN_server_fence_i_response_get,
       near_mem$EN_server_fence_request_put,
       near_mem$EN_server_fence_response_get,
       near_mem$EN_server_reset_request_put,
       near_mem$EN_server_reset_response_get,
       near_mem$EN_sfence_vma,
       near_mem$RDY_server_fence_i_request_put,
       near_mem$RDY_server_fence_i_response_get,
       near_mem$RDY_server_fence_request_put,
       near_mem$RDY_server_fence_response_get,
       near_mem$RDY_server_reset_request_put,
       near_mem$RDY_server_reset_response_get,
       near_mem$dmem_exc,
       near_mem$dmem_master_arlock,
       near_mem$dmem_master_arready,
       near_mem$dmem_master_arvalid,
       near_mem$dmem_master_awlock,
       near_mem$dmem_master_awready,
       near_mem$dmem_master_awvalid,
       near_mem$dmem_master_bready,
       near_mem$dmem_master_bvalid,
       near_mem$dmem_master_rlast,
       near_mem$dmem_master_rready,
       near_mem$dmem_master_rvalid,
       near_mem$dmem_master_wlast,
       near_mem$dmem_master_wready,
       near_mem$dmem_master_wvalid,
       near_mem$dmem_req_mstatus_MXR,
       near_mem$dmem_req_sstatus_SUM,
       near_mem$dmem_valid,
       near_mem$imem_exc,
       near_mem$imem_is_i32_not_i16,
       near_mem$imem_master_arlock,
       near_mem$imem_master_arready,
       near_mem$imem_master_arvalid,
       near_mem$imem_master_awlock,
       near_mem$imem_master_awready,
       near_mem$imem_master_awvalid,
       near_mem$imem_master_bready,
       near_mem$imem_master_bvalid,
       near_mem$imem_master_rlast,
       near_mem$imem_master_rready,
       near_mem$imem_master_rvalid,
       near_mem$imem_master_wlast,
       near_mem$imem_master_wready,
       near_mem$imem_master_wvalid,
       near_mem$imem_valid;

  // ports of submodule soc_map
  wire [63 : 0] soc_map$m_is_IO_addr_addr,
		soc_map$m_is_mem_addr_addr,
		soc_map$m_is_near_mem_IO_addr_addr,
		soc_map$m_pc_reset_value;

  // ports of submodule stage1_f_reset_reqs
  wire stage1_f_reset_reqs$CLR,
       stage1_f_reset_reqs$DEQ,
       stage1_f_reset_reqs$EMPTY_N,
       stage1_f_reset_reqs$ENQ,
       stage1_f_reset_reqs$FULL_N;

  // ports of submodule stage1_f_reset_rsps
  wire stage1_f_reset_rsps$CLR,
       stage1_f_reset_rsps$DEQ,
       stage1_f_reset_rsps$EMPTY_N,
       stage1_f_reset_rsps$ENQ,
       stage1_f_reset_rsps$FULL_N;

  // ports of submodule stage2_f_reset_reqs
  wire stage2_f_reset_reqs$CLR,
       stage2_f_reset_reqs$DEQ,
       stage2_f_reset_reqs$EMPTY_N,
       stage2_f_reset_reqs$ENQ,
       stage2_f_reset_reqs$FULL_N;

  // ports of submodule stage2_f_reset_rsps
  wire stage2_f_reset_rsps$CLR,
       stage2_f_reset_rsps$DEQ,
       stage2_f_reset_rsps$EMPTY_N,
       stage2_f_reset_rsps$ENQ,
       stage2_f_reset_rsps$FULL_N;

  // ports of submodule stage2_mbox
  wire [31 : 0] stage2_mbox$req_v1, stage2_mbox$req_v2, stage2_mbox$word;
  wire [3 : 0] stage2_mbox$set_verbosity_verbosity;
  wire [2 : 0] stage2_mbox$req_f3;
  wire stage2_mbox$EN_req,
       stage2_mbox$EN_req_reset,
       stage2_mbox$EN_rsp_reset,
       stage2_mbox$EN_set_verbosity,
       stage2_mbox$req_is_OP_not_OP_32,
       stage2_mbox$valid;

  // ports of submodule stage3_f_reset_reqs
  wire stage3_f_reset_reqs$CLR,
       stage3_f_reset_reqs$DEQ,
       stage3_f_reset_reqs$EMPTY_N,
       stage3_f_reset_reqs$ENQ,
       stage3_f_reset_reqs$FULL_N;

  // ports of submodule stage3_f_reset_rsps
  wire stage3_f_reset_rsps$CLR,
       stage3_f_reset_rsps$DEQ,
       stage3_f_reset_rsps$EMPTY_N,
       stage3_f_reset_rsps$ENQ,
       stage3_f_reset_rsps$FULL_N;

  // rule scheduling signals
  wire CAN_FIRE_RL_imem_rl_assert_fail,
       CAN_FIRE_RL_imem_rl_fetch_next_32b,
       CAN_FIRE_RL_rl_WFI_resume,
       CAN_FIRE_RL_rl_finish_FENCE,
       CAN_FIRE_RL_rl_finish_FENCE_I,
       CAN_FIRE_RL_rl_finish_SFENCE_VMA,
       CAN_FIRE_RL_rl_pipe,
       CAN_FIRE_RL_rl_reset_complete,
       CAN_FIRE_RL_rl_reset_from_WFI,
       CAN_FIRE_RL_rl_reset_start,
       CAN_FIRE_RL_rl_show_pipe,
       CAN_FIRE_RL_rl_stage1_CSRR_S_or_C,
       CAN_FIRE_RL_rl_stage1_CSRR_W,
       CAN_FIRE_RL_rl_stage1_FENCE,
       CAN_FIRE_RL_rl_stage1_FENCE_I,
       CAN_FIRE_RL_rl_stage1_SFENCE_VMA,
       CAN_FIRE_RL_rl_stage1_WFI,
       CAN_FIRE_RL_rl_stage1_interrupt,
       CAN_FIRE_RL_rl_stage1_restart_after_csrrx,
       CAN_FIRE_RL_rl_stage1_trap,
       CAN_FIRE_RL_rl_stage1_xRET,
       CAN_FIRE_RL_rl_stage2_nonpipe,
       CAN_FIRE_RL_rl_trap_fetch,
       CAN_FIRE_RL_stage1_rl_reset,
       CAN_FIRE_RL_stage2_rl_reset_begin,
       CAN_FIRE_RL_stage2_rl_reset_end,
       CAN_FIRE_RL_stage3_rl_reset,
       CAN_FIRE_dmem_master_m_arready,
       CAN_FIRE_dmem_master_m_awready,
       CAN_FIRE_dmem_master_m_bvalid,
       CAN_FIRE_dmem_master_m_rvalid,
       CAN_FIRE_dmem_master_m_wready,
       CAN_FIRE_hart0_server_reset_request_put,
       CAN_FIRE_hart0_server_reset_response_get,
       CAN_FIRE_imem_master_m_arready,
       CAN_FIRE_imem_master_m_awready,
       CAN_FIRE_imem_master_m_bvalid,
       CAN_FIRE_imem_master_m_rvalid,
       CAN_FIRE_imem_master_m_wready,
       CAN_FIRE_m_external_interrupt_req,
       CAN_FIRE_nmi_req,
       CAN_FIRE_s_external_interrupt_req,
       CAN_FIRE_set_verbosity,
       CAN_FIRE_software_interrupt_req,
       CAN_FIRE_timer_interrupt_req,
       WILL_FIRE_RL_imem_rl_assert_fail,
       WILL_FIRE_RL_imem_rl_fetch_next_32b,
       WILL_FIRE_RL_rl_WFI_resume,
       WILL_FIRE_RL_rl_finish_FENCE,
       WILL_FIRE_RL_rl_finish_FENCE_I,
       WILL_FIRE_RL_rl_finish_SFENCE_VMA,
       WILL_FIRE_RL_rl_pipe,
       WILL_FIRE_RL_rl_reset_complete,
       WILL_FIRE_RL_rl_reset_from_WFI,
       WILL_FIRE_RL_rl_reset_start,
       WILL_FIRE_RL_rl_show_pipe,
       WILL_FIRE_RL_rl_stage1_CSRR_S_or_C,
       WILL_FIRE_RL_rl_stage1_CSRR_W,
       WILL_FIRE_RL_rl_stage1_FENCE,
       WILL_FIRE_RL_rl_stage1_FENCE_I,
       WILL_FIRE_RL_rl_stage1_SFENCE_VMA,
       WILL_FIRE_RL_rl_stage1_WFI,
       WILL_FIRE_RL_rl_stage1_interrupt,
       WILL_FIRE_RL_rl_stage1_restart_after_csrrx,
       WILL_FIRE_RL_rl_stage1_trap,
       WILL_FIRE_RL_rl_stage1_xRET,
       WILL_FIRE_RL_rl_stage2_nonpipe,
       WILL_FIRE_RL_rl_trap_fetch,
       WILL_FIRE_RL_stage1_rl_reset,
       WILL_FIRE_RL_stage2_rl_reset_begin,
       WILL_FIRE_RL_stage2_rl_reset_end,
       WILL_FIRE_RL_stage3_rl_reset,
       WILL_FIRE_dmem_master_m_arready,
       WILL_FIRE_dmem_master_m_awready,
       WILL_FIRE_dmem_master_m_bvalid,
       WILL_FIRE_dmem_master_m_rvalid,
       WILL_FIRE_dmem_master_m_wready,
       WILL_FIRE_hart0_server_reset_request_put,
       WILL_FIRE_hart0_server_reset_response_get,
       WILL_FIRE_imem_master_m_arready,
       WILL_FIRE_imem_master_m_awready,
       WILL_FIRE_imem_master_m_bvalid,
       WILL_FIRE_imem_master_m_rvalid,
       WILL_FIRE_imem_master_m_wready,
       WILL_FIRE_m_external_interrupt_req,
       WILL_FIRE_nmi_req,
       WILL_FIRE_s_external_interrupt_req,
       WILL_FIRE_set_verbosity,
       WILL_FIRE_software_interrupt_req,
       WILL_FIRE_timer_interrupt_req;

  // inputs to muxes for submodule ports
  reg [31 : 0] MUX_csr_regfile$mav_csr_write_2__VAL_2;
  wire [31 : 0] MUX_near_mem$imem_req_2__VAL_1,
		MUX_near_mem$imem_req_2__VAL_2,
		MUX_near_mem$imem_req_2__VAL_5;
  wire [3 : 0] MUX_csr_regfile$csr_trap_actions_5__VAL_1,
	       MUX_rg_state$write_1__VAL_1,
	       MUX_rg_state$write_1__VAL_2,
	       MUX_rg_state$write_1__VAL_3;
  wire MUX_csr_regfile$mav_csr_write_1__SEL_1,
       MUX_gpr_regfile$write_rd_1__SEL_1,
       MUX_gpr_regfile$write_rd_1__SEL_3,
       MUX_imem_rg_f3$write_1__SEL_1,
       MUX_imem_rg_f3$write_1__SEL_2,
       MUX_imem_rg_mstatus_MXR$write_1__SEL_4,
       MUX_imem_rg_pc$write_1__SEL_4,
       MUX_near_mem$imem_req_1__SEL_6,
       MUX_rg_cur_priv$write_1__SEL_1,
       MUX_rg_mstatus_MXR$write_1__SEL_1,
       MUX_rg_next_pc$write_1__SEL_1,
       MUX_rg_state$write_1__SEL_1,
       MUX_rg_state$write_1__SEL_10,
       MUX_rg_state$write_1__SEL_11,
       MUX_rg_state$write_1__SEL_2,
       MUX_rg_state$write_1__SEL_3,
       MUX_rg_state$write_1__SEL_4,
       MUX_rg_state$write_1__SEL_6,
       MUX_rg_state$write_1__SEL_7,
       MUX_rg_state$write_1__SEL_8,
       MUX_rg_state$write_1__SEL_9,
       MUX_stage1_rg_full$write_1__VAL_2,
       MUX_stage2_rg_full$write_1__VAL_2;

  // remaining internal signals
  reg [31 : 0] IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d1021,
	       IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d936,
	       _theResult_____1_fst__h12725,
	       rs1_val__h17721,
	       x_out_bypass_rd_val__h5993,
	       x_out_data_to_stage2_addr__h11615,
	       x_out_data_to_stage2_val1__h11616,
	       x_out_data_to_stage3_rd_val__h5642;
  reg [4 : 0] x_out_bypass_rd__h5992, x_out_data_to_stage3_rd__h5641;
  reg [3 : 0] CASE_rg_cur_priv_0b0_8_0b1_9_11__q5,
	      CASE_theResult__280_BITS_14_TO_12_0b0_0_0b1_0__ETC__q12,
	      CASE_theResult__280_BITS_14_TO_12_0b0_0_0b1_0__ETC__q14,
	      CASE_theResult__280_BITS_14_TO_12_0b0_4_0b1_5_11__q13,
	      CASE_theResult__280_BITS_14_TO_12_0b0_IF_theRe_ETC__q15,
	      CASE_theResult__280_BITS_31_TO_20_0b0_CASE_rg__ETC__q6,
	      IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d725,
	      IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d740,
	      IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d744,
	      alu_outputs_exc_code__h12281;
  reg [2 : 0] CASE_theResult__280_BITS_6_TO_0_0b11_1_0b10011_ETC__q16,
	      IF_NOT_stage1_rg_full_94_95_OR_NOT_near_mem_im_ETC___d825;
  reg [1 : 0] CASE_stage2_rg_stage2_BITS_103_TO_101_0_2_1_IF_ETC__q1,
	      CASE_stage2_rg_stage2_BITS_103_TO_101_0_2_1_IF_ETC__q2;
  reg CASE_theResult__280_BITS_6_TO_0_0b10011_IF_NOT_ETC__q11,
      CASE_theResult__280_BITS_6_TO_0_0b10011_NOT_IF_ETC__q9,
      CASE_theResult__280_BITS_6_TO_0_0b11_NOT_theRe_ETC__q8,
      CASE_theResult__280_BITS_6_TO_0_0b11_theResult_ETC__q10,
      IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d534,
      IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d628,
      IF_stage2_rg_stage2_8_BITS_103_TO_101_9_EQ_1_1_ETC___d132,
      IF_stage2_rg_stage2_8_BITS_103_TO_101_9_EQ_1_1_ETC___d141;
  wire [127 : 0] csr_regfile_read_csr_mcycle__2_MINUS_rg_start__ETC___d1273;
  wire [63 : 0] _theResult____h22285,
		cpi__h22287,
		cpifrac__h22288,
		delta_CPI_cycles__h22283,
		delta_CPI_instrs___1__h22320,
		delta_CPI_instrs__h22284,
		x__h22286;
  wire [31 : 0] IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d937,
		IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS_2_9_ETC___d869,
		IF_csr_regfile_read_csr_IF_NOT_stage1_rg_full__ETC___d1220,
		IF_csr_regfile_read_misa__0_BIT_2_12_AND_IF_ne_ETC___d437,
		IF_csr_regfile_read_misa__0_BIT_2_12_AND_IF_ne_ETC___d439,
		IF_csr_regfile_read_misa__0_BIT_2_12_AND_IF_ne_ETC___d441,
		IF_csr_regfile_read_misa__0_BIT_2_12_AND_IF_ne_ETC___d442,
		IF_csr_regfile_read_misa__0_BIT_2_12_AND_IF_ne_ETC___d444,
		IF_csr_regfile_read_misa__0_BIT_2_12_AND_IF_ne_ETC___d445,
		IF_csr_regfile_read_misa__0_BIT_2_12_AND_IF_ne_ETC___d446,
		IF_csr_regfile_read_misa__0_BIT_2_12_AND_IF_ne_ETC___d448,
		IF_csr_regfile_read_misa__0_BIT_2_12_AND_IF_ne_ETC___d449,
		IF_csr_regfile_read_misa__0_BIT_2_12_AND_IF_ne_ETC___d450,
		IF_csr_regfile_read_misa__0_BIT_2_12_AND_IF_ne_ETC___d452,
		IF_csr_regfile_read_misa__0_BIT_2_12_AND_IF_ne_ETC___d453,
		IF_csr_regfile_read_misa__0_BIT_2_12_AND_IF_ne_ETC___d454,
		IF_csr_regfile_read_misa__0_BIT_2_12_AND_IF_ne_ETC___d455,
		IF_csr_regfile_read_misa__0_BIT_2_12_AND_IF_ne_ETC___d456,
		IF_csr_regfile_read_misa__0_BIT_2_12_AND_IF_ne_ETC___d457,
		IF_csr_regfile_read_misa__0_BIT_2_12_AND_IF_ne_ETC___d458,
		IF_csr_regfile_read_misa__0_BIT_2_12_AND_IF_ne_ETC___d459,
		IF_csr_regfile_read_misa__0_BIT_2_12_AND_IF_ne_ETC___d460,
		SEXT_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLU_ETC___d878,
		_theResult_____1_fst__h12718,
		_theResult_____1_fst__h12753,
		_theResult____h4280,
		_theResult___fst__h6320,
		_theResult___fst__h6348,
		_theResult___snd__h13851,
		alu_outputs___1_addr__h11739,
		alu_outputs___1_addr__h11760,
		alu_outputs___1_addr__h11786,
		alu_outputs___1_addr__h11981,
		alu_outputs___1_addr__h12002,
		alu_outputs___1_val1__h11890,
		alu_outputs___1_val1__h11928,
		alu_outputs___1_val1__h11944,
		alu_outputs___1_val1__h11960,
		alu_outputs___1_val1__h12242,
		alu_outputs___1_val1__h12263,
		branch_target__h11717,
		data_to_stage2_addr__h11607,
		fall_through_pc__h11571,
		instr___1__h6153,
		instr__h10038,
		instr__h10231,
		instr__h10348,
		instr__h10526,
		instr__h10645,
		instr__h10740,
		instr__h10876,
		instr__h11012,
		instr__h11148,
		instr__h11486,
		instr__h4278,
		instr__h6420,
		instr__h6565,
		instr__h6757,
		instr__h6952,
		instr__h7181,
		instr__h7524,
		instr__h7914,
		instr__h8030,
		instr__h8095,
		instr__h8412,
		instr__h8750,
		instr__h8934,
		instr__h9063,
		instr__h9500,
		instr__h9672,
		instr__h9845,
		instr_out___1__h6290,
		instr_out___1__h6322,
		instr_out___1__h6350,
		next_pc___1__h13393,
		next_pc__h13391,
		output_stage2___1_bypass_rd_val__h5981,
		rd_val___1__h12706,
		rd_val___1__h12714,
		rd_val___1__h12721,
		rd_val___1__h12728,
		rd_val___1__h12735,
		rd_val___1__h12742,
		rd_val__h11528,
		rd_val__h13747,
		rd_val__h13799,
		rd_val__h13821,
		rd_val__h6105,
		rs1_val__h17231,
		rs1_val_bypassed__h4288,
		rs2_val__h11713,
		trap_info_tval__h13230,
		val__h11530,
		val__h6107,
		value__h13281,
		x_out_data_to_stage2_instr__h11612,
		x_out_data_to_stage2_val2__h11617,
		x_out_next_pc__h11584,
		y__h18022;
  wire [20 : 0] SEXT_IF_near_mem_imem_pc_EQ_imem_rg_pc_PLUS_2__ETC___d288,
		theResult__280_BIT_31_CONCAT_theResult__280_BI_ETC__q4;
  wire [19 : 0] imm20__h8802;
  wire [12 : 0] SEXT_IF_near_mem_imem_pc_EQ_imem_rg_pc_PLUS_2__ETC___d317,
		theResult__280_BIT_31_CONCAT_theResult__280_BI_ETC__q3;
  wire [11 : 0] imm12__h10054,
		imm12__h6421,
		imm12__h6758,
		imm12__h8674,
		imm12__h9298,
		imm12__h9513,
		imm12__h9709,
		offset__h7128,
		theResult__280_BITS_31_TO_20__q17,
		theResult__280_BITS_31_TO_25_CONCAT_theResult__ETC__q7;
  wire [9 : 0] nzimm10__h9296, nzimm10__h9511;
  wire [8 : 0] offset__h8039;
  wire [7 : 0] offset__h6191;
  wire [6 : 0] offset__h6700;
  wire [5 : 0] imm6__h8672;
  wire [4 : 0] offset_BITS_4_TO_0___h6689,
	       offset_BITS_4_TO_0___h7120,
	       rd__h6760,
	       rs1__h6759,
	       shamt__h11875,
	       x_out_data_to_stage2_rd__h11614;
  wire [3 : 0] IF_NOT_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_P_ETC___d690,
	       IF_NOT_stage1_rg_full_94_95_OR_NOT_near_mem_im_ETC___d746,
	       IF_rg_cur_priv_3_EQ_0b11_04_OR_rg_cur_priv_3_E_ETC___d723,
	       alu_outputs___1_exc_code__h12238,
	       cur_verbosity__h2985,
	       x_out_trap_info_exc_code__h13233;
  wire [1 : 0] IF_NOT_near_mem_dmem_valid__09_28_OR_NOT_near__ETC___d176,
	       IF_near_mem_dmem_valid__09_THEN_IF_near_mem_dm_ETC___d112,
	       IF_stage2_rg_full_7_THEN_IF_stage2_rg_stage2_8_ETC___d118,
	       IF_stage2_rg_full_7_THEN_IF_stage2_rg_stage2_8_ETC___d180,
	       IF_stage2_rg_stage2_8_BITS_100_TO_96_48_EQ_0_7_ETC___d175,
	       IF_stage2_rg_stage2_8_BITS_103_TO_101_9_EQ_3_5_ETC___d115;
  wire IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d1080,
       IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d523,
       IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d525,
       IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d527,
       IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d622,
       IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d633,
       IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d680,
       IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d682,
       IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS_2_9_ETC___d653,
       IF_NOT_stage1_rg_full_94_95_OR_NOT_near_mem_im_ETC___d1270,
       IF_stage2_rg_full_7_THEN_IF_stage2_rg_stage2_8_ETC___d464,
       IF_stage2_rg_full_7_THEN_IF_stage2_rg_stage2_8_ETC___d466,
       NOT_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS_ETC___d564,
       NOT_IF_csr_regfile_read_csr_minstret__5_ULT_cf_ETC___d41,
       NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d1112,
       NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d1130,
       NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d1133,
       NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d1154,
       NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d1163,
       NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d1165,
       NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d1168,
       NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d1182,
       NOT_near_mem_imem_exc__85_38_AND_IF_IF_NOT_nea_ETC___d812,
       NOT_near_mem_imem_exc__85_38_AND_IF_IF_NOT_nea_ETC___d849,
       NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS_2_9_97_ETC___d205,
       NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS_2_9_97_ETC___d210,
       NOT_near_mem_imem_valid_96_OR_NOT_near_mem_ime_ETC___d1090,
       NOT_near_mem_imem_valid_96_OR_NOT_near_mem_ime_ETC___d1101,
       NOT_near_mem_imem_valid_96_OR_NOT_near_mem_ime_ETC___d1109,
       NOT_near_mem_imem_valid_96_OR_NOT_near_mem_ime_ETC___d469,
       _0_OR_0_OR_near_mem_imem_exc__85_OR_IF_IF_NOT_n_ETC___d1161,
       csr_regfile_interrupt_pending_rg_cur_priv_3_07_ETC___d1083,
       csr_regfile_interrupt_pending_rg_cur_priv_3_07_ETC___d1088,
       csr_regfile_interrupt_pending_rg_cur_priv_3_07_ETC___d1094,
       csr_regfile_read_misa__0_BIT_2_12_AND_IF_near__ETC___d302,
       csr_regfile_read_misa__0_BIT_2_12_AND_IF_near__ETC___d308,
       gpr_regfile_RDY_server_reset_request_put__031__ETC___d1043,
       near_mem_imem_exc__85_OR_IF_IF_NOT_near_mem_im_ETC___d949,
       near_mem_imem_exc__85_OR_IF_IF_NOT_near_mem_im_ETC___d952,
       near_mem_imem_exc__85_OR_IF_IF_NOT_near_mem_im_ETC___d955,
       near_mem_imem_exc__85_OR_IF_IF_NOT_near_mem_im_ETC___d958,
       near_mem_imem_exc__85_OR_IF_IF_NOT_near_mem_im_ETC___d961,
       near_mem_imem_exc__85_OR_IF_IF_NOT_near_mem_im_ETC___d964,
       near_mem_imem_exc__85_OR_IF_IF_NOT_near_mem_im_ETC___d967,
       near_mem_imem_exc__85_OR_IF_IF_NOT_near_mem_im_ETC___d970,
       near_mem_imem_exc__85_OR_IF_IF_NOT_near_mem_im_ETC___d973,
       near_mem_imem_exc__85_OR_IF_IF_NOT_near_mem_im_ETC___d976,
       near_mem_imem_exc__85_OR_IF_IF_NOT_near_mem_im_ETC___d979,
       near_mem_imem_exc__85_OR_IF_IF_NOT_near_mem_im_ETC___d982,
       near_mem_imem_pc_BITS_31_TO_2_EQ_imem_rg_pc_BI_ETC___d8,
       near_mem_imem_pc_EQ_imem_rg_pc_PLUS_2_9_97_OR__ETC___d476,
       near_mem_imem_pc_EQ_imem_rg_pc_PLUS_2_9_97_OR__ETC___d478,
       near_mem_imem_pc_EQ_imem_rg_pc_PLUS_2_9___d197,
       near_mem_imem_valid_AND_near_mem_imem_pc_EQ_im_ETC___d1079,
       near_mem_imem_valid_AND_near_mem_imem_pc_EQ_im_ETC___d484,
       near_mem_imem_valid_AND_near_mem_imem_pc_EQ_im_ETC___d636,
       near_mem_imem_valid_AND_near_mem_imem_pc_EQ_im_ETC___d685,
       rg_cur_priv_3_EQ_0b11_04_OR_rg_cur_priv_3_EQ_0_ETC___d721,
       rg_state_2_EQ_3_096_AND_NOT_csr_regfile_interr_ETC___d1185,
       rg_state_2_EQ_3_096_AND_stage3_rg_full_8_OR_NO_ETC___d1115,
       stage2_f_reset_rsps_i_notEmpty__052_AND_stage3_ETC___d1061;

  // action method hart0_server_reset_request_put
  assign RDY_hart0_server_reset_request_put = f_reset_reqs$FULL_N ;
  assign CAN_FIRE_hart0_server_reset_request_put = f_reset_reqs$FULL_N ;
  assign WILL_FIRE_hart0_server_reset_request_put =
	     EN_hart0_server_reset_request_put ;

  // actionvalue method hart0_server_reset_response_get
  assign hart0_server_reset_response_get = f_reset_rsps$D_OUT ;
  assign RDY_hart0_server_reset_response_get = f_reset_rsps$EMPTY_N ;
  assign CAN_FIRE_hart0_server_reset_response_get = f_reset_rsps$EMPTY_N ;
  assign WILL_FIRE_hart0_server_reset_response_get =
	     EN_hart0_server_reset_response_get ;

  // value method imem_master_m_awvalid
  assign imem_master_awvalid = near_mem$imem_master_awvalid ;

  // value method imem_master_m_awid
  assign imem_master_awid = near_mem$imem_master_awid ;

  // value method imem_master_m_awaddr
  assign imem_master_awaddr = near_mem$imem_master_awaddr ;

  // value method imem_master_m_awlen
  assign imem_master_awlen = near_mem$imem_master_awlen ;

  // value method imem_master_m_awsize
  assign imem_master_awsize = near_mem$imem_master_awsize ;

  // value method imem_master_m_awburst
  assign imem_master_awburst = near_mem$imem_master_awburst ;

  // value method imem_master_m_awlock
  assign imem_master_awlock = near_mem$imem_master_awlock ;

  // value method imem_master_m_awcache
  assign imem_master_awcache = near_mem$imem_master_awcache ;

  // value method imem_master_m_awprot
  assign imem_master_awprot = near_mem$imem_master_awprot ;

  // value method imem_master_m_awqos
  assign imem_master_awqos = near_mem$imem_master_awqos ;

  // value method imem_master_m_awregion
  assign imem_master_awregion = near_mem$imem_master_awregion ;

  // action method imem_master_m_awready
  assign CAN_FIRE_imem_master_m_awready = 1'd1 ;
  assign WILL_FIRE_imem_master_m_awready = 1'd1 ;

  // value method imem_master_m_wvalid
  assign imem_master_wvalid = near_mem$imem_master_wvalid ;

  // value method imem_master_m_wid
  assign imem_master_wid = near_mem$imem_master_wid ;

  // value method imem_master_m_wdata
  assign imem_master_wdata = near_mem$imem_master_wdata ;

  // value method imem_master_m_wstrb
  assign imem_master_wstrb = near_mem$imem_master_wstrb ;

  // value method imem_master_m_wlast
  assign imem_master_wlast = near_mem$imem_master_wlast ;

  // action method imem_master_m_wready
  assign CAN_FIRE_imem_master_m_wready = 1'd1 ;
  assign WILL_FIRE_imem_master_m_wready = 1'd1 ;

  // action method imem_master_m_bvalid
  assign CAN_FIRE_imem_master_m_bvalid = 1'd1 ;
  assign WILL_FIRE_imem_master_m_bvalid = 1'd1 ;

  // value method imem_master_m_bready
  assign imem_master_bready = near_mem$imem_master_bready ;

  // value method imem_master_m_arvalid
  assign imem_master_arvalid = near_mem$imem_master_arvalid ;

  // value method imem_master_m_arid
  assign imem_master_arid = near_mem$imem_master_arid ;

  // value method imem_master_m_araddr
  assign imem_master_araddr = near_mem$imem_master_araddr ;

  // value method imem_master_m_arlen
  assign imem_master_arlen = near_mem$imem_master_arlen ;

  // value method imem_master_m_arsize
  assign imem_master_arsize = near_mem$imem_master_arsize ;

  // value method imem_master_m_arburst
  assign imem_master_arburst = near_mem$imem_master_arburst ;

  // value method imem_master_m_arlock
  assign imem_master_arlock = near_mem$imem_master_arlock ;

  // value method imem_master_m_arcache
  assign imem_master_arcache = near_mem$imem_master_arcache ;

  // value method imem_master_m_arprot
  assign imem_master_arprot = near_mem$imem_master_arprot ;

  // value method imem_master_m_arqos
  assign imem_master_arqos = near_mem$imem_master_arqos ;

  // value method imem_master_m_arregion
  assign imem_master_arregion = near_mem$imem_master_arregion ;

  // action method imem_master_m_arready
  assign CAN_FIRE_imem_master_m_arready = 1'd1 ;
  assign WILL_FIRE_imem_master_m_arready = 1'd1 ;

  // action method imem_master_m_rvalid
  assign CAN_FIRE_imem_master_m_rvalid = 1'd1 ;
  assign WILL_FIRE_imem_master_m_rvalid = 1'd1 ;

  // value method imem_master_m_rready
  assign imem_master_rready = near_mem$imem_master_rready ;

  // value method dmem_master_m_awvalid
  assign dmem_master_awvalid = near_mem$dmem_master_awvalid ;

  // value method dmem_master_m_awid
  assign dmem_master_awid = near_mem$dmem_master_awid ;

  // value method dmem_master_m_awaddr
  assign dmem_master_awaddr = near_mem$dmem_master_awaddr ;

  // value method dmem_master_m_awlen
  assign dmem_master_awlen = near_mem$dmem_master_awlen ;

  // value method dmem_master_m_awsize
  assign dmem_master_awsize = near_mem$dmem_master_awsize ;

  // value method dmem_master_m_awburst
  assign dmem_master_awburst = near_mem$dmem_master_awburst ;

  // value method dmem_master_m_awlock
  assign dmem_master_awlock = near_mem$dmem_master_awlock ;

  // value method dmem_master_m_awcache
  assign dmem_master_awcache = near_mem$dmem_master_awcache ;

  // value method dmem_master_m_awprot
  assign dmem_master_awprot = near_mem$dmem_master_awprot ;

  // value method dmem_master_m_awqos
  assign dmem_master_awqos = near_mem$dmem_master_awqos ;

  // value method dmem_master_m_awregion
  assign dmem_master_awregion = near_mem$dmem_master_awregion ;

  // action method dmem_master_m_awready
  assign CAN_FIRE_dmem_master_m_awready = 1'd1 ;
  assign WILL_FIRE_dmem_master_m_awready = 1'd1 ;

  // value method dmem_master_m_wvalid
  assign dmem_master_wvalid = near_mem$dmem_master_wvalid ;

  // value method dmem_master_m_wid
  assign dmem_master_wid = near_mem$dmem_master_wid ;

  // value method dmem_master_m_wdata
  assign dmem_master_wdata = near_mem$dmem_master_wdata ;

  // value method dmem_master_m_wstrb
  assign dmem_master_wstrb = near_mem$dmem_master_wstrb ;

  // value method dmem_master_m_wlast
  assign dmem_master_wlast = near_mem$dmem_master_wlast ;

  // action method dmem_master_m_wready
  assign CAN_FIRE_dmem_master_m_wready = 1'd1 ;
  assign WILL_FIRE_dmem_master_m_wready = 1'd1 ;

  // action method dmem_master_m_bvalid
  assign CAN_FIRE_dmem_master_m_bvalid = 1'd1 ;
  assign WILL_FIRE_dmem_master_m_bvalid = 1'd1 ;

  // value method dmem_master_m_bready
  assign dmem_master_bready = near_mem$dmem_master_bready ;

  // value method dmem_master_m_arvalid
  assign dmem_master_arvalid = near_mem$dmem_master_arvalid ;

  // value method dmem_master_m_arid
  assign dmem_master_arid = near_mem$dmem_master_arid ;

  // value method dmem_master_m_araddr
  assign dmem_master_araddr = near_mem$dmem_master_araddr ;

  // value method dmem_master_m_arlen
  assign dmem_master_arlen = near_mem$dmem_master_arlen ;

  // value method dmem_master_m_arsize
  assign dmem_master_arsize = near_mem$dmem_master_arsize ;

  // value method dmem_master_m_arburst
  assign dmem_master_arburst = near_mem$dmem_master_arburst ;

  // value method dmem_master_m_arlock
  assign dmem_master_arlock = near_mem$dmem_master_arlock ;

  // value method dmem_master_m_arcache
  assign dmem_master_arcache = near_mem$dmem_master_arcache ;

  // value method dmem_master_m_arprot
  assign dmem_master_arprot = near_mem$dmem_master_arprot ;

  // value method dmem_master_m_arqos
  assign dmem_master_arqos = near_mem$dmem_master_arqos ;

  // value method dmem_master_m_arregion
  assign dmem_master_arregion = near_mem$dmem_master_arregion ;

  // action method dmem_master_m_arready
  assign CAN_FIRE_dmem_master_m_arready = 1'd1 ;
  assign WILL_FIRE_dmem_master_m_arready = 1'd1 ;

  // action method dmem_master_m_rvalid
  assign CAN_FIRE_dmem_master_m_rvalid = 1'd1 ;
  assign WILL_FIRE_dmem_master_m_rvalid = 1'd1 ;

  // value method dmem_master_m_rready
  assign dmem_master_rready = near_mem$dmem_master_rready ;

  // action method m_external_interrupt_req
  assign CAN_FIRE_m_external_interrupt_req = 1'd1 ;
  assign WILL_FIRE_m_external_interrupt_req = 1'd1 ;

  // action method s_external_interrupt_req
  assign CAN_FIRE_s_external_interrupt_req = 1'd1 ;
  assign WILL_FIRE_s_external_interrupt_req = 1'd1 ;

  // action method software_interrupt_req
  assign CAN_FIRE_software_interrupt_req = 1'd1 ;
  assign WILL_FIRE_software_interrupt_req = 1'd1 ;

  // action method timer_interrupt_req
  assign CAN_FIRE_timer_interrupt_req = 1'd1 ;
  assign WILL_FIRE_timer_interrupt_req = 1'd1 ;

  // action method nmi_req
  assign CAN_FIRE_nmi_req = 1'd1 ;
  assign WILL_FIRE_nmi_req = 1'd1 ;

  // action method set_verbosity
  assign RDY_set_verbosity = 1'd1 ;
  assign CAN_FIRE_set_verbosity = 1'd1 ;
  assign WILL_FIRE_set_verbosity = EN_set_verbosity ;

  // submodule csr_regfile
  mkCSR_RegFile csr_regfile(.CLK(CLK),
			    .RST_N(RST_N),
			    .access_permitted_1_csr_addr(csr_regfile$access_permitted_1_csr_addr),
			    .access_permitted_1_priv(csr_regfile$access_permitted_1_priv),
			    .access_permitted_1_read_not_write(csr_regfile$access_permitted_1_read_not_write),
			    .access_permitted_2_csr_addr(csr_regfile$access_permitted_2_csr_addr),
			    .access_permitted_2_priv(csr_regfile$access_permitted_2_priv),
			    .access_permitted_2_read_not_write(csr_regfile$access_permitted_2_read_not_write),
			    .csr_counter_read_fault_csr_addr(csr_regfile$csr_counter_read_fault_csr_addr),
			    .csr_counter_read_fault_priv(csr_regfile$csr_counter_read_fault_priv),
			    .csr_ret_actions_from_priv(csr_regfile$csr_ret_actions_from_priv),
			    .csr_trap_actions_exc_code(csr_regfile$csr_trap_actions_exc_code),
			    .csr_trap_actions_from_priv(csr_regfile$csr_trap_actions_from_priv),
			    .csr_trap_actions_interrupt(csr_regfile$csr_trap_actions_interrupt),
			    .csr_trap_actions_nmi(csr_regfile$csr_trap_actions_nmi),
			    .csr_trap_actions_pc(csr_regfile$csr_trap_actions_pc),
			    .csr_trap_actions_xtval(csr_regfile$csr_trap_actions_xtval),
			    .interrupt_pending_cur_priv(csr_regfile$interrupt_pending_cur_priv),
			    .m_external_interrupt_req_set_not_clear(csr_regfile$m_external_interrupt_req_set_not_clear),
			    .mav_csr_write_csr_addr(csr_regfile$mav_csr_write_csr_addr),
			    .mav_csr_write_word(csr_regfile$mav_csr_write_word),
			    .mav_read_csr_csr_addr(csr_regfile$mav_read_csr_csr_addr),
			    .nmi_req_set_not_clear(csr_regfile$nmi_req_set_not_clear),
			    .read_csr_csr_addr(csr_regfile$read_csr_csr_addr),
			    .read_csr_port2_csr_addr(csr_regfile$read_csr_port2_csr_addr),
			    .s_external_interrupt_req_set_not_clear(csr_regfile$s_external_interrupt_req_set_not_clear),
			    .software_interrupt_req_set_not_clear(csr_regfile$software_interrupt_req_set_not_clear),
			    .timer_interrupt_req_set_not_clear(csr_regfile$timer_interrupt_req_set_not_clear),
			    .EN_server_reset_request_put(csr_regfile$EN_server_reset_request_put),
			    .EN_server_reset_response_get(csr_regfile$EN_server_reset_response_get),
			    .EN_mav_read_csr(csr_regfile$EN_mav_read_csr),
			    .EN_mav_csr_write(csr_regfile$EN_mav_csr_write),
			    .EN_csr_trap_actions(csr_regfile$EN_csr_trap_actions),
			    .EN_csr_ret_actions(csr_regfile$EN_csr_ret_actions),
			    .EN_csr_minstret_incr(csr_regfile$EN_csr_minstret_incr),
			    .EN_debug(csr_regfile$EN_debug),
			    .RDY_server_reset_request_put(csr_regfile$RDY_server_reset_request_put),
			    .RDY_server_reset_response_get(csr_regfile$RDY_server_reset_response_get),
			    .read_csr(csr_regfile$read_csr),
			    .read_csr_port2(),
			    .mav_read_csr(),
			    .mav_csr_write(),
			    .read_misa(csr_regfile$read_misa),
			    .read_mstatus(csr_regfile$read_mstatus),
			    .read_ustatus(),
			    .read_satp(csr_regfile$read_satp),
			    .csr_trap_actions(csr_regfile$csr_trap_actions),
			    .RDY_csr_trap_actions(),
			    .csr_ret_actions(csr_regfile$csr_ret_actions),
			    .RDY_csr_ret_actions(),
			    .read_csr_minstret(csr_regfile$read_csr_minstret),
			    .read_csr_mcycle(csr_regfile$read_csr_mcycle),
			    .read_csr_mtime(),
			    .access_permitted_1(csr_regfile$access_permitted_1),
			    .access_permitted_2(csr_regfile$access_permitted_2),
			    .csr_counter_read_fault(),
			    .csr_mip_read(),
			    .interrupt_pending(csr_regfile$interrupt_pending),
			    .wfi_resume(csr_regfile$wfi_resume),
			    .nmi_pending(csr_regfile$nmi_pending),
			    .RDY_debug());

  // submodule f_reset_reqs
  FIFO2 #(.width(32'd1), .guarded(32'd1)) f_reset_reqs(.RST(RST_N),
						       .CLK(CLK),
						       .D_IN(f_reset_reqs$D_IN),
						       .ENQ(f_reset_reqs$ENQ),
						       .DEQ(f_reset_reqs$DEQ),
						       .CLR(f_reset_reqs$CLR),
						       .D_OUT(f_reset_reqs$D_OUT),
						       .FULL_N(f_reset_reqs$FULL_N),
						       .EMPTY_N(f_reset_reqs$EMPTY_N));

  // submodule f_reset_rsps
  FIFO2 #(.width(32'd1), .guarded(32'd1)) f_reset_rsps(.RST(RST_N),
						       .CLK(CLK),
						       .D_IN(f_reset_rsps$D_IN),
						       .ENQ(f_reset_rsps$ENQ),
						       .DEQ(f_reset_rsps$DEQ),
						       .CLR(f_reset_rsps$CLR),
						       .D_OUT(f_reset_rsps$D_OUT),
						       .FULL_N(f_reset_rsps$FULL_N),
						       .EMPTY_N(f_reset_rsps$EMPTY_N));

  // submodule gpr_regfile
  mkGPR_RegFile gpr_regfile(.CLK(CLK),
			    .RST_N(RST_N),
			    .read_rs1_port2_rs1(gpr_regfile$read_rs1_port2_rs1),
			    .read_rs1_rs1(gpr_regfile$read_rs1_rs1),
			    .read_rs2_rs2(gpr_regfile$read_rs2_rs2),
			    .write_rd_rd(gpr_regfile$write_rd_rd),
			    .write_rd_rd_val(gpr_regfile$write_rd_rd_val),
			    .EN_server_reset_request_put(gpr_regfile$EN_server_reset_request_put),
			    .EN_server_reset_response_get(gpr_regfile$EN_server_reset_response_get),
			    .EN_write_rd(gpr_regfile$EN_write_rd),
			    .RDY_server_reset_request_put(gpr_regfile$RDY_server_reset_request_put),
			    .RDY_server_reset_response_get(gpr_regfile$RDY_server_reset_response_get),
			    .read_rs1(gpr_regfile$read_rs1),
			    .read_rs1_port2(),
			    .read_rs2(gpr_regfile$read_rs2));

  // submodule near_mem
  mkNear_Mem near_mem(.CLK(CLK),
		      .RST_N(RST_N),
		      .dmem_master_arready(near_mem$dmem_master_arready),
		      .dmem_master_awready(near_mem$dmem_master_awready),
		      .dmem_master_bid(near_mem$dmem_master_bid),
		      .dmem_master_bresp(near_mem$dmem_master_bresp),
		      .dmem_master_bvalid(near_mem$dmem_master_bvalid),
		      .dmem_master_rdata(near_mem$dmem_master_rdata),
		      .dmem_master_rid(near_mem$dmem_master_rid),
		      .dmem_master_rlast(near_mem$dmem_master_rlast),
		      .dmem_master_rresp(near_mem$dmem_master_rresp),
		      .dmem_master_rvalid(near_mem$dmem_master_rvalid),
		      .dmem_master_wready(near_mem$dmem_master_wready),
		      .dmem_req_addr(near_mem$dmem_req_addr),
		      .dmem_req_amo_funct7(near_mem$dmem_req_amo_funct7),
		      .dmem_req_f3(near_mem$dmem_req_f3),
		      .dmem_req_mstatus_MXR(near_mem$dmem_req_mstatus_MXR),
		      .dmem_req_op(near_mem$dmem_req_op),
		      .dmem_req_priv(near_mem$dmem_req_priv),
		      .dmem_req_satp(near_mem$dmem_req_satp),
		      .dmem_req_sstatus_SUM(near_mem$dmem_req_sstatus_SUM),
		      .dmem_req_store_value(near_mem$dmem_req_store_value),
		      .imem_master_arready(near_mem$imem_master_arready),
		      .imem_master_awready(near_mem$imem_master_awready),
		      .imem_master_bid(near_mem$imem_master_bid),
		      .imem_master_bresp(near_mem$imem_master_bresp),
		      .imem_master_bvalid(near_mem$imem_master_bvalid),
		      .imem_master_rdata(near_mem$imem_master_rdata),
		      .imem_master_rid(near_mem$imem_master_rid),
		      .imem_master_rlast(near_mem$imem_master_rlast),
		      .imem_master_rresp(near_mem$imem_master_rresp),
		      .imem_master_rvalid(near_mem$imem_master_rvalid),
		      .imem_master_wready(near_mem$imem_master_wready),
		      .imem_req_addr(near_mem$imem_req_addr),
		      .imem_req_f3(near_mem$imem_req_f3),
		      .imem_req_mstatus_MXR(near_mem$imem_req_mstatus_MXR),
		      .imem_req_priv(near_mem$imem_req_priv),
		      .imem_req_satp(near_mem$imem_req_satp),
		      .imem_req_sstatus_SUM(near_mem$imem_req_sstatus_SUM),
		      .server_fence_request_put(near_mem$server_fence_request_put),
		      .EN_server_reset_request_put(near_mem$EN_server_reset_request_put),
		      .EN_server_reset_response_get(near_mem$EN_server_reset_response_get),
		      .EN_imem_req(near_mem$EN_imem_req),
		      .EN_dmem_req(near_mem$EN_dmem_req),
		      .EN_server_fence_i_request_put(near_mem$EN_server_fence_i_request_put),
		      .EN_server_fence_i_response_get(near_mem$EN_server_fence_i_response_get),
		      .EN_server_fence_request_put(near_mem$EN_server_fence_request_put),
		      .EN_server_fence_response_get(near_mem$EN_server_fence_response_get),
		      .EN_sfence_vma(near_mem$EN_sfence_vma),
		      .RDY_server_reset_request_put(near_mem$RDY_server_reset_request_put),
		      .RDY_server_reset_response_get(near_mem$RDY_server_reset_response_get),
		      .imem_valid(near_mem$imem_valid),
		      .imem_is_i32_not_i16(near_mem$imem_is_i32_not_i16),
		      .imem_pc(near_mem$imem_pc),
		      .imem_instr(near_mem$imem_instr),
		      .imem_exc(near_mem$imem_exc),
		      .imem_exc_code(near_mem$imem_exc_code),
		      .imem_tval(),
		      .imem_master_awvalid(near_mem$imem_master_awvalid),
		      .imem_master_awid(near_mem$imem_master_awid),
		      .imem_master_awaddr(near_mem$imem_master_awaddr),
		      .imem_master_awlen(near_mem$imem_master_awlen),
		      .imem_master_awsize(near_mem$imem_master_awsize),
		      .imem_master_awburst(near_mem$imem_master_awburst),
		      .imem_master_awlock(near_mem$imem_master_awlock),
		      .imem_master_awcache(near_mem$imem_master_awcache),
		      .imem_master_awprot(near_mem$imem_master_awprot),
		      .imem_master_awqos(near_mem$imem_master_awqos),
		      .imem_master_awregion(near_mem$imem_master_awregion),
		      .imem_master_wvalid(near_mem$imem_master_wvalid),
		      .imem_master_wid(near_mem$imem_master_wid),
		      .imem_master_wdata(near_mem$imem_master_wdata),
		      .imem_master_wstrb(near_mem$imem_master_wstrb),
		      .imem_master_wlast(near_mem$imem_master_wlast),
		      .imem_master_bready(near_mem$imem_master_bready),
		      .imem_master_arvalid(near_mem$imem_master_arvalid),
		      .imem_master_arid(near_mem$imem_master_arid),
		      .imem_master_araddr(near_mem$imem_master_araddr),
		      .imem_master_arlen(near_mem$imem_master_arlen),
		      .imem_master_arsize(near_mem$imem_master_arsize),
		      .imem_master_arburst(near_mem$imem_master_arburst),
		      .imem_master_arlock(near_mem$imem_master_arlock),
		      .imem_master_arcache(near_mem$imem_master_arcache),
		      .imem_master_arprot(near_mem$imem_master_arprot),
		      .imem_master_arqos(near_mem$imem_master_arqos),
		      .imem_master_arregion(near_mem$imem_master_arregion),
		      .imem_master_rready(near_mem$imem_master_rready),
		      .dmem_valid(near_mem$dmem_valid),
		      .dmem_word64(near_mem$dmem_word64),
		      .dmem_st_amo_val(),
		      .dmem_exc(near_mem$dmem_exc),
		      .dmem_exc_code(near_mem$dmem_exc_code),
		      .dmem_master_awvalid(near_mem$dmem_master_awvalid),
		      .dmem_master_awid(near_mem$dmem_master_awid),
		      .dmem_master_awaddr(near_mem$dmem_master_awaddr),
		      .dmem_master_awlen(near_mem$dmem_master_awlen),
		      .dmem_master_awsize(near_mem$dmem_master_awsize),
		      .dmem_master_awburst(near_mem$dmem_master_awburst),
		      .dmem_master_awlock(near_mem$dmem_master_awlock),
		      .dmem_master_awcache(near_mem$dmem_master_awcache),
		      .dmem_master_awprot(near_mem$dmem_master_awprot),
		      .dmem_master_awqos(near_mem$dmem_master_awqos),
		      .dmem_master_awregion(near_mem$dmem_master_awregion),
		      .dmem_master_wvalid(near_mem$dmem_master_wvalid),
		      .dmem_master_wid(near_mem$dmem_master_wid),
		      .dmem_master_wdata(near_mem$dmem_master_wdata),
		      .dmem_master_wstrb(near_mem$dmem_master_wstrb),
		      .dmem_master_wlast(near_mem$dmem_master_wlast),
		      .dmem_master_bready(near_mem$dmem_master_bready),
		      .dmem_master_arvalid(near_mem$dmem_master_arvalid),
		      .dmem_master_arid(near_mem$dmem_master_arid),
		      .dmem_master_araddr(near_mem$dmem_master_araddr),
		      .dmem_master_arlen(near_mem$dmem_master_arlen),
		      .dmem_master_arsize(near_mem$dmem_master_arsize),
		      .dmem_master_arburst(near_mem$dmem_master_arburst),
		      .dmem_master_arlock(near_mem$dmem_master_arlock),
		      .dmem_master_arcache(near_mem$dmem_master_arcache),
		      .dmem_master_arprot(near_mem$dmem_master_arprot),
		      .dmem_master_arqos(near_mem$dmem_master_arqos),
		      .dmem_master_arregion(near_mem$dmem_master_arregion),
		      .dmem_master_rready(near_mem$dmem_master_rready),
		      .RDY_server_fence_i_request_put(near_mem$RDY_server_fence_i_request_put),
		      .RDY_server_fence_i_response_get(near_mem$RDY_server_fence_i_response_get),
		      .RDY_server_fence_request_put(near_mem$RDY_server_fence_request_put),
		      .RDY_server_fence_response_get(near_mem$RDY_server_fence_response_get),
		      .RDY_sfence_vma());

  // submodule soc_map
  mkSoC_Map soc_map(.CLK(CLK),
		    .RST_N(RST_N),
		    .m_is_IO_addr_addr(soc_map$m_is_IO_addr_addr),
		    .m_is_mem_addr_addr(soc_map$m_is_mem_addr_addr),
		    .m_is_near_mem_IO_addr_addr(soc_map$m_is_near_mem_IO_addr_addr),
		    .m_near_mem_io_addr_base(),
		    .m_near_mem_io_addr_size(),
		    .m_near_mem_io_addr_lim(),
		    .m_plic_addr_base(),
		    .m_plic_addr_size(),
		    .m_plic_addr_lim(),
		    .m_uart0_addr_base(),
		    .m_uart0_addr_size(),
		    .m_uart0_addr_lim(),
		    .m_boot_rom_addr_base(),
		    .m_boot_rom_addr_size(),
		    .m_boot_rom_addr_lim(),
		    .m_mem0_controller_addr_base(),
		    .m_mem0_controller_addr_size(),
		    .m_mem0_controller_addr_lim(),
		    .m_tcm_addr_base(),
		    .m_tcm_addr_size(),
		    .m_tcm_addr_lim(),
		    .m_is_mem_addr(),
		    .m_is_IO_addr(),
		    .m_is_near_mem_IO_addr(),
		    .m_pc_reset_value(soc_map$m_pc_reset_value),
		    .m_mtvec_reset_value(),
		    .m_nmivec_reset_value());

  // submodule stage1_f_reset_reqs
  FIFO20 #(.guarded(32'd1)) stage1_f_reset_reqs(.RST(RST_N),
						.CLK(CLK),
						.ENQ(stage1_f_reset_reqs$ENQ),
						.DEQ(stage1_f_reset_reqs$DEQ),
						.CLR(stage1_f_reset_reqs$CLR),
						.FULL_N(stage1_f_reset_reqs$FULL_N),
						.EMPTY_N(stage1_f_reset_reqs$EMPTY_N));

  // submodule stage1_f_reset_rsps
  FIFO20 #(.guarded(32'd1)) stage1_f_reset_rsps(.RST(RST_N),
						.CLK(CLK),
						.ENQ(stage1_f_reset_rsps$ENQ),
						.DEQ(stage1_f_reset_rsps$DEQ),
						.CLR(stage1_f_reset_rsps$CLR),
						.FULL_N(stage1_f_reset_rsps$FULL_N),
						.EMPTY_N(stage1_f_reset_rsps$EMPTY_N));

  // submodule stage2_f_reset_reqs
  FIFO20 #(.guarded(32'd1)) stage2_f_reset_reqs(.RST(RST_N),
						.CLK(CLK),
						.ENQ(stage2_f_reset_reqs$ENQ),
						.DEQ(stage2_f_reset_reqs$DEQ),
						.CLR(stage2_f_reset_reqs$CLR),
						.FULL_N(stage2_f_reset_reqs$FULL_N),
						.EMPTY_N(stage2_f_reset_reqs$EMPTY_N));

  // submodule stage2_f_reset_rsps
  FIFO20 #(.guarded(32'd1)) stage2_f_reset_rsps(.RST(RST_N),
						.CLK(CLK),
						.ENQ(stage2_f_reset_rsps$ENQ),
						.DEQ(stage2_f_reset_rsps$DEQ),
						.CLR(stage2_f_reset_rsps$CLR),
						.FULL_N(stage2_f_reset_rsps$FULL_N),
						.EMPTY_N(stage2_f_reset_rsps$EMPTY_N));

  // submodule stage2_mbox
  mkRISCV_MBox stage2_mbox(.CLK(CLK),
			   .RST_N(RST_N),
			   .req_f3(stage2_mbox$req_f3),
			   .req_is_OP_not_OP_32(stage2_mbox$req_is_OP_not_OP_32),
			   .req_v1(stage2_mbox$req_v1),
			   .req_v2(stage2_mbox$req_v2),
			   .set_verbosity_verbosity(stage2_mbox$set_verbosity_verbosity),
			   .EN_set_verbosity(stage2_mbox$EN_set_verbosity),
			   .EN_req_reset(stage2_mbox$EN_req_reset),
			   .EN_rsp_reset(stage2_mbox$EN_rsp_reset),
			   .EN_req(stage2_mbox$EN_req),
			   .RDY_set_verbosity(),
			   .RDY_req_reset(),
			   .RDY_rsp_reset(),
			   .valid(stage2_mbox$valid),
			   .word(stage2_mbox$word));

  // submodule stage3_f_reset_reqs
  FIFO20 #(.guarded(32'd1)) stage3_f_reset_reqs(.RST(RST_N),
						.CLK(CLK),
						.ENQ(stage3_f_reset_reqs$ENQ),
						.DEQ(stage3_f_reset_reqs$DEQ),
						.CLR(stage3_f_reset_reqs$CLR),
						.FULL_N(stage3_f_reset_reqs$FULL_N),
						.EMPTY_N(stage3_f_reset_reqs$EMPTY_N));

  // submodule stage3_f_reset_rsps
  FIFO20 #(.guarded(32'd1)) stage3_f_reset_rsps(.RST(RST_N),
						.CLK(CLK),
						.ENQ(stage3_f_reset_rsps$ENQ),
						.DEQ(stage3_f_reset_rsps$DEQ),
						.CLR(stage3_f_reset_rsps$CLR),
						.FULL_N(stage3_f_reset_rsps$FULL_N),
						.EMPTY_N(stage3_f_reset_rsps$EMPTY_N));

  // rule RL_rl_show_pipe
  assign CAN_FIRE_RL_rl_show_pipe =
	     NOT_IF_csr_regfile_read_csr_minstret__5_ULT_cf_ETC___d41 &&
	     rg_state != 4'd0 &&
	     rg_state != 4'd1 &&
	     rg_state != 4'd10 ;
  assign WILL_FIRE_RL_rl_show_pipe = CAN_FIRE_RL_rl_show_pipe ;

  // rule RL_rl_stage2_nonpipe
  assign CAN_FIRE_RL_rl_stage2_nonpipe =
	     rg_state == 4'd3 && !stage3_rg_full &&
	     IF_stage2_rg_full_7_THEN_IF_stage2_rg_stage2_8_ETC___d118 ==
	     2'd3 &&
	     (!stage1_rg_full ||
	      near_mem_imem_valid_AND_near_mem_imem_pc_EQ_im_ETC___d484) ;
  assign WILL_FIRE_RL_rl_stage2_nonpipe = CAN_FIRE_RL_rl_stage2_nonpipe ;

  // rule RL_rl_stage1_CSRR_W
  assign CAN_FIRE_RL_rl_stage1_CSRR_W = MUX_rg_state$write_1__SEL_2 ;
  assign WILL_FIRE_RL_rl_stage1_CSRR_W = MUX_rg_state$write_1__SEL_2 ;

  // rule RL_rl_stage1_CSRR_S_or_C
  assign CAN_FIRE_RL_rl_stage1_CSRR_S_or_C = MUX_rg_state$write_1__SEL_3 ;
  assign WILL_FIRE_RL_rl_stage1_CSRR_S_or_C = MUX_rg_state$write_1__SEL_3 ;

  // rule RL_rl_stage1_restart_after_csrrx
  assign CAN_FIRE_RL_rl_stage1_restart_after_csrrx =
	     (!near_mem_imem_pc_BITS_31_TO_2_EQ_imem_rg_pc_BI_ETC___d8 ||
	      imem_rg_pc[1:0] == 2'b0 ||
	      near_mem$imem_instr[17:16] != 2'b11) &&
	     rg_state == 4'd6 ;
  assign WILL_FIRE_RL_rl_stage1_restart_after_csrrx =
	     CAN_FIRE_RL_rl_stage1_restart_after_csrrx ;

  // rule RL_rl_stage1_xRET
  assign CAN_FIRE_RL_rl_stage1_xRET =
	     rg_state_2_EQ_3_096_AND_NOT_csr_regfile_interr_ETC___d1185 &&
	     stage1_rg_full &&
	     near_mem_imem_valid_AND_near_mem_imem_pc_EQ_im_ETC___d636 &&
	     (IF_NOT_stage1_rg_full_94_95_OR_NOT_near_mem_im_ETC___d746 ==
	      4'd7 ||
	      IF_NOT_stage1_rg_full_94_95_OR_NOT_near_mem_im_ETC___d746 ==
	      4'd8 ||
	      IF_NOT_stage1_rg_full_94_95_OR_NOT_near_mem_im_ETC___d746 ==
	      4'd9) ;
  assign WILL_FIRE_RL_rl_stage1_xRET = CAN_FIRE_RL_rl_stage1_xRET ;

  // rule RL_rl_stage1_FENCE_I
  assign CAN_FIRE_RL_rl_stage1_FENCE_I = MUX_rg_state$write_1__SEL_8 ;
  assign WILL_FIRE_RL_rl_stage1_FENCE_I = MUX_rg_state$write_1__SEL_8 ;

  // rule RL_rl_finish_FENCE_I
  assign CAN_FIRE_RL_rl_finish_FENCE_I =
	     (!near_mem_imem_pc_BITS_31_TO_2_EQ_imem_rg_pc_BI_ETC___d8 ||
	      imem_rg_pc[1:0] == 2'b0 ||
	      near_mem$imem_instr[17:16] != 2'b11) &&
	     near_mem$RDY_server_fence_i_response_get &&
	     rg_state == 4'd7 ;
  assign WILL_FIRE_RL_rl_finish_FENCE_I = CAN_FIRE_RL_rl_finish_FENCE_I ;

  // rule RL_rl_stage1_FENCE
  assign CAN_FIRE_RL_rl_stage1_FENCE = MUX_rg_state$write_1__SEL_9 ;
  assign WILL_FIRE_RL_rl_stage1_FENCE = MUX_rg_state$write_1__SEL_9 ;

  // rule RL_rl_finish_FENCE
  assign CAN_FIRE_RL_rl_finish_FENCE =
	     (!near_mem_imem_pc_BITS_31_TO_2_EQ_imem_rg_pc_BI_ETC___d8 ||
	      imem_rg_pc[1:0] == 2'b0 ||
	      near_mem$imem_instr[17:16] != 2'b11) &&
	     near_mem$RDY_server_fence_response_get &&
	     rg_state == 4'd8 ;
  assign WILL_FIRE_RL_rl_finish_FENCE = CAN_FIRE_RL_rl_finish_FENCE ;

  // rule RL_rl_stage1_SFENCE_VMA
  assign CAN_FIRE_RL_rl_stage1_SFENCE_VMA = MUX_rg_state$write_1__SEL_10 ;
  assign WILL_FIRE_RL_rl_stage1_SFENCE_VMA = MUX_rg_state$write_1__SEL_10 ;

  // rule RL_rl_finish_SFENCE_VMA
  assign CAN_FIRE_RL_rl_finish_SFENCE_VMA =
	     (!near_mem_imem_pc_BITS_31_TO_2_EQ_imem_rg_pc_BI_ETC___d8 ||
	      imem_rg_pc[1:0] == 2'b0 ||
	      near_mem$imem_instr[17:16] != 2'b11) &&
	     rg_state == 4'd9 ;
  assign WILL_FIRE_RL_rl_finish_SFENCE_VMA =
	     CAN_FIRE_RL_rl_finish_SFENCE_VMA ;

  // rule RL_rl_stage1_WFI
  assign CAN_FIRE_RL_rl_stage1_WFI = MUX_rg_state$write_1__SEL_11 ;
  assign WILL_FIRE_RL_rl_stage1_WFI = MUX_rg_state$write_1__SEL_11 ;

  // rule RL_rl_WFI_resume
  assign CAN_FIRE_RL_rl_WFI_resume =
	     (!near_mem_imem_pc_BITS_31_TO_2_EQ_imem_rg_pc_BI_ETC___d8 ||
	      imem_rg_pc[1:0] == 2'b0 ||
	      near_mem$imem_instr[17:16] != 2'b11) &&
	     rg_state == 4'd10 &&
	     csr_regfile$wfi_resume ;
  assign WILL_FIRE_RL_rl_WFI_resume = CAN_FIRE_RL_rl_WFI_resume ;

  // rule RL_rl_reset_from_WFI
  assign CAN_FIRE_RL_rl_reset_from_WFI =
	     rg_state == 4'd10 && f_reset_reqs$EMPTY_N ;
  assign WILL_FIRE_RL_rl_reset_from_WFI = MUX_rg_state$write_1__SEL_4 ;

  // rule RL_rl_stage1_trap
  assign CAN_FIRE_RL_rl_stage1_trap =
	     rg_state == 4'd4 ||
	     rg_state_2_EQ_3_096_AND_NOT_csr_regfile_interr_ETC___d1185 &&
	     stage1_rg_full &&
	     near_mem_imem_valid_AND_near_mem_imem_pc_EQ_im_ETC___d636 &&
	     IF_NOT_stage1_rg_full_94_95_OR_NOT_near_mem_im_ETC___d746 ==
	     4'd11 ;
  assign WILL_FIRE_RL_rl_stage1_trap = CAN_FIRE_RL_rl_stage1_trap ;

  // rule RL_rl_trap_fetch
  assign CAN_FIRE_RL_rl_trap_fetch =
	     (!near_mem_imem_pc_BITS_31_TO_2_EQ_imem_rg_pc_BI_ETC___d8 ||
	      imem_rg_pc[1:0] == 2'b0 ||
	      near_mem$imem_instr[17:16] != 2'b11) &&
	     rg_state == 4'd5 ;
  assign WILL_FIRE_RL_rl_trap_fetch = CAN_FIRE_RL_rl_trap_fetch ;

  // rule RL_rl_stage1_interrupt
  assign CAN_FIRE_RL_rl_stage1_interrupt =
	     (csr_regfile$interrupt_pending[4] || csr_regfile$nmi_pending) &&
	     rg_state == 4'd3 &&
	     stage1_rg_full &&
	     near_mem_imem_valid_AND_near_mem_imem_pc_EQ_im_ETC___d484 &&
	     IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d1080 &&
	     IF_stage2_rg_full_7_THEN_IF_stage2_rg_stage2_8_ETC___d118 ==
	     2'd0 &&
	     !stage3_rg_full ;
  assign WILL_FIRE_RL_rl_stage1_interrupt = CAN_FIRE_RL_rl_stage1_interrupt ;

  // rule RL_imem_rl_assert_fail
  assign CAN_FIRE_RL_imem_rl_assert_fail = !near_mem$imem_is_i32_not_i16 ;
  assign WILL_FIRE_RL_imem_rl_assert_fail = CAN_FIRE_RL_imem_rl_assert_fail ;

  // rule RL_rl_reset_complete
  assign CAN_FIRE_RL_rl_reset_complete =
	     gpr_regfile$RDY_server_reset_response_get &&
	     near_mem$RDY_server_reset_response_get &&
	     csr_regfile$RDY_server_reset_response_get &&
	     stage1_f_reset_rsps$EMPTY_N &&
	     stage2_f_reset_rsps_i_notEmpty__052_AND_stage3_ETC___d1061 &&
	     rg_state == 4'd1 ;
  assign WILL_FIRE_RL_rl_reset_complete = MUX_rg_state$write_1__SEL_1 ;

  // rule RL_rl_pipe
  assign CAN_FIRE_RL_rl_pipe =
	     (csr_regfile_interrupt_pending_rg_cur_priv_3_07_ETC___d1094 ||
	      !near_mem_imem_pc_BITS_31_TO_2_EQ_imem_rg_pc_BI_ETC___d8 ||
	      imem_rg_pc[1:0] == 2'b0 ||
	      near_mem$imem_instr[17:16] != 2'b11) &&
	     rg_state_2_EQ_3_096_AND_stage3_rg_full_8_OR_NO_ETC___d1115 ;
  assign WILL_FIRE_RL_rl_pipe =
	     CAN_FIRE_RL_rl_pipe && !WILL_FIRE_RL_imem_rl_fetch_next_32b ;

  // rule RL_rl_reset_start
  assign CAN_FIRE_RL_rl_reset_start =
	     gpr_regfile_RDY_server_reset_request_put__031__ETC___d1043 &&
	     rg_state == 4'd0 ;
  assign WILL_FIRE_RL_rl_reset_start = CAN_FIRE_RL_rl_reset_start ;

  // rule RL_imem_rl_fetch_next_32b
  assign CAN_FIRE_RL_imem_rl_fetch_next_32b =
	     near_mem$imem_valid &&
	     near_mem_imem_pc_BITS_31_TO_2_EQ_imem_rg_pc_BI_ETC___d8 &&
	     imem_rg_pc[1:0] != 2'b0 &&
	     near_mem$imem_instr[17:16] == 2'b11 ;
  assign WILL_FIRE_RL_imem_rl_fetch_next_32b =
	     CAN_FIRE_RL_imem_rl_fetch_next_32b ;

  // rule RL_stage3_rl_reset
  assign CAN_FIRE_RL_stage3_rl_reset =
	     stage3_f_reset_reqs$EMPTY_N && stage3_f_reset_rsps$FULL_N ;
  assign WILL_FIRE_RL_stage3_rl_reset = CAN_FIRE_RL_stage3_rl_reset ;

  // rule RL_stage2_rl_reset_end
  assign CAN_FIRE_RL_stage2_rl_reset_end =
	     stage2_f_reset_rsps$FULL_N && stage2_rg_resetting ;
  assign WILL_FIRE_RL_stage2_rl_reset_end = CAN_FIRE_RL_stage2_rl_reset_end ;

  // rule RL_stage2_rl_reset_begin
  assign CAN_FIRE_RL_stage2_rl_reset_begin = stage2_f_reset_reqs$EMPTY_N ;
  assign WILL_FIRE_RL_stage2_rl_reset_begin = stage2_f_reset_reqs$EMPTY_N ;

  // rule RL_stage1_rl_reset
  assign CAN_FIRE_RL_stage1_rl_reset =
	     stage1_f_reset_reqs$EMPTY_N && stage1_f_reset_rsps$FULL_N ;
  assign WILL_FIRE_RL_stage1_rl_reset = CAN_FIRE_RL_stage1_rl_reset ;

  // inputs to muxes for submodule ports
  assign MUX_csr_regfile$mav_csr_write_1__SEL_1 =
	     WILL_FIRE_RL_rl_stage1_CSRR_W && csr_regfile$access_permitted_1 ;
  assign MUX_gpr_regfile$write_rd_1__SEL_1 =
	     WILL_FIRE_RL_rl_pipe && stage3_rg_full && stage3_rg_stage3[37] ;
  assign MUX_gpr_regfile$write_rd_1__SEL_3 =
	     WILL_FIRE_RL_rl_stage1_CSRR_S_or_C &&
	     csr_regfile$access_permitted_2 ;
  assign MUX_imem_rg_f3$write_1__SEL_1 =
	     WILL_FIRE_RL_rl_reset_complete && rg_run_on_reset ;
  assign MUX_imem_rg_f3$write_1__SEL_2 =
	     WILL_FIRE_RL_rl_pipe &&
	     NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d1112 &&
	     NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d1154 ;
  assign MUX_imem_rg_mstatus_MXR$write_1__SEL_4 =
	     WILL_FIRE_RL_rl_WFI_resume ||
	     WILL_FIRE_RL_rl_finish_SFENCE_VMA ||
	     WILL_FIRE_RL_rl_finish_FENCE ||
	     WILL_FIRE_RL_rl_finish_FENCE_I ||
	     WILL_FIRE_RL_rl_stage1_restart_after_csrrx ;
  assign MUX_imem_rg_pc$write_1__SEL_4 =
	     WILL_FIRE_RL_rl_trap_fetch || WILL_FIRE_RL_rl_WFI_resume ||
	     WILL_FIRE_RL_rl_finish_SFENCE_VMA ||
	     WILL_FIRE_RL_rl_finish_FENCE ||
	     WILL_FIRE_RL_rl_finish_FENCE_I ;
  assign MUX_near_mem$imem_req_1__SEL_6 =
	     WILL_FIRE_RL_rl_WFI_resume ||
	     WILL_FIRE_RL_rl_finish_SFENCE_VMA ||
	     WILL_FIRE_RL_rl_finish_FENCE ||
	     WILL_FIRE_RL_rl_finish_FENCE_I ;
  assign MUX_rg_cur_priv$write_1__SEL_1 =
	     WILL_FIRE_RL_rl_stage1_interrupt ||
	     WILL_FIRE_RL_rl_stage1_trap ||
	     WILL_FIRE_RL_rl_stage2_nonpipe ;
  assign MUX_rg_mstatus_MXR$write_1__SEL_1 =
	     WILL_FIRE_RL_rl_stage1_trap || WILL_FIRE_RL_rl_stage1_xRET ||
	     WILL_FIRE_RL_rl_stage2_nonpipe ;
  assign MUX_rg_next_pc$write_1__SEL_1 =
	     WILL_FIRE_RL_rl_stage1_WFI || WILL_FIRE_RL_rl_stage1_FENCE ||
	     WILL_FIRE_RL_rl_stage1_FENCE_I ||
	     WILL_FIRE_RL_rl_stage1_SFENCE_VMA ;
  assign MUX_rg_state$write_1__SEL_1 =
	     CAN_FIRE_RL_rl_reset_complete &&
	     !WILL_FIRE_RL_imem_rl_fetch_next_32b ;
  assign MUX_rg_state$write_1__SEL_2 =
	     rg_state_2_EQ_3_096_AND_NOT_csr_regfile_interr_ETC___d1185 &&
	     stage1_rg_full &&
	     near_mem_imem_valid_AND_near_mem_imem_pc_EQ_im_ETC___d636 &&
	     IF_NOT_stage1_rg_full_94_95_OR_NOT_near_mem_im_ETC___d746 ==
	     4'd2 ;
  assign MUX_rg_state$write_1__SEL_3 =
	     rg_state_2_EQ_3_096_AND_NOT_csr_regfile_interr_ETC___d1185 &&
	     stage1_rg_full &&
	     near_mem_imem_valid_AND_near_mem_imem_pc_EQ_im_ETC___d636 &&
	     IF_NOT_stage1_rg_full_94_95_OR_NOT_near_mem_im_ETC___d746 ==
	     4'd3 ;
  assign MUX_rg_state$write_1__SEL_4 =
	     CAN_FIRE_RL_rl_reset_from_WFI && !WILL_FIRE_RL_rl_WFI_resume ;
  assign MUX_rg_state$write_1__SEL_6 =
	     WILL_FIRE_RL_rl_trap_fetch || WILL_FIRE_RL_rl_WFI_resume ||
	     WILL_FIRE_RL_rl_finish_SFENCE_VMA ||
	     WILL_FIRE_RL_rl_finish_FENCE ||
	     WILL_FIRE_RL_rl_finish_FENCE_I ||
	     WILL_FIRE_RL_rl_stage1_restart_after_csrrx ;
  assign MUX_rg_state$write_1__SEL_7 =
	     WILL_FIRE_RL_rl_stage1_interrupt ||
	     WILL_FIRE_RL_rl_stage1_trap ||
	     WILL_FIRE_RL_rl_stage1_xRET ||
	     WILL_FIRE_RL_rl_stage2_nonpipe ;
  assign MUX_rg_state$write_1__SEL_8 =
	     near_mem$RDY_server_fence_i_request_put &&
	     rg_state_2_EQ_3_096_AND_NOT_csr_regfile_interr_ETC___d1185 &&
	     stage1_rg_full &&
	     near_mem_imem_valid_AND_near_mem_imem_pc_EQ_im_ETC___d636 &&
	     IF_NOT_stage1_rg_full_94_95_OR_NOT_near_mem_im_ETC___d746 ==
	     4'd5 ;
  assign MUX_rg_state$write_1__SEL_9 =
	     near_mem$RDY_server_fence_request_put &&
	     rg_state_2_EQ_3_096_AND_NOT_csr_regfile_interr_ETC___d1185 &&
	     stage1_rg_full &&
	     near_mem_imem_valid_AND_near_mem_imem_pc_EQ_im_ETC___d636 &&
	     IF_NOT_stage1_rg_full_94_95_OR_NOT_near_mem_im_ETC___d746 ==
	     4'd4 ;
  assign MUX_rg_state$write_1__SEL_10 =
	     rg_state_2_EQ_3_096_AND_NOT_csr_regfile_interr_ETC___d1185 &&
	     stage1_rg_full &&
	     near_mem_imem_valid_AND_near_mem_imem_pc_EQ_im_ETC___d636 &&
	     IF_NOT_stage1_rg_full_94_95_OR_NOT_near_mem_im_ETC___d746 ==
	     4'd6 ;
  assign MUX_rg_state$write_1__SEL_11 =
	     rg_state_2_EQ_3_096_AND_NOT_csr_regfile_interr_ETC___d1185 &&
	     stage1_rg_full &&
	     near_mem_imem_valid_AND_near_mem_imem_pc_EQ_im_ETC___d636 &&
	     IF_NOT_stage1_rg_full_94_95_OR_NOT_near_mem_im_ETC___d746 ==
	     4'd10 ;
  assign MUX_csr_regfile$csr_trap_actions_5__VAL_1 =
	     (csr_regfile$interrupt_pending[4] && !csr_regfile$nmi_pending) ?
	       csr_regfile$interrupt_pending[3:0] :
	       4'd0 ;
  always@(x_out_data_to_stage2_instr__h11612 or
	  csr_regfile$read_csr or
	  y__h18022 or
	  IF_csr_regfile_read_csr_IF_NOT_stage1_rg_full__ETC___d1220)
  begin
    case (x_out_data_to_stage2_instr__h11612[14:12])
      3'b010, 3'b110:
	  MUX_csr_regfile$mav_csr_write_2__VAL_2 =
	      IF_csr_regfile_read_csr_IF_NOT_stage1_rg_full__ETC___d1220;
      default: MUX_csr_regfile$mav_csr_write_2__VAL_2 =
		   csr_regfile$read_csr[31:0] & y__h18022;
    endcase
  end
  assign MUX_near_mem$imem_req_2__VAL_1 =
	     { soc_map$m_pc_reset_value[31:2], 2'b0 } ;
  assign MUX_near_mem$imem_req_2__VAL_2 =
	     { x_out_next_pc__h11584[31:2], 2'b0 } ;
  assign MUX_near_mem$imem_req_2__VAL_5 = { rg_next_pc[31:2], 2'b0 } ;
  assign MUX_rg_state$write_1__VAL_1 = rg_run_on_reset ? 4'd3 : 4'd2 ;
  assign MUX_rg_state$write_1__VAL_2 =
	     csr_regfile$access_permitted_1 ? 4'd6 : 4'd4 ;
  assign MUX_rg_state$write_1__VAL_3 =
	     csr_regfile$access_permitted_2 ? 4'd6 : 4'd4 ;
  assign MUX_stage1_rg_full$write_1__VAL_2 =
	     NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d1168 ||
	     (csr_regfile_interrupt_pending_rg_cur_priv_3_07_ETC___d1088 ||
	      NOT_near_mem_imem_valid_96_OR_NOT_near_mem_ime_ETC___d1109) &&
	     stage1_rg_full ;
  assign MUX_stage2_rg_full$write_1__VAL_2 =
	     NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d1163 ||
	     IF_stage2_rg_full_7_THEN_IF_stage2_rg_stage2_8_ETC___d118 !=
	     2'd2 &&
	     IF_stage2_rg_full_7_THEN_IF_stage2_rg_stage2_8_ETC___d118 !=
	     2'd0 ;

  // register cfg_logdelay
  assign cfg_logdelay$D_IN = set_verbosity_logdelay ;
  assign cfg_logdelay$EN = EN_set_verbosity ;

  // register cfg_verbosity
  assign cfg_verbosity$D_IN = set_verbosity_verbosity ;
  assign cfg_verbosity$EN = EN_set_verbosity ;

  // register imem_rg_f3
  assign imem_rg_f3$D_IN = 3'b010 ;
  assign imem_rg_f3$EN =
	     WILL_FIRE_RL_rl_reset_complete && rg_run_on_reset ||
	     WILL_FIRE_RL_rl_pipe &&
	     NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d1112 &&
	     NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d1154 ||
	     WILL_FIRE_RL_rl_trap_fetch ||
	     WILL_FIRE_RL_rl_WFI_resume ||
	     WILL_FIRE_RL_rl_finish_SFENCE_VMA ||
	     WILL_FIRE_RL_rl_finish_FENCE ||
	     WILL_FIRE_RL_rl_finish_FENCE_I ||
	     WILL_FIRE_RL_rl_stage1_restart_after_csrrx ;

  // register imem_rg_instr_15_0
  assign imem_rg_instr_15_0$D_IN = near_mem$imem_instr[31:16] ;
  assign imem_rg_instr_15_0$EN = CAN_FIRE_RL_imem_rl_fetch_next_32b ;

  // register imem_rg_mstatus_MXR
  assign imem_rg_mstatus_MXR$D_IN =
	     (MUX_imem_rg_f3$write_1__SEL_1 ||
	      MUX_imem_rg_f3$write_1__SEL_2 ||
	      MUX_imem_rg_mstatus_MXR$write_1__SEL_4) ?
	       csr_regfile$read_mstatus[19] :
	       rg_mstatus_MXR ;
  assign imem_rg_mstatus_MXR$EN =
	     WILL_FIRE_RL_rl_reset_complete && rg_run_on_reset ||
	     WILL_FIRE_RL_rl_pipe &&
	     NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d1112 &&
	     NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d1154 ||
	     WILL_FIRE_RL_rl_trap_fetch ||
	     WILL_FIRE_RL_rl_WFI_resume ||
	     WILL_FIRE_RL_rl_finish_SFENCE_VMA ||
	     WILL_FIRE_RL_rl_finish_FENCE ||
	     WILL_FIRE_RL_rl_finish_FENCE_I ||
	     WILL_FIRE_RL_rl_stage1_restart_after_csrrx ;

  // register imem_rg_pc
  always@(MUX_imem_rg_f3$write_1__SEL_1 or
	  soc_map$m_pc_reset_value or
	  MUX_imem_rg_f3$write_1__SEL_2 or
	  x_out_next_pc__h11584 or
	  WILL_FIRE_RL_rl_stage1_restart_after_csrrx or
	  MUX_imem_rg_pc$write_1__SEL_4 or rg_next_pc)
  begin
    case (1'b1) // synopsys parallel_case
      MUX_imem_rg_f3$write_1__SEL_1:
	  imem_rg_pc$D_IN = soc_map$m_pc_reset_value[31:0];
      MUX_imem_rg_f3$write_1__SEL_2: imem_rg_pc$D_IN = x_out_next_pc__h11584;
      WILL_FIRE_RL_rl_stage1_restart_after_csrrx:
	  imem_rg_pc$D_IN = x_out_next_pc__h11584;
      MUX_imem_rg_pc$write_1__SEL_4: imem_rg_pc$D_IN = rg_next_pc;
      default: imem_rg_pc$D_IN = 32'hAAAAAAAA /* unspecified value */ ;
    endcase
  end
  assign imem_rg_pc$EN =
	     WILL_FIRE_RL_rl_reset_complete && rg_run_on_reset ||
	     WILL_FIRE_RL_rl_pipe &&
	     NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d1112 &&
	     NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d1154 ||
	     WILL_FIRE_RL_rl_stage1_restart_after_csrrx ||
	     WILL_FIRE_RL_rl_trap_fetch ||
	     WILL_FIRE_RL_rl_WFI_resume ||
	     WILL_FIRE_RL_rl_finish_SFENCE_VMA ||
	     WILL_FIRE_RL_rl_finish_FENCE ||
	     WILL_FIRE_RL_rl_finish_FENCE_I ;

  // register imem_rg_priv
  assign imem_rg_priv$D_IN = rg_cur_priv ;
  assign imem_rg_priv$EN =
	     WILL_FIRE_RL_rl_reset_complete && rg_run_on_reset ||
	     WILL_FIRE_RL_rl_pipe &&
	     NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d1112 &&
	     NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d1154 ||
	     WILL_FIRE_RL_rl_trap_fetch ||
	     WILL_FIRE_RL_rl_WFI_resume ||
	     WILL_FIRE_RL_rl_finish_SFENCE_VMA ||
	     WILL_FIRE_RL_rl_finish_FENCE ||
	     WILL_FIRE_RL_rl_finish_FENCE_I ||
	     WILL_FIRE_RL_rl_stage1_restart_after_csrrx ;

  // register imem_rg_satp
  assign imem_rg_satp$D_IN = csr_regfile$read_satp ;
  assign imem_rg_satp$EN =
	     WILL_FIRE_RL_rl_reset_complete && rg_run_on_reset ||
	     WILL_FIRE_RL_rl_pipe &&
	     NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d1112 &&
	     NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d1154 ||
	     WILL_FIRE_RL_rl_trap_fetch ||
	     WILL_FIRE_RL_rl_WFI_resume ||
	     WILL_FIRE_RL_rl_finish_SFENCE_VMA ||
	     WILL_FIRE_RL_rl_finish_FENCE ||
	     WILL_FIRE_RL_rl_finish_FENCE_I ||
	     WILL_FIRE_RL_rl_stage1_restart_after_csrrx ;

  // register imem_rg_sstatus_SUM
  assign imem_rg_sstatus_SUM$D_IN =
	     WILL_FIRE_RL_rl_trap_fetch && rg_sstatus_SUM ;
  assign imem_rg_sstatus_SUM$EN =
	     WILL_FIRE_RL_rl_reset_complete && rg_run_on_reset ||
	     WILL_FIRE_RL_rl_pipe &&
	     NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d1112 &&
	     NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d1154 ||
	     WILL_FIRE_RL_rl_trap_fetch ||
	     WILL_FIRE_RL_rl_WFI_resume ||
	     WILL_FIRE_RL_rl_finish_SFENCE_VMA ||
	     WILL_FIRE_RL_rl_finish_FENCE ||
	     WILL_FIRE_RL_rl_finish_FENCE_I ||
	     WILL_FIRE_RL_rl_stage1_restart_after_csrrx ;

  // register imem_rg_tval
  always@(MUX_imem_rg_f3$write_1__SEL_1 or
	  soc_map$m_pc_reset_value or
	  MUX_imem_rg_f3$write_1__SEL_2 or
	  x_out_next_pc__h11584 or
	  WILL_FIRE_RL_rl_stage1_restart_after_csrrx or
	  MUX_imem_rg_pc$write_1__SEL_4 or
	  rg_next_pc or
	  WILL_FIRE_RL_imem_rl_fetch_next_32b or next_pc___1__h13393)
  begin
    case (1'b1) // synopsys parallel_case
      MUX_imem_rg_f3$write_1__SEL_1:
	  imem_rg_tval$D_IN = soc_map$m_pc_reset_value[31:0];
      MUX_imem_rg_f3$write_1__SEL_2:
	  imem_rg_tval$D_IN = x_out_next_pc__h11584;
      WILL_FIRE_RL_rl_stage1_restart_after_csrrx:
	  imem_rg_tval$D_IN = x_out_next_pc__h11584;
      MUX_imem_rg_pc$write_1__SEL_4: imem_rg_tval$D_IN = rg_next_pc;
      WILL_FIRE_RL_imem_rl_fetch_next_32b:
	  imem_rg_tval$D_IN = next_pc___1__h13393;
      default: imem_rg_tval$D_IN = 32'hAAAAAAAA /* unspecified value */ ;
    endcase
  end
  assign imem_rg_tval$EN =
	     WILL_FIRE_RL_rl_reset_complete && rg_run_on_reset ||
	     WILL_FIRE_RL_rl_pipe &&
	     NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d1112 &&
	     NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d1154 ||
	     WILL_FIRE_RL_rl_stage1_restart_after_csrrx ||
	     WILL_FIRE_RL_rl_trap_fetch ||
	     WILL_FIRE_RL_rl_WFI_resume ||
	     WILL_FIRE_RL_rl_finish_SFENCE_VMA ||
	     WILL_FIRE_RL_rl_finish_FENCE ||
	     WILL_FIRE_RL_rl_finish_FENCE_I ||
	     WILL_FIRE_RL_imem_rl_fetch_next_32b ;

  // register rg_cur_priv
  always@(MUX_rg_cur_priv$write_1__SEL_1 or
	  csr_regfile$csr_trap_actions or
	  WILL_FIRE_RL_rl_stage1_xRET or
	  csr_regfile$csr_ret_actions or WILL_FIRE_RL_rl_reset_start)
  begin
    case (1'b1) // synopsys parallel_case
      MUX_rg_cur_priv$write_1__SEL_1:
	  rg_cur_priv$D_IN = csr_regfile$csr_trap_actions[1:0];
      WILL_FIRE_RL_rl_stage1_xRET:
	  rg_cur_priv$D_IN = csr_regfile$csr_ret_actions[33:32];
      WILL_FIRE_RL_rl_reset_start: rg_cur_priv$D_IN = 2'b11;
      default: rg_cur_priv$D_IN = 2'b10 /* unspecified value */ ;
    endcase
  end
  assign rg_cur_priv$EN =
	     WILL_FIRE_RL_rl_stage1_interrupt ||
	     WILL_FIRE_RL_rl_stage1_trap ||
	     WILL_FIRE_RL_rl_stage2_nonpipe ||
	     WILL_FIRE_RL_rl_stage1_xRET ||
	     WILL_FIRE_RL_rl_reset_start ;

  // register rg_mstatus_MXR
  assign rg_mstatus_MXR$D_IN =
	     MUX_rg_mstatus_MXR$write_1__SEL_1 ?
	       csr_regfile$read_mstatus[19] :
	       csr_regfile$csr_trap_actions[53] ;
  assign rg_mstatus_MXR$EN =
	     WILL_FIRE_RL_rl_stage1_trap || WILL_FIRE_RL_rl_stage1_xRET ||
	     WILL_FIRE_RL_rl_stage2_nonpipe ||
	     WILL_FIRE_RL_rl_stage1_interrupt ;

  // register rg_next_pc
  always@(MUX_rg_next_pc$write_1__SEL_1 or
	  x_out_next_pc__h11584 or
	  MUX_rg_cur_priv$write_1__SEL_1 or
	  csr_regfile$csr_trap_actions or
	  WILL_FIRE_RL_rl_stage1_xRET or csr_regfile$csr_ret_actions)
  begin
    case (1'b1) // synopsys parallel_case
      MUX_rg_next_pc$write_1__SEL_1: rg_next_pc$D_IN = x_out_next_pc__h11584;
      MUX_rg_cur_priv$write_1__SEL_1:
	  rg_next_pc$D_IN = csr_regfile$csr_trap_actions[97:66];
      WILL_FIRE_RL_rl_stage1_xRET:
	  rg_next_pc$D_IN = csr_regfile$csr_ret_actions[65:34];
      default: rg_next_pc$D_IN = 32'hAAAAAAAA /* unspecified value */ ;
    endcase
  end
  assign rg_next_pc$EN =
	     WILL_FIRE_RL_rl_stage1_WFI || WILL_FIRE_RL_rl_stage1_FENCE ||
	     WILL_FIRE_RL_rl_stage1_FENCE_I ||
	     WILL_FIRE_RL_rl_stage1_SFENCE_VMA ||
	     WILL_FIRE_RL_rl_stage1_interrupt ||
	     WILL_FIRE_RL_rl_stage1_trap ||
	     WILL_FIRE_RL_rl_stage2_nonpipe ||
	     WILL_FIRE_RL_rl_stage1_xRET ;

  // register rg_run_on_reset
  assign rg_run_on_reset$D_IN = f_reset_reqs$D_OUT ;
  assign rg_run_on_reset$EN = CAN_FIRE_RL_rl_reset_start ;

  // register rg_sstatus_SUM
  assign rg_sstatus_SUM$D_IN =
	     WILL_FIRE_RL_rl_stage1_interrupt &&
	     csr_regfile$csr_trap_actions[52] ;
  assign rg_sstatus_SUM$EN = MUX_rg_state$write_1__SEL_7 ;

  // register rg_start_CPI_cycles
  assign rg_start_CPI_cycles$D_IN = csr_regfile$read_csr_mcycle ;
  assign rg_start_CPI_cycles$EN = MUX_imem_rg_f3$write_1__SEL_1 ;

  // register rg_start_CPI_instrs
  assign rg_start_CPI_instrs$D_IN = csr_regfile$read_csr_minstret ;
  assign rg_start_CPI_instrs$EN = MUX_imem_rg_f3$write_1__SEL_1 ;

  // register rg_state
  always@(WILL_FIRE_RL_rl_reset_complete or
	  MUX_rg_state$write_1__VAL_1 or
	  WILL_FIRE_RL_rl_stage1_CSRR_W or
	  MUX_rg_state$write_1__VAL_2 or
	  WILL_FIRE_RL_rl_stage1_CSRR_S_or_C or
	  MUX_rg_state$write_1__VAL_3 or
	  WILL_FIRE_RL_rl_reset_from_WFI or
	  WILL_FIRE_RL_rl_reset_start or
	  MUX_rg_state$write_1__SEL_6 or
	  MUX_rg_state$write_1__SEL_7 or
	  WILL_FIRE_RL_rl_stage1_FENCE_I or
	  WILL_FIRE_RL_rl_stage1_FENCE or
	  WILL_FIRE_RL_rl_stage1_SFENCE_VMA or WILL_FIRE_RL_rl_stage1_WFI)
  begin
    case (1'b1) // synopsys parallel_case
      WILL_FIRE_RL_rl_reset_complete:
	  rg_state$D_IN = MUX_rg_state$write_1__VAL_1;
      WILL_FIRE_RL_rl_stage1_CSRR_W:
	  rg_state$D_IN = MUX_rg_state$write_1__VAL_2;
      WILL_FIRE_RL_rl_stage1_CSRR_S_or_C:
	  rg_state$D_IN = MUX_rg_state$write_1__VAL_3;
      WILL_FIRE_RL_rl_reset_from_WFI: rg_state$D_IN = 4'd0;
      WILL_FIRE_RL_rl_reset_start: rg_state$D_IN = 4'd1;
      MUX_rg_state$write_1__SEL_6: rg_state$D_IN = 4'd3;
      MUX_rg_state$write_1__SEL_7: rg_state$D_IN = 4'd5;
      WILL_FIRE_RL_rl_stage1_FENCE_I: rg_state$D_IN = 4'd7;
      WILL_FIRE_RL_rl_stage1_FENCE: rg_state$D_IN = 4'd8;
      WILL_FIRE_RL_rl_stage1_SFENCE_VMA: rg_state$D_IN = 4'd9;
      WILL_FIRE_RL_rl_stage1_WFI: rg_state$D_IN = 4'd10;
      default: rg_state$D_IN = 4'b1010 /* unspecified value */ ;
    endcase
  end
  assign rg_state$EN =
	     WILL_FIRE_RL_rl_reset_complete ||
	     WILL_FIRE_RL_rl_stage1_CSRR_W ||
	     WILL_FIRE_RL_rl_stage1_CSRR_S_or_C ||
	     WILL_FIRE_RL_rl_reset_from_WFI ||
	     WILL_FIRE_RL_rl_reset_start ||
	     WILL_FIRE_RL_rl_trap_fetch ||
	     WILL_FIRE_RL_rl_WFI_resume ||
	     WILL_FIRE_RL_rl_finish_SFENCE_VMA ||
	     WILL_FIRE_RL_rl_finish_FENCE ||
	     WILL_FIRE_RL_rl_finish_FENCE_I ||
	     WILL_FIRE_RL_rl_stage1_restart_after_csrrx ||
	     WILL_FIRE_RL_rl_stage1_interrupt ||
	     WILL_FIRE_RL_rl_stage1_trap ||
	     WILL_FIRE_RL_rl_stage1_xRET ||
	     WILL_FIRE_RL_rl_stage2_nonpipe ||
	     WILL_FIRE_RL_rl_stage1_FENCE_I ||
	     WILL_FIRE_RL_rl_stage1_FENCE ||
	     WILL_FIRE_RL_rl_stage1_SFENCE_VMA ||
	     WILL_FIRE_RL_rl_stage1_WFI ;

  // register stage1_rg_full
  always@(WILL_FIRE_RL_stage1_rl_reset or
	  WILL_FIRE_RL_rl_pipe or
	  MUX_stage1_rg_full$write_1__VAL_2 or
	  MUX_imem_rg_f3$write_1__SEL_1 or
	  WILL_FIRE_RL_rl_stage1_interrupt or
	  WILL_FIRE_RL_rl_trap_fetch or
	  WILL_FIRE_RL_rl_stage1_trap or
	  WILL_FIRE_RL_rl_WFI_resume or
	  WILL_FIRE_RL_rl_finish_SFENCE_VMA or
	  WILL_FIRE_RL_rl_finish_FENCE or
	  WILL_FIRE_RL_rl_finish_FENCE_I or
	  WILL_FIRE_RL_rl_stage1_xRET or
	  WILL_FIRE_RL_rl_stage1_restart_after_csrrx or
	  WILL_FIRE_RL_rl_stage2_nonpipe)
  case (1'b1)
    WILL_FIRE_RL_stage1_rl_reset: stage1_rg_full$D_IN = 1'd0;
    WILL_FIRE_RL_rl_pipe:
	stage1_rg_full$D_IN = MUX_stage1_rg_full$write_1__VAL_2;
    MUX_imem_rg_f3$write_1__SEL_1: stage1_rg_full$D_IN = 1'd1;
    WILL_FIRE_RL_rl_stage1_interrupt: stage1_rg_full$D_IN = 1'd0;
    WILL_FIRE_RL_rl_trap_fetch: stage1_rg_full$D_IN = 1'd1;
    WILL_FIRE_RL_rl_stage1_trap: stage1_rg_full$D_IN = 1'd0;
    WILL_FIRE_RL_rl_WFI_resume || WILL_FIRE_RL_rl_finish_SFENCE_VMA ||
    WILL_FIRE_RL_rl_finish_FENCE ||
    WILL_FIRE_RL_rl_finish_FENCE_I:
	stage1_rg_full$D_IN = 1'd1;
    WILL_FIRE_RL_rl_stage1_xRET: stage1_rg_full$D_IN = 1'd0;
    WILL_FIRE_RL_rl_stage1_restart_after_csrrx: stage1_rg_full$D_IN = 1'd1;
    WILL_FIRE_RL_rl_stage2_nonpipe: stage1_rg_full$D_IN = 1'd0;
    default: stage1_rg_full$D_IN = 1'b0 /* unspecified value */ ;
  endcase
  assign stage1_rg_full$EN =
	     WILL_FIRE_RL_rl_reset_complete && rg_run_on_reset ||
	     WILL_FIRE_RL_rl_pipe ||
	     WILL_FIRE_RL_rl_stage1_interrupt ||
	     WILL_FIRE_RL_rl_stage1_trap ||
	     WILL_FIRE_RL_rl_stage1_xRET ||
	     WILL_FIRE_RL_rl_stage2_nonpipe ||
	     WILL_FIRE_RL_stage1_rl_reset ||
	     WILL_FIRE_RL_rl_trap_fetch ||
	     WILL_FIRE_RL_rl_WFI_resume ||
	     WILL_FIRE_RL_rl_finish_SFENCE_VMA ||
	     WILL_FIRE_RL_rl_finish_FENCE ||
	     WILL_FIRE_RL_rl_finish_FENCE_I ||
	     WILL_FIRE_RL_rl_stage1_restart_after_csrrx ;

  // register stage2_rg_full
  always@(stage2_f_reset_reqs$EMPTY_N or
	  WILL_FIRE_RL_rl_pipe or
	  MUX_stage2_rg_full$write_1__VAL_2 or
	  MUX_imem_rg_f3$write_1__SEL_1 or WILL_FIRE_RL_rl_stage2_nonpipe)
  case (1'b1)
    stage2_f_reset_reqs$EMPTY_N: stage2_rg_full$D_IN = 1'd0;
    WILL_FIRE_RL_rl_pipe:
	stage2_rg_full$D_IN = MUX_stage2_rg_full$write_1__VAL_2;
    MUX_imem_rg_f3$write_1__SEL_1 || WILL_FIRE_RL_rl_stage2_nonpipe:
	stage2_rg_full$D_IN = 1'd0;
    default: stage2_rg_full$D_IN = 1'b0 /* unspecified value */ ;
  endcase
  assign stage2_rg_full$EN =
	     WILL_FIRE_RL_rl_reset_complete && rg_run_on_reset ||
	     WILL_FIRE_RL_rl_pipe ||
	     WILL_FIRE_RL_rl_stage2_nonpipe ||
	     stage2_f_reset_reqs$EMPTY_N ;

  // register stage2_rg_resetting
  assign stage2_rg_resetting$D_IN = stage2_f_reset_reqs$EMPTY_N ;
  assign stage2_rg_resetting$EN =
	     WILL_FIRE_RL_stage2_rl_reset_end || stage2_f_reset_reqs$EMPTY_N ;

  // register stage2_rg_stage2
  assign stage2_rg_stage2$D_IN =
	     { rg_cur_priv,
	       imem_rg_pc,
	       x_out_data_to_stage2_instr__h11612,
	       IF_NOT_stage1_rg_full_94_95_OR_NOT_near_mem_im_ETC___d825,
	       x_out_data_to_stage2_rd__h11614,
	       x_out_data_to_stage2_addr__h11615,
	       x_out_data_to_stage2_val1__h11616,
	       x_out_data_to_stage2_val2__h11617 } ;
  assign stage2_rg_stage2$EN =
	     WILL_FIRE_RL_rl_pipe &&
	     NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d1133 ;

  // register stage3_rg_full
  always@(WILL_FIRE_RL_stage3_rl_reset or
	  WILL_FIRE_RL_rl_pipe or
	  IF_stage2_rg_full_7_THEN_IF_stage2_rg_stage2_8_ETC___d118 or
	  MUX_imem_rg_f3$write_1__SEL_1)
  case (1'b1)
    WILL_FIRE_RL_stage3_rl_reset: stage3_rg_full$D_IN = 1'd0;
    WILL_FIRE_RL_rl_pipe:
	stage3_rg_full$D_IN =
	    IF_stage2_rg_full_7_THEN_IF_stage2_rg_stage2_8_ETC___d118 == 2'd2;
    MUX_imem_rg_f3$write_1__SEL_1: stage3_rg_full$D_IN = 1'd0;
    default: stage3_rg_full$D_IN = 1'b0 /* unspecified value */ ;
  endcase
  assign stage3_rg_full$EN =
	     WILL_FIRE_RL_rl_reset_complete && rg_run_on_reset ||
	     WILL_FIRE_RL_rl_pipe ||
	     WILL_FIRE_RL_stage3_rl_reset ;

  // register stage3_rg_stage3
  assign stage3_rg_stage3$D_IN =
	     { stage2_rg_stage2[167:104],
	       stage2_rg_stage2[169:168],
	       stage2_rg_stage2[103:101] == 3'd0 ||
	       IF_stage2_rg_stage2_8_BITS_103_TO_101_9_EQ_1_1_ETC___d141,
	       x_out_data_to_stage3_rd__h5641,
	       x_out_data_to_stage3_rd_val__h5642 } ;
  assign stage3_rg_stage3$EN =
	     WILL_FIRE_RL_rl_pipe &&
	     IF_stage2_rg_full_7_THEN_IF_stage2_rg_stage2_8_ETC___d118 ==
	     2'd2 ;

  // submodule csr_regfile
  assign csr_regfile$access_permitted_1_csr_addr =
	     x_out_data_to_stage2_instr__h11612[31:20] ;
  assign csr_regfile$access_permitted_1_priv = rg_cur_priv ;
  assign csr_regfile$access_permitted_1_read_not_write = 1'd0 ;
  assign csr_regfile$access_permitted_2_csr_addr =
	     x_out_data_to_stage2_instr__h11612[31:20] ;
  assign csr_regfile$access_permitted_2_priv = rg_cur_priv ;
  assign csr_regfile$access_permitted_2_read_not_write =
	     rs1_val__h17721 == 32'd0 ;
  assign csr_regfile$csr_counter_read_fault_csr_addr = 12'h0 ;
  assign csr_regfile$csr_counter_read_fault_priv = 2'h0 ;
  always@(IF_NOT_stage1_rg_full_94_95_OR_NOT_near_mem_im_ETC___d746)
  begin
    case (IF_NOT_stage1_rg_full_94_95_OR_NOT_near_mem_im_ETC___d746)
      4'd7: csr_regfile$csr_ret_actions_from_priv = 2'b11;
      4'd8: csr_regfile$csr_ret_actions_from_priv = 2'b01;
      default: csr_regfile$csr_ret_actions_from_priv = 2'b0;
    endcase
  end
  always@(WILL_FIRE_RL_rl_stage1_interrupt or
	  MUX_csr_regfile$csr_trap_actions_5__VAL_1 or
	  WILL_FIRE_RL_rl_stage1_trap or
	  x_out_trap_info_exc_code__h13233 or
	  WILL_FIRE_RL_rl_stage2_nonpipe or near_mem$dmem_exc_code)
  begin
    case (1'b1) // synopsys parallel_case
      WILL_FIRE_RL_rl_stage1_interrupt:
	  csr_regfile$csr_trap_actions_exc_code =
	      MUX_csr_regfile$csr_trap_actions_5__VAL_1;
      WILL_FIRE_RL_rl_stage1_trap:
	  csr_regfile$csr_trap_actions_exc_code =
	      x_out_trap_info_exc_code__h13233;
      WILL_FIRE_RL_rl_stage2_nonpipe:
	  csr_regfile$csr_trap_actions_exc_code = near_mem$dmem_exc_code;
      default: csr_regfile$csr_trap_actions_exc_code =
		   4'b1010 /* unspecified value */ ;
    endcase
  end
  assign csr_regfile$csr_trap_actions_from_priv = rg_cur_priv ;
  assign csr_regfile$csr_trap_actions_interrupt =
	     WILL_FIRE_RL_rl_stage1_interrupt && !csr_regfile$nmi_pending ;
  assign csr_regfile$csr_trap_actions_nmi =
	     WILL_FIRE_RL_rl_stage1_interrupt && csr_regfile$nmi_pending ;
  assign csr_regfile$csr_trap_actions_pc =
	     WILL_FIRE_RL_rl_stage2_nonpipe ?
	       stage2_rg_stage2[167:136] :
	       imem_rg_pc ;
  always@(WILL_FIRE_RL_rl_stage1_interrupt or
	  WILL_FIRE_RL_rl_stage1_trap or
	  value__h13281 or WILL_FIRE_RL_rl_stage2_nonpipe or stage2_rg_stage2)
  begin
    case (1'b1) // synopsys parallel_case
      WILL_FIRE_RL_rl_stage1_interrupt:
	  csr_regfile$csr_trap_actions_xtval = 32'd0;
      WILL_FIRE_RL_rl_stage1_trap:
	  csr_regfile$csr_trap_actions_xtval = value__h13281;
      WILL_FIRE_RL_rl_stage2_nonpipe:
	  csr_regfile$csr_trap_actions_xtval = stage2_rg_stage2[95:64];
      default: csr_regfile$csr_trap_actions_xtval =
		   32'hAAAAAAAA /* unspecified value */ ;
    endcase
  end
  assign csr_regfile$interrupt_pending_cur_priv = rg_cur_priv ;
  assign csr_regfile$m_external_interrupt_req_set_not_clear =
	     m_external_interrupt_req_set_not_clear ;
  assign csr_regfile$mav_csr_write_csr_addr =
	     x_out_data_to_stage2_instr__h11612[31:20] ;
  assign csr_regfile$mav_csr_write_word =
	     MUX_csr_regfile$mav_csr_write_1__SEL_1 ?
	       rs1_val__h17231 :
	       MUX_csr_regfile$mav_csr_write_2__VAL_2 ;
  assign csr_regfile$mav_read_csr_csr_addr = 12'h0 ;
  assign csr_regfile$nmi_req_set_not_clear = nmi_req_set_not_clear ;
  assign csr_regfile$read_csr_csr_addr =
	     x_out_data_to_stage2_instr__h11612[31:20] ;
  assign csr_regfile$read_csr_port2_csr_addr = 12'h0 ;
  assign csr_regfile$s_external_interrupt_req_set_not_clear =
	     s_external_interrupt_req_set_not_clear ;
  assign csr_regfile$software_interrupt_req_set_not_clear =
	     software_interrupt_req_set_not_clear ;
  assign csr_regfile$timer_interrupt_req_set_not_clear =
	     timer_interrupt_req_set_not_clear ;
  assign csr_regfile$EN_server_reset_request_put =
	     CAN_FIRE_RL_rl_reset_start ;
  assign csr_regfile$EN_server_reset_response_get =
	     MUX_rg_state$write_1__SEL_1 ;
  assign csr_regfile$EN_mav_read_csr = 1'b0 ;
  assign csr_regfile$EN_mav_csr_write =
	     WILL_FIRE_RL_rl_stage1_CSRR_W &&
	     csr_regfile$access_permitted_1 ||
	     WILL_FIRE_RL_rl_stage1_CSRR_S_or_C &&
	     csr_regfile$access_permitted_2 &&
	     x_out_data_to_stage2_instr__h11612[19:15] != 5'd0 ;
  assign csr_regfile$EN_csr_trap_actions = MUX_rg_cur_priv$write_1__SEL_1 ;
  assign csr_regfile$EN_csr_ret_actions = CAN_FIRE_RL_rl_stage1_xRET ;
  assign csr_regfile$EN_csr_minstret_incr =
	     WILL_FIRE_RL_rl_pipe &&
	     IF_stage2_rg_full_7_THEN_IF_stage2_rg_stage2_8_ETC___d118 ==
	     2'd2 ||
	     WILL_FIRE_RL_rl_stage1_CSRR_W &&
	     csr_regfile$access_permitted_1 ||
	     WILL_FIRE_RL_rl_stage1_CSRR_S_or_C &&
	     csr_regfile$access_permitted_2 ||
	     WILL_FIRE_RL_rl_stage1_WFI ||
	     WILL_FIRE_RL_rl_stage1_FENCE ||
	     WILL_FIRE_RL_rl_stage1_FENCE_I ||
	     WILL_FIRE_RL_rl_stage1_xRET ||
	     WILL_FIRE_RL_rl_stage2_nonpipe ||
	     WILL_FIRE_RL_rl_stage1_SFENCE_VMA ;
  assign csr_regfile$EN_debug = 1'b0 ;

  // submodule f_reset_reqs
  assign f_reset_reqs$D_IN = hart0_server_reset_request_put ;
  assign f_reset_reqs$ENQ = EN_hart0_server_reset_request_put ;
  assign f_reset_reqs$DEQ =
	     gpr_regfile_RDY_server_reset_request_put__031__ETC___d1043 &&
	     rg_state == 4'd0 ;
  assign f_reset_reqs$CLR = 1'b0 ;

  // submodule f_reset_rsps
  assign f_reset_rsps$D_IN = rg_run_on_reset ;
  assign f_reset_rsps$ENQ = MUX_rg_state$write_1__SEL_1 ;
  assign f_reset_rsps$DEQ = EN_hart0_server_reset_response_get ;
  assign f_reset_rsps$CLR = 1'b0 ;

  // submodule gpr_regfile
  assign gpr_regfile$read_rs1_port2_rs1 = 5'h0 ;
  assign gpr_regfile$read_rs1_rs1 = _theResult____h4280[19:15] ;
  assign gpr_regfile$read_rs2_rs2 = _theResult____h4280[24:20] ;
  assign gpr_regfile$write_rd_rd =
	     MUX_gpr_regfile$write_rd_1__SEL_1 ?
	       stage3_rg_stage3[36:32] :
	       x_out_data_to_stage2_instr__h11612[11:7] ;
  assign gpr_regfile$write_rd_rd_val =
	     (MUX_csr_regfile$mav_csr_write_1__SEL_1 ||
	      MUX_gpr_regfile$write_rd_1__SEL_3) ?
	       csr_regfile$read_csr[31:0] :
	       stage3_rg_stage3[31:0] ;
  assign gpr_regfile$EN_server_reset_request_put =
	     CAN_FIRE_RL_rl_reset_start ;
  assign gpr_regfile$EN_server_reset_response_get =
	     MUX_rg_state$write_1__SEL_1 ;
  assign gpr_regfile$EN_write_rd =
	     WILL_FIRE_RL_rl_pipe && stage3_rg_full && stage3_rg_stage3[37] ||
	     WILL_FIRE_RL_rl_stage1_CSRR_W &&
	     csr_regfile$access_permitted_1 ||
	     WILL_FIRE_RL_rl_stage1_CSRR_S_or_C &&
	     csr_regfile$access_permitted_2 ;

  // submodule near_mem
  assign near_mem$dmem_master_arready = dmem_master_arready ;
  assign near_mem$dmem_master_awready = dmem_master_awready ;
  assign near_mem$dmem_master_bid = dmem_master_bid ;
  assign near_mem$dmem_master_bresp = dmem_master_bresp ;
  assign near_mem$dmem_master_bvalid = dmem_master_bvalid ;
  assign near_mem$dmem_master_rdata = dmem_master_rdata ;
  assign near_mem$dmem_master_rid = dmem_master_rid ;
  assign near_mem$dmem_master_rlast = dmem_master_rlast ;
  assign near_mem$dmem_master_rresp = dmem_master_rresp ;
  assign near_mem$dmem_master_rvalid = dmem_master_rvalid ;
  assign near_mem$dmem_master_wready = dmem_master_wready ;
  assign near_mem$dmem_req_addr = x_out_data_to_stage2_addr__h11615 ;
  assign near_mem$dmem_req_amo_funct7 =
	     x_out_data_to_stage2_val1__h11616[6:0] ;
  assign near_mem$dmem_req_f3 = x_out_data_to_stage2_instr__h11612[14:12] ;
  assign near_mem$dmem_req_mstatus_MXR = csr_regfile$read_mstatus[19] ;
  always@(IF_NOT_stage1_rg_full_94_95_OR_NOT_near_mem_im_ETC___d825)
  begin
    case (IF_NOT_stage1_rg_full_94_95_OR_NOT_near_mem_im_ETC___d825)
      3'd1: near_mem$dmem_req_op = 2'd0;
      3'd2: near_mem$dmem_req_op = 2'd1;
      default: near_mem$dmem_req_op = 2'd2;
    endcase
  end
  assign near_mem$dmem_req_priv =
	     csr_regfile$read_mstatus[17] ?
	       csr_regfile$read_mstatus[12:11] :
	       rg_cur_priv ;
  assign near_mem$dmem_req_satp = csr_regfile$read_satp ;
  assign near_mem$dmem_req_sstatus_SUM = 1'd0 ;
  assign near_mem$dmem_req_store_value =
	     { 32'd0, x_out_data_to_stage2_val2__h11617 } ;
  assign near_mem$imem_master_arready = imem_master_arready ;
  assign near_mem$imem_master_awready = imem_master_awready ;
  assign near_mem$imem_master_bid = imem_master_bid ;
  assign near_mem$imem_master_bresp = imem_master_bresp ;
  assign near_mem$imem_master_bvalid = imem_master_bvalid ;
  assign near_mem$imem_master_rdata = imem_master_rdata ;
  assign near_mem$imem_master_rid = imem_master_rid ;
  assign near_mem$imem_master_rlast = imem_master_rlast ;
  assign near_mem$imem_master_rresp = imem_master_rresp ;
  assign near_mem$imem_master_rvalid = imem_master_rvalid ;
  assign near_mem$imem_master_wready = imem_master_wready ;
  always@(MUX_imem_rg_f3$write_1__SEL_1 or
	  MUX_near_mem$imem_req_2__VAL_1 or
	  MUX_imem_rg_f3$write_1__SEL_2 or
	  MUX_near_mem$imem_req_2__VAL_2 or
	  WILL_FIRE_RL_imem_rl_fetch_next_32b or
	  next_pc___1__h13393 or
	  WILL_FIRE_RL_rl_stage1_restart_after_csrrx or
	  WILL_FIRE_RL_rl_trap_fetch or
	  MUX_near_mem$imem_req_2__VAL_5 or MUX_near_mem$imem_req_1__SEL_6)
  begin
    case (1'b1) // synopsys parallel_case
      MUX_imem_rg_f3$write_1__SEL_1:
	  near_mem$imem_req_addr = MUX_near_mem$imem_req_2__VAL_1;
      MUX_imem_rg_f3$write_1__SEL_2:
	  near_mem$imem_req_addr = MUX_near_mem$imem_req_2__VAL_2;
      WILL_FIRE_RL_imem_rl_fetch_next_32b:
	  near_mem$imem_req_addr = next_pc___1__h13393;
      WILL_FIRE_RL_rl_stage1_restart_after_csrrx:
	  near_mem$imem_req_addr = MUX_near_mem$imem_req_2__VAL_2;
      WILL_FIRE_RL_rl_trap_fetch:
	  near_mem$imem_req_addr = MUX_near_mem$imem_req_2__VAL_5;
      MUX_near_mem$imem_req_1__SEL_6:
	  near_mem$imem_req_addr = MUX_near_mem$imem_req_2__VAL_5;
      default: near_mem$imem_req_addr = 32'hAAAAAAAA /* unspecified value */ ;
    endcase
  end
  assign near_mem$imem_req_f3 =
	     WILL_FIRE_RL_imem_rl_fetch_next_32b ? imem_rg_f3 : 3'b010 ;
  always@(MUX_imem_rg_f3$write_1__SEL_1 or
	  MUX_imem_rg_f3$write_1__SEL_2 or
	  WILL_FIRE_RL_rl_stage1_restart_after_csrrx or
	  MUX_near_mem$imem_req_1__SEL_6 or
	  csr_regfile$read_mstatus or
	  WILL_FIRE_RL_rl_trap_fetch or
	  rg_mstatus_MXR or
	  WILL_FIRE_RL_imem_rl_fetch_next_32b or imem_rg_mstatus_MXR)
  begin
    case (1'b1) // synopsys parallel_case
      MUX_imem_rg_f3$write_1__SEL_1 || MUX_imem_rg_f3$write_1__SEL_2 ||
      WILL_FIRE_RL_rl_stage1_restart_after_csrrx ||
      MUX_near_mem$imem_req_1__SEL_6:
	  near_mem$imem_req_mstatus_MXR = csr_regfile$read_mstatus[19];
      WILL_FIRE_RL_rl_trap_fetch:
	  near_mem$imem_req_mstatus_MXR = rg_mstatus_MXR;
      WILL_FIRE_RL_imem_rl_fetch_next_32b:
	  near_mem$imem_req_mstatus_MXR = imem_rg_mstatus_MXR;
      default: near_mem$imem_req_mstatus_MXR = 1'b0 /* unspecified value */ ;
    endcase
  end
  assign near_mem$imem_req_priv =
	     (MUX_imem_rg_f3$write_1__SEL_1 ||
	      MUX_imem_rg_f3$write_1__SEL_2 ||
	      WILL_FIRE_RL_rl_stage1_restart_after_csrrx ||
	      WILL_FIRE_RL_rl_trap_fetch ||
	      MUX_near_mem$imem_req_1__SEL_6) ?
	       rg_cur_priv :
	       imem_rg_priv ;
  assign near_mem$imem_req_satp =
	     WILL_FIRE_RL_imem_rl_fetch_next_32b ?
	       imem_rg_satp :
	       csr_regfile$read_satp ;
  always@(WILL_FIRE_RL_rl_trap_fetch or
	  rg_sstatus_SUM or
	  WILL_FIRE_RL_imem_rl_fetch_next_32b or
	  imem_rg_sstatus_SUM or
	  MUX_imem_rg_f3$write_1__SEL_1 or
	  MUX_imem_rg_f3$write_1__SEL_2 or
	  WILL_FIRE_RL_rl_stage1_restart_after_csrrx or
	  MUX_near_mem$imem_req_1__SEL_6)
  begin
    case (1'b1) // synopsys parallel_case
      WILL_FIRE_RL_rl_trap_fetch:
	  near_mem$imem_req_sstatus_SUM = rg_sstatus_SUM;
      WILL_FIRE_RL_imem_rl_fetch_next_32b:
	  near_mem$imem_req_sstatus_SUM = imem_rg_sstatus_SUM;
      MUX_imem_rg_f3$write_1__SEL_1 || MUX_imem_rg_f3$write_1__SEL_2 ||
      WILL_FIRE_RL_rl_stage1_restart_after_csrrx ||
      MUX_near_mem$imem_req_1__SEL_6:
	  near_mem$imem_req_sstatus_SUM = 1'd0;
      default: near_mem$imem_req_sstatus_SUM = 1'b0 /* unspecified value */ ;
    endcase
  end
  assign near_mem$server_fence_request_put =
	     8'b10101010 /* unspecified value */  ;
  assign near_mem$EN_server_reset_request_put = CAN_FIRE_RL_rl_reset_start ;
  assign near_mem$EN_server_reset_response_get = MUX_rg_state$write_1__SEL_1 ;
  assign near_mem$EN_imem_req =
	     WILL_FIRE_RL_rl_reset_complete && rg_run_on_reset ||
	     WILL_FIRE_RL_rl_pipe &&
	     NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d1112 &&
	     NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d1154 ||
	     WILL_FIRE_RL_imem_rl_fetch_next_32b ||
	     WILL_FIRE_RL_rl_stage1_restart_after_csrrx ||
	     WILL_FIRE_RL_rl_trap_fetch ||
	     WILL_FIRE_RL_rl_WFI_resume ||
	     WILL_FIRE_RL_rl_finish_SFENCE_VMA ||
	     WILL_FIRE_RL_rl_finish_FENCE ||
	     WILL_FIRE_RL_rl_finish_FENCE_I ;
  assign near_mem$EN_dmem_req =
	     WILL_FIRE_RL_rl_pipe &&
	     NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d1133 &&
	     (IF_NOT_stage1_rg_full_94_95_OR_NOT_near_mem_im_ETC___d825 ==
	      3'd1 ||
	      IF_NOT_stage1_rg_full_94_95_OR_NOT_near_mem_im_ETC___d825 ==
	      3'd2 ||
	      IF_NOT_stage1_rg_full_94_95_OR_NOT_near_mem_im_ETC___d825 ==
	      3'd4) ;
  assign near_mem$EN_server_fence_i_request_put =
	     MUX_rg_state$write_1__SEL_8 ;
  assign near_mem$EN_server_fence_i_response_get =
	     CAN_FIRE_RL_rl_finish_FENCE_I ;
  assign near_mem$EN_server_fence_request_put = MUX_rg_state$write_1__SEL_9 ;
  assign near_mem$EN_server_fence_response_get = CAN_FIRE_RL_rl_finish_FENCE ;
  assign near_mem$EN_sfence_vma = MUX_rg_state$write_1__SEL_10 ;

  // submodule soc_map
  assign soc_map$m_is_IO_addr_addr = 64'h0 ;
  assign soc_map$m_is_mem_addr_addr = 64'h0 ;
  assign soc_map$m_is_near_mem_IO_addr_addr = 64'h0 ;

  // submodule stage1_f_reset_reqs
  assign stage1_f_reset_reqs$ENQ = CAN_FIRE_RL_rl_reset_start ;
  assign stage1_f_reset_reqs$DEQ = CAN_FIRE_RL_stage1_rl_reset ;
  assign stage1_f_reset_reqs$CLR = 1'b0 ;

  // submodule stage1_f_reset_rsps
  assign stage1_f_reset_rsps$ENQ = CAN_FIRE_RL_stage1_rl_reset ;
  assign stage1_f_reset_rsps$DEQ = MUX_rg_state$write_1__SEL_1 ;
  assign stage1_f_reset_rsps$CLR = 1'b0 ;

  // submodule stage2_f_reset_reqs
  assign stage2_f_reset_reqs$ENQ = CAN_FIRE_RL_rl_reset_start ;
  assign stage2_f_reset_reqs$DEQ = stage2_f_reset_reqs$EMPTY_N ;
  assign stage2_f_reset_reqs$CLR = 1'b0 ;

  // submodule stage2_f_reset_rsps
  assign stage2_f_reset_rsps$ENQ = CAN_FIRE_RL_stage2_rl_reset_end ;
  assign stage2_f_reset_rsps$DEQ = MUX_rg_state$write_1__SEL_1 ;
  assign stage2_f_reset_rsps$CLR = 1'b0 ;

  // submodule stage2_mbox
  assign stage2_mbox$req_f3 = x_out_data_to_stage2_instr__h11612[14:12] ;
  assign stage2_mbox$req_is_OP_not_OP_32 = !_theResult____h4280[3] ;
  assign stage2_mbox$req_v1 = x_out_data_to_stage2_val1__h11616 ;
  assign stage2_mbox$req_v2 = x_out_data_to_stage2_val2__h11617 ;
  assign stage2_mbox$set_verbosity_verbosity = 4'h0 ;
  assign stage2_mbox$EN_set_verbosity = 1'b0 ;
  assign stage2_mbox$EN_req_reset = 1'b0 ;
  assign stage2_mbox$EN_rsp_reset = 1'b0 ;
  assign stage2_mbox$EN_req =
	     WILL_FIRE_RL_rl_pipe &&
	     NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d1133 &&
	     IF_NOT_stage1_rg_full_94_95_OR_NOT_near_mem_im_ETC___d825 ==
	     3'd3 ;

  // submodule stage3_f_reset_reqs
  assign stage3_f_reset_reqs$ENQ = CAN_FIRE_RL_rl_reset_start ;
  assign stage3_f_reset_reqs$DEQ = CAN_FIRE_RL_stage3_rl_reset ;
  assign stage3_f_reset_reqs$CLR = 1'b0 ;

  // submodule stage3_f_reset_rsps
  assign stage3_f_reset_rsps$ENQ = CAN_FIRE_RL_stage3_rl_reset ;
  assign stage3_f_reset_rsps$DEQ = MUX_rg_state$write_1__SEL_1 ;
  assign stage3_f_reset_rsps$CLR = 1'b0 ;

  // remaining internal signals
  assign IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d1080 =
	     IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d680 ||
	     IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d682 ||
	     near_mem$imem_exc ||
	     IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d622 &&
	     IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d633 ;
  assign IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d523 =
	     rs1_val_bypassed__h4288 == rs2_val__h11713 ;
  assign IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d525 =
	     (rs1_val_bypassed__h4288 ^ 32'h80000000) <
	     (rs2_val__h11713 ^ 32'h80000000) ;
  assign IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d527 =
	     rs1_val_bypassed__h4288 < rs2_val__h11713 ;
  assign IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d622 =
	     (_theResult____h4280[6:0] == 7'b1100011) ?
	       _theResult____h4280[14:12] != 3'b0 &&
	       _theResult____h4280[14:12] != 3'b001 &&
	       _theResult____h4280[14:12] != 3'b100 &&
	       _theResult____h4280[14:12] != 3'b101 &&
	       _theResult____h4280[14:12] != 3'b110 &&
	       _theResult____h4280[14:12] != 3'b111 ||
	       IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d534 :
	       (_theResult____h4280[6:0] != 7'b0110011 ||
		_theResult____h4280[31:25] != 7'b0000001) &&
	       (((_theResult____h4280[6:0] == 7'b0010011 ||
		  _theResult____h4280[6:0] == 7'b0110011) &&
		 (_theResult____h4280[14:12] == 3'b001 ||
		  _theResult____h4280[14:12] == 3'b101)) ?
		  _theResult____h4280[25] :
		  CASE_theResult__280_BITS_6_TO_0_0b10011_NOT_IF_ETC__q9) ;
  assign IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d633 =
	     (_theResult____h4280[6:0] == 7'b1100011) ?
	       _theResult____h4280[14:12] != 3'b0 &&
	       _theResult____h4280[14:12] != 3'b001 &&
	       _theResult____h4280[14:12] != 3'b100 &&
	       _theResult____h4280[14:12] != 3'b101 &&
	       _theResult____h4280[14:12] != 3'b110 &&
	       _theResult____h4280[14:12] != 3'b111 ||
	       IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d628 :
	       _theResult____h4280[6:0] != 7'b1101111 &&
	       _theResult____h4280[6:0] != 7'b1100111 ;
  assign IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d680 =
	     (_theResult____h4280[6:0] == 7'b1100011) ?
	       (_theResult____h4280[14:12] == 3'b0 ||
		_theResult____h4280[14:12] == 3'b001 ||
		_theResult____h4280[14:12] == 3'b100 ||
		_theResult____h4280[14:12] == 3'b101 ||
		_theResult____h4280[14:12] == 3'b110 ||
		_theResult____h4280[14:12] == 3'b111) &&
	       IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d628 :
	       _theResult____h4280[6:0] == 7'b0110011 &&
	       _theResult____h4280[31:25] == 7'b0000001 ||
	       (((_theResult____h4280[6:0] == 7'b0010011 ||
		  _theResult____h4280[6:0] == 7'b0110011) &&
		 (_theResult____h4280[14:12] == 3'b001 ||
		  _theResult____h4280[14:12] == 3'b101)) ?
		  !_theResult____h4280[25] :
		  CASE_theResult__280_BITS_6_TO_0_0b10011_IF_NOT_ETC__q11) ;
  assign IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d682 =
	     (_theResult____h4280[6:0] == 7'b1100011) ?
	       (_theResult____h4280[14:12] == 3'b0 ||
		_theResult____h4280[14:12] == 3'b001 ||
		_theResult____h4280[14:12] == 3'b100 ||
		_theResult____h4280[14:12] == 3'b101 ||
		_theResult____h4280[14:12] == 3'b110 ||
		_theResult____h4280[14:12] == 3'b111) &&
	       IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d534 :
	       _theResult____h4280[6:0] == 7'b1101111 ||
	       _theResult____h4280[6:0] == 7'b1100111 ;
  assign IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d937 =
	     ((_theResult____h4280[6:0] == 7'b0010011 ||
	       _theResult____h4280[6:0] == 7'b0110011) &&
	      (_theResult____h4280[14:12] == 3'b001 ||
	       _theResult____h4280[14:12] == 3'b101)) ?
	       alu_outputs___1_val1__h11890 :
	       IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d936 ;
  assign IF_NOT_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_P_ETC___d690 =
	     NOT_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS_ETC___d564 ?
	       4'd11 :
	       4'd0 ;
  assign IF_NOT_near_mem_dmem_valid__09_28_OR_NOT_near__ETC___d176 =
	     (!near_mem$dmem_valid || !near_mem$dmem_exc) ?
	       IF_stage2_rg_stage2_8_BITS_100_TO_96_48_EQ_0_7_ETC___d175 :
	       2'd0 ;
  assign IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS_2_9_ETC___d653 =
	     _theResult____h4280[14:12] == 3'b0 &&
	     (_theResult____h4280[6:0] != 7'b0110011 ||
	      !_theResult____h4280[30]) ||
	     _theResult____h4280[14:12] == 3'b0 &&
	     _theResult____h4280[6:0] == 7'b0110011 &&
	     _theResult____h4280[30] ||
	     _theResult____h4280[14:12] == 3'b010 ||
	     _theResult____h4280[14:12] == 3'b011 ||
	     _theResult____h4280[14:12] == 3'b100 ||
	     _theResult____h4280[14:12] == 3'b110 ||
	     _theResult____h4280[14:12] == 3'b111 ;
  assign IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS_2_9_ETC___d869 =
	     NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS_2_9_97_ETC___d205 ?
	       next_pc___1__h13393 :
	       next_pc__h13391 ;
  assign IF_NOT_stage1_rg_full_94_95_OR_NOT_near_mem_im_ETC___d1270 =
	     imem_rg_pc == csr_regfile$csr_trap_actions[97:66] ;
  assign IF_NOT_stage1_rg_full_94_95_OR_NOT_near_mem_im_ETC___d746 =
	     near_mem$imem_exc ?
	       4'd11 :
	       IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d744 ;
  assign IF_csr_regfile_read_csr_IF_NOT_stage1_rg_full__ETC___d1220 =
	     csr_regfile$read_csr[31:0] | rs1_val__h17721 ;
  assign IF_csr_regfile_read_misa__0_BIT_2_12_AND_IF_ne_ETC___d437 =
	     (csr_regfile$read_misa[2] && instr__h4278[1:0] == 2'b01 &&
	      instr__h4278[15:10] == 6'b100011 &&
	      instr__h4278[6:5] == 2'b0) ?
	       instr__h11148 :
	       ((csr_regfile$read_misa[2] && instr__h4278[1:0] == 2'b10 &&
		 instr__h4278[15:12] == 4'b1001 &&
		 instr__h4278[11:7] == 5'd0 &&
		 instr__h4278[6:2] == 5'd0) ?
		  instr__h11486 :
		  32'h0) ;
  assign IF_csr_regfile_read_misa__0_BIT_2_12_AND_IF_ne_ETC___d439 =
	     (csr_regfile$read_misa[2] && instr__h4278[1:0] == 2'b01 &&
	      instr__h4278[15:10] == 6'b100011 &&
	      instr__h4278[6:5] == 2'b10) ?
	       instr__h10876 :
	       ((csr_regfile$read_misa[2] && instr__h4278[1:0] == 2'b01 &&
		 instr__h4278[15:10] == 6'b100011 &&
		 instr__h4278[6:5] == 2'b01) ?
		  instr__h11012 :
		  IF_csr_regfile_read_misa__0_BIT_2_12_AND_IF_ne_ETC___d437) ;
  assign IF_csr_regfile_read_misa__0_BIT_2_12_AND_IF_ne_ETC___d441 =
	     (csr_regfile_read_misa__0_BIT_2_12_AND_IF_near__ETC___d308 &&
	      instr__h4278[6:2] != 5'd0) ?
	       instr__h10645 :
	       ((csr_regfile$read_misa[2] && instr__h4278[1:0] == 2'b01 &&
		 instr__h4278[15:10] == 6'b100011 &&
		 instr__h4278[6:5] == 2'b11) ?
		  instr__h10740 :
		  IF_csr_regfile_read_misa__0_BIT_2_12_AND_IF_ne_ETC___d439) ;
  assign IF_csr_regfile_read_misa__0_BIT_2_12_AND_IF_ne_ETC___d442 =
	     (csr_regfile_read_misa__0_BIT_2_12_AND_IF_near__ETC___d302 &&
	      instr__h4278[6:2] != 5'd0) ?
	       instr__h10526 :
	       IF_csr_regfile_read_misa__0_BIT_2_12_AND_IF_ne_ETC___d441 ;
  assign IF_csr_regfile_read_misa__0_BIT_2_12_AND_IF_ne_ETC___d444 =
	     (csr_regfile$read_misa[2] && instr__h4278[1:0] == 2'b01 &&
	      instr__h4278[15:13] == 3'b100 &&
	      instr__h4278[11:10] == 2'b01 &&
	      imm6__h8672 != 6'd0 &&
	      !instr__h4278[12]) ?
	       instr__h10231 :
	       ((csr_regfile$read_misa[2] && instr__h4278[1:0] == 2'b01 &&
		 instr__h4278[15:13] == 3'b100 &&
		 instr__h4278[11:10] == 2'b10) ?
		  instr__h10348 :
		  IF_csr_regfile_read_misa__0_BIT_2_12_AND_IF_ne_ETC___d442) ;
  assign IF_csr_regfile_read_misa__0_BIT_2_12_AND_IF_ne_ETC___d445 =
	     (csr_regfile$read_misa[2] && instr__h4278[1:0] == 2'b01 &&
	      instr__h4278[15:13] == 3'b100 &&
	      instr__h4278[11:10] == 2'b0 &&
	      imm6__h8672 != 6'd0 &&
	      !instr__h4278[12]) ?
	       instr__h10038 :
	       IF_csr_regfile_read_misa__0_BIT_2_12_AND_IF_ne_ETC___d444 ;
  assign IF_csr_regfile_read_misa__0_BIT_2_12_AND_IF_ne_ETC___d446 =
	     (csr_regfile$read_misa[2] && instr__h4278[1:0] == 2'b10 &&
	      instr__h4278[15:13] == 3'b0 &&
	      instr__h4278[11:7] != 5'd0 &&
	      imm6__h8672 != 6'd0 &&
	      !instr__h4278[12]) ?
	       instr__h9845 :
	       IF_csr_regfile_read_misa__0_BIT_2_12_AND_IF_ne_ETC___d445 ;
  assign IF_csr_regfile_read_misa__0_BIT_2_12_AND_IF_ne_ETC___d448 =
	     (csr_regfile$read_misa[2] && instr__h4278[1:0] == 2'b01 &&
	      instr__h4278[15:13] == 3'b011 &&
	      instr__h4278[11:7] == 5'd2 &&
	      nzimm10__h9296 != 10'd0) ?
	       instr__h9500 :
	       ((csr_regfile$read_misa[2] && instr__h4278[1:0] == 2'b0 &&
		 instr__h4278[15:13] == 3'b0 &&
		 nzimm10__h9511 != 10'd0) ?
		  instr__h9672 :
		  IF_csr_regfile_read_misa__0_BIT_2_12_AND_IF_ne_ETC___d446) ;
  assign IF_csr_regfile_read_misa__0_BIT_2_12_AND_IF_ne_ETC___d449 =
	     (csr_regfile$read_misa[2] && instr__h4278[1:0] == 2'b01 &&
	      instr__h4278[15:13] == 3'b0 &&
	      instr__h4278[11:7] != 5'd0 &&
	      imm6__h8672 != 6'd0 ||
	      csr_regfile$read_misa[2] && instr__h4278[1:0] == 2'b01 &&
	      instr__h4278[15:13] == 3'b0 &&
	      instr__h4278[11:7] == 5'd0 &&
	      imm6__h8672 == 6'd0) ?
	       instr__h9063 :
	       IF_csr_regfile_read_misa__0_BIT_2_12_AND_IF_ne_ETC___d448 ;
  assign IF_csr_regfile_read_misa__0_BIT_2_12_AND_IF_ne_ETC___d450 =
	     (csr_regfile$read_misa[2] && instr__h4278[1:0] == 2'b01 &&
	      instr__h4278[15:13] == 3'b011 &&
	      instr__h4278[11:7] != 5'd0 &&
	      instr__h4278[11:7] != 5'd2 &&
	      imm6__h8672 != 6'd0) ?
	       instr__h8934 :
	       IF_csr_regfile_read_misa__0_BIT_2_12_AND_IF_ne_ETC___d449 ;
  assign IF_csr_regfile_read_misa__0_BIT_2_12_AND_IF_ne_ETC___d452 =
	     (csr_regfile$read_misa[2] && instr__h4278[1:0] == 2'b01 &&
	      instr__h4278[15:13] == 3'b111) ?
	       instr__h8412 :
	       ((csr_regfile$read_misa[2] && instr__h4278[1:0] == 2'b01 &&
		 instr__h4278[15:13] == 3'b010 &&
		 instr__h4278[11:7] != 5'd0) ?
		  instr__h8750 :
		  IF_csr_regfile_read_misa__0_BIT_2_12_AND_IF_ne_ETC___d450) ;
  assign IF_csr_regfile_read_misa__0_BIT_2_12_AND_IF_ne_ETC___d453 =
	     (csr_regfile$read_misa[2] && instr__h4278[1:0] == 2'b01 &&
	      instr__h4278[15:13] == 3'b110) ?
	       instr__h8095 :
	       IF_csr_regfile_read_misa__0_BIT_2_12_AND_IF_ne_ETC___d452 ;
  assign IF_csr_regfile_read_misa__0_BIT_2_12_AND_IF_ne_ETC___d454 =
	     (csr_regfile_read_misa__0_BIT_2_12_AND_IF_near__ETC___d308 &&
	      instr__h4278[6:2] == 5'd0) ?
	       instr__h8030 :
	       IF_csr_regfile_read_misa__0_BIT_2_12_AND_IF_ne_ETC___d453 ;
  assign IF_csr_regfile_read_misa__0_BIT_2_12_AND_IF_ne_ETC___d455 =
	     (csr_regfile_read_misa__0_BIT_2_12_AND_IF_near__ETC___d302 &&
	      instr__h4278[6:2] == 5'd0) ?
	       instr__h7914 :
	       IF_csr_regfile_read_misa__0_BIT_2_12_AND_IF_ne_ETC___d454 ;
  assign IF_csr_regfile_read_misa__0_BIT_2_12_AND_IF_ne_ETC___d456 =
	     (csr_regfile$read_misa[2] && instr__h4278[1:0] == 2'b01 &&
	      instr__h4278[15:13] == 3'b001) ?
	       instr__h7524 :
	       IF_csr_regfile_read_misa__0_BIT_2_12_AND_IF_ne_ETC___d455 ;
  assign IF_csr_regfile_read_misa__0_BIT_2_12_AND_IF_ne_ETC___d457 =
	     (csr_regfile$read_misa[2] && instr__h4278[1:0] == 2'b01 &&
	      instr__h4278[15:13] == 3'b101) ?
	       instr__h7181 :
	       IF_csr_regfile_read_misa__0_BIT_2_12_AND_IF_ne_ETC___d456 ;
  assign IF_csr_regfile_read_misa__0_BIT_2_12_AND_IF_ne_ETC___d458 =
	     (csr_regfile$read_misa[2] && instr__h4278[1:0] == 2'b0 &&
	      instr__h4278[15:13] == 3'b110) ?
	       instr__h6952 :
	       IF_csr_regfile_read_misa__0_BIT_2_12_AND_IF_ne_ETC___d457 ;
  assign IF_csr_regfile_read_misa__0_BIT_2_12_AND_IF_ne_ETC___d459 =
	     (csr_regfile$read_misa[2] && instr__h4278[1:0] == 2'b0 &&
	      instr__h4278[15:13] == 3'b010) ?
	       instr__h6757 :
	       IF_csr_regfile_read_misa__0_BIT_2_12_AND_IF_ne_ETC___d458 ;
  assign IF_csr_regfile_read_misa__0_BIT_2_12_AND_IF_ne_ETC___d460 =
	     (csr_regfile$read_misa[2] && instr__h4278[1:0] == 2'b10 &&
	      instr__h4278[15:13] == 3'b110) ?
	       instr__h6565 :
	       IF_csr_regfile_read_misa__0_BIT_2_12_AND_IF_ne_ETC___d459 ;
  assign IF_near_mem_dmem_valid__09_THEN_IF_near_mem_dm_ETC___d112 =
	     near_mem$dmem_valid ? (near_mem$dmem_exc ? 2'd3 : 2'd2) : 2'd1 ;
  assign IF_rg_cur_priv_3_EQ_0b11_04_OR_rg_cur_priv_3_E_ETC___d723 =
	     ((rg_cur_priv == 2'b11 ||
	       rg_cur_priv == 2'b01 && !csr_regfile$read_mstatus[22]) &&
	      _theResult____h4280[31:20] == 12'b000100000010) ?
	       4'd8 :
	       (rg_cur_priv_3_EQ_0b11_04_OR_rg_cur_priv_3_EQ_0_ETC___d721 ?
		  4'd10 :
		  4'd11) ;
  assign IF_stage2_rg_full_7_THEN_IF_stage2_rg_stage2_8_ETC___d118 =
	     stage2_rg_full ?
	       CASE_stage2_rg_stage2_BITS_103_TO_101_0_2_1_IF_ETC__q1 :
	       2'd0 ;
  assign IF_stage2_rg_full_7_THEN_IF_stage2_rg_stage2_8_ETC___d180 =
	     stage2_rg_full ?
	       CASE_stage2_rg_stage2_BITS_103_TO_101_0_2_1_IF_ETC__q2 :
	       2'd0 ;
  assign IF_stage2_rg_full_7_THEN_IF_stage2_rg_stage2_8_ETC___d464 =
	     x_out_bypass_rd__h5992 == _theResult____h4280[19:15] ;
  assign IF_stage2_rg_full_7_THEN_IF_stage2_rg_stage2_8_ETC___d466 =
	     x_out_bypass_rd__h5992 == _theResult____h4280[24:20] ;
  assign IF_stage2_rg_stage2_8_BITS_100_TO_96_48_EQ_0_7_ETC___d175 =
	     (stage2_rg_stage2[100:96] == 5'd0) ?
	       2'd0 :
	       ((near_mem$dmem_valid && !near_mem$dmem_exc) ? 2'd2 : 2'd1) ;
  assign IF_stage2_rg_stage2_8_BITS_103_TO_101_9_EQ_3_5_ETC___d115 =
	     stage2_mbox$valid ? 2'd2 : 2'd1 ;
  assign NOT_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS_ETC___d564 =
	     (_theResult____h4280[14:12] != 3'b0 ||
	      _theResult____h4280[6:0] == 7'b0110011 &&
	      _theResult____h4280[30]) &&
	     (_theResult____h4280[14:12] != 3'b0 ||
	      _theResult____h4280[6:0] != 7'b0110011 ||
	      !_theResult____h4280[30]) &&
	     _theResult____h4280[14:12] != 3'b010 &&
	     _theResult____h4280[14:12] != 3'b011 &&
	     _theResult____h4280[14:12] != 3'b100 &&
	     _theResult____h4280[14:12] != 3'b110 &&
	     _theResult____h4280[14:12] != 3'b111 ;
  assign NOT_IF_csr_regfile_read_csr_minstret__5_ULT_cf_ETC___d41 =
	     cur_verbosity__h2985 > 4'd1 ;
  assign NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d1112 =
	     !csr_regfile$interrupt_pending[4] && !csr_regfile$nmi_pending ||
	     (!stage1_rg_full ||
	      NOT_near_mem_imem_valid_96_OR_NOT_near_mem_ime_ETC___d1109) &&
	     (!stage1_rg_full ||
	      NOT_near_mem_imem_valid_96_OR_NOT_near_mem_ime_ETC___d1101) ;
  assign NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d1130 =
	     !csr_regfile$interrupt_pending[4] && !csr_regfile$nmi_pending ||
	     near_mem$imem_exc ||
	     IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d622 &&
	     IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d633 ;
  assign NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d1133 =
	     NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d1130 &&
	     (IF_stage2_rg_full_7_THEN_IF_stage2_rg_stage2_8_ETC___d118 ==
	      2'd2 ||
	      IF_stage2_rg_full_7_THEN_IF_stage2_rg_stage2_8_ETC___d118 ==
	      2'd0) &&
	     stage1_rg_full &&
	     near_mem_imem_valid_AND_near_mem_imem_pc_EQ_im_ETC___d685 ;
  assign NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d1154 =
	     NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d1130 &&
	     (IF_stage2_rg_full_7_THEN_IF_stage2_rg_stage2_8_ETC___d118 ==
	      2'd2 ||
	      IF_stage2_rg_full_7_THEN_IF_stage2_rg_stage2_8_ETC___d118 ==
	      2'd0) &&
	     near_mem_imem_valid_AND_near_mem_imem_pc_EQ_im_ETC___d685 ||
	     !stage1_rg_full ;
  assign NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d1163 =
	     (!csr_regfile$interrupt_pending[4] && !csr_regfile$nmi_pending ||
	      _0_OR_0_OR_near_mem_imem_exc__85_OR_IF_IF_NOT_n_ETC___d1161) &&
	     stage1_rg_full &&
	     near_mem_imem_valid_AND_near_mem_imem_pc_EQ_im_ETC___d685 ;
  assign NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d1165 =
	     (!csr_regfile$interrupt_pending[4] && !csr_regfile$nmi_pending ||
	      _0_OR_0_OR_near_mem_imem_exc__85_OR_IF_IF_NOT_n_ETC___d1161) &&
	     (IF_stage2_rg_full_7_THEN_IF_stage2_rg_stage2_8_ETC___d118 ==
	      2'd2 ||
	      IF_stage2_rg_full_7_THEN_IF_stage2_rg_stage2_8_ETC___d118 ==
	      2'd0) ;
  assign NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d1168 =
	     NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d1112 &&
	     (NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d1165 &&
	      near_mem_imem_valid_AND_near_mem_imem_pc_EQ_im_ETC___d685 ||
	      !stage1_rg_full) ;
  assign NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d1182 =
	     !csr_regfile$interrupt_pending[4] && !csr_regfile$nmi_pending ||
	     !near_mem$imem_exc &&
	     (IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d680 ||
	      IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d682) ;
  assign NOT_near_mem_imem_exc__85_38_AND_IF_IF_NOT_nea_ETC___d812 =
	     !near_mem$imem_exc &&
	     (IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d680 ||
	      IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d682) &&
	     IF_NOT_stage1_rg_full_94_95_OR_NOT_near_mem_im_ETC___d746 !=
	     4'd0 &&
	     IF_NOT_stage1_rg_full_94_95_OR_NOT_near_mem_im_ETC___d746 !=
	     4'd1 &&
	     IF_NOT_stage1_rg_full_94_95_OR_NOT_near_mem_im_ETC___d746 !=
	     4'd2 &&
	     IF_NOT_stage1_rg_full_94_95_OR_NOT_near_mem_im_ETC___d746 !=
	     4'd3 &&
	     IF_NOT_stage1_rg_full_94_95_OR_NOT_near_mem_im_ETC___d746 !=
	     4'd4 &&
	     IF_NOT_stage1_rg_full_94_95_OR_NOT_near_mem_im_ETC___d746 !=
	     4'd5 &&
	     IF_NOT_stage1_rg_full_94_95_OR_NOT_near_mem_im_ETC___d746 !=
	     4'd6 &&
	     IF_NOT_stage1_rg_full_94_95_OR_NOT_near_mem_im_ETC___d746 !=
	     4'd7 &&
	     IF_NOT_stage1_rg_full_94_95_OR_NOT_near_mem_im_ETC___d746 !=
	     4'd8 &&
	     IF_NOT_stage1_rg_full_94_95_OR_NOT_near_mem_im_ETC___d746 !=
	     4'd9 &&
	     IF_NOT_stage1_rg_full_94_95_OR_NOT_near_mem_im_ETC___d746 !=
	     4'd10 ;
  assign NOT_near_mem_imem_exc__85_38_AND_IF_IF_NOT_nea_ETC___d849 =
	     !near_mem$imem_exc &&
	     (IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d680 ||
	      IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d682) &&
	     IF_NOT_stage1_rg_full_94_95_OR_NOT_near_mem_im_ETC___d825 !=
	     3'd0 &&
	     IF_NOT_stage1_rg_full_94_95_OR_NOT_near_mem_im_ETC___d825 !=
	     3'd1 &&
	     IF_NOT_stage1_rg_full_94_95_OR_NOT_near_mem_im_ETC___d825 !=
	     3'd2 &&
	     IF_NOT_stage1_rg_full_94_95_OR_NOT_near_mem_im_ETC___d825 !=
	     3'd3 ;
  assign NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS_2_9_97_ETC___d205 =
	     !near_mem_imem_pc_EQ_imem_rg_pc_PLUS_2_9___d197 &&
	     (!near_mem_imem_pc_BITS_31_TO_2_EQ_imem_rg_pc_BI_ETC___d8 ||
	      imem_rg_pc[1:0] != 2'b0 ||
	      near_mem$imem_instr[1:0] != 2'b11) ;
  assign NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS_2_9_97_ETC___d210 =
	     NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS_2_9_97_ETC___d205 &&
	     (!near_mem_imem_pc_BITS_31_TO_2_EQ_imem_rg_pc_BI_ETC___d8 ||
	      imem_rg_pc[1:0] == 2'b0 ||
	      near_mem$imem_instr[17:16] == 2'b11) &&
	     (!near_mem_imem_pc_BITS_31_TO_2_EQ_imem_rg_pc_BI_ETC___d8 ||
	      imem_rg_pc[1:0] != 2'b0 ||
	      near_mem$imem_instr[1:0] == 2'b11) ;
  assign NOT_near_mem_imem_valid_96_OR_NOT_near_mem_ime_ETC___d1090 =
	     !near_mem$imem_valid ||
	     !near_mem_imem_pc_EQ_imem_rg_pc_PLUS_2_9___d197 ||
	     IF_stage2_rg_full_7_THEN_IF_stage2_rg_stage2_8_ETC___d180 ==
	     2'd1 &&
	     (IF_stage2_rg_full_7_THEN_IF_stage2_rg_stage2_8_ETC___d464 ||
	      IF_stage2_rg_full_7_THEN_IF_stage2_rg_stage2_8_ETC___d466) ;
  assign NOT_near_mem_imem_valid_96_OR_NOT_near_mem_ime_ETC___d1101 =
	     NOT_near_mem_imem_valid_96_OR_NOT_near_mem_ime_ETC___d469 ||
	     !near_mem$imem_exc &&
	     (IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d680 ||
	      IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d682) ;
  assign NOT_near_mem_imem_valid_96_OR_NOT_near_mem_ime_ETC___d1109 =
	     NOT_near_mem_imem_valid_96_OR_NOT_near_mem_ime_ETC___d469 ||
	     near_mem$imem_exc ||
	     IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d622 &&
	     IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d633 ;
  assign NOT_near_mem_imem_valid_96_OR_NOT_near_mem_ime_ETC___d469 =
	     !near_mem$imem_valid ||
	     NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS_2_9_97_ETC___d210 ||
	     IF_stage2_rg_full_7_THEN_IF_stage2_rg_stage2_8_ETC___d180 ==
	     2'd1 &&
	     (IF_stage2_rg_full_7_THEN_IF_stage2_rg_stage2_8_ETC___d464 ||
	      IF_stage2_rg_full_7_THEN_IF_stage2_rg_stage2_8_ETC___d466) ;
  assign SEXT_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLU_ETC___d878 =
	     { {20{theResult__280_BITS_31_TO_20__q17[11]}},
	       theResult__280_BITS_31_TO_20__q17 } ;
  assign SEXT_IF_near_mem_imem_pc_EQ_imem_rg_pc_PLUS_2__ETC___d288 =
	     { {9{offset__h7128[11]}}, offset__h7128 } ;
  assign SEXT_IF_near_mem_imem_pc_EQ_imem_rg_pc_PLUS_2__ETC___d317 =
	     { {4{offset__h8039[8]}}, offset__h8039 } ;
  assign _0_OR_0_OR_near_mem_imem_exc__85_OR_IF_IF_NOT_n_ETC___d1161 =
	     near_mem$imem_exc ||
	     IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d622 &&
	     IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d633 ;
  assign _theResult_____1_fst__h12718 =
	     (_theResult____h4280[14:12] == 3'b0 &&
	      _theResult____h4280[6:0] == 7'b0110011 &&
	      _theResult____h4280[30]) ?
	       rd_val___1__h12714 :
	       _theResult_____1_fst__h12725 ;
  assign _theResult_____1_fst__h12753 =
	     rs1_val_bypassed__h4288 & _theResult___snd__h13851 ;
  assign _theResult____h22285 =
	     (delta_CPI_instrs__h22284 == 64'd0) ?
	       delta_CPI_instrs___1__h22320 :
	       delta_CPI_instrs__h22284 ;
  assign _theResult____h4280 = x_out_data_to_stage2_instr__h11612 ;
  assign _theResult___fst__h6320 =
	     (near_mem_imem_pc_BITS_31_TO_2_EQ_imem_rg_pc_BI_ETC___d8 &&
	      imem_rg_pc[1:0] == 2'b0 &&
	      near_mem$imem_instr[1:0] != 2'b11) ?
	       instr_out___1__h6322 :
	       _theResult___fst__h6348 ;
  assign _theResult___fst__h6348 =
	     (near_mem_imem_pc_BITS_31_TO_2_EQ_imem_rg_pc_BI_ETC___d8 &&
	      imem_rg_pc[1:0] != 2'b0 &&
	      near_mem$imem_instr[17:16] != 2'b11) ?
	       instr_out___1__h6350 :
	       near_mem$imem_instr ;
  assign _theResult___snd__h13851 =
	     (_theResult____h4280[6:0] == 7'b0010011) ?
	       SEXT_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLU_ETC___d878 :
	       rs2_val__h11713 ;
  assign alu_outputs___1_addr__h11739 =
	     IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d534 ?
	       branch_target__h11717 :
	       IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS_2_9_ETC___d869 ;
  assign alu_outputs___1_addr__h11760 =
	     imem_rg_pc +
	     { {11{theResult__280_BIT_31_CONCAT_theResult__280_BI_ETC__q4[20]}},
	       theResult__280_BIT_31_CONCAT_theResult__280_BI_ETC__q4 } ;
  assign alu_outputs___1_addr__h11786 =
	     { alu_outputs___1_addr__h11981[31:1], 1'd0 } ;
  assign alu_outputs___1_addr__h11981 =
	     rs1_val_bypassed__h4288 +
	     SEXT_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLU_ETC___d878 ;
  assign alu_outputs___1_addr__h12002 =
	     rs1_val_bypassed__h4288 +
	     { {20{theResult__280_BITS_31_TO_25_CONCAT_theResult__ETC__q7[11]}},
	       theResult__280_BITS_31_TO_25_CONCAT_theResult__ETC__q7 } ;
  assign alu_outputs___1_exc_code__h12238 =
	     (_theResult____h4280[14:12] == 3'b0) ?
	       ((_theResult____h4280[11:7] == 5'd0 &&
		 _theResult____h4280[19:15] == 5'd0) ?
		  CASE_theResult__280_BITS_31_TO_20_0b0_CASE_rg__ETC__q6 :
		  4'd2) :
	       4'd2 ;
  assign alu_outputs___1_val1__h11890 =
	     (_theResult____h4280[14:12] == 3'b001) ?
	       rd_val__h13747 :
	       (_theResult____h4280[30] ? rd_val__h13821 : rd_val__h13799) ;
  assign alu_outputs___1_val1__h11928 =
	     (_theResult____h4280[14:12] == 3'b0 &&
	      (_theResult____h4280[6:0] != 7'b0110011 ||
	       !_theResult____h4280[30])) ?
	       rd_val___1__h12706 :
	       _theResult_____1_fst__h12718 ;
  assign alu_outputs___1_val1__h11944 =
	     { _theResult____h4280[31:12], 12'h0 } ;
  assign alu_outputs___1_val1__h11960 =
	     imem_rg_pc + alu_outputs___1_val1__h11944 ;
  assign alu_outputs___1_val1__h12242 =
	     _theResult____h4280[14] ?
	       { 27'd0, _theResult____h4280[19:15] } :
	       rs1_val_bypassed__h4288 ;
  assign alu_outputs___1_val1__h12263 =
	     { 25'd0, _theResult____h4280[31:25] } ;
  assign branch_target__h11717 =
	     imem_rg_pc +
	     { {19{theResult__280_BIT_31_CONCAT_theResult__280_BI_ETC__q3[12]}},
	       theResult__280_BIT_31_CONCAT_theResult__280_BI_ETC__q3 } ;
  assign cpi__h22287 = x__h22286 / 64'd10 ;
  assign cpifrac__h22288 = x__h22286 % 64'd10 ;
  assign csr_regfile_interrupt_pending_rg_cur_priv_3_07_ETC___d1083 =
	     (csr_regfile$interrupt_pending[4] || csr_regfile$nmi_pending) &&
	     stage1_rg_full &&
	     near_mem_imem_valid_AND_near_mem_imem_pc_EQ_im_ETC___d1079 &&
	     IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d1080 ;
  assign csr_regfile_interrupt_pending_rg_cur_priv_3_07_ETC___d1088 =
	     (csr_regfile$interrupt_pending[4] || csr_regfile$nmi_pending) &&
	     (IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d680 ||
	      IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d682) ||
	     IF_stage2_rg_full_7_THEN_IF_stage2_rg_stage2_8_ETC___d118 !=
	     2'd2 &&
	     IF_stage2_rg_full_7_THEN_IF_stage2_rg_stage2_8_ETC___d118 !=
	     2'd0 ;
  assign csr_regfile_interrupt_pending_rg_cur_priv_3_07_ETC___d1094 =
	     csr_regfile_interrupt_pending_rg_cur_priv_3_07_ETC___d1083 ||
	     (csr_regfile_interrupt_pending_rg_cur_priv_3_07_ETC___d1088 ||
	      NOT_near_mem_imem_valid_96_OR_NOT_near_mem_ime_ETC___d1090 ||
	      near_mem$imem_exc ||
	      IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d622 &&
	      IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d633) &&
	     stage1_rg_full ;
  assign csr_regfile_read_csr_mcycle__2_MINUS_rg_start__ETC___d1273 =
	     delta_CPI_cycles__h22283 * 64'd10 ;
  assign csr_regfile_read_misa__0_BIT_2_12_AND_IF_near__ETC___d302 =
	     csr_regfile$read_misa[2] && instr__h4278[1:0] == 2'b10 &&
	     instr__h4278[15:12] == 4'b1000 &&
	     instr__h4278[11:7] != 5'd0 ;
  assign csr_regfile_read_misa__0_BIT_2_12_AND_IF_near__ETC___d308 =
	     csr_regfile$read_misa[2] && instr__h4278[1:0] == 2'b10 &&
	     instr__h4278[15:12] == 4'b1001 &&
	     instr__h4278[11:7] != 5'd0 ;
  assign cur_verbosity__h2985 =
	     (csr_regfile$read_csr_minstret < cfg_logdelay) ?
	       4'd0 :
	       cfg_verbosity ;
  assign data_to_stage2_addr__h11607 = x_out_data_to_stage2_addr__h11615 ;
  assign delta_CPI_cycles__h22283 =
	     csr_regfile$read_csr_mcycle - rg_start_CPI_cycles ;
  assign delta_CPI_instrs___1__h22320 = delta_CPI_instrs__h22284 + 64'd1 ;
  assign delta_CPI_instrs__h22284 =
	     csr_regfile$read_csr_minstret - rg_start_CPI_instrs ;
  assign fall_through_pc__h11571 =
	     imem_rg_pc +
	     (near_mem_imem_pc_EQ_imem_rg_pc_PLUS_2_9_97_OR__ETC___d476 ?
		32'd4 :
		32'd2) ;
  assign gpr_regfile_RDY_server_reset_request_put__031__ETC___d1043 =
	     gpr_regfile$RDY_server_reset_request_put &&
	     near_mem$RDY_server_reset_request_put &&
	     csr_regfile$RDY_server_reset_request_put &&
	     f_reset_reqs$EMPTY_N &&
	     stage1_f_reset_reqs$FULL_N &&
	     stage2_f_reset_reqs$FULL_N &&
	     stage3_f_reset_reqs$FULL_N ;
  assign imm12__h10054 = { 7'b0100000, instr__h4278[6:2] } ;
  assign imm12__h6421 = { 4'd0, offset__h6191 } ;
  assign imm12__h6758 = { 5'd0, offset__h6700 } ;
  assign imm12__h8674 = { {6{imm6__h8672[5]}}, imm6__h8672 } ;
  assign imm12__h9298 = { {2{nzimm10__h9296[9]}}, nzimm10__h9296 } ;
  assign imm12__h9513 = { 2'd0, nzimm10__h9511 } ;
  assign imm12__h9709 = { 7'b0, instr__h4278[6:2] } ;
  assign imm20__h8802 = { {14{imm6__h8672[5]}}, imm6__h8672 } ;
  assign imm6__h8672 = { instr__h4278[12], instr__h4278[6:2] } ;
  assign instr___1__h6153 =
	     (csr_regfile$read_misa[2] && instr__h4278[1:0] == 2'b10 &&
	      instr__h4278[11:7] != 5'd0 &&
	      instr__h4278[15:13] == 3'b010) ?
	       instr__h6420 :
	       IF_csr_regfile_read_misa__0_BIT_2_12_AND_IF_ne_ETC___d460 ;
  assign instr__h10038 =
	     { imm12__h9709, rs1__h6759, 3'b101, rs1__h6759, 7'b0010011 } ;
  assign instr__h10231 =
	     { imm12__h10054, rs1__h6759, 3'b101, rs1__h6759, 7'b0010011 } ;
  assign instr__h10348 =
	     { imm12__h8674, rs1__h6759, 3'b111, rs1__h6759, 7'b0010011 } ;
  assign instr__h10526 =
	     { 7'b0,
	       instr__h4278[6:2],
	       8'd0,
	       instr__h4278[11:7],
	       7'b0110011 } ;
  assign instr__h10645 =
	     { 7'b0,
	       instr__h4278[6:2],
	       instr__h4278[11:7],
	       3'b0,
	       instr__h4278[11:7],
	       7'b0110011 } ;
  assign instr__h10740 =
	     { 7'b0, rd__h6760, rs1__h6759, 3'b111, rs1__h6759, 7'b0110011 } ;
  assign instr__h10876 =
	     { 7'b0, rd__h6760, rs1__h6759, 3'b110, rs1__h6759, 7'b0110011 } ;
  assign instr__h11012 =
	     { 7'b0, rd__h6760, rs1__h6759, 3'b100, rs1__h6759, 7'b0110011 } ;
  assign instr__h11148 =
	     { 7'b0100000,
	       rd__h6760,
	       rs1__h6759,
	       3'b0,
	       rs1__h6759,
	       7'b0110011 } ;
  assign instr__h11486 =
	     { 12'b000000000001,
	       instr__h4278[11:7],
	       3'b0,
	       instr__h4278[11:7],
	       7'b1110011 } ;
  assign instr__h4278 =
	     near_mem_imem_pc_EQ_imem_rg_pc_PLUS_2_9___d197 ?
	       instr_out___1__h6290 :
	       _theResult___fst__h6320 ;
  assign instr__h6420 =
	     { imm12__h6421, 8'd18, instr__h4278[11:7], 7'b0000011 } ;
  assign instr__h6565 =
	     { 4'd0,
	       instr__h4278[8:7],
	       instr__h4278[12],
	       instr__h4278[6:2],
	       8'd18,
	       offset_BITS_4_TO_0___h6689,
	       7'b0100011 } ;
  assign instr__h6757 =
	     { imm12__h6758, rs1__h6759, 3'b010, rd__h6760, 7'b0000011 } ;
  assign instr__h6952 =
	     { 5'd0,
	       instr__h4278[5],
	       instr__h4278[12],
	       rd__h6760,
	       rs1__h6759,
	       3'b010,
	       offset_BITS_4_TO_0___h7120,
	       7'b0100011 } ;
  assign instr__h7181 =
	     { SEXT_IF_near_mem_imem_pc_EQ_imem_rg_pc_PLUS_2__ETC___d288[20],
	       SEXT_IF_near_mem_imem_pc_EQ_imem_rg_pc_PLUS_2__ETC___d288[10:1],
	       SEXT_IF_near_mem_imem_pc_EQ_imem_rg_pc_PLUS_2__ETC___d288[11],
	       SEXT_IF_near_mem_imem_pc_EQ_imem_rg_pc_PLUS_2__ETC___d288[19:12],
	       12'd111 } ;
  assign instr__h7524 =
	     { SEXT_IF_near_mem_imem_pc_EQ_imem_rg_pc_PLUS_2__ETC___d288[20],
	       SEXT_IF_near_mem_imem_pc_EQ_imem_rg_pc_PLUS_2__ETC___d288[10:1],
	       SEXT_IF_near_mem_imem_pc_EQ_imem_rg_pc_PLUS_2__ETC___d288[11],
	       SEXT_IF_near_mem_imem_pc_EQ_imem_rg_pc_PLUS_2__ETC___d288[19:12],
	       12'd239 } ;
  assign instr__h7914 = { 12'd0, instr__h4278[11:7], 15'd103 } ;
  assign instr__h8030 = { 12'd0, instr__h4278[11:7], 15'd231 } ;
  assign instr__h8095 =
	     { SEXT_IF_near_mem_imem_pc_EQ_imem_rg_pc_PLUS_2__ETC___d317[12],
	       SEXT_IF_near_mem_imem_pc_EQ_imem_rg_pc_PLUS_2__ETC___d317[10:5],
	       5'd0,
	       rs1__h6759,
	       3'b0,
	       SEXT_IF_near_mem_imem_pc_EQ_imem_rg_pc_PLUS_2__ETC___d317[4:1],
	       SEXT_IF_near_mem_imem_pc_EQ_imem_rg_pc_PLUS_2__ETC___d317[11],
	       7'b1100011 } ;
  assign instr__h8412 =
	     { SEXT_IF_near_mem_imem_pc_EQ_imem_rg_pc_PLUS_2__ETC___d317[12],
	       SEXT_IF_near_mem_imem_pc_EQ_imem_rg_pc_PLUS_2__ETC___d317[10:5],
	       5'd0,
	       rs1__h6759,
	       3'b001,
	       SEXT_IF_near_mem_imem_pc_EQ_imem_rg_pc_PLUS_2__ETC___d317[4:1],
	       SEXT_IF_near_mem_imem_pc_EQ_imem_rg_pc_PLUS_2__ETC___d317[11],
	       7'b1100011 } ;
  assign instr__h8750 =
	     { imm12__h8674, 8'd0, instr__h4278[11:7], 7'b0010011 } ;
  assign instr__h8934 = { imm20__h8802, instr__h4278[11:7], 7'b0110111 } ;
  assign instr__h9063 =
	     { imm12__h8674,
	       instr__h4278[11:7],
	       3'b0,
	       instr__h4278[11:7],
	       7'b0010011 } ;
  assign instr__h9500 =
	     { imm12__h9298,
	       instr__h4278[11:7],
	       3'b0,
	       instr__h4278[11:7],
	       7'b0010011 } ;
  assign instr__h9672 = { imm12__h9513, 8'd16, rd__h6760, 7'b0010011 } ;
  assign instr__h9845 =
	     { imm12__h9709,
	       instr__h4278[11:7],
	       3'b001,
	       instr__h4278[11:7],
	       7'b0010011 } ;
  assign instr_out___1__h6290 =
	     { near_mem$imem_instr[15:0], imem_rg_instr_15_0 } ;
  assign instr_out___1__h6322 = { 16'b0, near_mem$imem_instr[15:0] } ;
  assign instr_out___1__h6350 = { 16'b0, near_mem$imem_instr[31:16] } ;
  assign near_mem_imem_exc__85_OR_IF_IF_NOT_near_mem_im_ETC___d949 =
	     (near_mem$imem_exc ||
	      IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d622 &&
	      IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d633) &&
	     IF_NOT_stage1_rg_full_94_95_OR_NOT_near_mem_im_ETC___d746 ==
	     4'd0 ;
  assign near_mem_imem_exc__85_OR_IF_IF_NOT_near_mem_im_ETC___d952 =
	     (near_mem$imem_exc ||
	      IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d622 &&
	      IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d633) &&
	     IF_NOT_stage1_rg_full_94_95_OR_NOT_near_mem_im_ETC___d746 ==
	     4'd1 ;
  assign near_mem_imem_exc__85_OR_IF_IF_NOT_near_mem_im_ETC___d955 =
	     (near_mem$imem_exc ||
	      IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d622 &&
	      IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d633) &&
	     IF_NOT_stage1_rg_full_94_95_OR_NOT_near_mem_im_ETC___d746 ==
	     4'd2 ;
  assign near_mem_imem_exc__85_OR_IF_IF_NOT_near_mem_im_ETC___d958 =
	     (near_mem$imem_exc ||
	      IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d622 &&
	      IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d633) &&
	     IF_NOT_stage1_rg_full_94_95_OR_NOT_near_mem_im_ETC___d746 ==
	     4'd3 ;
  assign near_mem_imem_exc__85_OR_IF_IF_NOT_near_mem_im_ETC___d961 =
	     (near_mem$imem_exc ||
	      IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d622 &&
	      IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d633) &&
	     IF_NOT_stage1_rg_full_94_95_OR_NOT_near_mem_im_ETC___d746 ==
	     4'd4 ;
  assign near_mem_imem_exc__85_OR_IF_IF_NOT_near_mem_im_ETC___d964 =
	     (near_mem$imem_exc ||
	      IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d622 &&
	      IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d633) &&
	     IF_NOT_stage1_rg_full_94_95_OR_NOT_near_mem_im_ETC___d746 ==
	     4'd5 ;
  assign near_mem_imem_exc__85_OR_IF_IF_NOT_near_mem_im_ETC___d967 =
	     (near_mem$imem_exc ||
	      IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d622 &&
	      IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d633) &&
	     IF_NOT_stage1_rg_full_94_95_OR_NOT_near_mem_im_ETC___d746 ==
	     4'd6 ;
  assign near_mem_imem_exc__85_OR_IF_IF_NOT_near_mem_im_ETC___d970 =
	     (near_mem$imem_exc ||
	      IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d622 &&
	      IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d633) &&
	     IF_NOT_stage1_rg_full_94_95_OR_NOT_near_mem_im_ETC___d746 ==
	     4'd7 ;
  assign near_mem_imem_exc__85_OR_IF_IF_NOT_near_mem_im_ETC___d973 =
	     (near_mem$imem_exc ||
	      IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d622 &&
	      IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d633) &&
	     IF_NOT_stage1_rg_full_94_95_OR_NOT_near_mem_im_ETC___d746 ==
	     4'd8 ;
  assign near_mem_imem_exc__85_OR_IF_IF_NOT_near_mem_im_ETC___d976 =
	     (near_mem$imem_exc ||
	      IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d622 &&
	      IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d633) &&
	     IF_NOT_stage1_rg_full_94_95_OR_NOT_near_mem_im_ETC___d746 ==
	     4'd9 ;
  assign near_mem_imem_exc__85_OR_IF_IF_NOT_near_mem_im_ETC___d979 =
	     (near_mem$imem_exc ||
	      IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d622 &&
	      IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d633) &&
	     IF_NOT_stage1_rg_full_94_95_OR_NOT_near_mem_im_ETC___d746 ==
	     4'd10 ;
  assign near_mem_imem_exc__85_OR_IF_IF_NOT_near_mem_im_ETC___d982 =
	     (near_mem$imem_exc ||
	      IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d622 &&
	      IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d633) &&
	     IF_NOT_stage1_rg_full_94_95_OR_NOT_near_mem_im_ETC___d746 !=
	     4'd0 &&
	     IF_NOT_stage1_rg_full_94_95_OR_NOT_near_mem_im_ETC___d746 !=
	     4'd1 &&
	     IF_NOT_stage1_rg_full_94_95_OR_NOT_near_mem_im_ETC___d746 !=
	     4'd2 &&
	     IF_NOT_stage1_rg_full_94_95_OR_NOT_near_mem_im_ETC___d746 !=
	     4'd3 &&
	     IF_NOT_stage1_rg_full_94_95_OR_NOT_near_mem_im_ETC___d746 !=
	     4'd4 &&
	     IF_NOT_stage1_rg_full_94_95_OR_NOT_near_mem_im_ETC___d746 !=
	     4'd5 &&
	     IF_NOT_stage1_rg_full_94_95_OR_NOT_near_mem_im_ETC___d746 !=
	     4'd6 &&
	     IF_NOT_stage1_rg_full_94_95_OR_NOT_near_mem_im_ETC___d746 !=
	     4'd7 &&
	     IF_NOT_stage1_rg_full_94_95_OR_NOT_near_mem_im_ETC___d746 !=
	     4'd8 &&
	     IF_NOT_stage1_rg_full_94_95_OR_NOT_near_mem_im_ETC___d746 !=
	     4'd9 &&
	     IF_NOT_stage1_rg_full_94_95_OR_NOT_near_mem_im_ETC___d746 !=
	     4'd10 ;
  assign near_mem_imem_pc_BITS_31_TO_2_EQ_imem_rg_pc_BI_ETC___d8 =
	     near_mem$imem_pc[31:2] == imem_rg_pc[31:2] ;
  assign near_mem_imem_pc_EQ_imem_rg_pc_PLUS_2_9_97_OR__ETC___d476 =
	     near_mem_imem_pc_EQ_imem_rg_pc_PLUS_2_9___d197 ||
	     near_mem_imem_pc_BITS_31_TO_2_EQ_imem_rg_pc_BI_ETC___d8 &&
	     imem_rg_pc[1:0] == 2'b0 &&
	     near_mem$imem_instr[1:0] == 2'b11 ;
  assign near_mem_imem_pc_EQ_imem_rg_pc_PLUS_2_9_97_OR__ETC___d478 =
	     near_mem_imem_pc_EQ_imem_rg_pc_PLUS_2_9_97_OR__ETC___d476 ||
	     near_mem_imem_pc_BITS_31_TO_2_EQ_imem_rg_pc_BI_ETC___d8 &&
	     imem_rg_pc[1:0] != 2'b0 &&
	     near_mem$imem_instr[17:16] != 2'b11 ||
	     near_mem_imem_pc_BITS_31_TO_2_EQ_imem_rg_pc_BI_ETC___d8 &&
	     imem_rg_pc[1:0] == 2'b0 &&
	     near_mem$imem_instr[1:0] != 2'b11 ;
  assign near_mem_imem_pc_EQ_imem_rg_pc_PLUS_2_9___d197 =
	     near_mem$imem_pc == next_pc___1__h13393 ;
  assign near_mem_imem_valid_AND_near_mem_imem_pc_EQ_im_ETC___d1079 =
	     near_mem$imem_valid &&
	     near_mem_imem_pc_EQ_imem_rg_pc_PLUS_2_9___d197 &&
	     (IF_stage2_rg_full_7_THEN_IF_stage2_rg_stage2_8_ETC___d180 !=
	      2'd1 ||
	      !IF_stage2_rg_full_7_THEN_IF_stage2_rg_stage2_8_ETC___d464 &&
	      !IF_stage2_rg_full_7_THEN_IF_stage2_rg_stage2_8_ETC___d466) ;
  assign near_mem_imem_valid_AND_near_mem_imem_pc_EQ_im_ETC___d484 =
	     near_mem$imem_valid &&
	     near_mem_imem_pc_EQ_imem_rg_pc_PLUS_2_9_97_OR__ETC___d478 &&
	     (IF_stage2_rg_full_7_THEN_IF_stage2_rg_stage2_8_ETC___d180 !=
	      2'd1 ||
	      !IF_stage2_rg_full_7_THEN_IF_stage2_rg_stage2_8_ETC___d464 &&
	      !IF_stage2_rg_full_7_THEN_IF_stage2_rg_stage2_8_ETC___d466) ;
  assign near_mem_imem_valid_AND_near_mem_imem_pc_EQ_im_ETC___d636 =
	     near_mem_imem_valid_AND_near_mem_imem_pc_EQ_im_ETC___d484 &&
	     (near_mem$imem_exc ||
	      IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d622 &&
	      IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d633) ;
  assign near_mem_imem_valid_AND_near_mem_imem_pc_EQ_im_ETC___d685 =
	     near_mem_imem_valid_AND_near_mem_imem_pc_EQ_im_ETC___d484 &&
	     !near_mem$imem_exc &&
	     (IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d680 ||
	      IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d682) ;
  assign next_pc___1__h13393 = imem_rg_pc + 32'd2 ;
  assign next_pc__h13391 = imem_rg_pc + 32'd4 ;
  assign nzimm10__h9296 =
	     { instr__h4278[12],
	       instr__h4278[4:3],
	       instr__h4278[5],
	       instr__h4278[2],
	       instr__h4278[6],
	       4'b0 } ;
  assign nzimm10__h9511 =
	     { instr__h4278[10:7],
	       instr__h4278[12:11],
	       instr__h4278[5],
	       instr__h4278[6],
	       2'b0 } ;
  assign offset_BITS_4_TO_0___h6689 = { instr__h4278[11:9], 2'b0 } ;
  assign offset_BITS_4_TO_0___h7120 =
	     { instr__h4278[11:10], instr__h4278[6], 2'b0 } ;
  assign offset__h6191 =
	     { instr__h4278[3:2],
	       instr__h4278[12],
	       instr__h4278[6:4],
	       2'b0 } ;
  assign offset__h6700 =
	     { instr__h4278[5], instr__h4278[12:10], instr__h4278[6], 2'b0 } ;
  assign offset__h7128 =
	     { instr__h4278[12],
	       instr__h4278[8],
	       instr__h4278[10:9],
	       instr__h4278[6],
	       instr__h4278[7],
	       instr__h4278[2],
	       instr__h4278[11],
	       instr__h4278[5:3],
	       1'b0 } ;
  assign offset__h8039 =
	     { instr__h4278[12],
	       instr__h4278[6:5],
	       instr__h4278[2],
	       instr__h4278[11:10],
	       instr__h4278[4:3],
	       1'b0 } ;
  assign output_stage2___1_bypass_rd_val__h5981 =
	     (!near_mem$dmem_valid || !near_mem$dmem_exc) ?
	       ((stage2_rg_stage2[100:96] == 5'd0) ?
		  stage2_rg_stage2[63:32] :
		  near_mem$dmem_word64[31:0]) :
	       stage2_rg_stage2[63:32] ;
  assign rd__h6760 = { 2'b01, instr__h4278[4:2] } ;
  assign rd_val___1__h12706 =
	     rs1_val_bypassed__h4288 + _theResult___snd__h13851 ;
  assign rd_val___1__h12714 =
	     rs1_val_bypassed__h4288 - _theResult___snd__h13851 ;
  assign rd_val___1__h12721 =
	     ((rs1_val_bypassed__h4288 ^ 32'h80000000) <
	      (_theResult___snd__h13851 ^ 32'h80000000)) ?
	       32'd1 :
	       32'd0 ;
  assign rd_val___1__h12728 =
	     (rs1_val_bypassed__h4288 < _theResult___snd__h13851) ?
	       32'd1 :
	       32'd0 ;
  assign rd_val___1__h12735 =
	     rs1_val_bypassed__h4288 ^ _theResult___snd__h13851 ;
  assign rd_val___1__h12742 =
	     rs1_val_bypassed__h4288 | _theResult___snd__h13851 ;
  assign rd_val__h11528 =
	     (stage3_rg_full && stage3_rg_stage3[37] &&
	      stage3_rg_stage3[36:32] == _theResult____h4280[24:20]) ?
	       stage3_rg_stage3[31:0] :
	       gpr_regfile$read_rs2 ;
  assign rd_val__h13747 = rs1_val_bypassed__h4288 << shamt__h11875 ;
  assign rd_val__h13799 = rs1_val_bypassed__h4288 >> shamt__h11875 ;
  assign rd_val__h13821 =
	     rs1_val_bypassed__h4288 >> shamt__h11875 |
	     ~(32'hFFFFFFFF >> shamt__h11875) &
	     {32{rs1_val_bypassed__h4288[31]}} ;
  assign rd_val__h6105 =
	     (stage3_rg_full && stage3_rg_stage3[37] &&
	      stage3_rg_stage3[36:32] == _theResult____h4280[19:15]) ?
	       stage3_rg_stage3[31:0] :
	       gpr_regfile$read_rs1 ;
  assign rg_cur_priv_3_EQ_0b11_04_OR_rg_cur_priv_3_EQ_0_ETC___d721 =
	     (rg_cur_priv == 2'b11 ||
	      rg_cur_priv == 2'b01 && !csr_regfile$read_mstatus[21] ||
	      rg_cur_priv == 2'b0 && csr_regfile$read_misa[13]) &&
	     _theResult____h4280[31:20] == 12'b000100000101 ;
  assign rg_state_2_EQ_3_096_AND_NOT_csr_regfile_interr_ETC___d1185 =
	     rg_state == 4'd3 &&
	     NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d1182 &&
	     !stage3_rg_full &&
	     IF_stage2_rg_full_7_THEN_IF_stage2_rg_stage2_8_ETC___d118 ==
	     2'd0 ;
  assign rg_state_2_EQ_3_096_AND_stage3_rg_full_8_OR_NO_ETC___d1115 =
	     rg_state == 4'd3 &&
	     (stage3_rg_full ||
	      IF_stage2_rg_full_7_THEN_IF_stage2_rg_stage2_8_ETC___d118 !=
	      2'd0 ||
	      stage1_rg_full) &&
	     (stage3_rg_full ||
	      IF_stage2_rg_full_7_THEN_IF_stage2_rg_stage2_8_ETC___d118 !=
	      2'd3) &&
	     (stage3_rg_full ||
	      IF_stage2_rg_full_7_THEN_IF_stage2_rg_stage2_8_ETC___d118 !=
	      2'd0 ||
	      !stage1_rg_full ||
	      NOT_near_mem_imem_valid_96_OR_NOT_near_mem_ime_ETC___d1101) &&
	     (NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d1112 ||
	      IF_stage2_rg_full_7_THEN_IF_stage2_rg_stage2_8_ETC___d118 !=
	      2'd0 ||
	      stage3_rg_full) ;
  assign rs1__h6759 = { 2'b01, instr__h4278[9:7] } ;
  assign rs1_val__h17231 =
	     (x_out_data_to_stage2_instr__h11612[14:12] == 3'b001) ?
	       x_out_data_to_stage2_val1__h11616 :
	       { 27'd0, x_out_data_to_stage2_instr__h11612[19:15] } ;
  assign rs1_val_bypassed__h4288 =
	     (_theResult____h4280[19:15] == 5'd0) ? 32'd0 : val__h6107 ;
  assign rs2_val__h11713 =
	     (_theResult____h4280[24:20] == 5'd0) ? 32'd0 : val__h11530 ;
  assign shamt__h11875 =
	     (_theResult____h4280[6:0] == 7'b0010011) ?
	       _theResult____h4280[24:20] :
	       rs2_val__h11713[4:0] ;
  assign stage2_f_reset_rsps_i_notEmpty__052_AND_stage3_ETC___d1061 =
	     stage2_f_reset_rsps$EMPTY_N && stage3_f_reset_rsps$EMPTY_N &&
	     f_reset_rsps$FULL_N &&
	     (!rg_run_on_reset ||
	      !near_mem_imem_pc_BITS_31_TO_2_EQ_imem_rg_pc_BI_ETC___d8 ||
	      imem_rg_pc[1:0] == 2'b0 ||
	      near_mem$imem_instr[17:16] != 2'b11) ;
  assign theResult__280_BITS_31_TO_20__q17 = _theResult____h4280[31:20] ;
  assign theResult__280_BITS_31_TO_25_CONCAT_theResult__ETC__q7 =
	     { _theResult____h4280[31:25], _theResult____h4280[11:7] } ;
  assign theResult__280_BIT_31_CONCAT_theResult__280_BI_ETC__q3 =
	     { _theResult____h4280[31],
	       _theResult____h4280[7],
	       _theResult____h4280[30:25],
	       _theResult____h4280[11:8],
	       1'b0 } ;
  assign theResult__280_BIT_31_CONCAT_theResult__280_BI_ETC__q4 =
	     { _theResult____h4280[31],
	       _theResult____h4280[19:12],
	       _theResult____h4280[20],
	       _theResult____h4280[30:21],
	       1'b0 } ;
  assign trap_info_tval__h13230 =
	     (_theResult____h4280[6:0] != 7'b1101111 &&
	      _theResult____h4280[6:0] != 7'b1100111 &&
	      (_theResult____h4280[6:0] != 7'b1110011 ||
	       _theResult____h4280[14:12] != 3'b0 ||
	       _theResult____h4280[11:7] != 5'd0 ||
	       _theResult____h4280[19:15] != 5'd0 ||
	       _theResult____h4280[31:20] != 12'b0 &&
	       _theResult____h4280[31:20] != 12'b000000000001)) ?
	       (near_mem_imem_pc_EQ_imem_rg_pc_PLUS_2_9_97_OR__ETC___d476 ?
		  _theResult____h4280 :
		  { 16'd0, instr__h4278[15:0] }) :
	       IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d1021 ;
  assign val__h11530 =
	     (IF_stage2_rg_full_7_THEN_IF_stage2_rg_stage2_8_ETC___d180 ==
	      2'd2 &&
	      IF_stage2_rg_full_7_THEN_IF_stage2_rg_stage2_8_ETC___d466) ?
	       x_out_bypass_rd_val__h5993 :
	       rd_val__h11528 ;
  assign val__h6107 =
	     (IF_stage2_rg_full_7_THEN_IF_stage2_rg_stage2_8_ETC___d180 ==
	      2'd2 &&
	      IF_stage2_rg_full_7_THEN_IF_stage2_rg_stage2_8_ETC___d464) ?
	       x_out_bypass_rd_val__h5993 :
	       rd_val__h6105 ;
  assign value__h13281 =
	     near_mem$imem_exc ? imem_rg_tval : trap_info_tval__h13230 ;
  assign x__h22286 =
	     csr_regfile_read_csr_mcycle__2_MINUS_rg_start__ETC___d1273[63:0] /
	     _theResult____h22285 ;
  assign x_out_data_to_stage2_instr__h11612 =
	     NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS_2_9_97_ETC___d205 ?
	       instr___1__h6153 :
	       instr__h4278 ;
  assign x_out_data_to_stage2_rd__h11614 =
	     (_theResult____h4280[6:0] == 7'b1100011) ?
	       5'd0 :
	       _theResult____h4280[11:7] ;
  assign x_out_data_to_stage2_val2__h11617 =
	     (_theResult____h4280[6:0] == 7'b1100011) ?
	       branch_target__h11717 :
	       rs2_val__h11713 ;
  assign x_out_next_pc__h11584 =
	     IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d682 ?
	       data_to_stage2_addr__h11607 :
	       fall_through_pc__h11571 ;
  assign x_out_trap_info_exc_code__h13233 =
	     near_mem$imem_exc ?
	       near_mem$imem_exc_code :
	       alu_outputs_exc_code__h12281 ;
  assign y__h18022 = ~rs1_val__h17721 ;
  always@(stage2_rg_stage2)
  begin
    case (stage2_rg_stage2[103:101])
      3'd0, 3'd1, 3'd4:
	  x_out_data_to_stage3_rd__h5641 = stage2_rg_stage2[100:96];
      3'd2: x_out_data_to_stage3_rd__h5641 = 5'd0;
      default: x_out_data_to_stage3_rd__h5641 = stage2_rg_stage2[100:96];
    endcase
  end
  always@(stage2_rg_stage2 or stage2_mbox$word or near_mem$dmem_word64)
  begin
    case (stage2_rg_stage2[103:101])
      3'd0: x_out_data_to_stage3_rd_val__h5642 = stage2_rg_stage2[63:32];
      3'd1, 3'd4:
	  x_out_data_to_stage3_rd_val__h5642 = near_mem$dmem_word64[31:0];
      default: x_out_data_to_stage3_rd_val__h5642 = stage2_mbox$word;
    endcase
  end
  always@(stage2_rg_stage2)
  begin
    case (stage2_rg_stage2[103:101])
      3'd0, 3'd1, 3'd4: x_out_bypass_rd__h5992 = stage2_rg_stage2[100:96];
      default: x_out_bypass_rd__h5992 = stage2_rg_stage2[100:96];
    endcase
  end
  always@(stage2_rg_stage2 or
	  stage2_mbox$word or output_stage2___1_bypass_rd_val__h5981)
  begin
    case (stage2_rg_stage2[103:101])
      3'd0: x_out_bypass_rd_val__h5993 = stage2_rg_stage2[63:32];
      3'd1, 3'd4:
	  x_out_bypass_rd_val__h5993 = output_stage2___1_bypass_rd_val__h5981;
      default: x_out_bypass_rd_val__h5993 = stage2_mbox$word;
    endcase
  end
  always@(stage2_rg_stage2 or
	  IF_stage2_rg_stage2_8_BITS_103_TO_101_9_EQ_3_5_ETC___d115 or
	  IF_near_mem_dmem_valid__09_THEN_IF_near_mem_dm_ETC___d112)
  begin
    case (stage2_rg_stage2[103:101])
      3'd0: CASE_stage2_rg_stage2_BITS_103_TO_101_0_2_1_IF_ETC__q1 = 2'd2;
      3'd1, 3'd2, 3'd4:
	  CASE_stage2_rg_stage2_BITS_103_TO_101_0_2_1_IF_ETC__q1 =
	      IF_near_mem_dmem_valid__09_THEN_IF_near_mem_dm_ETC___d112;
      default: CASE_stage2_rg_stage2_BITS_103_TO_101_0_2_1_IF_ETC__q1 =
		   IF_stage2_rg_stage2_8_BITS_103_TO_101_9_EQ_3_5_ETC___d115;
    endcase
  end
  always@(stage2_rg_stage2 or
	  stage2_mbox$valid or near_mem$dmem_valid or near_mem$dmem_exc)
  begin
    case (stage2_rg_stage2[103:101])
      3'd1, 3'd2, 3'd4:
	  IF_stage2_rg_stage2_8_BITS_103_TO_101_9_EQ_1_1_ETC___d132 =
	      !near_mem$dmem_valid || near_mem$dmem_exc;
      default: IF_stage2_rg_stage2_8_BITS_103_TO_101_9_EQ_1_1_ETC___d132 =
		   !stage2_mbox$valid;
    endcase
  end
  always@(stage2_rg_stage2 or
	  stage2_mbox$valid or near_mem$dmem_valid or near_mem$dmem_exc)
  begin
    case (stage2_rg_stage2[103:101])
      3'd1, 3'd2, 3'd4:
	  IF_stage2_rg_stage2_8_BITS_103_TO_101_9_EQ_1_1_ETC___d141 =
	      near_mem$dmem_valid && !near_mem$dmem_exc;
      default: IF_stage2_rg_stage2_8_BITS_103_TO_101_9_EQ_1_1_ETC___d141 =
		   stage2_mbox$valid;
    endcase
  end
  always@(stage2_rg_stage2 or
	  IF_stage2_rg_stage2_8_BITS_103_TO_101_9_EQ_3_5_ETC___d115 or
	  IF_NOT_near_mem_dmem_valid__09_28_OR_NOT_near__ETC___d176)
  begin
    case (stage2_rg_stage2[103:101])
      3'd0: CASE_stage2_rg_stage2_BITS_103_TO_101_0_2_1_IF_ETC__q2 = 2'd2;
      3'd1, 3'd4:
	  CASE_stage2_rg_stage2_BITS_103_TO_101_0_2_1_IF_ETC__q2 =
	      IF_NOT_near_mem_dmem_valid__09_28_OR_NOT_near__ETC___d176;
      3'd2: CASE_stage2_rg_stage2_BITS_103_TO_101_0_2_1_IF_ETC__q2 = 2'd0;
      default: CASE_stage2_rg_stage2_BITS_103_TO_101_0_2_1_IF_ETC__q2 =
		   IF_stage2_rg_stage2_8_BITS_103_TO_101_9_EQ_3_5_ETC___d115;
    endcase
  end
  always@(rg_cur_priv)
  begin
    case (rg_cur_priv)
      2'b0: CASE_rg_cur_priv_0b0_8_0b1_9_11__q5 = 4'd8;
      2'b01: CASE_rg_cur_priv_0b0_8_0b1_9_11__q5 = 4'd9;
      default: CASE_rg_cur_priv_0b0_8_0b1_9_11__q5 = 4'd11;
    endcase
  end
  always@(_theResult____h4280 or CASE_rg_cur_priv_0b0_8_0b1_9_11__q5)
  begin
    case (_theResult____h4280[31:20])
      12'b0:
	  CASE_theResult__280_BITS_31_TO_20_0b0_CASE_rg__ETC__q6 =
	      CASE_rg_cur_priv_0b0_8_0b1_9_11__q5;
      12'b000000000001:
	  CASE_theResult__280_BITS_31_TO_20_0b0_CASE_rg__ETC__q6 = 4'd3;
      default: CASE_theResult__280_BITS_31_TO_20_0b0_CASE_rg__ETC__q6 = 4'd2;
    endcase
  end
  always@(_theResult____h4280 or alu_outputs___1_exc_code__h12238)
  begin
    case (_theResult____h4280[6:0])
      7'b0000011,
      7'b0001111,
      7'b0010011,
      7'b0010111,
      7'b0100011,
      7'b0110011,
      7'b0110111,
      7'b1100011:
	  alu_outputs_exc_code__h12281 = 4'd2;
      7'b1100111, 7'b1101111: alu_outputs_exc_code__h12281 = 4'd0;
      7'b1110011:
	  alu_outputs_exc_code__h12281 = alu_outputs___1_exc_code__h12238;
      default: alu_outputs_exc_code__h12281 = 4'd2;
    endcase
  end
  always@(_theResult____h4280 or
	  IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d527 or
	  IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d523 or
	  IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d525)
  begin
    case (_theResult____h4280[14:12])
      3'b0:
	  IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d628 =
	      !IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d523;
      3'b001:
	  IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d628 =
	      IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d523;
      3'b100:
	  IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d628 =
	      !IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d525;
      3'b101:
	  IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d628 =
	      IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d525;
      3'b110:
	  IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d628 =
	      !IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d527;
      default: IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d628 =
		   _theResult____h4280[14:12] != 3'b111 ||
		   IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d527;
    endcase
  end
  always@(_theResult____h4280 or
	  IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d527 or
	  IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d523 or
	  IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d525)
  begin
    case (_theResult____h4280[14:12])
      3'b0:
	  IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d534 =
	      IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d523;
      3'b001:
	  IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d534 =
	      !IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d523;
      3'b100:
	  IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d534 =
	      IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d525;
      3'b101:
	  IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d534 =
	      !IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d525;
      3'b110:
	  IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d534 =
	      IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d527;
      default: IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d534 =
		   _theResult____h4280[14:12] == 3'b111 &&
		   !IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d527;
    endcase
  end
  always@(_theResult____h4280)
  begin
    case (_theResult____h4280[6:0])
      7'b0000011:
	  CASE_theResult__280_BITS_6_TO_0_0b11_NOT_theRe_ETC__q8 =
	      _theResult____h4280[14:12] != 3'b0 &&
	      _theResult____h4280[14:12] != 3'b100 &&
	      _theResult____h4280[14:12] != 3'b001 &&
	      _theResult____h4280[14:12] != 3'b101 &&
	      _theResult____h4280[14:12] != 3'b010;
      7'b0100011:
	  CASE_theResult__280_BITS_6_TO_0_0b11_NOT_theRe_ETC__q8 =
	      _theResult____h4280[14:12] != 3'b0 &&
	      _theResult____h4280[14:12] != 3'b001 &&
	      _theResult____h4280[14:12] != 3'b010;
      default: CASE_theResult__280_BITS_6_TO_0_0b11_NOT_theRe_ETC__q8 =
		   _theResult____h4280[6:0] != 7'b0101111 ||
		   _theResult____h4280[31:27] != 5'b00010 &&
		   _theResult____h4280[31:27] != 5'b00011 &&
		   _theResult____h4280[31:27] != 5'b0 &&
		   _theResult____h4280[31:27] != 5'b00001 &&
		   _theResult____h4280[31:27] != 5'b01100 &&
		   _theResult____h4280[31:27] != 5'b01000 &&
		   _theResult____h4280[31:27] != 5'b00100 &&
		   _theResult____h4280[31:27] != 5'b10000 &&
		   _theResult____h4280[31:27] != 5'b11000 &&
		   _theResult____h4280[31:27] != 5'b10100 &&
		   _theResult____h4280[31:27] != 5'b11100 ||
		   _theResult____h4280[14:12] != 3'b010;
    endcase
  end
  always@(_theResult____h4280 or
	  CASE_theResult__280_BITS_6_TO_0_0b11_NOT_theRe_ETC__q8 or
	  NOT_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS_ETC___d564)
  begin
    case (_theResult____h4280[6:0])
      7'b0010011, 7'b0110011:
	  CASE_theResult__280_BITS_6_TO_0_0b10011_NOT_IF_ETC__q9 =
	      NOT_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS_ETC___d564;
      default: CASE_theResult__280_BITS_6_TO_0_0b10011_NOT_IF_ETC__q9 =
		   _theResult____h4280[6:0] != 7'b0110111 &&
		   _theResult____h4280[6:0] != 7'b0010111 &&
		   CASE_theResult__280_BITS_6_TO_0_0b11_NOT_theRe_ETC__q8;
    endcase
  end
  always@(_theResult____h4280)
  begin
    case (_theResult____h4280[6:0])
      7'b0000011:
	  CASE_theResult__280_BITS_6_TO_0_0b11_theResult_ETC__q10 =
	      _theResult____h4280[14:12] == 3'b0 ||
	      _theResult____h4280[14:12] == 3'b100 ||
	      _theResult____h4280[14:12] == 3'b001 ||
	      _theResult____h4280[14:12] == 3'b101 ||
	      _theResult____h4280[14:12] == 3'b010;
      7'b0100011:
	  CASE_theResult__280_BITS_6_TO_0_0b11_theResult_ETC__q10 =
	      _theResult____h4280[14:12] == 3'b0 ||
	      _theResult____h4280[14:12] == 3'b001 ||
	      _theResult____h4280[14:12] == 3'b010;
      default: CASE_theResult__280_BITS_6_TO_0_0b11_theResult_ETC__q10 =
		   _theResult____h4280[6:0] == 7'b0101111 &&
		   (_theResult____h4280[31:27] == 5'b00010 ||
		    _theResult____h4280[31:27] == 5'b00011 ||
		    _theResult____h4280[31:27] == 5'b0 ||
		    _theResult____h4280[31:27] == 5'b00001 ||
		    _theResult____h4280[31:27] == 5'b01100 ||
		    _theResult____h4280[31:27] == 5'b01000 ||
		    _theResult____h4280[31:27] == 5'b00100 ||
		    _theResult____h4280[31:27] == 5'b10000 ||
		    _theResult____h4280[31:27] == 5'b11000 ||
		    _theResult____h4280[31:27] == 5'b10100 ||
		    _theResult____h4280[31:27] == 5'b11100) &&
		   _theResult____h4280[14:12] == 3'b010;
    endcase
  end
  always@(_theResult____h4280 or
	  CASE_theResult__280_BITS_6_TO_0_0b11_theResult_ETC__q10 or
	  IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS_2_9_ETC___d653)
  begin
    case (_theResult____h4280[6:0])
      7'b0010011, 7'b0110011:
	  CASE_theResult__280_BITS_6_TO_0_0b10011_IF_NOT_ETC__q11 =
	      IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS_2_9_ETC___d653;
      default: CASE_theResult__280_BITS_6_TO_0_0b10011_IF_NOT_ETC__q11 =
		   _theResult____h4280[6:0] == 7'b0110111 ||
		   _theResult____h4280[6:0] == 7'b0010111 ||
		   CASE_theResult__280_BITS_6_TO_0_0b11_theResult_ETC__q10;
    endcase
  end
  always@(_theResult____h4280 or
	  rg_cur_priv or
	  IF_rg_cur_priv_3_EQ_0b11_04_OR_rg_cur_priv_3_E_ETC___d723)
  begin
    case (_theResult____h4280[31:20])
      12'b0, 12'b000000000001:
	  IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d725 = 4'd11;
      default: IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d725 =
		   (rg_cur_priv == 2'b11 &&
		    _theResult____h4280[31:20] == 12'b001100000010) ?
		     4'd7 :
		     IF_rg_cur_priv_3_EQ_0b11_04_OR_rg_cur_priv_3_E_ETC___d723;
    endcase
  end
  always@(_theResult____h4280)
  begin
    case (_theResult____h4280[14:12])
      3'b0, 3'b001, 3'b010, 3'b100, 3'b101:
	  CASE_theResult__280_BITS_14_TO_12_0b0_0_0b1_0__ETC__q12 = 4'd0;
      default: CASE_theResult__280_BITS_14_TO_12_0b0_0_0b1_0__ETC__q12 =
		   4'd11;
    endcase
  end
  always@(_theResult____h4280)
  begin
    case (_theResult____h4280[14:12])
      3'b0: CASE_theResult__280_BITS_14_TO_12_0b0_4_0b1_5_11__q13 = 4'd4;
      3'b001: CASE_theResult__280_BITS_14_TO_12_0b0_4_0b1_5_11__q13 = 4'd5;
      default: CASE_theResult__280_BITS_14_TO_12_0b0_4_0b1_5_11__q13 = 4'd11;
    endcase
  end
  always@(_theResult____h4280)
  begin
    case (_theResult____h4280[14:12])
      3'b0, 3'b001, 3'b010:
	  CASE_theResult__280_BITS_14_TO_12_0b0_0_0b1_0__ETC__q14 = 4'd0;
      default: CASE_theResult__280_BITS_14_TO_12_0b0_0_0b1_0__ETC__q14 =
		   4'd11;
    endcase
  end
  always@(_theResult____h4280 or
	  IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d725)
  begin
    case (_theResult____h4280[14:12])
      3'b0:
	  CASE_theResult__280_BITS_14_TO_12_0b0_IF_theRe_ETC__q15 =
	      (_theResult____h4280[11:7] == 5'd0 &&
	       _theResult____h4280[19:15] == 5'd0) ?
		IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d725 :
		4'd11;
      3'b001, 3'b101:
	  CASE_theResult__280_BITS_14_TO_12_0b0_IF_theRe_ETC__q15 = 4'd2;
      3'b010, 3'b011, 3'b110, 3'b111:
	  CASE_theResult__280_BITS_14_TO_12_0b0_IF_theRe_ETC__q15 = 4'd3;
      3'd4: CASE_theResult__280_BITS_14_TO_12_0b0_IF_theRe_ETC__q15 = 4'd11;
    endcase
  end
  always@(_theResult____h4280 or
	  CASE_theResult__280_BITS_14_TO_12_0b0_0_0b1_0__ETC__q12 or
	  CASE_theResult__280_BITS_14_TO_12_0b0_4_0b1_5_11__q13 or
	  IF_NOT_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_P_ETC___d690 or
	  CASE_theResult__280_BITS_14_TO_12_0b0_0_0b1_0__ETC__q14 or
	  CASE_theResult__280_BITS_14_TO_12_0b0_IF_theRe_ETC__q15)
  begin
    case (_theResult____h4280[6:0])
      7'b0000011:
	  IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d740 =
	      CASE_theResult__280_BITS_14_TO_12_0b0_0_0b1_0__ETC__q12;
      7'b0001111:
	  IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d740 =
	      CASE_theResult__280_BITS_14_TO_12_0b0_4_0b1_5_11__q13;
      7'b0010011, 7'b0110011:
	  IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d740 =
	      IF_NOT_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_P_ETC___d690;
      7'b0010111, 7'b0110111:
	  IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d740 = 4'd0;
      7'b0100011:
	  IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d740 =
	      CASE_theResult__280_BITS_14_TO_12_0b0_0_0b1_0__ETC__q14;
      7'b0101111:
	  IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d740 =
	      ((_theResult____h4280[31:27] == 5'b00010 ||
		_theResult____h4280[31:27] == 5'b00011 ||
		_theResult____h4280[31:27] == 5'b0 ||
		_theResult____h4280[31:27] == 5'b00001 ||
		_theResult____h4280[31:27] == 5'b01100 ||
		_theResult____h4280[31:27] == 5'b01000 ||
		_theResult____h4280[31:27] == 5'b00100 ||
		_theResult____h4280[31:27] == 5'b10000 ||
		_theResult____h4280[31:27] == 5'b11000 ||
		_theResult____h4280[31:27] == 5'b10100 ||
		_theResult____h4280[31:27] == 5'b11100) &&
	       _theResult____h4280[14:12] == 3'b010) ?
		4'd0 :
		4'd11;
      7'b1110011:
	  IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d740 =
	      CASE_theResult__280_BITS_14_TO_12_0b0_IF_theRe_ETC__q15;
      default: IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d740 =
		   4'd11;
    endcase
  end
  always@(_theResult____h4280 or
	  IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d740 or
	  IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d534)
  begin
    case (_theResult____h4280[6:0])
      7'b1100011:
	  IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d744 =
	      (_theResult____h4280[14:12] != 3'b0 &&
	       _theResult____h4280[14:12] != 3'b001 &&
	       _theResult____h4280[14:12] != 3'b100 &&
	       _theResult____h4280[14:12] != 3'b101 &&
	       _theResult____h4280[14:12] != 3'b110 &&
	       _theResult____h4280[14:12] != 3'b111) ?
		4'd11 :
		(IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d534 ?
		   4'd1 :
		   4'd0);
      7'b1100111, 7'b1101111:
	  IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d744 = 4'd1;
      default: IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d744 =
		   (_theResult____h4280[6:0] == 7'b0110011 &&
		    _theResult____h4280[31:25] == 7'b0000001) ?
		     4'd0 :
		     (((_theResult____h4280[6:0] == 7'b0010011 ||
			_theResult____h4280[6:0] == 7'b0110011) &&
		       (_theResult____h4280[14:12] == 3'b001 ||
			_theResult____h4280[14:12] == 3'b101)) ?
			(_theResult____h4280[25] ? 4'd11 : 4'd0) :
			IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d740);
    endcase
  end
  always@(_theResult____h4280)
  begin
    case (_theResult____h4280[6:0])
      7'b0000011:
	  CASE_theResult__280_BITS_6_TO_0_0b11_1_0b10011_ETC__q16 = 3'd1;
      7'b0010011, 7'b0010111, 7'b0110011, 7'b0110111:
	  CASE_theResult__280_BITS_6_TO_0_0b11_1_0b10011_ETC__q16 = 3'd0;
      7'b0100011:
	  CASE_theResult__280_BITS_6_TO_0_0b11_1_0b10011_ETC__q16 = 3'd2;
      default: CASE_theResult__280_BITS_6_TO_0_0b11_1_0b10011_ETC__q16 = 3'd4;
    endcase
  end
  always@(_theResult____h4280 or
	  CASE_theResult__280_BITS_6_TO_0_0b11_1_0b10011_ETC__q16)
  begin
    case (_theResult____h4280[6:0])
      7'b1100011, 7'b1100111, 7'b1101111:
	  IF_NOT_stage1_rg_full_94_95_OR_NOT_near_mem_im_ETC___d825 = 3'd0;
      default: IF_NOT_stage1_rg_full_94_95_OR_NOT_near_mem_im_ETC___d825 =
		   (_theResult____h4280[6:0] == 7'b0110011 &&
		    _theResult____h4280[31:25] == 7'b0000001) ?
		     3'd3 :
		     CASE_theResult__280_BITS_6_TO_0_0b11_1_0b10011_ETC__q16;
    endcase
  end
  always@(_theResult____h4280 or
	  _theResult_____1_fst__h12753 or
	  rd_val___1__h12721 or
	  rd_val___1__h12728 or rd_val___1__h12735 or rd_val___1__h12742)
  begin
    case (_theResult____h4280[14:12])
      3'b010: _theResult_____1_fst__h12725 = rd_val___1__h12721;
      3'b011: _theResult_____1_fst__h12725 = rd_val___1__h12728;
      3'b100: _theResult_____1_fst__h12725 = rd_val___1__h12735;
      3'b110: _theResult_____1_fst__h12725 = rd_val___1__h12742;
      default: _theResult_____1_fst__h12725 = _theResult_____1_fst__h12753;
    endcase
  end
  always@(_theResult____h4280 or
	  rs1_val_bypassed__h4288 or
	  alu_outputs___1_addr__h11981 or
	  alu_outputs___1_addr__h12002 or
	  alu_outputs___1_addr__h11739 or
	  alu_outputs___1_addr__h11786 or alu_outputs___1_addr__h11760)
  begin
    case (_theResult____h4280[6:0])
      7'b0000011:
	  x_out_data_to_stage2_addr__h11615 = alu_outputs___1_addr__h11981;
      7'b0100011:
	  x_out_data_to_stage2_addr__h11615 = alu_outputs___1_addr__h12002;
      7'b1100011:
	  x_out_data_to_stage2_addr__h11615 = alu_outputs___1_addr__h11739;
      7'b1100111:
	  x_out_data_to_stage2_addr__h11615 = alu_outputs___1_addr__h11786;
      7'b1101111:
	  x_out_data_to_stage2_addr__h11615 = alu_outputs___1_addr__h11760;
      default: x_out_data_to_stage2_addr__h11615 = rs1_val_bypassed__h4288;
    endcase
  end
  always@(_theResult____h4280 or imem_rg_pc or data_to_stage2_addr__h11607)
  begin
    case (_theResult____h4280[6:0])
      7'b1100111, 7'b1101111:
	  IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d1021 =
	      data_to_stage2_addr__h11607;
      default: IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d1021 =
		   (_theResult____h4280[6:0] == 7'b1110011 &&
		    _theResult____h4280[14:12] == 3'b0 &&
		    _theResult____h4280[11:7] == 5'd0 &&
		    _theResult____h4280[19:15] == 5'd0 &&
		    _theResult____h4280[31:20] == 12'b000000000001) ?
		     imem_rg_pc :
		     32'd0;
    endcase
  end
  always@(_theResult____h4280 or
	  alu_outputs___1_val1__h12263 or
	  alu_outputs___1_val1__h11928 or
	  alu_outputs___1_val1__h11960 or
	  alu_outputs___1_val1__h11944 or alu_outputs___1_val1__h12242)
  begin
    case (_theResult____h4280[6:0])
      7'b0010011, 7'b0110011:
	  IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d936 =
	      alu_outputs___1_val1__h11928;
      7'b0010111:
	  IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d936 =
	      alu_outputs___1_val1__h11960;
      7'b0110111:
	  IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d936 =
	      alu_outputs___1_val1__h11944;
      7'b1110011:
	  IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d936 =
	      alu_outputs___1_val1__h12242;
      default: IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d936 =
		   alu_outputs___1_val1__h12263;
    endcase
  end
  always@(_theResult____h4280 or
	  rs1_val_bypassed__h4288 or
	  IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d937 or
	  IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS_2_9_ETC___d869)
  begin
    case (_theResult____h4280[6:0])
      7'b1100111, 7'b1101111:
	  x_out_data_to_stage2_val1__h11616 =
	      IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS_2_9_ETC___d869;
      default: x_out_data_to_stage2_val1__h11616 =
		   (_theResult____h4280[6:0] == 7'b0110011 &&
		    _theResult____h4280[31:25] == 7'b0000001) ?
		     rs1_val_bypassed__h4288 :
		     IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d937;
    endcase
  end
  always@(x_out_data_to_stage2_instr__h11612 or
	  x_out_data_to_stage2_val1__h11616)
  begin
    case (x_out_data_to_stage2_instr__h11612[14:12])
      3'b010, 3'b011: rs1_val__h17721 = x_out_data_to_stage2_val1__h11616;
      default: rs1_val__h17721 =
		   { 27'd0, x_out_data_to_stage2_instr__h11612[19:15] };
    endcase
  end

  // handling of inlined registers

  always@(posedge CLK)
  begin
    if (RST_N == `BSV_RESET_VALUE)
      begin
        cfg_logdelay <= `BSV_ASSIGNMENT_DELAY 64'd0;
	cfg_verbosity <= `BSV_ASSIGNMENT_DELAY 4'd0;
	rg_cur_priv <= `BSV_ASSIGNMENT_DELAY 2'b11;
	rg_run_on_reset <= `BSV_ASSIGNMENT_DELAY 1'd0;
	rg_state <= `BSV_ASSIGNMENT_DELAY 4'd0;
	stage1_rg_full <= `BSV_ASSIGNMENT_DELAY 1'd0;
	stage2_rg_full <= `BSV_ASSIGNMENT_DELAY 1'd0;
	stage2_rg_resetting <= `BSV_ASSIGNMENT_DELAY 1'd0;
	stage3_rg_full <= `BSV_ASSIGNMENT_DELAY 1'd0;
      end
    else
      begin
        if (cfg_logdelay$EN)
	  cfg_logdelay <= `BSV_ASSIGNMENT_DELAY cfg_logdelay$D_IN;
	if (cfg_verbosity$EN)
	  cfg_verbosity <= `BSV_ASSIGNMENT_DELAY cfg_verbosity$D_IN;
	if (rg_cur_priv$EN)
	  rg_cur_priv <= `BSV_ASSIGNMENT_DELAY rg_cur_priv$D_IN;
	if (rg_run_on_reset$EN)
	  rg_run_on_reset <= `BSV_ASSIGNMENT_DELAY rg_run_on_reset$D_IN;
	if (rg_state$EN) rg_state <= `BSV_ASSIGNMENT_DELAY rg_state$D_IN;
	if (stage1_rg_full$EN)
	  stage1_rg_full <= `BSV_ASSIGNMENT_DELAY stage1_rg_full$D_IN;
	if (stage2_rg_full$EN)
	  stage2_rg_full <= `BSV_ASSIGNMENT_DELAY stage2_rg_full$D_IN;
	if (stage2_rg_resetting$EN)
	  stage2_rg_resetting <= `BSV_ASSIGNMENT_DELAY
	      stage2_rg_resetting$D_IN;
	if (stage3_rg_full$EN)
	  stage3_rg_full <= `BSV_ASSIGNMENT_DELAY stage3_rg_full$D_IN;
      end
    if (imem_rg_f3$EN) imem_rg_f3 <= `BSV_ASSIGNMENT_DELAY imem_rg_f3$D_IN;
    if (imem_rg_instr_15_0$EN)
      imem_rg_instr_15_0 <= `BSV_ASSIGNMENT_DELAY imem_rg_instr_15_0$D_IN;
    if (imem_rg_mstatus_MXR$EN)
      imem_rg_mstatus_MXR <= `BSV_ASSIGNMENT_DELAY imem_rg_mstatus_MXR$D_IN;
    if (imem_rg_pc$EN) imem_rg_pc <= `BSV_ASSIGNMENT_DELAY imem_rg_pc$D_IN;
    if (imem_rg_priv$EN)
      imem_rg_priv <= `BSV_ASSIGNMENT_DELAY imem_rg_priv$D_IN;
    if (imem_rg_satp$EN)
      imem_rg_satp <= `BSV_ASSIGNMENT_DELAY imem_rg_satp$D_IN;
    if (imem_rg_sstatus_SUM$EN)
      imem_rg_sstatus_SUM <= `BSV_ASSIGNMENT_DELAY imem_rg_sstatus_SUM$D_IN;
    if (imem_rg_tval$EN)
      imem_rg_tval <= `BSV_ASSIGNMENT_DELAY imem_rg_tval$D_IN;
    if (rg_mstatus_MXR$EN)
      rg_mstatus_MXR <= `BSV_ASSIGNMENT_DELAY rg_mstatus_MXR$D_IN;
    if (rg_next_pc$EN) rg_next_pc <= `BSV_ASSIGNMENT_DELAY rg_next_pc$D_IN;
    if (rg_sstatus_SUM$EN)
      rg_sstatus_SUM <= `BSV_ASSIGNMENT_DELAY rg_sstatus_SUM$D_IN;
    if (rg_start_CPI_cycles$EN)
      rg_start_CPI_cycles <= `BSV_ASSIGNMENT_DELAY rg_start_CPI_cycles$D_IN;
    if (rg_start_CPI_instrs$EN)
      rg_start_CPI_instrs <= `BSV_ASSIGNMENT_DELAY rg_start_CPI_instrs$D_IN;
    if (stage2_rg_stage2$EN)
      stage2_rg_stage2 <= `BSV_ASSIGNMENT_DELAY stage2_rg_stage2$D_IN;
    if (stage3_rg_stage3$EN)
      stage3_rg_stage3 <= `BSV_ASSIGNMENT_DELAY stage3_rg_stage3$D_IN;
  end

  // synopsys translate_off
  `ifdef BSV_NO_INITIAL_BLOCKS
  `else // not BSV_NO_INITIAL_BLOCKS
  initial
  begin
    cfg_logdelay = 64'hAAAAAAAAAAAAAAAA;
    cfg_verbosity = 4'hA;
    imem_rg_f3 = 3'h2;
    imem_rg_instr_15_0 = 16'hAAAA;
    imem_rg_mstatus_MXR = 1'h0;
    imem_rg_pc = 32'hAAAAAAAA;
    imem_rg_priv = 2'h2;
    imem_rg_satp = 32'hAAAAAAAA;
    imem_rg_sstatus_SUM = 1'h0;
    imem_rg_tval = 32'hAAAAAAAA;
    rg_cur_priv = 2'h2;
    rg_mstatus_MXR = 1'h0;
    rg_next_pc = 32'hAAAAAAAA;
    rg_run_on_reset = 1'h0;
    rg_sstatus_SUM = 1'h0;
    rg_start_CPI_cycles = 64'hAAAAAAAAAAAAAAAA;
    rg_start_CPI_instrs = 64'hAAAAAAAAAAAAAAAA;
    rg_state = 4'hA;
    stage1_rg_full = 1'h0;
    stage2_rg_full = 1'h0;
    stage2_rg_resetting = 1'h0;
    stage2_rg_stage2 = 170'h2AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA;
    stage3_rg_full = 1'h0;
    stage3_rg_stage3 = 104'hAAAAAAAAAAAAAAAAAAAAAAAAAA;
  end
  `endif // BSV_NO_INITIAL_BLOCKS
  // synopsys translate_on

  // handling of system tasks

  // synopsys translate_off
  always@(negedge CLK)
  begin
    #0;
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe)
	$display("================================================================");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe)
	$display("%0d: Pipeline State:  minstret:%0d  cur_priv:%0d  mstatus:%0x",
		 csr_regfile$read_csr_mcycle,
		 csr_regfile$read_csr_minstret,
		 rg_cur_priv,
		 csr_regfile$read_mstatus);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe) $write("    ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe)
	$write("MStatus{",
	       "sd:%0d",
	       csr_regfile$read_mstatus[14:13] == 2'h3 ||
	       csr_regfile$read_mstatus[16:15] == 2'h3);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe && csr_regfile$read_misa[27:26] == 2'd2)
	$write(" sxl:%0d uxl:%0d", 2'd0, 2'd0);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe && csr_regfile$read_misa[27:26] != 2'd2)
	$write("");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe)
	$write(" tsr:%0d", csr_regfile$read_mstatus[22]);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe)
	$write(" tw:%0d", csr_regfile$read_mstatus[21]);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe)
	$write(" tvm:%0d", csr_regfile$read_mstatus[20]);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe)
	$write(" mxr:%0d", csr_regfile$read_mstatus[19]);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe)
	$write(" sum:%0d", csr_regfile$read_mstatus[18]);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe)
	$write(" mprv:%0d", csr_regfile$read_mstatus[17]);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe)
	$write(" xs:%0d", csr_regfile$read_mstatus[16:15]);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe)
	$write(" fs:%0d", csr_regfile$read_mstatus[14:13]);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe)
	$write(" mpp:%0d", csr_regfile$read_mstatus[12:11]);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe)
	$write(" spp:%0d", csr_regfile$read_mstatus[8]);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe)
	$write(" pies:%0d_%0d%0d",
	       csr_regfile$read_mstatus[7],
	       csr_regfile$read_mstatus[5],
	       csr_regfile$read_mstatus[4]);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe)
	$write(" ies:%0d_%0d%0d",
	       csr_regfile$read_mstatus[3],
	       csr_regfile$read_mstatus[1],
	       csr_regfile$read_mstatus[0]);
    if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_show_pipe) $write("}");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe) $write("\n");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe) $write("    Stage3: ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe) $write("Output_Stage3");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe && stage3_rg_full) $write(" PIPE");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe && !stage3_rg_full) $write(" EMPTY");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe) $write("\n");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe) $write("        Bypass  to Stage1: ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe) $write("Bypass {");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe &&
	  (!stage3_rg_full || !stage3_rg_stage3[37]))
	$write("Rd -");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe && stage3_rg_full && stage3_rg_stage3[37])
	$write("Rd %0d ",
	       stage3_rg_stage3[36:32],
	       "rd_val:%h",
	       stage3_rg_stage3[31:0]);
    if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_show_pipe) $write("}");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe) $write("\n");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe)
	$display("    Stage2: pc 0x%08h instr 0x%08h priv %0d",
		 stage2_rg_stage2[167:136],
		 stage2_rg_stage2[135:104],
		 stage2_rg_stage2[169:168]);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe) $write("        ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe &&
	  IF_stage2_rg_full_7_THEN_IF_stage2_rg_stage2_8_ETC___d118 == 2'd0)
	$write("Output_Stage2", " EMPTY");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe &&
	  IF_stage2_rg_full_7_THEN_IF_stage2_rg_stage2_8_ETC___d118 == 2'd1)
	$write("Output_Stage2", " BUSY: pc:%0h", stage2_rg_stage2[167:136]);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe &&
	  IF_stage2_rg_full_7_THEN_IF_stage2_rg_stage2_8_ETC___d118 == 2'd3)
	$write("Output_Stage2", " NONPIPE: ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe &&
	  IF_stage2_rg_full_7_THEN_IF_stage2_rg_stage2_8_ETC___d118 != 2'd0 &&
	  IF_stage2_rg_full_7_THEN_IF_stage2_rg_stage2_8_ETC___d118 != 2'd1 &&
	  IF_stage2_rg_full_7_THEN_IF_stage2_rg_stage2_8_ETC___d118 != 2'd3)
	$write("Output_Stage2", " PIPE: ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe &&
	  IF_stage2_rg_full_7_THEN_IF_stage2_rg_stage2_8_ETC___d118 == 2'd0)
	$write("");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe &&
	  IF_stage2_rg_full_7_THEN_IF_stage2_rg_stage2_8_ETC___d118 == 2'd1)
	$write("");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe &&
	  IF_stage2_rg_full_7_THEN_IF_stage2_rg_stage2_8_ETC___d118 == 2'd3)
	$write("");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe &&
	  IF_stage2_rg_full_7_THEN_IF_stage2_rg_stage2_8_ETC___d118 != 2'd0 &&
	  IF_stage2_rg_full_7_THEN_IF_stage2_rg_stage2_8_ETC___d118 != 2'd1 &&
	  IF_stage2_rg_full_7_THEN_IF_stage2_rg_stage2_8_ETC___d118 != 2'd3)
	$write("data_to_Stage3 {pc:%h  instr:%h  priv:%0d\n",
	       stage2_rg_stage2[167:136],
	       stage2_rg_stage2[135:104],
	       stage2_rg_stage2[169:168]);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe &&
	  IF_stage2_rg_full_7_THEN_IF_stage2_rg_stage2_8_ETC___d118 == 2'd0)
	$write("");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe &&
	  IF_stage2_rg_full_7_THEN_IF_stage2_rg_stage2_8_ETC___d118 == 2'd1)
	$write("");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe &&
	  IF_stage2_rg_full_7_THEN_IF_stage2_rg_stage2_8_ETC___d118 == 2'd3)
	$write("");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe &&
	  IF_stage2_rg_full_7_THEN_IF_stage2_rg_stage2_8_ETC___d118 != 2'd0 &&
	  IF_stage2_rg_full_7_THEN_IF_stage2_rg_stage2_8_ETC___d118 != 2'd1 &&
	  IF_stage2_rg_full_7_THEN_IF_stage2_rg_stage2_8_ETC___d118 != 2'd3)
	$write("        rd_valid:");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe &&
	  IF_stage2_rg_full_7_THEN_IF_stage2_rg_stage2_8_ETC___d118 == 2'd0)
	$write("");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe &&
	  IF_stage2_rg_full_7_THEN_IF_stage2_rg_stage2_8_ETC___d118 == 2'd1)
	$write("");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe &&
	  IF_stage2_rg_full_7_THEN_IF_stage2_rg_stage2_8_ETC___d118 == 2'd3)
	$write("");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe &&
	  IF_stage2_rg_full_7_THEN_IF_stage2_rg_stage2_8_ETC___d118 != 2'd0 &&
	  IF_stage2_rg_full_7_THEN_IF_stage2_rg_stage2_8_ETC___d118 != 2'd1 &&
	  IF_stage2_rg_full_7_THEN_IF_stage2_rg_stage2_8_ETC___d118 != 2'd3 &&
	  stage2_rg_stage2[103:101] != 3'd0 &&
	  IF_stage2_rg_stage2_8_BITS_103_TO_101_9_EQ_1_1_ETC___d132)
	$write("False");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe &&
	  IF_stage2_rg_full_7_THEN_IF_stage2_rg_stage2_8_ETC___d118 != 2'd0 &&
	  IF_stage2_rg_full_7_THEN_IF_stage2_rg_stage2_8_ETC___d118 != 2'd1 &&
	  IF_stage2_rg_full_7_THEN_IF_stage2_rg_stage2_8_ETC___d118 != 2'd3 &&
	  (stage2_rg_stage2[103:101] == 3'd0 ||
	   IF_stage2_rg_stage2_8_BITS_103_TO_101_9_EQ_1_1_ETC___d141))
	$write("True");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe &&
	  IF_stage2_rg_full_7_THEN_IF_stage2_rg_stage2_8_ETC___d118 == 2'd0)
	$write("");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe &&
	  IF_stage2_rg_full_7_THEN_IF_stage2_rg_stage2_8_ETC___d118 == 2'd1)
	$write("");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe &&
	  IF_stage2_rg_full_7_THEN_IF_stage2_rg_stage2_8_ETC___d118 == 2'd3)
	$write("");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe &&
	  IF_stage2_rg_full_7_THEN_IF_stage2_rg_stage2_8_ETC___d118 != 2'd0 &&
	  IF_stage2_rg_full_7_THEN_IF_stage2_rg_stage2_8_ETC___d118 != 2'd1 &&
	  IF_stage2_rg_full_7_THEN_IF_stage2_rg_stage2_8_ETC___d118 != 2'd3)
	$write("  grd:%0d  rd_val:%h\n",
	       x_out_data_to_stage3_rd__h5641,
	       x_out_data_to_stage3_rd_val__h5642);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe &&
	  IF_stage2_rg_full_7_THEN_IF_stage2_rg_stage2_8_ETC___d118 == 2'd0)
	$write("");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe &&
	  IF_stage2_rg_full_7_THEN_IF_stage2_rg_stage2_8_ETC___d118 == 2'd1)
	$write("");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe &&
	  IF_stage2_rg_full_7_THEN_IF_stage2_rg_stage2_8_ETC___d118 == 2'd3)
	$write("Trap_Info { ", "epc: ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe &&
	  IF_stage2_rg_full_7_THEN_IF_stage2_rg_stage2_8_ETC___d118 != 2'd0 &&
	  IF_stage2_rg_full_7_THEN_IF_stage2_rg_stage2_8_ETC___d118 != 2'd1 &&
	  IF_stage2_rg_full_7_THEN_IF_stage2_rg_stage2_8_ETC___d118 != 2'd3)
	$write("");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe &&
	  IF_stage2_rg_full_7_THEN_IF_stage2_rg_stage2_8_ETC___d118 == 2'd0)
	$write("");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe &&
	  IF_stage2_rg_full_7_THEN_IF_stage2_rg_stage2_8_ETC___d118 == 2'd1)
	$write("");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe &&
	  IF_stage2_rg_full_7_THEN_IF_stage2_rg_stage2_8_ETC___d118 == 2'd3)
	$write("'h%h", stage2_rg_stage2[167:136]);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe &&
	  IF_stage2_rg_full_7_THEN_IF_stage2_rg_stage2_8_ETC___d118 != 2'd0 &&
	  IF_stage2_rg_full_7_THEN_IF_stage2_rg_stage2_8_ETC___d118 != 2'd1 &&
	  IF_stage2_rg_full_7_THEN_IF_stage2_rg_stage2_8_ETC___d118 != 2'd3)
	$write("");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe &&
	  IF_stage2_rg_full_7_THEN_IF_stage2_rg_stage2_8_ETC___d118 == 2'd0)
	$write("");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe &&
	  IF_stage2_rg_full_7_THEN_IF_stage2_rg_stage2_8_ETC___d118 == 2'd1)
	$write("");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe &&
	  IF_stage2_rg_full_7_THEN_IF_stage2_rg_stage2_8_ETC___d118 == 2'd3)
	$write(", ", "exc_code: ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe &&
	  IF_stage2_rg_full_7_THEN_IF_stage2_rg_stage2_8_ETC___d118 != 2'd0 &&
	  IF_stage2_rg_full_7_THEN_IF_stage2_rg_stage2_8_ETC___d118 != 2'd1 &&
	  IF_stage2_rg_full_7_THEN_IF_stage2_rg_stage2_8_ETC___d118 != 2'd3)
	$write("");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe &&
	  IF_stage2_rg_full_7_THEN_IF_stage2_rg_stage2_8_ETC___d118 == 2'd0)
	$write("");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe &&
	  IF_stage2_rg_full_7_THEN_IF_stage2_rg_stage2_8_ETC___d118 == 2'd1)
	$write("");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe &&
	  IF_stage2_rg_full_7_THEN_IF_stage2_rg_stage2_8_ETC___d118 == 2'd3)
	$write("'h%h", near_mem$dmem_exc_code);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe &&
	  IF_stage2_rg_full_7_THEN_IF_stage2_rg_stage2_8_ETC___d118 != 2'd0 &&
	  IF_stage2_rg_full_7_THEN_IF_stage2_rg_stage2_8_ETC___d118 != 2'd1 &&
	  IF_stage2_rg_full_7_THEN_IF_stage2_rg_stage2_8_ETC___d118 != 2'd3)
	$write("");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe &&
	  IF_stage2_rg_full_7_THEN_IF_stage2_rg_stage2_8_ETC___d118 == 2'd0)
	$write("");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe &&
	  IF_stage2_rg_full_7_THEN_IF_stage2_rg_stage2_8_ETC___d118 == 2'd1)
	$write("");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe &&
	  IF_stage2_rg_full_7_THEN_IF_stage2_rg_stage2_8_ETC___d118 == 2'd3)
	$write(", ", "tval: ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe &&
	  IF_stage2_rg_full_7_THEN_IF_stage2_rg_stage2_8_ETC___d118 != 2'd0 &&
	  IF_stage2_rg_full_7_THEN_IF_stage2_rg_stage2_8_ETC___d118 != 2'd1 &&
	  IF_stage2_rg_full_7_THEN_IF_stage2_rg_stage2_8_ETC___d118 != 2'd3)
	$write("");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe &&
	  IF_stage2_rg_full_7_THEN_IF_stage2_rg_stage2_8_ETC___d118 == 2'd0)
	$write("");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe &&
	  IF_stage2_rg_full_7_THEN_IF_stage2_rg_stage2_8_ETC___d118 == 2'd1)
	$write("");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe &&
	  IF_stage2_rg_full_7_THEN_IF_stage2_rg_stage2_8_ETC___d118 == 2'd3)
	$write("'h%h", stage2_rg_stage2[95:64], " }");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe &&
	  IF_stage2_rg_full_7_THEN_IF_stage2_rg_stage2_8_ETC___d118 != 2'd0 &&
	  IF_stage2_rg_full_7_THEN_IF_stage2_rg_stage2_8_ETC___d118 != 2'd1 &&
	  IF_stage2_rg_full_7_THEN_IF_stage2_rg_stage2_8_ETC___d118 != 2'd3)
	$write("");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe &&
	  IF_stage2_rg_full_7_THEN_IF_stage2_rg_stage2_8_ETC___d118 == 2'd0)
	$write("");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe &&
	  IF_stage2_rg_full_7_THEN_IF_stage2_rg_stage2_8_ETC___d118 == 2'd1)
	$write("");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe &&
	  IF_stage2_rg_full_7_THEN_IF_stage2_rg_stage2_8_ETC___d118 == 2'd3)
	$write(" ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe &&
	  IF_stage2_rg_full_7_THEN_IF_stage2_rg_stage2_8_ETC___d118 != 2'd0 &&
	  IF_stage2_rg_full_7_THEN_IF_stage2_rg_stage2_8_ETC___d118 != 2'd1 &&
	  IF_stage2_rg_full_7_THEN_IF_stage2_rg_stage2_8_ETC___d118 != 2'd3)
	$write("");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe &&
	  IF_stage2_rg_full_7_THEN_IF_stage2_rg_stage2_8_ETC___d118 == 2'd0)
	$write("");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe &&
	  IF_stage2_rg_full_7_THEN_IF_stage2_rg_stage2_8_ETC___d118 == 2'd1)
	$write("");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe &&
	  IF_stage2_rg_full_7_THEN_IF_stage2_rg_stage2_8_ETC___d118 == 2'd3)
	$write("Trap_Info { ", "epc: ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe &&
	  IF_stage2_rg_full_7_THEN_IF_stage2_rg_stage2_8_ETC___d118 != 2'd0 &&
	  IF_stage2_rg_full_7_THEN_IF_stage2_rg_stage2_8_ETC___d118 != 2'd1 &&
	  IF_stage2_rg_full_7_THEN_IF_stage2_rg_stage2_8_ETC___d118 != 2'd3)
	$write("");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe &&
	  IF_stage2_rg_full_7_THEN_IF_stage2_rg_stage2_8_ETC___d118 == 2'd0)
	$write("");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe &&
	  IF_stage2_rg_full_7_THEN_IF_stage2_rg_stage2_8_ETC___d118 == 2'd1)
	$write("");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe &&
	  IF_stage2_rg_full_7_THEN_IF_stage2_rg_stage2_8_ETC___d118 == 2'd3)
	$write("'h%h", stage2_rg_stage2[167:136]);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe &&
	  IF_stage2_rg_full_7_THEN_IF_stage2_rg_stage2_8_ETC___d118 != 2'd0 &&
	  IF_stage2_rg_full_7_THEN_IF_stage2_rg_stage2_8_ETC___d118 != 2'd1 &&
	  IF_stage2_rg_full_7_THEN_IF_stage2_rg_stage2_8_ETC___d118 != 2'd3)
	$write("");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe &&
	  IF_stage2_rg_full_7_THEN_IF_stage2_rg_stage2_8_ETC___d118 == 2'd0)
	$write("");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe &&
	  IF_stage2_rg_full_7_THEN_IF_stage2_rg_stage2_8_ETC___d118 == 2'd1)
	$write("");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe &&
	  IF_stage2_rg_full_7_THEN_IF_stage2_rg_stage2_8_ETC___d118 == 2'd3)
	$write(", ", "exc_code: ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe &&
	  IF_stage2_rg_full_7_THEN_IF_stage2_rg_stage2_8_ETC___d118 != 2'd0 &&
	  IF_stage2_rg_full_7_THEN_IF_stage2_rg_stage2_8_ETC___d118 != 2'd1 &&
	  IF_stage2_rg_full_7_THEN_IF_stage2_rg_stage2_8_ETC___d118 != 2'd3)
	$write("");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe &&
	  IF_stage2_rg_full_7_THEN_IF_stage2_rg_stage2_8_ETC___d118 == 2'd0)
	$write("");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe &&
	  IF_stage2_rg_full_7_THEN_IF_stage2_rg_stage2_8_ETC___d118 == 2'd1)
	$write("");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe &&
	  IF_stage2_rg_full_7_THEN_IF_stage2_rg_stage2_8_ETC___d118 == 2'd3)
	$write("'h%h", near_mem$dmem_exc_code);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe &&
	  IF_stage2_rg_full_7_THEN_IF_stage2_rg_stage2_8_ETC___d118 != 2'd0 &&
	  IF_stage2_rg_full_7_THEN_IF_stage2_rg_stage2_8_ETC___d118 != 2'd1 &&
	  IF_stage2_rg_full_7_THEN_IF_stage2_rg_stage2_8_ETC___d118 != 2'd3)
	$write("");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe &&
	  IF_stage2_rg_full_7_THEN_IF_stage2_rg_stage2_8_ETC___d118 == 2'd0)
	$write("");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe &&
	  IF_stage2_rg_full_7_THEN_IF_stage2_rg_stage2_8_ETC___d118 == 2'd1)
	$write("");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe &&
	  IF_stage2_rg_full_7_THEN_IF_stage2_rg_stage2_8_ETC___d118 == 2'd3)
	$write(", ", "tval: ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe &&
	  IF_stage2_rg_full_7_THEN_IF_stage2_rg_stage2_8_ETC___d118 != 2'd0 &&
	  IF_stage2_rg_full_7_THEN_IF_stage2_rg_stage2_8_ETC___d118 != 2'd1 &&
	  IF_stage2_rg_full_7_THEN_IF_stage2_rg_stage2_8_ETC___d118 != 2'd3)
	$write("");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe &&
	  IF_stage2_rg_full_7_THEN_IF_stage2_rg_stage2_8_ETC___d118 == 2'd0)
	$write("");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe &&
	  IF_stage2_rg_full_7_THEN_IF_stage2_rg_stage2_8_ETC___d118 == 2'd1)
	$write("");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe &&
	  IF_stage2_rg_full_7_THEN_IF_stage2_rg_stage2_8_ETC___d118 == 2'd3)
	$write("'h%h", stage2_rg_stage2[95:64], " }");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe &&
	  IF_stage2_rg_full_7_THEN_IF_stage2_rg_stage2_8_ETC___d118 != 2'd0 &&
	  IF_stage2_rg_full_7_THEN_IF_stage2_rg_stage2_8_ETC___d118 != 2'd1 &&
	  IF_stage2_rg_full_7_THEN_IF_stage2_rg_stage2_8_ETC___d118 != 2'd3)
	$write("");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe) $write("\n");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe) $write("        Bypass  to Stage1: ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe) $write("Bypass {");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe &&
	  IF_stage2_rg_full_7_THEN_IF_stage2_rg_stage2_8_ETC___d180 == 2'd0)
	$write("Rd -");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe &&
	  IF_stage2_rg_full_7_THEN_IF_stage2_rg_stage2_8_ETC___d180 != 2'd0)
	$write("Rd %0d ", x_out_bypass_rd__h5992);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe &&
	  IF_stage2_rg_full_7_THEN_IF_stage2_rg_stage2_8_ETC___d180 == 2'd0)
	$write("");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe &&
	  IF_stage2_rg_full_7_THEN_IF_stage2_rg_stage2_8_ETC___d180 == 2'd1)
	$write("-");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe &&
	  IF_stage2_rg_full_7_THEN_IF_stage2_rg_stage2_8_ETC___d180 != 2'd0 &&
	  IF_stage2_rg_full_7_THEN_IF_stage2_rg_stage2_8_ETC___d180 != 2'd1)
	$write("rd_val:%h", x_out_bypass_rd_val__h5993);
    if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_show_pipe) $write("}");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe) $write("\n");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe)
	$display("    Stage1: pc 0x%08h instr 0x%08h priv %0d",
		 imem_rg_pc,
		 x_out_data_to_stage2_instr__h11612,
		 rg_cur_priv);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe) $write("        ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full &&
	  NOT_near_mem_imem_valid_96_OR_NOT_near_mem_ime_ETC___d469)
	$write("Output_Stage1", " BUSY pc:%h", imem_rg_pc);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full &&
	  near_mem_imem_valid_AND_near_mem_imem_pc_EQ_im_ETC___d636)
	$write("Output_Stage1", " NONPIPE: pc:%h", imem_rg_pc);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full &&
	  near_mem_imem_valid_AND_near_mem_imem_pc_EQ_im_ETC___d685)
	$write("Output_Stage1");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe && !stage1_rg_full)
	$write("Output_Stage1", " EMPTY");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full &&
	  NOT_near_mem_imem_valid_96_OR_NOT_near_mem_ime_ETC___d469)
	$write("");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full &&
	  near_mem_imem_valid_AND_near_mem_imem_pc_EQ_im_ETC___d636)
	$write("");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full &&
	  near_mem_imem_valid_AND_near_mem_imem_pc_EQ_im_ETC___d685)
	$write(" PIPE: ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe && !stage1_rg_full) $write("");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full &&
	  NOT_near_mem_imem_valid_96_OR_NOT_near_mem_ime_ETC___d469)
	$write("");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full &&
	  near_mem_imem_valid_AND_near_mem_imem_pc_EQ_im_ETC___d636)
	$write("");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full &&
	  near_mem_imem_valid_AND_near_mem_imem_pc_EQ_im_ETC___d484 &&
	  !near_mem$imem_exc &&
	  (IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d680 ||
	   IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d682) &&
	  IF_NOT_stage1_rg_full_94_95_OR_NOT_near_mem_im_ETC___d746 == 4'd0)
	$write("CONTROL_STRAIGHT");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full &&
	  near_mem_imem_valid_AND_near_mem_imem_pc_EQ_im_ETC___d484 &&
	  !near_mem$imem_exc &&
	  (IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d680 ||
	   IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d682) &&
	  IF_NOT_stage1_rg_full_94_95_OR_NOT_near_mem_im_ETC___d746 == 4'd1)
	$write("CONTROL_BRANCH");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full &&
	  near_mem_imem_valid_AND_near_mem_imem_pc_EQ_im_ETC___d484 &&
	  !near_mem$imem_exc &&
	  (IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d680 ||
	   IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d682) &&
	  IF_NOT_stage1_rg_full_94_95_OR_NOT_near_mem_im_ETC___d746 == 4'd2)
	$write("CONTROL_CSRR_W");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full &&
	  near_mem_imem_valid_AND_near_mem_imem_pc_EQ_im_ETC___d484 &&
	  !near_mem$imem_exc &&
	  (IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d680 ||
	   IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d682) &&
	  IF_NOT_stage1_rg_full_94_95_OR_NOT_near_mem_im_ETC___d746 == 4'd3)
	$write("CONTROL_CSRR_S_or_C");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full &&
	  near_mem_imem_valid_AND_near_mem_imem_pc_EQ_im_ETC___d484 &&
	  !near_mem$imem_exc &&
	  (IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d680 ||
	   IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d682) &&
	  IF_NOT_stage1_rg_full_94_95_OR_NOT_near_mem_im_ETC___d746 == 4'd4)
	$write("CONTROL_FENCE");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full &&
	  near_mem_imem_valid_AND_near_mem_imem_pc_EQ_im_ETC___d484 &&
	  !near_mem$imem_exc &&
	  (IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d680 ||
	   IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d682) &&
	  IF_NOT_stage1_rg_full_94_95_OR_NOT_near_mem_im_ETC___d746 == 4'd5)
	$write("CONTROL_FENCE_I");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full &&
	  near_mem_imem_valid_AND_near_mem_imem_pc_EQ_im_ETC___d484 &&
	  !near_mem$imem_exc &&
	  (IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d680 ||
	   IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d682) &&
	  IF_NOT_stage1_rg_full_94_95_OR_NOT_near_mem_im_ETC___d746 == 4'd6)
	$write("CONTROL_SFENCE_VMA");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full &&
	  near_mem_imem_valid_AND_near_mem_imem_pc_EQ_im_ETC___d484 &&
	  !near_mem$imem_exc &&
	  (IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d680 ||
	   IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d682) &&
	  IF_NOT_stage1_rg_full_94_95_OR_NOT_near_mem_im_ETC___d746 == 4'd7)
	$write("CONTROL_MRET");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full &&
	  near_mem_imem_valid_AND_near_mem_imem_pc_EQ_im_ETC___d484 &&
	  !near_mem$imem_exc &&
	  (IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d680 ||
	   IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d682) &&
	  IF_NOT_stage1_rg_full_94_95_OR_NOT_near_mem_im_ETC___d746 == 4'd8)
	$write("CONTROL_SRET");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full &&
	  near_mem_imem_valid_AND_near_mem_imem_pc_EQ_im_ETC___d484 &&
	  !near_mem$imem_exc &&
	  (IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d680 ||
	   IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d682) &&
	  IF_NOT_stage1_rg_full_94_95_OR_NOT_near_mem_im_ETC___d746 == 4'd9)
	$write("CONTROL_URET");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full &&
	  near_mem_imem_valid_AND_near_mem_imem_pc_EQ_im_ETC___d484 &&
	  !near_mem$imem_exc &&
	  (IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d680 ||
	   IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d682) &&
	  IF_NOT_stage1_rg_full_94_95_OR_NOT_near_mem_im_ETC___d746 == 4'd10)
	$write("CONTROL_WFI");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full &&
	  near_mem_imem_valid_AND_near_mem_imem_pc_EQ_im_ETC___d484 &&
	  NOT_near_mem_imem_exc__85_38_AND_IF_IF_NOT_nea_ETC___d812)
	$write("CONTROL_TRAP");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe && !stage1_rg_full) $write("");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full &&
	  NOT_near_mem_imem_valid_96_OR_NOT_near_mem_ime_ETC___d469)
	$write("");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full &&
	  near_mem_imem_valid_AND_near_mem_imem_pc_EQ_im_ETC___d636)
	$write("");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full &&
	  near_mem_imem_valid_AND_near_mem_imem_pc_EQ_im_ETC___d685)
	$write(" ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe && !stage1_rg_full) $write("");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full &&
	  NOT_near_mem_imem_valid_96_OR_NOT_near_mem_ime_ETC___d469)
	$write("");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full &&
	  near_mem_imem_valid_AND_near_mem_imem_pc_EQ_im_ETC___d636)
	$write("");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full &&
	  near_mem_imem_valid_AND_near_mem_imem_pc_EQ_im_ETC___d685)
	$write("data_to_Stage 2 {pc:%h  instr:%h  priv:%0d\n",
	       imem_rg_pc,
	       x_out_data_to_stage2_instr__h11612,
	       rg_cur_priv);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe && !stage1_rg_full) $write("");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full &&
	  NOT_near_mem_imem_valid_96_OR_NOT_near_mem_ime_ETC___d469)
	$write("");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full &&
	  near_mem_imem_valid_AND_near_mem_imem_pc_EQ_im_ETC___d636)
	$write("");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full &&
	  near_mem_imem_valid_AND_near_mem_imem_pc_EQ_im_ETC___d685)
	$write("            op_stage2:");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe && !stage1_rg_full) $write("");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full &&
	  NOT_near_mem_imem_valid_96_OR_NOT_near_mem_ime_ETC___d469)
	$write("");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full &&
	  near_mem_imem_valid_AND_near_mem_imem_pc_EQ_im_ETC___d636)
	$write("");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full &&
	  near_mem_imem_valid_AND_near_mem_imem_pc_EQ_im_ETC___d484 &&
	  !near_mem$imem_exc &&
	  (IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d680 ||
	   IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d682) &&
	  IF_NOT_stage1_rg_full_94_95_OR_NOT_near_mem_im_ETC___d825 == 3'd0)
	$write("OP_Stage2_ALU");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full &&
	  near_mem_imem_valid_AND_near_mem_imem_pc_EQ_im_ETC___d484 &&
	  !near_mem$imem_exc &&
	  (IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d680 ||
	   IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d682) &&
	  IF_NOT_stage1_rg_full_94_95_OR_NOT_near_mem_im_ETC___d825 == 3'd1)
	$write("OP_Stage2_LD");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full &&
	  near_mem_imem_valid_AND_near_mem_imem_pc_EQ_im_ETC___d484 &&
	  !near_mem$imem_exc &&
	  (IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d680 ||
	   IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d682) &&
	  IF_NOT_stage1_rg_full_94_95_OR_NOT_near_mem_im_ETC___d825 == 3'd2)
	$write("OP_Stage2_ST");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full &&
	  near_mem_imem_valid_AND_near_mem_imem_pc_EQ_im_ETC___d484 &&
	  !near_mem$imem_exc &&
	  (IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d680 ||
	   IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d682) &&
	  IF_NOT_stage1_rg_full_94_95_OR_NOT_near_mem_im_ETC___d825 == 3'd3)
	$write("OP_Stage2_M");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full &&
	  near_mem_imem_valid_AND_near_mem_imem_pc_EQ_im_ETC___d484 &&
	  NOT_near_mem_imem_exc__85_38_AND_IF_IF_NOT_nea_ETC___d849)
	$write("OP_Stage2_AMO");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe && !stage1_rg_full) $write("");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full &&
	  NOT_near_mem_imem_valid_96_OR_NOT_near_mem_ime_ETC___d469)
	$write("");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full &&
	  near_mem_imem_valid_AND_near_mem_imem_pc_EQ_im_ETC___d636)
	$write("");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full &&
	  near_mem_imem_valid_AND_near_mem_imem_pc_EQ_im_ETC___d685)
	$write("  rd:%0d\n", x_out_data_to_stage2_rd__h11614);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe && !stage1_rg_full) $write("");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full &&
	  NOT_near_mem_imem_valid_96_OR_NOT_near_mem_ime_ETC___d469)
	$write("");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full &&
	  near_mem_imem_valid_AND_near_mem_imem_pc_EQ_im_ETC___d636)
	$write("");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full &&
	  near_mem_imem_valid_AND_near_mem_imem_pc_EQ_im_ETC___d685)
	$write("            addr:%h  val1:%h  val2:%h}",
	       x_out_data_to_stage2_addr__h11615,
	       x_out_data_to_stage2_val1__h11616,
	       x_out_data_to_stage2_val2__h11617);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe && !stage1_rg_full) $write("");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full &&
	  NOT_near_mem_imem_valid_96_OR_NOT_near_mem_ime_ETC___d469)
	$write("");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full &&
	  near_mem_imem_valid_AND_near_mem_imem_pc_EQ_im_ETC___d636)
	$write(" ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full &&
	  near_mem_imem_valid_AND_near_mem_imem_pc_EQ_im_ETC___d685)
	$write("");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe && !stage1_rg_full) $write("");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full &&
	  NOT_near_mem_imem_valid_96_OR_NOT_near_mem_ime_ETC___d469)
	$write("");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full &&
	  near_mem_imem_valid_AND_near_mem_imem_pc_EQ_im_ETC___d484 &&
	  near_mem_imem_exc__85_OR_IF_IF_NOT_near_mem_im_ETC___d949)
	$write("CONTROL_STRAIGHT");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full &&
	  near_mem_imem_valid_AND_near_mem_imem_pc_EQ_im_ETC___d484 &&
	  near_mem_imem_exc__85_OR_IF_IF_NOT_near_mem_im_ETC___d952)
	$write("CONTROL_BRANCH");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full &&
	  near_mem_imem_valid_AND_near_mem_imem_pc_EQ_im_ETC___d484 &&
	  near_mem_imem_exc__85_OR_IF_IF_NOT_near_mem_im_ETC___d955)
	$write("CONTROL_CSRR_W");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full &&
	  near_mem_imem_valid_AND_near_mem_imem_pc_EQ_im_ETC___d484 &&
	  near_mem_imem_exc__85_OR_IF_IF_NOT_near_mem_im_ETC___d958)
	$write("CONTROL_CSRR_S_or_C");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full &&
	  near_mem_imem_valid_AND_near_mem_imem_pc_EQ_im_ETC___d484 &&
	  near_mem_imem_exc__85_OR_IF_IF_NOT_near_mem_im_ETC___d961)
	$write("CONTROL_FENCE");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full &&
	  near_mem_imem_valid_AND_near_mem_imem_pc_EQ_im_ETC___d484 &&
	  near_mem_imem_exc__85_OR_IF_IF_NOT_near_mem_im_ETC___d964)
	$write("CONTROL_FENCE_I");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full &&
	  near_mem_imem_valid_AND_near_mem_imem_pc_EQ_im_ETC___d484 &&
	  near_mem_imem_exc__85_OR_IF_IF_NOT_near_mem_im_ETC___d967)
	$write("CONTROL_SFENCE_VMA");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full &&
	  near_mem_imem_valid_AND_near_mem_imem_pc_EQ_im_ETC___d484 &&
	  near_mem_imem_exc__85_OR_IF_IF_NOT_near_mem_im_ETC___d970)
	$write("CONTROL_MRET");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full &&
	  near_mem_imem_valid_AND_near_mem_imem_pc_EQ_im_ETC___d484 &&
	  near_mem_imem_exc__85_OR_IF_IF_NOT_near_mem_im_ETC___d973)
	$write("CONTROL_SRET");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full &&
	  near_mem_imem_valid_AND_near_mem_imem_pc_EQ_im_ETC___d484 &&
	  near_mem_imem_exc__85_OR_IF_IF_NOT_near_mem_im_ETC___d976)
	$write("CONTROL_URET");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full &&
	  near_mem_imem_valid_AND_near_mem_imem_pc_EQ_im_ETC___d484 &&
	  near_mem_imem_exc__85_OR_IF_IF_NOT_near_mem_im_ETC___d979)
	$write("CONTROL_WFI");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full &&
	  near_mem_imem_valid_AND_near_mem_imem_pc_EQ_im_ETC___d484 &&
	  near_mem_imem_exc__85_OR_IF_IF_NOT_near_mem_im_ETC___d982)
	$write("CONTROL_TRAP");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full &&
	  near_mem_imem_valid_AND_near_mem_imem_pc_EQ_im_ETC___d685)
	$write("");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe && !stage1_rg_full) $write("");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full &&
	  NOT_near_mem_imem_valid_96_OR_NOT_near_mem_ime_ETC___d469)
	$write("");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full &&
	  near_mem_imem_valid_AND_near_mem_imem_pc_EQ_im_ETC___d636)
	$write(" ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full &&
	  near_mem_imem_valid_AND_near_mem_imem_pc_EQ_im_ETC___d685)
	$write("");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe && !stage1_rg_full) $write("");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full &&
	  NOT_near_mem_imem_valid_96_OR_NOT_near_mem_ime_ETC___d469)
	$write("");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full &&
	  near_mem_imem_valid_AND_near_mem_imem_pc_EQ_im_ETC___d636)
	$write("Trap_Info { ", "epc: ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full &&
	  near_mem_imem_valid_AND_near_mem_imem_pc_EQ_im_ETC___d685)
	$write("");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe && !stage1_rg_full) $write("");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full &&
	  NOT_near_mem_imem_valid_96_OR_NOT_near_mem_ime_ETC___d469)
	$write("");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full &&
	  near_mem_imem_valid_AND_near_mem_imem_pc_EQ_im_ETC___d636)
	$write("'h%h", imem_rg_pc);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full &&
	  near_mem_imem_valid_AND_near_mem_imem_pc_EQ_im_ETC___d685)
	$write("");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe && !stage1_rg_full) $write("");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full &&
	  NOT_near_mem_imem_valid_96_OR_NOT_near_mem_ime_ETC___d469)
	$write("");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full &&
	  near_mem_imem_valid_AND_near_mem_imem_pc_EQ_im_ETC___d636)
	$write(", ", "exc_code: ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full &&
	  near_mem_imem_valid_AND_near_mem_imem_pc_EQ_im_ETC___d685)
	$write("");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe && !stage1_rg_full) $write("");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full &&
	  NOT_near_mem_imem_valid_96_OR_NOT_near_mem_ime_ETC___d469)
	$write("");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full &&
	  near_mem_imem_valid_AND_near_mem_imem_pc_EQ_im_ETC___d636)
	$write("'h%h", x_out_trap_info_exc_code__h13233);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full &&
	  near_mem_imem_valid_AND_near_mem_imem_pc_EQ_im_ETC___d685)
	$write("");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe && !stage1_rg_full) $write("");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full &&
	  NOT_near_mem_imem_valid_96_OR_NOT_near_mem_ime_ETC___d469)
	$write("");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full &&
	  near_mem_imem_valid_AND_near_mem_imem_pc_EQ_im_ETC___d636)
	$write(", ", "tval: ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full &&
	  near_mem_imem_valid_AND_near_mem_imem_pc_EQ_im_ETC___d685)
	$write("");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe && !stage1_rg_full) $write("");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full &&
	  NOT_near_mem_imem_valid_96_OR_NOT_near_mem_ime_ETC___d469)
	$write("");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full &&
	  near_mem_imem_valid_AND_near_mem_imem_pc_EQ_im_ETC___d636)
	$write("'h%h", value__h13281, " }");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full &&
	  near_mem_imem_valid_AND_near_mem_imem_pc_EQ_im_ETC___d685)
	$write("");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe && !stage1_rg_full) $write("");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full &&
	  NOT_near_mem_imem_valid_96_OR_NOT_near_mem_ime_ETC___d469)
	$write("");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full &&
	  near_mem_imem_valid_AND_near_mem_imem_pc_EQ_im_ETC___d484)
	$write(" next_pc 0x%08h", x_out_next_pc__h11584);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe && !stage1_rg_full) $write("");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe) $write("\n");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe) $display("----------------");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_stage2_nonpipe &&
	  NOT_IF_csr_regfile_read_csr_minstret__5_ULT_cf_ETC___d41)
	$display("%0d: CPU.rl_stage2_nonpipe", csr_regfile$read_csr_mcycle);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_stage2_nonpipe && cur_verbosity__h2985 == 4'd1)
	$display("instret:%0d  PC:0x%0h  instr:0x%0h  priv:%0d",
		 csr_regfile$read_csr_minstret,
		 stage2_rg_stage2[167:136],
		 stage2_rg_stage2[135:104],
		 rg_cur_priv);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_stage2_nonpipe && cur_verbosity__h2985 != 4'd0)
	$display("    mcause:0x%0h  epc 0x%0h  tval:0x%0h  new pc 0x%0h, new mstatus 0x%0h",
		 csr_regfile$csr_trap_actions[33:2],
		 stage2_rg_stage2[167:136],
		 stage2_rg_stage2[95:64],
		 csr_regfile$csr_trap_actions[97:66],
		 csr_regfile$csr_trap_actions[65:34]);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_stage1_CSRR_W &&
	  NOT_IF_csr_regfile_read_csr_minstret__5_ULT_cf_ETC___d41)
	$display("%0d: CPU.rl_stage1_CSRR_W", csr_regfile$read_csr_mcycle);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_stage1_CSRR_W && csr_regfile$access_permitted_1 &&
	  cur_verbosity__h2985 == 4'd1)
	$display("instret:%0d  PC:0x%0h  instr:0x%0h  priv:%0d",
		 csr_regfile$read_csr_minstret,
		 imem_rg_pc,
		 x_out_data_to_stage2_instr__h11612,
		 rg_cur_priv);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_stage1_CSRR_W && csr_regfile$access_permitted_1 &&
	  NOT_IF_csr_regfile_read_csr_minstret__5_ULT_cf_ETC___d41)
	$display("    S1: write CSRRW/CSRRWI Rs1 %0d Rs1_val 0x%0h csr 0x%0h csr_val 0x%0h Rd %0d",
		 x_out_data_to_stage2_instr__h11612[19:15],
		 rs1_val__h17231,
		 x_out_data_to_stage2_instr__h11612[31:20],
		 csr_regfile$read_csr[31:0],
		 x_out_data_to_stage2_instr__h11612[11:7]);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_stage1_CSRR_W && !csr_regfile$access_permitted_1 &&
	  cur_verbosity__h2985 == 4'd1)
	$display("instret:%0d  PC:0x%0h  instr:0x%0h  priv:%0d",
		 csr_regfile$read_csr_minstret,
		 imem_rg_pc,
		 x_out_data_to_stage2_instr__h11612,
		 rg_cur_priv);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_stage1_CSRR_W && !csr_regfile$access_permitted_1 &&
	  NOT_IF_csr_regfile_read_csr_minstret__5_ULT_cf_ETC___d41)
	$display("    rl_stage1_CSRR_W: Trap on CSR permissions: Rs1 %0d Rs1_val 0x%0h csr 0x%0h Rd %0d",
		 x_out_data_to_stage2_instr__h11612[19:15],
		 rs1_val__h17231,
		 x_out_data_to_stage2_instr__h11612[31:20],
		 x_out_data_to_stage2_instr__h11612[11:7]);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_stage1_CSRR_S_or_C &&
	  NOT_IF_csr_regfile_read_csr_minstret__5_ULT_cf_ETC___d41)
	$display("%0d: CPU.rl_stage1_CSRR_S_or_C",
		 csr_regfile$read_csr_mcycle);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_stage1_CSRR_S_or_C &&
	  csr_regfile$access_permitted_2 &&
	  cur_verbosity__h2985 == 4'd1)
	$display("instret:%0d  PC:0x%0h  instr:0x%0h  priv:%0d",
		 csr_regfile$read_csr_minstret,
		 imem_rg_pc,
		 x_out_data_to_stage2_instr__h11612,
		 rg_cur_priv);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_stage1_CSRR_S_or_C &&
	  csr_regfile$access_permitted_2 &&
	  NOT_IF_csr_regfile_read_csr_minstret__5_ULT_cf_ETC___d41)
	$display("    S1: write CSRR_S_or_C: Rs1 %0d Rs1_val 0x%0h csr 0x%0h csr_val 0x%0h Rd %0d",
		 x_out_data_to_stage2_instr__h11612[19:15],
		 rs1_val__h17721,
		 x_out_data_to_stage2_instr__h11612[31:20],
		 csr_regfile$read_csr[31:0],
		 x_out_data_to_stage2_instr__h11612[11:7]);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_stage1_CSRR_S_or_C &&
	  !csr_regfile$access_permitted_2 &&
	  cur_verbosity__h2985 == 4'd1)
	$display("instret:%0d  PC:0x%0h  instr:0x%0h  priv:%0d",
		 csr_regfile$read_csr_minstret,
		 imem_rg_pc,
		 x_out_data_to_stage2_instr__h11612,
		 rg_cur_priv);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_stage1_CSRR_S_or_C &&
	  !csr_regfile$access_permitted_2 &&
	  NOT_IF_csr_regfile_read_csr_minstret__5_ULT_cf_ETC___d41)
	$display("    rl_stage1_CSRR_S_or_C: Trap on CSR permissions: Rs1 %0d Rs1_val 0x%0h csr 0x%0h Rd %0d",
		 x_out_data_to_stage2_instr__h11612[19:15],
		 rs1_val__h17721,
		 x_out_data_to_stage2_instr__h11612[31:20],
		 x_out_data_to_stage2_instr__h11612[11:7]);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_stage1_restart_after_csrrx &&
	  NOT_IF_csr_regfile_read_csr_minstret__5_ULT_cf_ETC___d41)
	$display("    CPU_Stage1.enq: 0x%08h", x_out_next_pc__h11584);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_stage1_restart_after_csrrx &&
	  NOT_IF_csr_regfile_read_csr_minstret__5_ULT_cf_ETC___d41)
	$display("%0d: rl_stage1_restart_after_csrrx: minstret:%0d  pc:%0x  cur_priv:%0d",
		 csr_regfile$read_csr_mcycle,
		 csr_regfile$read_csr_minstret,
		 x_out_next_pc__h11584,
		 rg_cur_priv);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_stage1_xRET &&
	  NOT_IF_csr_regfile_read_csr_minstret__5_ULT_cf_ETC___d41)
	$display("%0d: CPU.rl_stage1_xRET", csr_regfile$read_csr_mcycle);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_stage1_xRET && cur_verbosity__h2985 == 4'd1)
	$display("instret:%0d  PC:0x%0h  instr:0x%0h  priv:%0d",
		 csr_regfile$read_csr_minstret,
		 imem_rg_pc,
		 x_out_data_to_stage2_instr__h11612,
		 rg_cur_priv);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_stage1_xRET && cur_verbosity__h2985 != 4'd0)
	$display("    xRET: next_pc:0x%0h  new mstatus:0x%0h  new priv:%0d",
		 csr_regfile$csr_ret_actions[65:34],
		 csr_regfile$csr_ret_actions[31:0],
		 csr_regfile$csr_ret_actions[33:32]);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_stage1_FENCE_I &&
	  NOT_IF_csr_regfile_read_csr_minstret__5_ULT_cf_ETC___d41)
	$display("%0d: CPU.rl_stage1_FENCE_I", csr_regfile$read_csr_mcycle);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_stage1_FENCE_I && cur_verbosity__h2985 == 4'd1)
	$display("instret:%0d  PC:0x%0h  instr:0x%0h  priv:%0d",
		 csr_regfile$read_csr_minstret,
		 imem_rg_pc,
		 x_out_data_to_stage2_instr__h11612,
		 rg_cur_priv);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_stage1_FENCE_I &&
	  NOT_IF_csr_regfile_read_csr_minstret__5_ULT_cf_ETC___d41)
	$display("%0d: CPU.rl_stage1_FENCE_I", csr_regfile$read_csr_mcycle);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_finish_FENCE_I &&
	  NOT_IF_csr_regfile_read_csr_minstret__5_ULT_cf_ETC___d41)
	$display("%0d: CPU.rl_finish_FENCE_I", csr_regfile$read_csr_mcycle);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_finish_FENCE_I &&
	  NOT_IF_csr_regfile_read_csr_minstret__5_ULT_cf_ETC___d41)
	$display("    CPU_Stage1.enq: 0x%08h", rg_next_pc);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_finish_FENCE_I &&
	  NOT_IF_csr_regfile_read_csr_minstret__5_ULT_cf_ETC___d41)
	$display("    CPU.rl_finish_FENCE_I");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_stage1_FENCE &&
	  NOT_IF_csr_regfile_read_csr_minstret__5_ULT_cf_ETC___d41)
	$display("%0d: CPU.rl_stage1_FENCE", csr_regfile$read_csr_mcycle);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_stage1_FENCE && cur_verbosity__h2985 == 4'd1)
	$display("instret:%0d  PC:0x%0h  instr:0x%0h  priv:%0d",
		 csr_regfile$read_csr_minstret,
		 imem_rg_pc,
		 x_out_data_to_stage2_instr__h11612,
		 rg_cur_priv);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_stage1_FENCE &&
	  NOT_IF_csr_regfile_read_csr_minstret__5_ULT_cf_ETC___d41)
	$display("%0d: CPU.rl_stage1_FENCE", csr_regfile$read_csr_mcycle);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_finish_FENCE &&
	  NOT_IF_csr_regfile_read_csr_minstret__5_ULT_cf_ETC___d41)
	$display("%0d: CPU.rl_finish_FENCE", csr_regfile$read_csr_mcycle);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_finish_FENCE &&
	  NOT_IF_csr_regfile_read_csr_minstret__5_ULT_cf_ETC___d41)
	$display("    CPU_Stage1.enq: 0x%08h", rg_next_pc);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_finish_FENCE &&
	  NOT_IF_csr_regfile_read_csr_minstret__5_ULT_cf_ETC___d41)
	$display("    CPU.rl_finish_FENCE");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_stage1_SFENCE_VMA &&
	  NOT_IF_csr_regfile_read_csr_minstret__5_ULT_cf_ETC___d41)
	$display("%0d: CPU.rl_stage1_SFENCE_VMA",
		 csr_regfile$read_csr_mcycle);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_stage1_SFENCE_VMA && cur_verbosity__h2985 == 4'd1)
	$display("instret:%0d  PC:0x%0h  instr:0x%0h  priv:%0d",
		 csr_regfile$read_csr_minstret,
		 imem_rg_pc,
		 x_out_data_to_stage2_instr__h11612,
		 rg_cur_priv);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_stage1_SFENCE_VMA &&
	  NOT_IF_csr_regfile_read_csr_minstret__5_ULT_cf_ETC___d41)
	$display("%0d: CPU.rl_stage1_SFENCE_VMA",
		 csr_regfile$read_csr_mcycle);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_finish_SFENCE_VMA &&
	  NOT_IF_csr_regfile_read_csr_minstret__5_ULT_cf_ETC___d41)
	$display("%0d: CPU.rl_finish_SFENCE_VMA",
		 csr_regfile$read_csr_mcycle);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_finish_SFENCE_VMA &&
	  NOT_IF_csr_regfile_read_csr_minstret__5_ULT_cf_ETC___d41)
	$display("    CPU_Stage1.enq: 0x%08h", rg_next_pc);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_finish_SFENCE_VMA &&
	  NOT_IF_csr_regfile_read_csr_minstret__5_ULT_cf_ETC___d41)
	$display("    CPU.rl_finish_SFENCE_VMA");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_stage1_WFI &&
	  NOT_IF_csr_regfile_read_csr_minstret__5_ULT_cf_ETC___d41)
	$display("%0d: CPU.rl_stage1_WFI", csr_regfile$read_csr_mcycle);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_stage1_WFI && cur_verbosity__h2985 == 4'd1)
	$display("instret:%0d  PC:0x%0h  instr:0x%0h  priv:%0d",
		 csr_regfile$read_csr_minstret,
		 imem_rg_pc,
		 x_out_data_to_stage2_instr__h11612,
		 rg_cur_priv);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_stage1_WFI &&
	  NOT_IF_csr_regfile_read_csr_minstret__5_ULT_cf_ETC___d41)
	$display("    CPU.rl_stage1_WFI");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_WFI_resume &&
	  NOT_IF_csr_regfile_read_csr_minstret__5_ULT_cf_ETC___d41)
	$display("%0d: CPU.rl_WFI_resume", csr_regfile$read_csr_mcycle);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_WFI_resume && cur_verbosity__h2985 != 4'd0)
	$display("    WFI resume");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_WFI_resume &&
	  NOT_IF_csr_regfile_read_csr_minstret__5_ULT_cf_ETC___d41)
	$display("    CPU_Stage1.enq: 0x%08h", rg_next_pc);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_reset_from_WFI &&
	  NOT_IF_csr_regfile_read_csr_minstret__5_ULT_cf_ETC___d41)
	$display("%0d: CPU.rl_reset_from_WFI", csr_regfile$read_csr_mcycle);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_stage1_trap &&
	  NOT_IF_csr_regfile_read_csr_minstret__5_ULT_cf_ETC___d41)
	$display("%0d: CPU.rl_stage1_trap", csr_regfile$read_csr_mcycle);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_stage1_trap &&
	  IF_NOT_stage1_rg_full_94_95_OR_NOT_near_mem_im_ETC___d1270)
	$display("%0d: CPU.rl_stage1_trap: Tight infinite trap loop: pc 0x%0x instr 0x%08x",
		 csr_regfile$read_csr_mcycle,
		 csr_regfile$csr_trap_actions[97:66],
		 x_out_data_to_stage2_instr__h11612);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_stage1_trap &&
	  IF_NOT_stage1_rg_full_94_95_OR_NOT_near_mem_im_ETC___d1270)
	$display("CPI: %0d.%0d = (%0d/%0d) since last 'continue'",
		 cpi__h22287,
		 cpifrac__h22288,
		 delta_CPI_cycles__h22283,
		 _theResult____h22285);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_stage1_trap &&
	  IF_NOT_stage1_rg_full_94_95_OR_NOT_near_mem_im_ETC___d1270)
	$finish(32'd0);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_stage1_trap && cur_verbosity__h2985 == 4'd1)
	$display("instret:%0d  PC:0x%0h  instr:0x%0h  priv:%0d",
		 csr_regfile$read_csr_minstret,
		 imem_rg_pc,
		 x_out_data_to_stage2_instr__h11612,
		 rg_cur_priv);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_stage1_trap && cur_verbosity__h2985 != 4'd0)
	$display("%0d: CPU.rl_stage1_trap: priv:%0d  mcause:0x%0h  epc:0x%0h",
		 csr_regfile$read_csr_mcycle,
		 rg_cur_priv,
		 csr_regfile$csr_trap_actions[33:2],
		 imem_rg_pc);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_stage1_trap && cur_verbosity__h2985 != 4'd0)
	$display("    tval:0x%0h  new pc:0x%0h  new mstatus:0x%0h",
		 value__h13281,
		 csr_regfile$csr_trap_actions[97:66],
		 csr_regfile$csr_trap_actions[65:34]);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_trap_fetch &&
	  NOT_IF_csr_regfile_read_csr_minstret__5_ULT_cf_ETC___d41)
	$display("    CPU_Stage1.enq: 0x%08h", rg_next_pc);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_stage1_interrupt &&
	  NOT_IF_csr_regfile_read_csr_minstret__5_ULT_cf_ETC___d41)
	$display("%0d: CPU.rl_stage1_interrupt", csr_regfile$read_csr_mcycle);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_stage1_interrupt && cur_verbosity__h2985 == 4'd1)
	$display("instret:%0d  PC:0x%0h  instr:0x%0h  priv:%0d",
		 csr_regfile$read_csr_minstret,
		 imem_rg_pc,
		 x_out_data_to_stage2_instr__h11612,
		 rg_cur_priv);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_stage1_interrupt && cur_verbosity__h2985 != 4'd0)
	$display("%0d: CPU.rl_stage1_interrupt: epc 0x%0h  next PC 0x%0h  new_priv %0d  new mstatus 0x%0h",
		 csr_regfile$read_csr_mcycle,
		 imem_rg_pc,
		 csr_regfile$csr_trap_actions[97:66],
		 csr_regfile$csr_trap_actions[1:0],
		 csr_regfile$csr_trap_actions[65:34]);
    if (WILL_FIRE_RL_imem_rl_assert_fail)
      $display("ERROR: CPU_Fetch_C: imem32.is_i32_not_i16 is False");
    if (WILL_FIRE_RL_imem_rl_assert_fail) $finish(32'd1);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_reset_complete && rg_run_on_reset &&
	  NOT_IF_csr_regfile_read_csr_minstret__5_ULT_cf_ETC___d41)
	$display("    CPU_Stage1.enq: 0x%08h",
		 soc_map$m_pc_reset_value[31:0]);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_reset_complete && rg_run_on_reset)
	$display("%0d: CPU.rl_reset_complete: restart at PC = 0x%0h",
		 csr_regfile$read_csr_mcycle,
		 soc_map$m_pc_reset_value[31:0]);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_reset_complete && !rg_run_on_reset)
	$display("%0d: CPU.rl_reset_complete: entering DEBUG_MODE",
		 csr_regfile$read_csr_mcycle);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_pipe &&
	  NOT_IF_csr_regfile_read_csr_minstret__5_ULT_cf_ETC___d41)
	$display("%0d: CPU.rl_pipe", csr_regfile$read_csr_mcycle);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_pipe && stage3_rg_full && stage3_rg_stage3[37] &&
	  NOT_IF_csr_regfile_read_csr_minstret__5_ULT_cf_ETC___d41)
	$display("    S3.fa_deq: write GRd 0x%0h, rd_val 0x%0h",
		 stage3_rg_stage3[36:32],
		 stage3_rg_stage3[31:0]);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_pipe &&
	  IF_stage2_rg_full_7_THEN_IF_stage2_rg_stage2_8_ETC___d118 == 2'd2 &&
	  NOT_IF_csr_regfile_read_csr_minstret__5_ULT_cf_ETC___d41)
	$write("    S3.enq: ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_pipe &&
	  IF_stage2_rg_full_7_THEN_IF_stage2_rg_stage2_8_ETC___d118 == 2'd2 &&
	  NOT_IF_csr_regfile_read_csr_minstret__5_ULT_cf_ETC___d41)
	$write("data_to_Stage3 {pc:%h  instr:%h  priv:%0d\n",
	       stage2_rg_stage2[167:136],
	       stage2_rg_stage2[135:104],
	       stage2_rg_stage2[169:168]);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_pipe &&
	  IF_stage2_rg_full_7_THEN_IF_stage2_rg_stage2_8_ETC___d118 == 2'd2 &&
	  NOT_IF_csr_regfile_read_csr_minstret__5_ULT_cf_ETC___d41)
	$write("        rd_valid:");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_pipe &&
	  IF_stage2_rg_full_7_THEN_IF_stage2_rg_stage2_8_ETC___d118 == 2'd2 &&
	  NOT_IF_csr_regfile_read_csr_minstret__5_ULT_cf_ETC___d41 &&
	  stage2_rg_stage2[103:101] != 3'd0 &&
	  IF_stage2_rg_stage2_8_BITS_103_TO_101_9_EQ_1_1_ETC___d132)
	$write("False");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_pipe &&
	  IF_stage2_rg_full_7_THEN_IF_stage2_rg_stage2_8_ETC___d118 == 2'd2 &&
	  NOT_IF_csr_regfile_read_csr_minstret__5_ULT_cf_ETC___d41 &&
	  (stage2_rg_stage2[103:101] == 3'd0 ||
	   IF_stage2_rg_stage2_8_BITS_103_TO_101_9_EQ_1_1_ETC___d141))
	$write("True");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_pipe &&
	  IF_stage2_rg_full_7_THEN_IF_stage2_rg_stage2_8_ETC___d118 == 2'd2 &&
	  NOT_IF_csr_regfile_read_csr_minstret__5_ULT_cf_ETC___d41)
	$write("  grd:%0d  rd_val:%h\n",
	       x_out_data_to_stage3_rd__h5641,
	       x_out_data_to_stage3_rd_val__h5642);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_pipe &&
	  IF_stage2_rg_full_7_THEN_IF_stage2_rg_stage2_8_ETC___d118 == 2'd2 &&
	  NOT_IF_csr_regfile_read_csr_minstret__5_ULT_cf_ETC___d41)
	$write("\n");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_pipe &&
	  IF_stage2_rg_full_7_THEN_IF_stage2_rg_stage2_8_ETC___d118 == 2'd2 &&
	  cur_verbosity__h2985 == 4'd1)
	$display("instret:%0d  PC:0x%0h  instr:0x%0h  priv:%0d",
		 csr_regfile$read_csr_minstret,
		 stage2_rg_stage2[167:136],
		 stage2_rg_stage2[135:104],
		 rg_cur_priv);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_pipe &&
	  NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d1133 &&
	  NOT_IF_csr_regfile_read_csr_minstret__5_ULT_cf_ETC___d41)
	$display("    CPU_Stage2.enq (Data_Stage1_to_Stage2)");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_pipe &&
	  NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d1112 &&
	  NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d1154 &&
	  NOT_IF_csr_regfile_read_csr_minstret__5_ULT_cf_ETC___d41)
	$display("    CPU_Stage1.enq: 0x%08h", x_out_next_pc__h11584);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_reset_start)
	$display("================================================================");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_reset_start)
	$write("CPU: Bluespec  RISC-V  Piccolo  v3.0");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_reset_start) $display(" (RV32)");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_reset_start)
	$display("Copyright (c) 2016-2019 Bluespec, Inc. All Rights Reserved.");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_reset_start)
	$display("================================================================");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_reset_start && cur_verbosity__h2985 != 4'd0)
	$display("%0d: CPU.rl_reset_start", csr_regfile$read_csr_mcycle);
  end
  // synopsys translate_on
endmodule  // mkCPU

