//
// Generated by Bluespec Compiler, version 2018.10.beta1 (build e1df8052c, 2018-10-17)
//
//
//
//
// Ports:
// Name                         I/O  size props
// RDY_server_core_request_put    O     1 reg
// server_core_response_get       O    70 reg
// RDY_server_core_response_get   O     1 reg
// RDY_server_reset_request_put   O     1 reg
// RDY_server_reset_response_get  O     1 reg
// CLK                            I     1 clock
// RST_N                          I     1 reset
// server_core_request_put        I   202 reg
// EN_server_core_request_put     I     1
// EN_server_reset_request_put    I     1
// EN_server_reset_response_get   I     1
// EN_server_core_response_get    I     1
//
// No combinational paths from inputs to outputs
//
//

`ifdef BSV_ASSIGNMENT_DELAY
`else
  `define BSV_ASSIGNMENT_DELAY
`endif

`ifdef BSV_POSITIVE_RESET
  `define BSV_RESET_VALUE 1'b1
  `define BSV_RESET_EDGE posedge
`else
  `define BSV_RESET_VALUE 1'b0
  `define BSV_RESET_EDGE negedge
`endif

module mkFPU(CLK,
	     RST_N,

	     server_core_request_put,
	     EN_server_core_request_put,
	     RDY_server_core_request_put,

	     EN_server_core_response_get,
	     server_core_response_get,
	     RDY_server_core_response_get,

	     EN_server_reset_request_put,
	     RDY_server_reset_request_put,

	     EN_server_reset_response_get,
	     RDY_server_reset_response_get);
  input  CLK;
  input  RST_N;

  // action method server_core_request_put
  input  [201 : 0] server_core_request_put;
  input  EN_server_core_request_put;
  output RDY_server_core_request_put;

  // actionvalue method server_core_response_get
  input  EN_server_core_response_get;
  output [69 : 0] server_core_response_get;
  output RDY_server_core_response_get;

  // action method server_reset_request_put
  input  EN_server_reset_request_put;
  output RDY_server_reset_request_put;

  // action method server_reset_response_get
  input  EN_server_reset_response_get;
  output RDY_server_reset_response_get;

  // signals for module outputs
  wire [69 : 0] server_core_response_get;
  wire RDY_server_core_request_put,
       RDY_server_core_response_get,
       RDY_server_reset_request_put,
       RDY_server_reset_response_get;

  // inlined wires
  reg [68 : 0] resWire$wget;
  wire crg_done$EN_port0__write,
       crg_done$EN_port1__write,
       crg_done$port1__read,
       crg_done$port2__read,
       crg_done_1$EN_port0__write,
       crg_done_1$EN_port1__write,
       crg_done_1$port1__read,
       crg_done_1$port2__read,
       resWire$whas;

  // register crg_done
  reg crg_done;
  wire crg_done$D_IN, crg_done$EN;

  // register crg_done_1
  reg crg_done_1;
  wire crg_done_1$D_IN, crg_done_1$EN;

  // register rg_b
  reg [115 : 0] rg_b;
  wire [115 : 0] rg_b$D_IN;
  wire rg_b$EN;

  // register rg_busy
  reg rg_busy;
  wire rg_busy$D_IN, rg_busy$EN;

  // register rg_busy_1
  reg rg_busy_1;
  wire rg_busy_1$D_IN, rg_busy_1$EN;

  // register rg_d
  reg [57 : 0] rg_d;
  wire [57 : 0] rg_d$D_IN;
  wire rg_d$EN;

  // register rg_index
  reg [5 : 0] rg_index;
  wire [5 : 0] rg_index$D_IN;
  wire rg_index$EN;

  // register rg_index_1
  reg [5 : 0] rg_index_1;
  wire [5 : 0] rg_index_1$D_IN;
  wire rg_index_1$EN;

  // register rg_q
  reg [57 : 0] rg_q;
  wire [57 : 0] rg_q$D_IN;
  wire rg_q$EN;

  // register rg_r
  reg [115 : 0] rg_r;
  wire [115 : 0] rg_r$D_IN;
  wire rg_r$EN;

  // register rg_r_1
  reg [115 : 0] rg_r_1;
  wire [115 : 0] rg_r_1$D_IN;
  wire rg_r_1$EN;

  // register rg_res
  reg [116 : 0] rg_res;
  wire [116 : 0] rg_res$D_IN;
  wire rg_res$EN;

  // register rg_s
  reg [115 : 0] rg_s;
  wire [115 : 0] rg_s$D_IN;
  wire rg_s$EN;

  // ports of submodule fpu_div64_fOperands_S0
  wire [130 : 0] fpu_div64_fOperands_S0$D_IN, fpu_div64_fOperands_S0$D_OUT;
  wire fpu_div64_fOperands_S0$CLR,
       fpu_div64_fOperands_S0$DEQ,
       fpu_div64_fOperands_S0$EMPTY_N,
       fpu_div64_fOperands_S0$ENQ,
       fpu_div64_fOperands_S0$FULL_N;

  // ports of submodule fpu_div64_fResult_S5
  wire [68 : 0] fpu_div64_fResult_S5$D_IN, fpu_div64_fResult_S5$D_OUT;
  wire fpu_div64_fResult_S5$CLR,
       fpu_div64_fResult_S5$DEQ,
       fpu_div64_fResult_S5$EMPTY_N,
       fpu_div64_fResult_S5$ENQ,
       fpu_div64_fResult_S5$FULL_N;

  // ports of submodule fpu_div64_fState_S1
  wire [318 : 0] fpu_div64_fState_S1$D_IN, fpu_div64_fState_S1$D_OUT;
  wire fpu_div64_fState_S1$CLR,
       fpu_div64_fState_S1$DEQ,
       fpu_div64_fState_S1$EMPTY_N,
       fpu_div64_fState_S1$ENQ,
       fpu_div64_fState_S1$FULL_N;

  // ports of submodule fpu_div64_fState_S2
  wire [147 : 0] fpu_div64_fState_S2$D_IN, fpu_div64_fState_S2$D_OUT;
  wire fpu_div64_fState_S2$CLR,
       fpu_div64_fState_S2$DEQ,
       fpu_div64_fState_S2$EMPTY_N,
       fpu_div64_fState_S2$ENQ,
       fpu_div64_fState_S2$FULL_N;

  // ports of submodule fpu_div64_fState_S3
  wire [194 : 0] fpu_div64_fState_S3$D_IN, fpu_div64_fState_S3$D_OUT;
  wire fpu_div64_fState_S3$CLR,
       fpu_div64_fState_S3$DEQ,
       fpu_div64_fState_S3$EMPTY_N,
       fpu_div64_fState_S3$ENQ,
       fpu_div64_fState_S3$FULL_N;

  // ports of submodule fpu_div64_fState_S4
  wire [138 : 0] fpu_div64_fState_S4$D_IN, fpu_div64_fState_S4$D_OUT;
  wire fpu_div64_fState_S4$CLR,
       fpu_div64_fState_S4$DEQ,
       fpu_div64_fState_S4$EMPTY_N,
       fpu_div64_fState_S4$ENQ,
       fpu_div64_fState_S4$FULL_N;

  // ports of submodule fpu_madd_fOperand_S0
  wire [195 : 0] fpu_madd_fOperand_S0$D_IN, fpu_madd_fOperand_S0$D_OUT;
  wire fpu_madd_fOperand_S0$CLR,
       fpu_madd_fOperand_S0$DEQ,
       fpu_madd_fOperand_S0$EMPTY_N,
       fpu_madd_fOperand_S0$ENQ,
       fpu_madd_fOperand_S0$FULL_N;

  // ports of submodule fpu_madd_fProd_S2
  wire [105 : 0] fpu_madd_fProd_S2$D_IN, fpu_madd_fProd_S2$D_OUT;
  wire fpu_madd_fProd_S2$CLR,
       fpu_madd_fProd_S2$DEQ,
       fpu_madd_fProd_S2$EMPTY_N,
       fpu_madd_fProd_S2$ENQ,
       fpu_madd_fProd_S2$FULL_N;

  // ports of submodule fpu_madd_fProd_S3
  wire [105 : 0] fpu_madd_fProd_S3$D_IN, fpu_madd_fProd_S3$D_OUT;
  wire fpu_madd_fProd_S3$CLR,
       fpu_madd_fProd_S3$DEQ,
       fpu_madd_fProd_S3$EMPTY_N,
       fpu_madd_fProd_S3$ENQ,
       fpu_madd_fProd_S3$FULL_N;

  // ports of submodule fpu_madd_fResult_S9
  wire [68 : 0] fpu_madd_fResult_S9$D_IN, fpu_madd_fResult_S9$D_OUT;
  wire fpu_madd_fResult_S9$CLR,
       fpu_madd_fResult_S9$DEQ,
       fpu_madd_fResult_S9$EMPTY_N,
       fpu_madd_fResult_S9$ENQ,
       fpu_madd_fResult_S9$FULL_N;

  // ports of submodule fpu_madd_fState_S1
  wire [257 : 0] fpu_madd_fState_S1$D_IN, fpu_madd_fState_S1$D_OUT;
  wire fpu_madd_fState_S1$CLR,
       fpu_madd_fState_S1$DEQ,
       fpu_madd_fState_S1$EMPTY_N,
       fpu_madd_fState_S1$ENQ,
       fpu_madd_fState_S1$FULL_N;

  // ports of submodule fpu_madd_fState_S2
  wire [151 : 0] fpu_madd_fState_S2$D_IN, fpu_madd_fState_S2$D_OUT;
  wire fpu_madd_fState_S2$CLR,
       fpu_madd_fState_S2$DEQ,
       fpu_madd_fState_S2$EMPTY_N,
       fpu_madd_fState_S2$ENQ,
       fpu_madd_fState_S2$FULL_N;

  // ports of submodule fpu_madd_fState_S3
  wire [151 : 0] fpu_madd_fState_S3$D_IN, fpu_madd_fState_S3$D_OUT;
  wire fpu_madd_fState_S3$CLR,
       fpu_madd_fState_S3$DEQ,
       fpu_madd_fState_S3$EMPTY_N,
       fpu_madd_fState_S3$ENQ,
       fpu_madd_fState_S3$FULL_N;

  // ports of submodule fpu_madd_fState_S4
  wire [203 : 0] fpu_madd_fState_S4$D_IN, fpu_madd_fState_S4$D_OUT;
  wire fpu_madd_fState_S4$CLR,
       fpu_madd_fState_S4$DEQ,
       fpu_madd_fState_S4$EMPTY_N,
       fpu_madd_fState_S4$ENQ,
       fpu_madd_fState_S4$FULL_N;

  // ports of submodule fpu_madd_fState_S5
  wire [215 : 0] fpu_madd_fState_S5$D_IN, fpu_madd_fState_S5$D_OUT;
  wire fpu_madd_fState_S5$CLR,
       fpu_madd_fState_S5$DEQ,
       fpu_madd_fState_S5$EMPTY_N,
       fpu_madd_fState_S5$ENQ,
       fpu_madd_fState_S5$FULL_N;

  // ports of submodule fpu_madd_fState_S6
  wire [202 : 0] fpu_madd_fState_S6$D_IN, fpu_madd_fState_S6$D_OUT;
  wire fpu_madd_fState_S6$CLR,
       fpu_madd_fState_S6$DEQ,
       fpu_madd_fState_S6$EMPTY_N,
       fpu_madd_fState_S6$ENQ,
       fpu_madd_fState_S6$FULL_N;

  // ports of submodule fpu_madd_fState_S7
  wire [202 : 0] fpu_madd_fState_S7$D_IN, fpu_madd_fState_S7$D_OUT;
  wire fpu_madd_fState_S7$CLR,
       fpu_madd_fState_S7$DEQ,
       fpu_madd_fState_S7$EMPTY_N,
       fpu_madd_fState_S7$ENQ,
       fpu_madd_fState_S7$FULL_N;

  // ports of submodule fpu_madd_fState_S8
  wire [140 : 0] fpu_madd_fState_S8$D_IN, fpu_madd_fState_S8$D_OUT;
  wire fpu_madd_fState_S8$CLR,
       fpu_madd_fState_S8$DEQ,
       fpu_madd_fState_S8$EMPTY_N,
       fpu_madd_fState_S8$ENQ,
       fpu_madd_fState_S8$FULL_N;

  // ports of submodule fpu_sqr64_fOperand_S0
  wire [66 : 0] fpu_sqr64_fOperand_S0$D_IN, fpu_sqr64_fOperand_S0$D_OUT;
  wire fpu_sqr64_fOperand_S0$CLR,
       fpu_sqr64_fOperand_S0$DEQ,
       fpu_sqr64_fOperand_S0$EMPTY_N,
       fpu_sqr64_fOperand_S0$ENQ,
       fpu_sqr64_fOperand_S0$FULL_N;

  // ports of submodule fpu_sqr64_fResult_S5
  wire [68 : 0] fpu_sqr64_fResult_S5$D_IN, fpu_sqr64_fResult_S5$D_OUT;
  wire fpu_sqr64_fResult_S5$CLR,
       fpu_sqr64_fResult_S5$DEQ,
       fpu_sqr64_fResult_S5$EMPTY_N,
       fpu_sqr64_fResult_S5$ENQ,
       fpu_sqr64_fResult_S5$FULL_N;

  // ports of submodule fpu_sqr64_fState_S1
  wire [194 : 0] fpu_sqr64_fState_S1$D_IN, fpu_sqr64_fState_S1$D_OUT;
  wire fpu_sqr64_fState_S1$CLR,
       fpu_sqr64_fState_S1$DEQ,
       fpu_sqr64_fState_S1$EMPTY_N,
       fpu_sqr64_fState_S1$ENQ,
       fpu_sqr64_fState_S1$FULL_N;

  // ports of submodule fpu_sqr64_fState_S2
  wire [136 : 0] fpu_sqr64_fState_S2$D_IN, fpu_sqr64_fState_S2$D_OUT;
  wire fpu_sqr64_fState_S2$CLR,
       fpu_sqr64_fState_S2$DEQ,
       fpu_sqr64_fState_S2$EMPTY_N,
       fpu_sqr64_fState_S2$ENQ,
       fpu_sqr64_fState_S2$FULL_N;

  // ports of submodule fpu_sqr64_fState_S3
  wire [195 : 0] fpu_sqr64_fState_S3$D_IN, fpu_sqr64_fState_S3$D_OUT;
  wire fpu_sqr64_fState_S3$CLR,
       fpu_sqr64_fState_S3$DEQ,
       fpu_sqr64_fState_S3$EMPTY_N,
       fpu_sqr64_fState_S3$ENQ,
       fpu_sqr64_fState_S3$FULL_N;

  // ports of submodule fpu_sqr64_fState_S4
  wire [138 : 0] fpu_sqr64_fState_S4$D_IN, fpu_sqr64_fState_S4$D_OUT;
  wire fpu_sqr64_fState_S4$CLR,
       fpu_sqr64_fState_S4$DEQ,
       fpu_sqr64_fState_S4$EMPTY_N,
       fpu_sqr64_fState_S4$ENQ,
       fpu_sqr64_fState_S4$FULL_N;

  // ports of submodule iFifo
  wire [201 : 0] iFifo$D_IN, iFifo$D_OUT;
  wire iFifo$CLR, iFifo$DEQ, iFifo$EMPTY_N, iFifo$ENQ, iFifo$FULL_N;

  // ports of submodule isDoubleFifo
  wire isDoubleFifo$CLR,
       isDoubleFifo$DEQ,
       isDoubleFifo$D_IN,
       isDoubleFifo$D_OUT,
       isDoubleFifo$EMPTY_N,
       isDoubleFifo$ENQ,
       isDoubleFifo$FULL_N;

  // ports of submodule isNegateFifo
  wire isNegateFifo$CLR,
       isNegateFifo$DEQ,
       isNegateFifo$D_IN,
       isNegateFifo$D_OUT,
       isNegateFifo$EMPTY_N,
       isNegateFifo$ENQ,
       isNegateFifo$FULL_N;

  // ports of submodule oFifo
  wire [69 : 0] oFifo$D_IN, oFifo$D_OUT;
  wire oFifo$CLR, oFifo$DEQ, oFifo$EMPTY_N, oFifo$ENQ, oFifo$FULL_N;

  // ports of submodule resetReqsF
  wire resetReqsF$CLR,
       resetReqsF$DEQ,
       resetReqsF$EMPTY_N,
       resetReqsF$ENQ,
       resetReqsF$FULL_N;

  // ports of submodule resetRspsF
  wire resetRspsF$CLR,
       resetRspsF$DEQ,
       resetRspsF$EMPTY_N,
       resetRspsF$ENQ,
       resetRspsF$FULL_N;

  // ports of submodule rmdFifo
  wire [2 : 0] rmdFifo$D_IN, rmdFifo$D_OUT;
  wire rmdFifo$CLR, rmdFifo$DEQ, rmdFifo$EMPTY_N, rmdFifo$ENQ, rmdFifo$FULL_N;

  // rule scheduling signals
  wire CAN_FIRE_RL_fpu_div64_s1_stage,
       CAN_FIRE_RL_fpu_div64_s2_stage,
       CAN_FIRE_RL_fpu_div64_s3_stage,
       CAN_FIRE_RL_fpu_div64_s4_stage,
       CAN_FIRE_RL_fpu_div64_s5_stage,
       CAN_FIRE_RL_fpu_madd_s1_stage,
       CAN_FIRE_RL_fpu_madd_s2_stage,
       CAN_FIRE_RL_fpu_madd_s3_stage,
       CAN_FIRE_RL_fpu_madd_s4_stage,
       CAN_FIRE_RL_fpu_madd_s5_stage,
       CAN_FIRE_RL_fpu_madd_s6_stage,
       CAN_FIRE_RL_fpu_madd_s7_stage,
       CAN_FIRE_RL_fpu_madd_s8_stage,
       CAN_FIRE_RL_fpu_madd_s9_stage,
       CAN_FIRE_RL_fpu_sqr64_s1_stage,
       CAN_FIRE_RL_fpu_sqr64_s2_stage,
       CAN_FIRE_RL_fpu_sqr64_s3_stage,
       CAN_FIRE_RL_fpu_sqr64_s4_stage,
       CAN_FIRE_RL_fpu_sqr64_s5_stage,
       CAN_FIRE_RL_getResDiv,
       CAN_FIRE_RL_getResMAdd,
       CAN_FIRE_RL_getResSqr,
       CAN_FIRE_RL_passResult,
       CAN_FIRE_RL_rl_reset,
       CAN_FIRE_RL_start_op,
       CAN_FIRE_RL_work,
       CAN_FIRE_RL_work_1,
       CAN_FIRE___me_check_22,
       CAN_FIRE___me_check_23,
       CAN_FIRE_server_core_request_put,
       CAN_FIRE_server_core_response_get,
       CAN_FIRE_server_reset_request_put,
       CAN_FIRE_server_reset_response_get,
       WILL_FIRE_RL_fpu_div64_s1_stage,
       WILL_FIRE_RL_fpu_div64_s2_stage,
       WILL_FIRE_RL_fpu_div64_s3_stage,
       WILL_FIRE_RL_fpu_div64_s4_stage,
       WILL_FIRE_RL_fpu_div64_s5_stage,
       WILL_FIRE_RL_fpu_madd_s1_stage,
       WILL_FIRE_RL_fpu_madd_s2_stage,
       WILL_FIRE_RL_fpu_madd_s3_stage,
       WILL_FIRE_RL_fpu_madd_s4_stage,
       WILL_FIRE_RL_fpu_madd_s5_stage,
       WILL_FIRE_RL_fpu_madd_s6_stage,
       WILL_FIRE_RL_fpu_madd_s7_stage,
       WILL_FIRE_RL_fpu_madd_s8_stage,
       WILL_FIRE_RL_fpu_madd_s9_stage,
       WILL_FIRE_RL_fpu_sqr64_s1_stage,
       WILL_FIRE_RL_fpu_sqr64_s2_stage,
       WILL_FIRE_RL_fpu_sqr64_s3_stage,
       WILL_FIRE_RL_fpu_sqr64_s4_stage,
       WILL_FIRE_RL_fpu_sqr64_s5_stage,
       WILL_FIRE_RL_getResDiv,
       WILL_FIRE_RL_getResMAdd,
       WILL_FIRE_RL_getResSqr,
       WILL_FIRE_RL_passResult,
       WILL_FIRE_RL_rl_reset,
       WILL_FIRE_RL_start_op,
       WILL_FIRE_RL_work,
       WILL_FIRE_RL_work_1,
       WILL_FIRE___me_check_22,
       WILL_FIRE___me_check_23,
       WILL_FIRE_server_core_request_put,
       WILL_FIRE_server_core_response_get,
       WILL_FIRE_server_reset_request_put,
       WILL_FIRE_server_reset_response_get;

  // inputs to muxes for submodule ports
  wire [116 : 0] MUX_rg_res$write_1__VAL_2;
  wire [115 : 0] MUX_rg_b$write_1__VAL_1,
		 MUX_rg_b$write_1__VAL_2,
		 MUX_rg_r$write_1__VAL_1,
		 MUX_rg_r$write_1__VAL_2,
		 MUX_rg_r_1$write_1__VAL_2,
		 MUX_rg_s$write_1__VAL_1,
		 MUX_rg_s$write_1__VAL_2;
  wire [57 : 0] MUX_rg_d$write_1__VAL_1, MUX_rg_q$write_1__VAL_2;
  wire [5 : 0] MUX_rg_index$write_1__VAL_2, MUX_rg_index_1$write_1__VAL_2;
  wire MUX_crg_done$port1__write_1__SEL_1,
       MUX_crg_done$port1__write_1__SEL_2,
       MUX_crg_done_1$port1__write_1__SEL_1,
       MUX_crg_done_1$port1__write_1__SEL_2;

  // remaining internal signals
  reg [63 : 0] CASE_fpu_div64_fState_S4D_OUT_BITS_68_TO_66_0_ETC__q173,
	       CASE_fpu_sqr64_fState_S4D_OUT_BITS_68_TO_66_0_ETC__q183,
	       CASE_iFifoD_OUT_BITS_3_TO_0_0_460718241880001_ETC__q177,
	       CASE_iFifoD_OUT_BITS_3_TO_0_0_IF_iFifo_first__ETC__q176,
	       IF_iFifo_first__087_BITS_3_TO_0_088_EQ_0_089_O_ETC___d4623;
  reg [62 : 0] CASE_fpu_div64_fState_S3D_OUT_BITS_124_TO_122_ETC__q175,
	       CASE_fpu_div64_fState_S4D_OUT_BITS_1_TO_0_0_0_ETC__q172,
	       CASE_fpu_div64_fState_S4D_OUT_BITS_1_TO_0_0b0_ETC__q171,
	       CASE_fpu_div64_fState_S4D_OUT_BITS_68_TO_66_2_ETC__q169,
	       CASE_fpu_madd_fState_S8D_OUT_BITS_2_TO_1_0b0__ETC__q130,
	       CASE_fpu_madd_fState_S8D_OUT_BITS_2_TO_1_0b0__ETC__q131,
	       CASE_fpu_madd_fState_S8D_OUT_BITS_70_TO_68_0__ETC__q132,
	       CASE_fpu_sqr64_fState_S4D_OUT_BITS_1_TO_0_0_0_ETC__q182,
	       CASE_fpu_sqr64_fState_S4D_OUT_BITS_1_TO_0_0b0_ETC__q181,
	       CASE_fpu_sqr64_fState_S4D_OUT_BITS_68_TO_66_2_ETC__q179;
  reg [51 : 0] CASE_fpu_div64_fState_S4D_OUT_BITS_1_TO_0_0b0_ETC__q1,
	       CASE_fpu_div64_fState_S4D_OUT_BITS_1_TO_0_0b0_ETC__q2,
	       CASE_fpu_madd_fState_S8D_OUT_BITS_2_TO_1_0b0__ETC__q5,
	       CASE_fpu_madd_fState_S8D_OUT_BITS_2_TO_1_0b0__ETC__q6,
	       CASE_fpu_sqr64_fState_S4D_OUT_BITS_1_TO_0_0b0_ETC__q3,
	       CASE_fpu_sqr64_fState_S4D_OUT_BITS_1_TO_0_0b0_ETC__q4,
	       CASE_guard03262_0b0_sfdin11484_BITS_56_TO_5_0b_ETC__q110,
	       CASE_guard03262_0b0_sfdin11484_BITS_56_TO_5_0b_ETC__q111,
	       CASE_guard12301_0b0_theResult___snd20237_BITS__ETC__q112,
	       CASE_guard12301_0b0_theResult___snd20237_BITS__ETC__q113,
	       CASE_guard32952_0b0_theResult___snd40864_BITS__ETC__q75,
	       CASE_guard32952_0b0_theResult___snd40864_BITS__ETC__q76,
	       CASE_guard42201_0b0_sfdin50423_BITS_56_TO_5_0b_ETC__q77,
	       CASE_guard42201_0b0_sfdin50423_BITS_56_TO_5_0b_ETC__q78,
	       CASE_guard51240_0b0_theResult___snd59176_BITS__ETC__q79,
	       CASE_guard51240_0b0_theResult___snd59176_BITS__ETC__q80,
	       CASE_guard55375_0b0_theResult___snd63287_BITS__ETC__q48,
	       CASE_guard55375_0b0_theResult___snd63287_BITS__ETC__q49,
	       CASE_guard64624_0b0_sfdin72846_BITS_56_TO_5_0b_ETC__q50,
	       CASE_guard64624_0b0_sfdin72846_BITS_56_TO_5_0b_ETC__q51,
	       CASE_guard73663_0b0_theResult___snd81599_BITS__ETC__q52,
	       CASE_guard73663_0b0_theResult___snd81599_BITS__ETC__q53,
	       CASE_guard94013_0b0_theResult___snd01925_BITS__ETC__q108,
	       CASE_guard94013_0b0_theResult___snd01925_BITS__ETC__q109,
	       _theResult___fst_sfd__h142620,
	       _theResult___fst_sfd__h148292,
	       _theResult___fst_sfd__h164060,
	       _theResult___fst_sfd__h173650,
	       _theResult___fst_sfd__h182402,
	       _theResult___fst_sfd__h186932,
	       _theResult___fst_sfd__h19468,
	       _theResult___fst_sfd__h19957,
	       _theResult___fst_sfd__h202698,
	       _theResult___fst_sfd__h212288,
	       _theResult___fst_sfd__h221040,
	       _theResult___fst_sfd__h225871,
	       _theResult___fst_sfd__h241637,
	       _theResult___fst_sfd__h251227,
	       _theResult___fst_sfd__h259979,
	       _theResult___fst_sfd__h43554,
	       _theResult___fst_sfd__h95988;
  reg [22 : 0] CASE_guard69587_0b0_sfdin77680_BITS_56_TO_34_0_ETC__q162,
	       CASE_guard69587_0b0_sfdin77680_BITS_56_TO_34_0_ETC__q163,
	       CASE_guard78294_0b0_theResult___snd86293_BITS__ETC__q160,
	       CASE_guard78294_0b0_theResult___snd86293_BITS__ETC__q161,
	       CASE_guard87224_0b0_sfdin95446_BITS_56_TO_34_0_ETC__q164,
	       CASE_guard87224_0b0_sfdin95446_BITS_56_TO_34_0_ETC__q165,
	       CASE_guard96060_0b0_theResult___snd04083_BITS__ETC__q166,
	       CASE_guard96060_0b0_theResult___snd04083_BITS__ETC__q167,
	       _theResult___fst_sfd__h269560,
	       _theResult___fst_sfd__h278281,
	       _theResult___fst_sfd__h286863,
	       _theResult___fst_sfd__h296047,
	       _theResult___fst_sfd__h304683;
  reg [10 : 0] CASE_fpu_div64_fState_S4D_OUT_BITS_1_TO_0_0b0_ETC__q14,
	       CASE_fpu_div64_fState_S4D_OUT_BITS_1_TO_0_0b0_ETC__q15,
	       CASE_fpu_madd_fState_S8D_OUT_BITS_2_TO_1_0b0__ETC__q31,
	       CASE_fpu_madd_fState_S8D_OUT_BITS_2_TO_1_0b0__ETC__q32,
	       CASE_fpu_sqr64_fState_S4D_OUT_BITS_1_TO_0_0b0_ETC__q21,
	       CASE_fpu_sqr64_fState_S4D_OUT_BITS_1_TO_0_0b0_ETC__q22,
	       CASE_guard03262_0b0_theResult___fst_exp11490_0_ETC__q104,
	       CASE_guard03262_0b0_theResult___fst_exp11490_0_ETC__q105,
	       CASE_guard12301_0b0_theResult___fst_exp20291_0_ETC__q106,
	       CASE_guard12301_0b0_theResult___fst_exp20291_0_ETC__q107,
	       CASE_guard32952_0b0_theResult___fst_exp40913_0_ETC__q69,
	       CASE_guard32952_0b0_theResult___fst_exp40913_0_ETC__q70,
	       CASE_guard42201_0b0_theResult___fst_exp50429_0_ETC__q71,
	       CASE_guard42201_0b0_theResult___fst_exp50429_0_ETC__q72,
	       CASE_guard51240_0b0_theResult___fst_exp59230_0_ETC__q73,
	       CASE_guard51240_0b0_theResult___fst_exp59230_0_ETC__q74,
	       CASE_guard55375_0b0_theResult___fst_exp63336_0_ETC__q42,
	       CASE_guard55375_0b0_theResult___fst_exp63336_0_ETC__q43,
	       CASE_guard64624_0b0_theResult___fst_exp72852_0_ETC__q44,
	       CASE_guard64624_0b0_theResult___fst_exp72852_0_ETC__q45,
	       CASE_guard73663_0b0_theResult___fst_exp81653_0_ETC__q46,
	       CASE_guard73663_0b0_theResult___fst_exp81653_0_ETC__q47,
	       CASE_guard94013_0b0_theResult___fst_exp01974_0_ETC__q102,
	       CASE_guard94013_0b0_theResult___fst_exp01974_0_ETC__q103,
	       _theResult___fst_exp__h142619,
	       _theResult___fst_exp__h148291,
	       _theResult___fst_exp__h164059,
	       _theResult___fst_exp__h173649,
	       _theResult___fst_exp__h182401,
	       _theResult___fst_exp__h186931,
	       _theResult___fst_exp__h19467,
	       _theResult___fst_exp__h202697,
	       _theResult___fst_exp__h212287,
	       _theResult___fst_exp__h221039,
	       _theResult___fst_exp__h225870,
	       _theResult___fst_exp__h241636,
	       _theResult___fst_exp__h251226,
	       _theResult___fst_exp__h259978,
	       _theResult___fst_exp__h43553,
	       _theResult___fst_exp__h95987;
  reg [7 : 0] CASE_guard69587_0b0_theResult___fst_exp77686_0_ETC__q154,
	      CASE_guard69587_0b0_theResult___fst_exp77686_0_ETC__q155,
	      CASE_guard78294_0b0_theResult___fst_exp86342_0_ETC__q152,
	      CASE_guard78294_0b0_theResult___fst_exp86342_0_ETC__q153,
	      CASE_guard87224_0b0_theResult___fst_exp95452_0_ETC__q156,
	      CASE_guard87224_0b0_theResult___fst_exp95452_0_ETC__q157,
	      CASE_guard96060_0b0_theResult___fst_exp04137_0_ETC__q158,
	      CASE_guard96060_0b0_theResult___fst_exp04137_0_ETC__q159,
	      _theResult___fst_exp__h269559,
	      _theResult___fst_exp__h278280,
	      _theResult___fst_exp__h286862,
	      _theResult___fst_exp__h296046,
	      _theResult___fst_exp__h304682;
  reg CASE_fpu_div64_fOperands_S0D_OUT_BITS_2_TO_0__ETC__q9,
      CASE_fpu_div64_fState_S3D_OUT_BITS_124_TO_122_ETC__q174,
      CASE_fpu_div64_fState_S4D_OUT_BITS_1_TO_0_0b0_ETC__q170,
      CASE_fpu_div64_fState_S4D_OUT_BITS_68_TO_66_2_ETC__q168,
      CASE_fpu_madd_fState_S8D_OUT_BITS_2_TO_1_0b0__ETC__q126,
      CASE_fpu_madd_fState_S8D_OUT_BITS_70_TO_68_0__ETC__q127,
      CASE_fpu_sqr64_fState_S4D_OUT_BITS_1_TO_0_0b0_ETC__q180,
      CASE_fpu_sqr64_fState_S4D_OUT_BITS_68_TO_66_2_ETC__q178,
      CASE_guard03262_0b0_NOT_iFifoD_OUT_BIT_103_0b_ETC__q122,
      CASE_guard03262_0b0_iFifoD_OUT_BIT_103_0b1_iF_ETC__q116,
      CASE_guard12301_0b0_NOT_iFifoD_OUT_BIT_103_0b_ETC__q124,
      CASE_guard12301_0b0_iFifoD_OUT_BIT_103_0b1_iF_ETC__q118,
      CASE_guard32952_0b0_NOT_iFifoD_OUT_BIT_38_0b1_ETC__q87,
      CASE_guard32952_0b0_iFifoD_OUT_BIT_38_0b1_iFi_ETC__q81,
      CASE_guard42201_0b0_NOT_iFifoD_OUT_BIT_38_0b1_ETC__q89,
      CASE_guard42201_0b0_iFifoD_OUT_BIT_38_0b1_iFi_ETC__q83,
      CASE_guard51240_0b0_NOT_iFifoD_OUT_BIT_38_0b1_ETC__q91,
      CASE_guard51240_0b0_iFifoD_OUT_BIT_38_0b1_iFi_ETC__q85,
      CASE_guard55375_0b0_iFifoD_OUT_BIT_168_0b1_iF_ETC__q54,
      CASE_guard64624_0b0_iFifoD_OUT_BIT_168_0b1_iF_ETC__q56,
      CASE_guard69587_0b0_NOT_resWirewget_BIT_68_0b_ETC__q145,
      CASE_guard69587_0b0_resWirewget_BIT_68_0b1_re_ETC__q144,
      CASE_guard73663_0b0_iFifoD_OUT_BIT_168_0b1_iF_ETC__q58,
      CASE_guard78294_0b0_NOT_resWirewget_BIT_68_0b_ETC__q147,
      CASE_guard78294_0b0_resWirewget_BIT_68_0b1_re_ETC__q146,
      CASE_guard87224_0b0_NOT_resWirewget_BIT_68_0b_ETC__q149,
      CASE_guard87224_0b0_resWirewget_BIT_68_0b1_re_ETC__q148,
      CASE_guard94013_0b0_NOT_iFifoD_OUT_BIT_103_0b_ETC__q120,
      CASE_guard94013_0b0_iFifoD_OUT_BIT_103_0b1_iF_ETC__q114,
      CASE_guard96060_0b0_NOT_resWirewget_BIT_68_0b_ETC__q151,
      CASE_guard96060_0b0_resWirewget_BIT_68_0b1_re_ETC__q150,
      CASE_iFifoD_OUT_BITS_6_TO_4_0_CASE_guard03262_ETC__q117,
      CASE_iFifoD_OUT_BITS_6_TO_4_0_CASE_guard03262_ETC__q123,
      CASE_iFifoD_OUT_BITS_6_TO_4_0_CASE_guard12301_ETC__q119,
      CASE_iFifoD_OUT_BITS_6_TO_4_0_CASE_guard12301_ETC__q125,
      CASE_iFifoD_OUT_BITS_6_TO_4_0_CASE_guard32952_ETC__q82,
      CASE_iFifoD_OUT_BITS_6_TO_4_0_CASE_guard32952_ETC__q88,
      CASE_iFifoD_OUT_BITS_6_TO_4_0_CASE_guard42201_ETC__q84,
      CASE_iFifoD_OUT_BITS_6_TO_4_0_CASE_guard42201_ETC__q90,
      CASE_iFifoD_OUT_BITS_6_TO_4_0_CASE_guard51240_ETC__q86,
      CASE_iFifoD_OUT_BITS_6_TO_4_0_CASE_guard51240_ETC__q92,
      CASE_iFifoD_OUT_BITS_6_TO_4_0_CASE_guard55375_ETC__q55,
      CASE_iFifoD_OUT_BITS_6_TO_4_0_CASE_guard64624_ETC__q57,
      CASE_iFifoD_OUT_BITS_6_TO_4_0_CASE_guard73663_ETC__q59,
      CASE_iFifoD_OUT_BITS_6_TO_4_0_CASE_guard94013_ETC__q115,
      CASE_iFifoD_OUT_BITS_6_TO_4_0_CASE_guard94013_ETC__q121,
      IF_iFifo_first__087_BITS_3_TO_0_088_EQ_0_089_O_ETC___d3110,
      IF_iFifo_first__087_BITS_6_TO_4_118_EQ_0_191_O_ETC___d3320,
      IF_iFifo_first__087_BITS_6_TO_4_118_EQ_0_191_O_ETC___d4028,
      IF_iFifo_first__087_BITS_6_TO_4_118_EQ_0_191_O_ETC___d4582,
      IF_iFifo_first__087_BITS_6_TO_4_118_EQ_0_191_O_ETC___d4803,
      IF_iFifo_first__087_BITS_6_TO_4_118_EQ_0_191_O_ETC___d5348,
      IF_rmdFifo_first__778_EQ_0_779_OR_rmdFifo_firs_ETC___d6028,
      IF_rmdFifo_first__778_EQ_0_779_OR_rmdFifo_firs_ETC___d6400,
      IF_rmdFifo_first__778_EQ_0_779_THEN_IF_IF_IF_I_ETC___d5823,
      IF_rmdFifo_first__778_EQ_0_779_THEN_IF_IF_IF_I_ETC___d6324,
      IF_rmdFifo_first__778_EQ_0_779_THEN_IF_IF_IF_I_ETC___d6388,
      IF_rmdFifo_first__778_EQ_0_779_THEN_IF_IF_IF_I_ETC___d6409,
      IF_rmdFifo_first__778_EQ_0_779_THEN_IF_IF_IF_r_ETC___d6023,
      IF_rmdFifo_first__778_EQ_0_779_THEN_IF_IF_IF_r_ETC___d6373,
      IF_rmdFifo_first__778_EQ_0_779_THEN_IF_IF_IF_r_ETC___d6397,
      IF_rmdFifo_first__778_EQ_0_779_THEN_IF_IF_IF_r_ETC___d6418;
  wire [194 : 0] IF_fpu_sqr64_fOperand_S0_first__059_BITS_65_TO_ETC___d1212;
  wire [139 : 0] IF_NOT_fpu_madd_fState_S4_first__547_BIT_130_5_ETC___d2595;
  wire [118 : 0] IF_fpu_madd_fOperand_S0_first__803_BITS_129_TO_ETC___d1959;
  wire [115 : 0] IF_IF_rg_index_1_4_ULE_58_8_THEN_NOT_rg_b_9_EQ_ETC___d75,
		 IF_rg_index_1_4_ULE_58_8_THEN_IF_rg_res_1_BIT__ETC___d49,
		 IF_rg_index_1_4_ULE_58_8_THEN_IF_rg_res_1_BIT__ETC___d69,
		 IF_rg_index_1_4_ULE_58_8_THEN_IF_rg_res_1_BIT__ETC___d73,
		 IF_rg_index_1_4_ULE_58_8_THEN_IF_rg_res_1_BIT__ETC___d83,
		 IF_rg_index_ULE_57_THEN_IF_rg_r_0_BIT_115_1_TH_ETC___d22,
		 IF_rg_res_1_BIT_116_2_THEN_rg_res_1_BITS_115_T_ETC___d72,
		 _theResult___fst__h1476,
		 _theResult___fst__h1515,
		 _theResult___fst__h1600,
		 _theResult___snd_fst__h1478,
		 _theResult___snd_fst__h1517,
		 _theResult___snd_fst__h1602,
		 _theResult___snd_snd__h1649,
		 _theResult___snd_snd__h1715,
		 _theResult___snd_snd_snd__h1481,
		 _theResult___snd_snd_snd__h1520,
		 _theResult___snd_snd_snd__h1605,
		 b___1__h77160,
		 b__h1608,
		 b__h1712,
		 b__h32583,
		 r__h1659,
		 r__h1663,
		 r__h1724,
		 r__h1753,
		 s__h1658,
		 s__h1723,
		 sum__h1606,
		 sum__h1710,
		 value__h32541,
		 x__h85931;
  wire [113 : 0] x__h31426;
  wire [105 : 0] IF_0_CONCAT_IF_IF_7170_MINUS_fpu_madd_fState_S_ETC__q24,
		 _theResult___fst__h116827,
		 _theResult___snd__h130966,
		 _theResult___snd__h130980,
		 _theResult___snd__h130982,
		 _theResult___snd__h130994,
		 _theResult___snd__h131000,
		 _theResult___snd__h131018,
		 _theResult___snd__h131023,
		 fpu_madd_fProd_S3_first__009_SRL_IF_7170_MINUS_ETC___d2012,
		 sfdBC__h115662,
		 sfdin__h130943,
		 x__h116896;
  wire [68 : 0] IF_fpu_madd_fState_S8_first__960_BIT_67_963_AN_ETC___d3081;
  wire [63 : 0] IF_IF_fpu_madd_fOperand_S0_first__803_BIT_195__ETC___d1936,
		IF_IF_fpu_madd_fOperand_S0_first__803_BIT_195__ETC___d1939,
		IF_fpu_div64_fOperands_S0_first__06_BITS_65_TO_ETC___d455,
		IF_fpu_madd_fOperand_S0_first__803_BITS_129_TO_ETC___d1938,
		IF_iFifo_first__087_BITS_102_TO_95_625_EQ_255__ETC___d5328,
		IF_iFifo_first__087_BITS_102_TO_95_625_EQ_255__ETC___d5378,
		IF_iFifo_first__087_BITS_167_TO_160_130_EQ_255_ETC___d3846,
		IF_iFifo_first__087_BITS_37_TO_30_850_EQ_255_8_ETC___d4553,
		IF_iFifo_first__087_BITS_37_TO_30_850_EQ_255_8_ETC___d4612,
		IF_iFifo_first__087_BIT_136_624_THEN_IF_iFifo__ETC___d5330,
		IF_iFifo_first__087_BIT_201_115_THEN_IF_iFifo__ETC___d3848,
		IF_iFifo_first__087_BIT_71_849_THEN_IF_iFifo_f_ETC___d4555,
		IF_iFifo_first__087_BIT_71_849_THEN_IF_iFifo_f_ETC___d4618,
		IF_isDoubleFifo_first__407_THEN_IF_isNegateFif_ETC___d6657,
		NOT_fpu_div64_fOperands_S0_first__06_BITS_129__ETC___d452,
		fpu_div64_fState_S3_first__86_BIT_121_07_CONCA_ETC___d936;
  wire [62 : 0] IF_0b0_CONCAT_NOT_fpu_div64_fState_S4_first__4_ETC___d980,
		IF_0b0_CONCAT_NOT_fpu_madd_fState_S8_first__96_ETC___d3065,
		IF_0b0_CONCAT_NOT_fpu_sqr64_fState_S4_first__6_ETC___d1724,
		IF_IF_7170_MINUS_fpu_madd_fState_S3_first__995_ETC___d2534,
		IF_IF_fpu_div64_fState_S3_first__86_BITS_120_T_ETC___d929,
		IF_IF_fpu_madd_fOperand_S0_first__803_BIT_195__ETC___d1931,
		IF_IF_fpu_madd_fState_S7_first__651_BIT_128_65_ETC___d2952,
		IF_fpu_madd_fOperand_S0_first__803_BITS_129_TO_ETC___d1932,
		IF_fpu_madd_fOperand_S0_first__803_BIT_195_804_ETC___d1911,
		IF_fpu_madd_fState_S3_first__995_BITS_12_TO_0__ETC___d2536,
		IF_fpu_sqr64_fState_S3_first__375_BIT_58_384_A_ETC___d1678,
		IF_iFifo_first__087_BITS_102_TO_95_625_EQ_255__ETC___d5327,
		IF_iFifo_first__087_BITS_37_TO_30_850_EQ_255_8_ETC___d4552;
  wire [58 : 0] IF_0_CONCAT_IF_fpu_sqr64_fState_S3_first__375__ETC__q19,
		_theResult___snd__h94767,
		_theResult___snd__h94782,
		_theResult___snd__h94784,
		_theResult___snd__h94797,
		_theResult___snd__h94803,
		_theResult___snd__h94821,
		_theResult___snd__h94826,
		result__h85925,
		sfdin__h94744,
		x__h86149;
  wire [57 : 0] IF_0_CONCAT_IF_IF_fpu_div64_fState_S3_first__8_ETC__q12,
		IF_rg_index_ULE_57_THEN_rg_q_BITS_56_TO_0_CONC_ETC___d14,
		IF_rg_r_BIT_115_THEN_rg_q_PLUS_NEG_INV_rg_q_59_ETC__q10,
		_theResult____h32523,
		_theResult___snd__h34715,
		_theResult___snd__h42350,
		_theResult___snd__h42365,
		_theResult___snd__h42367,
		_theResult___snd__h42380,
		_theResult___snd__h42386,
		_theResult___snd__h42404,
		_theResult___snd__h42409,
		_theResult___snd_snd_snd__h33963,
		result__h32617,
		result__h32648,
		result__h32823,
		rg_q_PLUS_NEG_INV_rg_q_59_60___d561,
		sfd___1__h60702,
		sfd__h44951,
		sfd__h44953,
		sfdin__h34118,
		sfdin__h42327,
		x__h32762,
		x__h33052,
		x__h60693;
  wire [56 : 0] IF_0_CONCAT_IF_IF_0b0_CONCAT_NOT_resWire_wget__ETC__q133,
		IF_0_CONCAT_IF_IF_3074_MINUS_SEXT_iFifo_first__ETC__q37,
		IF_0_CONCAT_IF_IF_3074_MINUS_SEXT_iFifo_first__ETC__q64,
		IF_0_CONCAT_IF_IF_3074_MINUS_SEXT_iFifo_first__ETC__q97,
		IF_0_CONCAT_IF_IF_3970_MINUS_SEXT_resWire_wget_ETC__q139,
		IF_0_CONCAT_IF_IF_fpu_madd_fState_S7_first__65_ETC__q29,
		IF_0_CONCAT_IF_iFifo_first__087_BITS_102_TO_95_ETC__q100,
		IF_0_CONCAT_IF_iFifo_first__087_BITS_102_TO_95_ETC__q93,
		IF_0_CONCAT_IF_iFifo_first__087_BITS_167_TO_16_ETC__q33,
		IF_0_CONCAT_IF_iFifo_first__087_BITS_167_TO_16_ETC__q40,
		IF_0_CONCAT_IF_iFifo_first__087_BITS_37_TO_30__ETC__q60,
		IF_0_CONCAT_IF_iFifo_first__087_BITS_37_TO_30__ETC__q67,
		IF_0_CONCAT_IF_resWire_wget__410_BITS_67_TO_57_ETC__q135,
		IF_0_CONCAT_IF_resWire_wget__410_BITS_67_TO_57_ETC__q142,
		_0b0_CONCAT_NOT_iFifo_first__087_BITS_102_TO_95_ETC___d4813,
		_0b0_CONCAT_NOT_iFifo_first__087_BITS_167_TO_16_ETC___d3330,
		_0b0_CONCAT_NOT_iFifo_first__087_BITS_37_TO_30__ETC___d4038,
		_0b0_CONCAT_NOT_resWire_wget__410_BITS_67_TO_57_ETC___d6038,
		_theResult____h164614,
		_theResult____h203252,
		_theResult____h242191,
		_theResult____h269577,
		_theResult____h287214,
		_theResult___snd__h141392,
		_theResult___snd__h141406,
		_theResult___snd__h141408,
		_theResult___snd__h141420,
		_theResult___snd__h141426,
		_theResult___snd__h141444,
		_theResult___snd__h141449,
		_theResult___snd__h163287,
		_theResult___snd__h163289,
		_theResult___snd__h163296,
		_theResult___snd__h163302,
		_theResult___snd__h163325,
		_theResult___snd__h172863,
		_theResult___snd__h172874,
		_theResult___snd__h172876,
		_theResult___snd__h172886,
		_theResult___snd__h172892,
		_theResult___snd__h172915,
		_theResult___snd__h181599,
		_theResult___snd__h181613,
		_theResult___snd__h181619,
		_theResult___snd__h181637,
		_theResult___snd__h201925,
		_theResult___snd__h201927,
		_theResult___snd__h201934,
		_theResult___snd__h201940,
		_theResult___snd__h201963,
		_theResult___snd__h211501,
		_theResult___snd__h211512,
		_theResult___snd__h211514,
		_theResult___snd__h211524,
		_theResult___snd__h211530,
		_theResult___snd__h211553,
		_theResult___snd__h220237,
		_theResult___snd__h220251,
		_theResult___snd__h220257,
		_theResult___snd__h220275,
		_theResult___snd__h240864,
		_theResult___snd__h240866,
		_theResult___snd__h240873,
		_theResult___snd__h240879,
		_theResult___snd__h240902,
		_theResult___snd__h250440,
		_theResult___snd__h250451,
		_theResult___snd__h250453,
		_theResult___snd__h250463,
		_theResult___snd__h250469,
		_theResult___snd__h250492,
		_theResult___snd__h259176,
		_theResult___snd__h259190,
		_theResult___snd__h259196,
		_theResult___snd__h259214,
		_theResult___snd__h277697,
		_theResult___snd__h277708,
		_theResult___snd__h277710,
		_theResult___snd__h277720,
		_theResult___snd__h277726,
		_theResult___snd__h277749,
		_theResult___snd__h286293,
		_theResult___snd__h286295,
		_theResult___snd__h286302,
		_theResult___snd__h286308,
		_theResult___snd__h286331,
		_theResult___snd__h295463,
		_theResult___snd__h295474,
		_theResult___snd__h295476,
		_theResult___snd__h295486,
		_theResult___snd__h295492,
		_theResult___snd__h295515,
		_theResult___snd__h304083,
		_theResult___snd__h304097,
		_theResult___snd__h304103,
		_theResult___snd__h304121,
		fpu_madd_fState_S5_first__601_BITS_56_TO_0_610_ETC___d2615,
		guard__h132367,
		result__h132372,
		result__h165227,
		result__h203865,
		result__h242804,
		result__h287827,
		sfdA__h131577,
		sfdBC__h131578,
		sfd__h133119,
		sfd__h144536,
		sfd__h183176,
		sfd__h222115,
		sfd__h261975,
		sfdin__h141369,
		sfdin__h172846,
		sfdin__h211484,
		sfdin__h250423,
		sfdin__h277680,
		sfdin__h295446,
		value__h32661,
		x__h131940,
		x__h131944,
		x__h132359,
		x__h132871,
		x__h132880,
		x__h165324,
		x__h203962,
		x__h242901,
		x__h287924,
		x__h31487;
  wire [53 : 0] sfd__h142040,
		sfd__h163354,
		sfd__h172944,
		sfd__h181672,
		sfd__h201992,
		sfd__h211582,
		sfd__h220310,
		sfd__h240931,
		sfd__h250521,
		sfd__h259249,
		sfd__h42982,
		sfd__h95416,
		value__h270197,
		value__h31429,
		value__h53174;
  wire [52 : 0] sfdA__h2035,
		sfdA__h2039,
		sfdB__h2036,
		sfdB__h2041,
		x__h114243,
		x__h114255;
  wire [51 : 0] IF_IF_IF_IF_3074_MINUS_SEXT_iFifo_first__087_B_ETC___d3813,
		IF_IF_IF_IF_3074_MINUS_SEXT_iFifo_first__087_B_ETC___d3815,
		IF_IF_IF_IF_3074_MINUS_SEXT_iFifo_first__087_B_ETC___d4519,
		IF_IF_IF_IF_3074_MINUS_SEXT_iFifo_first__087_B_ETC___d4521,
		IF_IF_IF_IF_3074_MINUS_SEXT_iFifo_first__087_B_ETC___d5294,
		IF_IF_IF_IF_3074_MINUS_SEXT_iFifo_first__087_B_ETC___d5296,
		IF_IF_IF_iFifo_first__087_BITS_102_TO_95_625_E_ETC___d5268,
		IF_IF_IF_iFifo_first__087_BITS_102_TO_95_625_E_ETC___d5270,
		IF_IF_IF_iFifo_first__087_BITS_102_TO_95_625_E_ETC___d5313,
		IF_IF_IF_iFifo_first__087_BITS_102_TO_95_625_E_ETC___d5315,
		IF_IF_IF_iFifo_first__087_BITS_167_TO_160_130__ETC___d3786,
		IF_IF_IF_iFifo_first__087_BITS_167_TO_160_130__ETC___d3788,
		IF_IF_IF_iFifo_first__087_BITS_167_TO_160_130__ETC___d3832,
		IF_IF_IF_iFifo_first__087_BITS_167_TO_160_130__ETC___d3834,
		IF_IF_IF_iFifo_first__087_BITS_37_TO_30_850_EQ_ETC___d4493,
		IF_IF_IF_iFifo_first__087_BITS_37_TO_30_850_EQ_ETC___d4495,
		IF_IF_IF_iFifo_first__087_BITS_37_TO_30_850_EQ_ETC___d4538,
		IF_IF_IF_iFifo_first__087_BITS_37_TO_30_850_EQ_ETC___d4540,
		IF_fpu_div64_fOperands_S0_first__06_BITS_65_TO_ETC___d450,
		_theResult___fst_sfd__h164063,
		_theResult___fst_sfd__h173653,
		_theResult___fst_sfd__h182405,
		_theResult___fst_sfd__h182414,
		_theResult___fst_sfd__h182420,
		_theResult___fst_sfd__h202701,
		_theResult___fst_sfd__h212291,
		_theResult___fst_sfd__h221043,
		_theResult___fst_sfd__h221052,
		_theResult___fst_sfd__h221058,
		_theResult___fst_sfd__h241640,
		_theResult___fst_sfd__h251230,
		_theResult___fst_sfd__h259982,
		_theResult___fst_sfd__h259991,
		_theResult___fst_sfd__h259997,
		_theResult___fst_sfd__h43557,
		_theResult___fst_sfd__h95991,
		_theResult___fst_sfd__h96608,
		_theResult___sfd__h142542,
		_theResult___sfd__h163982,
		_theResult___sfd__h173572,
		_theResult___sfd__h182324,
		_theResult___sfd__h202620,
		_theResult___sfd__h212210,
		_theResult___sfd__h220962,
		_theResult___sfd__h241559,
		_theResult___sfd__h251149,
		_theResult___sfd__h259901,
		_theResult___sfd__h43476,
		_theResult___sfd__h95910,
		_theResult___snd_fst_sfd__h144486,
		_theResult___snd_fst_sfd__h164066,
		_theResult___snd_fst_sfd__h182408,
		_theResult___snd_fst_sfd__h183126,
		_theResult___snd_fst_sfd__h202704,
		_theResult___snd_fst_sfd__h221046,
		_theResult___snd_fst_sfd__h222065,
		_theResult___snd_fst_sfd__h241643,
		_theResult___snd_fst_sfd__h259985,
		_theResult___snd_fst_sfd__h31362,
		out___1_sfd__h144235,
		out___1_sfd__h182875,
		out___1_sfd__h221814,
		out_sfd__h142545,
		out_sfd__h163985,
		out_sfd__h173575,
		out_sfd__h182327,
		out_sfd__h202623,
		out_sfd__h212213,
		out_sfd__h220965,
		out_sfd__h241562,
		out_sfd__h251152,
		out_sfd__h259904,
		out_sfd__h43479,
		out_sfd__h95913,
		sfd__h18934,
		sfd__h18937,
		sfd__h45004,
		sfd__h99402,
		sfd__h99405,
		sfd__h99408;
  wire [24 : 0] sfd__h277778,
		sfd__h286360,
		sfd__h295544,
		sfd__h304156,
		value__h148923,
		value__h187561,
		value__h226500;
  wire [22 : 0] IF_IF_IF_IF_0b0_CONCAT_NOT_resWire_wget__410_B_ETC___d6576,
		IF_IF_IF_IF_0b0_CONCAT_NOT_resWire_wget__410_B_ETC___d6578,
		IF_IF_IF_IF_3970_MINUS_SEXT_resWire_wget__410__ETC___d6622,
		IF_IF_IF_IF_3970_MINUS_SEXT_resWire_wget__410__ETC___d6624,
		IF_IF_IF_resWire_wget__410_BITS_67_TO_57_416_E_ETC___d6595,
		IF_IF_IF_resWire_wget__410_BITS_67_TO_57_416_E_ETC___d6597,
		IF_IF_IF_resWire_wget__410_BITS_67_TO_57_416_E_ETC___d6641,
		IF_IF_IF_resWire_wget__410_BITS_67_TO_57_416_E_ETC___d6643,
		_theResult___fst_sfd__h278284,
		_theResult___fst_sfd__h286866,
		_theResult___fst_sfd__h296050,
		_theResult___fst_sfd__h304686,
		_theResult___fst_sfd__h304695,
		_theResult___fst_sfd__h304701,
		_theResult___sfd__h278203,
		_theResult___sfd__h286785,
		_theResult___sfd__h295969,
		_theResult___sfd__h304605,
		_theResult___snd_fst_sfd__h261925,
		_theResult___snd_fst_sfd__h286869,
		_theResult___snd_fst_sfd__h304689,
		out_sfd__h278206,
		out_sfd__h286788,
		out_sfd__h295972,
		out_sfd__h304608,
		sfd__h304707;
  wire [12 : 0] IF_fpu_div64_fOperands_S0_first__06_BITS_129_T_ETC___d352,
		IF_fpu_madd_fState_S4_first__547_BITS_128_TO_1_ETC___d2568,
		IF_fpu_madd_fState_S4_first__547_BITS_64_TO_54_ETC___d2563,
		IF_fpu_sqr64_fOperand_S0_first__059_BITS_65_TO_ETC___d1195,
		_7170_MINUS_fpu_madd_fState_S3_first__995_BITS__ETC___d2007,
		value__h130883,
		value__h141307,
		value__h31374,
		value__h31550,
		x__h116929,
		x__h132471,
		x__h52551,
		x__h52569;
  wire [11 : 0] IF_IF_7170_MINUS_fpu_madd_fState_S3_first__995_ETC___d2031,
		IF_IF_7170_MINUS_fpu_madd_fState_S3_first__995_ETC___d2462,
		IF_IF_fpu_div64_fState_S3_first__86_BITS_120_T_ETC___d643,
		IF_IF_fpu_div64_fState_S3_first__86_BITS_120_T_ETC___d882,
		IF_SEXT_iFifo_first__087_BITS_102_TO_95_625_MI_ETC___d5106,
		IF_SEXT_iFifo_first__087_BITS_167_TO_160_130_M_ETC___d3623,
		IF_SEXT_iFifo_first__087_BITS_37_TO_30_850_MIN_ETC___d4331,
		IF_fpu_madd_fState_S7_first__651_BITS_126_TO_1_ETC___d2668,
		IF_fpu_madd_fState_S7_first__651_BITS_126_TO_1_ETC___d2903,
		IF_fpu_sqr64_fOperand_S0_first__059_BITS_65_TO_ETC__q17,
		IF_fpu_sqr64_fState_S3_first__375_BITS_121_TO__ETC___d1389,
		IF_fpu_sqr64_fState_S3_first__375_BITS_121_TO__ETC___d1632,
		SEXT_iFifo_first__087_BITS_102_TO_95_625_MINUS_ETC___d4806,
		SEXT_iFifo_first__087_BITS_102_TO_95_625_MINUS_ETC__q96,
		SEXT_iFifo_first__087_BITS_167_TO_160_130_MINU_ETC___d3323,
		SEXT_iFifo_first__087_BITS_167_TO_160_130_MINU_ETC__q36,
		SEXT_iFifo_first__087_BITS_37_TO_30_850_MINUS__ETC___d4031,
		SEXT_iFifo_first__087_BITS_37_TO_30_850_MINUS__ETC__q63,
		SEXT_resWire_wget__410_BITS_67_TO_57_416_MINUS_ETC___d6031,
		SEXT_resWire_wget__410_BITS_67_TO_57_416_MINUS_ETC__q138,
		_3074_MINUS_0_CONCAT_IF_resWire_wget__410_BIT_5_ETC___d5531,
		_3074_MINUS_SEXT_iFifo_first__087_BITS_102_TO_9_ETC___d4809,
		_3074_MINUS_SEXT_iFifo_first__087_BITS_167_TO_1_ETC___d3326,
		_3074_MINUS_SEXT_iFifo_first__087_BITS_37_TO_30_ETC___d4034,
		_3970_MINUS_0_CONCAT_IF_iFifo_first__087_BIT_15_ETC___d3188,
		_3970_MINUS_0_CONCAT_IF_iFifo_first__087_BIT_29_ETC___d3908,
		_3970_MINUS_0_CONCAT_IF_iFifo_first__087_BIT_94_ETC___d4683,
		_3970_MINUS_SEXT_resWire_wget__410_BITS_67_TO_5_ETC___d6034,
		x__h165357,
		x__h203995,
		x__h242934,
		x__h287957;
  wire [10 : 0] IF_IF_IF_IF_3074_MINUS_SEXT_iFifo_first__087_B_ETC___d3729,
		IF_IF_IF_IF_3074_MINUS_SEXT_iFifo_first__087_B_ETC___d3731,
		IF_IF_IF_IF_3074_MINUS_SEXT_iFifo_first__087_B_ETC___d4436,
		IF_IF_IF_IF_3074_MINUS_SEXT_iFifo_first__087_B_ETC___d4438,
		IF_IF_IF_IF_3074_MINUS_SEXT_iFifo_first__087_B_ETC___d5211,
		IF_IF_IF_IF_3074_MINUS_SEXT_iFifo_first__087_B_ETC___d5213,
		IF_IF_IF_iFifo_first__087_BITS_102_TO_95_625_E_ETC___d5173,
		IF_IF_IF_iFifo_first__087_BITS_102_TO_95_625_E_ETC___d5175,
		IF_IF_IF_iFifo_first__087_BITS_102_TO_95_625_E_ETC___d5242,
		IF_IF_IF_iFifo_first__087_BITS_102_TO_95_625_E_ETC___d5244,
		IF_IF_IF_iFifo_first__087_BITS_167_TO_160_130__ETC___d3690,
		IF_IF_IF_iFifo_first__087_BITS_167_TO_160_130__ETC___d3692,
		IF_IF_IF_iFifo_first__087_BITS_167_TO_160_130__ETC___d3760,
		IF_IF_IF_iFifo_first__087_BITS_167_TO_160_130__ETC___d3762,
		IF_IF_IF_iFifo_first__087_BITS_37_TO_30_850_EQ_ETC___d4398,
		IF_IF_IF_iFifo_first__087_BITS_37_TO_30_850_EQ_ETC___d4400,
		IF_IF_IF_iFifo_first__087_BITS_37_TO_30_850_EQ_ETC___d4467,
		IF_IF_IF_iFifo_first__087_BITS_37_TO_30_850_EQ_ETC___d4469,
		IF_fpu_div64_fOperands_S0_first__06_BITS_65_TO_ETC___d433,
		IF_fpu_div64_fState_S4_first__43_BITS_64_TO_54_ETC___d977,
		IF_fpu_madd_fState_S8_first__960_BITS_65_TO_55_ETC___d2986,
		IF_fpu_madd_fState_S8_first__960_BITS_65_TO_55_ETC___d3011,
		IF_fpu_sqr64_fState_S4_first__687_BITS_64_TO_5_ETC___d1721,
		SEXT_iFifo_first__087_BITS_102_TO_95_625_MINUS_ETC__q99,
		SEXT_iFifo_first__087_BITS_167_TO_160_130_MINU_ETC__q39,
		SEXT_iFifo_first__087_BITS_37_TO_30_850_MINUS__ETC__q66,
		_theResult___exp__h142541,
		_theResult___exp__h163981,
		_theResult___exp__h173571,
		_theResult___exp__h182323,
		_theResult___exp__h202619,
		_theResult___exp__h212209,
		_theResult___exp__h220961,
		_theResult___exp__h241558,
		_theResult___exp__h251148,
		_theResult___exp__h259900,
		_theResult___exp__h43475,
		_theResult___exp__h95909,
		_theResult___fst__h31322,
		_theResult___fst_exp__h130949,
		_theResult___fst_exp__h130952,
		_theResult___fst_exp__h130971,
		_theResult___fst_exp__h130986,
		_theResult___fst_exp__h131025,
		_theResult___fst_exp__h131031,
		_theResult___fst_exp__h131034,
		_theResult___fst_exp__h141375,
		_theResult___fst_exp__h141378,
		_theResult___fst_exp__h141397,
		_theResult___fst_exp__h141412,
		_theResult___fst_exp__h141451,
		_theResult___fst_exp__h141457,
		_theResult___fst_exp__h141460,
		_theResult___fst_exp__h163327,
		_theResult___fst_exp__h163333,
		_theResult___fst_exp__h163336,
		_theResult___fst_exp__h164062,
		_theResult___fst_exp__h172852,
		_theResult___fst_exp__h172917,
		_theResult___fst_exp__h172923,
		_theResult___fst_exp__h172926,
		_theResult___fst_exp__h173652,
		_theResult___fst_exp__h181605,
		_theResult___fst_exp__h181644,
		_theResult___fst_exp__h181650,
		_theResult___fst_exp__h181653,
		_theResult___fst_exp__h182404,
		_theResult___fst_exp__h182413,
		_theResult___fst_exp__h182416,
		_theResult___fst_exp__h201965,
		_theResult___fst_exp__h201971,
		_theResult___fst_exp__h201974,
		_theResult___fst_exp__h202700,
		_theResult___fst_exp__h211490,
		_theResult___fst_exp__h211555,
		_theResult___fst_exp__h211561,
		_theResult___fst_exp__h211564,
		_theResult___fst_exp__h212290,
		_theResult___fst_exp__h220243,
		_theResult___fst_exp__h220282,
		_theResult___fst_exp__h220288,
		_theResult___fst_exp__h220291,
		_theResult___fst_exp__h221042,
		_theResult___fst_exp__h221051,
		_theResult___fst_exp__h221054,
		_theResult___fst_exp__h240904,
		_theResult___fst_exp__h240910,
		_theResult___fst_exp__h240913,
		_theResult___fst_exp__h241639,
		_theResult___fst_exp__h250429,
		_theResult___fst_exp__h250494,
		_theResult___fst_exp__h250500,
		_theResult___fst_exp__h250503,
		_theResult___fst_exp__h251229,
		_theResult___fst_exp__h259182,
		_theResult___fst_exp__h259221,
		_theResult___fst_exp__h259227,
		_theResult___fst_exp__h259230,
		_theResult___fst_exp__h259981,
		_theResult___fst_exp__h259990,
		_theResult___fst_exp__h259993,
		_theResult___fst_exp__h42284,
		_theResult___fst_exp__h42287,
		_theResult___fst_exp__h42290,
		_theResult___fst_exp__h42333,
		_theResult___fst_exp__h42336,
		_theResult___fst_exp__h42356,
		_theResult___fst_exp__h42372,
		_theResult___fst_exp__h42411,
		_theResult___fst_exp__h42417,
		_theResult___fst_exp__h42420,
		_theResult___fst_exp__h43556,
		_theResult___fst_exp__h94750,
		_theResult___fst_exp__h94753,
		_theResult___fst_exp__h94773,
		_theResult___fst_exp__h94789,
		_theResult___fst_exp__h94828,
		_theResult___fst_exp__h94834,
		_theResult___fst_exp__h94837,
		_theResult___fst_exp__h95990,
		_theResult___snd_fst_exp__h164065,
		_theResult___snd_fst_exp__h182407,
		_theResult___snd_fst_exp__h202703,
		_theResult___snd_fst_exp__h221045,
		_theResult___snd_fst_exp__h241642,
		_theResult___snd_fst_exp__h259984,
		_theResult___snd_fst_exp__h31334,
		_theResult___snd_fst_exp__h31337,
		_theResult___snd_fst_exp__h31361,
		din_exp30866_MINUS_1023__q23,
		din_exp__h130866,
		din_inc___2_exp__h142626,
		din_inc___2_exp__h182469,
		din_inc___2_exp__h182504,
		din_inc___2_exp__h182530,
		din_inc___2_exp__h221107,
		din_inc___2_exp__h221142,
		din_inc___2_exp__h221168,
		din_inc___2_exp__h260046,
		din_inc___2_exp__h260081,
		din_inc___2_exp__h260107,
		din_inc___2_exp__h43566,
		din_inc___2_exp__h96000,
		fpu_div64_fOperands_S0D_OUT_BITS_129_TO_119_M_ETC__q7,
		fpu_div64_fOperands_S0D_OUT_BITS_65_TO_55_MIN_ETC__q8,
		fpu_madd_fOperand_S0D_OUT_BITS_129_TO_119_MIN_ETC__q128,
		fpu_madd_fOperand_S0D_OUT_BITS_65_TO_55_MINUS_ETC__q129,
		fpu_madd_fState_S4D_OUT_BITS_128_TO_118_MINUS_ETC__q27,
		fpu_madd_fState_S4D_OUT_BITS_64_TO_54_MINUS_1023__q26,
		fpu_sqr64_fOperand_S0D_OUT_BITS_65_TO_55_MINU_ETC__q16,
		fpu_sqr64_fState_S3D_OUT_BITS_121_TO_111_MINU_ETC__q18,
		out_exp__h142544,
		out_exp__h163984,
		out_exp__h173574,
		out_exp__h182326,
		out_exp__h202622,
		out_exp__h212212,
		out_exp__h220964,
		out_exp__h241561,
		out_exp__h251151,
		out_exp__h259903,
		out_exp__h43478,
		out_exp__h95912,
		resWirewget_BITS_67_TO_57_MINUS_1023__q137,
		theResult___fst_exp2290_MINUS_1023__q11,
		value41307_BITS_10_TO_0_MINUS_1023__q28,
		x__h31541,
		x__h32769,
		x__h96539;
  wire [8 : 0] IF_SEXT_resWire_wget__410_BITS_67_TO_57_416_MI_ETC___d6332;
  wire [7 : 0] IF_IF_IF_IF_0b0_CONCAT_NOT_resWire_wget__410_B_ETC___d6448,
	       IF_IF_IF_IF_0b0_CONCAT_NOT_resWire_wget__410_B_ETC___d6450,
	       IF_IF_IF_IF_3970_MINUS_SEXT_resWire_wget__410__ETC___d6518,
	       IF_IF_IF_IF_3970_MINUS_SEXT_resWire_wget__410__ETC___d6520,
	       IF_IF_IF_resWire_wget__410_BITS_67_TO_57_416_E_ETC___d6479,
	       IF_IF_IF_resWire_wget__410_BITS_67_TO_57_416_E_ETC___d6481,
	       IF_IF_IF_resWire_wget__410_BITS_67_TO_57_416_E_ETC___d6549,
	       IF_IF_IF_resWire_wget__410_BITS_67_TO_57_416_E_ETC___d6551,
	       SEXT_resWire_wget__410_BITS_67_TO_57_416_MINUS_ETC__q141,
	       _theResult___exp__h278202,
	       _theResult___exp__h286784,
	       _theResult___exp__h295968,
	       _theResult___exp__h304604,
	       _theResult___fst_exp__h277686,
	       _theResult___fst_exp__h277751,
	       _theResult___fst_exp__h277757,
	       _theResult___fst_exp__h277760,
	       _theResult___fst_exp__h278283,
	       _theResult___fst_exp__h286333,
	       _theResult___fst_exp__h286339,
	       _theResult___fst_exp__h286342,
	       _theResult___fst_exp__h286865,
	       _theResult___fst_exp__h295452,
	       _theResult___fst_exp__h295517,
	       _theResult___fst_exp__h295523,
	       _theResult___fst_exp__h295526,
	       _theResult___fst_exp__h296049,
	       _theResult___fst_exp__h304089,
	       _theResult___fst_exp__h304128,
	       _theResult___fst_exp__h304134,
	       _theResult___fst_exp__h304137,
	       _theResult___fst_exp__h304685,
	       _theResult___fst_exp__h304694,
	       _theResult___fst_exp__h304697,
	       _theResult___snd_fst_exp__h286868,
	       _theResult___snd_fst_exp__h304688,
	       din_inc___2_exp__h304723,
	       din_inc___2_exp__h304749,
	       din_inc___2_exp__h304784,
	       din_inc___2_exp__h304810,
	       exp__h304706,
	       iFifoD_OUT_BITS_102_TO_95_MINUS_127__q95,
	       iFifoD_OUT_BITS_167_TO_160_MINUS_127__q35,
	       iFifoD_OUT_BITS_37_TO_30_MINUS_127__q62,
	       out_exp__h278205,
	       out_exp__h286787,
	       out_exp__h295971,
	       out_exp__h304607;
  wire [6 : 0] IF_IF_7170_MINUS_fpu_madd_fState_S3_first__995_ETC___d2460,
	       IF_fpu_sqr64_fState_S1_first__216_BIT_57_226_T_ETC___d1342,
	       x__h85465;
  wire [5 : 0] IF_IF_0b0_CONCAT_NOT_resWire_wget__410_BITS_67_ETC___d5767,
	       IF_IF_3074_MINUS_SEXT_iFifo_first__087_BITS_10_ETC___d5055,
	       IF_IF_3074_MINUS_SEXT_iFifo_first__087_BITS_16_ETC___d3572,
	       IF_IF_3074_MINUS_SEXT_iFifo_first__087_BITS_37_ETC___d4280,
	       IF_IF_3970_MINUS_SEXT_resWire_wget__410_BITS_6_ETC___d6278,
	       IF_IF_fpu_div64_fState_S3_first__86_BITS_120_T_ETC___d880,
	       IF_IF_fpu_madd_fState_S7_first__651_BIT_128_65_ETC___d2901,
	       IF_fpu_sqr64_fOperand_S0_first__059_BITS_65_TO_ETC___d1193,
	       IF_fpu_sqr64_fState_S3_first__375_BIT_58_384_T_ETC___d1630,
	       IF_iFifo_first__087_BITS_102_TO_95_625_EQ_0_63_ETC___d4757,
	       IF_iFifo_first__087_BITS_167_TO_160_130_EQ_0_1_ETC___d3271,
	       IF_iFifo_first__087_BITS_37_TO_30_850_EQ_0_856_ETC___d3982,
	       IF_resWire_wget__410_BITS_67_TO_57_416_EQ_0_42_ETC___d5982,
	       b__h11457,
	       b__h4039,
	       x__h60732;
  wire [4 : 0] IF_IF_fpu_div64_fState_S3_first__86_BITS_120_T_ETC___d926,
	       IF_fpu_div64_fState_S3_first__86_BITS_120_TO_1_ETC___d921,
	       IF_fpu_madd_fState_S3_first__995_BIT_151_996_T_ETC___d2525,
	       _0_CONCAT_IF_IF_0b0_CONCAT_NOT_resWire_wget__41_ETC___d6676,
	       _0_CONCAT_IF_IF_3970_MINUS_SEXT_resWire_wget__4_ETC___d6705,
	       _0_CONCAT_IF_resWire_wget__410_BITS_67_TO_57_41_ETC___d6688,
	       fpu_madd_fState_S3_first__995_BITS_86_TO_82_00_ETC___d2501,
	       fpu_madd_fState_S7_first__651_BITS_137_TO_133__ETC___d2942,
	       fpu_madd_fState_S8_first__960_BITS_75_TO_71_03_ETC___d3043,
	       resWire_wget__410_BITS_4_TO_0_658_OR_NOT_resWi_ETC___d6768;
  wire [2 : 0] IF_fpu_sqr64_fState_S3_first__375_BIT_195_376__ETC___d1671,
	       NOT_fpu_madd_fState_S3_first__995_BITS_12_TO_0_ETC___d2523;
  wire [1 : 0] IF_sfdin11484_BIT_4_THEN_2_ELSE_0__q98,
	       IF_sfdin2327_BIT_5_THEN_2_ELSE_0__q13,
	       IF_sfdin30943_BIT_53_THEN_2_ELSE_0__q25,
	       IF_sfdin41369_BIT_4_THEN_2_ELSE_0__q30,
	       IF_sfdin4744_BIT_6_THEN_2_ELSE_0__q20,
	       IF_sfdin50423_BIT_4_THEN_2_ELSE_0__q65,
	       IF_sfdin72846_BIT_4_THEN_2_ELSE_0__q38,
	       IF_sfdin77680_BIT_33_THEN_2_ELSE_0__q134,
	       IF_sfdin95446_BIT_33_THEN_2_ELSE_0__q140,
	       IF_theResult___snd01925_BIT_4_THEN_2_ELSE_0__q94,
	       IF_theResult___snd04083_BIT_33_THEN_2_ELSE_0__q143,
	       IF_theResult___snd20237_BIT_4_THEN_2_ELSE_0__q101,
	       IF_theResult___snd40864_BIT_4_THEN_2_ELSE_0__q61,
	       IF_theResult___snd59176_BIT_4_THEN_2_ELSE_0__q68,
	       IF_theResult___snd63287_BIT_4_THEN_2_ELSE_0__q34,
	       IF_theResult___snd81599_BIT_4_THEN_2_ELSE_0__q41,
	       IF_theResult___snd86293_BIT_33_THEN_2_ELSE_0__q136,
	       _theResult___snd_fst__h131051,
	       _theResult___snd_fst__h141477,
	       _theResult___snd_fst__h42439,
	       _theResult___snd_fst__h94856,
	       _theResult___snd_snd__h131371,
	       _theResult___snd_snd_snd__h131369,
	       guardBC__h115666,
	       guard__h133123,
	       guard__h155375,
	       guard__h164624,
	       guard__h173663,
	       guard__h194013,
	       guard__h203262,
	       guard__h212301,
	       guard__h232952,
	       guard__h242201,
	       guard__h251240,
	       guard__h269587,
	       guard__h278294,
	       guard__h287224,
	       guard__h296060,
	       guard__h33946,
	       guard__h86435,
	       x__h131406,
	       x__h141760,
	       x__h42705,
	       x__h95138;
  wire IF_3074_MINUS_0_CONCAT_IF_resWire_wget__410_BI_ETC___d6025,
       IF_3074_MINUS_0_CONCAT_IF_resWire_wget__410_BI_ETC___d6399,
       IF_3970_MINUS_0_CONCAT_IF_iFifo_first__087_BIT_ETC___d3317,
       IF_3970_MINUS_0_CONCAT_IF_iFifo_first__087_BIT_ETC___d4027,
       IF_3970_MINUS_0_CONCAT_IF_iFifo_first__087_BIT_ETC___d4581,
       IF_3970_MINUS_0_CONCAT_IF_iFifo_first__087_BIT_ETC___d4802,
       IF_3970_MINUS_0_CONCAT_IF_iFifo_first__087_BIT_ETC___d5347,
       IF_IF_fpu_madd_fOperand_S0_first__803_BIT_195__ETC___d1922,
       IF_NOT_fpu_madd_fState_S3_first__995_BITS_12_T_ETC___d2503,
       IF_NOT_fpu_madd_fState_S3_first__995_BITS_12_T_ETC___d2506,
       IF_SEXT_iFifo_first__087_BITS_102_TO_95_625_MI_ETC___d5146,
       IF_SEXT_iFifo_first__087_BITS_102_TO_95_625_MI_ETC___d5374,
       IF_SEXT_iFifo_first__087_BITS_167_TO_160_130_M_ETC___d3663,
       IF_SEXT_iFifo_first__087_BITS_37_TO_30_850_MIN_ETC___d4371,
       IF_SEXT_iFifo_first__087_BITS_37_TO_30_850_MIN_ETC___d4608,
       IF_SEXT_resWire_wget__410_BITS_67_TO_57_416_MI_ETC___d6375,
       IF_SEXT_resWire_wget__410_BITS_67_TO_57_416_MI_ETC___d6420,
       IF_SEXT_resWire_wget__410_BITS_67_TO_57_416_MI_ETC___d6734,
       IF_SEXT_resWire_wget__410_BITS_67_TO_57_416_MI_ETC___d6747,
       IF_SEXT_resWire_wget__410_BITS_67_TO_57_416_MI_ETC___d6760,
       IF_fpu_div64_fOperands_S0_first__06_BITS_129_T_ETC___d353,
       IF_fpu_div64_fOperands_S0_first__06_BITS_129_T_ETC___d355,
       IF_fpu_div64_fOperands_S0_first__06_BITS_129_T_ETC___d499,
       IF_fpu_div64_fOperands_S0_first__06_BITS_65_TO_ETC___d422,
       IF_fpu_div64_fState_S3_first__86_BITS_120_TO_1_ETC___d597,
       IF_fpu_madd_fOperand_S0_first__803_BIT_195_804_ETC___d1861,
       IF_fpu_madd_fOperand_S0_first__803_BIT_195_804_ETC___d1927,
       IF_fpu_madd_fOperand_S0_first__803_BIT_195_804_ETC___d1947,
       IF_fpu_madd_fState_S3_first__995_BITS_12_TO_0__ETC___d2516,
       IF_fpu_madd_fState_S3_first__995_BITS_12_TO_0__ETC___d2521,
       IF_fpu_madd_fState_S8_first__960_BIT_67_963_AN_ETC___d3060,
       IF_iFifo_first__087_BITS_102_TO_95_625_EQ_0_63_ETC___d5148,
       IF_iFifo_first__087_BITS_102_TO_95_625_EQ_0_63_ETC___d5376,
       IF_iFifo_first__087_BITS_167_TO_160_130_EQ_0_1_ETC___d3665,
       IF_iFifo_first__087_BITS_37_TO_30_850_EQ_0_856_ETC___d4373,
       IF_iFifo_first__087_BITS_37_TO_30_850_EQ_0_856_ETC___d4610,
       IF_isNegateFifo_first__409_THEN_IF_resWire_wge_ETC___d6424,
       IF_resWire_wget__410_BITS_67_TO_57_416_EQ_0_42_ETC___d6377,
       IF_resWire_wget__410_BITS_67_TO_57_416_EQ_0_42_ETC___d6422,
       IF_resWire_wget__410_BITS_67_TO_57_416_EQ_0_42_ETC___d6709,
       IF_resWire_wget__410_BITS_67_TO_57_416_EQ_0_42_ETC___d6720,
       IF_resWire_wget__410_BITS_67_TO_57_416_EQ_0_42_ETC___d6736,
       IF_resWire_wget__410_BITS_67_TO_57_416_EQ_0_42_ETC___d6749,
       IF_resWire_wget__410_BITS_67_TO_57_416_EQ_0_42_ETC___d6762,
       IF_rg_index_1_4_ULE_58_8_THEN_IF_rg_res_1_BIT__ETC___d85,
       IF_rg_index_1_4_ULE_58_8_THEN_NOT_rg_b_9_EQ_0__ETC___d56,
       IF_rg_index_1_4_ULE_58_8_THEN_rg_b_9_EQ_0_0_OR_ETC___d44,
       NOT_3074_MINUS_0_CONCAT_IF_resWire_wget__410_B_ETC___d6728,
       NOT_3074_MINUS_0_CONCAT_IF_resWire_wget__410_B_ETC___d6756,
       NOT_IF_fpu_madd_fOperand_S0_first__803_BIT_195_ETC___d1946,
       NOT_fpu_div64_fOperands_S0_first__06_BITS_129__ETC___d400,
       NOT_fpu_div64_fOperands_S0_first__06_BITS_65_T_ETC___d481,
       NOT_fpu_div64_fOperands_S0_first__06_BITS_65_T_ETC___d488,
       NOT_fpu_madd_fOperand_S0_first__803_BITS_129_T_ETC___d1923,
       NOT_fpu_madd_fOperand_S0_first__803_BIT_130_85_ETC___d1854,
       NOT_fpu_madd_fState_S3_first__995_BITS_12_TO_0_ETC___d2510,
       NOT_fpu_madd_fState_S4_first__547_BIT_130_553__ETC___d2584,
       NOT_iFifo_first__087_BIT_158_142_202_AND_NOT_i_ETC___d3244,
       NOT_iFifo_first__087_BIT_28_862_913_AND_NOT_iF_ETC___d3955,
       NOT_iFifo_first__087_BIT_93_637_688_AND_NOT_iF_ETC___d4730,
       NOT_resWire_wget__410_BIT_56_426_825_AND_NOT_r_ETC___d5927,
       SEXT_iFifo_first__087_BITS_102_TO_95_625_MINUS_ETC___d4807,
       SEXT_iFifo_first__087_BITS_102_TO_95_625_MINUS_ETC___d4808,
       SEXT_iFifo_first__087_BITS_167_TO_160_130_MINU_ETC___d3324,
       SEXT_iFifo_first__087_BITS_167_TO_160_130_MINU_ETC___d3325,
       SEXT_iFifo_first__087_BITS_37_TO_30_850_MINUS__ETC___d4032,
       SEXT_iFifo_first__087_BITS_37_TO_30_850_MINUS__ETC___d4033,
       SEXT_resWire_wget__410_BITS_67_TO_57_416_MINUS_ETC___d6032,
       SEXT_resWire_wget__410_BITS_67_TO_57_416_MINUS_ETC___d6033,
       _0_CONCAT_IF_IF_0b0_CONCAT_NOT_resWire_wget__41_ETC___d5769,
       _0_CONCAT_IF_IF_3074_MINUS_SEXT_iFifo_first__08_ETC___d3574,
       _0_CONCAT_IF_IF_3074_MINUS_SEXT_iFifo_first__08_ETC___d4282,
       _0_CONCAT_IF_IF_3074_MINUS_SEXT_iFifo_first__08_ETC___d5057,
       _0_CONCAT_IF_IF_3970_MINUS_SEXT_resWire_wget__4_ETC___d6280,
       _0_CONCAT_IF_IF_7170_MINUS_fpu_madd_fState_S3_f_ETC___d2463,
       _0_CONCAT_IF_IF_fpu_div64_fState_S3_first__86_B_ETC___d883,
       _0_CONCAT_IF_IF_fpu_madd_fState_S7_first__651_B_ETC___d2904,
       _0_CONCAT_IF_fpu_sqr64_fState_S3_first__375_BIT_ETC___d1633,
       _0_CONCAT_IF_iFifo_first__087_BITS_102_TO_95_62_ETC___d4759,
       _0_CONCAT_IF_iFifo_first__087_BITS_102_TO_95_62_ETC___d5107,
       _0_CONCAT_IF_iFifo_first__087_BITS_167_TO_160_1_ETC___d3273,
       _0_CONCAT_IF_iFifo_first__087_BITS_167_TO_160_1_ETC___d3624,
       _0_CONCAT_IF_iFifo_first__087_BITS_37_TO_30_850_ETC___d3984,
       _0_CONCAT_IF_iFifo_first__087_BITS_37_TO_30_850_ETC___d4332,
       _0_CONCAT_IF_resWire_wget__410_BITS_67_TO_57_41_ETC___d5984,
       _0_CONCAT_IF_resWire_wget__410_BITS_67_TO_57_41_ETC___d6333,
       _3074_MINUS_0_CONCAT_IF_resWire_wget__410_BIT_5_ETC___d5532,
       _3074_MINUS_0_CONCAT_IF_resWire_wget__410_BIT_5_ETC___d5533,
       _3074_MINUS_0_CONCAT_IF_resWire_wget__410_BIT_5_ETC___d6691,
       _3074_MINUS_0_CONCAT_IF_resWire_wget__410_BIT_5_ETC___d6716,
       _3074_MINUS_0_CONCAT_IF_resWire_wget__410_BIT_5_ETC___d6743,
       _3970_MINUS_0_CONCAT_IF_iFifo_first__087_BIT_15_ETC___d3189,
       _3970_MINUS_0_CONCAT_IF_iFifo_first__087_BIT_15_ETC___d3190,
       _3970_MINUS_0_CONCAT_IF_iFifo_first__087_BIT_29_ETC___d3909,
       _3970_MINUS_0_CONCAT_IF_iFifo_first__087_BIT_29_ETC___d3910,
       _3970_MINUS_0_CONCAT_IF_iFifo_first__087_BIT_94_ETC___d4684,
       _3970_MINUS_0_CONCAT_IF_iFifo_first__087_BIT_94_ETC___d4685,
       _7170_MINUS_fpu_madd_fState_S3_first__995_BITS__ETC___d2008,
       fpu_div64_fOperands_S0_first__06_BITS_129_TO_1_ETC___d363,
       fpu_div64_fOperands_S0_first__06_BITS_129_TO_1_ETC___d401,
       fpu_div64_fOperands_S0_first__06_BITS_129_TO_1_ETC___d436,
       fpu_div64_fOperands_S0_first__06_BITS_129_TO_1_ETC___d498,
       fpu_div64_fOperands_S0_first__06_BITS_65_TO_55_ETC___d359,
       fpu_div64_fOperands_S0_first__06_BIT_130_03_EQ_ETC___d405,
       fpu_madd_fOperand_S0_first__803_BITS_129_TO_11_ETC___d1857,
       fpu_madd_fOperand_S0_first__803_BITS_129_TO_11_ETC___d1926,
       fpu_madd_fOperand_S0_first__803_BIT_195_804_AN_ETC___d1855,
       fpu_madd_fState_S3_first__995_BITS_12_TO_0_001_ETC___d2002,
       fpu_madd_fState_S3_first__995_BITS_12_TO_0_001_ETC___d2004,
       guard__h165222,
       guard__h203860,
       guard__h242799,
       guard__h287822,
       rg_index_1_4_PLUS_1_6_ULE_58___d37,
       rg_index_1_4_ULE_58___d38,
       rg_index_PLUS_1_ULE_57___d6,
       rg_index_ULE_57___d7,
       rg_s_1_ULT_rg_r_1_0_PLUS_rg_b_9_2___d63,
       sfdlsb__h116825,
       sfdlsb__h32643,
       value_BIT_52___h53270;

  // action method server_core_request_put
  assign RDY_server_core_request_put = iFifo$FULL_N ;
  assign CAN_FIRE_server_core_request_put = iFifo$FULL_N ;
  assign WILL_FIRE_server_core_request_put = EN_server_core_request_put ;

  // actionvalue method server_core_response_get
  assign server_core_response_get = oFifo$D_OUT ;
  assign RDY_server_core_response_get = oFifo$EMPTY_N ;
  assign CAN_FIRE_server_core_response_get = oFifo$EMPTY_N ;
  assign WILL_FIRE_server_core_response_get = EN_server_core_response_get ;

  // action method server_reset_request_put
  assign RDY_server_reset_request_put = resetReqsF$FULL_N ;
  assign CAN_FIRE_server_reset_request_put = resetReqsF$FULL_N ;
  assign WILL_FIRE_server_reset_request_put = EN_server_reset_request_put ;

  // action method server_reset_response_get
  assign RDY_server_reset_response_get = resetRspsF$EMPTY_N ;
  assign CAN_FIRE_server_reset_response_get = resetRspsF$EMPTY_N ;
  assign WILL_FIRE_server_reset_response_get = EN_server_reset_response_get ;

  // submodule fpu_div64_fOperands_S0
  FIFOL1 #(.width(32'd131)) fpu_div64_fOperands_S0(.RST(RST_N),
						   .CLK(CLK),
						   .D_IN(fpu_div64_fOperands_S0$D_IN),
						   .ENQ(fpu_div64_fOperands_S0$ENQ),
						   .DEQ(fpu_div64_fOperands_S0$DEQ),
						   .CLR(fpu_div64_fOperands_S0$CLR),
						   .D_OUT(fpu_div64_fOperands_S0$D_OUT),
						   .FULL_N(fpu_div64_fOperands_S0$FULL_N),
						   .EMPTY_N(fpu_div64_fOperands_S0$EMPTY_N));

  // submodule fpu_div64_fResult_S5
  FIFOL1 #(.width(32'd69)) fpu_div64_fResult_S5(.RST(RST_N),
						.CLK(CLK),
						.D_IN(fpu_div64_fResult_S5$D_IN),
						.ENQ(fpu_div64_fResult_S5$ENQ),
						.DEQ(fpu_div64_fResult_S5$DEQ),
						.CLR(fpu_div64_fResult_S5$CLR),
						.D_OUT(fpu_div64_fResult_S5$D_OUT),
						.FULL_N(fpu_div64_fResult_S5$FULL_N),
						.EMPTY_N(fpu_div64_fResult_S5$EMPTY_N));

  // submodule fpu_div64_fState_S1
  FIFOL1 #(.width(32'd319)) fpu_div64_fState_S1(.RST(RST_N),
						.CLK(CLK),
						.D_IN(fpu_div64_fState_S1$D_IN),
						.ENQ(fpu_div64_fState_S1$ENQ),
						.DEQ(fpu_div64_fState_S1$DEQ),
						.CLR(fpu_div64_fState_S1$CLR),
						.D_OUT(fpu_div64_fState_S1$D_OUT),
						.FULL_N(fpu_div64_fState_S1$FULL_N),
						.EMPTY_N(fpu_div64_fState_S1$EMPTY_N));

  // submodule fpu_div64_fState_S2
  FIFOL1 #(.width(32'd148)) fpu_div64_fState_S2(.RST(RST_N),
						.CLK(CLK),
						.D_IN(fpu_div64_fState_S2$D_IN),
						.ENQ(fpu_div64_fState_S2$ENQ),
						.DEQ(fpu_div64_fState_S2$DEQ),
						.CLR(fpu_div64_fState_S2$CLR),
						.D_OUT(fpu_div64_fState_S2$D_OUT),
						.FULL_N(fpu_div64_fState_S2$FULL_N),
						.EMPTY_N(fpu_div64_fState_S2$EMPTY_N));

  // submodule fpu_div64_fState_S3
  FIFOL1 #(.width(32'd195)) fpu_div64_fState_S3(.RST(RST_N),
						.CLK(CLK),
						.D_IN(fpu_div64_fState_S3$D_IN),
						.ENQ(fpu_div64_fState_S3$ENQ),
						.DEQ(fpu_div64_fState_S3$DEQ),
						.CLR(fpu_div64_fState_S3$CLR),
						.D_OUT(fpu_div64_fState_S3$D_OUT),
						.FULL_N(fpu_div64_fState_S3$FULL_N),
						.EMPTY_N(fpu_div64_fState_S3$EMPTY_N));

  // submodule fpu_div64_fState_S4
  FIFOL1 #(.width(32'd139)) fpu_div64_fState_S4(.RST(RST_N),
						.CLK(CLK),
						.D_IN(fpu_div64_fState_S4$D_IN),
						.ENQ(fpu_div64_fState_S4$ENQ),
						.DEQ(fpu_div64_fState_S4$DEQ),
						.CLR(fpu_div64_fState_S4$CLR),
						.D_OUT(fpu_div64_fState_S4$D_OUT),
						.FULL_N(fpu_div64_fState_S4$FULL_N),
						.EMPTY_N(fpu_div64_fState_S4$EMPTY_N));

  // submodule fpu_madd_fOperand_S0
  FIFOL1 #(.width(32'd196)) fpu_madd_fOperand_S0(.RST(RST_N),
						 .CLK(CLK),
						 .D_IN(fpu_madd_fOperand_S0$D_IN),
						 .ENQ(fpu_madd_fOperand_S0$ENQ),
						 .DEQ(fpu_madd_fOperand_S0$DEQ),
						 .CLR(fpu_madd_fOperand_S0$CLR),
						 .D_OUT(fpu_madd_fOperand_S0$D_OUT),
						 .FULL_N(fpu_madd_fOperand_S0$FULL_N),
						 .EMPTY_N(fpu_madd_fOperand_S0$EMPTY_N));

  // submodule fpu_madd_fProd_S2
  FIFOL1 #(.width(32'd106)) fpu_madd_fProd_S2(.RST(RST_N),
					      .CLK(CLK),
					      .D_IN(fpu_madd_fProd_S2$D_IN),
					      .ENQ(fpu_madd_fProd_S2$ENQ),
					      .DEQ(fpu_madd_fProd_S2$DEQ),
					      .CLR(fpu_madd_fProd_S2$CLR),
					      .D_OUT(fpu_madd_fProd_S2$D_OUT),
					      .FULL_N(fpu_madd_fProd_S2$FULL_N),
					      .EMPTY_N(fpu_madd_fProd_S2$EMPTY_N));

  // submodule fpu_madd_fProd_S3
  FIFOL1 #(.width(32'd106)) fpu_madd_fProd_S3(.RST(RST_N),
					      .CLK(CLK),
					      .D_IN(fpu_madd_fProd_S3$D_IN),
					      .ENQ(fpu_madd_fProd_S3$ENQ),
					      .DEQ(fpu_madd_fProd_S3$DEQ),
					      .CLR(fpu_madd_fProd_S3$CLR),
					      .D_OUT(fpu_madd_fProd_S3$D_OUT),
					      .FULL_N(fpu_madd_fProd_S3$FULL_N),
					      .EMPTY_N(fpu_madd_fProd_S3$EMPTY_N));

  // submodule fpu_madd_fResult_S9
  FIFOL1 #(.width(32'd69)) fpu_madd_fResult_S9(.RST(RST_N),
					       .CLK(CLK),
					       .D_IN(fpu_madd_fResult_S9$D_IN),
					       .ENQ(fpu_madd_fResult_S9$ENQ),
					       .DEQ(fpu_madd_fResult_S9$DEQ),
					       .CLR(fpu_madd_fResult_S9$CLR),
					       .D_OUT(fpu_madd_fResult_S9$D_OUT),
					       .FULL_N(fpu_madd_fResult_S9$FULL_N),
					       .EMPTY_N(fpu_madd_fResult_S9$EMPTY_N));

  // submodule fpu_madd_fState_S1
  FIFOL1 #(.width(32'd258)) fpu_madd_fState_S1(.RST(RST_N),
					       .CLK(CLK),
					       .D_IN(fpu_madd_fState_S1$D_IN),
					       .ENQ(fpu_madd_fState_S1$ENQ),
					       .DEQ(fpu_madd_fState_S1$DEQ),
					       .CLR(fpu_madd_fState_S1$CLR),
					       .D_OUT(fpu_madd_fState_S1$D_OUT),
					       .FULL_N(fpu_madd_fState_S1$FULL_N),
					       .EMPTY_N(fpu_madd_fState_S1$EMPTY_N));

  // submodule fpu_madd_fState_S2
  FIFOL1 #(.width(32'd152)) fpu_madd_fState_S2(.RST(RST_N),
					       .CLK(CLK),
					       .D_IN(fpu_madd_fState_S2$D_IN),
					       .ENQ(fpu_madd_fState_S2$ENQ),
					       .DEQ(fpu_madd_fState_S2$DEQ),
					       .CLR(fpu_madd_fState_S2$CLR),
					       .D_OUT(fpu_madd_fState_S2$D_OUT),
					       .FULL_N(fpu_madd_fState_S2$FULL_N),
					       .EMPTY_N(fpu_madd_fState_S2$EMPTY_N));

  // submodule fpu_madd_fState_S3
  FIFOL1 #(.width(32'd152)) fpu_madd_fState_S3(.RST(RST_N),
					       .CLK(CLK),
					       .D_IN(fpu_madd_fState_S3$D_IN),
					       .ENQ(fpu_madd_fState_S3$ENQ),
					       .DEQ(fpu_madd_fState_S3$DEQ),
					       .CLR(fpu_madd_fState_S3$CLR),
					       .D_OUT(fpu_madd_fState_S3$D_OUT),
					       .FULL_N(fpu_madd_fState_S3$FULL_N),
					       .EMPTY_N(fpu_madd_fState_S3$EMPTY_N));

  // submodule fpu_madd_fState_S4
  FIFOL1 #(.width(32'd204)) fpu_madd_fState_S4(.RST(RST_N),
					       .CLK(CLK),
					       .D_IN(fpu_madd_fState_S4$D_IN),
					       .ENQ(fpu_madd_fState_S4$ENQ),
					       .DEQ(fpu_madd_fState_S4$DEQ),
					       .CLR(fpu_madd_fState_S4$CLR),
					       .D_OUT(fpu_madd_fState_S4$D_OUT),
					       .FULL_N(fpu_madd_fState_S4$FULL_N),
					       .EMPTY_N(fpu_madd_fState_S4$EMPTY_N));

  // submodule fpu_madd_fState_S5
  FIFOL1 #(.width(32'd216)) fpu_madd_fState_S5(.RST(RST_N),
					       .CLK(CLK),
					       .D_IN(fpu_madd_fState_S5$D_IN),
					       .ENQ(fpu_madd_fState_S5$ENQ),
					       .DEQ(fpu_madd_fState_S5$DEQ),
					       .CLR(fpu_madd_fState_S5$CLR),
					       .D_OUT(fpu_madd_fState_S5$D_OUT),
					       .FULL_N(fpu_madd_fState_S5$FULL_N),
					       .EMPTY_N(fpu_madd_fState_S5$EMPTY_N));

  // submodule fpu_madd_fState_S6
  FIFOL1 #(.width(32'd203)) fpu_madd_fState_S6(.RST(RST_N),
					       .CLK(CLK),
					       .D_IN(fpu_madd_fState_S6$D_IN),
					       .ENQ(fpu_madd_fState_S6$ENQ),
					       .DEQ(fpu_madd_fState_S6$DEQ),
					       .CLR(fpu_madd_fState_S6$CLR),
					       .D_OUT(fpu_madd_fState_S6$D_OUT),
					       .FULL_N(fpu_madd_fState_S6$FULL_N),
					       .EMPTY_N(fpu_madd_fState_S6$EMPTY_N));

  // submodule fpu_madd_fState_S7
  FIFOL1 #(.width(32'd203)) fpu_madd_fState_S7(.RST(RST_N),
					       .CLK(CLK),
					       .D_IN(fpu_madd_fState_S7$D_IN),
					       .ENQ(fpu_madd_fState_S7$ENQ),
					       .DEQ(fpu_madd_fState_S7$DEQ),
					       .CLR(fpu_madd_fState_S7$CLR),
					       .D_OUT(fpu_madd_fState_S7$D_OUT),
					       .FULL_N(fpu_madd_fState_S7$FULL_N),
					       .EMPTY_N(fpu_madd_fState_S7$EMPTY_N));

  // submodule fpu_madd_fState_S8
  FIFOL1 #(.width(32'd141)) fpu_madd_fState_S8(.RST(RST_N),
					       .CLK(CLK),
					       .D_IN(fpu_madd_fState_S8$D_IN),
					       .ENQ(fpu_madd_fState_S8$ENQ),
					       .DEQ(fpu_madd_fState_S8$DEQ),
					       .CLR(fpu_madd_fState_S8$CLR),
					       .D_OUT(fpu_madd_fState_S8$D_OUT),
					       .FULL_N(fpu_madd_fState_S8$FULL_N),
					       .EMPTY_N(fpu_madd_fState_S8$EMPTY_N));

  // submodule fpu_sqr64_fOperand_S0
  FIFOL1 #(.width(32'd67)) fpu_sqr64_fOperand_S0(.RST(RST_N),
						 .CLK(CLK),
						 .D_IN(fpu_sqr64_fOperand_S0$D_IN),
						 .ENQ(fpu_sqr64_fOperand_S0$ENQ),
						 .DEQ(fpu_sqr64_fOperand_S0$DEQ),
						 .CLR(fpu_sqr64_fOperand_S0$CLR),
						 .D_OUT(fpu_sqr64_fOperand_S0$D_OUT),
						 .FULL_N(fpu_sqr64_fOperand_S0$FULL_N),
						 .EMPTY_N(fpu_sqr64_fOperand_S0$EMPTY_N));

  // submodule fpu_sqr64_fResult_S5
  FIFOL1 #(.width(32'd69)) fpu_sqr64_fResult_S5(.RST(RST_N),
						.CLK(CLK),
						.D_IN(fpu_sqr64_fResult_S5$D_IN),
						.ENQ(fpu_sqr64_fResult_S5$ENQ),
						.DEQ(fpu_sqr64_fResult_S5$DEQ),
						.CLR(fpu_sqr64_fResult_S5$CLR),
						.D_OUT(fpu_sqr64_fResult_S5$D_OUT),
						.FULL_N(fpu_sqr64_fResult_S5$FULL_N),
						.EMPTY_N(fpu_sqr64_fResult_S5$EMPTY_N));

  // submodule fpu_sqr64_fState_S1
  FIFOL1 #(.width(32'd195)) fpu_sqr64_fState_S1(.RST(RST_N),
						.CLK(CLK),
						.D_IN(fpu_sqr64_fState_S1$D_IN),
						.ENQ(fpu_sqr64_fState_S1$ENQ),
						.DEQ(fpu_sqr64_fState_S1$DEQ),
						.CLR(fpu_sqr64_fState_S1$CLR),
						.D_OUT(fpu_sqr64_fState_S1$D_OUT),
						.FULL_N(fpu_sqr64_fState_S1$FULL_N),
						.EMPTY_N(fpu_sqr64_fState_S1$EMPTY_N));

  // submodule fpu_sqr64_fState_S2
  FIFOL1 #(.width(32'd137)) fpu_sqr64_fState_S2(.RST(RST_N),
						.CLK(CLK),
						.D_IN(fpu_sqr64_fState_S2$D_IN),
						.ENQ(fpu_sqr64_fState_S2$ENQ),
						.DEQ(fpu_sqr64_fState_S2$DEQ),
						.CLR(fpu_sqr64_fState_S2$CLR),
						.D_OUT(fpu_sqr64_fState_S2$D_OUT),
						.FULL_N(fpu_sqr64_fState_S2$FULL_N),
						.EMPTY_N(fpu_sqr64_fState_S2$EMPTY_N));

  // submodule fpu_sqr64_fState_S3
  FIFOL1 #(.width(32'd196)) fpu_sqr64_fState_S3(.RST(RST_N),
						.CLK(CLK),
						.D_IN(fpu_sqr64_fState_S3$D_IN),
						.ENQ(fpu_sqr64_fState_S3$ENQ),
						.DEQ(fpu_sqr64_fState_S3$DEQ),
						.CLR(fpu_sqr64_fState_S3$CLR),
						.D_OUT(fpu_sqr64_fState_S3$D_OUT),
						.FULL_N(fpu_sqr64_fState_S3$FULL_N),
						.EMPTY_N(fpu_sqr64_fState_S3$EMPTY_N));

  // submodule fpu_sqr64_fState_S4
  FIFOL1 #(.width(32'd139)) fpu_sqr64_fState_S4(.RST(RST_N),
						.CLK(CLK),
						.D_IN(fpu_sqr64_fState_S4$D_IN),
						.ENQ(fpu_sqr64_fState_S4$ENQ),
						.DEQ(fpu_sqr64_fState_S4$DEQ),
						.CLR(fpu_sqr64_fState_S4$CLR),
						.D_OUT(fpu_sqr64_fState_S4$D_OUT),
						.FULL_N(fpu_sqr64_fState_S4$FULL_N),
						.EMPTY_N(fpu_sqr64_fState_S4$EMPTY_N));

  // submodule iFifo
  FIFO2 #(.width(32'd202), .guarded(32'd1)) iFifo(.RST(RST_N),
						  .CLK(CLK),
						  .D_IN(iFifo$D_IN),
						  .ENQ(iFifo$ENQ),
						  .DEQ(iFifo$DEQ),
						  .CLR(iFifo$CLR),
						  .D_OUT(iFifo$D_OUT),
						  .FULL_N(iFifo$FULL_N),
						  .EMPTY_N(iFifo$EMPTY_N));

  // submodule isDoubleFifo
  FIFO2 #(.width(32'd1), .guarded(32'd1)) isDoubleFifo(.RST(RST_N),
						       .CLK(CLK),
						       .D_IN(isDoubleFifo$D_IN),
						       .ENQ(isDoubleFifo$ENQ),
						       .DEQ(isDoubleFifo$DEQ),
						       .CLR(isDoubleFifo$CLR),
						       .D_OUT(isDoubleFifo$D_OUT),
						       .FULL_N(isDoubleFifo$FULL_N),
						       .EMPTY_N(isDoubleFifo$EMPTY_N));

  // submodule isNegateFifo
  FIFO2 #(.width(32'd1), .guarded(32'd1)) isNegateFifo(.RST(RST_N),
						       .CLK(CLK),
						       .D_IN(isNegateFifo$D_IN),
						       .ENQ(isNegateFifo$ENQ),
						       .DEQ(isNegateFifo$DEQ),
						       .CLR(isNegateFifo$CLR),
						       .D_OUT(isNegateFifo$D_OUT),
						       .FULL_N(isNegateFifo$FULL_N),
						       .EMPTY_N(isNegateFifo$EMPTY_N));

  // submodule oFifo
  FIFO2 #(.width(32'd70), .guarded(32'd1)) oFifo(.RST(RST_N),
						 .CLK(CLK),
						 .D_IN(oFifo$D_IN),
						 .ENQ(oFifo$ENQ),
						 .DEQ(oFifo$DEQ),
						 .CLR(oFifo$CLR),
						 .D_OUT(oFifo$D_OUT),
						 .FULL_N(oFifo$FULL_N),
						 .EMPTY_N(oFifo$EMPTY_N));

  // submodule resetReqsF
  FIFO20 #(.guarded(32'd1)) resetReqsF(.RST(RST_N),
				       .CLK(CLK),
				       .ENQ(resetReqsF$ENQ),
				       .DEQ(resetReqsF$DEQ),
				       .CLR(resetReqsF$CLR),
				       .FULL_N(resetReqsF$FULL_N),
				       .EMPTY_N(resetReqsF$EMPTY_N));

  // submodule resetRspsF
  FIFO20 #(.guarded(32'd1)) resetRspsF(.RST(RST_N),
				       .CLK(CLK),
				       .ENQ(resetRspsF$ENQ),
				       .DEQ(resetRspsF$DEQ),
				       .CLR(resetRspsF$CLR),
				       .FULL_N(resetRspsF$FULL_N),
				       .EMPTY_N(resetRspsF$EMPTY_N));

  // submodule rmdFifo
  FIFO2 #(.width(32'd3), .guarded(32'd1)) rmdFifo(.RST(RST_N),
						  .CLK(CLK),
						  .D_IN(rmdFifo$D_IN),
						  .ENQ(rmdFifo$ENQ),
						  .DEQ(rmdFifo$DEQ),
						  .CLR(rmdFifo$CLR),
						  .D_OUT(rmdFifo$D_OUT),
						  .FULL_N(rmdFifo$FULL_N),
						  .EMPTY_N(rmdFifo$EMPTY_N));

  // rule RL_getResDiv
  assign CAN_FIRE_RL_getResDiv = fpu_div64_fResult_S5$EMPTY_N ;
  assign WILL_FIRE_RL_getResDiv = fpu_div64_fResult_S5$EMPTY_N ;

  // rule RL_getResSqr
  assign CAN_FIRE_RL_getResSqr = fpu_sqr64_fResult_S5$EMPTY_N ;
  assign WILL_FIRE_RL_getResSqr = fpu_sqr64_fResult_S5$EMPTY_N ;

  // rule RL_getResMAdd
  assign CAN_FIRE_RL_getResMAdd = fpu_madd_fResult_S9$EMPTY_N ;
  assign WILL_FIRE_RL_getResMAdd = fpu_madd_fResult_S9$EMPTY_N ;

  // rule __me_check_22
  assign CAN_FIRE___me_check_22 = 1'b1 ;
  assign WILL_FIRE___me_check_22 = 1'b1 ;

  // rule __me_check_23
  assign CAN_FIRE___me_check_23 = 1'b1 ;
  assign WILL_FIRE___me_check_23 = 1'b1 ;

  // rule RL_passResult
  assign CAN_FIRE_RL_passResult =
	     isDoubleFifo$EMPTY_N && isNegateFifo$EMPTY_N &&
	     rmdFifo$EMPTY_N &&
	     oFifo$FULL_N &&
	     resWire$whas ;
  assign WILL_FIRE_RL_passResult = CAN_FIRE_RL_passResult ;

  // rule RL_fpu_div64_s5_stage
  assign CAN_FIRE_RL_fpu_div64_s5_stage =
	     fpu_div64_fState_S4$EMPTY_N && fpu_div64_fResult_S5$FULL_N ;
  assign WILL_FIRE_RL_fpu_div64_s5_stage = CAN_FIRE_RL_fpu_div64_s5_stage ;

  // rule RL_fpu_div64_s4_stage
  assign CAN_FIRE_RL_fpu_div64_s4_stage =
	     fpu_div64_fState_S3$EMPTY_N && fpu_div64_fState_S4$FULL_N ;
  assign WILL_FIRE_RL_fpu_div64_s4_stage = CAN_FIRE_RL_fpu_div64_s4_stage ;

  // rule RL_fpu_div64_s3_stage
  assign CAN_FIRE_RL_fpu_div64_s3_stage =
	     fpu_div64_fState_S2$EMPTY_N && fpu_div64_fState_S3$FULL_N &&
	     (fpu_div64_fState_S2$D_OUT[147] || crg_done) ;
  assign WILL_FIRE_RL_fpu_div64_s3_stage = CAN_FIRE_RL_fpu_div64_s3_stage ;

  // rule RL_work
  assign CAN_FIRE_RL_work = rg_busy ;
  assign WILL_FIRE_RL_work = rg_busy ;

  // rule RL_fpu_div64_s2_stage
  assign CAN_FIRE_RL_fpu_div64_s2_stage =
	     fpu_div64_fState_S1$EMPTY_N && fpu_div64_fState_S2$FULL_N &&
	     (fpu_div64_fState_S1$D_OUT[318] || !rg_busy) ;
  assign WILL_FIRE_RL_fpu_div64_s2_stage =
	     CAN_FIRE_RL_fpu_div64_s2_stage && !rg_busy ;

  // rule RL_fpu_div64_s1_stage
  assign CAN_FIRE_RL_fpu_div64_s1_stage =
	     fpu_div64_fOperands_S0$EMPTY_N && fpu_div64_fState_S1$FULL_N ;
  assign WILL_FIRE_RL_fpu_div64_s1_stage = CAN_FIRE_RL_fpu_div64_s1_stage ;

  // rule RL_fpu_sqr64_s5_stage
  assign CAN_FIRE_RL_fpu_sqr64_s5_stage =
	     fpu_sqr64_fState_S4$EMPTY_N && fpu_sqr64_fResult_S5$FULL_N ;
  assign WILL_FIRE_RL_fpu_sqr64_s5_stage = CAN_FIRE_RL_fpu_sqr64_s5_stage ;

  // rule RL_fpu_sqr64_s4_stage
  assign CAN_FIRE_RL_fpu_sqr64_s4_stage =
	     fpu_sqr64_fState_S3$EMPTY_N && fpu_sqr64_fState_S4$FULL_N ;
  assign WILL_FIRE_RL_fpu_sqr64_s4_stage = CAN_FIRE_RL_fpu_sqr64_s4_stage ;

  // rule RL_fpu_sqr64_s3_stage
  assign CAN_FIRE_RL_fpu_sqr64_s3_stage =
	     fpu_sqr64_fState_S2$EMPTY_N && fpu_sqr64_fState_S3$FULL_N &&
	     (fpu_sqr64_fState_S2$D_OUT[136] || crg_done_1) ;
  assign WILL_FIRE_RL_fpu_sqr64_s3_stage = CAN_FIRE_RL_fpu_sqr64_s3_stage ;

  // rule RL_work_1
  assign CAN_FIRE_RL_work_1 = rg_busy_1 ;
  assign WILL_FIRE_RL_work_1 = rg_busy_1 ;

  // rule RL_fpu_sqr64_s2_stage
  assign CAN_FIRE_RL_fpu_sqr64_s2_stage =
	     fpu_sqr64_fState_S1$EMPTY_N && fpu_sqr64_fState_S2$FULL_N &&
	     (fpu_sqr64_fState_S1$D_OUT[194] || !rg_busy_1) ;
  assign WILL_FIRE_RL_fpu_sqr64_s2_stage =
	     CAN_FIRE_RL_fpu_sqr64_s2_stage && !rg_busy_1 ;

  // rule RL_fpu_sqr64_s1_stage
  assign CAN_FIRE_RL_fpu_sqr64_s1_stage =
	     fpu_sqr64_fOperand_S0$EMPTY_N && fpu_sqr64_fState_S1$FULL_N ;
  assign WILL_FIRE_RL_fpu_sqr64_s1_stage = CAN_FIRE_RL_fpu_sqr64_s1_stage ;

  // rule RL_fpu_madd_s9_stage
  assign CAN_FIRE_RL_fpu_madd_s9_stage =
	     fpu_madd_fState_S8$EMPTY_N && fpu_madd_fResult_S9$FULL_N ;
  assign WILL_FIRE_RL_fpu_madd_s9_stage = CAN_FIRE_RL_fpu_madd_s9_stage ;

  // rule RL_fpu_madd_s8_stage
  assign CAN_FIRE_RL_fpu_madd_s8_stage =
	     fpu_madd_fState_S7$EMPTY_N && fpu_madd_fState_S8$FULL_N ;
  assign WILL_FIRE_RL_fpu_madd_s8_stage = CAN_FIRE_RL_fpu_madd_s8_stage ;

  // rule RL_fpu_madd_s7_stage
  assign CAN_FIRE_RL_fpu_madd_s7_stage =
	     fpu_madd_fState_S6$EMPTY_N && fpu_madd_fState_S7$FULL_N ;
  assign WILL_FIRE_RL_fpu_madd_s7_stage = CAN_FIRE_RL_fpu_madd_s7_stage ;

  // rule RL_fpu_madd_s6_stage
  assign CAN_FIRE_RL_fpu_madd_s6_stage =
	     fpu_madd_fState_S5$EMPTY_N && fpu_madd_fState_S6$FULL_N ;
  assign WILL_FIRE_RL_fpu_madd_s6_stage = CAN_FIRE_RL_fpu_madd_s6_stage ;

  // rule RL_fpu_madd_s5_stage
  assign CAN_FIRE_RL_fpu_madd_s5_stage =
	     fpu_madd_fState_S4$EMPTY_N && fpu_madd_fState_S5$FULL_N ;
  assign WILL_FIRE_RL_fpu_madd_s5_stage = CAN_FIRE_RL_fpu_madd_s5_stage ;

  // rule RL_fpu_madd_s4_stage
  assign CAN_FIRE_RL_fpu_madd_s4_stage =
	     fpu_madd_fState_S3$EMPTY_N && fpu_madd_fProd_S3$EMPTY_N &&
	     fpu_madd_fState_S4$FULL_N ;
  assign WILL_FIRE_RL_fpu_madd_s4_stage = CAN_FIRE_RL_fpu_madd_s4_stage ;

  // rule RL_fpu_madd_s3_stage
  assign CAN_FIRE_RL_fpu_madd_s3_stage =
	     fpu_madd_fState_S2$EMPTY_N && fpu_madd_fProd_S2$EMPTY_N &&
	     fpu_madd_fProd_S3$FULL_N &&
	     fpu_madd_fState_S3$FULL_N ;
  assign WILL_FIRE_RL_fpu_madd_s3_stage = CAN_FIRE_RL_fpu_madd_s3_stage ;

  // rule RL_fpu_madd_s2_stage
  assign CAN_FIRE_RL_fpu_madd_s2_stage =
	     fpu_madd_fState_S1$EMPTY_N && fpu_madd_fProd_S2$FULL_N &&
	     fpu_madd_fState_S2$FULL_N ;
  assign WILL_FIRE_RL_fpu_madd_s2_stage = CAN_FIRE_RL_fpu_madd_s2_stage ;

  // rule RL_fpu_madd_s1_stage
  assign CAN_FIRE_RL_fpu_madd_s1_stage =
	     fpu_madd_fOperand_S0$EMPTY_N && fpu_madd_fState_S1$FULL_N ;
  assign WILL_FIRE_RL_fpu_madd_s1_stage = CAN_FIRE_RL_fpu_madd_s1_stage ;

  // rule RL_start_op
  assign CAN_FIRE_RL_start_op =
	     iFifo$EMPTY_N && isDoubleFifo$FULL_N && isNegateFifo$FULL_N &&
	     rmdFifo$FULL_N &&
	     IF_iFifo_first__087_BITS_3_TO_0_088_EQ_0_089_O_ETC___d3110 ;
  assign WILL_FIRE_RL_start_op = CAN_FIRE_RL_start_op ;

  // rule RL_rl_reset
  assign CAN_FIRE_RL_rl_reset = resetReqsF$EMPTY_N && resetRspsF$FULL_N ;
  assign WILL_FIRE_RL_rl_reset = CAN_FIRE_RL_rl_reset ;

  // inputs to muxes for submodule ports
  assign MUX_crg_done$port1__write_1__SEL_1 = rg_busy && rg_index == 6'd28 ;
  assign MUX_crg_done$port1__write_1__SEL_2 =
	     WILL_FIRE_RL_fpu_div64_s2_stage &&
	     !fpu_div64_fState_S1$D_OUT[318] ;
  assign MUX_crg_done_1$port1__write_1__SEL_1 =
	     rg_busy_1 && rg_index_1 == 6'd29 ;
  assign MUX_crg_done_1$port1__write_1__SEL_2 =
	     WILL_FIRE_RL_fpu_sqr64_s2_stage &&
	     !fpu_sqr64_fState_S1$D_OUT[194] ;
  assign MUX_rg_b$write_1__VAL_1 =
	     fpu_sqr64_fState_S1$D_OUT[57] ?
	       116'h40000000000000000000000000000 :
	       b___1__h77160 ;
  assign MUX_rg_b$write_1__VAL_2 =
	     rg_index_1_4_PLUS_1_6_ULE_58___d37 ?
	       _theResult___fst__h1476 :
	       IF_rg_index_1_4_ULE_58_8_THEN_IF_rg_res_1_BIT__ETC___d49 ;
  assign MUX_rg_d$write_1__VAL_1 =
	     { 1'd0, fpu_div64_fState_S1$D_OUT[67:11] } ;
  assign MUX_rg_index$write_1__VAL_2 = rg_index + 6'd1 ;
  assign MUX_rg_index_1$write_1__VAL_2 = rg_index_1 + 6'd1 ;
  assign MUX_rg_q$write_1__VAL_2 =
	     rg_index_PLUS_1_ULE_57___d6 ?
	       { IF_rg_index_ULE_57_THEN_rg_q_BITS_56_TO_0_CONC_ETC___d14[56:0],
		 !IF_rg_index_ULE_57_THEN_IF_rg_r_0_BIT_115_1_TH_ETC___d22[115] } :
	       IF_rg_index_ULE_57_THEN_rg_q_BITS_56_TO_0_CONC_ETC___d14 ;
  assign MUX_rg_r$write_1__VAL_1 =
	     { 2'd0, fpu_div64_fState_S1$D_OUT[181:68] } ;
  assign MUX_rg_r$write_1__VAL_2 =
	     rg_index_PLUS_1_ULE_57___d6 ?
	       (IF_rg_index_ULE_57_THEN_IF_rg_r_0_BIT_115_1_TH_ETC___d22[115] ?
		  { IF_rg_index_ULE_57_THEN_IF_rg_r_0_BIT_115_1_TH_ETC___d22[114:0],
		    1'd0 } +
		  b__h32583 :
		  { IF_rg_index_ULE_57_THEN_IF_rg_r_0_BIT_115_1_TH_ETC___d22[114:0],
		    1'd0 } -
		  b__h32583) :
	       IF_rg_index_ULE_57_THEN_IF_rg_r_0_BIT_115_1_TH_ETC___d22 ;
  assign MUX_rg_r_1$write_1__VAL_2 =
	     rg_index_1_4_PLUS_1_6_ULE_58___d37 ?
	       _theResult___snd_snd_snd__h1481 :
	       IF_rg_index_1_4_ULE_58_8_THEN_IF_rg_res_1_BIT__ETC___d69 ;
  assign MUX_rg_res$write_1__VAL_2 =
	     { rg_index_1_4_PLUS_1_6_ULE_58___d37 ?
		 IF_rg_index_1_4_ULE_58_8_THEN_rg_b_9_EQ_0_0_OR_ETC___d44 ||
		 IF_rg_index_1_4_ULE_58_8_THEN_IF_rg_res_1_BIT__ETC___d49 ==
		 116'd0 :
		 IF_rg_index_1_4_ULE_58_8_THEN_rg_b_9_EQ_0_0_OR_ETC___d44,
	       rg_index_1_4_PLUS_1_6_ULE_58___d37 ?
		 IF_IF_rg_index_1_4_ULE_58_8_THEN_NOT_rg_b_9_EQ_ETC___d75 :
		 IF_rg_index_1_4_ULE_58_8_THEN_IF_rg_res_1_BIT__ETC___d73 } ;
  assign MUX_rg_s$write_1__VAL_1 =
	     { fpu_sqr64_fState_S1$D_OUT[57:0], 58'd0 } ;
  assign MUX_rg_s$write_1__VAL_2 =
	     rg_index_1_4_PLUS_1_6_ULE_58___d37 ?
	       _theResult___snd_fst__h1478 :
	       IF_rg_index_1_4_ULE_58_8_THEN_IF_rg_res_1_BIT__ETC___d83 ;

  // inlined wires
  always@(fpu_div64_fResult_S5$EMPTY_N or
	  fpu_div64_fResult_S5$D_OUT or
	  fpu_sqr64_fResult_S5$EMPTY_N or
	  fpu_sqr64_fResult_S5$D_OUT or
	  fpu_madd_fResult_S9$EMPTY_N or fpu_madd_fResult_S9$D_OUT)
  begin
    case (1'b1) // synopsys parallel_case
      fpu_div64_fResult_S5$EMPTY_N: resWire$wget = fpu_div64_fResult_S5$D_OUT;
      fpu_sqr64_fResult_S5$EMPTY_N: resWire$wget = fpu_sqr64_fResult_S5$D_OUT;
      fpu_madd_fResult_S9$EMPTY_N: resWire$wget = fpu_madd_fResult_S9$D_OUT;
      default: resWire$wget = 69'h0AAAAAAAAAAAAAAAAA /* unspecified value */ ;
    endcase
  end
  assign resWire$whas =
	     fpu_div64_fResult_S5$EMPTY_N || fpu_sqr64_fResult_S5$EMPTY_N ||
	     fpu_madd_fResult_S9$EMPTY_N ;
  assign crg_done$EN_port0__write =
	     WILL_FIRE_RL_fpu_div64_s3_stage &&
	     !fpu_div64_fState_S2$D_OUT[147] ;
  assign crg_done$port1__read = !crg_done$EN_port0__write && crg_done ;
  assign crg_done$EN_port1__write =
	     rg_busy && rg_index == 6'd28 ||
	     WILL_FIRE_RL_fpu_div64_s2_stage &&
	     !fpu_div64_fState_S1$D_OUT[318] ;
  assign crg_done$port2__read =
	     crg_done$EN_port1__write ?
	       MUX_crg_done$port1__write_1__SEL_1 :
	       crg_done$port1__read ;
  assign crg_done_1$EN_port0__write =
	     WILL_FIRE_RL_fpu_sqr64_s3_stage &&
	     !fpu_sqr64_fState_S2$D_OUT[136] ;
  assign crg_done_1$port1__read = !crg_done_1$EN_port0__write && crg_done_1 ;
  assign crg_done_1$EN_port1__write =
	     rg_busy_1 && rg_index_1 == 6'd29 ||
	     WILL_FIRE_RL_fpu_sqr64_s2_stage &&
	     !fpu_sqr64_fState_S1$D_OUT[194] ;
  assign crg_done_1$port2__read =
	     crg_done_1$EN_port1__write ?
	       MUX_crg_done_1$port1__write_1__SEL_1 :
	       crg_done_1$port1__read ;

  // register crg_done
  assign crg_done$D_IN = crg_done$port2__read ;
  assign crg_done$EN = 1'b1 ;

  // register crg_done_1
  assign crg_done_1$D_IN = crg_done_1$port2__read ;
  assign crg_done_1$EN = 1'b1 ;

  // register rg_b
  assign rg_b$D_IN =
	     MUX_crg_done_1$port1__write_1__SEL_2 ?
	       MUX_rg_b$write_1__VAL_1 :
	       MUX_rg_b$write_1__VAL_2 ;
  assign rg_b$EN =
	     WILL_FIRE_RL_fpu_sqr64_s2_stage &&
	     !fpu_sqr64_fState_S1$D_OUT[194] ||
	     rg_busy_1 ;

  // register rg_busy
  assign rg_busy$D_IN = !MUX_crg_done$port1__write_1__SEL_1 ;
  assign rg_busy$EN =
	     rg_busy && rg_index == 6'd28 ||
	     WILL_FIRE_RL_fpu_div64_s2_stage &&
	     !fpu_div64_fState_S1$D_OUT[318] ;

  // register rg_busy_1
  assign rg_busy_1$D_IN = !MUX_crg_done_1$port1__write_1__SEL_1 ;
  assign rg_busy_1$EN =
	     rg_busy_1 && rg_index_1 == 6'd29 ||
	     WILL_FIRE_RL_fpu_sqr64_s2_stage &&
	     !fpu_sqr64_fState_S1$D_OUT[194] ;

  // register rg_d
  assign rg_d$D_IN =
	     MUX_crg_done$port1__write_1__SEL_2 ?
	       MUX_rg_d$write_1__VAL_1 :
	       rg_d ;
  assign rg_d$EN =
	     WILL_FIRE_RL_fpu_div64_s2_stage &&
	     !fpu_div64_fState_S1$D_OUT[318] ||
	     rg_busy ;

  // register rg_index
  assign rg_index$D_IN =
	     MUX_crg_done$port1__write_1__SEL_2 ?
	       6'd0 :
	       MUX_rg_index$write_1__VAL_2 ;
  assign rg_index$EN =
	     WILL_FIRE_RL_fpu_div64_s2_stage &&
	     !fpu_div64_fState_S1$D_OUT[318] ||
	     rg_busy ;

  // register rg_index_1
  assign rg_index_1$D_IN =
	     MUX_crg_done_1$port1__write_1__SEL_2 ?
	       6'd0 :
	       MUX_rg_index_1$write_1__VAL_2 ;
  assign rg_index_1$EN =
	     WILL_FIRE_RL_fpu_sqr64_s2_stage &&
	     !fpu_sqr64_fState_S1$D_OUT[194] ||
	     rg_busy_1 ;

  // register rg_q
  assign rg_q$D_IN =
	     MUX_crg_done$port1__write_1__SEL_2 ?
	       58'd0 :
	       MUX_rg_q$write_1__VAL_2 ;
  assign rg_q$EN =
	     WILL_FIRE_RL_fpu_div64_s2_stage &&
	     !fpu_div64_fState_S1$D_OUT[318] ||
	     rg_busy ;

  // register rg_r
  assign rg_r$D_IN =
	     MUX_crg_done$port1__write_1__SEL_2 ?
	       MUX_rg_r$write_1__VAL_1 :
	       MUX_rg_r$write_1__VAL_2 ;
  assign rg_r$EN =
	     WILL_FIRE_RL_fpu_div64_s2_stage &&
	     !fpu_div64_fState_S1$D_OUT[318] ||
	     rg_busy ;

  // register rg_r_1
  assign rg_r_1$D_IN =
	     MUX_crg_done_1$port1__write_1__SEL_2 ?
	       116'd0 :
	       MUX_rg_r_1$write_1__VAL_2 ;
  assign rg_r_1$EN =
	     WILL_FIRE_RL_fpu_sqr64_s2_stage &&
	     !fpu_sqr64_fState_S1$D_OUT[194] ||
	     rg_busy_1 ;

  // register rg_res
  assign rg_res$D_IN =
	     MUX_crg_done_1$port1__write_1__SEL_2 ?
	       117'h0AAAAAAAAAAAAAAAAAAAAAAAAAAAAA :
	       MUX_rg_res$write_1__VAL_2 ;
  assign rg_res$EN =
	     WILL_FIRE_RL_fpu_sqr64_s2_stage &&
	     !fpu_sqr64_fState_S1$D_OUT[194] ||
	     rg_busy_1 ;

  // register rg_s
  assign rg_s$D_IN =
	     MUX_crg_done_1$port1__write_1__SEL_2 ?
	       MUX_rg_s$write_1__VAL_1 :
	       MUX_rg_s$write_1__VAL_2 ;
  assign rg_s$EN =
	     WILL_FIRE_RL_fpu_sqr64_s2_stage &&
	     !fpu_sqr64_fState_S1$D_OUT[194] ||
	     rg_busy_1 ;

  // submodule fpu_div64_fOperands_S0
  assign fpu_div64_fOperands_S0$D_IN =
	     { IF_iFifo_first__087_BIT_201_115_THEN_IF_iFifo__ETC___d3848,
	       IF_iFifo_first__087_BIT_136_624_THEN_IF_iFifo__ETC___d5330,
	       iFifo$D_OUT[6:4] } ;
  assign fpu_div64_fOperands_S0$ENQ =
	     WILL_FIRE_RL_start_op && iFifo$D_OUT[3:0] == 4'd3 ;
  assign fpu_div64_fOperands_S0$DEQ = CAN_FIRE_RL_fpu_div64_s1_stage ;
  assign fpu_div64_fOperands_S0$CLR = 1'b0 ;

  // submodule fpu_div64_fResult_S5
  assign fpu_div64_fResult_S5$D_IN =
	     fpu_div64_fState_S4$D_OUT[138] ?
	       fpu_div64_fState_S4$D_OUT[137:69] :
	       { (fpu_div64_fState_S4$D_OUT[64:54] == 11'd2047) ?
		   fpu_div64_fState_S4$D_OUT[65:2] :
		   CASE_fpu_div64_fState_S4D_OUT_BITS_68_TO_66_0_ETC__q173,
		 fpu_div64_fState_S4$D_OUT[73:69] |
		 { 2'd0,
		   _theResult___fst_exp__h43556 == 11'd2047 &&
		   _theResult___fst_sfd__h43557 == 52'd0,
		   1'd0,
		   fpu_div64_fState_S4$D_OUT[64:54] != 11'd2047 &&
		   fpu_div64_fState_S4$D_OUT[1:0] != 2'b0 } } ;
  assign fpu_div64_fResult_S5$ENQ = CAN_FIRE_RL_fpu_div64_s5_stage ;
  assign fpu_div64_fResult_S5$DEQ = fpu_div64_fResult_S5$EMPTY_N ;
  assign fpu_div64_fResult_S5$CLR = 1'b0 ;

  // submodule fpu_div64_fState_S1
  assign fpu_div64_fState_S1$D_IN =
	     { fpu_div64_fOperands_S0_first__06_BITS_129_TO_1_ETC___d363,
	       (fpu_div64_fOperands_S0$D_OUT[129:119] == 11'd2047 &&
		fpu_div64_fOperands_S0$D_OUT[118:67] != 52'd0 &&
		!fpu_div64_fOperands_S0$D_OUT[118]) ?
		 { fpu_div64_fOperands_S0$D_OUT[130:119], sfd__h18934 } :
		 IF_fpu_div64_fOperands_S0_first__06_BITS_65_TO_ETC___d455,
	       fpu_div64_fOperands_S0$D_OUT[129:119] == 11'd2047 &&
	       fpu_div64_fOperands_S0$D_OUT[118:67] != 52'd0 &&
	       !fpu_div64_fOperands_S0$D_OUT[118] ||
	       fpu_div64_fOperands_S0$D_OUT[65:55] == 11'd2047 &&
	       fpu_div64_fOperands_S0$D_OUT[54:3] != 52'd0 &&
	       !fpu_div64_fOperands_S0$D_OUT[54] ||
	       (fpu_div64_fOperands_S0$D_OUT[129:119] != 11'd2047 ||
		!fpu_div64_fOperands_S0$D_OUT[118]) &&
	       (fpu_div64_fOperands_S0$D_OUT[65:55] != 11'd2047 ||
		!fpu_div64_fOperands_S0$D_OUT[54]) &&
	       fpu_div64_fOperands_S0_first__06_BITS_129_TO_1_ETC___d436,
	       (fpu_div64_fOperands_S0$D_OUT[129:119] != 11'd2047 ||
		fpu_div64_fOperands_S0$D_OUT[118:67] == 52'd0 ||
		fpu_div64_fOperands_S0$D_OUT[118]) &&
	       (fpu_div64_fOperands_S0$D_OUT[129:119] != 11'd2047 ||
		!fpu_div64_fOperands_S0$D_OUT[118]) &&
	       NOT_fpu_div64_fOperands_S0_first__06_BITS_129__ETC___d400 &&
	       fpu_div64_fOperands_S0$D_OUT[65:55] == 11'd0 &&
	       fpu_div64_fOperands_S0$D_OUT[54:3] == 52'd0 &&
	       (fpu_div64_fOperands_S0$D_OUT[129:119] != 11'd2047 ||
		fpu_div64_fOperands_S0$D_OUT[118:67] != 52'd0),
	       (fpu_div64_fOperands_S0$D_OUT[129:119] != 11'd2047 ||
		fpu_div64_fOperands_S0$D_OUT[118:67] == 52'd0 ||
		fpu_div64_fOperands_S0$D_OUT[118]) &&
	       (fpu_div64_fOperands_S0$D_OUT[65:55] != 11'd2047 ||
		fpu_div64_fOperands_S0$D_OUT[54:3] == 52'd0 ||
		fpu_div64_fOperands_S0$D_OUT[54]) &&
	       (fpu_div64_fOperands_S0$D_OUT[129:119] != 11'd2047 ||
		!fpu_div64_fOperands_S0$D_OUT[118]) &&
	       (fpu_div64_fOperands_S0$D_OUT[65:55] != 11'd2047 ||
		!fpu_div64_fOperands_S0$D_OUT[54]) &&
	       (fpu_div64_fOperands_S0$D_OUT[65:55] != 11'd0 ||
		fpu_div64_fOperands_S0$D_OUT[54:3] != 52'd0) &&
	       (fpu_div64_fOperands_S0$D_OUT[129:119] != 11'd2047 ||
		fpu_div64_fOperands_S0$D_OUT[118:67] != 52'd0) &&
	       (fpu_div64_fOperands_S0$D_OUT[129:119] != 11'd0 ||
		fpu_div64_fOperands_S0$D_OUT[118:67] != 52'd0) &&
	       (fpu_div64_fOperands_S0$D_OUT[65:55] != 11'd2047 ||
		fpu_div64_fOperands_S0$D_OUT[54:3] != 52'd0) &&
	       !IF_fpu_div64_fOperands_S0_first__06_BITS_129_T_ETC___d353,
	       (fpu_div64_fOperands_S0$D_OUT[129:119] != 11'd2047 ||
		fpu_div64_fOperands_S0$D_OUT[118:67] == 52'd0 ||
		fpu_div64_fOperands_S0$D_OUT[118]) &&
	       (fpu_div64_fOperands_S0$D_OUT[65:55] != 11'd2047 ||
		fpu_div64_fOperands_S0$D_OUT[54:3] == 52'd0 ||
		fpu_div64_fOperands_S0$D_OUT[54]) &&
	       (fpu_div64_fOperands_S0$D_OUT[129:119] != 11'd2047 ||
		!fpu_div64_fOperands_S0$D_OUT[118]) &&
	       (fpu_div64_fOperands_S0$D_OUT[65:55] != 11'd2047 ||
		!fpu_div64_fOperands_S0$D_OUT[54]) &&
	       NOT_fpu_div64_fOperands_S0_first__06_BITS_65_T_ETC___d481,
	       (fpu_div64_fOperands_S0$D_OUT[129:119] != 11'd2047 ||
		fpu_div64_fOperands_S0$D_OUT[118:67] == 52'd0 ||
		fpu_div64_fOperands_S0$D_OUT[118]) &&
	       (fpu_div64_fOperands_S0$D_OUT[65:55] != 11'd2047 ||
		fpu_div64_fOperands_S0$D_OUT[54:3] == 52'd0 ||
		fpu_div64_fOperands_S0$D_OUT[54]) &&
	       (fpu_div64_fOperands_S0$D_OUT[129:119] != 11'd2047 ||
		!fpu_div64_fOperands_S0$D_OUT[118]) &&
	       (fpu_div64_fOperands_S0$D_OUT[65:55] != 11'd2047 ||
		!fpu_div64_fOperands_S0$D_OUT[54]) &&
	       NOT_fpu_div64_fOperands_S0_first__06_BITS_65_T_ETC___d488,
	       fpu_div64_fOperands_S0$D_OUT[2:0],
	       !fpu_div64_fOperands_S0_first__06_BIT_130_03_EQ_ETC___d405,
	       _theResult___snd_fst_exp__h31361,
	       _theResult___snd_fst_sfd__h31362,
	       x__h31426,
	       x__h31487,
	       x__h31541 } ;
  assign fpu_div64_fState_S1$ENQ = CAN_FIRE_RL_fpu_div64_s1_stage ;
  assign fpu_div64_fState_S1$DEQ = WILL_FIRE_RL_fpu_div64_s2_stage ;
  assign fpu_div64_fState_S1$CLR = 1'b0 ;

  // submodule fpu_div64_fState_S2
  assign fpu_div64_fState_S2$D_IN =
	     { fpu_div64_fState_S1$D_OUT[318:182],
	       fpu_div64_fState_S1$D_OUT[10:0] } ;
  assign fpu_div64_fState_S2$ENQ = WILL_FIRE_RL_fpu_div64_s2_stage ;
  assign fpu_div64_fState_S2$DEQ = CAN_FIRE_RL_fpu_div64_s3_stage ;
  assign fpu_div64_fState_S2$CLR = 1'b0 ;

  // submodule fpu_div64_fState_S3
  assign fpu_div64_fState_S3$D_IN =
	     { fpu_div64_fState_S2$D_OUT[147:11], x__h33052 } ;
  assign fpu_div64_fState_S3$ENQ = CAN_FIRE_RL_fpu_div64_s3_stage ;
  assign fpu_div64_fState_S3$DEQ = CAN_FIRE_RL_fpu_div64_s4_stage ;
  assign fpu_div64_fState_S3$CLR = 1'b0 ;

  // submodule fpu_div64_fState_S4
  assign fpu_div64_fState_S4$D_IN =
	     { (fpu_div64_fState_S3$D_OUT[120:110] == 11'd2047) ?
		 fpu_div64_fState_S3$D_OUT[57:56] != 2'b0 ||
		 fpu_div64_fState_S3$D_OUT[194] :
		 fpu_div64_fState_S3$D_OUT[194],
	       (fpu_div64_fState_S3$D_OUT[120:110] == 11'd2047) ?
		 ((fpu_div64_fState_S3$D_OUT[57:56] == 2'b0) ?
		    fpu_div64_fState_S3$D_OUT[193:130] :
		    { CASE_fpu_div64_fState_S3D_OUT_BITS_124_TO_122_ETC__q174,
		      CASE_fpu_div64_fState_S3D_OUT_BITS_124_TO_122_ETC__q175 }) :
		 fpu_div64_fState_S3$D_OUT[193:130],
	       IF_IF_fpu_div64_fState_S3_first__86_BITS_120_T_ETC___d926,
	       fpu_div64_fState_S3$D_OUT[124:122],
	       fpu_div64_fState_S3_first__86_BIT_121_07_CONCA_ETC___d936,
	       x__h42705 } ;
  assign fpu_div64_fState_S4$ENQ = CAN_FIRE_RL_fpu_div64_s4_stage ;
  assign fpu_div64_fState_S4$DEQ = CAN_FIRE_RL_fpu_div64_s5_stage ;
  assign fpu_div64_fState_S4$CLR = 1'b0 ;

  // submodule fpu_madd_fOperand_S0
  assign fpu_madd_fOperand_S0$D_IN =
	     { iFifo$D_OUT[3:0] != 4'd2,
	       IF_iFifo_first__087_BITS_3_TO_0_088_EQ_0_089_O_ETC___d4623,
	       CASE_iFifoD_OUT_BITS_3_TO_0_0_IF_iFifo_first__ETC__q176,
	       CASE_iFifoD_OUT_BITS_3_TO_0_0_460718241880001_ETC__q177,
	       iFifo$D_OUT[6:4] } ;
  assign fpu_madd_fOperand_S0$ENQ =
	     WILL_FIRE_RL_start_op &&
	     (iFifo$D_OUT[3:0] == 4'd0 || iFifo$D_OUT[3:0] == 4'd1 ||
	      iFifo$D_OUT[3:0] == 4'd2 ||
	      iFifo$D_OUT[3:0] == 4'd5 ||
	      iFifo$D_OUT[3:0] == 4'd6 ||
	      iFifo$D_OUT[3:0] == 4'd7 ||
	      iFifo$D_OUT[3:0] == 4'd8) ;
  assign fpu_madd_fOperand_S0$DEQ = CAN_FIRE_RL_fpu_madd_s1_stage ;
  assign fpu_madd_fOperand_S0$CLR = 1'b0 ;

  // submodule fpu_madd_fProd_S2
  assign fpu_madd_fProd_S2$D_IN =
	     fpu_madd_fState_S1$D_OUT[105:53] *
	     fpu_madd_fState_S1$D_OUT[52:0] ;
  assign fpu_madd_fProd_S2$ENQ = CAN_FIRE_RL_fpu_madd_s2_stage ;
  assign fpu_madd_fProd_S2$DEQ = CAN_FIRE_RL_fpu_madd_s3_stage ;
  assign fpu_madd_fProd_S2$CLR = 1'b0 ;

  // submodule fpu_madd_fProd_S3
  assign fpu_madd_fProd_S3$D_IN = fpu_madd_fProd_S2$D_OUT ;
  assign fpu_madd_fProd_S3$ENQ = CAN_FIRE_RL_fpu_madd_s3_stage ;
  assign fpu_madd_fProd_S3$DEQ = CAN_FIRE_RL_fpu_madd_s4_stage ;
  assign fpu_madd_fProd_S3$CLR = 1'b0 ;

  // submodule fpu_madd_fResult_S9
  assign fpu_madd_fResult_S9$D_IN =
	     fpu_madd_fState_S8$D_OUT[140] ?
	       fpu_madd_fState_S8$D_OUT[139:71] :
	       IF_fpu_madd_fState_S8_first__960_BIT_67_963_AN_ETC___d3081 ;
  assign fpu_madd_fResult_S9$ENQ = CAN_FIRE_RL_fpu_madd_s9_stage ;
  assign fpu_madd_fResult_S9$DEQ = fpu_madd_fResult_S9$EMPTY_N ;
  assign fpu_madd_fResult_S9$CLR = 1'b0 ;

  // submodule fpu_madd_fState_S1
  assign fpu_madd_fState_S1$D_IN =
	     { x__h96539 == 11'd2047 &&
	       _theResult___fst_sfd__h96608 != 52'd0 &&
	       !_theResult___fst_sfd__h96608[51] ||
	       fpu_madd_fOperand_S0$D_OUT[129:119] == 11'd2047 &&
	       fpu_madd_fOperand_S0$D_OUT[118:67] != 52'd0 &&
	       !fpu_madd_fOperand_S0$D_OUT[118] ||
	       fpu_madd_fOperand_S0$D_OUT[65:55] == 11'd2047 &&
	       fpu_madd_fOperand_S0$D_OUT[54:3] != 52'd0 &&
	       !fpu_madd_fOperand_S0$D_OUT[54] ||
	       IF_fpu_madd_fOperand_S0_first__803_BIT_195_804_ETC___d1861,
	       IF_IF_fpu_madd_fOperand_S0_first__803_BIT_195__ETC___d1939,
	       IF_fpu_madd_fOperand_S0_first__803_BIT_195_804_ETC___d1947,
	       4'd0,
	       fpu_madd_fOperand_S0$D_OUT[2:0],
	       fpu_madd_fOperand_S0$D_OUT[195],
	       fpu_madd_fOperand_S0$D_OUT[195] &&
	       fpu_madd_fOperand_S0$D_OUT[194],
	       IF_fpu_madd_fOperand_S0_first__803_BIT_195_804_ETC___d1911,
	       NOT_fpu_madd_fOperand_S0_first__803_BIT_130_85_ETC___d1854,
	       IF_fpu_madd_fOperand_S0_first__803_BITS_129_TO_ETC___d1959 } ;
  assign fpu_madd_fState_S1$ENQ = CAN_FIRE_RL_fpu_madd_s1_stage ;
  assign fpu_madd_fState_S1$DEQ = CAN_FIRE_RL_fpu_madd_s2_stage ;
  assign fpu_madd_fState_S1$CLR = 1'b0 ;

  // submodule fpu_madd_fState_S2
  assign fpu_madd_fState_S2$D_IN = fpu_madd_fState_S1$D_OUT[257:106] ;
  assign fpu_madd_fState_S2$ENQ = CAN_FIRE_RL_fpu_madd_s2_stage ;
  assign fpu_madd_fState_S2$DEQ = CAN_FIRE_RL_fpu_madd_s3_stage ;
  assign fpu_madd_fState_S2$CLR = 1'b0 ;

  // submodule fpu_madd_fState_S3
  assign fpu_madd_fState_S3$D_IN = fpu_madd_fState_S2$D_OUT ;
  assign fpu_madd_fState_S3$ENQ = CAN_FIRE_RL_fpu_madd_s3_stage ;
  assign fpu_madd_fState_S3$DEQ = CAN_FIRE_RL_fpu_madd_s4_stage ;
  assign fpu_madd_fState_S3$CLR = 1'b0 ;

  // submodule fpu_madd_fState_S4
  assign fpu_madd_fState_S4$D_IN =
	     { fpu_madd_fState_S3$D_OUT[151:87],
	       IF_fpu_madd_fState_S3_first__995_BIT_151_996_T_ETC___d2525,
	       fpu_madd_fState_S3$D_OUT[81:14],
	       !fpu_madd_fState_S3$D_OUT[151] && fpu_madd_fState_S3$D_OUT[13],
	       fpu_madd_fState_S3$D_OUT[151] ?
		 63'd0 :
		 IF_fpu_madd_fState_S3_first__995_BITS_12_TO_0__ETC___d2536,
	       x__h131406 } ;
  assign fpu_madd_fState_S4$ENQ = CAN_FIRE_RL_fpu_madd_s4_stage ;
  assign fpu_madd_fState_S4$DEQ = CAN_FIRE_RL_fpu_madd_s5_stage ;
  assign fpu_madd_fState_S4$CLR = 1'b0 ;

  // submodule fpu_madd_fState_S5
  assign fpu_madd_fState_S5$D_IN =
	     { fpu_madd_fState_S4$D_OUT[203:130],
	       fpu_madd_fState_S4$D_OUT[129] != fpu_madd_fState_S4$D_OUT[65],
	       NOT_fpu_madd_fState_S4_first__547_BIT_130_553__ETC___d2584 ?
		 fpu_madd_fState_S4$D_OUT[65] :
		 fpu_madd_fState_S4$D_OUT[129],
	       IF_NOT_fpu_madd_fState_S4_first__547_BIT_130_5_ETC___d2595 } ;
  assign fpu_madd_fState_S5$ENQ = CAN_FIRE_RL_fpu_madd_s5_stage ;
  assign fpu_madd_fState_S5$DEQ = CAN_FIRE_RL_fpu_madd_s6_stage ;
  assign fpu_madd_fState_S5$CLR = 1'b0 ;

  // submodule fpu_madd_fState_S6
  assign fpu_madd_fState_S6$D_IN =
	     { fpu_madd_fState_S5$D_OUT[215:127],
	       fpu_madd_fState_S5$D_OUT[113:57],
	       x__h132359 } ;
  assign fpu_madd_fState_S6$ENQ = CAN_FIRE_RL_fpu_madd_s6_stage ;
  assign fpu_madd_fState_S6$DEQ = CAN_FIRE_RL_fpu_madd_s7_stage ;
  assign fpu_madd_fState_S6$CLR = 1'b0 ;

  // submodule fpu_madd_fState_S7
  assign fpu_madd_fState_S7$D_IN =
	     { fpu_madd_fState_S6$D_OUT[202:114], x__h132871, x__h132880 } ;
  assign fpu_madd_fState_S7$ENQ = CAN_FIRE_RL_fpu_madd_s7_stage ;
  assign fpu_madd_fState_S7$DEQ = CAN_FIRE_RL_fpu_madd_s8_stage ;
  assign fpu_madd_fState_S7$CLR = 1'b0 ;

  // submodule fpu_madd_fState_S8
  assign fpu_madd_fState_S8$D_IN =
	     { fpu_madd_fState_S7$D_OUT[202:138],
	       fpu_madd_fState_S7$D_OUT[202] ?
		 fpu_madd_fState_S7$D_OUT[137:133] :
		 fpu_madd_fState_S7_first__651_BITS_137_TO_133__ETC___d2942,
	       fpu_madd_fState_S7$D_OUT[132:129],
	       !fpu_madd_fState_S7$D_OUT[202] &&
	       fpu_madd_fState_S7$D_OUT[127],
	       fpu_madd_fState_S7$D_OUT[202] ?
		 63'd0 :
		 IF_IF_fpu_madd_fState_S7_first__651_BIT_128_65_ETC___d2952,
	       x__h141760,
	       fpu_madd_fState_S7$D_OUT[128] } ;
  assign fpu_madd_fState_S8$ENQ = CAN_FIRE_RL_fpu_madd_s8_stage ;
  assign fpu_madd_fState_S8$DEQ = CAN_FIRE_RL_fpu_madd_s9_stage ;
  assign fpu_madd_fState_S8$CLR = 1'b0 ;

  // submodule fpu_sqr64_fOperand_S0
  assign fpu_sqr64_fOperand_S0$D_IN =
	     { IF_iFifo_first__087_BIT_201_115_THEN_IF_iFifo__ETC___d3848,
	       iFifo$D_OUT[6:4] } ;
  assign fpu_sqr64_fOperand_S0$ENQ =
	     WILL_FIRE_RL_start_op && iFifo$D_OUT[3:0] == 4'd4 ;
  assign fpu_sqr64_fOperand_S0$DEQ = CAN_FIRE_RL_fpu_sqr64_s1_stage ;
  assign fpu_sqr64_fOperand_S0$CLR = 1'b0 ;

  // submodule fpu_sqr64_fResult_S5
  assign fpu_sqr64_fResult_S5$D_IN =
	     fpu_sqr64_fState_S4$D_OUT[138] ?
	       fpu_sqr64_fState_S4$D_OUT[137:69] :
	       { (fpu_sqr64_fState_S4$D_OUT[64:54] == 11'd2047) ?
		   fpu_sqr64_fState_S4$D_OUT[65:2] :
		   CASE_fpu_sqr64_fState_S4D_OUT_BITS_68_TO_66_0_ETC__q183,
		 fpu_sqr64_fState_S4$D_OUT[73:69] |
		 { 2'd0,
		   _theResult___fst_exp__h95990 == 11'd2047 &&
		   _theResult___fst_sfd__h95991 == 52'd0,
		   1'd0,
		   fpu_sqr64_fState_S4$D_OUT[64:54] != 11'd2047 &&
		   fpu_sqr64_fState_S4$D_OUT[1:0] != 2'b0 } } ;
  assign fpu_sqr64_fResult_S5$ENQ = CAN_FIRE_RL_fpu_sqr64_s5_stage ;
  assign fpu_sqr64_fResult_S5$DEQ = fpu_sqr64_fResult_S5$EMPTY_N ;
  assign fpu_sqr64_fResult_S5$CLR = 1'b0 ;

  // submodule fpu_sqr64_fState_S1
  assign fpu_sqr64_fState_S1$D_IN =
	     (fpu_sqr64_fOperand_S0$D_OUT[65:55] == 11'd2047 &&
	      fpu_sqr64_fOperand_S0$D_OUT[54:3] != 52'd0 &&
	      !fpu_sqr64_fOperand_S0$D_OUT[54]) ?
	       { 1'd1,
		 fpu_sqr64_fOperand_S0$D_OUT[66:55],
		 sfd__h45004,
		 130'h20AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA } :
	       IF_fpu_sqr64_fOperand_S0_first__059_BITS_65_TO_ETC___d1212 ;
  assign fpu_sqr64_fState_S1$ENQ = CAN_FIRE_RL_fpu_sqr64_s1_stage ;
  assign fpu_sqr64_fState_S1$DEQ = WILL_FIRE_RL_fpu_sqr64_s2_stage ;
  assign fpu_sqr64_fState_S1$CLR = 1'b0 ;

  // submodule fpu_sqr64_fState_S2
  assign fpu_sqr64_fState_S2$D_IN = fpu_sqr64_fState_S1$D_OUT[194:58] ;
  assign fpu_sqr64_fState_S2$ENQ = WILL_FIRE_RL_fpu_sqr64_s2_stage ;
  assign fpu_sqr64_fState_S2$DEQ = CAN_FIRE_RL_fpu_sqr64_s3_stage ;
  assign fpu_sqr64_fState_S2$CLR = 1'b0 ;

  // submodule fpu_sqr64_fState_S3
  assign fpu_sqr64_fState_S3$D_IN = { fpu_sqr64_fState_S2$D_OUT, x__h86149 } ;
  assign fpu_sqr64_fState_S3$ENQ = CAN_FIRE_RL_fpu_sqr64_s3_stage ;
  assign fpu_sqr64_fState_S3$DEQ = CAN_FIRE_RL_fpu_sqr64_s4_stage ;
  assign fpu_sqr64_fState_S3$CLR = 1'b0 ;

  // submodule fpu_sqr64_fState_S4
  assign fpu_sqr64_fState_S4$D_IN =
	     { fpu_sqr64_fState_S3$D_OUT[195:131],
	       fpu_sqr64_fState_S3$D_OUT[195] &&
	       fpu_sqr64_fState_S3$D_OUT[130],
	       fpu_sqr64_fState_S3$D_OUT[195] &&
	       fpu_sqr64_fState_S3$D_OUT[129],
	       IF_fpu_sqr64_fState_S3_first__375_BIT_195_376__ETC___d1671,
	       fpu_sqr64_fState_S3$D_OUT[125:122],
	       fpu_sqr64_fState_S3$D_OUT[195] ?
		 fpu_sqr64_fState_S3$D_OUT[121:59] :
		 IF_fpu_sqr64_fState_S3_first__375_BIT_58_384_A_ETC___d1678,
	       x__h95138 } ;
  assign fpu_sqr64_fState_S4$ENQ = CAN_FIRE_RL_fpu_sqr64_s4_stage ;
  assign fpu_sqr64_fState_S4$DEQ = CAN_FIRE_RL_fpu_sqr64_s5_stage ;
  assign fpu_sqr64_fState_S4$CLR = 1'b0 ;

  // submodule iFifo
  assign iFifo$D_IN = server_core_request_put ;
  assign iFifo$ENQ = EN_server_core_request_put ;
  assign iFifo$DEQ = CAN_FIRE_RL_start_op ;
  assign iFifo$CLR = CAN_FIRE_RL_rl_reset ;

  // submodule isDoubleFifo
  assign isDoubleFifo$D_IN = !iFifo$D_OUT[201] ;
  assign isDoubleFifo$ENQ = CAN_FIRE_RL_start_op ;
  assign isDoubleFifo$DEQ = CAN_FIRE_RL_passResult ;
  assign isDoubleFifo$CLR = CAN_FIRE_RL_rl_reset ;

  // submodule isNegateFifo
  assign isNegateFifo$D_IN =
	     iFifo$D_OUT[3:0] == 4'd7 || iFifo$D_OUT[3:0] == 4'd8 ;
  assign isNegateFifo$ENQ = CAN_FIRE_RL_start_op ;
  assign isNegateFifo$DEQ = CAN_FIRE_RL_passResult ;
  assign isNegateFifo$CLR = CAN_FIRE_RL_rl_reset ;

  // submodule oFifo
  assign oFifo$D_IN =
	     { !isDoubleFifo$D_OUT,
	       IF_isDoubleFifo_first__407_THEN_IF_isNegateFif_ETC___d6657,
	       isDoubleFifo$D_OUT ?
		 resWire$wget[4:0] :
		 resWire_wget__410_BITS_4_TO_0_658_OR_NOT_resWi_ETC___d6768 } ;
  assign oFifo$ENQ = CAN_FIRE_RL_passResult ;
  assign oFifo$DEQ = EN_server_core_response_get ;
  assign oFifo$CLR = CAN_FIRE_RL_rl_reset ;

  // submodule resetReqsF
  assign resetReqsF$ENQ = EN_server_reset_request_put ;
  assign resetReqsF$DEQ = CAN_FIRE_RL_rl_reset ;
  assign resetReqsF$CLR = 1'b0 ;

  // submodule resetRspsF
  assign resetRspsF$ENQ = CAN_FIRE_RL_rl_reset ;
  assign resetRspsF$DEQ = EN_server_reset_response_get ;
  assign resetRspsF$CLR = 1'b0 ;

  // submodule rmdFifo
  assign rmdFifo$D_IN = iFifo$D_OUT[6:4] ;
  assign rmdFifo$ENQ = CAN_FIRE_RL_start_op ;
  assign rmdFifo$DEQ = CAN_FIRE_RL_passResult ;
  assign rmdFifo$CLR = CAN_FIRE_RL_rl_reset ;

  // remaining internal signals
  assign IF_0_CONCAT_IF_IF_0b0_CONCAT_NOT_resWire_wget__ETC__q133 =
	     _0_CONCAT_IF_IF_0b0_CONCAT_NOT_resWire_wget__41_ETC___d5769 ?
	       _theResult___snd__h277749 :
	       _theResult____h269577 ;
  assign IF_0_CONCAT_IF_IF_3074_MINUS_SEXT_iFifo_first__ETC__q37 =
	     _0_CONCAT_IF_IF_3074_MINUS_SEXT_iFifo_first__08_ETC___d3574 ?
	       _theResult___snd__h172915 :
	       _theResult____h164614 ;
  assign IF_0_CONCAT_IF_IF_3074_MINUS_SEXT_iFifo_first__ETC__q64 =
	     _0_CONCAT_IF_IF_3074_MINUS_SEXT_iFifo_first__08_ETC___d4282 ?
	       _theResult___snd__h250492 :
	       _theResult____h242191 ;
  assign IF_0_CONCAT_IF_IF_3074_MINUS_SEXT_iFifo_first__ETC__q97 =
	     _0_CONCAT_IF_IF_3074_MINUS_SEXT_iFifo_first__08_ETC___d5057 ?
	       _theResult___snd__h211553 :
	       _theResult____h203252 ;
  assign IF_0_CONCAT_IF_IF_3970_MINUS_SEXT_resWire_wget_ETC__q139 =
	     _0_CONCAT_IF_IF_3970_MINUS_SEXT_resWire_wget__4_ETC___d6280 ?
	       _theResult___snd__h295515 :
	       _theResult____h287214 ;
  assign IF_0_CONCAT_IF_IF_7170_MINUS_fpu_madd_fState_S_ETC__q24 =
	     _0_CONCAT_IF_IF_7170_MINUS_fpu_madd_fState_S3_f_ETC___d2463 ?
	       _theResult___snd__h131023 :
	       _theResult___snd__h131018 ;
  assign IF_0_CONCAT_IF_IF_fpu_div64_fState_S3_first__8_ETC__q12 =
	     _0_CONCAT_IF_IF_fpu_div64_fState_S3_first__86_B_ETC___d883 ?
	       _theResult___snd__h42409 :
	       _theResult___snd__h42404 ;
  assign IF_0_CONCAT_IF_IF_fpu_madd_fState_S7_first__65_ETC__q29 =
	     _0_CONCAT_IF_IF_fpu_madd_fState_S7_first__651_B_ETC___d2904 ?
	       _theResult___snd__h141449 :
	       _theResult___snd__h141444 ;
  assign IF_0_CONCAT_IF_fpu_sqr64_fState_S3_first__375__ETC__q19 =
	     _0_CONCAT_IF_fpu_sqr64_fState_S3_first__375_BIT_ETC___d1633 ?
	       _theResult___snd__h94826 :
	       _theResult___snd__h94821 ;
  assign IF_0_CONCAT_IF_iFifo_first__087_BITS_102_TO_95_ETC__q100 =
	     _0_CONCAT_IF_iFifo_first__087_BITS_102_TO_95_62_ETC___d5107 ?
	       _theResult___snd__h201963 :
	       _theResult___snd__h220275 ;
  assign IF_0_CONCAT_IF_iFifo_first__087_BITS_102_TO_95_ETC__q93 =
	     _0_CONCAT_IF_iFifo_first__087_BITS_102_TO_95_62_ETC___d4759 ?
	       _theResult___snd__h201963 :
	       57'd0 ;
  assign IF_0_CONCAT_IF_iFifo_first__087_BITS_167_TO_16_ETC__q33 =
	     _0_CONCAT_IF_iFifo_first__087_BITS_167_TO_160_1_ETC___d3273 ?
	       _theResult___snd__h163325 :
	       57'd0 ;
  assign IF_0_CONCAT_IF_iFifo_first__087_BITS_167_TO_16_ETC__q40 =
	     _0_CONCAT_IF_iFifo_first__087_BITS_167_TO_160_1_ETC___d3624 ?
	       _theResult___snd__h163325 :
	       _theResult___snd__h181637 ;
  assign IF_0_CONCAT_IF_iFifo_first__087_BITS_37_TO_30__ETC__q60 =
	     _0_CONCAT_IF_iFifo_first__087_BITS_37_TO_30_850_ETC___d3984 ?
	       _theResult___snd__h240902 :
	       57'd0 ;
  assign IF_0_CONCAT_IF_iFifo_first__087_BITS_37_TO_30__ETC__q67 =
	     _0_CONCAT_IF_iFifo_first__087_BITS_37_TO_30_850_ETC___d4332 ?
	       _theResult___snd__h240902 :
	       _theResult___snd__h259214 ;
  assign IF_0_CONCAT_IF_resWire_wget__410_BITS_67_TO_57_ETC__q135 =
	     _0_CONCAT_IF_resWire_wget__410_BITS_67_TO_57_41_ETC___d5984 ?
	       _theResult___snd__h286331 :
	       57'd0 ;
  assign IF_0_CONCAT_IF_resWire_wget__410_BITS_67_TO_57_ETC__q142 =
	     _0_CONCAT_IF_resWire_wget__410_BITS_67_TO_57_41_ETC___d6333 ?
	       _theResult___snd__h286331 :
	       _theResult___snd__h304121 ;
  assign IF_0b0_CONCAT_NOT_fpu_div64_fState_S4_first__4_ETC___d980 =
	     sfd__h42982[53] ?
	       ((fpu_div64_fState_S4$D_OUT[64:54] == 11'd2046) ?
		  63'h7FF0000000000000 :
		  { din_inc___2_exp__h43566, sfd__h42982[52:1] }) :
	       { IF_fpu_div64_fState_S4_first__43_BITS_64_TO_54_ETC___d977,
		 sfd__h42982[51:0] } ;
  assign IF_0b0_CONCAT_NOT_fpu_madd_fState_S8_first__96_ETC___d3065 =
	     sfd__h142040[53] ?
	       ((fpu_madd_fState_S8$D_OUT[65:55] == 11'd2046) ?
		  63'h7FF0000000000000 :
		  { din_inc___2_exp__h142626, sfd__h142040[52:1] }) :
	       { IF_fpu_madd_fState_S8_first__960_BITS_65_TO_55_ETC___d2986,
		 sfd__h142040[51:0] } ;
  assign IF_0b0_CONCAT_NOT_fpu_sqr64_fState_S4_first__6_ETC___d1724 =
	     sfd__h95416[53] ?
	       ((fpu_sqr64_fState_S4$D_OUT[64:54] == 11'd2046) ?
		  63'h7FF0000000000000 :
		  { din_inc___2_exp__h96000, sfd__h95416[52:1] }) :
	       { IF_fpu_sqr64_fState_S4_first__687_BITS_64_TO_5_ETC___d1721,
		 sfd__h95416[51:0] } ;
  assign IF_3074_MINUS_0_CONCAT_IF_resWire_wget__410_BI_ETC___d6025 =
	     _3074_MINUS_0_CONCAT_IF_resWire_wget__410_BIT_5_ETC___d5533 ?
	       ((_theResult___fst_exp__h277686 == 8'd255) ?
		  !resWire$wget[68] :
		  IF_rmdFifo_first__778_EQ_0_779_THEN_IF_IF_IF_I_ETC___d5823) :
	       ((_theResult___fst_exp__h286342 == 8'd255) ?
		  !resWire$wget[68] :
		  IF_rmdFifo_first__778_EQ_0_779_THEN_IF_IF_IF_r_ETC___d6023) ;
  assign IF_3074_MINUS_0_CONCAT_IF_resWire_wget__410_BI_ETC___d6399 =
	     _3074_MINUS_0_CONCAT_IF_resWire_wget__410_BIT_5_ETC___d5533 ?
	       ((_theResult___fst_exp__h277686 == 8'd255) ?
		  resWire$wget[68] :
		  IF_rmdFifo_first__778_EQ_0_779_THEN_IF_IF_IF_I_ETC___d6388) :
	       ((_theResult___fst_exp__h286342 == 8'd255) ?
		  resWire$wget[68] :
		  IF_rmdFifo_first__778_EQ_0_779_THEN_IF_IF_IF_r_ETC___d6397) ;
  assign IF_3970_MINUS_0_CONCAT_IF_iFifo_first__087_BIT_ETC___d3317 =
	     _3970_MINUS_0_CONCAT_IF_iFifo_first__087_BIT_15_ETC___d3190 ?
	       (iFifo$D_OUT[6:4] == 3'd0 || iFifo$D_OUT[6:4] == 3'd1 ||
		iFifo$D_OUT[6:4] == 3'd2 ||
		iFifo$D_OUT[6:4] == 3'd3 ||
		iFifo$D_OUT[6:4] == 3'd4) &&
	       iFifo$D_OUT[168] :
	       ((_theResult___fst_exp__h163336 == 11'd2047) ?
		  iFifo$D_OUT[168] :
		  CASE_iFifoD_OUT_BITS_6_TO_4_0_CASE_guard55375_ETC__q55) ;
  assign IF_3970_MINUS_0_CONCAT_IF_iFifo_first__087_BIT_ETC___d4027 =
	     _3970_MINUS_0_CONCAT_IF_iFifo_first__087_BIT_29_ETC___d3910 ?
	       (iFifo$D_OUT[6:4] == 3'd0 || iFifo$D_OUT[6:4] == 3'd1 ||
		iFifo$D_OUT[6:4] == 3'd2 ||
		iFifo$D_OUT[6:4] == 3'd3 ||
		iFifo$D_OUT[6:4] == 3'd4) &&
	       iFifo$D_OUT[38] :
	       ((_theResult___fst_exp__h240913 == 11'd2047) ?
		  iFifo$D_OUT[38] :
		  CASE_iFifoD_OUT_BITS_6_TO_4_0_CASE_guard32952_ETC__q82) ;
  assign IF_3970_MINUS_0_CONCAT_IF_iFifo_first__087_BIT_ETC___d4581 =
	     _3970_MINUS_0_CONCAT_IF_iFifo_first__087_BIT_29_ETC___d3910 ?
	       iFifo$D_OUT[6:4] != 3'd0 && iFifo$D_OUT[6:4] != 3'd1 &&
	       iFifo$D_OUT[6:4] != 3'd2 &&
	       iFifo$D_OUT[6:4] != 3'd3 &&
	       iFifo$D_OUT[6:4] != 3'd4 ||
	       !iFifo$D_OUT[38] :
	       ((_theResult___fst_exp__h240913 == 11'd2047) ?
		  !iFifo$D_OUT[38] :
		  CASE_iFifoD_OUT_BITS_6_TO_4_0_CASE_guard32952_ETC__q88) ;
  assign IF_3970_MINUS_0_CONCAT_IF_iFifo_first__087_BIT_ETC___d4802 =
	     _3970_MINUS_0_CONCAT_IF_iFifo_first__087_BIT_94_ETC___d4685 ?
	       (iFifo$D_OUT[6:4] == 3'd0 || iFifo$D_OUT[6:4] == 3'd1 ||
		iFifo$D_OUT[6:4] == 3'd2 ||
		iFifo$D_OUT[6:4] == 3'd3 ||
		iFifo$D_OUT[6:4] == 3'd4) &&
	       iFifo$D_OUT[103] :
	       ((_theResult___fst_exp__h201974 == 11'd2047) ?
		  iFifo$D_OUT[103] :
		  CASE_iFifoD_OUT_BITS_6_TO_4_0_CASE_guard94013_ETC__q115) ;
  assign IF_3970_MINUS_0_CONCAT_IF_iFifo_first__087_BIT_ETC___d5347 =
	     _3970_MINUS_0_CONCAT_IF_iFifo_first__087_BIT_94_ETC___d4685 ?
	       iFifo$D_OUT[6:4] != 3'd0 && iFifo$D_OUT[6:4] != 3'd1 &&
	       iFifo$D_OUT[6:4] != 3'd2 &&
	       iFifo$D_OUT[6:4] != 3'd3 &&
	       iFifo$D_OUT[6:4] != 3'd4 ||
	       !iFifo$D_OUT[103] :
	       ((_theResult___fst_exp__h201974 == 11'd2047) ?
		  !iFifo$D_OUT[103] :
		  CASE_iFifoD_OUT_BITS_6_TO_4_0_CASE_guard94013_ETC__q121) ;
  assign IF_IF_0b0_CONCAT_NOT_resWire_wget__410_BITS_67_ETC___d5767 =
	     (_theResult____h269577[56] ?
		6'd0 :
		(_theResult____h269577[55] ?
		   6'd1 :
		   (_theResult____h269577[54] ?
		      6'd2 :
		      (_theResult____h269577[53] ?
			 6'd3 :
			 (_theResult____h269577[52] ?
			    6'd4 :
			    (_theResult____h269577[51] ?
			       6'd5 :
			       (_theResult____h269577[50] ?
				  6'd6 :
				  (_theResult____h269577[49] ?
				     6'd7 :
				     (_theResult____h269577[48] ?
					6'd8 :
					(_theResult____h269577[47] ?
					   6'd9 :
					   (_theResult____h269577[46] ?
					      6'd10 :
					      (_theResult____h269577[45] ?
						 6'd11 :
						 (_theResult____h269577[44] ?
						    6'd12 :
						    (_theResult____h269577[43] ?
						       6'd13 :
						       (_theResult____h269577[42] ?
							  6'd14 :
							  (_theResult____h269577[41] ?
							     6'd15 :
							     (_theResult____h269577[40] ?
								6'd16 :
								(_theResult____h269577[39] ?
								   6'd17 :
								   (_theResult____h269577[38] ?
								      6'd18 :
								      (_theResult____h269577[37] ?
									 6'd19 :
									 (_theResult____h269577[36] ?
									    6'd20 :
									    (_theResult____h269577[35] ?
									       6'd21 :
									       (_theResult____h269577[34] ?
										  6'd22 :
										  (_theResult____h269577[33] ?
										     6'd23 :
										     (_theResult____h269577[32] ?
											6'd24 :
											(_theResult____h269577[31] ?
											   6'd25 :
											   (_theResult____h269577[30] ?
											      6'd26 :
											      (_theResult____h269577[29] ?
												 6'd27 :
												 (_theResult____h269577[28] ?
												    6'd28 :
												    (_theResult____h269577[27] ?
												       6'd29 :
												       (_theResult____h269577[26] ?
													  6'd30 :
													  (_theResult____h269577[25] ?
													     6'd31 :
													     (_theResult____h269577[24] ?
														6'd32 :
														(_theResult____h269577[23] ?
														   6'd33 :
														   (_theResult____h269577[22] ?
														      6'd34 :
														      (_theResult____h269577[21] ?
															 6'd35 :
															 (_theResult____h269577[20] ?
															    6'd36 :
															    (_theResult____h269577[19] ?
															       6'd37 :
															       (_theResult____h269577[18] ?
																  6'd38 :
																  (_theResult____h269577[17] ?
																     6'd39 :
																     (_theResult____h269577[16] ?
																	6'd40 :
																	(_theResult____h269577[15] ?
																	   6'd41 :
																	   (_theResult____h269577[14] ?
																	      6'd42 :
																	      (_theResult____h269577[13] ?
																		 6'd43 :
																		 (_theResult____h269577[12] ?
																		    6'd44 :
																		    (_theResult____h269577[11] ?
																		       6'd45 :
																		       (_theResult____h269577[10] ?
																			  6'd46 :
																			  (_theResult____h269577[9] ?
																			     6'd47 :
																			     (_theResult____h269577[8] ?
																				6'd48 :
																				(_theResult____h269577[7] ?
																				   6'd49 :
																				   (_theResult____h269577[6] ?
																				      6'd50 :
																				      (_theResult____h269577[5] ?
																					 6'd51 :
																					 (_theResult____h269577[4] ?
																					    6'd52 :
																					    (_theResult____h269577[3] ?
																					       6'd53 :
																					       (_theResult____h269577[2] ?
																						  6'd54 :
																						  (_theResult____h269577[1] ?
																						     6'd55 :
																						     (_theResult____h269577[0] ?
																							6'd56 :
																							6'd57))))))))))))))))))))))))))))))))))))))))))))))))))))))))) -
	     6'd1 ;
  assign IF_IF_3074_MINUS_SEXT_iFifo_first__087_BITS_10_ETC___d5055 =
	     (_theResult____h203252[56] ?
		6'd0 :
		(_theResult____h203252[55] ?
		   6'd1 :
		   (_theResult____h203252[54] ?
		      6'd2 :
		      (_theResult____h203252[53] ?
			 6'd3 :
			 (_theResult____h203252[52] ?
			    6'd4 :
			    (_theResult____h203252[51] ?
			       6'd5 :
			       (_theResult____h203252[50] ?
				  6'd6 :
				  (_theResult____h203252[49] ?
				     6'd7 :
				     (_theResult____h203252[48] ?
					6'd8 :
					(_theResult____h203252[47] ?
					   6'd9 :
					   (_theResult____h203252[46] ?
					      6'd10 :
					      (_theResult____h203252[45] ?
						 6'd11 :
						 (_theResult____h203252[44] ?
						    6'd12 :
						    (_theResult____h203252[43] ?
						       6'd13 :
						       (_theResult____h203252[42] ?
							  6'd14 :
							  (_theResult____h203252[41] ?
							     6'd15 :
							     (_theResult____h203252[40] ?
								6'd16 :
								(_theResult____h203252[39] ?
								   6'd17 :
								   (_theResult____h203252[38] ?
								      6'd18 :
								      (_theResult____h203252[37] ?
									 6'd19 :
									 (_theResult____h203252[36] ?
									    6'd20 :
									    (_theResult____h203252[35] ?
									       6'd21 :
									       (_theResult____h203252[34] ?
										  6'd22 :
										  (_theResult____h203252[33] ?
										     6'd23 :
										     (_theResult____h203252[32] ?
											6'd24 :
											(_theResult____h203252[31] ?
											   6'd25 :
											   (_theResult____h203252[30] ?
											      6'd26 :
											      (_theResult____h203252[29] ?
												 6'd27 :
												 (_theResult____h203252[28] ?
												    6'd28 :
												    (_theResult____h203252[27] ?
												       6'd29 :
												       (_theResult____h203252[26] ?
													  6'd30 :
													  (_theResult____h203252[25] ?
													     6'd31 :
													     (_theResult____h203252[24] ?
														6'd32 :
														(_theResult____h203252[23] ?
														   6'd33 :
														   (_theResult____h203252[22] ?
														      6'd34 :
														      (_theResult____h203252[21] ?
															 6'd35 :
															 (_theResult____h203252[20] ?
															    6'd36 :
															    (_theResult____h203252[19] ?
															       6'd37 :
															       (_theResult____h203252[18] ?
																  6'd38 :
																  (_theResult____h203252[17] ?
																     6'd39 :
																     (_theResult____h203252[16] ?
																	6'd40 :
																	(_theResult____h203252[15] ?
																	   6'd41 :
																	   (_theResult____h203252[14] ?
																	      6'd42 :
																	      (_theResult____h203252[13] ?
																		 6'd43 :
																		 (_theResult____h203252[12] ?
																		    6'd44 :
																		    (_theResult____h203252[11] ?
																		       6'd45 :
																		       (_theResult____h203252[10] ?
																			  6'd46 :
																			  (_theResult____h203252[9] ?
																			     6'd47 :
																			     (_theResult____h203252[8] ?
																				6'd48 :
																				(_theResult____h203252[7] ?
																				   6'd49 :
																				   (_theResult____h203252[6] ?
																				      6'd50 :
																				      (_theResult____h203252[5] ?
																					 6'd51 :
																					 (_theResult____h203252[4] ?
																					    6'd52 :
																					    (_theResult____h203252[3] ?
																					       6'd53 :
																					       (_theResult____h203252[2] ?
																						  6'd54 :
																						  (_theResult____h203252[1] ?
																						     6'd55 :
																						     (_theResult____h203252[0] ?
																							6'd56 :
																							6'd57))))))))))))))))))))))))))))))))))))))))))))))))))))))))) -
	     6'd1 ;
  assign IF_IF_3074_MINUS_SEXT_iFifo_first__087_BITS_16_ETC___d3572 =
	     (_theResult____h164614[56] ?
		6'd0 :
		(_theResult____h164614[55] ?
		   6'd1 :
		   (_theResult____h164614[54] ?
		      6'd2 :
		      (_theResult____h164614[53] ?
			 6'd3 :
			 (_theResult____h164614[52] ?
			    6'd4 :
			    (_theResult____h164614[51] ?
			       6'd5 :
			       (_theResult____h164614[50] ?
				  6'd6 :
				  (_theResult____h164614[49] ?
				     6'd7 :
				     (_theResult____h164614[48] ?
					6'd8 :
					(_theResult____h164614[47] ?
					   6'd9 :
					   (_theResult____h164614[46] ?
					      6'd10 :
					      (_theResult____h164614[45] ?
						 6'd11 :
						 (_theResult____h164614[44] ?
						    6'd12 :
						    (_theResult____h164614[43] ?
						       6'd13 :
						       (_theResult____h164614[42] ?
							  6'd14 :
							  (_theResult____h164614[41] ?
							     6'd15 :
							     (_theResult____h164614[40] ?
								6'd16 :
								(_theResult____h164614[39] ?
								   6'd17 :
								   (_theResult____h164614[38] ?
								      6'd18 :
								      (_theResult____h164614[37] ?
									 6'd19 :
									 (_theResult____h164614[36] ?
									    6'd20 :
									    (_theResult____h164614[35] ?
									       6'd21 :
									       (_theResult____h164614[34] ?
										  6'd22 :
										  (_theResult____h164614[33] ?
										     6'd23 :
										     (_theResult____h164614[32] ?
											6'd24 :
											(_theResult____h164614[31] ?
											   6'd25 :
											   (_theResult____h164614[30] ?
											      6'd26 :
											      (_theResult____h164614[29] ?
												 6'd27 :
												 (_theResult____h164614[28] ?
												    6'd28 :
												    (_theResult____h164614[27] ?
												       6'd29 :
												       (_theResult____h164614[26] ?
													  6'd30 :
													  (_theResult____h164614[25] ?
													     6'd31 :
													     (_theResult____h164614[24] ?
														6'd32 :
														(_theResult____h164614[23] ?
														   6'd33 :
														   (_theResult____h164614[22] ?
														      6'd34 :
														      (_theResult____h164614[21] ?
															 6'd35 :
															 (_theResult____h164614[20] ?
															    6'd36 :
															    (_theResult____h164614[19] ?
															       6'd37 :
															       (_theResult____h164614[18] ?
																  6'd38 :
																  (_theResult____h164614[17] ?
																     6'd39 :
																     (_theResult____h164614[16] ?
																	6'd40 :
																	(_theResult____h164614[15] ?
																	   6'd41 :
																	   (_theResult____h164614[14] ?
																	      6'd42 :
																	      (_theResult____h164614[13] ?
																		 6'd43 :
																		 (_theResult____h164614[12] ?
																		    6'd44 :
																		    (_theResult____h164614[11] ?
																		       6'd45 :
																		       (_theResult____h164614[10] ?
																			  6'd46 :
																			  (_theResult____h164614[9] ?
																			     6'd47 :
																			     (_theResult____h164614[8] ?
																				6'd48 :
																				(_theResult____h164614[7] ?
																				   6'd49 :
																				   (_theResult____h164614[6] ?
																				      6'd50 :
																				      (_theResult____h164614[5] ?
																					 6'd51 :
																					 (_theResult____h164614[4] ?
																					    6'd52 :
																					    (_theResult____h164614[3] ?
																					       6'd53 :
																					       (_theResult____h164614[2] ?
																						  6'd54 :
																						  (_theResult____h164614[1] ?
																						     6'd55 :
																						     (_theResult____h164614[0] ?
																							6'd56 :
																							6'd57))))))))))))))))))))))))))))))))))))))))))))))))))))))))) -
	     6'd1 ;
  assign IF_IF_3074_MINUS_SEXT_iFifo_first__087_BITS_37_ETC___d4280 =
	     (_theResult____h242191[56] ?
		6'd0 :
		(_theResult____h242191[55] ?
		   6'd1 :
		   (_theResult____h242191[54] ?
		      6'd2 :
		      (_theResult____h242191[53] ?
			 6'd3 :
			 (_theResult____h242191[52] ?
			    6'd4 :
			    (_theResult____h242191[51] ?
			       6'd5 :
			       (_theResult____h242191[50] ?
				  6'd6 :
				  (_theResult____h242191[49] ?
				     6'd7 :
				     (_theResult____h242191[48] ?
					6'd8 :
					(_theResult____h242191[47] ?
					   6'd9 :
					   (_theResult____h242191[46] ?
					      6'd10 :
					      (_theResult____h242191[45] ?
						 6'd11 :
						 (_theResult____h242191[44] ?
						    6'd12 :
						    (_theResult____h242191[43] ?
						       6'd13 :
						       (_theResult____h242191[42] ?
							  6'd14 :
							  (_theResult____h242191[41] ?
							     6'd15 :
							     (_theResult____h242191[40] ?
								6'd16 :
								(_theResult____h242191[39] ?
								   6'd17 :
								   (_theResult____h242191[38] ?
								      6'd18 :
								      (_theResult____h242191[37] ?
									 6'd19 :
									 (_theResult____h242191[36] ?
									    6'd20 :
									    (_theResult____h242191[35] ?
									       6'd21 :
									       (_theResult____h242191[34] ?
										  6'd22 :
										  (_theResult____h242191[33] ?
										     6'd23 :
										     (_theResult____h242191[32] ?
											6'd24 :
											(_theResult____h242191[31] ?
											   6'd25 :
											   (_theResult____h242191[30] ?
											      6'd26 :
											      (_theResult____h242191[29] ?
												 6'd27 :
												 (_theResult____h242191[28] ?
												    6'd28 :
												    (_theResult____h242191[27] ?
												       6'd29 :
												       (_theResult____h242191[26] ?
													  6'd30 :
													  (_theResult____h242191[25] ?
													     6'd31 :
													     (_theResult____h242191[24] ?
														6'd32 :
														(_theResult____h242191[23] ?
														   6'd33 :
														   (_theResult____h242191[22] ?
														      6'd34 :
														      (_theResult____h242191[21] ?
															 6'd35 :
															 (_theResult____h242191[20] ?
															    6'd36 :
															    (_theResult____h242191[19] ?
															       6'd37 :
															       (_theResult____h242191[18] ?
																  6'd38 :
																  (_theResult____h242191[17] ?
																     6'd39 :
																     (_theResult____h242191[16] ?
																	6'd40 :
																	(_theResult____h242191[15] ?
																	   6'd41 :
																	   (_theResult____h242191[14] ?
																	      6'd42 :
																	      (_theResult____h242191[13] ?
																		 6'd43 :
																		 (_theResult____h242191[12] ?
																		    6'd44 :
																		    (_theResult____h242191[11] ?
																		       6'd45 :
																		       (_theResult____h242191[10] ?
																			  6'd46 :
																			  (_theResult____h242191[9] ?
																			     6'd47 :
																			     (_theResult____h242191[8] ?
																				6'd48 :
																				(_theResult____h242191[7] ?
																				   6'd49 :
																				   (_theResult____h242191[6] ?
																				      6'd50 :
																				      (_theResult____h242191[5] ?
																					 6'd51 :
																					 (_theResult____h242191[4] ?
																					    6'd52 :
																					    (_theResult____h242191[3] ?
																					       6'd53 :
																					       (_theResult____h242191[2] ?
																						  6'd54 :
																						  (_theResult____h242191[1] ?
																						     6'd55 :
																						     (_theResult____h242191[0] ?
																							6'd56 :
																							6'd57))))))))))))))))))))))))))))))))))))))))))))))))))))))))) -
	     6'd1 ;
  assign IF_IF_3970_MINUS_SEXT_resWire_wget__410_BITS_6_ETC___d6278 =
	     (_theResult____h287214[56] ?
		6'd0 :
		(_theResult____h287214[55] ?
		   6'd1 :
		   (_theResult____h287214[54] ?
		      6'd2 :
		      (_theResult____h287214[53] ?
			 6'd3 :
			 (_theResult____h287214[52] ?
			    6'd4 :
			    (_theResult____h287214[51] ?
			       6'd5 :
			       (_theResult____h287214[50] ?
				  6'd6 :
				  (_theResult____h287214[49] ?
				     6'd7 :
				     (_theResult____h287214[48] ?
					6'd8 :
					(_theResult____h287214[47] ?
					   6'd9 :
					   (_theResult____h287214[46] ?
					      6'd10 :
					      (_theResult____h287214[45] ?
						 6'd11 :
						 (_theResult____h287214[44] ?
						    6'd12 :
						    (_theResult____h287214[43] ?
						       6'd13 :
						       (_theResult____h287214[42] ?
							  6'd14 :
							  (_theResult____h287214[41] ?
							     6'd15 :
							     (_theResult____h287214[40] ?
								6'd16 :
								(_theResult____h287214[39] ?
								   6'd17 :
								   (_theResult____h287214[38] ?
								      6'd18 :
								      (_theResult____h287214[37] ?
									 6'd19 :
									 (_theResult____h287214[36] ?
									    6'd20 :
									    (_theResult____h287214[35] ?
									       6'd21 :
									       (_theResult____h287214[34] ?
										  6'd22 :
										  (_theResult____h287214[33] ?
										     6'd23 :
										     (_theResult____h287214[32] ?
											6'd24 :
											(_theResult____h287214[31] ?
											   6'd25 :
											   (_theResult____h287214[30] ?
											      6'd26 :
											      (_theResult____h287214[29] ?
												 6'd27 :
												 (_theResult____h287214[28] ?
												    6'd28 :
												    (_theResult____h287214[27] ?
												       6'd29 :
												       (_theResult____h287214[26] ?
													  6'd30 :
													  (_theResult____h287214[25] ?
													     6'd31 :
													     (_theResult____h287214[24] ?
														6'd32 :
														(_theResult____h287214[23] ?
														   6'd33 :
														   (_theResult____h287214[22] ?
														      6'd34 :
														      (_theResult____h287214[21] ?
															 6'd35 :
															 (_theResult____h287214[20] ?
															    6'd36 :
															    (_theResult____h287214[19] ?
															       6'd37 :
															       (_theResult____h287214[18] ?
																  6'd38 :
																  (_theResult____h287214[17] ?
																     6'd39 :
																     (_theResult____h287214[16] ?
																	6'd40 :
																	(_theResult____h287214[15] ?
																	   6'd41 :
																	   (_theResult____h287214[14] ?
																	      6'd42 :
																	      (_theResult____h287214[13] ?
																		 6'd43 :
																		 (_theResult____h287214[12] ?
																		    6'd44 :
																		    (_theResult____h287214[11] ?
																		       6'd45 :
																		       (_theResult____h287214[10] ?
																			  6'd46 :
																			  (_theResult____h287214[9] ?
																			     6'd47 :
																			     (_theResult____h287214[8] ?
																				6'd48 :
																				(_theResult____h287214[7] ?
																				   6'd49 :
																				   (_theResult____h287214[6] ?
																				      6'd50 :
																				      (_theResult____h287214[5] ?
																					 6'd51 :
																					 (_theResult____h287214[4] ?
																					    6'd52 :
																					    (_theResult____h287214[3] ?
																					       6'd53 :
																					       (_theResult____h287214[2] ?
																						  6'd54 :
																						  (_theResult____h287214[1] ?
																						     6'd55 :
																						     (_theResult____h287214[0] ?
																							6'd56 :
																							6'd57))))))))))))))))))))))))))))))))))))))))))))))))))))))))) -
	     6'd1 ;
  assign IF_IF_7170_MINUS_fpu_madd_fState_S3_first__995_ETC___d2031 =
	     (din_exp__h130866 == 11'd0) ?
	       12'd3074 :
	       { din_exp30866_MINUS_1023__q23[10],
		 din_exp30866_MINUS_1023__q23 } ;
  assign IF_IF_7170_MINUS_fpu_madd_fState_S3_first__995_ETC___d2460 =
	     (sfdBC__h115662[105] ?
		7'd0 :
		(sfdBC__h115662[104] ?
		   7'd1 :
		   (sfdBC__h115662[103] ?
		      7'd2 :
		      (sfdBC__h115662[102] ?
			 7'd3 :
			 (sfdBC__h115662[101] ?
			    7'd4 :
			    (sfdBC__h115662[100] ?
			       7'd5 :
			       (sfdBC__h115662[99] ?
				  7'd6 :
				  (sfdBC__h115662[98] ?
				     7'd7 :
				     (sfdBC__h115662[97] ?
					7'd8 :
					(sfdBC__h115662[96] ?
					   7'd9 :
					   (sfdBC__h115662[95] ?
					      7'd10 :
					      (sfdBC__h115662[94] ?
						 7'd11 :
						 (sfdBC__h115662[93] ?
						    7'd12 :
						    (sfdBC__h115662[92] ?
						       7'd13 :
						       (sfdBC__h115662[91] ?
							  7'd14 :
							  (sfdBC__h115662[90] ?
							     7'd15 :
							     (sfdBC__h115662[89] ?
								7'd16 :
								(sfdBC__h115662[88] ?
								   7'd17 :
								   (sfdBC__h115662[87] ?
								      7'd18 :
								      (sfdBC__h115662[86] ?
									 7'd19 :
									 (sfdBC__h115662[85] ?
									    7'd20 :
									    (sfdBC__h115662[84] ?
									       7'd21 :
									       (sfdBC__h115662[83] ?
										  7'd22 :
										  (sfdBC__h115662[82] ?
										     7'd23 :
										     (sfdBC__h115662[81] ?
											7'd24 :
											(sfdBC__h115662[80] ?
											   7'd25 :
											   (sfdBC__h115662[79] ?
											      7'd26 :
											      (sfdBC__h115662[78] ?
												 7'd27 :
												 (sfdBC__h115662[77] ?
												    7'd28 :
												    (sfdBC__h115662[76] ?
												       7'd29 :
												       (sfdBC__h115662[75] ?
													  7'd30 :
													  (sfdBC__h115662[74] ?
													     7'd31 :
													     (sfdBC__h115662[73] ?
														7'd32 :
														(sfdBC__h115662[72] ?
														   7'd33 :
														   (sfdBC__h115662[71] ?
														      7'd34 :
														      (sfdBC__h115662[70] ?
															 7'd35 :
															 (sfdBC__h115662[69] ?
															    7'd36 :
															    (sfdBC__h115662[68] ?
															       7'd37 :
															       (sfdBC__h115662[67] ?
																  7'd38 :
																  (sfdBC__h115662[66] ?
																     7'd39 :
																     (sfdBC__h115662[65] ?
																	7'd40 :
																	(sfdBC__h115662[64] ?
																	   7'd41 :
																	   (sfdBC__h115662[63] ?
																	      7'd42 :
																	      (sfdBC__h115662[62] ?
																		 7'd43 :
																		 (sfdBC__h115662[61] ?
																		    7'd44 :
																		    (sfdBC__h115662[60] ?
																		       7'd45 :
																		       (sfdBC__h115662[59] ?
																			  7'd46 :
																			  (sfdBC__h115662[58] ?
																			     7'd47 :
																			     (sfdBC__h115662[57] ?
																				7'd48 :
																				(sfdBC__h115662[56] ?
																				   7'd49 :
																				   (sfdBC__h115662[55] ?
																				      7'd50 :
																				      (sfdBC__h115662[54] ?
																					 7'd51 :
																					 (sfdBC__h115662[53] ?
																					    7'd52 :
																					    (sfdBC__h115662[52] ?
																					       7'd53 :
																					       (sfdBC__h115662[51] ?
																						  7'd54 :
																						  (sfdBC__h115662[50] ?
																						     7'd55 :
																						     (sfdBC__h115662[49] ?
																							7'd56 :
																							(sfdBC__h115662[48] ?
																							   7'd57 :
																							   (sfdBC__h115662[47] ?
																							      7'd58 :
																							      (sfdBC__h115662[46] ?
																								 7'd59 :
																								 (sfdBC__h115662[45] ?
																								    7'd60 :
																								    (sfdBC__h115662[44] ?
																								       7'd61 :
																								       (sfdBC__h115662[43] ?
																									  7'd62 :
																									  (sfdBC__h115662[42] ?
																									     7'd63 :
																									     (sfdBC__h115662[41] ?
																										7'd64 :
																										(sfdBC__h115662[40] ?
																										   7'd65 :
																										   (sfdBC__h115662[39] ?
																										      7'd66 :
																										      (sfdBC__h115662[38] ?
																											 7'd67 :
																											 (sfdBC__h115662[37] ?
																											    7'd68 :
																											    (sfdBC__h115662[36] ?
																											       7'd69 :
																											       (sfdBC__h115662[35] ?
																												  7'd70 :
																												  (sfdBC__h115662[34] ?
																												     7'd71 :
																												     (sfdBC__h115662[33] ?
																													7'd72 :
																													(sfdBC__h115662[32] ?
																													   7'd73 :
																													   (sfdBC__h115662[31] ?
																													      7'd74 :
																													      (sfdBC__h115662[30] ?
																														 7'd75 :
																														 (sfdBC__h115662[29] ?
																														    7'd76 :
																														    (sfdBC__h115662[28] ?
																														       7'd77 :
																														       (sfdBC__h115662[27] ?
																															  7'd78 :
																															  (sfdBC__h115662[26] ?
																															     7'd79 :
																															     (sfdBC__h115662[25] ?
																																7'd80 :
																																(sfdBC__h115662[24] ?
																																   7'd81 :
																																   (sfdBC__h115662[23] ?
																																      7'd82 :
																																      (sfdBC__h115662[22] ?
																																	 7'd83 :
																																	 (sfdBC__h115662[21] ?
																																	    7'd84 :
																																	    (sfdBC__h115662[20] ?
																																	       7'd85 :
																																	       (sfdBC__h115662[19] ?
																																		  7'd86 :
																																		  (sfdBC__h115662[18] ?
																																		     7'd87 :
																																		     (sfdBC__h115662[17] ?
																																			7'd88 :
																																			(sfdBC__h115662[16] ?
																																			   7'd89 :
																																			   (sfdBC__h115662[15] ?
																																			      7'd90 :
																																			      (sfdBC__h115662[14] ?
																																				 7'd91 :
																																				 (sfdBC__h115662[13] ?
																																				    7'd92 :
																																				    (sfdBC__h115662[12] ?
																																				       7'd93 :
																																				       (sfdBC__h115662[11] ?
																																					  7'd94 :
																																					  (sfdBC__h115662[10] ?
																																					     7'd95 :
																																					     (sfdBC__h115662[9] ?
																																						7'd96 :
																																						(sfdBC__h115662[8] ?
																																						   7'd97 :
																																						   (sfdBC__h115662[7] ?
																																						      7'd98 :
																																						      (sfdBC__h115662[6] ?
																																							 7'd99 :
																																							 (sfdBC__h115662[5] ?
																																							    7'd100 :
																																							    (sfdBC__h115662[4] ?
																																							       7'd101 :
																																							       (sfdBC__h115662[3] ?
																																								  7'd102 :
																																								  (sfdBC__h115662[2] ?
																																								     7'd103 :
																																								     (sfdBC__h115662[1] ?
																																									7'd104 :
																																									(sfdBC__h115662[0] ?
																																									   7'd105 :
																																									   7'd106)))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))) -
	     7'd1 ;
  assign IF_IF_7170_MINUS_fpu_madd_fState_S3_first__995_ETC___d2462 =
	     IF_IF_7170_MINUS_fpu_madd_fState_S3_first__995_ETC___d2031 -
	     12'd3074 ;
  assign IF_IF_7170_MINUS_fpu_madd_fState_S3_first__995_ETC___d2534 =
	     (sfdBC__h115662[105] &&
	      IF_IF_7170_MINUS_fpu_madd_fState_S3_first__995_ETC___d2031 ==
	      12'd1023) ?
	       63'h7FEFFFFFFFFFFFFF :
	       { _theResult___fst_exp__h130949, sfdin__h130943[105:54] } ;
  assign IF_IF_IF_IF_0b0_CONCAT_NOT_resWire_wget__410_B_ETC___d6448 =
	     (guard__h269587 == 2'b0 || resWire$wget[68]) ?
	       _theResult___fst_exp__h277686 :
	       _theResult___exp__h278202 ;
  assign IF_IF_IF_IF_0b0_CONCAT_NOT_resWire_wget__410_B_ETC___d6450 =
	     (guard__h269587 == 2'b0) ?
	       _theResult___fst_exp__h277686 :
	       (resWire$wget[68] ?
		  _theResult___exp__h278202 :
		  _theResult___fst_exp__h277686) ;
  assign IF_IF_IF_IF_0b0_CONCAT_NOT_resWire_wget__410_B_ETC___d6576 =
	     (guard__h269587 == 2'b0 || resWire$wget[68]) ?
	       sfdin__h277680[56:34] :
	       _theResult___sfd__h278203 ;
  assign IF_IF_IF_IF_0b0_CONCAT_NOT_resWire_wget__410_B_ETC___d6578 =
	     (guard__h269587 == 2'b0) ?
	       sfdin__h277680[56:34] :
	       (resWire$wget[68] ?
		  _theResult___sfd__h278203 :
		  sfdin__h277680[56:34]) ;
  assign IF_IF_IF_IF_3074_MINUS_SEXT_iFifo_first__087_B_ETC___d3729 =
	     (guard__h164624 == 2'b0 || iFifo$D_OUT[168]) ?
	       _theResult___fst_exp__h172852 :
	       _theResult___exp__h173571 ;
  assign IF_IF_IF_IF_3074_MINUS_SEXT_iFifo_first__087_B_ETC___d3731 =
	     (guard__h164624 == 2'b0) ?
	       _theResult___fst_exp__h172852 :
	       (iFifo$D_OUT[168] ?
		  _theResult___exp__h173571 :
		  _theResult___fst_exp__h172852) ;
  assign IF_IF_IF_IF_3074_MINUS_SEXT_iFifo_first__087_B_ETC___d3813 =
	     (guard__h164624 == 2'b0 || iFifo$D_OUT[168]) ?
	       sfdin__h172846[56:5] :
	       _theResult___sfd__h173572 ;
  assign IF_IF_IF_IF_3074_MINUS_SEXT_iFifo_first__087_B_ETC___d3815 =
	     (guard__h164624 == 2'b0) ?
	       sfdin__h172846[56:5] :
	       (iFifo$D_OUT[168] ?
		  _theResult___sfd__h173572 :
		  sfdin__h172846[56:5]) ;
  assign IF_IF_IF_IF_3074_MINUS_SEXT_iFifo_first__087_B_ETC___d4436 =
	     (guard__h242201 == 2'b0 || iFifo$D_OUT[38]) ?
	       _theResult___fst_exp__h250429 :
	       _theResult___exp__h251148 ;
  assign IF_IF_IF_IF_3074_MINUS_SEXT_iFifo_first__087_B_ETC___d4438 =
	     (guard__h242201 == 2'b0) ?
	       _theResult___fst_exp__h250429 :
	       (iFifo$D_OUT[38] ?
		  _theResult___exp__h251148 :
		  _theResult___fst_exp__h250429) ;
  assign IF_IF_IF_IF_3074_MINUS_SEXT_iFifo_first__087_B_ETC___d4519 =
	     (guard__h242201 == 2'b0 || iFifo$D_OUT[38]) ?
	       sfdin__h250423[56:5] :
	       _theResult___sfd__h251149 ;
  assign IF_IF_IF_IF_3074_MINUS_SEXT_iFifo_first__087_B_ETC___d4521 =
	     (guard__h242201 == 2'b0) ?
	       sfdin__h250423[56:5] :
	       (iFifo$D_OUT[38] ?
		  _theResult___sfd__h251149 :
		  sfdin__h250423[56:5]) ;
  assign IF_IF_IF_IF_3074_MINUS_SEXT_iFifo_first__087_B_ETC___d5211 =
	     (guard__h203262 == 2'b0 || iFifo$D_OUT[103]) ?
	       _theResult___fst_exp__h211490 :
	       _theResult___exp__h212209 ;
  assign IF_IF_IF_IF_3074_MINUS_SEXT_iFifo_first__087_B_ETC___d5213 =
	     (guard__h203262 == 2'b0) ?
	       _theResult___fst_exp__h211490 :
	       (iFifo$D_OUT[103] ?
		  _theResult___exp__h212209 :
		  _theResult___fst_exp__h211490) ;
  assign IF_IF_IF_IF_3074_MINUS_SEXT_iFifo_first__087_B_ETC___d5294 =
	     (guard__h203262 == 2'b0 || iFifo$D_OUT[103]) ?
	       sfdin__h211484[56:5] :
	       _theResult___sfd__h212210 ;
  assign IF_IF_IF_IF_3074_MINUS_SEXT_iFifo_first__087_B_ETC___d5296 =
	     (guard__h203262 == 2'b0) ?
	       sfdin__h211484[56:5] :
	       (iFifo$D_OUT[103] ?
		  _theResult___sfd__h212210 :
		  sfdin__h211484[56:5]) ;
  assign IF_IF_IF_IF_3970_MINUS_SEXT_resWire_wget__410__ETC___d6518 =
	     (guard__h287224 == 2'b0 || resWire$wget[68]) ?
	       _theResult___fst_exp__h295452 :
	       _theResult___exp__h295968 ;
  assign IF_IF_IF_IF_3970_MINUS_SEXT_resWire_wget__410__ETC___d6520 =
	     (guard__h287224 == 2'b0) ?
	       _theResult___fst_exp__h295452 :
	       (resWire$wget[68] ?
		  _theResult___exp__h295968 :
		  _theResult___fst_exp__h295452) ;
  assign IF_IF_IF_IF_3970_MINUS_SEXT_resWire_wget__410__ETC___d6622 =
	     (guard__h287224 == 2'b0 || resWire$wget[68]) ?
	       sfdin__h295446[56:34] :
	       _theResult___sfd__h295969 ;
  assign IF_IF_IF_IF_3970_MINUS_SEXT_resWire_wget__410__ETC___d6624 =
	     (guard__h287224 == 2'b0) ?
	       sfdin__h295446[56:34] :
	       (resWire$wget[68] ?
		  _theResult___sfd__h295969 :
		  sfdin__h295446[56:34]) ;
  assign IF_IF_IF_iFifo_first__087_BITS_102_TO_95_625_E_ETC___d5173 =
	     (guard__h194013 == 2'b0 || iFifo$D_OUT[103]) ?
	       _theResult___fst_exp__h201974 :
	       _theResult___exp__h202619 ;
  assign IF_IF_IF_iFifo_first__087_BITS_102_TO_95_625_E_ETC___d5175 =
	     (guard__h194013 == 2'b0) ?
	       _theResult___fst_exp__h201974 :
	       (iFifo$D_OUT[103] ?
		  _theResult___exp__h202619 :
		  _theResult___fst_exp__h201974) ;
  assign IF_IF_IF_iFifo_first__087_BITS_102_TO_95_625_E_ETC___d5242 =
	     (guard__h212301 == 2'b0 || iFifo$D_OUT[103]) ?
	       _theResult___fst_exp__h220291 :
	       _theResult___exp__h220961 ;
  assign IF_IF_IF_iFifo_first__087_BITS_102_TO_95_625_E_ETC___d5244 =
	     (guard__h212301 == 2'b0) ?
	       _theResult___fst_exp__h220291 :
	       (iFifo$D_OUT[103] ?
		  _theResult___exp__h220961 :
		  _theResult___fst_exp__h220291) ;
  assign IF_IF_IF_iFifo_first__087_BITS_102_TO_95_625_E_ETC___d5268 =
	     (guard__h194013 == 2'b0 || iFifo$D_OUT[103]) ?
	       _theResult___snd__h201925[56:5] :
	       _theResult___sfd__h202620 ;
  assign IF_IF_IF_iFifo_first__087_BITS_102_TO_95_625_E_ETC___d5270 =
	     (guard__h194013 == 2'b0) ?
	       _theResult___snd__h201925[56:5] :
	       (iFifo$D_OUT[103] ?
		  _theResult___sfd__h202620 :
		  _theResult___snd__h201925[56:5]) ;
  assign IF_IF_IF_iFifo_first__087_BITS_102_TO_95_625_E_ETC___d5313 =
	     (guard__h212301 == 2'b0 || iFifo$D_OUT[103]) ?
	       _theResult___snd__h220237[56:5] :
	       _theResult___sfd__h220962 ;
  assign IF_IF_IF_iFifo_first__087_BITS_102_TO_95_625_E_ETC___d5315 =
	     (guard__h212301 == 2'b0) ?
	       _theResult___snd__h220237[56:5] :
	       (iFifo$D_OUT[103] ?
		  _theResult___sfd__h220962 :
		  _theResult___snd__h220237[56:5]) ;
  assign IF_IF_IF_iFifo_first__087_BITS_167_TO_160_130__ETC___d3690 =
	     (guard__h155375 == 2'b0 || iFifo$D_OUT[168]) ?
	       _theResult___fst_exp__h163336 :
	       _theResult___exp__h163981 ;
  assign IF_IF_IF_iFifo_first__087_BITS_167_TO_160_130__ETC___d3692 =
	     (guard__h155375 == 2'b0) ?
	       _theResult___fst_exp__h163336 :
	       (iFifo$D_OUT[168] ?
		  _theResult___exp__h163981 :
		  _theResult___fst_exp__h163336) ;
  assign IF_IF_IF_iFifo_first__087_BITS_167_TO_160_130__ETC___d3760 =
	     (guard__h173663 == 2'b0 || iFifo$D_OUT[168]) ?
	       _theResult___fst_exp__h181653 :
	       _theResult___exp__h182323 ;
  assign IF_IF_IF_iFifo_first__087_BITS_167_TO_160_130__ETC___d3762 =
	     (guard__h173663 == 2'b0) ?
	       _theResult___fst_exp__h181653 :
	       (iFifo$D_OUT[168] ?
		  _theResult___exp__h182323 :
		  _theResult___fst_exp__h181653) ;
  assign IF_IF_IF_iFifo_first__087_BITS_167_TO_160_130__ETC___d3786 =
	     (guard__h155375 == 2'b0 || iFifo$D_OUT[168]) ?
	       _theResult___snd__h163287[56:5] :
	       _theResult___sfd__h163982 ;
  assign IF_IF_IF_iFifo_first__087_BITS_167_TO_160_130__ETC___d3788 =
	     (guard__h155375 == 2'b0) ?
	       _theResult___snd__h163287[56:5] :
	       (iFifo$D_OUT[168] ?
		  _theResult___sfd__h163982 :
		  _theResult___snd__h163287[56:5]) ;
  assign IF_IF_IF_iFifo_first__087_BITS_167_TO_160_130__ETC___d3832 =
	     (guard__h173663 == 2'b0 || iFifo$D_OUT[168]) ?
	       _theResult___snd__h181599[56:5] :
	       _theResult___sfd__h182324 ;
  assign IF_IF_IF_iFifo_first__087_BITS_167_TO_160_130__ETC___d3834 =
	     (guard__h173663 == 2'b0) ?
	       _theResult___snd__h181599[56:5] :
	       (iFifo$D_OUT[168] ?
		  _theResult___sfd__h182324 :
		  _theResult___snd__h181599[56:5]) ;
  assign IF_IF_IF_iFifo_first__087_BITS_37_TO_30_850_EQ_ETC___d4398 =
	     (guard__h232952 == 2'b0 || iFifo$D_OUT[38]) ?
	       _theResult___fst_exp__h240913 :
	       _theResult___exp__h241558 ;
  assign IF_IF_IF_iFifo_first__087_BITS_37_TO_30_850_EQ_ETC___d4400 =
	     (guard__h232952 == 2'b0) ?
	       _theResult___fst_exp__h240913 :
	       (iFifo$D_OUT[38] ?
		  _theResult___exp__h241558 :
		  _theResult___fst_exp__h240913) ;
  assign IF_IF_IF_iFifo_first__087_BITS_37_TO_30_850_EQ_ETC___d4467 =
	     (guard__h251240 == 2'b0 || iFifo$D_OUT[38]) ?
	       _theResult___fst_exp__h259230 :
	       _theResult___exp__h259900 ;
  assign IF_IF_IF_iFifo_first__087_BITS_37_TO_30_850_EQ_ETC___d4469 =
	     (guard__h251240 == 2'b0) ?
	       _theResult___fst_exp__h259230 :
	       (iFifo$D_OUT[38] ?
		  _theResult___exp__h259900 :
		  _theResult___fst_exp__h259230) ;
  assign IF_IF_IF_iFifo_first__087_BITS_37_TO_30_850_EQ_ETC___d4493 =
	     (guard__h232952 == 2'b0 || iFifo$D_OUT[38]) ?
	       _theResult___snd__h240864[56:5] :
	       _theResult___sfd__h241559 ;
  assign IF_IF_IF_iFifo_first__087_BITS_37_TO_30_850_EQ_ETC___d4495 =
	     (guard__h232952 == 2'b0) ?
	       _theResult___snd__h240864[56:5] :
	       (iFifo$D_OUT[38] ?
		  _theResult___sfd__h241559 :
		  _theResult___snd__h240864[56:5]) ;
  assign IF_IF_IF_iFifo_first__087_BITS_37_TO_30_850_EQ_ETC___d4538 =
	     (guard__h251240 == 2'b0 || iFifo$D_OUT[38]) ?
	       _theResult___snd__h259176[56:5] :
	       _theResult___sfd__h259901 ;
  assign IF_IF_IF_iFifo_first__087_BITS_37_TO_30_850_EQ_ETC___d4540 =
	     (guard__h251240 == 2'b0) ?
	       _theResult___snd__h259176[56:5] :
	       (iFifo$D_OUT[38] ?
		  _theResult___sfd__h259901 :
		  _theResult___snd__h259176[56:5]) ;
  assign IF_IF_IF_resWire_wget__410_BITS_67_TO_57_416_E_ETC___d6479 =
	     (guard__h278294 == 2'b0 || resWire$wget[68]) ?
	       _theResult___fst_exp__h286342 :
	       _theResult___exp__h286784 ;
  assign IF_IF_IF_resWire_wget__410_BITS_67_TO_57_416_E_ETC___d6481 =
	     (guard__h278294 == 2'b0) ?
	       _theResult___fst_exp__h286342 :
	       (resWire$wget[68] ?
		  _theResult___exp__h286784 :
		  _theResult___fst_exp__h286342) ;
  assign IF_IF_IF_resWire_wget__410_BITS_67_TO_57_416_E_ETC___d6549 =
	     (guard__h296060 == 2'b0 || resWire$wget[68]) ?
	       _theResult___fst_exp__h304137 :
	       _theResult___exp__h304604 ;
  assign IF_IF_IF_resWire_wget__410_BITS_67_TO_57_416_E_ETC___d6551 =
	     (guard__h296060 == 2'b0) ?
	       _theResult___fst_exp__h304137 :
	       (resWire$wget[68] ?
		  _theResult___exp__h304604 :
		  _theResult___fst_exp__h304137) ;
  assign IF_IF_IF_resWire_wget__410_BITS_67_TO_57_416_E_ETC___d6595 =
	     (guard__h278294 == 2'b0 || resWire$wget[68]) ?
	       _theResult___snd__h286293[56:34] :
	       _theResult___sfd__h286785 ;
  assign IF_IF_IF_resWire_wget__410_BITS_67_TO_57_416_E_ETC___d6597 =
	     (guard__h278294 == 2'b0) ?
	       _theResult___snd__h286293[56:34] :
	       (resWire$wget[68] ?
		  _theResult___sfd__h286785 :
		  _theResult___snd__h286293[56:34]) ;
  assign IF_IF_IF_resWire_wget__410_BITS_67_TO_57_416_E_ETC___d6641 =
	     (guard__h296060 == 2'b0 || resWire$wget[68]) ?
	       _theResult___snd__h304083[56:34] :
	       _theResult___sfd__h304605 ;
  assign IF_IF_IF_resWire_wget__410_BITS_67_TO_57_416_E_ETC___d6643 =
	     (guard__h296060 == 2'b0) ?
	       _theResult___snd__h304083[56:34] :
	       (resWire$wget[68] ?
		  _theResult___sfd__h304605 :
		  _theResult___snd__h304083[56:34]) ;
  assign IF_IF_fpu_div64_fState_S3_first__86_BITS_120_T_ETC___d643 =
	     (_theResult___fst_exp__h42290 == 11'd0) ?
	       12'd3074 :
	       { theResult___fst_exp2290_MINUS_1023__q11[10],
		 theResult___fst_exp2290_MINUS_1023__q11 } ;
  assign IF_IF_fpu_div64_fState_S3_first__86_BITS_120_T_ETC___d880 =
	     (sfdin__h34118[57] ?
		6'd0 :
		(sfdin__h34118[56] ?
		   6'd1 :
		   (sfdin__h34118[55] ?
		      6'd2 :
		      (sfdin__h34118[54] ?
			 6'd3 :
			 (sfdin__h34118[53] ?
			    6'd4 :
			    (sfdin__h34118[52] ?
			       6'd5 :
			       (sfdin__h34118[51] ?
				  6'd6 :
				  (sfdin__h34118[50] ?
				     6'd7 :
				     (sfdin__h34118[49] ?
					6'd8 :
					(sfdin__h34118[48] ?
					   6'd9 :
					   (sfdin__h34118[47] ?
					      6'd10 :
					      (sfdin__h34118[46] ?
						 6'd11 :
						 (sfdin__h34118[45] ?
						    6'd12 :
						    (sfdin__h34118[44] ?
						       6'd13 :
						       (sfdin__h34118[43] ?
							  6'd14 :
							  (sfdin__h34118[42] ?
							     6'd15 :
							     (sfdin__h34118[41] ?
								6'd16 :
								(sfdin__h34118[40] ?
								   6'd17 :
								   (sfdin__h34118[39] ?
								      6'd18 :
								      (sfdin__h34118[38] ?
									 6'd19 :
									 (sfdin__h34118[37] ?
									    6'd20 :
									    (sfdin__h34118[36] ?
									       6'd21 :
									       (sfdin__h34118[35] ?
										  6'd22 :
										  (sfdin__h34118[34] ?
										     6'd23 :
										     (sfdin__h34118[33] ?
											6'd24 :
											(sfdin__h34118[32] ?
											   6'd25 :
											   (sfdin__h34118[31] ?
											      6'd26 :
											      (sfdin__h34118[30] ?
												 6'd27 :
												 (sfdin__h34118[29] ?
												    6'd28 :
												    (sfdin__h34118[28] ?
												       6'd29 :
												       (sfdin__h34118[27] ?
													  6'd30 :
													  (sfdin__h34118[26] ?
													     6'd31 :
													     (sfdin__h34118[25] ?
														6'd32 :
														(sfdin__h34118[24] ?
														   6'd33 :
														   (sfdin__h34118[23] ?
														      6'd34 :
														      (sfdin__h34118[22] ?
															 6'd35 :
															 (sfdin__h34118[21] ?
															    6'd36 :
															    (sfdin__h34118[20] ?
															       6'd37 :
															       (sfdin__h34118[19] ?
																  6'd38 :
																  (sfdin__h34118[18] ?
																     6'd39 :
																     (sfdin__h34118[17] ?
																	6'd40 :
																	(sfdin__h34118[16] ?
																	   6'd41 :
																	   (sfdin__h34118[15] ?
																	      6'd42 :
																	      (sfdin__h34118[14] ?
																		 6'd43 :
																		 (sfdin__h34118[13] ?
																		    6'd44 :
																		    (sfdin__h34118[12] ?
																		       6'd45 :
																		       (sfdin__h34118[11] ?
																			  6'd46 :
																			  (sfdin__h34118[10] ?
																			     6'd47 :
																			     (sfdin__h34118[9] ?
																				6'd48 :
																				(sfdin__h34118[8] ?
																				   6'd49 :
																				   (sfdin__h34118[7] ?
																				      6'd50 :
																				      (sfdin__h34118[6] ?
																					 6'd51 :
																					 (sfdin__h34118[5] ?
																					    6'd52 :
																					    (sfdin__h34118[4] ?
																					       6'd53 :
																					       (sfdin__h34118[3] ?
																						  6'd54 :
																						  (sfdin__h34118[2] ?
																						     6'd55 :
																						     (sfdin__h34118[1] ?
																							6'd56 :
																							(sfdin__h34118[0] ?
																							   6'd57 :
																							   6'd58)))))))))))))))))))))))))))))))))))))))))))))))))))))))))) -
	     6'd1 ;
  assign IF_IF_fpu_div64_fState_S3_first__86_BITS_120_T_ETC___d882 =
	     IF_IF_fpu_div64_fState_S3_first__86_BITS_120_T_ETC___d643 -
	     12'd3074 ;
  assign IF_IF_fpu_div64_fState_S3_first__86_BITS_120_T_ETC___d926 =
	     IF_fpu_div64_fState_S3_first__86_BITS_120_TO_1_ETC___d597 ?
	       IF_fpu_div64_fState_S3_first__86_BITS_120_TO_1_ETC___d921 :
	       { fpu_div64_fState_S3$D_OUT[129:128],
		 (fpu_div64_fState_S3$D_OUT[120:110] == 11'd2047) ?
		   fpu_div64_fState_S3$D_OUT[57:56] != 2'b0 ||
		   fpu_div64_fState_S3$D_OUT[127] :
		   fpu_div64_fState_S3$D_OUT[127],
		 fpu_div64_fState_S3$D_OUT[126],
		 (fpu_div64_fState_S3$D_OUT[120:110] == 11'd2047) ?
		   fpu_div64_fState_S3$D_OUT[57:56] != 2'b0 ||
		   fpu_div64_fState_S3$D_OUT[125] :
		   fpu_div64_fState_S3$D_OUT[125] } ;
  assign IF_IF_fpu_div64_fState_S3_first__86_BITS_120_T_ETC___d929 =
	     (sfdin__h34118[57] &&
	      IF_IF_fpu_div64_fState_S3_first__86_BITS_120_T_ETC___d643 ==
	      12'd1023) ?
	       63'h7FEFFFFFFFFFFFFF :
	       { _theResult___fst_exp__h42333, sfdin__h42327[57:6] } ;
  assign IF_IF_fpu_madd_fOperand_S0_first__803_BIT_195__ETC___d1922 =
	     (x__h96539 == 11'd2047 &&
	      _theResult___fst_sfd__h96608 == 52'd0) ?
	       fpu_madd_fOperand_S0$D_OUT[195] &&
	       fpu_madd_fOperand_S0$D_OUT[194] :
	       ((fpu_madd_fOperand_S0$D_OUT[129:119] == 11'd2047 &&
		 fpu_madd_fOperand_S0$D_OUT[118:67] == 52'd0 ||
		 fpu_madd_fOperand_S0$D_OUT[65:55] == 11'd2047 &&
		 fpu_madd_fOperand_S0$D_OUT[54:3] == 52'd0) ?
		  NOT_fpu_madd_fOperand_S0_first__803_BIT_130_85_ETC___d1854 :
		  fpu_madd_fOperand_S0$D_OUT[195] &&
		  fpu_madd_fOperand_S0$D_OUT[194]) ;
  assign IF_IF_fpu_madd_fOperand_S0_first__803_BIT_195__ETC___d1931 =
	     (x__h96539 == 11'd2047 &&
	      _theResult___fst_sfd__h96608 == 52'd0) ?
	       IF_fpu_madd_fOperand_S0_first__803_BIT_195_804_ETC___d1911 :
	       ((fpu_madd_fOperand_S0$D_OUT[129:119] == 11'd2047 &&
		 fpu_madd_fOperand_S0$D_OUT[118:67] == 52'd0 ||
		 fpu_madd_fOperand_S0$D_OUT[65:55] == 11'd2047 &&
		 fpu_madd_fOperand_S0$D_OUT[54:3] == 52'd0) ?
		  63'h7FF0000000000000 :
		  IF_fpu_madd_fOperand_S0_first__803_BIT_195_804_ETC___d1911) ;
  assign IF_IF_fpu_madd_fOperand_S0_first__803_BIT_195__ETC___d1936 =
	     (x__h96539 == 11'd2047 && _theResult___fst_sfd__h96608[51]) ?
	       { fpu_madd_fOperand_S0$D_OUT[195] &&
		 fpu_madd_fOperand_S0$D_OUT[194],
		 IF_fpu_madd_fOperand_S0_first__803_BIT_195_804_ETC___d1911 } :
	       ((fpu_madd_fOperand_S0$D_OUT[129:119] == 11'd2047 &&
		 fpu_madd_fOperand_S0$D_OUT[118]) ?
		  fpu_madd_fOperand_S0$D_OUT[130:67] :
		  ((fpu_madd_fOperand_S0$D_OUT[65:55] == 11'd2047 &&
		    fpu_madd_fOperand_S0$D_OUT[54]) ?
		     fpu_madd_fOperand_S0$D_OUT[66:3] :
		     { NOT_fpu_madd_fOperand_S0_first__803_BITS_129_T_ETC___d1923,
		       IF_fpu_madd_fOperand_S0_first__803_BITS_129_TO_ETC___d1932 })) ;
  assign IF_IF_fpu_madd_fOperand_S0_first__803_BIT_195__ETC___d1939 =
	     (x__h96539 == 11'd2047 &&
	      _theResult___fst_sfd__h96608 != 52'd0 &&
	      !_theResult___fst_sfd__h96608[51]) ?
	       { fpu_madd_fOperand_S0$D_OUT[195] &&
		 fpu_madd_fOperand_S0$D_OUT[194],
		 x__h96539,
		 sfd__h99402 } :
	       IF_fpu_madd_fOperand_S0_first__803_BITS_129_TO_ETC___d1938 ;
  assign IF_IF_fpu_madd_fState_S7_first__651_BIT_128_65_ETC___d2901 =
	     (sfd__h133119[56] ?
		6'd0 :
		(sfd__h133119[55] ?
		   6'd1 :
		   (sfd__h133119[54] ?
		      6'd2 :
		      (sfd__h133119[53] ?
			 6'd3 :
			 (sfd__h133119[52] ?
			    6'd4 :
			    (sfd__h133119[51] ?
			       6'd5 :
			       (sfd__h133119[50] ?
				  6'd6 :
				  (sfd__h133119[49] ?
				     6'd7 :
				     (sfd__h133119[48] ?
					6'd8 :
					(sfd__h133119[47] ?
					   6'd9 :
					   (sfd__h133119[46] ?
					      6'd10 :
					      (sfd__h133119[45] ?
						 6'd11 :
						 (sfd__h133119[44] ?
						    6'd12 :
						    (sfd__h133119[43] ?
						       6'd13 :
						       (sfd__h133119[42] ?
							  6'd14 :
							  (sfd__h133119[41] ?
							     6'd15 :
							     (sfd__h133119[40] ?
								6'd16 :
								(sfd__h133119[39] ?
								   6'd17 :
								   (sfd__h133119[38] ?
								      6'd18 :
								      (sfd__h133119[37] ?
									 6'd19 :
									 (sfd__h133119[36] ?
									    6'd20 :
									    (sfd__h133119[35] ?
									       6'd21 :
									       (sfd__h133119[34] ?
										  6'd22 :
										  (sfd__h133119[33] ?
										     6'd23 :
										     (sfd__h133119[32] ?
											6'd24 :
											(sfd__h133119[31] ?
											   6'd25 :
											   (sfd__h133119[30] ?
											      6'd26 :
											      (sfd__h133119[29] ?
												 6'd27 :
												 (sfd__h133119[28] ?
												    6'd28 :
												    (sfd__h133119[27] ?
												       6'd29 :
												       (sfd__h133119[26] ?
													  6'd30 :
													  (sfd__h133119[25] ?
													     6'd31 :
													     (sfd__h133119[24] ?
														6'd32 :
														(sfd__h133119[23] ?
														   6'd33 :
														   (sfd__h133119[22] ?
														      6'd34 :
														      (sfd__h133119[21] ?
															 6'd35 :
															 (sfd__h133119[20] ?
															    6'd36 :
															    (sfd__h133119[19] ?
															       6'd37 :
															       (sfd__h133119[18] ?
																  6'd38 :
																  (sfd__h133119[17] ?
																     6'd39 :
																     (sfd__h133119[16] ?
																	6'd40 :
																	(sfd__h133119[15] ?
																	   6'd41 :
																	   (sfd__h133119[14] ?
																	      6'd42 :
																	      (sfd__h133119[13] ?
																		 6'd43 :
																		 (sfd__h133119[12] ?
																		    6'd44 :
																		    (sfd__h133119[11] ?
																		       6'd45 :
																		       (sfd__h133119[10] ?
																			  6'd46 :
																			  (sfd__h133119[9] ?
																			     6'd47 :
																			     (sfd__h133119[8] ?
																				6'd48 :
																				(sfd__h133119[7] ?
																				   6'd49 :
																				   (sfd__h133119[6] ?
																				      6'd50 :
																				      (sfd__h133119[5] ?
																					 6'd51 :
																					 (sfd__h133119[4] ?
																					    6'd52 :
																					    (sfd__h133119[3] ?
																					       6'd53 :
																					       (sfd__h133119[2] ?
																						  6'd54 :
																						  (sfd__h133119[1] ?
																						     6'd55 :
																						     (sfd__h133119[0] ?
																							6'd56 :
																							6'd57))))))))))))))))))))))))))))))))))))))))))))))))))))))))) -
	     6'd1 ;
  assign IF_IF_fpu_madd_fState_S7_first__651_BIT_128_65_ETC___d2952 =
	     (sfd__h133119[56] &&
	      IF_fpu_madd_fState_S7_first__651_BITS_126_TO_1_ETC___d2668 ==
	      12'd1023) ?
	       63'h7FEFFFFFFFFFFFFF :
	       { _theResult___fst_exp__h141375, sfdin__h141369[56:5] } ;
  assign IF_IF_rg_index_1_4_ULE_58_8_THEN_NOT_rg_b_9_EQ_ETC___d75 =
	     IF_rg_index_1_4_ULE_58_8_THEN_NOT_rg_b_9_EQ_0__ETC___d56 ?
	       ((IF_rg_index_1_4_ULE_58_8_THEN_IF_rg_res_1_BIT__ETC___d49 ==
		 116'd0) ?
		  IF_rg_index_1_4_ULE_58_8_THEN_IF_rg_res_1_BIT__ETC___d69 :
		  IF_rg_index_1_4_ULE_58_8_THEN_IF_rg_res_1_BIT__ETC___d73) :
	       IF_rg_index_1_4_ULE_58_8_THEN_IF_rg_res_1_BIT__ETC___d73 ;
  assign IF_NOT_fpu_madd_fState_S3_first__995_BITS_12_T_ETC___d2503 =
	     (!fpu_madd_fState_S3_first__995_BITS_12_TO_0_001_ETC___d2002 ||
	      fpu_madd_fState_S3_first__995_BITS_12_TO_0_001_ETC___d2004) ?
	       fpu_madd_fState_S3$D_OUT[86] :
	       fpu_madd_fState_S3_first__995_BITS_86_TO_82_00_ETC___d2501[4] ;
  assign IF_NOT_fpu_madd_fState_S3_first__995_BITS_12_T_ETC___d2506 =
	     (!fpu_madd_fState_S3_first__995_BITS_12_TO_0_001_ETC___d2002 ||
	      fpu_madd_fState_S3_first__995_BITS_12_TO_0_001_ETC___d2004) ?
	       fpu_madd_fState_S3$D_OUT[85] :
	       fpu_madd_fState_S3_first__995_BITS_86_TO_82_00_ETC___d2501[3] ;
  assign IF_NOT_fpu_madd_fState_S4_first__547_BIT_130_5_ETC___d2595 =
	     { NOT_fpu_madd_fState_S4_first__547_BIT_130_553__ETC___d2584 ?
		 IF_fpu_madd_fState_S4_first__547_BITS_64_TO_54_ETC___d2563 :
		 IF_fpu_madd_fState_S4_first__547_BITS_128_TO_1_ETC___d2568,
	       NOT_fpu_madd_fState_S4_first__547_BIT_130_553__ETC___d2584 ?
		 IF_fpu_madd_fState_S4_first__547_BITS_64_TO_54_ETC___d2563 -
		 IF_fpu_madd_fState_S4_first__547_BITS_128_TO_1_ETC___d2568 :
		 IF_fpu_madd_fState_S4_first__547_BITS_128_TO_1_ETC___d2568 -
		 IF_fpu_madd_fState_S4_first__547_BITS_64_TO_54_ETC___d2563,
	       x__h131940,
	       x__h131944 } ;
  assign IF_SEXT_iFifo_first__087_BITS_102_TO_95_625_MI_ETC___d5106 =
	     ((SEXT_iFifo_first__087_BITS_102_TO_95_625_MINUS_ETC__q96[10:0] ==
	       11'd0) ?
		12'd3074 :
		{ SEXT_iFifo_first__087_BITS_102_TO_95_625_MINUS_ETC__q99[10],
		  SEXT_iFifo_first__087_BITS_102_TO_95_625_MINUS_ETC__q99 }) -
	     12'd3074 ;
  assign IF_SEXT_iFifo_first__087_BITS_102_TO_95_625_MI_ETC___d5146 =
	     SEXT_iFifo_first__087_BITS_102_TO_95_625_MINUS_ETC___d4808 ?
	       ((_theResult___fst_exp__h211490 == 11'd2047) ?
		  iFifo$D_OUT[103] :
		  CASE_iFifoD_OUT_BITS_6_TO_4_0_CASE_guard03262_ETC__q117) :
	       ((_theResult___fst_exp__h220291 == 11'd2047) ?
		  iFifo$D_OUT[103] :
		  CASE_iFifoD_OUT_BITS_6_TO_4_0_CASE_guard12301_ETC__q119) ;
  assign IF_SEXT_iFifo_first__087_BITS_102_TO_95_625_MI_ETC___d5374 =
	     SEXT_iFifo_first__087_BITS_102_TO_95_625_MINUS_ETC___d4808 ?
	       ((_theResult___fst_exp__h211490 == 11'd2047) ?
		  !iFifo$D_OUT[103] :
		  CASE_iFifoD_OUT_BITS_6_TO_4_0_CASE_guard03262_ETC__q123) :
	       ((_theResult___fst_exp__h220291 == 11'd2047) ?
		  !iFifo$D_OUT[103] :
		  CASE_iFifoD_OUT_BITS_6_TO_4_0_CASE_guard12301_ETC__q125) ;
  assign IF_SEXT_iFifo_first__087_BITS_167_TO_160_130_M_ETC___d3623 =
	     ((SEXT_iFifo_first__087_BITS_167_TO_160_130_MINU_ETC__q36[10:0] ==
	       11'd0) ?
		12'd3074 :
		{ SEXT_iFifo_first__087_BITS_167_TO_160_130_MINU_ETC__q39[10],
		  SEXT_iFifo_first__087_BITS_167_TO_160_130_MINU_ETC__q39 }) -
	     12'd3074 ;
  assign IF_SEXT_iFifo_first__087_BITS_167_TO_160_130_M_ETC___d3663 =
	     SEXT_iFifo_first__087_BITS_167_TO_160_130_MINU_ETC___d3325 ?
	       ((_theResult___fst_exp__h172852 == 11'd2047) ?
		  iFifo$D_OUT[168] :
		  CASE_iFifoD_OUT_BITS_6_TO_4_0_CASE_guard64624_ETC__q57) :
	       ((_theResult___fst_exp__h181653 == 11'd2047) ?
		  iFifo$D_OUT[168] :
		  CASE_iFifoD_OUT_BITS_6_TO_4_0_CASE_guard73663_ETC__q59) ;
  assign IF_SEXT_iFifo_first__087_BITS_37_TO_30_850_MIN_ETC___d4331 =
	     ((SEXT_iFifo_first__087_BITS_37_TO_30_850_MINUS__ETC__q63[10:0] ==
	       11'd0) ?
		12'd3074 :
		{ SEXT_iFifo_first__087_BITS_37_TO_30_850_MINUS__ETC__q66[10],
		  SEXT_iFifo_first__087_BITS_37_TO_30_850_MINUS__ETC__q66 }) -
	     12'd3074 ;
  assign IF_SEXT_iFifo_first__087_BITS_37_TO_30_850_MIN_ETC___d4371 =
	     SEXT_iFifo_first__087_BITS_37_TO_30_850_MINUS__ETC___d4033 ?
	       ((_theResult___fst_exp__h250429 == 11'd2047) ?
		  iFifo$D_OUT[38] :
		  CASE_iFifoD_OUT_BITS_6_TO_4_0_CASE_guard42201_ETC__q84) :
	       ((_theResult___fst_exp__h259230 == 11'd2047) ?
		  iFifo$D_OUT[38] :
		  CASE_iFifoD_OUT_BITS_6_TO_4_0_CASE_guard51240_ETC__q86) ;
  assign IF_SEXT_iFifo_first__087_BITS_37_TO_30_850_MIN_ETC___d4608 =
	     SEXT_iFifo_first__087_BITS_37_TO_30_850_MINUS__ETC___d4033 ?
	       ((_theResult___fst_exp__h250429 == 11'd2047) ?
		  !iFifo$D_OUT[38] :
		  CASE_iFifoD_OUT_BITS_6_TO_4_0_CASE_guard42201_ETC__q90) :
	       ((_theResult___fst_exp__h259230 == 11'd2047) ?
		  !iFifo$D_OUT[38] :
		  CASE_iFifoD_OUT_BITS_6_TO_4_0_CASE_guard51240_ETC__q92) ;
  assign IF_SEXT_resWire_wget__410_BITS_67_TO_57_416_MI_ETC___d6332 =
	     ((SEXT_resWire_wget__410_BITS_67_TO_57_416_MINUS_ETC__q138[7:0] ==
	       8'd0) ?
		9'd386 :
		{ SEXT_resWire_wget__410_BITS_67_TO_57_416_MINUS_ETC__q141[7],
		  SEXT_resWire_wget__410_BITS_67_TO_57_416_MINUS_ETC__q141 }) -
	     9'd386 ;
  assign IF_SEXT_resWire_wget__410_BITS_67_TO_57_416_MI_ETC___d6375 =
	     SEXT_resWire_wget__410_BITS_67_TO_57_416_MINUS_ETC___d6033 ?
	       ((_theResult___fst_exp__h295452 == 8'd255) ?
		  !resWire$wget[68] :
		  IF_rmdFifo_first__778_EQ_0_779_THEN_IF_IF_IF_I_ETC___d6324) :
	       ((_theResult___fst_exp__h304137 == 8'd255) ?
		  !resWire$wget[68] :
		  IF_rmdFifo_first__778_EQ_0_779_THEN_IF_IF_IF_r_ETC___d6373) ;
  assign IF_SEXT_resWire_wget__410_BITS_67_TO_57_416_MI_ETC___d6420 =
	     SEXT_resWire_wget__410_BITS_67_TO_57_416_MINUS_ETC___d6033 ?
	       ((_theResult___fst_exp__h295452 == 8'd255) ?
		  resWire$wget[68] :
		  IF_rmdFifo_first__778_EQ_0_779_THEN_IF_IF_IF_I_ETC___d6409) :
	       ((_theResult___fst_exp__h304137 == 8'd255) ?
		  resWire$wget[68] :
		  IF_rmdFifo_first__778_EQ_0_779_THEN_IF_IF_IF_r_ETC___d6418) ;
  assign IF_SEXT_resWire_wget__410_BITS_67_TO_57_416_MI_ETC___d6734 =
	     SEXT_resWire_wget__410_BITS_67_TO_57_416_MINUS_ETC___d6033 ?
	       _0_CONCAT_IF_IF_3970_MINUS_SEXT_resWire_wget__4_ETC___d6705[2] :
	       _theResult___fst_exp__h304685 == 8'd255 &&
	       _theResult___fst_sfd__h304686 == 23'd0 ;
  assign IF_SEXT_resWire_wget__410_BITS_67_TO_57_416_MI_ETC___d6747 =
	     SEXT_resWire_wget__410_BITS_67_TO_57_416_MINUS_ETC___d6033 ?
	       _0_CONCAT_IF_IF_3970_MINUS_SEXT_resWire_wget__4_ETC___d6705[1] :
	       _theResult___fst_exp__h304137 == 8'd0 &&
	       guard__h296060 != 2'b0 ;
  assign IF_SEXT_resWire_wget__410_BITS_67_TO_57_416_MI_ETC___d6760 =
	     SEXT_resWire_wget__410_BITS_67_TO_57_416_MINUS_ETC___d6033 ?
	       _0_CONCAT_IF_IF_3970_MINUS_SEXT_resWire_wget__4_ETC___d6705[0] :
	       _theResult___fst_exp__h304137 != 8'd255 &&
	       guard__h296060 != 2'b0 ;
  assign IF_fpu_div64_fOperands_S0_first__06_BITS_129_T_ETC___d352 =
	     (((fpu_div64_fOperands_S0$D_OUT[129:119] == 11'd0) ?
		 13'd7170 :
		 { {2{fpu_div64_fOperands_S0D_OUT_BITS_129_TO_119_M_ETC__q7[10]}},
		   fpu_div64_fOperands_S0D_OUT_BITS_129_TO_119_M_ETC__q7 }) -
	      { 7'd0, b__h4039 }) -
	     (((fpu_div64_fOperands_S0$D_OUT[65:55] == 11'd0) ?
		 13'd7170 :
		 { {2{fpu_div64_fOperands_S0D_OUT_BITS_65_TO_55_MIN_ETC__q8[10]}},
		   fpu_div64_fOperands_S0D_OUT_BITS_65_TO_55_MIN_ETC__q8 }) -
	      { 7'd0, b__h11457 }) ;
  assign IF_fpu_div64_fOperands_S0_first__06_BITS_129_T_ETC___d353 =
	     (IF_fpu_div64_fOperands_S0_first__06_BITS_129_T_ETC___d352 ^
	      13'h1000) <=
	     13'd5120 ;
  assign IF_fpu_div64_fOperands_S0_first__06_BITS_129_T_ETC___d355 =
	     (IF_fpu_div64_fOperands_S0_first__06_BITS_129_T_ETC___d352 ^
	      13'h1000) <
	     13'd3020 ;
  assign IF_fpu_div64_fOperands_S0_first__06_BITS_129_T_ETC___d499 =
	     (IF_fpu_div64_fOperands_S0_first__06_BITS_129_T_ETC___d352 ^
	      13'h1000) <
	     13'd3074 ;
  assign IF_fpu_div64_fOperands_S0_first__06_BITS_65_TO_ETC___d422 =
	     (fpu_div64_fOperands_S0$D_OUT[65:55] == 11'd0 &&
	      fpu_div64_fOperands_S0$D_OUT[54:3] == 52'd0 ||
	      fpu_div64_fOperands_S0_first__06_BITS_129_TO_1_ETC___d401) ?
	       !fpu_div64_fOperands_S0_first__06_BIT_130_03_EQ_ETC___d405 :
	       CASE_fpu_div64_fOperands_S0D_OUT_BITS_2_TO_0__ETC__q9 ;
  assign IF_fpu_div64_fOperands_S0_first__06_BITS_65_TO_ETC___d433 =
	     (fpu_div64_fOperands_S0$D_OUT[65:55] == 11'd0 &&
	      fpu_div64_fOperands_S0$D_OUT[54:3] == 52'd0 ||
	      fpu_div64_fOperands_S0$D_OUT[129:119] == 11'd2047 &&
	      fpu_div64_fOperands_S0$D_OUT[118:67] == 52'd0) ?
	       11'd2047 :
	       ((fpu_div64_fOperands_S0$D_OUT[129:119] == 11'd0 &&
		 fpu_div64_fOperands_S0$D_OUT[118:67] == 52'd0 ||
		 fpu_div64_fOperands_S0$D_OUT[65:55] == 11'd2047 &&
		 fpu_div64_fOperands_S0$D_OUT[54:3] == 52'd0 ||
		 IF_fpu_div64_fOperands_S0_first__06_BITS_129_T_ETC___d353) ?
		  11'd0 :
		  _theResult___fst_exp__h19467) ;
  assign IF_fpu_div64_fOperands_S0_first__06_BITS_65_TO_ETC___d450 =
	     (fpu_div64_fOperands_S0$D_OUT[65:55] == 11'd0 &&
	      fpu_div64_fOperands_S0$D_OUT[54:3] == 52'd0 ||
	      fpu_div64_fOperands_S0_first__06_BITS_129_TO_1_ETC___d401) ?
	       52'd0 :
	       (IF_fpu_div64_fOperands_S0_first__06_BITS_129_T_ETC___d353 ?
		  _theResult___fst_sfd__h19957 :
		  _theResult___fst_sfd__h19468) ;
  assign IF_fpu_div64_fOperands_S0_first__06_BITS_65_TO_ETC___d455 =
	     (fpu_div64_fOperands_S0$D_OUT[65:55] == 11'd2047 &&
	      fpu_div64_fOperands_S0$D_OUT[54:3] != 52'd0 &&
	      !fpu_div64_fOperands_S0$D_OUT[54]) ?
	       { fpu_div64_fOperands_S0$D_OUT[66:55], sfd__h18937 } :
	       ((fpu_div64_fOperands_S0$D_OUT[129:119] == 11'd2047 &&
		 fpu_div64_fOperands_S0$D_OUT[118]) ?
		  fpu_div64_fOperands_S0$D_OUT[130:67] :
		  ((fpu_div64_fOperands_S0$D_OUT[65:55] == 11'd2047 &&
		    fpu_div64_fOperands_S0$D_OUT[54]) ?
		     fpu_div64_fOperands_S0$D_OUT[66:3] :
		     NOT_fpu_div64_fOperands_S0_first__06_BITS_129__ETC___d452)) ;
  assign IF_fpu_div64_fState_S3_first__86_BITS_120_TO_1_ETC___d597 =
	     (fpu_div64_fState_S3$D_OUT[120:110] == 11'd2047) ?
	       fpu_div64_fState_S3$D_OUT[57:56] == 2'b0 &&
	       !fpu_div64_fState_S3$D_OUT[194] :
	       !fpu_div64_fState_S3$D_OUT[194] ;
  assign IF_fpu_div64_fState_S3_first__86_BITS_120_TO_1_ETC___d921 =
	     ((fpu_div64_fState_S3$D_OUT[120:110] == 11'd2047) ?
		{ fpu_div64_fState_S3$D_OUT[129:128],
		  fpu_div64_fState_S3$D_OUT[57:56] != 2'b0 ||
		  fpu_div64_fState_S3$D_OUT[127],
		  fpu_div64_fState_S3$D_OUT[126],
		  fpu_div64_fState_S3$D_OUT[57:56] != 2'b0 ||
		  fpu_div64_fState_S3$D_OUT[125] } :
		fpu_div64_fState_S3$D_OUT[129:125]) |
	     { 2'd0,
	       sfdin__h34118[57] &&
	       IF_IF_fpu_div64_fState_S3_first__86_BITS_120_T_ETC___d643 ==
	       12'd1023,
	       _theResult___fst_exp__h42336 == 11'd0 && guard__h33946 != 2'd0,
	       sfdin__h34118[57] &&
	       IF_IF_fpu_div64_fState_S3_first__86_BITS_120_T_ETC___d643 ==
	       12'd1023 } ;
  assign IF_fpu_div64_fState_S4_first__43_BITS_64_TO_54_ETC___d977 =
	     (fpu_div64_fState_S4$D_OUT[64:54] == 11'd0 &&
	      sfd__h42982[53:52] == 2'b01) ?
	       11'd1 :
	       fpu_div64_fState_S4$D_OUT[64:54] ;
  assign IF_fpu_madd_fOperand_S0_first__803_BITS_129_TO_ETC___d1932 =
	     (fpu_madd_fOperand_S0_first__803_BITS_129_TO_11_ETC___d1926 ||
	      IF_fpu_madd_fOperand_S0_first__803_BIT_195_804_ETC___d1927 &&
	      !fpu_madd_fOperand_S0_first__803_BIT_195_804_AN_ETC___d1855) ?
	       63'h7FF8000000000000 :
	       IF_IF_fpu_madd_fOperand_S0_first__803_BIT_195__ETC___d1931 ;
  assign IF_fpu_madd_fOperand_S0_first__803_BITS_129_TO_ETC___d1938 =
	     (fpu_madd_fOperand_S0$D_OUT[129:119] == 11'd2047 &&
	      fpu_madd_fOperand_S0$D_OUT[118:67] != 52'd0 &&
	      !fpu_madd_fOperand_S0$D_OUT[118]) ?
	       { fpu_madd_fOperand_S0$D_OUT[130:119], sfd__h99405 } :
	       ((fpu_madd_fOperand_S0$D_OUT[65:55] == 11'd2047 &&
		 fpu_madd_fOperand_S0$D_OUT[54:3] != 52'd0 &&
		 !fpu_madd_fOperand_S0$D_OUT[54]) ?
		  { fpu_madd_fOperand_S0$D_OUT[66:55], sfd__h99408 } :
		  IF_IF_fpu_madd_fOperand_S0_first__803_BIT_195__ETC___d1936) ;
  assign IF_fpu_madd_fOperand_S0_first__803_BITS_129_TO_ETC___d1959 =
	     { ((fpu_madd_fOperand_S0$D_OUT[129:119] == 11'd0) ?
		  13'd7170 :
		  { {2{fpu_madd_fOperand_S0D_OUT_BITS_129_TO_119_MIN_ETC__q128[10]}},
		    fpu_madd_fOperand_S0D_OUT_BITS_129_TO_119_MIN_ETC__q128 }) +
	       ((fpu_madd_fOperand_S0$D_OUT[65:55] == 11'd0) ?
		  13'd7170 :
		  { {2{fpu_madd_fOperand_S0D_OUT_BITS_65_TO_55_MINUS_ETC__q129[10]}},
		    fpu_madd_fOperand_S0D_OUT_BITS_65_TO_55_MINUS_ETC__q129 }),
	       x__h114243,
	       x__h114255 } ;
  assign IF_fpu_madd_fOperand_S0_first__803_BIT_195_804_ETC___d1861 =
	     x__h96539 == 11'd2047 && _theResult___fst_sfd__h96608[51] ||
	     fpu_madd_fOperand_S0$D_OUT[129:119] == 11'd2047 &&
	     fpu_madd_fOperand_S0$D_OUT[118] ||
	     fpu_madd_fOperand_S0$D_OUT[65:55] == 11'd2047 &&
	     fpu_madd_fOperand_S0$D_OUT[54] ||
	     x__h96539 == 11'd2047 && _theResult___fst_sfd__h96608 == 52'd0 ||
	     fpu_madd_fOperand_S0_first__803_BITS_129_TO_11_ETC___d1857 ;
  assign IF_fpu_madd_fOperand_S0_first__803_BIT_195_804_ETC___d1911 =
	     fpu_madd_fOperand_S0$D_OUT[195] ?
	       fpu_madd_fOperand_S0$D_OUT[193:131] :
	       63'd0 ;
  assign IF_fpu_madd_fOperand_S0_first__803_BIT_195_804_ETC___d1927 =
	     x__h96539 == 11'd2047 && _theResult___fst_sfd__h96608 == 52'd0 &&
	     (fpu_madd_fOperand_S0$D_OUT[129:119] == 11'd2047 &&
	      fpu_madd_fOperand_S0$D_OUT[118:67] == 52'd0 ||
	      fpu_madd_fOperand_S0$D_OUT[65:55] == 11'd2047 &&
	      fpu_madd_fOperand_S0$D_OUT[54:3] == 52'd0) ;
  assign IF_fpu_madd_fOperand_S0_first__803_BIT_195_804_ETC___d1947 =
	     x__h96539 == 11'd2047 && _theResult___fst_sfd__h96608 != 52'd0 &&
	     !_theResult___fst_sfd__h96608[51] ||
	     fpu_madd_fOperand_S0$D_OUT[129:119] == 11'd2047 &&
	     fpu_madd_fOperand_S0$D_OUT[118:67] != 52'd0 &&
	     !fpu_madd_fOperand_S0$D_OUT[118] ||
	     fpu_madd_fOperand_S0$D_OUT[65:55] == 11'd2047 &&
	     fpu_madd_fOperand_S0$D_OUT[54:3] != 52'd0 &&
	     !fpu_madd_fOperand_S0$D_OUT[54] ||
	     NOT_IF_fpu_madd_fOperand_S0_first__803_BIT_195_ETC___d1946 ;
  assign IF_fpu_madd_fState_S3_first__995_BITS_12_TO_0__ETC___d2516 =
	     fpu_madd_fState_S3_first__995_BITS_12_TO_0_001_ETC___d2004 ?
	       fpu_madd_fProd_S3$D_OUT != 106'd0 ||
	       fpu_madd_fState_S3$D_OUT[83] :
	       fpu_madd_fState_S3_first__995_BITS_86_TO_82_00_ETC___d2501[1] ;
  assign IF_fpu_madd_fState_S3_first__995_BITS_12_TO_0__ETC___d2521 =
	     fpu_madd_fState_S3_first__995_BITS_12_TO_0_001_ETC___d2004 ?
	       fpu_madd_fProd_S3$D_OUT != 106'd0 ||
	       fpu_madd_fState_S3$D_OUT[82] :
	       fpu_madd_fState_S3_first__995_BITS_86_TO_82_00_ETC___d2501[0] ;
  assign IF_fpu_madd_fState_S3_first__995_BITS_12_TO_0__ETC___d2536 =
	     fpu_madd_fState_S3_first__995_BITS_12_TO_0_001_ETC___d2002 ?
	       (fpu_madd_fState_S3_first__995_BITS_12_TO_0_001_ETC___d2004 ?
		  63'd0 :
		  IF_IF_7170_MINUS_fpu_madd_fState_S3_first__995_ETC___d2534) :
	       63'h7FEFFFFFFFFFFFFF ;
  assign IF_fpu_madd_fState_S3_first__995_BIT_151_996_T_ETC___d2525 =
	     fpu_madd_fState_S3$D_OUT[151] ?
	       fpu_madd_fState_S3$D_OUT[86:82] :
	       { IF_NOT_fpu_madd_fState_S3_first__995_BITS_12_T_ETC___d2503,
		 IF_NOT_fpu_madd_fState_S3_first__995_BITS_12_T_ETC___d2506,
		 NOT_fpu_madd_fState_S3_first__995_BITS_12_TO_0_ETC___d2523 } ;
  assign IF_fpu_madd_fState_S4_first__547_BITS_128_TO_1_ETC___d2568 =
	     (fpu_madd_fState_S4$D_OUT[128:118] == 11'd0) ?
	       13'd7170 :
	       { {2{fpu_madd_fState_S4D_OUT_BITS_128_TO_118_MINUS_ETC__q27[10]}},
		 fpu_madd_fState_S4D_OUT_BITS_128_TO_118_MINUS_ETC__q27 } ;
  assign IF_fpu_madd_fState_S4_first__547_BITS_64_TO_54_ETC___d2563 =
	     (fpu_madd_fState_S4$D_OUT[64:54] == 11'd0) ?
	       13'd7170 :
	       { {2{fpu_madd_fState_S4D_OUT_BITS_64_TO_54_MINUS_1023__q26[10]}},
		 fpu_madd_fState_S4D_OUT_BITS_64_TO_54_MINUS_1023__q26 } ;
  assign IF_fpu_madd_fState_S7_first__651_BITS_126_TO_1_ETC___d2668 =
	     (value__h141307[10:0] == 11'd0) ?
	       12'd3074 :
	       { value41307_BITS_10_TO_0_MINUS_1023__q28[10],
		 value41307_BITS_10_TO_0_MINUS_1023__q28 } ;
  assign IF_fpu_madd_fState_S7_first__651_BITS_126_TO_1_ETC___d2903 =
	     IF_fpu_madd_fState_S7_first__651_BITS_126_TO_1_ETC___d2668 -
	     12'd3074 ;
  assign IF_fpu_madd_fState_S8_first__960_BITS_65_TO_55_ETC___d2986 =
	     (fpu_madd_fState_S8$D_OUT[65:55] == 11'd0 &&
	      sfd__h142040[53:52] == 2'b01) ?
	       11'd1 :
	       fpu_madd_fState_S8$D_OUT[65:55] ;
  assign IF_fpu_madd_fState_S8_first__960_BITS_65_TO_55_ETC___d3011 =
	     (fpu_madd_fState_S8$D_OUT[65:55] == 11'd2047) ?
	       fpu_madd_fState_S8$D_OUT[65:55] :
	       _theResult___fst_exp__h142619 ;
  assign IF_fpu_madd_fState_S8_first__960_BIT_67_963_AN_ETC___d3060 =
	     (fpu_madd_fState_S8$D_OUT[67] &&
	      IF_fpu_madd_fState_S8_first__960_BITS_65_TO_55_ETC___d3011 ==
	      11'd0 &&
	      ((fpu_madd_fState_S8$D_OUT[65:55] == 11'd2047) ?
		 fpu_madd_fState_S8$D_OUT[54:3] :
		 _theResult___fst_sfd__h142620) ==
	      52'd0 &&
	      !fpu_madd_fState_S8_first__960_BITS_75_TO_71_03_ETC___d3043[0] &&
	      fpu_madd_fState_S8$D_OUT[0]) ?
	       fpu_madd_fState_S8$D_OUT[70:68] == 3'd3 :
	       ((fpu_madd_fState_S8$D_OUT[65:55] == 11'd2047) ?
		  fpu_madd_fState_S8$D_OUT[66] :
		  CASE_fpu_madd_fState_S8D_OUT_BITS_70_TO_68_0__ETC__q127) ;
  assign IF_fpu_madd_fState_S8_first__960_BIT_67_963_AN_ETC___d3081 =
	     { IF_fpu_madd_fState_S8_first__960_BIT_67_963_AN_ETC___d3060,
	       (fpu_madd_fState_S8$D_OUT[65:55] == 11'd2047) ?
		 fpu_madd_fState_S8$D_OUT[65:3] :
		 CASE_fpu_madd_fState_S8D_OUT_BITS_70_TO_68_0__ETC__q132,
	       fpu_madd_fState_S8_first__960_BITS_75_TO_71_03_ETC___d3043 } ;
  assign IF_fpu_sqr64_fOperand_S0_first__059_BITS_65_TO_ETC___d1193 =
	     (fpu_sqr64_fOperand_S0$D_OUT[65:55] == 11'd0) ?
	       (fpu_sqr64_fOperand_S0$D_OUT[54] ?
		  6'd2 :
		  (fpu_sqr64_fOperand_S0$D_OUT[53] ?
		     6'd3 :
		     (fpu_sqr64_fOperand_S0$D_OUT[52] ?
			6'd4 :
			(fpu_sqr64_fOperand_S0$D_OUT[51] ?
			   6'd5 :
			   (fpu_sqr64_fOperand_S0$D_OUT[50] ?
			      6'd6 :
			      (fpu_sqr64_fOperand_S0$D_OUT[49] ?
				 6'd7 :
				 (fpu_sqr64_fOperand_S0$D_OUT[48] ?
				    6'd8 :
				    (fpu_sqr64_fOperand_S0$D_OUT[47] ?
				       6'd9 :
				       (fpu_sqr64_fOperand_S0$D_OUT[46] ?
					  6'd10 :
					  (fpu_sqr64_fOperand_S0$D_OUT[45] ?
					     6'd11 :
					     (fpu_sqr64_fOperand_S0$D_OUT[44] ?
						6'd12 :
						(fpu_sqr64_fOperand_S0$D_OUT[43] ?
						   6'd13 :
						   (fpu_sqr64_fOperand_S0$D_OUT[42] ?
						      6'd14 :
						      (fpu_sqr64_fOperand_S0$D_OUT[41] ?
							 6'd15 :
							 (fpu_sqr64_fOperand_S0$D_OUT[40] ?
							    6'd16 :
							    (fpu_sqr64_fOperand_S0$D_OUT[39] ?
							       6'd17 :
							       (fpu_sqr64_fOperand_S0$D_OUT[38] ?
								  6'd18 :
								  (fpu_sqr64_fOperand_S0$D_OUT[37] ?
								     6'd19 :
								     (fpu_sqr64_fOperand_S0$D_OUT[36] ?
									6'd20 :
									(fpu_sqr64_fOperand_S0$D_OUT[35] ?
									   6'd21 :
									   (fpu_sqr64_fOperand_S0$D_OUT[34] ?
									      6'd22 :
									      (fpu_sqr64_fOperand_S0$D_OUT[33] ?
										 6'd23 :
										 (fpu_sqr64_fOperand_S0$D_OUT[32] ?
										    6'd24 :
										    (fpu_sqr64_fOperand_S0$D_OUT[31] ?
										       6'd25 :
										       (fpu_sqr64_fOperand_S0$D_OUT[30] ?
											  6'd26 :
											  (fpu_sqr64_fOperand_S0$D_OUT[29] ?
											     6'd27 :
											     (fpu_sqr64_fOperand_S0$D_OUT[28] ?
												6'd28 :
												(fpu_sqr64_fOperand_S0$D_OUT[27] ?
												   6'd29 :
												   (fpu_sqr64_fOperand_S0$D_OUT[26] ?
												      6'd30 :
												      (fpu_sqr64_fOperand_S0$D_OUT[25] ?
													 6'd31 :
													 (fpu_sqr64_fOperand_S0$D_OUT[24] ?
													    6'd32 :
													    (fpu_sqr64_fOperand_S0$D_OUT[23] ?
													       6'd33 :
													       (fpu_sqr64_fOperand_S0$D_OUT[22] ?
														  6'd34 :
														  (fpu_sqr64_fOperand_S0$D_OUT[21] ?
														     6'd35 :
														     (fpu_sqr64_fOperand_S0$D_OUT[20] ?
															6'd36 :
															(fpu_sqr64_fOperand_S0$D_OUT[19] ?
															   6'd37 :
															   (fpu_sqr64_fOperand_S0$D_OUT[18] ?
															      6'd38 :
															      (fpu_sqr64_fOperand_S0$D_OUT[17] ?
																 6'd39 :
																 (fpu_sqr64_fOperand_S0$D_OUT[16] ?
																    6'd40 :
																    (fpu_sqr64_fOperand_S0$D_OUT[15] ?
																       6'd41 :
																       (fpu_sqr64_fOperand_S0$D_OUT[14] ?
																	  6'd42 :
																	  (fpu_sqr64_fOperand_S0$D_OUT[13] ?
																	     6'd43 :
																	     (fpu_sqr64_fOperand_S0$D_OUT[12] ?
																		6'd44 :
																		(fpu_sqr64_fOperand_S0$D_OUT[11] ?
																		   6'd45 :
																		   (fpu_sqr64_fOperand_S0$D_OUT[10] ?
																		      6'd46 :
																		      (fpu_sqr64_fOperand_S0$D_OUT[9] ?
																			 6'd47 :
																			 (fpu_sqr64_fOperand_S0$D_OUT[8] ?
																			    6'd48 :
																			    (fpu_sqr64_fOperand_S0$D_OUT[7] ?
																			       6'd49 :
																			       (fpu_sqr64_fOperand_S0$D_OUT[6] ?
																				  6'd50 :
																				  (fpu_sqr64_fOperand_S0$D_OUT[5] ?
																				     6'd51 :
																				     (fpu_sqr64_fOperand_S0$D_OUT[4] ?
																					6'd52 :
																					(fpu_sqr64_fOperand_S0$D_OUT[3] ?
																					   6'd53 :
																					   6'd58)))))))))))))))))))))))))))))))))))))))))))))))))))) :
	       6'd1 ;
  assign IF_fpu_sqr64_fOperand_S0_first__059_BITS_65_TO_ETC___d1195 =
	     ((fpu_sqr64_fOperand_S0$D_OUT[65:55] == 11'd0) ?
		13'd7170 :
		{ {2{fpu_sqr64_fOperand_S0D_OUT_BITS_65_TO_55_MINU_ETC__q16[10]}},
		  fpu_sqr64_fOperand_S0D_OUT_BITS_65_TO_55_MINU_ETC__q16 }) -
	     { 7'd0,
	       IF_fpu_sqr64_fOperand_S0_first__059_BITS_65_TO_ETC___d1193 } ;
  assign IF_fpu_sqr64_fOperand_S0_first__059_BITS_65_TO_ETC___d1212 =
	     (fpu_sqr64_fOperand_S0$D_OUT[65:55] == 11'd2047 &&
	      fpu_sqr64_fOperand_S0$D_OUT[54] ||
	      fpu_sqr64_fOperand_S0$D_OUT[65:55] == 11'd0 &&
	      fpu_sqr64_fOperand_S0$D_OUT[54:3] == 52'd0 ||
	      fpu_sqr64_fOperand_S0$D_OUT[65:55] == 11'd2047 &&
	      fpu_sqr64_fOperand_S0$D_OUT[54:3] == 52'd0 &&
	      !fpu_sqr64_fOperand_S0$D_OUT[66]) ?
	       { 1'd1,
		 fpu_sqr64_fOperand_S0$D_OUT[66:3],
		 130'h00AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA } :
	       (fpu_sqr64_fOperand_S0$D_OUT[66] ?
		  195'h5FFE00000000000020AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA :
		  { 70'h155555555555555540,
		    fpu_sqr64_fOperand_S0$D_OUT[2:0],
		    fpu_sqr64_fOperand_S0$D_OUT[66],
		    x__h52551[10:0],
		    fpu_sqr64_fOperand_S0$D_OUT[54:3],
		    x__h60693 }) ;
  assign IF_fpu_sqr64_fOperand_S0_first__059_BITS_65_TO_ETC__q17 =
	     IF_fpu_sqr64_fOperand_S0_first__059_BITS_65_TO_ETC___d1195[12:1] ;
  assign IF_fpu_sqr64_fState_S1_first__216_BIT_57_226_T_ETC___d1342 =
	     (fpu_sqr64_fState_S1$D_OUT[57] ?
		7'd0 :
		(fpu_sqr64_fState_S1$D_OUT[56] ?
		   7'd1 :
		   (fpu_sqr64_fState_S1$D_OUT[55] ?
		      7'd2 :
		      (fpu_sqr64_fState_S1$D_OUT[54] ?
			 7'd3 :
			 (fpu_sqr64_fState_S1$D_OUT[53] ?
			    7'd4 :
			    (fpu_sqr64_fState_S1$D_OUT[52] ?
			       7'd5 :
			       (fpu_sqr64_fState_S1$D_OUT[51] ?
				  7'd6 :
				  (fpu_sqr64_fState_S1$D_OUT[50] ?
				     7'd7 :
				     (fpu_sqr64_fState_S1$D_OUT[49] ?
					7'd8 :
					(fpu_sqr64_fState_S1$D_OUT[48] ?
					   7'd9 :
					   (fpu_sqr64_fState_S1$D_OUT[47] ?
					      7'd10 :
					      (fpu_sqr64_fState_S1$D_OUT[46] ?
						 7'd11 :
						 (fpu_sqr64_fState_S1$D_OUT[45] ?
						    7'd12 :
						    (fpu_sqr64_fState_S1$D_OUT[44] ?
						       7'd13 :
						       (fpu_sqr64_fState_S1$D_OUT[43] ?
							  7'd14 :
							  (fpu_sqr64_fState_S1$D_OUT[42] ?
							     7'd15 :
							     (fpu_sqr64_fState_S1$D_OUT[41] ?
								7'd16 :
								(fpu_sqr64_fState_S1$D_OUT[40] ?
								   7'd17 :
								   (fpu_sqr64_fState_S1$D_OUT[39] ?
								      7'd18 :
								      (fpu_sqr64_fState_S1$D_OUT[38] ?
									 7'd19 :
									 (fpu_sqr64_fState_S1$D_OUT[37] ?
									    7'd20 :
									    (fpu_sqr64_fState_S1$D_OUT[36] ?
									       7'd21 :
									       (fpu_sqr64_fState_S1$D_OUT[35] ?
										  7'd22 :
										  (fpu_sqr64_fState_S1$D_OUT[34] ?
										     7'd23 :
										     (fpu_sqr64_fState_S1$D_OUT[33] ?
											7'd24 :
											(fpu_sqr64_fState_S1$D_OUT[32] ?
											   7'd25 :
											   (fpu_sqr64_fState_S1$D_OUT[31] ?
											      7'd26 :
											      (fpu_sqr64_fState_S1$D_OUT[30] ?
												 7'd27 :
												 (fpu_sqr64_fState_S1$D_OUT[29] ?
												    7'd28 :
												    (fpu_sqr64_fState_S1$D_OUT[28] ?
												       7'd29 :
												       (fpu_sqr64_fState_S1$D_OUT[27] ?
													  7'd30 :
													  (fpu_sqr64_fState_S1$D_OUT[26] ?
													     7'd31 :
													     (fpu_sqr64_fState_S1$D_OUT[25] ?
														7'd32 :
														(fpu_sqr64_fState_S1$D_OUT[24] ?
														   7'd33 :
														   (fpu_sqr64_fState_S1$D_OUT[23] ?
														      7'd34 :
														      (fpu_sqr64_fState_S1$D_OUT[22] ?
															 7'd35 :
															 (fpu_sqr64_fState_S1$D_OUT[21] ?
															    7'd36 :
															    (fpu_sqr64_fState_S1$D_OUT[20] ?
															       7'd37 :
															       (fpu_sqr64_fState_S1$D_OUT[19] ?
																  7'd38 :
																  (fpu_sqr64_fState_S1$D_OUT[18] ?
																     7'd39 :
																     (fpu_sqr64_fState_S1$D_OUT[17] ?
																	7'd40 :
																	(fpu_sqr64_fState_S1$D_OUT[16] ?
																	   7'd41 :
																	   (fpu_sqr64_fState_S1$D_OUT[15] ?
																	      7'd42 :
																	      (fpu_sqr64_fState_S1$D_OUT[14] ?
																		 7'd43 :
																		 (fpu_sqr64_fState_S1$D_OUT[13] ?
																		    7'd44 :
																		    (fpu_sqr64_fState_S1$D_OUT[12] ?
																		       7'd45 :
																		       (fpu_sqr64_fState_S1$D_OUT[11] ?
																			  7'd46 :
																			  (fpu_sqr64_fState_S1$D_OUT[10] ?
																			     7'd47 :
																			     (fpu_sqr64_fState_S1$D_OUT[9] ?
																				7'd48 :
																				(fpu_sqr64_fState_S1$D_OUT[8] ?
																				   7'd49 :
																				   (fpu_sqr64_fState_S1$D_OUT[7] ?
																				      7'd50 :
																				      (fpu_sqr64_fState_S1$D_OUT[6] ?
																					 7'd51 :
																					 (fpu_sqr64_fState_S1$D_OUT[5] ?
																					    7'd52 :
																					    (fpu_sqr64_fState_S1$D_OUT[4] ?
																					       7'd53 :
																					       (fpu_sqr64_fState_S1$D_OUT[3] ?
																						  7'd54 :
																						  (fpu_sqr64_fState_S1$D_OUT[2] ?
																						     7'd55 :
																						     (fpu_sqr64_fState_S1$D_OUT[1] ?
																							7'd56 :
																							(fpu_sqr64_fState_S1$D_OUT[0] ?
																							   7'd57 :
																							   7'd116)))))))))))))))))))))))))))))))))))))))))))))))))))))))))) -
	     7'd1 ;
  assign IF_fpu_sqr64_fState_S3_first__375_BITS_121_TO__ETC___d1389 =
	     (fpu_sqr64_fState_S3$D_OUT[121:111] == 11'd0) ?
	       12'd3074 :
	       { fpu_sqr64_fState_S3D_OUT_BITS_121_TO_111_MINU_ETC__q18[10],
		 fpu_sqr64_fState_S3D_OUT_BITS_121_TO_111_MINU_ETC__q18 } ;
  assign IF_fpu_sqr64_fState_S3_first__375_BITS_121_TO__ETC___d1632 =
	     IF_fpu_sqr64_fState_S3_first__375_BITS_121_TO__ETC___d1389 -
	     12'd3074 ;
  assign IF_fpu_sqr64_fState_S3_first__375_BIT_195_376__ETC___d1671 =
	     fpu_sqr64_fState_S3$D_OUT[195] ?
	       fpu_sqr64_fState_S3$D_OUT[128:126] :
	       { fpu_sqr64_fState_S3$D_OUT[58] &&
		 IF_fpu_sqr64_fState_S3_first__375_BITS_121_TO__ETC___d1389 ==
		 12'd1023,
		 _theResult___fst_exp__h94753 == 11'd0 &&
		 guard__h86435 != 2'd0,
		 fpu_sqr64_fState_S3$D_OUT[58] &&
		 IF_fpu_sqr64_fState_S3_first__375_BITS_121_TO__ETC___d1389 ==
		 12'd1023 } ;
  assign IF_fpu_sqr64_fState_S3_first__375_BIT_58_384_A_ETC___d1678 =
	     (fpu_sqr64_fState_S3$D_OUT[58] &&
	      IF_fpu_sqr64_fState_S3_first__375_BITS_121_TO__ETC___d1389 ==
	      12'd1023) ?
	       63'h7FEFFFFFFFFFFFFF :
	       { _theResult___fst_exp__h94750, sfdin__h94744[58:7] } ;
  assign IF_fpu_sqr64_fState_S3_first__375_BIT_58_384_T_ETC___d1630 =
	     (fpu_sqr64_fState_S3$D_OUT[58] ?
		6'd0 :
		(fpu_sqr64_fState_S3$D_OUT[57] ?
		   6'd1 :
		   (fpu_sqr64_fState_S3$D_OUT[56] ?
		      6'd2 :
		      (fpu_sqr64_fState_S3$D_OUT[55] ?
			 6'd3 :
			 (fpu_sqr64_fState_S3$D_OUT[54] ?
			    6'd4 :
			    (fpu_sqr64_fState_S3$D_OUT[53] ?
			       6'd5 :
			       (fpu_sqr64_fState_S3$D_OUT[52] ?
				  6'd6 :
				  (fpu_sqr64_fState_S3$D_OUT[51] ?
				     6'd7 :
				     (fpu_sqr64_fState_S3$D_OUT[50] ?
					6'd8 :
					(fpu_sqr64_fState_S3$D_OUT[49] ?
					   6'd9 :
					   (fpu_sqr64_fState_S3$D_OUT[48] ?
					      6'd10 :
					      (fpu_sqr64_fState_S3$D_OUT[47] ?
						 6'd11 :
						 (fpu_sqr64_fState_S3$D_OUT[46] ?
						    6'd12 :
						    (fpu_sqr64_fState_S3$D_OUT[45] ?
						       6'd13 :
						       (fpu_sqr64_fState_S3$D_OUT[44] ?
							  6'd14 :
							  (fpu_sqr64_fState_S3$D_OUT[43] ?
							     6'd15 :
							     (fpu_sqr64_fState_S3$D_OUT[42] ?
								6'd16 :
								(fpu_sqr64_fState_S3$D_OUT[41] ?
								   6'd17 :
								   (fpu_sqr64_fState_S3$D_OUT[40] ?
								      6'd18 :
								      (fpu_sqr64_fState_S3$D_OUT[39] ?
									 6'd19 :
									 (fpu_sqr64_fState_S3$D_OUT[38] ?
									    6'd20 :
									    (fpu_sqr64_fState_S3$D_OUT[37] ?
									       6'd21 :
									       (fpu_sqr64_fState_S3$D_OUT[36] ?
										  6'd22 :
										  (fpu_sqr64_fState_S3$D_OUT[35] ?
										     6'd23 :
										     (fpu_sqr64_fState_S3$D_OUT[34] ?
											6'd24 :
											(fpu_sqr64_fState_S3$D_OUT[33] ?
											   6'd25 :
											   (fpu_sqr64_fState_S3$D_OUT[32] ?
											      6'd26 :
											      (fpu_sqr64_fState_S3$D_OUT[31] ?
												 6'd27 :
												 (fpu_sqr64_fState_S3$D_OUT[30] ?
												    6'd28 :
												    (fpu_sqr64_fState_S3$D_OUT[29] ?
												       6'd29 :
												       (fpu_sqr64_fState_S3$D_OUT[28] ?
													  6'd30 :
													  (fpu_sqr64_fState_S3$D_OUT[27] ?
													     6'd31 :
													     (fpu_sqr64_fState_S3$D_OUT[26] ?
														6'd32 :
														(fpu_sqr64_fState_S3$D_OUT[25] ?
														   6'd33 :
														   (fpu_sqr64_fState_S3$D_OUT[24] ?
														      6'd34 :
														      (fpu_sqr64_fState_S3$D_OUT[23] ?
															 6'd35 :
															 (fpu_sqr64_fState_S3$D_OUT[22] ?
															    6'd36 :
															    (fpu_sqr64_fState_S3$D_OUT[21] ?
															       6'd37 :
															       (fpu_sqr64_fState_S3$D_OUT[20] ?
																  6'd38 :
																  (fpu_sqr64_fState_S3$D_OUT[19] ?
																     6'd39 :
																     (fpu_sqr64_fState_S3$D_OUT[18] ?
																	6'd40 :
																	(fpu_sqr64_fState_S3$D_OUT[17] ?
																	   6'd41 :
																	   (fpu_sqr64_fState_S3$D_OUT[16] ?
																	      6'd42 :
																	      (fpu_sqr64_fState_S3$D_OUT[15] ?
																		 6'd43 :
																		 (fpu_sqr64_fState_S3$D_OUT[14] ?
																		    6'd44 :
																		    (fpu_sqr64_fState_S3$D_OUT[13] ?
																		       6'd45 :
																		       (fpu_sqr64_fState_S3$D_OUT[12] ?
																			  6'd46 :
																			  (fpu_sqr64_fState_S3$D_OUT[11] ?
																			     6'd47 :
																			     (fpu_sqr64_fState_S3$D_OUT[10] ?
																				6'd48 :
																				(fpu_sqr64_fState_S3$D_OUT[9] ?
																				   6'd49 :
																				   (fpu_sqr64_fState_S3$D_OUT[8] ?
																				      6'd50 :
																				      (fpu_sqr64_fState_S3$D_OUT[7] ?
																					 6'd51 :
																					 (fpu_sqr64_fState_S3$D_OUT[6] ?
																					    6'd52 :
																					    (fpu_sqr64_fState_S3$D_OUT[5] ?
																					       6'd53 :
																					       (fpu_sqr64_fState_S3$D_OUT[4] ?
																						  6'd54 :
																						  (fpu_sqr64_fState_S3$D_OUT[3] ?
																						     6'd55 :
																						     (fpu_sqr64_fState_S3$D_OUT[2] ?
																							6'd56 :
																							(fpu_sqr64_fState_S3$D_OUT[1] ?
																							   6'd57 :
																							   (fpu_sqr64_fState_S3$D_OUT[0] ?
																							      6'd58 :
																							      6'd59))))))))))))))))))))))))))))))))))))))))))))))))))))))))))) -
	     6'd1 ;
  assign IF_fpu_sqr64_fState_S4_first__687_BITS_64_TO_5_ETC___d1721 =
	     (fpu_sqr64_fState_S4$D_OUT[64:54] == 11'd0 &&
	      sfd__h95416[53:52] == 2'b01) ?
	       11'd1 :
	       fpu_sqr64_fState_S4$D_OUT[64:54] ;
  assign IF_iFifo_first__087_BITS_102_TO_95_625_EQ_0_63_ETC___d4757 =
	     ((iFifo$D_OUT[102:95] == 8'd0) ?
		(iFifo$D_OUT[94] ?
		   6'd2 :
		   (iFifo$D_OUT[93] ?
		      6'd3 :
		      (iFifo$D_OUT[92] ?
			 6'd4 :
			 (iFifo$D_OUT[91] ?
			    6'd5 :
			    (iFifo$D_OUT[90] ?
			       6'd6 :
			       (iFifo$D_OUT[89] ?
				  6'd7 :
				  (iFifo$D_OUT[88] ?
				     6'd8 :
				     (iFifo$D_OUT[87] ?
					6'd9 :
					(iFifo$D_OUT[86] ?
					   6'd10 :
					   (iFifo$D_OUT[85] ?
					      6'd11 :
					      (iFifo$D_OUT[84] ?
						 6'd12 :
						 (iFifo$D_OUT[83] ?
						    6'd13 :
						    (iFifo$D_OUT[82] ?
						       6'd14 :
						       (iFifo$D_OUT[81] ?
							  6'd15 :
							  (iFifo$D_OUT[80] ?
							     6'd16 :
							     (iFifo$D_OUT[79] ?
								6'd17 :
								(iFifo$D_OUT[78] ?
								   6'd18 :
								   (iFifo$D_OUT[77] ?
								      6'd19 :
								      (iFifo$D_OUT[76] ?
									 6'd20 :
									 (iFifo$D_OUT[75] ?
									    6'd21 :
									    (iFifo$D_OUT[74] ?
									       6'd22 :
									       (iFifo$D_OUT[73] ?
										  6'd23 :
										  (iFifo$D_OUT[72] ?
										     6'd24 :
										     6'd57))))))))))))))))))))))) :
		6'd1) -
	     6'd1 ;
  assign IF_iFifo_first__087_BITS_102_TO_95_625_EQ_0_63_ETC___d5148 =
	     (iFifo$D_OUT[102:95] == 8'd0) ?
	       (_3970_MINUS_0_CONCAT_IF_iFifo_first__087_BIT_94_ETC___d4684 ?
		  IF_3970_MINUS_0_CONCAT_IF_iFifo_first__087_BIT_ETC___d4802 :
		  IF_iFifo_first__087_BITS_6_TO_4_118_EQ_0_191_O_ETC___d4803) :
	       (SEXT_iFifo_first__087_BITS_102_TO_95_625_MINUS_ETC___d4807 ?
		  IF_SEXT_iFifo_first__087_BITS_102_TO_95_625_MI_ETC___d5146 :
		  IF_iFifo_first__087_BITS_6_TO_4_118_EQ_0_191_O_ETC___d4803) ;
  assign IF_iFifo_first__087_BITS_102_TO_95_625_EQ_0_63_ETC___d5376 =
	     (iFifo$D_OUT[102:95] == 8'd0) ?
	       (_3970_MINUS_0_CONCAT_IF_iFifo_first__087_BIT_94_ETC___d4684 ?
		  IF_3970_MINUS_0_CONCAT_IF_iFifo_first__087_BIT_ETC___d5347 :
		  IF_iFifo_first__087_BITS_6_TO_4_118_EQ_0_191_O_ETC___d5348) :
	       (SEXT_iFifo_first__087_BITS_102_TO_95_625_MINUS_ETC___d4807 ?
		  IF_SEXT_iFifo_first__087_BITS_102_TO_95_625_MI_ETC___d5374 :
		  IF_iFifo_first__087_BITS_6_TO_4_118_EQ_0_191_O_ETC___d5348) ;
  assign IF_iFifo_first__087_BITS_102_TO_95_625_EQ_255__ETC___d5327 =
	     { (iFifo$D_OUT[102:95] == 8'd255) ?
		 11'd2047 :
		 _theResult___fst_exp__h221054,
	       (iFifo$D_OUT[102:95] == 8'd255 &&
		iFifo$D_OUT[94:72] != 23'd0) ?
		 _theResult___snd_fst_sfd__h183126 :
		 _theResult___fst_sfd__h221058 } ;
  assign IF_iFifo_first__087_BITS_102_TO_95_625_EQ_255__ETC___d5328 =
	     { (iFifo$D_OUT[102:95] == 8'd255 &&
		iFifo$D_OUT[94:72] != 23'd0 ||
		(iFifo$D_OUT[102:95] == 8'd255 ||
		 iFifo$D_OUT[102:95] == 8'd0) &&
		iFifo$D_OUT[94:72] == 23'd0) ?
		 iFifo$D_OUT[103] :
		 IF_iFifo_first__087_BITS_102_TO_95_625_EQ_0_63_ETC___d5148,
	       IF_iFifo_first__087_BITS_102_TO_95_625_EQ_255__ETC___d5327 } ;
  assign IF_iFifo_first__087_BITS_102_TO_95_625_EQ_255__ETC___d5378 =
	     { (iFifo$D_OUT[102:95] == 8'd255 &&
		iFifo$D_OUT[94:72] != 23'd0 ||
		(iFifo$D_OUT[102:95] == 8'd255 ||
		 iFifo$D_OUT[102:95] == 8'd0) &&
		iFifo$D_OUT[94:72] == 23'd0) ?
		 !iFifo$D_OUT[103] :
		 IF_iFifo_first__087_BITS_102_TO_95_625_EQ_0_63_ETC___d5376,
	       IF_iFifo_first__087_BITS_102_TO_95_625_EQ_255__ETC___d5327 } ;
  assign IF_iFifo_first__087_BITS_167_TO_160_130_EQ_0_1_ETC___d3271 =
	     ((iFifo$D_OUT[167:160] == 8'd0) ?
		(iFifo$D_OUT[159] ?
		   6'd2 :
		   (iFifo$D_OUT[158] ?
		      6'd3 :
		      (iFifo$D_OUT[157] ?
			 6'd4 :
			 (iFifo$D_OUT[156] ?
			    6'd5 :
			    (iFifo$D_OUT[155] ?
			       6'd6 :
			       (iFifo$D_OUT[154] ?
				  6'd7 :
				  (iFifo$D_OUT[153] ?
				     6'd8 :
				     (iFifo$D_OUT[152] ?
					6'd9 :
					(iFifo$D_OUT[151] ?
					   6'd10 :
					   (iFifo$D_OUT[150] ?
					      6'd11 :
					      (iFifo$D_OUT[149] ?
						 6'd12 :
						 (iFifo$D_OUT[148] ?
						    6'd13 :
						    (iFifo$D_OUT[147] ?
						       6'd14 :
						       (iFifo$D_OUT[146] ?
							  6'd15 :
							  (iFifo$D_OUT[145] ?
							     6'd16 :
							     (iFifo$D_OUT[144] ?
								6'd17 :
								(iFifo$D_OUT[143] ?
								   6'd18 :
								   (iFifo$D_OUT[142] ?
								      6'd19 :
								      (iFifo$D_OUT[141] ?
									 6'd20 :
									 (iFifo$D_OUT[140] ?
									    6'd21 :
									    (iFifo$D_OUT[139] ?
									       6'd22 :
									       (iFifo$D_OUT[138] ?
										  6'd23 :
										  (iFifo$D_OUT[137] ?
										     6'd24 :
										     6'd57))))))))))))))))))))))) :
		6'd1) -
	     6'd1 ;
  assign IF_iFifo_first__087_BITS_167_TO_160_130_EQ_0_1_ETC___d3665 =
	     (iFifo$D_OUT[167:160] == 8'd0) ?
	       (_3970_MINUS_0_CONCAT_IF_iFifo_first__087_BIT_15_ETC___d3189 ?
		  IF_3970_MINUS_0_CONCAT_IF_iFifo_first__087_BIT_ETC___d3317 :
		  IF_iFifo_first__087_BITS_6_TO_4_118_EQ_0_191_O_ETC___d3320) :
	       (SEXT_iFifo_first__087_BITS_167_TO_160_130_MINU_ETC___d3324 ?
		  IF_SEXT_iFifo_first__087_BITS_167_TO_160_130_M_ETC___d3663 :
		  IF_iFifo_first__087_BITS_6_TO_4_118_EQ_0_191_O_ETC___d3320) ;
  assign IF_iFifo_first__087_BITS_167_TO_160_130_EQ_255_ETC___d3846 =
	     { (iFifo$D_OUT[167:160] == 8'd255 &&
		iFifo$D_OUT[159:137] != 23'd0 ||
		(iFifo$D_OUT[167:160] == 8'd255 ||
		 iFifo$D_OUT[167:160] == 8'd0) &&
		iFifo$D_OUT[159:137] == 23'd0) ?
		 iFifo$D_OUT[168] :
		 IF_iFifo_first__087_BITS_167_TO_160_130_EQ_0_1_ETC___d3665,
	       (iFifo$D_OUT[167:160] == 8'd255) ?
		 11'd2047 :
		 _theResult___fst_exp__h182416,
	       (iFifo$D_OUT[167:160] == 8'd255 &&
		iFifo$D_OUT[159:137] != 23'd0) ?
		 _theResult___snd_fst_sfd__h144486 :
		 _theResult___fst_sfd__h182420 } ;
  assign IF_iFifo_first__087_BITS_37_TO_30_850_EQ_0_856_ETC___d3982 =
	     ((iFifo$D_OUT[37:30] == 8'd0) ?
		(iFifo$D_OUT[29] ?
		   6'd2 :
		   (iFifo$D_OUT[28] ?
		      6'd3 :
		      (iFifo$D_OUT[27] ?
			 6'd4 :
			 (iFifo$D_OUT[26] ?
			    6'd5 :
			    (iFifo$D_OUT[25] ?
			       6'd6 :
			       (iFifo$D_OUT[24] ?
				  6'd7 :
				  (iFifo$D_OUT[23] ?
				     6'd8 :
				     (iFifo$D_OUT[22] ?
					6'd9 :
					(iFifo$D_OUT[21] ?
					   6'd10 :
					   (iFifo$D_OUT[20] ?
					      6'd11 :
					      (iFifo$D_OUT[19] ?
						 6'd12 :
						 (iFifo$D_OUT[18] ?
						    6'd13 :
						    (iFifo$D_OUT[17] ?
						       6'd14 :
						       (iFifo$D_OUT[16] ?
							  6'd15 :
							  (iFifo$D_OUT[15] ?
							     6'd16 :
							     (iFifo$D_OUT[14] ?
								6'd17 :
								(iFifo$D_OUT[13] ?
								   6'd18 :
								   (iFifo$D_OUT[12] ?
								      6'd19 :
								      (iFifo$D_OUT[11] ?
									 6'd20 :
									 (iFifo$D_OUT[10] ?
									    6'd21 :
									    (iFifo$D_OUT[9] ?
									       6'd22 :
									       (iFifo$D_OUT[8] ?
										  6'd23 :
										  (iFifo$D_OUT[7] ?
										     6'd24 :
										     6'd57))))))))))))))))))))))) :
		6'd1) -
	     6'd1 ;
  assign IF_iFifo_first__087_BITS_37_TO_30_850_EQ_0_856_ETC___d4373 =
	     (iFifo$D_OUT[37:30] == 8'd0) ?
	       (_3970_MINUS_0_CONCAT_IF_iFifo_first__087_BIT_29_ETC___d3909 ?
		  IF_3970_MINUS_0_CONCAT_IF_iFifo_first__087_BIT_ETC___d4027 :
		  IF_iFifo_first__087_BITS_6_TO_4_118_EQ_0_191_O_ETC___d4028) :
	       (SEXT_iFifo_first__087_BITS_37_TO_30_850_MINUS__ETC___d4032 ?
		  IF_SEXT_iFifo_first__087_BITS_37_TO_30_850_MIN_ETC___d4371 :
		  IF_iFifo_first__087_BITS_6_TO_4_118_EQ_0_191_O_ETC___d4028) ;
  assign IF_iFifo_first__087_BITS_37_TO_30_850_EQ_0_856_ETC___d4610 =
	     (iFifo$D_OUT[37:30] == 8'd0) ?
	       (_3970_MINUS_0_CONCAT_IF_iFifo_first__087_BIT_29_ETC___d3909 ?
		  IF_3970_MINUS_0_CONCAT_IF_iFifo_first__087_BIT_ETC___d4581 :
		  IF_iFifo_first__087_BITS_6_TO_4_118_EQ_0_191_O_ETC___d4582) :
	       (SEXT_iFifo_first__087_BITS_37_TO_30_850_MINUS__ETC___d4032 ?
		  IF_SEXT_iFifo_first__087_BITS_37_TO_30_850_MIN_ETC___d4608 :
		  IF_iFifo_first__087_BITS_6_TO_4_118_EQ_0_191_O_ETC___d4582) ;
  assign IF_iFifo_first__087_BITS_37_TO_30_850_EQ_255_8_ETC___d4552 =
	     { (iFifo$D_OUT[37:30] == 8'd255) ?
		 11'd2047 :
		 _theResult___fst_exp__h259993,
	       (iFifo$D_OUT[37:30] == 8'd255 && iFifo$D_OUT[29:7] != 23'd0) ?
		 _theResult___snd_fst_sfd__h222065 :
		 _theResult___fst_sfd__h259997 } ;
  assign IF_iFifo_first__087_BITS_37_TO_30_850_EQ_255_8_ETC___d4553 =
	     { (iFifo$D_OUT[37:30] == 8'd255 && iFifo$D_OUT[29:7] != 23'd0 ||
		(iFifo$D_OUT[37:30] == 8'd255 ||
		 iFifo$D_OUT[37:30] == 8'd0) &&
		iFifo$D_OUT[29:7] == 23'd0) ?
		 iFifo$D_OUT[38] :
		 IF_iFifo_first__087_BITS_37_TO_30_850_EQ_0_856_ETC___d4373,
	       IF_iFifo_first__087_BITS_37_TO_30_850_EQ_255_8_ETC___d4552 } ;
  assign IF_iFifo_first__087_BITS_37_TO_30_850_EQ_255_8_ETC___d4612 =
	     { (iFifo$D_OUT[37:30] == 8'd255 && iFifo$D_OUT[29:7] != 23'd0 ||
		(iFifo$D_OUT[37:30] == 8'd255 ||
		 iFifo$D_OUT[37:30] == 8'd0) &&
		iFifo$D_OUT[29:7] == 23'd0) ?
		 !iFifo$D_OUT[38] :
		 IF_iFifo_first__087_BITS_37_TO_30_850_EQ_0_856_ETC___d4610,
	       IF_iFifo_first__087_BITS_37_TO_30_850_EQ_255_8_ETC___d4552 } ;
  assign IF_iFifo_first__087_BIT_136_624_THEN_IF_iFifo__ETC___d5330 =
	     iFifo$D_OUT[136] ?
	       IF_iFifo_first__087_BITS_102_TO_95_625_EQ_255__ETC___d5328 :
	       iFifo$D_OUT[135:72] ;
  assign IF_iFifo_first__087_BIT_201_115_THEN_IF_iFifo__ETC___d3848 =
	     iFifo$D_OUT[201] ?
	       IF_iFifo_first__087_BITS_167_TO_160_130_EQ_255_ETC___d3846 :
	       iFifo$D_OUT[200:137] ;
  assign IF_iFifo_first__087_BIT_71_849_THEN_IF_iFifo_f_ETC___d4555 =
	     iFifo$D_OUT[71] ?
	       IF_iFifo_first__087_BITS_37_TO_30_850_EQ_255_8_ETC___d4553 :
	       iFifo$D_OUT[70:7] ;
  assign IF_iFifo_first__087_BIT_71_849_THEN_IF_iFifo_f_ETC___d4618 =
	     iFifo$D_OUT[71] ?
	       IF_iFifo_first__087_BITS_37_TO_30_850_EQ_255_8_ETC___d4612 :
	       { iFifo$D_OUT[71] || !iFifo$D_OUT[70], iFifo$D_OUT[69:7] } ;
  assign IF_isDoubleFifo_first__407_THEN_IF_isNegateFif_ETC___d6657 =
	     isDoubleFifo$D_OUT ?
	       { isNegateFifo$D_OUT ^ resWire$wget[68], resWire$wget[67:5] } :
	       { 32'hAAAAAAAA,
		 IF_isNegateFifo_first__409_THEN_IF_resWire_wge_ETC___d6424,
		 exp__h304706,
		 sfd__h304707 } ;
  assign IF_isNegateFifo_first__409_THEN_IF_resWire_wge_ETC___d6424 =
	     isNegateFifo$D_OUT ?
	       ((resWire$wget[67:57] == 11'd2047 &&
		 resWire$wget[56:5] != 52'd0 ||
		 (resWire$wget[67:57] == 11'd2047 ||
		  resWire$wget[67:57] == 11'd0) &&
		 resWire$wget[56:5] == 52'd0) ?
		  !resWire$wget[68] :
		  IF_resWire_wget__410_BITS_67_TO_57_416_EQ_0_42_ETC___d6377) :
	       ((resWire$wget[67:57] == 11'd2047 &&
		 resWire$wget[56:5] != 52'd0 ||
		 (resWire$wget[67:57] == 11'd2047 ||
		  resWire$wget[67:57] == 11'd0) &&
		 resWire$wget[56:5] == 52'd0) ?
		  resWire$wget[68] :
		  IF_resWire_wget__410_BITS_67_TO_57_416_EQ_0_42_ETC___d6422) ;
  assign IF_resWire_wget__410_BITS_67_TO_57_416_EQ_0_42_ETC___d5982 =
	     ((resWire$wget[67:57] == 11'd0) ?
		(resWire$wget[56] ?
		   6'd2 :
		   (resWire$wget[55] ?
		      6'd3 :
		      (resWire$wget[54] ?
			 6'd4 :
			 (resWire$wget[53] ?
			    6'd5 :
			    (resWire$wget[52] ?
			       6'd6 :
			       (resWire$wget[51] ?
				  6'd7 :
				  (resWire$wget[50] ?
				     6'd8 :
				     (resWire$wget[49] ?
					6'd9 :
					(resWire$wget[48] ?
					   6'd10 :
					   (resWire$wget[47] ?
					      6'd11 :
					      (resWire$wget[46] ?
						 6'd12 :
						 (resWire$wget[45] ?
						    6'd13 :
						    (resWire$wget[44] ?
						       6'd14 :
						       (resWire$wget[43] ?
							  6'd15 :
							  (resWire$wget[42] ?
							     6'd16 :
							     (resWire$wget[41] ?
								6'd17 :
								(resWire$wget[40] ?
								   6'd18 :
								   (resWire$wget[39] ?
								      6'd19 :
								      (resWire$wget[38] ?
									 6'd20 :
									 (resWire$wget[37] ?
									    6'd21 :
									    (resWire$wget[36] ?
									       6'd22 :
									       (resWire$wget[35] ?
										  6'd23 :
										  (resWire$wget[34] ?
										     6'd24 :
										     (resWire$wget[33] ?
											6'd25 :
											(resWire$wget[32] ?
											   6'd26 :
											   (resWire$wget[31] ?
											      6'd27 :
											      (resWire$wget[30] ?
												 6'd28 :
												 (resWire$wget[29] ?
												    6'd29 :
												    (resWire$wget[28] ?
												       6'd30 :
												       (resWire$wget[27] ?
													  6'd31 :
													  (resWire$wget[26] ?
													     6'd32 :
													     (resWire$wget[25] ?
														6'd33 :
														(resWire$wget[24] ?
														   6'd34 :
														   (resWire$wget[23] ?
														      6'd35 :
														      (resWire$wget[22] ?
															 6'd36 :
															 (resWire$wget[21] ?
															    6'd37 :
															    (resWire$wget[20] ?
															       6'd38 :
															       (resWire$wget[19] ?
																  6'd39 :
																  (resWire$wget[18] ?
																     6'd40 :
																     (resWire$wget[17] ?
																	6'd41 :
																	(resWire$wget[16] ?
																	   6'd42 :
																	   (resWire$wget[15] ?
																	      6'd43 :
																	      (resWire$wget[14] ?
																		 6'd44 :
																		 (resWire$wget[13] ?
																		    6'd45 :
																		    (resWire$wget[12] ?
																		       6'd46 :
																		       (resWire$wget[11] ?
																			  6'd47 :
																			  (resWire$wget[10] ?
																			     6'd48 :
																			     (resWire$wget[9] ?
																				6'd49 :
																				(resWire$wget[8] ?
																				   6'd50 :
																				   (resWire$wget[7] ?
																				      6'd51 :
																				      (resWire$wget[6] ?
																					 6'd52 :
																					 (resWire$wget[5] ?
																					    6'd53 :
																					    6'd57)))))))))))))))))))))))))))))))))))))))))))))))))))) :
		6'd1) -
	     6'd1 ;
  assign IF_resWire_wget__410_BITS_67_TO_57_416_EQ_0_42_ETC___d6377 =
	     (resWire$wget[67:57] == 11'd0) ?
	       (_3074_MINUS_0_CONCAT_IF_resWire_wget__410_BIT_5_ETC___d5532 ?
		  IF_3074_MINUS_0_CONCAT_IF_resWire_wget__410_BI_ETC___d6025 :
		  IF_rmdFifo_first__778_EQ_0_779_OR_rmdFifo_firs_ETC___d6028) :
	       (SEXT_resWire_wget__410_BITS_67_TO_57_416_MINUS_ETC___d6032 ?
		  IF_SEXT_resWire_wget__410_BITS_67_TO_57_416_MI_ETC___d6375 :
		  IF_rmdFifo_first__778_EQ_0_779_OR_rmdFifo_firs_ETC___d6028) ;
  assign IF_resWire_wget__410_BITS_67_TO_57_416_EQ_0_42_ETC___d6422 =
	     (resWire$wget[67:57] == 11'd0) ?
	       (_3074_MINUS_0_CONCAT_IF_resWire_wget__410_BIT_5_ETC___d5532 ?
		  IF_3074_MINUS_0_CONCAT_IF_resWire_wget__410_BI_ETC___d6399 :
		  IF_rmdFifo_first__778_EQ_0_779_OR_rmdFifo_firs_ETC___d6400) :
	       (SEXT_resWire_wget__410_BITS_67_TO_57_416_MINUS_ETC___d6032 ?
		  IF_SEXT_resWire_wget__410_BITS_67_TO_57_416_MI_ETC___d6420 :
		  IF_rmdFifo_first__778_EQ_0_779_OR_rmdFifo_firs_ETC___d6400) ;
  assign IF_resWire_wget__410_BITS_67_TO_57_416_EQ_0_42_ETC___d6709 =
	     (resWire$wget[67:57] == 11'd0) ?
	       _3074_MINUS_0_CONCAT_IF_resWire_wget__410_BIT_5_ETC___d6691 :
	       SEXT_resWire_wget__410_BITS_67_TO_57_416_MINUS_ETC___d6032 &&
	       SEXT_resWire_wget__410_BITS_67_TO_57_416_MINUS_ETC___d6033 &&
	       _0_CONCAT_IF_IF_3970_MINUS_SEXT_resWire_wget__4_ETC___d6705[4] ;
  assign IF_resWire_wget__410_BITS_67_TO_57_416_EQ_0_42_ETC___d6720 =
	     (resWire$wget[67:57] == 11'd0) ?
	       _3074_MINUS_0_CONCAT_IF_resWire_wget__410_BIT_5_ETC___d6716 :
	       SEXT_resWire_wget__410_BITS_67_TO_57_416_MINUS_ETC___d6032 &&
	       SEXT_resWire_wget__410_BITS_67_TO_57_416_MINUS_ETC___d6033 &&
	       _0_CONCAT_IF_IF_3970_MINUS_SEXT_resWire_wget__4_ETC___d6705[3] ;
  assign IF_resWire_wget__410_BITS_67_TO_57_416_EQ_0_42_ETC___d6736 =
	     (resWire$wget[67:57] == 11'd0) ?
	       NOT_3074_MINUS_0_CONCAT_IF_resWire_wget__410_B_ETC___d6728 :
	       !SEXT_resWire_wget__410_BITS_67_TO_57_416_MINUS_ETC___d6032 ||
	       IF_SEXT_resWire_wget__410_BITS_67_TO_57_416_MI_ETC___d6734 ;
  assign IF_resWire_wget__410_BITS_67_TO_57_416_EQ_0_42_ETC___d6749 =
	     (resWire$wget[67:57] == 11'd0) ?
	       _3074_MINUS_0_CONCAT_IF_resWire_wget__410_BIT_5_ETC___d6743 :
	       SEXT_resWire_wget__410_BITS_67_TO_57_416_MINUS_ETC___d6032 &&
	       IF_SEXT_resWire_wget__410_BITS_67_TO_57_416_MI_ETC___d6747 ;
  assign IF_resWire_wget__410_BITS_67_TO_57_416_EQ_0_42_ETC___d6762 =
	     (resWire$wget[67:57] == 11'd0) ?
	       NOT_3074_MINUS_0_CONCAT_IF_resWire_wget__410_B_ETC___d6756 :
	       !SEXT_resWire_wget__410_BITS_67_TO_57_416_MINUS_ETC___d6032 ||
	       IF_SEXT_resWire_wget__410_BITS_67_TO_57_416_MI_ETC___d6760 ;
  assign IF_rg_index_1_4_ULE_58_8_THEN_IF_rg_res_1_BIT__ETC___d49 =
	     rg_index_1_4_ULE_58___d38 ? _theResult___fst__h1515 : rg_b ;
  assign IF_rg_index_1_4_ULE_58_8_THEN_IF_rg_res_1_BIT__ETC___d69 =
	     rg_index_1_4_ULE_58___d38 ?
	       _theResult___snd_snd_snd__h1520 :
	       rg_r_1 ;
  assign IF_rg_index_1_4_ULE_58_8_THEN_IF_rg_res_1_BIT__ETC___d73 =
	     rg_index_1_4_ULE_58___d38 ?
	       IF_rg_res_1_BIT_116_2_THEN_rg_res_1_BITS_115_T_ETC___d72 :
	       rg_res[115:0] ;
  assign IF_rg_index_1_4_ULE_58_8_THEN_IF_rg_res_1_BIT__ETC___d83 =
	     rg_index_1_4_ULE_58___d38 ? _theResult___snd_fst__h1517 : rg_s ;
  assign IF_rg_index_1_4_ULE_58_8_THEN_IF_rg_res_1_BIT__ETC___d85 =
	     IF_rg_index_1_4_ULE_58_8_THEN_IF_rg_res_1_BIT__ETC___d83 <
	     sum__h1710 ;
  assign IF_rg_index_1_4_ULE_58_8_THEN_NOT_rg_b_9_EQ_0__ETC___d56 =
	     rg_index_1_4_ULE_58___d38 ?
	       rg_b != 116'd0 && !rg_res[116] :
	       !rg_res[116] ;
  assign IF_rg_index_1_4_ULE_58_8_THEN_rg_b_9_EQ_0_0_OR_ETC___d44 =
	     rg_index_1_4_ULE_58___d38 ?
	       rg_b == 116'd0 || rg_res[116] :
	       rg_res[116] ;
  assign IF_rg_index_ULE_57_THEN_IF_rg_r_0_BIT_115_1_TH_ETC___d22 =
	     rg_index_ULE_57___d7 ?
	       (rg_r[115] ?
		  { rg_r[114:0], 1'd0 } + b__h32583 :
		  { rg_r[114:0], 1'd0 } - b__h32583) :
	       rg_r ;
  assign IF_rg_index_ULE_57_THEN_rg_q_BITS_56_TO_0_CONC_ETC___d14 =
	     rg_index_ULE_57___d7 ? { rg_q[56:0], !rg_r[115] } : rg_q ;
  assign IF_rg_r_BIT_115_THEN_rg_q_PLUS_NEG_INV_rg_q_59_ETC__q10 =
	     rg_r[115] ?
	       rg_q_PLUS_NEG_INV_rg_q_59_60___d561 - 58'd1 :
	       rg_q_PLUS_NEG_INV_rg_q_59_60___d561 ;
  assign IF_rg_res_1_BIT_116_2_THEN_rg_res_1_BITS_115_T_ETC___d72 =
	     rg_res[116] ?
	       rg_res[115:0] :
	       ((rg_b == 116'd0) ? rg_r_1 : rg_res[115:0]) ;
  assign IF_sfdin11484_BIT_4_THEN_2_ELSE_0__q98 =
	     sfdin__h211484[4] ? 2'd2 : 2'd0 ;
  assign IF_sfdin2327_BIT_5_THEN_2_ELSE_0__q13 =
	     sfdin__h42327[5] ? 2'd2 : 2'd0 ;
  assign IF_sfdin30943_BIT_53_THEN_2_ELSE_0__q25 =
	     sfdin__h130943[53] ? 2'd2 : 2'd0 ;
  assign IF_sfdin41369_BIT_4_THEN_2_ELSE_0__q30 =
	     sfdin__h141369[4] ? 2'd2 : 2'd0 ;
  assign IF_sfdin4744_BIT_6_THEN_2_ELSE_0__q20 =
	     sfdin__h94744[6] ? 2'd2 : 2'd0 ;
  assign IF_sfdin50423_BIT_4_THEN_2_ELSE_0__q65 =
	     sfdin__h250423[4] ? 2'd2 : 2'd0 ;
  assign IF_sfdin72846_BIT_4_THEN_2_ELSE_0__q38 =
	     sfdin__h172846[4] ? 2'd2 : 2'd0 ;
  assign IF_sfdin77680_BIT_33_THEN_2_ELSE_0__q134 =
	     sfdin__h277680[33] ? 2'd2 : 2'd0 ;
  assign IF_sfdin95446_BIT_33_THEN_2_ELSE_0__q140 =
	     sfdin__h295446[33] ? 2'd2 : 2'd0 ;
  assign IF_theResult___snd01925_BIT_4_THEN_2_ELSE_0__q94 =
	     _theResult___snd__h201925[4] ? 2'd2 : 2'd0 ;
  assign IF_theResult___snd04083_BIT_33_THEN_2_ELSE_0__q143 =
	     _theResult___snd__h304083[33] ? 2'd2 : 2'd0 ;
  assign IF_theResult___snd20237_BIT_4_THEN_2_ELSE_0__q101 =
	     _theResult___snd__h220237[4] ? 2'd2 : 2'd0 ;
  assign IF_theResult___snd40864_BIT_4_THEN_2_ELSE_0__q61 =
	     _theResult___snd__h240864[4] ? 2'd2 : 2'd0 ;
  assign IF_theResult___snd59176_BIT_4_THEN_2_ELSE_0__q68 =
	     _theResult___snd__h259176[4] ? 2'd2 : 2'd0 ;
  assign IF_theResult___snd63287_BIT_4_THEN_2_ELSE_0__q34 =
	     _theResult___snd__h163287[4] ? 2'd2 : 2'd0 ;
  assign IF_theResult___snd81599_BIT_4_THEN_2_ELSE_0__q41 =
	     _theResult___snd__h181599[4] ? 2'd2 : 2'd0 ;
  assign IF_theResult___snd86293_BIT_33_THEN_2_ELSE_0__q136 =
	     _theResult___snd__h286293[33] ? 2'd2 : 2'd0 ;
  assign NOT_3074_MINUS_0_CONCAT_IF_resWire_wget__410_B_ETC___d6728 =
	     !_3074_MINUS_0_CONCAT_IF_resWire_wget__410_BIT_5_ETC___d5532 ||
	     (_3074_MINUS_0_CONCAT_IF_resWire_wget__410_BIT_5_ETC___d5533 ?
		_0_CONCAT_IF_IF_0b0_CONCAT_NOT_resWire_wget__41_ETC___d6676[2] :
		_0_CONCAT_IF_resWire_wget__410_BITS_67_TO_57_41_ETC___d6688[2]) ;
  assign NOT_3074_MINUS_0_CONCAT_IF_resWire_wget__410_B_ETC___d6756 =
	     !_3074_MINUS_0_CONCAT_IF_resWire_wget__410_BIT_5_ETC___d5532 ||
	     (_3074_MINUS_0_CONCAT_IF_resWire_wget__410_BIT_5_ETC___d5533 ?
		_0_CONCAT_IF_IF_0b0_CONCAT_NOT_resWire_wget__41_ETC___d6676[0] :
		_0_CONCAT_IF_resWire_wget__410_BITS_67_TO_57_41_ETC___d6688[0]) ;
  assign NOT_IF_fpu_madd_fOperand_S0_first__803_BIT_195_ETC___d1946 =
	     (x__h96539 != 11'd2047 || !_theResult___fst_sfd__h96608[51]) &&
	     (fpu_madd_fOperand_S0$D_OUT[129:119] != 11'd2047 ||
	      !fpu_madd_fOperand_S0$D_OUT[118]) &&
	     (fpu_madd_fOperand_S0$D_OUT[65:55] != 11'd2047 ||
	      !fpu_madd_fOperand_S0$D_OUT[54]) &&
	     (fpu_madd_fOperand_S0_first__803_BITS_129_TO_11_ETC___d1926 ||
	      IF_fpu_madd_fOperand_S0_first__803_BIT_195_804_ETC___d1927 &&
	      !fpu_madd_fOperand_S0_first__803_BIT_195_804_AN_ETC___d1855) ;
  assign NOT_fpu_div64_fOperands_S0_first__06_BITS_129__ETC___d400 =
	     (fpu_div64_fOperands_S0$D_OUT[129:119] != 11'd2047 ||
	      fpu_div64_fOperands_S0$D_OUT[118:67] != 52'd0 ||
	      fpu_div64_fOperands_S0$D_OUT[65:55] != 11'd2047 ||
	      fpu_div64_fOperands_S0$D_OUT[54:3] != 52'd0) &&
	     (fpu_div64_fOperands_S0$D_OUT[129:119] != 11'd0 ||
	      fpu_div64_fOperands_S0$D_OUT[118:67] != 52'd0 ||
	      fpu_div64_fOperands_S0$D_OUT[65:55] != 11'd0 ||
	      fpu_div64_fOperands_S0$D_OUT[54:3] != 52'd0) ;
  assign NOT_fpu_div64_fOperands_S0_first__06_BITS_129__ETC___d452 =
	     { NOT_fpu_div64_fOperands_S0_first__06_BITS_129__ETC___d400 &&
	       IF_fpu_div64_fOperands_S0_first__06_BITS_65_TO_ETC___d422,
	       IF_fpu_div64_fOperands_S0_first__06_BITS_65_TO_ETC___d433,
	       fpu_div64_fOperands_S0_first__06_BITS_129_TO_1_ETC___d436 ?
		 52'h8000000000000 :
		 IF_fpu_div64_fOperands_S0_first__06_BITS_65_TO_ETC___d450 } ;
  assign NOT_fpu_div64_fOperands_S0_first__06_BITS_65_T_ETC___d481 =
	     (fpu_div64_fOperands_S0$D_OUT[65:55] != 11'd0 ||
	      fpu_div64_fOperands_S0$D_OUT[54:3] != 52'd0) &&
	     (fpu_div64_fOperands_S0$D_OUT[129:119] != 11'd2047 ||
	      fpu_div64_fOperands_S0$D_OUT[118:67] != 52'd0) &&
	     (fpu_div64_fOperands_S0$D_OUT[129:119] != 11'd0 ||
	      fpu_div64_fOperands_S0$D_OUT[118:67] != 52'd0) &&
	     (fpu_div64_fOperands_S0$D_OUT[65:55] != 11'd2047 ||
	      fpu_div64_fOperands_S0$D_OUT[54:3] != 52'd0) &&
	     IF_fpu_div64_fOperands_S0_first__06_BITS_129_T_ETC___d353 &&
	     IF_fpu_div64_fOperands_S0_first__06_BITS_129_T_ETC___d355 ;
  assign NOT_fpu_div64_fOperands_S0_first__06_BITS_65_T_ETC___d488 =
	     (fpu_div64_fOperands_S0$D_OUT[65:55] != 11'd0 ||
	      fpu_div64_fOperands_S0$D_OUT[54:3] != 52'd0) &&
	     (fpu_div64_fOperands_S0$D_OUT[129:119] != 11'd2047 ||
	      fpu_div64_fOperands_S0$D_OUT[118:67] != 52'd0) &&
	     (fpu_div64_fOperands_S0$D_OUT[129:119] != 11'd0 ||
	      fpu_div64_fOperands_S0$D_OUT[118:67] != 52'd0) &&
	     (fpu_div64_fOperands_S0$D_OUT[65:55] != 11'd2047 ||
	      fpu_div64_fOperands_S0$D_OUT[54:3] != 52'd0) &&
	     (!IF_fpu_div64_fOperands_S0_first__06_BITS_129_T_ETC___d353 ||
	      IF_fpu_div64_fOperands_S0_first__06_BITS_129_T_ETC___d355) ;
  assign NOT_fpu_madd_fOperand_S0_first__803_BITS_129_T_ETC___d1923 =
	     (fpu_madd_fOperand_S0$D_OUT[129:119] != 11'd2047 ||
	      fpu_madd_fOperand_S0$D_OUT[118:67] != 52'd0 ||
	      fpu_madd_fOperand_S0$D_OUT[65:55] != 11'd0 ||
	      fpu_madd_fOperand_S0$D_OUT[54:3] != 52'd0) &&
	     (fpu_madd_fOperand_S0$D_OUT[129:119] != 11'd0 ||
	      fpu_madd_fOperand_S0$D_OUT[118:67] != 52'd0 ||
	      fpu_madd_fOperand_S0$D_OUT[65:55] != 11'd2047 ||
	      fpu_madd_fOperand_S0$D_OUT[54:3] != 52'd0) &&
	     (x__h96539 != 11'd2047 ||
	      _theResult___fst_sfd__h96608 != 52'd0 ||
	      (fpu_madd_fOperand_S0$D_OUT[129:119] != 11'd2047 ||
	       fpu_madd_fOperand_S0$D_OUT[118:67] != 52'd0) &&
	      (fpu_madd_fOperand_S0$D_OUT[65:55] != 11'd2047 ||
	       fpu_madd_fOperand_S0$D_OUT[54:3] != 52'd0) ||
	      fpu_madd_fOperand_S0_first__803_BIT_195_804_AN_ETC___d1855) &&
	     IF_IF_fpu_madd_fOperand_S0_first__803_BIT_195__ETC___d1922 ;
  assign NOT_fpu_madd_fOperand_S0_first__803_BIT_130_85_ETC___d1854 =
	     fpu_madd_fOperand_S0$D_OUT[130] !=
	     fpu_madd_fOperand_S0$D_OUT[66] ;
  assign NOT_fpu_madd_fState_S3_first__995_BITS_12_TO_0_ETC___d2510 =
	     !fpu_madd_fState_S3_first__995_BITS_12_TO_0_001_ETC___d2002 ||
	     (fpu_madd_fState_S3_first__995_BITS_12_TO_0_001_ETC___d2004 ?
		fpu_madd_fState_S3$D_OUT[84] :
		fpu_madd_fState_S3_first__995_BITS_86_TO_82_00_ETC___d2501[2]) ;
  assign NOT_fpu_madd_fState_S3_first__995_BITS_12_TO_0_ETC___d2523 =
	     { NOT_fpu_madd_fState_S3_first__995_BITS_12_TO_0_ETC___d2510,
	       fpu_madd_fState_S3_first__995_BITS_12_TO_0_001_ETC___d2002 ?
		 IF_fpu_madd_fState_S3_first__995_BITS_12_TO_0__ETC___d2516 :
		 fpu_madd_fState_S3$D_OUT[83],
	       !fpu_madd_fState_S3_first__995_BITS_12_TO_0_001_ETC___d2002 ||
	       IF_fpu_madd_fState_S3_first__995_BITS_12_TO_0__ETC___d2521 } ;
  assign NOT_fpu_madd_fState_S4_first__547_BIT_130_553__ETC___d2584 =
	     !fpu_madd_fState_S4$D_OUT[130] ||
	     (IF_fpu_madd_fState_S4_first__547_BITS_64_TO_54_ETC___d2563 ^
	      13'h1000) >
	     (IF_fpu_madd_fState_S4_first__547_BITS_128_TO_1_ETC___d2568 ^
	      13'h1000) ||
	     IF_fpu_madd_fState_S4_first__547_BITS_64_TO_54_ETC___d2563 ==
	     IF_fpu_madd_fState_S4_first__547_BITS_128_TO_1_ETC___d2568 &&
	     sfdBC__h131578 > sfdA__h131577 ;
  assign NOT_iFifo_first__087_BIT_158_142_202_AND_NOT_i_ETC___d3244 =
	     !iFifo$D_OUT[158] && !iFifo$D_OUT[157] && !iFifo$D_OUT[156] &&
	     !iFifo$D_OUT[155] &&
	     !iFifo$D_OUT[154] &&
	     !iFifo$D_OUT[153] &&
	     !iFifo$D_OUT[152] &&
	     !iFifo$D_OUT[151] &&
	     !iFifo$D_OUT[150] &&
	     !iFifo$D_OUT[149] &&
	     !iFifo$D_OUT[148] &&
	     !iFifo$D_OUT[147] &&
	     !iFifo$D_OUT[146] &&
	     !iFifo$D_OUT[145] &&
	     !iFifo$D_OUT[144] &&
	     !iFifo$D_OUT[143] &&
	     !iFifo$D_OUT[142] &&
	     !iFifo$D_OUT[141] &&
	     !iFifo$D_OUT[140] &&
	     !iFifo$D_OUT[139] &&
	     !iFifo$D_OUT[138] &&
	     !iFifo$D_OUT[137] ;
  assign NOT_iFifo_first__087_BIT_28_862_913_AND_NOT_iF_ETC___d3955 =
	     !iFifo$D_OUT[28] && !iFifo$D_OUT[27] && !iFifo$D_OUT[26] &&
	     !iFifo$D_OUT[25] &&
	     !iFifo$D_OUT[24] &&
	     !iFifo$D_OUT[23] &&
	     !iFifo$D_OUT[22] &&
	     !iFifo$D_OUT[21] &&
	     !iFifo$D_OUT[20] &&
	     !iFifo$D_OUT[19] &&
	     !iFifo$D_OUT[18] &&
	     !iFifo$D_OUT[17] &&
	     !iFifo$D_OUT[16] &&
	     !iFifo$D_OUT[15] &&
	     !iFifo$D_OUT[14] &&
	     !iFifo$D_OUT[13] &&
	     !iFifo$D_OUT[12] &&
	     !iFifo$D_OUT[11] &&
	     !iFifo$D_OUT[10] &&
	     !iFifo$D_OUT[9] &&
	     !iFifo$D_OUT[8] &&
	     !iFifo$D_OUT[7] ;
  assign NOT_iFifo_first__087_BIT_93_637_688_AND_NOT_iF_ETC___d4730 =
	     !iFifo$D_OUT[93] && !iFifo$D_OUT[92] && !iFifo$D_OUT[91] &&
	     !iFifo$D_OUT[90] &&
	     !iFifo$D_OUT[89] &&
	     !iFifo$D_OUT[88] &&
	     !iFifo$D_OUT[87] &&
	     !iFifo$D_OUT[86] &&
	     !iFifo$D_OUT[85] &&
	     !iFifo$D_OUT[84] &&
	     !iFifo$D_OUT[83] &&
	     !iFifo$D_OUT[82] &&
	     !iFifo$D_OUT[81] &&
	     !iFifo$D_OUT[80] &&
	     !iFifo$D_OUT[79] &&
	     !iFifo$D_OUT[78] &&
	     !iFifo$D_OUT[77] &&
	     !iFifo$D_OUT[76] &&
	     !iFifo$D_OUT[75] &&
	     !iFifo$D_OUT[74] &&
	     !iFifo$D_OUT[73] &&
	     !iFifo$D_OUT[72] ;
  assign NOT_resWire_wget__410_BIT_56_426_825_AND_NOT_r_ETC___d5927 =
	     !resWire$wget[56] && !resWire$wget[55] && !resWire$wget[54] &&
	     !resWire$wget[53] &&
	     !resWire$wget[52] &&
	     !resWire$wget[51] &&
	     !resWire$wget[50] &&
	     !resWire$wget[49] &&
	     !resWire$wget[48] &&
	     !resWire$wget[47] &&
	     !resWire$wget[46] &&
	     !resWire$wget[45] &&
	     !resWire$wget[44] &&
	     !resWire$wget[43] &&
	     !resWire$wget[42] &&
	     !resWire$wget[41] &&
	     !resWire$wget[40] &&
	     !resWire$wget[39] &&
	     !resWire$wget[38] &&
	     !resWire$wget[37] &&
	     !resWire$wget[36] &&
	     !resWire$wget[35] &&
	     !resWire$wget[34] &&
	     !resWire$wget[33] &&
	     !resWire$wget[32] &&
	     !resWire$wget[31] &&
	     !resWire$wget[30] &&
	     !resWire$wget[29] &&
	     !resWire$wget[28] &&
	     !resWire$wget[27] &&
	     !resWire$wget[26] &&
	     !resWire$wget[25] &&
	     !resWire$wget[24] &&
	     !resWire$wget[23] &&
	     !resWire$wget[22] &&
	     !resWire$wget[21] &&
	     !resWire$wget[20] &&
	     !resWire$wget[19] &&
	     !resWire$wget[18] &&
	     !resWire$wget[17] &&
	     !resWire$wget[16] &&
	     !resWire$wget[15] &&
	     !resWire$wget[14] &&
	     !resWire$wget[13] &&
	     !resWire$wget[12] &&
	     !resWire$wget[11] &&
	     !resWire$wget[10] &&
	     !resWire$wget[9] &&
	     !resWire$wget[8] &&
	     !resWire$wget[7] &&
	     !resWire$wget[6] &&
	     !resWire$wget[5] ;
  assign SEXT_iFifo_first__087_BITS_102_TO_95_625_MINUS_ETC___d4806 =
	     { {4{iFifoD_OUT_BITS_102_TO_95_MINUS_127__q95[7]}},
	       iFifoD_OUT_BITS_102_TO_95_MINUS_127__q95 } ;
  assign SEXT_iFifo_first__087_BITS_102_TO_95_625_MINUS_ETC___d4807 =
	     (SEXT_iFifo_first__087_BITS_102_TO_95_625_MINUS_ETC___d4806 ^
	      12'h800) <=
	     12'd3071 ;
  assign SEXT_iFifo_first__087_BITS_102_TO_95_625_MINUS_ETC___d4808 =
	     (SEXT_iFifo_first__087_BITS_102_TO_95_625_MINUS_ETC___d4806 ^
	      12'h800) <
	     12'd1026 ;
  assign SEXT_iFifo_first__087_BITS_102_TO_95_625_MINUS_ETC__q96 =
	     SEXT_iFifo_first__087_BITS_102_TO_95_625_MINUS_ETC___d4806 +
	     12'd1023 ;
  assign SEXT_iFifo_first__087_BITS_102_TO_95_625_MINUS_ETC__q99 =
	     SEXT_iFifo_first__087_BITS_102_TO_95_625_MINUS_ETC__q96[10:0] -
	     11'd1023 ;
  assign SEXT_iFifo_first__087_BITS_167_TO_160_130_MINU_ETC___d3323 =
	     { {4{iFifoD_OUT_BITS_167_TO_160_MINUS_127__q35[7]}},
	       iFifoD_OUT_BITS_167_TO_160_MINUS_127__q35 } ;
  assign SEXT_iFifo_first__087_BITS_167_TO_160_130_MINU_ETC___d3324 =
	     (SEXT_iFifo_first__087_BITS_167_TO_160_130_MINU_ETC___d3323 ^
	      12'h800) <=
	     12'd3071 ;
  assign SEXT_iFifo_first__087_BITS_167_TO_160_130_MINU_ETC___d3325 =
	     (SEXT_iFifo_first__087_BITS_167_TO_160_130_MINU_ETC___d3323 ^
	      12'h800) <
	     12'd1026 ;
  assign SEXT_iFifo_first__087_BITS_167_TO_160_130_MINU_ETC__q36 =
	     SEXT_iFifo_first__087_BITS_167_TO_160_130_MINU_ETC___d3323 +
	     12'd1023 ;
  assign SEXT_iFifo_first__087_BITS_167_TO_160_130_MINU_ETC__q39 =
	     SEXT_iFifo_first__087_BITS_167_TO_160_130_MINU_ETC__q36[10:0] -
	     11'd1023 ;
  assign SEXT_iFifo_first__087_BITS_37_TO_30_850_MINUS__ETC___d4031 =
	     { {4{iFifoD_OUT_BITS_37_TO_30_MINUS_127__q62[7]}},
	       iFifoD_OUT_BITS_37_TO_30_MINUS_127__q62 } ;
  assign SEXT_iFifo_first__087_BITS_37_TO_30_850_MINUS__ETC___d4032 =
	     (SEXT_iFifo_first__087_BITS_37_TO_30_850_MINUS__ETC___d4031 ^
	      12'h800) <=
	     12'd3071 ;
  assign SEXT_iFifo_first__087_BITS_37_TO_30_850_MINUS__ETC___d4033 =
	     (SEXT_iFifo_first__087_BITS_37_TO_30_850_MINUS__ETC___d4031 ^
	      12'h800) <
	     12'd1026 ;
  assign SEXT_iFifo_first__087_BITS_37_TO_30_850_MINUS__ETC__q63 =
	     SEXT_iFifo_first__087_BITS_37_TO_30_850_MINUS__ETC___d4031 +
	     12'd1023 ;
  assign SEXT_iFifo_first__087_BITS_37_TO_30_850_MINUS__ETC__q66 =
	     SEXT_iFifo_first__087_BITS_37_TO_30_850_MINUS__ETC__q63[10:0] -
	     11'd1023 ;
  assign SEXT_resWire_wget__410_BITS_67_TO_57_416_MINUS_ETC___d6031 =
	     { resWirewget_BITS_67_TO_57_MINUS_1023__q137[10],
	       resWirewget_BITS_67_TO_57_MINUS_1023__q137 } ;
  assign SEXT_resWire_wget__410_BITS_67_TO_57_416_MINUS_ETC___d6032 =
	     (SEXT_resWire_wget__410_BITS_67_TO_57_416_MINUS_ETC___d6031 ^
	      12'h800) <=
	     12'd2175 ;
  assign SEXT_resWire_wget__410_BITS_67_TO_57_416_MINUS_ETC___d6033 =
	     (SEXT_resWire_wget__410_BITS_67_TO_57_416_MINUS_ETC___d6031 ^
	      12'h800) <
	     12'd1922 ;
  assign SEXT_resWire_wget__410_BITS_67_TO_57_416_MINUS_ETC__q138 =
	     SEXT_resWire_wget__410_BITS_67_TO_57_416_MINUS_ETC___d6031 +
	     12'd127 ;
  assign SEXT_resWire_wget__410_BITS_67_TO_57_416_MINUS_ETC__q141 =
	     SEXT_resWire_wget__410_BITS_67_TO_57_416_MINUS_ETC__q138[7:0] -
	     8'd127 ;
  assign _0_CONCAT_IF_IF_0b0_CONCAT_NOT_resWire_wget__41_ETC___d5769 =
	     ({ 3'd0,
		IF_IF_0b0_CONCAT_NOT_resWire_wget__410_BITS_67_ETC___d5767 } ^
	      9'h100) <=
	     9'd256 ;
  assign _0_CONCAT_IF_IF_0b0_CONCAT_NOT_resWire_wget__41_ETC___d6676 =
	     { 3'd0,
	       _theResult___fst_exp__h277686 == 8'd0 &&
	       (sfdin__h277680[56:34] == 23'd0 || guard__h269587 != 2'b0),
	       1'd0 } |
	     { 2'd0,
	       _theResult___fst_exp__h278283 == 8'd255 &&
	       _theResult___fst_sfd__h278284 == 23'd0,
	       1'd0,
	       _theResult___fst_exp__h277686 != 8'd255 &&
	       guard__h269587 != 2'b0 } ;
  assign _0_CONCAT_IF_IF_3074_MINUS_SEXT_iFifo_first__08_ETC___d3574 =
	     ({ 6'd0,
		IF_IF_3074_MINUS_SEXT_iFifo_first__087_BITS_16_ETC___d3572 } ^
	      12'h800) <=
	     12'd2048 ;
  assign _0_CONCAT_IF_IF_3074_MINUS_SEXT_iFifo_first__08_ETC___d4282 =
	     ({ 6'd0,
		IF_IF_3074_MINUS_SEXT_iFifo_first__087_BITS_37_ETC___d4280 } ^
	      12'h800) <=
	     12'd2048 ;
  assign _0_CONCAT_IF_IF_3074_MINUS_SEXT_iFifo_first__08_ETC___d5057 =
	     ({ 6'd0,
		IF_IF_3074_MINUS_SEXT_iFifo_first__087_BITS_10_ETC___d5055 } ^
	      12'h800) <=
	     12'd2048 ;
  assign _0_CONCAT_IF_IF_3970_MINUS_SEXT_resWire_wget__4_ETC___d6280 =
	     ({ 3'd0,
		IF_IF_3970_MINUS_SEXT_resWire_wget__410_BITS_6_ETC___d6278 } ^
	      9'h100) <=
	     9'd256 ;
  assign _0_CONCAT_IF_IF_3970_MINUS_SEXT_resWire_wget__4_ETC___d6705 =
	     { 3'd0,
	       _theResult___fst_exp__h295452 == 8'd0 &&
	       (sfdin__h295446[56:34] == 23'd0 || guard__h287224 != 2'b0),
	       1'd0 } |
	     { 2'd0,
	       _theResult___fst_exp__h296049 == 8'd255 &&
	       _theResult___fst_sfd__h296050 == 23'd0,
	       1'd0,
	       _theResult___fst_exp__h295452 != 8'd255 &&
	       guard__h287224 != 2'b0 } ;
  assign _0_CONCAT_IF_IF_7170_MINUS_fpu_madd_fState_S3_f_ETC___d2463 =
	     ({ 5'd0,
		IF_IF_7170_MINUS_fpu_madd_fState_S3_first__995_ETC___d2460 } ^
	      12'h800) <=
	     (IF_IF_7170_MINUS_fpu_madd_fState_S3_first__995_ETC___d2462 ^
	      12'h800) ;
  assign _0_CONCAT_IF_IF_fpu_div64_fState_S3_first__86_B_ETC___d883 =
	     ({ 6'd0,
		IF_IF_fpu_div64_fState_S3_first__86_BITS_120_T_ETC___d880 } ^
	      12'h800) <=
	     (IF_IF_fpu_div64_fState_S3_first__86_BITS_120_T_ETC___d882 ^
	      12'h800) ;
  assign _0_CONCAT_IF_IF_fpu_madd_fState_S7_first__651_B_ETC___d2904 =
	     ({ 6'd0,
		IF_IF_fpu_madd_fState_S7_first__651_BIT_128_65_ETC___d2901 } ^
	      12'h800) <=
	     (IF_fpu_madd_fState_S7_first__651_BITS_126_TO_1_ETC___d2903 ^
	      12'h800) ;
  assign _0_CONCAT_IF_fpu_sqr64_fState_S3_first__375_BIT_ETC___d1633 =
	     ({ 6'd0,
		IF_fpu_sqr64_fState_S3_first__375_BIT_58_384_T_ETC___d1630 } ^
	      12'h800) <=
	     (IF_fpu_sqr64_fState_S3_first__375_BITS_121_TO__ETC___d1632 ^
	      12'h800) ;
  assign _0_CONCAT_IF_iFifo_first__087_BITS_102_TO_95_62_ETC___d4759 =
	     ({ 6'd0,
		IF_iFifo_first__087_BITS_102_TO_95_625_EQ_0_63_ETC___d4757 } ^
	      12'h800) <=
	     12'd2944 ;
  assign _0_CONCAT_IF_iFifo_first__087_BITS_102_TO_95_62_ETC___d5107 =
	     ({ 6'd0,
		IF_iFifo_first__087_BITS_102_TO_95_625_EQ_0_63_ETC___d4757 } ^
	      12'h800) <=
	     (IF_SEXT_iFifo_first__087_BITS_102_TO_95_625_MI_ETC___d5106 ^
	      12'h800) ;
  assign _0_CONCAT_IF_iFifo_first__087_BITS_167_TO_160_1_ETC___d3273 =
	     ({ 6'd0,
		IF_iFifo_first__087_BITS_167_TO_160_130_EQ_0_1_ETC___d3271 } ^
	      12'h800) <=
	     12'd2944 ;
  assign _0_CONCAT_IF_iFifo_first__087_BITS_167_TO_160_1_ETC___d3624 =
	     ({ 6'd0,
		IF_iFifo_first__087_BITS_167_TO_160_130_EQ_0_1_ETC___d3271 } ^
	      12'h800) <=
	     (IF_SEXT_iFifo_first__087_BITS_167_TO_160_130_M_ETC___d3623 ^
	      12'h800) ;
  assign _0_CONCAT_IF_iFifo_first__087_BITS_37_TO_30_850_ETC___d3984 =
	     ({ 6'd0,
		IF_iFifo_first__087_BITS_37_TO_30_850_EQ_0_856_ETC___d3982 } ^
	      12'h800) <=
	     12'd2944 ;
  assign _0_CONCAT_IF_iFifo_first__087_BITS_37_TO_30_850_ETC___d4332 =
	     ({ 6'd0,
		IF_iFifo_first__087_BITS_37_TO_30_850_EQ_0_856_ETC___d3982 } ^
	      12'h800) <=
	     (IF_SEXT_iFifo_first__087_BITS_37_TO_30_850_MIN_ETC___d4331 ^
	      12'h800) ;
  assign _0_CONCAT_IF_resWire_wget__410_BITS_67_TO_57_41_ETC___d5984 =
	     ({ 3'd0,
		IF_resWire_wget__410_BITS_67_TO_57_416_EQ_0_42_ETC___d5982 } ^
	      9'h100) <=
	     9'd384 ;
  assign _0_CONCAT_IF_resWire_wget__410_BITS_67_TO_57_41_ETC___d6333 =
	     ({ 3'd0,
		IF_resWire_wget__410_BITS_67_TO_57_416_EQ_0_42_ETC___d5982 } ^
	      9'h100) <=
	     (IF_SEXT_resWire_wget__410_BITS_67_TO_57_416_MI_ETC___d6332 ^
	      9'h100) ;
  assign _0_CONCAT_IF_resWire_wget__410_BITS_67_TO_57_41_ETC___d6688 =
	     { 3'd0,
	       _theResult___fst_exp__h286342 == 8'd0 &&
	       guard__h278294 != 2'b0,
	       1'd0 } |
	     { 2'd0,
	       _theResult___fst_exp__h286865 == 8'd255 &&
	       _theResult___fst_sfd__h286866 == 23'd0,
	       1'd0,
	       _theResult___fst_exp__h286342 != 8'd255 &&
	       guard__h278294 != 2'b0 } ;
  assign _0b0_CONCAT_NOT_iFifo_first__087_BITS_102_TO_95_ETC___d4813 =
	     sfd__h183176 >>
	     _3074_MINUS_SEXT_iFifo_first__087_BITS_102_TO_9_ETC___d4809 ;
  assign _0b0_CONCAT_NOT_iFifo_first__087_BITS_167_TO_16_ETC___d3330 =
	     sfd__h144536 >>
	     _3074_MINUS_SEXT_iFifo_first__087_BITS_167_TO_1_ETC___d3326 ;
  assign _0b0_CONCAT_NOT_iFifo_first__087_BITS_37_TO_30__ETC___d4038 =
	     sfd__h222115 >>
	     _3074_MINUS_SEXT_iFifo_first__087_BITS_37_TO_30_ETC___d4034 ;
  assign _0b0_CONCAT_NOT_resWire_wget__410_BITS_67_TO_57_ETC___d6038 =
	     sfd__h261975 >>
	     _3970_MINUS_SEXT_resWire_wget__410_BITS_67_TO_5_ETC___d6034 ;
  assign _3074_MINUS_0_CONCAT_IF_resWire_wget__410_BIT_5_ETC___d5531 =
	     12'd3074 -
	     { 6'd0,
	       resWire$wget[56] ?
		 6'd0 :
		 (resWire$wget[55] ?
		    6'd1 :
		    (resWire$wget[54] ?
		       6'd2 :
		       (resWire$wget[53] ?
			  6'd3 :
			  (resWire$wget[52] ?
			     6'd4 :
			     (resWire$wget[51] ?
				6'd5 :
				(resWire$wget[50] ?
				   6'd6 :
				   (resWire$wget[49] ?
				      6'd7 :
				      (resWire$wget[48] ?
					 6'd8 :
					 (resWire$wget[47] ?
					    6'd9 :
					    (resWire$wget[46] ?
					       6'd10 :
					       (resWire$wget[45] ?
						  6'd11 :
						  (resWire$wget[44] ?
						     6'd12 :
						     (resWire$wget[43] ?
							6'd13 :
							(resWire$wget[42] ?
							   6'd14 :
							   (resWire$wget[41] ?
							      6'd15 :
							      (resWire$wget[40] ?
								 6'd16 :
								 (resWire$wget[39] ?
								    6'd17 :
								    (resWire$wget[38] ?
								       6'd18 :
								       (resWire$wget[37] ?
									  6'd19 :
									  (resWire$wget[36] ?
									     6'd20 :
									     (resWire$wget[35] ?
										6'd21 :
										(resWire$wget[34] ?
										   6'd22 :
										   (resWire$wget[33] ?
										      6'd23 :
										      (resWire$wget[32] ?
											 6'd24 :
											 (resWire$wget[31] ?
											    6'd25 :
											    (resWire$wget[30] ?
											       6'd26 :
											       (resWire$wget[29] ?
												  6'd27 :
												  (resWire$wget[28] ?
												     6'd28 :
												     (resWire$wget[27] ?
													6'd29 :
													(resWire$wget[26] ?
													   6'd30 :
													   (resWire$wget[25] ?
													      6'd31 :
													      (resWire$wget[24] ?
														 6'd32 :
														 (resWire$wget[23] ?
														    6'd33 :
														    (resWire$wget[22] ?
														       6'd34 :
														       (resWire$wget[21] ?
															  6'd35 :
															  (resWire$wget[20] ?
															     6'd36 :
															     (resWire$wget[19] ?
																6'd37 :
																(resWire$wget[18] ?
																   6'd38 :
																   (resWire$wget[17] ?
																      6'd39 :
																      (resWire$wget[16] ?
																	 6'd40 :
																	 (resWire$wget[15] ?
																	    6'd41 :
																	    (resWire$wget[14] ?
																	       6'd42 :
																	       (resWire$wget[13] ?
																		  6'd43 :
																		  (resWire$wget[12] ?
																		     6'd44 :
																		     (resWire$wget[11] ?
																			6'd45 :
																			(resWire$wget[10] ?
																			   6'd46 :
																			   (resWire$wget[9] ?
																			      6'd47 :
																			      (resWire$wget[8] ?
																				 6'd48 :
																				 (resWire$wget[7] ?
																				    6'd49 :
																				    (resWire$wget[6] ?
																				       6'd50 :
																				       (resWire$wget[5] ?
																					  6'd51 :
																					  6'd52))))))))))))))))))))))))))))))))))))))))))))))))))) } ;
  assign _3074_MINUS_0_CONCAT_IF_resWire_wget__410_BIT_5_ETC___d5532 =
	     (_3074_MINUS_0_CONCAT_IF_resWire_wget__410_BIT_5_ETC___d5531 ^
	      12'h800) <=
	     12'd2175 ;
  assign _3074_MINUS_0_CONCAT_IF_resWire_wget__410_BIT_5_ETC___d5533 =
	     (_3074_MINUS_0_CONCAT_IF_resWire_wget__410_BIT_5_ETC___d5531 ^
	      12'h800) <
	     12'd1922 ;
  assign _3074_MINUS_0_CONCAT_IF_resWire_wget__410_BIT_5_ETC___d6691 =
	     _3074_MINUS_0_CONCAT_IF_resWire_wget__410_BIT_5_ETC___d5532 &&
	     (_3074_MINUS_0_CONCAT_IF_resWire_wget__410_BIT_5_ETC___d5533 ?
		_0_CONCAT_IF_IF_0b0_CONCAT_NOT_resWire_wget__41_ETC___d6676[4] :
		_0_CONCAT_IF_resWire_wget__410_BITS_67_TO_57_41_ETC___d6688[4]) ;
  assign _3074_MINUS_0_CONCAT_IF_resWire_wget__410_BIT_5_ETC___d6716 =
	     _3074_MINUS_0_CONCAT_IF_resWire_wget__410_BIT_5_ETC___d5532 &&
	     (_3074_MINUS_0_CONCAT_IF_resWire_wget__410_BIT_5_ETC___d5533 ?
		_0_CONCAT_IF_IF_0b0_CONCAT_NOT_resWire_wget__41_ETC___d6676[3] :
		_0_CONCAT_IF_resWire_wget__410_BITS_67_TO_57_41_ETC___d6688[3]) ;
  assign _3074_MINUS_0_CONCAT_IF_resWire_wget__410_BIT_5_ETC___d6743 =
	     _3074_MINUS_0_CONCAT_IF_resWire_wget__410_BIT_5_ETC___d5532 &&
	     (_3074_MINUS_0_CONCAT_IF_resWire_wget__410_BIT_5_ETC___d5533 ?
		_0_CONCAT_IF_IF_0b0_CONCAT_NOT_resWire_wget__41_ETC___d6676[1] :
		_0_CONCAT_IF_resWire_wget__410_BITS_67_TO_57_41_ETC___d6688[1]) ;
  assign _3074_MINUS_SEXT_iFifo_first__087_BITS_102_TO_9_ETC___d4809 =
	     12'd3074 -
	     SEXT_iFifo_first__087_BITS_102_TO_95_625_MINUS_ETC___d4806 ;
  assign _3074_MINUS_SEXT_iFifo_first__087_BITS_167_TO_1_ETC___d3326 =
	     12'd3074 -
	     SEXT_iFifo_first__087_BITS_167_TO_160_130_MINU_ETC___d3323 ;
  assign _3074_MINUS_SEXT_iFifo_first__087_BITS_37_TO_30_ETC___d4034 =
	     12'd3074 -
	     SEXT_iFifo_first__087_BITS_37_TO_30_850_MINUS__ETC___d4031 ;
  assign _3970_MINUS_0_CONCAT_IF_iFifo_first__087_BIT_15_ETC___d3188 =
	     12'd3970 -
	     { 7'd0,
	       iFifo$D_OUT[159] ?
		 5'd0 :
		 (iFifo$D_OUT[158] ?
		    5'd1 :
		    (iFifo$D_OUT[157] ?
		       5'd2 :
		       (iFifo$D_OUT[156] ?
			  5'd3 :
			  (iFifo$D_OUT[155] ?
			     5'd4 :
			     (iFifo$D_OUT[154] ?
				5'd5 :
				(iFifo$D_OUT[153] ?
				   5'd6 :
				   (iFifo$D_OUT[152] ?
				      5'd7 :
				      (iFifo$D_OUT[151] ?
					 5'd8 :
					 (iFifo$D_OUT[150] ?
					    5'd9 :
					    (iFifo$D_OUT[149] ?
					       5'd10 :
					       (iFifo$D_OUT[148] ?
						  5'd11 :
						  (iFifo$D_OUT[147] ?
						     5'd12 :
						     (iFifo$D_OUT[146] ?
							5'd13 :
							(iFifo$D_OUT[145] ?
							   5'd14 :
							   (iFifo$D_OUT[144] ?
							      5'd15 :
							      (iFifo$D_OUT[143] ?
								 5'd16 :
								 (iFifo$D_OUT[142] ?
								    5'd17 :
								    (iFifo$D_OUT[141] ?
								       5'd18 :
								       (iFifo$D_OUT[140] ?
									  5'd19 :
									  (iFifo$D_OUT[139] ?
									     5'd20 :
									     (iFifo$D_OUT[138] ?
										5'd21 :
										(iFifo$D_OUT[137] ?
										   5'd22 :
										   5'd23)))))))))))))))))))))) } ;
  assign _3970_MINUS_0_CONCAT_IF_iFifo_first__087_BIT_15_ETC___d3189 =
	     (_3970_MINUS_0_CONCAT_IF_iFifo_first__087_BIT_15_ETC___d3188 ^
	      12'h800) <=
	     12'd3071 ;
  assign _3970_MINUS_0_CONCAT_IF_iFifo_first__087_BIT_15_ETC___d3190 =
	     (_3970_MINUS_0_CONCAT_IF_iFifo_first__087_BIT_15_ETC___d3188 ^
	      12'h800) <
	     12'd1026 ;
  assign _3970_MINUS_0_CONCAT_IF_iFifo_first__087_BIT_29_ETC___d3908 =
	     12'd3970 -
	     { 7'd0,
	       iFifo$D_OUT[29] ?
		 5'd0 :
		 (iFifo$D_OUT[28] ?
		    5'd1 :
		    (iFifo$D_OUT[27] ?
		       5'd2 :
		       (iFifo$D_OUT[26] ?
			  5'd3 :
			  (iFifo$D_OUT[25] ?
			     5'd4 :
			     (iFifo$D_OUT[24] ?
				5'd5 :
				(iFifo$D_OUT[23] ?
				   5'd6 :
				   (iFifo$D_OUT[22] ?
				      5'd7 :
				      (iFifo$D_OUT[21] ?
					 5'd8 :
					 (iFifo$D_OUT[20] ?
					    5'd9 :
					    (iFifo$D_OUT[19] ?
					       5'd10 :
					       (iFifo$D_OUT[18] ?
						  5'd11 :
						  (iFifo$D_OUT[17] ?
						     5'd12 :
						     (iFifo$D_OUT[16] ?
							5'd13 :
							(iFifo$D_OUT[15] ?
							   5'd14 :
							   (iFifo$D_OUT[14] ?
							      5'd15 :
							      (iFifo$D_OUT[13] ?
								 5'd16 :
								 (iFifo$D_OUT[12] ?
								    5'd17 :
								    (iFifo$D_OUT[11] ?
								       5'd18 :
								       (iFifo$D_OUT[10] ?
									  5'd19 :
									  (iFifo$D_OUT[9] ?
									     5'd20 :
									     (iFifo$D_OUT[8] ?
										5'd21 :
										(iFifo$D_OUT[7] ?
										   5'd22 :
										   5'd23)))))))))))))))))))))) } ;
  assign _3970_MINUS_0_CONCAT_IF_iFifo_first__087_BIT_29_ETC___d3909 =
	     (_3970_MINUS_0_CONCAT_IF_iFifo_first__087_BIT_29_ETC___d3908 ^
	      12'h800) <=
	     12'd3071 ;
  assign _3970_MINUS_0_CONCAT_IF_iFifo_first__087_BIT_29_ETC___d3910 =
	     (_3970_MINUS_0_CONCAT_IF_iFifo_first__087_BIT_29_ETC___d3908 ^
	      12'h800) <
	     12'd1026 ;
  assign _3970_MINUS_0_CONCAT_IF_iFifo_first__087_BIT_94_ETC___d4683 =
	     12'd3970 -
	     { 7'd0,
	       iFifo$D_OUT[94] ?
		 5'd0 :
		 (iFifo$D_OUT[93] ?
		    5'd1 :
		    (iFifo$D_OUT[92] ?
		       5'd2 :
		       (iFifo$D_OUT[91] ?
			  5'd3 :
			  (iFifo$D_OUT[90] ?
			     5'd4 :
			     (iFifo$D_OUT[89] ?
				5'd5 :
				(iFifo$D_OUT[88] ?
				   5'd6 :
				   (iFifo$D_OUT[87] ?
				      5'd7 :
				      (iFifo$D_OUT[86] ?
					 5'd8 :
					 (iFifo$D_OUT[85] ?
					    5'd9 :
					    (iFifo$D_OUT[84] ?
					       5'd10 :
					       (iFifo$D_OUT[83] ?
						  5'd11 :
						  (iFifo$D_OUT[82] ?
						     5'd12 :
						     (iFifo$D_OUT[81] ?
							5'd13 :
							(iFifo$D_OUT[80] ?
							   5'd14 :
							   (iFifo$D_OUT[79] ?
							      5'd15 :
							      (iFifo$D_OUT[78] ?
								 5'd16 :
								 (iFifo$D_OUT[77] ?
								    5'd17 :
								    (iFifo$D_OUT[76] ?
								       5'd18 :
								       (iFifo$D_OUT[75] ?
									  5'd19 :
									  (iFifo$D_OUT[74] ?
									     5'd20 :
									     (iFifo$D_OUT[73] ?
										5'd21 :
										(iFifo$D_OUT[72] ?
										   5'd22 :
										   5'd23)))))))))))))))))))))) } ;
  assign _3970_MINUS_0_CONCAT_IF_iFifo_first__087_BIT_94_ETC___d4684 =
	     (_3970_MINUS_0_CONCAT_IF_iFifo_first__087_BIT_94_ETC___d4683 ^
	      12'h800) <=
	     12'd3071 ;
  assign _3970_MINUS_0_CONCAT_IF_iFifo_first__087_BIT_94_ETC___d4685 =
	     (_3970_MINUS_0_CONCAT_IF_iFifo_first__087_BIT_94_ETC___d4683 ^
	      12'h800) <
	     12'd1026 ;
  assign _3970_MINUS_SEXT_resWire_wget__410_BITS_67_TO_5_ETC___d6034 =
	     12'd3970 -
	     SEXT_resWire_wget__410_BITS_67_TO_57_416_MINUS_ETC___d6031 ;
  assign _7170_MINUS_fpu_madd_fState_S3_first__995_BITS__ETC___d2007 =
	     13'd7170 - fpu_madd_fState_S3$D_OUT[12:0] ;
  assign _7170_MINUS_fpu_madd_fState_S3_first__995_BITS__ETC___d2008 =
	     (_7170_MINUS_fpu_madd_fState_S3_first__995_BITS__ETC___d2007 ^
	      13'h1000) <=
	     13'd4096 ;
  assign _theResult____h164614 =
	     ((_3074_MINUS_SEXT_iFifo_first__087_BITS_167_TO_1_ETC___d3326 ^
	       12'h800) <
	      12'd2105) ?
	       result__h165227 :
	       ((value__h148923 == 25'd0) ? sfd__h144536 : 57'd1) ;
  assign _theResult____h203252 =
	     ((_3074_MINUS_SEXT_iFifo_first__087_BITS_102_TO_9_ETC___d4809 ^
	       12'h800) <
	      12'd2105) ?
	       result__h203865 :
	       ((value__h187561 == 25'd0) ? sfd__h183176 : 57'd1) ;
  assign _theResult____h242191 =
	     ((_3074_MINUS_SEXT_iFifo_first__087_BITS_37_TO_30_ETC___d4034 ^
	       12'h800) <
	      12'd2105) ?
	       result__h242804 :
	       ((value__h226500 == 25'd0) ? sfd__h222115 : 57'd1) ;
  assign _theResult____h269577 =
	     (value__h270197 == 54'd0) ? sfd__h261975 : 57'd1 ;
  assign _theResult____h287214 =
	     ((_3970_MINUS_SEXT_resWire_wget__410_BITS_67_TO_5_ETC___d6034 ^
	       12'h800) <
	      12'd2105) ?
	       result__h287827 :
	       _theResult____h269577 ;
  assign _theResult____h32523 =
	     (fpu_div64_fState_S2$D_OUT[10:0] < 11'd58) ?
	       result__h32648 :
	       result__h32823 ;
  assign _theResult___exp__h142541 =
	     sfd__h142040[53] ?
	       ((fpu_madd_fState_S8$D_OUT[65:55] == 11'd2046) ?
		  11'd2047 :
		  din_inc___2_exp__h142626) :
	       IF_fpu_madd_fState_S8_first__960_BITS_65_TO_55_ETC___d2986 ;
  assign _theResult___exp__h163981 =
	     sfd__h163354[53] ?
	       ((_theResult___fst_exp__h163336 == 11'd2046) ?
		  11'd2047 :
		  din_inc___2_exp__h182469) :
	       ((_theResult___fst_exp__h163336 == 11'd0 &&
		 sfd__h163354[53:52] == 2'b01) ?
		  11'd1 :
		  _theResult___fst_exp__h163336) ;
  assign _theResult___exp__h173571 =
	     sfd__h172944[53] ?
	       ((_theResult___fst_exp__h172852 == 11'd2046) ?
		  11'd2047 :
		  din_inc___2_exp__h182504) :
	       ((_theResult___fst_exp__h172852 == 11'd0 &&
		 sfd__h172944[53:52] == 2'b01) ?
		  11'd1 :
		  _theResult___fst_exp__h172852) ;
  assign _theResult___exp__h182323 =
	     sfd__h181672[53] ?
	       ((_theResult___fst_exp__h181653 == 11'd2046) ?
		  11'd2047 :
		  din_inc___2_exp__h182530) :
	       ((_theResult___fst_exp__h181653 == 11'd0 &&
		 sfd__h181672[53:52] == 2'b01) ?
		  11'd1 :
		  _theResult___fst_exp__h181653) ;
  assign _theResult___exp__h202619 =
	     sfd__h201992[53] ?
	       ((_theResult___fst_exp__h201974 == 11'd2046) ?
		  11'd2047 :
		  din_inc___2_exp__h221107) :
	       ((_theResult___fst_exp__h201974 == 11'd0 &&
		 sfd__h201992[53:52] == 2'b01) ?
		  11'd1 :
		  _theResult___fst_exp__h201974) ;
  assign _theResult___exp__h212209 =
	     sfd__h211582[53] ?
	       ((_theResult___fst_exp__h211490 == 11'd2046) ?
		  11'd2047 :
		  din_inc___2_exp__h221142) :
	       ((_theResult___fst_exp__h211490 == 11'd0 &&
		 sfd__h211582[53:52] == 2'b01) ?
		  11'd1 :
		  _theResult___fst_exp__h211490) ;
  assign _theResult___exp__h220961 =
	     sfd__h220310[53] ?
	       ((_theResult___fst_exp__h220291 == 11'd2046) ?
		  11'd2047 :
		  din_inc___2_exp__h221168) :
	       ((_theResult___fst_exp__h220291 == 11'd0 &&
		 sfd__h220310[53:52] == 2'b01) ?
		  11'd1 :
		  _theResult___fst_exp__h220291) ;
  assign _theResult___exp__h241558 =
	     sfd__h240931[53] ?
	       ((_theResult___fst_exp__h240913 == 11'd2046) ?
		  11'd2047 :
		  din_inc___2_exp__h260046) :
	       ((_theResult___fst_exp__h240913 == 11'd0 &&
		 sfd__h240931[53:52] == 2'b01) ?
		  11'd1 :
		  _theResult___fst_exp__h240913) ;
  assign _theResult___exp__h251148 =
	     sfd__h250521[53] ?
	       ((_theResult___fst_exp__h250429 == 11'd2046) ?
		  11'd2047 :
		  din_inc___2_exp__h260081) :
	       ((_theResult___fst_exp__h250429 == 11'd0 &&
		 sfd__h250521[53:52] == 2'b01) ?
		  11'd1 :
		  _theResult___fst_exp__h250429) ;
  assign _theResult___exp__h259900 =
	     sfd__h259249[53] ?
	       ((_theResult___fst_exp__h259230 == 11'd2046) ?
		  11'd2047 :
		  din_inc___2_exp__h260107) :
	       ((_theResult___fst_exp__h259230 == 11'd0 &&
		 sfd__h259249[53:52] == 2'b01) ?
		  11'd1 :
		  _theResult___fst_exp__h259230) ;
  assign _theResult___exp__h278202 =
	     sfd__h277778[24] ?
	       ((_theResult___fst_exp__h277686 == 8'd254) ?
		  8'd255 :
		  din_inc___2_exp__h304723) :
	       ((_theResult___fst_exp__h277686 == 8'd0 &&
		 sfd__h277778[24:23] == 2'b01) ?
		  8'd1 :
		  _theResult___fst_exp__h277686) ;
  assign _theResult___exp__h286784 =
	     sfd__h286360[24] ?
	       ((_theResult___fst_exp__h286342 == 8'd254) ?
		  8'd255 :
		  din_inc___2_exp__h304749) :
	       ((_theResult___fst_exp__h286342 == 8'd0 &&
		 sfd__h286360[24:23] == 2'b01) ?
		  8'd1 :
		  _theResult___fst_exp__h286342) ;
  assign _theResult___exp__h295968 =
	     sfd__h295544[24] ?
	       ((_theResult___fst_exp__h295452 == 8'd254) ?
		  8'd255 :
		  din_inc___2_exp__h304784) :
	       ((_theResult___fst_exp__h295452 == 8'd0 &&
		 sfd__h295544[24:23] == 2'b01) ?
		  8'd1 :
		  _theResult___fst_exp__h295452) ;
  assign _theResult___exp__h304604 =
	     sfd__h304156[24] ?
	       ((_theResult___fst_exp__h304137 == 8'd254) ?
		  8'd255 :
		  din_inc___2_exp__h304810) :
	       ((_theResult___fst_exp__h304137 == 8'd0 &&
		 sfd__h304156[24:23] == 2'b01) ?
		  8'd1 :
		  _theResult___fst_exp__h304137) ;
  assign _theResult___exp__h43475 =
	     sfd__h42982[53] ?
	       ((fpu_div64_fState_S4$D_OUT[64:54] == 11'd2046) ?
		  11'd2047 :
		  din_inc___2_exp__h43566) :
	       IF_fpu_div64_fState_S4_first__43_BITS_64_TO_54_ETC___d977 ;
  assign _theResult___exp__h95909 =
	     sfd__h95416[53] ?
	       ((fpu_sqr64_fState_S4$D_OUT[64:54] == 11'd2046) ?
		  11'd2047 :
		  din_inc___2_exp__h96000) :
	       IF_fpu_sqr64_fState_S4_first__687_BITS_64_TO_5_ETC___d1721 ;
  assign _theResult___fst__h116827 =
	     { fpu_madd_fProd_S3_first__009_SRL_IF_7170_MINUS_ETC___d2012[105:1],
	       fpu_madd_fProd_S3_first__009_SRL_IF_7170_MINUS_ETC___d2012[0] |
	       sfdlsb__h116825 } ;
  assign _theResult___fst__h1476 =
	     IF_rg_index_1_4_ULE_58_8_THEN_NOT_rg_b_9_EQ_0__ETC___d56 ?
	       _theResult___fst__h1600 :
	       IF_rg_index_1_4_ULE_58_8_THEN_IF_rg_res_1_BIT__ETC___d49 ;
  assign _theResult___fst__h1515 =
	     (rg_res[116] || rg_b == 116'd0) ? rg_b : b__h1608 ;
  assign _theResult___fst__h1600 =
	     (IF_rg_index_1_4_ULE_58_8_THEN_IF_rg_res_1_BIT__ETC___d49 ==
	      116'd0) ?
	       IF_rg_index_1_4_ULE_58_8_THEN_IF_rg_res_1_BIT__ETC___d49 :
	       b__h1712 ;
  assign _theResult___fst__h31322 =
	     IF_fpu_div64_fOperands_S0_first__06_BITS_129_T_ETC___d499 ?
	       value__h31550[10:0] :
	       11'd0 ;
  assign _theResult___fst_exp__h130949 =
	     sfdBC__h115662[105] ?
	       _theResult___fst_exp__h130971 :
	       _theResult___fst_exp__h131034 ;
  assign _theResult___fst_exp__h130952 =
	     (sfdBC__h115662[105] &&
	      IF_IF_7170_MINUS_fpu_madd_fState_S3_first__995_ETC___d2031 ==
	      12'd1023) ?
	       11'd2046 :
	       _theResult___fst_exp__h130949 ;
  assign _theResult___fst_exp__h130971 =
	     (din_exp__h130866 == 11'd0) ? 11'd2 : din_exp__h130866 + 11'd1 ;
  assign _theResult___fst_exp__h130986 =
	     (din_exp__h130866 == 11'd0) ? 11'd1 : din_exp__h130866 ;
  assign _theResult___fst_exp__h131025 =
	     din_exp__h130866 -
	     { 4'd0,
	       IF_IF_7170_MINUS_fpu_madd_fState_S3_first__995_ETC___d2460 } ;
  assign _theResult___fst_exp__h131031 =
	     (!sfdBC__h115662[105] && !sfdBC__h115662[104] &&
	      !sfdBC__h115662[103] &&
	      !sfdBC__h115662[102] &&
	      !sfdBC__h115662[101] &&
	      !sfdBC__h115662[100] &&
	      !sfdBC__h115662[99] &&
	      !sfdBC__h115662[98] &&
	      !sfdBC__h115662[97] &&
	      !sfdBC__h115662[96] &&
	      !sfdBC__h115662[95] &&
	      !sfdBC__h115662[94] &&
	      !sfdBC__h115662[93] &&
	      !sfdBC__h115662[92] &&
	      !sfdBC__h115662[91] &&
	      !sfdBC__h115662[90] &&
	      !sfdBC__h115662[89] &&
	      !sfdBC__h115662[88] &&
	      !sfdBC__h115662[87] &&
	      !sfdBC__h115662[86] &&
	      !sfdBC__h115662[85] &&
	      !sfdBC__h115662[84] &&
	      !sfdBC__h115662[83] &&
	      !sfdBC__h115662[82] &&
	      !sfdBC__h115662[81] &&
	      !sfdBC__h115662[80] &&
	      !sfdBC__h115662[79] &&
	      !sfdBC__h115662[78] &&
	      !sfdBC__h115662[77] &&
	      !sfdBC__h115662[76] &&
	      !sfdBC__h115662[75] &&
	      !sfdBC__h115662[74] &&
	      !sfdBC__h115662[73] &&
	      !sfdBC__h115662[72] &&
	      !sfdBC__h115662[71] &&
	      !sfdBC__h115662[70] &&
	      !sfdBC__h115662[69] &&
	      !sfdBC__h115662[68] &&
	      !sfdBC__h115662[67] &&
	      !sfdBC__h115662[66] &&
	      !sfdBC__h115662[65] &&
	      !sfdBC__h115662[64] &&
	      !sfdBC__h115662[63] &&
	      !sfdBC__h115662[62] &&
	      !sfdBC__h115662[61] &&
	      !sfdBC__h115662[60] &&
	      !sfdBC__h115662[59] &&
	      !sfdBC__h115662[58] &&
	      !sfdBC__h115662[57] &&
	      !sfdBC__h115662[56] &&
	      !sfdBC__h115662[55] &&
	      !sfdBC__h115662[54] &&
	      !sfdBC__h115662[53] &&
	      !sfdBC__h115662[52] &&
	      !sfdBC__h115662[51] &&
	      !sfdBC__h115662[50] &&
	      !sfdBC__h115662[49] &&
	      !sfdBC__h115662[48] &&
	      !sfdBC__h115662[47] &&
	      !sfdBC__h115662[46] &&
	      !sfdBC__h115662[45] &&
	      !sfdBC__h115662[44] &&
	      !sfdBC__h115662[43] &&
	      !sfdBC__h115662[42] &&
	      !sfdBC__h115662[41] &&
	      !sfdBC__h115662[40] &&
	      !sfdBC__h115662[39] &&
	      !sfdBC__h115662[38] &&
	      !sfdBC__h115662[37] &&
	      !sfdBC__h115662[36] &&
	      !sfdBC__h115662[35] &&
	      !sfdBC__h115662[34] &&
	      !sfdBC__h115662[33] &&
	      !sfdBC__h115662[32] &&
	      !sfdBC__h115662[31] &&
	      !sfdBC__h115662[30] &&
	      !sfdBC__h115662[29] &&
	      !sfdBC__h115662[28] &&
	      !sfdBC__h115662[27] &&
	      !sfdBC__h115662[26] &&
	      !sfdBC__h115662[25] &&
	      !sfdBC__h115662[24] &&
	      !sfdBC__h115662[23] &&
	      !sfdBC__h115662[22] &&
	      !sfdBC__h115662[21] &&
	      !sfdBC__h115662[20] &&
	      !sfdBC__h115662[19] &&
	      !sfdBC__h115662[18] &&
	      !sfdBC__h115662[17] &&
	      !sfdBC__h115662[16] &&
	      !sfdBC__h115662[15] &&
	      !sfdBC__h115662[14] &&
	      !sfdBC__h115662[13] &&
	      !sfdBC__h115662[12] &&
	      !sfdBC__h115662[11] &&
	      !sfdBC__h115662[10] &&
	      !sfdBC__h115662[9] &&
	      !sfdBC__h115662[8] &&
	      !sfdBC__h115662[7] &&
	      !sfdBC__h115662[6] &&
	      !sfdBC__h115662[5] &&
	      !sfdBC__h115662[4] &&
	      !sfdBC__h115662[3] &&
	      !sfdBC__h115662[2] &&
	      !sfdBC__h115662[1] &&
	      !sfdBC__h115662[0] ||
	      !_0_CONCAT_IF_IF_7170_MINUS_fpu_madd_fState_S3_f_ETC___d2463) ?
	       11'd0 :
	       _theResult___fst_exp__h131025 ;
  assign _theResult___fst_exp__h131034 =
	     (!sfdBC__h115662[105] && sfdBC__h115662[104]) ?
	       _theResult___fst_exp__h130986 :
	       _theResult___fst_exp__h131031 ;
  assign _theResult___fst_exp__h141375 =
	     sfd__h133119[56] ?
	       _theResult___fst_exp__h141397 :
	       _theResult___fst_exp__h141460 ;
  assign _theResult___fst_exp__h141378 =
	     (sfd__h133119[56] &&
	      IF_fpu_madd_fState_S7_first__651_BITS_126_TO_1_ETC___d2668 ==
	      12'd1023) ?
	       11'd2046 :
	       _theResult___fst_exp__h141375 ;
  assign _theResult___fst_exp__h141397 =
	     (value__h141307[10:0] == 11'd0) ?
	       11'd2 :
	       value__h141307[10:0] + 11'd1 ;
  assign _theResult___fst_exp__h141412 =
	     (value__h141307[10:0] == 11'd0) ? 11'd1 : value__h141307[10:0] ;
  assign _theResult___fst_exp__h141451 =
	     value__h141307[10:0] -
	     { 5'd0,
	       IF_IF_fpu_madd_fState_S7_first__651_BIT_128_65_ETC___d2901 } ;
  assign _theResult___fst_exp__h141457 =
	     (!sfd__h133119[56] && !sfd__h133119[55] && !sfd__h133119[54] &&
	      !sfd__h133119[53] &&
	      !sfd__h133119[52] &&
	      !sfd__h133119[51] &&
	      !sfd__h133119[50] &&
	      !sfd__h133119[49] &&
	      !sfd__h133119[48] &&
	      !sfd__h133119[47] &&
	      !sfd__h133119[46] &&
	      !sfd__h133119[45] &&
	      !sfd__h133119[44] &&
	      !sfd__h133119[43] &&
	      !sfd__h133119[42] &&
	      !sfd__h133119[41] &&
	      !sfd__h133119[40] &&
	      !sfd__h133119[39] &&
	      !sfd__h133119[38] &&
	      !sfd__h133119[37] &&
	      !sfd__h133119[36] &&
	      !sfd__h133119[35] &&
	      !sfd__h133119[34] &&
	      !sfd__h133119[33] &&
	      !sfd__h133119[32] &&
	      !sfd__h133119[31] &&
	      !sfd__h133119[30] &&
	      !sfd__h133119[29] &&
	      !sfd__h133119[28] &&
	      !sfd__h133119[27] &&
	      !sfd__h133119[26] &&
	      !sfd__h133119[25] &&
	      !sfd__h133119[24] &&
	      !sfd__h133119[23] &&
	      !sfd__h133119[22] &&
	      !sfd__h133119[21] &&
	      !sfd__h133119[20] &&
	      !sfd__h133119[19] &&
	      !sfd__h133119[18] &&
	      !sfd__h133119[17] &&
	      !sfd__h133119[16] &&
	      !sfd__h133119[15] &&
	      !sfd__h133119[14] &&
	      !sfd__h133119[13] &&
	      !sfd__h133119[12] &&
	      !sfd__h133119[11] &&
	      !sfd__h133119[10] &&
	      !sfd__h133119[9] &&
	      !sfd__h133119[8] &&
	      !sfd__h133119[7] &&
	      !sfd__h133119[6] &&
	      !sfd__h133119[5] &&
	      !sfd__h133119[4] &&
	      !sfd__h133119[3] &&
	      !sfd__h133119[2] &&
	      !sfd__h133119[1] &&
	      !sfd__h133119[0] ||
	      !_0_CONCAT_IF_IF_fpu_madd_fState_S7_first__651_B_ETC___d2904) ?
	       11'd0 :
	       _theResult___fst_exp__h141451 ;
  assign _theResult___fst_exp__h141460 =
	     (!sfd__h133119[56] && sfd__h133119[55]) ?
	       _theResult___fst_exp__h141412 :
	       _theResult___fst_exp__h141457 ;
  assign _theResult___fst_exp__h163327 =
	     11'd897 -
	     { 5'd0,
	       IF_iFifo_first__087_BITS_167_TO_160_130_EQ_0_1_ETC___d3271 } ;
  assign _theResult___fst_exp__h163333 =
	     (iFifo$D_OUT[167:160] == 8'd0 && !iFifo$D_OUT[159] &&
	      NOT_iFifo_first__087_BIT_158_142_202_AND_NOT_i_ETC___d3244 ||
	      !_0_CONCAT_IF_iFifo_first__087_BITS_167_TO_160_1_ETC___d3273) ?
	       11'd0 :
	       _theResult___fst_exp__h163327 ;
  assign _theResult___fst_exp__h163336 =
	     (iFifo$D_OUT[167:160] == 8'd0) ?
	       _theResult___fst_exp__h163333 :
	       11'd897 ;
  assign _theResult___fst_exp__h164062 =
	     (_theResult___fst_exp__h163336 == 11'd2047) ?
	       _theResult___fst_exp__h163336 :
	       _theResult___fst_exp__h164059 ;
  assign _theResult___fst_exp__h172852 =
	     _theResult____h164614[56] ?
	       11'd2 :
	       _theResult___fst_exp__h172926 ;
  assign _theResult___fst_exp__h172917 =
	     11'd0 -
	     { 5'd0,
	       IF_IF_3074_MINUS_SEXT_iFifo_first__087_BITS_16_ETC___d3572 } ;
  assign _theResult___fst_exp__h172923 =
	     (!_theResult____h164614[56] && !_theResult____h164614[55] &&
	      !_theResult____h164614[54] &&
	      !_theResult____h164614[53] &&
	      !_theResult____h164614[52] &&
	      !_theResult____h164614[51] &&
	      !_theResult____h164614[50] &&
	      !_theResult____h164614[49] &&
	      !_theResult____h164614[48] &&
	      !_theResult____h164614[47] &&
	      !_theResult____h164614[46] &&
	      !_theResult____h164614[45] &&
	      !_theResult____h164614[44] &&
	      !_theResult____h164614[43] &&
	      !_theResult____h164614[42] &&
	      !_theResult____h164614[41] &&
	      !_theResult____h164614[40] &&
	      !_theResult____h164614[39] &&
	      !_theResult____h164614[38] &&
	      !_theResult____h164614[37] &&
	      !_theResult____h164614[36] &&
	      !_theResult____h164614[35] &&
	      !_theResult____h164614[34] &&
	      !_theResult____h164614[33] &&
	      !_theResult____h164614[32] &&
	      !_theResult____h164614[31] &&
	      !_theResult____h164614[30] &&
	      !_theResult____h164614[29] &&
	      !_theResult____h164614[28] &&
	      !_theResult____h164614[27] &&
	      !_theResult____h164614[26] &&
	      !_theResult____h164614[25] &&
	      !_theResult____h164614[24] &&
	      !_theResult____h164614[23] &&
	      !_theResult____h164614[22] &&
	      !_theResult____h164614[21] &&
	      !_theResult____h164614[20] &&
	      !_theResult____h164614[19] &&
	      !_theResult____h164614[18] &&
	      !_theResult____h164614[17] &&
	      !_theResult____h164614[16] &&
	      !_theResult____h164614[15] &&
	      !_theResult____h164614[14] &&
	      !_theResult____h164614[13] &&
	      !_theResult____h164614[12] &&
	      !_theResult____h164614[11] &&
	      !_theResult____h164614[10] &&
	      !_theResult____h164614[9] &&
	      !_theResult____h164614[8] &&
	      !_theResult____h164614[7] &&
	      !_theResult____h164614[6] &&
	      !_theResult____h164614[5] &&
	      !_theResult____h164614[4] &&
	      !_theResult____h164614[3] &&
	      !_theResult____h164614[2] &&
	      !_theResult____h164614[1] &&
	      !_theResult____h164614[0] ||
	      !_0_CONCAT_IF_IF_3074_MINUS_SEXT_iFifo_first__08_ETC___d3574) ?
	       11'd0 :
	       _theResult___fst_exp__h172917 ;
  assign _theResult___fst_exp__h172926 =
	     (!_theResult____h164614[56] && _theResult____h164614[55]) ?
	       11'd1 :
	       _theResult___fst_exp__h172923 ;
  assign _theResult___fst_exp__h173652 =
	     (_theResult___fst_exp__h172852 == 11'd2047) ?
	       _theResult___fst_exp__h172852 :
	       _theResult___fst_exp__h173649 ;
  assign _theResult___fst_exp__h181605 =
	     (SEXT_iFifo_first__087_BITS_167_TO_160_130_MINU_ETC__q36[10:0] ==
	      11'd0) ?
	       11'd1 :
	       SEXT_iFifo_first__087_BITS_167_TO_160_130_MINU_ETC__q36[10:0] ;
  assign _theResult___fst_exp__h181644 =
	     SEXT_iFifo_first__087_BITS_167_TO_160_130_MINU_ETC__q36[10:0] -
	     { 5'd0,
	       IF_iFifo_first__087_BITS_167_TO_160_130_EQ_0_1_ETC___d3271 } ;
  assign _theResult___fst_exp__h181650 =
	     (iFifo$D_OUT[167:160] == 8'd0 && !iFifo$D_OUT[159] &&
	      NOT_iFifo_first__087_BIT_158_142_202_AND_NOT_i_ETC___d3244 ||
	      !_0_CONCAT_IF_iFifo_first__087_BITS_167_TO_160_1_ETC___d3624) ?
	       11'd0 :
	       _theResult___fst_exp__h181644 ;
  assign _theResult___fst_exp__h181653 =
	     (iFifo$D_OUT[167:160] == 8'd0) ?
	       _theResult___fst_exp__h181650 :
	       _theResult___fst_exp__h181605 ;
  assign _theResult___fst_exp__h182404 =
	     (_theResult___fst_exp__h181653 == 11'd2047) ?
	       _theResult___fst_exp__h181653 :
	       _theResult___fst_exp__h182401 ;
  assign _theResult___fst_exp__h182413 =
	     (iFifo$D_OUT[167:160] == 8'd0) ?
	       (_3970_MINUS_0_CONCAT_IF_iFifo_first__087_BIT_15_ETC___d3189 ?
		  _theResult___snd_fst_exp__h164065 :
		  _theResult___fst_exp__h148291) :
	       (SEXT_iFifo_first__087_BITS_167_TO_160_130_MINU_ETC___d3324 ?
		  _theResult___snd_fst_exp__h182407 :
		  _theResult___fst_exp__h148291) ;
  assign _theResult___fst_exp__h182416 =
	     (iFifo$D_OUT[167:160] == 8'd0 && iFifo$D_OUT[159:137] == 23'd0) ?
	       11'd0 :
	       _theResult___fst_exp__h182413 ;
  assign _theResult___fst_exp__h201965 =
	     11'd897 -
	     { 5'd0,
	       IF_iFifo_first__087_BITS_102_TO_95_625_EQ_0_63_ETC___d4757 } ;
  assign _theResult___fst_exp__h201971 =
	     (iFifo$D_OUT[102:95] == 8'd0 && !iFifo$D_OUT[94] &&
	      NOT_iFifo_first__087_BIT_93_637_688_AND_NOT_iF_ETC___d4730 ||
	      !_0_CONCAT_IF_iFifo_first__087_BITS_102_TO_95_62_ETC___d4759) ?
	       11'd0 :
	       _theResult___fst_exp__h201965 ;
  assign _theResult___fst_exp__h201974 =
	     (iFifo$D_OUT[102:95] == 8'd0) ?
	       _theResult___fst_exp__h201971 :
	       11'd897 ;
  assign _theResult___fst_exp__h202700 =
	     (_theResult___fst_exp__h201974 == 11'd2047) ?
	       _theResult___fst_exp__h201974 :
	       _theResult___fst_exp__h202697 ;
  assign _theResult___fst_exp__h211490 =
	     _theResult____h203252[56] ?
	       11'd2 :
	       _theResult___fst_exp__h211564 ;
  assign _theResult___fst_exp__h211555 =
	     11'd0 -
	     { 5'd0,
	       IF_IF_3074_MINUS_SEXT_iFifo_first__087_BITS_10_ETC___d5055 } ;
  assign _theResult___fst_exp__h211561 =
	     (!_theResult____h203252[56] && !_theResult____h203252[55] &&
	      !_theResult____h203252[54] &&
	      !_theResult____h203252[53] &&
	      !_theResult____h203252[52] &&
	      !_theResult____h203252[51] &&
	      !_theResult____h203252[50] &&
	      !_theResult____h203252[49] &&
	      !_theResult____h203252[48] &&
	      !_theResult____h203252[47] &&
	      !_theResult____h203252[46] &&
	      !_theResult____h203252[45] &&
	      !_theResult____h203252[44] &&
	      !_theResult____h203252[43] &&
	      !_theResult____h203252[42] &&
	      !_theResult____h203252[41] &&
	      !_theResult____h203252[40] &&
	      !_theResult____h203252[39] &&
	      !_theResult____h203252[38] &&
	      !_theResult____h203252[37] &&
	      !_theResult____h203252[36] &&
	      !_theResult____h203252[35] &&
	      !_theResult____h203252[34] &&
	      !_theResult____h203252[33] &&
	      !_theResult____h203252[32] &&
	      !_theResult____h203252[31] &&
	      !_theResult____h203252[30] &&
	      !_theResult____h203252[29] &&
	      !_theResult____h203252[28] &&
	      !_theResult____h203252[27] &&
	      !_theResult____h203252[26] &&
	      !_theResult____h203252[25] &&
	      !_theResult____h203252[24] &&
	      !_theResult____h203252[23] &&
	      !_theResult____h203252[22] &&
	      !_theResult____h203252[21] &&
	      !_theResult____h203252[20] &&
	      !_theResult____h203252[19] &&
	      !_theResult____h203252[18] &&
	      !_theResult____h203252[17] &&
	      !_theResult____h203252[16] &&
	      !_theResult____h203252[15] &&
	      !_theResult____h203252[14] &&
	      !_theResult____h203252[13] &&
	      !_theResult____h203252[12] &&
	      !_theResult____h203252[11] &&
	      !_theResult____h203252[10] &&
	      !_theResult____h203252[9] &&
	      !_theResult____h203252[8] &&
	      !_theResult____h203252[7] &&
	      !_theResult____h203252[6] &&
	      !_theResult____h203252[5] &&
	      !_theResult____h203252[4] &&
	      !_theResult____h203252[3] &&
	      !_theResult____h203252[2] &&
	      !_theResult____h203252[1] &&
	      !_theResult____h203252[0] ||
	      !_0_CONCAT_IF_IF_3074_MINUS_SEXT_iFifo_first__08_ETC___d5057) ?
	       11'd0 :
	       _theResult___fst_exp__h211555 ;
  assign _theResult___fst_exp__h211564 =
	     (!_theResult____h203252[56] && _theResult____h203252[55]) ?
	       11'd1 :
	       _theResult___fst_exp__h211561 ;
  assign _theResult___fst_exp__h212290 =
	     (_theResult___fst_exp__h211490 == 11'd2047) ?
	       _theResult___fst_exp__h211490 :
	       _theResult___fst_exp__h212287 ;
  assign _theResult___fst_exp__h220243 =
	     (SEXT_iFifo_first__087_BITS_102_TO_95_625_MINUS_ETC__q96[10:0] ==
	      11'd0) ?
	       11'd1 :
	       SEXT_iFifo_first__087_BITS_102_TO_95_625_MINUS_ETC__q96[10:0] ;
  assign _theResult___fst_exp__h220282 =
	     SEXT_iFifo_first__087_BITS_102_TO_95_625_MINUS_ETC__q96[10:0] -
	     { 5'd0,
	       IF_iFifo_first__087_BITS_102_TO_95_625_EQ_0_63_ETC___d4757 } ;
  assign _theResult___fst_exp__h220288 =
	     (iFifo$D_OUT[102:95] == 8'd0 && !iFifo$D_OUT[94] &&
	      NOT_iFifo_first__087_BIT_93_637_688_AND_NOT_iF_ETC___d4730 ||
	      !_0_CONCAT_IF_iFifo_first__087_BITS_102_TO_95_62_ETC___d5107) ?
	       11'd0 :
	       _theResult___fst_exp__h220282 ;
  assign _theResult___fst_exp__h220291 =
	     (iFifo$D_OUT[102:95] == 8'd0) ?
	       _theResult___fst_exp__h220288 :
	       _theResult___fst_exp__h220243 ;
  assign _theResult___fst_exp__h221042 =
	     (_theResult___fst_exp__h220291 == 11'd2047) ?
	       _theResult___fst_exp__h220291 :
	       _theResult___fst_exp__h221039 ;
  assign _theResult___fst_exp__h221051 =
	     (iFifo$D_OUT[102:95] == 8'd0) ?
	       (_3970_MINUS_0_CONCAT_IF_iFifo_first__087_BIT_94_ETC___d4684 ?
		  _theResult___snd_fst_exp__h202703 :
		  _theResult___fst_exp__h186931) :
	       (SEXT_iFifo_first__087_BITS_102_TO_95_625_MINUS_ETC___d4807 ?
		  _theResult___snd_fst_exp__h221045 :
		  _theResult___fst_exp__h186931) ;
  assign _theResult___fst_exp__h221054 =
	     (iFifo$D_OUT[102:95] == 8'd0 && iFifo$D_OUT[94:72] == 23'd0) ?
	       11'd0 :
	       _theResult___fst_exp__h221051 ;
  assign _theResult___fst_exp__h240904 =
	     11'd897 -
	     { 5'd0,
	       IF_iFifo_first__087_BITS_37_TO_30_850_EQ_0_856_ETC___d3982 } ;
  assign _theResult___fst_exp__h240910 =
	     (iFifo$D_OUT[37:30] == 8'd0 && !iFifo$D_OUT[29] &&
	      NOT_iFifo_first__087_BIT_28_862_913_AND_NOT_iF_ETC___d3955 ||
	      !_0_CONCAT_IF_iFifo_first__087_BITS_37_TO_30_850_ETC___d3984) ?
	       11'd0 :
	       _theResult___fst_exp__h240904 ;
  assign _theResult___fst_exp__h240913 =
	     (iFifo$D_OUT[37:30] == 8'd0) ?
	       _theResult___fst_exp__h240910 :
	       11'd897 ;
  assign _theResult___fst_exp__h241639 =
	     (_theResult___fst_exp__h240913 == 11'd2047) ?
	       _theResult___fst_exp__h240913 :
	       _theResult___fst_exp__h241636 ;
  assign _theResult___fst_exp__h250429 =
	     _theResult____h242191[56] ?
	       11'd2 :
	       _theResult___fst_exp__h250503 ;
  assign _theResult___fst_exp__h250494 =
	     11'd0 -
	     { 5'd0,
	       IF_IF_3074_MINUS_SEXT_iFifo_first__087_BITS_37_ETC___d4280 } ;
  assign _theResult___fst_exp__h250500 =
	     (!_theResult____h242191[56] && !_theResult____h242191[55] &&
	      !_theResult____h242191[54] &&
	      !_theResult____h242191[53] &&
	      !_theResult____h242191[52] &&
	      !_theResult____h242191[51] &&
	      !_theResult____h242191[50] &&
	      !_theResult____h242191[49] &&
	      !_theResult____h242191[48] &&
	      !_theResult____h242191[47] &&
	      !_theResult____h242191[46] &&
	      !_theResult____h242191[45] &&
	      !_theResult____h242191[44] &&
	      !_theResult____h242191[43] &&
	      !_theResult____h242191[42] &&
	      !_theResult____h242191[41] &&
	      !_theResult____h242191[40] &&
	      !_theResult____h242191[39] &&
	      !_theResult____h242191[38] &&
	      !_theResult____h242191[37] &&
	      !_theResult____h242191[36] &&
	      !_theResult____h242191[35] &&
	      !_theResult____h242191[34] &&
	      !_theResult____h242191[33] &&
	      !_theResult____h242191[32] &&
	      !_theResult____h242191[31] &&
	      !_theResult____h242191[30] &&
	      !_theResult____h242191[29] &&
	      !_theResult____h242191[28] &&
	      !_theResult____h242191[27] &&
	      !_theResult____h242191[26] &&
	      !_theResult____h242191[25] &&
	      !_theResult____h242191[24] &&
	      !_theResult____h242191[23] &&
	      !_theResult____h242191[22] &&
	      !_theResult____h242191[21] &&
	      !_theResult____h242191[20] &&
	      !_theResult____h242191[19] &&
	      !_theResult____h242191[18] &&
	      !_theResult____h242191[17] &&
	      !_theResult____h242191[16] &&
	      !_theResult____h242191[15] &&
	      !_theResult____h242191[14] &&
	      !_theResult____h242191[13] &&
	      !_theResult____h242191[12] &&
	      !_theResult____h242191[11] &&
	      !_theResult____h242191[10] &&
	      !_theResult____h242191[9] &&
	      !_theResult____h242191[8] &&
	      !_theResult____h242191[7] &&
	      !_theResult____h242191[6] &&
	      !_theResult____h242191[5] &&
	      !_theResult____h242191[4] &&
	      !_theResult____h242191[3] &&
	      !_theResult____h242191[2] &&
	      !_theResult____h242191[1] &&
	      !_theResult____h242191[0] ||
	      !_0_CONCAT_IF_IF_3074_MINUS_SEXT_iFifo_first__08_ETC___d4282) ?
	       11'd0 :
	       _theResult___fst_exp__h250494 ;
  assign _theResult___fst_exp__h250503 =
	     (!_theResult____h242191[56] && _theResult____h242191[55]) ?
	       11'd1 :
	       _theResult___fst_exp__h250500 ;
  assign _theResult___fst_exp__h251229 =
	     (_theResult___fst_exp__h250429 == 11'd2047) ?
	       _theResult___fst_exp__h250429 :
	       _theResult___fst_exp__h251226 ;
  assign _theResult___fst_exp__h259182 =
	     (SEXT_iFifo_first__087_BITS_37_TO_30_850_MINUS__ETC__q63[10:0] ==
	      11'd0) ?
	       11'd1 :
	       SEXT_iFifo_first__087_BITS_37_TO_30_850_MINUS__ETC__q63[10:0] ;
  assign _theResult___fst_exp__h259221 =
	     SEXT_iFifo_first__087_BITS_37_TO_30_850_MINUS__ETC__q63[10:0] -
	     { 5'd0,
	       IF_iFifo_first__087_BITS_37_TO_30_850_EQ_0_856_ETC___d3982 } ;
  assign _theResult___fst_exp__h259227 =
	     (iFifo$D_OUT[37:30] == 8'd0 && !iFifo$D_OUT[29] &&
	      NOT_iFifo_first__087_BIT_28_862_913_AND_NOT_iF_ETC___d3955 ||
	      !_0_CONCAT_IF_iFifo_first__087_BITS_37_TO_30_850_ETC___d4332) ?
	       11'd0 :
	       _theResult___fst_exp__h259221 ;
  assign _theResult___fst_exp__h259230 =
	     (iFifo$D_OUT[37:30] == 8'd0) ?
	       _theResult___fst_exp__h259227 :
	       _theResult___fst_exp__h259182 ;
  assign _theResult___fst_exp__h259981 =
	     (_theResult___fst_exp__h259230 == 11'd2047) ?
	       _theResult___fst_exp__h259230 :
	       _theResult___fst_exp__h259978 ;
  assign _theResult___fst_exp__h259990 =
	     (iFifo$D_OUT[37:30] == 8'd0) ?
	       (_3970_MINUS_0_CONCAT_IF_iFifo_first__087_BIT_29_ETC___d3909 ?
		  _theResult___snd_fst_exp__h241642 :
		  _theResult___fst_exp__h225870) :
	       (SEXT_iFifo_first__087_BITS_37_TO_30_850_MINUS__ETC___d4032 ?
		  _theResult___snd_fst_exp__h259984 :
		  _theResult___fst_exp__h225870) ;
  assign _theResult___fst_exp__h259993 =
	     (iFifo$D_OUT[37:30] == 8'd0 && iFifo$D_OUT[29:7] == 23'd0) ?
	       11'd0 :
	       _theResult___fst_exp__h259990 ;
  assign _theResult___fst_exp__h277686 =
	     _theResult____h269577[56] ?
	       8'd2 :
	       _theResult___fst_exp__h277760 ;
  assign _theResult___fst_exp__h277751 =
	     8'd0 -
	     { 2'd0,
	       IF_IF_0b0_CONCAT_NOT_resWire_wget__410_BITS_67_ETC___d5767 } ;
  assign _theResult___fst_exp__h277757 =
	     (!_theResult____h269577[56] && !_theResult____h269577[55] &&
	      !_theResult____h269577[54] &&
	      !_theResult____h269577[53] &&
	      !_theResult____h269577[52] &&
	      !_theResult____h269577[51] &&
	      !_theResult____h269577[50] &&
	      !_theResult____h269577[49] &&
	      !_theResult____h269577[48] &&
	      !_theResult____h269577[47] &&
	      !_theResult____h269577[46] &&
	      !_theResult____h269577[45] &&
	      !_theResult____h269577[44] &&
	      !_theResult____h269577[43] &&
	      !_theResult____h269577[42] &&
	      !_theResult____h269577[41] &&
	      !_theResult____h269577[40] &&
	      !_theResult____h269577[39] &&
	      !_theResult____h269577[38] &&
	      !_theResult____h269577[37] &&
	      !_theResult____h269577[36] &&
	      !_theResult____h269577[35] &&
	      !_theResult____h269577[34] &&
	      !_theResult____h269577[33] &&
	      !_theResult____h269577[32] &&
	      !_theResult____h269577[31] &&
	      !_theResult____h269577[30] &&
	      !_theResult____h269577[29] &&
	      !_theResult____h269577[28] &&
	      !_theResult____h269577[27] &&
	      !_theResult____h269577[26] &&
	      !_theResult____h269577[25] &&
	      !_theResult____h269577[24] &&
	      !_theResult____h269577[23] &&
	      !_theResult____h269577[22] &&
	      !_theResult____h269577[21] &&
	      !_theResult____h269577[20] &&
	      !_theResult____h269577[19] &&
	      !_theResult____h269577[18] &&
	      !_theResult____h269577[17] &&
	      !_theResult____h269577[16] &&
	      !_theResult____h269577[15] &&
	      !_theResult____h269577[14] &&
	      !_theResult____h269577[13] &&
	      !_theResult____h269577[12] &&
	      !_theResult____h269577[11] &&
	      !_theResult____h269577[10] &&
	      !_theResult____h269577[9] &&
	      !_theResult____h269577[8] &&
	      !_theResult____h269577[7] &&
	      !_theResult____h269577[6] &&
	      !_theResult____h269577[5] &&
	      !_theResult____h269577[4] &&
	      !_theResult____h269577[3] &&
	      !_theResult____h269577[2] &&
	      !_theResult____h269577[1] &&
	      !_theResult____h269577[0] ||
	      !_0_CONCAT_IF_IF_0b0_CONCAT_NOT_resWire_wget__41_ETC___d5769) ?
	       8'd0 :
	       _theResult___fst_exp__h277751 ;
  assign _theResult___fst_exp__h277760 =
	     (!_theResult____h269577[56] && _theResult____h269577[55]) ?
	       8'd1 :
	       _theResult___fst_exp__h277757 ;
  assign _theResult___fst_exp__h278283 =
	     (_theResult___fst_exp__h277686 == 8'd255) ?
	       _theResult___fst_exp__h277686 :
	       _theResult___fst_exp__h278280 ;
  assign _theResult___fst_exp__h286333 =
	     8'd129 -
	     { 2'd0,
	       IF_resWire_wget__410_BITS_67_TO_57_416_EQ_0_42_ETC___d5982 } ;
  assign _theResult___fst_exp__h286339 =
	     (resWire$wget[67:57] == 11'd0 &&
	      NOT_resWire_wget__410_BIT_56_426_825_AND_NOT_r_ETC___d5927 ||
	      !_0_CONCAT_IF_resWire_wget__410_BITS_67_TO_57_41_ETC___d5984) ?
	       8'd0 :
	       _theResult___fst_exp__h286333 ;
  assign _theResult___fst_exp__h286342 =
	     (resWire$wget[67:57] == 11'd0) ?
	       _theResult___fst_exp__h286339 :
	       8'd129 ;
  assign _theResult___fst_exp__h286865 =
	     (_theResult___fst_exp__h286342 == 8'd255) ?
	       _theResult___fst_exp__h286342 :
	       _theResult___fst_exp__h286862 ;
  assign _theResult___fst_exp__h295452 =
	     _theResult____h287214[56] ?
	       8'd2 :
	       _theResult___fst_exp__h295526 ;
  assign _theResult___fst_exp__h295517 =
	     8'd0 -
	     { 2'd0,
	       IF_IF_3970_MINUS_SEXT_resWire_wget__410_BITS_6_ETC___d6278 } ;
  assign _theResult___fst_exp__h295523 =
	     (!_theResult____h287214[56] && !_theResult____h287214[55] &&
	      !_theResult____h287214[54] &&
	      !_theResult____h287214[53] &&
	      !_theResult____h287214[52] &&
	      !_theResult____h287214[51] &&
	      !_theResult____h287214[50] &&
	      !_theResult____h287214[49] &&
	      !_theResult____h287214[48] &&
	      !_theResult____h287214[47] &&
	      !_theResult____h287214[46] &&
	      !_theResult____h287214[45] &&
	      !_theResult____h287214[44] &&
	      !_theResult____h287214[43] &&
	      !_theResult____h287214[42] &&
	      !_theResult____h287214[41] &&
	      !_theResult____h287214[40] &&
	      !_theResult____h287214[39] &&
	      !_theResult____h287214[38] &&
	      !_theResult____h287214[37] &&
	      !_theResult____h287214[36] &&
	      !_theResult____h287214[35] &&
	      !_theResult____h287214[34] &&
	      !_theResult____h287214[33] &&
	      !_theResult____h287214[32] &&
	      !_theResult____h287214[31] &&
	      !_theResult____h287214[30] &&
	      !_theResult____h287214[29] &&
	      !_theResult____h287214[28] &&
	      !_theResult____h287214[27] &&
	      !_theResult____h287214[26] &&
	      !_theResult____h287214[25] &&
	      !_theResult____h287214[24] &&
	      !_theResult____h287214[23] &&
	      !_theResult____h287214[22] &&
	      !_theResult____h287214[21] &&
	      !_theResult____h287214[20] &&
	      !_theResult____h287214[19] &&
	      !_theResult____h287214[18] &&
	      !_theResult____h287214[17] &&
	      !_theResult____h287214[16] &&
	      !_theResult____h287214[15] &&
	      !_theResult____h287214[14] &&
	      !_theResult____h287214[13] &&
	      !_theResult____h287214[12] &&
	      !_theResult____h287214[11] &&
	      !_theResult____h287214[10] &&
	      !_theResult____h287214[9] &&
	      !_theResult____h287214[8] &&
	      !_theResult____h287214[7] &&
	      !_theResult____h287214[6] &&
	      !_theResult____h287214[5] &&
	      !_theResult____h287214[4] &&
	      !_theResult____h287214[3] &&
	      !_theResult____h287214[2] &&
	      !_theResult____h287214[1] &&
	      !_theResult____h287214[0] ||
	      !_0_CONCAT_IF_IF_3970_MINUS_SEXT_resWire_wget__4_ETC___d6280) ?
	       8'd0 :
	       _theResult___fst_exp__h295517 ;
  assign _theResult___fst_exp__h295526 =
	     (!_theResult____h287214[56] && _theResult____h287214[55]) ?
	       8'd1 :
	       _theResult___fst_exp__h295523 ;
  assign _theResult___fst_exp__h296049 =
	     (_theResult___fst_exp__h295452 == 8'd255) ?
	       _theResult___fst_exp__h295452 :
	       _theResult___fst_exp__h296046 ;
  assign _theResult___fst_exp__h304089 =
	     (SEXT_resWire_wget__410_BITS_67_TO_57_416_MINUS_ETC__q138[7:0] ==
	      8'd0) ?
	       8'd1 :
	       SEXT_resWire_wget__410_BITS_67_TO_57_416_MINUS_ETC__q138[7:0] ;
  assign _theResult___fst_exp__h304128 =
	     SEXT_resWire_wget__410_BITS_67_TO_57_416_MINUS_ETC__q138[7:0] -
	     { 2'd0,
	       IF_resWire_wget__410_BITS_67_TO_57_416_EQ_0_42_ETC___d5982 } ;
  assign _theResult___fst_exp__h304134 =
	     (resWire$wget[67:57] == 11'd0 &&
	      NOT_resWire_wget__410_BIT_56_426_825_AND_NOT_r_ETC___d5927 ||
	      !_0_CONCAT_IF_resWire_wget__410_BITS_67_TO_57_41_ETC___d6333) ?
	       8'd0 :
	       _theResult___fst_exp__h304128 ;
  assign _theResult___fst_exp__h304137 =
	     (resWire$wget[67:57] == 11'd0) ?
	       _theResult___fst_exp__h304134 :
	       _theResult___fst_exp__h304089 ;
  assign _theResult___fst_exp__h304685 =
	     (_theResult___fst_exp__h304137 == 8'd255) ?
	       _theResult___fst_exp__h304137 :
	       _theResult___fst_exp__h304682 ;
  assign _theResult___fst_exp__h304694 =
	     (resWire$wget[67:57] == 11'd0) ?
	       (_3074_MINUS_0_CONCAT_IF_resWire_wget__410_BIT_5_ETC___d5532 ?
		  _theResult___snd_fst_exp__h286868 :
		  _theResult___fst_exp__h269559) :
	       (SEXT_resWire_wget__410_BITS_67_TO_57_416_MINUS_ETC___d6032 ?
		  _theResult___snd_fst_exp__h304688 :
		  _theResult___fst_exp__h269559) ;
  assign _theResult___fst_exp__h304697 =
	     (resWire$wget[67:57] == 11'd0 && resWire$wget[56:5] == 52'd0) ?
	       8'd0 :
	       _theResult___fst_exp__h304694 ;
  assign _theResult___fst_exp__h42284 =
	     fpu_div64_fState_S3$D_OUT[120:110] - 11'd1 ;
  assign _theResult___fst_exp__h42287 =
	     (fpu_div64_fState_S3$D_OUT[57:56] == 2'b0) ?
	       _theResult___fst_exp__h42284 :
	       11'd2046 ;
  assign _theResult___fst_exp__h42290 =
	     (fpu_div64_fState_S3$D_OUT[120:110] == 11'd2047) ?
	       _theResult___fst_exp__h42287 :
	       fpu_div64_fState_S3$D_OUT[120:110] ;
  assign _theResult___fst_exp__h42333 =
	     sfdin__h34118[57] ?
	       _theResult___fst_exp__h42356 :
	       _theResult___fst_exp__h42420 ;
  assign _theResult___fst_exp__h42336 =
	     (sfdin__h34118[57] &&
	      IF_IF_fpu_div64_fState_S3_first__86_BITS_120_T_ETC___d643 ==
	      12'd1023) ?
	       11'd2046 :
	       _theResult___fst_exp__h42333 ;
  assign _theResult___fst_exp__h42356 =
	     (_theResult___fst_exp__h42290 == 11'd0) ?
	       11'd2 :
	       _theResult___fst_exp__h42290 + 11'd1 ;
  assign _theResult___fst_exp__h42372 =
	     (_theResult___fst_exp__h42290 == 11'd0) ?
	       11'd1 :
	       _theResult___fst_exp__h42290 ;
  assign _theResult___fst_exp__h42411 =
	     _theResult___fst_exp__h42290 -
	     { 5'd0,
	       IF_IF_fpu_div64_fState_S3_first__86_BITS_120_T_ETC___d880 } ;
  assign _theResult___fst_exp__h42417 =
	     (!sfdin__h34118[57] && !sfdin__h34118[56] &&
	      !sfdin__h34118[55] &&
	      !sfdin__h34118[54] &&
	      !sfdin__h34118[53] &&
	      !sfdin__h34118[52] &&
	      !sfdin__h34118[51] &&
	      !sfdin__h34118[50] &&
	      !sfdin__h34118[49] &&
	      !sfdin__h34118[48] &&
	      !sfdin__h34118[47] &&
	      !sfdin__h34118[46] &&
	      !sfdin__h34118[45] &&
	      !sfdin__h34118[44] &&
	      !sfdin__h34118[43] &&
	      !sfdin__h34118[42] &&
	      !sfdin__h34118[41] &&
	      !sfdin__h34118[40] &&
	      !sfdin__h34118[39] &&
	      !sfdin__h34118[38] &&
	      !sfdin__h34118[37] &&
	      !sfdin__h34118[36] &&
	      !sfdin__h34118[35] &&
	      !sfdin__h34118[34] &&
	      !sfdin__h34118[33] &&
	      !sfdin__h34118[32] &&
	      !sfdin__h34118[31] &&
	      !sfdin__h34118[30] &&
	      !sfdin__h34118[29] &&
	      !sfdin__h34118[28] &&
	      !sfdin__h34118[27] &&
	      !sfdin__h34118[26] &&
	      !sfdin__h34118[25] &&
	      !sfdin__h34118[24] &&
	      !sfdin__h34118[23] &&
	      !sfdin__h34118[22] &&
	      !sfdin__h34118[21] &&
	      !sfdin__h34118[20] &&
	      !sfdin__h34118[19] &&
	      !sfdin__h34118[18] &&
	      !sfdin__h34118[17] &&
	      !sfdin__h34118[16] &&
	      !sfdin__h34118[15] &&
	      !sfdin__h34118[14] &&
	      !sfdin__h34118[13] &&
	      !sfdin__h34118[12] &&
	      !sfdin__h34118[11] &&
	      !sfdin__h34118[10] &&
	      !sfdin__h34118[9] &&
	      !sfdin__h34118[8] &&
	      !sfdin__h34118[7] &&
	      !sfdin__h34118[6] &&
	      !sfdin__h34118[5] &&
	      !sfdin__h34118[4] &&
	      !sfdin__h34118[3] &&
	      !sfdin__h34118[2] &&
	      !sfdin__h34118[1] &&
	      !sfdin__h34118[0] ||
	      !_0_CONCAT_IF_IF_fpu_div64_fState_S3_first__86_B_ETC___d883) ?
	       11'd0 :
	       _theResult___fst_exp__h42411 ;
  assign _theResult___fst_exp__h42420 =
	     (!sfdin__h34118[57] && sfdin__h34118[56]) ?
	       _theResult___fst_exp__h42372 :
	       _theResult___fst_exp__h42417 ;
  assign _theResult___fst_exp__h43556 =
	     (fpu_div64_fState_S4$D_OUT[64:54] == 11'd2047) ?
	       fpu_div64_fState_S4$D_OUT[64:54] :
	       _theResult___fst_exp__h43553 ;
  assign _theResult___fst_exp__h94750 =
	     fpu_sqr64_fState_S3$D_OUT[58] ?
	       _theResult___fst_exp__h94773 :
	       _theResult___fst_exp__h94837 ;
  assign _theResult___fst_exp__h94753 =
	     (fpu_sqr64_fState_S3$D_OUT[58] &&
	      IF_fpu_sqr64_fState_S3_first__375_BITS_121_TO__ETC___d1389 ==
	      12'd1023) ?
	       11'd2046 :
	       _theResult___fst_exp__h94750 ;
  assign _theResult___fst_exp__h94773 =
	     (fpu_sqr64_fState_S3$D_OUT[121:111] == 11'd0) ?
	       11'd2 :
	       fpu_sqr64_fState_S3$D_OUT[121:111] + 11'd1 ;
  assign _theResult___fst_exp__h94789 =
	     (fpu_sqr64_fState_S3$D_OUT[121:111] == 11'd0) ?
	       11'd1 :
	       fpu_sqr64_fState_S3$D_OUT[121:111] ;
  assign _theResult___fst_exp__h94828 =
	     fpu_sqr64_fState_S3$D_OUT[121:111] -
	     { 5'd0,
	       IF_fpu_sqr64_fState_S3_first__375_BIT_58_384_T_ETC___d1630 } ;
  assign _theResult___fst_exp__h94834 =
	     (!fpu_sqr64_fState_S3$D_OUT[58] &&
	      !fpu_sqr64_fState_S3$D_OUT[57] &&
	      !fpu_sqr64_fState_S3$D_OUT[56] &&
	      !fpu_sqr64_fState_S3$D_OUT[55] &&
	      !fpu_sqr64_fState_S3$D_OUT[54] &&
	      !fpu_sqr64_fState_S3$D_OUT[53] &&
	      !fpu_sqr64_fState_S3$D_OUT[52] &&
	      !fpu_sqr64_fState_S3$D_OUT[51] &&
	      !fpu_sqr64_fState_S3$D_OUT[50] &&
	      !fpu_sqr64_fState_S3$D_OUT[49] &&
	      !fpu_sqr64_fState_S3$D_OUT[48] &&
	      !fpu_sqr64_fState_S3$D_OUT[47] &&
	      !fpu_sqr64_fState_S3$D_OUT[46] &&
	      !fpu_sqr64_fState_S3$D_OUT[45] &&
	      !fpu_sqr64_fState_S3$D_OUT[44] &&
	      !fpu_sqr64_fState_S3$D_OUT[43] &&
	      !fpu_sqr64_fState_S3$D_OUT[42] &&
	      !fpu_sqr64_fState_S3$D_OUT[41] &&
	      !fpu_sqr64_fState_S3$D_OUT[40] &&
	      !fpu_sqr64_fState_S3$D_OUT[39] &&
	      !fpu_sqr64_fState_S3$D_OUT[38] &&
	      !fpu_sqr64_fState_S3$D_OUT[37] &&
	      !fpu_sqr64_fState_S3$D_OUT[36] &&
	      !fpu_sqr64_fState_S3$D_OUT[35] &&
	      !fpu_sqr64_fState_S3$D_OUT[34] &&
	      !fpu_sqr64_fState_S3$D_OUT[33] &&
	      !fpu_sqr64_fState_S3$D_OUT[32] &&
	      !fpu_sqr64_fState_S3$D_OUT[31] &&
	      !fpu_sqr64_fState_S3$D_OUT[30] &&
	      !fpu_sqr64_fState_S3$D_OUT[29] &&
	      !fpu_sqr64_fState_S3$D_OUT[28] &&
	      !fpu_sqr64_fState_S3$D_OUT[27] &&
	      !fpu_sqr64_fState_S3$D_OUT[26] &&
	      !fpu_sqr64_fState_S3$D_OUT[25] &&
	      !fpu_sqr64_fState_S3$D_OUT[24] &&
	      !fpu_sqr64_fState_S3$D_OUT[23] &&
	      !fpu_sqr64_fState_S3$D_OUT[22] &&
	      !fpu_sqr64_fState_S3$D_OUT[21] &&
	      !fpu_sqr64_fState_S3$D_OUT[20] &&
	      !fpu_sqr64_fState_S3$D_OUT[19] &&
	      !fpu_sqr64_fState_S3$D_OUT[18] &&
	      !fpu_sqr64_fState_S3$D_OUT[17] &&
	      !fpu_sqr64_fState_S3$D_OUT[16] &&
	      !fpu_sqr64_fState_S3$D_OUT[15] &&
	      !fpu_sqr64_fState_S3$D_OUT[14] &&
	      !fpu_sqr64_fState_S3$D_OUT[13] &&
	      !fpu_sqr64_fState_S3$D_OUT[12] &&
	      !fpu_sqr64_fState_S3$D_OUT[11] &&
	      !fpu_sqr64_fState_S3$D_OUT[10] &&
	      !fpu_sqr64_fState_S3$D_OUT[9] &&
	      !fpu_sqr64_fState_S3$D_OUT[8] &&
	      !fpu_sqr64_fState_S3$D_OUT[7] &&
	      !fpu_sqr64_fState_S3$D_OUT[6] &&
	      !fpu_sqr64_fState_S3$D_OUT[5] &&
	      !fpu_sqr64_fState_S3$D_OUT[4] &&
	      !fpu_sqr64_fState_S3$D_OUT[3] &&
	      !fpu_sqr64_fState_S3$D_OUT[2] &&
	      !fpu_sqr64_fState_S3$D_OUT[1] &&
	      !fpu_sqr64_fState_S3$D_OUT[0] ||
	      !_0_CONCAT_IF_fpu_sqr64_fState_S3_first__375_BIT_ETC___d1633) ?
	       11'd0 :
	       _theResult___fst_exp__h94828 ;
  assign _theResult___fst_exp__h94837 =
	     (!fpu_sqr64_fState_S3$D_OUT[58] &&
	      fpu_sqr64_fState_S3$D_OUT[57]) ?
	       _theResult___fst_exp__h94789 :
	       _theResult___fst_exp__h94834 ;
  assign _theResult___fst_exp__h95990 =
	     (fpu_sqr64_fState_S4$D_OUT[64:54] == 11'd2047) ?
	       fpu_sqr64_fState_S4$D_OUT[64:54] :
	       _theResult___fst_exp__h95987 ;
  assign _theResult___fst_sfd__h164063 =
	     (_theResult___fst_exp__h163336 == 11'd2047) ?
	       _theResult___snd__h163287[56:5] :
	       _theResult___fst_sfd__h164060 ;
  assign _theResult___fst_sfd__h173653 =
	     (_theResult___fst_exp__h172852 == 11'd2047) ?
	       sfdin__h172846[56:5] :
	       _theResult___fst_sfd__h173650 ;
  assign _theResult___fst_sfd__h182405 =
	     (_theResult___fst_exp__h181653 == 11'd2047) ?
	       _theResult___snd__h181599[56:5] :
	       _theResult___fst_sfd__h182402 ;
  assign _theResult___fst_sfd__h182414 =
	     (iFifo$D_OUT[167:160] == 8'd0) ?
	       (_3970_MINUS_0_CONCAT_IF_iFifo_first__087_BIT_15_ETC___d3189 ?
		  _theResult___snd_fst_sfd__h164066 :
		  _theResult___fst_sfd__h148292) :
	       (SEXT_iFifo_first__087_BITS_167_TO_160_130_MINU_ETC___d3324 ?
		  _theResult___snd_fst_sfd__h182408 :
		  _theResult___fst_sfd__h148292) ;
  assign _theResult___fst_sfd__h182420 =
	     ((iFifo$D_OUT[167:160] == 8'd255 ||
	       iFifo$D_OUT[167:160] == 8'd0) &&
	      iFifo$D_OUT[159:137] == 23'd0) ?
	       52'd0 :
	       _theResult___fst_sfd__h182414 ;
  assign _theResult___fst_sfd__h202701 =
	     (_theResult___fst_exp__h201974 == 11'd2047) ?
	       _theResult___snd__h201925[56:5] :
	       _theResult___fst_sfd__h202698 ;
  assign _theResult___fst_sfd__h212291 =
	     (_theResult___fst_exp__h211490 == 11'd2047) ?
	       sfdin__h211484[56:5] :
	       _theResult___fst_sfd__h212288 ;
  assign _theResult___fst_sfd__h221043 =
	     (_theResult___fst_exp__h220291 == 11'd2047) ?
	       _theResult___snd__h220237[56:5] :
	       _theResult___fst_sfd__h221040 ;
  assign _theResult___fst_sfd__h221052 =
	     (iFifo$D_OUT[102:95] == 8'd0) ?
	       (_3970_MINUS_0_CONCAT_IF_iFifo_first__087_BIT_94_ETC___d4684 ?
		  _theResult___snd_fst_sfd__h202704 :
		  _theResult___fst_sfd__h186932) :
	       (SEXT_iFifo_first__087_BITS_102_TO_95_625_MINUS_ETC___d4807 ?
		  _theResult___snd_fst_sfd__h221046 :
		  _theResult___fst_sfd__h186932) ;
  assign _theResult___fst_sfd__h221058 =
	     ((iFifo$D_OUT[102:95] == 8'd255 ||
	       iFifo$D_OUT[102:95] == 8'd0) &&
	      iFifo$D_OUT[94:72] == 23'd0) ?
	       52'd0 :
	       _theResult___fst_sfd__h221052 ;
  assign _theResult___fst_sfd__h241640 =
	     (_theResult___fst_exp__h240913 == 11'd2047) ?
	       _theResult___snd__h240864[56:5] :
	       _theResult___fst_sfd__h241637 ;
  assign _theResult___fst_sfd__h251230 =
	     (_theResult___fst_exp__h250429 == 11'd2047) ?
	       sfdin__h250423[56:5] :
	       _theResult___fst_sfd__h251227 ;
  assign _theResult___fst_sfd__h259982 =
	     (_theResult___fst_exp__h259230 == 11'd2047) ?
	       _theResult___snd__h259176[56:5] :
	       _theResult___fst_sfd__h259979 ;
  assign _theResult___fst_sfd__h259991 =
	     (iFifo$D_OUT[37:30] == 8'd0) ?
	       (_3970_MINUS_0_CONCAT_IF_iFifo_first__087_BIT_29_ETC___d3909 ?
		  _theResult___snd_fst_sfd__h241643 :
		  _theResult___fst_sfd__h225871) :
	       (SEXT_iFifo_first__087_BITS_37_TO_30_850_MINUS__ETC___d4032 ?
		  _theResult___snd_fst_sfd__h259985 :
		  _theResult___fst_sfd__h225871) ;
  assign _theResult___fst_sfd__h259997 =
	     ((iFifo$D_OUT[37:30] == 8'd255 || iFifo$D_OUT[37:30] == 8'd0) &&
	      iFifo$D_OUT[29:7] == 23'd0) ?
	       52'd0 :
	       _theResult___fst_sfd__h259991 ;
  assign _theResult___fst_sfd__h278284 =
	     (_theResult___fst_exp__h277686 == 8'd255) ?
	       sfdin__h277680[56:34] :
	       _theResult___fst_sfd__h278281 ;
  assign _theResult___fst_sfd__h286866 =
	     (_theResult___fst_exp__h286342 == 8'd255) ?
	       _theResult___snd__h286293[56:34] :
	       _theResult___fst_sfd__h286863 ;
  assign _theResult___fst_sfd__h296050 =
	     (_theResult___fst_exp__h295452 == 8'd255) ?
	       sfdin__h295446[56:34] :
	       _theResult___fst_sfd__h296047 ;
  assign _theResult___fst_sfd__h304686 =
	     (_theResult___fst_exp__h304137 == 8'd255) ?
	       _theResult___snd__h304083[56:34] :
	       _theResult___fst_sfd__h304683 ;
  assign _theResult___fst_sfd__h304695 =
	     (resWire$wget[67:57] == 11'd0) ?
	       (_3074_MINUS_0_CONCAT_IF_resWire_wget__410_BIT_5_ETC___d5532 ?
		  _theResult___snd_fst_sfd__h286869 :
		  _theResult___fst_sfd__h269560) :
	       (SEXT_resWire_wget__410_BITS_67_TO_57_416_MINUS_ETC___d6032 ?
		  _theResult___snd_fst_sfd__h304689 :
		  _theResult___fst_sfd__h269560) ;
  assign _theResult___fst_sfd__h304701 =
	     ((resWire$wget[67:57] == 11'd2047 ||
	       resWire$wget[67:57] == 11'd0) &&
	      resWire$wget[56:5] == 52'd0) ?
	       23'd0 :
	       _theResult___fst_sfd__h304695 ;
  assign _theResult___fst_sfd__h43557 =
	     (fpu_div64_fState_S4$D_OUT[64:54] == 11'd2047) ?
	       fpu_div64_fState_S4$D_OUT[53:2] :
	       _theResult___fst_sfd__h43554 ;
  assign _theResult___fst_sfd__h95991 =
	     (fpu_sqr64_fState_S4$D_OUT[64:54] == 11'd2047) ?
	       fpu_sqr64_fState_S4$D_OUT[53:2] :
	       _theResult___fst_sfd__h95988 ;
  assign _theResult___fst_sfd__h96608 =
	     fpu_madd_fOperand_S0$D_OUT[195] ?
	       fpu_madd_fOperand_S0$D_OUT[182:131] :
	       52'd0 ;
  assign _theResult___sfd__h142542 =
	     sfd__h142040[53] ?
	       ((fpu_madd_fState_S8$D_OUT[65:55] == 11'd2046) ?
		  52'd0 :
		  sfd__h142040[52:1]) :
	       sfd__h142040[51:0] ;
  assign _theResult___sfd__h163982 =
	     sfd__h163354[53] ?
	       ((_theResult___fst_exp__h163336 == 11'd2046) ?
		  52'd0 :
		  sfd__h163354[52:1]) :
	       sfd__h163354[51:0] ;
  assign _theResult___sfd__h173572 =
	     sfd__h172944[53] ?
	       ((_theResult___fst_exp__h172852 == 11'd2046) ?
		  52'd0 :
		  sfd__h172944[52:1]) :
	       sfd__h172944[51:0] ;
  assign _theResult___sfd__h182324 =
	     sfd__h181672[53] ?
	       ((_theResult___fst_exp__h181653 == 11'd2046) ?
		  52'd0 :
		  sfd__h181672[52:1]) :
	       sfd__h181672[51:0] ;
  assign _theResult___sfd__h202620 =
	     sfd__h201992[53] ?
	       ((_theResult___fst_exp__h201974 == 11'd2046) ?
		  52'd0 :
		  sfd__h201992[52:1]) :
	       sfd__h201992[51:0] ;
  assign _theResult___sfd__h212210 =
	     sfd__h211582[53] ?
	       ((_theResult___fst_exp__h211490 == 11'd2046) ?
		  52'd0 :
		  sfd__h211582[52:1]) :
	       sfd__h211582[51:0] ;
  assign _theResult___sfd__h220962 =
	     sfd__h220310[53] ?
	       ((_theResult___fst_exp__h220291 == 11'd2046) ?
		  52'd0 :
		  sfd__h220310[52:1]) :
	       sfd__h220310[51:0] ;
  assign _theResult___sfd__h241559 =
	     sfd__h240931[53] ?
	       ((_theResult___fst_exp__h240913 == 11'd2046) ?
		  52'd0 :
		  sfd__h240931[52:1]) :
	       sfd__h240931[51:0] ;
  assign _theResult___sfd__h251149 =
	     sfd__h250521[53] ?
	       ((_theResult___fst_exp__h250429 == 11'd2046) ?
		  52'd0 :
		  sfd__h250521[52:1]) :
	       sfd__h250521[51:0] ;
  assign _theResult___sfd__h259901 =
	     sfd__h259249[53] ?
	       ((_theResult___fst_exp__h259230 == 11'd2046) ?
		  52'd0 :
		  sfd__h259249[52:1]) :
	       sfd__h259249[51:0] ;
  assign _theResult___sfd__h278203 =
	     sfd__h277778[24] ?
	       ((_theResult___fst_exp__h277686 == 8'd254) ?
		  23'd0 :
		  sfd__h277778[23:1]) :
	       sfd__h277778[22:0] ;
  assign _theResult___sfd__h286785 =
	     sfd__h286360[24] ?
	       ((_theResult___fst_exp__h286342 == 8'd254) ?
		  23'd0 :
		  sfd__h286360[23:1]) :
	       sfd__h286360[22:0] ;
  assign _theResult___sfd__h295969 =
	     sfd__h295544[24] ?
	       ((_theResult___fst_exp__h295452 == 8'd254) ?
		  23'd0 :
		  sfd__h295544[23:1]) :
	       sfd__h295544[22:0] ;
  assign _theResult___sfd__h304605 =
	     sfd__h304156[24] ?
	       ((_theResult___fst_exp__h304137 == 8'd254) ?
		  23'd0 :
		  sfd__h304156[23:1]) :
	       sfd__h304156[22:0] ;
  assign _theResult___sfd__h43476 =
	     sfd__h42982[53] ?
	       ((fpu_div64_fState_S4$D_OUT[64:54] == 11'd2046) ?
		  52'd0 :
		  sfd__h42982[52:1]) :
	       sfd__h42982[51:0] ;
  assign _theResult___sfd__h95910 =
	     sfd__h95416[53] ?
	       ((fpu_sqr64_fState_S4$D_OUT[64:54] == 11'd2046) ?
		  52'd0 :
		  sfd__h95416[52:1]) :
	       sfd__h95416[51:0] ;
  assign _theResult___snd__h130966 = { sfdBC__h115662[104:0], 1'd0 } ;
  assign _theResult___snd__h130980 =
	     (!sfdBC__h115662[105] && sfdBC__h115662[104]) ?
	       _theResult___snd__h130982 :
	       _theResult___snd__h130994 ;
  assign _theResult___snd__h130982 = { sfdBC__h115662[103:0], 2'd0 } ;
  assign _theResult___snd__h130994 =
	     (!sfdBC__h115662[105] && !sfdBC__h115662[104] &&
	      !sfdBC__h115662[103] &&
	      !sfdBC__h115662[102] &&
	      !sfdBC__h115662[101] &&
	      !sfdBC__h115662[100] &&
	      !sfdBC__h115662[99] &&
	      !sfdBC__h115662[98] &&
	      !sfdBC__h115662[97] &&
	      !sfdBC__h115662[96] &&
	      !sfdBC__h115662[95] &&
	      !sfdBC__h115662[94] &&
	      !sfdBC__h115662[93] &&
	      !sfdBC__h115662[92] &&
	      !sfdBC__h115662[91] &&
	      !sfdBC__h115662[90] &&
	      !sfdBC__h115662[89] &&
	      !sfdBC__h115662[88] &&
	      !sfdBC__h115662[87] &&
	      !sfdBC__h115662[86] &&
	      !sfdBC__h115662[85] &&
	      !sfdBC__h115662[84] &&
	      !sfdBC__h115662[83] &&
	      !sfdBC__h115662[82] &&
	      !sfdBC__h115662[81] &&
	      !sfdBC__h115662[80] &&
	      !sfdBC__h115662[79] &&
	      !sfdBC__h115662[78] &&
	      !sfdBC__h115662[77] &&
	      !sfdBC__h115662[76] &&
	      !sfdBC__h115662[75] &&
	      !sfdBC__h115662[74] &&
	      !sfdBC__h115662[73] &&
	      !sfdBC__h115662[72] &&
	      !sfdBC__h115662[71] &&
	      !sfdBC__h115662[70] &&
	      !sfdBC__h115662[69] &&
	      !sfdBC__h115662[68] &&
	      !sfdBC__h115662[67] &&
	      !sfdBC__h115662[66] &&
	      !sfdBC__h115662[65] &&
	      !sfdBC__h115662[64] &&
	      !sfdBC__h115662[63] &&
	      !sfdBC__h115662[62] &&
	      !sfdBC__h115662[61] &&
	      !sfdBC__h115662[60] &&
	      !sfdBC__h115662[59] &&
	      !sfdBC__h115662[58] &&
	      !sfdBC__h115662[57] &&
	      !sfdBC__h115662[56] &&
	      !sfdBC__h115662[55] &&
	      !sfdBC__h115662[54] &&
	      !sfdBC__h115662[53] &&
	      !sfdBC__h115662[52] &&
	      !sfdBC__h115662[51] &&
	      !sfdBC__h115662[50] &&
	      !sfdBC__h115662[49] &&
	      !sfdBC__h115662[48] &&
	      !sfdBC__h115662[47] &&
	      !sfdBC__h115662[46] &&
	      !sfdBC__h115662[45] &&
	      !sfdBC__h115662[44] &&
	      !sfdBC__h115662[43] &&
	      !sfdBC__h115662[42] &&
	      !sfdBC__h115662[41] &&
	      !sfdBC__h115662[40] &&
	      !sfdBC__h115662[39] &&
	      !sfdBC__h115662[38] &&
	      !sfdBC__h115662[37] &&
	      !sfdBC__h115662[36] &&
	      !sfdBC__h115662[35] &&
	      !sfdBC__h115662[34] &&
	      !sfdBC__h115662[33] &&
	      !sfdBC__h115662[32] &&
	      !sfdBC__h115662[31] &&
	      !sfdBC__h115662[30] &&
	      !sfdBC__h115662[29] &&
	      !sfdBC__h115662[28] &&
	      !sfdBC__h115662[27] &&
	      !sfdBC__h115662[26] &&
	      !sfdBC__h115662[25] &&
	      !sfdBC__h115662[24] &&
	      !sfdBC__h115662[23] &&
	      !sfdBC__h115662[22] &&
	      !sfdBC__h115662[21] &&
	      !sfdBC__h115662[20] &&
	      !sfdBC__h115662[19] &&
	      !sfdBC__h115662[18] &&
	      !sfdBC__h115662[17] &&
	      !sfdBC__h115662[16] &&
	      !sfdBC__h115662[15] &&
	      !sfdBC__h115662[14] &&
	      !sfdBC__h115662[13] &&
	      !sfdBC__h115662[12] &&
	      !sfdBC__h115662[11] &&
	      !sfdBC__h115662[10] &&
	      !sfdBC__h115662[9] &&
	      !sfdBC__h115662[8] &&
	      !sfdBC__h115662[7] &&
	      !sfdBC__h115662[6] &&
	      !sfdBC__h115662[5] &&
	      !sfdBC__h115662[4] &&
	      !sfdBC__h115662[3] &&
	      !sfdBC__h115662[2] &&
	      !sfdBC__h115662[1] &&
	      !sfdBC__h115662[0]) ?
	       sfdBC__h115662 :
	       _theResult___snd__h131000 ;
  assign _theResult___snd__h131000 =
	     { IF_0_CONCAT_IF_IF_7170_MINUS_fpu_madd_fState_S_ETC__q24[103:0],
	       2'd0 } ;
  assign _theResult___snd__h131018 =
	     sfdBC__h115662 <<
	     IF_IF_7170_MINUS_fpu_madd_fState_S3_first__995_ETC___d2462 ;
  assign _theResult___snd__h131023 =
	     sfdBC__h115662 <<
	     IF_IF_7170_MINUS_fpu_madd_fState_S3_first__995_ETC___d2460 ;
  assign _theResult___snd__h141392 = { sfd__h133119[55:0], 1'd0 } ;
  assign _theResult___snd__h141406 =
	     (!sfd__h133119[56] && sfd__h133119[55]) ?
	       _theResult___snd__h141408 :
	       _theResult___snd__h141420 ;
  assign _theResult___snd__h141408 = { sfd__h133119[54:0], 2'd0 } ;
  assign _theResult___snd__h141420 =
	     (!sfd__h133119[56] && !sfd__h133119[55] && !sfd__h133119[54] &&
	      !sfd__h133119[53] &&
	      !sfd__h133119[52] &&
	      !sfd__h133119[51] &&
	      !sfd__h133119[50] &&
	      !sfd__h133119[49] &&
	      !sfd__h133119[48] &&
	      !sfd__h133119[47] &&
	      !sfd__h133119[46] &&
	      !sfd__h133119[45] &&
	      !sfd__h133119[44] &&
	      !sfd__h133119[43] &&
	      !sfd__h133119[42] &&
	      !sfd__h133119[41] &&
	      !sfd__h133119[40] &&
	      !sfd__h133119[39] &&
	      !sfd__h133119[38] &&
	      !sfd__h133119[37] &&
	      !sfd__h133119[36] &&
	      !sfd__h133119[35] &&
	      !sfd__h133119[34] &&
	      !sfd__h133119[33] &&
	      !sfd__h133119[32] &&
	      !sfd__h133119[31] &&
	      !sfd__h133119[30] &&
	      !sfd__h133119[29] &&
	      !sfd__h133119[28] &&
	      !sfd__h133119[27] &&
	      !sfd__h133119[26] &&
	      !sfd__h133119[25] &&
	      !sfd__h133119[24] &&
	      !sfd__h133119[23] &&
	      !sfd__h133119[22] &&
	      !sfd__h133119[21] &&
	      !sfd__h133119[20] &&
	      !sfd__h133119[19] &&
	      !sfd__h133119[18] &&
	      !sfd__h133119[17] &&
	      !sfd__h133119[16] &&
	      !sfd__h133119[15] &&
	      !sfd__h133119[14] &&
	      !sfd__h133119[13] &&
	      !sfd__h133119[12] &&
	      !sfd__h133119[11] &&
	      !sfd__h133119[10] &&
	      !sfd__h133119[9] &&
	      !sfd__h133119[8] &&
	      !sfd__h133119[7] &&
	      !sfd__h133119[6] &&
	      !sfd__h133119[5] &&
	      !sfd__h133119[4] &&
	      !sfd__h133119[3] &&
	      !sfd__h133119[2] &&
	      !sfd__h133119[1] &&
	      !sfd__h133119[0]) ?
	       sfd__h133119 :
	       _theResult___snd__h141426 ;
  assign _theResult___snd__h141426 =
	     { IF_0_CONCAT_IF_IF_fpu_madd_fState_S7_first__65_ETC__q29[54:0],
	       2'd0 } ;
  assign _theResult___snd__h141444 =
	     sfd__h133119 <<
	     IF_fpu_madd_fState_S7_first__651_BITS_126_TO_1_ETC___d2903 ;
  assign _theResult___snd__h141449 =
	     sfd__h133119 <<
	     IF_IF_fpu_madd_fState_S7_first__651_BIT_128_65_ETC___d2901 ;
  assign _theResult___snd__h163287 =
	     (iFifo$D_OUT[167:160] == 8'd0) ?
	       _theResult___snd__h163296 :
	       _theResult___snd__h163289 ;
  assign _theResult___snd__h163289 = { iFifo$D_OUT[159:137], 34'd0 } ;
  assign _theResult___snd__h163296 =
	     (iFifo$D_OUT[167:160] == 8'd0 && !iFifo$D_OUT[159] &&
	      NOT_iFifo_first__087_BIT_158_142_202_AND_NOT_i_ETC___d3244) ?
	       sfd__h144536 :
	       _theResult___snd__h163302 ;
  assign _theResult___snd__h163302 =
	     { IF_0_CONCAT_IF_iFifo_first__087_BITS_167_TO_16_ETC__q33[54:0],
	       2'd0 } ;
  assign _theResult___snd__h163325 =
	     sfd__h144536 <<
	     IF_iFifo_first__087_BITS_167_TO_160_130_EQ_0_1_ETC___d3271 ;
  assign _theResult___snd__h172863 = { _theResult____h164614[55:0], 1'd0 } ;
  assign _theResult___snd__h172874 =
	     (!_theResult____h164614[56] && _theResult____h164614[55]) ?
	       _theResult___snd__h172876 :
	       _theResult___snd__h172886 ;
  assign _theResult___snd__h172876 = { _theResult____h164614[54:0], 2'd0 } ;
  assign _theResult___snd__h172886 =
	     (!_theResult____h164614[56] && !_theResult____h164614[55] &&
	      !_theResult____h164614[54] &&
	      !_theResult____h164614[53] &&
	      !_theResult____h164614[52] &&
	      !_theResult____h164614[51] &&
	      !_theResult____h164614[50] &&
	      !_theResult____h164614[49] &&
	      !_theResult____h164614[48] &&
	      !_theResult____h164614[47] &&
	      !_theResult____h164614[46] &&
	      !_theResult____h164614[45] &&
	      !_theResult____h164614[44] &&
	      !_theResult____h164614[43] &&
	      !_theResult____h164614[42] &&
	      !_theResult____h164614[41] &&
	      !_theResult____h164614[40] &&
	      !_theResult____h164614[39] &&
	      !_theResult____h164614[38] &&
	      !_theResult____h164614[37] &&
	      !_theResult____h164614[36] &&
	      !_theResult____h164614[35] &&
	      !_theResult____h164614[34] &&
	      !_theResult____h164614[33] &&
	      !_theResult____h164614[32] &&
	      !_theResult____h164614[31] &&
	      !_theResult____h164614[30] &&
	      !_theResult____h164614[29] &&
	      !_theResult____h164614[28] &&
	      !_theResult____h164614[27] &&
	      !_theResult____h164614[26] &&
	      !_theResult____h164614[25] &&
	      !_theResult____h164614[24] &&
	      !_theResult____h164614[23] &&
	      !_theResult____h164614[22] &&
	      !_theResult____h164614[21] &&
	      !_theResult____h164614[20] &&
	      !_theResult____h164614[19] &&
	      !_theResult____h164614[18] &&
	      !_theResult____h164614[17] &&
	      !_theResult____h164614[16] &&
	      !_theResult____h164614[15] &&
	      !_theResult____h164614[14] &&
	      !_theResult____h164614[13] &&
	      !_theResult____h164614[12] &&
	      !_theResult____h164614[11] &&
	      !_theResult____h164614[10] &&
	      !_theResult____h164614[9] &&
	      !_theResult____h164614[8] &&
	      !_theResult____h164614[7] &&
	      !_theResult____h164614[6] &&
	      !_theResult____h164614[5] &&
	      !_theResult____h164614[4] &&
	      !_theResult____h164614[3] &&
	      !_theResult____h164614[2] &&
	      !_theResult____h164614[1] &&
	      !_theResult____h164614[0]) ?
	       _theResult____h164614 :
	       _theResult___snd__h172892 ;
  assign _theResult___snd__h172892 =
	     { IF_0_CONCAT_IF_IF_3074_MINUS_SEXT_iFifo_first__ETC__q37[54:0],
	       2'd0 } ;
  assign _theResult___snd__h172915 =
	     _theResult____h164614 <<
	     IF_IF_3074_MINUS_SEXT_iFifo_first__087_BITS_16_ETC___d3572 ;
  assign _theResult___snd__h181599 =
	     (iFifo$D_OUT[167:160] == 8'd0) ?
	       _theResult___snd__h181613 :
	       _theResult___snd__h163289 ;
  assign _theResult___snd__h181613 =
	     (iFifo$D_OUT[167:160] == 8'd0 && !iFifo$D_OUT[159] &&
	      NOT_iFifo_first__087_BIT_158_142_202_AND_NOT_i_ETC___d3244) ?
	       sfd__h144536 :
	       _theResult___snd__h181619 ;
  assign _theResult___snd__h181619 =
	     { IF_0_CONCAT_IF_iFifo_first__087_BITS_167_TO_16_ETC__q40[54:0],
	       2'd0 } ;
  assign _theResult___snd__h181637 =
	     sfd__h144536 <<
	     IF_SEXT_iFifo_first__087_BITS_167_TO_160_130_M_ETC___d3623 ;
  assign _theResult___snd__h201925 =
	     (iFifo$D_OUT[102:95] == 8'd0) ?
	       _theResult___snd__h201934 :
	       _theResult___snd__h201927 ;
  assign _theResult___snd__h201927 = { iFifo$D_OUT[94:72], 34'd0 } ;
  assign _theResult___snd__h201934 =
	     (iFifo$D_OUT[102:95] == 8'd0 && !iFifo$D_OUT[94] &&
	      NOT_iFifo_first__087_BIT_93_637_688_AND_NOT_iF_ETC___d4730) ?
	       sfd__h183176 :
	       _theResult___snd__h201940 ;
  assign _theResult___snd__h201940 =
	     { IF_0_CONCAT_IF_iFifo_first__087_BITS_102_TO_95_ETC__q93[54:0],
	       2'd0 } ;
  assign _theResult___snd__h201963 =
	     sfd__h183176 <<
	     IF_iFifo_first__087_BITS_102_TO_95_625_EQ_0_63_ETC___d4757 ;
  assign _theResult___snd__h211501 = { _theResult____h203252[55:0], 1'd0 } ;
  assign _theResult___snd__h211512 =
	     (!_theResult____h203252[56] && _theResult____h203252[55]) ?
	       _theResult___snd__h211514 :
	       _theResult___snd__h211524 ;
  assign _theResult___snd__h211514 = { _theResult____h203252[54:0], 2'd0 } ;
  assign _theResult___snd__h211524 =
	     (!_theResult____h203252[56] && !_theResult____h203252[55] &&
	      !_theResult____h203252[54] &&
	      !_theResult____h203252[53] &&
	      !_theResult____h203252[52] &&
	      !_theResult____h203252[51] &&
	      !_theResult____h203252[50] &&
	      !_theResult____h203252[49] &&
	      !_theResult____h203252[48] &&
	      !_theResult____h203252[47] &&
	      !_theResult____h203252[46] &&
	      !_theResult____h203252[45] &&
	      !_theResult____h203252[44] &&
	      !_theResult____h203252[43] &&
	      !_theResult____h203252[42] &&
	      !_theResult____h203252[41] &&
	      !_theResult____h203252[40] &&
	      !_theResult____h203252[39] &&
	      !_theResult____h203252[38] &&
	      !_theResult____h203252[37] &&
	      !_theResult____h203252[36] &&
	      !_theResult____h203252[35] &&
	      !_theResult____h203252[34] &&
	      !_theResult____h203252[33] &&
	      !_theResult____h203252[32] &&
	      !_theResult____h203252[31] &&
	      !_theResult____h203252[30] &&
	      !_theResult____h203252[29] &&
	      !_theResult____h203252[28] &&
	      !_theResult____h203252[27] &&
	      !_theResult____h203252[26] &&
	      !_theResult____h203252[25] &&
	      !_theResult____h203252[24] &&
	      !_theResult____h203252[23] &&
	      !_theResult____h203252[22] &&
	      !_theResult____h203252[21] &&
	      !_theResult____h203252[20] &&
	      !_theResult____h203252[19] &&
	      !_theResult____h203252[18] &&
	      !_theResult____h203252[17] &&
	      !_theResult____h203252[16] &&
	      !_theResult____h203252[15] &&
	      !_theResult____h203252[14] &&
	      !_theResult____h203252[13] &&
	      !_theResult____h203252[12] &&
	      !_theResult____h203252[11] &&
	      !_theResult____h203252[10] &&
	      !_theResult____h203252[9] &&
	      !_theResult____h203252[8] &&
	      !_theResult____h203252[7] &&
	      !_theResult____h203252[6] &&
	      !_theResult____h203252[5] &&
	      !_theResult____h203252[4] &&
	      !_theResult____h203252[3] &&
	      !_theResult____h203252[2] &&
	      !_theResult____h203252[1] &&
	      !_theResult____h203252[0]) ?
	       _theResult____h203252 :
	       _theResult___snd__h211530 ;
  assign _theResult___snd__h211530 =
	     { IF_0_CONCAT_IF_IF_3074_MINUS_SEXT_iFifo_first__ETC__q97[54:0],
	       2'd0 } ;
  assign _theResult___snd__h211553 =
	     _theResult____h203252 <<
	     IF_IF_3074_MINUS_SEXT_iFifo_first__087_BITS_10_ETC___d5055 ;
  assign _theResult___snd__h220237 =
	     (iFifo$D_OUT[102:95] == 8'd0) ?
	       _theResult___snd__h220251 :
	       _theResult___snd__h201927 ;
  assign _theResult___snd__h220251 =
	     (iFifo$D_OUT[102:95] == 8'd0 && !iFifo$D_OUT[94] &&
	      NOT_iFifo_first__087_BIT_93_637_688_AND_NOT_iF_ETC___d4730) ?
	       sfd__h183176 :
	       _theResult___snd__h220257 ;
  assign _theResult___snd__h220257 =
	     { IF_0_CONCAT_IF_iFifo_first__087_BITS_102_TO_95_ETC__q100[54:0],
	       2'd0 } ;
  assign _theResult___snd__h220275 =
	     sfd__h183176 <<
	     IF_SEXT_iFifo_first__087_BITS_102_TO_95_625_MI_ETC___d5106 ;
  assign _theResult___snd__h240864 =
	     (iFifo$D_OUT[37:30] == 8'd0) ?
	       _theResult___snd__h240873 :
	       _theResult___snd__h240866 ;
  assign _theResult___snd__h240866 = { iFifo$D_OUT[29:7], 34'd0 } ;
  assign _theResult___snd__h240873 =
	     (iFifo$D_OUT[37:30] == 8'd0 && !iFifo$D_OUT[29] &&
	      NOT_iFifo_first__087_BIT_28_862_913_AND_NOT_iF_ETC___d3955) ?
	       sfd__h222115 :
	       _theResult___snd__h240879 ;
  assign _theResult___snd__h240879 =
	     { IF_0_CONCAT_IF_iFifo_first__087_BITS_37_TO_30__ETC__q60[54:0],
	       2'd0 } ;
  assign _theResult___snd__h240902 =
	     sfd__h222115 <<
	     IF_iFifo_first__087_BITS_37_TO_30_850_EQ_0_856_ETC___d3982 ;
  assign _theResult___snd__h250440 = { _theResult____h242191[55:0], 1'd0 } ;
  assign _theResult___snd__h250451 =
	     (!_theResult____h242191[56] && _theResult____h242191[55]) ?
	       _theResult___snd__h250453 :
	       _theResult___snd__h250463 ;
  assign _theResult___snd__h250453 = { _theResult____h242191[54:0], 2'd0 } ;
  assign _theResult___snd__h250463 =
	     (!_theResult____h242191[56] && !_theResult____h242191[55] &&
	      !_theResult____h242191[54] &&
	      !_theResult____h242191[53] &&
	      !_theResult____h242191[52] &&
	      !_theResult____h242191[51] &&
	      !_theResult____h242191[50] &&
	      !_theResult____h242191[49] &&
	      !_theResult____h242191[48] &&
	      !_theResult____h242191[47] &&
	      !_theResult____h242191[46] &&
	      !_theResult____h242191[45] &&
	      !_theResult____h242191[44] &&
	      !_theResult____h242191[43] &&
	      !_theResult____h242191[42] &&
	      !_theResult____h242191[41] &&
	      !_theResult____h242191[40] &&
	      !_theResult____h242191[39] &&
	      !_theResult____h242191[38] &&
	      !_theResult____h242191[37] &&
	      !_theResult____h242191[36] &&
	      !_theResult____h242191[35] &&
	      !_theResult____h242191[34] &&
	      !_theResult____h242191[33] &&
	      !_theResult____h242191[32] &&
	      !_theResult____h242191[31] &&
	      !_theResult____h242191[30] &&
	      !_theResult____h242191[29] &&
	      !_theResult____h242191[28] &&
	      !_theResult____h242191[27] &&
	      !_theResult____h242191[26] &&
	      !_theResult____h242191[25] &&
	      !_theResult____h242191[24] &&
	      !_theResult____h242191[23] &&
	      !_theResult____h242191[22] &&
	      !_theResult____h242191[21] &&
	      !_theResult____h242191[20] &&
	      !_theResult____h242191[19] &&
	      !_theResult____h242191[18] &&
	      !_theResult____h242191[17] &&
	      !_theResult____h242191[16] &&
	      !_theResult____h242191[15] &&
	      !_theResult____h242191[14] &&
	      !_theResult____h242191[13] &&
	      !_theResult____h242191[12] &&
	      !_theResult____h242191[11] &&
	      !_theResult____h242191[10] &&
	      !_theResult____h242191[9] &&
	      !_theResult____h242191[8] &&
	      !_theResult____h242191[7] &&
	      !_theResult____h242191[6] &&
	      !_theResult____h242191[5] &&
	      !_theResult____h242191[4] &&
	      !_theResult____h242191[3] &&
	      !_theResult____h242191[2] &&
	      !_theResult____h242191[1] &&
	      !_theResult____h242191[0]) ?
	       _theResult____h242191 :
	       _theResult___snd__h250469 ;
  assign _theResult___snd__h250469 =
	     { IF_0_CONCAT_IF_IF_3074_MINUS_SEXT_iFifo_first__ETC__q64[54:0],
	       2'd0 } ;
  assign _theResult___snd__h250492 =
	     _theResult____h242191 <<
	     IF_IF_3074_MINUS_SEXT_iFifo_first__087_BITS_37_ETC___d4280 ;
  assign _theResult___snd__h259176 =
	     (iFifo$D_OUT[37:30] == 8'd0) ?
	       _theResult___snd__h259190 :
	       _theResult___snd__h240866 ;
  assign _theResult___snd__h259190 =
	     (iFifo$D_OUT[37:30] == 8'd0 && !iFifo$D_OUT[29] &&
	      NOT_iFifo_first__087_BIT_28_862_913_AND_NOT_iF_ETC___d3955) ?
	       sfd__h222115 :
	       _theResult___snd__h259196 ;
  assign _theResult___snd__h259196 =
	     { IF_0_CONCAT_IF_iFifo_first__087_BITS_37_TO_30__ETC__q67[54:0],
	       2'd0 } ;
  assign _theResult___snd__h259214 =
	     sfd__h222115 <<
	     IF_SEXT_iFifo_first__087_BITS_37_TO_30_850_MIN_ETC___d4331 ;
  assign _theResult___snd__h277697 = { _theResult____h269577[55:0], 1'd0 } ;
  assign _theResult___snd__h277708 =
	     (!_theResult____h269577[56] && _theResult____h269577[55]) ?
	       _theResult___snd__h277710 :
	       _theResult___snd__h277720 ;
  assign _theResult___snd__h277710 = { _theResult____h269577[54:0], 2'd0 } ;
  assign _theResult___snd__h277720 =
	     (!_theResult____h269577[56] && !_theResult____h269577[55] &&
	      !_theResult____h269577[54] &&
	      !_theResult____h269577[53] &&
	      !_theResult____h269577[52] &&
	      !_theResult____h269577[51] &&
	      !_theResult____h269577[50] &&
	      !_theResult____h269577[49] &&
	      !_theResult____h269577[48] &&
	      !_theResult____h269577[47] &&
	      !_theResult____h269577[46] &&
	      !_theResult____h269577[45] &&
	      !_theResult____h269577[44] &&
	      !_theResult____h269577[43] &&
	      !_theResult____h269577[42] &&
	      !_theResult____h269577[41] &&
	      !_theResult____h269577[40] &&
	      !_theResult____h269577[39] &&
	      !_theResult____h269577[38] &&
	      !_theResult____h269577[37] &&
	      !_theResult____h269577[36] &&
	      !_theResult____h269577[35] &&
	      !_theResult____h269577[34] &&
	      !_theResult____h269577[33] &&
	      !_theResult____h269577[32] &&
	      !_theResult____h269577[31] &&
	      !_theResult____h269577[30] &&
	      !_theResult____h269577[29] &&
	      !_theResult____h269577[28] &&
	      !_theResult____h269577[27] &&
	      !_theResult____h269577[26] &&
	      !_theResult____h269577[25] &&
	      !_theResult____h269577[24] &&
	      !_theResult____h269577[23] &&
	      !_theResult____h269577[22] &&
	      !_theResult____h269577[21] &&
	      !_theResult____h269577[20] &&
	      !_theResult____h269577[19] &&
	      !_theResult____h269577[18] &&
	      !_theResult____h269577[17] &&
	      !_theResult____h269577[16] &&
	      !_theResult____h269577[15] &&
	      !_theResult____h269577[14] &&
	      !_theResult____h269577[13] &&
	      !_theResult____h269577[12] &&
	      !_theResult____h269577[11] &&
	      !_theResult____h269577[10] &&
	      !_theResult____h269577[9] &&
	      !_theResult____h269577[8] &&
	      !_theResult____h269577[7] &&
	      !_theResult____h269577[6] &&
	      !_theResult____h269577[5] &&
	      !_theResult____h269577[4] &&
	      !_theResult____h269577[3] &&
	      !_theResult____h269577[2] &&
	      !_theResult____h269577[1] &&
	      !_theResult____h269577[0]) ?
	       _theResult____h269577 :
	       _theResult___snd__h277726 ;
  assign _theResult___snd__h277726 =
	     { IF_0_CONCAT_IF_IF_0b0_CONCAT_NOT_resWire_wget__ETC__q133[54:0],
	       2'd0 } ;
  assign _theResult___snd__h277749 =
	     _theResult____h269577 <<
	     IF_IF_0b0_CONCAT_NOT_resWire_wget__410_BITS_67_ETC___d5767 ;
  assign _theResult___snd__h286293 =
	     (resWire$wget[67:57] == 11'd0) ?
	       _theResult___snd__h286302 :
	       _theResult___snd__h286295 ;
  assign _theResult___snd__h286295 = { resWire$wget[56:5], 5'd0 } ;
  assign _theResult___snd__h286302 =
	     (resWire$wget[67:57] == 11'd0 &&
	      NOT_resWire_wget__410_BIT_56_426_825_AND_NOT_r_ETC___d5927) ?
	       sfd__h261975 :
	       _theResult___snd__h286308 ;
  assign _theResult___snd__h286308 =
	     { IF_0_CONCAT_IF_resWire_wget__410_BITS_67_TO_57_ETC__q135[54:0],
	       2'd0 } ;
  assign _theResult___snd__h286331 =
	     sfd__h261975 <<
	     IF_resWire_wget__410_BITS_67_TO_57_416_EQ_0_42_ETC___d5982 ;
  assign _theResult___snd__h295463 = { _theResult____h287214[55:0], 1'd0 } ;
  assign _theResult___snd__h295474 =
	     (!_theResult____h287214[56] && _theResult____h287214[55]) ?
	       _theResult___snd__h295476 :
	       _theResult___snd__h295486 ;
  assign _theResult___snd__h295476 = { _theResult____h287214[54:0], 2'd0 } ;
  assign _theResult___snd__h295486 =
	     (!_theResult____h287214[56] && !_theResult____h287214[55] &&
	      !_theResult____h287214[54] &&
	      !_theResult____h287214[53] &&
	      !_theResult____h287214[52] &&
	      !_theResult____h287214[51] &&
	      !_theResult____h287214[50] &&
	      !_theResult____h287214[49] &&
	      !_theResult____h287214[48] &&
	      !_theResult____h287214[47] &&
	      !_theResult____h287214[46] &&
	      !_theResult____h287214[45] &&
	      !_theResult____h287214[44] &&
	      !_theResult____h287214[43] &&
	      !_theResult____h287214[42] &&
	      !_theResult____h287214[41] &&
	      !_theResult____h287214[40] &&
	      !_theResult____h287214[39] &&
	      !_theResult____h287214[38] &&
	      !_theResult____h287214[37] &&
	      !_theResult____h287214[36] &&
	      !_theResult____h287214[35] &&
	      !_theResult____h287214[34] &&
	      !_theResult____h287214[33] &&
	      !_theResult____h287214[32] &&
	      !_theResult____h287214[31] &&
	      !_theResult____h287214[30] &&
	      !_theResult____h287214[29] &&
	      !_theResult____h287214[28] &&
	      !_theResult____h287214[27] &&
	      !_theResult____h287214[26] &&
	      !_theResult____h287214[25] &&
	      !_theResult____h287214[24] &&
	      !_theResult____h287214[23] &&
	      !_theResult____h287214[22] &&
	      !_theResult____h287214[21] &&
	      !_theResult____h287214[20] &&
	      !_theResult____h287214[19] &&
	      !_theResult____h287214[18] &&
	      !_theResult____h287214[17] &&
	      !_theResult____h287214[16] &&
	      !_theResult____h287214[15] &&
	      !_theResult____h287214[14] &&
	      !_theResult____h287214[13] &&
	      !_theResult____h287214[12] &&
	      !_theResult____h287214[11] &&
	      !_theResult____h287214[10] &&
	      !_theResult____h287214[9] &&
	      !_theResult____h287214[8] &&
	      !_theResult____h287214[7] &&
	      !_theResult____h287214[6] &&
	      !_theResult____h287214[5] &&
	      !_theResult____h287214[4] &&
	      !_theResult____h287214[3] &&
	      !_theResult____h287214[2] &&
	      !_theResult____h287214[1] &&
	      !_theResult____h287214[0]) ?
	       _theResult____h287214 :
	       _theResult___snd__h295492 ;
  assign _theResult___snd__h295492 =
	     { IF_0_CONCAT_IF_IF_3970_MINUS_SEXT_resWire_wget_ETC__q139[54:0],
	       2'd0 } ;
  assign _theResult___snd__h295515 =
	     _theResult____h287214 <<
	     IF_IF_3970_MINUS_SEXT_resWire_wget__410_BITS_6_ETC___d6278 ;
  assign _theResult___snd__h304083 =
	     (resWire$wget[67:57] == 11'd0) ?
	       _theResult___snd__h304097 :
	       _theResult___snd__h286295 ;
  assign _theResult___snd__h304097 =
	     (resWire$wget[67:57] == 11'd0 &&
	      NOT_resWire_wget__410_BIT_56_426_825_AND_NOT_r_ETC___d5927) ?
	       sfd__h261975 :
	       _theResult___snd__h304103 ;
  assign _theResult___snd__h304103 =
	     { IF_0_CONCAT_IF_resWire_wget__410_BITS_67_TO_57_ETC__q142[54:0],
	       2'd0 } ;
  assign _theResult___snd__h304121 =
	     sfd__h261975 <<
	     IF_SEXT_resWire_wget__410_BITS_67_TO_57_416_MI_ETC___d6332 ;
  assign _theResult___snd__h34715 =
	     { fpu_div64_fState_S3$D_OUT[56:0], 1'd0 } ;
  assign _theResult___snd__h42350 = { sfdin__h34118[56:0], 1'd0 } ;
  assign _theResult___snd__h42365 =
	     (!sfdin__h34118[57] && sfdin__h34118[56]) ?
	       _theResult___snd__h42367 :
	       _theResult___snd__h42380 ;
  assign _theResult___snd__h42367 = { sfdin__h34118[55:0], 2'd0 } ;
  assign _theResult___snd__h42380 =
	     (!sfdin__h34118[57] && !sfdin__h34118[56] &&
	      !sfdin__h34118[55] &&
	      !sfdin__h34118[54] &&
	      !sfdin__h34118[53] &&
	      !sfdin__h34118[52] &&
	      !sfdin__h34118[51] &&
	      !sfdin__h34118[50] &&
	      !sfdin__h34118[49] &&
	      !sfdin__h34118[48] &&
	      !sfdin__h34118[47] &&
	      !sfdin__h34118[46] &&
	      !sfdin__h34118[45] &&
	      !sfdin__h34118[44] &&
	      !sfdin__h34118[43] &&
	      !sfdin__h34118[42] &&
	      !sfdin__h34118[41] &&
	      !sfdin__h34118[40] &&
	      !sfdin__h34118[39] &&
	      !sfdin__h34118[38] &&
	      !sfdin__h34118[37] &&
	      !sfdin__h34118[36] &&
	      !sfdin__h34118[35] &&
	      !sfdin__h34118[34] &&
	      !sfdin__h34118[33] &&
	      !sfdin__h34118[32] &&
	      !sfdin__h34118[31] &&
	      !sfdin__h34118[30] &&
	      !sfdin__h34118[29] &&
	      !sfdin__h34118[28] &&
	      !sfdin__h34118[27] &&
	      !sfdin__h34118[26] &&
	      !sfdin__h34118[25] &&
	      !sfdin__h34118[24] &&
	      !sfdin__h34118[23] &&
	      !sfdin__h34118[22] &&
	      !sfdin__h34118[21] &&
	      !sfdin__h34118[20] &&
	      !sfdin__h34118[19] &&
	      !sfdin__h34118[18] &&
	      !sfdin__h34118[17] &&
	      !sfdin__h34118[16] &&
	      !sfdin__h34118[15] &&
	      !sfdin__h34118[14] &&
	      !sfdin__h34118[13] &&
	      !sfdin__h34118[12] &&
	      !sfdin__h34118[11] &&
	      !sfdin__h34118[10] &&
	      !sfdin__h34118[9] &&
	      !sfdin__h34118[8] &&
	      !sfdin__h34118[7] &&
	      !sfdin__h34118[6] &&
	      !sfdin__h34118[5] &&
	      !sfdin__h34118[4] &&
	      !sfdin__h34118[3] &&
	      !sfdin__h34118[2] &&
	      !sfdin__h34118[1] &&
	      !sfdin__h34118[0]) ?
	       sfdin__h34118 :
	       _theResult___snd__h42386 ;
  assign _theResult___snd__h42386 =
	     { IF_0_CONCAT_IF_IF_fpu_div64_fState_S3_first__8_ETC__q12[55:0],
	       2'd0 } ;
  assign _theResult___snd__h42404 =
	     sfdin__h34118 <<
	     IF_IF_fpu_div64_fState_S3_first__86_BITS_120_T_ETC___d882 ;
  assign _theResult___snd__h42409 =
	     sfdin__h34118 <<
	     IF_IF_fpu_div64_fState_S3_first__86_BITS_120_T_ETC___d880 ;
  assign _theResult___snd__h94767 =
	     { fpu_sqr64_fState_S3$D_OUT[57:0], 1'd0 } ;
  assign _theResult___snd__h94782 =
	     (!fpu_sqr64_fState_S3$D_OUT[58] &&
	      fpu_sqr64_fState_S3$D_OUT[57]) ?
	       _theResult___snd__h94784 :
	       _theResult___snd__h94797 ;
  assign _theResult___snd__h94784 =
	     { fpu_sqr64_fState_S3$D_OUT[56:0], 2'd0 } ;
  assign _theResult___snd__h94797 =
	     (!fpu_sqr64_fState_S3$D_OUT[58] &&
	      !fpu_sqr64_fState_S3$D_OUT[57] &&
	      !fpu_sqr64_fState_S3$D_OUT[56] &&
	      !fpu_sqr64_fState_S3$D_OUT[55] &&
	      !fpu_sqr64_fState_S3$D_OUT[54] &&
	      !fpu_sqr64_fState_S3$D_OUT[53] &&
	      !fpu_sqr64_fState_S3$D_OUT[52] &&
	      !fpu_sqr64_fState_S3$D_OUT[51] &&
	      !fpu_sqr64_fState_S3$D_OUT[50] &&
	      !fpu_sqr64_fState_S3$D_OUT[49] &&
	      !fpu_sqr64_fState_S3$D_OUT[48] &&
	      !fpu_sqr64_fState_S3$D_OUT[47] &&
	      !fpu_sqr64_fState_S3$D_OUT[46] &&
	      !fpu_sqr64_fState_S3$D_OUT[45] &&
	      !fpu_sqr64_fState_S3$D_OUT[44] &&
	      !fpu_sqr64_fState_S3$D_OUT[43] &&
	      !fpu_sqr64_fState_S3$D_OUT[42] &&
	      !fpu_sqr64_fState_S3$D_OUT[41] &&
	      !fpu_sqr64_fState_S3$D_OUT[40] &&
	      !fpu_sqr64_fState_S3$D_OUT[39] &&
	      !fpu_sqr64_fState_S3$D_OUT[38] &&
	      !fpu_sqr64_fState_S3$D_OUT[37] &&
	      !fpu_sqr64_fState_S3$D_OUT[36] &&
	      !fpu_sqr64_fState_S3$D_OUT[35] &&
	      !fpu_sqr64_fState_S3$D_OUT[34] &&
	      !fpu_sqr64_fState_S3$D_OUT[33] &&
	      !fpu_sqr64_fState_S3$D_OUT[32] &&
	      !fpu_sqr64_fState_S3$D_OUT[31] &&
	      !fpu_sqr64_fState_S3$D_OUT[30] &&
	      !fpu_sqr64_fState_S3$D_OUT[29] &&
	      !fpu_sqr64_fState_S3$D_OUT[28] &&
	      !fpu_sqr64_fState_S3$D_OUT[27] &&
	      !fpu_sqr64_fState_S3$D_OUT[26] &&
	      !fpu_sqr64_fState_S3$D_OUT[25] &&
	      !fpu_sqr64_fState_S3$D_OUT[24] &&
	      !fpu_sqr64_fState_S3$D_OUT[23] &&
	      !fpu_sqr64_fState_S3$D_OUT[22] &&
	      !fpu_sqr64_fState_S3$D_OUT[21] &&
	      !fpu_sqr64_fState_S3$D_OUT[20] &&
	      !fpu_sqr64_fState_S3$D_OUT[19] &&
	      !fpu_sqr64_fState_S3$D_OUT[18] &&
	      !fpu_sqr64_fState_S3$D_OUT[17] &&
	      !fpu_sqr64_fState_S3$D_OUT[16] &&
	      !fpu_sqr64_fState_S3$D_OUT[15] &&
	      !fpu_sqr64_fState_S3$D_OUT[14] &&
	      !fpu_sqr64_fState_S3$D_OUT[13] &&
	      !fpu_sqr64_fState_S3$D_OUT[12] &&
	      !fpu_sqr64_fState_S3$D_OUT[11] &&
	      !fpu_sqr64_fState_S3$D_OUT[10] &&
	      !fpu_sqr64_fState_S3$D_OUT[9] &&
	      !fpu_sqr64_fState_S3$D_OUT[8] &&
	      !fpu_sqr64_fState_S3$D_OUT[7] &&
	      !fpu_sqr64_fState_S3$D_OUT[6] &&
	      !fpu_sqr64_fState_S3$D_OUT[5] &&
	      !fpu_sqr64_fState_S3$D_OUT[4] &&
	      !fpu_sqr64_fState_S3$D_OUT[3] &&
	      !fpu_sqr64_fState_S3$D_OUT[2] &&
	      !fpu_sqr64_fState_S3$D_OUT[1] &&
	      !fpu_sqr64_fState_S3$D_OUT[0]) ?
	       fpu_sqr64_fState_S3$D_OUT[58:0] :
	       _theResult___snd__h94803 ;
  assign _theResult___snd__h94803 =
	     { IF_0_CONCAT_IF_fpu_sqr64_fState_S3_first__375__ETC__q19[56:0],
	       2'd0 } ;
  assign _theResult___snd__h94821 =
	     fpu_sqr64_fState_S3$D_OUT[58:0] <<
	     IF_fpu_sqr64_fState_S3_first__375_BITS_121_TO__ETC___d1632 ;
  assign _theResult___snd__h94826 =
	     fpu_sqr64_fState_S3$D_OUT[58:0] <<
	     IF_fpu_sqr64_fState_S3_first__375_BIT_58_384_T_ETC___d1630 ;
  assign _theResult___snd_fst__h131051 =
	     { IF_sfdin30943_BIT_53_THEN_2_ELSE_0__q25[1],
	       { sfdin__h130943[52:0], 52'd0 } != 105'd0 } ;
  assign _theResult___snd_fst__h141477 =
	     { IF_sfdin41369_BIT_4_THEN_2_ELSE_0__q30[1],
	       { sfdin__h141369[3:0], 52'd0 } != 56'd0 } ;
  assign _theResult___snd_fst__h1478 =
	     IF_rg_index_1_4_ULE_58_8_THEN_NOT_rg_b_9_EQ_0__ETC___d56 ?
	       _theResult___snd_fst__h1602 :
	       IF_rg_index_1_4_ULE_58_8_THEN_IF_rg_res_1_BIT__ETC___d83 ;
  assign _theResult___snd_fst__h1517 =
	     (rg_res[116] || rg_b == 116'd0 ||
	      rg_s_1_ULT_rg_r_1_0_PLUS_rg_b_9_2___d63) ?
	       rg_s :
	       s__h1658 ;
  assign _theResult___snd_fst__h1602 =
	     (IF_rg_index_1_4_ULE_58_8_THEN_IF_rg_res_1_BIT__ETC___d49 ==
	      116'd0 ||
	      IF_rg_index_1_4_ULE_58_8_THEN_IF_rg_res_1_BIT__ETC___d85) ?
	       IF_rg_index_1_4_ULE_58_8_THEN_IF_rg_res_1_BIT__ETC___d83 :
	       s__h1723 ;
  assign _theResult___snd_fst__h42439 =
	     { IF_sfdin2327_BIT_5_THEN_2_ELSE_0__q13[1],
	       { sfdin__h42327[4:0], 52'd0 } != 57'd0 } ;
  assign _theResult___snd_fst__h94856 =
	     { IF_sfdin4744_BIT_6_THEN_2_ELSE_0__q20[1],
	       { sfdin__h94744[5:0], 52'd0 } != 58'd0 } ;
  assign _theResult___snd_fst_exp__h164065 =
	     _3970_MINUS_0_CONCAT_IF_iFifo_first__087_BIT_15_ETC___d3190 ?
	       11'd0 :
	       _theResult___fst_exp__h164062 ;
  assign _theResult___snd_fst_exp__h182407 =
	     SEXT_iFifo_first__087_BITS_167_TO_160_130_MINU_ETC___d3325 ?
	       _theResult___fst_exp__h173652 :
	       _theResult___fst_exp__h182404 ;
  assign _theResult___snd_fst_exp__h202703 =
	     _3970_MINUS_0_CONCAT_IF_iFifo_first__087_BIT_94_ETC___d4685 ?
	       11'd0 :
	       _theResult___fst_exp__h202700 ;
  assign _theResult___snd_fst_exp__h221045 =
	     SEXT_iFifo_first__087_BITS_102_TO_95_625_MINUS_ETC___d4808 ?
	       _theResult___fst_exp__h212290 :
	       _theResult___fst_exp__h221042 ;
  assign _theResult___snd_fst_exp__h241642 =
	     _3970_MINUS_0_CONCAT_IF_iFifo_first__087_BIT_29_ETC___d3910 ?
	       11'd0 :
	       _theResult___fst_exp__h241639 ;
  assign _theResult___snd_fst_exp__h259984 =
	     SEXT_iFifo_first__087_BITS_37_TO_30_850_MINUS__ETC___d4033 ?
	       _theResult___fst_exp__h251229 :
	       _theResult___fst_exp__h259981 ;
  assign _theResult___snd_fst_exp__h286868 =
	     _3074_MINUS_0_CONCAT_IF_resWire_wget__410_BIT_5_ETC___d5533 ?
	       _theResult___fst_exp__h278283 :
	       _theResult___fst_exp__h286865 ;
  assign _theResult___snd_fst_exp__h304688 =
	     SEXT_resWire_wget__410_BITS_67_TO_57_416_MINUS_ETC___d6033 ?
	       _theResult___fst_exp__h296049 :
	       _theResult___fst_exp__h304685 ;
  assign _theResult___snd_fst_exp__h31334 =
	     (IF_fpu_div64_fOperands_S0_first__06_BITS_129_T_ETC___d355 ||
	      IF_fpu_div64_fOperands_S0_first__06_BITS_129_T_ETC___d499) ?
	       11'd0 :
	       value__h31374[10:0] ;
  assign _theResult___snd_fst_exp__h31337 =
	     IF_fpu_div64_fOperands_S0_first__06_BITS_129_T_ETC___d353 ?
	       _theResult___snd_fst_exp__h31334 :
	       11'd2046 ;
  assign _theResult___snd_fst_exp__h31361 =
	     fpu_div64_fOperands_S0_first__06_BITS_129_TO_1_ETC___d498 ?
	       11'd0 :
	       _theResult___snd_fst_exp__h31337 ;
  assign _theResult___snd_fst_sfd__h144486 =
	     (iFifo$D_OUT[159:137] == 23'd0) ?
	       52'h4000000000000 :
	       out___1_sfd__h144235 ;
  assign _theResult___snd_fst_sfd__h164066 =
	     _3970_MINUS_0_CONCAT_IF_iFifo_first__087_BIT_15_ETC___d3190 ?
	       52'd0 :
	       _theResult___fst_sfd__h164063 ;
  assign _theResult___snd_fst_sfd__h182408 =
	     SEXT_iFifo_first__087_BITS_167_TO_160_130_MINU_ETC___d3325 ?
	       _theResult___fst_sfd__h173653 :
	       _theResult___fst_sfd__h182405 ;
  assign _theResult___snd_fst_sfd__h183126 =
	     (iFifo$D_OUT[94:72] == 23'd0) ?
	       52'h4000000000000 :
	       out___1_sfd__h182875 ;
  assign _theResult___snd_fst_sfd__h202704 =
	     _3970_MINUS_0_CONCAT_IF_iFifo_first__087_BIT_94_ETC___d4685 ?
	       52'd0 :
	       _theResult___fst_sfd__h202701 ;
  assign _theResult___snd_fst_sfd__h221046 =
	     SEXT_iFifo_first__087_BITS_102_TO_95_625_MINUS_ETC___d4808 ?
	       _theResult___fst_sfd__h212291 :
	       _theResult___fst_sfd__h221043 ;
  assign _theResult___snd_fst_sfd__h222065 =
	     (iFifo$D_OUT[29:7] == 23'd0) ?
	       52'h4000000000000 :
	       out___1_sfd__h221814 ;
  assign _theResult___snd_fst_sfd__h241643 =
	     _3970_MINUS_0_CONCAT_IF_iFifo_first__087_BIT_29_ETC___d3910 ?
	       52'd0 :
	       _theResult___fst_sfd__h241640 ;
  assign _theResult___snd_fst_sfd__h259985 =
	     SEXT_iFifo_first__087_BITS_37_TO_30_850_MINUS__ETC___d4033 ?
	       _theResult___fst_sfd__h251230 :
	       _theResult___fst_sfd__h259982 ;
  assign _theResult___snd_fst_sfd__h261925 =
	     (resWire$wget[56:34] == 23'd0) ?
	       23'd2097152 :
	       resWire$wget[56:34] ;
  assign _theResult___snd_fst_sfd__h286869 =
	     _3074_MINUS_0_CONCAT_IF_resWire_wget__410_BIT_5_ETC___d5533 ?
	       _theResult___fst_sfd__h278284 :
	       _theResult___fst_sfd__h286866 ;
  assign _theResult___snd_fst_sfd__h304689 =
	     SEXT_resWire_wget__410_BITS_67_TO_57_416_MINUS_ETC___d6033 ?
	       _theResult___fst_sfd__h296050 :
	       _theResult___fst_sfd__h304686 ;
  assign _theResult___snd_fst_sfd__h31362 =
	     (fpu_div64_fOperands_S0_first__06_BITS_129_TO_1_ETC___d498 ||
	      IF_fpu_div64_fOperands_S0_first__06_BITS_129_T_ETC___d353) ?
	       52'd0 :
	       52'hFFFFFFFFFFFFF ;
  assign _theResult___snd_snd__h131371 =
	     (fpu_madd_fProd_S3$D_OUT == 106'd0) ? 2'd0 : 2'd1 ;
  assign _theResult___snd_snd__h1649 =
	     rg_s_1_ULT_rg_r_1_0_PLUS_rg_b_9_2___d63 ? r__h1663 : r__h1659 ;
  assign _theResult___snd_snd__h1715 =
	     IF_rg_index_1_4_ULE_58_8_THEN_IF_rg_res_1_BIT__ETC___d85 ?
	       r__h1753 :
	       r__h1724 ;
  assign _theResult___snd_snd_snd__h131369 =
	     fpu_madd_fState_S3_first__995_BITS_12_TO_0_001_ETC___d2004 ?
	       _theResult___snd_snd__h131371 :
	       guardBC__h115666 ;
  assign _theResult___snd_snd_snd__h1481 =
	     IF_rg_index_1_4_ULE_58_8_THEN_NOT_rg_b_9_EQ_0__ETC___d56 ?
	       _theResult___snd_snd_snd__h1605 :
	       IF_rg_index_1_4_ULE_58_8_THEN_IF_rg_res_1_BIT__ETC___d69 ;
  assign _theResult___snd_snd_snd__h1520 =
	     (rg_res[116] || rg_b == 116'd0) ?
	       rg_r_1 :
	       _theResult___snd_snd__h1649 ;
  assign _theResult___snd_snd_snd__h1605 =
	     (IF_rg_index_1_4_ULE_58_8_THEN_IF_rg_res_1_BIT__ETC___d49 ==
	      116'd0) ?
	       IF_rg_index_1_4_ULE_58_8_THEN_IF_rg_res_1_BIT__ETC___d69 :
	       _theResult___snd_snd__h1715 ;
  assign _theResult___snd_snd_snd__h33963 =
	     (fpu_div64_fState_S3$D_OUT[57:56] == 2'b0) ?
	       _theResult___snd__h34715 :
	       fpu_div64_fState_S3$D_OUT[57:0] ;
  assign b___1__h77160 = 116'h40000000000000000000000000000 >> x__h85465 ;
  assign b__h11457 =
	     (fpu_div64_fOperands_S0$D_OUT[65:55] == 11'd0) ?
	       (fpu_div64_fOperands_S0$D_OUT[54] ?
		  6'd1 :
		  (fpu_div64_fOperands_S0$D_OUT[53] ?
		     6'd2 :
		     (fpu_div64_fOperands_S0$D_OUT[52] ?
			6'd3 :
			(fpu_div64_fOperands_S0$D_OUT[51] ?
			   6'd4 :
			   (fpu_div64_fOperands_S0$D_OUT[50] ?
			      6'd5 :
			      (fpu_div64_fOperands_S0$D_OUT[49] ?
				 6'd6 :
				 (fpu_div64_fOperands_S0$D_OUT[48] ?
				    6'd7 :
				    (fpu_div64_fOperands_S0$D_OUT[47] ?
				       6'd8 :
				       (fpu_div64_fOperands_S0$D_OUT[46] ?
					  6'd9 :
					  (fpu_div64_fOperands_S0$D_OUT[45] ?
					     6'd10 :
					     (fpu_div64_fOperands_S0$D_OUT[44] ?
						6'd11 :
						(fpu_div64_fOperands_S0$D_OUT[43] ?
						   6'd12 :
						   (fpu_div64_fOperands_S0$D_OUT[42] ?
						      6'd13 :
						      (fpu_div64_fOperands_S0$D_OUT[41] ?
							 6'd14 :
							 (fpu_div64_fOperands_S0$D_OUT[40] ?
							    6'd15 :
							    (fpu_div64_fOperands_S0$D_OUT[39] ?
							       6'd16 :
							       (fpu_div64_fOperands_S0$D_OUT[38] ?
								  6'd17 :
								  (fpu_div64_fOperands_S0$D_OUT[37] ?
								     6'd18 :
								     (fpu_div64_fOperands_S0$D_OUT[36] ?
									6'd19 :
									(fpu_div64_fOperands_S0$D_OUT[35] ?
									   6'd20 :
									   (fpu_div64_fOperands_S0$D_OUT[34] ?
									      6'd21 :
									      (fpu_div64_fOperands_S0$D_OUT[33] ?
										 6'd22 :
										 (fpu_div64_fOperands_S0$D_OUT[32] ?
										    6'd23 :
										    (fpu_div64_fOperands_S0$D_OUT[31] ?
										       6'd24 :
										       (fpu_div64_fOperands_S0$D_OUT[30] ?
											  6'd25 :
											  (fpu_div64_fOperands_S0$D_OUT[29] ?
											     6'd26 :
											     (fpu_div64_fOperands_S0$D_OUT[28] ?
												6'd27 :
												(fpu_div64_fOperands_S0$D_OUT[27] ?
												   6'd28 :
												   (fpu_div64_fOperands_S0$D_OUT[26] ?
												      6'd29 :
												      (fpu_div64_fOperands_S0$D_OUT[25] ?
													 6'd30 :
													 (fpu_div64_fOperands_S0$D_OUT[24] ?
													    6'd31 :
													    (fpu_div64_fOperands_S0$D_OUT[23] ?
													       6'd32 :
													       (fpu_div64_fOperands_S0$D_OUT[22] ?
														  6'd33 :
														  (fpu_div64_fOperands_S0$D_OUT[21] ?
														     6'd34 :
														     (fpu_div64_fOperands_S0$D_OUT[20] ?
															6'd35 :
															(fpu_div64_fOperands_S0$D_OUT[19] ?
															   6'd36 :
															   (fpu_div64_fOperands_S0$D_OUT[18] ?
															      6'd37 :
															      (fpu_div64_fOperands_S0$D_OUT[17] ?
																 6'd38 :
																 (fpu_div64_fOperands_S0$D_OUT[16] ?
																    6'd39 :
																    (fpu_div64_fOperands_S0$D_OUT[15] ?
																       6'd40 :
																       (fpu_div64_fOperands_S0$D_OUT[14] ?
																	  6'd41 :
																	  (fpu_div64_fOperands_S0$D_OUT[13] ?
																	     6'd42 :
																	     (fpu_div64_fOperands_S0$D_OUT[12] ?
																		6'd43 :
																		(fpu_div64_fOperands_S0$D_OUT[11] ?
																		   6'd44 :
																		   (fpu_div64_fOperands_S0$D_OUT[10] ?
																		      6'd45 :
																		      (fpu_div64_fOperands_S0$D_OUT[9] ?
																			 6'd46 :
																			 (fpu_div64_fOperands_S0$D_OUT[8] ?
																			    6'd47 :
																			    (fpu_div64_fOperands_S0$D_OUT[7] ?
																			       6'd48 :
																			       (fpu_div64_fOperands_S0$D_OUT[6] ?
																				  6'd49 :
																				  (fpu_div64_fOperands_S0$D_OUT[5] ?
																				     6'd50 :
																				     (fpu_div64_fOperands_S0$D_OUT[4] ?
																					6'd51 :
																					(fpu_div64_fOperands_S0$D_OUT[3] ?
																					   6'd52 :
																					   6'd53)))))))))))))))))))))))))))))))))))))))))))))))))))) :
	       6'd0 ;
  assign b__h1608 = { 2'd0, rg_b[115:2] } ;
  assign b__h1712 =
	     { 2'd0,
	       IF_rg_index_1_4_ULE_58_8_THEN_IF_rg_res_1_BIT__ETC___d49[115:2] } ;
  assign b__h32583 = { rg_d, 58'd0 } ;
  assign b__h4039 =
	     (fpu_div64_fOperands_S0$D_OUT[129:119] == 11'd0) ?
	       (fpu_div64_fOperands_S0$D_OUT[118] ?
		  6'd1 :
		  (fpu_div64_fOperands_S0$D_OUT[117] ?
		     6'd2 :
		     (fpu_div64_fOperands_S0$D_OUT[116] ?
			6'd3 :
			(fpu_div64_fOperands_S0$D_OUT[115] ?
			   6'd4 :
			   (fpu_div64_fOperands_S0$D_OUT[114] ?
			      6'd5 :
			      (fpu_div64_fOperands_S0$D_OUT[113] ?
				 6'd6 :
				 (fpu_div64_fOperands_S0$D_OUT[112] ?
				    6'd7 :
				    (fpu_div64_fOperands_S0$D_OUT[111] ?
				       6'd8 :
				       (fpu_div64_fOperands_S0$D_OUT[110] ?
					  6'd9 :
					  (fpu_div64_fOperands_S0$D_OUT[109] ?
					     6'd10 :
					     (fpu_div64_fOperands_S0$D_OUT[108] ?
						6'd11 :
						(fpu_div64_fOperands_S0$D_OUT[107] ?
						   6'd12 :
						   (fpu_div64_fOperands_S0$D_OUT[106] ?
						      6'd13 :
						      (fpu_div64_fOperands_S0$D_OUT[105] ?
							 6'd14 :
							 (fpu_div64_fOperands_S0$D_OUT[104] ?
							    6'd15 :
							    (fpu_div64_fOperands_S0$D_OUT[103] ?
							       6'd16 :
							       (fpu_div64_fOperands_S0$D_OUT[102] ?
								  6'd17 :
								  (fpu_div64_fOperands_S0$D_OUT[101] ?
								     6'd18 :
								     (fpu_div64_fOperands_S0$D_OUT[100] ?
									6'd19 :
									(fpu_div64_fOperands_S0$D_OUT[99] ?
									   6'd20 :
									   (fpu_div64_fOperands_S0$D_OUT[98] ?
									      6'd21 :
									      (fpu_div64_fOperands_S0$D_OUT[97] ?
										 6'd22 :
										 (fpu_div64_fOperands_S0$D_OUT[96] ?
										    6'd23 :
										    (fpu_div64_fOperands_S0$D_OUT[95] ?
										       6'd24 :
										       (fpu_div64_fOperands_S0$D_OUT[94] ?
											  6'd25 :
											  (fpu_div64_fOperands_S0$D_OUT[93] ?
											     6'd26 :
											     (fpu_div64_fOperands_S0$D_OUT[92] ?
												6'd27 :
												(fpu_div64_fOperands_S0$D_OUT[91] ?
												   6'd28 :
												   (fpu_div64_fOperands_S0$D_OUT[90] ?
												      6'd29 :
												      (fpu_div64_fOperands_S0$D_OUT[89] ?
													 6'd30 :
													 (fpu_div64_fOperands_S0$D_OUT[88] ?
													    6'd31 :
													    (fpu_div64_fOperands_S0$D_OUT[87] ?
													       6'd32 :
													       (fpu_div64_fOperands_S0$D_OUT[86] ?
														  6'd33 :
														  (fpu_div64_fOperands_S0$D_OUT[85] ?
														     6'd34 :
														     (fpu_div64_fOperands_S0$D_OUT[84] ?
															6'd35 :
															(fpu_div64_fOperands_S0$D_OUT[83] ?
															   6'd36 :
															   (fpu_div64_fOperands_S0$D_OUT[82] ?
															      6'd37 :
															      (fpu_div64_fOperands_S0$D_OUT[81] ?
																 6'd38 :
																 (fpu_div64_fOperands_S0$D_OUT[80] ?
																    6'd39 :
																    (fpu_div64_fOperands_S0$D_OUT[79] ?
																       6'd40 :
																       (fpu_div64_fOperands_S0$D_OUT[78] ?
																	  6'd41 :
																	  (fpu_div64_fOperands_S0$D_OUT[77] ?
																	     6'd42 :
																	     (fpu_div64_fOperands_S0$D_OUT[76] ?
																		6'd43 :
																		(fpu_div64_fOperands_S0$D_OUT[75] ?
																		   6'd44 :
																		   (fpu_div64_fOperands_S0$D_OUT[74] ?
																		      6'd45 :
																		      (fpu_div64_fOperands_S0$D_OUT[73] ?
																			 6'd46 :
																			 (fpu_div64_fOperands_S0$D_OUT[72] ?
																			    6'd47 :
																			    (fpu_div64_fOperands_S0$D_OUT[71] ?
																			       6'd48 :
																			       (fpu_div64_fOperands_S0$D_OUT[70] ?
																				  6'd49 :
																				  (fpu_div64_fOperands_S0$D_OUT[69] ?
																				     6'd50 :
																				     (fpu_div64_fOperands_S0$D_OUT[68] ?
																					6'd51 :
																					(fpu_div64_fOperands_S0$D_OUT[67] ?
																					   6'd52 :
																					   6'd53)))))))))))))))))))))))))))))))))))))))))))))))))))) :
	       6'd0 ;
  assign din_exp30866_MINUS_1023__q23 = din_exp__h130866 - 11'd1023 ;
  assign din_exp__h130866 =
	     _7170_MINUS_fpu_madd_fState_S3_first__995_BITS__ETC___d2008 ?
	       value__h130883[10:0] :
	       11'd0 ;
  assign din_inc___2_exp__h142626 = fpu_madd_fState_S8$D_OUT[65:55] + 11'd1 ;
  assign din_inc___2_exp__h182469 = _theResult___fst_exp__h163336 + 11'd1 ;
  assign din_inc___2_exp__h182504 = _theResult___fst_exp__h172852 + 11'd1 ;
  assign din_inc___2_exp__h182530 = _theResult___fst_exp__h181653 + 11'd1 ;
  assign din_inc___2_exp__h221107 = _theResult___fst_exp__h201974 + 11'd1 ;
  assign din_inc___2_exp__h221142 = _theResult___fst_exp__h211490 + 11'd1 ;
  assign din_inc___2_exp__h221168 = _theResult___fst_exp__h220291 + 11'd1 ;
  assign din_inc___2_exp__h260046 = _theResult___fst_exp__h240913 + 11'd1 ;
  assign din_inc___2_exp__h260081 = _theResult___fst_exp__h250429 + 11'd1 ;
  assign din_inc___2_exp__h260107 = _theResult___fst_exp__h259230 + 11'd1 ;
  assign din_inc___2_exp__h304723 = _theResult___fst_exp__h277686 + 8'd1 ;
  assign din_inc___2_exp__h304749 = _theResult___fst_exp__h286342 + 8'd1 ;
  assign din_inc___2_exp__h304784 = _theResult___fst_exp__h295452 + 8'd1 ;
  assign din_inc___2_exp__h304810 = _theResult___fst_exp__h304137 + 8'd1 ;
  assign din_inc___2_exp__h43566 = fpu_div64_fState_S4$D_OUT[64:54] + 11'd1 ;
  assign din_inc___2_exp__h96000 = fpu_sqr64_fState_S4$D_OUT[64:54] + 11'd1 ;
  assign exp__h304706 =
	     (resWire$wget[67:57] == 11'd2047) ?
	       8'd255 :
	       _theResult___fst_exp__h304697 ;
  assign fpu_div64_fOperands_S0D_OUT_BITS_129_TO_119_M_ETC__q7 =
	     fpu_div64_fOperands_S0$D_OUT[129:119] - 11'd1023 ;
  assign fpu_div64_fOperands_S0D_OUT_BITS_65_TO_55_MIN_ETC__q8 =
	     fpu_div64_fOperands_S0$D_OUT[65:55] - 11'd1023 ;
  assign fpu_div64_fOperands_S0_first__06_BITS_129_TO_1_ETC___d363 =
	     fpu_div64_fOperands_S0$D_OUT[129:119] == 11'd2047 &&
	     fpu_div64_fOperands_S0$D_OUT[118:67] != 52'd0 &&
	     !fpu_div64_fOperands_S0$D_OUT[118] ||
	     fpu_div64_fOperands_S0$D_OUT[65:55] == 11'd2047 &&
	     fpu_div64_fOperands_S0$D_OUT[54:3] != 52'd0 &&
	     !fpu_div64_fOperands_S0$D_OUT[54] ||
	     fpu_div64_fOperands_S0$D_OUT[129:119] == 11'd2047 &&
	     fpu_div64_fOperands_S0$D_OUT[118] ||
	     fpu_div64_fOperands_S0$D_OUT[65:55] == 11'd2047 &&
	     fpu_div64_fOperands_S0$D_OUT[54] ||
	     fpu_div64_fOperands_S0_first__06_BITS_65_TO_55_ETC___d359 ;
  assign fpu_div64_fOperands_S0_first__06_BITS_129_TO_1_ETC___d401 =
	     fpu_div64_fOperands_S0$D_OUT[129:119] == 11'd2047 &&
	     fpu_div64_fOperands_S0$D_OUT[118:67] == 52'd0 ||
	     fpu_div64_fOperands_S0$D_OUT[129:119] == 11'd0 &&
	     fpu_div64_fOperands_S0$D_OUT[118:67] == 52'd0 ||
	     fpu_div64_fOperands_S0$D_OUT[65:55] == 11'd2047 &&
	     fpu_div64_fOperands_S0$D_OUT[54:3] == 52'd0 ;
  assign fpu_div64_fOperands_S0_first__06_BITS_129_TO_1_ETC___d436 =
	     fpu_div64_fOperands_S0$D_OUT[129:119] == 11'd2047 &&
	     fpu_div64_fOperands_S0$D_OUT[118:67] == 52'd0 &&
	     fpu_div64_fOperands_S0$D_OUT[65:55] == 11'd2047 &&
	     fpu_div64_fOperands_S0$D_OUT[54:3] == 52'd0 ||
	     fpu_div64_fOperands_S0$D_OUT[129:119] == 11'd0 &&
	     fpu_div64_fOperands_S0$D_OUT[118:67] == 52'd0 &&
	     fpu_div64_fOperands_S0$D_OUT[65:55] == 11'd0 &&
	     fpu_div64_fOperands_S0$D_OUT[54:3] == 52'd0 ;
  assign fpu_div64_fOperands_S0_first__06_BITS_129_TO_1_ETC___d498 =
	     fpu_div64_fOperands_S0$D_OUT[129:119] == 11'd2047 &&
	     fpu_div64_fOperands_S0$D_OUT[118:67] != 52'd0 &&
	     !fpu_div64_fOperands_S0$D_OUT[118] ||
	     fpu_div64_fOperands_S0$D_OUT[65:55] == 11'd2047 &&
	     fpu_div64_fOperands_S0$D_OUT[54:3] != 52'd0 &&
	     !fpu_div64_fOperands_S0$D_OUT[54] ||
	     fpu_div64_fOperands_S0$D_OUT[129:119] == 11'd2047 &&
	     fpu_div64_fOperands_S0$D_OUT[118] ||
	     fpu_div64_fOperands_S0$D_OUT[65:55] == 11'd2047 &&
	     fpu_div64_fOperands_S0$D_OUT[54] ||
	     fpu_div64_fOperands_S0$D_OUT[65:55] == 11'd0 &&
	     fpu_div64_fOperands_S0$D_OUT[54:3] == 52'd0 ||
	     fpu_div64_fOperands_S0_first__06_BITS_129_TO_1_ETC___d401 ;
  assign fpu_div64_fOperands_S0_first__06_BITS_65_TO_55_ETC___d359 =
	     fpu_div64_fOperands_S0$D_OUT[65:55] == 11'd0 &&
	     fpu_div64_fOperands_S0$D_OUT[54:3] == 52'd0 ||
	     fpu_div64_fOperands_S0$D_OUT[129:119] == 11'd2047 &&
	     fpu_div64_fOperands_S0$D_OUT[118:67] == 52'd0 ||
	     fpu_div64_fOperands_S0$D_OUT[129:119] == 11'd0 &&
	     fpu_div64_fOperands_S0$D_OUT[118:67] == 52'd0 ||
	     fpu_div64_fOperands_S0$D_OUT[65:55] == 11'd2047 &&
	     fpu_div64_fOperands_S0$D_OUT[54:3] == 52'd0 ||
	     !IF_fpu_div64_fOperands_S0_first__06_BITS_129_T_ETC___d353 ||
	     IF_fpu_div64_fOperands_S0_first__06_BITS_129_T_ETC___d355 ;
  assign fpu_div64_fOperands_S0_first__06_BIT_130_03_EQ_ETC___d405 =
	     fpu_div64_fOperands_S0$D_OUT[130] ==
	     fpu_div64_fOperands_S0$D_OUT[66] ;
  assign fpu_div64_fState_S3_first__86_BIT_121_07_CONCA_ETC___d936 =
	     { fpu_div64_fState_S3$D_OUT[121],
	       IF_fpu_div64_fState_S3_first__86_BITS_120_TO_1_ETC___d597 ?
		 IF_IF_fpu_div64_fState_S3_first__86_BITS_120_T_ETC___d929 :
		 ((fpu_div64_fState_S3$D_OUT[120:110] == 11'd2047) ?
		    ((fpu_div64_fState_S3$D_OUT[57:56] == 2'b0) ?
		       { _theResult___fst_exp__h42284,
			 fpu_div64_fState_S3$D_OUT[109:58] } :
		       63'h7FEFFFFFFFFFFFFF) :
		    fpu_div64_fState_S3$D_OUT[120:58]) } ;
  assign fpu_madd_fOperand_S0D_OUT_BITS_129_TO_119_MIN_ETC__q128 =
	     fpu_madd_fOperand_S0$D_OUT[129:119] - 11'd1023 ;
  assign fpu_madd_fOperand_S0D_OUT_BITS_65_TO_55_MINUS_ETC__q129 =
	     fpu_madd_fOperand_S0$D_OUT[65:55] - 11'd1023 ;
  assign fpu_madd_fOperand_S0_first__803_BITS_129_TO_11_ETC___d1857 =
	     fpu_madd_fOperand_S0$D_OUT[129:119] == 11'd2047 &&
	     fpu_madd_fOperand_S0$D_OUT[118:67] == 52'd0 ||
	     fpu_madd_fOperand_S0$D_OUT[65:55] == 11'd2047 &&
	     fpu_madd_fOperand_S0$D_OUT[54:3] == 52'd0 ||
	     x__h96539 == 11'd0 && _theResult___fst_sfd__h96608 == 52'd0 &&
	     (fpu_madd_fOperand_S0$D_OUT[129:119] == 11'd0 &&
	      fpu_madd_fOperand_S0$D_OUT[118:67] == 52'd0 ||
	      fpu_madd_fOperand_S0$D_OUT[65:55] == 11'd0 &&
	      fpu_madd_fOperand_S0$D_OUT[54:3] == 52'd0) &&
	     fpu_madd_fOperand_S0_first__803_BIT_195_804_AN_ETC___d1855 ;
  assign fpu_madd_fOperand_S0_first__803_BITS_129_TO_11_ETC___d1926 =
	     fpu_madd_fOperand_S0$D_OUT[129:119] == 11'd2047 &&
	     fpu_madd_fOperand_S0$D_OUT[118:67] == 52'd0 &&
	     fpu_madd_fOperand_S0$D_OUT[65:55] == 11'd0 &&
	     fpu_madd_fOperand_S0$D_OUT[54:3] == 52'd0 ||
	     fpu_madd_fOperand_S0$D_OUT[129:119] == 11'd0 &&
	     fpu_madd_fOperand_S0$D_OUT[118:67] == 52'd0 &&
	     fpu_madd_fOperand_S0$D_OUT[65:55] == 11'd2047 &&
	     fpu_madd_fOperand_S0$D_OUT[54:3] == 52'd0 ;
  assign fpu_madd_fOperand_S0_first__803_BIT_195_804_AN_ETC___d1855 =
	     (fpu_madd_fOperand_S0$D_OUT[195] &&
	      fpu_madd_fOperand_S0$D_OUT[194]) ==
	     NOT_fpu_madd_fOperand_S0_first__803_BIT_130_85_ETC___d1854 ;
  assign fpu_madd_fProd_S3_first__009_SRL_IF_7170_MINUS_ETC___d2012 =
	     fpu_madd_fProd_S3$D_OUT >>
	     _7170_MINUS_fpu_madd_fState_S3_first__995_BITS__ETC___d2007 ;
  assign fpu_madd_fState_S3_first__995_BITS_12_TO_0_001_ETC___d2002 =
	     (fpu_madd_fState_S3$D_OUT[12:0] ^ 13'h1000) <= 13'd5119 ;
  assign fpu_madd_fState_S3_first__995_BITS_12_TO_0_001_ETC___d2004 =
	     (fpu_madd_fState_S3$D_OUT[12:0] ^ 13'h1000) < 13'd3020 ;
  assign fpu_madd_fState_S3_first__995_BITS_86_TO_82_00_ETC___d2501 =
	     fpu_madd_fState_S3$D_OUT[86:82] |
	     { 2'd0,
	       sfdBC__h115662[105] &&
	       IF_IF_7170_MINUS_fpu_madd_fState_S3_first__995_ETC___d2031 ==
	       12'd1023,
	       _theResult___fst_exp__h130952 == 11'd0 &&
	       guardBC__h115666 != 2'd0,
	       sfdBC__h115662[105] &&
	       IF_IF_7170_MINUS_fpu_madd_fState_S3_first__995_ETC___d2031 ==
	       12'd1023 } ;
  assign fpu_madd_fState_S4D_OUT_BITS_128_TO_118_MINUS_ETC__q27 =
	     fpu_madd_fState_S4$D_OUT[128:118] - 11'd1023 ;
  assign fpu_madd_fState_S4D_OUT_BITS_64_TO_54_MINUS_1023__q26 =
	     fpu_madd_fState_S4$D_OUT[64:54] - 11'd1023 ;
  assign fpu_madd_fState_S5_first__601_BITS_56_TO_0_610_ETC___d2615 =
	     fpu_madd_fState_S5$D_OUT[56:0] >>
	     fpu_madd_fState_S5$D_OUT[126:114] ;
  assign fpu_madd_fState_S7_first__651_BITS_137_TO_133__ETC___d2942 =
	     fpu_madd_fState_S7$D_OUT[137:133] |
	     { 2'd0,
	       sfd__h133119[56] &&
	       IF_fpu_madd_fState_S7_first__651_BITS_126_TO_1_ETC___d2668 ==
	       12'd1023,
	       _theResult___fst_exp__h141378 == 11'd0 &&
	       guard__h133123 != 2'd0,
	       sfd__h133119[56] &&
	       IF_fpu_madd_fState_S7_first__651_BITS_126_TO_1_ETC___d2668 ==
	       12'd1023 } ;
  assign fpu_madd_fState_S8_first__960_BITS_75_TO_71_03_ETC___d3043 =
	     fpu_madd_fState_S8$D_OUT[75:71] |
	     { 2'd0,
	       IF_fpu_madd_fState_S8_first__960_BITS_65_TO_55_ETC___d3011 ==
	       11'd2047 &&
	       ((fpu_madd_fState_S8$D_OUT[65:55] == 11'd2047) ?
		  fpu_madd_fState_S8$D_OUT[54:3] :
		  _theResult___fst_sfd__h142620) ==
	       52'd0,
	       1'd0,
	       fpu_madd_fState_S8$D_OUT[65:55] != 11'd2047 &&
	       fpu_madd_fState_S8$D_OUT[2:1] != 2'b0 } ;
  assign fpu_sqr64_fOperand_S0D_OUT_BITS_65_TO_55_MINU_ETC__q16 =
	     fpu_sqr64_fOperand_S0$D_OUT[65:55] - 11'd1023 ;
  assign fpu_sqr64_fState_S3D_OUT_BITS_121_TO_111_MINU_ETC__q18 =
	     fpu_sqr64_fState_S3$D_OUT[121:111] - 11'd1023 ;
  assign guardBC__h115666 =
	     (sfdBC__h115662[105] &&
	      IF_IF_7170_MINUS_fpu_madd_fState_S3_first__995_ETC___d2031 ==
	      12'd1023) ?
	       2'd3 :
	       _theResult___snd_fst__h131051 ;
  assign guard__h132367 = fpu_madd_fState_S5$D_OUT[56:0] << x__h132471 ;
  assign guard__h133123 =
	     (sfd__h133119[56] &&
	      IF_fpu_madd_fState_S7_first__651_BITS_126_TO_1_ETC___d2668 ==
	      12'd1023) ?
	       2'd3 :
	       _theResult___snd_fst__h141477 ;
  assign guard__h155375 =
	     { IF_theResult___snd63287_BIT_4_THEN_2_ELSE_0__q34[1],
	       { _theResult___snd__h163287[3:0], 52'd0 } != 56'd0 } ;
  assign guard__h164624 =
	     { IF_sfdin72846_BIT_4_THEN_2_ELSE_0__q38[1],
	       { sfdin__h172846[3:0], 52'd0 } != 56'd0 } ;
  assign guard__h165222 = x__h165324 != 57'd0 ;
  assign guard__h173663 =
	     { IF_theResult___snd81599_BIT_4_THEN_2_ELSE_0__q41[1],
	       { _theResult___snd__h181599[3:0], 52'd0 } != 56'd0 } ;
  assign guard__h194013 =
	     { IF_theResult___snd01925_BIT_4_THEN_2_ELSE_0__q94[1],
	       { _theResult___snd__h201925[3:0], 52'd0 } != 56'd0 } ;
  assign guard__h203262 =
	     { IF_sfdin11484_BIT_4_THEN_2_ELSE_0__q98[1],
	       { sfdin__h211484[3:0], 52'd0 } != 56'd0 } ;
  assign guard__h203860 = x__h203962 != 57'd0 ;
  assign guard__h212301 =
	     { IF_theResult___snd20237_BIT_4_THEN_2_ELSE_0__q101[1],
	       { _theResult___snd__h220237[3:0], 52'd0 } != 56'd0 } ;
  assign guard__h232952 =
	     { IF_theResult___snd40864_BIT_4_THEN_2_ELSE_0__q61[1],
	       { _theResult___snd__h240864[3:0], 52'd0 } != 56'd0 } ;
  assign guard__h242201 =
	     { IF_sfdin50423_BIT_4_THEN_2_ELSE_0__q65[1],
	       { sfdin__h250423[3:0], 52'd0 } != 56'd0 } ;
  assign guard__h242799 = x__h242901 != 57'd0 ;
  assign guard__h251240 =
	     { IF_theResult___snd59176_BIT_4_THEN_2_ELSE_0__q68[1],
	       { _theResult___snd__h259176[3:0], 52'd0 } != 56'd0 } ;
  assign guard__h269587 =
	     { IF_sfdin77680_BIT_33_THEN_2_ELSE_0__q134[1],
	       { sfdin__h277680[32:0], 23'd0 } != 56'd0 } ;
  assign guard__h278294 =
	     { IF_theResult___snd86293_BIT_33_THEN_2_ELSE_0__q136[1],
	       { _theResult___snd__h286293[32:0], 23'd0 } != 56'd0 } ;
  assign guard__h287224 =
	     { IF_sfdin95446_BIT_33_THEN_2_ELSE_0__q140[1],
	       { sfdin__h295446[32:0], 23'd0 } != 56'd0 } ;
  assign guard__h287822 = x__h287924 != 57'd0 ;
  assign guard__h296060 =
	     { IF_theResult___snd04083_BIT_33_THEN_2_ELSE_0__q143[1],
	       { _theResult___snd__h304083[32:0], 23'd0 } != 56'd0 } ;
  assign guard__h33946 = x__h42705 ;
  assign guard__h86435 = x__h95138 ;
  assign iFifoD_OUT_BITS_102_TO_95_MINUS_127__q95 =
	     iFifo$D_OUT[102:95] - 8'd127 ;
  assign iFifoD_OUT_BITS_167_TO_160_MINUS_127__q35 =
	     iFifo$D_OUT[167:160] - 8'd127 ;
  assign iFifoD_OUT_BITS_37_TO_30_MINUS_127__q62 =
	     iFifo$D_OUT[37:30] - 8'd127 ;
  assign out___1_sfd__h144235 = { iFifo$D_OUT[159:137], 29'd0 } ;
  assign out___1_sfd__h182875 = { iFifo$D_OUT[94:72], 29'd0 } ;
  assign out___1_sfd__h221814 = { iFifo$D_OUT[29:7], 29'd0 } ;
  assign out_exp__h142544 =
	     fpu_madd_fState_S8$D_OUT[3] ?
	       _theResult___exp__h142541 :
	       fpu_madd_fState_S8$D_OUT[65:55] ;
  assign out_exp__h163984 =
	     _theResult___snd__h163287[5] ?
	       _theResult___exp__h163981 :
	       _theResult___fst_exp__h163336 ;
  assign out_exp__h173574 =
	     sfdin__h172846[5] ?
	       _theResult___exp__h173571 :
	       _theResult___fst_exp__h172852 ;
  assign out_exp__h182326 =
	     _theResult___snd__h181599[5] ?
	       _theResult___exp__h182323 :
	       _theResult___fst_exp__h181653 ;
  assign out_exp__h202622 =
	     _theResult___snd__h201925[5] ?
	       _theResult___exp__h202619 :
	       _theResult___fst_exp__h201974 ;
  assign out_exp__h212212 =
	     sfdin__h211484[5] ?
	       _theResult___exp__h212209 :
	       _theResult___fst_exp__h211490 ;
  assign out_exp__h220964 =
	     _theResult___snd__h220237[5] ?
	       _theResult___exp__h220961 :
	       _theResult___fst_exp__h220291 ;
  assign out_exp__h241561 =
	     _theResult___snd__h240864[5] ?
	       _theResult___exp__h241558 :
	       _theResult___fst_exp__h240913 ;
  assign out_exp__h251151 =
	     sfdin__h250423[5] ?
	       _theResult___exp__h251148 :
	       _theResult___fst_exp__h250429 ;
  assign out_exp__h259903 =
	     _theResult___snd__h259176[5] ?
	       _theResult___exp__h259900 :
	       _theResult___fst_exp__h259230 ;
  assign out_exp__h278205 =
	     sfdin__h277680[34] ?
	       _theResult___exp__h278202 :
	       _theResult___fst_exp__h277686 ;
  assign out_exp__h286787 =
	     _theResult___snd__h286293[34] ?
	       _theResult___exp__h286784 :
	       _theResult___fst_exp__h286342 ;
  assign out_exp__h295971 =
	     sfdin__h295446[34] ?
	       _theResult___exp__h295968 :
	       _theResult___fst_exp__h295452 ;
  assign out_exp__h304607 =
	     _theResult___snd__h304083[34] ?
	       _theResult___exp__h304604 :
	       _theResult___fst_exp__h304137 ;
  assign out_exp__h43478 =
	     fpu_div64_fState_S4$D_OUT[2] ?
	       _theResult___exp__h43475 :
	       fpu_div64_fState_S4$D_OUT[64:54] ;
  assign out_exp__h95912 =
	     fpu_sqr64_fState_S4$D_OUT[2] ?
	       _theResult___exp__h95909 :
	       fpu_sqr64_fState_S4$D_OUT[64:54] ;
  assign out_sfd__h142545 =
	     fpu_madd_fState_S8$D_OUT[3] ?
	       _theResult___sfd__h142542 :
	       fpu_madd_fState_S8$D_OUT[54:3] ;
  assign out_sfd__h163985 =
	     _theResult___snd__h163287[5] ?
	       _theResult___sfd__h163982 :
	       _theResult___snd__h163287[56:5] ;
  assign out_sfd__h173575 =
	     sfdin__h172846[5] ?
	       _theResult___sfd__h173572 :
	       sfdin__h172846[56:5] ;
  assign out_sfd__h182327 =
	     _theResult___snd__h181599[5] ?
	       _theResult___sfd__h182324 :
	       _theResult___snd__h181599[56:5] ;
  assign out_sfd__h202623 =
	     _theResult___snd__h201925[5] ?
	       _theResult___sfd__h202620 :
	       _theResult___snd__h201925[56:5] ;
  assign out_sfd__h212213 =
	     sfdin__h211484[5] ?
	       _theResult___sfd__h212210 :
	       sfdin__h211484[56:5] ;
  assign out_sfd__h220965 =
	     _theResult___snd__h220237[5] ?
	       _theResult___sfd__h220962 :
	       _theResult___snd__h220237[56:5] ;
  assign out_sfd__h241562 =
	     _theResult___snd__h240864[5] ?
	       _theResult___sfd__h241559 :
	       _theResult___snd__h240864[56:5] ;
  assign out_sfd__h251152 =
	     sfdin__h250423[5] ?
	       _theResult___sfd__h251149 :
	       sfdin__h250423[56:5] ;
  assign out_sfd__h259904 =
	     _theResult___snd__h259176[5] ?
	       _theResult___sfd__h259901 :
	       _theResult___snd__h259176[56:5] ;
  assign out_sfd__h278206 =
	     sfdin__h277680[34] ?
	       _theResult___sfd__h278203 :
	       sfdin__h277680[56:34] ;
  assign out_sfd__h286788 =
	     _theResult___snd__h286293[34] ?
	       _theResult___sfd__h286785 :
	       _theResult___snd__h286293[56:34] ;
  assign out_sfd__h295972 =
	     sfdin__h295446[34] ?
	       _theResult___sfd__h295969 :
	       sfdin__h295446[56:34] ;
  assign out_sfd__h304608 =
	     _theResult___snd__h304083[34] ?
	       _theResult___sfd__h304605 :
	       _theResult___snd__h304083[56:34] ;
  assign out_sfd__h43479 =
	     fpu_div64_fState_S4$D_OUT[2] ?
	       _theResult___sfd__h43476 :
	       fpu_div64_fState_S4$D_OUT[53:2] ;
  assign out_sfd__h95913 =
	     fpu_sqr64_fState_S4$D_OUT[2] ?
	       _theResult___sfd__h95910 :
	       fpu_sqr64_fState_S4$D_OUT[53:2] ;
  assign r__h1659 = r__h1663 + rg_b ;
  assign r__h1663 = { 1'd0, rg_r_1[115:1] } ;
  assign r__h1724 =
	     r__h1753 +
	     IF_rg_index_1_4_ULE_58_8_THEN_IF_rg_res_1_BIT__ETC___d49 ;
  assign r__h1753 =
	     { 1'd0,
	       IF_rg_index_1_4_ULE_58_8_THEN_IF_rg_res_1_BIT__ETC___d69[115:1] } ;
  assign resWire_wget__410_BITS_4_TO_0_658_OR_NOT_resWi_ETC___d6768 =
	     resWire$wget[4:0] |
	     { (resWire$wget[67:57] != 11'd2047 ||
		resWire$wget[56:5] == 52'd0) &&
	       (resWire$wget[67:57] != 11'd2047 ||
		resWire$wget[56:5] != 52'd0) &&
	       (resWire$wget[67:57] != 11'd0 ||
		resWire$wget[56:5] != 52'd0) &&
	       IF_resWire_wget__410_BITS_67_TO_57_416_EQ_0_42_ETC___d6709,
	       (resWire$wget[67:57] != 11'd2047 ||
		resWire$wget[56:5] == 52'd0) &&
	       (resWire$wget[67:57] != 11'd2047 ||
		resWire$wget[56:5] != 52'd0) &&
	       (resWire$wget[67:57] != 11'd0 ||
		resWire$wget[56:5] != 52'd0) &&
	       IF_resWire_wget__410_BITS_67_TO_57_416_EQ_0_42_ETC___d6720,
	       (resWire$wget[67:57] != 11'd2047 ||
		resWire$wget[56:5] == 52'd0) &&
	       (resWire$wget[67:57] != 11'd2047 ||
		resWire$wget[56:5] != 52'd0) &&
	       (resWire$wget[67:57] != 11'd0 ||
		resWire$wget[56:5] != 52'd0) &&
	       IF_resWire_wget__410_BITS_67_TO_57_416_EQ_0_42_ETC___d6736,
	       (resWire$wget[67:57] != 11'd2047 ||
		resWire$wget[56:5] == 52'd0) &&
	       (resWire$wget[67:57] != 11'd2047 ||
		resWire$wget[56:5] != 52'd0) &&
	       (resWire$wget[67:57] != 11'd0 ||
		resWire$wget[56:5] != 52'd0) &&
	       IF_resWire_wget__410_BITS_67_TO_57_416_EQ_0_42_ETC___d6749,
	       (resWire$wget[67:57] != 11'd2047 ||
		resWire$wget[56:5] == 52'd0) &&
	       (resWire$wget[67:57] != 11'd2047 ||
		resWire$wget[56:5] != 52'd0) &&
	       (resWire$wget[67:57] != 11'd0 ||
		resWire$wget[56:5] != 52'd0) &&
	       IF_resWire_wget__410_BITS_67_TO_57_416_EQ_0_42_ETC___d6762 } ;
  assign resWirewget_BITS_67_TO_57_MINUS_1023__q137 =
	     resWire$wget[67:57] - 11'd1023 ;
  assign result__h132372 =
	     { fpu_madd_fState_S5_first__601_BITS_56_TO_0_610_ETC___d2615[56:1],
	       fpu_madd_fState_S5_first__601_BITS_56_TO_0_610_ETC___d2615[0] |
	       guard__h132367 != 57'd0 } ;
  assign result__h165227 =
	     { _0b0_CONCAT_NOT_iFifo_first__087_BITS_167_TO_16_ETC___d3330[56:1],
	       _0b0_CONCAT_NOT_iFifo_first__087_BITS_167_TO_16_ETC___d3330[0] |
	       guard__h165222 } ;
  assign result__h203865 =
	     { _0b0_CONCAT_NOT_iFifo_first__087_BITS_102_TO_95_ETC___d4813[56:1],
	       _0b0_CONCAT_NOT_iFifo_first__087_BITS_102_TO_95_ETC___d4813[0] |
	       guard__h203860 } ;
  assign result__h242804 =
	     { _0b0_CONCAT_NOT_iFifo_first__087_BITS_37_TO_30__ETC___d4038[56:1],
	       _0b0_CONCAT_NOT_iFifo_first__087_BITS_37_TO_30__ETC___d4038[0] |
	       guard__h242799 } ;
  assign result__h287827 =
	     { _0b0_CONCAT_NOT_resWire_wget__410_BITS_67_TO_57_ETC___d6038[56:1],
	       _0b0_CONCAT_NOT_resWire_wget__410_BITS_67_TO_57_ETC___d6038[0] |
	       guard__h287822 } ;
  assign result__h32617 = { _theResult____h32523[57:1], 1'd1 } ;
  assign result__h32648 =
	     { 1'd0,
	       value__h32661[56:1],
	       value__h32661[0] | sfdlsb__h32643 } ;
  assign result__h32823 =
	     (IF_rg_r_BIT_115_THEN_rg_q_PLUS_NEG_INV_rg_q_59_ETC__q10[56:0] ==
	      57'd0) ?
	       58'd0 :
	       58'd1 ;
  assign result__h85925 = { x__h85931[58:1], 1'd1 } ;
  assign rg_index_1_4_PLUS_1_6_ULE_58___d37 = rg_index_1 + 6'd1 <= 6'd58 ;
  assign rg_index_1_4_ULE_58___d38 = rg_index_1 <= 6'd58 ;
  assign rg_index_PLUS_1_ULE_57___d6 = rg_index + 6'd1 <= 6'd57 ;
  assign rg_index_ULE_57___d7 = rg_index <= 6'd57 ;
  assign rg_q_PLUS_NEG_INV_rg_q_59_60___d561 = rg_q + -(~rg_q) ;
  assign rg_s_1_ULT_rg_r_1_0_PLUS_rg_b_9_2___d63 = rg_s < sum__h1606 ;
  assign s__h1658 = rg_s - sum__h1606 ;
  assign s__h1723 =
	     IF_rg_index_1_4_ULE_58_8_THEN_IF_rg_res_1_BIT__ETC___d83 -
	     sum__h1710 ;
  assign sfdA__h131577 =
	     { 1'b0,
	       fpu_madd_fState_S4$D_OUT[128:118] != 11'd0,
	       fpu_madd_fState_S4$D_OUT[117:66],
	       3'b0 } ;
  assign sfdA__h2035 =
	     { fpu_div64_fOperands_S0$D_OUT[129:119] != 11'd0,
	       fpu_div64_fOperands_S0$D_OUT[118:67] } ;
  assign sfdA__h2039 = sfdA__h2035 << b__h4039 ;
  assign sfdBC__h115662 =
	     _7170_MINUS_fpu_madd_fState_S3_first__995_BITS__ETC___d2008 ?
	       fpu_madd_fProd_S3$D_OUT :
	       _theResult___fst__h116827 ;
  assign sfdBC__h131578 =
	     { 1'b0,
	       fpu_madd_fState_S4$D_OUT[64:54] != 11'd0,
	       fpu_madd_fState_S4$D_OUT[53:0],
	       1'b0 } ;
  assign sfdB__h2036 =
	     { fpu_div64_fOperands_S0$D_OUT[65:55] != 11'd0,
	       fpu_div64_fOperands_S0$D_OUT[54:3] } ;
  assign sfdB__h2041 = sfdB__h2036 << b__h11457 ;
  assign sfd___1__h60702 = { 1'd0, sfd__h44953[57:1] } ;
  assign sfd__h133119 =
	     fpu_madd_fState_S7$D_OUT[128] ?
	       fpu_madd_fState_S7$D_OUT[56:0] :
	       fpu_madd_fState_S7$D_OUT[113:57] ;
  assign sfd__h142040 =
	     { 1'b0,
	       fpu_madd_fState_S8$D_OUT[65:55] != 11'd0,
	       fpu_madd_fState_S8$D_OUT[54:3] } +
	     54'd1 ;
  assign sfd__h144536 = { value__h148923, 32'd0 } ;
  assign sfd__h163354 =
	     { 1'b0,
	       _theResult___fst_exp__h163336 != 11'd0,
	       _theResult___snd__h163287[56:5] } +
	     54'd1 ;
  assign sfd__h172944 =
	     { 1'b0,
	       _theResult___fst_exp__h172852 != 11'd0,
	       sfdin__h172846[56:5] } +
	     54'd1 ;
  assign sfd__h181672 =
	     { 1'b0,
	       _theResult___fst_exp__h181653 != 11'd0,
	       _theResult___snd__h181599[56:5] } +
	     54'd1 ;
  assign sfd__h183176 = { value__h187561, 32'd0 } ;
  assign sfd__h18934 = { 1'd1, fpu_div64_fOperands_S0$D_OUT[117:67] } ;
  assign sfd__h18937 = { 1'd1, fpu_div64_fOperands_S0$D_OUT[53:3] } ;
  assign sfd__h201992 =
	     { 1'b0,
	       _theResult___fst_exp__h201974 != 11'd0,
	       _theResult___snd__h201925[56:5] } +
	     54'd1 ;
  assign sfd__h211582 =
	     { 1'b0,
	       _theResult___fst_exp__h211490 != 11'd0,
	       sfdin__h211484[56:5] } +
	     54'd1 ;
  assign sfd__h220310 =
	     { 1'b0,
	       _theResult___fst_exp__h220291 != 11'd0,
	       _theResult___snd__h220237[56:5] } +
	     54'd1 ;
  assign sfd__h222115 = { value__h226500, 32'd0 } ;
  assign sfd__h240931 =
	     { 1'b0,
	       _theResult___fst_exp__h240913 != 11'd0,
	       _theResult___snd__h240864[56:5] } +
	     54'd1 ;
  assign sfd__h250521 =
	     { 1'b0,
	       _theResult___fst_exp__h250429 != 11'd0,
	       sfdin__h250423[56:5] } +
	     54'd1 ;
  assign sfd__h259249 =
	     { 1'b0,
	       _theResult___fst_exp__h259230 != 11'd0,
	       _theResult___snd__h259176[56:5] } +
	     54'd1 ;
  assign sfd__h261975 = { value__h270197, 3'd0 } ;
  assign sfd__h277778 =
	     { 1'b0,
	       _theResult___fst_exp__h277686 != 8'd0,
	       sfdin__h277680[56:34] } +
	     25'd1 ;
  assign sfd__h286360 =
	     { 1'b0,
	       _theResult___fst_exp__h286342 != 8'd0,
	       _theResult___snd__h286293[56:34] } +
	     25'd1 ;
  assign sfd__h295544 =
	     { 1'b0,
	       _theResult___fst_exp__h295452 != 8'd0,
	       sfdin__h295446[56:34] } +
	     25'd1 ;
  assign sfd__h304156 =
	     { 1'b0,
	       _theResult___fst_exp__h304137 != 8'd0,
	       _theResult___snd__h304083[56:34] } +
	     25'd1 ;
  assign sfd__h304707 =
	     (resWire$wget[67:57] == 11'd2047 &&
	      resWire$wget[56:5] != 52'd0) ?
	       _theResult___snd_fst_sfd__h261925 :
	       _theResult___fst_sfd__h304701 ;
  assign sfd__h42982 =
	     { 1'b0,
	       fpu_div64_fState_S4$D_OUT[64:54] != 11'd0,
	       fpu_div64_fState_S4$D_OUT[53:2] } +
	     54'd1 ;
  assign sfd__h44951 = { value__h53174, 4'd0 } ;
  assign sfd__h44953 = sfd__h44951 << x__h60732 ;
  assign sfd__h45004 = { 1'd1, fpu_sqr64_fOperand_S0$D_OUT[53:3] } ;
  assign sfd__h95416 =
	     { 1'b0,
	       fpu_sqr64_fState_S4$D_OUT[64:54] != 11'd0,
	       fpu_sqr64_fState_S4$D_OUT[53:2] } +
	     54'd1 ;
  assign sfd__h99402 = { 1'd1, _theResult___fst_sfd__h96608[50:0] } ;
  assign sfd__h99405 = { 1'd1, fpu_madd_fOperand_S0$D_OUT[117:67] } ;
  assign sfd__h99408 = { 1'd1, fpu_madd_fOperand_S0$D_OUT[53:3] } ;
  assign sfdin__h130943 =
	     sfdBC__h115662[105] ?
	       _theResult___snd__h130966 :
	       _theResult___snd__h130980 ;
  assign sfdin__h141369 =
	     sfd__h133119[56] ?
	       _theResult___snd__h141392 :
	       _theResult___snd__h141406 ;
  assign sfdin__h172846 =
	     _theResult____h164614[56] ?
	       _theResult___snd__h172863 :
	       _theResult___snd__h172874 ;
  assign sfdin__h211484 =
	     _theResult____h203252[56] ?
	       _theResult___snd__h211501 :
	       _theResult___snd__h211512 ;
  assign sfdin__h250423 =
	     _theResult____h242191[56] ?
	       _theResult___snd__h250440 :
	       _theResult___snd__h250451 ;
  assign sfdin__h277680 =
	     _theResult____h269577[56] ?
	       _theResult___snd__h277697 :
	       _theResult___snd__h277708 ;
  assign sfdin__h295446 =
	     _theResult____h287214[56] ?
	       _theResult___snd__h295463 :
	       _theResult___snd__h295474 ;
  assign sfdin__h34118 =
	     (fpu_div64_fState_S3$D_OUT[120:110] == 11'd2047) ?
	       _theResult___snd_snd_snd__h33963 :
	       fpu_div64_fState_S3$D_OUT[57:0] ;
  assign sfdin__h42327 =
	     sfdin__h34118[57] ?
	       _theResult___snd__h42350 :
	       _theResult___snd__h42365 ;
  assign sfdin__h94744 =
	     fpu_sqr64_fState_S3$D_OUT[58] ?
	       _theResult___snd__h94767 :
	       _theResult___snd__h94782 ;
  assign sfdlsb__h116825 = x__h116896 != 106'd0 ;
  assign sfdlsb__h32643 = x__h32762 != 58'd0 ;
  assign sum__h1606 = rg_r_1 + rg_b ;
  assign sum__h1710 =
	     IF_rg_index_1_4_ULE_58_8_THEN_IF_rg_res_1_BIT__ETC___d69 +
	     IF_rg_index_1_4_ULE_58_8_THEN_IF_rg_res_1_BIT__ETC___d49 ;
  assign theResult___fst_exp2290_MINUS_1023__q11 =
	     _theResult___fst_exp__h42290 - 11'd1023 ;
  assign value41307_BITS_10_TO_0_MINUS_1023__q28 =
	     value__h141307[10:0] - 11'd1023 ;
  assign value_BIT_52___h53270 = fpu_sqr64_fOperand_S0$D_OUT[65:55] != 11'd0 ;
  assign value__h130883 = fpu_madd_fState_S3$D_OUT[12:0] + 13'd1023 ;
  assign value__h141307 = fpu_madd_fState_S7$D_OUT[126:114] + 13'd1023 ;
  assign value__h148923 =
	     { 1'b0, iFifo$D_OUT[167:160] != 8'd0, iFifo$D_OUT[159:137] } ;
  assign value__h187561 =
	     { 1'b0, iFifo$D_OUT[102:95] != 8'd0, iFifo$D_OUT[94:72] } ;
  assign value__h226500 =
	     { 1'b0, iFifo$D_OUT[37:30] != 8'd0, iFifo$D_OUT[29:7] } ;
  assign value__h270197 =
	     { 1'b0, resWire$wget[67:57] != 11'd0, resWire$wget[56:5] } ;
  assign value__h31374 =
	     IF_fpu_div64_fOperands_S0_first__06_BITS_129_T_ETC___d352 +
	     13'd1023 ;
  assign value__h31429 = { 1'b0, sfdA__h2039 } ;
  assign value__h31550 =
	     13'd7170 -
	     IF_fpu_div64_fOperands_S0_first__06_BITS_129_T_ETC___d352 ;
  assign value__h32541 = rg_r[115] ? rg_r + b__h32583 : rg_r ;
  assign value__h32661 =
	     IF_rg_r_BIT_115_THEN_rg_q_PLUS_NEG_INV_rg_q_59_ETC__q10[56:0] >>
	     fpu_div64_fState_S2$D_OUT[10:0] ;
  assign value__h53174 =
	     { 1'b0,
	       value_BIT_52___h53270,
	       fpu_sqr64_fOperand_S0$D_OUT[54:3] } ;
  assign x__h114243 =
	     { fpu_madd_fOperand_S0$D_OUT[129:119] != 11'd0,
	       fpu_madd_fOperand_S0$D_OUT[118:67] } ;
  assign x__h114255 =
	     { fpu_madd_fOperand_S0$D_OUT[65:55] != 11'd0,
	       fpu_madd_fOperand_S0$D_OUT[54:3] } ;
  assign x__h116896 = fpu_madd_fProd_S3$D_OUT << x__h116929 ;
  assign x__h116929 =
	     13'd106 -
	     _7170_MINUS_fpu_madd_fState_S3_first__995_BITS__ETC___d2007 ;
  assign x__h131406 =
	     fpu_madd_fState_S3_first__995_BITS_12_TO_0_001_ETC___d2002 ?
	       _theResult___snd_snd_snd__h131369 :
	       2'd3 ;
  assign x__h131940 =
	     { 1'b0,
	       NOT_fpu_madd_fState_S4_first__547_BIT_130_553__ETC___d2584 ?
		 { fpu_madd_fState_S4$D_OUT[64:54] != 11'd0,
		   fpu_madd_fState_S4$D_OUT[53:0],
		   1'b0 } :
		 { fpu_madd_fState_S4$D_OUT[128:118] != 11'd0,
		   fpu_madd_fState_S4$D_OUT[117:66],
		   3'b0 } } ;
  assign x__h131944 =
	     { 1'b0,
	       NOT_fpu_madd_fState_S4_first__547_BIT_130_553__ETC___d2584 ?
		 { fpu_madd_fState_S4$D_OUT[128:118] != 11'd0,
		   fpu_madd_fState_S4$D_OUT[117:66],
		   3'b0 } :
		 { fpu_madd_fState_S4$D_OUT[64:54] != 11'd0,
		   fpu_madd_fState_S4$D_OUT[53:0],
		   1'b0 } } ;
  assign x__h132359 =
	     fpu_madd_fState_S5$D_OUT[215] ?
	       fpu_madd_fState_S5$D_OUT[56:0] :
	       (((fpu_madd_fState_S5$D_OUT[126:114] ^ 13'h1000) < 13'd4153) ?
		  result__h132372 :
		  ((fpu_madd_fState_S5$D_OUT[56:0] == 57'd0) ?
		     fpu_madd_fState_S5$D_OUT[56:0] :
		     57'd1)) ;
  assign x__h132471 = 13'd57 - fpu_madd_fState_S5$D_OUT[126:114] ;
  assign x__h132871 =
	     fpu_madd_fState_S6$D_OUT[113:57] +
	     fpu_madd_fState_S6$D_OUT[56:0] ;
  assign x__h132880 =
	     fpu_madd_fState_S6$D_OUT[113:57] -
	     fpu_madd_fState_S6$D_OUT[56:0] ;
  assign x__h141760 = fpu_madd_fState_S7$D_OUT[202] ? 2'd0 : guard__h133123 ;
  assign x__h165324 = sfd__h144536 << x__h165357 ;
  assign x__h165357 =
	     12'd57 -
	     _3074_MINUS_SEXT_iFifo_first__087_BITS_167_TO_1_ETC___d3326 ;
  assign x__h203962 = sfd__h183176 << x__h203995 ;
  assign x__h203995 =
	     12'd57 -
	     _3074_MINUS_SEXT_iFifo_first__087_BITS_102_TO_9_ETC___d4809 ;
  assign x__h242901 = sfd__h222115 << x__h242934 ;
  assign x__h242934 =
	     12'd57 -
	     _3074_MINUS_SEXT_iFifo_first__087_BITS_37_TO_30_ETC___d4034 ;
  assign x__h287924 = sfd__h261975 << x__h287957 ;
  assign x__h287957 =
	     12'd57 -
	     _3970_MINUS_SEXT_resWire_wget__410_BITS_67_TO_5_ETC___d6034 ;
  assign x__h31426 = { value__h31429, 60'd0 } ;
  assign x__h31487 = { sfdB__h2041, 4'b0 } ;
  assign x__h31541 =
	     fpu_div64_fOperands_S0_first__06_BITS_129_TO_1_ETC___d363 ?
	       11'd0 :
	       _theResult___fst__h31322 ;
  assign x__h32762 =
	     { 1'd0,
	       IF_rg_r_BIT_115_THEN_rg_q_PLUS_NEG_INV_rg_q_59_ETC__q10[56:0] } <<
	     x__h32769 ;
  assign x__h32769 = 11'd58 - fpu_div64_fState_S2$D_OUT[10:0] ;
  assign x__h33052 =
	     (value__h32541[114:58] == 57'd0) ?
	       _theResult____h32523 :
	       result__h32617 ;
  assign x__h42705 =
	     (sfdin__h34118[57] &&
	      IF_IF_fpu_div64_fState_S3_first__86_BITS_120_T_ETC___d643 ==
	      12'd1023) ?
	       2'd3 :
	       _theResult___snd_fst__h42439 ;
  assign x__h52551 = x__h52569 + 13'd1024 ;
  assign x__h52569 =
	     { IF_fpu_sqr64_fOperand_S0_first__059_BITS_65_TO_ETC__q17[11],
	       IF_fpu_sqr64_fOperand_S0_first__059_BITS_65_TO_ETC__q17 } ;
  assign x__h60693 =
	     IF_fpu_sqr64_fOperand_S0_first__059_BITS_65_TO_ETC___d1195[0] ?
	       sfd__h44953 :
	       sfd___1__h60702 ;
  assign x__h60732 =
	     IF_fpu_sqr64_fOperand_S0_first__059_BITS_65_TO_ETC___d1193 -
	     6'd1 ;
  assign x__h85465 =
	     IF_fpu_sqr64_fState_S1_first__216_BIT_57_226_T_ETC___d1342[0] ?
	       IF_fpu_sqr64_fState_S1_first__216_BIT_57_226_T_ETC___d1342 +
	       7'd1 :
	       IF_fpu_sqr64_fState_S1_first__216_BIT_57_226_T_ETC___d1342 ;
  assign x__h85931 = rg_res[116] ? rg_res[115:0] : 116'd0 ;
  assign x__h86149 = (rg_s == 116'd0) ? x__h85931[58:0] : result__h85925 ;
  assign x__h95138 =
	     (fpu_sqr64_fState_S3$D_OUT[58] &&
	      IF_fpu_sqr64_fState_S3_first__375_BITS_121_TO__ETC___d1389 ==
	      12'd1023) ?
	       2'd3 :
	       _theResult___snd_fst__h94856 ;
  assign x__h96539 =
	     fpu_madd_fOperand_S0$D_OUT[195] ?
	       fpu_madd_fOperand_S0$D_OUT[193:183] :
	       11'd0 ;
  always@(fpu_div64_fState_S4$D_OUT or
	  out_sfd__h43479 or _theResult___sfd__h43476)
  begin
    case (fpu_div64_fState_S4$D_OUT[1:0])
      2'b0, 2'b01:
	  CASE_fpu_div64_fState_S4D_OUT_BITS_1_TO_0_0b0_ETC__q1 =
	      fpu_div64_fState_S4$D_OUT[53:2];
      2'b10:
	  CASE_fpu_div64_fState_S4D_OUT_BITS_1_TO_0_0b0_ETC__q1 =
	      out_sfd__h43479;
      2'b11:
	  CASE_fpu_div64_fState_S4D_OUT_BITS_1_TO_0_0b0_ETC__q1 =
	      _theResult___sfd__h43476;
    endcase
  end
  always@(fpu_div64_fState_S4$D_OUT or _theResult___sfd__h43476)
  begin
    case (fpu_div64_fState_S4$D_OUT[1:0])
      2'b0:
	  CASE_fpu_div64_fState_S4D_OUT_BITS_1_TO_0_0b0_ETC__q2 =
	      fpu_div64_fState_S4$D_OUT[53:2];
      2'b01, 2'b10, 2'b11:
	  CASE_fpu_div64_fState_S4D_OUT_BITS_1_TO_0_0b0_ETC__q2 =
	      _theResult___sfd__h43476;
    endcase
  end
  always@(fpu_div64_fState_S4$D_OUT or
	  CASE_fpu_div64_fState_S4D_OUT_BITS_1_TO_0_0b0_ETC__q1 or
	  CASE_fpu_div64_fState_S4D_OUT_BITS_1_TO_0_0b0_ETC__q2 or
	  _theResult___sfd__h43476)
  begin
    case (fpu_div64_fState_S4$D_OUT[68:66])
      3'd0:
	  _theResult___fst_sfd__h43554 =
	      CASE_fpu_div64_fState_S4D_OUT_BITS_1_TO_0_0b0_ETC__q1;
      3'd1:
	  _theResult___fst_sfd__h43554 =
	      CASE_fpu_div64_fState_S4D_OUT_BITS_1_TO_0_0b0_ETC__q2;
      3'd2:
	  _theResult___fst_sfd__h43554 =
	      (fpu_div64_fState_S4$D_OUT[1:0] == 2'b0 ||
	       fpu_div64_fState_S4$D_OUT[65]) ?
		fpu_div64_fState_S4$D_OUT[53:2] :
		_theResult___sfd__h43476;
      3'd3:
	  _theResult___fst_sfd__h43554 =
	      (fpu_div64_fState_S4$D_OUT[1:0] == 2'b0) ?
		fpu_div64_fState_S4$D_OUT[53:2] :
		(fpu_div64_fState_S4$D_OUT[65] ?
		   _theResult___sfd__h43476 :
		   fpu_div64_fState_S4$D_OUT[53:2]);
      3'd4: _theResult___fst_sfd__h43554 = fpu_div64_fState_S4$D_OUT[53:2];
      default: _theResult___fst_sfd__h43554 = 52'd0;
    endcase
  end
  always@(fpu_sqr64_fState_S4$D_OUT or
	  out_sfd__h95913 or _theResult___sfd__h95910)
  begin
    case (fpu_sqr64_fState_S4$D_OUT[1:0])
      2'b0, 2'b01:
	  CASE_fpu_sqr64_fState_S4D_OUT_BITS_1_TO_0_0b0_ETC__q3 =
	      fpu_sqr64_fState_S4$D_OUT[53:2];
      2'b10:
	  CASE_fpu_sqr64_fState_S4D_OUT_BITS_1_TO_0_0b0_ETC__q3 =
	      out_sfd__h95913;
      2'b11:
	  CASE_fpu_sqr64_fState_S4D_OUT_BITS_1_TO_0_0b0_ETC__q3 =
	      _theResult___sfd__h95910;
    endcase
  end
  always@(fpu_sqr64_fState_S4$D_OUT or _theResult___sfd__h95910)
  begin
    case (fpu_sqr64_fState_S4$D_OUT[1:0])
      2'b0:
	  CASE_fpu_sqr64_fState_S4D_OUT_BITS_1_TO_0_0b0_ETC__q4 =
	      fpu_sqr64_fState_S4$D_OUT[53:2];
      2'b01, 2'b10, 2'b11:
	  CASE_fpu_sqr64_fState_S4D_OUT_BITS_1_TO_0_0b0_ETC__q4 =
	      _theResult___sfd__h95910;
    endcase
  end
  always@(fpu_sqr64_fState_S4$D_OUT or
	  CASE_fpu_sqr64_fState_S4D_OUT_BITS_1_TO_0_0b0_ETC__q3 or
	  CASE_fpu_sqr64_fState_S4D_OUT_BITS_1_TO_0_0b0_ETC__q4 or
	  _theResult___sfd__h95910)
  begin
    case (fpu_sqr64_fState_S4$D_OUT[68:66])
      3'd0:
	  _theResult___fst_sfd__h95988 =
	      CASE_fpu_sqr64_fState_S4D_OUT_BITS_1_TO_0_0b0_ETC__q3;
      3'd1:
	  _theResult___fst_sfd__h95988 =
	      CASE_fpu_sqr64_fState_S4D_OUT_BITS_1_TO_0_0b0_ETC__q4;
      3'd2:
	  _theResult___fst_sfd__h95988 =
	      (fpu_sqr64_fState_S4$D_OUT[1:0] == 2'b0 ||
	       fpu_sqr64_fState_S4$D_OUT[65]) ?
		fpu_sqr64_fState_S4$D_OUT[53:2] :
		_theResult___sfd__h95910;
      3'd3:
	  _theResult___fst_sfd__h95988 =
	      (fpu_sqr64_fState_S4$D_OUT[1:0] == 2'b0) ?
		fpu_sqr64_fState_S4$D_OUT[53:2] :
		(fpu_sqr64_fState_S4$D_OUT[65] ?
		   _theResult___sfd__h95910 :
		   fpu_sqr64_fState_S4$D_OUT[53:2]);
      3'd4: _theResult___fst_sfd__h95988 = fpu_sqr64_fState_S4$D_OUT[53:2];
      default: _theResult___fst_sfd__h95988 = 52'd0;
    endcase
  end
  always@(fpu_madd_fState_S8$D_OUT or
	  out_sfd__h142545 or _theResult___sfd__h142542)
  begin
    case (fpu_madd_fState_S8$D_OUT[2:1])
      2'b0, 2'b01:
	  CASE_fpu_madd_fState_S8D_OUT_BITS_2_TO_1_0b0__ETC__q5 =
	      fpu_madd_fState_S8$D_OUT[54:3];
      2'b10:
	  CASE_fpu_madd_fState_S8D_OUT_BITS_2_TO_1_0b0__ETC__q5 =
	      out_sfd__h142545;
      2'b11:
	  CASE_fpu_madd_fState_S8D_OUT_BITS_2_TO_1_0b0__ETC__q5 =
	      _theResult___sfd__h142542;
    endcase
  end
  always@(fpu_madd_fState_S8$D_OUT or _theResult___sfd__h142542)
  begin
    case (fpu_madd_fState_S8$D_OUT[2:1])
      2'b0:
	  CASE_fpu_madd_fState_S8D_OUT_BITS_2_TO_1_0b0__ETC__q6 =
	      fpu_madd_fState_S8$D_OUT[54:3];
      2'b01, 2'b10, 2'b11:
	  CASE_fpu_madd_fState_S8D_OUT_BITS_2_TO_1_0b0__ETC__q6 =
	      _theResult___sfd__h142542;
    endcase
  end
  always@(fpu_madd_fState_S8$D_OUT or
	  CASE_fpu_madd_fState_S8D_OUT_BITS_2_TO_1_0b0__ETC__q5 or
	  CASE_fpu_madd_fState_S8D_OUT_BITS_2_TO_1_0b0__ETC__q6 or
	  _theResult___sfd__h142542)
  begin
    case (fpu_madd_fState_S8$D_OUT[70:68])
      3'd0:
	  _theResult___fst_sfd__h142620 =
	      CASE_fpu_madd_fState_S8D_OUT_BITS_2_TO_1_0b0__ETC__q5;
      3'd1:
	  _theResult___fst_sfd__h142620 =
	      CASE_fpu_madd_fState_S8D_OUT_BITS_2_TO_1_0b0__ETC__q6;
      3'd2:
	  _theResult___fst_sfd__h142620 =
	      (fpu_madd_fState_S8$D_OUT[2:1] == 2'b0 ||
	       fpu_madd_fState_S8$D_OUT[66]) ?
		fpu_madd_fState_S8$D_OUT[54:3] :
		_theResult___sfd__h142542;
      3'd3:
	  _theResult___fst_sfd__h142620 =
	      (fpu_madd_fState_S8$D_OUT[2:1] == 2'b0) ?
		fpu_madd_fState_S8$D_OUT[54:3] :
		(fpu_madd_fState_S8$D_OUT[66] ?
		   _theResult___sfd__h142542 :
		   fpu_madd_fState_S8$D_OUT[54:3]);
      3'd4: _theResult___fst_sfd__h142620 = fpu_madd_fState_S8$D_OUT[54:3];
      default: _theResult___fst_sfd__h142620 = 52'd0;
    endcase
  end
  always@(iFifo$D_OUT)
  begin
    case (iFifo$D_OUT[6:4])
      3'd0, 3'd1: _theResult___fst_exp__h148291 = 11'd2047;
      3'd2:
	  _theResult___fst_exp__h148291 =
	      iFifo$D_OUT[168] ? 11'd2046 : 11'd2047;
      3'd3:
	  _theResult___fst_exp__h148291 =
	      iFifo$D_OUT[168] ? 11'd2047 : 11'd2046;
      3'd4: _theResult___fst_exp__h148291 = 11'd2046;
      default: _theResult___fst_exp__h148291 = 11'd0;
    endcase
  end
  always@(iFifo$D_OUT)
  begin
    case (iFifo$D_OUT[6:4])
      3'd0, 3'd1: _theResult___fst_sfd__h148292 = 52'd0;
      3'd2:
	  _theResult___fst_sfd__h148292 =
	      iFifo$D_OUT[168] ? 52'hFFFFFFFFFFFFF : 52'd0;
      3'd3:
	  _theResult___fst_sfd__h148292 =
	      iFifo$D_OUT[168] ? 52'd0 : 52'hFFFFFFFFFFFFF;
      3'd4: _theResult___fst_sfd__h148292 = 52'hFFFFFFFFFFFFF;
      default: _theResult___fst_sfd__h148292 = 52'd0;
    endcase
  end
  always@(iFifo$D_OUT)
  begin
    case (iFifo$D_OUT[6:4])
      3'd0, 3'd1: _theResult___fst_exp__h186931 = 11'd2047;
      3'd2:
	  _theResult___fst_exp__h186931 =
	      iFifo$D_OUT[103] ? 11'd2046 : 11'd2047;
      3'd3:
	  _theResult___fst_exp__h186931 =
	      iFifo$D_OUT[103] ? 11'd2047 : 11'd2046;
      3'd4: _theResult___fst_exp__h186931 = 11'd2046;
      default: _theResult___fst_exp__h186931 = 11'd0;
    endcase
  end
  always@(iFifo$D_OUT)
  begin
    case (iFifo$D_OUT[6:4])
      3'd0, 3'd1: _theResult___fst_exp__h225870 = 11'd2047;
      3'd2:
	  _theResult___fst_exp__h225870 =
	      iFifo$D_OUT[38] ? 11'd2046 : 11'd2047;
      3'd3:
	  _theResult___fst_exp__h225870 =
	      iFifo$D_OUT[38] ? 11'd2047 : 11'd2046;
      3'd4: _theResult___fst_exp__h225870 = 11'd2046;
      default: _theResult___fst_exp__h225870 = 11'd0;
    endcase
  end
  always@(iFifo$D_OUT)
  begin
    case (iFifo$D_OUT[6:4])
      3'd0, 3'd1: _theResult___fst_sfd__h186932 = 52'd0;
      3'd2:
	  _theResult___fst_sfd__h186932 =
	      iFifo$D_OUT[103] ? 52'hFFFFFFFFFFFFF : 52'd0;
      3'd3:
	  _theResult___fst_sfd__h186932 =
	      iFifo$D_OUT[103] ? 52'd0 : 52'hFFFFFFFFFFFFF;
      3'd4: _theResult___fst_sfd__h186932 = 52'hFFFFFFFFFFFFF;
      default: _theResult___fst_sfd__h186932 = 52'd0;
    endcase
  end
  always@(iFifo$D_OUT)
  begin
    case (iFifo$D_OUT[6:4])
      3'd0, 3'd1: _theResult___fst_sfd__h225871 = 52'd0;
      3'd2:
	  _theResult___fst_sfd__h225871 =
	      iFifo$D_OUT[38] ? 52'hFFFFFFFFFFFFF : 52'd0;
      3'd3:
	  _theResult___fst_sfd__h225871 =
	      iFifo$D_OUT[38] ? 52'd0 : 52'hFFFFFFFFFFFFF;
      3'd4: _theResult___fst_sfd__h225871 = 52'hFFFFFFFFFFFFF;
      default: _theResult___fst_sfd__h225871 = 52'd0;
    endcase
  end
  always@(fpu_div64_fOperands_S0$D_OUT or
	  fpu_div64_fOperands_S0_first__06_BIT_130_03_EQ_ETC___d405)
  begin
    case (fpu_div64_fOperands_S0$D_OUT[2:0])
      3'd0, 3'd1: _theResult___fst_exp__h19467 = 11'd2047;
      3'd2:
	  _theResult___fst_exp__h19467 =
	      fpu_div64_fOperands_S0_first__06_BIT_130_03_EQ_ETC___d405 ?
		11'd2047 :
		11'd2046;
      3'd3:
	  _theResult___fst_exp__h19467 =
	      fpu_div64_fOperands_S0_first__06_BIT_130_03_EQ_ETC___d405 ?
		11'd2046 :
		11'd2047;
      3'd4: _theResult___fst_exp__h19467 = 11'd2046;
      default: _theResult___fst_exp__h19467 = 11'd0;
    endcase
  end
  always@(fpu_div64_fOperands_S0$D_OUT or
	  fpu_div64_fOperands_S0_first__06_BIT_130_03_EQ_ETC___d405)
  begin
    case (fpu_div64_fOperands_S0$D_OUT[2:0])
      3'd0, 3'd1: _theResult___fst_sfd__h19468 = 52'd0;
      3'd2:
	  _theResult___fst_sfd__h19468 =
	      fpu_div64_fOperands_S0_first__06_BIT_130_03_EQ_ETC___d405 ?
		52'd0 :
		52'hFFFFFFFFFFFFF;
      3'd3:
	  _theResult___fst_sfd__h19468 =
	      fpu_div64_fOperands_S0_first__06_BIT_130_03_EQ_ETC___d405 ?
		52'hFFFFFFFFFFFFF :
		52'd0;
      3'd4: _theResult___fst_sfd__h19468 = 52'hFFFFFFFFFFFFF;
      default: _theResult___fst_sfd__h19468 = 52'd0;
    endcase
  end
  always@(fpu_div64_fOperands_S0$D_OUT or
	  fpu_div64_fOperands_S0_first__06_BIT_130_03_EQ_ETC___d405)
  begin
    case (fpu_div64_fOperands_S0$D_OUT[2:0])
      3'd0: _theResult___fst_sfd__h19957 = 52'd0;
      3'd1: _theResult___fst_sfd__h19957 = 52'd1;
      3'd2:
	  _theResult___fst_sfd__h19957 =
	      fpu_div64_fOperands_S0_first__06_BIT_130_03_EQ_ETC___d405 ?
		52'd1 :
		52'd0;
      3'd3:
	  _theResult___fst_sfd__h19957 =
	      fpu_div64_fOperands_S0_first__06_BIT_130_03_EQ_ETC___d405 ?
		52'd0 :
		52'd1;
      default: _theResult___fst_sfd__h19957 = 52'd0;
    endcase
  end
  always@(fpu_div64_fOperands_S0$D_OUT or
	  fpu_div64_fOperands_S0_first__06_BIT_130_03_EQ_ETC___d405)
  begin
    case (fpu_div64_fOperands_S0$D_OUT[2:0])
      3'd0, 3'd1, 3'd2, 3'd3:
	  CASE_fpu_div64_fOperands_S0D_OUT_BITS_2_TO_0__ETC__q9 =
	      !fpu_div64_fOperands_S0_first__06_BIT_130_03_EQ_ETC___d405;
      default: CASE_fpu_div64_fOperands_S0D_OUT_BITS_2_TO_0__ETC__q9 =
		   fpu_div64_fOperands_S0$D_OUT[2:0] == 3'd4 &&
		   !fpu_div64_fOperands_S0_first__06_BIT_130_03_EQ_ETC___d405;
    endcase
  end
  always@(fpu_div64_fState_S4$D_OUT or
	  out_exp__h43478 or _theResult___exp__h43475)
  begin
    case (fpu_div64_fState_S4$D_OUT[1:0])
      2'b0, 2'b01:
	  CASE_fpu_div64_fState_S4D_OUT_BITS_1_TO_0_0b0_ETC__q14 =
	      fpu_div64_fState_S4$D_OUT[64:54];
      2'b10:
	  CASE_fpu_div64_fState_S4D_OUT_BITS_1_TO_0_0b0_ETC__q14 =
	      out_exp__h43478;
      2'b11:
	  CASE_fpu_div64_fState_S4D_OUT_BITS_1_TO_0_0b0_ETC__q14 =
	      _theResult___exp__h43475;
    endcase
  end
  always@(fpu_div64_fState_S4$D_OUT or _theResult___exp__h43475)
  begin
    case (fpu_div64_fState_S4$D_OUT[1:0])
      2'b0:
	  CASE_fpu_div64_fState_S4D_OUT_BITS_1_TO_0_0b0_ETC__q15 =
	      fpu_div64_fState_S4$D_OUT[64:54];
      2'b01, 2'b10, 2'b11:
	  CASE_fpu_div64_fState_S4D_OUT_BITS_1_TO_0_0b0_ETC__q15 =
	      _theResult___exp__h43475;
    endcase
  end
  always@(fpu_div64_fState_S4$D_OUT or
	  CASE_fpu_div64_fState_S4D_OUT_BITS_1_TO_0_0b0_ETC__q14 or
	  CASE_fpu_div64_fState_S4D_OUT_BITS_1_TO_0_0b0_ETC__q15 or
	  _theResult___exp__h43475)
  begin
    case (fpu_div64_fState_S4$D_OUT[68:66])
      3'd0:
	  _theResult___fst_exp__h43553 =
	      CASE_fpu_div64_fState_S4D_OUT_BITS_1_TO_0_0b0_ETC__q14;
      3'd1:
	  _theResult___fst_exp__h43553 =
	      CASE_fpu_div64_fState_S4D_OUT_BITS_1_TO_0_0b0_ETC__q15;
      3'd2:
	  _theResult___fst_exp__h43553 =
	      (fpu_div64_fState_S4$D_OUT[1:0] == 2'b0 ||
	       fpu_div64_fState_S4$D_OUT[65]) ?
		fpu_div64_fState_S4$D_OUT[64:54] :
		_theResult___exp__h43475;
      3'd3:
	  _theResult___fst_exp__h43553 =
	      (fpu_div64_fState_S4$D_OUT[1:0] == 2'b0) ?
		fpu_div64_fState_S4$D_OUT[64:54] :
		(fpu_div64_fState_S4$D_OUT[65] ?
		   _theResult___exp__h43475 :
		   fpu_div64_fState_S4$D_OUT[64:54]);
      3'd4: _theResult___fst_exp__h43553 = fpu_div64_fState_S4$D_OUT[64:54];
      default: _theResult___fst_exp__h43553 = 11'd0;
    endcase
  end
  always@(fpu_sqr64_fState_S4$D_OUT or
	  out_exp__h95912 or _theResult___exp__h95909)
  begin
    case (fpu_sqr64_fState_S4$D_OUT[1:0])
      2'b0, 2'b01:
	  CASE_fpu_sqr64_fState_S4D_OUT_BITS_1_TO_0_0b0_ETC__q21 =
	      fpu_sqr64_fState_S4$D_OUT[64:54];
      2'b10:
	  CASE_fpu_sqr64_fState_S4D_OUT_BITS_1_TO_0_0b0_ETC__q21 =
	      out_exp__h95912;
      2'b11:
	  CASE_fpu_sqr64_fState_S4D_OUT_BITS_1_TO_0_0b0_ETC__q21 =
	      _theResult___exp__h95909;
    endcase
  end
  always@(fpu_sqr64_fState_S4$D_OUT or _theResult___exp__h95909)
  begin
    case (fpu_sqr64_fState_S4$D_OUT[1:0])
      2'b0:
	  CASE_fpu_sqr64_fState_S4D_OUT_BITS_1_TO_0_0b0_ETC__q22 =
	      fpu_sqr64_fState_S4$D_OUT[64:54];
      2'b01, 2'b10, 2'b11:
	  CASE_fpu_sqr64_fState_S4D_OUT_BITS_1_TO_0_0b0_ETC__q22 =
	      _theResult___exp__h95909;
    endcase
  end
  always@(fpu_sqr64_fState_S4$D_OUT or
	  CASE_fpu_sqr64_fState_S4D_OUT_BITS_1_TO_0_0b0_ETC__q21 or
	  CASE_fpu_sqr64_fState_S4D_OUT_BITS_1_TO_0_0b0_ETC__q22 or
	  _theResult___exp__h95909)
  begin
    case (fpu_sqr64_fState_S4$D_OUT[68:66])
      3'd0:
	  _theResult___fst_exp__h95987 =
	      CASE_fpu_sqr64_fState_S4D_OUT_BITS_1_TO_0_0b0_ETC__q21;
      3'd1:
	  _theResult___fst_exp__h95987 =
	      CASE_fpu_sqr64_fState_S4D_OUT_BITS_1_TO_0_0b0_ETC__q22;
      3'd2:
	  _theResult___fst_exp__h95987 =
	      (fpu_sqr64_fState_S4$D_OUT[1:0] == 2'b0 ||
	       fpu_sqr64_fState_S4$D_OUT[65]) ?
		fpu_sqr64_fState_S4$D_OUT[64:54] :
		_theResult___exp__h95909;
      3'd3:
	  _theResult___fst_exp__h95987 =
	      (fpu_sqr64_fState_S4$D_OUT[1:0] == 2'b0) ?
		fpu_sqr64_fState_S4$D_OUT[64:54] :
		(fpu_sqr64_fState_S4$D_OUT[65] ?
		   _theResult___exp__h95909 :
		   fpu_sqr64_fState_S4$D_OUT[64:54]);
      3'd4: _theResult___fst_exp__h95987 = fpu_sqr64_fState_S4$D_OUT[64:54];
      default: _theResult___fst_exp__h95987 = 11'd0;
    endcase
  end
  always@(fpu_madd_fState_S8$D_OUT or
	  out_exp__h142544 or _theResult___exp__h142541)
  begin
    case (fpu_madd_fState_S8$D_OUT[2:1])
      2'b0, 2'b01:
	  CASE_fpu_madd_fState_S8D_OUT_BITS_2_TO_1_0b0__ETC__q31 =
	      fpu_madd_fState_S8$D_OUT[65:55];
      2'b10:
	  CASE_fpu_madd_fState_S8D_OUT_BITS_2_TO_1_0b0__ETC__q31 =
	      out_exp__h142544;
      2'b11:
	  CASE_fpu_madd_fState_S8D_OUT_BITS_2_TO_1_0b0__ETC__q31 =
	      _theResult___exp__h142541;
    endcase
  end
  always@(fpu_madd_fState_S8$D_OUT or _theResult___exp__h142541)
  begin
    case (fpu_madd_fState_S8$D_OUT[2:1])
      2'b0:
	  CASE_fpu_madd_fState_S8D_OUT_BITS_2_TO_1_0b0__ETC__q32 =
	      fpu_madd_fState_S8$D_OUT[65:55];
      2'b01, 2'b10, 2'b11:
	  CASE_fpu_madd_fState_S8D_OUT_BITS_2_TO_1_0b0__ETC__q32 =
	      _theResult___exp__h142541;
    endcase
  end
  always@(fpu_madd_fState_S8$D_OUT or
	  CASE_fpu_madd_fState_S8D_OUT_BITS_2_TO_1_0b0__ETC__q31 or
	  CASE_fpu_madd_fState_S8D_OUT_BITS_2_TO_1_0b0__ETC__q32 or
	  _theResult___exp__h142541)
  begin
    case (fpu_madd_fState_S8$D_OUT[70:68])
      3'd0:
	  _theResult___fst_exp__h142619 =
	      CASE_fpu_madd_fState_S8D_OUT_BITS_2_TO_1_0b0__ETC__q31;
      3'd1:
	  _theResult___fst_exp__h142619 =
	      CASE_fpu_madd_fState_S8D_OUT_BITS_2_TO_1_0b0__ETC__q32;
      3'd2:
	  _theResult___fst_exp__h142619 =
	      (fpu_madd_fState_S8$D_OUT[2:1] == 2'b0 ||
	       fpu_madd_fState_S8$D_OUT[66]) ?
		fpu_madd_fState_S8$D_OUT[65:55] :
		_theResult___exp__h142541;
      3'd3:
	  _theResult___fst_exp__h142619 =
	      (fpu_madd_fState_S8$D_OUT[2:1] == 2'b0) ?
		fpu_madd_fState_S8$D_OUT[65:55] :
		(fpu_madd_fState_S8$D_OUT[66] ?
		   _theResult___exp__h142541 :
		   fpu_madd_fState_S8$D_OUT[65:55]);
      3'd4: _theResult___fst_exp__h142619 = fpu_madd_fState_S8$D_OUT[65:55];
      default: _theResult___fst_exp__h142619 = 11'd0;
    endcase
  end
  always@(guard__h155375 or
	  _theResult___fst_exp__h163336 or
	  out_exp__h163984 or _theResult___exp__h163981)
  begin
    case (guard__h155375)
      2'b0, 2'b01:
	  CASE_guard55375_0b0_theResult___fst_exp63336_0_ETC__q42 =
	      _theResult___fst_exp__h163336;
      2'b10:
	  CASE_guard55375_0b0_theResult___fst_exp63336_0_ETC__q42 =
	      out_exp__h163984;
      2'b11:
	  CASE_guard55375_0b0_theResult___fst_exp63336_0_ETC__q42 =
	      _theResult___exp__h163981;
    endcase
  end
  always@(guard__h155375 or
	  _theResult___fst_exp__h163336 or _theResult___exp__h163981)
  begin
    case (guard__h155375)
      2'b0:
	  CASE_guard55375_0b0_theResult___fst_exp63336_0_ETC__q43 =
	      _theResult___fst_exp__h163336;
      2'b01, 2'b10, 2'b11:
	  CASE_guard55375_0b0_theResult___fst_exp63336_0_ETC__q43 =
	      _theResult___exp__h163981;
    endcase
  end
  always@(iFifo$D_OUT or
	  CASE_guard55375_0b0_theResult___fst_exp63336_0_ETC__q42 or
	  CASE_guard55375_0b0_theResult___fst_exp63336_0_ETC__q43 or
	  IF_IF_IF_iFifo_first__087_BITS_167_TO_160_130__ETC___d3690 or
	  IF_IF_IF_iFifo_first__087_BITS_167_TO_160_130__ETC___d3692 or
	  _theResult___fst_exp__h163336)
  begin
    case (iFifo$D_OUT[6:4])
      3'd0:
	  _theResult___fst_exp__h164059 =
	      CASE_guard55375_0b0_theResult___fst_exp63336_0_ETC__q42;
      3'd1:
	  _theResult___fst_exp__h164059 =
	      CASE_guard55375_0b0_theResult___fst_exp63336_0_ETC__q43;
      3'd2:
	  _theResult___fst_exp__h164059 =
	      IF_IF_IF_iFifo_first__087_BITS_167_TO_160_130__ETC___d3690;
      3'd3:
	  _theResult___fst_exp__h164059 =
	      IF_IF_IF_iFifo_first__087_BITS_167_TO_160_130__ETC___d3692;
      3'd4: _theResult___fst_exp__h164059 = _theResult___fst_exp__h163336;
      default: _theResult___fst_exp__h164059 = 11'd0;
    endcase
  end
  always@(guard__h164624 or
	  _theResult___fst_exp__h172852 or
	  out_exp__h173574 or _theResult___exp__h173571)
  begin
    case (guard__h164624)
      2'b0, 2'b01:
	  CASE_guard64624_0b0_theResult___fst_exp72852_0_ETC__q44 =
	      _theResult___fst_exp__h172852;
      2'b10:
	  CASE_guard64624_0b0_theResult___fst_exp72852_0_ETC__q44 =
	      out_exp__h173574;
      2'b11:
	  CASE_guard64624_0b0_theResult___fst_exp72852_0_ETC__q44 =
	      _theResult___exp__h173571;
    endcase
  end
  always@(guard__h164624 or
	  _theResult___fst_exp__h172852 or _theResult___exp__h173571)
  begin
    case (guard__h164624)
      2'b0:
	  CASE_guard64624_0b0_theResult___fst_exp72852_0_ETC__q45 =
	      _theResult___fst_exp__h172852;
      2'b01, 2'b10, 2'b11:
	  CASE_guard64624_0b0_theResult___fst_exp72852_0_ETC__q45 =
	      _theResult___exp__h173571;
    endcase
  end
  always@(iFifo$D_OUT or
	  CASE_guard64624_0b0_theResult___fst_exp72852_0_ETC__q44 or
	  CASE_guard64624_0b0_theResult___fst_exp72852_0_ETC__q45 or
	  IF_IF_IF_IF_3074_MINUS_SEXT_iFifo_first__087_B_ETC___d3729 or
	  IF_IF_IF_IF_3074_MINUS_SEXT_iFifo_first__087_B_ETC___d3731 or
	  _theResult___fst_exp__h172852)
  begin
    case (iFifo$D_OUT[6:4])
      3'd0:
	  _theResult___fst_exp__h173649 =
	      CASE_guard64624_0b0_theResult___fst_exp72852_0_ETC__q44;
      3'd1:
	  _theResult___fst_exp__h173649 =
	      CASE_guard64624_0b0_theResult___fst_exp72852_0_ETC__q45;
      3'd2:
	  _theResult___fst_exp__h173649 =
	      IF_IF_IF_IF_3074_MINUS_SEXT_iFifo_first__087_B_ETC___d3729;
      3'd3:
	  _theResult___fst_exp__h173649 =
	      IF_IF_IF_IF_3074_MINUS_SEXT_iFifo_first__087_B_ETC___d3731;
      3'd4: _theResult___fst_exp__h173649 = _theResult___fst_exp__h172852;
      default: _theResult___fst_exp__h173649 = 11'd0;
    endcase
  end
  always@(guard__h173663 or
	  _theResult___fst_exp__h181653 or
	  out_exp__h182326 or _theResult___exp__h182323)
  begin
    case (guard__h173663)
      2'b0, 2'b01:
	  CASE_guard73663_0b0_theResult___fst_exp81653_0_ETC__q46 =
	      _theResult___fst_exp__h181653;
      2'b10:
	  CASE_guard73663_0b0_theResult___fst_exp81653_0_ETC__q46 =
	      out_exp__h182326;
      2'b11:
	  CASE_guard73663_0b0_theResult___fst_exp81653_0_ETC__q46 =
	      _theResult___exp__h182323;
    endcase
  end
  always@(guard__h173663 or
	  _theResult___fst_exp__h181653 or _theResult___exp__h182323)
  begin
    case (guard__h173663)
      2'b0:
	  CASE_guard73663_0b0_theResult___fst_exp81653_0_ETC__q47 =
	      _theResult___fst_exp__h181653;
      2'b01, 2'b10, 2'b11:
	  CASE_guard73663_0b0_theResult___fst_exp81653_0_ETC__q47 =
	      _theResult___exp__h182323;
    endcase
  end
  always@(iFifo$D_OUT or
	  CASE_guard73663_0b0_theResult___fst_exp81653_0_ETC__q46 or
	  CASE_guard73663_0b0_theResult___fst_exp81653_0_ETC__q47 or
	  IF_IF_IF_iFifo_first__087_BITS_167_TO_160_130__ETC___d3760 or
	  IF_IF_IF_iFifo_first__087_BITS_167_TO_160_130__ETC___d3762 or
	  _theResult___fst_exp__h181653)
  begin
    case (iFifo$D_OUT[6:4])
      3'd0:
	  _theResult___fst_exp__h182401 =
	      CASE_guard73663_0b0_theResult___fst_exp81653_0_ETC__q46;
      3'd1:
	  _theResult___fst_exp__h182401 =
	      CASE_guard73663_0b0_theResult___fst_exp81653_0_ETC__q47;
      3'd2:
	  _theResult___fst_exp__h182401 =
	      IF_IF_IF_iFifo_first__087_BITS_167_TO_160_130__ETC___d3760;
      3'd3:
	  _theResult___fst_exp__h182401 =
	      IF_IF_IF_iFifo_first__087_BITS_167_TO_160_130__ETC___d3762;
      3'd4: _theResult___fst_exp__h182401 = _theResult___fst_exp__h181653;
      default: _theResult___fst_exp__h182401 = 11'd0;
    endcase
  end
  always@(guard__h155375 or
	  _theResult___snd__h163287 or
	  out_sfd__h163985 or _theResult___sfd__h163982)
  begin
    case (guard__h155375)
      2'b0, 2'b01:
	  CASE_guard55375_0b0_theResult___snd63287_BITS__ETC__q48 =
	      _theResult___snd__h163287[56:5];
      2'b10:
	  CASE_guard55375_0b0_theResult___snd63287_BITS__ETC__q48 =
	      out_sfd__h163985;
      2'b11:
	  CASE_guard55375_0b0_theResult___snd63287_BITS__ETC__q48 =
	      _theResult___sfd__h163982;
    endcase
  end
  always@(guard__h155375 or
	  _theResult___snd__h163287 or _theResult___sfd__h163982)
  begin
    case (guard__h155375)
      2'b0:
	  CASE_guard55375_0b0_theResult___snd63287_BITS__ETC__q49 =
	      _theResult___snd__h163287[56:5];
      2'b01, 2'b10, 2'b11:
	  CASE_guard55375_0b0_theResult___snd63287_BITS__ETC__q49 =
	      _theResult___sfd__h163982;
    endcase
  end
  always@(iFifo$D_OUT or
	  CASE_guard55375_0b0_theResult___snd63287_BITS__ETC__q48 or
	  CASE_guard55375_0b0_theResult___snd63287_BITS__ETC__q49 or
	  IF_IF_IF_iFifo_first__087_BITS_167_TO_160_130__ETC___d3786 or
	  IF_IF_IF_iFifo_first__087_BITS_167_TO_160_130__ETC___d3788 or
	  _theResult___snd__h163287)
  begin
    case (iFifo$D_OUT[6:4])
      3'd0:
	  _theResult___fst_sfd__h164060 =
	      CASE_guard55375_0b0_theResult___snd63287_BITS__ETC__q48;
      3'd1:
	  _theResult___fst_sfd__h164060 =
	      CASE_guard55375_0b0_theResult___snd63287_BITS__ETC__q49;
      3'd2:
	  _theResult___fst_sfd__h164060 =
	      IF_IF_IF_iFifo_first__087_BITS_167_TO_160_130__ETC___d3786;
      3'd3:
	  _theResult___fst_sfd__h164060 =
	      IF_IF_IF_iFifo_first__087_BITS_167_TO_160_130__ETC___d3788;
      3'd4: _theResult___fst_sfd__h164060 = _theResult___snd__h163287[56:5];
      default: _theResult___fst_sfd__h164060 = 52'd0;
    endcase
  end
  always@(guard__h164624 or
	  sfdin__h172846 or out_sfd__h173575 or _theResult___sfd__h173572)
  begin
    case (guard__h164624)
      2'b0, 2'b01:
	  CASE_guard64624_0b0_sfdin72846_BITS_56_TO_5_0b_ETC__q50 =
	      sfdin__h172846[56:5];
      2'b10:
	  CASE_guard64624_0b0_sfdin72846_BITS_56_TO_5_0b_ETC__q50 =
	      out_sfd__h173575;
      2'b11:
	  CASE_guard64624_0b0_sfdin72846_BITS_56_TO_5_0b_ETC__q50 =
	      _theResult___sfd__h173572;
    endcase
  end
  always@(guard__h164624 or sfdin__h172846 or _theResult___sfd__h173572)
  begin
    case (guard__h164624)
      2'b0:
	  CASE_guard64624_0b0_sfdin72846_BITS_56_TO_5_0b_ETC__q51 =
	      sfdin__h172846[56:5];
      2'b01, 2'b10, 2'b11:
	  CASE_guard64624_0b0_sfdin72846_BITS_56_TO_5_0b_ETC__q51 =
	      _theResult___sfd__h173572;
    endcase
  end
  always@(iFifo$D_OUT or
	  CASE_guard64624_0b0_sfdin72846_BITS_56_TO_5_0b_ETC__q50 or
	  CASE_guard64624_0b0_sfdin72846_BITS_56_TO_5_0b_ETC__q51 or
	  IF_IF_IF_IF_3074_MINUS_SEXT_iFifo_first__087_B_ETC___d3813 or
	  IF_IF_IF_IF_3074_MINUS_SEXT_iFifo_first__087_B_ETC___d3815 or
	  sfdin__h172846)
  begin
    case (iFifo$D_OUT[6:4])
      3'd0:
	  _theResult___fst_sfd__h173650 =
	      CASE_guard64624_0b0_sfdin72846_BITS_56_TO_5_0b_ETC__q50;
      3'd1:
	  _theResult___fst_sfd__h173650 =
	      CASE_guard64624_0b0_sfdin72846_BITS_56_TO_5_0b_ETC__q51;
      3'd2:
	  _theResult___fst_sfd__h173650 =
	      IF_IF_IF_IF_3074_MINUS_SEXT_iFifo_first__087_B_ETC___d3813;
      3'd3:
	  _theResult___fst_sfd__h173650 =
	      IF_IF_IF_IF_3074_MINUS_SEXT_iFifo_first__087_B_ETC___d3815;
      3'd4: _theResult___fst_sfd__h173650 = sfdin__h172846[56:5];
      default: _theResult___fst_sfd__h173650 = 52'd0;
    endcase
  end
  always@(guard__h173663 or
	  _theResult___snd__h181599 or
	  out_sfd__h182327 or _theResult___sfd__h182324)
  begin
    case (guard__h173663)
      2'b0, 2'b01:
	  CASE_guard73663_0b0_theResult___snd81599_BITS__ETC__q52 =
	      _theResult___snd__h181599[56:5];
      2'b10:
	  CASE_guard73663_0b0_theResult___snd81599_BITS__ETC__q52 =
	      out_sfd__h182327;
      2'b11:
	  CASE_guard73663_0b0_theResult___snd81599_BITS__ETC__q52 =
	      _theResult___sfd__h182324;
    endcase
  end
  always@(guard__h173663 or
	  _theResult___snd__h181599 or _theResult___sfd__h182324)
  begin
    case (guard__h173663)
      2'b0:
	  CASE_guard73663_0b0_theResult___snd81599_BITS__ETC__q53 =
	      _theResult___snd__h181599[56:5];
      2'b01, 2'b10, 2'b11:
	  CASE_guard73663_0b0_theResult___snd81599_BITS__ETC__q53 =
	      _theResult___sfd__h182324;
    endcase
  end
  always@(iFifo$D_OUT or
	  CASE_guard73663_0b0_theResult___snd81599_BITS__ETC__q52 or
	  CASE_guard73663_0b0_theResult___snd81599_BITS__ETC__q53 or
	  IF_IF_IF_iFifo_first__087_BITS_167_TO_160_130__ETC___d3832 or
	  IF_IF_IF_iFifo_first__087_BITS_167_TO_160_130__ETC___d3834 or
	  _theResult___snd__h181599)
  begin
    case (iFifo$D_OUT[6:4])
      3'd0:
	  _theResult___fst_sfd__h182402 =
	      CASE_guard73663_0b0_theResult___snd81599_BITS__ETC__q52;
      3'd1:
	  _theResult___fst_sfd__h182402 =
	      CASE_guard73663_0b0_theResult___snd81599_BITS__ETC__q53;
      3'd2:
	  _theResult___fst_sfd__h182402 =
	      IF_IF_IF_iFifo_first__087_BITS_167_TO_160_130__ETC___d3832;
      3'd3:
	  _theResult___fst_sfd__h182402 =
	      IF_IF_IF_iFifo_first__087_BITS_167_TO_160_130__ETC___d3834;
      3'd4: _theResult___fst_sfd__h182402 = _theResult___snd__h181599[56:5];
      default: _theResult___fst_sfd__h182402 = 52'd0;
    endcase
  end
  always@(guard__h155375 or iFifo$D_OUT)
  begin
    case (guard__h155375)
      2'b0, 2'b01, 2'b10:
	  CASE_guard55375_0b0_iFifoD_OUT_BIT_168_0b1_iF_ETC__q54 =
	      iFifo$D_OUT[168];
      2'd3:
	  CASE_guard55375_0b0_iFifoD_OUT_BIT_168_0b1_iF_ETC__q54 =
	      guard__h155375 == 2'b11 && iFifo$D_OUT[168];
    endcase
  end
  always@(iFifo$D_OUT or
	  CASE_guard55375_0b0_iFifoD_OUT_BIT_168_0b1_iF_ETC__q54 or
	  guard__h155375)
  begin
    case (iFifo$D_OUT[6:4])
      3'd0:
	  CASE_iFifoD_OUT_BITS_6_TO_4_0_CASE_guard55375_ETC__q55 =
	      CASE_guard55375_0b0_iFifoD_OUT_BIT_168_0b1_iF_ETC__q54;
      3'd1:
	  CASE_iFifoD_OUT_BITS_6_TO_4_0_CASE_guard55375_ETC__q55 =
	      (guard__h155375 == 2'b0) ?
		iFifo$D_OUT[168] :
		(guard__h155375 == 2'b01 || guard__h155375 == 2'b10 ||
		 guard__h155375 == 2'b11) &&
		iFifo$D_OUT[168];
      3'd2, 3'd3:
	  CASE_iFifoD_OUT_BITS_6_TO_4_0_CASE_guard55375_ETC__q55 =
	      iFifo$D_OUT[168];
      default: CASE_iFifoD_OUT_BITS_6_TO_4_0_CASE_guard55375_ETC__q55 =
		   iFifo$D_OUT[6:4] == 3'd4 && iFifo$D_OUT[168];
    endcase
  end
  always@(iFifo$D_OUT)
  begin
    case (iFifo$D_OUT[6:4])
      3'd0, 3'd1, 3'd2, 3'd3:
	  IF_iFifo_first__087_BITS_6_TO_4_118_EQ_0_191_O_ETC___d3320 =
	      iFifo$D_OUT[168];
      default: IF_iFifo_first__087_BITS_6_TO_4_118_EQ_0_191_O_ETC___d3320 =
		   iFifo$D_OUT[6:4] == 3'd4 && iFifo$D_OUT[168];
    endcase
  end
  always@(guard__h164624 or iFifo$D_OUT)
  begin
    case (guard__h164624)
      2'b0, 2'b01, 2'b10:
	  CASE_guard64624_0b0_iFifoD_OUT_BIT_168_0b1_iF_ETC__q56 =
	      iFifo$D_OUT[168];
      2'd3:
	  CASE_guard64624_0b0_iFifoD_OUT_BIT_168_0b1_iF_ETC__q56 =
	      guard__h164624 == 2'b11 && iFifo$D_OUT[168];
    endcase
  end
  always@(iFifo$D_OUT or
	  CASE_guard64624_0b0_iFifoD_OUT_BIT_168_0b1_iF_ETC__q56 or
	  guard__h164624)
  begin
    case (iFifo$D_OUT[6:4])
      3'd0:
	  CASE_iFifoD_OUT_BITS_6_TO_4_0_CASE_guard64624_ETC__q57 =
	      CASE_guard64624_0b0_iFifoD_OUT_BIT_168_0b1_iF_ETC__q56;
      3'd1:
	  CASE_iFifoD_OUT_BITS_6_TO_4_0_CASE_guard64624_ETC__q57 =
	      (guard__h164624 == 2'b0) ?
		iFifo$D_OUT[168] :
		(guard__h164624 == 2'b01 || guard__h164624 == 2'b10 ||
		 guard__h164624 == 2'b11) &&
		iFifo$D_OUT[168];
      3'd2, 3'd3:
	  CASE_iFifoD_OUT_BITS_6_TO_4_0_CASE_guard64624_ETC__q57 =
	      iFifo$D_OUT[168];
      default: CASE_iFifoD_OUT_BITS_6_TO_4_0_CASE_guard64624_ETC__q57 =
		   iFifo$D_OUT[6:4] == 3'd4 && iFifo$D_OUT[168];
    endcase
  end
  always@(guard__h173663 or iFifo$D_OUT)
  begin
    case (guard__h173663)
      2'b0, 2'b01, 2'b10:
	  CASE_guard73663_0b0_iFifoD_OUT_BIT_168_0b1_iF_ETC__q58 =
	      iFifo$D_OUT[168];
      2'd3:
	  CASE_guard73663_0b0_iFifoD_OUT_BIT_168_0b1_iF_ETC__q58 =
	      guard__h173663 == 2'b11 && iFifo$D_OUT[168];
    endcase
  end
  always@(iFifo$D_OUT or
	  CASE_guard73663_0b0_iFifoD_OUT_BIT_168_0b1_iF_ETC__q58 or
	  guard__h173663)
  begin
    case (iFifo$D_OUT[6:4])
      3'd0:
	  CASE_iFifoD_OUT_BITS_6_TO_4_0_CASE_guard73663_ETC__q59 =
	      CASE_guard73663_0b0_iFifoD_OUT_BIT_168_0b1_iF_ETC__q58;
      3'd1:
	  CASE_iFifoD_OUT_BITS_6_TO_4_0_CASE_guard73663_ETC__q59 =
	      (guard__h173663 == 2'b0) ?
		iFifo$D_OUT[168] :
		(guard__h173663 == 2'b01 || guard__h173663 == 2'b10 ||
		 guard__h173663 == 2'b11) &&
		iFifo$D_OUT[168];
      3'd2, 3'd3:
	  CASE_iFifoD_OUT_BITS_6_TO_4_0_CASE_guard73663_ETC__q59 =
	      iFifo$D_OUT[168];
      default: CASE_iFifoD_OUT_BITS_6_TO_4_0_CASE_guard73663_ETC__q59 =
		   iFifo$D_OUT[6:4] == 3'd4 && iFifo$D_OUT[168];
    endcase
  end
  always@(guard__h232952 or
	  _theResult___fst_exp__h240913 or
	  out_exp__h241561 or _theResult___exp__h241558)
  begin
    case (guard__h232952)
      2'b0, 2'b01:
	  CASE_guard32952_0b0_theResult___fst_exp40913_0_ETC__q69 =
	      _theResult___fst_exp__h240913;
      2'b10:
	  CASE_guard32952_0b0_theResult___fst_exp40913_0_ETC__q69 =
	      out_exp__h241561;
      2'b11:
	  CASE_guard32952_0b0_theResult___fst_exp40913_0_ETC__q69 =
	      _theResult___exp__h241558;
    endcase
  end
  always@(guard__h232952 or
	  _theResult___fst_exp__h240913 or _theResult___exp__h241558)
  begin
    case (guard__h232952)
      2'b0:
	  CASE_guard32952_0b0_theResult___fst_exp40913_0_ETC__q70 =
	      _theResult___fst_exp__h240913;
      2'b01, 2'b10, 2'b11:
	  CASE_guard32952_0b0_theResult___fst_exp40913_0_ETC__q70 =
	      _theResult___exp__h241558;
    endcase
  end
  always@(iFifo$D_OUT or
	  CASE_guard32952_0b0_theResult___fst_exp40913_0_ETC__q69 or
	  CASE_guard32952_0b0_theResult___fst_exp40913_0_ETC__q70 or
	  IF_IF_IF_iFifo_first__087_BITS_37_TO_30_850_EQ_ETC___d4398 or
	  IF_IF_IF_iFifo_first__087_BITS_37_TO_30_850_EQ_ETC___d4400 or
	  _theResult___fst_exp__h240913)
  begin
    case (iFifo$D_OUT[6:4])
      3'd0:
	  _theResult___fst_exp__h241636 =
	      CASE_guard32952_0b0_theResult___fst_exp40913_0_ETC__q69;
      3'd1:
	  _theResult___fst_exp__h241636 =
	      CASE_guard32952_0b0_theResult___fst_exp40913_0_ETC__q70;
      3'd2:
	  _theResult___fst_exp__h241636 =
	      IF_IF_IF_iFifo_first__087_BITS_37_TO_30_850_EQ_ETC___d4398;
      3'd3:
	  _theResult___fst_exp__h241636 =
	      IF_IF_IF_iFifo_first__087_BITS_37_TO_30_850_EQ_ETC___d4400;
      3'd4: _theResult___fst_exp__h241636 = _theResult___fst_exp__h240913;
      default: _theResult___fst_exp__h241636 = 11'd0;
    endcase
  end
  always@(guard__h242201 or
	  _theResult___fst_exp__h250429 or
	  out_exp__h251151 or _theResult___exp__h251148)
  begin
    case (guard__h242201)
      2'b0, 2'b01:
	  CASE_guard42201_0b0_theResult___fst_exp50429_0_ETC__q71 =
	      _theResult___fst_exp__h250429;
      2'b10:
	  CASE_guard42201_0b0_theResult___fst_exp50429_0_ETC__q71 =
	      out_exp__h251151;
      2'b11:
	  CASE_guard42201_0b0_theResult___fst_exp50429_0_ETC__q71 =
	      _theResult___exp__h251148;
    endcase
  end
  always@(guard__h242201 or
	  _theResult___fst_exp__h250429 or _theResult___exp__h251148)
  begin
    case (guard__h242201)
      2'b0:
	  CASE_guard42201_0b0_theResult___fst_exp50429_0_ETC__q72 =
	      _theResult___fst_exp__h250429;
      2'b01, 2'b10, 2'b11:
	  CASE_guard42201_0b0_theResult___fst_exp50429_0_ETC__q72 =
	      _theResult___exp__h251148;
    endcase
  end
  always@(iFifo$D_OUT or
	  CASE_guard42201_0b0_theResult___fst_exp50429_0_ETC__q71 or
	  CASE_guard42201_0b0_theResult___fst_exp50429_0_ETC__q72 or
	  IF_IF_IF_IF_3074_MINUS_SEXT_iFifo_first__087_B_ETC___d4436 or
	  IF_IF_IF_IF_3074_MINUS_SEXT_iFifo_first__087_B_ETC___d4438 or
	  _theResult___fst_exp__h250429)
  begin
    case (iFifo$D_OUT[6:4])
      3'd0:
	  _theResult___fst_exp__h251226 =
	      CASE_guard42201_0b0_theResult___fst_exp50429_0_ETC__q71;
      3'd1:
	  _theResult___fst_exp__h251226 =
	      CASE_guard42201_0b0_theResult___fst_exp50429_0_ETC__q72;
      3'd2:
	  _theResult___fst_exp__h251226 =
	      IF_IF_IF_IF_3074_MINUS_SEXT_iFifo_first__087_B_ETC___d4436;
      3'd3:
	  _theResult___fst_exp__h251226 =
	      IF_IF_IF_IF_3074_MINUS_SEXT_iFifo_first__087_B_ETC___d4438;
      3'd4: _theResult___fst_exp__h251226 = _theResult___fst_exp__h250429;
      default: _theResult___fst_exp__h251226 = 11'd0;
    endcase
  end
  always@(guard__h251240 or
	  _theResult___fst_exp__h259230 or
	  out_exp__h259903 or _theResult___exp__h259900)
  begin
    case (guard__h251240)
      2'b0, 2'b01:
	  CASE_guard51240_0b0_theResult___fst_exp59230_0_ETC__q73 =
	      _theResult___fst_exp__h259230;
      2'b10:
	  CASE_guard51240_0b0_theResult___fst_exp59230_0_ETC__q73 =
	      out_exp__h259903;
      2'b11:
	  CASE_guard51240_0b0_theResult___fst_exp59230_0_ETC__q73 =
	      _theResult___exp__h259900;
    endcase
  end
  always@(guard__h251240 or
	  _theResult___fst_exp__h259230 or _theResult___exp__h259900)
  begin
    case (guard__h251240)
      2'b0:
	  CASE_guard51240_0b0_theResult___fst_exp59230_0_ETC__q74 =
	      _theResult___fst_exp__h259230;
      2'b01, 2'b10, 2'b11:
	  CASE_guard51240_0b0_theResult___fst_exp59230_0_ETC__q74 =
	      _theResult___exp__h259900;
    endcase
  end
  always@(iFifo$D_OUT or
	  CASE_guard51240_0b0_theResult___fst_exp59230_0_ETC__q73 or
	  CASE_guard51240_0b0_theResult___fst_exp59230_0_ETC__q74 or
	  IF_IF_IF_iFifo_first__087_BITS_37_TO_30_850_EQ_ETC___d4467 or
	  IF_IF_IF_iFifo_first__087_BITS_37_TO_30_850_EQ_ETC___d4469 or
	  _theResult___fst_exp__h259230)
  begin
    case (iFifo$D_OUT[6:4])
      3'd0:
	  _theResult___fst_exp__h259978 =
	      CASE_guard51240_0b0_theResult___fst_exp59230_0_ETC__q73;
      3'd1:
	  _theResult___fst_exp__h259978 =
	      CASE_guard51240_0b0_theResult___fst_exp59230_0_ETC__q74;
      3'd2:
	  _theResult___fst_exp__h259978 =
	      IF_IF_IF_iFifo_first__087_BITS_37_TO_30_850_EQ_ETC___d4467;
      3'd3:
	  _theResult___fst_exp__h259978 =
	      IF_IF_IF_iFifo_first__087_BITS_37_TO_30_850_EQ_ETC___d4469;
      3'd4: _theResult___fst_exp__h259978 = _theResult___fst_exp__h259230;
      default: _theResult___fst_exp__h259978 = 11'd0;
    endcase
  end
  always@(guard__h232952 or
	  _theResult___snd__h240864 or
	  out_sfd__h241562 or _theResult___sfd__h241559)
  begin
    case (guard__h232952)
      2'b0, 2'b01:
	  CASE_guard32952_0b0_theResult___snd40864_BITS__ETC__q75 =
	      _theResult___snd__h240864[56:5];
      2'b10:
	  CASE_guard32952_0b0_theResult___snd40864_BITS__ETC__q75 =
	      out_sfd__h241562;
      2'b11:
	  CASE_guard32952_0b0_theResult___snd40864_BITS__ETC__q75 =
	      _theResult___sfd__h241559;
    endcase
  end
  always@(guard__h232952 or
	  _theResult___snd__h240864 or _theResult___sfd__h241559)
  begin
    case (guard__h232952)
      2'b0:
	  CASE_guard32952_0b0_theResult___snd40864_BITS__ETC__q76 =
	      _theResult___snd__h240864[56:5];
      2'b01, 2'b10, 2'b11:
	  CASE_guard32952_0b0_theResult___snd40864_BITS__ETC__q76 =
	      _theResult___sfd__h241559;
    endcase
  end
  always@(iFifo$D_OUT or
	  CASE_guard32952_0b0_theResult___snd40864_BITS__ETC__q75 or
	  CASE_guard32952_0b0_theResult___snd40864_BITS__ETC__q76 or
	  IF_IF_IF_iFifo_first__087_BITS_37_TO_30_850_EQ_ETC___d4493 or
	  IF_IF_IF_iFifo_first__087_BITS_37_TO_30_850_EQ_ETC___d4495 or
	  _theResult___snd__h240864)
  begin
    case (iFifo$D_OUT[6:4])
      3'd0:
	  _theResult___fst_sfd__h241637 =
	      CASE_guard32952_0b0_theResult___snd40864_BITS__ETC__q75;
      3'd1:
	  _theResult___fst_sfd__h241637 =
	      CASE_guard32952_0b0_theResult___snd40864_BITS__ETC__q76;
      3'd2:
	  _theResult___fst_sfd__h241637 =
	      IF_IF_IF_iFifo_first__087_BITS_37_TO_30_850_EQ_ETC___d4493;
      3'd3:
	  _theResult___fst_sfd__h241637 =
	      IF_IF_IF_iFifo_first__087_BITS_37_TO_30_850_EQ_ETC___d4495;
      3'd4: _theResult___fst_sfd__h241637 = _theResult___snd__h240864[56:5];
      default: _theResult___fst_sfd__h241637 = 52'd0;
    endcase
  end
  always@(guard__h242201 or
	  sfdin__h250423 or out_sfd__h251152 or _theResult___sfd__h251149)
  begin
    case (guard__h242201)
      2'b0, 2'b01:
	  CASE_guard42201_0b0_sfdin50423_BITS_56_TO_5_0b_ETC__q77 =
	      sfdin__h250423[56:5];
      2'b10:
	  CASE_guard42201_0b0_sfdin50423_BITS_56_TO_5_0b_ETC__q77 =
	      out_sfd__h251152;
      2'b11:
	  CASE_guard42201_0b0_sfdin50423_BITS_56_TO_5_0b_ETC__q77 =
	      _theResult___sfd__h251149;
    endcase
  end
  always@(guard__h242201 or sfdin__h250423 or _theResult___sfd__h251149)
  begin
    case (guard__h242201)
      2'b0:
	  CASE_guard42201_0b0_sfdin50423_BITS_56_TO_5_0b_ETC__q78 =
	      sfdin__h250423[56:5];
      2'b01, 2'b10, 2'b11:
	  CASE_guard42201_0b0_sfdin50423_BITS_56_TO_5_0b_ETC__q78 =
	      _theResult___sfd__h251149;
    endcase
  end
  always@(iFifo$D_OUT or
	  CASE_guard42201_0b0_sfdin50423_BITS_56_TO_5_0b_ETC__q77 or
	  CASE_guard42201_0b0_sfdin50423_BITS_56_TO_5_0b_ETC__q78 or
	  IF_IF_IF_IF_3074_MINUS_SEXT_iFifo_first__087_B_ETC___d4519 or
	  IF_IF_IF_IF_3074_MINUS_SEXT_iFifo_first__087_B_ETC___d4521 or
	  sfdin__h250423)
  begin
    case (iFifo$D_OUT[6:4])
      3'd0:
	  _theResult___fst_sfd__h251227 =
	      CASE_guard42201_0b0_sfdin50423_BITS_56_TO_5_0b_ETC__q77;
      3'd1:
	  _theResult___fst_sfd__h251227 =
	      CASE_guard42201_0b0_sfdin50423_BITS_56_TO_5_0b_ETC__q78;
      3'd2:
	  _theResult___fst_sfd__h251227 =
	      IF_IF_IF_IF_3074_MINUS_SEXT_iFifo_first__087_B_ETC___d4519;
      3'd3:
	  _theResult___fst_sfd__h251227 =
	      IF_IF_IF_IF_3074_MINUS_SEXT_iFifo_first__087_B_ETC___d4521;
      3'd4: _theResult___fst_sfd__h251227 = sfdin__h250423[56:5];
      default: _theResult___fst_sfd__h251227 = 52'd0;
    endcase
  end
  always@(guard__h251240 or
	  _theResult___snd__h259176 or
	  out_sfd__h259904 or _theResult___sfd__h259901)
  begin
    case (guard__h251240)
      2'b0, 2'b01:
	  CASE_guard51240_0b0_theResult___snd59176_BITS__ETC__q79 =
	      _theResult___snd__h259176[56:5];
      2'b10:
	  CASE_guard51240_0b0_theResult___snd59176_BITS__ETC__q79 =
	      out_sfd__h259904;
      2'b11:
	  CASE_guard51240_0b0_theResult___snd59176_BITS__ETC__q79 =
	      _theResult___sfd__h259901;
    endcase
  end
  always@(guard__h251240 or
	  _theResult___snd__h259176 or _theResult___sfd__h259901)
  begin
    case (guard__h251240)
      2'b0:
	  CASE_guard51240_0b0_theResult___snd59176_BITS__ETC__q80 =
	      _theResult___snd__h259176[56:5];
      2'b01, 2'b10, 2'b11:
	  CASE_guard51240_0b0_theResult___snd59176_BITS__ETC__q80 =
	      _theResult___sfd__h259901;
    endcase
  end
  always@(iFifo$D_OUT or
	  CASE_guard51240_0b0_theResult___snd59176_BITS__ETC__q79 or
	  CASE_guard51240_0b0_theResult___snd59176_BITS__ETC__q80 or
	  IF_IF_IF_iFifo_first__087_BITS_37_TO_30_850_EQ_ETC___d4538 or
	  IF_IF_IF_iFifo_first__087_BITS_37_TO_30_850_EQ_ETC___d4540 or
	  _theResult___snd__h259176)
  begin
    case (iFifo$D_OUT[6:4])
      3'd0:
	  _theResult___fst_sfd__h259979 =
	      CASE_guard51240_0b0_theResult___snd59176_BITS__ETC__q79;
      3'd1:
	  _theResult___fst_sfd__h259979 =
	      CASE_guard51240_0b0_theResult___snd59176_BITS__ETC__q80;
      3'd2:
	  _theResult___fst_sfd__h259979 =
	      IF_IF_IF_iFifo_first__087_BITS_37_TO_30_850_EQ_ETC___d4538;
      3'd3:
	  _theResult___fst_sfd__h259979 =
	      IF_IF_IF_iFifo_first__087_BITS_37_TO_30_850_EQ_ETC___d4540;
      3'd4: _theResult___fst_sfd__h259979 = _theResult___snd__h259176[56:5];
      default: _theResult___fst_sfd__h259979 = 52'd0;
    endcase
  end
  always@(guard__h232952 or iFifo$D_OUT)
  begin
    case (guard__h232952)
      2'b0, 2'b01, 2'b10:
	  CASE_guard32952_0b0_iFifoD_OUT_BIT_38_0b1_iFi_ETC__q81 =
	      iFifo$D_OUT[38];
      2'd3:
	  CASE_guard32952_0b0_iFifoD_OUT_BIT_38_0b1_iFi_ETC__q81 =
	      guard__h232952 == 2'b11 && iFifo$D_OUT[38];
    endcase
  end
  always@(iFifo$D_OUT or
	  CASE_guard32952_0b0_iFifoD_OUT_BIT_38_0b1_iFi_ETC__q81 or
	  guard__h232952)
  begin
    case (iFifo$D_OUT[6:4])
      3'd0:
	  CASE_iFifoD_OUT_BITS_6_TO_4_0_CASE_guard32952_ETC__q82 =
	      CASE_guard32952_0b0_iFifoD_OUT_BIT_38_0b1_iFi_ETC__q81;
      3'd1:
	  CASE_iFifoD_OUT_BITS_6_TO_4_0_CASE_guard32952_ETC__q82 =
	      (guard__h232952 == 2'b0) ?
		iFifo$D_OUT[38] :
		(guard__h232952 == 2'b01 || guard__h232952 == 2'b10 ||
		 guard__h232952 == 2'b11) &&
		iFifo$D_OUT[38];
      3'd2, 3'd3:
	  CASE_iFifoD_OUT_BITS_6_TO_4_0_CASE_guard32952_ETC__q82 =
	      iFifo$D_OUT[38];
      default: CASE_iFifoD_OUT_BITS_6_TO_4_0_CASE_guard32952_ETC__q82 =
		   iFifo$D_OUT[6:4] == 3'd4 && iFifo$D_OUT[38];
    endcase
  end
  always@(iFifo$D_OUT)
  begin
    case (iFifo$D_OUT[6:4])
      3'd0, 3'd1, 3'd2, 3'd3:
	  IF_iFifo_first__087_BITS_6_TO_4_118_EQ_0_191_O_ETC___d4028 =
	      iFifo$D_OUT[38];
      default: IF_iFifo_first__087_BITS_6_TO_4_118_EQ_0_191_O_ETC___d4028 =
		   iFifo$D_OUT[6:4] == 3'd4 && iFifo$D_OUT[38];
    endcase
  end
  always@(guard__h242201 or iFifo$D_OUT)
  begin
    case (guard__h242201)
      2'b0, 2'b01, 2'b10:
	  CASE_guard42201_0b0_iFifoD_OUT_BIT_38_0b1_iFi_ETC__q83 =
	      iFifo$D_OUT[38];
      2'd3:
	  CASE_guard42201_0b0_iFifoD_OUT_BIT_38_0b1_iFi_ETC__q83 =
	      guard__h242201 == 2'b11 && iFifo$D_OUT[38];
    endcase
  end
  always@(iFifo$D_OUT or
	  CASE_guard42201_0b0_iFifoD_OUT_BIT_38_0b1_iFi_ETC__q83 or
	  guard__h242201)
  begin
    case (iFifo$D_OUT[6:4])
      3'd0:
	  CASE_iFifoD_OUT_BITS_6_TO_4_0_CASE_guard42201_ETC__q84 =
	      CASE_guard42201_0b0_iFifoD_OUT_BIT_38_0b1_iFi_ETC__q83;
      3'd1:
	  CASE_iFifoD_OUT_BITS_6_TO_4_0_CASE_guard42201_ETC__q84 =
	      (guard__h242201 == 2'b0) ?
		iFifo$D_OUT[38] :
		(guard__h242201 == 2'b01 || guard__h242201 == 2'b10 ||
		 guard__h242201 == 2'b11) &&
		iFifo$D_OUT[38];
      3'd2, 3'd3:
	  CASE_iFifoD_OUT_BITS_6_TO_4_0_CASE_guard42201_ETC__q84 =
	      iFifo$D_OUT[38];
      default: CASE_iFifoD_OUT_BITS_6_TO_4_0_CASE_guard42201_ETC__q84 =
		   iFifo$D_OUT[6:4] == 3'd4 && iFifo$D_OUT[38];
    endcase
  end
  always@(guard__h251240 or iFifo$D_OUT)
  begin
    case (guard__h251240)
      2'b0, 2'b01, 2'b10:
	  CASE_guard51240_0b0_iFifoD_OUT_BIT_38_0b1_iFi_ETC__q85 =
	      iFifo$D_OUT[38];
      2'd3:
	  CASE_guard51240_0b0_iFifoD_OUT_BIT_38_0b1_iFi_ETC__q85 =
	      guard__h251240 == 2'b11 && iFifo$D_OUT[38];
    endcase
  end
  always@(iFifo$D_OUT or
	  CASE_guard51240_0b0_iFifoD_OUT_BIT_38_0b1_iFi_ETC__q85 or
	  guard__h251240)
  begin
    case (iFifo$D_OUT[6:4])
      3'd0:
	  CASE_iFifoD_OUT_BITS_6_TO_4_0_CASE_guard51240_ETC__q86 =
	      CASE_guard51240_0b0_iFifoD_OUT_BIT_38_0b1_iFi_ETC__q85;
      3'd1:
	  CASE_iFifoD_OUT_BITS_6_TO_4_0_CASE_guard51240_ETC__q86 =
	      (guard__h251240 == 2'b0) ?
		iFifo$D_OUT[38] :
		(guard__h251240 == 2'b01 || guard__h251240 == 2'b10 ||
		 guard__h251240 == 2'b11) &&
		iFifo$D_OUT[38];
      3'd2, 3'd3:
	  CASE_iFifoD_OUT_BITS_6_TO_4_0_CASE_guard51240_ETC__q86 =
	      iFifo$D_OUT[38];
      default: CASE_iFifoD_OUT_BITS_6_TO_4_0_CASE_guard51240_ETC__q86 =
		   iFifo$D_OUT[6:4] == 3'd4 && iFifo$D_OUT[38];
    endcase
  end
  always@(guard__h232952 or iFifo$D_OUT)
  begin
    case (guard__h232952)
      2'b0, 2'b01, 2'b10:
	  CASE_guard32952_0b0_NOT_iFifoD_OUT_BIT_38_0b1_ETC__q87 =
	      !iFifo$D_OUT[38];
      2'd3:
	  CASE_guard32952_0b0_NOT_iFifoD_OUT_BIT_38_0b1_ETC__q87 =
	      guard__h232952 != 2'b11 || !iFifo$D_OUT[38];
    endcase
  end
  always@(iFifo$D_OUT or
	  CASE_guard32952_0b0_NOT_iFifoD_OUT_BIT_38_0b1_ETC__q87 or
	  guard__h232952)
  begin
    case (iFifo$D_OUT[6:4])
      3'd0:
	  CASE_iFifoD_OUT_BITS_6_TO_4_0_CASE_guard32952_ETC__q88 =
	      CASE_guard32952_0b0_NOT_iFifoD_OUT_BIT_38_0b1_ETC__q87;
      3'd1:
	  CASE_iFifoD_OUT_BITS_6_TO_4_0_CASE_guard32952_ETC__q88 =
	      (guard__h232952 == 2'b0) ?
		!iFifo$D_OUT[38] :
		guard__h232952 != 2'b01 && guard__h232952 != 2'b10 &&
		guard__h232952 != 2'b11 ||
		!iFifo$D_OUT[38];
      3'd2, 3'd3:
	  CASE_iFifoD_OUT_BITS_6_TO_4_0_CASE_guard32952_ETC__q88 =
	      !iFifo$D_OUT[38];
      default: CASE_iFifoD_OUT_BITS_6_TO_4_0_CASE_guard32952_ETC__q88 =
		   iFifo$D_OUT[6:4] != 3'd4 || !iFifo$D_OUT[38];
    endcase
  end
  always@(guard__h242201 or iFifo$D_OUT)
  begin
    case (guard__h242201)
      2'b0, 2'b01, 2'b10:
	  CASE_guard42201_0b0_NOT_iFifoD_OUT_BIT_38_0b1_ETC__q89 =
	      !iFifo$D_OUT[38];
      2'd3:
	  CASE_guard42201_0b0_NOT_iFifoD_OUT_BIT_38_0b1_ETC__q89 =
	      guard__h242201 != 2'b11 || !iFifo$D_OUT[38];
    endcase
  end
  always@(iFifo$D_OUT or
	  CASE_guard42201_0b0_NOT_iFifoD_OUT_BIT_38_0b1_ETC__q89 or
	  guard__h242201)
  begin
    case (iFifo$D_OUT[6:4])
      3'd0:
	  CASE_iFifoD_OUT_BITS_6_TO_4_0_CASE_guard42201_ETC__q90 =
	      CASE_guard42201_0b0_NOT_iFifoD_OUT_BIT_38_0b1_ETC__q89;
      3'd1:
	  CASE_iFifoD_OUT_BITS_6_TO_4_0_CASE_guard42201_ETC__q90 =
	      (guard__h242201 == 2'b0) ?
		!iFifo$D_OUT[38] :
		guard__h242201 != 2'b01 && guard__h242201 != 2'b10 &&
		guard__h242201 != 2'b11 ||
		!iFifo$D_OUT[38];
      3'd2, 3'd3:
	  CASE_iFifoD_OUT_BITS_6_TO_4_0_CASE_guard42201_ETC__q90 =
	      !iFifo$D_OUT[38];
      default: CASE_iFifoD_OUT_BITS_6_TO_4_0_CASE_guard42201_ETC__q90 =
		   iFifo$D_OUT[6:4] != 3'd4 || !iFifo$D_OUT[38];
    endcase
  end
  always@(guard__h251240 or iFifo$D_OUT)
  begin
    case (guard__h251240)
      2'b0, 2'b01, 2'b10:
	  CASE_guard51240_0b0_NOT_iFifoD_OUT_BIT_38_0b1_ETC__q91 =
	      !iFifo$D_OUT[38];
      2'd3:
	  CASE_guard51240_0b0_NOT_iFifoD_OUT_BIT_38_0b1_ETC__q91 =
	      guard__h251240 != 2'b11 || !iFifo$D_OUT[38];
    endcase
  end
  always@(iFifo$D_OUT or
	  CASE_guard51240_0b0_NOT_iFifoD_OUT_BIT_38_0b1_ETC__q91 or
	  guard__h251240)
  begin
    case (iFifo$D_OUT[6:4])
      3'd0:
	  CASE_iFifoD_OUT_BITS_6_TO_4_0_CASE_guard51240_ETC__q92 =
	      CASE_guard51240_0b0_NOT_iFifoD_OUT_BIT_38_0b1_ETC__q91;
      3'd1:
	  CASE_iFifoD_OUT_BITS_6_TO_4_0_CASE_guard51240_ETC__q92 =
	      (guard__h251240 == 2'b0) ?
		!iFifo$D_OUT[38] :
		guard__h251240 != 2'b01 && guard__h251240 != 2'b10 &&
		guard__h251240 != 2'b11 ||
		!iFifo$D_OUT[38];
      3'd2, 3'd3:
	  CASE_iFifoD_OUT_BITS_6_TO_4_0_CASE_guard51240_ETC__q92 =
	      !iFifo$D_OUT[38];
      default: CASE_iFifoD_OUT_BITS_6_TO_4_0_CASE_guard51240_ETC__q92 =
		   iFifo$D_OUT[6:4] != 3'd4 || !iFifo$D_OUT[38];
    endcase
  end
  always@(iFifo$D_OUT)
  begin
    case (iFifo$D_OUT[6:4])
      3'd0, 3'd1, 3'd2, 3'd3:
	  IF_iFifo_first__087_BITS_6_TO_4_118_EQ_0_191_O_ETC___d4582 =
	      !iFifo$D_OUT[38];
      default: IF_iFifo_first__087_BITS_6_TO_4_118_EQ_0_191_O_ETC___d4582 =
		   iFifo$D_OUT[6:4] != 3'd4 || !iFifo$D_OUT[38];
    endcase
  end
  always@(guard__h194013 or
	  _theResult___fst_exp__h201974 or
	  out_exp__h202622 or _theResult___exp__h202619)
  begin
    case (guard__h194013)
      2'b0, 2'b01:
	  CASE_guard94013_0b0_theResult___fst_exp01974_0_ETC__q102 =
	      _theResult___fst_exp__h201974;
      2'b10:
	  CASE_guard94013_0b0_theResult___fst_exp01974_0_ETC__q102 =
	      out_exp__h202622;
      2'b11:
	  CASE_guard94013_0b0_theResult___fst_exp01974_0_ETC__q102 =
	      _theResult___exp__h202619;
    endcase
  end
  always@(guard__h194013 or
	  _theResult___fst_exp__h201974 or _theResult___exp__h202619)
  begin
    case (guard__h194013)
      2'b0:
	  CASE_guard94013_0b0_theResult___fst_exp01974_0_ETC__q103 =
	      _theResult___fst_exp__h201974;
      2'b01, 2'b10, 2'b11:
	  CASE_guard94013_0b0_theResult___fst_exp01974_0_ETC__q103 =
	      _theResult___exp__h202619;
    endcase
  end
  always@(iFifo$D_OUT or
	  CASE_guard94013_0b0_theResult___fst_exp01974_0_ETC__q102 or
	  CASE_guard94013_0b0_theResult___fst_exp01974_0_ETC__q103 or
	  IF_IF_IF_iFifo_first__087_BITS_102_TO_95_625_E_ETC___d5173 or
	  IF_IF_IF_iFifo_first__087_BITS_102_TO_95_625_E_ETC___d5175 or
	  _theResult___fst_exp__h201974)
  begin
    case (iFifo$D_OUT[6:4])
      3'd0:
	  _theResult___fst_exp__h202697 =
	      CASE_guard94013_0b0_theResult___fst_exp01974_0_ETC__q102;
      3'd1:
	  _theResult___fst_exp__h202697 =
	      CASE_guard94013_0b0_theResult___fst_exp01974_0_ETC__q103;
      3'd2:
	  _theResult___fst_exp__h202697 =
	      IF_IF_IF_iFifo_first__087_BITS_102_TO_95_625_E_ETC___d5173;
      3'd3:
	  _theResult___fst_exp__h202697 =
	      IF_IF_IF_iFifo_first__087_BITS_102_TO_95_625_E_ETC___d5175;
      3'd4: _theResult___fst_exp__h202697 = _theResult___fst_exp__h201974;
      default: _theResult___fst_exp__h202697 = 11'd0;
    endcase
  end
  always@(guard__h203262 or
	  _theResult___fst_exp__h211490 or
	  out_exp__h212212 or _theResult___exp__h212209)
  begin
    case (guard__h203262)
      2'b0, 2'b01:
	  CASE_guard03262_0b0_theResult___fst_exp11490_0_ETC__q104 =
	      _theResult___fst_exp__h211490;
      2'b10:
	  CASE_guard03262_0b0_theResult___fst_exp11490_0_ETC__q104 =
	      out_exp__h212212;
      2'b11:
	  CASE_guard03262_0b0_theResult___fst_exp11490_0_ETC__q104 =
	      _theResult___exp__h212209;
    endcase
  end
  always@(guard__h203262 or
	  _theResult___fst_exp__h211490 or _theResult___exp__h212209)
  begin
    case (guard__h203262)
      2'b0:
	  CASE_guard03262_0b0_theResult___fst_exp11490_0_ETC__q105 =
	      _theResult___fst_exp__h211490;
      2'b01, 2'b10, 2'b11:
	  CASE_guard03262_0b0_theResult___fst_exp11490_0_ETC__q105 =
	      _theResult___exp__h212209;
    endcase
  end
  always@(iFifo$D_OUT or
	  CASE_guard03262_0b0_theResult___fst_exp11490_0_ETC__q104 or
	  CASE_guard03262_0b0_theResult___fst_exp11490_0_ETC__q105 or
	  IF_IF_IF_IF_3074_MINUS_SEXT_iFifo_first__087_B_ETC___d5211 or
	  IF_IF_IF_IF_3074_MINUS_SEXT_iFifo_first__087_B_ETC___d5213 or
	  _theResult___fst_exp__h211490)
  begin
    case (iFifo$D_OUT[6:4])
      3'd0:
	  _theResult___fst_exp__h212287 =
	      CASE_guard03262_0b0_theResult___fst_exp11490_0_ETC__q104;
      3'd1:
	  _theResult___fst_exp__h212287 =
	      CASE_guard03262_0b0_theResult___fst_exp11490_0_ETC__q105;
      3'd2:
	  _theResult___fst_exp__h212287 =
	      IF_IF_IF_IF_3074_MINUS_SEXT_iFifo_first__087_B_ETC___d5211;
      3'd3:
	  _theResult___fst_exp__h212287 =
	      IF_IF_IF_IF_3074_MINUS_SEXT_iFifo_first__087_B_ETC___d5213;
      3'd4: _theResult___fst_exp__h212287 = _theResult___fst_exp__h211490;
      default: _theResult___fst_exp__h212287 = 11'd0;
    endcase
  end
  always@(guard__h212301 or
	  _theResult___fst_exp__h220291 or
	  out_exp__h220964 or _theResult___exp__h220961)
  begin
    case (guard__h212301)
      2'b0, 2'b01:
	  CASE_guard12301_0b0_theResult___fst_exp20291_0_ETC__q106 =
	      _theResult___fst_exp__h220291;
      2'b10:
	  CASE_guard12301_0b0_theResult___fst_exp20291_0_ETC__q106 =
	      out_exp__h220964;
      2'b11:
	  CASE_guard12301_0b0_theResult___fst_exp20291_0_ETC__q106 =
	      _theResult___exp__h220961;
    endcase
  end
  always@(guard__h212301 or
	  _theResult___fst_exp__h220291 or _theResult___exp__h220961)
  begin
    case (guard__h212301)
      2'b0:
	  CASE_guard12301_0b0_theResult___fst_exp20291_0_ETC__q107 =
	      _theResult___fst_exp__h220291;
      2'b01, 2'b10, 2'b11:
	  CASE_guard12301_0b0_theResult___fst_exp20291_0_ETC__q107 =
	      _theResult___exp__h220961;
    endcase
  end
  always@(iFifo$D_OUT or
	  CASE_guard12301_0b0_theResult___fst_exp20291_0_ETC__q106 or
	  CASE_guard12301_0b0_theResult___fst_exp20291_0_ETC__q107 or
	  IF_IF_IF_iFifo_first__087_BITS_102_TO_95_625_E_ETC___d5242 or
	  IF_IF_IF_iFifo_first__087_BITS_102_TO_95_625_E_ETC___d5244 or
	  _theResult___fst_exp__h220291)
  begin
    case (iFifo$D_OUT[6:4])
      3'd0:
	  _theResult___fst_exp__h221039 =
	      CASE_guard12301_0b0_theResult___fst_exp20291_0_ETC__q106;
      3'd1:
	  _theResult___fst_exp__h221039 =
	      CASE_guard12301_0b0_theResult___fst_exp20291_0_ETC__q107;
      3'd2:
	  _theResult___fst_exp__h221039 =
	      IF_IF_IF_iFifo_first__087_BITS_102_TO_95_625_E_ETC___d5242;
      3'd3:
	  _theResult___fst_exp__h221039 =
	      IF_IF_IF_iFifo_first__087_BITS_102_TO_95_625_E_ETC___d5244;
      3'd4: _theResult___fst_exp__h221039 = _theResult___fst_exp__h220291;
      default: _theResult___fst_exp__h221039 = 11'd0;
    endcase
  end
  always@(guard__h194013 or
	  _theResult___snd__h201925 or
	  out_sfd__h202623 or _theResult___sfd__h202620)
  begin
    case (guard__h194013)
      2'b0, 2'b01:
	  CASE_guard94013_0b0_theResult___snd01925_BITS__ETC__q108 =
	      _theResult___snd__h201925[56:5];
      2'b10:
	  CASE_guard94013_0b0_theResult___snd01925_BITS__ETC__q108 =
	      out_sfd__h202623;
      2'b11:
	  CASE_guard94013_0b0_theResult___snd01925_BITS__ETC__q108 =
	      _theResult___sfd__h202620;
    endcase
  end
  always@(guard__h194013 or
	  _theResult___snd__h201925 or _theResult___sfd__h202620)
  begin
    case (guard__h194013)
      2'b0:
	  CASE_guard94013_0b0_theResult___snd01925_BITS__ETC__q109 =
	      _theResult___snd__h201925[56:5];
      2'b01, 2'b10, 2'b11:
	  CASE_guard94013_0b0_theResult___snd01925_BITS__ETC__q109 =
	      _theResult___sfd__h202620;
    endcase
  end
  always@(iFifo$D_OUT or
	  CASE_guard94013_0b0_theResult___snd01925_BITS__ETC__q108 or
	  CASE_guard94013_0b0_theResult___snd01925_BITS__ETC__q109 or
	  IF_IF_IF_iFifo_first__087_BITS_102_TO_95_625_E_ETC___d5268 or
	  IF_IF_IF_iFifo_first__087_BITS_102_TO_95_625_E_ETC___d5270 or
	  _theResult___snd__h201925)
  begin
    case (iFifo$D_OUT[6:4])
      3'd0:
	  _theResult___fst_sfd__h202698 =
	      CASE_guard94013_0b0_theResult___snd01925_BITS__ETC__q108;
      3'd1:
	  _theResult___fst_sfd__h202698 =
	      CASE_guard94013_0b0_theResult___snd01925_BITS__ETC__q109;
      3'd2:
	  _theResult___fst_sfd__h202698 =
	      IF_IF_IF_iFifo_first__087_BITS_102_TO_95_625_E_ETC___d5268;
      3'd3:
	  _theResult___fst_sfd__h202698 =
	      IF_IF_IF_iFifo_first__087_BITS_102_TO_95_625_E_ETC___d5270;
      3'd4: _theResult___fst_sfd__h202698 = _theResult___snd__h201925[56:5];
      default: _theResult___fst_sfd__h202698 = 52'd0;
    endcase
  end
  always@(guard__h203262 or
	  sfdin__h211484 or out_sfd__h212213 or _theResult___sfd__h212210)
  begin
    case (guard__h203262)
      2'b0, 2'b01:
	  CASE_guard03262_0b0_sfdin11484_BITS_56_TO_5_0b_ETC__q110 =
	      sfdin__h211484[56:5];
      2'b10:
	  CASE_guard03262_0b0_sfdin11484_BITS_56_TO_5_0b_ETC__q110 =
	      out_sfd__h212213;
      2'b11:
	  CASE_guard03262_0b0_sfdin11484_BITS_56_TO_5_0b_ETC__q110 =
	      _theResult___sfd__h212210;
    endcase
  end
  always@(guard__h203262 or sfdin__h211484 or _theResult___sfd__h212210)
  begin
    case (guard__h203262)
      2'b0:
	  CASE_guard03262_0b0_sfdin11484_BITS_56_TO_5_0b_ETC__q111 =
	      sfdin__h211484[56:5];
      2'b01, 2'b10, 2'b11:
	  CASE_guard03262_0b0_sfdin11484_BITS_56_TO_5_0b_ETC__q111 =
	      _theResult___sfd__h212210;
    endcase
  end
  always@(iFifo$D_OUT or
	  CASE_guard03262_0b0_sfdin11484_BITS_56_TO_5_0b_ETC__q110 or
	  CASE_guard03262_0b0_sfdin11484_BITS_56_TO_5_0b_ETC__q111 or
	  IF_IF_IF_IF_3074_MINUS_SEXT_iFifo_first__087_B_ETC___d5294 or
	  IF_IF_IF_IF_3074_MINUS_SEXT_iFifo_first__087_B_ETC___d5296 or
	  sfdin__h211484)
  begin
    case (iFifo$D_OUT[6:4])
      3'd0:
	  _theResult___fst_sfd__h212288 =
	      CASE_guard03262_0b0_sfdin11484_BITS_56_TO_5_0b_ETC__q110;
      3'd1:
	  _theResult___fst_sfd__h212288 =
	      CASE_guard03262_0b0_sfdin11484_BITS_56_TO_5_0b_ETC__q111;
      3'd2:
	  _theResult___fst_sfd__h212288 =
	      IF_IF_IF_IF_3074_MINUS_SEXT_iFifo_first__087_B_ETC___d5294;
      3'd3:
	  _theResult___fst_sfd__h212288 =
	      IF_IF_IF_IF_3074_MINUS_SEXT_iFifo_first__087_B_ETC___d5296;
      3'd4: _theResult___fst_sfd__h212288 = sfdin__h211484[56:5];
      default: _theResult___fst_sfd__h212288 = 52'd0;
    endcase
  end
  always@(guard__h212301 or
	  _theResult___snd__h220237 or
	  out_sfd__h220965 or _theResult___sfd__h220962)
  begin
    case (guard__h212301)
      2'b0, 2'b01:
	  CASE_guard12301_0b0_theResult___snd20237_BITS__ETC__q112 =
	      _theResult___snd__h220237[56:5];
      2'b10:
	  CASE_guard12301_0b0_theResult___snd20237_BITS__ETC__q112 =
	      out_sfd__h220965;
      2'b11:
	  CASE_guard12301_0b0_theResult___snd20237_BITS__ETC__q112 =
	      _theResult___sfd__h220962;
    endcase
  end
  always@(guard__h212301 or
	  _theResult___snd__h220237 or _theResult___sfd__h220962)
  begin
    case (guard__h212301)
      2'b0:
	  CASE_guard12301_0b0_theResult___snd20237_BITS__ETC__q113 =
	      _theResult___snd__h220237[56:5];
      2'b01, 2'b10, 2'b11:
	  CASE_guard12301_0b0_theResult___snd20237_BITS__ETC__q113 =
	      _theResult___sfd__h220962;
    endcase
  end
  always@(iFifo$D_OUT or
	  CASE_guard12301_0b0_theResult___snd20237_BITS__ETC__q112 or
	  CASE_guard12301_0b0_theResult___snd20237_BITS__ETC__q113 or
	  IF_IF_IF_iFifo_first__087_BITS_102_TO_95_625_E_ETC___d5313 or
	  IF_IF_IF_iFifo_first__087_BITS_102_TO_95_625_E_ETC___d5315 or
	  _theResult___snd__h220237)
  begin
    case (iFifo$D_OUT[6:4])
      3'd0:
	  _theResult___fst_sfd__h221040 =
	      CASE_guard12301_0b0_theResult___snd20237_BITS__ETC__q112;
      3'd1:
	  _theResult___fst_sfd__h221040 =
	      CASE_guard12301_0b0_theResult___snd20237_BITS__ETC__q113;
      3'd2:
	  _theResult___fst_sfd__h221040 =
	      IF_IF_IF_iFifo_first__087_BITS_102_TO_95_625_E_ETC___d5313;
      3'd3:
	  _theResult___fst_sfd__h221040 =
	      IF_IF_IF_iFifo_first__087_BITS_102_TO_95_625_E_ETC___d5315;
      3'd4: _theResult___fst_sfd__h221040 = _theResult___snd__h220237[56:5];
      default: _theResult___fst_sfd__h221040 = 52'd0;
    endcase
  end
  always@(guard__h194013 or iFifo$D_OUT)
  begin
    case (guard__h194013)
      2'b0, 2'b01, 2'b10:
	  CASE_guard94013_0b0_iFifoD_OUT_BIT_103_0b1_iF_ETC__q114 =
	      iFifo$D_OUT[103];
      2'd3:
	  CASE_guard94013_0b0_iFifoD_OUT_BIT_103_0b1_iF_ETC__q114 =
	      guard__h194013 == 2'b11 && iFifo$D_OUT[103];
    endcase
  end
  always@(iFifo$D_OUT or
	  CASE_guard94013_0b0_iFifoD_OUT_BIT_103_0b1_iF_ETC__q114 or
	  guard__h194013)
  begin
    case (iFifo$D_OUT[6:4])
      3'd0:
	  CASE_iFifoD_OUT_BITS_6_TO_4_0_CASE_guard94013_ETC__q115 =
	      CASE_guard94013_0b0_iFifoD_OUT_BIT_103_0b1_iF_ETC__q114;
      3'd1:
	  CASE_iFifoD_OUT_BITS_6_TO_4_0_CASE_guard94013_ETC__q115 =
	      (guard__h194013 == 2'b0) ?
		iFifo$D_OUT[103] :
		(guard__h194013 == 2'b01 || guard__h194013 == 2'b10 ||
		 guard__h194013 == 2'b11) &&
		iFifo$D_OUT[103];
      3'd2, 3'd3:
	  CASE_iFifoD_OUT_BITS_6_TO_4_0_CASE_guard94013_ETC__q115 =
	      iFifo$D_OUT[103];
      default: CASE_iFifoD_OUT_BITS_6_TO_4_0_CASE_guard94013_ETC__q115 =
		   iFifo$D_OUT[6:4] == 3'd4 && iFifo$D_OUT[103];
    endcase
  end
  always@(iFifo$D_OUT)
  begin
    case (iFifo$D_OUT[6:4])
      3'd0, 3'd1, 3'd2, 3'd3:
	  IF_iFifo_first__087_BITS_6_TO_4_118_EQ_0_191_O_ETC___d4803 =
	      iFifo$D_OUT[103];
      default: IF_iFifo_first__087_BITS_6_TO_4_118_EQ_0_191_O_ETC___d4803 =
		   iFifo$D_OUT[6:4] == 3'd4 && iFifo$D_OUT[103];
    endcase
  end
  always@(guard__h203262 or iFifo$D_OUT)
  begin
    case (guard__h203262)
      2'b0, 2'b01, 2'b10:
	  CASE_guard03262_0b0_iFifoD_OUT_BIT_103_0b1_iF_ETC__q116 =
	      iFifo$D_OUT[103];
      2'd3:
	  CASE_guard03262_0b0_iFifoD_OUT_BIT_103_0b1_iF_ETC__q116 =
	      guard__h203262 == 2'b11 && iFifo$D_OUT[103];
    endcase
  end
  always@(iFifo$D_OUT or
	  CASE_guard03262_0b0_iFifoD_OUT_BIT_103_0b1_iF_ETC__q116 or
	  guard__h203262)
  begin
    case (iFifo$D_OUT[6:4])
      3'd0:
	  CASE_iFifoD_OUT_BITS_6_TO_4_0_CASE_guard03262_ETC__q117 =
	      CASE_guard03262_0b0_iFifoD_OUT_BIT_103_0b1_iF_ETC__q116;
      3'd1:
	  CASE_iFifoD_OUT_BITS_6_TO_4_0_CASE_guard03262_ETC__q117 =
	      (guard__h203262 == 2'b0) ?
		iFifo$D_OUT[103] :
		(guard__h203262 == 2'b01 || guard__h203262 == 2'b10 ||
		 guard__h203262 == 2'b11) &&
		iFifo$D_OUT[103];
      3'd2, 3'd3:
	  CASE_iFifoD_OUT_BITS_6_TO_4_0_CASE_guard03262_ETC__q117 =
	      iFifo$D_OUT[103];
      default: CASE_iFifoD_OUT_BITS_6_TO_4_0_CASE_guard03262_ETC__q117 =
		   iFifo$D_OUT[6:4] == 3'd4 && iFifo$D_OUT[103];
    endcase
  end
  always@(guard__h212301 or iFifo$D_OUT)
  begin
    case (guard__h212301)
      2'b0, 2'b01, 2'b10:
	  CASE_guard12301_0b0_iFifoD_OUT_BIT_103_0b1_iF_ETC__q118 =
	      iFifo$D_OUT[103];
      2'd3:
	  CASE_guard12301_0b0_iFifoD_OUT_BIT_103_0b1_iF_ETC__q118 =
	      guard__h212301 == 2'b11 && iFifo$D_OUT[103];
    endcase
  end
  always@(iFifo$D_OUT or
	  CASE_guard12301_0b0_iFifoD_OUT_BIT_103_0b1_iF_ETC__q118 or
	  guard__h212301)
  begin
    case (iFifo$D_OUT[6:4])
      3'd0:
	  CASE_iFifoD_OUT_BITS_6_TO_4_0_CASE_guard12301_ETC__q119 =
	      CASE_guard12301_0b0_iFifoD_OUT_BIT_103_0b1_iF_ETC__q118;
      3'd1:
	  CASE_iFifoD_OUT_BITS_6_TO_4_0_CASE_guard12301_ETC__q119 =
	      (guard__h212301 == 2'b0) ?
		iFifo$D_OUT[103] :
		(guard__h212301 == 2'b01 || guard__h212301 == 2'b10 ||
		 guard__h212301 == 2'b11) &&
		iFifo$D_OUT[103];
      3'd2, 3'd3:
	  CASE_iFifoD_OUT_BITS_6_TO_4_0_CASE_guard12301_ETC__q119 =
	      iFifo$D_OUT[103];
      default: CASE_iFifoD_OUT_BITS_6_TO_4_0_CASE_guard12301_ETC__q119 =
		   iFifo$D_OUT[6:4] == 3'd4 && iFifo$D_OUT[103];
    endcase
  end
  always@(guard__h194013 or iFifo$D_OUT)
  begin
    case (guard__h194013)
      2'b0, 2'b01, 2'b10:
	  CASE_guard94013_0b0_NOT_iFifoD_OUT_BIT_103_0b_ETC__q120 =
	      !iFifo$D_OUT[103];
      2'd3:
	  CASE_guard94013_0b0_NOT_iFifoD_OUT_BIT_103_0b_ETC__q120 =
	      guard__h194013 != 2'b11 || !iFifo$D_OUT[103];
    endcase
  end
  always@(iFifo$D_OUT or
	  CASE_guard94013_0b0_NOT_iFifoD_OUT_BIT_103_0b_ETC__q120 or
	  guard__h194013)
  begin
    case (iFifo$D_OUT[6:4])
      3'd0:
	  CASE_iFifoD_OUT_BITS_6_TO_4_0_CASE_guard94013_ETC__q121 =
	      CASE_guard94013_0b0_NOT_iFifoD_OUT_BIT_103_0b_ETC__q120;
      3'd1:
	  CASE_iFifoD_OUT_BITS_6_TO_4_0_CASE_guard94013_ETC__q121 =
	      (guard__h194013 == 2'b0) ?
		!iFifo$D_OUT[103] :
		guard__h194013 != 2'b01 && guard__h194013 != 2'b10 &&
		guard__h194013 != 2'b11 ||
		!iFifo$D_OUT[103];
      3'd2, 3'd3:
	  CASE_iFifoD_OUT_BITS_6_TO_4_0_CASE_guard94013_ETC__q121 =
	      !iFifo$D_OUT[103];
      default: CASE_iFifoD_OUT_BITS_6_TO_4_0_CASE_guard94013_ETC__q121 =
		   iFifo$D_OUT[6:4] != 3'd4 || !iFifo$D_OUT[103];
    endcase
  end
  always@(iFifo$D_OUT)
  begin
    case (iFifo$D_OUT[6:4])
      3'd0, 3'd1, 3'd2, 3'd3:
	  IF_iFifo_first__087_BITS_6_TO_4_118_EQ_0_191_O_ETC___d5348 =
	      !iFifo$D_OUT[103];
      default: IF_iFifo_first__087_BITS_6_TO_4_118_EQ_0_191_O_ETC___d5348 =
		   iFifo$D_OUT[6:4] != 3'd4 || !iFifo$D_OUT[103];
    endcase
  end
  always@(guard__h203262 or iFifo$D_OUT)
  begin
    case (guard__h203262)
      2'b0, 2'b01, 2'b10:
	  CASE_guard03262_0b0_NOT_iFifoD_OUT_BIT_103_0b_ETC__q122 =
	      !iFifo$D_OUT[103];
      2'd3:
	  CASE_guard03262_0b0_NOT_iFifoD_OUT_BIT_103_0b_ETC__q122 =
	      guard__h203262 != 2'b11 || !iFifo$D_OUT[103];
    endcase
  end
  always@(iFifo$D_OUT or
	  CASE_guard03262_0b0_NOT_iFifoD_OUT_BIT_103_0b_ETC__q122 or
	  guard__h203262)
  begin
    case (iFifo$D_OUT[6:4])
      3'd0:
	  CASE_iFifoD_OUT_BITS_6_TO_4_0_CASE_guard03262_ETC__q123 =
	      CASE_guard03262_0b0_NOT_iFifoD_OUT_BIT_103_0b_ETC__q122;
      3'd1:
	  CASE_iFifoD_OUT_BITS_6_TO_4_0_CASE_guard03262_ETC__q123 =
	      (guard__h203262 == 2'b0) ?
		!iFifo$D_OUT[103] :
		guard__h203262 != 2'b01 && guard__h203262 != 2'b10 &&
		guard__h203262 != 2'b11 ||
		!iFifo$D_OUT[103];
      3'd2, 3'd3:
	  CASE_iFifoD_OUT_BITS_6_TO_4_0_CASE_guard03262_ETC__q123 =
	      !iFifo$D_OUT[103];
      default: CASE_iFifoD_OUT_BITS_6_TO_4_0_CASE_guard03262_ETC__q123 =
		   iFifo$D_OUT[6:4] != 3'd4 || !iFifo$D_OUT[103];
    endcase
  end
  always@(guard__h212301 or iFifo$D_OUT)
  begin
    case (guard__h212301)
      2'b0, 2'b01, 2'b10:
	  CASE_guard12301_0b0_NOT_iFifoD_OUT_BIT_103_0b_ETC__q124 =
	      !iFifo$D_OUT[103];
      2'd3:
	  CASE_guard12301_0b0_NOT_iFifoD_OUT_BIT_103_0b_ETC__q124 =
	      guard__h212301 != 2'b11 || !iFifo$D_OUT[103];
    endcase
  end
  always@(iFifo$D_OUT or
	  CASE_guard12301_0b0_NOT_iFifoD_OUT_BIT_103_0b_ETC__q124 or
	  guard__h212301)
  begin
    case (iFifo$D_OUT[6:4])
      3'd0:
	  CASE_iFifoD_OUT_BITS_6_TO_4_0_CASE_guard12301_ETC__q125 =
	      CASE_guard12301_0b0_NOT_iFifoD_OUT_BIT_103_0b_ETC__q124;
      3'd1:
	  CASE_iFifoD_OUT_BITS_6_TO_4_0_CASE_guard12301_ETC__q125 =
	      (guard__h212301 == 2'b0) ?
		!iFifo$D_OUT[103] :
		guard__h212301 != 2'b01 && guard__h212301 != 2'b10 &&
		guard__h212301 != 2'b11 ||
		!iFifo$D_OUT[103];
      3'd2, 3'd3:
	  CASE_iFifoD_OUT_BITS_6_TO_4_0_CASE_guard12301_ETC__q125 =
	      !iFifo$D_OUT[103];
      default: CASE_iFifoD_OUT_BITS_6_TO_4_0_CASE_guard12301_ETC__q125 =
		   iFifo$D_OUT[6:4] != 3'd4 || !iFifo$D_OUT[103];
    endcase
  end
  always@(fpu_madd_fState_S8$D_OUT)
  begin
    case (fpu_madd_fState_S8$D_OUT[2:1])
      2'b0, 2'b01, 2'b10:
	  CASE_fpu_madd_fState_S8D_OUT_BITS_2_TO_1_0b0__ETC__q126 =
	      fpu_madd_fState_S8$D_OUT[66];
      2'd3:
	  CASE_fpu_madd_fState_S8D_OUT_BITS_2_TO_1_0b0__ETC__q126 =
	      fpu_madd_fState_S8$D_OUT[2:1] == 2'b11 &&
	      fpu_madd_fState_S8$D_OUT[66];
    endcase
  end
  always@(fpu_madd_fState_S8$D_OUT or
	  CASE_fpu_madd_fState_S8D_OUT_BITS_2_TO_1_0b0__ETC__q126)
  begin
    case (fpu_madd_fState_S8$D_OUT[70:68])
      3'd0:
	  CASE_fpu_madd_fState_S8D_OUT_BITS_70_TO_68_0__ETC__q127 =
	      CASE_fpu_madd_fState_S8D_OUT_BITS_2_TO_1_0b0__ETC__q126;
      3'd1:
	  CASE_fpu_madd_fState_S8D_OUT_BITS_70_TO_68_0__ETC__q127 =
	      (fpu_madd_fState_S8$D_OUT[2:1] == 2'b0) ?
		fpu_madd_fState_S8$D_OUT[66] :
		(fpu_madd_fState_S8$D_OUT[2:1] == 2'b01 ||
		 fpu_madd_fState_S8$D_OUT[2:1] == 2'b10 ||
		 fpu_madd_fState_S8$D_OUT[2:1] == 2'b11) &&
		fpu_madd_fState_S8$D_OUT[66];
      3'd2, 3'd3:
	  CASE_fpu_madd_fState_S8D_OUT_BITS_70_TO_68_0__ETC__q127 =
	      fpu_madd_fState_S8$D_OUT[66];
      default: CASE_fpu_madd_fState_S8D_OUT_BITS_70_TO_68_0__ETC__q127 =
		   fpu_madd_fState_S8$D_OUT[70:68] == 3'd4 &&
		   fpu_madd_fState_S8$D_OUT[66];
    endcase
  end
  always@(iFifo$D_OUT or
	  IF_iFifo_first__087_BIT_71_849_THEN_IF_iFifo_f_ETC___d4618 or
	  IF_iFifo_first__087_BIT_201_115_THEN_IF_iFifo__ETC___d3848 or
	  IF_iFifo_first__087_BIT_71_849_THEN_IF_iFifo_f_ETC___d4555)
  begin
    case (iFifo$D_OUT[3:0])
      4'd0, 4'd1:
	  IF_iFifo_first__087_BITS_3_TO_0_088_EQ_0_089_O_ETC___d4623 =
	      IF_iFifo_first__087_BIT_201_115_THEN_IF_iFifo__ETC___d3848;
      4'd5, 4'd7:
	  IF_iFifo_first__087_BITS_3_TO_0_088_EQ_0_089_O_ETC___d4623 =
	      IF_iFifo_first__087_BIT_71_849_THEN_IF_iFifo_f_ETC___d4555;
      4'd6:
	  IF_iFifo_first__087_BITS_3_TO_0_088_EQ_0_089_O_ETC___d4623 =
	      IF_iFifo_first__087_BIT_71_849_THEN_IF_iFifo_f_ETC___d4618;
      default: IF_iFifo_first__087_BITS_3_TO_0_088_EQ_0_089_O_ETC___d4623 =
		   IF_iFifo_first__087_BIT_71_849_THEN_IF_iFifo_f_ETC___d4618;
    endcase
  end
  always@(fpu_madd_fState_S8$D_OUT or
	  IF_0b0_CONCAT_NOT_fpu_madd_fState_S8_first__96_ETC___d3065)
  begin
    case (fpu_madd_fState_S8$D_OUT[2:1])
      2'b0, 2'b01:
	  CASE_fpu_madd_fState_S8D_OUT_BITS_2_TO_1_0b0__ETC__q130 =
	      fpu_madd_fState_S8$D_OUT[65:3];
      2'b10:
	  CASE_fpu_madd_fState_S8D_OUT_BITS_2_TO_1_0b0__ETC__q130 =
	      fpu_madd_fState_S8$D_OUT[3] ?
		IF_0b0_CONCAT_NOT_fpu_madd_fState_S8_first__96_ETC___d3065 :
		fpu_madd_fState_S8$D_OUT[65:3];
      2'b11:
	  CASE_fpu_madd_fState_S8D_OUT_BITS_2_TO_1_0b0__ETC__q130 =
	      IF_0b0_CONCAT_NOT_fpu_madd_fState_S8_first__96_ETC___d3065;
    endcase
  end
  always@(fpu_madd_fState_S8$D_OUT or
	  IF_0b0_CONCAT_NOT_fpu_madd_fState_S8_first__96_ETC___d3065)
  begin
    case (fpu_madd_fState_S8$D_OUT[2:1])
      2'b0:
	  CASE_fpu_madd_fState_S8D_OUT_BITS_2_TO_1_0b0__ETC__q131 =
	      fpu_madd_fState_S8$D_OUT[65:3];
      2'b01, 2'b10, 2'b11:
	  CASE_fpu_madd_fState_S8D_OUT_BITS_2_TO_1_0b0__ETC__q131 =
	      IF_0b0_CONCAT_NOT_fpu_madd_fState_S8_first__96_ETC___d3065;
    endcase
  end
  always@(fpu_madd_fState_S8$D_OUT or
	  CASE_fpu_madd_fState_S8D_OUT_BITS_2_TO_1_0b0__ETC__q130 or
	  CASE_fpu_madd_fState_S8D_OUT_BITS_2_TO_1_0b0__ETC__q131 or
	  IF_0b0_CONCAT_NOT_fpu_madd_fState_S8_first__96_ETC___d3065)
  begin
    case (fpu_madd_fState_S8$D_OUT[70:68])
      3'd0:
	  CASE_fpu_madd_fState_S8D_OUT_BITS_70_TO_68_0__ETC__q132 =
	      CASE_fpu_madd_fState_S8D_OUT_BITS_2_TO_1_0b0__ETC__q130;
      3'd1:
	  CASE_fpu_madd_fState_S8D_OUT_BITS_70_TO_68_0__ETC__q132 =
	      CASE_fpu_madd_fState_S8D_OUT_BITS_2_TO_1_0b0__ETC__q131;
      3'd2:
	  CASE_fpu_madd_fState_S8D_OUT_BITS_70_TO_68_0__ETC__q132 =
	      (fpu_madd_fState_S8$D_OUT[2:1] == 2'b0 ||
	       fpu_madd_fState_S8$D_OUT[66]) ?
		fpu_madd_fState_S8$D_OUT[65:3] :
		IF_0b0_CONCAT_NOT_fpu_madd_fState_S8_first__96_ETC___d3065;
      3'd3:
	  CASE_fpu_madd_fState_S8D_OUT_BITS_70_TO_68_0__ETC__q132 =
	      (fpu_madd_fState_S8$D_OUT[2:1] == 2'b0) ?
		fpu_madd_fState_S8$D_OUT[65:3] :
		(fpu_madd_fState_S8$D_OUT[66] ?
		   IF_0b0_CONCAT_NOT_fpu_madd_fState_S8_first__96_ETC___d3065 :
		   fpu_madd_fState_S8$D_OUT[65:3]);
      3'd4:
	  CASE_fpu_madd_fState_S8D_OUT_BITS_70_TO_68_0__ETC__q132 =
	      fpu_madd_fState_S8$D_OUT[65:3];
      default: CASE_fpu_madd_fState_S8D_OUT_BITS_70_TO_68_0__ETC__q132 =
		   63'd0;
    endcase
  end
  always@(iFifo$D_OUT or
	  fpu_madd_fOperand_S0$FULL_N or
	  fpu_div64_fOperands_S0$FULL_N or fpu_sqr64_fOperand_S0$FULL_N)
  begin
    case (iFifo$D_OUT[3:0])
      4'd0, 4'd1, 4'd2, 4'd5, 4'd6, 4'd7:
	  IF_iFifo_first__087_BITS_3_TO_0_088_EQ_0_089_O_ETC___d3110 =
	      fpu_madd_fOperand_S0$FULL_N;
      4'd3:
	  IF_iFifo_first__087_BITS_3_TO_0_088_EQ_0_089_O_ETC___d3110 =
	      fpu_div64_fOperands_S0$FULL_N;
      4'd4:
	  IF_iFifo_first__087_BITS_3_TO_0_088_EQ_0_089_O_ETC___d3110 =
	      fpu_sqr64_fOperand_S0$FULL_N;
      default: IF_iFifo_first__087_BITS_3_TO_0_088_EQ_0_089_O_ETC___d3110 =
		   iFifo$D_OUT[3:0] != 4'd8 || fpu_madd_fOperand_S0$FULL_N;
    endcase
  end
  always@(rmdFifo$D_OUT or resWire$wget)
  begin
    case (rmdFifo$D_OUT)
      3'd0, 3'd1: _theResult___fst_exp__h269559 = 8'd255;
      3'd2:
	  _theResult___fst_exp__h269559 = resWire$wget[68] ? 8'd254 : 8'd255;
      3'd3:
	  _theResult___fst_exp__h269559 = resWire$wget[68] ? 8'd255 : 8'd254;
      3'd4: _theResult___fst_exp__h269559 = 8'd254;
      default: _theResult___fst_exp__h269559 = 8'd0;
    endcase
  end
  always@(rmdFifo$D_OUT or resWire$wget)
  begin
    case (rmdFifo$D_OUT)
      3'd0, 3'd1: _theResult___fst_sfd__h269560 = 23'd0;
      3'd2:
	  _theResult___fst_sfd__h269560 =
	      resWire$wget[68] ? 23'd8388607 : 23'd0;
      3'd3:
	  _theResult___fst_sfd__h269560 =
	      resWire$wget[68] ? 23'd0 : 23'd8388607;
      3'd4: _theResult___fst_sfd__h269560 = 23'd8388607;
      default: _theResult___fst_sfd__h269560 = 23'd0;
    endcase
  end
  always@(guard__h269587 or resWire$wget)
  begin
    case (guard__h269587)
      2'b0, 2'b01, 2'b10:
	  CASE_guard69587_0b0_resWirewget_BIT_68_0b1_re_ETC__q144 =
	      resWire$wget[68];
      2'd3:
	  CASE_guard69587_0b0_resWirewget_BIT_68_0b1_re_ETC__q144 =
	      guard__h269587 == 2'b11 && resWire$wget[68];
    endcase
  end
  always@(rmdFifo$D_OUT or
	  resWire$wget or
	  CASE_guard69587_0b0_resWirewget_BIT_68_0b1_re_ETC__q144 or
	  guard__h269587)
  begin
    case (rmdFifo$D_OUT)
      3'd0:
	  IF_rmdFifo_first__778_EQ_0_779_THEN_IF_IF_IF_I_ETC___d6388 =
	      CASE_guard69587_0b0_resWirewget_BIT_68_0b1_re_ETC__q144;
      3'd1:
	  IF_rmdFifo_first__778_EQ_0_779_THEN_IF_IF_IF_I_ETC___d6388 =
	      (guard__h269587 == 2'b0) ?
		resWire$wget[68] :
		(guard__h269587 == 2'b01 || guard__h269587 == 2'b10 ||
		 guard__h269587 == 2'b11) &&
		resWire$wget[68];
      3'd2, 3'd3:
	  IF_rmdFifo_first__778_EQ_0_779_THEN_IF_IF_IF_I_ETC___d6388 =
	      resWire$wget[68];
      default: IF_rmdFifo_first__778_EQ_0_779_THEN_IF_IF_IF_I_ETC___d6388 =
		   rmdFifo$D_OUT == 3'd4 && resWire$wget[68];
    endcase
  end
  always@(guard__h269587 or resWire$wget)
  begin
    case (guard__h269587)
      2'b0, 2'b01, 2'b10:
	  CASE_guard69587_0b0_NOT_resWirewget_BIT_68_0b_ETC__q145 =
	      !resWire$wget[68];
      2'd3:
	  CASE_guard69587_0b0_NOT_resWirewget_BIT_68_0b_ETC__q145 =
	      guard__h269587 != 2'b11 || !resWire$wget[68];
    endcase
  end
  always@(rmdFifo$D_OUT or
	  resWire$wget or
	  CASE_guard69587_0b0_NOT_resWirewget_BIT_68_0b_ETC__q145 or
	  guard__h269587)
  begin
    case (rmdFifo$D_OUT)
      3'd0:
	  IF_rmdFifo_first__778_EQ_0_779_THEN_IF_IF_IF_I_ETC___d5823 =
	      CASE_guard69587_0b0_NOT_resWirewget_BIT_68_0b_ETC__q145;
      3'd1:
	  IF_rmdFifo_first__778_EQ_0_779_THEN_IF_IF_IF_I_ETC___d5823 =
	      (guard__h269587 == 2'b0) ?
		!resWire$wget[68] :
		guard__h269587 != 2'b01 && guard__h269587 != 2'b10 &&
		guard__h269587 != 2'b11 ||
		!resWire$wget[68];
      3'd2, 3'd3:
	  IF_rmdFifo_first__778_EQ_0_779_THEN_IF_IF_IF_I_ETC___d5823 =
	      !resWire$wget[68];
      default: IF_rmdFifo_first__778_EQ_0_779_THEN_IF_IF_IF_I_ETC___d5823 =
		   rmdFifo$D_OUT != 3'd4 || !resWire$wget[68];
    endcase
  end
  always@(guard__h278294 or resWire$wget)
  begin
    case (guard__h278294)
      2'b0, 2'b01, 2'b10:
	  CASE_guard78294_0b0_resWirewget_BIT_68_0b1_re_ETC__q146 =
	      resWire$wget[68];
      2'd3:
	  CASE_guard78294_0b0_resWirewget_BIT_68_0b1_re_ETC__q146 =
	      guard__h278294 == 2'b11 && resWire$wget[68];
    endcase
  end
  always@(rmdFifo$D_OUT or
	  resWire$wget or
	  CASE_guard78294_0b0_resWirewget_BIT_68_0b1_re_ETC__q146 or
	  guard__h278294)
  begin
    case (rmdFifo$D_OUT)
      3'd0:
	  IF_rmdFifo_first__778_EQ_0_779_THEN_IF_IF_IF_r_ETC___d6397 =
	      CASE_guard78294_0b0_resWirewget_BIT_68_0b1_re_ETC__q146;
      3'd1:
	  IF_rmdFifo_first__778_EQ_0_779_THEN_IF_IF_IF_r_ETC___d6397 =
	      (guard__h278294 == 2'b0) ?
		resWire$wget[68] :
		(guard__h278294 == 2'b01 || guard__h278294 == 2'b10 ||
		 guard__h278294 == 2'b11) &&
		resWire$wget[68];
      3'd2, 3'd3:
	  IF_rmdFifo_first__778_EQ_0_779_THEN_IF_IF_IF_r_ETC___d6397 =
	      resWire$wget[68];
      default: IF_rmdFifo_first__778_EQ_0_779_THEN_IF_IF_IF_r_ETC___d6397 =
		   rmdFifo$D_OUT == 3'd4 && resWire$wget[68];
    endcase
  end
  always@(guard__h278294 or resWire$wget)
  begin
    case (guard__h278294)
      2'b0, 2'b01, 2'b10:
	  CASE_guard78294_0b0_NOT_resWirewget_BIT_68_0b_ETC__q147 =
	      !resWire$wget[68];
      2'd3:
	  CASE_guard78294_0b0_NOT_resWirewget_BIT_68_0b_ETC__q147 =
	      guard__h278294 != 2'b11 || !resWire$wget[68];
    endcase
  end
  always@(rmdFifo$D_OUT or
	  resWire$wget or
	  CASE_guard78294_0b0_NOT_resWirewget_BIT_68_0b_ETC__q147 or
	  guard__h278294)
  begin
    case (rmdFifo$D_OUT)
      3'd0:
	  IF_rmdFifo_first__778_EQ_0_779_THEN_IF_IF_IF_r_ETC___d6023 =
	      CASE_guard78294_0b0_NOT_resWirewget_BIT_68_0b_ETC__q147;
      3'd1:
	  IF_rmdFifo_first__778_EQ_0_779_THEN_IF_IF_IF_r_ETC___d6023 =
	      (guard__h278294 == 2'b0) ?
		!resWire$wget[68] :
		guard__h278294 != 2'b01 && guard__h278294 != 2'b10 &&
		guard__h278294 != 2'b11 ||
		!resWire$wget[68];
      3'd2, 3'd3:
	  IF_rmdFifo_first__778_EQ_0_779_THEN_IF_IF_IF_r_ETC___d6023 =
	      !resWire$wget[68];
      default: IF_rmdFifo_first__778_EQ_0_779_THEN_IF_IF_IF_r_ETC___d6023 =
		   rmdFifo$D_OUT != 3'd4 || !resWire$wget[68];
    endcase
  end
  always@(guard__h287224 or resWire$wget)
  begin
    case (guard__h287224)
      2'b0, 2'b01, 2'b10:
	  CASE_guard87224_0b0_resWirewget_BIT_68_0b1_re_ETC__q148 =
	      resWire$wget[68];
      2'd3:
	  CASE_guard87224_0b0_resWirewget_BIT_68_0b1_re_ETC__q148 =
	      guard__h287224 == 2'b11 && resWire$wget[68];
    endcase
  end
  always@(rmdFifo$D_OUT or
	  resWire$wget or
	  CASE_guard87224_0b0_resWirewget_BIT_68_0b1_re_ETC__q148 or
	  guard__h287224)
  begin
    case (rmdFifo$D_OUT)
      3'd0:
	  IF_rmdFifo_first__778_EQ_0_779_THEN_IF_IF_IF_I_ETC___d6409 =
	      CASE_guard87224_0b0_resWirewget_BIT_68_0b1_re_ETC__q148;
      3'd1:
	  IF_rmdFifo_first__778_EQ_0_779_THEN_IF_IF_IF_I_ETC___d6409 =
	      (guard__h287224 == 2'b0) ?
		resWire$wget[68] :
		(guard__h287224 == 2'b01 || guard__h287224 == 2'b10 ||
		 guard__h287224 == 2'b11) &&
		resWire$wget[68];
      3'd2, 3'd3:
	  IF_rmdFifo_first__778_EQ_0_779_THEN_IF_IF_IF_I_ETC___d6409 =
	      resWire$wget[68];
      default: IF_rmdFifo_first__778_EQ_0_779_THEN_IF_IF_IF_I_ETC___d6409 =
		   rmdFifo$D_OUT == 3'd4 && resWire$wget[68];
    endcase
  end
  always@(guard__h287224 or resWire$wget)
  begin
    case (guard__h287224)
      2'b0, 2'b01, 2'b10:
	  CASE_guard87224_0b0_NOT_resWirewget_BIT_68_0b_ETC__q149 =
	      !resWire$wget[68];
      2'd3:
	  CASE_guard87224_0b0_NOT_resWirewget_BIT_68_0b_ETC__q149 =
	      guard__h287224 != 2'b11 || !resWire$wget[68];
    endcase
  end
  always@(rmdFifo$D_OUT or
	  resWire$wget or
	  CASE_guard87224_0b0_NOT_resWirewget_BIT_68_0b_ETC__q149 or
	  guard__h287224)
  begin
    case (rmdFifo$D_OUT)
      3'd0:
	  IF_rmdFifo_first__778_EQ_0_779_THEN_IF_IF_IF_I_ETC___d6324 =
	      CASE_guard87224_0b0_NOT_resWirewget_BIT_68_0b_ETC__q149;
      3'd1:
	  IF_rmdFifo_first__778_EQ_0_779_THEN_IF_IF_IF_I_ETC___d6324 =
	      (guard__h287224 == 2'b0) ?
		!resWire$wget[68] :
		guard__h287224 != 2'b01 && guard__h287224 != 2'b10 &&
		guard__h287224 != 2'b11 ||
		!resWire$wget[68];
      3'd2, 3'd3:
	  IF_rmdFifo_first__778_EQ_0_779_THEN_IF_IF_IF_I_ETC___d6324 =
	      !resWire$wget[68];
      default: IF_rmdFifo_first__778_EQ_0_779_THEN_IF_IF_IF_I_ETC___d6324 =
		   rmdFifo$D_OUT != 3'd4 || !resWire$wget[68];
    endcase
  end
  always@(guard__h296060 or resWire$wget)
  begin
    case (guard__h296060)
      2'b0, 2'b01, 2'b10:
	  CASE_guard96060_0b0_resWirewget_BIT_68_0b1_re_ETC__q150 =
	      resWire$wget[68];
      2'd3:
	  CASE_guard96060_0b0_resWirewget_BIT_68_0b1_re_ETC__q150 =
	      guard__h296060 == 2'b11 && resWire$wget[68];
    endcase
  end
  always@(rmdFifo$D_OUT or
	  resWire$wget or
	  CASE_guard96060_0b0_resWirewget_BIT_68_0b1_re_ETC__q150 or
	  guard__h296060)
  begin
    case (rmdFifo$D_OUT)
      3'd0:
	  IF_rmdFifo_first__778_EQ_0_779_THEN_IF_IF_IF_r_ETC___d6418 =
	      CASE_guard96060_0b0_resWirewget_BIT_68_0b1_re_ETC__q150;
      3'd1:
	  IF_rmdFifo_first__778_EQ_0_779_THEN_IF_IF_IF_r_ETC___d6418 =
	      (guard__h296060 == 2'b0) ?
		resWire$wget[68] :
		(guard__h296060 == 2'b01 || guard__h296060 == 2'b10 ||
		 guard__h296060 == 2'b11) &&
		resWire$wget[68];
      3'd2, 3'd3:
	  IF_rmdFifo_first__778_EQ_0_779_THEN_IF_IF_IF_r_ETC___d6418 =
	      resWire$wget[68];
      default: IF_rmdFifo_first__778_EQ_0_779_THEN_IF_IF_IF_r_ETC___d6418 =
		   rmdFifo$D_OUT == 3'd4 && resWire$wget[68];
    endcase
  end
  always@(guard__h296060 or resWire$wget)
  begin
    case (guard__h296060)
      2'b0, 2'b01, 2'b10:
	  CASE_guard96060_0b0_NOT_resWirewget_BIT_68_0b_ETC__q151 =
	      !resWire$wget[68];
      2'd3:
	  CASE_guard96060_0b0_NOT_resWirewget_BIT_68_0b_ETC__q151 =
	      guard__h296060 != 2'b11 || !resWire$wget[68];
    endcase
  end
  always@(rmdFifo$D_OUT or
	  resWire$wget or
	  CASE_guard96060_0b0_NOT_resWirewget_BIT_68_0b_ETC__q151 or
	  guard__h296060)
  begin
    case (rmdFifo$D_OUT)
      3'd0:
	  IF_rmdFifo_first__778_EQ_0_779_THEN_IF_IF_IF_r_ETC___d6373 =
	      CASE_guard96060_0b0_NOT_resWirewget_BIT_68_0b_ETC__q151;
      3'd1:
	  IF_rmdFifo_first__778_EQ_0_779_THEN_IF_IF_IF_r_ETC___d6373 =
	      (guard__h296060 == 2'b0) ?
		!resWire$wget[68] :
		guard__h296060 != 2'b01 && guard__h296060 != 2'b10 &&
		guard__h296060 != 2'b11 ||
		!resWire$wget[68];
      3'd2, 3'd3:
	  IF_rmdFifo_first__778_EQ_0_779_THEN_IF_IF_IF_r_ETC___d6373 =
	      !resWire$wget[68];
      default: IF_rmdFifo_first__778_EQ_0_779_THEN_IF_IF_IF_r_ETC___d6373 =
		   rmdFifo$D_OUT != 3'd4 || !resWire$wget[68];
    endcase
  end
  always@(rmdFifo$D_OUT or resWire$wget)
  begin
    case (rmdFifo$D_OUT)
      3'd0, 3'd1, 3'd2, 3'd3:
	  IF_rmdFifo_first__778_EQ_0_779_OR_rmdFifo_firs_ETC___d6400 =
	      resWire$wget[68];
      default: IF_rmdFifo_first__778_EQ_0_779_OR_rmdFifo_firs_ETC___d6400 =
		   rmdFifo$D_OUT == 3'd4 && resWire$wget[68];
    endcase
  end
  always@(rmdFifo$D_OUT or resWire$wget)
  begin
    case (rmdFifo$D_OUT)
      3'd0, 3'd1, 3'd2, 3'd3:
	  IF_rmdFifo_first__778_EQ_0_779_OR_rmdFifo_firs_ETC___d6028 =
	      !resWire$wget[68];
      default: IF_rmdFifo_first__778_EQ_0_779_OR_rmdFifo_firs_ETC___d6028 =
		   rmdFifo$D_OUT != 3'd4 || !resWire$wget[68];
    endcase
  end
  always@(guard__h278294 or
	  _theResult___fst_exp__h286342 or
	  out_exp__h286787 or _theResult___exp__h286784)
  begin
    case (guard__h278294)
      2'b0, 2'b01:
	  CASE_guard78294_0b0_theResult___fst_exp86342_0_ETC__q152 =
	      _theResult___fst_exp__h286342;
      2'b10:
	  CASE_guard78294_0b0_theResult___fst_exp86342_0_ETC__q152 =
	      out_exp__h286787;
      2'b11:
	  CASE_guard78294_0b0_theResult___fst_exp86342_0_ETC__q152 =
	      _theResult___exp__h286784;
    endcase
  end
  always@(guard__h278294 or
	  _theResult___fst_exp__h286342 or _theResult___exp__h286784)
  begin
    case (guard__h278294)
      2'b0:
	  CASE_guard78294_0b0_theResult___fst_exp86342_0_ETC__q153 =
	      _theResult___fst_exp__h286342;
      2'b01, 2'b10, 2'b11:
	  CASE_guard78294_0b0_theResult___fst_exp86342_0_ETC__q153 =
	      _theResult___exp__h286784;
    endcase
  end
  always@(rmdFifo$D_OUT or
	  CASE_guard78294_0b0_theResult___fst_exp86342_0_ETC__q152 or
	  CASE_guard78294_0b0_theResult___fst_exp86342_0_ETC__q153 or
	  IF_IF_IF_resWire_wget__410_BITS_67_TO_57_416_E_ETC___d6479 or
	  IF_IF_IF_resWire_wget__410_BITS_67_TO_57_416_E_ETC___d6481 or
	  _theResult___fst_exp__h286342)
  begin
    case (rmdFifo$D_OUT)
      3'd0:
	  _theResult___fst_exp__h286862 =
	      CASE_guard78294_0b0_theResult___fst_exp86342_0_ETC__q152;
      3'd1:
	  _theResult___fst_exp__h286862 =
	      CASE_guard78294_0b0_theResult___fst_exp86342_0_ETC__q153;
      3'd2:
	  _theResult___fst_exp__h286862 =
	      IF_IF_IF_resWire_wget__410_BITS_67_TO_57_416_E_ETC___d6479;
      3'd3:
	  _theResult___fst_exp__h286862 =
	      IF_IF_IF_resWire_wget__410_BITS_67_TO_57_416_E_ETC___d6481;
      3'd4: _theResult___fst_exp__h286862 = _theResult___fst_exp__h286342;
      default: _theResult___fst_exp__h286862 = 8'd0;
    endcase
  end
  always@(guard__h269587 or
	  _theResult___fst_exp__h277686 or
	  out_exp__h278205 or _theResult___exp__h278202)
  begin
    case (guard__h269587)
      2'b0, 2'b01:
	  CASE_guard69587_0b0_theResult___fst_exp77686_0_ETC__q154 =
	      _theResult___fst_exp__h277686;
      2'b10:
	  CASE_guard69587_0b0_theResult___fst_exp77686_0_ETC__q154 =
	      out_exp__h278205;
      2'b11:
	  CASE_guard69587_0b0_theResult___fst_exp77686_0_ETC__q154 =
	      _theResult___exp__h278202;
    endcase
  end
  always@(guard__h269587 or
	  _theResult___fst_exp__h277686 or _theResult___exp__h278202)
  begin
    case (guard__h269587)
      2'b0:
	  CASE_guard69587_0b0_theResult___fst_exp77686_0_ETC__q155 =
	      _theResult___fst_exp__h277686;
      2'b01, 2'b10, 2'b11:
	  CASE_guard69587_0b0_theResult___fst_exp77686_0_ETC__q155 =
	      _theResult___exp__h278202;
    endcase
  end
  always@(rmdFifo$D_OUT or
	  CASE_guard69587_0b0_theResult___fst_exp77686_0_ETC__q154 or
	  CASE_guard69587_0b0_theResult___fst_exp77686_0_ETC__q155 or
	  IF_IF_IF_IF_0b0_CONCAT_NOT_resWire_wget__410_B_ETC___d6448 or
	  IF_IF_IF_IF_0b0_CONCAT_NOT_resWire_wget__410_B_ETC___d6450 or
	  _theResult___fst_exp__h277686)
  begin
    case (rmdFifo$D_OUT)
      3'd0:
	  _theResult___fst_exp__h278280 =
	      CASE_guard69587_0b0_theResult___fst_exp77686_0_ETC__q154;
      3'd1:
	  _theResult___fst_exp__h278280 =
	      CASE_guard69587_0b0_theResult___fst_exp77686_0_ETC__q155;
      3'd2:
	  _theResult___fst_exp__h278280 =
	      IF_IF_IF_IF_0b0_CONCAT_NOT_resWire_wget__410_B_ETC___d6448;
      3'd3:
	  _theResult___fst_exp__h278280 =
	      IF_IF_IF_IF_0b0_CONCAT_NOT_resWire_wget__410_B_ETC___d6450;
      3'd4: _theResult___fst_exp__h278280 = _theResult___fst_exp__h277686;
      default: _theResult___fst_exp__h278280 = 8'd0;
    endcase
  end
  always@(guard__h287224 or
	  _theResult___fst_exp__h295452 or
	  out_exp__h295971 or _theResult___exp__h295968)
  begin
    case (guard__h287224)
      2'b0, 2'b01:
	  CASE_guard87224_0b0_theResult___fst_exp95452_0_ETC__q156 =
	      _theResult___fst_exp__h295452;
      2'b10:
	  CASE_guard87224_0b0_theResult___fst_exp95452_0_ETC__q156 =
	      out_exp__h295971;
      2'b11:
	  CASE_guard87224_0b0_theResult___fst_exp95452_0_ETC__q156 =
	      _theResult___exp__h295968;
    endcase
  end
  always@(guard__h287224 or
	  _theResult___fst_exp__h295452 or _theResult___exp__h295968)
  begin
    case (guard__h287224)
      2'b0:
	  CASE_guard87224_0b0_theResult___fst_exp95452_0_ETC__q157 =
	      _theResult___fst_exp__h295452;
      2'b01, 2'b10, 2'b11:
	  CASE_guard87224_0b0_theResult___fst_exp95452_0_ETC__q157 =
	      _theResult___exp__h295968;
    endcase
  end
  always@(rmdFifo$D_OUT or
	  CASE_guard87224_0b0_theResult___fst_exp95452_0_ETC__q156 or
	  CASE_guard87224_0b0_theResult___fst_exp95452_0_ETC__q157 or
	  IF_IF_IF_IF_3970_MINUS_SEXT_resWire_wget__410__ETC___d6518 or
	  IF_IF_IF_IF_3970_MINUS_SEXT_resWire_wget__410__ETC___d6520 or
	  _theResult___fst_exp__h295452)
  begin
    case (rmdFifo$D_OUT)
      3'd0:
	  _theResult___fst_exp__h296046 =
	      CASE_guard87224_0b0_theResult___fst_exp95452_0_ETC__q156;
      3'd1:
	  _theResult___fst_exp__h296046 =
	      CASE_guard87224_0b0_theResult___fst_exp95452_0_ETC__q157;
      3'd2:
	  _theResult___fst_exp__h296046 =
	      IF_IF_IF_IF_3970_MINUS_SEXT_resWire_wget__410__ETC___d6518;
      3'd3:
	  _theResult___fst_exp__h296046 =
	      IF_IF_IF_IF_3970_MINUS_SEXT_resWire_wget__410__ETC___d6520;
      3'd4: _theResult___fst_exp__h296046 = _theResult___fst_exp__h295452;
      default: _theResult___fst_exp__h296046 = 8'd0;
    endcase
  end
  always@(guard__h296060 or
	  _theResult___fst_exp__h304137 or
	  out_exp__h304607 or _theResult___exp__h304604)
  begin
    case (guard__h296060)
      2'b0, 2'b01:
	  CASE_guard96060_0b0_theResult___fst_exp04137_0_ETC__q158 =
	      _theResult___fst_exp__h304137;
      2'b10:
	  CASE_guard96060_0b0_theResult___fst_exp04137_0_ETC__q158 =
	      out_exp__h304607;
      2'b11:
	  CASE_guard96060_0b0_theResult___fst_exp04137_0_ETC__q158 =
	      _theResult___exp__h304604;
    endcase
  end
  always@(guard__h296060 or
	  _theResult___fst_exp__h304137 or _theResult___exp__h304604)
  begin
    case (guard__h296060)
      2'b0:
	  CASE_guard96060_0b0_theResult___fst_exp04137_0_ETC__q159 =
	      _theResult___fst_exp__h304137;
      2'b01, 2'b10, 2'b11:
	  CASE_guard96060_0b0_theResult___fst_exp04137_0_ETC__q159 =
	      _theResult___exp__h304604;
    endcase
  end
  always@(rmdFifo$D_OUT or
	  CASE_guard96060_0b0_theResult___fst_exp04137_0_ETC__q158 or
	  CASE_guard96060_0b0_theResult___fst_exp04137_0_ETC__q159 or
	  IF_IF_IF_resWire_wget__410_BITS_67_TO_57_416_E_ETC___d6549 or
	  IF_IF_IF_resWire_wget__410_BITS_67_TO_57_416_E_ETC___d6551 or
	  _theResult___fst_exp__h304137)
  begin
    case (rmdFifo$D_OUT)
      3'd0:
	  _theResult___fst_exp__h304682 =
	      CASE_guard96060_0b0_theResult___fst_exp04137_0_ETC__q158;
      3'd1:
	  _theResult___fst_exp__h304682 =
	      CASE_guard96060_0b0_theResult___fst_exp04137_0_ETC__q159;
      3'd2:
	  _theResult___fst_exp__h304682 =
	      IF_IF_IF_resWire_wget__410_BITS_67_TO_57_416_E_ETC___d6549;
      3'd3:
	  _theResult___fst_exp__h304682 =
	      IF_IF_IF_resWire_wget__410_BITS_67_TO_57_416_E_ETC___d6551;
      3'd4: _theResult___fst_exp__h304682 = _theResult___fst_exp__h304137;
      default: _theResult___fst_exp__h304682 = 8'd0;
    endcase
  end
  always@(guard__h278294 or
	  _theResult___snd__h286293 or
	  out_sfd__h286788 or _theResult___sfd__h286785)
  begin
    case (guard__h278294)
      2'b0, 2'b01:
	  CASE_guard78294_0b0_theResult___snd86293_BITS__ETC__q160 =
	      _theResult___snd__h286293[56:34];
      2'b10:
	  CASE_guard78294_0b0_theResult___snd86293_BITS__ETC__q160 =
	      out_sfd__h286788;
      2'b11:
	  CASE_guard78294_0b0_theResult___snd86293_BITS__ETC__q160 =
	      _theResult___sfd__h286785;
    endcase
  end
  always@(guard__h278294 or
	  _theResult___snd__h286293 or _theResult___sfd__h286785)
  begin
    case (guard__h278294)
      2'b0:
	  CASE_guard78294_0b0_theResult___snd86293_BITS__ETC__q161 =
	      _theResult___snd__h286293[56:34];
      2'b01, 2'b10, 2'b11:
	  CASE_guard78294_0b0_theResult___snd86293_BITS__ETC__q161 =
	      _theResult___sfd__h286785;
    endcase
  end
  always@(rmdFifo$D_OUT or
	  CASE_guard78294_0b0_theResult___snd86293_BITS__ETC__q160 or
	  CASE_guard78294_0b0_theResult___snd86293_BITS__ETC__q161 or
	  IF_IF_IF_resWire_wget__410_BITS_67_TO_57_416_E_ETC___d6595 or
	  IF_IF_IF_resWire_wget__410_BITS_67_TO_57_416_E_ETC___d6597 or
	  _theResult___snd__h286293)
  begin
    case (rmdFifo$D_OUT)
      3'd0:
	  _theResult___fst_sfd__h286863 =
	      CASE_guard78294_0b0_theResult___snd86293_BITS__ETC__q160;
      3'd1:
	  _theResult___fst_sfd__h286863 =
	      CASE_guard78294_0b0_theResult___snd86293_BITS__ETC__q161;
      3'd2:
	  _theResult___fst_sfd__h286863 =
	      IF_IF_IF_resWire_wget__410_BITS_67_TO_57_416_E_ETC___d6595;
      3'd3:
	  _theResult___fst_sfd__h286863 =
	      IF_IF_IF_resWire_wget__410_BITS_67_TO_57_416_E_ETC___d6597;
      3'd4: _theResult___fst_sfd__h286863 = _theResult___snd__h286293[56:34];
      default: _theResult___fst_sfd__h286863 = 23'd0;
    endcase
  end
  always@(guard__h269587 or
	  sfdin__h277680 or out_sfd__h278206 or _theResult___sfd__h278203)
  begin
    case (guard__h269587)
      2'b0, 2'b01:
	  CASE_guard69587_0b0_sfdin77680_BITS_56_TO_34_0_ETC__q162 =
	      sfdin__h277680[56:34];
      2'b10:
	  CASE_guard69587_0b0_sfdin77680_BITS_56_TO_34_0_ETC__q162 =
	      out_sfd__h278206;
      2'b11:
	  CASE_guard69587_0b0_sfdin77680_BITS_56_TO_34_0_ETC__q162 =
	      _theResult___sfd__h278203;
    endcase
  end
  always@(guard__h269587 or sfdin__h277680 or _theResult___sfd__h278203)
  begin
    case (guard__h269587)
      2'b0:
	  CASE_guard69587_0b0_sfdin77680_BITS_56_TO_34_0_ETC__q163 =
	      sfdin__h277680[56:34];
      2'b01, 2'b10, 2'b11:
	  CASE_guard69587_0b0_sfdin77680_BITS_56_TO_34_0_ETC__q163 =
	      _theResult___sfd__h278203;
    endcase
  end
  always@(rmdFifo$D_OUT or
	  CASE_guard69587_0b0_sfdin77680_BITS_56_TO_34_0_ETC__q162 or
	  CASE_guard69587_0b0_sfdin77680_BITS_56_TO_34_0_ETC__q163 or
	  IF_IF_IF_IF_0b0_CONCAT_NOT_resWire_wget__410_B_ETC___d6576 or
	  IF_IF_IF_IF_0b0_CONCAT_NOT_resWire_wget__410_B_ETC___d6578 or
	  sfdin__h277680)
  begin
    case (rmdFifo$D_OUT)
      3'd0:
	  _theResult___fst_sfd__h278281 =
	      CASE_guard69587_0b0_sfdin77680_BITS_56_TO_34_0_ETC__q162;
      3'd1:
	  _theResult___fst_sfd__h278281 =
	      CASE_guard69587_0b0_sfdin77680_BITS_56_TO_34_0_ETC__q163;
      3'd2:
	  _theResult___fst_sfd__h278281 =
	      IF_IF_IF_IF_0b0_CONCAT_NOT_resWire_wget__410_B_ETC___d6576;
      3'd3:
	  _theResult___fst_sfd__h278281 =
	      IF_IF_IF_IF_0b0_CONCAT_NOT_resWire_wget__410_B_ETC___d6578;
      3'd4: _theResult___fst_sfd__h278281 = sfdin__h277680[56:34];
      default: _theResult___fst_sfd__h278281 = 23'd0;
    endcase
  end
  always@(guard__h287224 or
	  sfdin__h295446 or out_sfd__h295972 or _theResult___sfd__h295969)
  begin
    case (guard__h287224)
      2'b0, 2'b01:
	  CASE_guard87224_0b0_sfdin95446_BITS_56_TO_34_0_ETC__q164 =
	      sfdin__h295446[56:34];
      2'b10:
	  CASE_guard87224_0b0_sfdin95446_BITS_56_TO_34_0_ETC__q164 =
	      out_sfd__h295972;
      2'b11:
	  CASE_guard87224_0b0_sfdin95446_BITS_56_TO_34_0_ETC__q164 =
	      _theResult___sfd__h295969;
    endcase
  end
  always@(guard__h287224 or sfdin__h295446 or _theResult___sfd__h295969)
  begin
    case (guard__h287224)
      2'b0:
	  CASE_guard87224_0b0_sfdin95446_BITS_56_TO_34_0_ETC__q165 =
	      sfdin__h295446[56:34];
      2'b01, 2'b10, 2'b11:
	  CASE_guard87224_0b0_sfdin95446_BITS_56_TO_34_0_ETC__q165 =
	      _theResult___sfd__h295969;
    endcase
  end
  always@(rmdFifo$D_OUT or
	  CASE_guard87224_0b0_sfdin95446_BITS_56_TO_34_0_ETC__q164 or
	  CASE_guard87224_0b0_sfdin95446_BITS_56_TO_34_0_ETC__q165 or
	  IF_IF_IF_IF_3970_MINUS_SEXT_resWire_wget__410__ETC___d6622 or
	  IF_IF_IF_IF_3970_MINUS_SEXT_resWire_wget__410__ETC___d6624 or
	  sfdin__h295446)
  begin
    case (rmdFifo$D_OUT)
      3'd0:
	  _theResult___fst_sfd__h296047 =
	      CASE_guard87224_0b0_sfdin95446_BITS_56_TO_34_0_ETC__q164;
      3'd1:
	  _theResult___fst_sfd__h296047 =
	      CASE_guard87224_0b0_sfdin95446_BITS_56_TO_34_0_ETC__q165;
      3'd2:
	  _theResult___fst_sfd__h296047 =
	      IF_IF_IF_IF_3970_MINUS_SEXT_resWire_wget__410__ETC___d6622;
      3'd3:
	  _theResult___fst_sfd__h296047 =
	      IF_IF_IF_IF_3970_MINUS_SEXT_resWire_wget__410__ETC___d6624;
      3'd4: _theResult___fst_sfd__h296047 = sfdin__h295446[56:34];
      default: _theResult___fst_sfd__h296047 = 23'd0;
    endcase
  end
  always@(guard__h296060 or
	  _theResult___snd__h304083 or
	  out_sfd__h304608 or _theResult___sfd__h304605)
  begin
    case (guard__h296060)
      2'b0, 2'b01:
	  CASE_guard96060_0b0_theResult___snd04083_BITS__ETC__q166 =
	      _theResult___snd__h304083[56:34];
      2'b10:
	  CASE_guard96060_0b0_theResult___snd04083_BITS__ETC__q166 =
	      out_sfd__h304608;
      2'b11:
	  CASE_guard96060_0b0_theResult___snd04083_BITS__ETC__q166 =
	      _theResult___sfd__h304605;
    endcase
  end
  always@(guard__h296060 or
	  _theResult___snd__h304083 or _theResult___sfd__h304605)
  begin
    case (guard__h296060)
      2'b0:
	  CASE_guard96060_0b0_theResult___snd04083_BITS__ETC__q167 =
	      _theResult___snd__h304083[56:34];
      2'b01, 2'b10, 2'b11:
	  CASE_guard96060_0b0_theResult___snd04083_BITS__ETC__q167 =
	      _theResult___sfd__h304605;
    endcase
  end
  always@(rmdFifo$D_OUT or
	  CASE_guard96060_0b0_theResult___snd04083_BITS__ETC__q166 or
	  CASE_guard96060_0b0_theResult___snd04083_BITS__ETC__q167 or
	  IF_IF_IF_resWire_wget__410_BITS_67_TO_57_416_E_ETC___d6641 or
	  IF_IF_IF_resWire_wget__410_BITS_67_TO_57_416_E_ETC___d6643 or
	  _theResult___snd__h304083)
  begin
    case (rmdFifo$D_OUT)
      3'd0:
	  _theResult___fst_sfd__h304683 =
	      CASE_guard96060_0b0_theResult___snd04083_BITS__ETC__q166;
      3'd1:
	  _theResult___fst_sfd__h304683 =
	      CASE_guard96060_0b0_theResult___snd04083_BITS__ETC__q167;
      3'd2:
	  _theResult___fst_sfd__h304683 =
	      IF_IF_IF_resWire_wget__410_BITS_67_TO_57_416_E_ETC___d6641;
      3'd3:
	  _theResult___fst_sfd__h304683 =
	      IF_IF_IF_resWire_wget__410_BITS_67_TO_57_416_E_ETC___d6643;
      3'd4: _theResult___fst_sfd__h304683 = _theResult___snd__h304083[56:34];
      default: _theResult___fst_sfd__h304683 = 23'd0;
    endcase
  end
  always@(fpu_div64_fState_S4$D_OUT)
  begin
    case (fpu_div64_fState_S4$D_OUT[68:66])
      3'd2, 3'd3:
	  CASE_fpu_div64_fState_S4D_OUT_BITS_68_TO_66_2_ETC__q168 =
	      fpu_div64_fState_S4$D_OUT[65];
      default: CASE_fpu_div64_fState_S4D_OUT_BITS_68_TO_66_2_ETC__q168 =
		   fpu_div64_fState_S4$D_OUT[68:66] == 3'd4 &&
		   fpu_div64_fState_S4$D_OUT[65];
    endcase
  end
  always@(fpu_div64_fState_S4$D_OUT or
	  IF_0b0_CONCAT_NOT_fpu_div64_fState_S4_first__4_ETC___d980)
  begin
    case (fpu_div64_fState_S4$D_OUT[68:66])
      3'd2:
	  CASE_fpu_div64_fState_S4D_OUT_BITS_68_TO_66_2_ETC__q169 =
	      (fpu_div64_fState_S4$D_OUT[1:0] == 2'b0 ||
	       fpu_div64_fState_S4$D_OUT[65]) ?
		fpu_div64_fState_S4$D_OUT[64:2] :
		IF_0b0_CONCAT_NOT_fpu_div64_fState_S4_first__4_ETC___d980;
      3'd3:
	  CASE_fpu_div64_fState_S4D_OUT_BITS_68_TO_66_2_ETC__q169 =
	      (fpu_div64_fState_S4$D_OUT[1:0] == 2'b0) ?
		fpu_div64_fState_S4$D_OUT[64:2] :
		(fpu_div64_fState_S4$D_OUT[65] ?
		   IF_0b0_CONCAT_NOT_fpu_div64_fState_S4_first__4_ETC___d980 :
		   fpu_div64_fState_S4$D_OUT[64:2]);
      3'd4:
	  CASE_fpu_div64_fState_S4D_OUT_BITS_68_TO_66_2_ETC__q169 =
	      fpu_div64_fState_S4$D_OUT[64:2];
      default: CASE_fpu_div64_fState_S4D_OUT_BITS_68_TO_66_2_ETC__q169 =
		   63'd0;
    endcase
  end
  always@(fpu_div64_fState_S4$D_OUT)
  begin
    case (fpu_div64_fState_S4$D_OUT[1:0])
      2'b0, 2'b01, 2'b10:
	  CASE_fpu_div64_fState_S4D_OUT_BITS_1_TO_0_0b0_ETC__q170 =
	      fpu_div64_fState_S4$D_OUT[65];
      2'd3:
	  CASE_fpu_div64_fState_S4D_OUT_BITS_1_TO_0_0b0_ETC__q170 =
	      fpu_div64_fState_S4$D_OUT[1:0] == 2'b11 &&
	      fpu_div64_fState_S4$D_OUT[65];
    endcase
  end
  always@(fpu_div64_fState_S4$D_OUT or
	  IF_0b0_CONCAT_NOT_fpu_div64_fState_S4_first__4_ETC___d980)
  begin
    case (fpu_div64_fState_S4$D_OUT[1:0])
      2'b0, 2'b01:
	  CASE_fpu_div64_fState_S4D_OUT_BITS_1_TO_0_0b0_ETC__q171 =
	      fpu_div64_fState_S4$D_OUT[64:2];
      2'b10:
	  CASE_fpu_div64_fState_S4D_OUT_BITS_1_TO_0_0b0_ETC__q171 =
	      fpu_div64_fState_S4$D_OUT[2] ?
		IF_0b0_CONCAT_NOT_fpu_div64_fState_S4_first__4_ETC___d980 :
		fpu_div64_fState_S4$D_OUT[64:2];
      2'b11:
	  CASE_fpu_div64_fState_S4D_OUT_BITS_1_TO_0_0b0_ETC__q171 =
	      IF_0b0_CONCAT_NOT_fpu_div64_fState_S4_first__4_ETC___d980;
    endcase
  end
  always@(fpu_div64_fState_S4$D_OUT or
	  IF_0b0_CONCAT_NOT_fpu_div64_fState_S4_first__4_ETC___d980)
  begin
    case (fpu_div64_fState_S4$D_OUT[1:0])
      2'd0: CASE_fpu_div64_fState_S4D_OUT_BITS_1_TO_0_0_0_ETC__q172 = 63'd0;
      2'b01, 2'b10, 2'b11:
	  CASE_fpu_div64_fState_S4D_OUT_BITS_1_TO_0_0_0_ETC__q172 =
	      IF_0b0_CONCAT_NOT_fpu_div64_fState_S4_first__4_ETC___d980;
    endcase
  end
  always@(fpu_div64_fState_S4$D_OUT or
	  CASE_fpu_div64_fState_S4D_OUT_BITS_68_TO_66_2_ETC__q168 or
	  CASE_fpu_div64_fState_S4D_OUT_BITS_68_TO_66_2_ETC__q169 or
	  CASE_fpu_div64_fState_S4D_OUT_BITS_1_TO_0_0b0_ETC__q170 or
	  CASE_fpu_div64_fState_S4D_OUT_BITS_1_TO_0_0b0_ETC__q171 or
	  CASE_fpu_div64_fState_S4D_OUT_BITS_1_TO_0_0_0_ETC__q172)
  begin
    case (fpu_div64_fState_S4$D_OUT[68:66])
      3'd0:
	  CASE_fpu_div64_fState_S4D_OUT_BITS_68_TO_66_0_ETC__q173 =
	      { CASE_fpu_div64_fState_S4D_OUT_BITS_1_TO_0_0b0_ETC__q170,
		CASE_fpu_div64_fState_S4D_OUT_BITS_1_TO_0_0b0_ETC__q171 };
      3'd1:
	  CASE_fpu_div64_fState_S4D_OUT_BITS_68_TO_66_0_ETC__q173 =
	      (fpu_div64_fState_S4$D_OUT[1:0] == 2'b0) ?
		fpu_div64_fState_S4$D_OUT[65:2] :
		{ (fpu_div64_fState_S4$D_OUT[1:0] == 2'b01 ||
		   fpu_div64_fState_S4$D_OUT[1:0] == 2'b10 ||
		   fpu_div64_fState_S4$D_OUT[1:0] == 2'b11) &&
		  fpu_div64_fState_S4$D_OUT[65],
		  CASE_fpu_div64_fState_S4D_OUT_BITS_1_TO_0_0_0_ETC__q172 };
      default: CASE_fpu_div64_fState_S4D_OUT_BITS_68_TO_66_0_ETC__q173 =
		   { CASE_fpu_div64_fState_S4D_OUT_BITS_68_TO_66_2_ETC__q168,
		     CASE_fpu_div64_fState_S4D_OUT_BITS_68_TO_66_2_ETC__q169 };
    endcase
  end
  always@(fpu_div64_fState_S3$D_OUT)
  begin
    case (fpu_div64_fState_S3$D_OUT[124:122])
      3'd0, 3'd1, 3'd2, 3'd3:
	  CASE_fpu_div64_fState_S3D_OUT_BITS_124_TO_122_ETC__q174 =
	      fpu_div64_fState_S3$D_OUT[121];
      default: CASE_fpu_div64_fState_S3D_OUT_BITS_124_TO_122_ETC__q174 =
		   fpu_div64_fState_S3$D_OUT[124:122] == 3'd4 &&
		   fpu_div64_fState_S3$D_OUT[121];
    endcase
  end
  always@(fpu_div64_fState_S3$D_OUT)
  begin
    case (fpu_div64_fState_S3$D_OUT[124:122])
      3'd0, 3'd1:
	  CASE_fpu_div64_fState_S3D_OUT_BITS_124_TO_122_ETC__q175 =
	      63'h7FF0000000000000;
      3'd2:
	  CASE_fpu_div64_fState_S3D_OUT_BITS_124_TO_122_ETC__q175 =
	      fpu_div64_fState_S3$D_OUT[121] ?
		63'h7FEFFFFFFFFFFFFF :
		63'h7FF0000000000000;
      3'd3:
	  CASE_fpu_div64_fState_S3D_OUT_BITS_124_TO_122_ETC__q175 =
	      fpu_div64_fState_S3$D_OUT[121] ?
		63'h7FF0000000000000 :
		63'h7FEFFFFFFFFFFFFF;
      3'd4:
	  CASE_fpu_div64_fState_S3D_OUT_BITS_124_TO_122_ETC__q175 =
	      63'h7FEFFFFFFFFFFFFF;
      default: CASE_fpu_div64_fState_S3D_OUT_BITS_124_TO_122_ETC__q175 =
		   63'd0;
    endcase
  end
  always@(iFifo$D_OUT or
	  IF_iFifo_first__087_BIT_201_115_THEN_IF_iFifo__ETC___d3848 or
	  IF_iFifo_first__087_BIT_136_624_THEN_IF_iFifo__ETC___d5330 or
	  IF_iFifo_first__087_BITS_102_TO_95_625_EQ_255__ETC___d5378)
  begin
    case (iFifo$D_OUT[3:0])
      4'd0:
	  CASE_iFifoD_OUT_BITS_3_TO_0_0_IF_iFifo_first__ETC__q176 =
	      IF_iFifo_first__087_BIT_136_624_THEN_IF_iFifo__ETC___d5330;
      4'd1:
	  CASE_iFifoD_OUT_BITS_3_TO_0_0_IF_iFifo_first__ETC__q176 =
	      iFifo$D_OUT[136] ?
		IF_iFifo_first__087_BITS_102_TO_95_625_EQ_255__ETC___d5378 :
		{ iFifo$D_OUT[136] || !iFifo$D_OUT[135],
		  iFifo$D_OUT[134:72] };
      default: CASE_iFifoD_OUT_BITS_3_TO_0_0_IF_iFifo_first__ETC__q176 =
		   IF_iFifo_first__087_BIT_201_115_THEN_IF_iFifo__ETC___d3848;
    endcase
  end
  always@(iFifo$D_OUT or
	  IF_iFifo_first__087_BIT_136_624_THEN_IF_iFifo__ETC___d5330)
  begin
    case (iFifo$D_OUT[3:0])
      4'd0, 4'd1:
	  CASE_iFifoD_OUT_BITS_3_TO_0_0_460718241880001_ETC__q177 =
	      64'h3FF0000000000000;
      default: CASE_iFifoD_OUT_BITS_3_TO_0_0_460718241880001_ETC__q177 =
		   IF_iFifo_first__087_BIT_136_624_THEN_IF_iFifo__ETC___d5330;
    endcase
  end
  always@(fpu_sqr64_fState_S4$D_OUT)
  begin
    case (fpu_sqr64_fState_S4$D_OUT[68:66])
      3'd2, 3'd3:
	  CASE_fpu_sqr64_fState_S4D_OUT_BITS_68_TO_66_2_ETC__q178 =
	      fpu_sqr64_fState_S4$D_OUT[65];
      default: CASE_fpu_sqr64_fState_S4D_OUT_BITS_68_TO_66_2_ETC__q178 =
		   fpu_sqr64_fState_S4$D_OUT[68:66] == 3'd4 &&
		   fpu_sqr64_fState_S4$D_OUT[65];
    endcase
  end
  always@(fpu_sqr64_fState_S4$D_OUT or
	  IF_0b0_CONCAT_NOT_fpu_sqr64_fState_S4_first__6_ETC___d1724)
  begin
    case (fpu_sqr64_fState_S4$D_OUT[68:66])
      3'd2:
	  CASE_fpu_sqr64_fState_S4D_OUT_BITS_68_TO_66_2_ETC__q179 =
	      (fpu_sqr64_fState_S4$D_OUT[1:0] == 2'b0 ||
	       fpu_sqr64_fState_S4$D_OUT[65]) ?
		fpu_sqr64_fState_S4$D_OUT[64:2] :
		IF_0b0_CONCAT_NOT_fpu_sqr64_fState_S4_first__6_ETC___d1724;
      3'd3:
	  CASE_fpu_sqr64_fState_S4D_OUT_BITS_68_TO_66_2_ETC__q179 =
	      (fpu_sqr64_fState_S4$D_OUT[1:0] == 2'b0) ?
		fpu_sqr64_fState_S4$D_OUT[64:2] :
		(fpu_sqr64_fState_S4$D_OUT[65] ?
		   IF_0b0_CONCAT_NOT_fpu_sqr64_fState_S4_first__6_ETC___d1724 :
		   fpu_sqr64_fState_S4$D_OUT[64:2]);
      3'd4:
	  CASE_fpu_sqr64_fState_S4D_OUT_BITS_68_TO_66_2_ETC__q179 =
	      fpu_sqr64_fState_S4$D_OUT[64:2];
      default: CASE_fpu_sqr64_fState_S4D_OUT_BITS_68_TO_66_2_ETC__q179 =
		   63'd0;
    endcase
  end
  always@(fpu_sqr64_fState_S4$D_OUT)
  begin
    case (fpu_sqr64_fState_S4$D_OUT[1:0])
      2'b0, 2'b01, 2'b10:
	  CASE_fpu_sqr64_fState_S4D_OUT_BITS_1_TO_0_0b0_ETC__q180 =
	      fpu_sqr64_fState_S4$D_OUT[65];
      2'd3:
	  CASE_fpu_sqr64_fState_S4D_OUT_BITS_1_TO_0_0b0_ETC__q180 =
	      fpu_sqr64_fState_S4$D_OUT[1:0] == 2'b11 &&
	      fpu_sqr64_fState_S4$D_OUT[65];
    endcase
  end
  always@(fpu_sqr64_fState_S4$D_OUT or
	  IF_0b0_CONCAT_NOT_fpu_sqr64_fState_S4_first__6_ETC___d1724)
  begin
    case (fpu_sqr64_fState_S4$D_OUT[1:0])
      2'b0, 2'b01:
	  CASE_fpu_sqr64_fState_S4D_OUT_BITS_1_TO_0_0b0_ETC__q181 =
	      fpu_sqr64_fState_S4$D_OUT[64:2];
      2'b10:
	  CASE_fpu_sqr64_fState_S4D_OUT_BITS_1_TO_0_0b0_ETC__q181 =
	      fpu_sqr64_fState_S4$D_OUT[2] ?
		IF_0b0_CONCAT_NOT_fpu_sqr64_fState_S4_first__6_ETC___d1724 :
		fpu_sqr64_fState_S4$D_OUT[64:2];
      2'b11:
	  CASE_fpu_sqr64_fState_S4D_OUT_BITS_1_TO_0_0b0_ETC__q181 =
	      IF_0b0_CONCAT_NOT_fpu_sqr64_fState_S4_first__6_ETC___d1724;
    endcase
  end
  always@(fpu_sqr64_fState_S4$D_OUT or
	  IF_0b0_CONCAT_NOT_fpu_sqr64_fState_S4_first__6_ETC___d1724)
  begin
    case (fpu_sqr64_fState_S4$D_OUT[1:0])
      2'd0: CASE_fpu_sqr64_fState_S4D_OUT_BITS_1_TO_0_0_0_ETC__q182 = 63'd0;
      2'b01, 2'b10, 2'b11:
	  CASE_fpu_sqr64_fState_S4D_OUT_BITS_1_TO_0_0_0_ETC__q182 =
	      IF_0b0_CONCAT_NOT_fpu_sqr64_fState_S4_first__6_ETC___d1724;
    endcase
  end
  always@(fpu_sqr64_fState_S4$D_OUT or
	  CASE_fpu_sqr64_fState_S4D_OUT_BITS_68_TO_66_2_ETC__q178 or
	  CASE_fpu_sqr64_fState_S4D_OUT_BITS_68_TO_66_2_ETC__q179 or
	  CASE_fpu_sqr64_fState_S4D_OUT_BITS_1_TO_0_0b0_ETC__q180 or
	  CASE_fpu_sqr64_fState_S4D_OUT_BITS_1_TO_0_0b0_ETC__q181 or
	  CASE_fpu_sqr64_fState_S4D_OUT_BITS_1_TO_0_0_0_ETC__q182)
  begin
    case (fpu_sqr64_fState_S4$D_OUT[68:66])
      3'd0:
	  CASE_fpu_sqr64_fState_S4D_OUT_BITS_68_TO_66_0_ETC__q183 =
	      { CASE_fpu_sqr64_fState_S4D_OUT_BITS_1_TO_0_0b0_ETC__q180,
		CASE_fpu_sqr64_fState_S4D_OUT_BITS_1_TO_0_0b0_ETC__q181 };
      3'd1:
	  CASE_fpu_sqr64_fState_S4D_OUT_BITS_68_TO_66_0_ETC__q183 =
	      (fpu_sqr64_fState_S4$D_OUT[1:0] == 2'b0) ?
		fpu_sqr64_fState_S4$D_OUT[65:2] :
		{ (fpu_sqr64_fState_S4$D_OUT[1:0] == 2'b01 ||
		   fpu_sqr64_fState_S4$D_OUT[1:0] == 2'b10 ||
		   fpu_sqr64_fState_S4$D_OUT[1:0] == 2'b11) &&
		  fpu_sqr64_fState_S4$D_OUT[65],
		  CASE_fpu_sqr64_fState_S4D_OUT_BITS_1_TO_0_0_0_ETC__q182 };
      default: CASE_fpu_sqr64_fState_S4D_OUT_BITS_68_TO_66_0_ETC__q183 =
		   { CASE_fpu_sqr64_fState_S4D_OUT_BITS_68_TO_66_2_ETC__q178,
		     CASE_fpu_sqr64_fState_S4D_OUT_BITS_68_TO_66_2_ETC__q179 };
    endcase
  end

  // handling of inlined registers

  always@(posedge CLK)
  begin
    if (RST_N == `BSV_RESET_VALUE)
      begin
        crg_done <= `BSV_ASSIGNMENT_DELAY 1'd0;
	crg_done_1 <= `BSV_ASSIGNMENT_DELAY 1'd0;
	rg_busy <= `BSV_ASSIGNMENT_DELAY 1'd0;
	rg_busy_1 <= `BSV_ASSIGNMENT_DELAY 1'd0;
      end
    else
      begin
        if (crg_done$EN) crg_done <= `BSV_ASSIGNMENT_DELAY crg_done$D_IN;
	if (crg_done_1$EN)
	  crg_done_1 <= `BSV_ASSIGNMENT_DELAY crg_done_1$D_IN;
	if (rg_busy$EN) rg_busy <= `BSV_ASSIGNMENT_DELAY rg_busy$D_IN;
	if (rg_busy_1$EN) rg_busy_1 <= `BSV_ASSIGNMENT_DELAY rg_busy_1$D_IN;
      end
    if (rg_b$EN) rg_b <= `BSV_ASSIGNMENT_DELAY rg_b$D_IN;
    if (rg_d$EN) rg_d <= `BSV_ASSIGNMENT_DELAY rg_d$D_IN;
    if (rg_index$EN) rg_index <= `BSV_ASSIGNMENT_DELAY rg_index$D_IN;
    if (rg_index_1$EN) rg_index_1 <= `BSV_ASSIGNMENT_DELAY rg_index_1$D_IN;
    if (rg_q$EN) rg_q <= `BSV_ASSIGNMENT_DELAY rg_q$D_IN;
    if (rg_r$EN) rg_r <= `BSV_ASSIGNMENT_DELAY rg_r$D_IN;
    if (rg_r_1$EN) rg_r_1 <= `BSV_ASSIGNMENT_DELAY rg_r_1$D_IN;
    if (rg_res$EN) rg_res <= `BSV_ASSIGNMENT_DELAY rg_res$D_IN;
    if (rg_s$EN) rg_s <= `BSV_ASSIGNMENT_DELAY rg_s$D_IN;
  end

  // synopsys translate_off
  `ifdef BSV_NO_INITIAL_BLOCKS
  `else // not BSV_NO_INITIAL_BLOCKS
  initial
  begin
    crg_done = 1'h0;
    crg_done_1 = 1'h0;
    rg_b = 116'hAAAAAAAAAAAAAAAAAAAAAAAAAAAAA;
    rg_busy = 1'h0;
    rg_busy_1 = 1'h0;
    rg_d = 58'h2AAAAAAAAAAAAAA;
    rg_index = 6'h2A;
    rg_index_1 = 6'h2A;
    rg_q = 58'h2AAAAAAAAAAAAAA;
    rg_r = 116'hAAAAAAAAAAAAAAAAAAAAAAAAAAAAA;
    rg_r_1 = 116'hAAAAAAAAAAAAAAAAAAAAAAAAAAAAA;
    rg_res = 117'h0AAAAAAAAAAAAAAAAAAAAAAAAAAAAA;
    rg_s = 116'hAAAAAAAAAAAAAAAAAAAAAAAAAAAAA;
  end
  `endif // BSV_NO_INITIAL_BLOCKS
  // synopsys translate_on

  // handling of system tasks

  // synopsys translate_off
  always@(negedge CLK)
  begin
    #0;
    if (RST_N != `BSV_RESET_VALUE)
      if (fpu_div64_fResult_S5$EMPTY_N && fpu_madd_fResult_S9$EMPTY_N)
	$display("Error: \"../../src_Core/CPU/FPU.bsv\", line 109, column 29: (R0001)\n  Mutually exclusive rules (from the ME sets [RL_getResDiv] and\n  [RL_getResMAdd] ) fired in the same clock cycle.\n");
    if (RST_N != `BSV_RESET_VALUE)
      if (fpu_div64_fResult_S5$EMPTY_N && fpu_sqr64_fResult_S5$EMPTY_N)
	$display("Error: \"../../src_Core/CPU/FPU.bsv\", line 109, column 29: (R0001)\n  Mutually exclusive rules (from the ME sets [RL_getResDiv] and [RL_getResSqr]\n  ) fired in the same clock cycle.\n");
    if (RST_N != `BSV_RESET_VALUE)
      if (fpu_sqr64_fResult_S5$EMPTY_N && fpu_madd_fResult_S9$EMPTY_N)
	$display("Error: \"../../src_Core/CPU/FPU.bsv\", line 109, column 40: (R0001)\n  Mutually exclusive rules (from the ME sets [RL_getResSqr] and\n  [RL_getResMAdd] ) fired in the same clock cycle.\n");
  end
  // synopsys translate_on
endmodule  // mkFPU

