//
// Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24)
//
//
//
//
// Ports:
// Name                         I/O  size props
// RDY_hart0_server_reset_request_put  O     1 reg
// hart0_server_reset_response_get  O     1 reg
// RDY_hart0_server_reset_response_get  O     1 reg
// imem_master_awvalid            O     1 reg
// imem_master_awid               O     4 reg
// imem_master_awaddr             O    64 reg
// imem_master_awlen              O     8 reg
// imem_master_awsize             O     3 reg
// imem_master_awburst            O     2 reg
// imem_master_awlock             O     1 reg
// imem_master_awcache            O     4 reg
// imem_master_awprot             O     3 reg
// imem_master_awqos              O     4 reg
// imem_master_awregion           O     4 reg
// imem_master_wvalid             O     1 reg
// imem_master_wdata              O    64 reg
// imem_master_wstrb              O     8 reg
// imem_master_wlast              O     1 reg
// imem_master_bready             O     1 reg
// imem_master_arvalid            O     1 reg
// imem_master_arid               O     4 reg
// imem_master_araddr             O    64 reg
// imem_master_arlen              O     8 reg
// imem_master_arsize             O     3 reg
// imem_master_arburst            O     2 reg
// imem_master_arlock             O     1 reg
// imem_master_arcache            O     4 reg
// imem_master_arprot             O     3 reg
// imem_master_arqos              O     4 reg
// imem_master_arregion           O     4 reg
// imem_master_rready             O     1 reg
// dmem_master_awvalid            O     1 reg
// dmem_master_awid               O     4 reg
// dmem_master_awaddr             O    64 reg
// dmem_master_awlen              O     8 reg
// dmem_master_awsize             O     3 reg
// dmem_master_awburst            O     2 reg
// dmem_master_awlock             O     1 reg
// dmem_master_awcache            O     4 reg
// dmem_master_awprot             O     3 reg
// dmem_master_awqos              O     4 reg
// dmem_master_awregion           O     4 reg
// dmem_master_wvalid             O     1 reg
// dmem_master_wdata              O    64 reg
// dmem_master_wstrb              O     8 reg
// dmem_master_wlast              O     1 reg
// dmem_master_bready             O     1 reg
// dmem_master_arvalid            O     1 reg
// dmem_master_arid               O     4 reg
// dmem_master_araddr             O    64 reg
// dmem_master_arlen              O     8 reg
// dmem_master_arsize             O     3 reg
// dmem_master_arburst            O     2 reg
// dmem_master_arlock             O     1 reg
// dmem_master_arcache            O     4 reg
// dmem_master_arprot             O     3 reg
// dmem_master_arqos              O     4 reg
// dmem_master_arregion           O     4 reg
// dmem_master_rready             O     1 reg
// RDY_set_verbosity              O     1 const
// trace_data_out_get             O   235 reg
// RDY_trace_data_out_get         O     1 reg
// RDY_hart0_server_run_halt_request_put  O     1 reg
// hart0_server_run_halt_response_get  O     1 reg
// RDY_hart0_server_run_halt_response_get  O     1 reg
// RDY_hart0_put_other_req_put    O     1 const
// RDY_hart0_gpr_mem_server_request_put  O     1 reg
// hart0_gpr_mem_server_response_get  O    33 reg
// RDY_hart0_gpr_mem_server_response_get  O     1 reg
// RDY_hart0_csr_mem_server_request_put  O     1 reg
// hart0_csr_mem_server_response_get  O    33 reg
// RDY_hart0_csr_mem_server_response_get  O     1 reg
// CLK                            I     1 clock
// RST_N                          I     1 reset
// hart0_server_reset_request_put  I     1 reg
// imem_master_awready            I     1
// imem_master_wready             I     1
// imem_master_bvalid             I     1
// imem_master_bid                I     4 reg
// imem_master_bresp              I     2 reg
// imem_master_arready            I     1
// imem_master_rvalid             I     1
// imem_master_rid                I     4 reg
// imem_master_rdata              I    64 reg
// imem_master_rresp              I     2 reg
// imem_master_rlast              I     1 reg
// dmem_master_awready            I     1
// dmem_master_wready             I     1
// dmem_master_bvalid             I     1
// dmem_master_bid                I     4 reg
// dmem_master_bresp              I     2 reg
// dmem_master_arready            I     1
// dmem_master_rvalid             I     1
// dmem_master_rid                I     4 reg
// dmem_master_rdata              I    64 reg
// dmem_master_rresp              I     2 reg
// dmem_master_rlast              I     1 reg
// m_external_interrupt_req_set_not_clear  I     1 reg
// s_external_interrupt_req_set_not_clear  I     1 reg
// software_interrupt_req_set_not_clear  I     1 reg
// timer_interrupt_req_set_not_clear  I     1 reg
// nmi_req_set_not_clear          I     1
// set_verbosity_verbosity        I     4
// set_verbosity_logdelay         I    64 reg
// hart0_server_run_halt_request_put  I     1 reg
// hart0_put_other_req_put        I     4
// hart0_gpr_mem_server_request_put  I    38 reg
// hart0_csr_mem_server_request_put  I    45 reg
// EN_hart0_server_reset_request_put  I     1
// EN_set_verbosity               I     1
// EN_hart0_server_run_halt_request_put  I     1
// EN_hart0_put_other_req_put     I     1
// EN_hart0_gpr_mem_server_request_put  I     1
// EN_hart0_csr_mem_server_request_put  I     1
// EN_hart0_server_reset_response_get  I     1
// EN_trace_data_out_get          I     1
// EN_hart0_server_run_halt_response_get  I     1
// EN_hart0_gpr_mem_server_response_get  I     1
// EN_hart0_csr_mem_server_response_get  I     1
//
// No combinational paths from inputs to outputs
//
//

`ifdef BSV_ASSIGNMENT_DELAY
`else
  `define BSV_ASSIGNMENT_DELAY
`endif

`ifdef BSV_POSITIVE_RESET
  `define BSV_RESET_VALUE 1'b1
  `define BSV_RESET_EDGE posedge
`else
  `define BSV_RESET_VALUE 1'b0
  `define BSV_RESET_EDGE negedge
`endif

module mkCPU(CLK,
	     RST_N,

	     hart0_server_reset_request_put,
	     EN_hart0_server_reset_request_put,
	     RDY_hart0_server_reset_request_put,

	     EN_hart0_server_reset_response_get,
	     hart0_server_reset_response_get,
	     RDY_hart0_server_reset_response_get,

	     imem_master_awvalid,

	     imem_master_awid,

	     imem_master_awaddr,

	     imem_master_awlen,

	     imem_master_awsize,

	     imem_master_awburst,

	     imem_master_awlock,

	     imem_master_awcache,

	     imem_master_awprot,

	     imem_master_awqos,

	     imem_master_awregion,

	     imem_master_awready,

	     imem_master_wvalid,

	     imem_master_wdata,

	     imem_master_wstrb,

	     imem_master_wlast,

	     imem_master_wready,

	     imem_master_bvalid,
	     imem_master_bid,
	     imem_master_bresp,

	     imem_master_bready,

	     imem_master_arvalid,

	     imem_master_arid,

	     imem_master_araddr,

	     imem_master_arlen,

	     imem_master_arsize,

	     imem_master_arburst,

	     imem_master_arlock,

	     imem_master_arcache,

	     imem_master_arprot,

	     imem_master_arqos,

	     imem_master_arregion,

	     imem_master_arready,

	     imem_master_rvalid,
	     imem_master_rid,
	     imem_master_rdata,
	     imem_master_rresp,
	     imem_master_rlast,

	     imem_master_rready,

	     dmem_master_awvalid,

	     dmem_master_awid,

	     dmem_master_awaddr,

	     dmem_master_awlen,

	     dmem_master_awsize,

	     dmem_master_awburst,

	     dmem_master_awlock,

	     dmem_master_awcache,

	     dmem_master_awprot,

	     dmem_master_awqos,

	     dmem_master_awregion,

	     dmem_master_awready,

	     dmem_master_wvalid,

	     dmem_master_wdata,

	     dmem_master_wstrb,

	     dmem_master_wlast,

	     dmem_master_wready,

	     dmem_master_bvalid,
	     dmem_master_bid,
	     dmem_master_bresp,

	     dmem_master_bready,

	     dmem_master_arvalid,

	     dmem_master_arid,

	     dmem_master_araddr,

	     dmem_master_arlen,

	     dmem_master_arsize,

	     dmem_master_arburst,

	     dmem_master_arlock,

	     dmem_master_arcache,

	     dmem_master_arprot,

	     dmem_master_arqos,

	     dmem_master_arregion,

	     dmem_master_arready,

	     dmem_master_rvalid,
	     dmem_master_rid,
	     dmem_master_rdata,
	     dmem_master_rresp,
	     dmem_master_rlast,

	     dmem_master_rready,

	     m_external_interrupt_req_set_not_clear,

	     s_external_interrupt_req_set_not_clear,

	     software_interrupt_req_set_not_clear,

	     timer_interrupt_req_set_not_clear,

	     nmi_req_set_not_clear,

	     set_verbosity_verbosity,
	     set_verbosity_logdelay,
	     EN_set_verbosity,
	     RDY_set_verbosity,

	     EN_trace_data_out_get,
	     trace_data_out_get,
	     RDY_trace_data_out_get,

	     hart0_server_run_halt_request_put,
	     EN_hart0_server_run_halt_request_put,
	     RDY_hart0_server_run_halt_request_put,

	     EN_hart0_server_run_halt_response_get,
	     hart0_server_run_halt_response_get,
	     RDY_hart0_server_run_halt_response_get,

	     hart0_put_other_req_put,
	     EN_hart0_put_other_req_put,
	     RDY_hart0_put_other_req_put,

	     hart0_gpr_mem_server_request_put,
	     EN_hart0_gpr_mem_server_request_put,
	     RDY_hart0_gpr_mem_server_request_put,

	     EN_hart0_gpr_mem_server_response_get,
	     hart0_gpr_mem_server_response_get,
	     RDY_hart0_gpr_mem_server_response_get,

	     hart0_csr_mem_server_request_put,
	     EN_hart0_csr_mem_server_request_put,
	     RDY_hart0_csr_mem_server_request_put,

	     EN_hart0_csr_mem_server_response_get,
	     hart0_csr_mem_server_response_get,
	     RDY_hart0_csr_mem_server_response_get);
  input  CLK;
  input  RST_N;

  // action method hart0_server_reset_request_put
  input  hart0_server_reset_request_put;
  input  EN_hart0_server_reset_request_put;
  output RDY_hart0_server_reset_request_put;

  // actionvalue method hart0_server_reset_response_get
  input  EN_hart0_server_reset_response_get;
  output hart0_server_reset_response_get;
  output RDY_hart0_server_reset_response_get;

  // value method imem_master_m_awvalid
  output imem_master_awvalid;

  // value method imem_master_m_awid
  output [3 : 0] imem_master_awid;

  // value method imem_master_m_awaddr
  output [63 : 0] imem_master_awaddr;

  // value method imem_master_m_awlen
  output [7 : 0] imem_master_awlen;

  // value method imem_master_m_awsize
  output [2 : 0] imem_master_awsize;

  // value method imem_master_m_awburst
  output [1 : 0] imem_master_awburst;

  // value method imem_master_m_awlock
  output imem_master_awlock;

  // value method imem_master_m_awcache
  output [3 : 0] imem_master_awcache;

  // value method imem_master_m_awprot
  output [2 : 0] imem_master_awprot;

  // value method imem_master_m_awqos
  output [3 : 0] imem_master_awqos;

  // value method imem_master_m_awregion
  output [3 : 0] imem_master_awregion;

  // value method imem_master_m_awuser

  // action method imem_master_m_awready
  input  imem_master_awready;

  // value method imem_master_m_wvalid
  output imem_master_wvalid;

  // value method imem_master_m_wdata
  output [63 : 0] imem_master_wdata;

  // value method imem_master_m_wstrb
  output [7 : 0] imem_master_wstrb;

  // value method imem_master_m_wlast
  output imem_master_wlast;

  // value method imem_master_m_wuser

  // action method imem_master_m_wready
  input  imem_master_wready;

  // action method imem_master_m_bvalid
  input  imem_master_bvalid;
  input  [3 : 0] imem_master_bid;
  input  [1 : 0] imem_master_bresp;

  // value method imem_master_m_bready
  output imem_master_bready;

  // value method imem_master_m_arvalid
  output imem_master_arvalid;

  // value method imem_master_m_arid
  output [3 : 0] imem_master_arid;

  // value method imem_master_m_araddr
  output [63 : 0] imem_master_araddr;

  // value method imem_master_m_arlen
  output [7 : 0] imem_master_arlen;

  // value method imem_master_m_arsize
  output [2 : 0] imem_master_arsize;

  // value method imem_master_m_arburst
  output [1 : 0] imem_master_arburst;

  // value method imem_master_m_arlock
  output imem_master_arlock;

  // value method imem_master_m_arcache
  output [3 : 0] imem_master_arcache;

  // value method imem_master_m_arprot
  output [2 : 0] imem_master_arprot;

  // value method imem_master_m_arqos
  output [3 : 0] imem_master_arqos;

  // value method imem_master_m_arregion
  output [3 : 0] imem_master_arregion;

  // value method imem_master_m_aruser

  // action method imem_master_m_arready
  input  imem_master_arready;

  // action method imem_master_m_rvalid
  input  imem_master_rvalid;
  input  [3 : 0] imem_master_rid;
  input  [63 : 0] imem_master_rdata;
  input  [1 : 0] imem_master_rresp;
  input  imem_master_rlast;

  // value method imem_master_m_rready
  output imem_master_rready;

  // value method dmem_master_m_awvalid
  output dmem_master_awvalid;

  // value method dmem_master_m_awid
  output [3 : 0] dmem_master_awid;

  // value method dmem_master_m_awaddr
  output [63 : 0] dmem_master_awaddr;

  // value method dmem_master_m_awlen
  output [7 : 0] dmem_master_awlen;

  // value method dmem_master_m_awsize
  output [2 : 0] dmem_master_awsize;

  // value method dmem_master_m_awburst
  output [1 : 0] dmem_master_awburst;

  // value method dmem_master_m_awlock
  output dmem_master_awlock;

  // value method dmem_master_m_awcache
  output [3 : 0] dmem_master_awcache;

  // value method dmem_master_m_awprot
  output [2 : 0] dmem_master_awprot;

  // value method dmem_master_m_awqos
  output [3 : 0] dmem_master_awqos;

  // value method dmem_master_m_awregion
  output [3 : 0] dmem_master_awregion;

  // value method dmem_master_m_awuser

  // action method dmem_master_m_awready
  input  dmem_master_awready;

  // value method dmem_master_m_wvalid
  output dmem_master_wvalid;

  // value method dmem_master_m_wdata
  output [63 : 0] dmem_master_wdata;

  // value method dmem_master_m_wstrb
  output [7 : 0] dmem_master_wstrb;

  // value method dmem_master_m_wlast
  output dmem_master_wlast;

  // value method dmem_master_m_wuser

  // action method dmem_master_m_wready
  input  dmem_master_wready;

  // action method dmem_master_m_bvalid
  input  dmem_master_bvalid;
  input  [3 : 0] dmem_master_bid;
  input  [1 : 0] dmem_master_bresp;

  // value method dmem_master_m_bready
  output dmem_master_bready;

  // value method dmem_master_m_arvalid
  output dmem_master_arvalid;

  // value method dmem_master_m_arid
  output [3 : 0] dmem_master_arid;

  // value method dmem_master_m_araddr
  output [63 : 0] dmem_master_araddr;

  // value method dmem_master_m_arlen
  output [7 : 0] dmem_master_arlen;

  // value method dmem_master_m_arsize
  output [2 : 0] dmem_master_arsize;

  // value method dmem_master_m_arburst
  output [1 : 0] dmem_master_arburst;

  // value method dmem_master_m_arlock
  output dmem_master_arlock;

  // value method dmem_master_m_arcache
  output [3 : 0] dmem_master_arcache;

  // value method dmem_master_m_arprot
  output [2 : 0] dmem_master_arprot;

  // value method dmem_master_m_arqos
  output [3 : 0] dmem_master_arqos;

  // value method dmem_master_m_arregion
  output [3 : 0] dmem_master_arregion;

  // value method dmem_master_m_aruser

  // action method dmem_master_m_arready
  input  dmem_master_arready;

  // action method dmem_master_m_rvalid
  input  dmem_master_rvalid;
  input  [3 : 0] dmem_master_rid;
  input  [63 : 0] dmem_master_rdata;
  input  [1 : 0] dmem_master_rresp;
  input  dmem_master_rlast;

  // value method dmem_master_m_rready
  output dmem_master_rready;

  // action method m_external_interrupt_req
  input  m_external_interrupt_req_set_not_clear;

  // action method s_external_interrupt_req
  input  s_external_interrupt_req_set_not_clear;

  // action method software_interrupt_req
  input  software_interrupt_req_set_not_clear;

  // action method timer_interrupt_req
  input  timer_interrupt_req_set_not_clear;

  // action method nmi_req
  input  nmi_req_set_not_clear;

  // action method set_verbosity
  input  [3 : 0] set_verbosity_verbosity;
  input  [63 : 0] set_verbosity_logdelay;
  input  EN_set_verbosity;
  output RDY_set_verbosity;

  // actionvalue method trace_data_out_get
  input  EN_trace_data_out_get;
  output [234 : 0] trace_data_out_get;
  output RDY_trace_data_out_get;

  // action method hart0_server_run_halt_request_put
  input  hart0_server_run_halt_request_put;
  input  EN_hart0_server_run_halt_request_put;
  output RDY_hart0_server_run_halt_request_put;

  // actionvalue method hart0_server_run_halt_response_get
  input  EN_hart0_server_run_halt_response_get;
  output hart0_server_run_halt_response_get;
  output RDY_hart0_server_run_halt_response_get;

  // action method hart0_put_other_req_put
  input  [3 : 0] hart0_put_other_req_put;
  input  EN_hart0_put_other_req_put;
  output RDY_hart0_put_other_req_put;

  // action method hart0_gpr_mem_server_request_put
  input  [37 : 0] hart0_gpr_mem_server_request_put;
  input  EN_hart0_gpr_mem_server_request_put;
  output RDY_hart0_gpr_mem_server_request_put;

  // actionvalue method hart0_gpr_mem_server_response_get
  input  EN_hart0_gpr_mem_server_response_get;
  output [32 : 0] hart0_gpr_mem_server_response_get;
  output RDY_hart0_gpr_mem_server_response_get;

  // action method hart0_csr_mem_server_request_put
  input  [44 : 0] hart0_csr_mem_server_request_put;
  input  EN_hart0_csr_mem_server_request_put;
  output RDY_hart0_csr_mem_server_request_put;

  // actionvalue method hart0_csr_mem_server_response_get
  input  EN_hart0_csr_mem_server_response_get;
  output [32 : 0] hart0_csr_mem_server_response_get;
  output RDY_hart0_csr_mem_server_response_get;

  // signals for module outputs
  wire [234 : 0] trace_data_out_get;
  wire [63 : 0] dmem_master_araddr,
		dmem_master_awaddr,
		dmem_master_wdata,
		imem_master_araddr,
		imem_master_awaddr,
		imem_master_wdata;
  wire [32 : 0] hart0_csr_mem_server_response_get,
		hart0_gpr_mem_server_response_get;
  wire [7 : 0] dmem_master_arlen,
	       dmem_master_awlen,
	       dmem_master_wstrb,
	       imem_master_arlen,
	       imem_master_awlen,
	       imem_master_wstrb;
  wire [3 : 0] dmem_master_arcache,
	       dmem_master_arid,
	       dmem_master_arqos,
	       dmem_master_arregion,
	       dmem_master_awcache,
	       dmem_master_awid,
	       dmem_master_awqos,
	       dmem_master_awregion,
	       imem_master_arcache,
	       imem_master_arid,
	       imem_master_arqos,
	       imem_master_arregion,
	       imem_master_awcache,
	       imem_master_awid,
	       imem_master_awqos,
	       imem_master_awregion;
  wire [2 : 0] dmem_master_arprot,
	       dmem_master_arsize,
	       dmem_master_awprot,
	       dmem_master_awsize,
	       imem_master_arprot,
	       imem_master_arsize,
	       imem_master_awprot,
	       imem_master_awsize;
  wire [1 : 0] dmem_master_arburst,
	       dmem_master_awburst,
	       imem_master_arburst,
	       imem_master_awburst;
  wire RDY_hart0_csr_mem_server_request_put,
       RDY_hart0_csr_mem_server_response_get,
       RDY_hart0_gpr_mem_server_request_put,
       RDY_hart0_gpr_mem_server_response_get,
       RDY_hart0_put_other_req_put,
       RDY_hart0_server_reset_request_put,
       RDY_hart0_server_reset_response_get,
       RDY_hart0_server_run_halt_request_put,
       RDY_hart0_server_run_halt_response_get,
       RDY_set_verbosity,
       RDY_trace_data_out_get,
       dmem_master_arlock,
       dmem_master_arvalid,
       dmem_master_awlock,
       dmem_master_awvalid,
       dmem_master_bready,
       dmem_master_rready,
       dmem_master_wlast,
       dmem_master_wvalid,
       hart0_server_reset_response_get,
       hart0_server_run_halt_response_get,
       imem_master_arlock,
       imem_master_arvalid,
       imem_master_awlock,
       imem_master_awvalid,
       imem_master_bready,
       imem_master_rready,
       imem_master_wlast,
       imem_master_wvalid;

  // register cfg_logdelay
  reg [63 : 0] cfg_logdelay;
  wire [63 : 0] cfg_logdelay$D_IN;
  wire cfg_logdelay$EN;

  // register cfg_verbosity
  reg [3 : 0] cfg_verbosity;
  wire [3 : 0] cfg_verbosity$D_IN;
  wire cfg_verbosity$EN;

  // register imem_rg_cache_addr
  reg [31 : 0] imem_rg_cache_addr;
  wire [31 : 0] imem_rg_cache_addr$D_IN;
  wire imem_rg_cache_addr$EN;

  // register imem_rg_cache_b16
  reg [15 : 0] imem_rg_cache_b16;
  wire [15 : 0] imem_rg_cache_b16$D_IN;
  wire imem_rg_cache_b16$EN;

  // register imem_rg_f3
  reg [2 : 0] imem_rg_f3;
  wire [2 : 0] imem_rg_f3$D_IN;
  wire imem_rg_f3$EN;

  // register imem_rg_mstatus_MXR
  reg imem_rg_mstatus_MXR;
  wire imem_rg_mstatus_MXR$D_IN, imem_rg_mstatus_MXR$EN;

  // register imem_rg_pc
  reg [31 : 0] imem_rg_pc;
  reg [31 : 0] imem_rg_pc$D_IN;
  wire imem_rg_pc$EN;

  // register imem_rg_priv
  reg [1 : 0] imem_rg_priv;
  wire [1 : 0] imem_rg_priv$D_IN;
  wire imem_rg_priv$EN;

  // register imem_rg_satp
  reg [31 : 0] imem_rg_satp;
  wire [31 : 0] imem_rg_satp$D_IN;
  wire imem_rg_satp$EN;

  // register imem_rg_sstatus_SUM
  reg imem_rg_sstatus_SUM;
  wire imem_rg_sstatus_SUM$D_IN, imem_rg_sstatus_SUM$EN;

  // register imem_rg_tval
  reg [31 : 0] imem_rg_tval;
  reg [31 : 0] imem_rg_tval$D_IN;
  wire imem_rg_tval$EN;

  // register rg_csr_pc
  reg [31 : 0] rg_csr_pc;
  wire [31 : 0] rg_csr_pc$D_IN;
  wire rg_csr_pc$EN;

  // register rg_csr_val1
  reg [31 : 0] rg_csr_val1;
  wire [31 : 0] rg_csr_val1$D_IN;
  wire rg_csr_val1$EN;

  // register rg_cur_priv
  reg [1 : 0] rg_cur_priv;
  reg [1 : 0] rg_cur_priv$D_IN;
  wire rg_cur_priv$EN;

  // register rg_mstatus_MXR
  reg rg_mstatus_MXR;
  wire rg_mstatus_MXR$D_IN, rg_mstatus_MXR$EN;

  // register rg_next_pc
  reg [31 : 0] rg_next_pc;
  reg [31 : 0] rg_next_pc$D_IN;
  wire rg_next_pc$EN;

  // register rg_prev_mip
  reg [31 : 0] rg_prev_mip;
  wire [31 : 0] rg_prev_mip$D_IN;
  wire rg_prev_mip$EN;

  // register rg_run_on_reset
  reg rg_run_on_reset;
  wire rg_run_on_reset$D_IN, rg_run_on_reset$EN;

  // register rg_sstatus_SUM
  reg rg_sstatus_SUM;
  wire rg_sstatus_SUM$D_IN, rg_sstatus_SUM$EN;

  // register rg_start_CPI_cycles
  reg [63 : 0] rg_start_CPI_cycles;
  wire [63 : 0] rg_start_CPI_cycles$D_IN;
  wire rg_start_CPI_cycles$EN;

  // register rg_start_CPI_instrs
  reg [63 : 0] rg_start_CPI_instrs;
  wire [63 : 0] rg_start_CPI_instrs$D_IN;
  wire rg_start_CPI_instrs$EN;

  // register rg_state
  reg [3 : 0] rg_state;
  reg [3 : 0] rg_state$D_IN;
  wire rg_state$EN;

  // register rg_step_count
  reg rg_step_count;
  wire rg_step_count$D_IN, rg_step_count$EN;

  // register rg_stop_req
  reg rg_stop_req;
  wire rg_stop_req$D_IN, rg_stop_req$EN;

  // register rg_trap_info
  reg [67 : 0] rg_trap_info;
  reg [67 : 0] rg_trap_info$D_IN;
  wire rg_trap_info$EN;

  // register rg_trap_instr
  reg [31 : 0] rg_trap_instr;
  wire [31 : 0] rg_trap_instr$D_IN;
  wire rg_trap_instr$EN;

  // register rg_trap_interrupt
  reg rg_trap_interrupt;
  wire rg_trap_interrupt$D_IN, rg_trap_interrupt$EN;

  // register rg_trap_trace_data
  reg [234 : 0] rg_trap_trace_data;
  wire [234 : 0] rg_trap_trace_data$D_IN;
  wire rg_trap_trace_data$EN;

  // register stage1_rg_full
  reg stage1_rg_full;
  reg stage1_rg_full$D_IN;
  wire stage1_rg_full$EN;

  // register stage2_rg_full
  reg stage2_rg_full;
  reg stage2_rg_full$D_IN;
  wire stage2_rg_full$EN;

  // register stage2_rg_resetting
  reg stage2_rg_resetting;
  wire stage2_rg_resetting$D_IN, stage2_rg_resetting$EN;

  // register stage2_rg_stage2
  reg [404 : 0] stage2_rg_stage2;
  wire [404 : 0] stage2_rg_stage2$D_IN;
  wire stage2_rg_stage2$EN;

  // register stage3_rg_full
  reg stage3_rg_full;
  reg stage3_rg_full$D_IN;
  wire stage3_rg_full$EN;

  // register stage3_rg_stage3
  reg [103 : 0] stage3_rg_stage3;
  wire [103 : 0] stage3_rg_stage3$D_IN;
  wire stage3_rg_stage3$EN;

  // ports of submodule csr_regfile
  reg [31 : 0] csr_regfile$mav_csr_write_word;
  reg [2 : 0] csr_regfile$write_dcsr_cause_priv_cause;
  reg [1 : 0] csr_regfile$csr_ret_actions_from_priv;
  wire [97 : 0] csr_regfile$csr_trap_actions;
  wire [65 : 0] csr_regfile$csr_ret_actions;
  wire [63 : 0] csr_regfile$read_csr_mcycle, csr_regfile$read_csr_minstret;
  wire [32 : 0] csr_regfile$read_csr, csr_regfile$read_csr_port2;
  wire [31 : 0] csr_regfile$csr_mip_read,
		csr_regfile$csr_trap_actions_pc,
		csr_regfile$csr_trap_actions_xtval,
		csr_regfile$mav_csr_write,
		csr_regfile$read_dpc,
		csr_regfile$read_mstatus,
		csr_regfile$read_satp,
		csr_regfile$write_dpc_pc;
  wire [27 : 0] csr_regfile$read_misa;
  wire [11 : 0] csr_regfile$access_permitted_1_csr_addr,
		csr_regfile$access_permitted_2_csr_addr,
		csr_regfile$csr_counter_read_fault_csr_addr,
		csr_regfile$mav_csr_write_csr_addr,
		csr_regfile$mav_read_csr_csr_addr,
		csr_regfile$read_csr_csr_addr,
		csr_regfile$read_csr_port2_csr_addr;
  wire [4 : 0] csr_regfile$interrupt_pending;
  wire [3 : 0] csr_regfile$csr_trap_actions_exc_code;
  wire [1 : 0] csr_regfile$access_permitted_1_priv,
	       csr_regfile$access_permitted_2_priv,
	       csr_regfile$csr_counter_read_fault_priv,
	       csr_regfile$csr_trap_actions_from_priv,
	       csr_regfile$dcsr_break_enters_debug_cur_priv,
	       csr_regfile$interrupt_pending_cur_priv,
	       csr_regfile$write_dcsr_cause_priv_priv;
  wire csr_regfile$EN_csr_minstret_incr,
       csr_regfile$EN_csr_ret_actions,
       csr_regfile$EN_csr_trap_actions,
       csr_regfile$EN_debug,
       csr_regfile$EN_mav_csr_write,
       csr_regfile$EN_mav_read_csr,
       csr_regfile$EN_server_reset_request_put,
       csr_regfile$EN_server_reset_response_get,
       csr_regfile$EN_write_dcsr_cause_priv,
       csr_regfile$EN_write_dpc,
       csr_regfile$RDY_server_reset_request_put,
       csr_regfile$RDY_server_reset_response_get,
       csr_regfile$access_permitted_1,
       csr_regfile$access_permitted_1_read_not_write,
       csr_regfile$access_permitted_2,
       csr_regfile$access_permitted_2_read_not_write,
       csr_regfile$csr_trap_actions_interrupt,
       csr_regfile$csr_trap_actions_nmi,
       csr_regfile$dcsr_break_enters_debug,
       csr_regfile$m_external_interrupt_req_set_not_clear,
       csr_regfile$nmi_pending,
       csr_regfile$nmi_req_set_not_clear,
       csr_regfile$read_dcsr_step,
       csr_regfile$s_external_interrupt_req_set_not_clear,
       csr_regfile$software_interrupt_req_set_not_clear,
       csr_regfile$timer_interrupt_req_set_not_clear,
       csr_regfile$wfi_resume;

  // ports of submodule f_csr_reqs
  wire [44 : 0] f_csr_reqs$D_IN, f_csr_reqs$D_OUT;
  wire f_csr_reqs$CLR,
       f_csr_reqs$DEQ,
       f_csr_reqs$EMPTY_N,
       f_csr_reqs$ENQ,
       f_csr_reqs$FULL_N;

  // ports of submodule f_csr_rsps
  reg [32 : 0] f_csr_rsps$D_IN;
  wire [32 : 0] f_csr_rsps$D_OUT;
  wire f_csr_rsps$CLR,
       f_csr_rsps$DEQ,
       f_csr_rsps$EMPTY_N,
       f_csr_rsps$ENQ,
       f_csr_rsps$FULL_N;

  // ports of submodule f_gpr_reqs
  wire [37 : 0] f_gpr_reqs$D_IN, f_gpr_reqs$D_OUT;
  wire f_gpr_reqs$CLR,
       f_gpr_reqs$DEQ,
       f_gpr_reqs$EMPTY_N,
       f_gpr_reqs$ENQ,
       f_gpr_reqs$FULL_N;

  // ports of submodule f_gpr_rsps
  reg [32 : 0] f_gpr_rsps$D_IN;
  wire [32 : 0] f_gpr_rsps$D_OUT;
  wire f_gpr_rsps$CLR,
       f_gpr_rsps$DEQ,
       f_gpr_rsps$EMPTY_N,
       f_gpr_rsps$ENQ,
       f_gpr_rsps$FULL_N;

  // ports of submodule f_reset_reqs
  wire f_reset_reqs$CLR,
       f_reset_reqs$DEQ,
       f_reset_reqs$D_IN,
       f_reset_reqs$D_OUT,
       f_reset_reqs$EMPTY_N,
       f_reset_reqs$ENQ,
       f_reset_reqs$FULL_N;

  // ports of submodule f_reset_rsps
  wire f_reset_rsps$CLR,
       f_reset_rsps$DEQ,
       f_reset_rsps$D_IN,
       f_reset_rsps$D_OUT,
       f_reset_rsps$EMPTY_N,
       f_reset_rsps$ENQ,
       f_reset_rsps$FULL_N;

  // ports of submodule f_run_halt_reqs
  wire f_run_halt_reqs$CLR,
       f_run_halt_reqs$DEQ,
       f_run_halt_reqs$D_IN,
       f_run_halt_reqs$D_OUT,
       f_run_halt_reqs$EMPTY_N,
       f_run_halt_reqs$ENQ,
       f_run_halt_reqs$FULL_N;

  // ports of submodule f_run_halt_rsps
  wire f_run_halt_rsps$CLR,
       f_run_halt_rsps$DEQ,
       f_run_halt_rsps$D_IN,
       f_run_halt_rsps$D_OUT,
       f_run_halt_rsps$EMPTY_N,
       f_run_halt_rsps$ENQ,
       f_run_halt_rsps$FULL_N;

  // ports of submodule f_trace_data
  reg [234 : 0] f_trace_data$D_IN;
  wire [234 : 0] f_trace_data$D_OUT;
  wire f_trace_data$CLR,
       f_trace_data$DEQ,
       f_trace_data$EMPTY_N,
       f_trace_data$ENQ,
       f_trace_data$FULL_N;

  // ports of submodule gpr_regfile
  reg [31 : 0] gpr_regfile$write_rd_rd_val;
  reg [4 : 0] gpr_regfile$write_rd_rd;
  wire [31 : 0] gpr_regfile$read_rs1,
		gpr_regfile$read_rs1_port2,
		gpr_regfile$read_rs2;
  wire [4 : 0] gpr_regfile$read_rs1_port2_rs1,
	       gpr_regfile$read_rs1_rs1,
	       gpr_regfile$read_rs2_rs2;
  wire gpr_regfile$EN_server_reset_request_put,
       gpr_regfile$EN_server_reset_response_get,
       gpr_regfile$EN_write_rd,
       gpr_regfile$RDY_server_reset_request_put,
       gpr_regfile$RDY_server_reset_response_get;

  // ports of submodule near_mem
  reg [31 : 0] near_mem$imem_req_addr;
  reg [1 : 0] near_mem$dmem_req_op;
  reg near_mem$imem_req_mstatus_MXR, near_mem$imem_req_sstatus_SUM;
  wire [63 : 0] near_mem$dmem_master_araddr,
		near_mem$dmem_master_awaddr,
		near_mem$dmem_master_rdata,
		near_mem$dmem_master_wdata,
		near_mem$dmem_req_store_value,
		near_mem$dmem_word64,
		near_mem$imem_master_araddr,
		near_mem$imem_master_awaddr,
		near_mem$imem_master_rdata,
		near_mem$imem_master_wdata;
  wire [31 : 0] near_mem$dmem_req_addr,
		near_mem$dmem_req_satp,
		near_mem$imem_instr,
		near_mem$imem_pc,
		near_mem$imem_req_satp;
  wire [7 : 0] near_mem$dmem_master_arlen,
	       near_mem$dmem_master_awlen,
	       near_mem$dmem_master_wstrb,
	       near_mem$imem_master_arlen,
	       near_mem$imem_master_awlen,
	       near_mem$imem_master_wstrb,
	       near_mem$server_fence_request_put;
  wire [6 : 0] near_mem$dmem_req_amo_funct7;
  wire [3 : 0] near_mem$dmem_exc_code,
	       near_mem$dmem_master_arcache,
	       near_mem$dmem_master_arid,
	       near_mem$dmem_master_arqos,
	       near_mem$dmem_master_arregion,
	       near_mem$dmem_master_awcache,
	       near_mem$dmem_master_awid,
	       near_mem$dmem_master_awqos,
	       near_mem$dmem_master_awregion,
	       near_mem$dmem_master_bid,
	       near_mem$dmem_master_rid,
	       near_mem$imem_exc_code,
	       near_mem$imem_master_arcache,
	       near_mem$imem_master_arid,
	       near_mem$imem_master_arqos,
	       near_mem$imem_master_arregion,
	       near_mem$imem_master_awcache,
	       near_mem$imem_master_awid,
	       near_mem$imem_master_awqos,
	       near_mem$imem_master_awregion,
	       near_mem$imem_master_bid,
	       near_mem$imem_master_rid;
  wire [2 : 0] near_mem$dmem_master_arprot,
	       near_mem$dmem_master_arsize,
	       near_mem$dmem_master_awprot,
	       near_mem$dmem_master_awsize,
	       near_mem$dmem_req_f3,
	       near_mem$imem_master_arprot,
	       near_mem$imem_master_arsize,
	       near_mem$imem_master_awprot,
	       near_mem$imem_master_awsize,
	       near_mem$imem_req_f3;
  wire [1 : 0] near_mem$dmem_master_arburst,
	       near_mem$dmem_master_awburst,
	       near_mem$dmem_master_bresp,
	       near_mem$dmem_master_rresp,
	       near_mem$dmem_req_priv,
	       near_mem$imem_master_arburst,
	       near_mem$imem_master_awburst,
	       near_mem$imem_master_bresp,
	       near_mem$imem_master_rresp,
	       near_mem$imem_req_priv;
  wire near_mem$EN_dmem_req,
       near_mem$EN_imem_req,
       near_mem$EN_server_fence_i_request_put,
       near_mem$EN_server_fence_i_response_get,
       near_mem$EN_server_fence_request_put,
       near_mem$EN_server_fence_response_get,
       near_mem$EN_server_reset_request_put,
       near_mem$EN_server_reset_response_get,
       near_mem$EN_sfence_vma,
       near_mem$RDY_server_fence_i_request_put,
       near_mem$RDY_server_fence_i_response_get,
       near_mem$RDY_server_fence_request_put,
       near_mem$RDY_server_fence_response_get,
       near_mem$RDY_server_reset_request_put,
       near_mem$RDY_server_reset_response_get,
       near_mem$dmem_exc,
       near_mem$dmem_master_arlock,
       near_mem$dmem_master_arready,
       near_mem$dmem_master_arvalid,
       near_mem$dmem_master_awlock,
       near_mem$dmem_master_awready,
       near_mem$dmem_master_awvalid,
       near_mem$dmem_master_bready,
       near_mem$dmem_master_bvalid,
       near_mem$dmem_master_rlast,
       near_mem$dmem_master_rready,
       near_mem$dmem_master_rvalid,
       near_mem$dmem_master_wlast,
       near_mem$dmem_master_wready,
       near_mem$dmem_master_wvalid,
       near_mem$dmem_req_mstatus_MXR,
       near_mem$dmem_req_sstatus_SUM,
       near_mem$dmem_valid,
       near_mem$imem_exc,
       near_mem$imem_is_i32_not_i16,
       near_mem$imem_master_arlock,
       near_mem$imem_master_arready,
       near_mem$imem_master_arvalid,
       near_mem$imem_master_awlock,
       near_mem$imem_master_awready,
       near_mem$imem_master_awvalid,
       near_mem$imem_master_bready,
       near_mem$imem_master_bvalid,
       near_mem$imem_master_rlast,
       near_mem$imem_master_rready,
       near_mem$imem_master_rvalid,
       near_mem$imem_master_wlast,
       near_mem$imem_master_wready,
       near_mem$imem_master_wvalid,
       near_mem$imem_valid;

  // ports of submodule soc_map
  wire [63 : 0] soc_map$m_is_IO_addr_addr,
		soc_map$m_is_mem_addr_addr,
		soc_map$m_is_near_mem_IO_addr_addr,
		soc_map$m_pc_reset_value;

  // ports of submodule stage1_f_reset_reqs
  wire stage1_f_reset_reqs$CLR,
       stage1_f_reset_reqs$DEQ,
       stage1_f_reset_reqs$EMPTY_N,
       stage1_f_reset_reqs$ENQ,
       stage1_f_reset_reqs$FULL_N;

  // ports of submodule stage1_f_reset_rsps
  wire stage1_f_reset_rsps$CLR,
       stage1_f_reset_rsps$DEQ,
       stage1_f_reset_rsps$EMPTY_N,
       stage1_f_reset_rsps$ENQ,
       stage1_f_reset_rsps$FULL_N;

  // ports of submodule stage2_f_reset_reqs
  wire stage2_f_reset_reqs$CLR,
       stage2_f_reset_reqs$DEQ,
       stage2_f_reset_reqs$EMPTY_N,
       stage2_f_reset_reqs$ENQ,
       stage2_f_reset_reqs$FULL_N;

  // ports of submodule stage2_f_reset_rsps
  wire stage2_f_reset_rsps$CLR,
       stage2_f_reset_rsps$DEQ,
       stage2_f_reset_rsps$EMPTY_N,
       stage2_f_reset_rsps$ENQ,
       stage2_f_reset_rsps$FULL_N;

  // ports of submodule stage2_mbox
  wire [31 : 0] stage2_mbox$req_v1, stage2_mbox$req_v2, stage2_mbox$word;
  wire [3 : 0] stage2_mbox$set_verbosity_verbosity;
  wire [2 : 0] stage2_mbox$req_f3;
  wire stage2_mbox$EN_req,
       stage2_mbox$EN_req_reset,
       stage2_mbox$EN_rsp_reset,
       stage2_mbox$EN_set_verbosity,
       stage2_mbox$req_is_OP_not_OP_32,
       stage2_mbox$valid;

  // ports of submodule stage3_f_reset_reqs
  wire stage3_f_reset_reqs$CLR,
       stage3_f_reset_reqs$DEQ,
       stage3_f_reset_reqs$EMPTY_N,
       stage3_f_reset_reqs$ENQ,
       stage3_f_reset_reqs$FULL_N;

  // ports of submodule stage3_f_reset_rsps
  wire stage3_f_reset_rsps$CLR,
       stage3_f_reset_rsps$DEQ,
       stage3_f_reset_rsps$EMPTY_N,
       stage3_f_reset_rsps$ENQ,
       stage3_f_reset_rsps$FULL_N;

  // rule scheduling signals
  wire CAN_FIRE_RL_imem_rl_assert_fail,
       CAN_FIRE_RL_imem_rl_fetch_next_32b,
       CAN_FIRE_RL_rl_BREAK_cache_flush_finish,
       CAN_FIRE_RL_rl_WFI_resume,
       CAN_FIRE_RL_rl_debug_csr_access_busy,
       CAN_FIRE_RL_rl_debug_gpr_access_busy,
       CAN_FIRE_RL_rl_debug_halt,
       CAN_FIRE_RL_rl_debug_halt_redundant,
       CAN_FIRE_RL_rl_debug_read_csr,
       CAN_FIRE_RL_rl_debug_read_gpr,
       CAN_FIRE_RL_rl_debug_run,
       CAN_FIRE_RL_rl_debug_run_redundant,
       CAN_FIRE_RL_rl_debug_write_csr,
       CAN_FIRE_RL_rl_debug_write_gpr,
       CAN_FIRE_RL_rl_finish_FENCE,
       CAN_FIRE_RL_rl_finish_FENCE_I,
       CAN_FIRE_RL_rl_finish_SFENCE_VMA,
       CAN_FIRE_RL_rl_pipe,
       CAN_FIRE_RL_rl_reset_complete,
       CAN_FIRE_RL_rl_reset_from_Debug_Module,
       CAN_FIRE_RL_rl_reset_from_WFI,
       CAN_FIRE_RL_rl_reset_start,
       CAN_FIRE_RL_rl_show_pipe,
       CAN_FIRE_RL_rl_stage1_CSRR_S_or_C,
       CAN_FIRE_RL_rl_stage1_CSRR_S_or_C_2,
       CAN_FIRE_RL_rl_stage1_CSRR_W,
       CAN_FIRE_RL_rl_stage1_CSRR_W_2,
       CAN_FIRE_RL_rl_stage1_FENCE,
       CAN_FIRE_RL_rl_stage1_FENCE_I,
       CAN_FIRE_RL_rl_stage1_SFENCE_VMA,
       CAN_FIRE_RL_rl_stage1_WFI,
       CAN_FIRE_RL_rl_stage1_interrupt,
       CAN_FIRE_RL_rl_stage1_mip_cmd,
       CAN_FIRE_RL_rl_stage1_restart_after_csrrx,
       CAN_FIRE_RL_rl_stage1_stop,
       CAN_FIRE_RL_rl_stage1_trap,
       CAN_FIRE_RL_rl_stage1_xRET,
       CAN_FIRE_RL_rl_stage2_nonpipe,
       CAN_FIRE_RL_rl_trap,
       CAN_FIRE_RL_rl_trap_BREAK_to_Debug_Mode,
       CAN_FIRE_RL_rl_trap_fetch,
       CAN_FIRE_RL_stage1_rl_reset,
       CAN_FIRE_RL_stage2_rl_reset_begin,
       CAN_FIRE_RL_stage2_rl_reset_end,
       CAN_FIRE_RL_stage3_rl_reset,
       CAN_FIRE_dmem_master_m_arready,
       CAN_FIRE_dmem_master_m_awready,
       CAN_FIRE_dmem_master_m_bvalid,
       CAN_FIRE_dmem_master_m_rvalid,
       CAN_FIRE_dmem_master_m_wready,
       CAN_FIRE_hart0_csr_mem_server_request_put,
       CAN_FIRE_hart0_csr_mem_server_response_get,
       CAN_FIRE_hart0_gpr_mem_server_request_put,
       CAN_FIRE_hart0_gpr_mem_server_response_get,
       CAN_FIRE_hart0_put_other_req_put,
       CAN_FIRE_hart0_server_reset_request_put,
       CAN_FIRE_hart0_server_reset_response_get,
       CAN_FIRE_hart0_server_run_halt_request_put,
       CAN_FIRE_hart0_server_run_halt_response_get,
       CAN_FIRE_imem_master_m_arready,
       CAN_FIRE_imem_master_m_awready,
       CAN_FIRE_imem_master_m_bvalid,
       CAN_FIRE_imem_master_m_rvalid,
       CAN_FIRE_imem_master_m_wready,
       CAN_FIRE_m_external_interrupt_req,
       CAN_FIRE_nmi_req,
       CAN_FIRE_s_external_interrupt_req,
       CAN_FIRE_set_verbosity,
       CAN_FIRE_software_interrupt_req,
       CAN_FIRE_timer_interrupt_req,
       CAN_FIRE_trace_data_out_get,
       WILL_FIRE_RL_imem_rl_assert_fail,
       WILL_FIRE_RL_imem_rl_fetch_next_32b,
       WILL_FIRE_RL_rl_BREAK_cache_flush_finish,
       WILL_FIRE_RL_rl_WFI_resume,
       WILL_FIRE_RL_rl_debug_csr_access_busy,
       WILL_FIRE_RL_rl_debug_gpr_access_busy,
       WILL_FIRE_RL_rl_debug_halt,
       WILL_FIRE_RL_rl_debug_halt_redundant,
       WILL_FIRE_RL_rl_debug_read_csr,
       WILL_FIRE_RL_rl_debug_read_gpr,
       WILL_FIRE_RL_rl_debug_run,
       WILL_FIRE_RL_rl_debug_run_redundant,
       WILL_FIRE_RL_rl_debug_write_csr,
       WILL_FIRE_RL_rl_debug_write_gpr,
       WILL_FIRE_RL_rl_finish_FENCE,
       WILL_FIRE_RL_rl_finish_FENCE_I,
       WILL_FIRE_RL_rl_finish_SFENCE_VMA,
       WILL_FIRE_RL_rl_pipe,
       WILL_FIRE_RL_rl_reset_complete,
       WILL_FIRE_RL_rl_reset_from_Debug_Module,
       WILL_FIRE_RL_rl_reset_from_WFI,
       WILL_FIRE_RL_rl_reset_start,
       WILL_FIRE_RL_rl_show_pipe,
       WILL_FIRE_RL_rl_stage1_CSRR_S_or_C,
       WILL_FIRE_RL_rl_stage1_CSRR_S_or_C_2,
       WILL_FIRE_RL_rl_stage1_CSRR_W,
       WILL_FIRE_RL_rl_stage1_CSRR_W_2,
       WILL_FIRE_RL_rl_stage1_FENCE,
       WILL_FIRE_RL_rl_stage1_FENCE_I,
       WILL_FIRE_RL_rl_stage1_SFENCE_VMA,
       WILL_FIRE_RL_rl_stage1_WFI,
       WILL_FIRE_RL_rl_stage1_interrupt,
       WILL_FIRE_RL_rl_stage1_mip_cmd,
       WILL_FIRE_RL_rl_stage1_restart_after_csrrx,
       WILL_FIRE_RL_rl_stage1_stop,
       WILL_FIRE_RL_rl_stage1_trap,
       WILL_FIRE_RL_rl_stage1_xRET,
       WILL_FIRE_RL_rl_stage2_nonpipe,
       WILL_FIRE_RL_rl_trap,
       WILL_FIRE_RL_rl_trap_BREAK_to_Debug_Mode,
       WILL_FIRE_RL_rl_trap_fetch,
       WILL_FIRE_RL_stage1_rl_reset,
       WILL_FIRE_RL_stage2_rl_reset_begin,
       WILL_FIRE_RL_stage2_rl_reset_end,
       WILL_FIRE_RL_stage3_rl_reset,
       WILL_FIRE_dmem_master_m_arready,
       WILL_FIRE_dmem_master_m_awready,
       WILL_FIRE_dmem_master_m_bvalid,
       WILL_FIRE_dmem_master_m_rvalid,
       WILL_FIRE_dmem_master_m_wready,
       WILL_FIRE_hart0_csr_mem_server_request_put,
       WILL_FIRE_hart0_csr_mem_server_response_get,
       WILL_FIRE_hart0_gpr_mem_server_request_put,
       WILL_FIRE_hart0_gpr_mem_server_response_get,
       WILL_FIRE_hart0_put_other_req_put,
       WILL_FIRE_hart0_server_reset_request_put,
       WILL_FIRE_hart0_server_reset_response_get,
       WILL_FIRE_hart0_server_run_halt_request_put,
       WILL_FIRE_hart0_server_run_halt_response_get,
       WILL_FIRE_imem_master_m_arready,
       WILL_FIRE_imem_master_m_awready,
       WILL_FIRE_imem_master_m_bvalid,
       WILL_FIRE_imem_master_m_rvalid,
       WILL_FIRE_imem_master_m_wready,
       WILL_FIRE_m_external_interrupt_req,
       WILL_FIRE_nmi_req,
       WILL_FIRE_s_external_interrupt_req,
       WILL_FIRE_set_verbosity,
       WILL_FIRE_software_interrupt_req,
       WILL_FIRE_timer_interrupt_req,
       WILL_FIRE_trace_data_out_get;

  // inputs to muxes for submodule ports
  reg [31 : 0] MUX_csr_regfile$mav_csr_write_2__VAL_2;
  wire [234 : 0] MUX_f_trace_data$enq_1__VAL_1,
		 MUX_f_trace_data$enq_1__VAL_2,
		 MUX_f_trace_data$enq_1__VAL_3,
		 MUX_f_trace_data$enq_1__VAL_6,
		 MUX_f_trace_data$enq_1__VAL_7,
		 MUX_f_trace_data$enq_1__VAL_8;
  wire [67 : 0] MUX_rg_trap_info$write_1__VAL_1,
		MUX_rg_trap_info$write_1__VAL_2,
		MUX_rg_trap_info$write_1__VAL_3,
		MUX_rg_trap_info$write_1__VAL_4;
  wire [32 : 0] MUX_f_csr_rsps$enq_1__VAL_3, MUX_f_gpr_rsps$enq_1__VAL_3;
  wire [31 : 0] MUX_imem_rg_tval$write_1__VAL_6,
		MUX_near_mem$imem_req_2__VAL_1,
		MUX_near_mem$imem_req_2__VAL_2,
		MUX_near_mem$imem_req_2__VAL_5,
		MUX_near_mem$imem_req_2__VAL_7;
  wire [3 : 0] MUX_rg_state$write_1__VAL_1,
	       MUX_rg_state$write_1__VAL_2,
	       MUX_rg_state$write_1__VAL_3;
  wire [2 : 0] MUX_csr_regfile$write_dcsr_cause_priv_1__VAL_2;
  wire MUX_csr_regfile$mav_csr_write_1__SEL_1,
       MUX_csr_regfile$mav_csr_write_1__SEL_2,
       MUX_csr_regfile$write_dcsr_cause_priv_1__SEL_1,
       MUX_f_run_halt_rsps$enq_1__SEL_1,
       MUX_f_trace_data$enq_1__SEL_1,
       MUX_f_trace_data$enq_1__SEL_3,
       MUX_f_trace_data$enq_1__SEL_4,
       MUX_gpr_regfile$write_rd_1__SEL_1,
       MUX_imem_rg_f3$write_1__SEL_1,
       MUX_imem_rg_f3$write_1__SEL_2,
       MUX_imem_rg_mstatus_MXR$write_1__SEL_4,
       MUX_imem_rg_pc$write_1__SEL_4,
       MUX_near_mem$imem_req_1__SEL_6,
       MUX_rg_next_pc$write_1__SEL_3,
       MUX_rg_state$write_1__SEL_1,
       MUX_rg_state$write_1__SEL_10,
       MUX_rg_state$write_1__SEL_11,
       MUX_rg_state$write_1__SEL_12,
       MUX_rg_state$write_1__SEL_13,
       MUX_rg_state$write_1__SEL_2,
       MUX_rg_state$write_1__SEL_3,
       MUX_rg_state$write_1__SEL_4,
       MUX_rg_state$write_1__SEL_5,
       MUX_rg_state$write_1__SEL_6,
       MUX_rg_state$write_1__SEL_7,
       MUX_rg_state$write_1__SEL_8,
       MUX_rg_state$write_1__SEL_9,
       MUX_rg_step_count$write_1__PSEL_1,
       MUX_rg_step_count$write_1__SEL_3,
       MUX_rg_trap_info$write_1__SEL_1,
       MUX_rg_trap_instr$write_1__SEL_1,
       MUX_rg_trap_interrupt$write_1__SEL_1,
       MUX_rg_trap_trace_data$write_1__SEL_1,
       MUX_stage1_rg_full$write_1__VAL_8,
       MUX_stage2_rg_full$write_1__VAL_3;

  // declarations used by system tasks
  // synopsys translate_off
  reg [31 : 0] v__h2309;
  reg [31 : 0] v__h2303;
  // synopsys translate_on

  // remaining internal signals
  reg [63 : 0] x_out_data_to_stage2_trace_data_word3__h18724;
  reg [31 : 0] CASE_stage2_rg_stage2_BITS_338_TO_336_0_stage2_ETC__q19,
	       IF_IF_imem_rg_pc_BITS_1_TO_0_EQ_0b0_OR_NOT_ime_ETC___d1050,
	       IF_IF_imem_rg_pc_BITS_1_TO_0_EQ_0b0_OR_NOT_ime_ETC___d1256,
	       IF_IF_imem_rg_pc_BITS_1_TO_0_EQ_0b0_OR_NOT_ime_ETC___d965,
	       _theResult_____1_fst__h14295,
	       rs1_val__h23025,
	       x__h19341,
	       x__h19610,
	       x_out_bypass_rd_val__h7451,
	       x_out_data_to_stage2_addr__h13093,
	       x_out_data_to_stage2_val1__h13094,
	       x_out_data_to_stage3_rd_val__h7111;
  reg [4 : 0] CASE_theResult__973_BITS_6_TO_0_0b11_9_0b1111__ETC__q18,
	      x_out_bypass_rd__h7450,
	      x_out_data_to_stage2_trace_data_rd__h18721,
	      x_out_data_to_stage3_rd__h7110;
  reg [3 : 0] CASE_rg_cur_priv_0b0_8_0b1_9_11__q5,
	      CASE_theResult__973_BITS_14_TO_12_0b0_0_0b1_0__ETC__q12,
	      CASE_theResult__973_BITS_14_TO_12_0b0_0_0b1_0__ETC__q14,
	      CASE_theResult__973_BITS_14_TO_12_0b0_4_0b1_5_11__q13,
	      CASE_theResult__973_BITS_14_TO_12_0b0_IF_theRe_ETC__q15,
	      CASE_theResult__973_BITS_31_TO_20_0b0_CASE_rg__ETC__q6,
	      IF_IF_imem_rg_pc_BITS_1_TO_0_EQ_0b0_OR_NOT_ime_ETC___d754,
	      IF_IF_imem_rg_pc_BITS_1_TO_0_EQ_0b0_OR_NOT_ime_ETC___d769,
	      IF_IF_imem_rg_pc_BITS_1_TO_0_EQ_0b0_OR_NOT_ime_ETC___d773,
	      alu_outputs_exc_code__h13792;
  reg [2 : 0] CASE_theResult__973_BITS_6_TO_0_0b11_1_0b10011_ETC__q16,
	      IF_NOT_stage1_rg_full_03_04_OR_NOT_near_mem_im_ETC___d854;
  reg [1 : 0] CASE_stage2_rg_stage2_BITS_338_TO_336_0_2_1_IF_ETC__q1,
	      CASE_stage2_rg_stage2_BITS_338_TO_336_0_2_1_IF_ETC__q2;
  reg CASE_theResult__973_BITS_6_TO_0_0b10011_IF_ime_ETC__q11,
      CASE_theResult__973_BITS_6_TO_0_0b10011_NOT_IF_ETC__q9,
      CASE_theResult__973_BITS_6_TO_0_0b11_NOT_theRe_ETC__q8,
      CASE_theResult__973_BITS_6_TO_0_0b11_theResult_ETC__q10,
      IF_IF_imem_rg_pc_BITS_1_TO_0_EQ_0b0_OR_NOT_ime_ETC___d563,
      IF_IF_imem_rg_pc_BITS_1_TO_0_EQ_0b0_OR_NOT_ime_ETC___d657,
      IF_stage2_rg_stage2_6_BITS_338_TO_336_7_EQ_1_9_ETC___d140,
      IF_stage2_rg_stage2_6_BITS_338_TO_336_7_EQ_1_9_ETC___d149;
  wire [234 : 0] IF_NOT_stage1_rg_full_03_04_OR_NOT_near_mem_im_ETC___d1286;
  wire [127 : 0] csr_regfile_read_csr_mcycle__0_MINUS_rg_start__ETC___d1585;
  wire [63 : 0] _theResult____h29734,
		alu_outputs___1_trace_data_word3__h18597,
		alu_outputs___1_trace_data_word3__h18617,
		cpi__h29736,
		cpifrac__h29737,
		delta_CPI_cycles__h29732,
		delta_CPI_instrs___1__h29769,
		delta_CPI_instrs__h29733,
		x__h29735,
		x_word3__h21617,
		x_word3__h23406;
  wire [35 : 0] IF_near_mem_imem_exc__14_THEN_near_mem_imem_ex_ETC___d1405;
  wire [31 : 0] IF_IF_imem_rg_pc_BITS_1_TO_0_EQ_0b0_OR_NOT_ime_ETC___d1257,
		IF_IF_imem_rg_pc_BITS_1_TO_0_EQ_0b0_OR_NOT_ime_ETC___d966,
		IF_NOT_imem_rg_pc_BITS_1_TO_0_EQ_0b0_AND_imem__ETC___d251,
		IF_csr_regfile_read_csr_rg_trap_instr_435_BITS_ETC___d1487,
		IF_csr_regfile_read_misa__8_BIT_2_35_AND_IF_NO_ETC___d466,
		IF_csr_regfile_read_misa__8_BIT_2_35_AND_IF_NO_ETC___d468,
		IF_csr_regfile_read_misa__8_BIT_2_35_AND_IF_NO_ETC___d470,
		IF_csr_regfile_read_misa__8_BIT_2_35_AND_IF_NO_ETC___d471,
		IF_csr_regfile_read_misa__8_BIT_2_35_AND_IF_NO_ETC___d473,
		IF_csr_regfile_read_misa__8_BIT_2_35_AND_IF_NO_ETC___d474,
		IF_csr_regfile_read_misa__8_BIT_2_35_AND_IF_NO_ETC___d475,
		IF_csr_regfile_read_misa__8_BIT_2_35_AND_IF_NO_ETC___d477,
		IF_csr_regfile_read_misa__8_BIT_2_35_AND_IF_NO_ETC___d478,
		IF_csr_regfile_read_misa__8_BIT_2_35_AND_IF_NO_ETC___d479,
		IF_csr_regfile_read_misa__8_BIT_2_35_AND_IF_NO_ETC___d481,
		IF_csr_regfile_read_misa__8_BIT_2_35_AND_IF_NO_ETC___d482,
		IF_csr_regfile_read_misa__8_BIT_2_35_AND_IF_NO_ETC___d483,
		IF_csr_regfile_read_misa__8_BIT_2_35_AND_IF_NO_ETC___d484,
		IF_csr_regfile_read_misa__8_BIT_2_35_AND_IF_NO_ETC___d485,
		IF_csr_regfile_read_misa__8_BIT_2_35_AND_IF_NO_ETC___d486,
		IF_csr_regfile_read_misa__8_BIT_2_35_AND_IF_NO_ETC___d487,
		IF_csr_regfile_read_misa__8_BIT_2_35_AND_IF_NO_ETC___d488,
		IF_csr_regfile_read_misa__8_BIT_2_35_AND_IF_NO_ETC___d489,
		IF_imem_rg_pc_BITS_1_TO_0_EQ_0b0_AND_imem_rg_p_ETC___d252,
		IF_imem_rg_pc_BITS_1_TO_0_EQ_0b0_OR_NOT_imem_r_ETC___d898,
		SEXT_IF_imem_rg_pc_BITS_1_TO_0_EQ_0b0_OR_NOT_i_ETC___d907,
		_theResult_____1_fst__h14288,
		_theResult_____1_fst__h14323,
		_theResult____h13381,
		_theResult____h4973,
		_theResult___snd__h15566,
		addr_of_b32___1__h17149,
		addr_of_b32___1__h20695,
		addr_of_b32___1__h28882,
		addr_of_b32___1__h30512,
		addr_of_b32__h17037,
		addr_of_b32__h20583,
		addr_of_b32__h28770,
		addr_of_b32__h30400,
		alu_outputs___1_addr__h13234,
		alu_outputs___1_addr__h13258,
		alu_outputs___1_addr__h13287,
		alu_outputs___1_trace_data_word1__h18615,
		alu_outputs___1_val1__h13751,
		alu_outputs___1_val1__h13773,
		branch_target__h13210,
		data_to_stage2_addr__h13084,
		eaddr__h13475,
		eaddr__h13496,
		fall_through_pc__h13043,
		instr___1__h7611,
		instr__h10222,
		instr__h10406,
		instr__h10535,
		instr__h10972,
		instr__h11144,
		instr__h11317,
		instr__h11510,
		instr__h11703,
		instr__h11820,
		instr__h11998,
		instr__h12117,
		instr__h12212,
		instr__h12348,
		instr__h12484,
		instr__h12620,
		instr__h12958,
		instr__h4971,
		instr__h7892,
		instr__h8037,
		instr__h8229,
		instr__h8424,
		instr__h8653,
		instr__h8996,
		instr__h9386,
		instr__h9502,
		instr__h9567,
		instr__h9884,
		instr_out___1__h7749,
		instr_out___1__h7771,
		next_pc___1__h14997,
		next_pc__h14995,
		output_stage2___1_bypass_rd_val__h7439,
		rd_val___1__h14276,
		rd_val___1__h14284,
		rd_val___1__h14291,
		rd_val___1__h14298,
		rd_val___1__h14305,
		rd_val___1__h14312,
		rd_val__h13000,
		rd_val__h13421,
		rd_val__h13439,
		rd_val__h13456,
		rd_val__h15462,
		rd_val__h15514,
		rd_val__h15536,
		rd_val__h7563,
		rs1_val__h22206,
		rs1_val_bypassed__h4981,
		rs2_val__h13206,
		trap_info_tval__h14833,
		val__h13002,
		val__h7565,
		value__h14885,
		x__h19433,
		x__h19810,
		x__h21782,
		x__h23453,
		x__h23461,
		x_out_data_to_stage2_instr__h13090,
		x_out_data_to_stage2_val2__h13095,
		x_out_next_pc__h13057,
		y__h23296;
  wire [20 : 0] SEXT_IF_NOT_imem_rg_pc_BITS_1_TO_0_EQ_0b0_AND__ETC___d317,
		theResult__973_BIT_31_CONCAT_theResult__973_BI_ETC__q4;
  wire [19 : 0] imm20__h10274;
  wire [12 : 0] SEXT_IF_NOT_imem_rg_pc_BITS_1_TO_0_EQ_0b0_AND__ETC___d346,
		theResult__973_BIT_31_CONCAT_theResult__973_BI_ETC__q3;
  wire [11 : 0] imm12__h10146,
		imm12__h10770,
		imm12__h10985,
		imm12__h11181,
		imm12__h11526,
		imm12__h7893,
		imm12__h8230,
		offset__h8600,
		theResult__973_BITS_31_TO_20__q17,
		theResult__973_BITS_31_TO_25_CONCAT_theResult__ETC__q7;
  wire [9 : 0] nzimm10__h10768, nzimm10__h10983;
  wire [8 : 0] offset__h9511;
  wire [7 : 0] offset__h7649;
  wire [6 : 0] offset__h8172;
  wire [5 : 0] imm6__h10144;
  wire [4 : 0] offset_BITS_4_TO_0___h8161,
	       offset_BITS_4_TO_0___h8592,
	       rd__h8232,
	       rs1__h8231,
	       shamt__h13377,
	       td1_rd__h24478,
	       x_out_data_to_stage2_rd__h13092,
	       x_rd__h21614;
  wire [3 : 0] IF_NOT_IF_imem_rg_pc_BITS_1_TO_0_EQ_0b0_OR_NOT_ETC___d719,
	       IF_NOT_stage1_rg_full_03_04_OR_NOT_near_mem_im_ETC___d775,
	       IF_rg_cur_priv_1_EQ_0b11_33_OR_rg_cur_priv_1_E_ETC___d752,
	       alu_outputs___1_exc_code__h13747,
	       cur_verbosity__h3490,
	       x_exc_code__h29483,
	       x_out_trap_info_exc_code__h14836;
  wire [1 : 0] IF_NOT_near_mem_dmem_valid__17_36_OR_NOT_near__ETC___d184,
	       IF_near_mem_dmem_valid__17_THEN_IF_near_mem_dm_ETC___d120,
	       IF_stage2_rg_full_5_THEN_IF_stage2_rg_stage2_6_ETC___d126,
	       IF_stage2_rg_full_5_THEN_IF_stage2_rg_stage2_6_ETC___d188,
	       IF_stage2_rg_stage2_6_BITS_335_TO_331_56_EQ_0__ETC___d183,
	       IF_stage2_rg_stage2_6_BITS_338_TO_336_7_EQ_3_0_ETC___d123;
  wire IF_IF_imem_rg_pc_BITS_1_TO_0_EQ_0b0_OR_NOT_ime_ETC___d1113,
       IF_IF_imem_rg_pc_BITS_1_TO_0_EQ_0b0_OR_NOT_ime_ETC___d1151,
       IF_IF_imem_rg_pc_BITS_1_TO_0_EQ_0b0_OR_NOT_ime_ETC___d1160,
       IF_IF_imem_rg_pc_BITS_1_TO_0_EQ_0b0_OR_NOT_ime_ETC___d1372,
       IF_IF_imem_rg_pc_BITS_1_TO_0_EQ_0b0_OR_NOT_ime_ETC___d1373,
       IF_IF_imem_rg_pc_BITS_1_TO_0_EQ_0b0_OR_NOT_ime_ETC___d1377,
       IF_IF_imem_rg_pc_BITS_1_TO_0_EQ_0b0_OR_NOT_ime_ETC___d552,
       IF_IF_imem_rg_pc_BITS_1_TO_0_EQ_0b0_OR_NOT_ime_ETC___d554,
       IF_IF_imem_rg_pc_BITS_1_TO_0_EQ_0b0_OR_NOT_ime_ETC___d556,
       IF_IF_imem_rg_pc_BITS_1_TO_0_EQ_0b0_OR_NOT_ime_ETC___d651,
       IF_IF_imem_rg_pc_BITS_1_TO_0_EQ_0b0_OR_NOT_ime_ETC___d662,
       IF_IF_imem_rg_pc_BITS_1_TO_0_EQ_0b0_OR_NOT_ime_ETC___d709,
       IF_IF_imem_rg_pc_BITS_1_TO_0_EQ_0b0_OR_NOT_ime_ETC___d711,
       IF_imem_rg_pc_BITS_1_TO_0_EQ_0b0_OR_NOT_imem_r_ETC___d682,
       IF_stage2_rg_full_5_THEN_IF_stage2_rg_stage2_6_ETC___d493,
       IF_stage2_rg_full_5_THEN_IF_stage2_rg_stage2_6_ETC___d495,
       NOT_IF_NOT_stage1_rg_full_03_04_OR_NOT_near_me_ETC___d1354,
       NOT_IF_csr_regfile_read_csr_minstret__7_ULT_cf_ETC___d43,
       NOT_IF_imem_rg_pc_BITS_1_TO_0_EQ_0b0_OR_NOT_im_ETC___d593,
       NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d1224,
       NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d1318,
       NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d1338,
       NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d1389,
       NOT_csr_regfile_read_dpc__602_BITS_1_TO_0_603__ETC___d1611,
       NOT_imem_rg_pc_BITS_1_TO_0_EQ_0b0_AND_imem_rg__ETC___d1340,
       NOT_imem_rg_pc_BITS_1_TO_0_EQ_0b0_AND_imem_rg__ETC___d238,
       NOT_imem_rg_pc_BITS_1_TO_0_EQ_0b0_AND_imem_rg__ETC___d248,
       NOT_imem_rg_pc_BITS_1_TO_0_EQ_0b0_AND_imem_rg__ETC___d505,
       NOT_imem_rg_pc_BITS_1_TO_0_EQ_0b0_AND_imem_rg__ETC___d507,
       NOT_imem_rg_pc_BITS_31_TO_2_0_EQ_imem_rg_cache_ETC___d1157,
       NOT_near_mem_imem_exc__14_67_AND_IF_IF_imem_rg_ETC___d1387,
       NOT_near_mem_imem_exc__14_67_AND_IF_IF_imem_rg_ETC___d841,
       NOT_near_mem_imem_exc__14_67_AND_IF_IF_imem_rg_ETC___d878,
       NOT_near_mem_imem_valid_05_OR_imem_rg_pc_BITS__ETC___d1168,
       NOT_near_mem_imem_valid_05_OR_imem_rg_pc_BITS__ETC___d1181,
       NOT_near_mem_imem_valid_05_OR_imem_rg_pc_BITS__ETC___d498,
       NOT_rg_next_pc_524_BITS_1_TO_0_525_EQ_0b0_526__ETC___d1533,
       NOT_rg_stop_req_138_173_AND_NOT_rg_step_count__ETC___d1180,
       NOT_rg_stop_req_138_173_AND_NOT_rg_step_count__ETC___d1184,
       NOT_soc_map_m_pc_reset_value__096_BITS_1_TO_0__ETC___d1108,
       NOT_stage1_rg_full_03_04_OR_NOT_near_mem_imem__ETC___d1316,
       NOT_stage1_rg_full_03_04_OR_NOT_near_mem_imem__ETC___d1324,
       NOT_stage1_rg_full_03_04_OR_imem_rg_pc_BITS_1__ETC___d1336,
       NOT_stage1_rg_full_03_04_OR_imem_rg_pc_BITS_1__ETC___d1344,
       _0_OR_0_OR_near_mem_imem_exc__14_OR_IF_IF_imem__ETC___d1360,
       _0_OR_0_OR_near_mem_imem_exc__14_OR_IF_IF_imem__ETC___d1362,
       _0_OR_0_OR_near_mem_imem_exc__14_OR_IF_IF_imem__ETC___d1364,
       _0_OR_0_OR_near_mem_imem_exc__14_OR_IF_IF_imem__ETC___d1367,
       _0_OR_0_OR_near_mem_imem_exc__14_OR_IF_IF_imem__ETC___d1370,
       csr_regfile_RDY_server_reset_response_get__076_ETC___d1091,
       csr_regfile_csr_mip_read__118_EQ_rg_prev_mip_119___d1120,
       csr_regfile_interrupt_pending_rg_cur_priv_1_14_ETC___d1147,
       csr_regfile_read_misa__8_BIT_2_35_AND_IF_NOT_i_ETC___d331,
       csr_regfile_read_misa__8_BIT_2_35_AND_IF_NOT_i_ETC___d337,
       imem_rg_pc_BITS_1_TO_0_EQ_0b0_OR_NOT_imem_rg_p_ETC___d1330,
       imem_rg_pc_BITS_1_TO_0_EQ_0b0_OR_NOT_imem_rg_p_ETC___d1331,
       imem_rg_pc_BITS_1_TO_0_EQ_0b0_OR_NOT_imem_rg_p_ETC___d1333,
       imem_rg_pc_BITS_1_TO_0_EQ_0b0_OR_NOT_imem_rg_p_ETC___d226,
       imem_rg_pc_BITS_1_TO_0_EQ_0b0_OR_NOT_imem_rg_p_ETC___d230,
       imem_rg_pc_BITS_1_TO_0_EQ_0b0_OR_NOT_imem_rg_p_ETC___d233,
       imem_rg_pc_BITS_1_TO_0_EQ_0b0_OR_NOT_near_mem__ETC___d1085,
       imem_rg_pc_BITS_31_TO_2_0_EQ_imem_rg_cache_add_ETC___d1135,
       imem_rg_pc_BITS_31_TO_2_0_EQ_imem_rg_cache_add_ETC___d208,
       imem_rg_pc_BITS_31_TO_2_0_EQ_near_mem_imem_pc__ETC___d13,
       near_mem_RDY_server_reset_request_put__055_AND_ETC___d1067,
       near_mem_imem_exc__14_OR_IF_IF_imem_rg_pc_BITS_ETC___d1002,
       near_mem_imem_exc__14_OR_IF_IF_imem_rg_pc_BITS_ETC___d1005,
       near_mem_imem_exc__14_OR_IF_IF_imem_rg_pc_BITS_ETC___d1008,
       near_mem_imem_exc__14_OR_IF_IF_imem_rg_pc_BITS_ETC___d1011,
       near_mem_imem_exc__14_OR_IF_IF_imem_rg_pc_BITS_ETC___d1222,
       near_mem_imem_exc__14_OR_IF_IF_imem_rg_pc_BITS_ETC___d1227,
       near_mem_imem_exc__14_OR_IF_IF_imem_rg_pc_BITS_ETC___d1305,
       near_mem_imem_exc__14_OR_IF_IF_imem_rg_pc_BITS_ETC___d1307,
       near_mem_imem_exc__14_OR_IF_IF_imem_rg_pc_BITS_ETC___d1309,
       near_mem_imem_exc__14_OR_IF_IF_imem_rg_pc_BITS_ETC___d1311,
       near_mem_imem_exc__14_OR_IF_IF_imem_rg_pc_BITS_ETC___d1313,
       near_mem_imem_exc__14_OR_IF_IF_imem_rg_pc_BITS_ETC___d1315,
       near_mem_imem_exc__14_OR_IF_IF_imem_rg_pc_BITS_ETC___d1342,
       near_mem_imem_exc__14_OR_IF_IF_imem_rg_pc_BITS_ETC___d978,
       near_mem_imem_exc__14_OR_IF_IF_imem_rg_pc_BITS_ETC___d981,
       near_mem_imem_exc__14_OR_IF_IF_imem_rg_pc_BITS_ETC___d984,
       near_mem_imem_exc__14_OR_IF_IF_imem_rg_pc_BITS_ETC___d987,
       near_mem_imem_exc__14_OR_IF_IF_imem_rg_pc_BITS_ETC___d990,
       near_mem_imem_exc__14_OR_IF_IF_imem_rg_pc_BITS_ETC___d993,
       near_mem_imem_exc__14_OR_IF_IF_imem_rg_pc_BITS_ETC___d996,
       near_mem_imem_exc__14_OR_IF_IF_imem_rg_pc_BITS_ETC___d999,
       near_mem_imem_pc__1_EQ_imem_rg_pc_PLUS_2_11___d212,
       near_mem_imem_valid_AND_NOT_imem_rg_pc_BITS_1__ETC___d513,
       near_mem_imem_valid_AND_NOT_imem_rg_pc_BITS_1__ETC___d665,
       near_mem_imem_valid_AND_NOT_imem_rg_pc_BITS_1__ETC___d714,
       rg_cur_priv_1_EQ_0b11_33_OR_rg_cur_priv_1_EQ_0_ETC___d750,
       rg_state_4_EQ_4_112_AND_NOT_near_mem_imem_exc__ETC___d1394,
       rg_state_4_EQ_4_112_AND_rg_stop_req_138_OR_rg__ETC___d1581,
       rg_state_4_EQ_4_112_AND_stage3_rg_full_6_OR_NO_ETC___d1187,
       rg_stop_req_138_OR_rg_step_count_139_140_AND_s_ETC___d1576,
       stage1_rg_full_03_AND_imem_rg_pc_BITS_31_TO_2__ETC___d1141,
       stage1_rg_full_03_AND_near_mem_imem_valid_AND__ETC___d1116,
       stage1_rg_full_03_AND_near_mem_imem_valid_AND__ETC___d1380;

  // action method hart0_server_reset_request_put
  assign RDY_hart0_server_reset_request_put = f_reset_reqs$FULL_N ;
  assign CAN_FIRE_hart0_server_reset_request_put = f_reset_reqs$FULL_N ;
  assign WILL_FIRE_hart0_server_reset_request_put =
	     EN_hart0_server_reset_request_put ;

  // actionvalue method hart0_server_reset_response_get
  assign hart0_server_reset_response_get = f_reset_rsps$D_OUT ;
  assign RDY_hart0_server_reset_response_get = f_reset_rsps$EMPTY_N ;
  assign CAN_FIRE_hart0_server_reset_response_get = f_reset_rsps$EMPTY_N ;
  assign WILL_FIRE_hart0_server_reset_response_get =
	     EN_hart0_server_reset_response_get ;

  // value method imem_master_m_awvalid
  assign imem_master_awvalid = near_mem$imem_master_awvalid ;

  // value method imem_master_m_awid
  assign imem_master_awid = near_mem$imem_master_awid ;

  // value method imem_master_m_awaddr
  assign imem_master_awaddr = near_mem$imem_master_awaddr ;

  // value method imem_master_m_awlen
  assign imem_master_awlen = near_mem$imem_master_awlen ;

  // value method imem_master_m_awsize
  assign imem_master_awsize = near_mem$imem_master_awsize ;

  // value method imem_master_m_awburst
  assign imem_master_awburst = near_mem$imem_master_awburst ;

  // value method imem_master_m_awlock
  assign imem_master_awlock = near_mem$imem_master_awlock ;

  // value method imem_master_m_awcache
  assign imem_master_awcache = near_mem$imem_master_awcache ;

  // value method imem_master_m_awprot
  assign imem_master_awprot = near_mem$imem_master_awprot ;

  // value method imem_master_m_awqos
  assign imem_master_awqos = near_mem$imem_master_awqos ;

  // value method imem_master_m_awregion
  assign imem_master_awregion = near_mem$imem_master_awregion ;

  // action method imem_master_m_awready
  assign CAN_FIRE_imem_master_m_awready = 1'd1 ;
  assign WILL_FIRE_imem_master_m_awready = 1'd1 ;

  // value method imem_master_m_wvalid
  assign imem_master_wvalid = near_mem$imem_master_wvalid ;

  // value method imem_master_m_wdata
  assign imem_master_wdata = near_mem$imem_master_wdata ;

  // value method imem_master_m_wstrb
  assign imem_master_wstrb = near_mem$imem_master_wstrb ;

  // value method imem_master_m_wlast
  assign imem_master_wlast = near_mem$imem_master_wlast ;

  // action method imem_master_m_wready
  assign CAN_FIRE_imem_master_m_wready = 1'd1 ;
  assign WILL_FIRE_imem_master_m_wready = 1'd1 ;

  // action method imem_master_m_bvalid
  assign CAN_FIRE_imem_master_m_bvalid = 1'd1 ;
  assign WILL_FIRE_imem_master_m_bvalid = 1'd1 ;

  // value method imem_master_m_bready
  assign imem_master_bready = near_mem$imem_master_bready ;

  // value method imem_master_m_arvalid
  assign imem_master_arvalid = near_mem$imem_master_arvalid ;

  // value method imem_master_m_arid
  assign imem_master_arid = near_mem$imem_master_arid ;

  // value method imem_master_m_araddr
  assign imem_master_araddr = near_mem$imem_master_araddr ;

  // value method imem_master_m_arlen
  assign imem_master_arlen = near_mem$imem_master_arlen ;

  // value method imem_master_m_arsize
  assign imem_master_arsize = near_mem$imem_master_arsize ;

  // value method imem_master_m_arburst
  assign imem_master_arburst = near_mem$imem_master_arburst ;

  // value method imem_master_m_arlock
  assign imem_master_arlock = near_mem$imem_master_arlock ;

  // value method imem_master_m_arcache
  assign imem_master_arcache = near_mem$imem_master_arcache ;

  // value method imem_master_m_arprot
  assign imem_master_arprot = near_mem$imem_master_arprot ;

  // value method imem_master_m_arqos
  assign imem_master_arqos = near_mem$imem_master_arqos ;

  // value method imem_master_m_arregion
  assign imem_master_arregion = near_mem$imem_master_arregion ;

  // action method imem_master_m_arready
  assign CAN_FIRE_imem_master_m_arready = 1'd1 ;
  assign WILL_FIRE_imem_master_m_arready = 1'd1 ;

  // action method imem_master_m_rvalid
  assign CAN_FIRE_imem_master_m_rvalid = 1'd1 ;
  assign WILL_FIRE_imem_master_m_rvalid = 1'd1 ;

  // value method imem_master_m_rready
  assign imem_master_rready = near_mem$imem_master_rready ;

  // value method dmem_master_m_awvalid
  assign dmem_master_awvalid = near_mem$dmem_master_awvalid ;

  // value method dmem_master_m_awid
  assign dmem_master_awid = near_mem$dmem_master_awid ;

  // value method dmem_master_m_awaddr
  assign dmem_master_awaddr = near_mem$dmem_master_awaddr ;

  // value method dmem_master_m_awlen
  assign dmem_master_awlen = near_mem$dmem_master_awlen ;

  // value method dmem_master_m_awsize
  assign dmem_master_awsize = near_mem$dmem_master_awsize ;

  // value method dmem_master_m_awburst
  assign dmem_master_awburst = near_mem$dmem_master_awburst ;

  // value method dmem_master_m_awlock
  assign dmem_master_awlock = near_mem$dmem_master_awlock ;

  // value method dmem_master_m_awcache
  assign dmem_master_awcache = near_mem$dmem_master_awcache ;

  // value method dmem_master_m_awprot
  assign dmem_master_awprot = near_mem$dmem_master_awprot ;

  // value method dmem_master_m_awqos
  assign dmem_master_awqos = near_mem$dmem_master_awqos ;

  // value method dmem_master_m_awregion
  assign dmem_master_awregion = near_mem$dmem_master_awregion ;

  // action method dmem_master_m_awready
  assign CAN_FIRE_dmem_master_m_awready = 1'd1 ;
  assign WILL_FIRE_dmem_master_m_awready = 1'd1 ;

  // value method dmem_master_m_wvalid
  assign dmem_master_wvalid = near_mem$dmem_master_wvalid ;

  // value method dmem_master_m_wdata
  assign dmem_master_wdata = near_mem$dmem_master_wdata ;

  // value method dmem_master_m_wstrb
  assign dmem_master_wstrb = near_mem$dmem_master_wstrb ;

  // value method dmem_master_m_wlast
  assign dmem_master_wlast = near_mem$dmem_master_wlast ;

  // action method dmem_master_m_wready
  assign CAN_FIRE_dmem_master_m_wready = 1'd1 ;
  assign WILL_FIRE_dmem_master_m_wready = 1'd1 ;

  // action method dmem_master_m_bvalid
  assign CAN_FIRE_dmem_master_m_bvalid = 1'd1 ;
  assign WILL_FIRE_dmem_master_m_bvalid = 1'd1 ;

  // value method dmem_master_m_bready
  assign dmem_master_bready = near_mem$dmem_master_bready ;

  // value method dmem_master_m_arvalid
  assign dmem_master_arvalid = near_mem$dmem_master_arvalid ;

  // value method dmem_master_m_arid
  assign dmem_master_arid = near_mem$dmem_master_arid ;

  // value method dmem_master_m_araddr
  assign dmem_master_araddr = near_mem$dmem_master_araddr ;

  // value method dmem_master_m_arlen
  assign dmem_master_arlen = near_mem$dmem_master_arlen ;

  // value method dmem_master_m_arsize
  assign dmem_master_arsize = near_mem$dmem_master_arsize ;

  // value method dmem_master_m_arburst
  assign dmem_master_arburst = near_mem$dmem_master_arburst ;

  // value method dmem_master_m_arlock
  assign dmem_master_arlock = near_mem$dmem_master_arlock ;

  // value method dmem_master_m_arcache
  assign dmem_master_arcache = near_mem$dmem_master_arcache ;

  // value method dmem_master_m_arprot
  assign dmem_master_arprot = near_mem$dmem_master_arprot ;

  // value method dmem_master_m_arqos
  assign dmem_master_arqos = near_mem$dmem_master_arqos ;

  // value method dmem_master_m_arregion
  assign dmem_master_arregion = near_mem$dmem_master_arregion ;

  // action method dmem_master_m_arready
  assign CAN_FIRE_dmem_master_m_arready = 1'd1 ;
  assign WILL_FIRE_dmem_master_m_arready = 1'd1 ;

  // action method dmem_master_m_rvalid
  assign CAN_FIRE_dmem_master_m_rvalid = 1'd1 ;
  assign WILL_FIRE_dmem_master_m_rvalid = 1'd1 ;

  // value method dmem_master_m_rready
  assign dmem_master_rready = near_mem$dmem_master_rready ;

  // action method m_external_interrupt_req
  assign CAN_FIRE_m_external_interrupt_req = 1'd1 ;
  assign WILL_FIRE_m_external_interrupt_req = 1'd1 ;

  // action method s_external_interrupt_req
  assign CAN_FIRE_s_external_interrupt_req = 1'd1 ;
  assign WILL_FIRE_s_external_interrupt_req = 1'd1 ;

  // action method software_interrupt_req
  assign CAN_FIRE_software_interrupt_req = 1'd1 ;
  assign WILL_FIRE_software_interrupt_req = 1'd1 ;

  // action method timer_interrupt_req
  assign CAN_FIRE_timer_interrupt_req = 1'd1 ;
  assign WILL_FIRE_timer_interrupt_req = 1'd1 ;

  // action method nmi_req
  assign CAN_FIRE_nmi_req = 1'd1 ;
  assign WILL_FIRE_nmi_req = 1'd1 ;

  // action method set_verbosity
  assign RDY_set_verbosity = 1'd1 ;
  assign CAN_FIRE_set_verbosity = 1'd1 ;
  assign WILL_FIRE_set_verbosity = EN_set_verbosity ;

  // actionvalue method trace_data_out_get
  assign trace_data_out_get = f_trace_data$D_OUT ;
  assign RDY_trace_data_out_get = f_trace_data$EMPTY_N ;
  assign CAN_FIRE_trace_data_out_get = f_trace_data$EMPTY_N ;
  assign WILL_FIRE_trace_data_out_get = EN_trace_data_out_get ;

  // action method hart0_server_run_halt_request_put
  assign RDY_hart0_server_run_halt_request_put = f_run_halt_reqs$FULL_N ;
  assign CAN_FIRE_hart0_server_run_halt_request_put = f_run_halt_reqs$FULL_N ;
  assign WILL_FIRE_hart0_server_run_halt_request_put =
	     EN_hart0_server_run_halt_request_put ;

  // actionvalue method hart0_server_run_halt_response_get
  assign hart0_server_run_halt_response_get = f_run_halt_rsps$D_OUT ;
  assign RDY_hart0_server_run_halt_response_get = f_run_halt_rsps$EMPTY_N ;
  assign CAN_FIRE_hart0_server_run_halt_response_get =
	     f_run_halt_rsps$EMPTY_N ;
  assign WILL_FIRE_hart0_server_run_halt_response_get =
	     EN_hart0_server_run_halt_response_get ;

  // action method hart0_put_other_req_put
  assign RDY_hart0_put_other_req_put = 1'd1 ;
  assign CAN_FIRE_hart0_put_other_req_put = 1'd1 ;
  assign WILL_FIRE_hart0_put_other_req_put = EN_hart0_put_other_req_put ;

  // action method hart0_gpr_mem_server_request_put
  assign RDY_hart0_gpr_mem_server_request_put = f_gpr_reqs$FULL_N ;
  assign CAN_FIRE_hart0_gpr_mem_server_request_put = f_gpr_reqs$FULL_N ;
  assign WILL_FIRE_hart0_gpr_mem_server_request_put =
	     EN_hart0_gpr_mem_server_request_put ;

  // actionvalue method hart0_gpr_mem_server_response_get
  assign hart0_gpr_mem_server_response_get = f_gpr_rsps$D_OUT ;
  assign RDY_hart0_gpr_mem_server_response_get = f_gpr_rsps$EMPTY_N ;
  assign CAN_FIRE_hart0_gpr_mem_server_response_get = f_gpr_rsps$EMPTY_N ;
  assign WILL_FIRE_hart0_gpr_mem_server_response_get =
	     EN_hart0_gpr_mem_server_response_get ;

  // action method hart0_csr_mem_server_request_put
  assign RDY_hart0_csr_mem_server_request_put = f_csr_reqs$FULL_N ;
  assign CAN_FIRE_hart0_csr_mem_server_request_put = f_csr_reqs$FULL_N ;
  assign WILL_FIRE_hart0_csr_mem_server_request_put =
	     EN_hart0_csr_mem_server_request_put ;

  // actionvalue method hart0_csr_mem_server_response_get
  assign hart0_csr_mem_server_response_get = f_csr_rsps$D_OUT ;
  assign RDY_hart0_csr_mem_server_response_get = f_csr_rsps$EMPTY_N ;
  assign CAN_FIRE_hart0_csr_mem_server_response_get = f_csr_rsps$EMPTY_N ;
  assign WILL_FIRE_hart0_csr_mem_server_response_get =
	     EN_hart0_csr_mem_server_response_get ;

  // submodule csr_regfile
  mkCSR_RegFile csr_regfile(.CLK(CLK),
			    .RST_N(RST_N),
			    .access_permitted_1_csr_addr(csr_regfile$access_permitted_1_csr_addr),
			    .access_permitted_1_priv(csr_regfile$access_permitted_1_priv),
			    .access_permitted_1_read_not_write(csr_regfile$access_permitted_1_read_not_write),
			    .access_permitted_2_csr_addr(csr_regfile$access_permitted_2_csr_addr),
			    .access_permitted_2_priv(csr_regfile$access_permitted_2_priv),
			    .access_permitted_2_read_not_write(csr_regfile$access_permitted_2_read_not_write),
			    .csr_counter_read_fault_csr_addr(csr_regfile$csr_counter_read_fault_csr_addr),
			    .csr_counter_read_fault_priv(csr_regfile$csr_counter_read_fault_priv),
			    .csr_ret_actions_from_priv(csr_regfile$csr_ret_actions_from_priv),
			    .csr_trap_actions_exc_code(csr_regfile$csr_trap_actions_exc_code),
			    .csr_trap_actions_from_priv(csr_regfile$csr_trap_actions_from_priv),
			    .csr_trap_actions_interrupt(csr_regfile$csr_trap_actions_interrupt),
			    .csr_trap_actions_nmi(csr_regfile$csr_trap_actions_nmi),
			    .csr_trap_actions_pc(csr_regfile$csr_trap_actions_pc),
			    .csr_trap_actions_xtval(csr_regfile$csr_trap_actions_xtval),
			    .dcsr_break_enters_debug_cur_priv(csr_regfile$dcsr_break_enters_debug_cur_priv),
			    .interrupt_pending_cur_priv(csr_regfile$interrupt_pending_cur_priv),
			    .m_external_interrupt_req_set_not_clear(csr_regfile$m_external_interrupt_req_set_not_clear),
			    .mav_csr_write_csr_addr(csr_regfile$mav_csr_write_csr_addr),
			    .mav_csr_write_word(csr_regfile$mav_csr_write_word),
			    .mav_read_csr_csr_addr(csr_regfile$mav_read_csr_csr_addr),
			    .nmi_req_set_not_clear(csr_regfile$nmi_req_set_not_clear),
			    .read_csr_csr_addr(csr_regfile$read_csr_csr_addr),
			    .read_csr_port2_csr_addr(csr_regfile$read_csr_port2_csr_addr),
			    .s_external_interrupt_req_set_not_clear(csr_regfile$s_external_interrupt_req_set_not_clear),
			    .software_interrupt_req_set_not_clear(csr_regfile$software_interrupt_req_set_not_clear),
			    .timer_interrupt_req_set_not_clear(csr_regfile$timer_interrupt_req_set_not_clear),
			    .write_dcsr_cause_priv_cause(csr_regfile$write_dcsr_cause_priv_cause),
			    .write_dcsr_cause_priv_priv(csr_regfile$write_dcsr_cause_priv_priv),
			    .write_dpc_pc(csr_regfile$write_dpc_pc),
			    .EN_server_reset_request_put(csr_regfile$EN_server_reset_request_put),
			    .EN_server_reset_response_get(csr_regfile$EN_server_reset_response_get),
			    .EN_mav_read_csr(csr_regfile$EN_mav_read_csr),
			    .EN_mav_csr_write(csr_regfile$EN_mav_csr_write),
			    .EN_csr_trap_actions(csr_regfile$EN_csr_trap_actions),
			    .EN_csr_ret_actions(csr_regfile$EN_csr_ret_actions),
			    .EN_csr_minstret_incr(csr_regfile$EN_csr_minstret_incr),
			    .EN_write_dpc(csr_regfile$EN_write_dpc),
			    .EN_write_dcsr_cause_priv(csr_regfile$EN_write_dcsr_cause_priv),
			    .EN_debug(csr_regfile$EN_debug),
			    .RDY_server_reset_request_put(csr_regfile$RDY_server_reset_request_put),
			    .RDY_server_reset_response_get(csr_regfile$RDY_server_reset_response_get),
			    .read_csr(csr_regfile$read_csr),
			    .read_csr_port2(csr_regfile$read_csr_port2),
			    .mav_read_csr(),
			    .mav_csr_write(csr_regfile$mav_csr_write),
			    .read_misa(csr_regfile$read_misa),
			    .read_mstatus(csr_regfile$read_mstatus),
			    .read_ustatus(),
			    .read_satp(csr_regfile$read_satp),
			    .csr_trap_actions(csr_regfile$csr_trap_actions),
			    .RDY_csr_trap_actions(),
			    .csr_ret_actions(csr_regfile$csr_ret_actions),
			    .RDY_csr_ret_actions(),
			    .read_csr_minstret(csr_regfile$read_csr_minstret),
			    .read_csr_mcycle(csr_regfile$read_csr_mcycle),
			    .read_csr_mtime(),
			    .access_permitted_1(csr_regfile$access_permitted_1),
			    .access_permitted_2(csr_regfile$access_permitted_2),
			    .csr_counter_read_fault(),
			    .csr_mip_read(csr_regfile$csr_mip_read),
			    .interrupt_pending(csr_regfile$interrupt_pending),
			    .wfi_resume(csr_regfile$wfi_resume),
			    .nmi_pending(csr_regfile$nmi_pending),
			    .read_dpc(csr_regfile$read_dpc),
			    .RDY_read_dpc(),
			    .RDY_write_dpc(),
			    .dcsr_break_enters_debug(csr_regfile$dcsr_break_enters_debug),
			    .RDY_dcsr_break_enters_debug(),
			    .read_dcsr_step(csr_regfile$read_dcsr_step),
			    .RDY_read_dcsr_step(),
			    .RDY_debug());

  // submodule f_csr_reqs
  FIFO2 #(.width(32'd45), .guarded(32'd1)) f_csr_reqs(.RST(RST_N),
						      .CLK(CLK),
						      .D_IN(f_csr_reqs$D_IN),
						      .ENQ(f_csr_reqs$ENQ),
						      .DEQ(f_csr_reqs$DEQ),
						      .CLR(f_csr_reqs$CLR),
						      .D_OUT(f_csr_reqs$D_OUT),
						      .FULL_N(f_csr_reqs$FULL_N),
						      .EMPTY_N(f_csr_reqs$EMPTY_N));

  // submodule f_csr_rsps
  FIFO2 #(.width(32'd33), .guarded(32'd1)) f_csr_rsps(.RST(RST_N),
						      .CLK(CLK),
						      .D_IN(f_csr_rsps$D_IN),
						      .ENQ(f_csr_rsps$ENQ),
						      .DEQ(f_csr_rsps$DEQ),
						      .CLR(f_csr_rsps$CLR),
						      .D_OUT(f_csr_rsps$D_OUT),
						      .FULL_N(f_csr_rsps$FULL_N),
						      .EMPTY_N(f_csr_rsps$EMPTY_N));

  // submodule f_gpr_reqs
  FIFO2 #(.width(32'd38), .guarded(32'd1)) f_gpr_reqs(.RST(RST_N),
						      .CLK(CLK),
						      .D_IN(f_gpr_reqs$D_IN),
						      .ENQ(f_gpr_reqs$ENQ),
						      .DEQ(f_gpr_reqs$DEQ),
						      .CLR(f_gpr_reqs$CLR),
						      .D_OUT(f_gpr_reqs$D_OUT),
						      .FULL_N(f_gpr_reqs$FULL_N),
						      .EMPTY_N(f_gpr_reqs$EMPTY_N));

  // submodule f_gpr_rsps
  FIFO2 #(.width(32'd33), .guarded(32'd1)) f_gpr_rsps(.RST(RST_N),
						      .CLK(CLK),
						      .D_IN(f_gpr_rsps$D_IN),
						      .ENQ(f_gpr_rsps$ENQ),
						      .DEQ(f_gpr_rsps$DEQ),
						      .CLR(f_gpr_rsps$CLR),
						      .D_OUT(f_gpr_rsps$D_OUT),
						      .FULL_N(f_gpr_rsps$FULL_N),
						      .EMPTY_N(f_gpr_rsps$EMPTY_N));

  // submodule f_reset_reqs
  FIFO2 #(.width(32'd1), .guarded(32'd1)) f_reset_reqs(.RST(RST_N),
						       .CLK(CLK),
						       .D_IN(f_reset_reqs$D_IN),
						       .ENQ(f_reset_reqs$ENQ),
						       .DEQ(f_reset_reqs$DEQ),
						       .CLR(f_reset_reqs$CLR),
						       .D_OUT(f_reset_reqs$D_OUT),
						       .FULL_N(f_reset_reqs$FULL_N),
						       .EMPTY_N(f_reset_reqs$EMPTY_N));

  // submodule f_reset_rsps
  FIFO2 #(.width(32'd1), .guarded(32'd1)) f_reset_rsps(.RST(RST_N),
						       .CLK(CLK),
						       .D_IN(f_reset_rsps$D_IN),
						       .ENQ(f_reset_rsps$ENQ),
						       .DEQ(f_reset_rsps$DEQ),
						       .CLR(f_reset_rsps$CLR),
						       .D_OUT(f_reset_rsps$D_OUT),
						       .FULL_N(f_reset_rsps$FULL_N),
						       .EMPTY_N(f_reset_rsps$EMPTY_N));

  // submodule f_run_halt_reqs
  FIFO2 #(.width(32'd1), .guarded(32'd1)) f_run_halt_reqs(.RST(RST_N),
							  .CLK(CLK),
							  .D_IN(f_run_halt_reqs$D_IN),
							  .ENQ(f_run_halt_reqs$ENQ),
							  .DEQ(f_run_halt_reqs$DEQ),
							  .CLR(f_run_halt_reqs$CLR),
							  .D_OUT(f_run_halt_reqs$D_OUT),
							  .FULL_N(f_run_halt_reqs$FULL_N),
							  .EMPTY_N(f_run_halt_reqs$EMPTY_N));

  // submodule f_run_halt_rsps
  FIFO2 #(.width(32'd1), .guarded(32'd1)) f_run_halt_rsps(.RST(RST_N),
							  .CLK(CLK),
							  .D_IN(f_run_halt_rsps$D_IN),
							  .ENQ(f_run_halt_rsps$ENQ),
							  .DEQ(f_run_halt_rsps$DEQ),
							  .CLR(f_run_halt_rsps$CLR),
							  .D_OUT(f_run_halt_rsps$D_OUT),
							  .FULL_N(f_run_halt_rsps$FULL_N),
							  .EMPTY_N(f_run_halt_rsps$EMPTY_N));

  // submodule f_trace_data
  FIFO2 #(.width(32'd235), .guarded(32'd1)) f_trace_data(.RST(RST_N),
							 .CLK(CLK),
							 .D_IN(f_trace_data$D_IN),
							 .ENQ(f_trace_data$ENQ),
							 .DEQ(f_trace_data$DEQ),
							 .CLR(f_trace_data$CLR),
							 .D_OUT(f_trace_data$D_OUT),
							 .FULL_N(f_trace_data$FULL_N),
							 .EMPTY_N(f_trace_data$EMPTY_N));

  // submodule gpr_regfile
  mkGPR_RegFile gpr_regfile(.CLK(CLK),
			    .RST_N(RST_N),
			    .read_rs1_port2_rs1(gpr_regfile$read_rs1_port2_rs1),
			    .read_rs1_rs1(gpr_regfile$read_rs1_rs1),
			    .read_rs2_rs2(gpr_regfile$read_rs2_rs2),
			    .write_rd_rd(gpr_regfile$write_rd_rd),
			    .write_rd_rd_val(gpr_regfile$write_rd_rd_val),
			    .EN_server_reset_request_put(gpr_regfile$EN_server_reset_request_put),
			    .EN_server_reset_response_get(gpr_regfile$EN_server_reset_response_get),
			    .EN_write_rd(gpr_regfile$EN_write_rd),
			    .RDY_server_reset_request_put(gpr_regfile$RDY_server_reset_request_put),
			    .RDY_server_reset_response_get(gpr_regfile$RDY_server_reset_response_get),
			    .read_rs1(gpr_regfile$read_rs1),
			    .read_rs1_port2(gpr_regfile$read_rs1_port2),
			    .read_rs2(gpr_regfile$read_rs2));

  // submodule near_mem
  mkNear_Mem near_mem(.CLK(CLK),
		      .RST_N(RST_N),
		      .dmem_master_arready(near_mem$dmem_master_arready),
		      .dmem_master_awready(near_mem$dmem_master_awready),
		      .dmem_master_bid(near_mem$dmem_master_bid),
		      .dmem_master_bresp(near_mem$dmem_master_bresp),
		      .dmem_master_bvalid(near_mem$dmem_master_bvalid),
		      .dmem_master_rdata(near_mem$dmem_master_rdata),
		      .dmem_master_rid(near_mem$dmem_master_rid),
		      .dmem_master_rlast(near_mem$dmem_master_rlast),
		      .dmem_master_rresp(near_mem$dmem_master_rresp),
		      .dmem_master_rvalid(near_mem$dmem_master_rvalid),
		      .dmem_master_wready(near_mem$dmem_master_wready),
		      .dmem_req_addr(near_mem$dmem_req_addr),
		      .dmem_req_amo_funct7(near_mem$dmem_req_amo_funct7),
		      .dmem_req_f3(near_mem$dmem_req_f3),
		      .dmem_req_mstatus_MXR(near_mem$dmem_req_mstatus_MXR),
		      .dmem_req_op(near_mem$dmem_req_op),
		      .dmem_req_priv(near_mem$dmem_req_priv),
		      .dmem_req_satp(near_mem$dmem_req_satp),
		      .dmem_req_sstatus_SUM(near_mem$dmem_req_sstatus_SUM),
		      .dmem_req_store_value(near_mem$dmem_req_store_value),
		      .imem_master_arready(near_mem$imem_master_arready),
		      .imem_master_awready(near_mem$imem_master_awready),
		      .imem_master_bid(near_mem$imem_master_bid),
		      .imem_master_bresp(near_mem$imem_master_bresp),
		      .imem_master_bvalid(near_mem$imem_master_bvalid),
		      .imem_master_rdata(near_mem$imem_master_rdata),
		      .imem_master_rid(near_mem$imem_master_rid),
		      .imem_master_rlast(near_mem$imem_master_rlast),
		      .imem_master_rresp(near_mem$imem_master_rresp),
		      .imem_master_rvalid(near_mem$imem_master_rvalid),
		      .imem_master_wready(near_mem$imem_master_wready),
		      .imem_req_addr(near_mem$imem_req_addr),
		      .imem_req_f3(near_mem$imem_req_f3),
		      .imem_req_mstatus_MXR(near_mem$imem_req_mstatus_MXR),
		      .imem_req_priv(near_mem$imem_req_priv),
		      .imem_req_satp(near_mem$imem_req_satp),
		      .imem_req_sstatus_SUM(near_mem$imem_req_sstatus_SUM),
		      .server_fence_request_put(near_mem$server_fence_request_put),
		      .EN_server_reset_request_put(near_mem$EN_server_reset_request_put),
		      .EN_server_reset_response_get(near_mem$EN_server_reset_response_get),
		      .EN_imem_req(near_mem$EN_imem_req),
		      .EN_dmem_req(near_mem$EN_dmem_req),
		      .EN_server_fence_i_request_put(near_mem$EN_server_fence_i_request_put),
		      .EN_server_fence_i_response_get(near_mem$EN_server_fence_i_response_get),
		      .EN_server_fence_request_put(near_mem$EN_server_fence_request_put),
		      .EN_server_fence_response_get(near_mem$EN_server_fence_response_get),
		      .EN_sfence_vma(near_mem$EN_sfence_vma),
		      .RDY_server_reset_request_put(near_mem$RDY_server_reset_request_put),
		      .RDY_server_reset_response_get(near_mem$RDY_server_reset_response_get),
		      .imem_valid(near_mem$imem_valid),
		      .imem_is_i32_not_i16(near_mem$imem_is_i32_not_i16),
		      .imem_pc(near_mem$imem_pc),
		      .imem_instr(near_mem$imem_instr),
		      .imem_exc(near_mem$imem_exc),
		      .imem_exc_code(near_mem$imem_exc_code),
		      .imem_tval(),
		      .imem_master_awvalid(near_mem$imem_master_awvalid),
		      .imem_master_awid(near_mem$imem_master_awid),
		      .imem_master_awaddr(near_mem$imem_master_awaddr),
		      .imem_master_awlen(near_mem$imem_master_awlen),
		      .imem_master_awsize(near_mem$imem_master_awsize),
		      .imem_master_awburst(near_mem$imem_master_awburst),
		      .imem_master_awlock(near_mem$imem_master_awlock),
		      .imem_master_awcache(near_mem$imem_master_awcache),
		      .imem_master_awprot(near_mem$imem_master_awprot),
		      .imem_master_awqos(near_mem$imem_master_awqos),
		      .imem_master_awregion(near_mem$imem_master_awregion),
		      .imem_master_wvalid(near_mem$imem_master_wvalid),
		      .imem_master_wdata(near_mem$imem_master_wdata),
		      .imem_master_wstrb(near_mem$imem_master_wstrb),
		      .imem_master_wlast(near_mem$imem_master_wlast),
		      .imem_master_bready(near_mem$imem_master_bready),
		      .imem_master_arvalid(near_mem$imem_master_arvalid),
		      .imem_master_arid(near_mem$imem_master_arid),
		      .imem_master_araddr(near_mem$imem_master_araddr),
		      .imem_master_arlen(near_mem$imem_master_arlen),
		      .imem_master_arsize(near_mem$imem_master_arsize),
		      .imem_master_arburst(near_mem$imem_master_arburst),
		      .imem_master_arlock(near_mem$imem_master_arlock),
		      .imem_master_arcache(near_mem$imem_master_arcache),
		      .imem_master_arprot(near_mem$imem_master_arprot),
		      .imem_master_arqos(near_mem$imem_master_arqos),
		      .imem_master_arregion(near_mem$imem_master_arregion),
		      .imem_master_rready(near_mem$imem_master_rready),
		      .dmem_valid(near_mem$dmem_valid),
		      .dmem_word64(near_mem$dmem_word64),
		      .dmem_st_amo_val(),
		      .dmem_exc(near_mem$dmem_exc),
		      .dmem_exc_code(near_mem$dmem_exc_code),
		      .dmem_master_awvalid(near_mem$dmem_master_awvalid),
		      .dmem_master_awid(near_mem$dmem_master_awid),
		      .dmem_master_awaddr(near_mem$dmem_master_awaddr),
		      .dmem_master_awlen(near_mem$dmem_master_awlen),
		      .dmem_master_awsize(near_mem$dmem_master_awsize),
		      .dmem_master_awburst(near_mem$dmem_master_awburst),
		      .dmem_master_awlock(near_mem$dmem_master_awlock),
		      .dmem_master_awcache(near_mem$dmem_master_awcache),
		      .dmem_master_awprot(near_mem$dmem_master_awprot),
		      .dmem_master_awqos(near_mem$dmem_master_awqos),
		      .dmem_master_awregion(near_mem$dmem_master_awregion),
		      .dmem_master_wvalid(near_mem$dmem_master_wvalid),
		      .dmem_master_wdata(near_mem$dmem_master_wdata),
		      .dmem_master_wstrb(near_mem$dmem_master_wstrb),
		      .dmem_master_wlast(near_mem$dmem_master_wlast),
		      .dmem_master_bready(near_mem$dmem_master_bready),
		      .dmem_master_arvalid(near_mem$dmem_master_arvalid),
		      .dmem_master_arid(near_mem$dmem_master_arid),
		      .dmem_master_araddr(near_mem$dmem_master_araddr),
		      .dmem_master_arlen(near_mem$dmem_master_arlen),
		      .dmem_master_arsize(near_mem$dmem_master_arsize),
		      .dmem_master_arburst(near_mem$dmem_master_arburst),
		      .dmem_master_arlock(near_mem$dmem_master_arlock),
		      .dmem_master_arcache(near_mem$dmem_master_arcache),
		      .dmem_master_arprot(near_mem$dmem_master_arprot),
		      .dmem_master_arqos(near_mem$dmem_master_arqos),
		      .dmem_master_arregion(near_mem$dmem_master_arregion),
		      .dmem_master_rready(near_mem$dmem_master_rready),
		      .RDY_server_fence_i_request_put(near_mem$RDY_server_fence_i_request_put),
		      .RDY_server_fence_i_response_get(near_mem$RDY_server_fence_i_response_get),
		      .RDY_server_fence_request_put(near_mem$RDY_server_fence_request_put),
		      .RDY_server_fence_response_get(near_mem$RDY_server_fence_response_get),
		      .RDY_sfence_vma());

  // submodule soc_map
  mkSoC_Map soc_map(.CLK(CLK),
		    .RST_N(RST_N),
		    .m_is_IO_addr_addr(soc_map$m_is_IO_addr_addr),
		    .m_is_mem_addr_addr(soc_map$m_is_mem_addr_addr),
		    .m_is_near_mem_IO_addr_addr(soc_map$m_is_near_mem_IO_addr_addr),
		    .m_plic_addr_base(),
		    .m_plic_addr_size(),
		    .m_plic_addr_lim(),
		    .m_near_mem_io_addr_base(),
		    .m_near_mem_io_addr_size(),
		    .m_near_mem_io_addr_lim(),
		    .m_flash_mem_addr_base(),
		    .m_flash_mem_addr_size(),
		    .m_flash_mem_addr_lim(),
		    .m_ethernet_0_addr_base(),
		    .m_ethernet_0_addr_size(),
		    .m_ethernet_0_addr_lim(),
		    .m_dma_0_addr_base(),
		    .m_dma_0_addr_size(),
		    .m_dma_0_addr_lim(),
		    .m_uart16550_0_addr_base(),
		    .m_uart16550_0_addr_size(),
		    .m_uart16550_0_addr_lim(),
		    .m_gpio_0_addr_base(),
		    .m_gpio_0_addr_size(),
		    .m_gpio_0_addr_lim(),
		    .m_boot_rom_addr_base(),
		    .m_boot_rom_addr_size(),
		    .m_boot_rom_addr_lim(),
		    .m_ddr4_0_uncached_addr_base(),
		    .m_ddr4_0_uncached_addr_size(),
		    .m_ddr4_0_uncached_addr_lim(),
		    .m_ddr4_0_cached_addr_base(),
		    .m_ddr4_0_cached_addr_size(),
		    .m_ddr4_0_cached_addr_lim(),
		    .m_is_mem_addr(),
		    .m_is_IO_addr(),
		    .m_is_near_mem_IO_addr(),
		    .m_pc_reset_value(soc_map$m_pc_reset_value),
		    .m_mtvec_reset_value(),
		    .m_nmivec_reset_value());

  // submodule stage1_f_reset_reqs
  FIFO20 #(.guarded(32'd1)) stage1_f_reset_reqs(.RST(RST_N),
						.CLK(CLK),
						.ENQ(stage1_f_reset_reqs$ENQ),
						.DEQ(stage1_f_reset_reqs$DEQ),
						.CLR(stage1_f_reset_reqs$CLR),
						.FULL_N(stage1_f_reset_reqs$FULL_N),
						.EMPTY_N(stage1_f_reset_reqs$EMPTY_N));

  // submodule stage1_f_reset_rsps
  FIFO20 #(.guarded(32'd1)) stage1_f_reset_rsps(.RST(RST_N),
						.CLK(CLK),
						.ENQ(stage1_f_reset_rsps$ENQ),
						.DEQ(stage1_f_reset_rsps$DEQ),
						.CLR(stage1_f_reset_rsps$CLR),
						.FULL_N(stage1_f_reset_rsps$FULL_N),
						.EMPTY_N(stage1_f_reset_rsps$EMPTY_N));

  // submodule stage2_f_reset_reqs
  FIFO20 #(.guarded(32'd1)) stage2_f_reset_reqs(.RST(RST_N),
						.CLK(CLK),
						.ENQ(stage2_f_reset_reqs$ENQ),
						.DEQ(stage2_f_reset_reqs$DEQ),
						.CLR(stage2_f_reset_reqs$CLR),
						.FULL_N(stage2_f_reset_reqs$FULL_N),
						.EMPTY_N(stage2_f_reset_reqs$EMPTY_N));

  // submodule stage2_f_reset_rsps
  FIFO20 #(.guarded(32'd1)) stage2_f_reset_rsps(.RST(RST_N),
						.CLK(CLK),
						.ENQ(stage2_f_reset_rsps$ENQ),
						.DEQ(stage2_f_reset_rsps$DEQ),
						.CLR(stage2_f_reset_rsps$CLR),
						.FULL_N(stage2_f_reset_rsps$FULL_N),
						.EMPTY_N(stage2_f_reset_rsps$EMPTY_N));

  // submodule stage2_mbox
  mkRISCV_MBox stage2_mbox(.CLK(CLK),
			   .RST_N(RST_N),
			   .req_f3(stage2_mbox$req_f3),
			   .req_is_OP_not_OP_32(stage2_mbox$req_is_OP_not_OP_32),
			   .req_v1(stage2_mbox$req_v1),
			   .req_v2(stage2_mbox$req_v2),
			   .set_verbosity_verbosity(stage2_mbox$set_verbosity_verbosity),
			   .EN_set_verbosity(stage2_mbox$EN_set_verbosity),
			   .EN_req_reset(stage2_mbox$EN_req_reset),
			   .EN_rsp_reset(stage2_mbox$EN_rsp_reset),
			   .EN_req(stage2_mbox$EN_req),
			   .RDY_set_verbosity(),
			   .RDY_req_reset(),
			   .RDY_rsp_reset(),
			   .valid(stage2_mbox$valid),
			   .word(stage2_mbox$word));

  // submodule stage3_f_reset_reqs
  FIFO20 #(.guarded(32'd1)) stage3_f_reset_reqs(.RST(RST_N),
						.CLK(CLK),
						.ENQ(stage3_f_reset_reqs$ENQ),
						.DEQ(stage3_f_reset_reqs$DEQ),
						.CLR(stage3_f_reset_reqs$CLR),
						.FULL_N(stage3_f_reset_reqs$FULL_N),
						.EMPTY_N(stage3_f_reset_reqs$EMPTY_N));

  // submodule stage3_f_reset_rsps
  FIFO20 #(.guarded(32'd1)) stage3_f_reset_rsps(.RST(RST_N),
						.CLK(CLK),
						.ENQ(stage3_f_reset_rsps$ENQ),
						.DEQ(stage3_f_reset_rsps$DEQ),
						.CLR(stage3_f_reset_rsps$CLR),
						.FULL_N(stage3_f_reset_rsps$FULL_N),
						.EMPTY_N(stage3_f_reset_rsps$EMPTY_N));

  // rule RL_rl_show_pipe
  assign CAN_FIRE_RL_rl_show_pipe =
	     NOT_IF_csr_regfile_read_csr_minstret__7_ULT_cf_ETC___d43 &&
	     rg_state != 4'd0 &&
	     rg_state != 4'd1 &&
	     rg_state != 4'd2 &&
	     rg_state != 4'd3 &&
	     rg_state != 4'd13 ;
  assign WILL_FIRE_RL_rl_show_pipe = CAN_FIRE_RL_rl_show_pipe ;

  // rule RL_rl_stage1_mip_cmd
  assign CAN_FIRE_RL_rl_stage1_mip_cmd =
	     f_trace_data$FULL_N && rg_state == 4'd4 &&
	     stage1_rg_full_03_AND_near_mem_imem_valid_AND__ETC___d1116 &&
	     !stage3_rg_full &&
	     !csr_regfile_csr_mip_read__118_EQ_rg_prev_mip_119___d1120 ;
  assign WILL_FIRE_RL_rl_stage1_mip_cmd = CAN_FIRE_RL_rl_stage1_mip_cmd ;

  // rule RL_rl_stage1_SFENCE_VMA
  assign CAN_FIRE_RL_rl_stage1_SFENCE_VMA =
	     f_trace_data$FULL_N &&
	     rg_state_4_EQ_4_112_AND_NOT_near_mem_imem_exc__ETC___d1394 &&
	     IF_NOT_stage1_rg_full_03_04_OR_NOT_near_mem_im_ETC___d775 ==
	     4'd6 ;
  assign WILL_FIRE_RL_rl_stage1_SFENCE_VMA =
	     CAN_FIRE_RL_rl_stage1_SFENCE_VMA ;

  // rule RL_rl_debug_run_redundant
  assign CAN_FIRE_RL_rl_debug_run_redundant =
	     f_run_halt_rsps$FULL_N && f_run_halt_reqs$EMPTY_N &&
	     f_run_halt_reqs$D_OUT &&
	     rg_state != 4'd0 &&
	     rg_state != 4'd1 &&
	     rg_state != 4'd2 &&
	     rg_state != 4'd3 ;
  assign WILL_FIRE_RL_rl_debug_run_redundant =
	     CAN_FIRE_RL_rl_debug_run_redundant &&
	     !WILL_FIRE_RL_rl_trap_BREAK_to_Debug_Mode ;

  // rule RL_rl_debug_halt_redundant
  assign CAN_FIRE_RL_rl_debug_halt_redundant =
	     f_run_halt_rsps$FULL_N && f_run_halt_reqs$EMPTY_N &&
	     !f_run_halt_reqs$D_OUT &&
	     (rg_state == 4'd0 || rg_state == 4'd1 || rg_state == 4'd2 ||
	      rg_state == 4'd3) ;
  assign WILL_FIRE_RL_rl_debug_halt_redundant =
	     CAN_FIRE_RL_rl_debug_halt_redundant &&
	     !WILL_FIRE_RL_rl_BREAK_cache_flush_finish ;

  // rule RL_rl_debug_read_gpr
  assign CAN_FIRE_RL_rl_debug_read_gpr =
	     f_gpr_reqs$EMPTY_N && f_gpr_rsps$FULL_N && rg_state == 4'd3 &&
	     !f_gpr_reqs$D_OUT[37] ;
  assign WILL_FIRE_RL_rl_debug_read_gpr = CAN_FIRE_RL_rl_debug_read_gpr ;

  // rule RL_rl_debug_write_gpr
  assign CAN_FIRE_RL_rl_debug_write_gpr =
	     f_gpr_reqs$EMPTY_N && f_gpr_rsps$FULL_N && rg_state == 4'd3 &&
	     f_gpr_reqs$D_OUT[37] ;
  assign WILL_FIRE_RL_rl_debug_write_gpr = CAN_FIRE_RL_rl_debug_write_gpr ;

  // rule RL_rl_debug_gpr_access_busy
  assign CAN_FIRE_RL_rl_debug_gpr_access_busy =
	     f_gpr_reqs$EMPTY_N && f_gpr_rsps$FULL_N && rg_state != 4'd3 ;
  assign WILL_FIRE_RL_rl_debug_gpr_access_busy =
	     CAN_FIRE_RL_rl_debug_gpr_access_busy ;

  // rule RL_rl_debug_read_csr
  assign CAN_FIRE_RL_rl_debug_read_csr =
	     f_csr_reqs$EMPTY_N && f_csr_rsps$FULL_N && rg_state == 4'd3 &&
	     !f_csr_reqs$D_OUT[44] ;
  assign WILL_FIRE_RL_rl_debug_read_csr = CAN_FIRE_RL_rl_debug_read_csr ;

  // rule RL_rl_debug_run
  assign CAN_FIRE_RL_rl_debug_run =
	     imem_rg_pc_BITS_1_TO_0_EQ_0b0_OR_NOT_near_mem__ETC___d1085 &&
	     f_run_halt_rsps$FULL_N &&
	     f_run_halt_reqs$EMPTY_N &&
	     f_run_halt_reqs$D_OUT &&
	     rg_state == 4'd3 ;
  assign WILL_FIRE_RL_rl_debug_run =
	     CAN_FIRE_RL_rl_debug_run &&
	     !WILL_FIRE_RL_rl_reset_from_Debug_Module ;

  // rule RL_rl_debug_write_csr
  assign CAN_FIRE_RL_rl_debug_write_csr =
	     f_csr_reqs$EMPTY_N && f_csr_rsps$FULL_N && rg_state == 4'd3 &&
	     f_csr_reqs$D_OUT[44] ;
  assign WILL_FIRE_RL_rl_debug_write_csr =
	     CAN_FIRE_RL_rl_debug_write_csr && !WILL_FIRE_RL_rl_debug_run ;

  // rule RL_rl_debug_csr_access_busy
  assign CAN_FIRE_RL_rl_debug_csr_access_busy =
	     f_csr_reqs$EMPTY_N && f_csr_rsps$FULL_N && rg_state != 4'd3 ;
  assign WILL_FIRE_RL_rl_debug_csr_access_busy =
	     CAN_FIRE_RL_rl_debug_csr_access_busy ;

  // rule RL_rl_stage1_trap
  assign CAN_FIRE_RL_rl_stage1_trap =
	     rg_state_4_EQ_4_112_AND_NOT_near_mem_imem_exc__ETC___d1394 &&
	     IF_NOT_stage1_rg_full_03_04_OR_NOT_near_mem_im_ETC___d775 ==
	     4'd11 &&
	     (x_out_trap_info_exc_code__h14836 != 4'd3 ||
	      !csr_regfile$dcsr_break_enters_debug) ;
  assign WILL_FIRE_RL_rl_stage1_trap = CAN_FIRE_RL_rl_stage1_trap ;

  // rule RL_rl_stage1_CSRR_W
  assign CAN_FIRE_RL_rl_stage1_CSRR_W = MUX_rg_state$write_1__SEL_11 ;
  assign WILL_FIRE_RL_rl_stage1_CSRR_W = MUX_rg_state$write_1__SEL_11 ;

  // rule RL_rl_stage1_CSRR_S_or_C
  assign CAN_FIRE_RL_rl_stage1_CSRR_S_or_C = MUX_rg_state$write_1__SEL_12 ;
  assign WILL_FIRE_RL_rl_stage1_CSRR_S_or_C = MUX_rg_state$write_1__SEL_12 ;

  // rule RL_rl_stage1_xRET
  assign CAN_FIRE_RL_rl_stage1_xRET =
	     f_trace_data$FULL_N &&
	     rg_state_4_EQ_4_112_AND_NOT_near_mem_imem_exc__ETC___d1394 &&
	     (IF_NOT_stage1_rg_full_03_04_OR_NOT_near_mem_im_ETC___d775 ==
	      4'd7 ||
	      IF_NOT_stage1_rg_full_03_04_OR_NOT_near_mem_im_ETC___d775 ==
	      4'd8 ||
	      IF_NOT_stage1_rg_full_03_04_OR_NOT_near_mem_im_ETC___d775 ==
	      4'd9) ;
  assign WILL_FIRE_RL_rl_stage1_xRET = CAN_FIRE_RL_rl_stage1_xRET ;

  // rule RL_rl_stage1_FENCE_I
  assign CAN_FIRE_RL_rl_stage1_FENCE_I = MUX_rg_state$write_1__SEL_13 ;
  assign WILL_FIRE_RL_rl_stage1_FENCE_I = MUX_rg_state$write_1__SEL_13 ;

  // rule RL_rl_stage1_FENCE
  assign CAN_FIRE_RL_rl_stage1_FENCE =
	     near_mem$RDY_server_fence_request_put && f_trace_data$FULL_N &&
	     rg_state_4_EQ_4_112_AND_NOT_near_mem_imem_exc__ETC___d1394 &&
	     IF_NOT_stage1_rg_full_03_04_OR_NOT_near_mem_im_ETC___d775 ==
	     4'd4 ;
  assign WILL_FIRE_RL_rl_stage1_FENCE = CAN_FIRE_RL_rl_stage1_FENCE ;

  // rule RL_rl_stage1_WFI
  assign CAN_FIRE_RL_rl_stage1_WFI =
	     f_trace_data$FULL_N &&
	     rg_state_4_EQ_4_112_AND_NOT_near_mem_imem_exc__ETC___d1394 &&
	     IF_NOT_stage1_rg_full_03_04_OR_NOT_near_mem_im_ETC___d775 ==
	     4'd10 ;
  assign WILL_FIRE_RL_rl_stage1_WFI = CAN_FIRE_RL_rl_stage1_WFI ;

  // rule RL_rl_WFI_resume
  assign CAN_FIRE_RL_rl_WFI_resume =
	     imem_rg_pc_BITS_1_TO_0_EQ_0b0_OR_NOT_near_mem__ETC___d1085 &&
	     rg_state == 4'd13 &&
	     (csr_regfile$wfi_resume || rg_stop_req || rg_step_count) &&
	     (!stage1_rg_full ||
	      near_mem_imem_valid_AND_NOT_imem_rg_pc_BITS_1__ETC___d513) ;
  assign WILL_FIRE_RL_rl_WFI_resume = CAN_FIRE_RL_rl_WFI_resume ;

  // rule RL_rl_trap_BREAK_to_Debug_Mode
  assign CAN_FIRE_RL_rl_trap_BREAK_to_Debug_Mode =
	     near_mem$RDY_server_fence_i_request_put &&
	     f_run_halt_rsps$FULL_N &&
	     rg_state_4_EQ_4_112_AND_NOT_near_mem_imem_exc__ETC___d1394 &&
	     IF_NOT_stage1_rg_full_03_04_OR_NOT_near_mem_im_ETC___d775 ==
	     4'd11 &&
	     x_out_trap_info_exc_code__h14836 == 4'd3 &&
	     csr_regfile$dcsr_break_enters_debug ;
  assign WILL_FIRE_RL_rl_trap_BREAK_to_Debug_Mode =
	     CAN_FIRE_RL_rl_trap_BREAK_to_Debug_Mode ;

  // rule RL_rl_BREAK_cache_flush_finish
  assign CAN_FIRE_RL_rl_BREAK_cache_flush_finish =
	     MUX_rg_state$write_1__SEL_7 ;
  assign WILL_FIRE_RL_rl_BREAK_cache_flush_finish =
	     MUX_rg_state$write_1__SEL_7 ;

  // rule RL_rl_stage1_stop
  assign CAN_FIRE_RL_rl_stage1_stop =
	     near_mem$RDY_server_fence_i_request_put &&
	     rg_state_4_EQ_4_112_AND_rg_stop_req_138_OR_rg__ETC___d1581 ;
  assign WILL_FIRE_RL_rl_stage1_stop =
	     CAN_FIRE_RL_rl_stage1_stop &&
	     !WILL_FIRE_RL_rl_reset_from_Debug_Module ;

  // rule RL_imem_rl_assert_fail
  assign CAN_FIRE_RL_imem_rl_assert_fail = !near_mem$imem_is_i32_not_i16 ;
  assign WILL_FIRE_RL_imem_rl_assert_fail = CAN_FIRE_RL_imem_rl_assert_fail ;

  // rule RL_rl_reset_complete
  assign CAN_FIRE_RL_rl_reset_complete =
	     gpr_regfile$RDY_server_reset_response_get &&
	     near_mem$RDY_server_reset_response_get &&
	     csr_regfile_RDY_server_reset_response_get__076_ETC___d1091 &&
	     rg_state == 4'd1 ;
  assign WILL_FIRE_RL_rl_reset_complete = MUX_rg_state$write_1__SEL_1 ;

  // rule RL_rl_pipe
  assign CAN_FIRE_RL_rl_pipe =
	     (IF_stage2_rg_full_5_THEN_IF_stage2_rg_stage2_6_ETC___d126 !=
	      2'd2 ||
	      f_trace_data$FULL_N) &&
	     (stage1_rg_full_03_AND_imem_rg_pc_BITS_31_TO_2__ETC___d1141 ||
	      !csr_regfile_csr_mip_read__118_EQ_rg_prev_mip_119___d1120 ||
	      csr_regfile_interrupt_pending_rg_cur_priv_1_14_ETC___d1147 ||
	      IF_IF_imem_rg_pc_BITS_1_TO_0_EQ_0b0_OR_NOT_ime_ETC___d1160 ||
	      imem_rg_pc_BITS_1_TO_0_EQ_0b0_OR_NOT_near_mem__ETC___d1085) &&
	     rg_state_4_EQ_4_112_AND_stage3_rg_full_6_OR_NO_ETC___d1187 ;
  assign WILL_FIRE_RL_rl_pipe =
	     CAN_FIRE_RL_rl_pipe && !WILL_FIRE_RL_imem_rl_fetch_next_32b ;

  // rule RL_rl_debug_halt
  assign CAN_FIRE_RL_rl_debug_halt =
	     f_run_halt_reqs$EMPTY_N && !f_run_halt_reqs$D_OUT &&
	     rg_state != 4'd0 &&
	     rg_state != 4'd1 &&
	     rg_state != 4'd2 &&
	     rg_state != 4'd3 ;
  assign WILL_FIRE_RL_rl_debug_halt =
	     CAN_FIRE_RL_rl_debug_halt && !WILL_FIRE_RL_rl_stage1_stop &&
	     !WILL_FIRE_RL_rl_trap_BREAK_to_Debug_Mode &&
	     !WILL_FIRE_RL_rl_WFI_resume &&
	     !WILL_FIRE_RL_rl_stage1_WFI &&
	     !WILL_FIRE_RL_rl_stage1_FENCE &&
	     !WILL_FIRE_RL_rl_stage1_FENCE_I &&
	     !WILL_FIRE_RL_rl_stage1_xRET &&
	     !WILL_FIRE_RL_rl_stage1_CSRR_S_or_C &&
	     !WILL_FIRE_RL_rl_stage1_CSRR_W &&
	     !WILL_FIRE_RL_rl_stage1_trap ;

  // rule RL_rl_stage2_nonpipe
  assign CAN_FIRE_RL_rl_stage2_nonpipe =
	     rg_state == 4'd4 && !stage3_rg_full &&
	     IF_stage2_rg_full_5_THEN_IF_stage2_rg_stage2_6_ETC___d126 ==
	     2'd3 ;
  assign WILL_FIRE_RL_rl_stage2_nonpipe = CAN_FIRE_RL_rl_stage2_nonpipe ;

  // rule RL_rl_trap
  assign CAN_FIRE_RL_rl_trap =
	     f_trace_data$FULL_N && rg_state == 4'd5 &&
	     (!stage1_rg_full ||
	      near_mem_imem_valid_AND_NOT_imem_rg_pc_BITS_1__ETC___d513) ;
  assign WILL_FIRE_RL_rl_trap = CAN_FIRE_RL_rl_trap ;

  // rule RL_rl_stage1_CSRR_W_2
  assign CAN_FIRE_RL_rl_stage1_CSRR_W_2 = MUX_rg_state$write_1__SEL_2 ;
  assign WILL_FIRE_RL_rl_stage1_CSRR_W_2 = MUX_rg_state$write_1__SEL_2 ;

  // rule RL_rl_stage1_CSRR_S_or_C_2
  assign CAN_FIRE_RL_rl_stage1_CSRR_S_or_C_2 = MUX_rg_state$write_1__SEL_3 ;
  assign WILL_FIRE_RL_rl_stage1_CSRR_S_or_C_2 = MUX_rg_state$write_1__SEL_3 ;

  // rule RL_rl_stage1_restart_after_csrrx
  assign CAN_FIRE_RL_rl_stage1_restart_after_csrrx =
	     imem_rg_pc_BITS_1_TO_0_EQ_0b0_OR_NOT_near_mem__ETC___d1085 &&
	     rg_state == 4'd9 ;
  assign WILL_FIRE_RL_rl_stage1_restart_after_csrrx =
	     CAN_FIRE_RL_rl_stage1_restart_after_csrrx ;

  // rule RL_rl_finish_FENCE_I
  assign CAN_FIRE_RL_rl_finish_FENCE_I =
	     imem_rg_pc_BITS_1_TO_0_EQ_0b0_OR_NOT_near_mem__ETC___d1085 &&
	     near_mem$RDY_server_fence_i_response_get &&
	     rg_state == 4'd10 ;
  assign WILL_FIRE_RL_rl_finish_FENCE_I = CAN_FIRE_RL_rl_finish_FENCE_I ;

  // rule RL_rl_finish_FENCE
  assign CAN_FIRE_RL_rl_finish_FENCE =
	     imem_rg_pc_BITS_1_TO_0_EQ_0b0_OR_NOT_near_mem__ETC___d1085 &&
	     near_mem$RDY_server_fence_response_get &&
	     rg_state == 4'd11 ;
  assign WILL_FIRE_RL_rl_finish_FENCE = CAN_FIRE_RL_rl_finish_FENCE ;

  // rule RL_rl_finish_SFENCE_VMA
  assign CAN_FIRE_RL_rl_finish_SFENCE_VMA =
	     imem_rg_pc_BITS_1_TO_0_EQ_0b0_OR_NOT_near_mem__ETC___d1085 &&
	     rg_state == 4'd12 ;
  assign WILL_FIRE_RL_rl_finish_SFENCE_VMA =
	     CAN_FIRE_RL_rl_finish_SFENCE_VMA ;

  // rule RL_rl_reset_from_WFI
  assign CAN_FIRE_RL_rl_reset_from_WFI =
	     rg_state == 4'd13 && f_reset_reqs$EMPTY_N ;
  assign WILL_FIRE_RL_rl_reset_from_WFI =
	     CAN_FIRE_RL_rl_reset_from_WFI && !WILL_FIRE_RL_rl_WFI_resume ;

  // rule RL_rl_trap_fetch
  assign CAN_FIRE_RL_rl_trap_fetch =
	     imem_rg_pc_BITS_1_TO_0_EQ_0b0_OR_NOT_near_mem__ETC___d1085 &&
	     rg_state == 4'd6 ;
  assign WILL_FIRE_RL_rl_trap_fetch = CAN_FIRE_RL_rl_trap_fetch ;

  // rule RL_rl_reset_from_Debug_Module
  assign CAN_FIRE_RL_rl_reset_from_Debug_Module =
	     f_reset_reqs$EMPTY_N && rg_state != 4'd0 ;
  assign WILL_FIRE_RL_rl_reset_from_Debug_Module =
	     CAN_FIRE_RL_rl_reset_from_Debug_Module &&
	     !WILL_FIRE_RL_rl_BREAK_cache_flush_finish &&
	     !WILL_FIRE_RL_rl_trap_BREAK_to_Debug_Mode &&
	     !WILL_FIRE_RL_rl_trap_fetch &&
	     !WILL_FIRE_RL_rl_reset_from_WFI &&
	     !WILL_FIRE_RL_rl_WFI_resume &&
	     !WILL_FIRE_RL_rl_stage1_WFI &&
	     !WILL_FIRE_RL_rl_finish_SFENCE_VMA &&
	     !WILL_FIRE_RL_rl_finish_FENCE &&
	     !WILL_FIRE_RL_rl_stage1_FENCE &&
	     !WILL_FIRE_RL_rl_finish_FENCE_I &&
	     !WILL_FIRE_RL_rl_stage1_FENCE_I &&
	     !WILL_FIRE_RL_rl_stage1_xRET &&
	     !WILL_FIRE_RL_rl_stage1_restart_after_csrrx &&
	     !WILL_FIRE_RL_rl_stage1_CSRR_S_or_C_2 &&
	     !WILL_FIRE_RL_rl_stage1_CSRR_S_or_C &&
	     !WILL_FIRE_RL_rl_stage1_CSRR_W_2 &&
	     !WILL_FIRE_RL_rl_stage1_CSRR_W &&
	     !WILL_FIRE_RL_rl_trap &&
	     !WILL_FIRE_RL_rl_stage1_trap &&
	     !WILL_FIRE_RL_rl_stage2_nonpipe ;

  // rule RL_rl_stage1_interrupt
  assign CAN_FIRE_RL_rl_stage1_interrupt =
	     (csr_regfile$interrupt_pending[4] || csr_regfile$nmi_pending) &&
	     rg_state == 4'd4 &&
	     stage1_rg_full_03_AND_near_mem_imem_valid_AND__ETC___d1116 &&
	     !stage3_rg_full &&
	     csr_regfile_csr_mip_read__118_EQ_rg_prev_mip_119___d1120 ;
  assign WILL_FIRE_RL_rl_stage1_interrupt =
	     CAN_FIRE_RL_rl_stage1_interrupt &&
	     !WILL_FIRE_RL_rl_reset_from_Debug_Module ;

  // rule RL_rl_reset_start
  assign CAN_FIRE_RL_rl_reset_start = MUX_rg_state$write_1__SEL_5 ;
  assign WILL_FIRE_RL_rl_reset_start = MUX_rg_state$write_1__SEL_5 ;

  // rule RL_imem_rl_fetch_next_32b
  assign CAN_FIRE_RL_imem_rl_fetch_next_32b =
	     near_mem$imem_valid && imem_rg_pc[1:0] != 2'b0 &&
	     imem_rg_pc_BITS_31_TO_2_0_EQ_near_mem_imem_pc__ETC___d13 &&
	     near_mem$imem_instr[17:16] == 2'b11 ;
  assign WILL_FIRE_RL_imem_rl_fetch_next_32b =
	     CAN_FIRE_RL_imem_rl_fetch_next_32b ;

  // rule RL_stage3_rl_reset
  assign CAN_FIRE_RL_stage3_rl_reset =
	     stage3_f_reset_reqs$EMPTY_N && stage3_f_reset_rsps$FULL_N ;
  assign WILL_FIRE_RL_stage3_rl_reset = CAN_FIRE_RL_stage3_rl_reset ;

  // rule RL_stage2_rl_reset_end
  assign CAN_FIRE_RL_stage2_rl_reset_end =
	     stage2_f_reset_rsps$FULL_N && stage2_rg_resetting ;
  assign WILL_FIRE_RL_stage2_rl_reset_end = CAN_FIRE_RL_stage2_rl_reset_end ;

  // rule RL_stage2_rl_reset_begin
  assign CAN_FIRE_RL_stage2_rl_reset_begin = stage2_f_reset_reqs$EMPTY_N ;
  assign WILL_FIRE_RL_stage2_rl_reset_begin = stage2_f_reset_reqs$EMPTY_N ;

  // rule RL_stage1_rl_reset
  assign CAN_FIRE_RL_stage1_rl_reset =
	     stage1_f_reset_reqs$EMPTY_N && stage1_f_reset_rsps$FULL_N ;
  assign WILL_FIRE_RL_stage1_rl_reset = CAN_FIRE_RL_stage1_rl_reset ;

  // inputs to muxes for submodule ports
  assign MUX_csr_regfile$mav_csr_write_1__SEL_1 =
	     WILL_FIRE_RL_rl_stage1_CSRR_W_2 &&
	     csr_regfile$access_permitted_1 ;
  assign MUX_csr_regfile$mav_csr_write_1__SEL_2 =
	     WILL_FIRE_RL_rl_stage1_CSRR_S_or_C_2 &&
	     csr_regfile$access_permitted_2 &&
	     rg_trap_instr[19:15] != 5'd0 ;
  assign MUX_csr_regfile$write_dcsr_cause_priv_1__SEL_1 =
	     WILL_FIRE_RL_rl_reset_complete && !rg_run_on_reset ;
  assign MUX_f_run_halt_rsps$enq_1__SEL_1 =
	     WILL_FIRE_RL_rl_debug_halt_redundant ||
	     WILL_FIRE_RL_rl_BREAK_cache_flush_finish ||
	     WILL_FIRE_RL_rl_trap_BREAK_to_Debug_Mode ;
  assign MUX_f_trace_data$enq_1__SEL_1 =
	     WILL_FIRE_RL_rl_pipe &&
	     IF_stage2_rg_full_5_THEN_IF_stage2_rg_stage2_6_ETC___d126 ==
	     2'd2 ;
  assign MUX_f_trace_data$enq_1__SEL_3 =
	     WILL_FIRE_RL_rl_stage1_CSRR_S_or_C_2 &&
	     csr_regfile$access_permitted_2 ;
  assign MUX_f_trace_data$enq_1__SEL_4 =
	     WILL_FIRE_RL_rl_stage1_WFI || WILL_FIRE_RL_rl_stage1_FENCE ||
	     WILL_FIRE_RL_rl_stage1_FENCE_I ||
	     WILL_FIRE_RL_rl_stage1_SFENCE_VMA ;
  assign MUX_gpr_regfile$write_rd_1__SEL_1 =
	     WILL_FIRE_RL_rl_pipe && stage3_rg_full && stage3_rg_stage3[37] ;
  assign MUX_imem_rg_f3$write_1__SEL_1 =
	     WILL_FIRE_RL_rl_reset_complete && rg_run_on_reset ;
  assign MUX_imem_rg_f3$write_1__SEL_2 =
	     WILL_FIRE_RL_rl_pipe &&
	     NOT_stage1_rg_full_03_04_OR_NOT_near_mem_imem__ETC___d1324 ;
  assign MUX_imem_rg_mstatus_MXR$write_1__SEL_4 =
	     WILL_FIRE_RL_rl_debug_run || WILL_FIRE_RL_rl_WFI_resume ||
	     WILL_FIRE_RL_rl_finish_SFENCE_VMA ||
	     WILL_FIRE_RL_rl_finish_FENCE ||
	     WILL_FIRE_RL_rl_finish_FENCE_I ||
	     WILL_FIRE_RL_rl_stage1_restart_after_csrrx ;
  assign MUX_imem_rg_pc$write_1__SEL_4 =
	     WILL_FIRE_RL_rl_trap_fetch || WILL_FIRE_RL_rl_WFI_resume ||
	     WILL_FIRE_RL_rl_finish_SFENCE_VMA ||
	     WILL_FIRE_RL_rl_finish_FENCE ||
	     WILL_FIRE_RL_rl_finish_FENCE_I ;
  assign MUX_near_mem$imem_req_1__SEL_6 =
	     WILL_FIRE_RL_rl_WFI_resume ||
	     WILL_FIRE_RL_rl_finish_SFENCE_VMA ||
	     WILL_FIRE_RL_rl_finish_FENCE ||
	     WILL_FIRE_RL_rl_finish_FENCE_I ;
  assign MUX_rg_next_pc$write_1__SEL_3 =
	     WILL_FIRE_RL_rl_stage1_WFI || WILL_FIRE_RL_rl_stage1_FENCE ||
	     WILL_FIRE_RL_rl_stage1_FENCE_I ||
	     WILL_FIRE_RL_rl_stage1_CSRR_S_or_C ||
	     WILL_FIRE_RL_rl_stage1_CSRR_W ||
	     WILL_FIRE_RL_rl_stage1_SFENCE_VMA ;
  assign MUX_rg_state$write_1__SEL_1 =
	     CAN_FIRE_RL_rl_reset_complete &&
	     !WILL_FIRE_RL_imem_rl_fetch_next_32b &&
	     !WILL_FIRE_RL_rl_reset_from_Debug_Module ;
  assign MUX_rg_state$write_1__SEL_2 =
	     (!csr_regfile$access_permitted_1 || f_trace_data$FULL_N) &&
	     rg_state == 4'd7 ;
  assign MUX_rg_state$write_1__SEL_3 =
	     (!csr_regfile$access_permitted_2 || f_trace_data$FULL_N) &&
	     rg_state == 4'd8 ;
  assign MUX_rg_state$write_1__SEL_4 =
	     WILL_FIRE_RL_rl_reset_from_Debug_Module ||
	     WILL_FIRE_RL_rl_reset_from_WFI ;
  assign MUX_rg_state$write_1__SEL_5 =
	     gpr_regfile$RDY_server_reset_request_put &&
	     near_mem_RDY_server_reset_request_put__055_AND_ETC___d1067 &&
	     rg_state == 4'd0 ;
  assign MUX_rg_state$write_1__SEL_6 =
	     WILL_FIRE_RL_rl_stage1_stop ||
	     WILL_FIRE_RL_rl_trap_BREAK_to_Debug_Mode ;
  assign MUX_rg_state$write_1__SEL_7 =
	     near_mem$RDY_server_fence_i_response_get &&
	     f_run_halt_rsps$FULL_N &&
	     rg_state == 4'd2 ;
  assign MUX_rg_state$write_1__SEL_8 =
	     WILL_FIRE_RL_rl_debug_run || WILL_FIRE_RL_rl_trap_fetch ||
	     WILL_FIRE_RL_rl_WFI_resume ||
	     WILL_FIRE_RL_rl_finish_SFENCE_VMA ||
	     WILL_FIRE_RL_rl_finish_FENCE ||
	     WILL_FIRE_RL_rl_finish_FENCE_I ||
	     WILL_FIRE_RL_rl_stage1_restart_after_csrrx ;
  assign MUX_rg_state$write_1__SEL_9 =
	     WILL_FIRE_RL_rl_stage1_interrupt ||
	     WILL_FIRE_RL_rl_stage1_trap ||
	     WILL_FIRE_RL_rl_stage2_nonpipe ;
  assign MUX_rg_state$write_1__SEL_10 =
	     WILL_FIRE_RL_rl_stage1_xRET || WILL_FIRE_RL_rl_trap ;
  assign MUX_rg_state$write_1__SEL_11 =
	     rg_state_4_EQ_4_112_AND_NOT_near_mem_imem_exc__ETC___d1394 &&
	     IF_NOT_stage1_rg_full_03_04_OR_NOT_near_mem_im_ETC___d775 ==
	     4'd2 ;
  assign MUX_rg_state$write_1__SEL_12 =
	     rg_state_4_EQ_4_112_AND_NOT_near_mem_imem_exc__ETC___d1394 &&
	     IF_NOT_stage1_rg_full_03_04_OR_NOT_near_mem_im_ETC___d775 ==
	     4'd3 ;
  assign MUX_rg_state$write_1__SEL_13 =
	     near_mem$RDY_server_fence_i_request_put && f_trace_data$FULL_N &&
	     rg_state_4_EQ_4_112_AND_NOT_near_mem_imem_exc__ETC___d1394 &&
	     IF_NOT_stage1_rg_full_03_04_OR_NOT_near_mem_im_ETC___d775 ==
	     4'd5 ;
  assign MUX_rg_step_count$write_1__PSEL_1 =
	     WILL_FIRE_RL_rl_finish_SFENCE_VMA ||
	     WILL_FIRE_RL_rl_finish_FENCE ||
	     WILL_FIRE_RL_rl_finish_FENCE_I ||
	     WILL_FIRE_RL_rl_stage1_restart_after_csrrx ||
	     WILL_FIRE_RL_rl_trap ||
	     WILL_FIRE_RL_rl_pipe ;
  assign MUX_rg_step_count$write_1__SEL_3 =
	     WILL_FIRE_RL_rl_stage1_stop || WILL_FIRE_RL_rl_reset_start ;
  assign MUX_rg_trap_info$write_1__SEL_1 =
	     WILL_FIRE_RL_rl_stage1_CSRR_S_or_C ||
	     WILL_FIRE_RL_rl_stage1_CSRR_W ;
  assign MUX_rg_trap_instr$write_1__SEL_1 =
	     WILL_FIRE_RL_rl_stage1_interrupt ||
	     WILL_FIRE_RL_rl_stage1_CSRR_S_or_C ||
	     WILL_FIRE_RL_rl_stage1_CSRR_W ||
	     WILL_FIRE_RL_rl_stage1_trap ;
  assign MUX_rg_trap_interrupt$write_1__SEL_1 =
	     WILL_FIRE_RL_rl_stage1_CSRR_S_or_C ||
	     WILL_FIRE_RL_rl_stage1_CSRR_W ||
	     WILL_FIRE_RL_rl_stage1_trap ||
	     WILL_FIRE_RL_rl_stage2_nonpipe ;
  assign MUX_rg_trap_trace_data$write_1__SEL_1 =
	     WILL_FIRE_RL_rl_stage1_CSRR_S_or_C ||
	     WILL_FIRE_RL_rl_stage1_CSRR_W ||
	     WILL_FIRE_RL_rl_stage1_trap ;
  always@(rg_trap_instr or
	  csr_regfile$read_csr or
	  y__h23296 or
	  IF_csr_regfile_read_csr_rg_trap_instr_435_BITS_ETC___d1487)
  begin
    case (rg_trap_instr[14:12])
      3'b010, 3'b110:
	  MUX_csr_regfile$mav_csr_write_2__VAL_2 =
	      IF_csr_regfile_read_csr_rg_trap_instr_435_BITS_ETC___d1487;
      default: MUX_csr_regfile$mav_csr_write_2__VAL_2 =
		   csr_regfile$read_csr[31:0] & y__h23296;
    endcase
  end
  assign MUX_csr_regfile$write_dcsr_cause_priv_1__VAL_2 =
	     rg_stop_req ? 3'd3 : 3'd4 ;
  assign MUX_f_csr_rsps$enq_1__VAL_3 =
	     { 1'd1, csr_regfile$read_csr_port2[31:0] } ;
  assign MUX_f_gpr_rsps$enq_1__VAL_3 = { 1'd1, gpr_regfile$read_rs1_port2 } ;
  assign MUX_f_trace_data$enq_1__VAL_1 =
	     { stage2_rg_stage2[234:160],
	       CASE_stage2_rg_stage2_BITS_338_TO_336_0_stage2_ETC__q19,
	       stage2_rg_stage2[127:0] } ;
  assign MUX_f_trace_data$enq_1__VAL_2 =
	     { 5'd16,
	       rg_trap_trace_data[229:165],
	       rg_trap_instr[11:7],
	       csr_regfile$read_csr[31:0],
	       32'd1,
	       x_word3__h23406,
	       csr_regfile$mav_csr_write } ;
  assign MUX_f_trace_data$enq_1__VAL_3 =
	     { 5'd16,
	       rg_trap_trace_data[229:165],
	       rg_trap_instr[11:7],
	       csr_regfile$read_csr[31:0],
	       x__h23453,
	       x_word3__h23406,
	       x__h23461 } ;
  assign MUX_f_trace_data$enq_1__VAL_6 =
	     { 203'h0EAAAAAAA955555554AAAAAAAAAAAAAAAAA0000000000000344,
	       csr_regfile$csr_mip_read } ;
  assign MUX_f_trace_data$enq_1__VAL_7 =
	     { rg_trap_interrupt ? 5'd17 : 5'd14,
	       csr_regfile$csr_trap_actions[97:66],
	       rg_trap_trace_data[197:165],
	       x_rd__h21614,
	       csr_regfile$csr_trap_actions[65:2],
	       x_word3__h21617,
	       x__h21782 } ;
  assign MUX_f_trace_data$enq_1__VAL_8 =
	     { 5'd15,
	       csr_regfile$csr_ret_actions[65:34],
	       NOT_imem_rg_pc_BITS_1_TO_0_EQ_0b0_AND_imem_rg__ETC___d505,
	       x__h19433,
	       td1_rd__h24478,
	       csr_regfile$csr_ret_actions[31:0],
	       128'hAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA } ;
  assign MUX_imem_rg_tval$write_1__VAL_6 = near_mem$imem_pc + 32'd4 ;
  assign MUX_near_mem$imem_req_2__VAL_1 =
	     NOT_soc_map_m_pc_reset_value__096_BITS_1_TO_0__ETC___d1108 ?
	       addr_of_b32___1__h17149 :
	       addr_of_b32__h17037 ;
  assign MUX_near_mem$imem_req_2__VAL_2 =
	     NOT_IF_NOT_stage1_rg_full_03_04_OR_NOT_near_me_ETC___d1354 ?
	       addr_of_b32___1__h20695 :
	       addr_of_b32__h20583 ;
  assign MUX_near_mem$imem_req_2__VAL_5 =
	     NOT_rg_next_pc_524_BITS_1_TO_0_525_EQ_0b0_526__ETC___d1533 ?
	       addr_of_b32___1__h28882 :
	       addr_of_b32__h28770 ;
  assign MUX_near_mem$imem_req_2__VAL_7 =
	     NOT_csr_regfile_read_dpc__602_BITS_1_TO_0_603__ETC___d1611 ?
	       addr_of_b32___1__h30512 :
	       addr_of_b32__h30400 ;
  assign MUX_rg_state$write_1__VAL_1 = rg_run_on_reset ? 4'd4 : 4'd3 ;
  assign MUX_rg_state$write_1__VAL_2 =
	     csr_regfile$access_permitted_1 ? 4'd9 : 4'd5 ;
  assign MUX_rg_state$write_1__VAL_3 =
	     csr_regfile$access_permitted_2 ? 4'd9 : 4'd5 ;
  assign MUX_rg_trap_info$write_1__VAL_1 =
	     { imem_rg_pc, 4'd2, value__h14885 } ;
  assign MUX_rg_trap_info$write_1__VAL_2 =
	     { stage2_rg_stage2[402:371],
	       near_mem$dmem_exc_code,
	       stage2_rg_stage2[330:299] } ;
  assign MUX_rg_trap_info$write_1__VAL_3 =
	     { imem_rg_pc,
	       IF_near_mem_imem_exc__14_THEN_near_mem_imem_ex_ETC___d1405 } ;
  assign MUX_rg_trap_info$write_1__VAL_4 =
	     { imem_rg_pc, x_exc_code__h29483, 32'd0 } ;
  assign MUX_stage1_rg_full$write_1__VAL_8 =
	     NOT_stage1_rg_full_03_04_OR_NOT_near_mem_imem__ETC___d1316 &&
	     csr_regfile_csr_mip_read__118_EQ_rg_prev_mip_119___d1120 &&
	     NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d1318 &&
	     _0_OR_0_OR_near_mem_imem_exc__14_OR_IF_IF_imem__ETC___d1370 ||
	     IF_IF_imem_rg_pc_BITS_1_TO_0_EQ_0b0_OR_NOT_ime_ETC___d1377 ;
  assign MUX_stage2_rg_full$write_1__VAL_3 =
	     _0_OR_0_OR_near_mem_imem_exc__14_OR_IF_IF_imem__ETC___d1364 &&
	     stage1_rg_full &&
	     near_mem_imem_valid_AND_NOT_imem_rg_pc_BITS_1__ETC___d714 ||
	     IF_stage2_rg_full_5_THEN_IF_stage2_rg_stage2_6_ETC___d126 !=
	     2'd2 &&
	     IF_stage2_rg_full_5_THEN_IF_stage2_rg_stage2_6_ETC___d126 !=
	     2'd0 ;

  // register cfg_logdelay
  assign cfg_logdelay$D_IN = set_verbosity_logdelay ;
  assign cfg_logdelay$EN = EN_set_verbosity ;

  // register cfg_verbosity
  assign cfg_verbosity$D_IN =
	     EN_hart0_put_other_req_put ?
	       hart0_put_other_req_put :
	       set_verbosity_verbosity ;
  assign cfg_verbosity$EN = EN_set_verbosity || EN_hart0_put_other_req_put ;

  // register imem_rg_cache_addr
  assign imem_rg_cache_addr$D_IN = near_mem$imem_pc ;
  assign imem_rg_cache_addr$EN =
	     MUX_rg_state$write_1__SEL_8 && near_mem$imem_valid ||
	     WILL_FIRE_RL_rl_reset_complete && rg_run_on_reset &&
	     near_mem$imem_valid ||
	     WILL_FIRE_RL_rl_pipe &&
	     NOT_stage1_rg_full_03_04_OR_imem_rg_pc_BITS_1__ETC___d1344 &&
	     near_mem$imem_valid ||
	     WILL_FIRE_RL_imem_rl_fetch_next_32b ;

  // register imem_rg_cache_b16
  assign imem_rg_cache_b16$D_IN = near_mem$imem_instr[31:16] ;
  assign imem_rg_cache_b16$EN =
	     MUX_rg_state$write_1__SEL_8 && near_mem$imem_valid ||
	     WILL_FIRE_RL_rl_reset_complete && rg_run_on_reset &&
	     near_mem$imem_valid ||
	     WILL_FIRE_RL_rl_pipe &&
	     NOT_stage1_rg_full_03_04_OR_imem_rg_pc_BITS_1__ETC___d1344 &&
	     near_mem$imem_valid ||
	     WILL_FIRE_RL_imem_rl_fetch_next_32b ;

  // register imem_rg_f3
  assign imem_rg_f3$D_IN = 3'b010 ;
  assign imem_rg_f3$EN =
	     WILL_FIRE_RL_rl_reset_complete && rg_run_on_reset ||
	     WILL_FIRE_RL_rl_pipe &&
	     NOT_stage1_rg_full_03_04_OR_NOT_near_mem_imem__ETC___d1324 ||
	     WILL_FIRE_RL_rl_debug_run ||
	     WILL_FIRE_RL_rl_trap_fetch ||
	     WILL_FIRE_RL_rl_WFI_resume ||
	     WILL_FIRE_RL_rl_finish_SFENCE_VMA ||
	     WILL_FIRE_RL_rl_finish_FENCE ||
	     WILL_FIRE_RL_rl_finish_FENCE_I ||
	     WILL_FIRE_RL_rl_stage1_restart_after_csrrx ;

  // register imem_rg_mstatus_MXR
  assign imem_rg_mstatus_MXR$D_IN =
	     (MUX_imem_rg_f3$write_1__SEL_1 ||
	      MUX_imem_rg_f3$write_1__SEL_2 ||
	      MUX_imem_rg_mstatus_MXR$write_1__SEL_4) ?
	       csr_regfile$read_mstatus[19] :
	       rg_mstatus_MXR ;
  assign imem_rg_mstatus_MXR$EN =
	     WILL_FIRE_RL_rl_reset_complete && rg_run_on_reset ||
	     WILL_FIRE_RL_rl_pipe &&
	     NOT_stage1_rg_full_03_04_OR_NOT_near_mem_imem__ETC___d1324 ||
	     WILL_FIRE_RL_rl_trap_fetch ||
	     WILL_FIRE_RL_rl_debug_run ||
	     WILL_FIRE_RL_rl_WFI_resume ||
	     WILL_FIRE_RL_rl_finish_SFENCE_VMA ||
	     WILL_FIRE_RL_rl_finish_FENCE ||
	     WILL_FIRE_RL_rl_finish_FENCE_I ||
	     WILL_FIRE_RL_rl_stage1_restart_after_csrrx ;

  // register imem_rg_pc
  always@(MUX_imem_rg_f3$write_1__SEL_1 or
	  soc_map$m_pc_reset_value or
	  MUX_imem_rg_f3$write_1__SEL_2 or
	  x_out_next_pc__h13057 or
	  WILL_FIRE_RL_rl_stage1_restart_after_csrrx or
	  MUX_imem_rg_pc$write_1__SEL_4 or
	  rg_next_pc or WILL_FIRE_RL_rl_debug_run or csr_regfile$read_dpc)
  begin
    case (1'b1) // synopsys parallel_case
      MUX_imem_rg_f3$write_1__SEL_1:
	  imem_rg_pc$D_IN = soc_map$m_pc_reset_value[31:0];
      MUX_imem_rg_f3$write_1__SEL_2: imem_rg_pc$D_IN = x_out_next_pc__h13057;
      WILL_FIRE_RL_rl_stage1_restart_after_csrrx:
	  imem_rg_pc$D_IN = x_out_next_pc__h13057;
      MUX_imem_rg_pc$write_1__SEL_4: imem_rg_pc$D_IN = rg_next_pc;
      WILL_FIRE_RL_rl_debug_run: imem_rg_pc$D_IN = csr_regfile$read_dpc;
      default: imem_rg_pc$D_IN = 32'hAAAAAAAA /* unspecified value */ ;
    endcase
  end
  assign imem_rg_pc$EN =
	     WILL_FIRE_RL_rl_reset_complete && rg_run_on_reset ||
	     WILL_FIRE_RL_rl_pipe &&
	     NOT_stage1_rg_full_03_04_OR_NOT_near_mem_imem__ETC___d1324 ||
	     WILL_FIRE_RL_rl_stage1_restart_after_csrrx ||
	     WILL_FIRE_RL_rl_trap_fetch ||
	     WILL_FIRE_RL_rl_WFI_resume ||
	     WILL_FIRE_RL_rl_finish_SFENCE_VMA ||
	     WILL_FIRE_RL_rl_finish_FENCE ||
	     WILL_FIRE_RL_rl_finish_FENCE_I ||
	     WILL_FIRE_RL_rl_debug_run ;

  // register imem_rg_priv
  assign imem_rg_priv$D_IN = rg_cur_priv ;
  assign imem_rg_priv$EN =
	     WILL_FIRE_RL_rl_reset_complete && rg_run_on_reset ||
	     WILL_FIRE_RL_rl_pipe &&
	     NOT_stage1_rg_full_03_04_OR_NOT_near_mem_imem__ETC___d1324 ||
	     WILL_FIRE_RL_rl_debug_run ||
	     WILL_FIRE_RL_rl_trap_fetch ||
	     WILL_FIRE_RL_rl_WFI_resume ||
	     WILL_FIRE_RL_rl_finish_SFENCE_VMA ||
	     WILL_FIRE_RL_rl_finish_FENCE ||
	     WILL_FIRE_RL_rl_finish_FENCE_I ||
	     WILL_FIRE_RL_rl_stage1_restart_after_csrrx ;

  // register imem_rg_satp
  assign imem_rg_satp$D_IN = csr_regfile$read_satp ;
  assign imem_rg_satp$EN =
	     WILL_FIRE_RL_rl_reset_complete && rg_run_on_reset ||
	     WILL_FIRE_RL_rl_pipe &&
	     NOT_stage1_rg_full_03_04_OR_NOT_near_mem_imem__ETC___d1324 ||
	     WILL_FIRE_RL_rl_debug_run ||
	     WILL_FIRE_RL_rl_trap_fetch ||
	     WILL_FIRE_RL_rl_WFI_resume ||
	     WILL_FIRE_RL_rl_finish_SFENCE_VMA ||
	     WILL_FIRE_RL_rl_finish_FENCE ||
	     WILL_FIRE_RL_rl_finish_FENCE_I ||
	     WILL_FIRE_RL_rl_stage1_restart_after_csrrx ;

  // register imem_rg_sstatus_SUM
  assign imem_rg_sstatus_SUM$D_IN =
	     WILL_FIRE_RL_rl_trap_fetch && rg_sstatus_SUM ;
  assign imem_rg_sstatus_SUM$EN =
	     WILL_FIRE_RL_rl_reset_complete && rg_run_on_reset ||
	     WILL_FIRE_RL_rl_pipe &&
	     NOT_stage1_rg_full_03_04_OR_NOT_near_mem_imem__ETC___d1324 ||
	     WILL_FIRE_RL_rl_trap_fetch ||
	     WILL_FIRE_RL_rl_debug_run ||
	     WILL_FIRE_RL_rl_WFI_resume ||
	     WILL_FIRE_RL_rl_finish_SFENCE_VMA ||
	     WILL_FIRE_RL_rl_finish_FENCE ||
	     WILL_FIRE_RL_rl_finish_FENCE_I ||
	     WILL_FIRE_RL_rl_stage1_restart_after_csrrx ;

  // register imem_rg_tval
  always@(MUX_imem_rg_f3$write_1__SEL_1 or
	  soc_map$m_pc_reset_value or
	  MUX_imem_rg_f3$write_1__SEL_2 or
	  x_out_next_pc__h13057 or
	  WILL_FIRE_RL_rl_stage1_restart_after_csrrx or
	  MUX_imem_rg_pc$write_1__SEL_4 or
	  rg_next_pc or
	  WILL_FIRE_RL_rl_debug_run or
	  csr_regfile$read_dpc or
	  WILL_FIRE_RL_imem_rl_fetch_next_32b or
	  MUX_imem_rg_tval$write_1__VAL_6)
  begin
    case (1'b1) // synopsys parallel_case
      MUX_imem_rg_f3$write_1__SEL_1:
	  imem_rg_tval$D_IN = soc_map$m_pc_reset_value[31:0];
      MUX_imem_rg_f3$write_1__SEL_2:
	  imem_rg_tval$D_IN = x_out_next_pc__h13057;
      WILL_FIRE_RL_rl_stage1_restart_after_csrrx:
	  imem_rg_tval$D_IN = x_out_next_pc__h13057;
      MUX_imem_rg_pc$write_1__SEL_4: imem_rg_tval$D_IN = rg_next_pc;
      WILL_FIRE_RL_rl_debug_run: imem_rg_tval$D_IN = csr_regfile$read_dpc;
      WILL_FIRE_RL_imem_rl_fetch_next_32b:
	  imem_rg_tval$D_IN = MUX_imem_rg_tval$write_1__VAL_6;
      default: imem_rg_tval$D_IN = 32'hAAAAAAAA /* unspecified value */ ;
    endcase
  end
  assign imem_rg_tval$EN =
	     WILL_FIRE_RL_rl_reset_complete && rg_run_on_reset ||
	     WILL_FIRE_RL_rl_pipe &&
	     NOT_stage1_rg_full_03_04_OR_NOT_near_mem_imem__ETC___d1324 ||
	     WILL_FIRE_RL_rl_stage1_restart_after_csrrx ||
	     WILL_FIRE_RL_rl_trap_fetch ||
	     WILL_FIRE_RL_rl_WFI_resume ||
	     WILL_FIRE_RL_rl_finish_SFENCE_VMA ||
	     WILL_FIRE_RL_rl_finish_FENCE ||
	     WILL_FIRE_RL_rl_finish_FENCE_I ||
	     WILL_FIRE_RL_rl_debug_run ||
	     WILL_FIRE_RL_imem_rl_fetch_next_32b ;

  // register rg_csr_pc
  assign rg_csr_pc$D_IN = imem_rg_pc ;
  assign rg_csr_pc$EN = MUX_rg_trap_info$write_1__SEL_1 ;

  // register rg_csr_val1
  assign rg_csr_val1$D_IN = x_out_data_to_stage2_val1__h13094 ;
  assign rg_csr_val1$EN = MUX_rg_trap_info$write_1__SEL_1 ;

  // register rg_cur_priv
  always@(WILL_FIRE_RL_rl_trap or
	  csr_regfile$csr_trap_actions or
	  WILL_FIRE_RL_rl_stage1_xRET or
	  csr_regfile$csr_ret_actions or WILL_FIRE_RL_rl_reset_start)
  begin
    case (1'b1) // synopsys parallel_case
      WILL_FIRE_RL_rl_trap:
	  rg_cur_priv$D_IN = csr_regfile$csr_trap_actions[1:0];
      WILL_FIRE_RL_rl_stage1_xRET:
	  rg_cur_priv$D_IN = csr_regfile$csr_ret_actions[33:32];
      WILL_FIRE_RL_rl_reset_start: rg_cur_priv$D_IN = 2'b11;
      default: rg_cur_priv$D_IN = 2'b10 /* unspecified value */ ;
    endcase
  end
  assign rg_cur_priv$EN =
	     WILL_FIRE_RL_rl_trap || WILL_FIRE_RL_rl_stage1_xRET ||
	     WILL_FIRE_RL_rl_reset_start ;

  // register rg_mstatus_MXR
  assign rg_mstatus_MXR$D_IN = csr_regfile$read_mstatus[19] ;
  assign rg_mstatus_MXR$EN = MUX_rg_state$write_1__SEL_10 ;

  // register rg_next_pc
  always@(WILL_FIRE_RL_rl_trap or
	  csr_regfile$csr_trap_actions or
	  WILL_FIRE_RL_rl_stage1_xRET or
	  csr_regfile$csr_ret_actions or
	  MUX_rg_next_pc$write_1__SEL_3 or x_out_next_pc__h13057)
  begin
    case (1'b1) // synopsys parallel_case
      WILL_FIRE_RL_rl_trap:
	  rg_next_pc$D_IN = csr_regfile$csr_trap_actions[97:66];
      WILL_FIRE_RL_rl_stage1_xRET:
	  rg_next_pc$D_IN = csr_regfile$csr_ret_actions[65:34];
      MUX_rg_next_pc$write_1__SEL_3: rg_next_pc$D_IN = x_out_next_pc__h13057;
      default: rg_next_pc$D_IN = 32'hAAAAAAAA /* unspecified value */ ;
    endcase
  end
  assign rg_next_pc$EN =
	     WILL_FIRE_RL_rl_trap || WILL_FIRE_RL_rl_stage1_xRET ||
	     WILL_FIRE_RL_rl_stage1_WFI ||
	     WILL_FIRE_RL_rl_stage1_FENCE ||
	     WILL_FIRE_RL_rl_stage1_FENCE_I ||
	     WILL_FIRE_RL_rl_stage1_CSRR_S_or_C ||
	     WILL_FIRE_RL_rl_stage1_CSRR_W ||
	     WILL_FIRE_RL_rl_stage1_SFENCE_VMA ;

  // register rg_prev_mip
  assign rg_prev_mip$D_IN =
	     WILL_FIRE_RL_rl_stage1_mip_cmd ?
	       csr_regfile$csr_mip_read :
	       32'd0 ;
  assign rg_prev_mip$EN =
	     WILL_FIRE_RL_rl_stage1_mip_cmd || WILL_FIRE_RL_rl_reset_start ;

  // register rg_run_on_reset
  assign rg_run_on_reset$D_IN = f_reset_reqs$D_OUT ;
  assign rg_run_on_reset$EN = MUX_rg_state$write_1__SEL_5 ;

  // register rg_sstatus_SUM
  assign rg_sstatus_SUM$D_IN = 1'd0 ;
  assign rg_sstatus_SUM$EN = MUX_rg_state$write_1__SEL_10 ;

  // register rg_start_CPI_cycles
  assign rg_start_CPI_cycles$D_IN = csr_regfile$read_csr_mcycle ;
  assign rg_start_CPI_cycles$EN =
	     WILL_FIRE_RL_rl_reset_complete && rg_run_on_reset ||
	     WILL_FIRE_RL_rl_debug_run ;

  // register rg_start_CPI_instrs
  assign rg_start_CPI_instrs$D_IN = csr_regfile$read_csr_minstret ;
  assign rg_start_CPI_instrs$EN =
	     WILL_FIRE_RL_rl_reset_complete && rg_run_on_reset ||
	     WILL_FIRE_RL_rl_debug_run ;

  // register rg_state
  always@(WILL_FIRE_RL_rl_reset_complete or
	  MUX_rg_state$write_1__VAL_1 or
	  WILL_FIRE_RL_rl_stage1_CSRR_W_2 or
	  MUX_rg_state$write_1__VAL_2 or
	  WILL_FIRE_RL_rl_stage1_CSRR_S_or_C_2 or
	  MUX_rg_state$write_1__VAL_3 or
	  MUX_rg_state$write_1__SEL_4 or
	  WILL_FIRE_RL_rl_reset_start or
	  MUX_rg_state$write_1__SEL_6 or
	  WILL_FIRE_RL_rl_BREAK_cache_flush_finish or
	  MUX_rg_state$write_1__SEL_8 or
	  MUX_rg_state$write_1__SEL_9 or
	  MUX_rg_state$write_1__SEL_10 or
	  WILL_FIRE_RL_rl_stage1_CSRR_W or
	  WILL_FIRE_RL_rl_stage1_CSRR_S_or_C or
	  WILL_FIRE_RL_rl_stage1_FENCE_I or
	  WILL_FIRE_RL_rl_stage1_FENCE or
	  WILL_FIRE_RL_rl_stage1_SFENCE_VMA or WILL_FIRE_RL_rl_stage1_WFI)
  begin
    case (1'b1) // synopsys parallel_case
      WILL_FIRE_RL_rl_reset_complete:
	  rg_state$D_IN = MUX_rg_state$write_1__VAL_1;
      WILL_FIRE_RL_rl_stage1_CSRR_W_2:
	  rg_state$D_IN = MUX_rg_state$write_1__VAL_2;
      WILL_FIRE_RL_rl_stage1_CSRR_S_or_C_2:
	  rg_state$D_IN = MUX_rg_state$write_1__VAL_3;
      MUX_rg_state$write_1__SEL_4: rg_state$D_IN = 4'd0;
      WILL_FIRE_RL_rl_reset_start: rg_state$D_IN = 4'd1;
      MUX_rg_state$write_1__SEL_6: rg_state$D_IN = 4'd2;
      WILL_FIRE_RL_rl_BREAK_cache_flush_finish: rg_state$D_IN = 4'd3;
      MUX_rg_state$write_1__SEL_8: rg_state$D_IN = 4'd4;
      MUX_rg_state$write_1__SEL_9: rg_state$D_IN = 4'd5;
      MUX_rg_state$write_1__SEL_10: rg_state$D_IN = 4'd6;
      WILL_FIRE_RL_rl_stage1_CSRR_W: rg_state$D_IN = 4'd7;
      WILL_FIRE_RL_rl_stage1_CSRR_S_or_C: rg_state$D_IN = 4'd8;
      WILL_FIRE_RL_rl_stage1_FENCE_I: rg_state$D_IN = 4'd10;
      WILL_FIRE_RL_rl_stage1_FENCE: rg_state$D_IN = 4'd11;
      WILL_FIRE_RL_rl_stage1_SFENCE_VMA: rg_state$D_IN = 4'd12;
      WILL_FIRE_RL_rl_stage1_WFI: rg_state$D_IN = 4'd13;
      default: rg_state$D_IN = 4'b1010 /* unspecified value */ ;
    endcase
  end
  assign rg_state$EN =
	     WILL_FIRE_RL_rl_reset_complete ||
	     WILL_FIRE_RL_rl_stage1_CSRR_W_2 ||
	     WILL_FIRE_RL_rl_stage1_CSRR_S_or_C_2 ||
	     WILL_FIRE_RL_rl_reset_from_Debug_Module ||
	     WILL_FIRE_RL_rl_reset_from_WFI ||
	     WILL_FIRE_RL_rl_reset_start ||
	     WILL_FIRE_RL_rl_stage1_stop ||
	     WILL_FIRE_RL_rl_trap_BREAK_to_Debug_Mode ||
	     WILL_FIRE_RL_rl_BREAK_cache_flush_finish ||
	     WILL_FIRE_RL_rl_debug_run ||
	     WILL_FIRE_RL_rl_trap_fetch ||
	     WILL_FIRE_RL_rl_WFI_resume ||
	     WILL_FIRE_RL_rl_finish_SFENCE_VMA ||
	     WILL_FIRE_RL_rl_finish_FENCE ||
	     WILL_FIRE_RL_rl_finish_FENCE_I ||
	     WILL_FIRE_RL_rl_stage1_restart_after_csrrx ||
	     WILL_FIRE_RL_rl_stage1_interrupt ||
	     WILL_FIRE_RL_rl_stage1_trap ||
	     WILL_FIRE_RL_rl_stage2_nonpipe ||
	     WILL_FIRE_RL_rl_stage1_xRET ||
	     WILL_FIRE_RL_rl_trap ||
	     WILL_FIRE_RL_rl_stage1_CSRR_W ||
	     WILL_FIRE_RL_rl_stage1_CSRR_S_or_C ||
	     WILL_FIRE_RL_rl_stage1_FENCE_I ||
	     WILL_FIRE_RL_rl_stage1_FENCE ||
	     WILL_FIRE_RL_rl_stage1_SFENCE_VMA ||
	     WILL_FIRE_RL_rl_stage1_WFI ;

  // register rg_step_count
  assign rg_step_count$D_IN = !MUX_rg_step_count$write_1__SEL_3 ;
  assign rg_step_count$EN =
	     MUX_rg_step_count$write_1__PSEL_1 &&
	     stage1_rg_full_03_AND_near_mem_imem_valid_AND__ETC___d1380 &&
	     !rg_step_count ||
	     (WILL_FIRE_RL_rl_stage1_WFI || WILL_FIRE_RL_rl_stage1_xRET) &&
	     csr_regfile$read_dcsr_step &&
	     !rg_step_count ||
	     WILL_FIRE_RL_rl_stage1_stop ||
	     WILL_FIRE_RL_rl_reset_start ;

  // register rg_stop_req
  assign rg_stop_req$D_IN = !MUX_rg_step_count$write_1__SEL_3 ;
  assign rg_stop_req$EN =
	     WILL_FIRE_RL_rl_stage1_stop || WILL_FIRE_RL_rl_reset_start ||
	     WILL_FIRE_RL_rl_debug_halt ;

  // register rg_trap_info
  always@(MUX_rg_trap_info$write_1__SEL_1 or
	  MUX_rg_trap_info$write_1__VAL_1 or
	  WILL_FIRE_RL_rl_stage2_nonpipe or
	  MUX_rg_trap_info$write_1__VAL_2 or
	  WILL_FIRE_RL_rl_stage1_trap or
	  MUX_rg_trap_info$write_1__VAL_3 or
	  WILL_FIRE_RL_rl_stage1_interrupt or MUX_rg_trap_info$write_1__VAL_4)
  begin
    case (1'b1) // synopsys parallel_case
      MUX_rg_trap_info$write_1__SEL_1:
	  rg_trap_info$D_IN = MUX_rg_trap_info$write_1__VAL_1;
      WILL_FIRE_RL_rl_stage2_nonpipe:
	  rg_trap_info$D_IN = MUX_rg_trap_info$write_1__VAL_2;
      WILL_FIRE_RL_rl_stage1_trap:
	  rg_trap_info$D_IN = MUX_rg_trap_info$write_1__VAL_3;
      WILL_FIRE_RL_rl_stage1_interrupt:
	  rg_trap_info$D_IN = MUX_rg_trap_info$write_1__VAL_4;
      default: rg_trap_info$D_IN =
		   68'hAAAAAAAAAAAAAAAAA /* unspecified value */ ;
    endcase
  end
  assign rg_trap_info$EN =
	     WILL_FIRE_RL_rl_stage1_CSRR_S_or_C ||
	     WILL_FIRE_RL_rl_stage1_CSRR_W ||
	     WILL_FIRE_RL_rl_stage2_nonpipe ||
	     WILL_FIRE_RL_rl_stage1_trap ||
	     WILL_FIRE_RL_rl_stage1_interrupt ;

  // register rg_trap_instr
  assign rg_trap_instr$D_IN =
	     MUX_rg_trap_instr$write_1__SEL_1 ?
	       x_out_data_to_stage2_instr__h13090 :
	       stage2_rg_stage2[370:339] ;
  assign rg_trap_instr$EN =
	     WILL_FIRE_RL_rl_stage1_interrupt ||
	     WILL_FIRE_RL_rl_stage1_CSRR_S_or_C ||
	     WILL_FIRE_RL_rl_stage1_CSRR_W ||
	     WILL_FIRE_RL_rl_stage1_trap ||
	     WILL_FIRE_RL_rl_stage2_nonpipe ;

  // register rg_trap_interrupt
  assign rg_trap_interrupt$D_IN = !MUX_rg_trap_interrupt$write_1__SEL_1 ;
  assign rg_trap_interrupt$EN =
	     WILL_FIRE_RL_rl_stage1_CSRR_S_or_C ||
	     WILL_FIRE_RL_rl_stage1_CSRR_W ||
	     WILL_FIRE_RL_rl_stage1_trap ||
	     WILL_FIRE_RL_rl_stage2_nonpipe ||
	     WILL_FIRE_RL_rl_stage1_interrupt ;

  // register rg_trap_trace_data
  assign rg_trap_trace_data$D_IN =
	     MUX_rg_trap_trace_data$write_1__SEL_1 ?
	       IF_NOT_stage1_rg_full_03_04_OR_NOT_near_mem_im_ETC___d1286 :
	       MUX_f_trace_data$enq_1__VAL_1 ;
  assign rg_trap_trace_data$EN = MUX_rg_trap_interrupt$write_1__SEL_1 ;

  // register stage1_rg_full
  always@(WILL_FIRE_RL_stage1_rl_reset or
	  WILL_FIRE_RL_rl_trap_fetch or
	  WILL_FIRE_RL_rl_finish_SFENCE_VMA or
	  WILL_FIRE_RL_rl_finish_FENCE or
	  WILL_FIRE_RL_rl_finish_FENCE_I or
	  WILL_FIRE_RL_rl_stage1_restart_after_csrrx or
	  WILL_FIRE_RL_rl_trap or
	  WILL_FIRE_RL_rl_pipe or
	  MUX_stage1_rg_full$write_1__VAL_8 or
	  MUX_imem_rg_f3$write_1__SEL_1 or
	  WILL_FIRE_RL_rl_WFI_resume or
	  WILL_FIRE_RL_rl_stage1_WFI or
	  WILL_FIRE_RL_rl_stage1_xRET or WILL_FIRE_RL_rl_debug_run)
  case (1'b1)
    WILL_FIRE_RL_stage1_rl_reset: stage1_rg_full$D_IN = 1'd0;
    WILL_FIRE_RL_rl_trap_fetch || WILL_FIRE_RL_rl_finish_SFENCE_VMA ||
    WILL_FIRE_RL_rl_finish_FENCE ||
    WILL_FIRE_RL_rl_finish_FENCE_I ||
    WILL_FIRE_RL_rl_stage1_restart_after_csrrx:
	stage1_rg_full$D_IN = 1'd1;
    WILL_FIRE_RL_rl_trap: stage1_rg_full$D_IN = 1'd0;
    WILL_FIRE_RL_rl_pipe:
	stage1_rg_full$D_IN = MUX_stage1_rg_full$write_1__VAL_8;
    MUX_imem_rg_f3$write_1__SEL_1 || WILL_FIRE_RL_rl_WFI_resume:
	stage1_rg_full$D_IN = 1'd1;
    WILL_FIRE_RL_rl_stage1_WFI || WILL_FIRE_RL_rl_stage1_xRET:
	stage1_rg_full$D_IN = 1'd0;
    WILL_FIRE_RL_rl_debug_run: stage1_rg_full$D_IN = 1'd1;
    default: stage1_rg_full$D_IN = 1'b0 /* unspecified value */ ;
  endcase
  assign stage1_rg_full$EN =
	     WILL_FIRE_RL_rl_reset_complete && rg_run_on_reset ||
	     WILL_FIRE_RL_rl_pipe ||
	     WILL_FIRE_RL_rl_stage1_WFI ||
	     WILL_FIRE_RL_rl_stage1_xRET ||
	     WILL_FIRE_RL_rl_trap ||
	     WILL_FIRE_RL_stage1_rl_reset ||
	     WILL_FIRE_RL_rl_debug_run ||
	     WILL_FIRE_RL_rl_trap_fetch ||
	     WILL_FIRE_RL_rl_WFI_resume ||
	     WILL_FIRE_RL_rl_finish_SFENCE_VMA ||
	     WILL_FIRE_RL_rl_finish_FENCE ||
	     WILL_FIRE_RL_rl_finish_FENCE_I ||
	     WILL_FIRE_RL_rl_stage1_restart_after_csrrx ;

  // register stage2_rg_full
  always@(stage2_f_reset_reqs$EMPTY_N or
	  WILL_FIRE_RL_rl_trap or
	  WILL_FIRE_RL_rl_pipe or
	  MUX_stage2_rg_full$write_1__VAL_3 or
	  MUX_imem_rg_f3$write_1__SEL_1 or WILL_FIRE_RL_rl_debug_run)
  case (1'b1)
    stage2_f_reset_reqs$EMPTY_N || WILL_FIRE_RL_rl_trap:
	stage2_rg_full$D_IN = 1'd0;
    WILL_FIRE_RL_rl_pipe:
	stage2_rg_full$D_IN = MUX_stage2_rg_full$write_1__VAL_3;
    MUX_imem_rg_f3$write_1__SEL_1 || WILL_FIRE_RL_rl_debug_run:
	stage2_rg_full$D_IN = 1'd0;
    default: stage2_rg_full$D_IN = 1'b0 /* unspecified value */ ;
  endcase
  assign stage2_rg_full$EN =
	     WILL_FIRE_RL_rl_reset_complete && rg_run_on_reset ||
	     WILL_FIRE_RL_rl_pipe ||
	     WILL_FIRE_RL_rl_debug_run ||
	     WILL_FIRE_RL_rl_trap ||
	     stage2_f_reset_reqs$EMPTY_N ;

  // register stage2_rg_resetting
  assign stage2_rg_resetting$D_IN = stage2_f_reset_reqs$EMPTY_N ;
  assign stage2_rg_resetting$EN =
	     WILL_FIRE_RL_stage2_rl_reset_end || stage2_f_reset_reqs$EMPTY_N ;

  // register stage2_rg_stage2
  assign stage2_rg_stage2$D_IN =
	     { rg_cur_priv,
	       imem_rg_pc,
	       x_out_data_to_stage2_instr__h13090,
	       IF_NOT_stage1_rg_full_03_04_OR_NOT_near_mem_im_ETC___d854,
	       x_out_data_to_stage2_rd__h13092,
	       x_out_data_to_stage2_addr__h13093,
	       x_out_data_to_stage2_val1__h13094,
	       x_out_data_to_stage2_val2__h13095,
	       IF_NOT_stage1_rg_full_03_04_OR_NOT_near_mem_im_ETC___d1286 } ;
  assign stage2_rg_stage2$EN =
	     WILL_FIRE_RL_rl_pipe &&
	     near_mem_imem_exc__14_OR_IF_IF_imem_rg_pc_BITS_ETC___d1227 &&
	     stage1_rg_full &&
	     near_mem_imem_valid_AND_NOT_imem_rg_pc_BITS_1__ETC___d714 ;

  // register stage3_rg_full
  always@(WILL_FIRE_RL_stage3_rl_reset or
	  WILL_FIRE_RL_rl_pipe or
	  IF_stage2_rg_full_5_THEN_IF_stage2_rg_stage2_6_ETC___d126 or
	  MUX_imem_rg_f3$write_1__SEL_1 or WILL_FIRE_RL_rl_debug_run)
  case (1'b1)
    WILL_FIRE_RL_stage3_rl_reset: stage3_rg_full$D_IN = 1'd0;
    WILL_FIRE_RL_rl_pipe:
	stage3_rg_full$D_IN =
	    IF_stage2_rg_full_5_THEN_IF_stage2_rg_stage2_6_ETC___d126 == 2'd2;
    MUX_imem_rg_f3$write_1__SEL_1 || WILL_FIRE_RL_rl_debug_run:
	stage3_rg_full$D_IN = 1'd0;
    default: stage3_rg_full$D_IN = 1'b0 /* unspecified value */ ;
  endcase
  assign stage3_rg_full$EN =
	     WILL_FIRE_RL_rl_reset_complete && rg_run_on_reset ||
	     WILL_FIRE_RL_rl_pipe ||
	     WILL_FIRE_RL_rl_debug_run ||
	     WILL_FIRE_RL_stage3_rl_reset ;

  // register stage3_rg_stage3
  assign stage3_rg_stage3$D_IN =
	     { stage2_rg_stage2[402:339],
	       stage2_rg_stage2[404:403],
	       stage2_rg_stage2[338:336] == 3'd0 ||
	       IF_stage2_rg_stage2_6_BITS_338_TO_336_7_EQ_1_9_ETC___d149,
	       x_out_data_to_stage3_rd__h7110,
	       x_out_data_to_stage3_rd_val__h7111 } ;
  assign stage3_rg_stage3$EN = MUX_f_trace_data$enq_1__SEL_1 ;

  // submodule csr_regfile
  assign csr_regfile$access_permitted_1_csr_addr = rg_trap_instr[31:20] ;
  assign csr_regfile$access_permitted_1_priv = rg_cur_priv ;
  assign csr_regfile$access_permitted_1_read_not_write = 1'd0 ;
  assign csr_regfile$access_permitted_2_csr_addr = rg_trap_instr[31:20] ;
  assign csr_regfile$access_permitted_2_priv = rg_cur_priv ;
  assign csr_regfile$access_permitted_2_read_not_write =
	     rs1_val__h23025 == 32'd0 ;
  assign csr_regfile$csr_counter_read_fault_csr_addr = 12'h0 ;
  assign csr_regfile$csr_counter_read_fault_priv = 2'h0 ;
  always@(IF_NOT_stage1_rg_full_03_04_OR_NOT_near_mem_im_ETC___d775)
  begin
    case (IF_NOT_stage1_rg_full_03_04_OR_NOT_near_mem_im_ETC___d775)
      4'd7: csr_regfile$csr_ret_actions_from_priv = 2'b11;
      4'd8: csr_regfile$csr_ret_actions_from_priv = 2'b01;
      default: csr_regfile$csr_ret_actions_from_priv = 2'b0;
    endcase
  end
  assign csr_regfile$csr_trap_actions_exc_code = rg_trap_info[35:32] ;
  assign csr_regfile$csr_trap_actions_from_priv = rg_cur_priv ;
  assign csr_regfile$csr_trap_actions_interrupt =
	     rg_trap_interrupt && !csr_regfile$nmi_pending ;
  assign csr_regfile$csr_trap_actions_nmi =
	     rg_trap_interrupt && csr_regfile$nmi_pending ;
  assign csr_regfile$csr_trap_actions_pc = rg_trap_info[67:36] ;
  assign csr_regfile$csr_trap_actions_xtval = rg_trap_info[31:0] ;
  assign csr_regfile$dcsr_break_enters_debug_cur_priv = rg_cur_priv ;
  assign csr_regfile$interrupt_pending_cur_priv = rg_cur_priv ;
  assign csr_regfile$m_external_interrupt_req_set_not_clear =
	     m_external_interrupt_req_set_not_clear ;
  assign csr_regfile$mav_csr_write_csr_addr =
	     (MUX_csr_regfile$mav_csr_write_1__SEL_1 ||
	      MUX_csr_regfile$mav_csr_write_1__SEL_2) ?
	       rg_trap_instr[31:20] :
	       f_csr_reqs$D_OUT[43:32] ;
  always@(MUX_csr_regfile$mav_csr_write_1__SEL_1 or
	  rs1_val__h22206 or
	  MUX_csr_regfile$mav_csr_write_1__SEL_2 or
	  MUX_csr_regfile$mav_csr_write_2__VAL_2 or
	  WILL_FIRE_RL_rl_debug_write_csr or f_csr_reqs$D_OUT)
  begin
    case (1'b1) // synopsys parallel_case
      MUX_csr_regfile$mav_csr_write_1__SEL_1:
	  csr_regfile$mav_csr_write_word = rs1_val__h22206;
      MUX_csr_regfile$mav_csr_write_1__SEL_2:
	  csr_regfile$mav_csr_write_word =
	      MUX_csr_regfile$mav_csr_write_2__VAL_2;
      WILL_FIRE_RL_rl_debug_write_csr:
	  csr_regfile$mav_csr_write_word = f_csr_reqs$D_OUT[31:0];
      default: csr_regfile$mav_csr_write_word =
		   32'hAAAAAAAA /* unspecified value */ ;
    endcase
  end
  assign csr_regfile$mav_read_csr_csr_addr = 12'h0 ;
  assign csr_regfile$nmi_req_set_not_clear = nmi_req_set_not_clear ;
  assign csr_regfile$read_csr_csr_addr = rg_trap_instr[31:20] ;
  assign csr_regfile$read_csr_port2_csr_addr = f_csr_reqs$D_OUT[43:32] ;
  assign csr_regfile$s_external_interrupt_req_set_not_clear =
	     s_external_interrupt_req_set_not_clear ;
  assign csr_regfile$software_interrupt_req_set_not_clear =
	     software_interrupt_req_set_not_clear ;
  assign csr_regfile$timer_interrupt_req_set_not_clear =
	     timer_interrupt_req_set_not_clear ;
  always@(MUX_csr_regfile$write_dcsr_cause_priv_1__SEL_1 or
	  WILL_FIRE_RL_rl_stage1_stop or
	  MUX_csr_regfile$write_dcsr_cause_priv_1__VAL_2 or
	  WILL_FIRE_RL_rl_trap_BREAK_to_Debug_Mode)
  begin
    case (1'b1) // synopsys parallel_case
      MUX_csr_regfile$write_dcsr_cause_priv_1__SEL_1:
	  csr_regfile$write_dcsr_cause_priv_cause = 3'd3;
      WILL_FIRE_RL_rl_stage1_stop:
	  csr_regfile$write_dcsr_cause_priv_cause =
	      MUX_csr_regfile$write_dcsr_cause_priv_1__VAL_2;
      WILL_FIRE_RL_rl_trap_BREAK_to_Debug_Mode:
	  csr_regfile$write_dcsr_cause_priv_cause = 3'd1;
      default: csr_regfile$write_dcsr_cause_priv_cause =
		   3'b010 /* unspecified value */ ;
    endcase
  end
  assign csr_regfile$write_dcsr_cause_priv_priv =
	     (WILL_FIRE_RL_rl_stage1_stop ||
	      WILL_FIRE_RL_rl_trap_BREAK_to_Debug_Mode) ?
	       rg_cur_priv :
	       2'b11 ;
  assign csr_regfile$write_dpc_pc =
	     MUX_csr_regfile$write_dcsr_cause_priv_1__SEL_1 ?
	       soc_map$m_pc_reset_value[31:0] :
	       imem_rg_pc ;
  assign csr_regfile$EN_server_reset_request_put =
	     MUX_rg_state$write_1__SEL_5 ;
  assign csr_regfile$EN_server_reset_response_get =
	     MUX_rg_state$write_1__SEL_1 ;
  assign csr_regfile$EN_mav_read_csr = 1'b0 ;
  assign csr_regfile$EN_mav_csr_write =
	     WILL_FIRE_RL_rl_stage1_CSRR_W_2 &&
	     csr_regfile$access_permitted_1 ||
	     WILL_FIRE_RL_rl_stage1_CSRR_S_or_C_2 &&
	     csr_regfile$access_permitted_2 &&
	     rg_trap_instr[19:15] != 5'd0 ||
	     WILL_FIRE_RL_rl_debug_write_csr ;
  assign csr_regfile$EN_csr_trap_actions = CAN_FIRE_RL_rl_trap ;
  assign csr_regfile$EN_csr_ret_actions = CAN_FIRE_RL_rl_stage1_xRET ;
  assign csr_regfile$EN_csr_minstret_incr =
	     WILL_FIRE_RL_rl_pipe &&
	     IF_stage2_rg_full_5_THEN_IF_stage2_rg_stage2_6_ETC___d126 ==
	     2'd2 ||
	     WILL_FIRE_RL_rl_stage1_CSRR_W_2 &&
	     csr_regfile$access_permitted_1 ||
	     WILL_FIRE_RL_rl_stage1_CSRR_S_or_C_2 &&
	     csr_regfile$access_permitted_2 ||
	     WILL_FIRE_RL_rl_stage1_WFI ||
	     WILL_FIRE_RL_rl_stage1_FENCE ||
	     WILL_FIRE_RL_rl_stage1_FENCE_I ||
	     WILL_FIRE_RL_rl_stage1_xRET ||
	     WILL_FIRE_RL_rl_stage1_SFENCE_VMA ;
  assign csr_regfile$EN_write_dpc =
	     WILL_FIRE_RL_rl_reset_complete && !rg_run_on_reset ||
	     WILL_FIRE_RL_rl_stage1_stop ||
	     WILL_FIRE_RL_rl_trap_BREAK_to_Debug_Mode ;
  assign csr_regfile$EN_write_dcsr_cause_priv =
	     WILL_FIRE_RL_rl_reset_complete && !rg_run_on_reset ||
	     WILL_FIRE_RL_rl_stage1_stop ||
	     WILL_FIRE_RL_rl_trap_BREAK_to_Debug_Mode ;
  assign csr_regfile$EN_debug = 1'b0 ;

  // submodule f_csr_reqs
  assign f_csr_reqs$D_IN = hart0_csr_mem_server_request_put ;
  assign f_csr_reqs$ENQ = EN_hart0_csr_mem_server_request_put ;
  assign f_csr_reqs$DEQ =
	     WILL_FIRE_RL_rl_debug_csr_access_busy ||
	     WILL_FIRE_RL_rl_debug_write_csr ||
	     WILL_FIRE_RL_rl_debug_read_csr ;
  assign f_csr_reqs$CLR = 1'b0 ;

  // submodule f_csr_rsps
  always@(WILL_FIRE_RL_rl_debug_csr_access_busy or
	  WILL_FIRE_RL_rl_debug_write_csr or
	  WILL_FIRE_RL_rl_debug_read_csr or MUX_f_csr_rsps$enq_1__VAL_3)
  begin
    case (1'b1) // synopsys parallel_case
      WILL_FIRE_RL_rl_debug_csr_access_busy: f_csr_rsps$D_IN = 33'h0AAAAAAAA;
      WILL_FIRE_RL_rl_debug_write_csr: f_csr_rsps$D_IN = 33'h1AAAAAAAA;
      WILL_FIRE_RL_rl_debug_read_csr:
	  f_csr_rsps$D_IN = MUX_f_csr_rsps$enq_1__VAL_3;
      default: f_csr_rsps$D_IN = 33'h0AAAAAAAA /* unspecified value */ ;
    endcase
  end
  assign f_csr_rsps$ENQ =
	     WILL_FIRE_RL_rl_debug_csr_access_busy ||
	     WILL_FIRE_RL_rl_debug_write_csr ||
	     WILL_FIRE_RL_rl_debug_read_csr ;
  assign f_csr_rsps$DEQ = EN_hart0_csr_mem_server_response_get ;
  assign f_csr_rsps$CLR = 1'b0 ;

  // submodule f_gpr_reqs
  assign f_gpr_reqs$D_IN = hart0_gpr_mem_server_request_put ;
  assign f_gpr_reqs$ENQ = EN_hart0_gpr_mem_server_request_put ;
  assign f_gpr_reqs$DEQ =
	     WILL_FIRE_RL_rl_debug_gpr_access_busy ||
	     WILL_FIRE_RL_rl_debug_write_gpr ||
	     WILL_FIRE_RL_rl_debug_read_gpr ;
  assign f_gpr_reqs$CLR = 1'b0 ;

  // submodule f_gpr_rsps
  always@(WILL_FIRE_RL_rl_debug_gpr_access_busy or
	  WILL_FIRE_RL_rl_debug_write_gpr or
	  WILL_FIRE_RL_rl_debug_read_gpr or MUX_f_gpr_rsps$enq_1__VAL_3)
  begin
    case (1'b1) // synopsys parallel_case
      WILL_FIRE_RL_rl_debug_gpr_access_busy: f_gpr_rsps$D_IN = 33'h0AAAAAAAA;
      WILL_FIRE_RL_rl_debug_write_gpr: f_gpr_rsps$D_IN = 33'h1AAAAAAAA;
      WILL_FIRE_RL_rl_debug_read_gpr:
	  f_gpr_rsps$D_IN = MUX_f_gpr_rsps$enq_1__VAL_3;
      default: f_gpr_rsps$D_IN = 33'h0AAAAAAAA /* unspecified value */ ;
    endcase
  end
  assign f_gpr_rsps$ENQ =
	     WILL_FIRE_RL_rl_debug_gpr_access_busy ||
	     WILL_FIRE_RL_rl_debug_write_gpr ||
	     WILL_FIRE_RL_rl_debug_read_gpr ;
  assign f_gpr_rsps$DEQ = EN_hart0_gpr_mem_server_response_get ;
  assign f_gpr_rsps$CLR = 1'b0 ;

  // submodule f_reset_reqs
  assign f_reset_reqs$D_IN = hart0_server_reset_request_put ;
  assign f_reset_reqs$ENQ = EN_hart0_server_reset_request_put ;
  assign f_reset_reqs$DEQ =
	     gpr_regfile$RDY_server_reset_request_put &&
	     near_mem_RDY_server_reset_request_put__055_AND_ETC___d1067 &&
	     rg_state == 4'd0 ;
  assign f_reset_reqs$CLR = 1'b0 ;

  // submodule f_reset_rsps
  assign f_reset_rsps$D_IN = rg_run_on_reset ;
  assign f_reset_rsps$ENQ = MUX_rg_state$write_1__SEL_1 ;
  assign f_reset_rsps$DEQ = EN_hart0_server_reset_response_get ;
  assign f_reset_rsps$CLR = 1'b0 ;

  // submodule f_run_halt_reqs
  assign f_run_halt_reqs$D_IN = hart0_server_run_halt_request_put ;
  assign f_run_halt_reqs$ENQ = EN_hart0_server_run_halt_request_put ;
  assign f_run_halt_reqs$DEQ =
	     WILL_FIRE_RL_rl_debug_halt_redundant ||
	     WILL_FIRE_RL_rl_debug_run ||
	     WILL_FIRE_RL_rl_debug_halt ||
	     WILL_FIRE_RL_rl_debug_run_redundant ;
  assign f_run_halt_reqs$CLR = 1'b0 ;

  // submodule f_run_halt_rsps
  assign f_run_halt_rsps$D_IN = !MUX_f_run_halt_rsps$enq_1__SEL_1 ;
  assign f_run_halt_rsps$ENQ =
	     WILL_FIRE_RL_rl_debug_halt_redundant ||
	     WILL_FIRE_RL_rl_BREAK_cache_flush_finish ||
	     WILL_FIRE_RL_rl_trap_BREAK_to_Debug_Mode ||
	     WILL_FIRE_RL_rl_debug_run ||
	     WILL_FIRE_RL_rl_debug_run_redundant ;
  assign f_run_halt_rsps$DEQ = EN_hart0_server_run_halt_response_get ;
  assign f_run_halt_rsps$CLR = 1'b0 ;

  // submodule f_trace_data
  always@(MUX_f_trace_data$enq_1__SEL_1 or
	  MUX_f_trace_data$enq_1__VAL_1 or
	  MUX_csr_regfile$mav_csr_write_1__SEL_1 or
	  MUX_f_trace_data$enq_1__VAL_2 or
	  MUX_f_trace_data$enq_1__SEL_3 or
	  MUX_f_trace_data$enq_1__VAL_3 or
	  MUX_f_trace_data$enq_1__SEL_4 or
	  IF_NOT_stage1_rg_full_03_04_OR_NOT_near_mem_im_ETC___d1286 or
	  WILL_FIRE_RL_rl_reset_start or
	  WILL_FIRE_RL_rl_stage1_mip_cmd or
	  MUX_f_trace_data$enq_1__VAL_6 or
	  WILL_FIRE_RL_rl_trap or
	  MUX_f_trace_data$enq_1__VAL_7 or
	  WILL_FIRE_RL_rl_stage1_xRET or MUX_f_trace_data$enq_1__VAL_8)
  begin
    case (1'b1) // synopsys parallel_case
      MUX_f_trace_data$enq_1__SEL_1:
	  f_trace_data$D_IN = MUX_f_trace_data$enq_1__VAL_1;
      MUX_csr_regfile$mav_csr_write_1__SEL_1:
	  f_trace_data$D_IN = MUX_f_trace_data$enq_1__VAL_2;
      MUX_f_trace_data$enq_1__SEL_3:
	  f_trace_data$D_IN = MUX_f_trace_data$enq_1__VAL_3;
      MUX_f_trace_data$enq_1__SEL_4:
	  f_trace_data$D_IN =
	      IF_NOT_stage1_rg_full_03_04_OR_NOT_near_mem_im_ETC___d1286;
      WILL_FIRE_RL_rl_reset_start:
	  f_trace_data$D_IN =
	      235'h02AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA;
      WILL_FIRE_RL_rl_stage1_mip_cmd:
	  f_trace_data$D_IN = MUX_f_trace_data$enq_1__VAL_6;
      WILL_FIRE_RL_rl_trap: f_trace_data$D_IN = MUX_f_trace_data$enq_1__VAL_7;
      WILL_FIRE_RL_rl_stage1_xRET:
	  f_trace_data$D_IN = MUX_f_trace_data$enq_1__VAL_8;
      default: f_trace_data$D_IN =
		   235'h2AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA /* unspecified value */ ;
    endcase
  end
  assign f_trace_data$ENQ =
	     WILL_FIRE_RL_rl_pipe &&
	     IF_stage2_rg_full_5_THEN_IF_stage2_rg_stage2_6_ETC___d126 ==
	     2'd2 ||
	     WILL_FIRE_RL_rl_stage1_CSRR_W_2 &&
	     csr_regfile$access_permitted_1 ||
	     WILL_FIRE_RL_rl_stage1_CSRR_S_or_C_2 &&
	     csr_regfile$access_permitted_2 ||
	     WILL_FIRE_RL_rl_stage1_WFI ||
	     WILL_FIRE_RL_rl_stage1_FENCE ||
	     WILL_FIRE_RL_rl_stage1_FENCE_I ||
	     WILL_FIRE_RL_rl_stage1_SFENCE_VMA ||
	     WILL_FIRE_RL_rl_reset_start ||
	     WILL_FIRE_RL_rl_stage1_mip_cmd ||
	     WILL_FIRE_RL_rl_trap ||
	     WILL_FIRE_RL_rl_stage1_xRET ;
  assign f_trace_data$DEQ = EN_trace_data_out_get ;
  assign f_trace_data$CLR = 1'b0 ;

  // submodule gpr_regfile
  assign gpr_regfile$read_rs1_port2_rs1 = f_gpr_reqs$D_OUT[36:32] ;
  assign gpr_regfile$read_rs1_rs1 = _theResult____h4973[19:15] ;
  assign gpr_regfile$read_rs2_rs2 = _theResult____h4973[24:20] ;
  always@(MUX_csr_regfile$mav_csr_write_1__SEL_1 or
	  MUX_f_trace_data$enq_1__SEL_3 or
	  rg_trap_instr or
	  WILL_FIRE_RL_rl_debug_write_gpr or
	  f_gpr_reqs$D_OUT or
	  MUX_gpr_regfile$write_rd_1__SEL_1 or stage3_rg_stage3)
  begin
    case (1'b1) // synopsys parallel_case
      MUX_csr_regfile$mav_csr_write_1__SEL_1 || MUX_f_trace_data$enq_1__SEL_3:
	  gpr_regfile$write_rd_rd = rg_trap_instr[11:7];
      WILL_FIRE_RL_rl_debug_write_gpr:
	  gpr_regfile$write_rd_rd = f_gpr_reqs$D_OUT[36:32];
      MUX_gpr_regfile$write_rd_1__SEL_1:
	  gpr_regfile$write_rd_rd = stage3_rg_stage3[36:32];
      default: gpr_regfile$write_rd_rd = 5'b01010 /* unspecified value */ ;
    endcase
  end
  always@(MUX_csr_regfile$mav_csr_write_1__SEL_1 or
	  MUX_f_trace_data$enq_1__SEL_3 or
	  csr_regfile$read_csr or
	  WILL_FIRE_RL_rl_debug_write_gpr or
	  f_gpr_reqs$D_OUT or
	  MUX_gpr_regfile$write_rd_1__SEL_1 or stage3_rg_stage3)
  begin
    case (1'b1) // synopsys parallel_case
      MUX_csr_regfile$mav_csr_write_1__SEL_1 || MUX_f_trace_data$enq_1__SEL_3:
	  gpr_regfile$write_rd_rd_val = csr_regfile$read_csr[31:0];
      WILL_FIRE_RL_rl_debug_write_gpr:
	  gpr_regfile$write_rd_rd_val = f_gpr_reqs$D_OUT[31:0];
      MUX_gpr_regfile$write_rd_1__SEL_1:
	  gpr_regfile$write_rd_rd_val = stage3_rg_stage3[31:0];
      default: gpr_regfile$write_rd_rd_val =
		   32'hAAAAAAAA /* unspecified value */ ;
    endcase
  end
  assign gpr_regfile$EN_server_reset_request_put =
	     MUX_rg_state$write_1__SEL_5 ;
  assign gpr_regfile$EN_server_reset_response_get =
	     MUX_rg_state$write_1__SEL_1 ;
  assign gpr_regfile$EN_write_rd =
	     WILL_FIRE_RL_rl_pipe && stage3_rg_full && stage3_rg_stage3[37] ||
	     WILL_FIRE_RL_rl_stage1_CSRR_W_2 &&
	     csr_regfile$access_permitted_1 ||
	     WILL_FIRE_RL_rl_stage1_CSRR_S_or_C_2 &&
	     csr_regfile$access_permitted_2 ||
	     WILL_FIRE_RL_rl_debug_write_gpr ;

  // submodule near_mem
  assign near_mem$dmem_master_arready = dmem_master_arready ;
  assign near_mem$dmem_master_awready = dmem_master_awready ;
  assign near_mem$dmem_master_bid = dmem_master_bid ;
  assign near_mem$dmem_master_bresp = dmem_master_bresp ;
  assign near_mem$dmem_master_bvalid = dmem_master_bvalid ;
  assign near_mem$dmem_master_rdata = dmem_master_rdata ;
  assign near_mem$dmem_master_rid = dmem_master_rid ;
  assign near_mem$dmem_master_rlast = dmem_master_rlast ;
  assign near_mem$dmem_master_rresp = dmem_master_rresp ;
  assign near_mem$dmem_master_rvalid = dmem_master_rvalid ;
  assign near_mem$dmem_master_wready = dmem_master_wready ;
  assign near_mem$dmem_req_addr = x_out_data_to_stage2_addr__h13093 ;
  assign near_mem$dmem_req_amo_funct7 =
	     x_out_data_to_stage2_val1__h13094[6:0] ;
  assign near_mem$dmem_req_f3 = x_out_data_to_stage2_instr__h13090[14:12] ;
  assign near_mem$dmem_req_mstatus_MXR = csr_regfile$read_mstatus[19] ;
  always@(IF_NOT_stage1_rg_full_03_04_OR_NOT_near_mem_im_ETC___d854)
  begin
    case (IF_NOT_stage1_rg_full_03_04_OR_NOT_near_mem_im_ETC___d854)
      3'd1: near_mem$dmem_req_op = 2'd0;
      3'd2: near_mem$dmem_req_op = 2'd1;
      default: near_mem$dmem_req_op = 2'd2;
    endcase
  end
  assign near_mem$dmem_req_priv =
	     csr_regfile$read_mstatus[17] ?
	       csr_regfile$read_mstatus[12:11] :
	       rg_cur_priv ;
  assign near_mem$dmem_req_satp = csr_regfile$read_satp ;
  assign near_mem$dmem_req_sstatus_SUM = 1'd0 ;
  assign near_mem$dmem_req_store_value =
	     { 32'd0, x_out_data_to_stage2_val2__h13095 } ;
  assign near_mem$imem_master_arready = imem_master_arready ;
  assign near_mem$imem_master_awready = imem_master_awready ;
  assign near_mem$imem_master_bid = imem_master_bid ;
  assign near_mem$imem_master_bresp = imem_master_bresp ;
  assign near_mem$imem_master_bvalid = imem_master_bvalid ;
  assign near_mem$imem_master_rdata = imem_master_rdata ;
  assign near_mem$imem_master_rid = imem_master_rid ;
  assign near_mem$imem_master_rlast = imem_master_rlast ;
  assign near_mem$imem_master_rresp = imem_master_rresp ;
  assign near_mem$imem_master_rvalid = imem_master_rvalid ;
  assign near_mem$imem_master_wready = imem_master_wready ;
  always@(MUX_imem_rg_f3$write_1__SEL_1 or
	  MUX_near_mem$imem_req_2__VAL_1 or
	  MUX_imem_rg_f3$write_1__SEL_2 or
	  MUX_near_mem$imem_req_2__VAL_2 or
	  WILL_FIRE_RL_imem_rl_fetch_next_32b or
	  MUX_imem_rg_tval$write_1__VAL_6 or
	  WILL_FIRE_RL_rl_stage1_restart_after_csrrx or
	  WILL_FIRE_RL_rl_trap_fetch or
	  MUX_near_mem$imem_req_2__VAL_5 or
	  MUX_near_mem$imem_req_1__SEL_6 or
	  WILL_FIRE_RL_rl_debug_run or MUX_near_mem$imem_req_2__VAL_7)
  begin
    case (1'b1) // synopsys parallel_case
      MUX_imem_rg_f3$write_1__SEL_1:
	  near_mem$imem_req_addr = MUX_near_mem$imem_req_2__VAL_1;
      MUX_imem_rg_f3$write_1__SEL_2:
	  near_mem$imem_req_addr = MUX_near_mem$imem_req_2__VAL_2;
      WILL_FIRE_RL_imem_rl_fetch_next_32b:
	  near_mem$imem_req_addr = MUX_imem_rg_tval$write_1__VAL_6;
      WILL_FIRE_RL_rl_stage1_restart_after_csrrx:
	  near_mem$imem_req_addr = MUX_near_mem$imem_req_2__VAL_2;
      WILL_FIRE_RL_rl_trap_fetch:
	  near_mem$imem_req_addr = MUX_near_mem$imem_req_2__VAL_5;
      MUX_near_mem$imem_req_1__SEL_6:
	  near_mem$imem_req_addr = MUX_near_mem$imem_req_2__VAL_5;
      WILL_FIRE_RL_rl_debug_run:
	  near_mem$imem_req_addr = MUX_near_mem$imem_req_2__VAL_7;
      default: near_mem$imem_req_addr = 32'hAAAAAAAA /* unspecified value */ ;
    endcase
  end
  assign near_mem$imem_req_f3 =
	     WILL_FIRE_RL_imem_rl_fetch_next_32b ? imem_rg_f3 : 3'b010 ;
  always@(MUX_imem_rg_f3$write_1__SEL_1 or
	  MUX_imem_rg_f3$write_1__SEL_2 or
	  WILL_FIRE_RL_rl_stage1_restart_after_csrrx or
	  MUX_near_mem$imem_req_1__SEL_6 or
	  WILL_FIRE_RL_rl_debug_run or
	  csr_regfile$read_mstatus or
	  WILL_FIRE_RL_rl_trap_fetch or
	  rg_mstatus_MXR or
	  WILL_FIRE_RL_imem_rl_fetch_next_32b or imem_rg_mstatus_MXR)
  begin
    case (1'b1) // synopsys parallel_case
      MUX_imem_rg_f3$write_1__SEL_1 || MUX_imem_rg_f3$write_1__SEL_2 ||
      WILL_FIRE_RL_rl_stage1_restart_after_csrrx ||
      MUX_near_mem$imem_req_1__SEL_6 ||
      WILL_FIRE_RL_rl_debug_run:
	  near_mem$imem_req_mstatus_MXR = csr_regfile$read_mstatus[19];
      WILL_FIRE_RL_rl_trap_fetch:
	  near_mem$imem_req_mstatus_MXR = rg_mstatus_MXR;
      WILL_FIRE_RL_imem_rl_fetch_next_32b:
	  near_mem$imem_req_mstatus_MXR = imem_rg_mstatus_MXR;
      default: near_mem$imem_req_mstatus_MXR = 1'b0 /* unspecified value */ ;
    endcase
  end
  assign near_mem$imem_req_priv =
	     (MUX_imem_rg_f3$write_1__SEL_1 ||
	      MUX_imem_rg_f3$write_1__SEL_2 ||
	      WILL_FIRE_RL_rl_stage1_restart_after_csrrx ||
	      WILL_FIRE_RL_rl_trap_fetch ||
	      MUX_near_mem$imem_req_1__SEL_6 ||
	      WILL_FIRE_RL_rl_debug_run) ?
	       rg_cur_priv :
	       imem_rg_priv ;
  assign near_mem$imem_req_satp =
	     WILL_FIRE_RL_imem_rl_fetch_next_32b ?
	       imem_rg_satp :
	       csr_regfile$read_satp ;
  always@(WILL_FIRE_RL_rl_trap_fetch or
	  rg_sstatus_SUM or
	  WILL_FIRE_RL_imem_rl_fetch_next_32b or
	  imem_rg_sstatus_SUM or
	  MUX_imem_rg_f3$write_1__SEL_1 or
	  MUX_imem_rg_f3$write_1__SEL_2 or
	  WILL_FIRE_RL_rl_stage1_restart_after_csrrx or
	  MUX_near_mem$imem_req_1__SEL_6 or WILL_FIRE_RL_rl_debug_run)
  begin
    case (1'b1) // synopsys parallel_case
      WILL_FIRE_RL_rl_trap_fetch:
	  near_mem$imem_req_sstatus_SUM = rg_sstatus_SUM;
      WILL_FIRE_RL_imem_rl_fetch_next_32b:
	  near_mem$imem_req_sstatus_SUM = imem_rg_sstatus_SUM;
      MUX_imem_rg_f3$write_1__SEL_1 || MUX_imem_rg_f3$write_1__SEL_2 ||
      WILL_FIRE_RL_rl_stage1_restart_after_csrrx ||
      MUX_near_mem$imem_req_1__SEL_6 ||
      WILL_FIRE_RL_rl_debug_run:
	  near_mem$imem_req_sstatus_SUM = 1'd0;
      default: near_mem$imem_req_sstatus_SUM = 1'b0 /* unspecified value */ ;
    endcase
  end
  assign near_mem$server_fence_request_put =
	     8'b10101010 /* unspecified value */  ;
  assign near_mem$EN_server_reset_request_put = MUX_rg_state$write_1__SEL_5 ;
  assign near_mem$EN_server_reset_response_get = MUX_rg_state$write_1__SEL_1 ;
  assign near_mem$EN_imem_req =
	     WILL_FIRE_RL_rl_reset_complete && rg_run_on_reset ||
	     WILL_FIRE_RL_rl_pipe &&
	     NOT_stage1_rg_full_03_04_OR_NOT_near_mem_imem__ETC___d1324 ||
	     WILL_FIRE_RL_imem_rl_fetch_next_32b ||
	     WILL_FIRE_RL_rl_stage1_restart_after_csrrx ||
	     WILL_FIRE_RL_rl_trap_fetch ||
	     WILL_FIRE_RL_rl_WFI_resume ||
	     WILL_FIRE_RL_rl_finish_SFENCE_VMA ||
	     WILL_FIRE_RL_rl_finish_FENCE ||
	     WILL_FIRE_RL_rl_finish_FENCE_I ||
	     WILL_FIRE_RL_rl_debug_run ;
  assign near_mem$EN_dmem_req =
	     WILL_FIRE_RL_rl_pipe &&
	     near_mem_imem_exc__14_OR_IF_IF_imem_rg_pc_BITS_ETC___d1227 &&
	     stage1_rg_full &&
	     near_mem_imem_valid_AND_NOT_imem_rg_pc_BITS_1__ETC___d714 &&
	     (IF_NOT_stage1_rg_full_03_04_OR_NOT_near_mem_im_ETC___d854 ==
	      3'd1 ||
	      IF_NOT_stage1_rg_full_03_04_OR_NOT_near_mem_im_ETC___d854 ==
	      3'd2 ||
	      IF_NOT_stage1_rg_full_03_04_OR_NOT_near_mem_im_ETC___d854 ==
	      3'd4) ;
  assign near_mem$EN_server_fence_i_request_put =
	     WILL_FIRE_RL_rl_stage1_stop ||
	     WILL_FIRE_RL_rl_trap_BREAK_to_Debug_Mode ||
	     WILL_FIRE_RL_rl_stage1_FENCE_I ;
  assign near_mem$EN_server_fence_i_response_get =
	     WILL_FIRE_RL_rl_BREAK_cache_flush_finish ||
	     WILL_FIRE_RL_rl_finish_FENCE_I ;
  assign near_mem$EN_server_fence_request_put = CAN_FIRE_RL_rl_stage1_FENCE ;
  assign near_mem$EN_server_fence_response_get = CAN_FIRE_RL_rl_finish_FENCE ;
  assign near_mem$EN_sfence_vma = CAN_FIRE_RL_rl_stage1_SFENCE_VMA ;

  // submodule soc_map
  assign soc_map$m_is_IO_addr_addr = 64'h0 ;
  assign soc_map$m_is_mem_addr_addr = 64'h0 ;
  assign soc_map$m_is_near_mem_IO_addr_addr = 64'h0 ;

  // submodule stage1_f_reset_reqs
  assign stage1_f_reset_reqs$ENQ = MUX_rg_state$write_1__SEL_5 ;
  assign stage1_f_reset_reqs$DEQ = CAN_FIRE_RL_stage1_rl_reset ;
  assign stage1_f_reset_reqs$CLR = 1'b0 ;

  // submodule stage1_f_reset_rsps
  assign stage1_f_reset_rsps$ENQ = CAN_FIRE_RL_stage1_rl_reset ;
  assign stage1_f_reset_rsps$DEQ = MUX_rg_state$write_1__SEL_1 ;
  assign stage1_f_reset_rsps$CLR = 1'b0 ;

  // submodule stage2_f_reset_reqs
  assign stage2_f_reset_reqs$ENQ = MUX_rg_state$write_1__SEL_5 ;
  assign stage2_f_reset_reqs$DEQ = stage2_f_reset_reqs$EMPTY_N ;
  assign stage2_f_reset_reqs$CLR = 1'b0 ;

  // submodule stage2_f_reset_rsps
  assign stage2_f_reset_rsps$ENQ = CAN_FIRE_RL_stage2_rl_reset_end ;
  assign stage2_f_reset_rsps$DEQ = MUX_rg_state$write_1__SEL_1 ;
  assign stage2_f_reset_rsps$CLR = 1'b0 ;

  // submodule stage2_mbox
  assign stage2_mbox$req_f3 = x_out_data_to_stage2_instr__h13090[14:12] ;
  assign stage2_mbox$req_is_OP_not_OP_32 = !_theResult____h4973[3] ;
  assign stage2_mbox$req_v1 = x_out_data_to_stage2_val1__h13094 ;
  assign stage2_mbox$req_v2 = x_out_data_to_stage2_val2__h13095 ;
  assign stage2_mbox$set_verbosity_verbosity = 4'h0 ;
  assign stage2_mbox$EN_set_verbosity = 1'b0 ;
  assign stage2_mbox$EN_req_reset = 1'b0 ;
  assign stage2_mbox$EN_rsp_reset = 1'b0 ;
  assign stage2_mbox$EN_req =
	     WILL_FIRE_RL_rl_pipe &&
	     near_mem_imem_exc__14_OR_IF_IF_imem_rg_pc_BITS_ETC___d1227 &&
	     stage1_rg_full &&
	     near_mem_imem_valid_AND_NOT_imem_rg_pc_BITS_1__ETC___d714 &&
	     IF_NOT_stage1_rg_full_03_04_OR_NOT_near_mem_im_ETC___d854 ==
	     3'd3 ;

  // submodule stage3_f_reset_reqs
  assign stage3_f_reset_reqs$ENQ = MUX_rg_state$write_1__SEL_5 ;
  assign stage3_f_reset_reqs$DEQ = CAN_FIRE_RL_stage3_rl_reset ;
  assign stage3_f_reset_reqs$CLR = 1'b0 ;

  // submodule stage3_f_reset_rsps
  assign stage3_f_reset_rsps$ENQ = CAN_FIRE_RL_stage3_rl_reset ;
  assign stage3_f_reset_rsps$DEQ = MUX_rg_state$write_1__SEL_1 ;
  assign stage3_f_reset_rsps$CLR = 1'b0 ;

  // remaining internal signals
  assign IF_IF_imem_rg_pc_BITS_1_TO_0_EQ_0b0_OR_NOT_ime_ETC___d1113 =
	     IF_IF_imem_rg_pc_BITS_1_TO_0_EQ_0b0_OR_NOT_ime_ETC___d709 ||
	     IF_IF_imem_rg_pc_BITS_1_TO_0_EQ_0b0_OR_NOT_ime_ETC___d711 ||
	     near_mem$imem_exc ||
	     IF_IF_imem_rg_pc_BITS_1_TO_0_EQ_0b0_OR_NOT_ime_ETC___d651 &&
	     IF_IF_imem_rg_pc_BITS_1_TO_0_EQ_0b0_OR_NOT_ime_ETC___d662 ;
  assign IF_IF_imem_rg_pc_BITS_1_TO_0_EQ_0b0_OR_NOT_ime_ETC___d1151 =
	     (IF_IF_imem_rg_pc_BITS_1_TO_0_EQ_0b0_OR_NOT_ime_ETC___d709 ||
	      IF_IF_imem_rg_pc_BITS_1_TO_0_EQ_0b0_OR_NOT_ime_ETC___d711) &&
	     (rg_stop_req || rg_step_count) ||
	     (csr_regfile$interrupt_pending[4] || csr_regfile$nmi_pending) &&
	     (IF_IF_imem_rg_pc_BITS_1_TO_0_EQ_0b0_OR_NOT_ime_ETC___d709 ||
	      IF_IF_imem_rg_pc_BITS_1_TO_0_EQ_0b0_OR_NOT_ime_ETC___d711) ;
  assign IF_IF_imem_rg_pc_BITS_1_TO_0_EQ_0b0_OR_NOT_ime_ETC___d1160 =
	     (IF_IF_imem_rg_pc_BITS_1_TO_0_EQ_0b0_OR_NOT_ime_ETC___d1151 ||
	      IF_stage2_rg_full_5_THEN_IF_stage2_rg_stage2_6_ETC___d126 !=
	      2'd2 &&
	      IF_stage2_rg_full_5_THEN_IF_stage2_rg_stage2_6_ETC___d126 !=
	      2'd0 ||
	      NOT_imem_rg_pc_BITS_31_TO_2_0_EQ_imem_rg_cache_ETC___d1157 ||
	      near_mem$imem_exc ||
	      IF_IF_imem_rg_pc_BITS_1_TO_0_EQ_0b0_OR_NOT_ime_ETC___d651 &&
	      IF_IF_imem_rg_pc_BITS_1_TO_0_EQ_0b0_OR_NOT_ime_ETC___d662) &&
	     stage1_rg_full ;
  assign IF_IF_imem_rg_pc_BITS_1_TO_0_EQ_0b0_OR_NOT_ime_ETC___d1257 =
	     ((_theResult____h4973[6:0] == 7'b0010011 ||
	       _theResult____h4973[6:0] == 7'b0110011) &&
	      (_theResult____h4973[14:12] == 3'b001 ||
	       _theResult____h4973[14:12] == 3'b101)) ?
	       _theResult____h13381 :
	       IF_IF_imem_rg_pc_BITS_1_TO_0_EQ_0b0_OR_NOT_ime_ETC___d1256 ;
  assign IF_IF_imem_rg_pc_BITS_1_TO_0_EQ_0b0_OR_NOT_ime_ETC___d1372 =
	     (IF_IF_imem_rg_pc_BITS_1_TO_0_EQ_0b0_OR_NOT_ime_ETC___d709 ||
	      IF_IF_imem_rg_pc_BITS_1_TO_0_EQ_0b0_OR_NOT_ime_ETC___d711) &&
	     (rg_stop_req || rg_step_count) ||
	     !csr_regfile_csr_mip_read__118_EQ_rg_prev_mip_119___d1120 ;
  assign IF_IF_imem_rg_pc_BITS_1_TO_0_EQ_0b0_OR_NOT_ime_ETC___d1373 =
	     IF_IF_imem_rg_pc_BITS_1_TO_0_EQ_0b0_OR_NOT_ime_ETC___d1372 ||
	     (csr_regfile$interrupt_pending[4] || csr_regfile$nmi_pending) &&
	     (IF_IF_imem_rg_pc_BITS_1_TO_0_EQ_0b0_OR_NOT_ime_ETC___d709 ||
	      IF_IF_imem_rg_pc_BITS_1_TO_0_EQ_0b0_OR_NOT_ime_ETC___d711) ;
  assign IF_IF_imem_rg_pc_BITS_1_TO_0_EQ_0b0_OR_NOT_ime_ETC___d1377 =
	     (IF_IF_imem_rg_pc_BITS_1_TO_0_EQ_0b0_OR_NOT_ime_ETC___d1373 ||
	      IF_stage2_rg_full_5_THEN_IF_stage2_rg_stage2_6_ETC___d126 !=
	      2'd2 &&
	      IF_stage2_rg_full_5_THEN_IF_stage2_rg_stage2_6_ETC___d126 !=
	      2'd0 ||
	      NOT_near_mem_imem_valid_05_OR_imem_rg_pc_BITS__ETC___d1181) &&
	     stage1_rg_full ;
  assign IF_IF_imem_rg_pc_BITS_1_TO_0_EQ_0b0_OR_NOT_ime_ETC___d552 =
	     rs1_val_bypassed__h4981 == rs2_val__h13206 ;
  assign IF_IF_imem_rg_pc_BITS_1_TO_0_EQ_0b0_OR_NOT_ime_ETC___d554 =
	     (rs1_val_bypassed__h4981 ^ 32'h80000000) <
	     (rs2_val__h13206 ^ 32'h80000000) ;
  assign IF_IF_imem_rg_pc_BITS_1_TO_0_EQ_0b0_OR_NOT_ime_ETC___d556 =
	     rs1_val_bypassed__h4981 < rs2_val__h13206 ;
  assign IF_IF_imem_rg_pc_BITS_1_TO_0_EQ_0b0_OR_NOT_ime_ETC___d651 =
	     (_theResult____h4973[6:0] == 7'b1100011) ?
	       _theResult____h4973[14:12] != 3'b0 &&
	       _theResult____h4973[14:12] != 3'b001 &&
	       _theResult____h4973[14:12] != 3'b100 &&
	       _theResult____h4973[14:12] != 3'b101 &&
	       _theResult____h4973[14:12] != 3'b110 &&
	       _theResult____h4973[14:12] != 3'b111 ||
	       IF_IF_imem_rg_pc_BITS_1_TO_0_EQ_0b0_OR_NOT_ime_ETC___d563 :
	       (_theResult____h4973[6:0] != 7'b0110011 ||
		_theResult____h4973[31:25] != 7'b0000001) &&
	       (((_theResult____h4973[6:0] == 7'b0010011 ||
		  _theResult____h4973[6:0] == 7'b0110011) &&
		 (_theResult____h4973[14:12] == 3'b001 ||
		  _theResult____h4973[14:12] == 3'b101)) ?
		  _theResult____h4973[25] :
		  CASE_theResult__973_BITS_6_TO_0_0b10011_NOT_IF_ETC__q9) ;
  assign IF_IF_imem_rg_pc_BITS_1_TO_0_EQ_0b0_OR_NOT_ime_ETC___d662 =
	     (_theResult____h4973[6:0] == 7'b1100011) ?
	       _theResult____h4973[14:12] != 3'b0 &&
	       _theResult____h4973[14:12] != 3'b001 &&
	       _theResult____h4973[14:12] != 3'b100 &&
	       _theResult____h4973[14:12] != 3'b101 &&
	       _theResult____h4973[14:12] != 3'b110 &&
	       _theResult____h4973[14:12] != 3'b111 ||
	       IF_IF_imem_rg_pc_BITS_1_TO_0_EQ_0b0_OR_NOT_ime_ETC___d657 :
	       _theResult____h4973[6:0] != 7'b1101111 &&
	       _theResult____h4973[6:0] != 7'b1100111 ;
  assign IF_IF_imem_rg_pc_BITS_1_TO_0_EQ_0b0_OR_NOT_ime_ETC___d709 =
	     (_theResult____h4973[6:0] == 7'b1100011) ?
	       (_theResult____h4973[14:12] == 3'b0 ||
		_theResult____h4973[14:12] == 3'b001 ||
		_theResult____h4973[14:12] == 3'b100 ||
		_theResult____h4973[14:12] == 3'b101 ||
		_theResult____h4973[14:12] == 3'b110 ||
		_theResult____h4973[14:12] == 3'b111) &&
	       IF_IF_imem_rg_pc_BITS_1_TO_0_EQ_0b0_OR_NOT_ime_ETC___d657 :
	       _theResult____h4973[6:0] == 7'b0110011 &&
	       _theResult____h4973[31:25] == 7'b0000001 ||
	       (((_theResult____h4973[6:0] == 7'b0010011 ||
		  _theResult____h4973[6:0] == 7'b0110011) &&
		 (_theResult____h4973[14:12] == 3'b001 ||
		  _theResult____h4973[14:12] == 3'b101)) ?
		  !_theResult____h4973[25] :
		  CASE_theResult__973_BITS_6_TO_0_0b10011_IF_ime_ETC__q11) ;
  assign IF_IF_imem_rg_pc_BITS_1_TO_0_EQ_0b0_OR_NOT_ime_ETC___d711 =
	     (_theResult____h4973[6:0] == 7'b1100011) ?
	       (_theResult____h4973[14:12] == 3'b0 ||
		_theResult____h4973[14:12] == 3'b001 ||
		_theResult____h4973[14:12] == 3'b100 ||
		_theResult____h4973[14:12] == 3'b101 ||
		_theResult____h4973[14:12] == 3'b110 ||
		_theResult____h4973[14:12] == 3'b111) &&
	       IF_IF_imem_rg_pc_BITS_1_TO_0_EQ_0b0_OR_NOT_ime_ETC___d563 :
	       _theResult____h4973[6:0] == 7'b1101111 ||
	       _theResult____h4973[6:0] == 7'b1100111 ;
  assign IF_IF_imem_rg_pc_BITS_1_TO_0_EQ_0b0_OR_NOT_ime_ETC___d966 =
	     ((_theResult____h4973[6:0] == 7'b0010011 ||
	       _theResult____h4973[6:0] == 7'b0110011) &&
	      (_theResult____h4973[14:12] == 3'b001 ||
	       _theResult____h4973[14:12] == 3'b101)) ?
	       _theResult____h13381 :
	       IF_IF_imem_rg_pc_BITS_1_TO_0_EQ_0b0_OR_NOT_ime_ETC___d965 ;
  assign IF_NOT_IF_imem_rg_pc_BITS_1_TO_0_EQ_0b0_OR_NOT_ETC___d719 =
	     NOT_IF_imem_rg_pc_BITS_1_TO_0_EQ_0b0_OR_NOT_im_ETC___d593 ?
	       4'd11 :
	       4'd0 ;
  assign IF_NOT_imem_rg_pc_BITS_1_TO_0_EQ_0b0_AND_imem__ETC___d251 =
	     NOT_imem_rg_pc_BITS_1_TO_0_EQ_0b0_AND_imem_rg__ETC___d248 ?
	       { 16'b0,
		 imem_rg_pc_BITS_31_TO_2_0_EQ_near_mem_imem_pc__ETC___d13 ?
		   near_mem$imem_instr[31:16] :
		   imem_rg_cache_b16 } :
	       near_mem$imem_instr ;
  assign IF_NOT_near_mem_dmem_valid__17_36_OR_NOT_near__ETC___d184 =
	     (!near_mem$dmem_valid || !near_mem$dmem_exc) ?
	       IF_stage2_rg_stage2_6_BITS_335_TO_331_56_EQ_0__ETC___d183 :
	       2'd0 ;
  assign IF_NOT_stage1_rg_full_03_04_OR_NOT_near_mem_im_ETC___d1286 =
	     { CASE_theResult__973_BITS_6_TO_0_0b11_9_0b1111__ETC__q18,
	       x__h19341,
	       NOT_imem_rg_pc_BITS_1_TO_0_EQ_0b0_AND_imem_rg__ETC___d505,
	       x__h19433,
	       x_out_data_to_stage2_trace_data_rd__h18721,
	       x__h19610,
	       rs2_val__h13206,
	       x_out_data_to_stage2_trace_data_word3__h18724,
	       x__h19810 } ;
  assign IF_NOT_stage1_rg_full_03_04_OR_NOT_near_mem_im_ETC___d775 =
	     near_mem$imem_exc ?
	       4'd11 :
	       IF_IF_imem_rg_pc_BITS_1_TO_0_EQ_0b0_OR_NOT_ime_ETC___d773 ;
  assign IF_csr_regfile_read_csr_rg_trap_instr_435_BITS_ETC___d1487 =
	     csr_regfile$read_csr[31:0] | rs1_val__h23025 ;
  assign IF_csr_regfile_read_misa__8_BIT_2_35_AND_IF_NO_ETC___d466 =
	     (csr_regfile$read_misa[2] && instr__h4971[1:0] == 2'b01 &&
	      instr__h4971[15:10] == 6'b100011 &&
	      instr__h4971[6:5] == 2'b0) ?
	       instr__h12620 :
	       ((csr_regfile$read_misa[2] && instr__h4971[1:0] == 2'b10 &&
		 instr__h4971[15:12] == 4'b1001 &&
		 instr__h4971[11:7] == 5'd0 &&
		 instr__h4971[6:2] == 5'd0) ?
		  instr__h12958 :
		  32'h0) ;
  assign IF_csr_regfile_read_misa__8_BIT_2_35_AND_IF_NO_ETC___d468 =
	     (csr_regfile$read_misa[2] && instr__h4971[1:0] == 2'b01 &&
	      instr__h4971[15:10] == 6'b100011 &&
	      instr__h4971[6:5] == 2'b10) ?
	       instr__h12348 :
	       ((csr_regfile$read_misa[2] && instr__h4971[1:0] == 2'b01 &&
		 instr__h4971[15:10] == 6'b100011 &&
		 instr__h4971[6:5] == 2'b01) ?
		  instr__h12484 :
		  IF_csr_regfile_read_misa__8_BIT_2_35_AND_IF_NO_ETC___d466) ;
  assign IF_csr_regfile_read_misa__8_BIT_2_35_AND_IF_NO_ETC___d470 =
	     (csr_regfile_read_misa__8_BIT_2_35_AND_IF_NOT_i_ETC___d337 &&
	      instr__h4971[6:2] != 5'd0) ?
	       instr__h12117 :
	       ((csr_regfile$read_misa[2] && instr__h4971[1:0] == 2'b01 &&
		 instr__h4971[15:10] == 6'b100011 &&
		 instr__h4971[6:5] == 2'b11) ?
		  instr__h12212 :
		  IF_csr_regfile_read_misa__8_BIT_2_35_AND_IF_NO_ETC___d468) ;
  assign IF_csr_regfile_read_misa__8_BIT_2_35_AND_IF_NO_ETC___d471 =
	     (csr_regfile_read_misa__8_BIT_2_35_AND_IF_NOT_i_ETC___d331 &&
	      instr__h4971[6:2] != 5'd0) ?
	       instr__h11998 :
	       IF_csr_regfile_read_misa__8_BIT_2_35_AND_IF_NO_ETC___d470 ;
  assign IF_csr_regfile_read_misa__8_BIT_2_35_AND_IF_NO_ETC___d473 =
	     (csr_regfile$read_misa[2] && instr__h4971[1:0] == 2'b01 &&
	      instr__h4971[15:13] == 3'b100 &&
	      instr__h4971[11:10] == 2'b01 &&
	      imm6__h10144 != 6'd0 &&
	      !instr__h4971[12]) ?
	       instr__h11703 :
	       ((csr_regfile$read_misa[2] && instr__h4971[1:0] == 2'b01 &&
		 instr__h4971[15:13] == 3'b100 &&
		 instr__h4971[11:10] == 2'b10) ?
		  instr__h11820 :
		  IF_csr_regfile_read_misa__8_BIT_2_35_AND_IF_NO_ETC___d471) ;
  assign IF_csr_regfile_read_misa__8_BIT_2_35_AND_IF_NO_ETC___d474 =
	     (csr_regfile$read_misa[2] && instr__h4971[1:0] == 2'b01 &&
	      instr__h4971[15:13] == 3'b100 &&
	      instr__h4971[11:10] == 2'b0 &&
	      imm6__h10144 != 6'd0 &&
	      !instr__h4971[12]) ?
	       instr__h11510 :
	       IF_csr_regfile_read_misa__8_BIT_2_35_AND_IF_NO_ETC___d473 ;
  assign IF_csr_regfile_read_misa__8_BIT_2_35_AND_IF_NO_ETC___d475 =
	     (csr_regfile$read_misa[2] && instr__h4971[1:0] == 2'b10 &&
	      instr__h4971[15:13] == 3'b0 &&
	      instr__h4971[11:7] != 5'd0 &&
	      imm6__h10144 != 6'd0 &&
	      !instr__h4971[12]) ?
	       instr__h11317 :
	       IF_csr_regfile_read_misa__8_BIT_2_35_AND_IF_NO_ETC___d474 ;
  assign IF_csr_regfile_read_misa__8_BIT_2_35_AND_IF_NO_ETC___d477 =
	     (csr_regfile$read_misa[2] && instr__h4971[1:0] == 2'b01 &&
	      instr__h4971[15:13] == 3'b011 &&
	      instr__h4971[11:7] == 5'd2 &&
	      nzimm10__h10768 != 10'd0) ?
	       instr__h10972 :
	       ((csr_regfile$read_misa[2] && instr__h4971[1:0] == 2'b0 &&
		 instr__h4971[15:13] == 3'b0 &&
		 nzimm10__h10983 != 10'd0) ?
		  instr__h11144 :
		  IF_csr_regfile_read_misa__8_BIT_2_35_AND_IF_NO_ETC___d475) ;
  assign IF_csr_regfile_read_misa__8_BIT_2_35_AND_IF_NO_ETC___d478 =
	     (csr_regfile$read_misa[2] && instr__h4971[1:0] == 2'b01 &&
	      instr__h4971[15:13] == 3'b0 &&
	      instr__h4971[11:7] != 5'd0 &&
	      imm6__h10144 != 6'd0 ||
	      csr_regfile$read_misa[2] && instr__h4971[1:0] == 2'b01 &&
	      instr__h4971[15:13] == 3'b0 &&
	      instr__h4971[11:7] == 5'd0 &&
	      imm6__h10144 == 6'd0) ?
	       instr__h10535 :
	       IF_csr_regfile_read_misa__8_BIT_2_35_AND_IF_NO_ETC___d477 ;
  assign IF_csr_regfile_read_misa__8_BIT_2_35_AND_IF_NO_ETC___d479 =
	     (csr_regfile$read_misa[2] && instr__h4971[1:0] == 2'b01 &&
	      instr__h4971[15:13] == 3'b011 &&
	      instr__h4971[11:7] != 5'd0 &&
	      instr__h4971[11:7] != 5'd2 &&
	      imm6__h10144 != 6'd0) ?
	       instr__h10406 :
	       IF_csr_regfile_read_misa__8_BIT_2_35_AND_IF_NO_ETC___d478 ;
  assign IF_csr_regfile_read_misa__8_BIT_2_35_AND_IF_NO_ETC___d481 =
	     (csr_regfile$read_misa[2] && instr__h4971[1:0] == 2'b01 &&
	      instr__h4971[15:13] == 3'b111) ?
	       instr__h9884 :
	       ((csr_regfile$read_misa[2] && instr__h4971[1:0] == 2'b01 &&
		 instr__h4971[15:13] == 3'b010 &&
		 instr__h4971[11:7] != 5'd0) ?
		  instr__h10222 :
		  IF_csr_regfile_read_misa__8_BIT_2_35_AND_IF_NO_ETC___d479) ;
  assign IF_csr_regfile_read_misa__8_BIT_2_35_AND_IF_NO_ETC___d482 =
	     (csr_regfile$read_misa[2] && instr__h4971[1:0] == 2'b01 &&
	      instr__h4971[15:13] == 3'b110) ?
	       instr__h9567 :
	       IF_csr_regfile_read_misa__8_BIT_2_35_AND_IF_NO_ETC___d481 ;
  assign IF_csr_regfile_read_misa__8_BIT_2_35_AND_IF_NO_ETC___d483 =
	     (csr_regfile_read_misa__8_BIT_2_35_AND_IF_NOT_i_ETC___d337 &&
	      instr__h4971[6:2] == 5'd0) ?
	       instr__h9502 :
	       IF_csr_regfile_read_misa__8_BIT_2_35_AND_IF_NO_ETC___d482 ;
  assign IF_csr_regfile_read_misa__8_BIT_2_35_AND_IF_NO_ETC___d484 =
	     (csr_regfile_read_misa__8_BIT_2_35_AND_IF_NOT_i_ETC___d331 &&
	      instr__h4971[6:2] == 5'd0) ?
	       instr__h9386 :
	       IF_csr_regfile_read_misa__8_BIT_2_35_AND_IF_NO_ETC___d483 ;
  assign IF_csr_regfile_read_misa__8_BIT_2_35_AND_IF_NO_ETC___d485 =
	     (csr_regfile$read_misa[2] && instr__h4971[1:0] == 2'b01 &&
	      instr__h4971[15:13] == 3'b001) ?
	       instr__h8996 :
	       IF_csr_regfile_read_misa__8_BIT_2_35_AND_IF_NO_ETC___d484 ;
  assign IF_csr_regfile_read_misa__8_BIT_2_35_AND_IF_NO_ETC___d486 =
	     (csr_regfile$read_misa[2] && instr__h4971[1:0] == 2'b01 &&
	      instr__h4971[15:13] == 3'b101) ?
	       instr__h8653 :
	       IF_csr_regfile_read_misa__8_BIT_2_35_AND_IF_NO_ETC___d485 ;
  assign IF_csr_regfile_read_misa__8_BIT_2_35_AND_IF_NO_ETC___d487 =
	     (csr_regfile$read_misa[2] && instr__h4971[1:0] == 2'b0 &&
	      instr__h4971[15:13] == 3'b110) ?
	       instr__h8424 :
	       IF_csr_regfile_read_misa__8_BIT_2_35_AND_IF_NO_ETC___d486 ;
  assign IF_csr_regfile_read_misa__8_BIT_2_35_AND_IF_NO_ETC___d488 =
	     (csr_regfile$read_misa[2] && instr__h4971[1:0] == 2'b0 &&
	      instr__h4971[15:13] == 3'b010) ?
	       instr__h8229 :
	       IF_csr_regfile_read_misa__8_BIT_2_35_AND_IF_NO_ETC___d487 ;
  assign IF_csr_regfile_read_misa__8_BIT_2_35_AND_IF_NO_ETC___d489 =
	     (csr_regfile$read_misa[2] && instr__h4971[1:0] == 2'b10 &&
	      instr__h4971[15:13] == 3'b110) ?
	       instr__h8037 :
	       IF_csr_regfile_read_misa__8_BIT_2_35_AND_IF_NO_ETC___d488 ;
  assign IF_imem_rg_pc_BITS_1_TO_0_EQ_0b0_AND_imem_rg_p_ETC___d252 =
	     (imem_rg_pc[1:0] == 2'b0 &&
	      imem_rg_pc_BITS_31_TO_2_0_EQ_near_mem_imem_pc__ETC___d13 &&
	      near_mem$imem_instr[1:0] != 2'b11) ?
	       instr_out___1__h7771 :
	       IF_NOT_imem_rg_pc_BITS_1_TO_0_EQ_0b0_AND_imem__ETC___d251 ;
  assign IF_imem_rg_pc_BITS_1_TO_0_EQ_0b0_OR_NOT_imem_r_ETC___d682 =
	     _theResult____h4973[14:12] == 3'b0 &&
	     (_theResult____h4973[6:0] != 7'b0110011 ||
	      !_theResult____h4973[30]) ||
	     _theResult____h4973[14:12] == 3'b0 &&
	     _theResult____h4973[6:0] == 7'b0110011 &&
	     _theResult____h4973[30] ||
	     _theResult____h4973[14:12] == 3'b010 ||
	     _theResult____h4973[14:12] == 3'b011 ||
	     _theResult____h4973[14:12] == 3'b100 ||
	     _theResult____h4973[14:12] == 3'b110 ||
	     _theResult____h4973[14:12] == 3'b111 ;
  assign IF_imem_rg_pc_BITS_1_TO_0_EQ_0b0_OR_NOT_imem_r_ETC___d898 =
	     imem_rg_pc_BITS_1_TO_0_EQ_0b0_OR_NOT_imem_rg_p_ETC___d226 ?
	       next_pc___1__h14997 :
	       next_pc__h14995 ;
  assign IF_near_mem_dmem_valid__17_THEN_IF_near_mem_dm_ETC___d120 =
	     near_mem$dmem_valid ? (near_mem$dmem_exc ? 2'd3 : 2'd2) : 2'd1 ;
  assign IF_near_mem_imem_exc__14_THEN_near_mem_imem_ex_ETC___d1405 =
	     near_mem$imem_exc ?
	       { near_mem$imem_exc_code, imem_rg_tval } :
	       { alu_outputs_exc_code__h13792, trap_info_tval__h14833 } ;
  assign IF_rg_cur_priv_1_EQ_0b11_33_OR_rg_cur_priv_1_E_ETC___d752 =
	     ((rg_cur_priv == 2'b11 ||
	       rg_cur_priv == 2'b01 && !csr_regfile$read_mstatus[22]) &&
	      _theResult____h4973[31:20] == 12'b000100000010) ?
	       4'd8 :
	       (rg_cur_priv_1_EQ_0b11_33_OR_rg_cur_priv_1_EQ_0_ETC___d750 ?
		  4'd10 :
		  4'd11) ;
  assign IF_stage2_rg_full_5_THEN_IF_stage2_rg_stage2_6_ETC___d126 =
	     stage2_rg_full ?
	       CASE_stage2_rg_stage2_BITS_338_TO_336_0_2_1_IF_ETC__q1 :
	       2'd0 ;
  assign IF_stage2_rg_full_5_THEN_IF_stage2_rg_stage2_6_ETC___d188 =
	     stage2_rg_full ?
	       CASE_stage2_rg_stage2_BITS_338_TO_336_0_2_1_IF_ETC__q2 :
	       2'd0 ;
  assign IF_stage2_rg_full_5_THEN_IF_stage2_rg_stage2_6_ETC___d493 =
	     x_out_bypass_rd__h7450 == _theResult____h4973[19:15] ;
  assign IF_stage2_rg_full_5_THEN_IF_stage2_rg_stage2_6_ETC___d495 =
	     x_out_bypass_rd__h7450 == _theResult____h4973[24:20] ;
  assign IF_stage2_rg_stage2_6_BITS_335_TO_331_56_EQ_0__ETC___d183 =
	     (stage2_rg_stage2[335:331] == 5'd0) ?
	       2'd0 :
	       ((near_mem$dmem_valid && !near_mem$dmem_exc) ? 2'd2 : 2'd1) ;
  assign IF_stage2_rg_stage2_6_BITS_338_TO_336_7_EQ_3_0_ETC___d123 =
	     stage2_mbox$valid ? 2'd2 : 2'd1 ;
  assign NOT_IF_NOT_stage1_rg_full_03_04_OR_NOT_near_me_ETC___d1354 =
	     x_out_next_pc__h13057[1:0] != 2'b0 && near_mem$imem_valid &&
	     addr_of_b32__h20583 == near_mem$imem_pc &&
	     near_mem$imem_instr[17:16] == 2'b11 ;
  assign NOT_IF_csr_regfile_read_csr_minstret__7_ULT_cf_ETC___d43 =
	     cur_verbosity__h3490 > 4'd1 ;
  assign NOT_IF_imem_rg_pc_BITS_1_TO_0_EQ_0b0_OR_NOT_im_ETC___d593 =
	     (_theResult____h4973[14:12] != 3'b0 ||
	      _theResult____h4973[6:0] == 7'b0110011 &&
	      _theResult____h4973[30]) &&
	     (_theResult____h4973[14:12] != 3'b0 ||
	      _theResult____h4973[6:0] != 7'b0110011 ||
	      !_theResult____h4973[30]) &&
	     _theResult____h4973[14:12] != 3'b010 &&
	     _theResult____h4973[14:12] != 3'b011 &&
	     _theResult____h4973[14:12] != 3'b100 &&
	     _theResult____h4973[14:12] != 3'b110 &&
	     _theResult____h4973[14:12] != 3'b111 ;
  assign NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d1224 =
	     !csr_regfile$interrupt_pending[4] && !csr_regfile$nmi_pending ||
	     near_mem$imem_exc ||
	     IF_IF_imem_rg_pc_BITS_1_TO_0_EQ_0b0_OR_NOT_ime_ETC___d651 &&
	     IF_IF_imem_rg_pc_BITS_1_TO_0_EQ_0b0_OR_NOT_ime_ETC___d662 ;
  assign NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d1318 =
	     !csr_regfile$interrupt_pending[4] && !csr_regfile$nmi_pending ||
	     (!stage1_rg_full ||
	      NOT_near_mem_imem_valid_05_OR_imem_rg_pc_BITS__ETC___d1181) &&
	     (!stage1_rg_full ||
	      NOT_near_mem_imem_valid_05_OR_imem_rg_pc_BITS__ETC___d1168) ;
  assign NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d1338 =
	     !csr_regfile$interrupt_pending[4] && !csr_regfile$nmi_pending ||
	     (!stage1_rg_full ||
	      imem_rg_pc_BITS_1_TO_0_EQ_0b0_OR_NOT_imem_rg_p_ETC___d1331) &&
	     (!stage1_rg_full ||
	      imem_rg_pc_BITS_1_TO_0_EQ_0b0_OR_NOT_imem_rg_p_ETC___d1333) ;
  assign NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d1389 =
	     !csr_regfile$interrupt_pending[4] && !csr_regfile$nmi_pending ||
	     !near_mem$imem_exc &&
	     (IF_IF_imem_rg_pc_BITS_1_TO_0_EQ_0b0_OR_NOT_ime_ETC___d709 ||
	      IF_IF_imem_rg_pc_BITS_1_TO_0_EQ_0b0_OR_NOT_ime_ETC___d711) ;
  assign NOT_csr_regfile_read_dpc__602_BITS_1_TO_0_603__ETC___d1611 =
	     csr_regfile$read_dpc[1:0] != 2'b0 && near_mem$imem_valid &&
	     addr_of_b32__h30400 == near_mem$imem_pc &&
	     near_mem$imem_instr[17:16] == 2'b11 ;
  assign NOT_imem_rg_pc_BITS_1_TO_0_EQ_0b0_AND_imem_rg__ETC___d1340 =
	     NOT_imem_rg_pc_BITS_1_TO_0_EQ_0b0_AND_imem_rg__ETC___d507 &&
	     (IF_stage2_rg_full_5_THEN_IF_stage2_rg_stage2_6_ETC___d188 !=
	      2'd1 ||
	      !IF_stage2_rg_full_5_THEN_IF_stage2_rg_stage2_6_ETC___d493 &&
	      !IF_stage2_rg_full_5_THEN_IF_stage2_rg_stage2_6_ETC___d495) ;
  assign NOT_imem_rg_pc_BITS_1_TO_0_EQ_0b0_AND_imem_rg__ETC___d238 =
	     imem_rg_pc[1:0] != 2'b0 &&
	     imem_rg_pc_BITS_31_TO_2_0_EQ_imem_rg_cache_add_ETC___d208 &&
	     near_mem_imem_pc__1_EQ_imem_rg_pc_PLUS_2_11___d212 &&
	     imem_rg_cache_b16[1:0] == 2'b11 ;
  assign NOT_imem_rg_pc_BITS_1_TO_0_EQ_0b0_AND_imem_rg__ETC___d248 =
	     imem_rg_pc[1:0] != 2'b0 &&
	     (imem_rg_pc_BITS_31_TO_2_0_EQ_near_mem_imem_pc__ETC___d13 &&
	      near_mem$imem_instr[17:16] != 2'b11 ||
	      imem_rg_pc_BITS_31_TO_2_0_EQ_imem_rg_cache_add_ETC___d208 &&
	      imem_rg_cache_b16[1:0] != 2'b11) ;
  assign NOT_imem_rg_pc_BITS_1_TO_0_EQ_0b0_AND_imem_rg__ETC___d505 =
	     NOT_imem_rg_pc_BITS_1_TO_0_EQ_0b0_AND_imem_rg__ETC___d238 ||
	     imem_rg_pc[1:0] == 2'b0 &&
	     imem_rg_pc_BITS_31_TO_2_0_EQ_near_mem_imem_pc__ETC___d13 &&
	     near_mem$imem_instr[1:0] == 2'b11 ;
  assign NOT_imem_rg_pc_BITS_1_TO_0_EQ_0b0_AND_imem_rg__ETC___d507 =
	     NOT_imem_rg_pc_BITS_1_TO_0_EQ_0b0_AND_imem_rg__ETC___d505 ||
	     NOT_imem_rg_pc_BITS_1_TO_0_EQ_0b0_AND_imem_rg__ETC___d248 ||
	     imem_rg_pc[1:0] == 2'b0 &&
	     imem_rg_pc_BITS_31_TO_2_0_EQ_near_mem_imem_pc__ETC___d13 &&
	     near_mem$imem_instr[1:0] != 2'b11 ;
  assign NOT_imem_rg_pc_BITS_31_TO_2_0_EQ_imem_rg_cache_ETC___d1157 =
	     (!imem_rg_pc_BITS_31_TO_2_0_EQ_imem_rg_cache_add_ETC___d208 ||
	      !near_mem_imem_pc__1_EQ_imem_rg_pc_PLUS_2_11___d212 ||
	      imem_rg_cache_b16[1:0] != 2'b11) &&
	     (!imem_rg_pc_BITS_31_TO_2_0_EQ_imem_rg_cache_add_ETC___d208 ||
	      imem_rg_cache_b16[1:0] == 2'b11) ||
	     IF_stage2_rg_full_5_THEN_IF_stage2_rg_stage2_6_ETC___d188 ==
	     2'd1 &&
	     (IF_stage2_rg_full_5_THEN_IF_stage2_rg_stage2_6_ETC___d493 ||
	      IF_stage2_rg_full_5_THEN_IF_stage2_rg_stage2_6_ETC___d495) ;
  assign NOT_near_mem_imem_exc__14_67_AND_IF_IF_imem_rg_ETC___d1387 =
	     !near_mem$imem_exc &&
	     (IF_IF_imem_rg_pc_BITS_1_TO_0_EQ_0b0_OR_NOT_ime_ETC___d709 ||
	      IF_IF_imem_rg_pc_BITS_1_TO_0_EQ_0b0_OR_NOT_ime_ETC___d711) ||
	     !rg_stop_req && !rg_step_count ;
  assign NOT_near_mem_imem_exc__14_67_AND_IF_IF_imem_rg_ETC___d841 =
	     !near_mem$imem_exc &&
	     (IF_IF_imem_rg_pc_BITS_1_TO_0_EQ_0b0_OR_NOT_ime_ETC___d709 ||
	      IF_IF_imem_rg_pc_BITS_1_TO_0_EQ_0b0_OR_NOT_ime_ETC___d711) &&
	     IF_NOT_stage1_rg_full_03_04_OR_NOT_near_mem_im_ETC___d775 !=
	     4'd0 &&
	     IF_NOT_stage1_rg_full_03_04_OR_NOT_near_mem_im_ETC___d775 !=
	     4'd1 &&
	     IF_NOT_stage1_rg_full_03_04_OR_NOT_near_mem_im_ETC___d775 !=
	     4'd2 &&
	     IF_NOT_stage1_rg_full_03_04_OR_NOT_near_mem_im_ETC___d775 !=
	     4'd3 &&
	     IF_NOT_stage1_rg_full_03_04_OR_NOT_near_mem_im_ETC___d775 !=
	     4'd4 &&
	     IF_NOT_stage1_rg_full_03_04_OR_NOT_near_mem_im_ETC___d775 !=
	     4'd5 &&
	     IF_NOT_stage1_rg_full_03_04_OR_NOT_near_mem_im_ETC___d775 !=
	     4'd6 &&
	     IF_NOT_stage1_rg_full_03_04_OR_NOT_near_mem_im_ETC___d775 !=
	     4'd7 &&
	     IF_NOT_stage1_rg_full_03_04_OR_NOT_near_mem_im_ETC___d775 !=
	     4'd8 &&
	     IF_NOT_stage1_rg_full_03_04_OR_NOT_near_mem_im_ETC___d775 !=
	     4'd9 &&
	     IF_NOT_stage1_rg_full_03_04_OR_NOT_near_mem_im_ETC___d775 !=
	     4'd10 ;
  assign NOT_near_mem_imem_exc__14_67_AND_IF_IF_imem_rg_ETC___d878 =
	     !near_mem$imem_exc &&
	     (IF_IF_imem_rg_pc_BITS_1_TO_0_EQ_0b0_OR_NOT_ime_ETC___d709 ||
	      IF_IF_imem_rg_pc_BITS_1_TO_0_EQ_0b0_OR_NOT_ime_ETC___d711) &&
	     IF_NOT_stage1_rg_full_03_04_OR_NOT_near_mem_im_ETC___d854 !=
	     3'd0 &&
	     IF_NOT_stage1_rg_full_03_04_OR_NOT_near_mem_im_ETC___d854 !=
	     3'd1 &&
	     IF_NOT_stage1_rg_full_03_04_OR_NOT_near_mem_im_ETC___d854 !=
	     3'd2 &&
	     IF_NOT_stage1_rg_full_03_04_OR_NOT_near_mem_im_ETC___d854 !=
	     3'd3 ;
  assign NOT_near_mem_imem_valid_05_OR_imem_rg_pc_BITS__ETC___d1168 =
	     NOT_near_mem_imem_valid_05_OR_imem_rg_pc_BITS__ETC___d498 ||
	     !near_mem$imem_exc &&
	     (IF_IF_imem_rg_pc_BITS_1_TO_0_EQ_0b0_OR_NOT_ime_ETC___d709 ||
	      IF_IF_imem_rg_pc_BITS_1_TO_0_EQ_0b0_OR_NOT_ime_ETC___d711) ;
  assign NOT_near_mem_imem_valid_05_OR_imem_rg_pc_BITS__ETC___d1181 =
	     NOT_near_mem_imem_valid_05_OR_imem_rg_pc_BITS__ETC___d498 ||
	     near_mem$imem_exc ||
	     IF_IF_imem_rg_pc_BITS_1_TO_0_EQ_0b0_OR_NOT_ime_ETC___d651 &&
	     IF_IF_imem_rg_pc_BITS_1_TO_0_EQ_0b0_OR_NOT_ime_ETC___d662 ;
  assign NOT_near_mem_imem_valid_05_OR_imem_rg_pc_BITS__ETC___d498 =
	     !near_mem$imem_valid ||
	     imem_rg_pc_BITS_1_TO_0_EQ_0b0_OR_NOT_imem_rg_p_ETC___d233 ||
	     IF_stage2_rg_full_5_THEN_IF_stage2_rg_stage2_6_ETC___d188 ==
	     2'd1 &&
	     (IF_stage2_rg_full_5_THEN_IF_stage2_rg_stage2_6_ETC___d493 ||
	      IF_stage2_rg_full_5_THEN_IF_stage2_rg_stage2_6_ETC___d495) ;
  assign NOT_rg_next_pc_524_BITS_1_TO_0_525_EQ_0b0_526__ETC___d1533 =
	     rg_next_pc[1:0] != 2'b0 && near_mem$imem_valid &&
	     addr_of_b32__h28770 == near_mem$imem_pc &&
	     near_mem$imem_instr[17:16] == 2'b11 ;
  assign NOT_rg_stop_req_138_173_AND_NOT_rg_step_count__ETC___d1180 =
	     !rg_stop_req && !rg_step_count &&
	     csr_regfile_csr_mip_read__118_EQ_rg_prev_mip_119___d1120 &&
	     !csr_regfile$interrupt_pending[4] &&
	     !csr_regfile$nmi_pending ;
  assign NOT_rg_stop_req_138_173_AND_NOT_rg_step_count__ETC___d1184 =
	     NOT_rg_stop_req_138_173_AND_NOT_rg_step_count__ETC___d1180 ||
	     (!stage1_rg_full ||
	      NOT_near_mem_imem_valid_05_OR_imem_rg_pc_BITS__ETC___d1181) &&
	     (!stage1_rg_full ||
	      NOT_near_mem_imem_valid_05_OR_imem_rg_pc_BITS__ETC___d1168) ;
  assign NOT_soc_map_m_pc_reset_value__096_BITS_1_TO_0__ETC___d1108 =
	     soc_map$m_pc_reset_value[1:0] != 2'b0 && near_mem$imem_valid &&
	     addr_of_b32__h17037 == near_mem$imem_pc &&
	     near_mem$imem_instr[17:16] == 2'b11 ;
  assign NOT_stage1_rg_full_03_04_OR_NOT_near_mem_imem__ETC___d1316 =
	     (!stage1_rg_full ||
	      NOT_near_mem_imem_valid_05_OR_imem_rg_pc_BITS__ETC___d1181) &&
	     (!stage1_rg_full ||
	      NOT_near_mem_imem_valid_05_OR_imem_rg_pc_BITS__ETC___d1168) ||
	     !rg_stop_req && !rg_step_count ;
  assign NOT_stage1_rg_full_03_04_OR_NOT_near_mem_imem__ETC___d1324 =
	     NOT_stage1_rg_full_03_04_OR_NOT_near_mem_imem__ETC___d1316 &&
	     csr_regfile_csr_mip_read__118_EQ_rg_prev_mip_119___d1120 &&
	     NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d1318 &&
	     (near_mem_imem_exc__14_OR_IF_IF_imem_rg_pc_BITS_ETC___d1222 &&
	      NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d1224 &&
	      (IF_stage2_rg_full_5_THEN_IF_stage2_rg_stage2_6_ETC___d126 ==
	       2'd2 ||
	       IF_stage2_rg_full_5_THEN_IF_stage2_rg_stage2_6_ETC___d126 ==
	       2'd0) &&
	      near_mem_imem_valid_AND_NOT_imem_rg_pc_BITS_1__ETC___d714 ||
	      !stage1_rg_full) ;
  assign NOT_stage1_rg_full_03_04_OR_imem_rg_pc_BITS_1__ETC___d1336 =
	     (!stage1_rg_full ||
	      imem_rg_pc_BITS_1_TO_0_EQ_0b0_OR_NOT_imem_rg_p_ETC___d1331) &&
	     (!stage1_rg_full ||
	      imem_rg_pc_BITS_1_TO_0_EQ_0b0_OR_NOT_imem_rg_p_ETC___d1333) ||
	     !rg_stop_req && !rg_step_count ;
  assign NOT_stage1_rg_full_03_04_OR_imem_rg_pc_BITS_1__ETC___d1344 =
	     NOT_stage1_rg_full_03_04_OR_imem_rg_pc_BITS_1__ETC___d1336 &&
	     csr_regfile_csr_mip_read__118_EQ_rg_prev_mip_119___d1120 &&
	     NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d1338 &&
	     (near_mem_imem_exc__14_OR_IF_IF_imem_rg_pc_BITS_ETC___d1342 ||
	      !stage1_rg_full) ;
  assign SEXT_IF_NOT_imem_rg_pc_BITS_1_TO_0_EQ_0b0_AND__ETC___d317 =
	     { {9{offset__h8600[11]}}, offset__h8600 } ;
  assign SEXT_IF_NOT_imem_rg_pc_BITS_1_TO_0_EQ_0b0_AND__ETC___d346 =
	     { {4{offset__h9511[8]}}, offset__h9511 } ;
  assign SEXT_IF_imem_rg_pc_BITS_1_TO_0_EQ_0b0_OR_NOT_i_ETC___d907 =
	     { {20{theResult__973_BITS_31_TO_20__q17[11]}},
	       theResult__973_BITS_31_TO_20__q17 } ;
  assign _0_OR_0_OR_near_mem_imem_exc__14_OR_IF_IF_imem__ETC___d1360 =
	     near_mem$imem_exc ||
	     IF_IF_imem_rg_pc_BITS_1_TO_0_EQ_0b0_OR_NOT_ime_ETC___d651 &&
	     IF_IF_imem_rg_pc_BITS_1_TO_0_EQ_0b0_OR_NOT_ime_ETC___d662 ;
  assign _0_OR_0_OR_near_mem_imem_exc__14_OR_IF_IF_imem__ETC___d1362 =
	     (_0_OR_0_OR_near_mem_imem_exc__14_OR_IF_IF_imem__ETC___d1360 ||
	      !rg_stop_req && !rg_step_count) &&
	     csr_regfile_csr_mip_read__118_EQ_rg_prev_mip_119___d1120 ;
  assign _0_OR_0_OR_near_mem_imem_exc__14_OR_IF_IF_imem__ETC___d1364 =
	     _0_OR_0_OR_near_mem_imem_exc__14_OR_IF_IF_imem__ETC___d1362 &&
	     (!csr_regfile$interrupt_pending[4] && !csr_regfile$nmi_pending ||
	      _0_OR_0_OR_near_mem_imem_exc__14_OR_IF_IF_imem__ETC___d1360) ;
  assign _0_OR_0_OR_near_mem_imem_exc__14_OR_IF_IF_imem__ETC___d1367 =
	     (_0_OR_0_OR_near_mem_imem_exc__14_OR_IF_IF_imem__ETC___d1360 ||
	      !rg_stop_req && !rg_step_count) &&
	     (!csr_regfile$interrupt_pending[4] && !csr_regfile$nmi_pending ||
	      _0_OR_0_OR_near_mem_imem_exc__14_OR_IF_IF_imem__ETC___d1360) ;
  assign _0_OR_0_OR_near_mem_imem_exc__14_OR_IF_IF_imem__ETC___d1370 =
	     _0_OR_0_OR_near_mem_imem_exc__14_OR_IF_IF_imem__ETC___d1367 &&
	     (IF_stage2_rg_full_5_THEN_IF_stage2_rg_stage2_6_ETC___d126 ==
	      2'd2 ||
	      IF_stage2_rg_full_5_THEN_IF_stage2_rg_stage2_6_ETC___d126 ==
	      2'd0) &&
	     near_mem_imem_valid_AND_NOT_imem_rg_pc_BITS_1__ETC___d714 ||
	     !stage1_rg_full ;
  assign _theResult_____1_fst__h14288 =
	     (_theResult____h4973[14:12] == 3'b0 &&
	      _theResult____h4973[6:0] == 7'b0110011 &&
	      _theResult____h4973[30]) ?
	       rd_val___1__h14284 :
	       _theResult_____1_fst__h14295 ;
  assign _theResult_____1_fst__h14323 =
	     rs1_val_bypassed__h4981 & _theResult___snd__h15566 ;
  assign _theResult____h13381 =
	     (_theResult____h4973[14:12] == 3'b001) ?
	       rd_val__h15462 :
	       (_theResult____h4973[30] ? rd_val__h15536 : rd_val__h15514) ;
  assign _theResult____h29734 =
	     (delta_CPI_instrs__h29733 == 64'd0) ?
	       delta_CPI_instrs___1__h29769 :
	       delta_CPI_instrs__h29733 ;
  assign _theResult____h4973 = x_out_data_to_stage2_instr__h13090 ;
  assign _theResult___snd__h15566 =
	     (_theResult____h4973[6:0] == 7'b0010011) ?
	       SEXT_IF_imem_rg_pc_BITS_1_TO_0_EQ_0b0_OR_NOT_i_ETC___d907 :
	       rs2_val__h13206 ;
  assign addr_of_b32___1__h17149 = addr_of_b32__h17037 + 32'd4 ;
  assign addr_of_b32___1__h20695 = addr_of_b32__h20583 + 32'd4 ;
  assign addr_of_b32___1__h28882 = addr_of_b32__h28770 + 32'd4 ;
  assign addr_of_b32___1__h30512 = addr_of_b32__h30400 + 32'd4 ;
  assign addr_of_b32__h17037 = { soc_map$m_pc_reset_value[31:2], 2'd0 } ;
  assign addr_of_b32__h20583 = { x_out_next_pc__h13057[31:2], 2'd0 } ;
  assign addr_of_b32__h28770 = { rg_next_pc[31:2], 2'd0 } ;
  assign addr_of_b32__h30400 = { csr_regfile$read_dpc[31:2], 2'd0 } ;
  assign alu_outputs___1_addr__h13234 =
	     IF_IF_imem_rg_pc_BITS_1_TO_0_EQ_0b0_OR_NOT_ime_ETC___d563 ?
	       branch_target__h13210 :
	       IF_imem_rg_pc_BITS_1_TO_0_EQ_0b0_OR_NOT_imem_r_ETC___d898 ;
  assign alu_outputs___1_addr__h13258 =
	     imem_rg_pc +
	     { {11{theResult__973_BIT_31_CONCAT_theResult__973_BI_ETC__q4[20]}},
	       theResult__973_BIT_31_CONCAT_theResult__973_BI_ETC__q4 } ;
  assign alu_outputs___1_addr__h13287 = { eaddr__h13475[31:1], 1'd0 } ;
  assign alu_outputs___1_exc_code__h13747 =
	     (_theResult____h4973[14:12] == 3'b0) ?
	       ((_theResult____h4973[11:7] == 5'd0 &&
		 _theResult____h4973[19:15] == 5'd0) ?
		  CASE_theResult__973_BITS_31_TO_20_0b0_CASE_rg__ETC__q6 :
		  4'd2) :
	       4'd2 ;
  assign alu_outputs___1_trace_data_word1__h18615 = x__h19810 ;
  assign alu_outputs___1_trace_data_word3__h18597 = { 32'd0, eaddr__h13475 } ;
  assign alu_outputs___1_trace_data_word3__h18617 = { 32'd0, eaddr__h13496 } ;
  assign alu_outputs___1_val1__h13751 =
	     _theResult____h4973[14] ?
	       { 27'd0, _theResult____h4973[19:15] } :
	       rs1_val_bypassed__h4981 ;
  assign alu_outputs___1_val1__h13773 =
	     { 25'd0, _theResult____h4973[31:25] } ;
  assign branch_target__h13210 =
	     imem_rg_pc +
	     { {19{theResult__973_BIT_31_CONCAT_theResult__973_BI_ETC__q3[12]}},
	       theResult__973_BIT_31_CONCAT_theResult__973_BI_ETC__q3 } ;
  assign cpi__h29736 = x__h29735 / 64'd10 ;
  assign cpifrac__h29737 = x__h29735 % 64'd10 ;
  assign csr_regfile_RDY_server_reset_response_get__076_ETC___d1091 =
	     csr_regfile$RDY_server_reset_response_get &&
	     stage1_f_reset_rsps$EMPTY_N &&
	     stage2_f_reset_rsps$EMPTY_N &&
	     stage3_f_reset_rsps$EMPTY_N &&
	     f_reset_rsps$FULL_N &&
	     (!rg_run_on_reset ||
	      imem_rg_pc_BITS_1_TO_0_EQ_0b0_OR_NOT_near_mem__ETC___d1085) ;
  assign csr_regfile_csr_mip_read__118_EQ_rg_prev_mip_119___d1120 =
	     csr_regfile$csr_mip_read == rg_prev_mip ;
  assign csr_regfile_interrupt_pending_rg_cur_priv_1_14_ETC___d1147 =
	     (csr_regfile$interrupt_pending[4] || csr_regfile$nmi_pending) &&
	     stage1_rg_full &&
	     imem_rg_pc_BITS_31_TO_2_0_EQ_imem_rg_cache_add_ETC___d1135 &&
	     IF_IF_imem_rg_pc_BITS_1_TO_0_EQ_0b0_OR_NOT_ime_ETC___d1113 ;
  assign csr_regfile_read_csr_mcycle__0_MINUS_rg_start__ETC___d1585 =
	     delta_CPI_cycles__h29732 * 64'd10 ;
  assign csr_regfile_read_misa__8_BIT_2_35_AND_IF_NOT_i_ETC___d331 =
	     csr_regfile$read_misa[2] && instr__h4971[1:0] == 2'b10 &&
	     instr__h4971[15:12] == 4'b1000 &&
	     instr__h4971[11:7] != 5'd0 ;
  assign csr_regfile_read_misa__8_BIT_2_35_AND_IF_NOT_i_ETC___d337 =
	     csr_regfile$read_misa[2] && instr__h4971[1:0] == 2'b10 &&
	     instr__h4971[15:12] == 4'b1001 &&
	     instr__h4971[11:7] != 5'd0 ;
  assign cur_verbosity__h3490 =
	     (csr_regfile$read_csr_minstret < cfg_logdelay) ?
	       4'd0 :
	       cfg_verbosity ;
  assign data_to_stage2_addr__h13084 = x_out_data_to_stage2_addr__h13093 ;
  assign delta_CPI_cycles__h29732 =
	     csr_regfile$read_csr_mcycle - rg_start_CPI_cycles ;
  assign delta_CPI_instrs___1__h29769 = delta_CPI_instrs__h29733 + 64'd1 ;
  assign delta_CPI_instrs__h29733 =
	     csr_regfile$read_csr_minstret - rg_start_CPI_instrs ;
  assign eaddr__h13475 =
	     rs1_val_bypassed__h4981 +
	     SEXT_IF_imem_rg_pc_BITS_1_TO_0_EQ_0b0_OR_NOT_i_ETC___d907 ;
  assign eaddr__h13496 =
	     rs1_val_bypassed__h4981 +
	     { {20{theResult__973_BITS_31_TO_25_CONCAT_theResult__ETC__q7[11]}},
	       theResult__973_BITS_31_TO_25_CONCAT_theResult__ETC__q7 } ;
  assign fall_through_pc__h13043 =
	     imem_rg_pc +
	     (NOT_imem_rg_pc_BITS_1_TO_0_EQ_0b0_AND_imem_rg__ETC___d505 ?
		32'd4 :
		32'd2) ;
  assign imem_rg_pc_BITS_1_TO_0_EQ_0b0_OR_NOT_imem_rg_p_ETC___d1330 =
	     imem_rg_pc_BITS_1_TO_0_EQ_0b0_OR_NOT_imem_rg_p_ETC___d233 ||
	     IF_stage2_rg_full_5_THEN_IF_stage2_rg_stage2_6_ETC___d188 ==
	     2'd1 &&
	     (IF_stage2_rg_full_5_THEN_IF_stage2_rg_stage2_6_ETC___d493 ||
	      IF_stage2_rg_full_5_THEN_IF_stage2_rg_stage2_6_ETC___d495) ;
  assign imem_rg_pc_BITS_1_TO_0_EQ_0b0_OR_NOT_imem_rg_p_ETC___d1331 =
	     imem_rg_pc_BITS_1_TO_0_EQ_0b0_OR_NOT_imem_rg_p_ETC___d1330 ||
	     near_mem$imem_exc ||
	     IF_IF_imem_rg_pc_BITS_1_TO_0_EQ_0b0_OR_NOT_ime_ETC___d651 &&
	     IF_IF_imem_rg_pc_BITS_1_TO_0_EQ_0b0_OR_NOT_ime_ETC___d662 ;
  assign imem_rg_pc_BITS_1_TO_0_EQ_0b0_OR_NOT_imem_rg_p_ETC___d1333 =
	     imem_rg_pc_BITS_1_TO_0_EQ_0b0_OR_NOT_imem_rg_p_ETC___d1330 ||
	     !near_mem$imem_exc &&
	     (IF_IF_imem_rg_pc_BITS_1_TO_0_EQ_0b0_OR_NOT_ime_ETC___d709 ||
	      IF_IF_imem_rg_pc_BITS_1_TO_0_EQ_0b0_OR_NOT_ime_ETC___d711) ;
  assign imem_rg_pc_BITS_1_TO_0_EQ_0b0_OR_NOT_imem_rg_p_ETC___d226 =
	     (imem_rg_pc[1:0] == 2'b0 ||
	      !imem_rg_pc_BITS_31_TO_2_0_EQ_imem_rg_cache_add_ETC___d208 ||
	      !near_mem_imem_pc__1_EQ_imem_rg_pc_PLUS_2_11___d212 ||
	      imem_rg_cache_b16[1:0] != 2'b11) &&
	     (imem_rg_pc[1:0] != 2'b0 ||
	      !imem_rg_pc_BITS_31_TO_2_0_EQ_near_mem_imem_pc__ETC___d13 ||
	      near_mem$imem_instr[1:0] != 2'b11) ;
  assign imem_rg_pc_BITS_1_TO_0_EQ_0b0_OR_NOT_imem_rg_p_ETC___d230 =
	     imem_rg_pc[1:0] == 2'b0 ||
	     (!imem_rg_pc_BITS_31_TO_2_0_EQ_near_mem_imem_pc__ETC___d13 ||
	      near_mem$imem_instr[17:16] == 2'b11) &&
	     (!imem_rg_pc_BITS_31_TO_2_0_EQ_imem_rg_cache_add_ETC___d208 ||
	      imem_rg_cache_b16[1:0] == 2'b11) ;
  assign imem_rg_pc_BITS_1_TO_0_EQ_0b0_OR_NOT_imem_rg_p_ETC___d233 =
	     imem_rg_pc_BITS_1_TO_0_EQ_0b0_OR_NOT_imem_rg_p_ETC___d226 &&
	     imem_rg_pc_BITS_1_TO_0_EQ_0b0_OR_NOT_imem_rg_p_ETC___d230 &&
	     (imem_rg_pc[1:0] != 2'b0 ||
	      !imem_rg_pc_BITS_31_TO_2_0_EQ_near_mem_imem_pc__ETC___d13 ||
	      near_mem$imem_instr[1:0] == 2'b11) ;
  assign imem_rg_pc_BITS_1_TO_0_EQ_0b0_OR_NOT_near_mem__ETC___d1085 =
	     imem_rg_pc[1:0] == 2'b0 || !near_mem$imem_valid ||
	     !imem_rg_pc_BITS_31_TO_2_0_EQ_near_mem_imem_pc__ETC___d13 ||
	     near_mem$imem_instr[17:16] != 2'b11 ;
  assign imem_rg_pc_BITS_31_TO_2_0_EQ_imem_rg_cache_add_ETC___d1135 =
	     imem_rg_pc_BITS_31_TO_2_0_EQ_imem_rg_cache_add_ETC___d208 &&
	     (near_mem_imem_pc__1_EQ_imem_rg_pc_PLUS_2_11___d212 ||
	      imem_rg_cache_b16[1:0] != 2'b11) &&
	     (IF_stage2_rg_full_5_THEN_IF_stage2_rg_stage2_6_ETC___d188 !=
	      2'd1 ||
	      !IF_stage2_rg_full_5_THEN_IF_stage2_rg_stage2_6_ETC___d493 &&
	      !IF_stage2_rg_full_5_THEN_IF_stage2_rg_stage2_6_ETC___d495) ;
  assign imem_rg_pc_BITS_31_TO_2_0_EQ_imem_rg_cache_add_ETC___d208 =
	     imem_rg_pc[31:2] == imem_rg_cache_addr[31:2] ;
  assign imem_rg_pc_BITS_31_TO_2_0_EQ_near_mem_imem_pc__ETC___d13 =
	     imem_rg_pc[31:2] == near_mem$imem_pc[31:2] ;
  assign imm12__h10146 = { {6{imm6__h10144[5]}}, imm6__h10144 } ;
  assign imm12__h10770 = { {2{nzimm10__h10768[9]}}, nzimm10__h10768 } ;
  assign imm12__h10985 = { 2'd0, nzimm10__h10983 } ;
  assign imm12__h11181 = { 7'b0, instr__h4971[6:2] } ;
  assign imm12__h11526 = { 7'b0100000, instr__h4971[6:2] } ;
  assign imm12__h7893 = { 4'd0, offset__h7649 } ;
  assign imm12__h8230 = { 5'd0, offset__h8172 } ;
  assign imm20__h10274 = { {14{imm6__h10144[5]}}, imm6__h10144 } ;
  assign imm6__h10144 = { instr__h4971[12], instr__h4971[6:2] } ;
  assign instr___1__h7611 =
	     (csr_regfile$read_misa[2] && instr__h4971[1:0] == 2'b10 &&
	      instr__h4971[11:7] != 5'd0 &&
	      instr__h4971[15:13] == 3'b010) ?
	       instr__h7892 :
	       IF_csr_regfile_read_misa__8_BIT_2_35_AND_IF_NO_ETC___d489 ;
  assign instr__h10222 =
	     { imm12__h10146, 8'd0, instr__h4971[11:7], 7'b0010011 } ;
  assign instr__h10406 = { imm20__h10274, instr__h4971[11:7], 7'b0110111 } ;
  assign instr__h10535 =
	     { imm12__h10146,
	       instr__h4971[11:7],
	       3'b0,
	       instr__h4971[11:7],
	       7'b0010011 } ;
  assign instr__h10972 =
	     { imm12__h10770,
	       instr__h4971[11:7],
	       3'b0,
	       instr__h4971[11:7],
	       7'b0010011 } ;
  assign instr__h11144 = { imm12__h10985, 8'd16, rd__h8232, 7'b0010011 } ;
  assign instr__h11317 =
	     { imm12__h11181,
	       instr__h4971[11:7],
	       3'b001,
	       instr__h4971[11:7],
	       7'b0010011 } ;
  assign instr__h11510 =
	     { imm12__h11181, rs1__h8231, 3'b101, rs1__h8231, 7'b0010011 } ;
  assign instr__h11703 =
	     { imm12__h11526, rs1__h8231, 3'b101, rs1__h8231, 7'b0010011 } ;
  assign instr__h11820 =
	     { imm12__h10146, rs1__h8231, 3'b111, rs1__h8231, 7'b0010011 } ;
  assign instr__h11998 =
	     { 7'b0,
	       instr__h4971[6:2],
	       8'd0,
	       instr__h4971[11:7],
	       7'b0110011 } ;
  assign instr__h12117 =
	     { 7'b0,
	       instr__h4971[6:2],
	       instr__h4971[11:7],
	       3'b0,
	       instr__h4971[11:7],
	       7'b0110011 } ;
  assign instr__h12212 =
	     { 7'b0, rd__h8232, rs1__h8231, 3'b111, rs1__h8231, 7'b0110011 } ;
  assign instr__h12348 =
	     { 7'b0, rd__h8232, rs1__h8231, 3'b110, rs1__h8231, 7'b0110011 } ;
  assign instr__h12484 =
	     { 7'b0, rd__h8232, rs1__h8231, 3'b100, rs1__h8231, 7'b0110011 } ;
  assign instr__h12620 =
	     { 7'b0100000,
	       rd__h8232,
	       rs1__h8231,
	       3'b0,
	       rs1__h8231,
	       7'b0110011 } ;
  assign instr__h12958 =
	     { 12'b000000000001,
	       instr__h4971[11:7],
	       3'b0,
	       instr__h4971[11:7],
	       7'b1110011 } ;
  assign instr__h4971 =
	     NOT_imem_rg_pc_BITS_1_TO_0_EQ_0b0_AND_imem_rg__ETC___d238 ?
	       instr_out___1__h7749 :
	       IF_imem_rg_pc_BITS_1_TO_0_EQ_0b0_AND_imem_rg_p_ETC___d252 ;
  assign instr__h7892 =
	     { imm12__h7893, 8'd18, instr__h4971[11:7], 7'b0000011 } ;
  assign instr__h8037 =
	     { 4'd0,
	       instr__h4971[8:7],
	       instr__h4971[12],
	       instr__h4971[6:2],
	       8'd18,
	       offset_BITS_4_TO_0___h8161,
	       7'b0100011 } ;
  assign instr__h8229 =
	     { imm12__h8230, rs1__h8231, 3'b010, rd__h8232, 7'b0000011 } ;
  assign instr__h8424 =
	     { 5'd0,
	       instr__h4971[5],
	       instr__h4971[12],
	       rd__h8232,
	       rs1__h8231,
	       3'b010,
	       offset_BITS_4_TO_0___h8592,
	       7'b0100011 } ;
  assign instr__h8653 =
	     { SEXT_IF_NOT_imem_rg_pc_BITS_1_TO_0_EQ_0b0_AND__ETC___d317[20],
	       SEXT_IF_NOT_imem_rg_pc_BITS_1_TO_0_EQ_0b0_AND__ETC___d317[10:1],
	       SEXT_IF_NOT_imem_rg_pc_BITS_1_TO_0_EQ_0b0_AND__ETC___d317[11],
	       SEXT_IF_NOT_imem_rg_pc_BITS_1_TO_0_EQ_0b0_AND__ETC___d317[19:12],
	       12'd111 } ;
  assign instr__h8996 =
	     { SEXT_IF_NOT_imem_rg_pc_BITS_1_TO_0_EQ_0b0_AND__ETC___d317[20],
	       SEXT_IF_NOT_imem_rg_pc_BITS_1_TO_0_EQ_0b0_AND__ETC___d317[10:1],
	       SEXT_IF_NOT_imem_rg_pc_BITS_1_TO_0_EQ_0b0_AND__ETC___d317[11],
	       SEXT_IF_NOT_imem_rg_pc_BITS_1_TO_0_EQ_0b0_AND__ETC___d317[19:12],
	       12'd239 } ;
  assign instr__h9386 = { 12'd0, instr__h4971[11:7], 15'd103 } ;
  assign instr__h9502 = { 12'd0, instr__h4971[11:7], 15'd231 } ;
  assign instr__h9567 =
	     { SEXT_IF_NOT_imem_rg_pc_BITS_1_TO_0_EQ_0b0_AND__ETC___d346[12],
	       SEXT_IF_NOT_imem_rg_pc_BITS_1_TO_0_EQ_0b0_AND__ETC___d346[10:5],
	       5'd0,
	       rs1__h8231,
	       3'b0,
	       SEXT_IF_NOT_imem_rg_pc_BITS_1_TO_0_EQ_0b0_AND__ETC___d346[4:1],
	       SEXT_IF_NOT_imem_rg_pc_BITS_1_TO_0_EQ_0b0_AND__ETC___d346[11],
	       7'b1100011 } ;
  assign instr__h9884 =
	     { SEXT_IF_NOT_imem_rg_pc_BITS_1_TO_0_EQ_0b0_AND__ETC___d346[12],
	       SEXT_IF_NOT_imem_rg_pc_BITS_1_TO_0_EQ_0b0_AND__ETC___d346[10:5],
	       5'd0,
	       rs1__h8231,
	       3'b001,
	       SEXT_IF_NOT_imem_rg_pc_BITS_1_TO_0_EQ_0b0_AND__ETC___d346[4:1],
	       SEXT_IF_NOT_imem_rg_pc_BITS_1_TO_0_EQ_0b0_AND__ETC___d346[11],
	       7'b1100011 } ;
  assign instr_out___1__h7749 =
	     { near_mem$imem_instr[15:0], imem_rg_cache_b16 } ;
  assign instr_out___1__h7771 = { 16'b0, near_mem$imem_instr[15:0] } ;
  assign near_mem_RDY_server_reset_request_put__055_AND_ETC___d1067 =
	     near_mem$RDY_server_reset_request_put &&
	     csr_regfile$RDY_server_reset_request_put &&
	     f_reset_reqs$EMPTY_N &&
	     stage1_f_reset_reqs$FULL_N &&
	     stage2_f_reset_reqs$FULL_N &&
	     stage3_f_reset_reqs$FULL_N &&
	     f_trace_data$FULL_N ;
  assign near_mem_imem_exc__14_OR_IF_IF_imem_rg_pc_BITS_ETC___d1002 =
	     (near_mem$imem_exc ||
	      IF_IF_imem_rg_pc_BITS_1_TO_0_EQ_0b0_OR_NOT_ime_ETC___d651 &&
	      IF_IF_imem_rg_pc_BITS_1_TO_0_EQ_0b0_OR_NOT_ime_ETC___d662) &&
	     IF_NOT_stage1_rg_full_03_04_OR_NOT_near_mem_im_ETC___d775 ==
	     4'd8 ;
  assign near_mem_imem_exc__14_OR_IF_IF_imem_rg_pc_BITS_ETC___d1005 =
	     (near_mem$imem_exc ||
	      IF_IF_imem_rg_pc_BITS_1_TO_0_EQ_0b0_OR_NOT_ime_ETC___d651 &&
	      IF_IF_imem_rg_pc_BITS_1_TO_0_EQ_0b0_OR_NOT_ime_ETC___d662) &&
	     IF_NOT_stage1_rg_full_03_04_OR_NOT_near_mem_im_ETC___d775 ==
	     4'd9 ;
  assign near_mem_imem_exc__14_OR_IF_IF_imem_rg_pc_BITS_ETC___d1008 =
	     (near_mem$imem_exc ||
	      IF_IF_imem_rg_pc_BITS_1_TO_0_EQ_0b0_OR_NOT_ime_ETC___d651 &&
	      IF_IF_imem_rg_pc_BITS_1_TO_0_EQ_0b0_OR_NOT_ime_ETC___d662) &&
	     IF_NOT_stage1_rg_full_03_04_OR_NOT_near_mem_im_ETC___d775 ==
	     4'd10 ;
  assign near_mem_imem_exc__14_OR_IF_IF_imem_rg_pc_BITS_ETC___d1011 =
	     (near_mem$imem_exc ||
	      IF_IF_imem_rg_pc_BITS_1_TO_0_EQ_0b0_OR_NOT_ime_ETC___d651 &&
	      IF_IF_imem_rg_pc_BITS_1_TO_0_EQ_0b0_OR_NOT_ime_ETC___d662) &&
	     IF_NOT_stage1_rg_full_03_04_OR_NOT_near_mem_im_ETC___d775 !=
	     4'd0 &&
	     IF_NOT_stage1_rg_full_03_04_OR_NOT_near_mem_im_ETC___d775 !=
	     4'd1 &&
	     IF_NOT_stage1_rg_full_03_04_OR_NOT_near_mem_im_ETC___d775 !=
	     4'd2 &&
	     IF_NOT_stage1_rg_full_03_04_OR_NOT_near_mem_im_ETC___d775 !=
	     4'd3 &&
	     IF_NOT_stage1_rg_full_03_04_OR_NOT_near_mem_im_ETC___d775 !=
	     4'd4 &&
	     IF_NOT_stage1_rg_full_03_04_OR_NOT_near_mem_im_ETC___d775 !=
	     4'd5 &&
	     IF_NOT_stage1_rg_full_03_04_OR_NOT_near_mem_im_ETC___d775 !=
	     4'd6 &&
	     IF_NOT_stage1_rg_full_03_04_OR_NOT_near_mem_im_ETC___d775 !=
	     4'd7 &&
	     IF_NOT_stage1_rg_full_03_04_OR_NOT_near_mem_im_ETC___d775 !=
	     4'd8 &&
	     IF_NOT_stage1_rg_full_03_04_OR_NOT_near_mem_im_ETC___d775 !=
	     4'd9 &&
	     IF_NOT_stage1_rg_full_03_04_OR_NOT_near_mem_im_ETC___d775 !=
	     4'd10 ;
  assign near_mem_imem_exc__14_OR_IF_IF_imem_rg_pc_BITS_ETC___d1222 =
	     near_mem$imem_exc ||
	     IF_IF_imem_rg_pc_BITS_1_TO_0_EQ_0b0_OR_NOT_ime_ETC___d651 &&
	     IF_IF_imem_rg_pc_BITS_1_TO_0_EQ_0b0_OR_NOT_ime_ETC___d662 ||
	     !rg_stop_req && !rg_step_count ;
  assign near_mem_imem_exc__14_OR_IF_IF_imem_rg_pc_BITS_ETC___d1227 =
	     near_mem_imem_exc__14_OR_IF_IF_imem_rg_pc_BITS_ETC___d1222 &&
	     csr_regfile_csr_mip_read__118_EQ_rg_prev_mip_119___d1120 &&
	     NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d1224 &&
	     (IF_stage2_rg_full_5_THEN_IF_stage2_rg_stage2_6_ETC___d126 ==
	      2'd2 ||
	      IF_stage2_rg_full_5_THEN_IF_stage2_rg_stage2_6_ETC___d126 ==
	      2'd0) ;
  assign near_mem_imem_exc__14_OR_IF_IF_imem_rg_pc_BITS_ETC___d1305 =
	     near_mem_imem_exc__14_OR_IF_IF_imem_rg_pc_BITS_ETC___d1227 &&
	     stage1_rg_full &&
	     near_mem_imem_valid_AND_NOT_imem_rg_pc_BITS_1__ETC___d714 &&
	     NOT_IF_csr_regfile_read_csr_minstret__7_ULT_cf_ETC___d43 ;
  assign near_mem_imem_exc__14_OR_IF_IF_imem_rg_pc_BITS_ETC___d1307 =
	     near_mem_imem_exc__14_OR_IF_IF_imem_rg_pc_BITS_ETC___d1227 &&
	     stage1_rg_full &&
	     near_mem_imem_valid_AND_NOT_imem_rg_pc_BITS_1__ETC___d714 &&
	     NOT_IF_csr_regfile_read_csr_minstret__7_ULT_cf_ETC___d43 &&
	     IF_NOT_stage1_rg_full_03_04_OR_NOT_near_mem_im_ETC___d854 ==
	     3'd0 ;
  assign near_mem_imem_exc__14_OR_IF_IF_imem_rg_pc_BITS_ETC___d1309 =
	     near_mem_imem_exc__14_OR_IF_IF_imem_rg_pc_BITS_ETC___d1227 &&
	     stage1_rg_full &&
	     near_mem_imem_valid_AND_NOT_imem_rg_pc_BITS_1__ETC___d714 &&
	     NOT_IF_csr_regfile_read_csr_minstret__7_ULT_cf_ETC___d43 &&
	     IF_NOT_stage1_rg_full_03_04_OR_NOT_near_mem_im_ETC___d854 ==
	     3'd1 ;
  assign near_mem_imem_exc__14_OR_IF_IF_imem_rg_pc_BITS_ETC___d1311 =
	     near_mem_imem_exc__14_OR_IF_IF_imem_rg_pc_BITS_ETC___d1227 &&
	     stage1_rg_full &&
	     near_mem_imem_valid_AND_NOT_imem_rg_pc_BITS_1__ETC___d714 &&
	     NOT_IF_csr_regfile_read_csr_minstret__7_ULT_cf_ETC___d43 &&
	     IF_NOT_stage1_rg_full_03_04_OR_NOT_near_mem_im_ETC___d854 ==
	     3'd2 ;
  assign near_mem_imem_exc__14_OR_IF_IF_imem_rg_pc_BITS_ETC___d1313 =
	     near_mem_imem_exc__14_OR_IF_IF_imem_rg_pc_BITS_ETC___d1227 &&
	     stage1_rg_full &&
	     near_mem_imem_valid_AND_NOT_imem_rg_pc_BITS_1__ETC___d714 &&
	     NOT_IF_csr_regfile_read_csr_minstret__7_ULT_cf_ETC___d43 &&
	     IF_NOT_stage1_rg_full_03_04_OR_NOT_near_mem_im_ETC___d854 ==
	     3'd3 ;
  assign near_mem_imem_exc__14_OR_IF_IF_imem_rg_pc_BITS_ETC___d1315 =
	     near_mem_imem_exc__14_OR_IF_IF_imem_rg_pc_BITS_ETC___d1227 &&
	     stage1_rg_full &&
	     near_mem_imem_valid_AND_NOT_imem_rg_pc_BITS_1__ETC___d714 &&
	     NOT_IF_csr_regfile_read_csr_minstret__7_ULT_cf_ETC___d43 &&
	     IF_NOT_stage1_rg_full_03_04_OR_NOT_near_mem_im_ETC___d854 !=
	     3'd0 &&
	     IF_NOT_stage1_rg_full_03_04_OR_NOT_near_mem_im_ETC___d854 !=
	     3'd1 &&
	     IF_NOT_stage1_rg_full_03_04_OR_NOT_near_mem_im_ETC___d854 !=
	     3'd2 &&
	     IF_NOT_stage1_rg_full_03_04_OR_NOT_near_mem_im_ETC___d854 !=
	     3'd3 ;
  assign near_mem_imem_exc__14_OR_IF_IF_imem_rg_pc_BITS_ETC___d1342 =
	     near_mem_imem_exc__14_OR_IF_IF_imem_rg_pc_BITS_ETC___d1222 &&
	     NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d1224 &&
	     (IF_stage2_rg_full_5_THEN_IF_stage2_rg_stage2_6_ETC___d126 ==
	      2'd2 ||
	      IF_stage2_rg_full_5_THEN_IF_stage2_rg_stage2_6_ETC___d126 ==
	      2'd0) &&
	     NOT_imem_rg_pc_BITS_1_TO_0_EQ_0b0_AND_imem_rg__ETC___d1340 &&
	     !near_mem$imem_exc &&
	     (IF_IF_imem_rg_pc_BITS_1_TO_0_EQ_0b0_OR_NOT_ime_ETC___d709 ||
	      IF_IF_imem_rg_pc_BITS_1_TO_0_EQ_0b0_OR_NOT_ime_ETC___d711) ;
  assign near_mem_imem_exc__14_OR_IF_IF_imem_rg_pc_BITS_ETC___d978 =
	     (near_mem$imem_exc ||
	      IF_IF_imem_rg_pc_BITS_1_TO_0_EQ_0b0_OR_NOT_ime_ETC___d651 &&
	      IF_IF_imem_rg_pc_BITS_1_TO_0_EQ_0b0_OR_NOT_ime_ETC___d662) &&
	     IF_NOT_stage1_rg_full_03_04_OR_NOT_near_mem_im_ETC___d775 ==
	     4'd0 ;
  assign near_mem_imem_exc__14_OR_IF_IF_imem_rg_pc_BITS_ETC___d981 =
	     (near_mem$imem_exc ||
	      IF_IF_imem_rg_pc_BITS_1_TO_0_EQ_0b0_OR_NOT_ime_ETC___d651 &&
	      IF_IF_imem_rg_pc_BITS_1_TO_0_EQ_0b0_OR_NOT_ime_ETC___d662) &&
	     IF_NOT_stage1_rg_full_03_04_OR_NOT_near_mem_im_ETC___d775 ==
	     4'd1 ;
  assign near_mem_imem_exc__14_OR_IF_IF_imem_rg_pc_BITS_ETC___d984 =
	     (near_mem$imem_exc ||
	      IF_IF_imem_rg_pc_BITS_1_TO_0_EQ_0b0_OR_NOT_ime_ETC___d651 &&
	      IF_IF_imem_rg_pc_BITS_1_TO_0_EQ_0b0_OR_NOT_ime_ETC___d662) &&
	     IF_NOT_stage1_rg_full_03_04_OR_NOT_near_mem_im_ETC___d775 ==
	     4'd2 ;
  assign near_mem_imem_exc__14_OR_IF_IF_imem_rg_pc_BITS_ETC___d987 =
	     (near_mem$imem_exc ||
	      IF_IF_imem_rg_pc_BITS_1_TO_0_EQ_0b0_OR_NOT_ime_ETC___d651 &&
	      IF_IF_imem_rg_pc_BITS_1_TO_0_EQ_0b0_OR_NOT_ime_ETC___d662) &&
	     IF_NOT_stage1_rg_full_03_04_OR_NOT_near_mem_im_ETC___d775 ==
	     4'd3 ;
  assign near_mem_imem_exc__14_OR_IF_IF_imem_rg_pc_BITS_ETC___d990 =
	     (near_mem$imem_exc ||
	      IF_IF_imem_rg_pc_BITS_1_TO_0_EQ_0b0_OR_NOT_ime_ETC___d651 &&
	      IF_IF_imem_rg_pc_BITS_1_TO_0_EQ_0b0_OR_NOT_ime_ETC___d662) &&
	     IF_NOT_stage1_rg_full_03_04_OR_NOT_near_mem_im_ETC___d775 ==
	     4'd4 ;
  assign near_mem_imem_exc__14_OR_IF_IF_imem_rg_pc_BITS_ETC___d993 =
	     (near_mem$imem_exc ||
	      IF_IF_imem_rg_pc_BITS_1_TO_0_EQ_0b0_OR_NOT_ime_ETC___d651 &&
	      IF_IF_imem_rg_pc_BITS_1_TO_0_EQ_0b0_OR_NOT_ime_ETC___d662) &&
	     IF_NOT_stage1_rg_full_03_04_OR_NOT_near_mem_im_ETC___d775 ==
	     4'd5 ;
  assign near_mem_imem_exc__14_OR_IF_IF_imem_rg_pc_BITS_ETC___d996 =
	     (near_mem$imem_exc ||
	      IF_IF_imem_rg_pc_BITS_1_TO_0_EQ_0b0_OR_NOT_ime_ETC___d651 &&
	      IF_IF_imem_rg_pc_BITS_1_TO_0_EQ_0b0_OR_NOT_ime_ETC___d662) &&
	     IF_NOT_stage1_rg_full_03_04_OR_NOT_near_mem_im_ETC___d775 ==
	     4'd6 ;
  assign near_mem_imem_exc__14_OR_IF_IF_imem_rg_pc_BITS_ETC___d999 =
	     (near_mem$imem_exc ||
	      IF_IF_imem_rg_pc_BITS_1_TO_0_EQ_0b0_OR_NOT_ime_ETC___d651 &&
	      IF_IF_imem_rg_pc_BITS_1_TO_0_EQ_0b0_OR_NOT_ime_ETC___d662) &&
	     IF_NOT_stage1_rg_full_03_04_OR_NOT_near_mem_im_ETC___d775 ==
	     4'd7 ;
  assign near_mem_imem_pc__1_EQ_imem_rg_pc_PLUS_2_11___d212 =
	     near_mem$imem_pc == next_pc___1__h14997 ;
  assign near_mem_imem_valid_AND_NOT_imem_rg_pc_BITS_1__ETC___d513 =
	     near_mem$imem_valid &&
	     NOT_imem_rg_pc_BITS_1_TO_0_EQ_0b0_AND_imem_rg__ETC___d507 &&
	     (IF_stage2_rg_full_5_THEN_IF_stage2_rg_stage2_6_ETC___d188 !=
	      2'd1 ||
	      !IF_stage2_rg_full_5_THEN_IF_stage2_rg_stage2_6_ETC___d493 &&
	      !IF_stage2_rg_full_5_THEN_IF_stage2_rg_stage2_6_ETC___d495) ;
  assign near_mem_imem_valid_AND_NOT_imem_rg_pc_BITS_1__ETC___d665 =
	     near_mem_imem_valid_AND_NOT_imem_rg_pc_BITS_1__ETC___d513 &&
	     (near_mem$imem_exc ||
	      IF_IF_imem_rg_pc_BITS_1_TO_0_EQ_0b0_OR_NOT_ime_ETC___d651 &&
	      IF_IF_imem_rg_pc_BITS_1_TO_0_EQ_0b0_OR_NOT_ime_ETC___d662) ;
  assign near_mem_imem_valid_AND_NOT_imem_rg_pc_BITS_1__ETC___d714 =
	     near_mem_imem_valid_AND_NOT_imem_rg_pc_BITS_1__ETC___d513 &&
	     !near_mem$imem_exc &&
	     (IF_IF_imem_rg_pc_BITS_1_TO_0_EQ_0b0_OR_NOT_ime_ETC___d709 ||
	      IF_IF_imem_rg_pc_BITS_1_TO_0_EQ_0b0_OR_NOT_ime_ETC___d711) ;
  assign next_pc___1__h14997 = imem_rg_pc + 32'd2 ;
  assign next_pc__h14995 = imem_rg_pc + 32'd4 ;
  assign nzimm10__h10768 =
	     { instr__h4971[12],
	       instr__h4971[4:3],
	       instr__h4971[5],
	       instr__h4971[2],
	       instr__h4971[6],
	       4'b0 } ;
  assign nzimm10__h10983 =
	     { instr__h4971[10:7],
	       instr__h4971[12:11],
	       instr__h4971[5],
	       instr__h4971[6],
	       2'b0 } ;
  assign offset_BITS_4_TO_0___h8161 = { instr__h4971[11:9], 2'b0 } ;
  assign offset_BITS_4_TO_0___h8592 =
	     { instr__h4971[11:10], instr__h4971[6], 2'b0 } ;
  assign offset__h7649 =
	     { instr__h4971[3:2],
	       instr__h4971[12],
	       instr__h4971[6:4],
	       2'b0 } ;
  assign offset__h8172 =
	     { instr__h4971[5], instr__h4971[12:10], instr__h4971[6], 2'b0 } ;
  assign offset__h8600 =
	     { instr__h4971[12],
	       instr__h4971[8],
	       instr__h4971[10:9],
	       instr__h4971[6],
	       instr__h4971[7],
	       instr__h4971[2],
	       instr__h4971[11],
	       instr__h4971[5:3],
	       1'b0 } ;
  assign offset__h9511 =
	     { instr__h4971[12],
	       instr__h4971[6:5],
	       instr__h4971[2],
	       instr__h4971[11:10],
	       instr__h4971[4:3],
	       1'b0 } ;
  assign output_stage2___1_bypass_rd_val__h7439 =
	     (!near_mem$dmem_valid || !near_mem$dmem_exc) ?
	       ((stage2_rg_stage2[335:331] == 5'd0) ?
		  stage2_rg_stage2[298:267] :
		  near_mem$dmem_word64[31:0]) :
	       stage2_rg_stage2[298:267] ;
  assign rd__h8232 = { 2'b01, instr__h4971[4:2] } ;
  assign rd_val___1__h14276 =
	     rs1_val_bypassed__h4981 + _theResult___snd__h15566 ;
  assign rd_val___1__h14284 =
	     rs1_val_bypassed__h4981 - _theResult___snd__h15566 ;
  assign rd_val___1__h14291 =
	     ((rs1_val_bypassed__h4981 ^ 32'h80000000) <
	      (_theResult___snd__h15566 ^ 32'h80000000)) ?
	       32'd1 :
	       32'd0 ;
  assign rd_val___1__h14298 =
	     (rs1_val_bypassed__h4981 < _theResult___snd__h15566) ?
	       32'd1 :
	       32'd0 ;
  assign rd_val___1__h14305 =
	     rs1_val_bypassed__h4981 ^ _theResult___snd__h15566 ;
  assign rd_val___1__h14312 =
	     rs1_val_bypassed__h4981 | _theResult___snd__h15566 ;
  assign rd_val__h13000 =
	     (stage3_rg_full && stage3_rg_stage3[37] &&
	      stage3_rg_stage3[36:32] == _theResult____h4973[24:20]) ?
	       stage3_rg_stage3[31:0] :
	       gpr_regfile$read_rs2 ;
  assign rd_val__h13421 =
	     (_theResult____h4973[14:12] == 3'b0 &&
	      (_theResult____h4973[6:0] != 7'b0110011 ||
	       !_theResult____h4973[30])) ?
	       rd_val___1__h14276 :
	       _theResult_____1_fst__h14288 ;
  assign rd_val__h13439 = { _theResult____h4973[31:12], 12'h0 } ;
  assign rd_val__h13456 = imem_rg_pc + rd_val__h13439 ;
  assign rd_val__h15462 = rs1_val_bypassed__h4981 << shamt__h13377 ;
  assign rd_val__h15514 = rs1_val_bypassed__h4981 >> shamt__h13377 ;
  assign rd_val__h15536 =
	     rs1_val_bypassed__h4981 >> shamt__h13377 |
	     ~(32'hFFFFFFFF >> shamt__h13377) &
	     {32{rs1_val_bypassed__h4981[31]}} ;
  assign rd_val__h7563 =
	     (stage3_rg_full && stage3_rg_stage3[37] &&
	      stage3_rg_stage3[36:32] == _theResult____h4973[19:15]) ?
	       stage3_rg_stage3[31:0] :
	       gpr_regfile$read_rs1 ;
  assign rg_cur_priv_1_EQ_0b11_33_OR_rg_cur_priv_1_EQ_0_ETC___d750 =
	     (rg_cur_priv == 2'b11 ||
	      rg_cur_priv == 2'b01 && !csr_regfile$read_mstatus[21] ||
	      rg_cur_priv == 2'b0 && csr_regfile$read_misa[13]) &&
	     _theResult____h4973[31:20] == 12'b000100000101 ;
  assign rg_state_4_EQ_4_112_AND_NOT_near_mem_imem_exc__ETC___d1394 =
	     rg_state == 4'd4 &&
	     NOT_near_mem_imem_exc__14_67_AND_IF_IF_imem_rg_ETC___d1387 &&
	     csr_regfile_csr_mip_read__118_EQ_rg_prev_mip_119___d1120 &&
	     NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d1389 &&
	     !stage3_rg_full &&
	     IF_stage2_rg_full_5_THEN_IF_stage2_rg_stage2_6_ETC___d126 ==
	     2'd0 &&
	     stage1_rg_full &&
	     near_mem_imem_valid_AND_NOT_imem_rg_pc_BITS_1__ETC___d665 ;
  assign rg_state_4_EQ_4_112_AND_rg_stop_req_138_OR_rg__ETC___d1581 =
	     rg_state == 4'd4 &&
	     rg_stop_req_138_OR_rg_step_count_139_140_AND_s_ETC___d1576 &&
	     IF_stage2_rg_full_5_THEN_IF_stage2_rg_stage2_6_ETC___d126 ==
	     2'd0 &&
	     !stage3_rg_full &&
	     csr_regfile_csr_mip_read__118_EQ_rg_prev_mip_119___d1120 &&
	     !csr_regfile$interrupt_pending[4] &&
	     !csr_regfile$nmi_pending ;
  assign rg_state_4_EQ_4_112_AND_stage3_rg_full_6_OR_NO_ETC___d1187 =
	     rg_state == 4'd4 &&
	     (stage3_rg_full ||
	      IF_stage2_rg_full_5_THEN_IF_stage2_rg_stage2_6_ETC___d126 !=
	      2'd0 ||
	      stage1_rg_full) &&
	     (stage3_rg_full ||
	      IF_stage2_rg_full_5_THEN_IF_stage2_rg_stage2_6_ETC___d126 !=
	      2'd3) &&
	     (stage3_rg_full ||
	      IF_stage2_rg_full_5_THEN_IF_stage2_rg_stage2_6_ETC___d126 !=
	      2'd0 ||
	      !stage1_rg_full ||
	      NOT_near_mem_imem_valid_05_OR_imem_rg_pc_BITS__ETC___d1168) &&
	     (NOT_rg_stop_req_138_173_AND_NOT_rg_step_count__ETC___d1184 ||
	      IF_stage2_rg_full_5_THEN_IF_stage2_rg_stage2_6_ETC___d126 !=
	      2'd0 ||
	      stage3_rg_full) ;
  assign rg_stop_req_138_OR_rg_step_count_139_140_AND_s_ETC___d1576 =
	     (rg_stop_req || rg_step_count) && stage1_rg_full &&
	     near_mem_imem_valid_AND_NOT_imem_rg_pc_BITS_1__ETC___d513 &&
	     IF_IF_imem_rg_pc_BITS_1_TO_0_EQ_0b0_OR_NOT_ime_ETC___d1113 ;
  assign rs1__h8231 = { 2'b01, instr__h4971[9:7] } ;
  assign rs1_val__h22206 =
	     (rg_trap_instr[14:12] == 3'b001) ?
	       rg_csr_val1 :
	       { 27'd0, rg_trap_instr[19:15] } ;
  assign rs1_val_bypassed__h4981 =
	     (_theResult____h4973[19:15] == 5'd0) ? 32'd0 : val__h7565 ;
  assign rs2_val__h13206 =
	     (_theResult____h4973[24:20] == 5'd0) ? 32'd0 : val__h13002 ;
  assign shamt__h13377 =
	     (_theResult____h4973[6:0] == 7'b0010011) ?
	       _theResult____h4973[24:20] :
	       rs2_val__h13206[4:0] ;
  assign stage1_rg_full_03_AND_imem_rg_pc_BITS_31_TO_2__ETC___d1141 =
	     stage1_rg_full &&
	     imem_rg_pc_BITS_31_TO_2_0_EQ_imem_rg_cache_add_ETC___d1135 &&
	     IF_IF_imem_rg_pc_BITS_1_TO_0_EQ_0b0_OR_NOT_ime_ETC___d1113 &&
	     (rg_stop_req || rg_step_count) ;
  assign stage1_rg_full_03_AND_near_mem_imem_valid_AND__ETC___d1116 =
	     stage1_rg_full &&
	     near_mem_imem_valid_AND_NOT_imem_rg_pc_BITS_1__ETC___d513 &&
	     IF_IF_imem_rg_pc_BITS_1_TO_0_EQ_0b0_OR_NOT_ime_ETC___d1113 &&
	     IF_stage2_rg_full_5_THEN_IF_stage2_rg_stage2_6_ETC___d126 ==
	     2'd0 ;
  assign stage1_rg_full_03_AND_near_mem_imem_valid_AND__ETC___d1380 =
	     stage1_rg_full &&
	     near_mem_imem_valid_AND_NOT_imem_rg_pc_BITS_1__ETC___d513 &&
	     IF_IF_imem_rg_pc_BITS_1_TO_0_EQ_0b0_OR_NOT_ime_ETC___d1113 &&
	     csr_regfile$read_dcsr_step ;
  assign td1_rd__h24478 = { 3'd0, csr_regfile$csr_ret_actions[33:32] } ;
  assign theResult__973_BITS_31_TO_20__q17 = _theResult____h4973[31:20] ;
  assign theResult__973_BITS_31_TO_25_CONCAT_theResult__ETC__q7 =
	     { _theResult____h4973[31:25], _theResult____h4973[11:7] } ;
  assign theResult__973_BIT_31_CONCAT_theResult__973_BI_ETC__q3 =
	     { _theResult____h4973[31],
	       _theResult____h4973[7],
	       _theResult____h4973[30:25],
	       _theResult____h4973[11:8],
	       1'b0 } ;
  assign theResult__973_BIT_31_CONCAT_theResult__973_BI_ETC__q4 =
	     { _theResult____h4973[31],
	       _theResult____h4973[19:12],
	       _theResult____h4973[20],
	       _theResult____h4973[30:21],
	       1'b0 } ;
  assign trap_info_tval__h14833 =
	     (_theResult____h4973[6:0] != 7'b1101111 &&
	      _theResult____h4973[6:0] != 7'b1100111 &&
	      (_theResult____h4973[6:0] != 7'b1110011 ||
	       _theResult____h4973[14:12] != 3'b0 ||
	       _theResult____h4973[11:7] != 5'd0 ||
	       _theResult____h4973[19:15] != 5'd0 ||
	       _theResult____h4973[31:20] != 12'b0 &&
	       _theResult____h4973[31:20] != 12'b000000000001)) ?
	       (NOT_imem_rg_pc_BITS_1_TO_0_EQ_0b0_AND_imem_rg__ETC___d505 ?
		  _theResult____h4973 :
		  { 16'd0, instr__h4971[15:0] }) :
	       IF_IF_imem_rg_pc_BITS_1_TO_0_EQ_0b0_OR_NOT_ime_ETC___d1050 ;
  assign val__h13002 =
	     (IF_stage2_rg_full_5_THEN_IF_stage2_rg_stage2_6_ETC___d188 ==
	      2'd2 &&
	      IF_stage2_rg_full_5_THEN_IF_stage2_rg_stage2_6_ETC___d495) ?
	       x_out_bypass_rd_val__h7451 :
	       rd_val__h13000 ;
  assign val__h7565 =
	     (IF_stage2_rg_full_5_THEN_IF_stage2_rg_stage2_6_ETC___d188 ==
	      2'd2 &&
	      IF_stage2_rg_full_5_THEN_IF_stage2_rg_stage2_6_ETC___d493) ?
	       x_out_bypass_rd_val__h7451 :
	       rd_val__h7563 ;
  assign value__h14885 =
	     near_mem$imem_exc ? imem_rg_tval : trap_info_tval__h14833 ;
  assign x__h19433 =
	     imem_rg_pc_BITS_1_TO_0_EQ_0b0_OR_NOT_imem_rg_p_ETC___d226 ?
	       { 16'd0, instr__h4971[15:0] } :
	       _theResult____h4973 ;
  assign x__h19810 = { 29'd0, _theResult____h4973[14:12] } ;
  assign x__h21782 = rg_trap_interrupt ? 32'd0 : rg_trap_info[31:0] ;
  assign x__h23453 = (rg_trap_instr[19:15] == 5'd0) ? 32'd0 : 32'd1 ;
  assign x__h23461 =
	     (rg_trap_instr[19:15] == 5'd0) ?
	       32'hAAAAAAAA :
	       csr_regfile$mav_csr_write ;
  assign x__h29735 =
	     csr_regfile_read_csr_mcycle__0_MINUS_rg_start__ETC___d1585[63:0] /
	     _theResult____h29734 ;
  assign x_exc_code__h29483 =
	     (csr_regfile$interrupt_pending[4] && !csr_regfile$nmi_pending) ?
	       csr_regfile$interrupt_pending[3:0] :
	       4'd0 ;
  assign x_out_data_to_stage2_instr__h13090 =
	     imem_rg_pc_BITS_1_TO_0_EQ_0b0_OR_NOT_imem_rg_p_ETC___d226 ?
	       instr___1__h7611 :
	       instr__h4971 ;
  assign x_out_data_to_stage2_rd__h13092 =
	     (_theResult____h4973[6:0] == 7'b1100011) ?
	       5'd0 :
	       _theResult____h4973[11:7] ;
  assign x_out_data_to_stage2_val2__h13095 =
	     (_theResult____h4973[6:0] == 7'b1100011) ?
	       branch_target__h13210 :
	       rs2_val__h13206 ;
  assign x_out_next_pc__h13057 =
	     IF_IF_imem_rg_pc_BITS_1_TO_0_EQ_0b0_OR_NOT_ime_ETC___d711 ?
	       data_to_stage2_addr__h13084 :
	       fall_through_pc__h13043 ;
  assign x_out_trap_info_exc_code__h14836 =
	     near_mem$imem_exc ?
	       near_mem$imem_exc_code :
	       alu_outputs_exc_code__h13792 ;
  assign x_rd__h21614 = { 3'd0, csr_regfile$csr_trap_actions[1:0] } ;
  assign x_word3__h21617 = { 32'd0, rg_trap_info[67:36] } ;
  assign x_word3__h23406 = { 52'd0, rg_trap_instr[31:20] } ;
  assign y__h23296 = ~rs1_val__h23025 ;
  always@(stage2_rg_stage2)
  begin
    case (stage2_rg_stage2[338:336])
      3'd0, 3'd1, 3'd4:
	  x_out_data_to_stage3_rd__h7110 = stage2_rg_stage2[335:331];
      3'd2: x_out_data_to_stage3_rd__h7110 = 5'd0;
      default: x_out_data_to_stage3_rd__h7110 = stage2_rg_stage2[335:331];
    endcase
  end
  always@(stage2_rg_stage2 or stage2_mbox$word or near_mem$dmem_word64)
  begin
    case (stage2_rg_stage2[338:336])
      3'd0, 3'd2:
	  x_out_data_to_stage3_rd_val__h7111 = stage2_rg_stage2[298:267];
      3'd1, 3'd4:
	  x_out_data_to_stage3_rd_val__h7111 = near_mem$dmem_word64[31:0];
      default: x_out_data_to_stage3_rd_val__h7111 = stage2_mbox$word;
    endcase
  end
  always@(stage2_rg_stage2)
  begin
    case (stage2_rg_stage2[338:336])
      3'd0, 3'd1, 3'd4: x_out_bypass_rd__h7450 = stage2_rg_stage2[335:331];
      default: x_out_bypass_rd__h7450 = stage2_rg_stage2[335:331];
    endcase
  end
  always@(rg_trap_instr or rg_csr_val1)
  begin
    case (rg_trap_instr[14:12])
      3'b010, 3'b011: rs1_val__h23025 = rg_csr_val1;
      default: rs1_val__h23025 = { 27'd0, rg_trap_instr[19:15] };
    endcase
  end
  always@(stage2_rg_stage2 or
	  stage2_mbox$word or output_stage2___1_bypass_rd_val__h7439)
  begin
    case (stage2_rg_stage2[338:336])
      3'd0: x_out_bypass_rd_val__h7451 = stage2_rg_stage2[298:267];
      3'd1, 3'd4:
	  x_out_bypass_rd_val__h7451 = output_stage2___1_bypass_rd_val__h7439;
      default: x_out_bypass_rd_val__h7451 = stage2_mbox$word;
    endcase
  end
  always@(stage2_rg_stage2 or
	  IF_stage2_rg_stage2_6_BITS_338_TO_336_7_EQ_3_0_ETC___d123 or
	  IF_near_mem_dmem_valid__17_THEN_IF_near_mem_dm_ETC___d120)
  begin
    case (stage2_rg_stage2[338:336])
      3'd0: CASE_stage2_rg_stage2_BITS_338_TO_336_0_2_1_IF_ETC__q1 = 2'd2;
      3'd1, 3'd2, 3'd4:
	  CASE_stage2_rg_stage2_BITS_338_TO_336_0_2_1_IF_ETC__q1 =
	      IF_near_mem_dmem_valid__17_THEN_IF_near_mem_dm_ETC___d120;
      default: CASE_stage2_rg_stage2_BITS_338_TO_336_0_2_1_IF_ETC__q1 =
		   IF_stage2_rg_stage2_6_BITS_338_TO_336_7_EQ_3_0_ETC___d123;
    endcase
  end
  always@(stage2_rg_stage2 or
	  stage2_mbox$valid or near_mem$dmem_valid or near_mem$dmem_exc)
  begin
    case (stage2_rg_stage2[338:336])
      3'd1, 3'd2, 3'd4:
	  IF_stage2_rg_stage2_6_BITS_338_TO_336_7_EQ_1_9_ETC___d140 =
	      !near_mem$dmem_valid || near_mem$dmem_exc;
      default: IF_stage2_rg_stage2_6_BITS_338_TO_336_7_EQ_1_9_ETC___d140 =
		   !stage2_mbox$valid;
    endcase
  end
  always@(stage2_rg_stage2 or
	  stage2_mbox$valid or near_mem$dmem_valid or near_mem$dmem_exc)
  begin
    case (stage2_rg_stage2[338:336])
      3'd1, 3'd2, 3'd4:
	  IF_stage2_rg_stage2_6_BITS_338_TO_336_7_EQ_1_9_ETC___d149 =
	      near_mem$dmem_valid && !near_mem$dmem_exc;
      default: IF_stage2_rg_stage2_6_BITS_338_TO_336_7_EQ_1_9_ETC___d149 =
		   stage2_mbox$valid;
    endcase
  end
  always@(stage2_rg_stage2 or
	  IF_stage2_rg_stage2_6_BITS_338_TO_336_7_EQ_3_0_ETC___d123 or
	  IF_NOT_near_mem_dmem_valid__17_36_OR_NOT_near__ETC___d184)
  begin
    case (stage2_rg_stage2[338:336])
      3'd0: CASE_stage2_rg_stage2_BITS_338_TO_336_0_2_1_IF_ETC__q2 = 2'd2;
      3'd1, 3'd4:
	  CASE_stage2_rg_stage2_BITS_338_TO_336_0_2_1_IF_ETC__q2 =
	      IF_NOT_near_mem_dmem_valid__17_36_OR_NOT_near__ETC___d184;
      3'd2: CASE_stage2_rg_stage2_BITS_338_TO_336_0_2_1_IF_ETC__q2 = 2'd0;
      default: CASE_stage2_rg_stage2_BITS_338_TO_336_0_2_1_IF_ETC__q2 =
		   IF_stage2_rg_stage2_6_BITS_338_TO_336_7_EQ_3_0_ETC___d123;
    endcase
  end
  always@(_theResult____h4973)
  begin
    case (_theResult____h4973[6:0])
      7'b0000011,
      7'b0010011,
      7'b0010111,
      7'b0101111,
      7'b0110011,
      7'b0110111,
      7'b1100111,
      7'b1101111:
	  x_out_data_to_stage2_trace_data_rd__h18721 =
	      _theResult____h4973[11:7];
      default: x_out_data_to_stage2_trace_data_rd__h18721 = 5'd2;
    endcase
  end
  always@(rg_cur_priv)
  begin
    case (rg_cur_priv)
      2'b0: CASE_rg_cur_priv_0b0_8_0b1_9_11__q5 = 4'd8;
      2'b01: CASE_rg_cur_priv_0b0_8_0b1_9_11__q5 = 4'd9;
      default: CASE_rg_cur_priv_0b0_8_0b1_9_11__q5 = 4'd11;
    endcase
  end
  always@(_theResult____h4973 or CASE_rg_cur_priv_0b0_8_0b1_9_11__q5)
  begin
    case (_theResult____h4973[31:20])
      12'b0:
	  CASE_theResult__973_BITS_31_TO_20_0b0_CASE_rg__ETC__q6 =
	      CASE_rg_cur_priv_0b0_8_0b1_9_11__q5;
      12'b000000000001:
	  CASE_theResult__973_BITS_31_TO_20_0b0_CASE_rg__ETC__q6 = 4'd3;
      default: CASE_theResult__973_BITS_31_TO_20_0b0_CASE_rg__ETC__q6 = 4'd2;
    endcase
  end
  always@(_theResult____h4973 or alu_outputs___1_exc_code__h13747)
  begin
    case (_theResult____h4973[6:0])
      7'b0000011,
      7'b0001111,
      7'b0010011,
      7'b0010111,
      7'b0100011,
      7'b0110011,
      7'b0110111,
      7'b1100011:
	  alu_outputs_exc_code__h13792 = 4'd2;
      7'b1100111, 7'b1101111: alu_outputs_exc_code__h13792 = 4'd0;
      7'b1110011:
	  alu_outputs_exc_code__h13792 = alu_outputs___1_exc_code__h13747;
      default: alu_outputs_exc_code__h13792 = 4'd2;
    endcase
  end
  always@(_theResult____h4973 or
	  IF_IF_imem_rg_pc_BITS_1_TO_0_EQ_0b0_OR_NOT_ime_ETC___d556 or
	  IF_IF_imem_rg_pc_BITS_1_TO_0_EQ_0b0_OR_NOT_ime_ETC___d552 or
	  IF_IF_imem_rg_pc_BITS_1_TO_0_EQ_0b0_OR_NOT_ime_ETC___d554)
  begin
    case (_theResult____h4973[14:12])
      3'b0:
	  IF_IF_imem_rg_pc_BITS_1_TO_0_EQ_0b0_OR_NOT_ime_ETC___d657 =
	      !IF_IF_imem_rg_pc_BITS_1_TO_0_EQ_0b0_OR_NOT_ime_ETC___d552;
      3'b001:
	  IF_IF_imem_rg_pc_BITS_1_TO_0_EQ_0b0_OR_NOT_ime_ETC___d657 =
	      IF_IF_imem_rg_pc_BITS_1_TO_0_EQ_0b0_OR_NOT_ime_ETC___d552;
      3'b100:
	  IF_IF_imem_rg_pc_BITS_1_TO_0_EQ_0b0_OR_NOT_ime_ETC___d657 =
	      !IF_IF_imem_rg_pc_BITS_1_TO_0_EQ_0b0_OR_NOT_ime_ETC___d554;
      3'b101:
	  IF_IF_imem_rg_pc_BITS_1_TO_0_EQ_0b0_OR_NOT_ime_ETC___d657 =
	      IF_IF_imem_rg_pc_BITS_1_TO_0_EQ_0b0_OR_NOT_ime_ETC___d554;
      3'b110:
	  IF_IF_imem_rg_pc_BITS_1_TO_0_EQ_0b0_OR_NOT_ime_ETC___d657 =
	      !IF_IF_imem_rg_pc_BITS_1_TO_0_EQ_0b0_OR_NOT_ime_ETC___d556;
      default: IF_IF_imem_rg_pc_BITS_1_TO_0_EQ_0b0_OR_NOT_ime_ETC___d657 =
		   _theResult____h4973[14:12] != 3'b111 ||
		   IF_IF_imem_rg_pc_BITS_1_TO_0_EQ_0b0_OR_NOT_ime_ETC___d556;
    endcase
  end
  always@(_theResult____h4973 or
	  IF_IF_imem_rg_pc_BITS_1_TO_0_EQ_0b0_OR_NOT_ime_ETC___d556 or
	  IF_IF_imem_rg_pc_BITS_1_TO_0_EQ_0b0_OR_NOT_ime_ETC___d552 or
	  IF_IF_imem_rg_pc_BITS_1_TO_0_EQ_0b0_OR_NOT_ime_ETC___d554)
  begin
    case (_theResult____h4973[14:12])
      3'b0:
	  IF_IF_imem_rg_pc_BITS_1_TO_0_EQ_0b0_OR_NOT_ime_ETC___d563 =
	      IF_IF_imem_rg_pc_BITS_1_TO_0_EQ_0b0_OR_NOT_ime_ETC___d552;
      3'b001:
	  IF_IF_imem_rg_pc_BITS_1_TO_0_EQ_0b0_OR_NOT_ime_ETC___d563 =
	      !IF_IF_imem_rg_pc_BITS_1_TO_0_EQ_0b0_OR_NOT_ime_ETC___d552;
      3'b100:
	  IF_IF_imem_rg_pc_BITS_1_TO_0_EQ_0b0_OR_NOT_ime_ETC___d563 =
	      IF_IF_imem_rg_pc_BITS_1_TO_0_EQ_0b0_OR_NOT_ime_ETC___d554;
      3'b101:
	  IF_IF_imem_rg_pc_BITS_1_TO_0_EQ_0b0_OR_NOT_ime_ETC___d563 =
	      !IF_IF_imem_rg_pc_BITS_1_TO_0_EQ_0b0_OR_NOT_ime_ETC___d554;
      3'b110:
	  IF_IF_imem_rg_pc_BITS_1_TO_0_EQ_0b0_OR_NOT_ime_ETC___d563 =
	      IF_IF_imem_rg_pc_BITS_1_TO_0_EQ_0b0_OR_NOT_ime_ETC___d556;
      default: IF_IF_imem_rg_pc_BITS_1_TO_0_EQ_0b0_OR_NOT_ime_ETC___d563 =
		   _theResult____h4973[14:12] == 3'b111 &&
		   !IF_IF_imem_rg_pc_BITS_1_TO_0_EQ_0b0_OR_NOT_ime_ETC___d556;
    endcase
  end
  always@(_theResult____h4973)
  begin
    case (_theResult____h4973[6:0])
      7'b0000011:
	  CASE_theResult__973_BITS_6_TO_0_0b11_NOT_theRe_ETC__q8 =
	      _theResult____h4973[14:12] != 3'b0 &&
	      _theResult____h4973[14:12] != 3'b100 &&
	      _theResult____h4973[14:12] != 3'b001 &&
	      _theResult____h4973[14:12] != 3'b101 &&
	      _theResult____h4973[14:12] != 3'b010;
      7'b0100011:
	  CASE_theResult__973_BITS_6_TO_0_0b11_NOT_theRe_ETC__q8 =
	      _theResult____h4973[14:12] != 3'b0 &&
	      _theResult____h4973[14:12] != 3'b001 &&
	      _theResult____h4973[14:12] != 3'b010;
      default: CASE_theResult__973_BITS_6_TO_0_0b11_NOT_theRe_ETC__q8 =
		   _theResult____h4973[6:0] != 7'b0101111 ||
		   _theResult____h4973[31:27] != 5'b00010 &&
		   _theResult____h4973[31:27] != 5'b00011 &&
		   _theResult____h4973[31:27] != 5'b0 &&
		   _theResult____h4973[31:27] != 5'b00001 &&
		   _theResult____h4973[31:27] != 5'b01100 &&
		   _theResult____h4973[31:27] != 5'b01000 &&
		   _theResult____h4973[31:27] != 5'b00100 &&
		   _theResult____h4973[31:27] != 5'b10000 &&
		   _theResult____h4973[31:27] != 5'b11000 &&
		   _theResult____h4973[31:27] != 5'b10100 &&
		   _theResult____h4973[31:27] != 5'b11100 ||
		   _theResult____h4973[14:12] != 3'b010;
    endcase
  end
  always@(_theResult____h4973 or
	  CASE_theResult__973_BITS_6_TO_0_0b11_NOT_theRe_ETC__q8 or
	  NOT_IF_imem_rg_pc_BITS_1_TO_0_EQ_0b0_OR_NOT_im_ETC___d593)
  begin
    case (_theResult____h4973[6:0])
      7'b0010011, 7'b0110011:
	  CASE_theResult__973_BITS_6_TO_0_0b10011_NOT_IF_ETC__q9 =
	      NOT_IF_imem_rg_pc_BITS_1_TO_0_EQ_0b0_OR_NOT_im_ETC___d593;
      default: CASE_theResult__973_BITS_6_TO_0_0b10011_NOT_IF_ETC__q9 =
		   _theResult____h4973[6:0] != 7'b0110111 &&
		   _theResult____h4973[6:0] != 7'b0010111 &&
		   CASE_theResult__973_BITS_6_TO_0_0b11_NOT_theRe_ETC__q8;
    endcase
  end
  always@(_theResult____h4973)
  begin
    case (_theResult____h4973[6:0])
      7'b0000011:
	  CASE_theResult__973_BITS_6_TO_0_0b11_theResult_ETC__q10 =
	      _theResult____h4973[14:12] == 3'b0 ||
	      _theResult____h4973[14:12] == 3'b100 ||
	      _theResult____h4973[14:12] == 3'b001 ||
	      _theResult____h4973[14:12] == 3'b101 ||
	      _theResult____h4973[14:12] == 3'b010;
      7'b0100011:
	  CASE_theResult__973_BITS_6_TO_0_0b11_theResult_ETC__q10 =
	      _theResult____h4973[14:12] == 3'b0 ||
	      _theResult____h4973[14:12] == 3'b001 ||
	      _theResult____h4973[14:12] == 3'b010;
      default: CASE_theResult__973_BITS_6_TO_0_0b11_theResult_ETC__q10 =
		   _theResult____h4973[6:0] == 7'b0101111 &&
		   (_theResult____h4973[31:27] == 5'b00010 ||
		    _theResult____h4973[31:27] == 5'b00011 ||
		    _theResult____h4973[31:27] == 5'b0 ||
		    _theResult____h4973[31:27] == 5'b00001 ||
		    _theResult____h4973[31:27] == 5'b01100 ||
		    _theResult____h4973[31:27] == 5'b01000 ||
		    _theResult____h4973[31:27] == 5'b00100 ||
		    _theResult____h4973[31:27] == 5'b10000 ||
		    _theResult____h4973[31:27] == 5'b11000 ||
		    _theResult____h4973[31:27] == 5'b10100 ||
		    _theResult____h4973[31:27] == 5'b11100) &&
		   _theResult____h4973[14:12] == 3'b010;
    endcase
  end
  always@(_theResult____h4973 or
	  CASE_theResult__973_BITS_6_TO_0_0b11_theResult_ETC__q10 or
	  IF_imem_rg_pc_BITS_1_TO_0_EQ_0b0_OR_NOT_imem_r_ETC___d682)
  begin
    case (_theResult____h4973[6:0])
      7'b0010011, 7'b0110011:
	  CASE_theResult__973_BITS_6_TO_0_0b10011_IF_ime_ETC__q11 =
	      IF_imem_rg_pc_BITS_1_TO_0_EQ_0b0_OR_NOT_imem_r_ETC___d682;
      default: CASE_theResult__973_BITS_6_TO_0_0b10011_IF_ime_ETC__q11 =
		   _theResult____h4973[6:0] == 7'b0110111 ||
		   _theResult____h4973[6:0] == 7'b0010111 ||
		   CASE_theResult__973_BITS_6_TO_0_0b11_theResult_ETC__q10;
    endcase
  end
  always@(_theResult____h4973 or
	  rg_cur_priv or
	  IF_rg_cur_priv_1_EQ_0b11_33_OR_rg_cur_priv_1_E_ETC___d752)
  begin
    case (_theResult____h4973[31:20])
      12'b0, 12'b000000000001:
	  IF_IF_imem_rg_pc_BITS_1_TO_0_EQ_0b0_OR_NOT_ime_ETC___d754 = 4'd11;
      default: IF_IF_imem_rg_pc_BITS_1_TO_0_EQ_0b0_OR_NOT_ime_ETC___d754 =
		   (rg_cur_priv == 2'b11 &&
		    _theResult____h4973[31:20] == 12'b001100000010) ?
		     4'd7 :
		     IF_rg_cur_priv_1_EQ_0b11_33_OR_rg_cur_priv_1_E_ETC___d752;
    endcase
  end
  always@(_theResult____h4973)
  begin
    case (_theResult____h4973[14:12])
      3'b0, 3'b001, 3'b010, 3'b100, 3'b101:
	  CASE_theResult__973_BITS_14_TO_12_0b0_0_0b1_0__ETC__q12 = 4'd0;
      default: CASE_theResult__973_BITS_14_TO_12_0b0_0_0b1_0__ETC__q12 =
		   4'd11;
    endcase
  end
  always@(_theResult____h4973)
  begin
    case (_theResult____h4973[14:12])
      3'b0: CASE_theResult__973_BITS_14_TO_12_0b0_4_0b1_5_11__q13 = 4'd4;
      3'b001: CASE_theResult__973_BITS_14_TO_12_0b0_4_0b1_5_11__q13 = 4'd5;
      default: CASE_theResult__973_BITS_14_TO_12_0b0_4_0b1_5_11__q13 = 4'd11;
    endcase
  end
  always@(_theResult____h4973)
  begin
    case (_theResult____h4973[14:12])
      3'b0, 3'b001, 3'b010:
	  CASE_theResult__973_BITS_14_TO_12_0b0_0_0b1_0__ETC__q14 = 4'd0;
      default: CASE_theResult__973_BITS_14_TO_12_0b0_0_0b1_0__ETC__q14 =
		   4'd11;
    endcase
  end
  always@(_theResult____h4973 or
	  IF_IF_imem_rg_pc_BITS_1_TO_0_EQ_0b0_OR_NOT_ime_ETC___d754)
  begin
    case (_theResult____h4973[14:12])
      3'b0:
	  CASE_theResult__973_BITS_14_TO_12_0b0_IF_theRe_ETC__q15 =
	      (_theResult____h4973[11:7] == 5'd0 &&
	       _theResult____h4973[19:15] == 5'd0) ?
		IF_IF_imem_rg_pc_BITS_1_TO_0_EQ_0b0_OR_NOT_ime_ETC___d754 :
		4'd11;
      3'b001, 3'b101:
	  CASE_theResult__973_BITS_14_TO_12_0b0_IF_theRe_ETC__q15 = 4'd2;
      3'b010, 3'b011, 3'b110, 3'b111:
	  CASE_theResult__973_BITS_14_TO_12_0b0_IF_theRe_ETC__q15 = 4'd3;
      3'd4: CASE_theResult__973_BITS_14_TO_12_0b0_IF_theRe_ETC__q15 = 4'd11;
    endcase
  end
  always@(_theResult____h4973 or
	  CASE_theResult__973_BITS_14_TO_12_0b0_0_0b1_0__ETC__q12 or
	  CASE_theResult__973_BITS_14_TO_12_0b0_4_0b1_5_11__q13 or
	  IF_NOT_IF_imem_rg_pc_BITS_1_TO_0_EQ_0b0_OR_NOT_ETC___d719 or
	  CASE_theResult__973_BITS_14_TO_12_0b0_0_0b1_0__ETC__q14 or
	  CASE_theResult__973_BITS_14_TO_12_0b0_IF_theRe_ETC__q15)
  begin
    case (_theResult____h4973[6:0])
      7'b0000011:
	  IF_IF_imem_rg_pc_BITS_1_TO_0_EQ_0b0_OR_NOT_ime_ETC___d769 =
	      CASE_theResult__973_BITS_14_TO_12_0b0_0_0b1_0__ETC__q12;
      7'b0001111:
	  IF_IF_imem_rg_pc_BITS_1_TO_0_EQ_0b0_OR_NOT_ime_ETC___d769 =
	      CASE_theResult__973_BITS_14_TO_12_0b0_4_0b1_5_11__q13;
      7'b0010011, 7'b0110011:
	  IF_IF_imem_rg_pc_BITS_1_TO_0_EQ_0b0_OR_NOT_ime_ETC___d769 =
	      IF_NOT_IF_imem_rg_pc_BITS_1_TO_0_EQ_0b0_OR_NOT_ETC___d719;
      7'b0010111, 7'b0110111:
	  IF_IF_imem_rg_pc_BITS_1_TO_0_EQ_0b0_OR_NOT_ime_ETC___d769 = 4'd0;
      7'b0100011:
	  IF_IF_imem_rg_pc_BITS_1_TO_0_EQ_0b0_OR_NOT_ime_ETC___d769 =
	      CASE_theResult__973_BITS_14_TO_12_0b0_0_0b1_0__ETC__q14;
      7'b0101111:
	  IF_IF_imem_rg_pc_BITS_1_TO_0_EQ_0b0_OR_NOT_ime_ETC___d769 =
	      ((_theResult____h4973[31:27] == 5'b00010 ||
		_theResult____h4973[31:27] == 5'b00011 ||
		_theResult____h4973[31:27] == 5'b0 ||
		_theResult____h4973[31:27] == 5'b00001 ||
		_theResult____h4973[31:27] == 5'b01100 ||
		_theResult____h4973[31:27] == 5'b01000 ||
		_theResult____h4973[31:27] == 5'b00100 ||
		_theResult____h4973[31:27] == 5'b10000 ||
		_theResult____h4973[31:27] == 5'b11000 ||
		_theResult____h4973[31:27] == 5'b10100 ||
		_theResult____h4973[31:27] == 5'b11100) &&
	       _theResult____h4973[14:12] == 3'b010) ?
		4'd0 :
		4'd11;
      7'b1110011:
	  IF_IF_imem_rg_pc_BITS_1_TO_0_EQ_0b0_OR_NOT_ime_ETC___d769 =
	      CASE_theResult__973_BITS_14_TO_12_0b0_IF_theRe_ETC__q15;
      default: IF_IF_imem_rg_pc_BITS_1_TO_0_EQ_0b0_OR_NOT_ime_ETC___d769 =
		   4'd11;
    endcase
  end
  always@(_theResult____h4973 or
	  IF_IF_imem_rg_pc_BITS_1_TO_0_EQ_0b0_OR_NOT_ime_ETC___d769 or
	  IF_IF_imem_rg_pc_BITS_1_TO_0_EQ_0b0_OR_NOT_ime_ETC___d563)
  begin
    case (_theResult____h4973[6:0])
      7'b1100011:
	  IF_IF_imem_rg_pc_BITS_1_TO_0_EQ_0b0_OR_NOT_ime_ETC___d773 =
	      (_theResult____h4973[14:12] != 3'b0 &&
	       _theResult____h4973[14:12] != 3'b001 &&
	       _theResult____h4973[14:12] != 3'b100 &&
	       _theResult____h4973[14:12] != 3'b101 &&
	       _theResult____h4973[14:12] != 3'b110 &&
	       _theResult____h4973[14:12] != 3'b111) ?
		4'd11 :
		(IF_IF_imem_rg_pc_BITS_1_TO_0_EQ_0b0_OR_NOT_ime_ETC___d563 ?
		   4'd1 :
		   4'd0);
      7'b1100111, 7'b1101111:
	  IF_IF_imem_rg_pc_BITS_1_TO_0_EQ_0b0_OR_NOT_ime_ETC___d773 = 4'd1;
      default: IF_IF_imem_rg_pc_BITS_1_TO_0_EQ_0b0_OR_NOT_ime_ETC___d773 =
		   (_theResult____h4973[6:0] == 7'b0110011 &&
		    _theResult____h4973[31:25] == 7'b0000001) ?
		     4'd0 :
		     (((_theResult____h4973[6:0] == 7'b0010011 ||
			_theResult____h4973[6:0] == 7'b0110011) &&
		       (_theResult____h4973[14:12] == 3'b001 ||
			_theResult____h4973[14:12] == 3'b101)) ?
			(_theResult____h4973[25] ? 4'd11 : 4'd0) :
			IF_IF_imem_rg_pc_BITS_1_TO_0_EQ_0b0_OR_NOT_ime_ETC___d769);
    endcase
  end
  always@(_theResult____h4973)
  begin
    case (_theResult____h4973[6:0])
      7'b0000011:
	  CASE_theResult__973_BITS_6_TO_0_0b11_1_0b10011_ETC__q16 = 3'd1;
      7'b0010011, 7'b0010111, 7'b0110011, 7'b0110111:
	  CASE_theResult__973_BITS_6_TO_0_0b11_1_0b10011_ETC__q16 = 3'd0;
      7'b0100011:
	  CASE_theResult__973_BITS_6_TO_0_0b11_1_0b10011_ETC__q16 = 3'd2;
      default: CASE_theResult__973_BITS_6_TO_0_0b11_1_0b10011_ETC__q16 = 3'd4;
    endcase
  end
  always@(_theResult____h4973 or
	  CASE_theResult__973_BITS_6_TO_0_0b11_1_0b10011_ETC__q16)
  begin
    case (_theResult____h4973[6:0])
      7'b1100011, 7'b1100111, 7'b1101111:
	  IF_NOT_stage1_rg_full_03_04_OR_NOT_near_mem_im_ETC___d854 = 3'd0;
      default: IF_NOT_stage1_rg_full_03_04_OR_NOT_near_mem_im_ETC___d854 =
		   (_theResult____h4973[6:0] == 7'b0110011 &&
		    _theResult____h4973[31:25] == 7'b0000001) ?
		     3'd3 :
		     CASE_theResult__973_BITS_6_TO_0_0b11_1_0b10011_ETC__q16;
    endcase
  end
  always@(_theResult____h4973 or
	  rs1_val_bypassed__h4981 or
	  alu_outputs___1_trace_data_word3__h18597 or
	  alu_outputs___1_trace_data_word3__h18617)
  begin
    case (_theResult____h4973[6:0])
      7'b0000011:
	  x_out_data_to_stage2_trace_data_word3__h18724 =
	      alu_outputs___1_trace_data_word3__h18597;
      7'b0100011:
	  x_out_data_to_stage2_trace_data_word3__h18724 =
	      alu_outputs___1_trace_data_word3__h18617;
      default: x_out_data_to_stage2_trace_data_word3__h18724 =
		   { 32'd0, rs1_val_bypassed__h4981 };
    endcase
  end
  always@(_theResult____h4973 or
	  _theResult_____1_fst__h14323 or
	  rd_val___1__h14291 or
	  rd_val___1__h14298 or rd_val___1__h14305 or rd_val___1__h14312)
  begin
    case (_theResult____h4973[14:12])
      3'b010: _theResult_____1_fst__h14295 = rd_val___1__h14291;
      3'b011: _theResult_____1_fst__h14295 = rd_val___1__h14298;
      3'b100: _theResult_____1_fst__h14295 = rd_val___1__h14305;
      3'b110: _theResult_____1_fst__h14295 = rd_val___1__h14312;
      default: _theResult_____1_fst__h14295 = _theResult_____1_fst__h14323;
    endcase
  end
  always@(_theResult____h4973 or
	  rs1_val_bypassed__h4981 or
	  eaddr__h13475 or
	  eaddr__h13496 or
	  alu_outputs___1_addr__h13234 or
	  alu_outputs___1_addr__h13287 or alu_outputs___1_addr__h13258)
  begin
    case (_theResult____h4973[6:0])
      7'b0000011: x_out_data_to_stage2_addr__h13093 = eaddr__h13475;
      7'b0100011: x_out_data_to_stage2_addr__h13093 = eaddr__h13496;
      7'b1100011:
	  x_out_data_to_stage2_addr__h13093 = alu_outputs___1_addr__h13234;
      7'b1100111:
	  x_out_data_to_stage2_addr__h13093 = alu_outputs___1_addr__h13287;
      7'b1101111:
	  x_out_data_to_stage2_addr__h13093 = alu_outputs___1_addr__h13258;
      default: x_out_data_to_stage2_addr__h13093 = rs1_val_bypassed__h4981;
    endcase
  end
  always@(_theResult____h4973 or
	  IF_imem_rg_pc_BITS_1_TO_0_EQ_0b0_OR_NOT_imem_r_ETC___d898 or
	  alu_outputs___1_addr__h13234 or
	  alu_outputs___1_addr__h13287 or alu_outputs___1_addr__h13258)
  begin
    case (_theResult____h4973[6:0])
      7'b1100011: x__h19341 = alu_outputs___1_addr__h13234;
      7'b1100111: x__h19341 = alu_outputs___1_addr__h13287;
      7'b1101111: x__h19341 = alu_outputs___1_addr__h13258;
      default: x__h19341 =
		   IF_imem_rg_pc_BITS_1_TO_0_EQ_0b0_OR_NOT_imem_r_ETC___d898;
    endcase
  end
  always@(_theResult____h4973 or imem_rg_pc or data_to_stage2_addr__h13084)
  begin
    case (_theResult____h4973[6:0])
      7'b1100111, 7'b1101111:
	  IF_IF_imem_rg_pc_BITS_1_TO_0_EQ_0b0_OR_NOT_ime_ETC___d1050 =
	      data_to_stage2_addr__h13084;
      default: IF_IF_imem_rg_pc_BITS_1_TO_0_EQ_0b0_OR_NOT_ime_ETC___d1050 =
		   (_theResult____h4973[6:0] == 7'b1110011 &&
		    _theResult____h4973[14:12] == 3'b0 &&
		    _theResult____h4973[11:7] == 5'd0 &&
		    _theResult____h4973[19:15] == 5'd0 &&
		    _theResult____h4973[31:20] == 12'b000000000001) ?
		     imem_rg_pc :
		     32'd0;
    endcase
  end
  always@(_theResult____h4973 or
	  alu_outputs___1_trace_data_word1__h18615 or
	  rd_val__h13421 or rd_val__h13456 or rd_val__h13439)
  begin
    case (_theResult____h4973[6:0])
      7'b0010011, 7'b0110011:
	  IF_IF_imem_rg_pc_BITS_1_TO_0_EQ_0b0_OR_NOT_ime_ETC___d1256 =
	      rd_val__h13421;
      7'b0010111:
	  IF_IF_imem_rg_pc_BITS_1_TO_0_EQ_0b0_OR_NOT_ime_ETC___d1256 =
	      rd_val__h13456;
      7'b0110111:
	  IF_IF_imem_rg_pc_BITS_1_TO_0_EQ_0b0_OR_NOT_ime_ETC___d1256 =
	      rd_val__h13439;
      default: IF_IF_imem_rg_pc_BITS_1_TO_0_EQ_0b0_OR_NOT_ime_ETC___d1256 =
		   alu_outputs___1_trace_data_word1__h18615;
    endcase
  end
  always@(_theResult____h4973 or
	  alu_outputs___1_val1__h13773 or
	  rd_val__h13421 or
	  rd_val__h13456 or rd_val__h13439 or alu_outputs___1_val1__h13751)
  begin
    case (_theResult____h4973[6:0])
      7'b0010011, 7'b0110011:
	  IF_IF_imem_rg_pc_BITS_1_TO_0_EQ_0b0_OR_NOT_ime_ETC___d965 =
	      rd_val__h13421;
      7'b0010111:
	  IF_IF_imem_rg_pc_BITS_1_TO_0_EQ_0b0_OR_NOT_ime_ETC___d965 =
	      rd_val__h13456;
      7'b0110111:
	  IF_IF_imem_rg_pc_BITS_1_TO_0_EQ_0b0_OR_NOT_ime_ETC___d965 =
	      rd_val__h13439;
      7'b1110011:
	  IF_IF_imem_rg_pc_BITS_1_TO_0_EQ_0b0_OR_NOT_ime_ETC___d965 =
	      alu_outputs___1_val1__h13751;
      default: IF_IF_imem_rg_pc_BITS_1_TO_0_EQ_0b0_OR_NOT_ime_ETC___d965 =
		   alu_outputs___1_val1__h13773;
    endcase
  end
  always@(_theResult____h4973 or
	  IF_IF_imem_rg_pc_BITS_1_TO_0_EQ_0b0_OR_NOT_ime_ETC___d1257 or
	  IF_imem_rg_pc_BITS_1_TO_0_EQ_0b0_OR_NOT_imem_r_ETC___d898)
  begin
    case (_theResult____h4973[6:0])
      7'b1100111, 7'b1101111:
	  x__h19610 =
	      IF_imem_rg_pc_BITS_1_TO_0_EQ_0b0_OR_NOT_imem_r_ETC___d898;
      default: x__h19610 =
		   IF_IF_imem_rg_pc_BITS_1_TO_0_EQ_0b0_OR_NOT_ime_ETC___d1257;
    endcase
  end
  always@(_theResult____h4973 or
	  rs1_val_bypassed__h4981 or
	  IF_IF_imem_rg_pc_BITS_1_TO_0_EQ_0b0_OR_NOT_ime_ETC___d966 or
	  IF_imem_rg_pc_BITS_1_TO_0_EQ_0b0_OR_NOT_imem_r_ETC___d898)
  begin
    case (_theResult____h4973[6:0])
      7'b1100111, 7'b1101111:
	  x_out_data_to_stage2_val1__h13094 =
	      IF_imem_rg_pc_BITS_1_TO_0_EQ_0b0_OR_NOT_imem_r_ETC___d898;
      default: x_out_data_to_stage2_val1__h13094 =
		   (_theResult____h4973[6:0] == 7'b0110011 &&
		    _theResult____h4973[31:25] == 7'b0000001) ?
		     rs1_val_bypassed__h4981 :
		     IF_IF_imem_rg_pc_BITS_1_TO_0_EQ_0b0_OR_NOT_ime_ETC___d966;
    endcase
  end
  always@(_theResult____h4973)
  begin
    case (_theResult____h4973[6:0])
      7'b0000011:
	  CASE_theResult__973_BITS_6_TO_0_0b11_9_0b1111__ETC__q18 = 5'd9;
      7'b0001111, 7'b1100011, 7'b1110011:
	  CASE_theResult__973_BITS_6_TO_0_0b11_9_0b1111__ETC__q18 = 5'd5;
      7'b0010011, 7'b0010111, 7'b0110011, 7'b0110111, 7'b1100111, 7'b1101111:
	  CASE_theResult__973_BITS_6_TO_0_0b11_9_0b1111__ETC__q18 = 5'd6;
      7'b0100011:
	  CASE_theResult__973_BITS_6_TO_0_0b11_9_0b1111__ETC__q18 = 5'd11;
      7'b0101111:
	  CASE_theResult__973_BITS_6_TO_0_0b11_9_0b1111__ETC__q18 = 5'd13;
      default: CASE_theResult__973_BITS_6_TO_0_0b11_9_0b1111__ETC__q18 =
		   5'd14;
    endcase
  end
  always@(stage2_rg_stage2 or stage2_mbox$word or near_mem$dmem_word64)
  begin
    case (stage2_rg_stage2[338:336])
      3'd0, 3'd2:
	  CASE_stage2_rg_stage2_BITS_338_TO_336_0_stage2_ETC__q19 =
	      stage2_rg_stage2[159:128];
      3'd1, 3'd4:
	  CASE_stage2_rg_stage2_BITS_338_TO_336_0_stage2_ETC__q19 =
	      near_mem$dmem_word64[31:0];
      default: CASE_stage2_rg_stage2_BITS_338_TO_336_0_stage2_ETC__q19 =
		   stage2_mbox$word;
    endcase
  end

  // handling of inlined registers

  always@(posedge CLK)
  begin
    if (RST_N == `BSV_RESET_VALUE)
      begin
        cfg_logdelay <= `BSV_ASSIGNMENT_DELAY 64'd0;
	cfg_verbosity <= `BSV_ASSIGNMENT_DELAY 4'd0;
	imem_rg_cache_addr <= `BSV_ASSIGNMENT_DELAY 32'hFFFFFFFF;
	rg_cur_priv <= `BSV_ASSIGNMENT_DELAY 2'b11;
	rg_prev_mip <= `BSV_ASSIGNMENT_DELAY 32'd0;
	rg_run_on_reset <= `BSV_ASSIGNMENT_DELAY 1'd0;
	rg_state <= `BSV_ASSIGNMENT_DELAY 4'd0;
	rg_step_count <= `BSV_ASSIGNMENT_DELAY 1'd0;
	rg_stop_req <= `BSV_ASSIGNMENT_DELAY 1'd0;
	stage1_rg_full <= `BSV_ASSIGNMENT_DELAY 1'd0;
	stage2_rg_full <= `BSV_ASSIGNMENT_DELAY 1'd0;
	stage2_rg_resetting <= `BSV_ASSIGNMENT_DELAY 1'd0;
	stage3_rg_full <= `BSV_ASSIGNMENT_DELAY 1'd0;
      end
    else
      begin
        if (cfg_logdelay$EN)
	  cfg_logdelay <= `BSV_ASSIGNMENT_DELAY cfg_logdelay$D_IN;
	if (cfg_verbosity$EN)
	  cfg_verbosity <= `BSV_ASSIGNMENT_DELAY cfg_verbosity$D_IN;
	if (imem_rg_cache_addr$EN)
	  imem_rg_cache_addr <= `BSV_ASSIGNMENT_DELAY imem_rg_cache_addr$D_IN;
	if (rg_cur_priv$EN)
	  rg_cur_priv <= `BSV_ASSIGNMENT_DELAY rg_cur_priv$D_IN;
	if (rg_prev_mip$EN)
	  rg_prev_mip <= `BSV_ASSIGNMENT_DELAY rg_prev_mip$D_IN;
	if (rg_run_on_reset$EN)
	  rg_run_on_reset <= `BSV_ASSIGNMENT_DELAY rg_run_on_reset$D_IN;
	if (rg_state$EN) rg_state <= `BSV_ASSIGNMENT_DELAY rg_state$D_IN;
	if (rg_step_count$EN)
	  rg_step_count <= `BSV_ASSIGNMENT_DELAY rg_step_count$D_IN;
	if (rg_stop_req$EN)
	  rg_stop_req <= `BSV_ASSIGNMENT_DELAY rg_stop_req$D_IN;
	if (stage1_rg_full$EN)
	  stage1_rg_full <= `BSV_ASSIGNMENT_DELAY stage1_rg_full$D_IN;
	if (stage2_rg_full$EN)
	  stage2_rg_full <= `BSV_ASSIGNMENT_DELAY stage2_rg_full$D_IN;
	if (stage2_rg_resetting$EN)
	  stage2_rg_resetting <= `BSV_ASSIGNMENT_DELAY
	      stage2_rg_resetting$D_IN;
	if (stage3_rg_full$EN)
	  stage3_rg_full <= `BSV_ASSIGNMENT_DELAY stage3_rg_full$D_IN;
      end
    if (imem_rg_cache_b16$EN)
      imem_rg_cache_b16 <= `BSV_ASSIGNMENT_DELAY imem_rg_cache_b16$D_IN;
    if (imem_rg_f3$EN) imem_rg_f3 <= `BSV_ASSIGNMENT_DELAY imem_rg_f3$D_IN;
    if (imem_rg_mstatus_MXR$EN)
      imem_rg_mstatus_MXR <= `BSV_ASSIGNMENT_DELAY imem_rg_mstatus_MXR$D_IN;
    if (imem_rg_pc$EN) imem_rg_pc <= `BSV_ASSIGNMENT_DELAY imem_rg_pc$D_IN;
    if (imem_rg_priv$EN)
      imem_rg_priv <= `BSV_ASSIGNMENT_DELAY imem_rg_priv$D_IN;
    if (imem_rg_satp$EN)
      imem_rg_satp <= `BSV_ASSIGNMENT_DELAY imem_rg_satp$D_IN;
    if (imem_rg_sstatus_SUM$EN)
      imem_rg_sstatus_SUM <= `BSV_ASSIGNMENT_DELAY imem_rg_sstatus_SUM$D_IN;
    if (imem_rg_tval$EN)
      imem_rg_tval <= `BSV_ASSIGNMENT_DELAY imem_rg_tval$D_IN;
    if (rg_csr_pc$EN) rg_csr_pc <= `BSV_ASSIGNMENT_DELAY rg_csr_pc$D_IN;
    if (rg_csr_val1$EN) rg_csr_val1 <= `BSV_ASSIGNMENT_DELAY rg_csr_val1$D_IN;
    if (rg_mstatus_MXR$EN)
      rg_mstatus_MXR <= `BSV_ASSIGNMENT_DELAY rg_mstatus_MXR$D_IN;
    if (rg_next_pc$EN) rg_next_pc <= `BSV_ASSIGNMENT_DELAY rg_next_pc$D_IN;
    if (rg_sstatus_SUM$EN)
      rg_sstatus_SUM <= `BSV_ASSIGNMENT_DELAY rg_sstatus_SUM$D_IN;
    if (rg_start_CPI_cycles$EN)
      rg_start_CPI_cycles <= `BSV_ASSIGNMENT_DELAY rg_start_CPI_cycles$D_IN;
    if (rg_start_CPI_instrs$EN)
      rg_start_CPI_instrs <= `BSV_ASSIGNMENT_DELAY rg_start_CPI_instrs$D_IN;
    if (rg_trap_info$EN)
      rg_trap_info <= `BSV_ASSIGNMENT_DELAY rg_trap_info$D_IN;
    if (rg_trap_instr$EN)
      rg_trap_instr <= `BSV_ASSIGNMENT_DELAY rg_trap_instr$D_IN;
    if (rg_trap_interrupt$EN)
      rg_trap_interrupt <= `BSV_ASSIGNMENT_DELAY rg_trap_interrupt$D_IN;
    if (rg_trap_trace_data$EN)
      rg_trap_trace_data <= `BSV_ASSIGNMENT_DELAY rg_trap_trace_data$D_IN;
    if (stage2_rg_stage2$EN)
      stage2_rg_stage2 <= `BSV_ASSIGNMENT_DELAY stage2_rg_stage2$D_IN;
    if (stage3_rg_stage3$EN)
      stage3_rg_stage3 <= `BSV_ASSIGNMENT_DELAY stage3_rg_stage3$D_IN;
  end

  // synopsys translate_off
  `ifdef BSV_NO_INITIAL_BLOCKS
  `else // not BSV_NO_INITIAL_BLOCKS
  initial
  begin
    cfg_logdelay = 64'hAAAAAAAAAAAAAAAA;
    cfg_verbosity = 4'hA;
    imem_rg_cache_addr = 32'hAAAAAAAA;
    imem_rg_cache_b16 = 16'hAAAA;
    imem_rg_f3 = 3'h2;
    imem_rg_mstatus_MXR = 1'h0;
    imem_rg_pc = 32'hAAAAAAAA;
    imem_rg_priv = 2'h2;
    imem_rg_satp = 32'hAAAAAAAA;
    imem_rg_sstatus_SUM = 1'h0;
    imem_rg_tval = 32'hAAAAAAAA;
    rg_csr_pc = 32'hAAAAAAAA;
    rg_csr_val1 = 32'hAAAAAAAA;
    rg_cur_priv = 2'h2;
    rg_mstatus_MXR = 1'h0;
    rg_next_pc = 32'hAAAAAAAA;
    rg_prev_mip = 32'hAAAAAAAA;
    rg_run_on_reset = 1'h0;
    rg_sstatus_SUM = 1'h0;
    rg_start_CPI_cycles = 64'hAAAAAAAAAAAAAAAA;
    rg_start_CPI_instrs = 64'hAAAAAAAAAAAAAAAA;
    rg_state = 4'hA;
    rg_step_count = 1'h0;
    rg_stop_req = 1'h0;
    rg_trap_info = 68'hAAAAAAAAAAAAAAAAA;
    rg_trap_instr = 32'hAAAAAAAA;
    rg_trap_interrupt = 1'h0;
    rg_trap_trace_data =
	235'h2AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA;
    stage1_rg_full = 1'h0;
    stage2_rg_full = 1'h0;
    stage2_rg_resetting = 1'h0;
    stage2_rg_stage2 =
	405'h0AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA;
    stage3_rg_full = 1'h0;
    stage3_rg_stage3 = 104'hAAAAAAAAAAAAAAAAAAAAAAAAAA;
  end
  `endif // BSV_NO_INITIAL_BLOCKS
  // synopsys translate_on

  // handling of system tasks

  // synopsys translate_off
  always@(negedge CLK)
  begin
    #0;
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe)
	$display("================================================================");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe)
	$display("%0d: Pipeline State:  minstret:%0d  cur_priv:%0d  mstatus:%0x",
		 csr_regfile$read_csr_mcycle,
		 csr_regfile$read_csr_minstret,
		 rg_cur_priv,
		 csr_regfile$read_mstatus);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe) $write("    ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe)
	$write("MStatus{",
	       "sd:%0d",
	       csr_regfile$read_mstatus[14:13] == 2'h3 ||
	       csr_regfile$read_mstatus[16:15] == 2'h3);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe && csr_regfile$read_misa[27:26] == 2'd2)
	$write(" sxl:%0d uxl:%0d", 2'd0, 2'd0);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe && csr_regfile$read_misa[27:26] != 2'd2)
	$write("");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe)
	$write(" tsr:%0d", csr_regfile$read_mstatus[22]);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe)
	$write(" tw:%0d", csr_regfile$read_mstatus[21]);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe)
	$write(" tvm:%0d", csr_regfile$read_mstatus[20]);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe)
	$write(" mxr:%0d", csr_regfile$read_mstatus[19]);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe)
	$write(" sum:%0d", csr_regfile$read_mstatus[18]);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe)
	$write(" mprv:%0d", csr_regfile$read_mstatus[17]);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe)
	$write(" xs:%0d", csr_regfile$read_mstatus[16:15]);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe)
	$write(" fs:%0d", csr_regfile$read_mstatus[14:13]);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe)
	$write(" mpp:%0d", csr_regfile$read_mstatus[12:11]);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe)
	$write(" spp:%0d", csr_regfile$read_mstatus[8]);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe)
	$write(" pies:%0d_%0d%0d",
	       csr_regfile$read_mstatus[7],
	       csr_regfile$read_mstatus[5],
	       csr_regfile$read_mstatus[4]);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe)
	$write(" ies:%0d_%0d%0d",
	       csr_regfile$read_mstatus[3],
	       csr_regfile$read_mstatus[1],
	       csr_regfile$read_mstatus[0]);
    if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_show_pipe) $write("}");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe) $write("\n");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe) $write("    Stage3: ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe) $write("Output_Stage3");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe && stage3_rg_full) $write(" PIPE");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe && !stage3_rg_full) $write(" EMPTY");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe) $write("\n");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe) $write("        Bypass  to Stage1: ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe) $write("Bypass {");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe &&
	  (!stage3_rg_full || !stage3_rg_stage3[37]))
	$write("Rd -");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe && stage3_rg_full && stage3_rg_stage3[37])
	$write("Rd %0d ",
	       stage3_rg_stage3[36:32],
	       "rd_val:%h",
	       stage3_rg_stage3[31:0]);
    if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_show_pipe) $write("}");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe) $write("\n");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe)
	$display("    Stage2: pc 0x%08h instr 0x%08h priv %0d",
		 stage2_rg_stage2[402:371],
		 stage2_rg_stage2[370:339],
		 stage2_rg_stage2[404:403]);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe) $write("        ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe &&
	  IF_stage2_rg_full_5_THEN_IF_stage2_rg_stage2_6_ETC___d126 == 2'd0)
	$write("Output_Stage2", " EMPTY");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe &&
	  IF_stage2_rg_full_5_THEN_IF_stage2_rg_stage2_6_ETC___d126 == 2'd1)
	$write("Output_Stage2", " BUSY: pc:%0h", stage2_rg_stage2[402:371]);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe &&
	  IF_stage2_rg_full_5_THEN_IF_stage2_rg_stage2_6_ETC___d126 == 2'd3)
	$write("Output_Stage2", " NONPIPE: ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe &&
	  IF_stage2_rg_full_5_THEN_IF_stage2_rg_stage2_6_ETC___d126 != 2'd0 &&
	  IF_stage2_rg_full_5_THEN_IF_stage2_rg_stage2_6_ETC___d126 != 2'd1 &&
	  IF_stage2_rg_full_5_THEN_IF_stage2_rg_stage2_6_ETC___d126 != 2'd3)
	$write("Output_Stage2", " PIPE: ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe &&
	  IF_stage2_rg_full_5_THEN_IF_stage2_rg_stage2_6_ETC___d126 == 2'd0)
	$write("");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe &&
	  IF_stage2_rg_full_5_THEN_IF_stage2_rg_stage2_6_ETC___d126 == 2'd1)
	$write("");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe &&
	  IF_stage2_rg_full_5_THEN_IF_stage2_rg_stage2_6_ETC___d126 == 2'd3)
	$write("");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe &&
	  IF_stage2_rg_full_5_THEN_IF_stage2_rg_stage2_6_ETC___d126 != 2'd0 &&
	  IF_stage2_rg_full_5_THEN_IF_stage2_rg_stage2_6_ETC___d126 != 2'd1 &&
	  IF_stage2_rg_full_5_THEN_IF_stage2_rg_stage2_6_ETC___d126 != 2'd3)
	$write("data_to_Stage3 {pc:%h  instr:%h  priv:%0d\n",
	       stage2_rg_stage2[402:371],
	       stage2_rg_stage2[370:339],
	       stage2_rg_stage2[404:403]);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe &&
	  IF_stage2_rg_full_5_THEN_IF_stage2_rg_stage2_6_ETC___d126 == 2'd0)
	$write("");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe &&
	  IF_stage2_rg_full_5_THEN_IF_stage2_rg_stage2_6_ETC___d126 == 2'd1)
	$write("");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe &&
	  IF_stage2_rg_full_5_THEN_IF_stage2_rg_stage2_6_ETC___d126 == 2'd3)
	$write("");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe &&
	  IF_stage2_rg_full_5_THEN_IF_stage2_rg_stage2_6_ETC___d126 != 2'd0 &&
	  IF_stage2_rg_full_5_THEN_IF_stage2_rg_stage2_6_ETC___d126 != 2'd1 &&
	  IF_stage2_rg_full_5_THEN_IF_stage2_rg_stage2_6_ETC___d126 != 2'd3)
	$write("        rd_valid:");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe &&
	  IF_stage2_rg_full_5_THEN_IF_stage2_rg_stage2_6_ETC___d126 == 2'd0)
	$write("");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe &&
	  IF_stage2_rg_full_5_THEN_IF_stage2_rg_stage2_6_ETC___d126 == 2'd1)
	$write("");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe &&
	  IF_stage2_rg_full_5_THEN_IF_stage2_rg_stage2_6_ETC___d126 == 2'd3)
	$write("");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe &&
	  IF_stage2_rg_full_5_THEN_IF_stage2_rg_stage2_6_ETC___d126 != 2'd0 &&
	  IF_stage2_rg_full_5_THEN_IF_stage2_rg_stage2_6_ETC___d126 != 2'd1 &&
	  IF_stage2_rg_full_5_THEN_IF_stage2_rg_stage2_6_ETC___d126 != 2'd3 &&
	  stage2_rg_stage2[338:336] != 3'd0 &&
	  IF_stage2_rg_stage2_6_BITS_338_TO_336_7_EQ_1_9_ETC___d140)
	$write("False");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe &&
	  IF_stage2_rg_full_5_THEN_IF_stage2_rg_stage2_6_ETC___d126 != 2'd0 &&
	  IF_stage2_rg_full_5_THEN_IF_stage2_rg_stage2_6_ETC___d126 != 2'd1 &&
	  IF_stage2_rg_full_5_THEN_IF_stage2_rg_stage2_6_ETC___d126 != 2'd3 &&
	  (stage2_rg_stage2[338:336] == 3'd0 ||
	   IF_stage2_rg_stage2_6_BITS_338_TO_336_7_EQ_1_9_ETC___d149))
	$write("True");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe &&
	  IF_stage2_rg_full_5_THEN_IF_stage2_rg_stage2_6_ETC___d126 == 2'd0)
	$write("");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe &&
	  IF_stage2_rg_full_5_THEN_IF_stage2_rg_stage2_6_ETC___d126 == 2'd1)
	$write("");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe &&
	  IF_stage2_rg_full_5_THEN_IF_stage2_rg_stage2_6_ETC___d126 == 2'd3)
	$write("");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe &&
	  IF_stage2_rg_full_5_THEN_IF_stage2_rg_stage2_6_ETC___d126 != 2'd0 &&
	  IF_stage2_rg_full_5_THEN_IF_stage2_rg_stage2_6_ETC___d126 != 2'd1 &&
	  IF_stage2_rg_full_5_THEN_IF_stage2_rg_stage2_6_ETC___d126 != 2'd3)
	$write("  grd:%0d  rd_val:%h\n",
	       x_out_data_to_stage3_rd__h7110,
	       x_out_data_to_stage3_rd_val__h7111);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe &&
	  IF_stage2_rg_full_5_THEN_IF_stage2_rg_stage2_6_ETC___d126 == 2'd0)
	$write("");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe &&
	  IF_stage2_rg_full_5_THEN_IF_stage2_rg_stage2_6_ETC___d126 == 2'd1)
	$write("");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe &&
	  IF_stage2_rg_full_5_THEN_IF_stage2_rg_stage2_6_ETC___d126 == 2'd3)
	$write("Trap_Info { ", "epc: ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe &&
	  IF_stage2_rg_full_5_THEN_IF_stage2_rg_stage2_6_ETC___d126 != 2'd0 &&
	  IF_stage2_rg_full_5_THEN_IF_stage2_rg_stage2_6_ETC___d126 != 2'd1 &&
	  IF_stage2_rg_full_5_THEN_IF_stage2_rg_stage2_6_ETC___d126 != 2'd3)
	$write("");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe &&
	  IF_stage2_rg_full_5_THEN_IF_stage2_rg_stage2_6_ETC___d126 == 2'd0)
	$write("");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe &&
	  IF_stage2_rg_full_5_THEN_IF_stage2_rg_stage2_6_ETC___d126 == 2'd1)
	$write("");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe &&
	  IF_stage2_rg_full_5_THEN_IF_stage2_rg_stage2_6_ETC___d126 == 2'd3)
	$write("'h%h", stage2_rg_stage2[402:371]);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe &&
	  IF_stage2_rg_full_5_THEN_IF_stage2_rg_stage2_6_ETC___d126 != 2'd0 &&
	  IF_stage2_rg_full_5_THEN_IF_stage2_rg_stage2_6_ETC___d126 != 2'd1 &&
	  IF_stage2_rg_full_5_THEN_IF_stage2_rg_stage2_6_ETC___d126 != 2'd3)
	$write("");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe &&
	  IF_stage2_rg_full_5_THEN_IF_stage2_rg_stage2_6_ETC___d126 == 2'd0)
	$write("");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe &&
	  IF_stage2_rg_full_5_THEN_IF_stage2_rg_stage2_6_ETC___d126 == 2'd1)
	$write("");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe &&
	  IF_stage2_rg_full_5_THEN_IF_stage2_rg_stage2_6_ETC___d126 == 2'd3)
	$write(", ", "exc_code: ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe &&
	  IF_stage2_rg_full_5_THEN_IF_stage2_rg_stage2_6_ETC___d126 != 2'd0 &&
	  IF_stage2_rg_full_5_THEN_IF_stage2_rg_stage2_6_ETC___d126 != 2'd1 &&
	  IF_stage2_rg_full_5_THEN_IF_stage2_rg_stage2_6_ETC___d126 != 2'd3)
	$write("");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe &&
	  IF_stage2_rg_full_5_THEN_IF_stage2_rg_stage2_6_ETC___d126 == 2'd0)
	$write("");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe &&
	  IF_stage2_rg_full_5_THEN_IF_stage2_rg_stage2_6_ETC___d126 == 2'd1)
	$write("");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe &&
	  IF_stage2_rg_full_5_THEN_IF_stage2_rg_stage2_6_ETC___d126 == 2'd3)
	$write("'h%h", near_mem$dmem_exc_code);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe &&
	  IF_stage2_rg_full_5_THEN_IF_stage2_rg_stage2_6_ETC___d126 != 2'd0 &&
	  IF_stage2_rg_full_5_THEN_IF_stage2_rg_stage2_6_ETC___d126 != 2'd1 &&
	  IF_stage2_rg_full_5_THEN_IF_stage2_rg_stage2_6_ETC___d126 != 2'd3)
	$write("");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe &&
	  IF_stage2_rg_full_5_THEN_IF_stage2_rg_stage2_6_ETC___d126 == 2'd0)
	$write("");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe &&
	  IF_stage2_rg_full_5_THEN_IF_stage2_rg_stage2_6_ETC___d126 == 2'd1)
	$write("");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe &&
	  IF_stage2_rg_full_5_THEN_IF_stage2_rg_stage2_6_ETC___d126 == 2'd3)
	$write(", ", "tval: ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe &&
	  IF_stage2_rg_full_5_THEN_IF_stage2_rg_stage2_6_ETC___d126 != 2'd0 &&
	  IF_stage2_rg_full_5_THEN_IF_stage2_rg_stage2_6_ETC___d126 != 2'd1 &&
	  IF_stage2_rg_full_5_THEN_IF_stage2_rg_stage2_6_ETC___d126 != 2'd3)
	$write("");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe &&
	  IF_stage2_rg_full_5_THEN_IF_stage2_rg_stage2_6_ETC___d126 == 2'd0)
	$write("");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe &&
	  IF_stage2_rg_full_5_THEN_IF_stage2_rg_stage2_6_ETC___d126 == 2'd1)
	$write("");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe &&
	  IF_stage2_rg_full_5_THEN_IF_stage2_rg_stage2_6_ETC___d126 == 2'd3)
	$write("'h%h", stage2_rg_stage2[330:299], " }");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe &&
	  IF_stage2_rg_full_5_THEN_IF_stage2_rg_stage2_6_ETC___d126 != 2'd0 &&
	  IF_stage2_rg_full_5_THEN_IF_stage2_rg_stage2_6_ETC___d126 != 2'd1 &&
	  IF_stage2_rg_full_5_THEN_IF_stage2_rg_stage2_6_ETC___d126 != 2'd3)
	$write("");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe &&
	  IF_stage2_rg_full_5_THEN_IF_stage2_rg_stage2_6_ETC___d126 == 2'd0)
	$write("");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe &&
	  IF_stage2_rg_full_5_THEN_IF_stage2_rg_stage2_6_ETC___d126 == 2'd1)
	$write("");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe &&
	  IF_stage2_rg_full_5_THEN_IF_stage2_rg_stage2_6_ETC___d126 == 2'd3)
	$write(" ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe &&
	  IF_stage2_rg_full_5_THEN_IF_stage2_rg_stage2_6_ETC___d126 != 2'd0 &&
	  IF_stage2_rg_full_5_THEN_IF_stage2_rg_stage2_6_ETC___d126 != 2'd1 &&
	  IF_stage2_rg_full_5_THEN_IF_stage2_rg_stage2_6_ETC___d126 != 2'd3)
	$write("");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe &&
	  IF_stage2_rg_full_5_THEN_IF_stage2_rg_stage2_6_ETC___d126 == 2'd0)
	$write("");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe &&
	  IF_stage2_rg_full_5_THEN_IF_stage2_rg_stage2_6_ETC___d126 == 2'd1)
	$write("");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe &&
	  IF_stage2_rg_full_5_THEN_IF_stage2_rg_stage2_6_ETC___d126 == 2'd3)
	$write("Trap_Info { ", "epc: ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe &&
	  IF_stage2_rg_full_5_THEN_IF_stage2_rg_stage2_6_ETC___d126 != 2'd0 &&
	  IF_stage2_rg_full_5_THEN_IF_stage2_rg_stage2_6_ETC___d126 != 2'd1 &&
	  IF_stage2_rg_full_5_THEN_IF_stage2_rg_stage2_6_ETC___d126 != 2'd3)
	$write("");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe &&
	  IF_stage2_rg_full_5_THEN_IF_stage2_rg_stage2_6_ETC___d126 == 2'd0)
	$write("");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe &&
	  IF_stage2_rg_full_5_THEN_IF_stage2_rg_stage2_6_ETC___d126 == 2'd1)
	$write("");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe &&
	  IF_stage2_rg_full_5_THEN_IF_stage2_rg_stage2_6_ETC___d126 == 2'd3)
	$write("'h%h", stage2_rg_stage2[402:371]);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe &&
	  IF_stage2_rg_full_5_THEN_IF_stage2_rg_stage2_6_ETC___d126 != 2'd0 &&
	  IF_stage2_rg_full_5_THEN_IF_stage2_rg_stage2_6_ETC___d126 != 2'd1 &&
	  IF_stage2_rg_full_5_THEN_IF_stage2_rg_stage2_6_ETC___d126 != 2'd3)
	$write("");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe &&
	  IF_stage2_rg_full_5_THEN_IF_stage2_rg_stage2_6_ETC___d126 == 2'd0)
	$write("");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe &&
	  IF_stage2_rg_full_5_THEN_IF_stage2_rg_stage2_6_ETC___d126 == 2'd1)
	$write("");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe &&
	  IF_stage2_rg_full_5_THEN_IF_stage2_rg_stage2_6_ETC___d126 == 2'd3)
	$write(", ", "exc_code: ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe &&
	  IF_stage2_rg_full_5_THEN_IF_stage2_rg_stage2_6_ETC___d126 != 2'd0 &&
	  IF_stage2_rg_full_5_THEN_IF_stage2_rg_stage2_6_ETC___d126 != 2'd1 &&
	  IF_stage2_rg_full_5_THEN_IF_stage2_rg_stage2_6_ETC___d126 != 2'd3)
	$write("");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe &&
	  IF_stage2_rg_full_5_THEN_IF_stage2_rg_stage2_6_ETC___d126 == 2'd0)
	$write("");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe &&
	  IF_stage2_rg_full_5_THEN_IF_stage2_rg_stage2_6_ETC___d126 == 2'd1)
	$write("");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe &&
	  IF_stage2_rg_full_5_THEN_IF_stage2_rg_stage2_6_ETC___d126 == 2'd3)
	$write("'h%h", near_mem$dmem_exc_code);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe &&
	  IF_stage2_rg_full_5_THEN_IF_stage2_rg_stage2_6_ETC___d126 != 2'd0 &&
	  IF_stage2_rg_full_5_THEN_IF_stage2_rg_stage2_6_ETC___d126 != 2'd1 &&
	  IF_stage2_rg_full_5_THEN_IF_stage2_rg_stage2_6_ETC___d126 != 2'd3)
	$write("");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe &&
	  IF_stage2_rg_full_5_THEN_IF_stage2_rg_stage2_6_ETC___d126 == 2'd0)
	$write("");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe &&
	  IF_stage2_rg_full_5_THEN_IF_stage2_rg_stage2_6_ETC___d126 == 2'd1)
	$write("");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe &&
	  IF_stage2_rg_full_5_THEN_IF_stage2_rg_stage2_6_ETC___d126 == 2'd3)
	$write(", ", "tval: ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe &&
	  IF_stage2_rg_full_5_THEN_IF_stage2_rg_stage2_6_ETC___d126 != 2'd0 &&
	  IF_stage2_rg_full_5_THEN_IF_stage2_rg_stage2_6_ETC___d126 != 2'd1 &&
	  IF_stage2_rg_full_5_THEN_IF_stage2_rg_stage2_6_ETC___d126 != 2'd3)
	$write("");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe &&
	  IF_stage2_rg_full_5_THEN_IF_stage2_rg_stage2_6_ETC___d126 == 2'd0)
	$write("");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe &&
	  IF_stage2_rg_full_5_THEN_IF_stage2_rg_stage2_6_ETC___d126 == 2'd1)
	$write("");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe &&
	  IF_stage2_rg_full_5_THEN_IF_stage2_rg_stage2_6_ETC___d126 == 2'd3)
	$write("'h%h", stage2_rg_stage2[330:299], " }");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe &&
	  IF_stage2_rg_full_5_THEN_IF_stage2_rg_stage2_6_ETC___d126 != 2'd0 &&
	  IF_stage2_rg_full_5_THEN_IF_stage2_rg_stage2_6_ETC___d126 != 2'd1 &&
	  IF_stage2_rg_full_5_THEN_IF_stage2_rg_stage2_6_ETC___d126 != 2'd3)
	$write("");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe) $write("\n");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe) $write("        Bypass  to Stage1: ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe) $write("Bypass {");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe &&
	  IF_stage2_rg_full_5_THEN_IF_stage2_rg_stage2_6_ETC___d188 == 2'd0)
	$write("Rd -");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe &&
	  IF_stage2_rg_full_5_THEN_IF_stage2_rg_stage2_6_ETC___d188 != 2'd0)
	$write("Rd %0d ", x_out_bypass_rd__h7450);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe &&
	  IF_stage2_rg_full_5_THEN_IF_stage2_rg_stage2_6_ETC___d188 == 2'd0)
	$write("");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe &&
	  IF_stage2_rg_full_5_THEN_IF_stage2_rg_stage2_6_ETC___d188 == 2'd1)
	$write("-");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe &&
	  IF_stage2_rg_full_5_THEN_IF_stage2_rg_stage2_6_ETC___d188 != 2'd0 &&
	  IF_stage2_rg_full_5_THEN_IF_stage2_rg_stage2_6_ETC___d188 != 2'd1)
	$write("rd_val:%h", x_out_bypass_rd_val__h7451);
    if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_show_pipe) $write("}");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe) $write("\n");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe)
	$display("    Stage1: pc 0x%08h instr 0x%08h priv %0d",
		 imem_rg_pc,
		 x_out_data_to_stage2_instr__h13090,
		 rg_cur_priv);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe) $write("        ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full &&
	  NOT_near_mem_imem_valid_05_OR_imem_rg_pc_BITS__ETC___d498)
	$write("Output_Stage1", " BUSY pc:%h", imem_rg_pc);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full &&
	  near_mem_imem_valid_AND_NOT_imem_rg_pc_BITS_1__ETC___d665)
	$write("Output_Stage1", " NONPIPE: pc:%h", imem_rg_pc);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full &&
	  near_mem_imem_valid_AND_NOT_imem_rg_pc_BITS_1__ETC___d714)
	$write("Output_Stage1");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe && !stage1_rg_full)
	$write("Output_Stage1", " EMPTY");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full &&
	  NOT_near_mem_imem_valid_05_OR_imem_rg_pc_BITS__ETC___d498)
	$write("");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full &&
	  near_mem_imem_valid_AND_NOT_imem_rg_pc_BITS_1__ETC___d665)
	$write("");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full &&
	  near_mem_imem_valid_AND_NOT_imem_rg_pc_BITS_1__ETC___d714)
	$write(" PIPE: ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe && !stage1_rg_full) $write("");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full &&
	  NOT_near_mem_imem_valid_05_OR_imem_rg_pc_BITS__ETC___d498)
	$write("");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full &&
	  near_mem_imem_valid_AND_NOT_imem_rg_pc_BITS_1__ETC___d665)
	$write("");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full &&
	  near_mem_imem_valid_AND_NOT_imem_rg_pc_BITS_1__ETC___d513 &&
	  !near_mem$imem_exc &&
	  (IF_IF_imem_rg_pc_BITS_1_TO_0_EQ_0b0_OR_NOT_ime_ETC___d709 ||
	   IF_IF_imem_rg_pc_BITS_1_TO_0_EQ_0b0_OR_NOT_ime_ETC___d711) &&
	  IF_NOT_stage1_rg_full_03_04_OR_NOT_near_mem_im_ETC___d775 == 4'd0)
	$write("CONTROL_STRAIGHT");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full &&
	  near_mem_imem_valid_AND_NOT_imem_rg_pc_BITS_1__ETC___d513 &&
	  !near_mem$imem_exc &&
	  (IF_IF_imem_rg_pc_BITS_1_TO_0_EQ_0b0_OR_NOT_ime_ETC___d709 ||
	   IF_IF_imem_rg_pc_BITS_1_TO_0_EQ_0b0_OR_NOT_ime_ETC___d711) &&
	  IF_NOT_stage1_rg_full_03_04_OR_NOT_near_mem_im_ETC___d775 == 4'd1)
	$write("CONTROL_BRANCH");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full &&
	  near_mem_imem_valid_AND_NOT_imem_rg_pc_BITS_1__ETC___d513 &&
	  !near_mem$imem_exc &&
	  (IF_IF_imem_rg_pc_BITS_1_TO_0_EQ_0b0_OR_NOT_ime_ETC___d709 ||
	   IF_IF_imem_rg_pc_BITS_1_TO_0_EQ_0b0_OR_NOT_ime_ETC___d711) &&
	  IF_NOT_stage1_rg_full_03_04_OR_NOT_near_mem_im_ETC___d775 == 4'd2)
	$write("CONTROL_CSRR_W");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full &&
	  near_mem_imem_valid_AND_NOT_imem_rg_pc_BITS_1__ETC___d513 &&
	  !near_mem$imem_exc &&
	  (IF_IF_imem_rg_pc_BITS_1_TO_0_EQ_0b0_OR_NOT_ime_ETC___d709 ||
	   IF_IF_imem_rg_pc_BITS_1_TO_0_EQ_0b0_OR_NOT_ime_ETC___d711) &&
	  IF_NOT_stage1_rg_full_03_04_OR_NOT_near_mem_im_ETC___d775 == 4'd3)
	$write("CONTROL_CSRR_S_or_C");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full &&
	  near_mem_imem_valid_AND_NOT_imem_rg_pc_BITS_1__ETC___d513 &&
	  !near_mem$imem_exc &&
	  (IF_IF_imem_rg_pc_BITS_1_TO_0_EQ_0b0_OR_NOT_ime_ETC___d709 ||
	   IF_IF_imem_rg_pc_BITS_1_TO_0_EQ_0b0_OR_NOT_ime_ETC___d711) &&
	  IF_NOT_stage1_rg_full_03_04_OR_NOT_near_mem_im_ETC___d775 == 4'd4)
	$write("CONTROL_FENCE");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full &&
	  near_mem_imem_valid_AND_NOT_imem_rg_pc_BITS_1__ETC___d513 &&
	  !near_mem$imem_exc &&
	  (IF_IF_imem_rg_pc_BITS_1_TO_0_EQ_0b0_OR_NOT_ime_ETC___d709 ||
	   IF_IF_imem_rg_pc_BITS_1_TO_0_EQ_0b0_OR_NOT_ime_ETC___d711) &&
	  IF_NOT_stage1_rg_full_03_04_OR_NOT_near_mem_im_ETC___d775 == 4'd5)
	$write("CONTROL_FENCE_I");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full &&
	  near_mem_imem_valid_AND_NOT_imem_rg_pc_BITS_1__ETC___d513 &&
	  !near_mem$imem_exc &&
	  (IF_IF_imem_rg_pc_BITS_1_TO_0_EQ_0b0_OR_NOT_ime_ETC___d709 ||
	   IF_IF_imem_rg_pc_BITS_1_TO_0_EQ_0b0_OR_NOT_ime_ETC___d711) &&
	  IF_NOT_stage1_rg_full_03_04_OR_NOT_near_mem_im_ETC___d775 == 4'd6)
	$write("CONTROL_SFENCE_VMA");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full &&
	  near_mem_imem_valid_AND_NOT_imem_rg_pc_BITS_1__ETC___d513 &&
	  !near_mem$imem_exc &&
	  (IF_IF_imem_rg_pc_BITS_1_TO_0_EQ_0b0_OR_NOT_ime_ETC___d709 ||
	   IF_IF_imem_rg_pc_BITS_1_TO_0_EQ_0b0_OR_NOT_ime_ETC___d711) &&
	  IF_NOT_stage1_rg_full_03_04_OR_NOT_near_mem_im_ETC___d775 == 4'd7)
	$write("CONTROL_MRET");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full &&
	  near_mem_imem_valid_AND_NOT_imem_rg_pc_BITS_1__ETC___d513 &&
	  !near_mem$imem_exc &&
	  (IF_IF_imem_rg_pc_BITS_1_TO_0_EQ_0b0_OR_NOT_ime_ETC___d709 ||
	   IF_IF_imem_rg_pc_BITS_1_TO_0_EQ_0b0_OR_NOT_ime_ETC___d711) &&
	  IF_NOT_stage1_rg_full_03_04_OR_NOT_near_mem_im_ETC___d775 == 4'd8)
	$write("CONTROL_SRET");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full &&
	  near_mem_imem_valid_AND_NOT_imem_rg_pc_BITS_1__ETC___d513 &&
	  !near_mem$imem_exc &&
	  (IF_IF_imem_rg_pc_BITS_1_TO_0_EQ_0b0_OR_NOT_ime_ETC___d709 ||
	   IF_IF_imem_rg_pc_BITS_1_TO_0_EQ_0b0_OR_NOT_ime_ETC___d711) &&
	  IF_NOT_stage1_rg_full_03_04_OR_NOT_near_mem_im_ETC___d775 == 4'd9)
	$write("CONTROL_URET");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full &&
	  near_mem_imem_valid_AND_NOT_imem_rg_pc_BITS_1__ETC___d513 &&
	  !near_mem$imem_exc &&
	  (IF_IF_imem_rg_pc_BITS_1_TO_0_EQ_0b0_OR_NOT_ime_ETC___d709 ||
	   IF_IF_imem_rg_pc_BITS_1_TO_0_EQ_0b0_OR_NOT_ime_ETC___d711) &&
	  IF_NOT_stage1_rg_full_03_04_OR_NOT_near_mem_im_ETC___d775 == 4'd10)
	$write("CONTROL_WFI");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full &&
	  near_mem_imem_valid_AND_NOT_imem_rg_pc_BITS_1__ETC___d513 &&
	  NOT_near_mem_imem_exc__14_67_AND_IF_IF_imem_rg_ETC___d841)
	$write("CONTROL_TRAP");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe && !stage1_rg_full) $write("");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full &&
	  NOT_near_mem_imem_valid_05_OR_imem_rg_pc_BITS__ETC___d498)
	$write("");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full &&
	  near_mem_imem_valid_AND_NOT_imem_rg_pc_BITS_1__ETC___d665)
	$write("");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full &&
	  near_mem_imem_valid_AND_NOT_imem_rg_pc_BITS_1__ETC___d714)
	$write(" ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe && !stage1_rg_full) $write("");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full &&
	  NOT_near_mem_imem_valid_05_OR_imem_rg_pc_BITS__ETC___d498)
	$write("");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full &&
	  near_mem_imem_valid_AND_NOT_imem_rg_pc_BITS_1__ETC___d665)
	$write("");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe && !stage1_rg_full) $write("");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full &&
	  NOT_near_mem_imem_valid_05_OR_imem_rg_pc_BITS__ETC___d498)
	$write("");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full &&
	  near_mem_imem_valid_AND_NOT_imem_rg_pc_BITS_1__ETC___d665)
	$write("");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe && !stage1_rg_full) $write("");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full &&
	  NOT_near_mem_imem_valid_05_OR_imem_rg_pc_BITS__ETC___d498)
	$write("");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full &&
	  near_mem_imem_valid_AND_NOT_imem_rg_pc_BITS_1__ETC___d665)
	$write("");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe && !stage1_rg_full) $write("");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full &&
	  NOT_near_mem_imem_valid_05_OR_imem_rg_pc_BITS__ETC___d498)
	$write("");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full &&
	  near_mem_imem_valid_AND_NOT_imem_rg_pc_BITS_1__ETC___d665)
	$write("");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe && !stage1_rg_full) $write("");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full &&
	  NOT_near_mem_imem_valid_05_OR_imem_rg_pc_BITS__ETC___d498)
	$write("");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full &&
	  near_mem_imem_valid_AND_NOT_imem_rg_pc_BITS_1__ETC___d665)
	$write("");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full &&
	  near_mem_imem_valid_AND_NOT_imem_rg_pc_BITS_1__ETC___d714)
	$write("}");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe && !stage1_rg_full) $write("");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full &&
	  NOT_near_mem_imem_valid_05_OR_imem_rg_pc_BITS__ETC___d498)
	$write("");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full &&
	  near_mem_imem_valid_AND_NOT_imem_rg_pc_BITS_1__ETC___d665)
	$write("");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full &&
	  near_mem_imem_valid_AND_NOT_imem_rg_pc_BITS_1__ETC___d714)
	$write("data_to_Stage 2 {pc:%h  instr:%h  priv:%0d\n",
	       imem_rg_pc,
	       x_out_data_to_stage2_instr__h13090,
	       rg_cur_priv);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe && !stage1_rg_full) $write("");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full &&
	  NOT_near_mem_imem_valid_05_OR_imem_rg_pc_BITS__ETC___d498)
	$write("");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full &&
	  near_mem_imem_valid_AND_NOT_imem_rg_pc_BITS_1__ETC___d665)
	$write("");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full &&
	  near_mem_imem_valid_AND_NOT_imem_rg_pc_BITS_1__ETC___d714)
	$write("            op_stage2:");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe && !stage1_rg_full) $write("");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full &&
	  NOT_near_mem_imem_valid_05_OR_imem_rg_pc_BITS__ETC___d498)
	$write("");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full &&
	  near_mem_imem_valid_AND_NOT_imem_rg_pc_BITS_1__ETC___d665)
	$write("");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full &&
	  near_mem_imem_valid_AND_NOT_imem_rg_pc_BITS_1__ETC___d513 &&
	  !near_mem$imem_exc &&
	  (IF_IF_imem_rg_pc_BITS_1_TO_0_EQ_0b0_OR_NOT_ime_ETC___d709 ||
	   IF_IF_imem_rg_pc_BITS_1_TO_0_EQ_0b0_OR_NOT_ime_ETC___d711) &&
	  IF_NOT_stage1_rg_full_03_04_OR_NOT_near_mem_im_ETC___d854 == 3'd0)
	$write("OP_Stage2_ALU");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full &&
	  near_mem_imem_valid_AND_NOT_imem_rg_pc_BITS_1__ETC___d513 &&
	  !near_mem$imem_exc &&
	  (IF_IF_imem_rg_pc_BITS_1_TO_0_EQ_0b0_OR_NOT_ime_ETC___d709 ||
	   IF_IF_imem_rg_pc_BITS_1_TO_0_EQ_0b0_OR_NOT_ime_ETC___d711) &&
	  IF_NOT_stage1_rg_full_03_04_OR_NOT_near_mem_im_ETC___d854 == 3'd1)
	$write("OP_Stage2_LD");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full &&
	  near_mem_imem_valid_AND_NOT_imem_rg_pc_BITS_1__ETC___d513 &&
	  !near_mem$imem_exc &&
	  (IF_IF_imem_rg_pc_BITS_1_TO_0_EQ_0b0_OR_NOT_ime_ETC___d709 ||
	   IF_IF_imem_rg_pc_BITS_1_TO_0_EQ_0b0_OR_NOT_ime_ETC___d711) &&
	  IF_NOT_stage1_rg_full_03_04_OR_NOT_near_mem_im_ETC___d854 == 3'd2)
	$write("OP_Stage2_ST");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full &&
	  near_mem_imem_valid_AND_NOT_imem_rg_pc_BITS_1__ETC___d513 &&
	  !near_mem$imem_exc &&
	  (IF_IF_imem_rg_pc_BITS_1_TO_0_EQ_0b0_OR_NOT_ime_ETC___d709 ||
	   IF_IF_imem_rg_pc_BITS_1_TO_0_EQ_0b0_OR_NOT_ime_ETC___d711) &&
	  IF_NOT_stage1_rg_full_03_04_OR_NOT_near_mem_im_ETC___d854 == 3'd3)
	$write("OP_Stage2_M");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full &&
	  near_mem_imem_valid_AND_NOT_imem_rg_pc_BITS_1__ETC___d513 &&
	  NOT_near_mem_imem_exc__14_67_AND_IF_IF_imem_rg_ETC___d878)
	$write("OP_Stage2_AMO");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe && !stage1_rg_full) $write("");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full &&
	  NOT_near_mem_imem_valid_05_OR_imem_rg_pc_BITS__ETC___d498)
	$write("");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full &&
	  near_mem_imem_valid_AND_NOT_imem_rg_pc_BITS_1__ETC___d665)
	$write("");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full &&
	  near_mem_imem_valid_AND_NOT_imem_rg_pc_BITS_1__ETC___d714)
	$write("  rd:%0d\n", x_out_data_to_stage2_rd__h13092);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe && !stage1_rg_full) $write("");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full &&
	  NOT_near_mem_imem_valid_05_OR_imem_rg_pc_BITS__ETC___d498)
	$write("");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full &&
	  near_mem_imem_valid_AND_NOT_imem_rg_pc_BITS_1__ETC___d665)
	$write("");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full &&
	  near_mem_imem_valid_AND_NOT_imem_rg_pc_BITS_1__ETC___d714)
	$write("            addr:%h  val1:%h  val2:%h}",
	       x_out_data_to_stage2_addr__h13093,
	       x_out_data_to_stage2_val1__h13094,
	       x_out_data_to_stage2_val2__h13095);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe && !stage1_rg_full) $write("");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full &&
	  NOT_near_mem_imem_valid_05_OR_imem_rg_pc_BITS__ETC___d498)
	$write("");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full &&
	  near_mem_imem_valid_AND_NOT_imem_rg_pc_BITS_1__ETC___d665)
	$write(" ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full &&
	  near_mem_imem_valid_AND_NOT_imem_rg_pc_BITS_1__ETC___d714)
	$write("");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe && !stage1_rg_full) $write("");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full &&
	  NOT_near_mem_imem_valid_05_OR_imem_rg_pc_BITS__ETC___d498)
	$write("");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full &&
	  near_mem_imem_valid_AND_NOT_imem_rg_pc_BITS_1__ETC___d513 &&
	  near_mem_imem_exc__14_OR_IF_IF_imem_rg_pc_BITS_ETC___d978)
	$write("CONTROL_STRAIGHT");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full &&
	  near_mem_imem_valid_AND_NOT_imem_rg_pc_BITS_1__ETC___d513 &&
	  near_mem_imem_exc__14_OR_IF_IF_imem_rg_pc_BITS_ETC___d981)
	$write("CONTROL_BRANCH");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full &&
	  near_mem_imem_valid_AND_NOT_imem_rg_pc_BITS_1__ETC___d513 &&
	  near_mem_imem_exc__14_OR_IF_IF_imem_rg_pc_BITS_ETC___d984)
	$write("CONTROL_CSRR_W");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full &&
	  near_mem_imem_valid_AND_NOT_imem_rg_pc_BITS_1__ETC___d513 &&
	  near_mem_imem_exc__14_OR_IF_IF_imem_rg_pc_BITS_ETC___d987)
	$write("CONTROL_CSRR_S_or_C");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full &&
	  near_mem_imem_valid_AND_NOT_imem_rg_pc_BITS_1__ETC___d513 &&
	  near_mem_imem_exc__14_OR_IF_IF_imem_rg_pc_BITS_ETC___d990)
	$write("CONTROL_FENCE");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full &&
	  near_mem_imem_valid_AND_NOT_imem_rg_pc_BITS_1__ETC___d513 &&
	  near_mem_imem_exc__14_OR_IF_IF_imem_rg_pc_BITS_ETC___d993)
	$write("CONTROL_FENCE_I");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full &&
	  near_mem_imem_valid_AND_NOT_imem_rg_pc_BITS_1__ETC___d513 &&
	  near_mem_imem_exc__14_OR_IF_IF_imem_rg_pc_BITS_ETC___d996)
	$write("CONTROL_SFENCE_VMA");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full &&
	  near_mem_imem_valid_AND_NOT_imem_rg_pc_BITS_1__ETC___d513 &&
	  near_mem_imem_exc__14_OR_IF_IF_imem_rg_pc_BITS_ETC___d999)
	$write("CONTROL_MRET");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full &&
	  near_mem_imem_valid_AND_NOT_imem_rg_pc_BITS_1__ETC___d513 &&
	  near_mem_imem_exc__14_OR_IF_IF_imem_rg_pc_BITS_ETC___d1002)
	$write("CONTROL_SRET");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full &&
	  near_mem_imem_valid_AND_NOT_imem_rg_pc_BITS_1__ETC___d513 &&
	  near_mem_imem_exc__14_OR_IF_IF_imem_rg_pc_BITS_ETC___d1005)
	$write("CONTROL_URET");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full &&
	  near_mem_imem_valid_AND_NOT_imem_rg_pc_BITS_1__ETC___d513 &&
	  near_mem_imem_exc__14_OR_IF_IF_imem_rg_pc_BITS_ETC___d1008)
	$write("CONTROL_WFI");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full &&
	  near_mem_imem_valid_AND_NOT_imem_rg_pc_BITS_1__ETC___d513 &&
	  near_mem_imem_exc__14_OR_IF_IF_imem_rg_pc_BITS_ETC___d1011)
	$write("CONTROL_TRAP");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full &&
	  near_mem_imem_valid_AND_NOT_imem_rg_pc_BITS_1__ETC___d714)
	$write("");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe && !stage1_rg_full) $write("");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full &&
	  NOT_near_mem_imem_valid_05_OR_imem_rg_pc_BITS__ETC___d498)
	$write("");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full &&
	  near_mem_imem_valid_AND_NOT_imem_rg_pc_BITS_1__ETC___d665)
	$write(" ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full &&
	  near_mem_imem_valid_AND_NOT_imem_rg_pc_BITS_1__ETC___d714)
	$write("");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe && !stage1_rg_full) $write("");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full &&
	  NOT_near_mem_imem_valid_05_OR_imem_rg_pc_BITS__ETC___d498)
	$write("");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full &&
	  near_mem_imem_valid_AND_NOT_imem_rg_pc_BITS_1__ETC___d665)
	$write("Trap_Info { ", "epc: ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full &&
	  near_mem_imem_valid_AND_NOT_imem_rg_pc_BITS_1__ETC___d714)
	$write("");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe && !stage1_rg_full) $write("");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full &&
	  NOT_near_mem_imem_valid_05_OR_imem_rg_pc_BITS__ETC___d498)
	$write("");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full &&
	  near_mem_imem_valid_AND_NOT_imem_rg_pc_BITS_1__ETC___d665)
	$write("'h%h", imem_rg_pc);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full &&
	  near_mem_imem_valid_AND_NOT_imem_rg_pc_BITS_1__ETC___d714)
	$write("");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe && !stage1_rg_full) $write("");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full &&
	  NOT_near_mem_imem_valid_05_OR_imem_rg_pc_BITS__ETC___d498)
	$write("");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full &&
	  near_mem_imem_valid_AND_NOT_imem_rg_pc_BITS_1__ETC___d665)
	$write(", ", "exc_code: ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full &&
	  near_mem_imem_valid_AND_NOT_imem_rg_pc_BITS_1__ETC___d714)
	$write("");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe && !stage1_rg_full) $write("");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full &&
	  NOT_near_mem_imem_valid_05_OR_imem_rg_pc_BITS__ETC___d498)
	$write("");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full &&
	  near_mem_imem_valid_AND_NOT_imem_rg_pc_BITS_1__ETC___d665)
	$write("'h%h", x_out_trap_info_exc_code__h14836);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full &&
	  near_mem_imem_valid_AND_NOT_imem_rg_pc_BITS_1__ETC___d714)
	$write("");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe && !stage1_rg_full) $write("");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full &&
	  NOT_near_mem_imem_valid_05_OR_imem_rg_pc_BITS__ETC___d498)
	$write("");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full &&
	  near_mem_imem_valid_AND_NOT_imem_rg_pc_BITS_1__ETC___d665)
	$write(", ", "tval: ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full &&
	  near_mem_imem_valid_AND_NOT_imem_rg_pc_BITS_1__ETC___d714)
	$write("");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe && !stage1_rg_full) $write("");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full &&
	  NOT_near_mem_imem_valid_05_OR_imem_rg_pc_BITS__ETC___d498)
	$write("");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full &&
	  near_mem_imem_valid_AND_NOT_imem_rg_pc_BITS_1__ETC___d665)
	$write("'h%h", value__h14885, " }");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full &&
	  near_mem_imem_valid_AND_NOT_imem_rg_pc_BITS_1__ETC___d714)
	$write("");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe && !stage1_rg_full) $write("");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full &&
	  NOT_near_mem_imem_valid_05_OR_imem_rg_pc_BITS__ETC___d498)
	$write("");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe && !stage1_rg_full) $write("");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe) $write("\n");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe) $display("----------------");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_stage1_mip_cmd &&
	  NOT_IF_csr_regfile_read_csr_minstret__7_ULT_cf_ETC___d43)
	$display("%0d: %m.rl_stage1_mip_cmd: MIP new 0x%0h, old 0x%0h",
		 csr_regfile$read_csr_mcycle,
		 csr_regfile$csr_mip_read,
		 rg_prev_mip);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_stage1_SFENCE_VMA &&
	  NOT_IF_csr_regfile_read_csr_minstret__7_ULT_cf_ETC___d43)
	$display("%0d: %m.rl_stage1_SFENCE_VMA", csr_regfile$read_csr_mcycle);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_stage1_SFENCE_VMA && cur_verbosity__h3490 == 4'd1)
	$display("instret:%0d  PC:0x%0h  instr:0x%0h  priv:%0d",
		 csr_regfile$read_csr_minstret,
		 imem_rg_pc,
		 x_out_data_to_stage2_instr__h13090,
		 rg_cur_priv);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_stage1_SFENCE_VMA &&
	  NOT_IF_csr_regfile_read_csr_minstret__7_ULT_cf_ETC___d43)
	$display("%0d: %m.rl_stage1_SFENCE_VMA", csr_regfile$read_csr_mcycle);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_debug_run_redundant &&
	  NOT_IF_csr_regfile_read_csr_minstret__7_ULT_cf_ETC___d43)
	$display("%0d: %m.rl_debug_run_redundant",
		 csr_regfile$read_csr_mcycle);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_debug_run_redundant)
	$display("%0d: %m.debug_run_redundant: CPU already running.",
		 csr_regfile$read_csr_mcycle);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_debug_halt_redundant &&
	  NOT_IF_csr_regfile_read_csr_minstret__7_ULT_cf_ETC___d43)
	$display("%0d: %m.rl_debug_halt_redundant",
		 csr_regfile$read_csr_mcycle);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_debug_halt_redundant)
	$display("%0d: %m.rl_debug_halt_redundant: CPU already halted.",
		 csr_regfile$read_csr_mcycle);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_debug_halt_redundant) $write("    state = ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_debug_halt_redundant && rg_state == 4'd0)
	$write("CPU_RESET1");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_debug_halt_redundant && rg_state == 4'd1)
	$write("CPU_RESET2");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_debug_halt_redundant && rg_state == 4'd2)
	$write("CPU_GDB_PAUSING");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_debug_halt_redundant && rg_state == 4'd3)
	$write("CPU_DEBUG_MODE");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_debug_halt_redundant && rg_state == 4'd4)
	$write("CPU_RUNNING");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_debug_halt_redundant && rg_state == 4'd5)
	$write("CPU_TRAP");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_debug_halt_redundant && rg_state == 4'd6)
	$write("CPU_START_TRAP_HANDLER");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_debug_halt_redundant && rg_state == 4'd7)
	$write("CPU_CSRRW_2");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_debug_halt_redundant && rg_state == 4'd8)
	$write("CPU_CSRR_S_or_C_2");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_debug_halt_redundant && rg_state == 4'd9)
	$write("CPU_CSRRX_RESTART");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_debug_halt_redundant && rg_state == 4'd10)
	$write("CPU_FENCE_I");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_debug_halt_redundant && rg_state == 4'd11)
	$write("CPU_FENCE");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_debug_halt_redundant && rg_state == 4'd12)
	$write("CPU_SFENCE_VMA");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_debug_halt_redundant && rg_state != 4'd0 &&
	  rg_state != 4'd1 &&
	  rg_state != 4'd2 &&
	  rg_state != 4'd3 &&
	  rg_state != 4'd4 &&
	  rg_state != 4'd5 &&
	  rg_state != 4'd6 &&
	  rg_state != 4'd7 &&
	  rg_state != 4'd8 &&
	  rg_state != 4'd9 &&
	  rg_state != 4'd10 &&
	  rg_state != 4'd11 &&
	  rg_state != 4'd12)
	$write("CPU_WFI_PAUSED");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_debug_halt_redundant) $write("\n");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_debug_read_gpr &&
	  NOT_IF_csr_regfile_read_csr_minstret__7_ULT_cf_ETC___d43)
	$display("%0d: %m.rl_debug_read_gpr: reg %0d => 0x%0h",
		 csr_regfile$read_csr_mcycle,
		 f_gpr_reqs$D_OUT[36:32],
		 gpr_regfile$read_rs1_port2);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_debug_write_gpr &&
	  NOT_IF_csr_regfile_read_csr_minstret__7_ULT_cf_ETC___d43)
	$display("%0d: %m.rl_debug_write_gpr: reg %0d <= 0x%0h",
		 csr_regfile$read_csr_mcycle,
		 f_gpr_reqs$D_OUT[36:32],
		 f_gpr_reqs$D_OUT[31:0]);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_debug_gpr_access_busy &&
	  NOT_IF_csr_regfile_read_csr_minstret__7_ULT_cf_ETC___d43)
	$display("%0d: %m.rl_debug_gpr_access_busy",
		 csr_regfile$read_csr_mcycle);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_debug_read_csr &&
	  NOT_IF_csr_regfile_read_csr_minstret__7_ULT_cf_ETC___d43)
	$display("%0d: %m.rl_debug_read_csr: csr %0d => 0x%0h",
		 csr_regfile$read_csr_mcycle,
		 f_csr_reqs$D_OUT[43:32],
		 csr_regfile$read_csr_port2[31:0]);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_debug_run &&
	  NOT_IF_csr_regfile_read_csr_minstret__7_ULT_cf_ETC___d43)
	$display("%0d: %m.rl_debug_run", csr_regfile$read_csr_mcycle);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_debug_run &&
	  NOT_IF_csr_regfile_read_csr_minstret__7_ULT_cf_ETC___d43)
	$display("    CPU_Stage1.enq: 0x%08h", csr_regfile$read_dpc);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_debug_run)
	$display("%0d: %m.rl_debug_run: restart at PC = 0x%0h",
		 csr_regfile$read_csr_mcycle,
		 csr_regfile$read_dpc);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_debug_run &&
	  NOT_IF_csr_regfile_read_csr_minstret__7_ULT_cf_ETC___d43)
	$display("%0d: %m.rl_debug_run: 'run' from dpc 0x%0h",
		 csr_regfile$read_csr_mcycle,
		 csr_regfile$read_dpc);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_debug_write_csr &&
	  NOT_IF_csr_regfile_read_csr_minstret__7_ULT_cf_ETC___d43)
	$display("%0d: %m.rl_debug_write_csr: csr 0x%0h 0x%0h <= 0x%0h",
		 csr_regfile$read_csr_mcycle,
		 f_csr_reqs$D_OUT[43:32],
		 f_csr_reqs$D_OUT[31:0],
		 csr_regfile$mav_csr_write);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_debug_csr_access_busy &&
	  NOT_IF_csr_regfile_read_csr_minstret__7_ULT_cf_ETC___d43)
	$display("%0d: %m.rl_debug_csr_access_busy",
		 csr_regfile$read_csr_mcycle);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_stage1_trap &&
	  NOT_IF_csr_regfile_read_csr_minstret__7_ULT_cf_ETC___d43)
	$display("%0d: %m.rl_stage1_trap", csr_regfile$read_csr_mcycle);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_stage1_CSRR_W &&
	  NOT_IF_csr_regfile_read_csr_minstret__7_ULT_cf_ETC___d43)
	$display("%0d: %m.rl_stage1_CSRR_W", csr_regfile$read_csr_mcycle);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_stage1_CSRR_S_or_C &&
	  NOT_IF_csr_regfile_read_csr_minstret__7_ULT_cf_ETC___d43)
	$display("%0d: %m.rl_stage1_CSRR_S_or_C",
		 csr_regfile$read_csr_mcycle);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_stage1_xRET &&
	  NOT_IF_csr_regfile_read_csr_minstret__7_ULT_cf_ETC___d43)
	$display("%0d: %m.rl_stage1_xRET", csr_regfile$read_csr_mcycle);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_stage1_xRET && cur_verbosity__h3490 == 4'd1)
	$display("instret:%0d  PC:0x%0h  instr:0x%0h  priv:%0d",
		 csr_regfile$read_csr_minstret,
		 imem_rg_pc,
		 x_out_data_to_stage2_instr__h13090,
		 rg_cur_priv);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_stage1_xRET && cur_verbosity__h3490 != 4'd0)
	$display("    xRET: next_pc:0x%0h  new mstatus:0x%0h  new priv:%0d",
		 csr_regfile$csr_ret_actions[65:34],
		 csr_regfile$csr_ret_actions[31:0],
		 csr_regfile$csr_ret_actions[33:32]);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_stage1_FENCE_I &&
	  NOT_IF_csr_regfile_read_csr_minstret__7_ULT_cf_ETC___d43)
	$display("%0d: %m.rl_stage1_FENCE_I", csr_regfile$read_csr_mcycle);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_stage1_FENCE_I && cur_verbosity__h3490 == 4'd1)
	$display("instret:%0d  PC:0x%0h  instr:0x%0h  priv:%0d",
		 csr_regfile$read_csr_minstret,
		 imem_rg_pc,
		 x_out_data_to_stage2_instr__h13090,
		 rg_cur_priv);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_stage1_FENCE_I &&
	  NOT_IF_csr_regfile_read_csr_minstret__7_ULT_cf_ETC___d43)
	$display("%0d: %m.rl_stage1_FENCE_I", csr_regfile$read_csr_mcycle);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_stage1_FENCE &&
	  NOT_IF_csr_regfile_read_csr_minstret__7_ULT_cf_ETC___d43)
	$display("%0d: %m.rl_stage1_FENCE", csr_regfile$read_csr_mcycle);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_stage1_FENCE && cur_verbosity__h3490 == 4'd1)
	$display("instret:%0d  PC:0x%0h  instr:0x%0h  priv:%0d",
		 csr_regfile$read_csr_minstret,
		 imem_rg_pc,
		 x_out_data_to_stage2_instr__h13090,
		 rg_cur_priv);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_stage1_FENCE &&
	  NOT_IF_csr_regfile_read_csr_minstret__7_ULT_cf_ETC___d43)
	$display("%0d: %m.rl_stage1_FENCE", csr_regfile$read_csr_mcycle);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_stage1_WFI &&
	  NOT_IF_csr_regfile_read_csr_minstret__7_ULT_cf_ETC___d43)
	$display("%0d: %m.rl_stage1_WFI", csr_regfile$read_csr_mcycle);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_stage1_WFI && cur_verbosity__h3490 == 4'd1)
	$display("instret:%0d  PC:0x%0h  instr:0x%0h  priv:%0d",
		 csr_regfile$read_csr_minstret,
		 imem_rg_pc,
		 x_out_data_to_stage2_instr__h13090,
		 rg_cur_priv);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_stage1_WFI &&
	  NOT_IF_csr_regfile_read_csr_minstret__7_ULT_cf_ETC___d43)
	$display("    CPU.rl_stage1_WFI");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_WFI_resume &&
	  NOT_IF_csr_regfile_read_csr_minstret__7_ULT_cf_ETC___d43)
	$display("%0d: %m.rl_WFI_resume", csr_regfile$read_csr_mcycle);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_WFI_resume && cur_verbosity__h3490 != 4'd0)
	$display("    WFI resume");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_WFI_resume &&
	  NOT_IF_csr_regfile_read_csr_minstret__7_ULT_cf_ETC___d43)
	$display("    CPU_Stage1.enq: 0x%08h", rg_next_pc);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_trap_BREAK_to_Debug_Mode &&
	  NOT_IF_csr_regfile_read_csr_minstret__7_ULT_cf_ETC___d43)
	$display("%0d: %m.rl_trap_BREAK_to_Debug_Mode",
		 csr_regfile$read_csr_mcycle);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_trap_BREAK_to_Debug_Mode)
	$display("%0d: %m.rl_trap_BREAK_to_Debug_Mode: PC 0x%08h instr 0x%08h",
		 csr_regfile$read_csr_mcycle,
		 imem_rg_pc,
		 x_out_data_to_stage2_instr__h13090);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_trap_BREAK_to_Debug_Mode &&
	  NOT_IF_csr_regfile_read_csr_minstret__7_ULT_cf_ETC___d43)
	$display("    Flushing caches");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_BREAK_cache_flush_finish &&
	  NOT_IF_csr_regfile_read_csr_minstret__7_ULT_cf_ETC___d43)
	$display("%0d: %m.rl_BREAK_cache_flush_finish",
		 csr_regfile$read_csr_mcycle);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_stage1_stop &&
	  NOT_IF_csr_regfile_read_csr_minstret__7_ULT_cf_ETC___d43)
	$display("%0d: %m.rl_stage1_stop", csr_regfile$read_csr_mcycle);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_stage1_stop && rg_stop_req)
	$display("%0d: %m.rl_stage1_stop: Stop for debugger. minstret %0d priv %0d PC 0x%0h instr 0x%0h",
		 csr_regfile$read_csr_mcycle,
		 csr_regfile$read_csr_minstret,
		 rg_cur_priv,
		 imem_rg_pc,
		 x_out_data_to_stage2_instr__h13090);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_stage1_stop && rg_stop_req)
	$display("CPI: %0d.%0d = (%0d/%0d) since last 'continue'",
		 cpi__h29736,
		 cpifrac__h29737,
		 delta_CPI_cycles__h29732,
		 _theResult____h29734);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_stage1_stop && !rg_stop_req)
	$display("%0d: %m.rl_stage1_stop: Stop after single-step. PC = 0x%08h",
		 csr_regfile$read_csr_mcycle,
		 imem_rg_pc);
    if (WILL_FIRE_RL_imem_rl_assert_fail)
      begin
        v__h2309 = $stime;
	#0;
      end
    v__h2303 = v__h2309 / 32'd10;
    if (WILL_FIRE_RL_imem_rl_assert_fail)
      $display("%0d: ERROR: CPU_Fetch_C: imem32.is_i32_not_i16 is False",
	       v__h2303);
    if (WILL_FIRE_RL_imem_rl_assert_fail) $finish(32'd1);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_reset_complete && rg_run_on_reset &&
	  NOT_IF_csr_regfile_read_csr_minstret__7_ULT_cf_ETC___d43)
	$display("    CPU_Stage1.enq: 0x%08h",
		 soc_map$m_pc_reset_value[31:0]);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_reset_complete && rg_run_on_reset)
	$display("%0d: %m.rl_reset_complete: restart at PC = 0x%0h",
		 csr_regfile$read_csr_mcycle,
		 soc_map$m_pc_reset_value[31:0]);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_reset_complete && !rg_run_on_reset)
	$display("%0d: %m.rl_reset_complete: entering DEBUG_MODE",
		 csr_regfile$read_csr_mcycle);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_pipe &&
	  NOT_IF_csr_regfile_read_csr_minstret__7_ULT_cf_ETC___d43)
	$display("%0d: %m.rl_pipe", csr_regfile$read_csr_mcycle);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_pipe && stage3_rg_full && stage3_rg_stage3[37] &&
	  NOT_IF_csr_regfile_read_csr_minstret__7_ULT_cf_ETC___d43)
	$display("    S3.fa_deq: write GRd 0x%0h, rd_val 0x%0h",
		 stage3_rg_stage3[36:32],
		 stage3_rg_stage3[31:0]);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_pipe &&
	  IF_stage2_rg_full_5_THEN_IF_stage2_rg_stage2_6_ETC___d126 == 2'd2 &&
	  NOT_IF_csr_regfile_read_csr_minstret__7_ULT_cf_ETC___d43)
	$write("    S3.enq: ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_pipe &&
	  IF_stage2_rg_full_5_THEN_IF_stage2_rg_stage2_6_ETC___d126 == 2'd2 &&
	  NOT_IF_csr_regfile_read_csr_minstret__7_ULT_cf_ETC___d43)
	$write("data_to_Stage3 {pc:%h  instr:%h  priv:%0d\n",
	       stage2_rg_stage2[402:371],
	       stage2_rg_stage2[370:339],
	       stage2_rg_stage2[404:403]);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_pipe &&
	  IF_stage2_rg_full_5_THEN_IF_stage2_rg_stage2_6_ETC___d126 == 2'd2 &&
	  NOT_IF_csr_regfile_read_csr_minstret__7_ULT_cf_ETC___d43)
	$write("        rd_valid:");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_pipe &&
	  IF_stage2_rg_full_5_THEN_IF_stage2_rg_stage2_6_ETC___d126 == 2'd2 &&
	  NOT_IF_csr_regfile_read_csr_minstret__7_ULT_cf_ETC___d43 &&
	  stage2_rg_stage2[338:336] != 3'd0 &&
	  IF_stage2_rg_stage2_6_BITS_338_TO_336_7_EQ_1_9_ETC___d140)
	$write("False");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_pipe &&
	  IF_stage2_rg_full_5_THEN_IF_stage2_rg_stage2_6_ETC___d126 == 2'd2 &&
	  NOT_IF_csr_regfile_read_csr_minstret__7_ULT_cf_ETC___d43 &&
	  (stage2_rg_stage2[338:336] == 3'd0 ||
	   IF_stage2_rg_stage2_6_BITS_338_TO_336_7_EQ_1_9_ETC___d149))
	$write("True");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_pipe &&
	  IF_stage2_rg_full_5_THEN_IF_stage2_rg_stage2_6_ETC___d126 == 2'd2 &&
	  NOT_IF_csr_regfile_read_csr_minstret__7_ULT_cf_ETC___d43)
	$write("  grd:%0d  rd_val:%h\n",
	       x_out_data_to_stage3_rd__h7110,
	       x_out_data_to_stage3_rd_val__h7111);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_pipe &&
	  IF_stage2_rg_full_5_THEN_IF_stage2_rg_stage2_6_ETC___d126 == 2'd2 &&
	  NOT_IF_csr_regfile_read_csr_minstret__7_ULT_cf_ETC___d43)
	$write("\n");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_pipe &&
	  IF_stage2_rg_full_5_THEN_IF_stage2_rg_stage2_6_ETC___d126 == 2'd2 &&
	  cur_verbosity__h3490 == 4'd1)
	$display("instret:%0d  PC:0x%0h  instr:0x%0h  priv:%0d",
		 csr_regfile$read_csr_minstret,
		 stage2_rg_stage2[402:371],
		 stage2_rg_stage2[370:339],
		 rg_cur_priv);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_pipe &&
	  near_mem_imem_exc__14_OR_IF_IF_imem_rg_pc_BITS_ETC___d1305)
	$write("    CPU_Stage2.enq (Data_Stage1_to_Stage2) ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_pipe &&
	  near_mem_imem_exc__14_OR_IF_IF_imem_rg_pc_BITS_ETC___d1305)
	$write("data_to_Stage 2 {pc:%h  instr:%h  priv:%0d\n",
	       imem_rg_pc,
	       x_out_data_to_stage2_instr__h13090,
	       rg_cur_priv);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_pipe &&
	  near_mem_imem_exc__14_OR_IF_IF_imem_rg_pc_BITS_ETC___d1305)
	$write("            op_stage2:");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_pipe &&
	  near_mem_imem_exc__14_OR_IF_IF_imem_rg_pc_BITS_ETC___d1307)
	$write("OP_Stage2_ALU");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_pipe &&
	  near_mem_imem_exc__14_OR_IF_IF_imem_rg_pc_BITS_ETC___d1309)
	$write("OP_Stage2_LD");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_pipe &&
	  near_mem_imem_exc__14_OR_IF_IF_imem_rg_pc_BITS_ETC___d1311)
	$write("OP_Stage2_ST");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_pipe &&
	  near_mem_imem_exc__14_OR_IF_IF_imem_rg_pc_BITS_ETC___d1313)
	$write("OP_Stage2_M");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_pipe &&
	  near_mem_imem_exc__14_OR_IF_IF_imem_rg_pc_BITS_ETC___d1315)
	$write("OP_Stage2_AMO");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_pipe &&
	  near_mem_imem_exc__14_OR_IF_IF_imem_rg_pc_BITS_ETC___d1305)
	$write("  rd:%0d\n", x_out_data_to_stage2_rd__h13092);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_pipe &&
	  near_mem_imem_exc__14_OR_IF_IF_imem_rg_pc_BITS_ETC___d1305)
	$write("            addr:%h  val1:%h  val2:%h}",
	       x_out_data_to_stage2_addr__h13093,
	       x_out_data_to_stage2_val1__h13094,
	       x_out_data_to_stage2_val2__h13095);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_pipe &&
	  near_mem_imem_exc__14_OR_IF_IF_imem_rg_pc_BITS_ETC___d1305)
	$write("\n");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_pipe &&
	  NOT_stage1_rg_full_03_04_OR_NOT_near_mem_imem__ETC___d1324 &&
	  NOT_IF_csr_regfile_read_csr_minstret__7_ULT_cf_ETC___d43)
	$display("    CPU_Stage1.enq: 0x%08h", x_out_next_pc__h13057);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_debug_halt &&
	  NOT_IF_csr_regfile_read_csr_minstret__7_ULT_cf_ETC___d43)
	$display("%0d: %m.rl_debug_halt", csr_regfile$read_csr_mcycle);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_debug_halt &&
	  NOT_IF_csr_regfile_read_csr_minstret__7_ULT_cf_ETC___d43)
	$display("%0d: %m.rl_debug_halt", csr_regfile$read_csr_mcycle);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_stage2_nonpipe &&
	  NOT_IF_csr_regfile_read_csr_minstret__7_ULT_cf_ETC___d43)
	$display("%0d: %m.rl_stage2_nonpipe", csr_regfile$read_csr_mcycle);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_trap && cur_verbosity__h3490 == 4'd1)
	$display("instret:%0d  PC:0x%0h  instr:0x%0h  priv:%0d",
		 csr_regfile$read_csr_minstret,
		 rg_trap_info[67:36],
		 rg_trap_instr,
		 rg_cur_priv);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_trap && cur_verbosity__h3490 != 4'd0)
	$display("    mcause:0x%0h  epc 0x%0h  tval:0x%0h  next_pc 0x%0h, new_priv %0d new_mstatus 0x%0h",
		 csr_regfile$csr_trap_actions[33:2],
		 rg_trap_info[67:36],
		 rg_trap_info[31:0],
		 csr_regfile$csr_trap_actions[97:66],
		 csr_regfile$csr_trap_actions[1:0],
		 csr_regfile$csr_trap_actions[65:34]);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_stage1_CSRR_W_2 &&
	  NOT_IF_csr_regfile_read_csr_minstret__7_ULT_cf_ETC___d43)
	$display("%0d: %m.rl_stage1_CSRR_W_2", csr_regfile$read_csr_mcycle);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_stage1_CSRR_W_2 && csr_regfile$access_permitted_1 &&
	  cur_verbosity__h3490 == 4'd1)
	$display("instret:%0d  PC:0x%0h  instr:0x%0h  priv:%0d",
		 csr_regfile$read_csr_minstret,
		 rg_csr_pc,
		 rg_trap_instr,
		 rg_cur_priv);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_stage1_CSRR_W_2 && csr_regfile$access_permitted_1 &&
	  NOT_IF_csr_regfile_read_csr_minstret__7_ULT_cf_ETC___d43)
	$display("    S1: write CSRRW/CSRRWI Rs1 %0d Rs1_val 0x%0h csr 0x%0h csr_val 0x%0h Rd %0d",
		 rg_trap_instr[19:15],
		 rs1_val__h22206,
		 rg_trap_instr[31:20],
		 csr_regfile$read_csr[31:0],
		 rg_trap_instr[11:7]);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_stage1_CSRR_W_2 &&
	  !csr_regfile$access_permitted_1 &&
	  NOT_IF_csr_regfile_read_csr_minstret__7_ULT_cf_ETC___d43)
	$display("    rl_stage1_CSRR_W: Trap on CSR permissions: Rs1 %0d Rs1_val 0x%0h csr 0x%0h Rd %0d",
		 rg_trap_instr[19:15],
		 rs1_val__h22206,
		 rg_trap_instr[31:20],
		 rg_trap_instr[11:7]);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_stage1_CSRR_S_or_C_2 &&
	  NOT_IF_csr_regfile_read_csr_minstret__7_ULT_cf_ETC___d43)
	$display("%0d: %m.rl_stage1_CSRR_S_or_C_2",
		 csr_regfile$read_csr_mcycle);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_stage1_CSRR_S_or_C_2 &&
	  csr_regfile$access_permitted_2 &&
	  cur_verbosity__h3490 == 4'd1)
	$display("instret:%0d  PC:0x%0h  instr:0x%0h  priv:%0d",
		 csr_regfile$read_csr_minstret,
		 rg_csr_pc,
		 rg_trap_instr,
		 rg_cur_priv);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_stage1_CSRR_S_or_C_2 &&
	  csr_regfile$access_permitted_2 &&
	  NOT_IF_csr_regfile_read_csr_minstret__7_ULT_cf_ETC___d43)
	$display("    S1: write CSRR_S_or_C: Rs1 %0d Rs1_val 0x%0h csr 0x%0h csr_val 0x%0h Rd %0d",
		 rg_trap_instr[19:15],
		 rs1_val__h23025,
		 rg_trap_instr[31:20],
		 csr_regfile$read_csr[31:0],
		 rg_trap_instr[11:7]);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_stage1_CSRR_S_or_C_2 &&
	  !csr_regfile$access_permitted_2 &&
	  NOT_IF_csr_regfile_read_csr_minstret__7_ULT_cf_ETC___d43)
	$display("    rl_stage1_CSRR_S_or_C: Trap on CSR permissions: Rs1 %0d Rs1_val 0x%0h csr 0x%0h Rd %0d",
		 rg_trap_instr[19:15],
		 rs1_val__h23025,
		 rg_trap_instr[31:20],
		 rg_trap_instr[11:7]);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_stage1_restart_after_csrrx &&
	  NOT_IF_csr_regfile_read_csr_minstret__7_ULT_cf_ETC___d43)
	$display("    CPU_Stage1.enq: 0x%08h", x_out_next_pc__h13057);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_stage1_restart_after_csrrx &&
	  NOT_IF_csr_regfile_read_csr_minstret__7_ULT_cf_ETC___d43)
	$display("%0d: rl_stage1_restart_after_csrrx: minstret:%0d  pc:%0x  cur_priv:%0d",
		 csr_regfile$read_csr_mcycle,
		 csr_regfile$read_csr_minstret,
		 x_out_next_pc__h13057,
		 rg_cur_priv);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_finish_FENCE_I &&
	  NOT_IF_csr_regfile_read_csr_minstret__7_ULT_cf_ETC___d43)
	$display("%0d: %m.rl_finish_FENCE_I", csr_regfile$read_csr_mcycle);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_finish_FENCE_I &&
	  NOT_IF_csr_regfile_read_csr_minstret__7_ULT_cf_ETC___d43)
	$display("    CPU_Stage1.enq: 0x%08h", rg_next_pc);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_finish_FENCE_I &&
	  NOT_IF_csr_regfile_read_csr_minstret__7_ULT_cf_ETC___d43)
	$display("    CPU.rl_finish_FENCE_I");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_finish_FENCE &&
	  NOT_IF_csr_regfile_read_csr_minstret__7_ULT_cf_ETC___d43)
	$display("%0d: %m.rl_finish_FENCE", csr_regfile$read_csr_mcycle);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_finish_FENCE &&
	  NOT_IF_csr_regfile_read_csr_minstret__7_ULT_cf_ETC___d43)
	$display("    CPU_Stage1.enq: 0x%08h", rg_next_pc);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_finish_FENCE &&
	  NOT_IF_csr_regfile_read_csr_minstret__7_ULT_cf_ETC___d43)
	$display("    CPU.rl_finish_FENCE");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_finish_SFENCE_VMA &&
	  NOT_IF_csr_regfile_read_csr_minstret__7_ULT_cf_ETC___d43)
	$display("%0d: %m.rl_finish_SFENCE_VMA", csr_regfile$read_csr_mcycle);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_finish_SFENCE_VMA &&
	  NOT_IF_csr_regfile_read_csr_minstret__7_ULT_cf_ETC___d43)
	$display("    CPU_Stage1.enq: 0x%08h", rg_next_pc);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_finish_SFENCE_VMA &&
	  NOT_IF_csr_regfile_read_csr_minstret__7_ULT_cf_ETC___d43)
	$display("    CPU.rl_finish_SFENCE_VMA");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_reset_from_WFI &&
	  NOT_IF_csr_regfile_read_csr_minstret__7_ULT_cf_ETC___d43)
	$display("%0d: %m.rl_reset_from_WFI", csr_regfile$read_csr_mcycle);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_trap_fetch &&
	  NOT_IF_csr_regfile_read_csr_minstret__7_ULT_cf_ETC___d43)
	$display("    CPU_Stage1.enq: 0x%08h", rg_next_pc);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_reset_from_Debug_Module)
	$display("%0d: %m.rl_reset_from_Debug_Module",
		 csr_regfile$read_csr_mcycle);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_stage1_interrupt &&
	  NOT_IF_csr_regfile_read_csr_minstret__7_ULT_cf_ETC___d43)
	$display("%0d: %m.rl_stage1_interrupt", csr_regfile$read_csr_mcycle);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_reset_start)
	$display("================================================================");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_reset_start)
	$write("CPU: Bluespec  RISC-V  Piccolo  v3.0");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_reset_start) $display(" (RV32)");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_reset_start)
	$display("Copyright (c) 2016-2019 Bluespec, Inc. All Rights Reserved.");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_reset_start)
	$display("================================================================");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_reset_start && cur_verbosity__h3490 != 4'd0)
	$display("%0d: %m.rl_reset_start", csr_regfile$read_csr_mcycle);
  end
  // synopsys translate_on
endmodule  // mkCPU

