Skip to content
[Jenkins]Jenkins
log in

Workspace

/ RISC-V /
.git
.Xil
core
documentation
lib
peripherals
processor
test
build_digilent_arty_a7_100t.tclAug 6, 2026, 4:15:12 AM3.31 KiB
clockInfo.txtAug 6, 2026, 4:16:55 AM375 B
digilent_arty_a7_100t.bitAug 6, 2026, 4:18:23 AM3.65 MiB
digilent_arty_a7_clock_utilization.rptAug 6, 2026, 4:17:18 AM22.02 KiB
digilent_arty_a7_control_sets.rptAug 6, 2026, 4:17:17 AM25.43 KiB
digilent_arty_a7_drc.rptAug 6, 2026, 4:18:00 AM2.34 KiB
digilent_arty_a7_io.rptAug 6, 2026, 4:17:17 AM96.81 KiB
digilent_arty_a7_power.rptAug 6, 2026, 4:18:02 AM8.69 KiB
digilent_arty_a7_route_status.rptAug 6, 2026, 4:17:58 AM651 B
digilent_arty_a7_timing.rptAug 6, 2026, 4:18:01 AM22.75 KiB
digilent_arty_a7_utilization_hierarchical_place.rptAug 6, 2026, 4:17:17 AM7.55 KiB
digilent_arty_a7_utilization_place.rptAug 6, 2026, 4:17:17 AM10.65 KiB
LICENSEAug 6, 2026, 4:15:05 AM1.07 KiB
processor_ci_defines.vhAug 6, 2026, 4:15:12 AM300 B
README.mdAug 6, 2026, 4:15:05 AM812 B
simplified_pipeline.pngAug 6, 2026, 4:15:05 AM177.18 KiB