Skip to content
[Jenkins]Jenkins
log in

Workspace

/ RISC-V /
.git
.Xil
core
documentation
lib
peripherals
processor
test
build_digilent_arty_a7_100t.tclJul 4, 2026, 4:15:10 AM3.31 KiB
clockInfo.txtJul 4, 2026, 4:16:53 AM375 B
digilent_arty_a7_100t.bitJul 4, 2026, 4:18:12 AM3.65 MiB
digilent_arty_a7_clock_utilization.rptJul 4, 2026, 4:17:07 AM22.02 KiB
digilent_arty_a7_control_sets.rptJul 4, 2026, 4:17:06 AM25.43 KiB
digilent_arty_a7_drc.rptJul 4, 2026, 4:17:49 AM2.34 KiB
digilent_arty_a7_io.rptJul 4, 2026, 4:17:05 AM96.81 KiB
digilent_arty_a7_power.rptJul 4, 2026, 4:17:51 AM8.69 KiB
digilent_arty_a7_route_status.rptJul 4, 2026, 4:17:47 AM651 B
digilent_arty_a7_timing.rptJul 4, 2026, 4:17:50 AM22.75 KiB
digilent_arty_a7_utilization_hierarchical_place.rptJul 4, 2026, 4:17:05 AM7.55 KiB
digilent_arty_a7_utilization_place.rptJul 4, 2026, 4:17:05 AM10.65 KiB
LICENSEJul 4, 2026, 4:15:03 AM1.07 KiB
processor_ci_defines.vhJul 4, 2026, 4:15:10 AM300 B
README.mdJul 4, 2026, 4:15:03 AM812 B
simplified_pipeline.pngJul 4, 2026, 4:15:03 AM177.18 KiB