Skip to content
[Jenkins]Jenkins
log in

Workspace

/ RISC-V /
.git
.Xil
core
documentation
lib
peripherals
processor
test
build_digilent_arty_a7_100t.tclJun 28, 2026, 4:15:10 AM3.31 KiB
clockInfo.txtJun 28, 2026, 4:16:51 AM375 B
digilent_arty_a7_100t.bitJun 28, 2026, 4:18:09 AM3.65 MiB
digilent_arty_a7_clock_utilization.rptJun 28, 2026, 4:17:05 AM22.02 KiB
digilent_arty_a7_control_sets.rptJun 28, 2026, 4:17:03 AM25.43 KiB
digilent_arty_a7_drc.rptJun 28, 2026, 4:17:46 AM2.34 KiB
digilent_arty_a7_io.rptJun 28, 2026, 4:17:03 AM96.81 KiB
digilent_arty_a7_power.rptJun 28, 2026, 4:17:49 AM8.69 KiB
digilent_arty_a7_route_status.rptJun 28, 2026, 4:17:45 AM651 B
digilent_arty_a7_timing.rptJun 28, 2026, 4:17:47 AM22.75 KiB
digilent_arty_a7_utilization_hierarchical_place.rptJun 28, 2026, 4:17:03 AM7.55 KiB
digilent_arty_a7_utilization_place.rptJun 28, 2026, 4:17:03 AM10.65 KiB
LICENSEJun 28, 2026, 4:15:03 AM1.07 KiB
processor_ci_defines.vhJun 28, 2026, 4:15:10 AM300 B
README.mdJun 28, 2026, 4:15:03 AM812 B
simplified_pipeline.pngJun 28, 2026, 4:15:03 AM177.18 KiB