# Peripherals
This directory contains a bunch of useful Verilog modules that can be used with Hornet.

### `memory_2rw.v`
This module is based on an SRAM macro generated by OpenRAM[1]. It is a 2-port RW memory. You can use this as your main memory. All SoCs presented under the `processor` folder use this module.

### `mtime_registers.v`
This module implements the `mtime` and the `mtimecmp` registers as defined in the privileged spec. You can simply use this as a memory-mapped peripheral.

### `uart.v`
This is a simple UART module based on Russell Merrick's[2] UART designs. The `fpga_uart` example SoC uses this module to communicate with the computer through a serial port.

### `loader.v`
This module is used in the `fpga_uart` SoC. It controls the reset signals of the SoC. This allows the SoC to be programmed through UART. It's a very specialized peripheral, unlike the others above.

### References
[1] https://github.com/VLSIDA/OpenRAM \
[2] https://github.com/nandland
