Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
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| Tool Version : Vivado v.2023.2 (lin64) Build 4029153 Fri Oct 13 20:13:54 MDT 2023
| Date         : Thu Jul 16 00:17:10 2026
| Host         : 685a421e500f running 64-bit unknown
| Command      : report_control_sets -verbose -file digilent_arty_a7_control_sets.rpt
| Design       : fpga_top
| Device       : xc7a100t
---------------------------------------------------------------------------------------------------------------------------------------------

Control Set Information

Table of Contents
-----------------
1. Summary
2. Histogram
3. Flip-Flop Distribution
4. Detailed Control Set Information

1. Summary
----------

+----------------------------------------------------------+-------+
|                          Status                          | Count |
+----------------------------------------------------------+-------+
| Total control sets                                       |    97 |
|    Minimum number of control sets                        |    97 |
|    Addition due to synthesis replication                 |     0 |
|    Addition due to physical synthesis replication        |     0 |
| Unused register locations in slices containing registers |    88 |
+----------------------------------------------------------+-------+
* Control sets can be merged at opt_design using control_set_merge or merge_equivalent_drivers
** Run report_qor_suggestions for automated merging and remapping suggestions


2. Histogram
------------

+--------------------+-------+
|       Fanout       | Count |
+--------------------+-------+
| Total control sets |    97 |
| >= 0 to < 4        |     3 |
| >= 4 to < 6        |     5 |
| >= 6 to < 8        |     2 |
| >= 8 to < 10       |     8 |
| >= 10 to < 12      |     4 |
| >= 12 to < 14      |     4 |
| >= 14 to < 16      |     0 |
| >= 16              |    71 |
+--------------------+-------+
* Control sets can be remapped at either synth_design or opt_design


3. Flip-Flop Distribution
-------------------------

+--------------+-----------------------+------------------------+-----------------+--------------+
| Clock Enable | Synchronous Set/Reset | Asynchronous Set/Reset | Total Registers | Total Slices |
+--------------+-----------------------+------------------------+-----------------+--------------+
| No           | No                    | No                     |               8 |            6 |
| No           | No                    | Yes                    |             638 |          198 |
| No           | Yes                   | No                     |             148 |           56 |
| Yes          | No                    | No                     |             163 |           53 |
| Yes          | No                    | Yes                    |            1596 |          781 |
| Yes          | Yes                   | No                     |             407 |          105 |
+--------------+-----------------------+------------------------+-----------------+--------------+


4. Detailed Control Set Information
-----------------------------------

+--------------------------------------+---------------------------------------------------------------------+--------------------------------------------------------------+------------------+----------------+--------------+
|             Clock Signal             |                            Enable Signal                            |                       Set/Reset Signal                       | Slice Load Count | Bel Load Count | Bels / Slice |
+--------------------------------------+---------------------------------------------------------------------+--------------------------------------------------------------+------------------+----------------+--------------+
|  clk_IBUF_BUFG                       |                                                                     |                                                              |                1 |              1 |         1.00 |
|  u_Controller/ClkDivider/clk_o_pulse |                                                                     |                                                              |                1 |              1 |         1.00 |
|  clk_o_BUFG                          | ptop/u_Controller/Uart/i_uart_tx/txd_reg_i_2_n_0                    | ptop/u_Controller/Uart/i_uart_tx/txd_reg_i_1_n_0             |                1 |              1 |         1.00 |
|  clk_o_BUFG                          | ptop/u_Controller/Uart/i_uart_rx/next_bit                           | ptop/u_Controller/Uart/i_uart_rx/bit_counter[3]_i_1_n_0      |                1 |              4 |         4.00 |
|  clk_o_BUFG                          | ptop/u_Controller/Uart/i_uart_tx/bit_counter[3]_i_2__0_n_0          | ptop/u_Controller/Uart/i_uart_tx/bit_counter[3]_i_1__0_n_0   |                1 |              4 |         4.00 |
|  clk_o_BUFG                          | ptop/u_Controller/Uart/i_uart_tx/E[0]                               |                                                              |                1 |              4 |         4.00 |
|  clk_o_BUFG                          | ResetBootSystem/counter                                             |                                                              |                1 |              4 |         4.00 |
|  clk_o_BUFG                          | ptop/u_Controller/Interpreter/return_state                          | ResetBootSystem/rst_o_reg_0                                  |                3 |              5 |         1.67 |
|  clk_o_BUFG                          |                                                                     |                                                              |                4 |              6 |         1.50 |
|  clk_o_BUFG                          | ptop/u_Controller/Uart/i_uart_tx/data_to_send[6]_i_1_n_0            | ResetBootSystem/rst_o_reg_0                                  |                2 |              7 |         3.50 |
|  clk_o_BUFG                          | ptop/u_Controller/Uart/uart_tx_en                                   | ResetBootSystem/rst_o_reg_0                                  |                1 |              8 |         8.00 |
|  clk_o_BUFG                          | ptop/u_Controller/Uart/i_uart_rx/E[0]                               | ResetBootSystem/rst_o_reg_0                                  |                2 |              8 |         4.00 |
|  clk_o_BUFG                          | ptop/u_Controller/Uart/tx_fifo/FSM_sequential_state_write_reg[0][0] | ResetBootSystem/rst_o_reg_0                                  |                1 |              8 |         8.00 |
|  clk_o_BUFG                          | ptop/u_Controller/Uart/i_uart_rx/recieved_data0                     | ptop/u_Controller/Uart/i_uart_rx/recieved_data[7]_i_1_n_0    |                2 |              8 |         4.00 |
|  clk_o_BUFG                          | ptop/u_Controller/Uart/i_uart_rx/uart_rx_data[7]_i_1_n_0            | ResetBootSystem/rst_o_reg_0                                  |                2 |              8 |         4.00 |
|  clk_o_BUFG                          | ptop/u_Controller/Interpreter/accumulator[7]_i_1_n_0                | ResetBootSystem/rst_o_reg_0                                  |                1 |              8 |         8.00 |
|  clk_o_BUFG                          | ptop/u_Controller/Interpreter/counter                               | ResetBootSystem/rst_o_reg_0                                  |                2 |              8 |         4.00 |
|  u_Controller/ClkDivider/clk_o_pulse | ptop/core0/EXMEM_preg_misaligned_reg_inv_n_0                        | ptop/core0/MULDIV/MUL/async_rst_reg                          |                5 |              8 |         1.60 |
|  clk_o_BUFG                          | ptop/u_Controller/Uart/i_uart_rx/cycle_counter0                     | ptop/u_Controller/Uart/i_uart_rx/cycle_counter[9]_i_1__0_n_0 |                3 |             10 |         3.33 |
|  clk_o_BUFG                          | ptop/u_Controller/Uart/i_uart_tx/txd_reg_i_2_n_0                    | ResetBootSystem/SR[0]                                        |                3 |             10 |         3.33 |
|  clk_o_BUFG                          | ptop/u_Controller/Uart/tx_fifo/read_ptr[2]_i_1_n_0                  | ResetBootSystem/rst_o_reg_0                                  |                3 |             11 |         3.67 |
|  clk_o_BUFG                          | ptop/u_Controller/Uart/rx_fifo/read_ptr0                            | ResetBootSystem/rst_o_reg_0                                  |                3 |             11 |         3.67 |
|  clk_o_BUFG                          | ptop/u_Controller/Uart/rx_fifo/memory_reg_0_7_0_5_i_1__0_n_0        |                                                              |                2 |             12 |         6.00 |
|  clk_o_BUFG                          | ptop/u_Controller/Uart/tx_fifo/memory_reg_0_7_0_5_i_1_n_0           |                                                              |                2 |             12 |         6.00 |
|  clk_o_BUFG                          | ptop/u_Controller/Interpreter/address[31]_i_1_n_0                   |                                                              |                7 |             12 |         1.71 |
|  u_Controller/ClkDivider/clk_o_pulse | ptop/core0/MULDIV/MULDIV_ctrl/E[0]                                  | ptop/core0/MULDIV/MUL/async_rst_reg                          |                5 |             13 |         2.60 |
|  u_Controller/ClkDivider/clk_o_pulse | ptop/core0/CSR_UNIT/mie[31]_i_1_n_0                                 | ptop/core0/MULDIV/MUL/async_rst_reg                          |                9 |             19 |         2.11 |
|  clk_o_BUFG                          | ptop/u_Controller/Interpreter/num_of_cycles_to_pulse[23]_i_1_n_0    |                                                              |                8 |             24 |         3.00 |
|  clk_o_BUFG                          | ptop/u_Controller/Interpreter/memory_page_number[23]_i_2_n_0        | ptop/u_Controller/Interpreter/memory_page_number[23]_i_1_n_0 |                7 |             24 |         3.43 |
|  clk_o_BUFG                          | ptop/u_Controller/Interpreter/accumulator[31]_i_1_n_0               | ResetBootSystem/rst_o_reg_0                                  |                6 |             24 |         4.00 |
|  clk_o_BUFG                          | ptop/u_Controller/Interpreter/num_of_pages                          | ResetBootSystem/rst_o_reg_0                                  |                4 |             24 |         6.00 |
|  clk_o_BUFG                          | ptop/u_Controller/Interpreter/timeout                               | ResetBootSystem/rst_o_reg_0                                  |                6 |             24 |         4.00 |
|  clk_o_BUFG                          | ptop/u_Controller/Uart/tx_fifo/E[0]                                 | ResetBootSystem/rst_o_reg_0                                  |                5 |             32 |         6.40 |
|  u_Controller/ClkDivider/clk_o_pulse | ptop/core0/CSR_UNIT/mcause[31]_i_1_n_0                              | ptop/core0/MULDIV/MUL/async_rst_reg                          |                9 |             32 |         3.56 |
|  u_Controller/ClkDivider/clk_o_pulse | ptop/core0/CSR_UNIT/mepc[31]_i_1_n_0                                | ptop/core0/MULDIV/MUL/async_rst_reg                          |               11 |             32 |         2.91 |
| ~u_Controller/ClkDivider/clk_o_pulse | ptop/core0/register_bank[24][31]_i_1_n_0                            | ptop/core0/MULDIV/MUL/async_rst_reg                          |               17 |             32 |         1.88 |
|  clk_o_BUFG                          | ptop/u_Controller/Uart/rx_fifo/E[0]                                 | ResetBootSystem/rst_o_reg_0                                  |                4 |             32 |         8.00 |
| ~u_Controller/ClkDivider/clk_o_pulse | ptop/core0/register_bank[26][31]_i_1_n_0                            | ptop/core0/MULDIV/MUL/async_rst_reg                          |               17 |             32 |         1.88 |
|  u_Controller/ClkDivider/clk_o_pulse | ptop/core0/CSR_UNIT/mtvec                                           | ptop/core0/MULDIV/MUL/async_rst_reg                          |               11 |             32 |         2.91 |
|  clk_o_BUFG                          | ptop/u_Controller/Interpreter/communication_buffer[31]_i_1_n_0      | ResetBootSystem/rst_o_reg_0                                  |                9 |             32 |         3.56 |
|  clk_o_BUFG                          | ptop/u_Controller/Interpreter/read_buffer                           | ResetBootSystem/rst_o_reg_0                                  |               19 |             32 |         1.68 |
|  clk_o_BUFG                          | ptop/u_Controller/Interpreter/write_data[31]_i_1_n_0                |                                                              |               15 |             32 |         2.13 |
|  clk_o_BUFG                          | ptop/u_Controller/Interpreter/communication_write_data[31]_i_1_n_0  |                                                              |                7 |             32 |         4.57 |
|  u_Controller/ClkDivider/clk_o_pulse | ptop/core0/CSR_UNIT/mscratch[31]_i_1_n_0                            | ptop/core0/MULDIV/MUL/async_rst_reg                          |               12 |             32 |         2.67 |
|  clk_o_BUFG                          | ptop/u_Controller/Interpreter/timeout_counter                       | ResetBootSystem/rst_o_reg_0                                  |                6 |             32 |         5.33 |
|  clk_o_BUFG                          | ptop/u_Controller/Interpreter/end_position[31]_i_1_n_0              | ResetBootSystem/rst_o_reg_0                                  |                8 |             32 |         4.00 |
|  clk_o_BUFG                          | ptop/u_Controller/ClkDivider/pulse_counter[0]_i_1_n_0               | ResetBootSystem/rst_o_reg_0                                  |                8 |             32 |         4.00 |
| ~u_Controller/ClkDivider/clk_o_pulse | ptop/core0/register_bank[21][31]_i_1_n_0                            | ptop/core0/MULDIV/MUL/async_rst_reg                          |               15 |             32 |         2.13 |
| ~u_Controller/ClkDivider/clk_o_pulse | ptop/core0/register_bank[3][31]_i_1_n_0                             | ptop/core0/MULDIV/MUL/async_rst_reg                          |               13 |             32 |         2.46 |
| ~u_Controller/ClkDivider/clk_o_pulse | ptop/core0/register_bank[19][31]_i_1_n_0                            | ptop/core0/MULDIV/MUL/async_rst_reg                          |               15 |             32 |         2.13 |
| ~u_Controller/ClkDivider/clk_o_pulse | ptop/core0/register_bank[4][31]_i_1_n_0                             | ptop/core0/MULDIV/MUL/async_rst_reg                          |               16 |             32 |         2.00 |
| ~u_Controller/ClkDivider/clk_o_pulse | ptop/core0/register_bank[27][31]_i_1_n_0                            | ptop/core0/MULDIV/MUL/async_rst_reg                          |               22 |             32 |         1.45 |
| ~u_Controller/ClkDivider/clk_o_pulse | ptop/core0/register_bank[2][31]_i_1_n_0                             | ptop/core0/MULDIV/MUL/async_rst_reg                          |               14 |             32 |         2.29 |
| ~u_Controller/ClkDivider/clk_o_pulse | ptop/core0/register_bank[23][31]_i_1_n_0                            | ptop/core0/MULDIV/MUL/async_rst_reg                          |               23 |             32 |         1.39 |
| ~u_Controller/ClkDivider/clk_o_pulse | ptop/core0/register_bank[13][31]_i_1_n_0                            | ptop/core0/MULDIV/MUL/async_rst_reg                          |               10 |             32 |         3.20 |
| ~u_Controller/ClkDivider/clk_o_pulse | ptop/core0/register_bank[15][31]_i_1_n_0                            | ptop/core0/MULDIV/MUL/async_rst_reg                          |               16 |             32 |         2.00 |
| ~u_Controller/ClkDivider/clk_o_pulse | ptop/core0/register_bank[28][31]_i_1_n_0                            | ptop/core0/MULDIV/MUL/async_rst_reg                          |               19 |             32 |         1.68 |
| ~u_Controller/ClkDivider/clk_o_pulse | ptop/core0/register_bank[31][31]_i_1_n_0                            | ptop/core0/MULDIV/MUL/async_rst_reg                          |               25 |             32 |         1.28 |
| ~u_Controller/ClkDivider/clk_o_pulse | ptop/core0/register_bank[1][31]_i_1_n_0                             | ptop/core0/MULDIV/MUL/async_rst_reg                          |               20 |             32 |         1.60 |
| ~u_Controller/ClkDivider/clk_o_pulse | ptop/core0/register_bank[10][31]_i_1_n_0                            | ptop/core0/MULDIV/MUL/async_rst_reg                          |               14 |             32 |         2.29 |
| ~u_Controller/ClkDivider/clk_o_pulse | ptop/core0/register_bank[12][31]_i_1_n_0                            | ptop/core0/MULDIV/MUL/async_rst_reg                          |               10 |             32 |         3.20 |
| ~u_Controller/ClkDivider/clk_o_pulse | ptop/core0/register_bank[7][31]_i_1_n_0                             | ptop/core0/MULDIV/MUL/async_rst_reg                          |               27 |             32 |         1.19 |
| ~u_Controller/ClkDivider/clk_o_pulse | ptop/core0/register_bank[11][31]_i_1_n_0                            | ptop/core0/MULDIV/MUL/async_rst_reg                          |               15 |             32 |         2.13 |
| ~u_Controller/ClkDivider/clk_o_pulse | ptop/core0/register_bank[25][31]_i_1_n_0                            | ptop/core0/MULDIV/MUL/async_rst_reg                          |               20 |             32 |         1.60 |
| ~u_Controller/ClkDivider/clk_o_pulse | ptop/core0/register_bank[9][31]_i_1_n_0                             | ptop/core0/MULDIV/MUL/async_rst_reg                          |               27 |             32 |         1.19 |
| ~u_Controller/ClkDivider/clk_o_pulse | ptop/core0/register_bank[30][31]_i_1_n_0                            | ptop/core0/MULDIV/MUL/async_rst_reg                          |               23 |             32 |         1.39 |
| ~u_Controller/ClkDivider/clk_o_pulse | ptop/core0/register_bank[17][31]_i_1_n_0                            | ptop/core0/MULDIV/MUL/async_rst_reg                          |               14 |             32 |         2.29 |
| ~u_Controller/ClkDivider/clk_o_pulse | ptop/core0/register_bank[16][31]_i_1_n_0                            | ptop/core0/MULDIV/MUL/async_rst_reg                          |               16 |             32 |         2.00 |
| ~u_Controller/ClkDivider/clk_o_pulse | ptop/core0/register_bank[29][31]_i_1_n_0                            | ptop/core0/MULDIV/MUL/async_rst_reg                          |               21 |             32 |         1.52 |
| ~u_Controller/ClkDivider/clk_o_pulse | ptop/core0/register_bank[18][31]_i_1_n_0                            | ptop/core0/MULDIV/MUL/async_rst_reg                          |               15 |             32 |         2.13 |
| ~u_Controller/ClkDivider/clk_o_pulse | ptop/core0/register_bank[8][31]_i_1_n_0                             | ptop/core0/MULDIV/MUL/async_rst_reg                          |               25 |             32 |         1.28 |
| ~u_Controller/ClkDivider/clk_o_pulse | ptop/core0/register_bank[20][31]_i_1_n_0                            | ptop/core0/MULDIV/MUL/async_rst_reg                          |               13 |             32 |         2.46 |
| ~u_Controller/ClkDivider/clk_o_pulse | ptop/core0/register_bank[22][31]_i_1_n_0                            | ptop/core0/MULDIV/MUL/async_rst_reg                          |               19 |             32 |         1.68 |
| ~u_Controller/ClkDivider/clk_o_pulse | ptop/core0/register_bank[14][31]_i_1_n_0                            | ptop/core0/MULDIV/MUL/async_rst_reg                          |               19 |             32 |         1.68 |
| ~u_Controller/ClkDivider/clk_o_pulse | ptop/core0/register_bank[5][31]_i_1_n_0                             | ptop/core0/MULDIV/MUL/async_rst_reg                          |               15 |             32 |         2.13 |
| ~u_Controller/ClkDivider/clk_o_pulse | ptop/core0/register_bank[6][31]_i_1_n_0                             | ptop/core0/MULDIV/MUL/async_rst_reg                          |               21 |             32 |         1.52 |
|  clk_o_BUFG                          | ptop/u_Controller/Interpreter/num_of_positions[23]_i_1_n_0          |                                                              |               14 |             55 |         3.93 |
|  u_Controller/ClkDivider/clk_o_pulse |                                                                     | ptop/sync_data[31]_i_1_n_0                                   |               26 |             64 |         2.46 |
|  u_Controller/ClkDivider/clk_o_pulse | ptop/core0/MULDIV/MULDIV_ctrl/FSM_onehot_current_state_reg[0]_0[0]  | ptop/core0/MULDIV/MUL/async_rst_reg                          |               37 |             64 |         1.73 |
|  u_Controller/ClkDivider/clk_o_pulse | ptop/core0/MULDIV/MULDIV_ctrl/FSM_onehot_current_state_reg[5]_1[0]  | ptop/core0/MULDIV/MUL/async_rst_reg                          |               28 |             64 |         2.29 |
|  u_Controller/ClkDivider/clk_o_pulse | ptop/core0/MULDIV/MULDIV_ctrl/rdy_reg[0]                            | ptop/core0/MULDIV/MUL/async_rst_reg                          |               17 |             64 |         3.76 |
|  clk_o_BUFG                          |                                                                     | ResetBootSystem/rst_o_reg_0                                  |               30 |             84 |         2.80 |
|  u_Controller/ClkDivider/clk_o_pulse | ptop/core0/CSR_UNIT/STATE_reg_0                                     | ptop/core0/MULDIV/MUL/async_rst_reg                          |               35 |            102 |         2.91 |
|  u_Controller/ClkDivider/clk_o_pulse | ptop/core0/MULDIV/MULDIV_ctrl/IDEX_preg_imm                         | ptop/core0/MULDIV/MUL/async_rst_reg                          |               38 |            110 |         2.89 |
|  clk_o_BUFG                          | ptop/core0/CSR_UNIT/address_reg[31]_2                               |                                                              |               32 |            128 |         4.00 |
|  clk_o_BUFG                          | ptop/core0/CSR_UNIT/address_reg[31]_0                               |                                                              |               32 |            128 |         4.00 |
|  clk_o_BUFG                          | ptop/core0/CSR_UNIT/address_reg[31]                                 |                                                              |               32 |            128 |         4.00 |
|  clk_o_BUFG                          | ptop/core0/CSR_UNIT/address_reg[31]_1                               |                                                              |               32 |            128 |         4.00 |
|  clk_o_BUFG                          | ptop/u_Controller/Interpreter/memory_mux_selector_reg_10            |                                                              |               32 |            128 |         4.00 |
|  clk_o_BUFG                          | ptop/u_Controller/Interpreter/address_reg[31]_0                     |                                                              |               32 |            128 |         4.00 |
|  clk_o_BUFG                          | ptop/u_Controller/Interpreter/address_reg[31]_1                     |                                                              |               32 |            128 |         4.00 |
|  clk_o_BUFG                          | ptop/u_Controller/Interpreter/address_reg[31]_2                     |                                                              |               32 |            128 |         4.00 |
|  clk_o_BUFG                          | ptop/u_Controller/Interpreter/address_reg[31]_3                     |                                                              |               32 |            128 |         4.00 |
|  clk_o_BUFG                          | ptop/u_Controller/Interpreter/memory_mux_selector_reg_9             |                                                              |               32 |            128 |         4.00 |
|  clk_o_BUFG                          | ptop/u_Controller/Interpreter/memory_mux_selector_reg_11            |                                                              |               32 |            128 |         4.00 |
|  clk_o_BUFG                          | ptop/u_Controller/Interpreter/memory_mux_selector_reg_12            |                                                              |               32 |            128 |         4.00 |
|  u_Controller/ClkDivider/clk_o_pulse |                                                                     | ptop/core0/MULDIV/MUL/async_rst_reg                          |              198 |            638 |         3.22 |
+--------------------------------------+---------------------------------------------------------------------+--------------------------------------------------------------+------------------+----------------+--------------+


