Skip to content

Workspace

/ RISC-V /
.git
.Xil
core
documentation
lib
peripherals
processor
test
build_digilent_arty_a7_100t.tclJun 21, 2026, 4:16:07 AM3.31 KiB
clockInfo.txtJun 21, 2026, 4:17:48 AM375 B
digilent_arty_a7_100t.bitJun 21, 2026, 4:19:06 AM3.65 MiB
digilent_arty_a7_clock_utilization.rptJun 21, 2026, 4:18:01 AM22.02 KiB
digilent_arty_a7_control_sets.rptJun 21, 2026, 4:18:00 AM25.43 KiB
digilent_arty_a7_drc.rptJun 21, 2026, 4:18:43 AM2.34 KiB
digilent_arty_a7_io.rptJun 21, 2026, 4:18:00 AM96.81 KiB
digilent_arty_a7_power.rptJun 21, 2026, 4:18:45 AM8.69 KiB
digilent_arty_a7_route_status.rptJun 21, 2026, 4:18:41 AM651 B
digilent_arty_a7_timing.rptJun 21, 2026, 4:18:43 AM22.75 KiB
digilent_arty_a7_utilization_hierarchical_place.rptJun 21, 2026, 4:17:59 AM7.55 KiB
digilent_arty_a7_utilization_place.rptJun 21, 2026, 4:18:00 AM10.65 KiB
LICENSEJun 21, 2026, 4:16:00 AM1.07 KiB
processor_ci_defines.vhJun 21, 2026, 4:16:07 AM300 B
README.mdJun 21, 2026, 4:16:00 AM812 B
simplified_pipeline.pngJun 21, 2026, 4:16:00 AM177.18 KiB