Skip to content
[Jenkins]Jenkins
log in

Workspace

/ RPU /
.git
.Xil
tests
vhdl
build_digilent_arty_a7_100t.tclAug 5, 2026, 2:11:08 AM3.02 KiB
clockInfo.txtAug 5, 2026, 2:12:40 AM375 B
digilent_arty_a7_100t.bitAug 5, 2026, 2:13:49 AM3.65 MiB
digilent_arty_a7_clock_utilization.rptAug 5, 2026, 2:12:50 AM21.28 KiB
digilent_arty_a7_control_sets.rptAug 5, 2026, 2:12:50 AM19.69 KiB
digilent_arty_a7_drc.rptAug 5, 2026, 2:13:28 AM19.75 KiB
digilent_arty_a7_io.rptAug 5, 2026, 2:12:50 AM96.81 KiB
digilent_arty_a7_power.rptAug 5, 2026, 2:13:30 AM8.85 KiB
digilent_arty_a7_route_status.rptAug 5, 2026, 2:13:26 AM651 B
digilent_arty_a7_timing.rptAug 5, 2026, 2:13:28 AM22.74 KiB
digilent_arty_a7_utilization_hierarchical_place.rptAug 5, 2026, 2:12:50 AM5.05 KiB
digilent_arty_a7_utilization_place.rptAug 5, 2026, 2:12:50 AM10.87 KiB
LICENSEAug 5, 2026, 2:09:38 AM11.09 KiB
processor_ci_defines.vhAug 5, 2026, 2:11:08 AM300 B
README.mdAug 5, 2026, 2:09:38 AM1.24 KiB
rpu_core_diagram.pngAug 5, 2026, 2:09:38 AM87.03 KiB