Skip to content
[Jenkins]Jenkins
log in

Workspace

/ RPU /
.git
.Xil
tests
vhdl
build_digilent_arty_a7_100t.tclSep 22, 2026, 2:11:13 AM3.02 KiB
clockInfo.txtSep 22, 2026, 2:12:41 AM375 B
digilent_arty_a7_100t.bitSep 22, 2026, 2:13:48 AM3.65 MiB
digilent_arty_a7_clock_utilization.rptSep 22, 2026, 2:12:50 AM21.28 KiB
digilent_arty_a7_control_sets.rptSep 22, 2026, 2:12:49 AM19.69 KiB
digilent_arty_a7_drc.rptSep 22, 2026, 2:13:27 AM19.75 KiB
digilent_arty_a7_io.rptSep 22, 2026, 2:12:49 AM96.81 KiB
digilent_arty_a7_power.rptSep 22, 2026, 2:13:28 AM8.85 KiB
digilent_arty_a7_route_status.rptSep 22, 2026, 2:13:25 AM651 B
digilent_arty_a7_timing.rptSep 22, 2026, 2:13:27 AM22.74 KiB
digilent_arty_a7_utilization_hierarchical_place.rptSep 22, 2026, 2:12:49 AM5.05 KiB
digilent_arty_a7_utilization_place.rptSep 22, 2026, 2:12:49 AM10.87 KiB
LICENSESep 22, 2026, 2:08:53 AM11.09 KiB
processor_ci_defines.vhSep 22, 2026, 2:11:13 AM300 B
README.mdSep 22, 2026, 2:08:53 AM1.24 KiB
rpu_core_diagram.pngSep 22, 2026, 2:08:53 AM87.03 KiB