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build_digilent_arty_a7_100t.tclSep 9, 2026, 2:11:08 AM3.02 KiB
clockInfo.txtSep 9, 2026, 2:12:36 AM375 B
digilent_arty_a7_100t.bitSep 9, 2026, 2:13:43 AM3.65 MiB
digilent_arty_a7_clock_utilization.rptSep 9, 2026, 2:12:45 AM21.28 KiB
digilent_arty_a7_control_sets.rptSep 9, 2026, 2:12:44 AM19.69 KiB
digilent_arty_a7_drc.rptSep 9, 2026, 2:13:22 AM19.75 KiB
digilent_arty_a7_io.rptSep 9, 2026, 2:12:44 AM96.81 KiB
digilent_arty_a7_power.rptSep 9, 2026, 2:13:24 AM8.85 KiB
digilent_arty_a7_route_status.rptSep 9, 2026, 2:13:21 AM651 B
digilent_arty_a7_timing.rptSep 9, 2026, 2:13:22 AM22.74 KiB
digilent_arty_a7_utilization_hierarchical_place.rptSep 9, 2026, 2:12:44 AM5.05 KiB
digilent_arty_a7_utilization_place.rptSep 9, 2026, 2:12:44 AM10.87 KiB
LICENSESep 9, 2026, 2:08:45 AM11.09 KiB
processor_ci_defines.vhSep 9, 2026, 2:11:08 AM300 B
README.mdSep 9, 2026, 2:08:45 AM1.24 KiB
rpu_core_diagram.pngSep 9, 2026, 2:08:45 AM87.03 KiB