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	vhdl
	build_digilent_arty_a7_100t.tcl	Jul 16, 2026, 2:11:07 AM	3.02 KiB
	clockInfo.txt	Jul 16, 2026, 2:12:33 AM	375 B
	digilent_arty_a7_clock_utilization.rpt	Jul 16, 2026, 2:12:43 AM	21.28 KiB
	digilent_arty_a7_control_sets.rpt	Jul 16, 2026, 2:12:42 AM	19.69 KiB
	digilent_arty_a7_io.rpt	Jul 16, 2026, 2:12:42 AM	96.81 KiB
	digilent_arty_a7_utilization_hierarchical_place.rpt	Jul 16, 2026, 2:12:42 AM	5.05 KiB
	digilent_arty_a7_utilization_place.rpt	Jul 16, 2026, 2:12:42 AM	10.87 KiB
	LICENSE	Jul 16, 2026, 2:09:55 AM	11.09 KiB
	processor_ci_defines.vh	Jul 16, 2026, 2:11:07 AM	300 B
	README.md	Jul 16, 2026, 2:09:55 AM	1.24 KiB
	rpu_core_diagram.png	Jul 16, 2026, 2:09:55 AM	87.03 KiB
(all files in zip)