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            "MEM_WIDTH": [ { "value": "32", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
            "MEM_ECC": [ { "value": "NONE", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
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        "BRAM_PORTB": {
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          "abstraction_type": "xilinx.com:interface:bram_rtl:1.0",
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            "MASTER_TYPE": [ { "value": "OTHER", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
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          },
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            "WE": [ { "physical_name": "web" } ]
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      "memory_maps": {
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              "usage": "memory",
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              "parameters": {
                "OFFSET_BASE_PARAM": [ { "value": "C_BASEADDR" } ],
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              }
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          }
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      }
    }
  }
}