<?xml version="1.0" encoding="UTF-8"?>
<wave_config>
   <wave_state>
   </wave_state>
   <db_ref_list>
      <db_ref path="Testbench_FPGA_Platform_behav.wdb" id="1">
         <top_modules>
            <top_module name="RS5_pkg" />
            <top_module name="Testbench_FPGA_Platform" />
            <top_module name="glbl" />
         </top_modules>
      </db_ref>
   </db_ref_list>
   <zoom_setting>
      <ZoomStartTime time="0.000000 us"></ZoomStartTime>
      <ZoomEndTime time="28.300001 us"></ZoomEndTime>
      <Cursor1Time time="3.400000 us"></Cursor1Time>
   </zoom_setting>
   <column_width_setting>
      <NameColumnWidth column_width="242"></NameColumnWidth>
      <ValueColumnWidth column_width="110"></ValueColumnWidth>
   </column_width_setting>
   <WVObjectSize size="31" />
   <wvobject type="logic" fp_name="/Testbench_FPGA_Platform/clk">
      <obj_property name="ElementShortName">clk</obj_property>
      <obj_property name="ObjectShortName">clk</obj_property>
   </wvobject>
   <wvobject type="logic" fp_name="/Testbench_FPGA_Platform/rstCPU">
      <obj_property name="ElementShortName">rstCPU</obj_property>
      <obj_property name="ObjectShortName">rstCPU</obj_property>
   </wvobject>
   <wvobject type="logic" fp_name="/Testbench_FPGA_Platform/BTND">
      <obj_property name="ElementShortName">BTND</obj_property>
      <obj_property name="ObjectShortName">BTND</obj_property>
   </wvobject>
   <wvobject type="array" fp_name="/Testbench_FPGA_Platform/i_cnt">
      <obj_property name="ElementShortName">i_cnt[31:0]</obj_property>
      <obj_property name="ObjectShortName">i_cnt[31:0]</obj_property>
   </wvobject>
   <wvobject type="logic" fp_name="/Testbench_FPGA_Platform/dut/mei">
      <obj_property name="ElementShortName">mei</obj_property>
      <obj_property name="ObjectShortName">mei</obj_property>
   </wvobject>
   <wvobject type="array" fp_name="/Testbench_FPGA_Platform/dut/data_peripherals">
      <obj_property name="ElementShortName">data_peripherals[31:0]</obj_property>
      <obj_property name="ObjectShortName">data_peripherals[31:0]</obj_property>
   </wvobject>
   <wvobject type="logic" fp_name="/Testbench_FPGA_Platform/dut/interrupt_ack">
      <obj_property name="ElementShortName">interrupt_ack</obj_property>
      <obj_property name="ObjectShortName">interrupt_ack</obj_property>
   </wvobject>
   <wvobject type="array" fp_name="/Testbench_FPGA_Platform/dut/dut/CSRBank1/mstatus">
      <obj_property name="ElementShortName">mstatus[31:0]</obj_property>
      <obj_property name="ObjectShortName">mstatus[31:0]</obj_property>
   </wvobject>
   <wvobject type="logic" fp_name="/Testbench_FPGA_Platform/dut/dut/CSRBank1/mstatus_mie">
      <obj_property name="ElementShortName">mstatus_mie</obj_property>
      <obj_property name="ObjectShortName">mstatus_mie</obj_property>
   </wvobject>
   <wvobject type="array" fp_name="/Testbench_FPGA_Platform/dut/dut/fetch1/pc_o">
      <obj_property name="ElementShortName">pc_o[31:0]</obj_property>
      <obj_property name="ObjectShortName">pc_o[31:0]</obj_property>
   </wvobject>
   <wvobject type="array" fp_name="/Testbench_FPGA_Platform/dut/dut/decoder1/instruction_operation_o">
      <obj_property name="ElementShortName">instruction_operation_o[46:0]</obj_property>
      <obj_property name="ObjectShortName">instruction_operation_o[46:0]</obj_property>
   </wvobject>
   <wvobject type="array" fp_name="/Testbench_FPGA_Platform/dut/dut/CSRBank1/mie">
      <obj_property name="ElementShortName">mie[31:0]</obj_property>
      <obj_property name="ObjectShortName">mie[31:0]</obj_property>
   </wvobject>
   <wvobject type="array" fp_name="/Testbench_FPGA_Platform/dut/dut/CSRBank1/mip">
      <obj_property name="ElementShortName">mip[31:0]</obj_property>
      <obj_property name="ObjectShortName">mip[31:0]</obj_property>
   </wvobject>
   <wvobject type="array" fp_name="/Testbench_FPGA_Platform/dut/dut/CSRBank1/irq_i">
      <obj_property name="ElementShortName">irq_i[31:0]</obj_property>
      <obj_property name="ObjectShortName">irq_i[31:0]</obj_property>
   </wvobject>
   <wvobject type="logic" fp_name="/Testbench_FPGA_Platform/dut/Peripherals1/BTND_debounced">
      <obj_property name="ElementShortName">BTND_debounced</obj_property>
      <obj_property name="ObjectShortName">BTND_debounced</obj_property>
   </wvobject>
   <wvobject type="array" fp_name="/Testbench_FPGA_Platform/dut/Peripherals1/irq">
      <obj_property name="ElementShortName">irq[2:1]</obj_property>
      <obj_property name="ObjectShortName">irq[2:1]</obj_property>
      <obj_property name="isExpanded"></obj_property>
   </wvobject>
   <wvobject type="logic" fp_name="/Testbench_FPGA_Platform/dut/Peripherals1/button_irq">
      <obj_property name="ElementShortName">button_irq</obj_property>
      <obj_property name="ObjectShortName">button_irq</obj_property>
   </wvobject>
   <wvobject type="array" fp_name="/Testbench_FPGA_Platform/dut/Peripherals1/interrupt_req_o">
      <obj_property name="ElementShortName">interrupt_req_o[2:1]</obj_property>
      <obj_property name="ObjectShortName">interrupt_req_o[2:1]</obj_property>
      <obj_property name="isExpanded"></obj_property>
   </wvobject>
   <wvobject type="logic" fp_name="/Testbench_FPGA_Platform/dut/plic1/irq_o">
      <obj_property name="ElementShortName">irq_o</obj_property>
      <obj_property name="ObjectShortName">irq_o</obj_property>
   </wvobject>
   <wvobject type="array" fp_name="/Testbench_FPGA_Platform/dut/plic1/ie">
      <obj_property name="ElementShortName">ie[2:1]</obj_property>
      <obj_property name="ObjectShortName">ie[2:1]</obj_property>
   </wvobject>
   <wvobject type="array" fp_name="/Testbench_FPGA_Platform/dut/plic1/ip">
      <obj_property name="ElementShortName">ip[2:1]</obj_property>
      <obj_property name="ObjectShortName">ip[2:1]</obj_property>
   </wvobject>
   <wvobject type="array" fp_name="/Testbench_FPGA_Platform/dut/cpu_data_in">
      <obj_property name="ElementShortName">cpu_data_in[31:0]</obj_property>
      <obj_property name="ObjectShortName">cpu_data_in[31:0]</obj_property>
   </wvobject>
   <wvobject type="logic" fp_name="/Testbench_FPGA_Platform/dut/enable_peripherals_r">
      <obj_property name="ElementShortName">enable_peripherals_r</obj_property>
      <obj_property name="ObjectShortName">enable_peripherals_r</obj_property>
   </wvobject>
   <wvobject type="array" fp_name="/Testbench_FPGA_Platform/dut/cpu_data_address">
      <obj_property name="ElementShortName">cpu_data_address[31:0]</obj_property>
      <obj_property name="ObjectShortName">cpu_data_address[31:0]</obj_property>
   </wvobject>
   <wvobject type="array" fp_name="/Testbench_FPGA_Platform/dut/cpu_data_out">
      <obj_property name="ElementShortName">cpu_data_out[31:0]</obj_property>
      <obj_property name="ObjectShortName">cpu_data_out[31:0]</obj_property>
   </wvobject>
   <wvobject type="logic" fp_name="/Testbench_FPGA_Platform/dut/Peripherals1/UART_ready_rx">
      <obj_property name="ElementShortName">UART_ready_rx</obj_property>
      <obj_property name="ObjectShortName">UART_ready_rx</obj_property>
   </wvobject>
   <wvobject type="logic" fp_name="/Testbench_FPGA_Platform/dut/Peripherals1/UART_RX_irq">
      <obj_property name="ElementShortName">UART_RX_irq</obj_property>
      <obj_property name="ObjectShortName">UART_RX_irq</obj_property>
   </wvobject>
   <wvobject type="array" fp_name="/Testbench_FPGA_Platform/dut/Peripherals1/UART_data_rx_reg">
      <obj_property name="ElementShortName">UART_data_rx_reg[7:0]</obj_property>
      <obj_property name="ObjectShortName">UART_data_rx_reg[7:0]</obj_property>
   </wvobject>
   <wvobject type="array" fp_name="/Testbench_FPGA_Platform/dut/Peripherals1/UART_data_rx">
      <obj_property name="ElementShortName">UART_data_rx[7:0]</obj_property>
      <obj_property name="ObjectShortName">UART_data_rx[7:0]</obj_property>
   </wvobject>
   <wvobject type="logic" fp_name="/Testbench_FPGA_Platform/dut/plic1/iack_i">
      <obj_property name="ElementShortName">iack_i</obj_property>
      <obj_property name="ObjectShortName">iack_i</obj_property>
   </wvobject>
   <wvobject type="array" fp_name="/Testbench_FPGA_Platform/dut/plic1/iack_o">
      <obj_property name="ElementShortName">iack_o[2:1]</obj_property>
      <obj_property name="ObjectShortName">iack_o[2:1]</obj_property>
   </wvobject>
</wave_config>
