read_verilog -sv /eda/processor_ci/rtl/RV12.sv
read_verilog -sv /var/jenkins_home/workspace/RV12/RV12/submodules/ahb3lite_pkg/rtl/verilog/ahb3lite_pkg.sv
read_verilog -sv /var/jenkins_home/workspace/RV12/RV12/rtl/verilog/pkg/riscv_cache_pkg.sv
read_verilog -sv /var/jenkins_home/workspace/RV12/RV12/rtl/verilog/pkg/riscv_du_pkg.sv
read_verilog -sv /var/jenkins_home/workspace/RV12/RV12/rtl/verilog/pkg/riscv_opcodes_pkg.sv
read_verilog -sv /var/jenkins_home/workspace/RV12/RV12/rtl/verilog/pkg/riscv_rv12_pkg.sv
read_verilog -sv /var/jenkins_home/workspace/RV12/RV12/rtl/verilog/pkg/riscv_state1.10_pkg.sv
read_verilog -sv /var/jenkins_home/workspace/RV12/RV12/rtl/verilog/pkg/riscv_state_20240411_pkg.sv
read_verilog -sv /var/jenkins_home/workspace/RV12/RV12/rtl/verilog/pkg/riscv_state1.7_pkg.sv
read_verilog -sv /var/jenkins_home/workspace/RV12/RV12/rtl/verilog/pkg/riscv_state1.9_pkg.sv
read_verilog -sv /var/jenkins_home/workspace/RV12/RV12/rtl/verilog/pkg/riscv_pma_pkg.sv
read_verilog -sv /var/jenkins_home/workspace/RV12/RV12/rtl/verilog/pkg/biu_constants_pkg.sv
read_verilog -sv /var/jenkins_home/workspace/RV12/RV12/rtl/verilog/ahb3lite/biu_ahb3lite.sv
read_verilog -sv /var/jenkins_home/workspace/RV12/RV12/rtl/verilog/ahb3lite/riscv_top_ahb3lite.sv
read_verilog -sv /var/jenkins_home/workspace/RV12/RV12/rtl/verilog/core/riscv_bp.sv
read_verilog -sv /var/jenkins_home/workspace/RV12/RV12/rtl/verilog/core/riscv_core.sv
read_verilog -sv /var/jenkins_home/workspace/RV12/RV12/rtl/verilog/core/riscv_du.sv
read_verilog -sv /var/jenkins_home/workspace/RV12/RV12/rtl/verilog/core/riscv_dwb.sv
read_verilog -sv /var/jenkins_home/workspace/RV12/RV12/rtl/verilog/core/riscv_ex.sv
read_verilog -sv /var/jenkins_home/workspace/RV12/RV12/rtl/verilog/core/riscv_id.sv
read_verilog -sv /var/jenkins_home/workspace/RV12/RV12/rtl/verilog/core/riscv_if.sv
read_verilog -sv /var/jenkins_home/workspace/RV12/RV12/rtl/verilog/core/riscv_mem.sv
read_verilog -sv /var/jenkins_home/workspace/RV12/RV12/rtl/verilog/core/riscv_parcel_queue.sv
read_verilog -sv /var/jenkins_home/workspace/RV12/RV12/rtl/verilog/core/riscv_pd.sv
read_verilog -sv /var/jenkins_home/workspace/RV12/RV12/rtl/verilog/core/riscv_rf.sv
read_verilog -sv /var/jenkins_home/workspace/RV12/RV12/rtl/verilog/core/riscv_rsb.sv
read_verilog -sv /var/jenkins_home/workspace/RV12/RV12/rtl/verilog/core/riscv_state1.10.sv
read_verilog -sv /var/jenkins_home/workspace/RV12/RV12/rtl/verilog/core/riscv_state1.7.sv
read_verilog -sv /var/jenkins_home/workspace/RV12/RV12/rtl/verilog/core/riscv_state1.9.sv
read_verilog -sv /var/jenkins_home/workspace/RV12/RV12/rtl/verilog/core/riscv_state_20240411.sv
read_verilog -sv /var/jenkins_home/workspace/RV12/RV12/rtl/verilog/core/riscv_wb.sv
read_verilog -sv /var/jenkins_home/workspace/RV12/RV12/rtl/verilog/core/cache/riscv_cache_biu_ctrl.sv
read_verilog -sv /var/jenkins_home/workspace/RV12/RV12/rtl/verilog/core/cache/riscv_cache_memory.sv
read_verilog -sv /var/jenkins_home/workspace/RV12/RV12/rtl/verilog/core/cache/riscv_cache_setup.sv
read_verilog -sv /var/jenkins_home/workspace/RV12/RV12/rtl/verilog/core/cache/riscv_cache_tag.sv
read_verilog -sv /var/jenkins_home/workspace/RV12/RV12/rtl/verilog/core/cache/riscv_dcache_core.sv
read_verilog -sv /var/jenkins_home/workspace/RV12/RV12/rtl/verilog/core/cache/riscv_dcache_fsm.sv
read_verilog -sv /var/jenkins_home/workspace/RV12/RV12/rtl/verilog/core/cache/riscv_icache_core.sv
read_verilog -sv /var/jenkins_home/workspace/RV12/RV12/rtl/verilog/core/cache/riscv_icache_fsm.sv
read_verilog -sv /var/jenkins_home/workspace/RV12/RV12/rtl/verilog/core/cache/riscv_nodcache_core.sv
read_verilog -sv /var/jenkins_home/workspace/RV12/RV12/rtl/verilog/core/cache/riscv_noicache_core.sv
read_verilog -sv /var/jenkins_home/workspace/RV12/RV12/rtl/verilog/core/ex/riscv_alu.sv
read_verilog -sv /var/jenkins_home/workspace/RV12/RV12/rtl/verilog/core/ex/riscv_bu.sv
read_verilog -sv /var/jenkins_home/workspace/RV12/RV12/rtl/verilog/core/ex/riscv_div.sv
read_verilog -sv /var/jenkins_home/workspace/RV12/RV12/rtl/verilog/core/ex/riscv_lsu.sv
read_verilog -sv /var/jenkins_home/workspace/RV12/RV12/rtl/verilog/core/ex/riscv_mul.sv
read_verilog -sv /var/jenkins_home/workspace/RV12/RV12/rtl/verilog/core/memory/riscv_dmem_ctrl.sv
read_verilog -sv /var/jenkins_home/workspace/RV12/RV12/rtl/verilog/core/memory/riscv_imem_ctrl.sv
read_verilog -sv /var/jenkins_home/workspace/RV12/RV12/rtl/verilog/core/memory/riscv_membuf.sv
read_verilog -sv /var/jenkins_home/workspace/RV12/RV12/rtl/verilog/core/memory/riscv_memmisaligned.sv
read_verilog -sv /var/jenkins_home/workspace/RV12/RV12/rtl/verilog/core/memory/riscv_mmu.sv
read_verilog -sv /var/jenkins_home/workspace/RV12/RV12/rtl/verilog/core/memory/riscv_pmachk.sv
read_verilog -sv /var/jenkins_home/workspace/RV12/RV12/rtl/verilog/core/memory/riscv_pmpchk.sv
read_verilog -sv /var/jenkins_home/workspace/RV12/RV12/rtl/verilog/core/memory/riscv_wbuf.sv
read_verilog -sv /var/jenkins_home/workspace/RV12/RV12/rtl/verilog/core/mmu/riscv_nommu.sv
read_verilog -sv /eda/processor-ci-controller/modules/uart.sv
read_verilog /eda/processor-ci-controller/modules/UART/rtl/uart_rx.v
read_verilog /eda/processor-ci-controller/modules/UART/rtl/uart_tx.v

#read_verilog -sv /eda/processor-ci-controller/modules/spi.sv;
#read_verilog -sv /eda/processor-ci-controller/modules/SPI-Slave/rtl/spi_slave.sv;

read_verilog -sv /eda/processor_ci/internal/ahblite_to_wishbone.sv
read_verilog -sv /eda/processor_ci/internal/axi4_to_wishbone.sv
read_verilog -sv /eda/processor_ci/internal/axi4lite_to_wishbone.sv
read_verilog -sv /eda/processor-ci-controller/rtl/fifo.sv
read_verilog -sv /eda/processor-ci-controller/rtl/reset.sv
read_verilog -sv /eda/processor-ci-controller/rtl/clk_divider.sv
read_verilog -sv /eda/processor-ci-controller/rtl/memory.sv
read_verilog -sv /eda/processor-ci-controller/rtl/interpreter.sv
read_verilog -sv /eda/processor-ci-controller/rtl/controller.sv
read_verilog -sv /eda/processor-ci-controller/rtl/timer.sv
read_verilog -sv /eda/processor_ci/internal/fpga_top.sv

set_param general.maxThreads 16

read_xdc "/eda/processor_ci/constraints/digilent_arty_a7_100t.xdc"
set_property PROCESSING_ORDER EARLY [get_files /eda/processor_ci/constraints/digilent_arty_a7_100t.xdc]

# synth
synth_design -top "fpga_top" -part "xc7a100tcsg324-1"

# place and route
opt_design
place_design

report_utilization -hierarchical -file digilent_arty_a7_utilization_hierarchical_place.rpt
report_utilization               -file digilent_arty_a7_utilization_place.rpt
report_io                        -file digilent_arty_a7_io.rpt
report_control_sets -verbose     -file digilent_arty_a7_control_sets.rpt
report_clock_utilization         -file digilent_arty_a7_clock_utilization.rpt


route_design

report_timing_summary -no_header -no_detailed_paths
report_route_status                            -file digilent_arty_a7_route_status.rpt
report_drc                                     -file digilent_arty_a7_drc.rpt
report_timing_summary -datasheet -max_paths 10 -file digilent_arty_a7_timing.rpt
report_power                                   -file digilent_arty_a7_power.rpt


# write bitstream
write_bitstream -force "digilent_arty_a7_100t.bit"

exit