label clk clk clk_fast clk clk rst rst PC label #FFFFFF PC_in[31:0] PC_in[31:0] UNSIGNEDDECRADIX PC_out[31:0] PC_out[31:0] UNSIGNEDDECRADIX IF_ID_PC[31:0] IF_ID_PC[31:0] UNSIGNEDDECRADIX ID_EX_PC[31:0] ID_EX_PC[31:0] UNSIGNEDDECRADIX EX_MEM_PC[31:0] EX_MEM_PC[31:0] UNSIGNEDDECRADIX MEM_WB_PC[31:0] MEM_WB_PC[31:0] UNSIGNEDDECRADIX ctrls_part1[12:0] ctrls_part1[12:0] ctrls_part2[3:0] ctrls_part2[3:0] ctrls_part3[4:0] ctrls_part3[4:0] CSR label #E0FFFF ecall ecall ebreak ebreak interFlag interFlag interF interF ID_EX_EBreak ID_EX_EBreak ID_EX_ECall ID_EX_ECall ID_EX_MRET ID_EX_MRET ID_EX_interAddr[31:0] ID_EX_interAddr[31:0] UNSIGNEDDECRADIX csr_read[31:0] csr_read[31:0] csrAddr[11:0] csrAddr[11:0] HEXRADIX MEM_WB_CSRWrite MEM_WB_CSRWrite MEM_WB_RegR1[31:0] MEM_WB_RegR1[31:0] BINARYRADIX MEM_WB_CSRData[31:0] MEM_WB_CSRData[31:0] BINARYRADIX MEM_WB_CSRI MEM_WB_CSRI CSR[6:0][31:0] CSR[6:0][31:0] Branch Or PC Mux label #E0FFFF CompressedFlag CompressedFlag PC4_Or_Branch[31:0] PC4_Or_Branch[31:0] UNSIGNEDDECRADIX ID_EX_PC[31:0] ID_EX_PC[31:0] PC_Or_Branch[31:0] PC_Or_Branch[31:0] PC Src Mux label #E0FFFF sel[1:0] sel[1:0] in1[31:0] in1[31:0] in2[31:0] in2[31:0] in3[31:0] in3[31:0] out[31:0] out[31:0] HEXRADIX MEM Address MUX label #E0FFFF MEMORY label #E0FFFF memMuxOut[31:0] memMuxOut[31:0] UNSIGNEDDECRADIX Mem_out[31:0] Mem_out[31:0] mem[4095:0][7:0] mem[4095:0][7:0] IF_ID Reg label #E0FFFF IF_ID_InstOut[31:0] IF_ID_InstOut[31:0] Stages Regs label #E0FFFF ID_EX_PC[31:0] ID_EX_PC[31:0] Register label #E0FFFF clk clk MEM_WB_CSRWrite MEM_WB_CSRWrite MEM_WB_csr_read[31:0] MEM_WB_csr_read[31:0] RegW[31:0] RegW[31:0] UNSIGNEDDECRADIX WriteEn WriteEn regsrc[4:0] regsrc[4:0] UNSIGNEDDECRADIX rs2[4:0] rs2[4:0] RegR1[31:0] RegR1[31:0] RegR2[31:0] RegR2[31:0] xs[31:0][31:0] xs[31:0][31:0] [31][31:0] [31][31:0] [30][31:0] [30][31:0] [29][31:0] [29][31:0] [28][31:0] [28][31:0] [27][31:0] [27][31:0] [26][31:0] [26][31:0] [25][31:0] [25][31:0] [24][31:0] [24][31:0] [23][31:0] [23][31:0] [22][31:0] [22][31:0] [21][31:0] [21][31:0] [20][31:0] [20][31:0] [19][31:0] [19][31:0] [18][31:0] [18][31:0] [17][31:0] [17][31:0] [16][31:0] [16][31:0] [15][31:0] [15][31:0] [14][31:0] [14][31:0] [13][31:0] [13][31:0] [12][31:0] [12][31:0] [11][31:0] [11][31:0] [10][31:0] [10][31:0] [9][31:0] [9][31:0] [8][31:0] [8][31:0] [7][31:0] [7][31:0] [6][31:0] [6][31:0] [5][31:0] [5][31:0] [4][31:0] [4][31:0] [3][31:0] [3][31:0] [2][31:0] [2][31:0] UNSIGNEDDECRADIX [1][31:0] [1][31:0] [0][31:0] [0][31:0] [31][31:0] [31][31:0] [30][31:0] [30][31:0] [29][31:0] [29][31:0] [28][31:0] [28][31:0] [27][31:0] [27][31:0] [26][31:0] [26][31:0] [25][31:0] [25][31:0] [24][31:0] [24][31:0] [23][31:0] [23][31:0] [22][31:0] [22][31:0] [21][31:0] [21][31:0] [20][31:0] [20][31:0] [19][31:0] [19][31:0] [18][31:0] [18][31:0] [17][31:0] [17][31:0] [16][31:0] [16][31:0] [15][31:0] [15][31:0] [14][31:0] [14][31:0] [13][31:0] [13][31:0] [12][31:0] [12][31:0] [11][31:0] [11][31:0] [10][31:0] [10][31:0] [9][31:0] [9][31:0] [8][31:0] [8][31:0] [7][31:0] [7][31:0] [6][31:0] [6][31:0] [5][31:0] [5][31:0] [4][31:0] [4][31:0] [3][31:0] [3][31:0] [2][31:0] [2][31:0] [1][31:0] [1][31:0] [0][31:0] [0][31:0] RegFile MUX label #E0FFFF Write Back MUX label #E0FFFF ALU label #E0FFFF fwdA[1:0] fwdA[1:0] fwdB[1:0] fwdB[1:0] ID_EX_RegR1[31:0] ID_EX_RegR1[31:0] UNSIGNEDDECRADIX ALUSrcMux_out[31:0] ALUSrcMux_out[31:0] UNSIGNEDDECRADIX ALU_OprandA[31:0] ALU_OprandA[31:0] UNSIGNEDDECRADIX ALU_OprandB[31:0] ALU_OprandB[31:0] UNSIGNEDDECRADIX ALU_out[31:0] ALU_out[31:0] HEXRADIX ALU Control label #E0FFFF Branch label #E0FFFF branchTaken branchTaken Control Unit label #E0FFFF instr[31:0] instr[31:0] opcode[4:0] opcode[4:0] Branch Branch Jump[1:0] Jump[1:0] MemRead MemRead MemToReg MemToReg ALUOp[1:0] ALUOp[1:0] MemWrite MemWrite ALUSrc ALUSrc RegWrite RegWrite Mode[2:0] Mode[2:0] Lui Lui ECall ECall EBreak EBreak MRET MRET CSRWrite CSRWrite [1] [1] [4] [4] [7] [7]