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** © Copyright 2009 Xilinx, Inc. All rights reserved.
** This file contains confidential and proprietary information of Xilinx, Inc. and 
** is protected under U.S. and international copyright and other intellectual property laws.
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**   ____  ____ 
**  /   /\/   / 
** /___/  \  /   Vendor: Xilinx 
** \   \   \/    
**  \   \        readme.txt Version: 1.1  
**  /   /        Date Last Modified:  
** /___/   /\    Date Created: 
** \   \  /  \   Associated Filename: <rdf0041.zip>
**  \___\/\___\ 
** 
**  Device: Virtex-6 FPGA
**  Purpose: ML605 user constraints file (UCF).
**  Reference: 
**  Revision History: v1.1, ML605
**   
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**
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** IMPORTANT NOTES **

This is to provide information for the Virtex-6 FPGA ML605 Evaluation Kit. The zip file contains:

1. ML605 Master UCF file: ML605.ucf
2. This readme file

The UCF template is provided for designs targeted to ML605. Net names provided in the constraints correlate with net names on the ML605 schematic. On identifying the appropriate pins, replace the net names in the UCF with net names in your RTL.





