--- mig39/mig_39/user_design/rtl/mig_39.vhd	2012-12-20 08:13:08.000000000 +0100
+++ mig39_copy/mig_39/user_design/rtl/mig_39.vhd	2012-12-20 08:19:50.487825838 +0100
@@ -65,7 +65,7 @@
 --*****************************************************************************
 library ieee;
 use ieee.std_logic_1164.all;
-entity mig_39 is
+entity mig_38 is
 generic
   (
             C3_P0_MASK_SIZE           : integer := 4;
@@ -165,11 +165,13 @@
    c3_p2_rd_empty                          : out std_logic;
    c3_p2_rd_count                          : out std_logic_vector(6 downto 0);
    c3_p2_rd_overflow                       : out std_logic;
-   c3_p2_rd_error                          : out std_logic
+   c3_p2_rd_error                          : out std_logic;
+   clk_125                                 : out std_logic;
+   clk_50                                  : out std_logic
   );
-end mig_39;
+end mig_38;
 
-architecture arc of mig_39 is
+architecture arc of mig_38 is
 
  
 component memc3_infrastructure is
@@ -198,8 +200,9 @@
       pll_ce_0                               : out   std_logic;
       pll_ce_90                              : out   std_logic;
       pll_lock                               : out   std_logic;
-      mcb_drp_clk                            : out   std_logic
-
+      mcb_drp_clk                            : out std_logic;
+      clk_125                                : out std_logic;
+      clk_50                                 : out std_logic
       );
   end component;
 
@@ -363,8 +366,8 @@
    constant C3_CLKOUT1_DIVIDE       : integer := 1; 
    constant C3_CLKOUT2_DIVIDE       : integer := 16; 
    constant C3_CLKOUT3_DIVIDE       : integer := 8; 
-   constant C3_CLKFBOUT_MULT        : integer := 2; 
-   constant C3_DIVCLK_DIVIDE        : integer := 1; 
+   constant C3_CLKFBOUT_MULT        : integer := 2*5; 
+   constant C3_DIVCLK_DIVIDE        : integer := 1*3; 
    constant C3_INCLK_PERIOD         : integer := ((C3_MEMCLK_PERIOD * C3_CLKFBOUT_MULT) / (C3_DIVCLK_DIVIDE * C3_CLKOUT0_DIVIDE * 2)); 
    constant C3_ARB_NUM_TIME_SLOTS   : integer := 12; 
    constant C3_ARB_TIME_SLOT_0      : bit_vector(5 downto 0) := o"02"; 
@@ -487,7 +490,9 @@
    pll_ce_0                        => c3_pll_ce_0,
    pll_ce_90                       => c3_pll_ce_90,
    pll_lock                        => c3_pll_lock,
-   mcb_drp_clk                     => c3_mcb_drp_clk
+   mcb_drp_clk                     => c3_mcb_drp_clk,
+   clk_125                         => clk_125,
+   clk_50                          => clk_50
    );
 
  
