This LEON design is tailored to the Digilent Nexys Video board
---------------------------------------------------------

Simulation and synthesis
------------------------

The design currently supports synthesis with Xilinx Vivado (tested
with Vivado 2017.1).

The XILINX_VIVADO variable must be exported for the mig_7series target
to work correctly: export XILINX_VIVADO

If enabled by the user, the design uses the Xilinx MIG memory
interface with an AHB-2.0 interface (experimental).  The MIG source
code cannot be distributed due to the prohibitive Xilinx license, so
the MIG must be re-generated with coregen before simulation and
synthesis can be done.

Xilinx MIG interface will automatically be generated when Vivado is
launched.

To simulate using XSIM and run systest.c on the Leon design using the
memory controller from Xilinx use the make targets:

  make soft
  make vivado-launch

To simulate using Modelsim/Aldec and run systest.c on the Leon design using 
the memory controller from Xilinx use the make targets:

  make map_xilinx_7series_lib
  make sim
  make mig_7series (only required if Xilinx MIG is enabled via xconfig)
  make soft
  make sim-launch

To simulate using Aldec Riviera use the following make targets:

  make map_xilinx_7series_lib
  make riviera
  make mig_series7 (only required if Xilinx MIG is enabled via xconfig)
  make soft
  make riviera-launch

To synthesize the design, do

  make vivado (or make vivado-launch for the GUI flow)

Finally, to program the FPGA:
  
  make vivado-prog-fpga


Design specifics
----------------
* The default configuration sets the system frequency to 70 MHz.

* The AHB clock is generated by the MMCM module in the MIG
  controller, and can be controlled via Coregen. When the 
  MIG DDR2 controller isn't present the AHB clock is generated
  from CLKGEN, and can be controlled via xconfig

* In order to connect through the USB JTAG-interface run "grmon -digilent".

* System reset is mapped to the CPU RESET button

* LED 0/1 indicate USB-UART RX/TX activity. (Connected to Debug UART)

* LED 2 DSU Debug Mode

* LED 3 indicate processor in error mode

* LED 4 indicate the end of the calibration phase for the memory controller

* The application UART1 is unconnected. To enable it, uncomment the in/out
  pads for the apbuart and comment out the ahbuart pads.

* The JTAG DSU interface is enabled and accessible via the USB/JTAG port
  and USB/UART.
  Start grmon with -digilent to connect with USB/JTAG.

* The on-board SPI-Flash memory is interfaced through the Gaisler SPI
  memory controller, and it is mapped at address 0x0.  By default, the
  simulation assumes that the boot-code is read from the SPI-Flash.
  To enable it issue "make xconfig" and set the SPI Memory controller
  tab. The following configuration has been tested on hardware:

- Enable SD card support:              No
- Read instruction:                    0B
- Dummy byte:                          No
- Dual output:                         No
- Address offset:                      0
- Clock divisor for device clock:      2
- Clock divisor for alt. device clock: 2

* Ethernet is only supported in 10/100Mbit mode. 

Example GRMON2 session:


-bash-4.1$ grmon2cli -digilent -u

  GRMON2 LEON debug monitor v2.0.70 32-bit internal version
  
  Copyright (C) 2016 Cobham Gaisler - All rights reserved.
  For latest updates, go to http://www.gaisler.com/
  Comments or bug-reports to support@gaisler.com
  
 JTAG chain (1): xc7a200t 

  GRLIB build version: 4162
  Detected frequency:  100 MHz
  
  Component                            Vendor
  LEON3 SPARC V8 Processor             Cobham Gaisler
  AHB Debug UART                       Cobham Gaisler
  JTAG Debug Link                      Cobham Gaisler
  AHB/APB Bridge                       Cobham Gaisler
  LEON3 Debug Support Unit             Cobham Gaisler
  Xilinx MIG DDR2 Controller           Cobham Gaisler
  SPI Memory Controller                Cobham Gaisler
  Generic UART                         Cobham Gaisler
  Multi-processor Interrupt Ctrl.      Cobham Gaisler
  Modular Timer Unit                   Cobham Gaisler
  
  Use command 'info sys' to print a detailed report of attached cores

grmon2> load ~/tests/hello
  40000000 .text                     39.0kB /  39.0kB   [===============>] 100%
  40009C20 .data                      2.9kB /   2.9kB   [===============>] 100%
  Total size: 41.90kB (446.38kbit/s)
  Entry point 0x40000000
  Image /home/jan/tests/hello loaded
  
grmon2> verify ~/tests/hello
  40000000 .text                     39.0kB /  39.0kB   [===============>] 100%
  40009C20 .data                      2.9kB /   2.9kB   [===============>] 100%
  Total size: 41.90kB (446.38kbit/s)
  Entry point 0x40000000
  Image of /home/jan/tests/hello verified without errors
  
grmon2> run
Hello world!
  
  Program exited normally.
  
grmon2> info sys
  cpu0      Cobham Gaisler  LEON3 SPARC V8 Processor    
            AHB Master 0
  ahbuart0  Cobham Gaisler  AHB Debug UART    
            AHB Master 1
            APB: 80000700 - 80000800
            Baudrate 115200, AHB frequency 100.00 MHz
  ahbjtag0  Cobham Gaisler  JTAG Debug Link    
            AHB Master 2
  apbmst0   Cobham Gaisler  AHB/APB Bridge    
            AHB: 80000000 - 80100000
  dsu0      Cobham Gaisler  LEON3 Debug Support Unit    
            AHB: 90000000 - A0000000
            AHB trace: 64 lines, 32-bit bus
            CPU0:  win 8, hwbp 2, itrace 64, V8 mul/div, lddel 1
                   stack pointer 0x47fffff0
                   icache 4 * 4 kB, 32 B/line, rnd
                   dcache 4 * 4 kB, 32 B/line, rnd
  mig0      Cobham Gaisler  Xilinx MIG DDR2 Controller    
            AHB: 40000000 - 48000000
            APB: 80000500 - 80000600
            SDRAM: 128 Mbyte
  spim0     Cobham Gaisler  SPI Memory Controller    
            AHB: FFF70000 - FFF70100
            AHB: 00000000 - 01000000
            IRQ: 7
            SPI memory device read command: 0x0b
  uart0     Cobham Gaisler  Generic UART    
            APB: 80000100 - 80000200
            IRQ: 2
            Baudrate 38343, FIFO debug mode
  irqmp0    Cobham Gaisler  Multi-processor Interrupt Ctrl.    
            APB: 80000200 - 80000300
  gptimer0  Cobham Gaisler  Modular Timer Unit    
            APB: 80000300 - 80000400
            IRQ: 8
            8-bit scalar, 2 * 32-bit timers, divisor 100
  
grmon2> 
