##############################################################
#
# Xilinx Core Generator version 13.2
# Date: Fri May 11 12:21:06 2012
#
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#
#  This file contains the customisation parameters for a
#  Xilinx CORE Generator IP GUI. It is strongly recommended
#  that you do not manually alter this file as it may cause
#  unexpected and unsupported behavior.
#
##############################################################
#
#  Generated from component: xilinx.com:ip:s6_pcie:1.4
#
##############################################################
#
# BEGIN Project Options
SET addpads = false
SET asysymbol = true
SET busformat = BusFormatParenNotRipped
SET createndf = false
SET designentry = VHDL
SET device = xc6slx45t
SET devicefamily = spartan6
SET flowvendor = Synplicity
SET formalverification = false
SET foundationsym = false
SET implementationfiletype = Ngc
SET package = fgg484
SET removerpms = false
SET simulationfiles = Behavioral
SET speedgrade = -3
SET verilogsim = false
SET vhdlsim = true
# END Project Options
# BEGIN Select
SELECT Spartan-6_Integrated_Block_for_PCI_Express family Xilinx,_Inc. 1.4
# END Select
# BEGIN Parameters
CSET acceptable_l0_latency=No_limit
CSET acceptable_l1_latency=No_limit
CSET bar0_64bit=false
CSET bar0_enabled=true
CSET bar0_prefetchable=false
CSET bar0_scale=Megabytes
CSET bar0_size=2
CSET bar0_type=Memory
CSET bar1_64bit=false
CSET bar1_enabled=false
CSET bar1_prefetchable=false
CSET bar1_scale=Bytes
CSET bar1_size=1
CSET bar1_type=N/A
CSET bar2_64bit=false
CSET bar2_enabled=false
CSET bar2_prefetchable=false
CSET bar2_scale=Bytes
CSET bar2_size=128
CSET bar2_type=N/A
CSET bar3_64bit=false
CSET bar3_enabled=false
CSET bar3_prefetchable=false
CSET bar3_scale=Bytes
CSET bar3_size=1
CSET bar3_type=N/A
CSET bar4_64bit=false
CSET bar4_enabled=false
CSET bar4_prefetchable=false
CSET bar4_scale=Bytes
CSET bar4_size=1
CSET bar4_type=N/A
CSET bar5_enabled=false
CSET bar5_prefetchable=false
CSET bar5_scale=Kilobytes
CSET bar5_size=1
CSET bar5_type=N/A
CSET base_class_menu=Simple_communication_controllers
CSET cardbus_cis_pointer=00000000
CSET class_code_base=05
CSET class_code_interface=00
CSET class_code_sub=00
CSET component_name=s6_pcie_v1_4
CSET cpl_finite=false
CSET d0_pme_support=true
CSET d0_power_consumed=0
CSET d0_power_consumed_factor=0
CSET d0_power_dissipated=0
CSET d0_power_dissipated_factor=0
CSET d1_pme_support=true
CSET d1_power_consumed=0
CSET d1_power_consumed_factor=0
CSET d1_power_dissipated=0
CSET d1_power_dissipated_factor=0
CSET d1_support=true
CSET d2_pme_support=true
CSET d2_power_consumed=0
CSET d2_power_consumed_factor=0
CSET d2_power_dissipated=0
CSET d2_power_dissipated_factor=0
CSET d2_support=true
CSET d3_power_consumed=0
CSET d3_power_consumed_factor=0
CSET d3_power_dissipated=0
CSET d3_power_dissipated_factor=0
CSET d3hot_pme_support=true
CSET device_id=0007
CSET device_port_type=PCI_Express_Endpoint_device
CSET device_specific_initialization=false
CSET dsn_enabled=true
CSET enable_aspm_l1_support=false
CSET enable_slot_clock_cfg=true
CSET expansion_rom_enabled=false
CSET expansion_rom_scale=Kilobytes
CSET expansion_rom_size=2
CSET expose_unused_transceiver_ports=false
CSET ext_pci_cfg_space=false
CSET extended_tag_field=false
CSET force_no_scrambling=false
CSET gt_channel=Channel_0
CSET gt_loc=X0Y0
CSET legacy_interrupt=INTA
CSET max_payload_size=128_bytes
CSET multiple_message_capable=1_vector
CSET override_low_latency=false
CSET pci_cfg_space=false
CSET perf_level=Good
CSET phantom_functions=No_function_number_bits_used
CSET ref_clk_freq=125_MHz
CSET revision_id=00
CSET sub_class_interface_menu=Generic_XT_compatible_serial_controller
CSET subsystem_id=0007
CSET subsystem_vendor_id=10EE
CSET trans_buf_pipeline=None
CSET trim_tlp_digest=false
CSET vendor_id=10EE
CSET xlnx_ref_board=SP605_Rev_A-D
# END Parameters
GENERATE
# CRC: 4655bf03
