## This file is a general .ucf for the Anvyl board adapted to GRLIB/Leon3.

##Clock Signal 100MHz
NET "clk"	LOC=D11 |	IOSTANDARD = "LVCMOS33";
NET "clk" TNM_NET = sys_clk_pin;
TIMESPEC TS_sys_clk_pin = PERIOD sys_clk_pin 100000 kHz;

# ==== Ethernet PHY timing constraints ====
NET "PhyClk50Mhz"	LOC=C12	|	IOSTANDARD=LVCMOS33;			#Bank = 0, pin name = IO_L37N_GCLK12_0,					Sch name = ETH-REFCLK
NET "PhyClk50Mhz" TNM_NET = PhyClk50Mhz;
TIMESPEC TS_PhyClk50Mhz = PERIOD PhyClk50Mhz 50 MHz HIGH 50%;
OFFSET = IN 15 ns VALID 16.4 ns BEFORE "PhyClk50Mhz" RISING;
OFFSET = OUT 7 VALID 9 ns BEFORE "PhyClk50Mhz" RISING;

# ==== Internal timing constraints ====
# Avoid problems with internal reset signal.
NET "resetn"    TNM_NET = FFS "rstintff" ;
TIMESPEC "TS_rstint_tig" = FROM "rstintff" TIG ;

# VGA pixel clock is asynchronous to system clock.
NET "clkm"          TNM_NET = "clkm" ;
NET "video_clk"     TNM_NET = "video_clk" ;
TIMESPEC "TS_video_clk"     = PERIOD "video_clk" 20 ns PRIORITY 1 ;
TIMESPEC "TS_clkm_videoclk" = FROM "clkm" TO "video_clk" 10 ns DATAPATHONLY ;
TIMESPEC "TS_videoclk_clkm" = FROM "video_clk" TO "clkm" 10 ns DATAPATHONLY ;

# TMDS signals are passed asynchronously to serializer.
NET "video_fastclk" TNM_NET = "video_fastclk" ;
TIMESPEC "TS_video_fastclk" = PERIOD "video_fastclk" 5 ns PRIORITY 1 ;
TIMESPEC "TS_video_clk_fastclk" = FROM "video_clk" TO "video_fastclk" 5 ns DATAPATHONLY ;

##Switches
NET "switch<0>"	LOC= V5	|	IOSTANDARD=LVCMOS18;		#Bank = 3, pin name = IO_L13N_3,	Sch name = SW0
NET "switch<1>"	LOC= U4	|	IOSTANDARD=LVCMOS18;		#Bank = 3, pin name = IO_L18P_3,	Sch name = SW1
NET "switch<2>"	LOC= V3	|	IOSTANDARD=LVCMOS18;		#Bank = 3, pin name = IO_L18N_3,	Sch name = SW2
NET "switch<3>"	LOC= P4	|	IOSTANDARD=LVCMOS18;		#Bank = 3, pin name = IO_L21P_3,	Sch name = SW3
NET "switch<4>"	LOC= R4	|	IOSTANDARD=LVCMOS18;		#Bank = 3, pin name = IO_L21N_3,	Sch name = SW4
NET "switch<5>"	LOC= P6	|	IOSTANDARD=LVCMOS18;		#Bank = 3, pin name = IO_L22P_3,	Sch name = SW5
NET "dsubre"	LOC= P5	|	IOSTANDARD=LVCMOS18;		#Bank = 3, pin name = IO_L22N_3,	Sch name = SW6
NET "dsuen"	LOC= P8	|	IOSTANDARD=LVCMOS18;		#Bank = 3, pin name = IO_L23P_3,	Sch name = SW7

## LEDs
NET "led<0>"	LOC=W3	|	IOSTANDARD=LVCMOS18;		#Bank = 3, pin name = IO_L9P_3,		Sch name = LD0
NET "led<1>"	LOC=Y4	|	IOSTANDARD=LVCMOS18;		#Bank = 3, pin name = IO_L7N_3,		Sch name = LD1
NET "led<2>"	LOC=Y1	|	IOSTANDARD=LVCMOS18;		#Bank = 3, pin name = IO_L2N_3,		Sch name = LD2
NET "led<3>"	LOC=Y3	|	IOSTANDARD=LVCMOS18;		#Bank = 3, pin name = IO_L8P_3,		Sch name = LD3
NET "led<4>"	LOC=AB4	|	IOSTANDARD=LVCMOS18;		#Bank = 3, pin name = IO_L12N_3,	Sch name = LD4
NET "led<5>"	LOC=W1	|	IOSTANDARD=LVCMOS18;		#Bank = 3, pin name = IO_L9N_3,		Sch name = LD5
NET "dsuact"	LOC=AB3	|	IOSTANDARD=LVCMOS18;		#Bank = 3, pin name = IO_L8N_3,		Sch name = LD6
NET "errorn"	LOC=AA4	|	IOSTANDARD=LVCMOS18;		#Bank = 3, pin name = IO_L12P_3,	Sch name = LD7

## GYR LEDs
NET "gyrled(0)"	LOC="T7"	|	IOSTANDARD = LVCMOS18;	#Bank = 3, pin name = IO_L10N_3,		Sch name = LDT1-G
NET "gyrled(1)"	LOC="W4"	|	IOSTANDARD = LVCMOS18;	#Bank = 3, pin name = IO_L7P_3,			Sch name = LDT1-Y
NET "gyrled(2)"	LOC="U8"	|	IOSTANDARD = LVCMOS18;	#Bank = 3, pin name = IO_L10P_3,		Sch name = LDT1-R
NET "gyrled(3)"	LOC="R7"	|	IOSTANDARD = LVCMOS18;	#Bank = 3, pin name = IO_L11N_3,		Sch name = LDT2-G
NET "gyrled(4)"	LOC="U6"	|	IOSTANDARD = LVCMOS18;	#Bank = 3, pin name = IO_L13P_3,		Sch name = LDT2-Y
NET "gyrled(5)"	LOC="T8"	|	IOSTANDARD = LVCMOS18;	#Bank = 3, pin name = IO_L11P_3,		Sch name = LDT2-R

## Buttons
NET "button(0)"	LOC = E6		|	IOSTANDARD=LVCMOS18;		#Bank = 3, pin name = IO_L82P_3,	Sch name = BTN0
NET "button(1)"	LOC = D5		|	IOSTANDARD=LVCMOS18; 		#Bank = 3, pin name = IO_L82N_3,	Sch name = BTN1
NET "button(2)"	LOC = A3		|	IOSTANDARD=LVCMOS18;		#Bank = 3, pin name = IO_L83P_3,	Sch name = BTN2
NET "resetn"	LOC = AB9	|	IOSTANDARD=LVCMOS33;

## 7 Segment Display
	#NET "SEG[0]"	LOC=AA21	|	IOSTANDARD=LVCMOS33;			#Bank = 1, pin name = IO_L63P_1,	Sch name = 7SD-AA
	#NET "SEG[1]"	LOC=AA22	|	IOSTANDARD=LVCMOS33;			#Bank = 1, pin name = IO_L63N_1,	Sch name = 7SD-AB
	#NET "SEG[2]"	LOC=Y22	|	IOSTANDARD=LVCMOS33;			#Bank = 1, pin name = IO_L59N_1,	Sch name = 7SD-AC
	#NET "SEG[3]"	LOC=N15	|	IOSTANDARD=LVCMOS33;			#Bank = 1, pin name = IO_L60P_1,	Sch name = 7SD-AD
	#NET "SEG[4]"	LOC=AB19	|	IOSTANDARD=LVCMOS33;			#Bank = 1, pin name = IO_L65P_1,	Sch name = 7SD-AE
	#NET "SEG[5]"	LOC=P20	|	IOSTANDARD=LVCMOS33;			#Bank = 1, pin name = IO_L64N_1,	Sch name = 7SD-AF
	#NET "SEG[6]"	LOC=Y21	|	IOSTANDARD=LVCMOS33;			#Bank = 1, pin name = IO_L59P_1,	Sch name = 7SD-AG

	#NET dp	LOC=P15	|	IOSTANDARD=LVCMOS33;					#Bank = 1, pin name = IO_L62P_1,	Sch name = 7SD-DP

	#NET "AN[1]"	LOC = P16		|	IOSTANDARD=LVCMOS33;		#Bank = 1, pin name = IO_L62N_1,	Sch name = 7SD-C1
	#NET "AN[0]"	LOC = M17		|	IOSTANDARD=LVCMOS33;		#Bank = 1, pin name = IO_L58N_1,	Sch name = 7SD-C2
	#NET "AN[3]"	LOC = N16		|	IOSTANDARD=LVCMOS33;		#Bank = 1, pin name = IO_L60N_1,	Sch name = 7SD-C3
	#NET "AN[2]"	LOC = P19		|	IOSTANDARD=LVCMOS33;		#Bank = 1, pin name = IO_L64P_1,	Sch name = 7SD-C4
	#NET "AN[5]"	LOC = AA20	|	IOSTANDARD=LVCMOS33;		#Bank = 1, pin name = IO_L61P_1,	Sch name = 7SD-C5
	#NET "AN[4]"	LOC = AB21	|	IOSTANDARD=LVCMOS33;		#Bank = 1, pin name = IO_L61N_1,	Sch name = 7SD-C6
	
## DIP Switches
NET "dipswitch(0)"	LOC = G6	|	IOSTANDARD=LVCMOS18; 		#Bank = 3, pin name = IO_L74P_3,	Sch name = DIPA-1
NET "dipswitch(1)"	LOC = G4	|	IOSTANDARD=LVCMOS18; 		#Bank = 3, pin name = IO_L74N_3,	Sch name = DIPA-2
NET "dipswitch(2)"	LOC = F5	|	IOSTANDARD=LVCMOS18; 		#Bank = 3, pin name = IO_L75P_3,	Sch name = DIPA-3
NET "dipswitch(3)"	LOC = E5	|	IOSTANDARD=LVCMOS18; 		#Bank = 3, pin name = IO_L75N_3,	Sch name = DIPA-4
NET "dipswitch(4)"	LOC = F8	|	IOSTANDARD=LVCMOS18; 		#Bank = 3, pin name = IO_L80P_3,	Sch name = DIPB-1
NET "dipswitch(5)"	LOC = F7	|	IOSTANDARD=LVCMOS18; 		#Bank = 3, pin name = IO_L80N_3,	Sch name = DIPB-2
NET "dipswitch(6)"	LOC = C4	|	IOSTANDARD=LVCMOS18; 		#Bank = 3, pin name = IO_L81P_3,	Sch name = DIPB-3
NET "dipswitch(7)"	LOC = D3	|	IOSTANDARD=LVCMOS18; 		#Bank = 3, pin name = IO_L81N_3,	Sch name = DIPB-4

## Keypad
	#NET "KYPD_COL[0]"	LOC = H8	|	IOSTANDARD=LVCMOS18;			#Bank = 3, pin name = IO_L58P_3,	Sch name = COL1
	#NET "KYPD_COL[1]"	LOC = J7	|	IOSTANDARD=LVCMOS18;			#Bank = 3, pin name = IO_L58N_3,	Sch name = COL2
	#NET "KYPD_COL[2]"	LOC = K8	|	IOSTANDARD=LVCMOS18;			#Bank = 3, pin name = IO_L59P_3,	Sch name = COL3
	#NET "KYPD_COL[3]"	LOC = K7	|	IOSTANDARD=LVCMOS18;			#Bank = 3, pin name = IO_L59N_3,	Sch name = COL4
	
	#NET "KYPD_ROW[0]"	LOC = E4	|	IOSTANDARD=LVCMOS18;		#Bank = 3, pin name = IO_L60P_3,	Sch name = ROW1
	#NET "KYPD_ROW[1]"	LOC = F3	|	IOSTANDARD=LVCMOS18;		#Bank = 3, pin name = IO_L60N_3,	Sch name = ROW2
	#NET "KYPD_ROW[2]"	LOC = G8	|	IOSTANDARD=LVCMOS18;		#Bank = 3, pin name = IO_L73P_3,	Sch name = ROW3
	#NET "KYPD_ROW[3]"	LOC = G7	|	IOSTANDARD=LVCMOS18; 		#Bank = 3, pin name = IO_L73N_3,	Sch name = ROW4

## OLED
	#NET	"OLED_SDIN"	LOC = C8		|	IOSTANDARD=LVCMOS33;		#Bank = 0, pin name = IO_L7N_0,	Sch name = OLED-SDIN
	#NET	"OLED_SCLK"	LOC = D7	|	IOSTANDARD=LVCMOS33;		#Bank = 0, pin name = IO_L7P_0,	Sch name = OLED-SCLK
	#NET	"OLED_DC"	LOC=A8			|	IOSTANDARD=LVCMOS33;		#Bank = 0, pin name = IO_L6N_0,	Sch name = OLED-DC
	#NET	"OLED_RES"	LOC=B8			|	IOSTANDARD=LVCMOS33;		#Bank = 0, pin name = IO_L6P_0,	Sch name = OLED-RES
	#NET	"OLED_VBAT"	LOC=C7		|	IOSTANDARD=LVCMOS33;		#Bank = 0, pin name = IO_L5P_0,	Sch name = OLED-VBAT
	#NET	"OLED_VDD"	LOC=A7			|	IOSTANDARD=LVCMOS33;		#Bank = 0, pin name = IO_L5N_0,	Sch name = OLED-VDD
	
## IIC
	#NET	"IIC_SDA"	LOC=C5	|	PULLUP	|	IOSTANDARD=LVCMOS33;		#Bank = 0, pin name = IO_L1N_VREF_0,	Sch name = SCL
	#NET	"IIC_SCL"	LOC=A4	|	PULLUP	|	IOSTANDARD=LVCMOS33;		#Bank = 0, pin name = IO_L2P_0,				Sch name = SDA

## AUDIO
	#NET "AC_PLAYBACKDATA"	LOC=A5			|	IOSTANDARD=LVCMOS33; 		#Bank = 0, pin name = IO_L2N_0,						Sch name = AC-PBDAT
	#NET "AC_PLAYBACKLRC" 	LOC=D6			|	IOSTANDARD=LVCMOS33; 		#Bank = 0, pin name = IO_L3P_0,						Sch name = AC-PBLRC	#DAC Playback sampling rate clock
	#NET	"AC_RECDATA"				LOC=C6			|	IOSTANDARD=LVCMOS33;		#Bank = 0, pin name = IO_L3N_0,						Sch name = AC-RECDAT
	#NET	"AC_RECLRC"				LOC=B6			|	IOSTANDARD=LVCMOS33;		#Bank = 0, pin name = IO_L4P_0,						Sch name = AC-RECLRC	#ADC Recording sampling rate clock
	#NET "AC_BCLK" 					LOC=B120		|	IOSTANDARD=LVCMOS33;		#Bank = 0, pin name = IO_L36P_GCLK15_0,	Sch name = AC-BCLK
	#NET "AC_CLKO"					LOC=C11		|	IOSTANDARD=LVCMOS33;		#Bank = 0, pin name = IO_L35P_GCLK17_0,	Sch name = AC-CLKO	# MCLK IN FROM CODEC
	#NET "AC_MUTE"					LOC=A15		|	IOSTANDARD=LVCMOS33;		#Bank = 0, pin name = IO_L62N_VREF_0,		Sch name = AC-MUTE	# mute
	#NET "AC_MCLK"					LOC=A6			|	IOSTANDARD=LVCMOS33;		#Bank = 0, pin name = IO_L4N_0,						Sch name = AC-MCLK

## USB
NET "kbd_clk"	LOC=A12	| IOSTANDARD=LVCMOS33 | PULLUP; #Bank = 0, pin name = IO_L36N_GCLK14_0,	Sch name = USBH1-SCK1
NET "kbd_data"	LOC=B16	| IOSTANDARD=LVCMOS33 | PULLUP; #Bank = 0, pin name = IO_L63P_SCP7_0, Sch name = USBH1-SDI1

#NET "USB1_SDO"	LOC=A16 | IOSTANDARD=LVCMOS33; #Bank = 0, pin name = IO_L63N_SCP6_0, Sch name = USBH1-SDO1
#NET "USB1_SS"	LOC=C17	| IOSTANDARD=LVCMOS33; #Bank = 0, pin name = IO_L64P_SCP5_0, Sch name = USBH1-SS1
	
NET "mou_clk"	LOC=K17	| IOSTANDARD=LVCMOS33 | PULLUP ; #Bank = 1, pin name = IO_L40N_GCLK10_M1A6_1,	Sch name = USBH2-CLK
NET "mou_data"	LOC=L17	| IOSTANDARD=LVCMOS33 | PULLUP ; #Bank = 1, pin name = IO_L40P_GCLK11_M1A5_1,	Sch name = USBH2-DATA

## RS232
NET "txd1"	LOC =T20		| 	IOSTANDARD = "LVCMOS33";
NET "rxd1"	LOC =T19 		| 	IOSTANDARD = "LVCMOS33";
	
## HDMI
NET "tmdstx_dat_p[0]" 	LOC=D10	| IOSTANDARD=TMDS_33;	#Bank = 0, pin name = IO_L33P_0,		Sch name = HDMI-TX-0 P
NET "tmdstx_dat_p[1]" 	LOC=C9	| IOSTANDARD=TMDS_33;	#Bank = 0, pin name = IO_L8P_0,			Sch name = HDMI-TX-1 P
NET "tmdstx_dat_p[2]"	LOC=D9	| IOSTANDARD=TMDS_33;	#Bank = 0, pin name = IO_L32P_0,		Sch name = HDMI-TX-2 P
NET "tmdstx_clk_p"	LOC=B10	| IOSTANDARD=TMDS_33;	#Bank = 0, pin name = IO_L34P_GCLK19_0,		Sch name = HDMI-TX-CLK P
NET "tmdstx_dat_n[0]"	LOC=C10	| IOSTANDARD=TMDS_33;	#Bank = 0, pin name = IO_L33N_0,		Sch name = HDMI-TX-0 N
NET "tmdstx_dat_n[1]" 	LOC=A9	| IOSTANDARD=TMDS_33;	#Bank = 0, pin name = IO_L8N_VREF_0,		Sch name = HDMI-TX-1 N
NET "tmdstx_dat_n[2]" 	LOC=D8	| IOSTANDARD=TMDS_33;	#Bank = 0, pin name = IO_L32N_0,		Sch name = HDMI-TX-2 N
NET "tmdstx_clk_n"		LOC=A10	| IOSTANDARD=TMDS_33;	#Bank = 0, pin name = IO_L34N_GCLK18_0,		Sch name = HDMI-TX-CLK N
	
## Ethernet
# Moved to begining of file.
#NET "PhyClk50Mhz"	LOC=C12	|	IOSTANDARD=LVCMOS33;			#Bank = 0, pin name = IO_L37N_GCLK12_0,					Sch name = ETH-REFCLK
NET "PhyMdc"		LOC=C15	|	IOSTANDARD=LVCMOS33;			#Bank = 0, pin name = IO_L62P_0,					Sch name = ETH-MDC
NET "PhyMdio"		LOC=A14	|	IOSTANDARD=LVCMOS33;			#Bank = 0, pin name = IO_L50N_0,					Sch name = ETH-MDIO
NET "PhyTxEn"		LOC=D15	|	IOSTANDARD=LVCMOS33;			#Bank = 0, pin name = IO_L46P_0,					Sch name = ETH-TXEN
NET "PhyTxd<0>"		LOC=E10	|	IOSTANDARD=LVCMOS33;			#Bank = 0, pin name = IO_L38N_VREF_0,					Sch name = ETH-TXD0
NET "PhyTxd<1>"		LOC=F10	|	IOSTANDARD=LVCMOS33;			#Bank = 0, pin name = IO_L38P_0,					Sch name = ETH-TXD1
NET "PhyCrs"		LOC=B14	|	IOSTANDARD=LVCMOS33;			#Bank = 0, pin name = IO_L50P_0,					Sch name = ETH-CRSDV
NET "PhyRxEr"		LOC=A13	|	IOSTANDARD=LVCMOS33;			#Bank = 0, pin name = IO_L48N_0,					Sch name = ETH-RXERR
NET "PhyRxd<0>"		LOC=C13	|	IOSTANDARD=LVCMOS33;			#Bank = 0, pin name = IO_L48P_0,					Sch name = ETH-RXD0
NET "PhyRxd<1>"		LOC=C14	|	IOSTANDARD=LVCMOS33;			#Bank = 0, pin name = IO_L46N_0,					Sch name = ETH-RXD1
	
## BREADBOARD
#NET "BB1"   LOC=AB20 | IOSTANDARD=LVCMOS33; #Bank = 1, pin name = IO_L65N_1, Sch name = BB1
#NET "BB2"   LOC=P17  | IOSTANDARD=LVCMOS33; #Bank = 1, pin name = IO_L66P_1, Sch name = BB2
#NET "BB3"   LOC=P18  | IOSTANDARD=LVCMOS33; #Bank = 1, pin name = IO_L66N_1, Sch name = BB3
#NET "BB4"   LOC=Y19  | IOSTANDARD=LVCMOS33; #Bank = 1, pin name = IO_L67P_1, Sch name = BB4
#NET "BB5"  LOC=Y20  | IOSTANDARD=LVCMOS33; #Bank = 1, pin name = IO_L67N_1, Sch name = BB5
#NET "BB6"  LOC=R15  | IOSTANDARD=LVCMOS33; #Bank = 1, pin name = IO_L68P_1, Sch name = BB6
#NET "BB7"  LOC=R16  | IOSTANDARD=LVCMOS33; #Bank = 1, pin name = IO_L68N_1, Sch name = BB7
#NET "BB8"  LOC=R17  | IOSTANDARD=LVCMOS33; #Bank = 1, pin name = IO_L70P_1, Sch name = BB8
#NET "BB9"  LOC=R19  | IOSTANDARD=LVCMOS33; #Bank = 1, pin name = IO_L70N_1, Sch name = BB9
#NET "BB10" LOC=V19  | IOSTANDARD=LVCMOS33; #Bank = 1, pin name = IO_L71P_1, Sch name = BB10

## JA
	#NET "JA1"	LOC = AA18	|	IOSTANDARD=LVCMOS33;	#Bank = 2, pin name = IO_L2P_CMPCLK_2,			Sch name = JA1
	#NET "JA2"	LOC = AA16	|	IOSTANDARD=LVCMOS33;	#Bank = 2, pin name = IO_L4P_2,								Sch name = JA2
	#NET "JA3"	LOC = Y15		|	IOSTANDARD=LVCMOS33;	#Bank = 2, pin name = IO_L5P_2,								Sch name = JA3
	#NET "JA4"	LOC = V15		|	IOSTANDARD=LVCMOS33;	#Bank = 2, pin name = IO_L13N_D10_2,					Sch name = JA4
	#NET "JA7"	LOC = AB18	|	IOSTANDARD=LVCMOS33;	#Bank = 2, pin name = IO_L2N_CMPMOSI_2,			Sch name = JA7
	#NET "JA8"	LOC = AB16	|	IOSTANDARD=LVCMOS33;	#Bank = 2, pin name = IO_L4N_VREF_2,					Sch name = JA8
	#NET "JA9"	LOC = AB15	|	IOSTANDARD=LVCMOS33;	#Bank = 2, pin name = IO_L5N_2,								Sch name = JA9
	#NET "JA10"	LOC=W15		|	IOSTANDARD=LVCMOS33;	#Bank = 2, pin name = IO_L14P_D11_2,					Sch name = JA10
	
## JB
	#NET "JB1"	LOC = Y16		|	IOSTANDARD=LVCMOS33;	#Bank = 2, pin name = IO_L14N_D12_2,					Sch name = JB1
	#NET "JB2"	LOC = AB14	|	IOSTANDARD=LVCMOS33;	#Bank = 2, pin name = IO_L15N_2,							Sch name = JB2
	#NET "JB3"	LOC = Y14		|	IOSTANDARD=LVCMOS33;	#Bank = 2, pin name = IO_L16N_VREF_2,				Sch name = JB3
	#NET "JB4"	LOC = U14		|	IOSTANDARD=LVCMOS33;	#Bank = 2, pin name = IO_L20N_2,							Sch name = JB4
	#NET "JB7"	LOC = AA14	|	IOSTANDARD=LVCMOS33;	#Bank = 2, pin name = IO_L15P_2,							Sch name = JB7
	#NET "JB8"	LOC = W14	|	IOSTANDARD=LVCMOS33;	#Bank = 2, pin name = IO_L16P_2,							Sch name = JB8
	#NET "JB9"	LOC = T14		|	IOSTANDARD=LVCMOS33;	#Bank = 2, pin name = IO_L20P_2,							Sch name = JB9
	#NET "JB10"	LOC=W11		|	IOSTANDARD=LVCMOS33;	#Bank = 2, pin name = IO_L29P_GCLK3_2,				Sch name = JB10
	
## JC
	#NET "JC1"	LOC = Y10		|	IOSTANDARD=LVCMOS33;	#Bank = 2, pin name = IO_L29N_GCLK2_2,								Sch name = JC1
	#NET "JC2"	LOC = AB12	|	IOSTANDARD=LVCMOS33;	#Bank = 2, pin name = IO_L30N_GCLK0_USERCCLK_2,		Sch name = JC2
	#NET "JC3"	LOC = AB11	|	IOSTANDARD=LVCMOS33;	#Bank = 2, pin name = IO_L31N_GCLK30_D15_2,					Sch name = JC3
	#NET "JC4"	LOC = AB10	|	IOSTANDARD=LVCMOS33;	#Bank = 2, pin name = IO_L32N_GCLK28_2,							Sch name = JC4
	#NET "JC7"	LOC = AA12	|	IOSTANDARD=LVCMOS33;	#Bank = 2, pin name = IO_L30P_GCLK1_D13_2,					Sch name = JC7
	#NET "JC8"	LOC = Y11		|	IOSTANDARD=LVCMOS33;	#Bank = 2, pin name = IO_L31P_GCLK31_D14_2,					Sch name = JC8
	#NET "JC9"	LOC = AA10	|	IOSTANDARD=LVCMOS33;	#Bank = 2, pin name = IO_L32P_GCLK29_2,							Sch name = JC9
	#NET "JC10"	LOC=Y13		|	IOSTANDARD=LVCMOS33;	#Bank = 2, pin name = IO_L41P_2,											Sch name = JC10
	
## JD
	#NET "JD1"	LOC = AB13	|	IOSTANDARD=LVCMOS33;	#Bank = 2, pin name = IO_L41N_VREF_2,			Sch name = JD1
	#NET "JD2"	LOC = Y12		|	IOSTANDARD=LVCMOS33;	#Bank = 2, pin name = IO_L42N_2,						Sch name = JD2
	#NET "JD3"	LOC = T11		|	IOSTANDARD=LVCMOS33;	#Bank = 2, pin name = IO_L43N_2,						Sch name = JD3
	#NET "JD4"	LOC = W10	|	IOSTANDARD=LVCMOS33;	#Bank = 2, pin name = IO_L44N_2,						Sch name = JD4
	#NET "JD7"	LOC = W12	|	IOSTANDARD=LVCMOS33;	#Bank = 2, pin name = IO_L42P_2,						Sch name = JD7
	#NET "JD8"	LOC = R11		|	IOSTANDARD=LVCMOS33;	#Bank = 2, pin name = IO_L43P_2,						Sch name = JD8
	#NET "JD9"	LOC = V11		|	IOSTANDARD=LVCMOS33;	#Bank = 2, pin name = IO_L44P_2,						Sch name = JD9
	#NET "JD10"	LOC= T10		|	IOSTANDARD=LVCMOS33;	#Bank = 2, pin name = IO_L45P_2,						Sch name = JD10
	
## JE
	#NET "JE1"	LOC = U10	|	IOSTANDARD=LVCMOS33;		#Bank = 2, pin name = IO_L45N_2,					Sch name = JE1
	#NET "JE2"	LOC = V9	|	IOSTANDARD=LVCMOS33;		#Bank = 2, pin name = IO_L46N_2,					Sch name = JE2
	#NET "JE3"	LOC = Y8	|	IOSTANDARD=LVCMOS33;		#Bank = 2, pin name = IO_L47N_2,					Sch name = JE3
	#NET "JE4"	LOC = AA8	|	IOSTANDARD=LVCMOS33;		#Bank = 2, pin name = IO_L49P_D3_2,			Sch name = JE4
	#NET "JE7"	LOC = U9	|	IOSTANDARD=LVCMOS33;		#Bank = 2, pin name = IO_L46P_2,					Sch name = JE7
	#NET "JE8"	LOC = W9	|	IOSTANDARD=LVCMOS33;		#Bank = 2, pin name = IO_L47P_2,					Sch name = JE8
	#NET "JE9"	LOC = Y9	|	IOSTANDARD=LVCMOS33;		#Bank = 2, pin name = IO_L48P_D7_2,			Sch name = JE9
	#NET "JE10"	LOC= AB8	|	IOSTANDARD=LVCMOS33;		#Bank = 2, pin name = IO_L49N_D4_2,			Sch name = JE10

## JF
	#NET "JF1"	LOC = V7	|	IOSTANDARD=LVCMOS33;		#Bank = 2, pin name = IO_L50P_2,					Sch name = JF1
	#NET "JF2"	LOC = W6	|	IOSTANDARD=LVCMOS33;		#Bank = 2, pin name = IO_L62P_D5_2,			Sch name = JF2
	#NET "JF3"	LOC = Y7	|	IOSTANDARD=LVCMOS33;		#Bank = 2, pin name = IO_L63P_2,					Sch name = JF3
	#NET "JF4"	LOC = AA6	|	IOSTANDARD=LVCMOS33;		#Bank = 2, pin name = IO_L64P_D8_2,			Sch name = JF4
	#NET "JF7"	LOC = W8	|	IOSTANDARD=LVCMOS33;		#Bank = 2, pin name = IO_L50N_2,					Sch name = JF7
	#NET "JF8"	LOC = Y6	|	IOSTANDARD=LVCMOS33;		#Bank = 2, pin name = IO_L62N_D6_2,			Sch name = JF8
	#NET "JF9"	LOC = AB7	|	IOSTANDARD=LVCMOS33;		#Bank = 2, pin name = IO_L63N_2,					Sch name = JF9
	#NET "JF10"	LOC= AB6	|	IOSTANDARD=LVCMOS33;		#Bank = 2, pin name = IO_L64N_D9_2,			Sch name = JF10
	
## JG
	#NET "JG1"	LOC = V20	|	IOSTANDARD=LVCMOS33;		#Bank = 1, pin name = IO_L71N_1,						Sch name = JG1
	#NET "JG2"	LOC = T18	|	IOSTANDARD=LVCMOS33;		#Bank = 1, pin name = IO_L72N_1,						Sch name = JG2
	#NET "JG3"	LOC = D17	|	IOSTANDARD=LVCMOS33;		#Bank = 0, pin name = IO_L65P_SCP3_0,			Sch name = JG3
	#NET "JG4"	LOC = B18	|	IOSTANDARD=LVCMOS33;		#Bank = 0, pin name = IO_L66P_SCP1_0,			Sch name = JG4
	#NET "JG7"	LOC = T17	|	IOSTANDARD=LVCMOS33;		#Bank = 1, pin name = IO_L72P_1,						Sch name = JG7
	#NET "JG8"	LOC = A17	|	IOSTANDARD=LVCMOS33;		#Bank = 0, pin name = IO_L64N_SCP4_0,			Sch name = JG8
	#NET "JG9"	LOC = C16	|	IOSTANDARD=LVCMOS33;		#Bank = 0, pin name = IO_L65N_SCP2_0,			Sch name = JG9
	#NET "JG10"	LOC= A18	|	IOSTANDARD=LVCMOS33;		#Bank = 0, pin name = IO_L66N_SCP0_0,			Sch name = JG10
	
## VGA
	#NET "RED_O[0]"	LOC = "T3"	|	IOSTANDARD=LVCMOS18;				#Bank = 3, pin name = IO_L26P_3,						Sch name = VGA-R1
	#NET "RED_O[1]"	LOC = "B2"	|	IOSTANDARD=LVCMOS18;				#Bank = 3, pin name = IO_L54P_M3RESET_3,	Sch name = VGA-R2
	#NET "RED_O[2]"	LOC = "H3"	|	IOSTANDARD=LVCMOS18;				#Bank = 3, pin name = IO_L55N_M3A14_3,			Sch name = VGA-R3
	#NET "RED_O[3]"	LOC = "H4"	|	IOSTANDARD=LVCMOS18;				#Bank = 3, pin name = IO_L55P_M3A13_3,			Sch name = VGA-R4
	
	#NET "GREEN_O[0]"	LOC = "T4"		|	IOSTANDARD=LVCMOS18;		#Bank = 3, pin name = IO_L26P_3,						Sch name = VGA-G1
	#NET "GREEN_O[1]"	LOC = "M6"		|	IOSTANDARD=LVCMOS18;		#Bank = 3, pin name = IO_L31P_3,						Sch name = VGA-G2
	#NET "GREEN_O[2]"	LOC = "H6"		|	IOSTANDARD=LVCMOS18;		#Bank = 3, pin name = IO_L57P_3,						Sch name = VGA-G3
	#NET "GREEN_O[3]"	LOC = "N6"		|	IOSTANDARD=LVCMOS18;		#Bank = 3, pin name = IO_L24N_3,						Sch name = VGA-G4

	#NET "BLUE_O[0]"	LOC = "M8"	|	IOSTANDARD=LVCMOS18;				#Bank = 3, pin name = IO_L25P_3,						Sch name = VGA-B1
	#NET "BLUE_O[1]"	LOC = "M7"	|	IOSTANDARD=LVCMOS18;				#Bank = 3, pin name = IO_L25N_3,						Sch name = VGA-B2	
	#NET "BLUE_O[2]"	LOC = "N7"	|	IOSTANDARD=LVCMOS18;				#Bank = 3, pin name = IO_L24P_3,						Sch name = VGA-B3
	#NET "BLUE_O[3]"	LOC = "P7"	|	IOSTANDARD=LVCMOS18;				#Bank = 3, pin name = IO_L23N_3,						Sch name = VGA-B4

	#NET "VSYNC_O"	LOC = "V18"	|	IOSTANDARD=LVCMOS33;			#Bank = 1, pin name = IO_L73N_1,						Sch name = VGA-VS
	#NET "HSYNC_O"	LOC = "V17"	|	IOSTANDARD=LVCMOS33;			#Bank = 1, pin name = IO_L73P_1,						Sch name = VGA-HS

## Touchscreen TFT
	#NET "TFT_VDDEN_O"	LOC ="W20"	|	IOSTANDARD=LVCMOS33;														#Bank = 1, pin name = IO_L53P_1,												Sch name = TFT-EN
	#NET "TFT_B_O[0]"		LOC ="N22"	|	IOSTANDARD=LVCMOS33	|	OUT_TERM = UNTUNED_75;	#Bank = 1, pin name = IO_L47N_LDC_M1DQ1_1,						Sch name = TFT-B0
	#NET "TFT_B_O[1]"		LOC ="P22"	|	IOSTANDARD=LVCMOS33	|	OUT_TERM = UNTUNED_75;	#Bank = 1, pin name = IO_L48N_M1DQ9_1,								Sch name = TFT-B1
	#NET "TFT_B_O[2]"		LOC ="P21"	|	IOSTANDARD=LVCMOS33	|	OUT_TERM = UNTUNED_75;	#Bank = 1, pin name = IO_L48P_HDC_M1DQ8_1,						Sch name = TFT-B2
	#NET "TFT_B_O[3]"		LOC ="R22"	|	IOSTANDARD=LVCMOS33	|	OUT_TERM = UNTUNED_75;	#Bank = 1, pin name = IO_L49N_M1DQ11_1,								Sch name = TFT-B3
	#NET "TFT_B_O[4]"		LOC ="T22"	|	IOSTANDARD=LVCMOS33	|	OUT_TERM = UNTUNED_75;	#Bank = 1, pin name = IO_L50N_M1UDQSN_1,							Sch name = TFT-B4
	#NET "TFT_B_O[5]"		LOC ="T21"	|	IOSTANDARD=LVCMOS33	|	OUT_TERM = UNTUNED_75;	#Bank = 1, pin name = IO_L50P_M1UDQS_1,								Sch name = TFT-B5
	#NET "TFT_B_O[6]"		LOC ="U22"	|	IOSTANDARD=LVCMOS33	|	OUT_TERM = UNTUNED_75;	#Bank = 1, pin name = IO_L51N_M1DQ13_1,								Sch name = TFT-B6
	#NET "TFT_B_O[7]"		LOC ="V22"	|	IOSTANDARD=LVCMOS33	|	OUT_TERM = UNTUNED_75;	#Bank = 1, pin name = IO_L52N_M1DQ15_1,								Sch name = TFT-B7
	#NET "TFT_CLK_O"	LOC ="L20"	|	IOSTANDARD=LVCMOS33	|	OUT_TERM = UNTUNED_75;	#Bank = 1, pin name = IO_L43P_GCLK5_M1DQ4_1,					Sch name = TFT-CLK
	#NET "TFT_DE_O"		LOC ="W22"	|	IOSTANDARD=LVCMOS33	|	OUT_TERM = UNTUNED_75;	#Bank = 1, pin name = IO_L53N_VREF_1,									Sch name = TFT-DE
	#NET "TFT_DISP_O"	LOC ="V21"	|	IOSTANDARD=LVCMOS33	|	OUT_TERM = UNTUNED_75;	#Bank = 1, pin name = IO_L52P_M1DQ14_1,								Sch name = TFT-DISP
	#NET "TFT_G_O[0]"		LOC ="C22"	|	IOSTANDARD=LVCMOS33	|	OUT_TERM = UNTUNED_75;	#Bank = 1, pin name = IO_L35N_A10_M1A2_1,							Sch name = TFT-G0
	#NET "TFT_G_O[1]"		LOC ="B22"	|	IOSTANDARD=LVCMOS33	|	OUT_TERM = UNTUNED_75;	#Bank = 1, pin name = IO_L37N_A6_M1A1_1,								Sch name = TFT-G1
	#NET "TFT_G_O[2]"		LOC ="B21"	|	IOSTANDARD=LVCMOS33	|	OUT_TERM = UNTUNED_75;	#Bank = 1, pin name = IO_L37P_A7_M1A0_1,								Sch name = TFT-G2
	#NET "TFT_G_O[3]"		LOC ="H22"	|	IOSTANDARD=LVCMOS33	|	OUT_TERM = UNTUNED_75;	#Bank = 1, pin name = IO_L34N_A12_M1BA2_1,							Sch name = TFT-G3
	#NET "TFT_G_O[4]"		LOC ="K22"	|	IOSTANDARD=LVCMOS33	|	OUT_TERM = UNTUNED_75;	#Bank = 1, pin name = IO_L44N_A2_M1DQ7_1,							Sch name = TFT-G4
	#NET "TFT_G_O[5]"		LOC ="L22"	|	IOSTANDARD=LVCMOS33	|	OUT_TERM = UNTUNED_75;	#Bank = 1, pin name = IO_L43N_GCLK4_M1DQ5_1,					Sch name = TFT-G5
	#NET "TFT_G_O[6]"		LOC ="M22"	|	IOSTANDARD=LVCMOS33	|	OUT_TERM = UNTUNED_75;	#Bank = 1, pin name = IO_L45N_A0_M1LDQSN_1,						Sch name = TFT-G6
	#NET "TFT_G_O[7]"		LOC ="M21"	|	IOSTANDARD=LVCMOS33	|	OUT_TERM = UNTUNED_75;	#Bank = 1, pin name = IO_L45P_A1_M1LDQS_1,						Sch name = TFT-G7
	#NET "TFT_BKLT_O"	LOC ="M16"	|	IOSTANDARD=LVCMOS33	|	OUT_TERM = UNTUNED_75;	#Bank = 1, pin name = IO_L58P_1,												Sch name = TFT-LED
	#NET "TFT_R_O[0]"		LOC ="R20"	|	IOSTANDARD=LVCMOS33	|	OUT_TERM = UNTUNED_75;	#Bank = 1, pin name = IO_L49P_M1DQ10_1,								Sch name = TFT-R0
	#NET "TFT_R_O[1]"		LOC ="N19"	|	IOSTANDARD=LVCMOS33	|	OUT_TERM = UNTUNED_75;	#Bank = 1, pin name = IO_L46P_FCS_B_M1DQ2_1,					Sch name = TFT-R1
	#NET "TFT_R_O[2]"		LOC ="K19"	|	IOSTANDARD=LVCMOS33	|	OUT_TERM = UNTUNED_75;	#Bank = 1, pin name = IO_L36N_A8_M1BA1_1,							Sch name = TFT-R2
	#NET "TFT_R_O[3]"		LOC ="K20"	|	IOSTANDARD=LVCMOS33	|	OUT_TERM = UNTUNED_75;	#Bank = 1, pin name = IO_L42N_GCLK6_TRDY1_M1LDM_1,		Sch name = TFT-R3
	#NET "TFT_R_O[4]"		LOC ="K18"	|	IOSTANDARD=LVCMOS33	|	OUT_TERM = UNTUNED_75;	#Bank = 1, pin name = IO_L36P_A9_M1BA0_1,							Sch name = TFT-R4
	#NET "TFT_R_O[5]"		LOC ="J19"		|	IOSTANDARD=LVCMOS33	|	OUT_TERM = UNTUNED_75;	#Bank = 1, pin name = IO_L38N_A4_M1CLKN_1,						Sch name = TFT-R5
	#NET "TFT_R_O[6]"		LOC ="J17"		|	IOSTANDARD=LVCMOS33	|	OUT_TERM = UNTUNED_75;	#Bank = 1, pin name = IO_L38P_A5_M1CLK_1,							Sch name = TFT-R6
	#NET "TFT_R_O[7]"		LOC ="C20"	|	IOSTANDARD=LVCMOS33	|	OUT_TERM = UNTUNED_75;	#Bank = 1, pin name = IO_L35P_A11_M1A7_1,							Sch name = TFT-R7
	#NET "TP_BUSY_I"		LOC ="M19"	|	IOSTANDARD=LVCMOS33;															#Bank = 1, pin name = IO_L41N_GCLK8_M1CASN_1,				Sch name = TFT-BUSY
	#NET "TP_CS_O"		LOC ="M20"	|	IOSTANDARD=LVCMOS33	|	OUT_TERM = UNTUNED_75;	#Bank = 1, pin name = IO_L46N_FOE_B_M1DQ3_1,					Sch name = TFT-CS
	#NET "TP_DCLK_O"	LOC ="K21"	|	IOSTANDARD=LVCMOS33	|	OUT_TERM = UNTUNED_75;	#Bank = 1, pin name = IO_L44P_A3_M1DQ6_1,							Sch name = TFT-DCLK
	#NET "TP_DIN_O"		LOC ="U20"	|	IOSTANDARD=LVCMOS33	|	OUT_TERM = UNTUNED_75;	#Bank = 1, pin name = IO_L51P_M1DQ12_1,								Sch name = TFT-DIN
	#NET "TP_DOUT_I"		LOC ="M18"	|	IOSTANDARD=LVCMOS33;															#Bank = 1, pin name = IO_L41P_GCLK9_IRDY1_M1RASN_1,	Sch name = TFT-DOUT
	#NET "TP_PENIRQ_I"	LOC ="N20"	|	IOSTANDARD=LVCMOS33;															#Bank = 1, pin name = IO_L47P_FWE_B_M1DQ0_1,					Sch name = TFT-PEN
	
	#INST "TFT_R_O[7]" TNM = "TFT_PIXEL_BUS";
	#INST "TFT_R_O[0]" TNM = "TFT_PIXEL_BUS";
	#INST "TFT_R_O[1]" TNM = "TFT_PIXEL_BUS";
	#INST "TFT_R_O[2]" TNM = "TFT_PIXEL_BUS";
	#INST "TFT_R_O[3]" TNM = "TFT_PIXEL_BUS";
	#INST "TFT_R_O[4]" TNM = "TFT_PIXEL_BUS";
	#INST "TFT_R_O[5]" TNM = "TFT_PIXEL_BUS";
	#INST "TFT_R_O[6]" TNM = "TFT_PIXEL_BUS";
	#INST "TFT_B_O[0]" TNM = "TFT_PIXEL_BUS";
	#INST "TFT_B_O[1]" TNM = "TFT_PIXEL_BUS";
	#INST "TFT_B_O[2]" TNM = "TFT_PIXEL_BUS";
	#INST "TFT_B_O[3]" TNM = "TFT_PIXEL_BUS";
	#INST "TFT_B_O[4]" TNM = "TFT_PIXEL_BUS";
	#INST "TFT_B_O[5]" TNM = "TFT_PIXEL_BUS";
	#INST "TFT_B_O[6]" TNM = "TFT_PIXEL_BUS";
	#INST "TFT_B_O[7]" TNM = "TFT_PIXEL_BUS";
	#INST "TFT_CLK_O" TNM = "TFT_PIXEL_BUS";
	#INST "TFT_DE_O" TNM = "TFT_PIXEL_BUS";
	#INST "TFT_G_O[0]" TNM = "TFT_PIXEL_BUS";
	#INST "TFT_G_O[1]" TNM = "TFT_PIXEL_BUS";
	#INST "TFT_G_O[2]" TNM = "TFT_PIXEL_BUS";
	#INST "TFT_G_O[3]" TNM = "TFT_PIXEL_BUS";
	#INST "TFT_G_O[4]" TNM = "TFT_PIXEL_BUS";
	#INST "TFT_G_O[5]" TNM = "TFT_PIXEL_BUS";
	#INST "TFT_G_O[6]" TNM = "TFT_PIXEL_BUS";
	#INST "TFT_G_O[7]" TNM = "TFT_PIXEL_BUS";
	#TIMEGRP "TFT_PIXEL_BUS" OFFSET = OUT  AFTER "CLK_I" REFERENCE_PIN "TFT_CLK_O";
	
## SRAM
	#NET "Memory_address[0]"	LOC = "F22" 		| 	IOSTANDARD = "LVCMOS33";		#Bank = 1, pin name = IO_L29N_A22_M1A14_1,			Sch name = SRAM-A0
	#NET "Memory_address[1]"	LOC = "F21" 		| 	IOSTANDARD = "LVCMOS33";		#Bank = 1, pin name = IO_L29P_A23_M1A13_1,			Sch name = SRAM-A1
	#NET "Memory_address[2]"	LOC = "E22" 		| 	IOSTANDARD = "LVCMOS33";		#Bank = 1, pin name = IO_L31N_A18_M1A12_1,			Sch name = SRAM-A2
	#NET "Memory_address[3]"	LOC = "D22" 		| 	IOSTANDARD = "LVCMOS33";		#Bank = 1, pin name = IO_L33N_A14_M1A4_1,			Sch name = SRAM-A3
	#NET "Memory_address[4]"	LOC = "D21" 		| 	IOSTANDARD = "LVCMOS33";		#Bank = 1, pin name = IO_L33P_A15_M1A10_1,			Sch name = SRAM-A4
	#NET "Memory_address[5]"	LOC = "D19" 		| 	IOSTANDARD = "LVCMOS33";		#Bank = 1, pin name = IO_L11P_1,								Sch name = SRAM-A5
	#NET "Memory_address[6]"	LOC = "D20" 		| 	IOSTANDARD = "LVCMOS33";		#Bank = 1, pin name = IO_L11N_1,								Sch name = SRAM-A6
	#NET "Memory_address[7]"	LOC = "E20" 		| 	IOSTANDARD = "LVCMOS33";		#Bank = 1, pin name = IO_L31P_A19_M1CKE_1,		Sch name = SRAM-A7
	#NET "Memory_address[8]"	LOC = "G17" 		| 	IOSTANDARD = "LVCMOS33";		#Bank = 1, pin name = IO_L13P_1,								Sch name = SRAM-A8
	#NET "Memory_address[9]"	LOC = "H18" 		| 	IOSTANDARD = "LVCMOS33";		#Bank = 1, pin name = IO_L17N_1,								Sch name = SRAM-A9
	#NET "Memory_address[10]"	LOC = "H13"	| 	IOSTANDARD = "LVCMOS33";		#Bank = 1, pin name = IO_L21P_1,								Sch name = SRAM-A10
	#NET "Memory_address[11]"	LOC = "H12"	| 	IOSTANDARD = "LVCMOS33";		#Bank = 1, pin name = IO_L219P_1,								Sch name = SRAM-A11
	#NET "Memory_address[12]"	LOC = "K16"	| 	IOSTANDARD = "LVCMOS33";		#Bank = 1, pin name = IO_L28N_VREF_1,					Sch name = SRAM-A12
	#NET "Memory_address[13]"	LOC = "L15" 	| 	IOSTANDARD = "LVCMOS33";		#Bank = 1, pin name = IO_L28P_1,								Sch name = SRAM-A13
	#NET "Memory_address[14]"	LOC = "G15"	| 	IOSTANDARD = "LVCMOS33";		#Bank = 1, pin name = IO_L10P_1,								Sch name = SRAM-A14
	#NET "Memory_address[15]"	LOC = "J16" 	| 	IOSTANDARD = "LVCMOS33";		#Bank = 1, pin name = IO_L20P_1,								Sch name = SRAM-A15
	#NET "Memory_address[16]"	LOC = "H17"	| 	IOSTANDARD = "LVCMOS33";		#Bank = 1, pin name = IO_L17P_1,								Sch name = SRAM-A16
	#NET "Memory_address[17]"	LOC = "H16"	| 	IOSTANDARD = "LVCMOS33";		#Bank = 1, pin name = IO_L20N_1,								Sch name = SRAM-A17
	#NET "Memory_address[18]"	LOC = "G16"	| 	IOSTANDARD = "LVCMOS33";		#Bank = 1, pin name = IO_L10N_1,								Sch name = SRAM-A18

	#NET "Memory_data[0]"	LOC = "H21"			| 	IOSTANDARD = "LVCMOS33";		#Bank = 1, pin name = IO_L34P_A13_M1WE_1,			Sch name = SRAM-DQ0
	#NET "Memory_data[1]"	LOC = "A20"			| 	IOSTANDARD = "LVCMOS33";		#Bank = 1, pin name = IO_L16N_1,								Sch name = SRAM-DQ1
	#NET "Memory_data[2]"	LOC = "A21"			| 	IOSTANDARD = "LVCMOS33";		#Bank = 1, pin name = IO_L14N_1,								Sch name = SRAM-DQ2
	#NET "Memory_data[3]"	LOC = "A19"			| 	IOSTANDARD = "LVCMOS33";		#Bank = 1, pin name = IO_L16P_1,								Sch name = SRAM-DQ3
	#NET "Memory_data[4]"	LOC = "B20"			| 	IOSTANDARD = "LVCMOS33";		#Bank = 1, pin name = IO_L14P_1,								Sch name = SRAM-DQ4
	#NET "Memory_data[5]"	LOC = "C18"			| 	IOSTANDARD = "LVCMOS33";		#Bank = 1, pin name = IO_L12P_1,								Sch name = SRAM-DQ5
	#NET "Memory_data[6]"	LOC = "C19"			| 	IOSTANDARD = "LVCMOS33";		#Bank = 1, pin name = IO_L12N_1,								Sch name = SRAM-DQ6
	#NET "Memory_data[7]"	LOC = "F15"			| 	IOSTANDARD = "LVCMOS33";		#Bank = 1, pin name = IO_L1P_A25_1,							Sch name = SRAM-DQ7
	#NET "Memory_data[8]"	LOC = "F18"			| 	IOSTANDARD = "LVCMOS33";		#Bank = 1, pin name = IO_L15N_1,								Sch name = SRAM-DQ8
	#NET "Memory_data[9]"	LOC = "F17"			| 	IOSTANDARD = "LVCMOS33";		#Bank = 1, pin name = IO_L15P_1,								Sch name = SRAM-DQ9
	#NET "Memory_data[10]"	LOC = "F14"			| 	IOSTANDARD = "LVCMOS33";		#Bank = 1, pin name = IO_L9N_1,									Sch name = SRAM-DQ10
	#NET "Memory_data[11]"	LOC = "F13"			| 	IOSTANDARD = "LVCMOS33";		#Bank = 1, pin name = IO_L9P,										Sch name = SRAM-DQ11
	#NET "Memory_data[12]"	LOC = "H14"			| 	IOSTANDARD = "LVCMOS33";		#Bank = 1, pin name = IO_L21N_1,								Sch name = SRAM-DQ12
	#NET "Memory_data[13]"	LOC = "H19"			| 	IOSTANDARD = "LVCMOS33";		#Bank = 1, pin name = IO_L30P_A21_M1RESET_1,	Sch name = SRAM-DQ13
	#NET "Memory_data[14]"	LOC = "H20"			| 	IOSTANDARD = "LVCMOS33";		#Bank = 1, pin name = IO_L30N_A20_M1A11_1,			Sch name = SRAM-DQ14
	#NET "Memory_data[15]"	LOC = "G20"			| 	IOSTANDARD = "LVCMOS33";		#Bank = 1, pin name = IO_L32P_A17_M1A8_1,			Sch name = SRAM-DQ15
	
	#NET "SRAM_CS1"	LOC = "G22" 				| 	IOSTANDARD = "LVCMOS33"; 				#Bank = 1, pin name = IO_L32N_A16_M1A9_1,			Sch name = SRAM-CS1

	#NET "SRAM_CS2"	LOC = "G13"					| 	IOSTANDARD = "LVCMOS33";						#Bank = 1, pin name = IO_L19N_1,								Sch name = SRAM-CS2

	#NET "SRAM_OE"	LOC = "F19" 					| 	IOSTANDARD = "LVCMOS33";						#Bank = 1, pin name = IO_L18P_1,								Sch name = SRAM-OE
	#NET "SRAM_WE"	LOC = "F16"					| 	IOSTANDARD = "LVCMOS33";						#Bank = 1, pin name = IO_L1N_A24_VREF_1,				Sch name = SRAM-WE

	#NET "SRAM_UPPER_B"	LOC = "F20"		| 	IOSTANDARD = "LVCMOS33" | DRIVE = 2 | PULLDOWN;	#Bank = 1, pin name = IO_L18N_1,		Sch name = SRAM-UB
	#NET "SRAM_LOWER_B"	LOC = "G19"		| 	IOSTANDARD = "LVCMOS33" | DRIVE = 2 | PULLDOWN;	#Bank = 1, pin name = IO_L13N_1,		Sch name = SRAM-LB
	
# ==== SPI flash memory ====

NET "spi_clk"    LOC = "W17" | IOSTANDARD = LVCMOS33 ; # SCK , R15, W17, W17
NET "spi_sel_n"  LOC = "AB5"  | IOSTANDARD = LVCMOS33 ; # CS, V3, T13, AB5?, AB5
NET "spi_mosi"   LOC = "AB17" | IOSTANDARD = LVCMOS33 ; # SDI/DQ0, AB16, AB17, AB17
NET "spi_miso"   LOC = "Y17" | IOSTANDARD = LVCMOS33 ; # SDO/DQ1, R13, Y17, Y17
#HOLD/DQ3, V14, W13
#WP/DQ2, T14, V13

## DDR2
NET "ddr_dq(0)"		LOC=N3	|	IOSTANDARD=LVCMOS18;		#Bank = 3, pin name = IO_L37P_M3DQ0_3,				Sch name = DDR-DQ0
NET "ddr_dq(1)"		LOC=N1	|	IOSTANDARD=LVCMOS18;		#Bank = 3, pin name = IO_L37N_M3DQ1_3,				Sch name = DDR-DQ1
NET "ddr_dq(2)"		LOC=M2	|	IOSTANDARD=LVCMOS18;		#Bank = 3, pin name = IO_L38P_M3DQ2_3,				Sch name = DDR-DQ2
NET "ddr_dq(3)"		LOC=M1	|	IOSTANDARD=LVCMOS18;		#Bank = 3, pin name = IO_L38N_M3DQ3_3,				Sch name = DDR-DQ3
NET "ddr_dq(4)"		LOC=J3	|	IOSTANDARD=LVCMOS18;		#Bank = 3, pin name = IO_L41P_GCLK27_M3DQ4_3,Sch name = DDR-DQ4
NET "ddr_dq(5)"		LOC=J1	|	IOSTANDARD=LVCMOS18;		#Bank = 3, pin name = IO_L41N_GCLK26_M3DQ5_3,Sch name = DDR-DQ5
NET "ddr_dq(6)"		LOC=K2	|	IOSTANDARD=LVCMOS18;		#Bank = 3, pin name = IO_L40P_M3DQ6_3,				Sch name = DDR-DQ6
NET "ddr_dq(7)"		LOC=K1	|	IOSTANDARD=LVCMOS18;		#Bank = 3, pin name = IO_L40N_M3DQ7_3,				Sch name = DDR-DQ7
NET "ddr_dq(8)"		LOC=P2	|	IOSTANDARD=LVCMOS18;		#Bank = 3, pin name = IO_L36P_M3DQ8_3,				Sch name = DDR-DQ8
NET "ddr_dq(9)"		LOC=P1	|	IOSTANDARD=LVCMOS18;		#Bank = 3, pin name = IO_L36N_M3DQ9_3,				Sch name = DDR-DQ9
NET "ddr_dq(10)"	LOC=R3	|	IOSTANDARD=LVCMOS18;		#Bank = 3, pin name = IO_L35P_M3DQ10_3,				Sch name = DDR-DQ10
NET "ddr_dq(11)"	LOC=R1	|	IOSTANDARD=LVCMOS18;		#Bank = 3, pin name = IO_L35N_M3DQ11_3,				Sch name = DDR-DQ11
NET "ddr_dq(12)"	LOC=U3	|	IOSTANDARD=LVCMOS18;		#Bank = 3, pin name = IO_L33P_M3DQ12_3,				Sch name = DDR-DQ12
NET "ddr_dq(13)"	LOC=U1	|	IOSTANDARD=LVCMOS18;		#Bank = 3, pin name = IO_L33N_M3DQ13_3,				Sch name = DDR-DQ13
NET "ddr_dq(14)"	LOC=V2	|	IOSTANDARD=LVCMOS18;		#Bank = 3, pin name = IO_L32P_M3DQ14_3,				Sch name = DDR-DQ14
NET "ddr_dq(15)"	LOC=V1	|	IOSTANDARD=LVCMOS18;		#Bank = 3, pin name = IO_L32N_M3DQ15_3,				Sch name = DDR-DQ15
NET "ddr_ad(0)"		LOC=M5	|	IOSTANDARD=LVCMOS18;		#Bank = 3, pin name = IO_L47P_M3A0_3,				Sch name = DDR-A0
NET "ddr_ad(1)"		LOC=L4	|	IOSTANDARD=LVCMOS18;		#Bank = 3, pin name = IO_L47N_M3A1_3,				Sch name = DDR-A1
NET "ddr_ad(2)"		LOC=K3	|	IOSTANDARD=LVCMOS18;		#Bank = 3, pin name = IO_L49N_M3A2_3,				Sch name = DDR-A2
NET "ddr_ad(3)"		LOC=M4	|	IOSTANDARD=LVCMOS18;		#Bank = 3, pin name = IO_L45P_M3A3_3,				Sch name = DDR-A3
NET "ddr_ad(4)"		LOC=K5	|	IOSTANDARD=LVCMOS18;		#Bank = 3, pin name = IO_L51N_M3A4_3,				Sch name = DDR-A4
NET "ddr_ad(5)"		LOC=G3	|	IOSTANDARD=LVCMOS18;		#Bank = 3, pin name = IO_L44P_GCLK21_M3A5_3,			Sch name = DDR-A5
NET "ddr_ad(6)"		LOC=G1	|	IOSTANDARD=LVCMOS18;		#Bank = 3, pin name = IO_L44N_GCLK20_M3A6_3,			Sch name = DDR-A6
NET "ddr_ad(7)"		LOC=K4	|	IOSTANDARD=LVCMOS18;		#Bank = 3, pin name = IO_L49P_M3A7_3,				Sch name = DDR-A7
NET "ddr_ad(8)"		LOC=C3	|	IOSTANDARD=LVCMOS18;		#Bank = 3, pin name = IO_L52P_M3A8_3,				Sch name = DDR-A8
NET "ddr_ad(9)"		LOC=C1	|	IOSTANDARD=LVCMOS18;		#Bank = 3, pin name = IO_L52N_M3A9_3,				Sch name = DDR-A9
NET "ddr_ad(10)" 	LOC=K6	|	IOSTANDARD=LVCMOS18;		#Bank = 3, pin name = IO_L51P_M3A10_3,				Sch name = DDR-A10
NET "ddr_ad(11)" 	LOC=B1	|	IOSTANDARD=LVCMOS18;		#Bank = 3, pin name = IO_L54N_M3A11_3,				Sch name = DDR-A11
NET "ddr_ad(12)" 	LOC=J4	|	IOSTANDARD=LVCMOS18;		#Bank = 3, pin name = IO_L53N_M3A12_3,				Sch name = DDR-A12
NET "ddr_cke"		LOC=J6	|	IOSTANDARD=LVCMOS18;		#Bank = 3, pin name = IO_L53P_M3CKE_3,				Sch name = DDR-CKE		#CLK ENABLE
NET "ddr_clk"  		LOC=F2	|	IOSTANDARD=DIFF_SSTL18_II;	#Bank = 3, pin name = IO_L45N_M3CLK_3,				Sch name = DDR-CK P		#+CLK
NET "ddr_clkb"		LOC=F1	|	IOSTANDARD=DIFF_SSTL18_II;	#Bank = 3, pin name = IO_L46P_M3CLKN_3,				Sch name = DDR-CK N		#-CLK	
NET "ddr_ba(0)"		LOC=E3	|	IOSTANDARD=LVCMOS18;		#Bank = 3, pin name = IO_L48P_M3BA0_3,				Sch name = DDR-BA0		#BANK ADDRESS INPUTS
NET "ddr_ba(1)"		LOC=E1	|	IOSTANDARD=LVCMOS18;		#Bank = 3, pin name = IO_L48N_M3BA1_3,				Sch name = DDR-BA1
NET "ddr_ba(2)"		LOC=D1	|	IOSTANDARD=LVCMOS18;		#Bank = 3, pin name = IO_L50N_M3BA2_3,				Sch name = DDR-BA2
NET "ddr_dm(1)"		LOC=H2	|	IOSTANDARD=LVCMOS18;		#Bank = 3, pin name = IO_L42P_GCLK25_TRDY2_M3UDM_3, Sch name = DDR-UDM	#DQ WRITE MASK ENABLE INPUTS
NET "ddr_dm(0)"		LOC=H1	|	IOSTANDARD=LVCMOS18;		#Bank = 3, pin name = IO_L42N_GCLK24_M3LDM_3,			Sch name = DDR-LDM	
NET "ddr_odt"		LOC=M3	|	IOSTANDARD=LVCMOS18;		#Bank = 3, pin name = IO_L45N_M3ODT_3,				Sch name = DDR-ODT		#ON-DIE TERMINATION
NET "ddr_we" 		LOC=D2 	|	IOSTANDARD=LVCMOS18;
NET "ddr_dqs(1)"	LOC=T2	|	IOSTANDARD=DIFF_SSTL18_II;	#Bank = 3, pin name = IO_L34P_M3UDQS_3, 			Sch name = DDR-UDQS P	#DATA STROBE INPUTS/OUTPUTS
NET "ddr_dqsn(1)"	LOC=T1	|	IOSTANDARD=DIFF_SSTL18_II;			#Bank = 3, pin name = IO_L34N_M3UDQSN_3,	Sch name = DDR-UDQS N
NET "ddr_dqs(0)"	LOC=L3	|	IOSTANDARD=DIFF_SSTL18_II;			#Bank = 3, pin name = IO_L39P_M3LDQS_3,		Sch name = DDR-LDQS P
NET "ddr_dqsn(0)"	 LOC=L1	|	IOSTANDARD=DIFF_SSTL18_II;			#Bank = 3, pin name = IO_L39N_M3LDQSN_3,	Sch name = DDR-LDQS N
NET "ddr_ras"		LOC=N4	|	IOSTANDARD=LVCMOS18;			#Bank = 3, pin name = IO_L43P_GCLK23_M3RASN_3,		Sch name = DDR-RAS	#ROW ADDRESS STROBE INPUT
NET "ddr_cas" 		LOC=P3	|	IOSTANDARD=LVCMOS18;			#Bank = 3, pin name = IO_L43N_GCLK22_IRDY2_M3CASN_3,	Sch name = DDR-CAS	#COLUMN ADDRESS STROBE INPUT

	