##########################################################################
# Target Board: Xilinx Spartan6 SP601 Board                       ##
##########################################################################

# ==== Clock inputs (USER CLK 27 MHz) ====
NET "clk27" LOC = "V10";
NET "clk27" PERIOD = 37ns HIGH 50%;

# ==== Clock inputs (DDR CLK 200 MHz) ====
NET "clk200_n" LOC = "K16";
NET "clk200_p" LOC = "K15";
NET "clk200_p" PERIOD = 5ns HIGH 50%;

NET erx_clk PERIOD = 40.000;
OFFSET = IN : 10.000 : BEFORE erx_clk;
NET etx_clk PERIOD = 40.000;
OFFSET = OUT : 20.000 : AFTER etx_clk;
OFFSET = IN : 10.000 : BEFORE etx_clk;

# Avoid false paths between main clock and DDR clock
NET "clkm"  TNM_NET = "clkm";
#NET "clkml" TNM_NET = "clkml";
#TIMESPEC "TS_clkm_clkml" = FROM "clkm" TO "clkml" TIG;
#TIMESPEC "TS_clkml_clkm" = FROM "clkml" TO "clkm" TIG;

#INST "clkgen0_xc3s_v_dll0" LOC = DCM_X2Y3;
#INST "clkgen0/xc3s.v/dll0" LOC = DCM_X2Y3;
#INST "ddr2sp0.ddrc0/ddr_phy0/ddr_phy0/sp3a.ddr_phy0/read_dll" LOC = DCM_X0Y1;
#INST "ddr2sp0.ddrc0_ddr_phy0_ddr_phy0_sp3a.ddr_phy0_read_dll" LOC = DCM_X0Y1;
#INST "ddr2sp0.ddrc0/ddr_phy0/ddr_phy0/sp3a.ddr_phy0/dll" LOC = DCM_X1Y0;
#INST "ddr2sp0_ddrc0_ddr_phy0_ddr_phy0_sp3a_ddr_phy0_dll" LOC = DCM_X1Y0;

# ==== Pushbuttons ====
NET reset	LOC = N4;
NET dsubre	LOC = P4;    # GPIO_BUTTON0

# ==== Discrete LEDs ====
NET led(0)	LOC = E13;
NET led(1)	LOC = C14;
NET led(2)	LOC = C4;
NET errorn	LOC = A4 | IOSTANDARD = LVCMOS25;

# ==== DIP Switches ====
NET sw(0)	LOC = D14;
NET sw(1)	LOC = E12;
NET sw(2)	LOC = F12;
NET sw(3)	LOC = V13;

# ==== DDR2 SDRAM (16-bit data buss) ====

NET "ddr_dq(*)"                                 IN_TERM = NONE;       
NET "ddr_dqs(*)"                                   IN_TERM = NONE;       
NET  "ddr_dq(*)"            IOSTANDARD = SSTL18_II;
NET  "ddr_ad(*)"             IOSTANDARD = SSTL18_II;
NET  "ddr_ba(*)"            IOSTANDARD = SSTL18_II;
NET  "ddr_dqs(*)"              IOSTANDARD = DIFF_SSTL18_II;
NET  "ddr_clk"               IOSTANDARD = DIFF_SSTL18_II;
NET  "ddr_clkb"             IOSTANDARD = DIFF_SSTL18_II;
NET  "ddr_cke"              IOSTANDARD = SSTL18_II;
NET  "ddr_ras"            IOSTANDARD = SSTL18_II;
NET  "ddr_cas"            IOSTANDARD = SSTL18_II;
NET  "ddr_we"             IOSTANDARD = SSTL18_II;
NET  "ddr_odt"              IOSTANDARD = SSTL18_II;
NET  "ddr_dm(*)"               IOSTANDARD = SSTL18_II;
NET  "ddr_rzq"                   IOSTANDARD = SSTL18_II;
NET  "ddr_zio"                   IOSTANDARD = SSTL18_II;

NET  "ddr_ad(0)"            LOC = "J7" ;
NET  "ddr_ad(10)"           LOC = "F4" ;
NET  "ddr_ad(11)"           LOC = "D3" ;
NET  "ddr_ad(12)"           LOC = "G6" ;
NET  "ddr_ad(1)"            LOC = "J6" ;
NET  "ddr_ad(2)"            LOC = "H5" ;
NET  "ddr_ad(3)"            LOC = "L7" ;
NET  "ddr_ad(4)"            LOC = "F3" ;
NET  "ddr_ad(5)"            LOC = "H4" ;
NET  "ddr_ad(6)"            LOC = "H3" ;
NET  "ddr_ad(7)"            LOC = "H6" ;
NET  "ddr_ad(8)"            LOC = "D2" ;
NET  "ddr_ad(9)"            LOC = "D1" ;
#
NET  "ddr_ba(0)"           LOC = "F2" ;
NET  "ddr_ba(1)"           LOC = "F1" ;
NET  "ddr_ba(2)"           LOC = "E1" ;
#Data
NET  "ddr_dq(0)"           LOC = "L2" ;
NET  "ddr_dq(10)"          LOC = "N2" ;
NET  "ddr_dq(11)"          LOC = "N1" ;
NET  "ddr_dq(12)"          LOC = "T2" ;
NET  "ddr_dq(13)"          LOC = "T1" ;
NET  "ddr_dq(14)"          LOC = "U2" ;
NET  "ddr_dq(15)"          LOC = "U1" ;
NET  "ddr_dq(1)"           LOC = "L1" ;
NET  "ddr_dq(2)"           LOC = "K2" ;
NET  "ddr_dq(3)"           LOC = "K1" ;
NET  "ddr_dq(4)"           LOC = "H2" ;
NET  "ddr_dq(5)"           LOC = "H1" ;
NET  "ddr_dq(6)"           LOC = "J3" ;
NET  "ddr_dq(7)"           LOC = "J1" ;
NET  "ddr_dq(8)"           LOC = "M3" ;
NET  "ddr_dq(9)"           LOC = "M1" ;
NET  "ddr_cas"           LOC = "K5" ;
NET  "ddr_clk"              LOC = "G3" ;
NET  "ddr_clkb"            LOC = "G1" ;
NET  "ddr_cke"             LOC = "H7" ;
NET  "ddr_dm(0)"                 LOC = "K3" ;
#
NET  "ddr_dqs(0)"                LOC = "L4" ;
#NET  "ddr_dqsn(0)"                LOC = "L3" ;
NET  "ddr_odt"                LOC = "K6" ;
NET  "ddr_ras"              LOC = "L5" ;
NET  "ddr_dm(1)"                LOC = "K4" ;
NET  "ddr_dqs(1)"               LOC = "P2" ;
NET  "ddr_we"               LOC = "E3" ;

# The specific pin below for RZQ is required for xc6slx16-csg324 
# revision 1.1 silicon to be compatible with calibrated input termination
# The ZIO pin can be assigned to any unused no connect (NC) pin within the MCB bank

NET  "ddr_rzq"                                  LOC = "C2" ;
NET  "ddr_zio"                                  LOC = "L6" ;

#
## ==== Ethernet PHY ====
NET reset_o2    LOC = L13 | IOSTANDARD = LVCMOS25;
NET erx_clk	LOC = L16 | IOSTANDARD = LVCMOS25;
NET etx_clk	LOC = B9  | IOSTANDARD = LVCMOS25;
NET erx_crs	LOC = M13 | IOSTANDARD = LVCMOS25;
NET erx_dv	LOC = N18 | IOSTANDARD = LVCMOS25;
NET erx_col	LOC = L14 | IOSTANDARD = LVCMOS25;
NET erx_er	LOC = P17 | IOSTANDARD = LVCMOS25;
NET erxd(0)	LOC = M14 | IOSTANDARD = LVCMOS25;
NET erxd(1)	LOC = U18 | IOSTANDARD = LVCMOS25;
NET erxd(2)	LOC = U17 | IOSTANDARD = LVCMOS25;
NET erxd(3)	LOC = T18 | IOSTANDARD = LVCMOS25;
NET erxd(4)	LOC = T17 | IOSTANDARD = LVCMOS25;
NET erxd(5)	LOC = N16 | IOSTANDARD = LVCMOS25;
NET erxd(6)	LOC = N15 | IOSTANDARD = LVCMOS25;
NET erxd(7)	LOC = P18 | IOSTANDARD = LVCMOS25;
NET etx_en	LOC = B8  | IOSTANDARD = LVCMOS25;
NET etx_er	LOC = A8  | IOSTANDARD = LVCMOS25;
NET emdc	LOC = N14 | IOSTANDARD = LVCMOS25;
NET emdio	LOC = P16 | IOSTANDARD = LVCMOS25;
NET etxd(0)	LOC = F8  | IOSTANDARD = LVCMOS25;
NET etxd(1)	LOC = G8  | IOSTANDARD = LVCMOS25;
NET etxd(2)	LOC = A6  | IOSTANDARD = LVCMOS25;
NET etxd(3)	LOC = B6  | IOSTANDARD = LVCMOS25;
NET etxd(4)	LOC = E6  | IOSTANDARD = LVCMOS25;
NET etxd(5)	LOC = F7  | IOSTANDARD = LVCMOS25;
NET etxd(6)	LOC = A5  | IOSTANDARD = LVCMOS25;
NET etxd(7)	LOC = C5  | IOSTANDARD = LVCMOS25;

##
##NET GTX_CLK	LOC = A9  | IOSTANDARD = LVCMOS18;
##NET INT        LOC = J13 | IOSTANDARD = LVCMOS18;
##NET MCLK	LOC = N6  | IOSTANDARD = LVCMOS18;
#
## ==== Debug UART (AHB) RS232 ====
NET dsurx	LOC = L12 | IOSTANDARD = LVCMOS25;
NET dsutx	LOC = K14 | IOSTANDARD = LVCMOS25;
#
## ==== Flash Memory ====
NET reset_o1    LOC = B3   | IOSTANDARD = LVCMOS25;
NET address(24)	LOC = F16  | IOSTANDARD = LVCMOS25;
NET address(23)	LOC = C17  | IOSTANDARD = LVCMOS25;
NET address(22)	LOC = C18  | IOSTANDARD = LVCMOS25;
NET address(21)	LOC = F14  | IOSTANDARD = LVCMOS25;
NET address(20)	LOC = G14  | IOSTANDARD = LVCMOS25;
NET address(19)	LOC = D17  | IOSTANDARD = LVCMOS25;
NET address(18)	LOC = D18  | IOSTANDARD = LVCMOS25;
NET address(17)	LOC = H12  | IOSTANDARD = LVCMOS25;
NET address(16)	LOC = G13  | IOSTANDARD = LVCMOS25;
NET address(15)	LOC = E16  | IOSTANDARD = LVCMOS25;
NET address(14)	LOC = E18  | IOSTANDARD = LVCMOS25;
NET address(13)	LOC = K12  | IOSTANDARD = LVCMOS25;
NET address(12)	LOC = K13  | IOSTANDARD = LVCMOS25;
NET address(11)	LOC = F17  | IOSTANDARD = LVCMOS25;
NET address(10)	LOC = F18  | IOSTANDARD = LVCMOS25;
NET address(9)	LOC = H13  | IOSTANDARD = LVCMOS25;
NET address(8)	LOC = H14  | IOSTANDARD = LVCMOS25;
NET address(7)	LOC = H15  | IOSTANDARD = LVCMOS25;
NET address(6)	LOC = H16  | IOSTANDARD = LVCMOS25;
NET address(5)	LOC = G16  | IOSTANDARD = LVCMOS25;
NET address(4)	LOC = G18  | IOSTANDARD = LVCMOS25;
NET address(3)	LOC = J16  | IOSTANDARD = LVCMOS25;
NET address(2)	LOC = J18  | IOSTANDARD = LVCMOS25;
NET address(1)	LOC = K17 | IOSTANDARD = LVCMOS25;
NET address(0)	LOC = K18 | IOSTANDARD = LVCMOS25;
#
NET data(7)	LOC = R5   | IOSTANDARD = LVCMOS25;
NET data(6)	LOC = T3   | IOSTANDARD = LVCMOS25;
NET data(5)	LOC = R3   | IOSTANDARD = LVCMOS25;
NET data(4)	LOC = V5   | IOSTANDARD = LVCMOS25;
NET data(3)	LOC = U5   | IOSTANDARD = LVCMOS25;
NET data(2)	LOC = V14  | IOSTANDARD = LVCMOS25;
NET data(1)	LOC = T14  | IOSTANDARD = LVCMOS25;
NET data(0)	LOC = R13  | IOSTANDARD = LVCMOS25;
NET oen		LOC = L18  | IOSTANDARD = LVCMOS25;
NET writen	LOC = M16  | IOSTANDARD = LVCMOS25;
NET romsn	LOC = L17  | IOSTANDARD = LVCMOS25;
