

Prompt for target technology
CONFIG_SYN_INFERRED
  Selects the target technology for memory and pads.
  The following are available:

  - Inferred: Generic FPGA or ASIC targets if your synthesis tool
    is capable of inferring RAMs and pads automatically.

  - Actel ProAsic/P/3, IGLOO/2, RTG4 and Axcelerator FPGAs
  - Aeroflex UT25CRH Rad-Hard 0.25 um CMOS
  - Altera: Most Altera FPGA families
  - Altera-CycloneIII: Altera Cyclone-III/IV FPGA family
  - Altera-Stratix: Altera Stratix FPGA family
  - Altera-StratixII: Altera Stratix/Cyclone-II FPGA families
  - Altera-StratixIII: Altera Stratix-III FPGA family
  - Altera-StratixIV: Altera Stratix-IV FPGA family
  - Altera-StratixV: Altera Stratix-V FPGA family
  - ATC18: Atmel-Nantes 0.18 um rad-hard CMOS
  - Lattice : EC/ECP/XP FPGAs
  - Quicklogic : Eclipse/E/II FPGAs
  - UMC-0.18 : UMC 0.18 um CMOS with Virtual Silicon libraries
  - Xilinx-Spartan/2/3/6: Xilinx Spartan/2/3/6 libraries
  - Xilinx-Spartan3E: Xilinx Spartan3E libraries
  - Xilinx-Virtex/E: Xilinx Virtex/E libraries
  - Xilinx-Virtex2/4/5/6/7: Xilinx Virtex2/4/5/6/7 libraries

  Note: Level of technology support depends on type of GRLIB
  distribution. A technology may be present in this list while the
  tech support files are missing from the GRLIB distribution.
  Actel support is only available in commercial and FT distributions.

  Additional target technologies are available that are not selectable
  via the xconfig tool.

Ram library
CONFIG_MEM_VIRAGE
  Select RAM generators for ASIC targets.

Transceiver type
CONFIG_TRANS_GTP0
  Select the transceiver type used in your FPGA

Infer ram
CONFIG_SYN_INFER_RAM
  Say Y here if you want the synthesis tool to infer your
  RAM automatically. Say N to directly instantiate technology-
  specific RAM cells for the selected target technology package.

Infer pads
CONFIG_SYN_INFER_PADS
  Say Y here if you want the synthesis tool to infer pads.
  Say N to directly instantiate technology-specific pads from
  the selected target technology package.

No async reset
CONFIG_SYN_NO_ASYNC
  Say Y here if you disable asynchronous reset in some of the IP cores.
  Might be necessary if the target library does not have cells with
  asynchronous set/reset.

Scan support
CONFIG_SYN_SCAN
  Say Y here to enable scan support in some cores. This will enable
  the scan support generics where available and add logic to make
  the design testable using full-scan.

Use Virtex CLKDLL for clock synchronisation
CONFIG_CLK_INFERRED
  Certain target technologies include clock generators to scale or
  phase-adjust the system and SDRAM clocks. This is currently supported
  for Xilinx, Altera and Proasic3 FPGAs. Depending on technology, you
  can select to use the Xilinx CKLDLL macro (Virtex, VirtexE, Spartan1/2),
  the Xilinx DCM (Virtex-2, Spartan3, Virtex-4), the Xilinx PLLE2 (Virtex-7,
  Kintex-7, Artix-4), the Altera ALTDLL (Stratix, Cyclone), or the 
  Proasic3 PLL. Choose the 'inferred' option to skip a clock generator.

Clock multiplier
CONFIG_CLK_MUL
  When using the Xilinx DCM, Xilinx PLLE2 or Altera ALTPLL, 
  the system clock can be multiplied with a factor of 2 - 32, 
  and divided by a factor of 1 - 32. This makes it possible to 
  generate almost any desired processor frequency. When using 
  the Xilinx CLKDLL generator, the resulting frequency scale f
  actor (mul/div) must be one of 1/2, 1 or 2. On Proasic3, 
  the factor can be 1 - 128. 
  
  WARNING: The resulting clock must be within the limits specified
  by the target FPGA family.

Clock divider
CONFIG_CLK_DIV
  When using the Xilinx DCM, Xilinx PLLE2 or Altera ALTPLL, 
  the system clock can be multiplied with a factor of 2 - 32, 
  and divided by a factor of 1 - 32. This makes it possible to 
  generate almost any desired processor frequency. When using 
  the Xilinx CLKDLL generator, the resulting frequency scale f
  actor (mul/div) must be one of 1/2, 1 or 2. On Proasic3, 
  the factor can be 1 - 128. 
  
  WARNING: The resulting clock must be within the limits specified
  by the target FPGA family.

Output clock divider
CONFIG_OCLK_DIV
  When using the Proasic3 PLL, the system clock is generated by three
  parameters: input clock multiplication, input clock division and
  output clock division. Only certain values of these parameters
  are allowed, but unfortunately this is not documented by Actel.
  To find the correct values, run the Libero Smartgen tool and
  insert you desired input and output clock frequencies in the
  Static PLL configurator. The mul/div factors can then be read
  out from tool.

Output clock divider, 2nd clock
CONFIG_OCLKB_DIV
  See help for 'Ouput division factor'. Set this to 0 to disable the
  second clock output.

Output clock divider, 3rd clock
CONFIG_OCLKC_DIV
  See help for 'Ouput division factor'. Set this to 0 to disable the
  third clock output.

System clock multiplier
CONFIG_CLKDLL_1_2
  The Xilinx CLKDLL can scale the input clock with a factor of 0.5, 1.0, 
  or 2.0. Useful when the target board has an oscillator with a too high 
  (or low) frequency for your design. The divided clock will be used as the
  main clock for the whole processor (except PCI and ethernet clocks).

System clock multiplier
CONFIG_DCM_2_3
  The Xilinx DCM and Altera ALTDLL can scale the input clock with a large
  range of factors. Useful when the target board has an oscillator with a 
  too high (or low) frequency for your design. The divided clock will
  be used as the main clock for the whole processor (except PCI and 
  ethernet clocks). NOTE: the resulting frequency must be at least
  24 MHz or the DCM and ALTDLL might not work.

Enable CLKDLL for PCI clock
CONFIG_PCI_CLKDLL
  Say Y here to re-synchronize the PCI clock using a 
  Virtex BUFGDLL macro. Will improve PCI clock-to-output 
  delays on the expense of input-setup requirements.

Use PCI clock system clock
CONFIG_PCI_SYSCLK
  Say Y here to the PCI clock to generate the system clock.
  The PCI clock can be scaled using the DCM or CLKDLL to 
  generate a suitable processor clock.

External SDRAM clock feedback
CONFIG_CLK_NOFB
  Say Y here to disable the external clock feedback to synchronize the
  SDRAM clock. This option is necessary if your board or design does not
  have an external clock feedback that is connected to the pllref input
  of the clock generator.

Number of processors
CONFIG_PROC_NUM
  The number of processor cores. The LEON3MP design can accomodate
  up to 4 LEON3 processor cores. Use 1 unless you know what you are
  doing ...

Force values from example configuration
CONFIG_LEON3_MIN
  If you select any other value than Custom-configuration then the
  configuration choices will be forced to settings corresponding to
  the selected example configuration. The example configurations are
  described in the document LEON/GRLIB Design and Configuration Guide
  located at doc/guide.pdf.

  Due to limitations in the configuration tool it is not possible to
  update all choices without first saving the configuration and
  restarting the tool. Perform the steps below to set the processor
  configuration to example configuration values: 

  1. Select example configuration (MIN, GP, HP). This will result
     in most processor configuration menus being disabled.
  2. Go back to the main menu and select Save and Exit
  3. Start the xconfig tool again
  4. Go into processor configuration and select Custom-configuration.
     All configuration values can now be changed again and have been
     initialized to example configuration that was selected earlier.
  5. Make any changes and then quit xconfig via Save and Exit

  Some options set from the example configuration may need to be changed.
  One such setting is the FPU multiplier, if the FPU is enabled, where
  timing is improved for several FPGA technologies by selecting the
  technology specific multiplier and where the DW multiplier is generally
  a good choice for ASIC.

Number of SPARC register windows
CONFIG_IU_NWINDOWS
  The SPARC architecture (and LEON) allows 2 - 32 register windows.
  However, any number except 8 will require that you modify and
  recompile your run-time system or kernel. Unless you know what
  you are doing, use 8.

SPARC V8 multiply and divide instruction
CONFIG_IU_V8MULDIV
  If you say Y here, the SPARC V8 multiply and divide instructions
  will be implemented. The instructions are: UMUL, UMULCC, SMUL,
  SMULCC, UDIV, UDIVCC, SDIV, SDIVCC. In code containing frequent
  integer multiplications and divisions, significant performance
  increase can be achieved. Emulated floating-point operations will
  also benefit from this option.

  By default, the gcc compiler does not emit multiply or divide
  instructions and your code must be compiled with -mv8 to see any
  performance increase. On the other hand, code compiled with -mv8
  will generate an illegal instruction trap when executed on processors
  with this option disabled.

  The divider consumes approximately 2 kgates, the multiplier 6 kgates.

Multiplier latency
CONFIG_IU_MUL_LATENCY_2
  Implementation options for the integer multiplier.

  Type        Implementation              issue-rate/latency
  2-clocks    32x32 pipelined multiplier     1/2
  4-clocks    16x16 standard multiplier      4/4
  5-clocks    16x16 pipelined multiplier     4/5

MAC operation
CONFIG_IU_MUL_MAC
  If you say Y here, the SPARC V8e UMAC/SMAC (multiply-accumulate)
  instructions will be enabled. The instructions implement a
  single-cycle 16x16->32 bits multiply with a 40-bits accumulator.
  The details of these instructions can be found in the LEON manual,
  This option is only available when 16x16 multiplier is used.

Multiplier structure
CONFIG_IU_MUL_INFERRED
  Structure options for the integer multiplier. The multiplier
  can be implemented with the following structures:

  * Inferred by the synthesis tool
  * Generated using Module Generators from NTNU
  * Using technology specific netlists (TechSpec)
  * Using Synopsys Designware (DW02_mult and DW_mult_pipe)

Branch prediction
CONFIG_IU_BP
  Enabling branch prediction will improve performance with
  up to 20%, depending on application. The timing and area
  overhead are minor, so it is recommended to always enable
  this option.

Single vector trapping
CONFIG_IU_SVT
  Single-vector trapping is a SPARC V8e option to reduce code-size
  in small applications. If enabled, the processor will jump to
  the address of trap 0 (tt = 0x00) for all traps. No trap table
  is then needed. The trap type is present in %psr.tt and must
  be decoded by the O/S. Saves 4 Kbyte of code, but increases
  trap and interrupt overhead. Currently, the only O/S supporting
  this option is eCos. To enable SVT, the O/S must also set bit 13
  in %asr17.

Load latency
CONFIG_IU_LDELAY
  Defines the pipeline load delay (= pipeline cycles before the data
  from a load instruction is available for the next instruction).
  One cycle gives best performance, but might create a critical path
  on targets with slow (data) cache memories. A 2-cycle delay can
  improve timing but will reduce performance with about 5%.

Reset address
CONFIG_IU_RSTADDR
  By default, a SPARC processor starts execution at address 0.
  With this option, any 4-kbyte aligned reset start address can be
  choosen. Keep at 0 unless you really know what you are doing.

Power-down
CONFIG_PWD
  Say Y here to enable the power-down feature of the processor.
  Might reduce the maximum frequency slightly on FPGA targets.
  For details on the power-down operation, see the LEON3 manual.

Hardware watchpoints
CONFIG_IU_WATCHPOINTS
  The processor can have up to 4 hardware watchpoints, allowing to
  create both data and instruction breakpoints at any memory location,
  also in PROM. Each watchpoint will use approximately 500 gates.
  Use 0 to disable the watchpoint function.

Floating-point enable
CONFIG_FPU_ENABLE
  Say Y here to enable the floating-point interface for the GRFPU-lite
  or GRFPU. Note that no FPUs are provided with the GPL version
  of GRLIB. Both FPUs are commercial cores and must be obtained separately.

FPU selection
CONFIG_FPU_GRFPU
  Select between Gaisler Research's GRFPU and GRFPU-lite FPUs. All cores
  are fully IEEE-754 compatible and support all SPARC FPU instructions.

GRFPU Multiplier
CONFIG_FPU_GRFPU_INFMUL
  On FPGA targets choose inferred multiplier. For ASIC implementations
  choose between Synopsys Design Ware (DW) multiplier or Module
  Generator (ModGen) multiplier. The DW multiplier gives better results
  (smaller area and better timing) but requires a DW license.
  The ModGen multiplier is part of GRLIB and does not require a license.
  The Technology Specific multiplier option selects a pre-designed
  multiplier using technology specific macrocells when available, else
  an inferred multiplier is used.

Shared GRFPU
CONFIG_FPU_GRFPU_SH
  If enabled multiple CPU cores will share one GRFPU.

GRFPC Configuration
CONFIG_FPU_GRFPC0
  Configures the GRFPU-LITE controller.

  In simple configuration controller executes FP instructions
  in parallel with  integer instructions. FP operands are fetched
  in the register file stage and the result is written in the write
  stage. This option uses least area resources.

  Data forwarding configuration gives ~ 10 % higher FP performance than
  the simple configuration by adding data forwarding between the pipeline
  stages.

  Non-blocking controller allows FP load and store instructions to
  execute in parallel with FP instructions. The performance increase is
  ~ 20 % for FP applications. This option uses most logic resources and
  is suitable for ASIC implementations.

Floating-point netlist
CONFIG_FPU_NETLIST
  Say Y here to use a VHDL netlist of the GRFPU-Lite. This is
  only available in certain versions of grlib.

Enable Instruction cache
CONFIG_ICACHE_ENABLE
  The instruction cache should always be enabled to allow
  maximum performance. Some low-end system might want to
  save area and disable the cache, but this will reduce
  the performance with a factor of 2 - 3.

Enable Data cache
CONFIG_DCACHE_ENABLE
  The data cache should always be enabled to allow
  maximum performance. Some low-end system might want to
  save area and disable the cache, but this will reduce
  the performance with a factor of 2 at least.

Instruction cache associativity
CONFIG_ICACHE_ASSO1
  The instruction cache can be implemented as a multi-way cache with
  1 - 4 ways. Higher associativity usually increases the cache hit
  rate and thereby the performance. The downside is higher power
  consumption and increased gate-count for tag comparators.

  Note that a 1-way cache is effectively a direct-mapped cache.

Instruction cache way size
CONFIG_ICACHE_SZ1
  The size of each way in the instuction cache (kbytes). Valid values
  are 1 - 64 in binary steps. Note that the full range is only supported
  by the generic and virtex2 targets. Most target packages are limited
  to 2 - 16 kbyte. Large way size gives higher performance but might
  affect the maximum frequency (on ASIC targets). The total instruction
  cache size is the number of way multiplied with the way size.

Instruction cache line size
CONFIG_ICACHE_LZ16
  The instruction cache line size. Can be set to either 16 or 32
  bytes per line. Instruction caches typically benefit from larger
  line sizes, but on small caches it migh be better with 16 bytes/line
  to limit eviction miss rate.

Instruction cache replacement algorithm
CONFIG_ICACHE_ALGORND
  Cache replacement algorithm for caches with 2 - 4 ways. The 'random'
  algorithm selects the way to evict randomly. The least-recently-replaced
  (LRR) algorithm evicts the way least recently replaced. The least-
  recently-used (LRU) algorithm evicts the way least recently accessed.
  The random algorithm uses a simple 1- or 2-bit counter to select
  the eviction way and has low area overhead. The LRR scheme uses one
  extra bit in the tag ram and has therefore also low area overhead.
  However, the LRR scheme can only be used with 2-way caches. The LRU
  scheme has typically the best performance but also highest area overhead.
  A 2-way LRU uses 1 flip-flop per line, a 3-way LRU uses 3 flip-flops
  per line, and a 4-way LRU uses 5 flip-flops per line to store the access
  history.

Instruction cache locking
CONFIG_ICACHE_LOCK
  Say Y here to enable cache locking in the instruction cache.
  Locking can be done on cache-line level, but will increase the
  width of the tag ram with one bit. If you don't know what
  locking is good for, it is safe to say N.

Data cache associativity
CONFIG_DCACHE_ASSO1
  The data cache can be implemented as a multi-way cache with
  1 - 4 ways. Higher associativity usually increases the cache hit
  rate and thereby the performance. The downside is higher power
  consumption and increased gate-count for tag comparators.

  Note that a 1-way cache is effectively a direct-mapped cache.

  If the MMU is enabled then bus snooping is required to avoid
  aliasing effects in multi-way caches.

Data cache way size
CONFIG_DCACHE_SZ1
  The size of each way in the data cache (kbytes). Valid values are
  1 - 64 in binary steps. Note that the full range is only supported
  by the generic and virtex2 targets. Most target packages are limited
  to 2 - 16 kbyte. A large cache gives higher performance but the
  data cache is timing critical an a too large setting might affect
  the maximum frequency (on ASIC targets). The total data cache size
  is the number of ways multiplied with the way size.

  Note that when the MMU is enabled, bus snooping should also be
  enabled and the data cache way size should not exceed the MMU
  page size.

Data cache line size
CONFIG_DCACHE_LZ16
  The data cache line size. Can be set to either 16 or 32 bytes per
  line. A smaller line size gives better associativity and higher
  cache hit rate, but requires a larger tag memory.

Data cache replacement algorithm
CONFIG_DCACHE_ALGORND
  See the explanation for instruction cache replacement algorithm.

Data cache locking
CONFIG_DCACHE_LOCK
  Say Y here to enable cache locking in the data cache.
  Locking can be done on cache-line level, but will increase the
  width of the tag ram with one bit. If you don't know what
  locking is good for, it is safe to say N.

Data cache snooping
CONFIG_DCACHE_SNOOP
  Say Y here to enable data cache snooping on the AHB bus.

  With snooping, AHB writes by other masters to data that is in the
  data cache will be automatically detected and the cache line will
  be marked as invalid. This simplifies software design in systems
  with DMA units or multiple processors accessing the same memory.
  It is a requirement (together with separate physical/snoop tags)
  to run Linux on more than one CPU.

  Depending on the separate snoop tags option, snooping will be
  implemented using either dual-port (common tags) or two-port
  RAMs (separate tags). A workaround if dual port RAMs are
  not available for the target technology is to use separate
  snoop tags even if it is not needed otherwise.

Separate snoop tags
CONFIG_DCACHE_SNOOP_SEPTAG
  Enable a separate memory to store the data tags used for snooping.
  This is necessary when snooping support is wanted in systems
  with MMU, typically for SMP systems. In this case, the snoop
  tags will contain the physical tag address while the normal
  tags contain the virtual tag address.

  When separate snoop tags are enabled, the tag RAMs will be implemented
  using two-port RAMs instead of dual-port RAMs. A workaround if
  dual port RAMs are not available for the target technology is
  therefore to use separate snoop tags even if it is not needed.

  Note that it is also possible to implement the tags using single port
  RAMs with valid bits in flip-flops.

Single-port RAM for separate tags
CONFIG_DCACHE_SNOOP_SP
  Use single-port RAM to implement separate physical tags. This leads
  to the cache tag valid bits being implemented in flip-flops.

Fixed cacheability map
CONFIG_CACHE_FIXED
  If this variable is 0, the cacheable memory regions are defined
  by the AHB plug&play information (default). To overriden the
  plug&play settings, this variable can be set to indicate which
  areas should be cached. The value is treated as a 16-bit hex value
  with each bit defining if a 256 Mbyte segment should be cached or not.
  The right-most (LSB) bit defines the cacheability of AHB address
  0 - 256 MByte, while the left-most bit (MSB) defines AHB address
  3840 - 4096 MByte. If the bit is set, the corresponding area is
  cacheable. A value of 00F3 defines address 0 - 0x20000000 and
  0x40000000 - 0x80000000 as cacheable.

Local data ram
CONFIG_DCACHE_LRAM
  Say Y here to add a local ram to the data cache controller.
  Accesses to the ram (load/store) will be performed at 0 waitstates
  and store data will never be written back to the AHB bus.

Size of local data ram
CONFIG_DCACHE_LRAM_SZ1
  Defines the size of the local data ram in Kbytes. Note that most
  technology libraries do not support larger rams than 16 Kbyte.

Start address of local data ram
CONFIG_DCACHE_LRSTART
  Defines the 8 MSB bits of start address of the local data ram.
  By default set to 8f (start address = 0x8f000000), but any value
  (except 0) is possible. Note that the local data ram 'shadows'
  a 16 Mbyte block of the address space.

MMU enable
CONFIG_MMU_ENABLE
  Say Y here to enable the Memory Management Unit.

MMU split icache/dcache table lookaside buffer
CONFIG_MMU_COMBINED
  Select "combined" for a combined icache/dcache table lookaside buffer,
  "split" for a split icache/dcache table lookaside buffer

MMU tlb replacement scheme
CONFIG_MMU_REPARRAY
  Select "LRU" to use the "least recently used" algorithm for TLB
  replacement, or "Increment" for a simple incremental replacement
  scheme.

Combined i/dcache tlb
CONFIG_MMU_I2
  Select the number of entries for the instruction TLB, or the
  combined icache/dcache TLB if such is used.

Split tlb, dcache
CONFIG_MMU_D2
  Select the number of entries for the dcache TLB.

Fast writebuffer
CONFIG_MMU_FASTWB
  Only selectable if split tlb is enabled. In case fast writebuffer is
  enabled the tlb hit will be made concurrent to the cache hit. This
  leads to higher store performance, but increased power and area.

MMU pagesize
CONFIG_MMU_PAGE_4K
  The deafult SPARC V8 SRMMU page size is 4 Kbyte. This limits the
  cache way size to 4 Kbyte, and total data cache size to 16 Kbyte,
  when the MMU is used. To increase the maximum data cache size,
  the MMU pages size can be increased to up 32 Kbyte. This will
  give a maximum data cache size of 128 Kbyte.

  Note that an MMU page size different than 4 Kbyte will require
  a special linux tool-chain if glibc is used. If you don't know
  what you are doing, stay with 4 Kbyte.

DSU enable
CONFIG_DSU_ENABLE
  The debug support unit (DSU) allows non-intrusive debugging and tracing
  of both executed instructions and AHB transfers. If you want to enable
  the DSU, say Y here and select the configuration below.

Trace buffer enable
CONFIG_DSU_TRACEBUF
  Say Y to enable the trace buffer. The buffer is not necessary for
  debugging, only for tracing instructions and data transfers.

Enable instruction tracing
CONFIG_DSU_ITRACE
  If you say Y here, an instruction trace buffer will be implemented
  in each processor. The trace buffer will trace executed instructions
  and their results, and place them in a circular buffer. The buffer
  can be read out by any AHB master, and in particular by the debug
  communication link.

Size of trace buffer
CONFIG_DSU_ITRACESZ1
  Select the buffer size (in kbytes) for the instruction trace buffer.
  Each line in the buffer needs 16 bytes. A 128-entry buffer will thus
  need 2 kbyte.

Enable two-port instruction trace buffer
CONFIG_DSU_ITRACE_2P
  If you say Y here, the instruction trace buffer will be implemented
  in each processor with a two-port RAM. It will then be possible
  to read the buffer through its second port, while the processor 
  instructions are being traced.

Enable AHB tracing
CONFIG_DSU_ATRACE
  If you say Y here, an AHB trace buffer will be implemented in the
  debug support unit processor. The AHB buffer will trace all transfers
  on the AHB bus and save them in a circular buffer. The trace buffer
  can be read out by any AHB master, and in particular by the debug
  communication link.

Size of trace buffer
CONFIG_DSU_ATRACESZ1
  Select the buffer size (in kbytes) for the AHB trace buffer.
  Each line in the buffer needs 16 bytes. A 128-entry buffer will thus
  need 2 kbyte.

AHB trace buffer filters
CONFIG_DSU_AFILT
  If you say Y here, the debug support unit will allow filtering of
  AHB trace buffer inputs. Filters allow to select which masters,
  slaves and types of accesses that should be saved to the buffer.

AHB statistics outputs
CONFIG_DSU_ASTAT
  If you say Y here, the debug support unit will enable its statistics
  outputs. These outputs can be connected to a L4STAT unit in order to
  count events on the AHB bus. This option will also enable AHB trace
  buffer filters.


LEON3FT enable
CONFIG_LEON3FT_EN
  Say Y here to use the fault-tolerant LEON3FT core instead of the
  standard non-FT LEON3.

IU Register file protection
CONFIG_IUFT_NONE
  Select the FT implementation in the LEON3FT integer unit
  register file. The options include parity, parity with
  sparing, 7-bit BCH, 7-bit BCH with on-the-fly (OTF)
  correction, technology-specific and TMR.

FPU Register file protection
CONFIG_FPUFT_NONE
  Say Y to enable SEU protection of the FPU register file.
  The GRFPU-Lite will be protected with parity, PDMR and TMR.
  The GRFPU can use PDMR or TMR only.

Cache memory error injection
CONFIG_RF_ERRINJ
  Say Y here to enable error injection in to the IU/FPU regfiles.
  Affects only simulation.

Cache memory protection
CONFIG_CACHE_FT_NONE
  Enable SEU error-correction in the cache memories.

  None - No protection
  Parity     - Technology agnostic parity protection
  SECDEC-BCH - SECDED for cache, slow and large area overhead
  TechSpec   - Use target technology protection

  The recommended setting is Parity. Target technologies
  with built in protection on SRAMs can have area savings
  with TechSpec. Currently this option should only be used
  for Microsemi RTG4.

Cache memory error injection
CONFIG_CACHE_ERRINJ
  Say Y here to enable error injection in to the cache memories.
  Affects only simulation.

Leon3ft netlist
CONFIG_LEON3_NETLIST
  Say Y here to use a VHDL netlist of the LEON3FT. This is
  only available in certain versions of grlib.

IU assembly printing
CONFIG_IU_DISAS
  Enable printing of executed instructions to the console.

IU assembly printing in netlist
CONFIG_IU_DISAS_NET
  Enable printing of executed instructions to the console also
  when simulating a netlist. NOTE: with this option enabled, it
  will not be possible to pass place&route.

32-bit program counters
CONFIG_DEBUG_PC32
  Since the LSB 2 bits of the program counters always are zero, they are
  normally not implemented. If you say Y here, the program counters will
  be implemented with full 32 bits, making debugging of the VHDL model
  much easier. Turn of this option for synthesis or you will be wasting
  area.

LEON3 Statistical Module
CONFIG_STAT_ENABLE
  Say Y here to enable the LEON3 Statistical Unit. The unit consists
  of a number of timers that can count various processor and MMU/FPU
  events to allow analysis of processor behavior and performance. 

Number of L3S counters
CONFIG_STAT_CNT 
  Set the number of 32-bit counters in the unit (1 - 32).

Number of L3S accumulative counters
CONFIG_STAT_NMAX
  If this value is higher than 0, the core will include functionality 
  for tracking the longest consecutive time that an event is active or 
  inactive. The functionality will be available for the nmax first 
  counters. This value must not exceed the number of available counters

SPARC V8E non-privileged ASI access
CONFIG_NP_ASI
  In SPARC-V8E implementations providing for non-privileged ASI access
  functions, LOAD and STORE from Alternate space instructions
  accessing ASI’s 0016 - 7F16 are privileged instructions. LOAD and
  STORE from Alternate space instructions accessing ASI’s 8016 - FF16
  are non-privileged instructions. This option enables this non-
  privileged behavior.
CONFIG_AHB_DEFMST
  Sets the default AHB master (see AMBA 2.0 specification for definition).
  Should not be set to a value larger than the number of AHB masters - 1.
  For highest processor performance, leave it at 0.

Default AHB master
CONFIG_AHB_RROBIN
  Say Y here to enable round-robin arbitration of the AHB bus. A N will
  select fixed priority, with the master with the highest bus index having
  the highest priority.

Support AHB split-transactions
CONFIG_AHB_SPLIT
  Say Y here to enable AHB split-transaction support in the AHB arbiter.
  Unless you actually have an AHB slave that can generate AHB split
  responses, say N and save some gates.

Enable full PnP decoding
CONFIG_AHB_FPNPEN
  Say Y here to enable full decoding of the PnP configuration records in
  in the AHB arbiter. When disabled the user-defined registers in the
  PnP configuration records are not mapped in the configuration area.

IO area start address
CONFIG_AHB_IOADDR
  Selects the MSB adddress (HADDR[31:20]) of the AHB IO area, as defined 
  in the plug&play extentions of the AMBA bus. Should be kept to FFF 
  unless you really know what you are doing.

APB bridge address          
CONFIG_APB_HADDR
  Selects the MSB adddress (HADDR[31:20]) of the APB bridge. Should be
  kept at 800 for software compatibility. 

AHB monitor                 
CONFIG_AHB_MON
  Say Y to enable the AHB bus monitor. The monitor will check for
  illegal AHB transactions during simulation. It has no impact on
  synthesis.

Report AHB errors
CONFIG_AHB_MONERR
  Print out detected AHB violations on console.

Report AHB warnings
CONFIG_AHB_MONWAR
  Print out detected AHB warnings on console.

Write trace to console
CONFIG_AHB_DTRACE
  Say yes here to write a trace of all AHB transfers to the
  simulator console. Has not impact on final netlist.

DSU enable
CONFIG_DSU_UART
  Say Y to enable the AHB uart (serial-to-AHB). This is the most
  commonly used debug communication link.

JTAG Enable
CONFIG_DSU_JTAG
  Say Y to enable the JTAG debug link (JTAG-to-AHB). Debugging is done 
  with GRMON through the boards JTAG chain at speeds of up to 800 kbits/s. 

  The TAP controller can be implemented in custom macros on
  Altera, Actel Proasic/3 and Xilinx devices. The commercial
  GRLIB also includes a generic TAP controller in VHDL.

  Supported JTAG cables are Xilinx Parallel Cable III and IV, 
  Xilinx Platform cables (USB), and Altera parallel and USB cables,
  Amontech JTAG key, various FTDI chip based USB/JTAG devices, and
  Actel Flash Pro 3/4 cable.

Ethernet DSU enable
CONFIG_DSU_ETH
  Say Y to enable the Ethernet Debug Communication Link (EDCL). The link
  provides a DSU gateway between ethernet and the AHB bus. Debugging is
  done at 10 or 100 Mbit/s, using the GRMON debug monitor. You must
  enable the GRETH Ethernet MAC for this option to become active.

Size of EDCL trace buffer
CONFIG_DSU_ETHSZ1
  Select the buffer size (in kbytes) for the EDCL. 1 or 2 kbyte is
  usually enough, while a larger buffer will increase the transfer rate.
  When operating at 100 Mbit, use a buffer size of at least 8 kbyte for
  maximum throughput.

MSB IP address
CONFIG_DSU_IPMSB
  Set the MSB 16 bits of the IP address of the EDCL.

LSB IP address
CONFIG_DSU_IPLSB
  Set the LSB 16 bits of the IP address of the EDCL.

MSB ethernet address
CONFIG_DSU_ETHMSB
  Set the MSB 24 bits of the ethernet address of the EDCL.

LSB ethernet address
CONFIG_DSU_ETHLSB
  Set the LSB 24 bits of the ethernet address of the EDCL.

Programmable MAC/IP address
CONFIG_DSU_ETH_PROG
  Say Y to make the LSB 4 bits of the EDCL MAC and IP address
  configurable using the ethi.edcladdr inputs.
PROM/SRAM memory controller
CONFIG_SRCTRL
  Say Y here to enable a simple (and small) PROM/SRAM memory controller.
  The controller has a fixed number of waitstates, and is primarily
  intended for FPGA implementations. The RAM data bus is always 32 bits,
  the PROM can be configured to either 8 or 32 bits (hardwired).

8-bit memory support
CONFIG_SRCTRL_8BIT
  If you say Y here, the simple PROM/SRAM memory controller will
  implement 8-bit PROM mode.

PROM waitstates
CONFIG_SRCTRL_PROMWS
  Select the number of waitstates for PROM access.

RAM waitstates
CONFIG_SRCTRL_RAMWS
  Select the number of waitstates for RAM access.

IO waitstates
CONFIG_SRCTRL_IOWS
  Select the number of waitstates for IO access.

Read-modify-write support
CONFIG_SRCTRL_RMW
  Say Y here to perform byte- and half-word writes as a
  read-modify-write sequence. This is necessary if your
  SRAM does not have individual byte enables. If you are
  unsure, it is safe to say Y.

SRAM bank select
CONFIG_SRCTRL_SRBANKS
  Select number of SRAM banks.

SRAM bank size select
CONFIG_SRCTRL_BANKSZ
  Select size of SRAM banks in kBytes.

PROM address bit select
CONFIG_SRCTRL_ROMASEL
  Select address bit for PROM bank decoding.
Leon2 memory controller
CONFIG_MCTRL_LEON2
  Say Y here to enable the LEON2 memory controller. The controller
  can access PROM, I/O, SRAM and SDRAM. The bus width for PROM
  and SRAM is programmable to 8-, 16- or 32-bits.

8-bit memory support
CONFIG_MCTRL_8BIT
  If you say Y here, the PROM/SRAM memory controller will support
  8-bit mode, i.e. operate from 8-bit devices as if they were 32-bit.
  Say N to save a few hundred gates.

16-bit memory support
CONFIG_MCTRL_16BIT
  If you say Y here, the PROM/SRAM memory controller will support
  16-bit mode, i.e. operate from 16-bit devices as if they were 32-bit.
  Say N to save a few hundred gates.

Write strobe feedback
CONFIG_MCTRL_WFB
  If you say Y here, the PROM/SRAM write strobes (WRITEN, WEN) will
  be used to enable the data bus drivers during write cycles. This
  will guarantee that the data is still valid on the rising edge of
  the write strobe. If you say N, the write strobes and the data bus
  drivers will be clocked on the rising edge, potentially creating
  a hold time problem in external memory or I/O. However, in all
  practical cases, there is enough capacitance in the data bus lines
  to keep the value stable for a few (many?) nano-seconds after the
  buffers have been disabled, making it safe to say N and remove a 
  combinational path in the netlist that might be difficult to 
  analyze.

Write strobe feedback
CONFIG_MCTRL_5CS
  If you say Y here, the 5th (RAMSN[4]) SRAM chip select signal will
  be enabled. If you don't intend to use it, say N and save some gates.

SDRAM controller enable
CONFIG_MCTRL_SDRAM
  Say Y here to enabled the PC100/PC133 SDRAM controller. If you don't
  intend to use SDRAM, say N and save about 1 kgates.

SDRAM controller inverted clock
CONFIG_MCTRL_SDRAM_INVCLK
  If you say Y here, the SDRAM controller output signals will be delayed
  with 1/2 clock in respect to the SDRAM clock. This will allow the used
  of an SDRAM clock which in not strictly in phase with the internal 
  clock. This option will limit the SDRAM frequency to 40 - 50 MHz.

  On FPGA targets without SDRAM clock synchronizations through PLL/DLL, 
  say Y. On ASIC targets, say N and tell your foundry to balance the 
  SDRAM clock output.

SDRAM separate address buses
CONFIG_MCTRL_SDRAM_SEPBUS
  Say Y here if your SDRAM is connected through separate address
  and data buses (SA & SD). This is the case on the GR-CPCI-XC2V6000
  board, but not on the GR-PCI-XC2V3000 or Avnet XCV1500E boards.

64-bit data bus
CONFIG_MCTRL_SDRAM_BUS64
  Say Y here to enable 64-bit SDRAM data bus.

Page burst enable
CONFIG_MCTRL_PAGE
  Say Y here to enable SDRAM page burst operation. This will implement
  read operations using page bursts rather than 8-word bursts and save
  about 500 gates (100 LUTs). Note that not all SDRAM supports page 
  burst, so use this option with care.

Programmable page burst enable
CONFIG_MCTRL_PROGPAGE
  Say Y here to enable programmable SDRAM page burst operation. This
  will allow to dynamically enable/disable page burst by setting
  bit 17 in MCFG2.

SDRAM controller enable
CONFIG_SDCTRL
  Say Y here to enabled a 32/64-bit PC133 SDRAM controller. 

SDRAM controller inverted clock
CONFIG_SDCTRL_INVCLK
  If you say Y here, the SDRAM clock will be inverted in respect to the
  system clock and the SDRAM signals. This will limit the SDRAM frequency
  to 50/66 MHz, but has the benefit that you will not need a PLL to
  generate the SDRAM clock. On FPGA targets, say Y. On ASIC targets,
  say N and tell your foundry to balance the SDRAM clock output.

64-bit data bus
CONFIG_SDCTRL_BUS64
  Say Y here to enable 64-bit data bus.

Page burst enable
CONFIG_SDCTRL_PAGE
  Say Y here to enable SDRAM page burst operation. This will implement
  read operations using page bursts rather than 8-word bursts and save
  about 500 gates (100 LUTs). Note that not all SDRAM supports page 
  burst, so use this option with care.

Programmable page burst enable
CONFIG_SDCTRL_PROGPAGE
  Say Y here to enable programmable SDRAM page burst operation. This
  will allow to dynamically enable/disable page burst by setting
  bit 17 in MCFG2.

On-chip rom
CONFIG_AHBROM_ENABLE
  Say Y here to add a block on on-chip rom to the AHB bus. The ram
  provides 0-waitstates read access,  burst support, and 8-, 16- 
  and 32-bit data size. The rom will be syntheised into block rams
  on Xilinx and Altera FPGA devices, and into gates on ASIC 
  technologies. GRLIB includes a utility to automatically create
  the rom VHDL model (ahbrom.vhd) from an ELF file. Refer to the GRLIB
  documentation for details.

On-chip rom address
CONFIG_AHBROM_START
  Set the start address of AHB ROM (HADDR[31:20]). The ROM will occupy
  a 1 Mbyte slot at the selected address. Default is 000, corresponding
  to AHB address 0x00000000. When address 0x0 is selected, the rom area
  of any other memory controller is set to 0x10000000 to avoid conflicts.

Enable pipeline register for on-chip rom
CONFIG_AHBROM_PIPE
  Say Y here to add a data pipeline register to the on-chip rom.
  This should be done when the rom is implemenented in (ASIC) gates,
  or in logic cells on FPGAs. Do not use this option when the rom is
  implemented in block rams. If enabled, the rom will operate with 
  one waitstate.

On-chip ram
CONFIG_AHBRAM_ENABLE
  Say Y here to add a block on on-chip ram to the AHB bus. The ram
  provides 0-waitstates read access and 0/1 waitstates write access.
  All AHB burst types are supported, as well as 8-, 16- and 32-bit
  data size.

On-chip ram size
CONFIG_AHBRAM_SZ1
  Set the size of the on-chip AHB ram. The ram is infered/instantiated
  as four byte-wide ram slices to allow byte and half-word write
  accesses. It is therefore essential that the target package can
  infer byte-wide rams. This is currently supported on the generic,
  virtex, virtex2, proasic and axellerator targets.

On-chip ram address
CONFIG_AHBRAM_START
  Set the start address of AHB RAM (HADDR[31:20]). The RAM will occupy
  a 1 Mbyte slot at the selected address. Default is A00, corresponding
  to AHB address 0xA0000000.

On-chip ram pipeline stage
CONFIG_AHBRAM_PIPE
  Set this option to add an extra pipeline stage to the read data of the 
  on-chip RAM. This can improve timing, especially when the memory is 
  large, at the cost of adding an additional cycle delay on read.
Gaisler Ethernet MAC enable
CONFIG_GRETH_ENABLE
  Say Y here to enable the Gaisler Research Ethernet MAC . The MAC has 
  one AHB master interface to read and write packets to memory, and one
  APB slave interface for accessing the control registers. 

Gaisler Ethernet 1G MAC enable
CONFIG_GRETH_GIGA
  Say Y here to enable the Gaisler Research 1000 Mbit Ethernet MAC . 
  The 1G MAC is only available in the commercial version of GRLIB,
  so do NOT enable it if you are using the GPL version.

CONFIG_GRETH_FIFO4
  Set the depth of the receive and transmit FIFOs in the MAC core.
  The MAC core will perform AHB burst read/writes with half the
  size of the FIFO depth.

CONFIG_GRETH_FT
  Enable fault-tolerance (parity with sparing) for internal RAM
  in Ethernet core. Note that FT for EDCL buffer is enabled via
  separate setting.

CONFIG_GRETH_EDCLFT
  Enable protection for EDCL buffer. This is typically not used as
  the EDCL debug link is not used in harsh environments.
CAN interface enable
CONFIG_CAN_ENABLE
  Say Y here to enable the CAN interace from OpenCores. The core has one
  AHB slave interface for accessing the control registers. The CAN core
  ir register-compatible with the SAJ1000 core from Philips.

CAN register address
CONFIG_CANIO
  The control registers of the CAN core occupy 4 kbyte, and are 
  mapped in the AHB bus I/O area (0xFFF00000 - 0xFFFFF000). This setting
  defines at which address in the I/O area the registers appear (HADDR[19:8]).

CAN interrupt
CONFIG_CANIRQ
  Defines which interrupt number the CAN core will generate.

CAN loob-back testing
CONFIG_CANLOOP
  If you say Y here, the receiver and trasmitter of the CAN core will
  be connected together in a loop-back fashion. This will make it 
  possible to perform loop-back test, but not data will be sent
  or received from the outside. ONLY for testing!

CAN Synchronous reset
CONFIG_CAN_SYNCRST
  If you say Y here, the CAN core will be implemented with
  synchronous reset rather than asynchronous. This is needed
  when the target library does not implement registers with
  async reset. Unless you know what you are doing, say N.

CAN FT memories
CONFIG_CAN_FT
  If you say Y here, the CAN FIFOs will be implemented using
  SEU protected RAM blocks. Only applicable to the FT version
  of grlib.
PCI interface type
CONFIG_GRPCI2_MASTER
  Enable the PCI initiator.

PCI interface type
CONFIG_GRPCI2_TARGET
  Enable the PCI target.

PCI DMA controller
CONFIG_GRPCI2_DMA
  Enable the PCI DMA controller.

PCI device-id
CONFIG_GRPCI2_DEVICEID
  Sets the PCI device ID in the PCI configuration area.

PCI vendor-id
CONFIG_GRPCI2_VENDORID
  Sets the PCI vendor ID in the PCI configuration area.

PCI class-code
CONFIG_GRPCI2_CLASS
  Sets the PCI class-code in the PCI configuration area.

PCI revision-id
CONFIG_GRPCI2_REVID
  Sets the PCI revision ID in the PCI configuration area.

PCI Capability pointer
CONFIG_GRPCI2_CAPPOINT
  Sets the PCI capability pointer in the PCI configuration area. 
  Sets the offset for the extended PCI Configuration Space.

PCI Next Capability pointer
CONFIG_GRPCI2_NEXTCAPPOINT
  Sets the PCI capability pointer of second item in the extended 
  capability list (in the PCI configuration) If no user defined 
  extended capability item is implemented this should be set to 0.

PCI BAR size
CONFIG_GRPCI2_BAR0
  Set the size of BAR 0. 26 => bit[31:26] in the BAR register is 
  implemented. BAR size = 64 MiB.

PCI BAR size
CONFIG_GRPCI2_BAR1
  see help for BAR0.

PCI BAR size
CONFIG_GRPCI2_BAR2
  see help for BAR0.

PCI BAR size
CONFIG_GRPCI2_BAR3
  see help for BAR0.

PCI BAR size
CONFIG_GRPCI2_BAR4
  see help for BAR0.

PCI BAR size
CONFIG_GRPCI2_BAR5
  see help for BAR0.

FIFO depth
CONFIG_GRPCI2_FIFO8
  The number words in each PCI FIFO buffer.

FIFO count
CONFIG_GRPCI2_FIFOCNT1
  The number buffer implemented in each FIFO.

GRPCI2 PCI little-endian
CONFIG_GRPCI2_ENDIAN
  Set the default PCI bus endianes.

GRPCI2 Device Interrupt
CONFIG_GRPCI2_DINT
  Enable the device to assert the PCI int signal.

GRPCI2 Device Interrupt mask
CONFIG_GRPCI2_DINTMASK
  The default mask. '1' = enable.

GRPCI2 Host Interrupt
CONFIG_GRPCI2_HINT
  Enable the device to sample the PCI int signal.

GRPCI2 Host Interrupt mask
CONFIG_GRPCI2_HINTMASK
  The default mask. '1' = enable.

GRPCI2 PCI trace buffer
CONFIG_GRPCI2_TRACE0
  Set the depth of the PCI trace buffer.

GRPCI2 Input pad bypass
CONFIG_GRPCI2_BYPASS
  If the PADs do not implements output-to-input bypass, this option 
  implements the bypass in the core.

Extended Configuration Space mappit
CONFIG_GRPCI2_EXTCFG
  The mapping of the user defined Extended PCI Configuration Space 
  to AMBA.

PCI arbiter enable
CONFIG_PCI_ARBITER
  To enable a PCI arbiter, say Y here.

PCI APB interface enable
CONFIG_PCI_ARBITER_APB
  Say Y here to enable the APB interface on the PCI arbiter. This makes
  it possible to dynamically re-assign PCI master priorities. See the
  PCI arbiter manual for details.

PCI arbiter request signals
CONFIG_PCI_ARBITER_NREQ
  The number of PCI bus request/grant pairs. Should be not
  be more than 8. Note that the processor needs one, so the
  minimum should be 2.

Spacewire link
CONFIG_SPW_ENABLE
  Say Y here to enable one or more Spacewire serial links. The links
  are based on the GRSPW core from Gaisler Research.

Number of spacewire links
CONFIG_SPW_NUM
  Select the number of links to implement. Each link will be a
  separate AHB master and APB slave for configuration.

AHB FIFO depth
CONFIG_SPW_AHBFIFO4
  Select the AHB FIFO depth (in 32-bit words).

RX FIFO depth
CONFIG_SPW_RXFIFO16
  Select the receiver FIFO depth (in bytes).

RMAP protocol
CONFIG_SPW_RMAP
  Enable hardware target support for the RMAP protocol (
  draft C for GRSPW1 and ECSS-E-ST-50-11C Draft V1.3 
  for GRSPW2).

RMAP Buffer depth
CONFIG_SPW_RMAPBUF2
  Select the size of the RMAP buffer (in bytes).

RMAP CRC
CONFIG_SPW_RMAPCRC
  Enable hardware calculation of the RMAP CRC checksum. RMAP CRC
  is always enabled when the RMAP hardware target is enabled so this
  parameter will have no effect in that case.

Rx unaligned
CONFIG_SPW_RXUNAL
  Enable support for byte writes used for non word-aligned 
  receiver buffer addresses. Without this enabled data will
  still be written at the correct location but complete words
  will always be written so data outside the intended boundaries
  might be overwritten.

Netlists
CONFIG_SPW_NETLIST
  Use the netlist version of GRSPW. This option is required if
  you have not licensed the source code of the Spacewire core.
  Currently only supported for Xilinx and Actel FPGAs.
  The AHB/RX FIFO sizes should be set to 16 word/byte. If the
  RMAP is enabled, set the buffer size to 128 bytes. Other netlist
  configurations can be requested from Gaisler Research.

Spacewire FT
CONFIG_SPW_FT
  Say Y here to implement the Spacewire block rams with fault-tolerance
  against SEU errors.

Spacewire core
CONFIG_SPW_GRSPW1
  Select to use GRSPW1 core or GRSPW2 core.

DMA channels
CONFIG_SPW_DMACHAN
  Set the number of DMA channels for the GRSPW2 core.
  Set to 1 for now ...

Ports
CONFIG_SPW_PORTS
  Set the number of SpaceWire ports for the GRSPW2 core

Same clock for SpaceWire receiver and transmitter
CONFIG_SPW_RTSAME            
  Say Y here if the same clock is connected to both the receiver
  and transmitter in the GRSPW2 core. This will remove two
  asynchronous resets and some synchronization logic. This is only
  applicable for the SDR and DDR inputs modes.


Receiver clock type
CONFIG_SPW_RX_SDR
  Selects the input clocking scheme for the GRSPW2. SDR means that the
  core samples data and strobe using single data rate registers at the
  receiver clock frequency. DDR is the same except DDR registers are used.
  Xor selects the traditional self clocking scheme using a xor gate. 
  Aeroflex sets the receiver in a mode compatible with the Aeroflex
  SpaceWire transceiver.

Receiver clock type
CONFIG_SPW_TX_SDR
  Selects the output clocking scheme for the GRSPW2. SDR means that the
  core transmits data and strobe using single data rate registers at the
  transmitter clock frequency. DDR is the same except DDR registers are used.
  Aeroflex sets the transmitter in a mode compatible with the Aeroflex
  SpaceWire transceiver.
UART1 enable
CONFIG_UART1_ENABLE
  Say Y here to enable UART1, or the console UART. This is needed to
  get any print-out from LEON3 systems regardless of operating system.

UART1 FIFO
CONFIG_UA1_FIFO1
  The UART has configurable transmitt and receive FIFO's, which can
  be set to 1 - 32 bytes. Use 1 for minimum area, or 8 - 32 for
  maximum throughput.


UART2 enable
CONFIG_UART2_ENABLE
  Say Y here to enable UART2, or the secondary UART. This UART can be
  used to connect a second console (uClinux) or to control external
  equipment.

UART2 FIFO
CONFIG_UA2_FIFO1
  The UART has configurable transmitt and receive FIFO's, which can
  be set to 1 - 32 bytes. Use 1 for minimum area, or 8 - 32 for
  maximum throughput.

LEON3 interrupt controller
CONFIG_IRQ3_ENABLE
  Say Y here to enable the LEON3 interrupt controller. This is needed
  if you want to be able to receive interrupts. Operating systems like
  Linux, RTEMS and eCos needs this option to be enabled. If you intend
  to use the Bare-C run-time and not use interrupts, you could disable
  the interrupt controller and save about 500 gates.

LEON3 interrupt controller broadcast
CONFIG_IRQ3_BROADCAST_ENABLE
  If enabled the broadcast register is used to determine which
  interrupt should be sent to all cpus instead of just the first
  one that consumes it.

Secondary interrupts
CONFIG_IRQ3_SEC
  The interrupt controller handles 15 interrupts by default (1 - 15).
  These correspond to the 15 SPARC asyncronous traps (0x11 - 0x1F),
  and AMBA interrupts 1 - 15. This option will enable 16 additional
  (secondary) interrupts, corresponding to AMBA interrupts 16 - 31.
  The secondary interrupts will be multiplexed onto one of the first
  15 interrupts. The total number of handled interrupts can then
  be up to 30 (14 primary and 16 secondary).

Number of interrupts
CONFIG_IRQ3_NSEC
  Defines which of the first 15 interrupts should be used for the
  secondary (16 - 31) interrupts. Interrupt 15 should be avoided
  since it is not maskable by the processor.
Timer module enable
CONFIG_GPT_ENABLE
  Say Y here to enable the Modular Timer Unit. The timer unit consists
  of one common scaler and up to 7 independent timers. The timer unit
  is needed for Linux, RTEMS, eCos and the Bare-C run-times.

Timer module enable
CONFIG_GPT_NTIM
  Set the number of timers in the timer unit (1 - 7).

Scaler width
CONFIG_GPT_SW
  Set the width if the common pre-scaler (2 - 16 bits). The scaler
  is used to divide the system clock down to 1 MHz, so 8 bits should
  be sufficient for most implementations (allows clocks up to 256 MHz).

Timer width
CONFIG_GPT_TW
  Set the width if the timers (2 - 32 bits). 32 bits is recommended
  for the Bare-C run-time, lower values (e.g. 16 bits) can work with
  RTEMS and Linux.

Timer Interrupt
CONFIG_GPT_IRQ
  Set the interrupt number for the first timer. Remaining timers will
  have incrementing interrupts, unless the separate-interrupts option
  below is disabled.

Watchdog enable
CONFIG_GPT_WDOGEN
  Say Y here to enable the watchdog functionality in the timer unit.

Watchdog time-out value
CONFIG_GPT_WDOG
  This value will be loaded in the watchdog timer at reset.

GPIO port
CONFIG_GRGPIO_ENABLE
  Say Y here to enable a general purpose I/O port. The port can be
  configured from 1 - 32 bits, whith each port signal individually
  programmable as input or output. The port signals can also serve
  as interrupt inputs.

GPIO port witdth
CONFIG_GRGPIO_WIDTH
  Number of bits in the I/O port. Must be in the range of 1 - 32.

GPIO interrupt mask
CONFIG_GRGPIO_IMASK
  The I/O port interrupt mask defines which bits in the I/O port
  should be able to create an interrupt. 

UART debugging
CONFIG_DEBUG_UART
  During simulation, the output from the UARTs is printed on the
  simulator console. Since the ratio between the system clock and
  UART baud-rate is quite high, simulating UART output will be very
  slow. If you say Y here, the UARTs will print a character as soon
  as it is stored in the transmitter data register. The transmitter
  ready flag will be permanently set, speeding up simulation. However,
  the output on the UART tx line will be garbled.  Has not impact on
  synthesis, but will cause the LEON test bench to fail.

FPU register tracing
CONFIG_DEBUG_FPURF
  If you say Y here, all writes to the floating-point unit register file
  will be printed on the simulator console.

