/////////////////////////////////////////////////////
// FPGA reset
/////////////////////////////////////////////////////

NET "FPGA_CPU_RESET_B" LOC ="J15";
NET "FPGA_CPU_RESET_B" PULLUP;
NET "FPGA_CPU_RESET_B" TIG;

/////////////////////////////////////////////////////
// Board clocks
/////////////////////////////////////////////////////
# Main clock
NET "USER_CLKSYS" period = 10.000;
NET "USER_CLKSYS" LOC ="L29";

# User supplied clock
#NET "USER_CLK2" LOC ="K29";

#
#NET "USER_SMA_CLK_P" LOC ="K30";
#NET "USER_SMA_CLK_N" LOC ="L30";

#
#NET "SATACLK_QO_P" LOC ="F4";
#NET "SATACLK_QO_N" LOC ="F3";

#
#NET "LVDS_CLKEXT_P_C" LOC ="V4";
#NET "LVDS_CLKEXT_N_C" LOC ="V3";

# System ACE clock
NET "SYSACE_FPGA_CLK" LOC ="L17";
NET "SYSACE_FPGA_CLK" period = 29.000;

/////////////////////////////////////////////////////
// Design clocks
/////////////////////////////////////////////////////

NET "clkm" 		TNM_NET = "clkm";
NET "clkml0" 		TNM_NET = "clkml0";
NET "sgmii_refclk" PERIOD = 8.000 ;

#NET "clkml1" 		TNM_NET = "clkml1";

############################################################################
# Enable these if you run the DDR2 controller unsynchronized from AHB clock
#TIMESPEC "TS_clkm_clkml0" = FROM "clkm" TO "clkml0" TIG;
#TIMESPEC "TS_clkm_clkml1" = FROM "clkm" TO "clkml1" TIG;
#TIMESPEC "TS_clkml0_clkm" = FROM "clkml0" TO "clkm" TIG;
#TIMESPEC "TS_clkml1_clkm" = FROM "clkml1" TO "clkm" TIG;
############################################################################

NET "pciclk"            TNM_NET="pciclk";
TIMESPEC "TS_clkm_pciclk" = FROM "clkm" TO "pciclk" TIG;
TIMESPEC "TS_pciclk_clkm" = FROM "pciclk" TO "clkm" TIG;

# PCI clock feedback. PCI_P_CLK5_R is generated by FPGA
# and PCI_P_CLK5 is the feedback.
NET "PCI_P_CLK5" period = 30.000;

#NET "*dqinl*" MAXDELAY = 1900 ps;
#NET "ddrsp0.ddrc0/ddr32.ddrc/rwdata*" MAXDELAY = 2100 ps;
#NET "ddrsp0.ddrc1/ddr32.ddrc/rwdata*" MAXDELAY = 2100 ps;
#NET "*rclk180b" MAXDELAY = 2040 ps;


/////////////////////////////////////////////////////
// Delays
/////////////////////////////////////////////////////

OFFSET = OUT : 11.000 : AFTER PCI_P_CLK5;
OFFSET = IN : 7.000 : BEFORE PCI_P_CLK5;

/////////////////////////////////////////////////////
// VGA clocks
/////////////////////////////////////////////////////
# Use only when SVGA core is enabled

#NET "clkvga" TNM_NET = "clkvga" | PERIOD = 15.385;
#NET "clk25" TNM_NET = "clk25" | PERIOD = 40.000;
#NET "clk40" TNM_NET = "clk40" | PERIOD = 25.000;
#NET "clk65" TNM_NET = "clk65" | PERIOD = 15.385;
#TIMESPEC "TSPLB_TFT25" = FROM "clkm" TO "clk25" TIG;
#TIMESPEC "TSPLB_TFT40" = FROM "clkm" TO "clk40" TIG;
#TIMESPEC "TSPLB_TFT65" = FROM "clkm" TO "clk65" TIG;
#TIMESPEC "TSTFT25_PLB" = FROM "clk25" TO "clkm" TIG;
#TIMESPEC "TSTFT25_TFT40" = FROM "clk25" TO "clk40" TIG;
#TIMESPEC "TSTFT25_TFT65" = FROM "clk25" TO "clk65" TIG;
#TIMESPEC "TSTFT40_PLB" = FROM "clk40" TO "clkm" TIG;
#TIMESPEC "TSTFT40_TFT25" = FROM "clk40" TO "clk25" TIG;
#TIMESPEC "TSTFT40_TFT65" = FROM "clk40" TO "clk65" TIG;
#TIMESPEC "TSTFT65_PLB" = FROM "clk65" TO "clkm" TIG;
#TIMESPEC "TSTFT65_TFT25" = FROM "clk65" TO "clk25" TIG;
#TIMESPEC "TSTFT65_TFT40" = FROM "clk65" TO "clk40" TIG;

/////////////////////////////////////////////////////
// IDELAYCTRL LOC properties
/////////////////////////////////////////////////////

INST "ddrsp0.ddrc0/nftphy.ddr_phy0/ddr_phy0/seppads.phywop/xc4v.ddr_phy0/idelctrl.0.u" LOC = "IDELAYCTRL_X0Y3";
INST "ddrsp0.ddrc0/nftphy.ddr_phy0/ddr_phy0/seppads.phywop/xc4v.ddr_phy0/idelctrl.1.u" LOC = "IDELAYCTRL_X0Y6";
# Not used when instantiating 32 bits
INST "ddrsp0.ddrc0/nftphy.ddr_phy0/ddr_phy0/seppads.phywop/xc4v.ddr_phy0/idelctrl.2.u" LOC = "IDELAYCTRL_X0Y4";
INST "ddrsp0.ddrc0/nftphy.ddr_phy0/ddr_phy0/seppads.phywop/xc4v.ddr_phy0/idelctrl[0].u" LOC = "IDELAYCTRL_X0Y3";
INST "ddrsp0.ddrc0/nftphy.ddr_phy0/ddr_phy0/seppads.phywop/xc4v.ddr_phy0/idelctrl[1].u" LOC = "IDELAYCTRL_X0Y6";
# Not used when instantiating 32 bits
INST "ddrsp0.ddrc0/nftphy.ddr_phy0/ddr_phy0/seppads.phywop/xc4v.ddr_phy0/idelctrl[2].u" LOC = "IDELAYCTRL_X0Y4";

INST "ddrsp0.ddrc1/nftphy.ddr_phy0/ddr_phy0/seppads.phywop/xc4v.ddr_phy0/idelctrl.0.u" LOC = "IDELAYCTRL_X0Y2";
INST "ddrsp0.ddrc1/nftphy.ddr_phy0/ddr_phy0/seppads.phywop/xc4v.ddr_phy0/idelctrl.1.u" LOC = "IDELAYCTRL_X0Y7";
# Not used when instantiating 32 bits
INST "ddrsp0.ddrc1/nftphy.ddr_phy0/ddr_phy0/seppads.phywop/xc4v.ddr_phy0/idelctrl.2.u" LOC = "IDELAYCTRL_X0Y8";
INST "ddrsp0.ddrc1/nftphy.ddr_phy0/ddr_phy0/seppads.phywop/xc4v.ddr_phy0/idelctrl[0].u" LOC = "IDELAYCTRL_X0Y2";
INST "ddrsp0.ddrc1/nftphy.ddr_phy0/ddr_phy0/seppads.phywop/xc4v.ddr_phy0/idelctrl[1].u" LOC = "IDELAYCTRL_X0Y7";
# Not used when instantiating 32 bits
INST "ddrsp0.ddrc1/nftphy.ddr_phy0/ddr_phy0/seppads.phywop/xc4v.ddr_phy0/idelctrl[2].u" LOC = "IDELAYCTRL_X0Y8";

/////////////////////////////////////////////////////
// Flash
/////////////////////////////////////////////////////

NET "FLASH_WE_B" LOC ="AM28";
NET "FLASH_WAIT" LOC ="W11";
NET "FLASH_RESET_B" LOC ="K7";
NET "FLASH_OE_B" LOC ="AM13";
NET "FLASH_D(9)" LOC ="AL15";
NET "FLASH_D(8)" LOC ="AL16";
NET "FLASH_D(7)" LOC ="AN13";
NET "FLASH_D(6)" LOC ="AP13";
NET "FLASH_D(5)" LOC ="AK28";
NET "FLASH_D(4)" LOC ="AK29";
NET "FLASH_D(3)" LOC ="AN14";
NET "FLASH_D(2)" LOC ="AM14";
NET "FLASH_D(15)" LOC ="AN30";
NET "FLASH_D(14)" LOC ="AP30";
NET "FLASH_D(13)" LOC ="AK17";
NET "FLASH_D(12)" LOC ="AL17";
NET "FLASH_D(11)" LOC ="AN29";
NET "FLASH_D(10)" LOC ="AP28";
NET "FLASH_D(1)" LOC ="AK27";
NET "FLASH_D(0)" LOC ="AJ26";
NET "FLASH_CLK" LOC ="AN28";
NET "FLASH_CE_B" LOC ="AL14";
NET "FLASH_ADV_B" LOC ="AL29";
NET "FLASH_A(9)" LOC ="N15";
NET "FLASH_A(8)" LOC ="N14";
NET "FLASH_A(7)" LOC ="N28";
NET "FLASH_A(6)" LOC ="N29";
NET "FLASH_A(5)" LOC ="M14";
NET "FLASH_A(4)" LOC ="M13";
NET "FLASH_A(3)" LOC ="N30";
NET "FLASH_A(21)" LOC ="AL30";
NET "FLASH_A(20)" LOC ="AM29";
NET "FLASH_A(2)" LOC ="M29";
NET "FLASH_A(19)" LOC ="N25";
NET "FLASH_A(18)" LOC ="P25";
NET "FLASH_A(17)" LOC ="P18";
NET "FLASH_A(16)" LOC ="P17";
NET "FLASH_A(15)" LOC ="P26";
NET "FLASH_A(14)" LOC ="N26";
NET "FLASH_A(13)" LOC ="M16";
NET "FLASH_A(12)" LOC ="N16";
NET "FLASH_A(11)" LOC ="P27";
NET "FLASH_A(10)" LOC ="P28";
NET "FLASH_A(1)" LOC ="N13";
NET "FLASH_A(0)" LOC ="P13";
# These are mapped exclusively for flash on the SoC
#NET "SYSACE_FLASH_CFGA1" LOC ="AK12";
#NET "SYSACE_FLASH_CFGA0" LOC ="AK13";
#NET "FLASH_A(23)" LOC ="AK12";
#NET "FLASH_A(22)" LOC ="AK13";

/////////////////////////////////////////////////////
// DDR2
/////////////////////////////////////////////////////

# DIMM1
NET "DIMM1_DDR2_WE_B" LOC ="V40";
NET "DIMM1_DDR2_S_B(1)" LOC ="AE37";
NET "DIMM1_DDR2_S_B(0)" LOC ="AU42";
NET "DIMM1_DDR2_RAS_B" LOC ="V41";
NET "DIMM1_DDR2_PLL_CLKIN_P" LOC ="Y39";
NET "DIMM1_DDR2_PLL_CLKIN_N" LOC ="Y38";
NET "DIMM1_DDR2_ODT(1)" LOC ="AF37";
NET "DIMM1_DDR2_ODT(0)" LOC ="AV41";
NET "DIMM1_DDR2_DQS_P(8)" LOC ="AH34";
NET "DIMM1_DDR2_DQS_P(8)" IOSTANDARD = SSTL18_II_DCI;
NET "DIMM1_DDR2_DQS_N(8)" LOC ="AG34";
NET "DIMM1_DDR2_DQS_N(8)" IOSTANDARD = SSTL18_II_DCI;
NET "DIMM1_DDR2_DQS_P(7)" LOC ="AF35";
NET "DIMM1_DDR2_DQS_P(7)" IOSTANDARD = DIFF_SSTL18_II_DCI;
NET "DIMM1_DDR2_DQS_N(7)" LOC ="AF36";
NET "DIMM1_DDR2_DQS_N(7)" IOSTANDARD = DIFF_SSTL18_II_DCI;
NET "DIMM1_DDR2_DQS_P(6)" LOC ="AE35";
NET "DIMM1_DDR2_DQS_P(6)" IOSTANDARD = DIFF_SSTL18_II_DCI;
NET "DIMM1_DDR2_DQS_N(6)" LOC ="AF34";
NET "DIMM1_DDR2_DQS_N(6)" IOSTANDARD = DIFF_SSTL18_II_DCI;
NET "DIMM1_DDR2_DQS_P(5)" LOC ="AT39";
NET "DIMM1_DDR2_DQS_P(5)" IOSTANDARD = DIFF_SSTL18_II_DCI;
NET "DIMM1_DDR2_DQS_N(5)" LOC ="AR39";
NET "DIMM1_DDR2_DQS_N(5)" IOSTANDARD = DIFF_SSTL18_II_DCI;
NET "DIMM1_DDR2_DQS_P(4)" LOC ="AV40";
NET "DIMM1_DDR2_DQS_P(4)" IOSTANDARD = DIFF_SSTL18_II_DCI;
NET "DIMM1_DDR2_DQS_N(4)" LOC ="AU39";
NET "DIMM1_DDR2_DQS_N(4)" IOSTANDARD = DIFF_SSTL18_II_DCI;
NET "DIMM1_DDR2_DQS_P(3)" LOC ="AR40";
NET "DIMM1_DDR2_DQS_P(3)" IOSTANDARD = DIFF_SSTL18_II_DCI;
NET "DIMM1_DDR2_DQS_N(3)" LOC ="AT40";
NET "DIMM1_DDR2_DQS_N(3)" IOSTANDARD = DIFF_SSTL18_II_DCI;
NET "DIMM1_DDR2_DQS_P(2)" LOC ="AC40";
NET "DIMM1_DDR2_DQS_P(2)" IOSTANDARD = DIFF_SSTL18_II_DCI;
NET "DIMM1_DDR2_DQS_N(2)" LOC ="AC39";
NET "DIMM1_DDR2_DQS_N(2)" IOSTANDARD = DIFF_SSTL18_II_DCI;
NET "DIMM1_DDR2_DQS_P(1)" LOC ="AE40";
NET "DIMM1_DDR2_DQS_P(1)" IOSTANDARD = DIFF_SSTL18_II_DCI;
NET "DIMM1_DDR2_DQS_N(1)" LOC ="AD40";
NET "DIMM1_DDR2_DQS_N(1)" IOSTANDARD = DIFF_SSTL18_II_DCI;
NET "DIMM1_DDR2_DQS_P(0)" LOC ="AB39";
NET "DIMM1_DDR2_DQS_P(0)" IOSTANDARD = DIFF_SSTL18_II_DCI;
NET "DIMM1_DDR2_DQS_N(0)" LOC ="AC38";
NET "DIMM1_DDR2_DQS_N(0)" IOSTANDARD = DIFF_SSTL18_II_DCI;
NET "DIMM1_DDR2_DQM(8)" LOC ="AD33";
NET "DIMM1_DDR2_DQM(7)" LOC ="AV39";
NET "DIMM1_DDR2_DQM(6)" LOC ="AK35";
NET "DIMM1_DDR2_DQM(5)" LOC ="AN40";
NET "DIMM1_DDR2_DQM(4)" LOC ="AG37";
NET "DIMM1_DDR2_DQM(3)" LOC ="AC36";
NET "DIMM1_DDR2_DQM(2)" LOC ="AP41";
NET "DIMM1_DDR2_DQM(1)" LOC ="AH41";
NET "DIMM1_DDR2_DQM(0)" LOC ="AC41";
NET "DIMM1_DDR2_DQ(9)" LOC ="AF42";
NET "DIMM1_DDR2_DQ(8)" LOC ="AE42";
NET "DIMM1_DDR2_DQ(7)" LOC ="AF41";
NET "DIMM1_DDR2_DQ(63)" LOC ="AN34";
NET "DIMM1_DDR2_DQ(62)" LOC ="AU38";
NET "DIMM1_DDR2_DQ(61)" LOC ="AR37";
NET "DIMM1_DDR2_DQ(60)" LOC ="AN36";
NET "DIMM1_DDR2_DQ(6)" LOC ="AF40";
NET "DIMM1_DDR2_DQ(59)" LOC ="AU37";
NET "DIMM1_DDR2_DQ(58)" LOC ="AT36";
NET "DIMM1_DDR2_DQ(57)" LOC ="AT37";
NET "DIMM1_DDR2_DQ(56)" LOC ="AP35";
NET "DIMM1_DDR2_DQ(55)" LOC ="AK34";
NET "DIMM1_DDR2_DQ(54)" LOC ="AR38";
NET "DIMM1_DDR2_DQ(53)" LOC ="AL36";
NET "DIMM1_DDR2_DQ(52)" LOC ="AE32";
NET "DIMM1_DDR2_DQ(51)" LOC ="AL34";
NET "DIMM1_DDR2_DQ(50)" LOC ="AM34";
NET "DIMM1_DDR2_DQ(5)" LOC ="AB42";
NET "DIMM1_DDR2_DQ(49)" LOC ="AM36";
NET "DIMM1_DDR2_DQ(48)" LOC ="AL35";
NET "DIMM1_DDR2_DQ(47)" LOC ="AN39";
NET "DIMM1_DDR2_DQ(46)" LOC ="AN38";
NET "DIMM1_DDR2_DQ(45)" LOC ="AK38";
NET "DIMM1_DDR2_DQ(44)" LOC ="AL39";
NET "DIMM1_DDR2_DQ(43)" LOC ="AP38";
NET "DIMM1_DDR2_DQ(42)" LOC ="AM37";
NET "DIMM1_DDR2_DQ(41)" LOC ="AP40";
NET "DIMM1_DDR2_DQ(40)" LOC ="AM38";
NET "DIMM1_DDR2_DQ(4)" LOC ="AB41";
NET "DIMM1_DDR2_DQ(39)" LOC ="AJ37";
NET "DIMM1_DDR2_DQ(38)" LOC ="AK39";
NET "DIMM1_DDR2_DQ(37)" LOC ="AG38";
NET "DIMM1_DDR2_DQ(36)" LOC ="AF39";
NET "DIMM1_DDR2_DQ(35)" LOC ="AM39";
NET "DIMM1_DDR2_DQ(34)" LOC ="AL37";
NET "DIMM1_DDR2_DQ(33)" LOC ="AH38";
NET "DIMM1_DDR2_DQ(32)" LOC ="AJ38";
NET "DIMM1_DDR2_DQ(31)" LOC ="AD37";
NET "DIMM1_DDR2_DQ(30)" LOC ="AD35";
NET "DIMM1_DDR2_DQ(3)" LOC ="AD41";
NET "DIMM1_DDR2_DQ(29)" LOC ="AC35";
NET "DIMM1_DDR2_DQ(28)" LOC ="AB34";
NET "DIMM1_DDR2_DQ(27)" LOC ="AE38";
NET "DIMM1_DDR2_DQ(26)" LOC ="AD36";
NET "DIMM1_DDR2_DQ(25)" LOC ="AC34";
NET "DIMM1_DDR2_DQ(24)" LOC ="AB36";
NET "DIMM1_DDR2_DQ(23)" LOC ="AT41";
NET "DIMM1_DDR2_DQ(22)" LOC ="AT42";
NET "DIMM1_DDR2_DQ(21)" LOC ="AM41";
NET "DIMM1_DDR2_DQ(20)" LOC ="AN41";
NET "DIMM1_DDR2_DQ(2)" LOC ="AD42";
NET "DIMM1_DDR2_DQ(19)" LOC ="AR42";
NET "DIMM1_DDR2_DQ(18)" LOC ="AP42";
NET "DIMM1_DDR2_DQ(17)" LOC ="AL42";
NET "DIMM1_DDR2_DQ(16)" LOC ="AK42";
NET "DIMM1_DDR2_DQ(15)" LOC ="AL41";
NET "DIMM1_DDR2_DQ(14)" LOC ="AJ42";
NET "DIMM1_DDR2_DQ(13)" LOC ="AH40";
NET "DIMM1_DDR2_DQ(12)" LOC ="AG42";
NET "DIMM1_DDR2_DQ(11)" LOC ="AJ40";
NET "DIMM1_DDR2_DQ(10)" LOC ="AJ41";
NET "DIMM1_DDR2_DQ(1)" LOC ="AB37";
NET "DIMM1_DDR2_DQ(0)" LOC ="AB38";
NET "DIMM1_DDR2_CKE(1)" LOC ="AE39";
NET "DIMM1_DDR2_CKE(0)" LOC ="AU41";
NET "DIMM1_DDR2_DQ(71)" LOC ="AE33";
NET "DIMM1_DDR2_DQ(70)" LOC ="AE34";
NET "DIMM1_DDR2_DQ(69)" LOC ="AC33";
NET "DIMM1_DDR2_DQ(68)" LOC ="AB32";
NET "DIMM1_DDR2_DQ(67)" LOC ="AH36";
NET "DIMM1_DDR2_DQ(66)" LOC ="AG36";
NET "DIMM1_DDR2_DQ(65)" LOC ="AD32";
NET "DIMM1_DDR2_DQ(64)" LOC ="AB33";
NET "DIMM1_DDR2_CAS_B" LOC ="Y42";
NET "DIMM1_DDR2_BA(2)" LOC ="AH35";
NET "DIMM1_DDR2_BA(1)" LOC ="AJ36";
NET "DIMM1_DDR2_BA(0)" LOC ="AJ35";
NET "DIMM1_DDR2_A(9)" LOC ="F42";
NET "DIMM1_DDR2_A(8)" LOC ="G42";
NET "DIMM1_DDR2_A(7)" LOC ="J42";
NET "DIMM1_DDR2_A(6)" LOC ="H41";
NET "DIMM1_DDR2_A(5)" LOC ="M42";
NET "DIMM1_DDR2_A(4)" LOC ="L42";
NET "DIMM1_DDR2_A(3)" LOC ="K42";
NET "DIMM1_DDR2_A(2)" LOC ="M41";
NET "DIMM1_DDR2_A(13)" LOC ="W41";
NET "DIMM1_DDR2_A(12)" LOC ="F41";
NET "DIMM1_DDR2_A(11)" LOC ="G41";
NET "DIMM1_DDR2_A(10)" LOC ="W42";
NET "DIMM1_DDR2_A(1)" LOC ="J41";
NET "DIMM1_DDR2_A(0)" LOC ="R40";

NET  "DIMM0_DDR2_DQ[*]"                               IOSTANDARD = SSTL18_II_DCI;
NET  "DIMM0_DDR2_DQM[*]"                               IOSTANDARD = SSTL18_II_DCI;
NET  "DIMM1_DDR2_DQ[*]"                               IOSTANDARD = SSTL18_II_DCI;
NET  "DIMM1_DDR2_DQM[*]"                               IOSTANDARD = SSTL18_II_DCI;

# DIMM0
NET "DIMM0_DDR2_WE_B" LOC ="Y40";
NET "DIMM0_DDR2_S_B(1)" LOC ="M37";
NET "DIMM0_DDR2_S_B(0)" LOC ="U32";
NET "DIMM0_DDR2_RAS_B" LOC ="W40";
NET "DIMM0_DDR2_PLL_CLKIN_P" LOC ="AA40";
NET "DIMM0_DDR2_PLL_CLKIN_N" LOC ="AA39";
NET "DIMM0_DDR2_ODT(1)" LOC ="K35";
NET "DIMM0_DDR2_ODT(0)" LOC ="U31";
NET "DIMM0_DDR2_DQS_P(8)" LOC ="H40";
NET "DIMM0_DDR2_DQS_P(8)" IOSTANDARD = SSTL18_II_DCI;
NET "DIMM0_DDR2_DQS_N(8)" LOC ="J40";
NET "DIMM0_DDR2_DQS_N(8)" IOSTANDARD = SSTL18_II_DCI;
NET "DIMM0_DDR2_DQS_P(7)" LOC ="K38";
NET "DIMM0_DDR2_DQS_P(7)" IOSTANDARD = DIFF_SSTL18_II_DCI;
NET "DIMM0_DDR2_DQS_N(7)" LOC ="J38";
NET "DIMM0_DDR2_DQS_N(7)" IOSTANDARD = DIFF_SSTL18_II_DCI;
NET "DIMM0_DDR2_DQS_P(6)" LOC ="M38";
NET "DIMM0_DDR2_DQS_P(6)" IOSTANDARD = DIFF_SSTL18_II_DCI;
NET "DIMM0_DDR2_DQS_N(6)" LOC ="L39";
NET "DIMM0_DDR2_DQS_N(6)" IOSTANDARD = DIFF_SSTL18_II_DCI;
NET "DIMM0_DDR2_DQS_P(5)" LOC ="U36";
NET "DIMM0_DDR2_DQS_P(5)" IOSTANDARD = DIFF_SSTL18_II_DCI;
NET "DIMM0_DDR2_DQS_N(5)" LOC ="V36";
NET "DIMM0_DDR2_DQS_N(5)" IOSTANDARD = DIFF_SSTL18_II_DCI;
NET "DIMM0_DDR2_DQS_P(4)" LOC ="R35";
NET "DIMM0_DDR2_DQS_P(4)" IOSTANDARD = DIFF_SSTL18_II_DCI;
NET "DIMM0_DDR2_DQS_N(4)" LOC ="T36";
NET "DIMM0_DDR2_DQS_N(4)" IOSTANDARD = DIFF_SSTL18_II_DCI;
NET "DIMM0_DDR2_DQS_P(3)" LOC ="T34";
NET "DIMM0_DDR2_DQS_P(3)" IOSTANDARD = DIFF_SSTL18_II_DCI;
NET "DIMM0_DDR2_DQS_N(3)" LOC ="U33";
NET "DIMM0_DDR2_DQS_N(3)" IOSTANDARD = DIFF_SSTL18_II_DCI;
NET "DIMM0_DDR2_DQS_P(2)" LOC ="E32";
NET "DIMM0_DDR2_DQS_P(2)" IOSTANDARD = DIFF_SSTL18_II_DCI;
NET "DIMM0_DDR2_DQS_N(2)" LOC ="E33";
NET "DIMM0_DDR2_DQS_N(2)" IOSTANDARD = DIFF_SSTL18_II_DCI;
NET "DIMM0_DDR2_DQS_P(1)" LOC ="F31";
NET "DIMM0_DDR2_DQS_P(1)" IOSTANDARD = DIFF_SSTL18_II_DCI;
NET "DIMM0_DDR2_DQS_N(1)" LOC ="F32";
NET "DIMM0_DDR2_DQS_N(1)" IOSTANDARD = DIFF_SSTL18_II_DCI;
NET "DIMM0_DDR2_DQS_P(0)" LOC ="E34";
NET "DIMM0_DDR2_DQS_P(0)" IOSTANDARD = DIFF_SSTL18_II_DCI;
NET "DIMM0_DDR2_DQS_N(0)" LOC ="F34";
NET "DIMM0_DDR2_DQS_N(0)" IOSTANDARD = DIFF_SSTL18_II_DCI;
NET "DIMM0_DDR2_DQM(8)" LOC ="G39";
NET "DIMM0_DDR2_DQM(7)" LOC ="W36";
NET "DIMM0_DDR2_DQM(6)" LOC ="T39";
NET "DIMM0_DDR2_DQM(5)" LOC ="V35";
NET "DIMM0_DDR2_DQM(4)" LOC ="M36";
NET "DIMM0_DDR2_DQM(3)" LOC ="F36";
NET "DIMM0_DDR2_DQM(2)" LOC ="P33";
NET "DIMM0_DDR2_DQM(1)" LOC ="L32";
NET "DIMM0_DDR2_DQM(0)" LOC ="F35";
NET "DIMM0_DDR2_DQ(9)" LOC ="L31";
NET "DIMM0_DDR2_DQ(8)" LOC ="J33";
NET "DIMM0_DDR2_DQ(7)" LOC ="H34";
NET "DIMM0_DDR2_DQ(63)" LOC ="W35";
NET "DIMM0_DDR2_DQ(62)" LOC ="W37";
NET "DIMM0_DDR2_DQ(61)" LOC ="T37";
NET "DIMM0_DDR2_DQ(60)" LOC ="P37";
NET "DIMM0_DDR2_DQ(6)" LOC ="H31";
NET "DIMM0_DDR2_DQ(59)" LOC ="Y34";
NET "DIMM0_DDR2_DQ(58)" LOC ="AA34";
NET "DIMM0_DDR2_DQ(57)" LOC ="AA36";
NET "DIMM0_DDR2_DQ(56)" LOC ="AA35";
NET "DIMM0_DDR2_DQ(55)" LOC ="V39";
NET "DIMM0_DDR2_DQ(54)" LOC ="R37";
NET "DIMM0_DDR2_DQ(53)" LOC ="R39";
NET "DIMM0_DDR2_DQ(52)" LOC ="N38";
NET "DIMM0_DDR2_DQ(51)" LOC ="W38";
NET "DIMM0_DDR2_DQ(50)" LOC ="Y35";
NET "DIMM0_DDR2_DQ(5)" LOC ="G33";
NET "DIMM0_DDR2_DQ(49)" LOC ="P38";
NET "DIMM0_DDR2_DQ(48)" LOC ="U38";
NET "DIMM0_DDR2_DQ(47)" LOC ="W33";
NET "DIMM0_DDR2_DQ(46)" LOC ="Y33";
NET "DIMM0_DDR2_DQ(45)" LOC ="T35";
NET "DIMM0_DDR2_DQ(44)" LOC ="R34";
NET "DIMM0_DDR2_DQ(43)" LOC ="AA32";
NET "DIMM0_DDR2_DQ(42)" LOC ="Y32";
NET "DIMM0_DDR2_DQ(41)" LOC ="W32";
NET "DIMM0_DDR2_DQ(40)" LOC ="V33";
NET "DIMM0_DDR2_DQ(4)" LOC ="G32";
NET "DIMM0_DDR2_DQ(39)" LOC ="P35";
NET "DIMM0_DDR2_DQ(38)" LOC ="N36";
NET "DIMM0_DDR2_DQ(37)" LOC ="L36";
NET "DIMM0_DDR2_DQ(36)" LOC ="J35";
NET "DIMM0_DDR2_DQ(35)" LOC ="U34";
NET "DIMM0_DDR2_DQ(34)" LOC ="V34";
NET "DIMM0_DDR2_DQ(33)" LOC ="P36";
NET "DIMM0_DDR2_DQ(32)" LOC ="N35";
NET "DIMM0_DDR2_DQ(31)" LOC ="J37";
NET "DIMM0_DDR2_DQ(30)" LOC ="H35";
NET "DIMM0_DDR2_DQ(3)" LOC ="H33";
NET "DIMM0_DDR2_DQ(29)" LOC ="E38";
NET "DIMM0_DDR2_DQ(28)" LOC ="D37";
NET "DIMM0_DDR2_DQ(27)" LOC ="K37";
NET "DIMM0_DDR2_DQ(26)" LOC ="J36";
NET "DIMM0_DDR2_DQ(25)" LOC ="G36";
NET "DIMM0_DDR2_DQ(24)" LOC ="F37";
NET "DIMM0_DDR2_DQ(23)" LOC ="T31";
NET "DIMM0_DDR2_DQ(22)" LOC ="R32";
NET "DIMM0_DDR2_DQ(21)" LOC ="P31";
NET "DIMM0_DDR2_DQ(20)" LOC ="N34";
NET "DIMM0_DDR2_DQ(2)" LOC ="J31";
NET "DIMM0_DDR2_DQ(19)" LOC ="T32";
NET "DIMM0_DDR2_DQ(18)" LOC ="R33";
NET "DIMM0_DDR2_DQ(17)" LOC ="P32";
NET "DIMM0_DDR2_DQ(16)" LOC ="N33";
NET "DIMM0_DDR2_DQ(15)" LOC ="N31";
NET "DIMM0_DDR2_DQ(14)" LOC ="M32";
NET "DIMM0_DDR2_DQ(13)" LOC ="K33";
NET "DIMM0_DDR2_DQ(12)" LOC ="K32";
NET "DIMM0_DDR2_DQ(11)" LOC ="M34";
NET "DIMM0_DDR2_DQ(10)" LOC ="M33";
NET "DIMM0_DDR2_DQ(1)" LOC ="G31";
NET "DIMM0_DDR2_DQ(0)" LOC ="E35";
NET "DIMM0_DDR2_CKE(1)" LOC ="L37";
NET "DIMM0_DDR2_CKE(0)" LOC ="M31";
NET  "dimm0_ddr2_reset_n"                             IOSTANDARD = LVCMOS33;
NET  "dimm0_ddr2_reset_n"                              LOC = "AG33" ;       #Bank 11
NET "DIMM0_DDR2_DQ(71)" LOC ="H39";
NET "DIMM0_DDR2_DQ(70)" LOC ="G38";
NET "DIMM0_DDR2_DQ(69)" LOC ="E39";
NET "DIMM0_DDR2_DQ(68)" LOC ="E40";
NET "DIMM0_DDR2_DQ(67)" LOC ="H38";
NET "DIMM0_DDR2_DQ(66)" LOC ="K40";
NET "DIMM0_DDR2_DQ(65)" LOC ="F39";
NET "DIMM0_DDR2_DQ(64)" LOC ="F40";
NET "DIMM0_DDR2_CAS_B" LOC ="AA37";
NET "DIMM0_DDR2_BA(2)" LOC ="K39";
NET "DIMM0_DDR2_BA(1)" LOC ="M39";
NET "DIMM0_DDR2_BA(0)" LOC ="N39";
NET "DIMM0_DDR2_A(9)" LOC ="L40";
NET "DIMM0_DDR2_A(8)" LOC ="P42";
NET "DIMM0_DDR2_A(7)" LOC ="R42";
NET "DIMM0_DDR2_A(6)" LOC ="P41";
NET "DIMM0_DDR2_A(5)" LOC ="T40";
NET "DIMM0_DDR2_A(4)" LOC ="U42";
NET "DIMM0_DDR2_A(3)" LOC ="T42";
NET "DIMM0_DDR2_A(2)" LOC ="U41";
NET "DIMM0_DDR2_A(13)" LOC ="Y37";
NET "DIMM0_DDR2_A(12)" LOC ="N41";
NET "DIMM0_DDR2_A(11)" LOC ="N40";
NET "DIMM0_DDR2_A(10)" LOC ="AA41";
NET "DIMM0_DDR2_A(1)" LOC ="P40";
NET "DIMM0_DDR2_A(0)" LOC ="AA42";

/////////////////////////////////////////////////////
// Ethernet
/////////////////////////////////////////////////////

# PHY 1 uses SGMII
NET "PHY1_RESET" LOC ="AL25";
NET "PHY1_MDIO" LOC ="AT32";
NET "PHY1_MDC" LOC ="AU31";
NET "PHY1_INT" LOC ="AV31";
NET "SGMIICLK_QO_P" LOC ="C4";
NET "SGMIICLK_QO_N" LOC ="C3";
NET "PHY1_SGMII_TX_P" LOC = "B1";
NET "PHY1_SGMII_TX_N" LOC = "B2";
NET "PHY1_SGMII_RX_P" LOC = "A2";
NET "PHY1_SGMII_RX_N" LOC = "A3";
INST eth2.e2/pcs0/serdes0/xilinx.xil0/gtx0.gtx_dual_i LOC=GTX_DUAL_X0Y8;
# PHY 0
NET "PHY0_TXER" LOC ="AT31";
NET "PHY0_TXD(3)" LOC ="AN31";
NET "PHY0_TXD(2)" LOC ="AR32";
NET "PHY0_TXD(1)" LOC ="AP32";
NET "PHY0_TXD(0)" LOC ="AR33";
NET "PHY0_TXCTL_TXEN" LOC ="AP31";
NET "PHY0_TXCLK" LOC ="M26";
NET "PHY0_RXER" LOC ="AP33";
NET "PHY0_RXD(3)" LOC ="AM33";
NET "PHY0_RXD(2)" LOC ="AK33";
NET "PHY0_RXD(1)" LOC ="AJ33";
NET "PHY0_RXD(0)" LOC ="AJ32";
NET "PHY0_RXCTL_RXDV" LOC ="AN33";
NET "PHY0_RXCLK" LOC ="J17";
NET "PHY0_RESET" LOC ="AK32";
NET "PHY0_MDIO" LOC ="AL31";
NET "PHY0_MDC" LOC ="AM32";
# Not used by GRETH
#NET "PHY0_INT" LOC ="AL32";
# Only for RGMII, which is not supported
#NET "PHY0_GTXCLK" LOC ="AM31";

/////////////////////////////////////////////////////
// System ACE MPU
/////////////////////////////////////////////////////

NET "SYSACE_MPWE" LOC ="AR8";
NET "SYSACE_MPOE" LOC ="AK10";
NET "SYSACE_MPIRQ" LOC ="AK9";
NET "SYSACE_MPD(9)" LOC ="AV5";
NET "SYSACE_MPD(8)" LOC ="AV6";
NET "SYSACE_MPD(7)" LOC ="AH11";
NET "SYSACE_MPD(6)" LOC ="AH10";
NET "SYSACE_MPD(5)" LOC ="AU6";
NET "SYSACE_MPD(4)" LOC ="AT5";
NET "SYSACE_MPD(3)" LOC ="AH9";
NET "SYSACE_MPD(2)" LOC ="AG9";
NET "SYSACE_MPD(15)" LOC ="AK8";
NET "SYSACE_MPD(14)" LOC ="AP8";
NET "SYSACE_MPD(13)" LOC ="AT7";
NET "SYSACE_MPD(12)" LOC ="AJ8";
NET "SYSACE_MPD(11)" LOC ="AJ10";
NET "SYSACE_MPD(10)" LOC ="AJ11";
NET "SYSACE_MPD(1)" LOC ="AR5";
NET "SYSACE_MPD(0)" LOC ="AT6";
NET "SYSACE_MPCE" LOC ="AN8";
# Not used
#NET "SYSACE_MPBRDY" LOC ="AN4";
NET "SYSACE_MPA(6)" LOC ="AG11";
NET "SYSACE_MPA(5)" LOC ="AG12";
NET "SYSACE_MPA(4)" LOC ="AM8";
NET "SYSACE_MPA(3)" LOC ="AM7";
NET "SYSACE_MPA(2)" LOC ="AM6";
NET "SYSACE_MPA(1)" LOC ="AN6";
NET "SYSACE_MPA(0)" LOC ="AR7";
# Removed
#NET "SYSACE_FLASH_CFGA1" LOC ="AK12";
#NET "SYSACE_FLASH_CFGA0" LOC ="AK13";

/////////////////////////////////////////////////////
// Green LEDs
/////////////////////////////////////////////////////

NET "DBG_LED(3)" LOC ="AL6";
NET "DBG_LED(2)" LOC ="AN5";
NET "DBG_LED(1)" LOC ="AP6";
NET "DBG_LED(0)" LOC ="AL7";

/////////////////////////////////////////////////////
// Red/Green LEDs
/////////////////////////////////////////////////////

NET "OPB_BUS_ERROR" LOC ="AL19";
NET "PLB_BUS_ERROR" LOC ="AK24";
#NET "FPGA_DONE" LOC ="R14";
#NET "FPGA_INIT" LOC ="T14";

/////////////////////////////////////////////////////
// LCD
/////////////////////////////////////////////////////

#NET "FPGA_LCD_RW" LOC ="Y9";
#NET "FPGA_LCD_RS" LOC ="Y8";
#NET "FPGA_LCD_E" LOC ="W10";
#NET "FPGA_LCD_DB(7)" LOC ="Y10";
#NET "FPGA_LCD_DB(6)" LOC ="AA9";
#NET "FPGA_LCD_DB(5)" LOC ="AA10";
#NET "FPGA_LCD_DB(4)" LOC ="AA11";
#NET "FPGA_LCD_DB(3)" LOC ="T4";
#NET "FPGA_LCD_DB(2)" LOC ="T5";
#NET "FPGA_LCD_DB(1)" LOC ="R5";
#NET "FPGA_LCD_DB(0)" LOC ="R4";

/////////////////////////////////////////////////////
// JTAG Trace/Debug
/////////////////////////////////////////////////////

#NET "ATCB_CLK_R" LOC ="J16";
#NET "TRC_TS6" LOC ="AR17";
#NET "TRC_TS5" LOC ="AP17";
#NET "TRC_TS4" LOC ="AT27";
#NET "TRC_TS3" LOC ="AU28";
#NET "TRC_TS2" LOC ="AT16";
#NET "TRC_TS1" LOC ="AT17";
#NET "TRC_TS0" LOC ="AT29";
#NET "TRC_ES4" LOC ="AR15";
#NET "TRC_ES3" LOC ="AT26";
#NET "TRC_ES2" LOC ="AT15";
#NET "TRC_ES1" LOC ="AN20";
#NET "TRC_ES0" LOC ="AN19";
#NET "TRC_CLK_R" LOC ="AR27";
#NET "TRC_BS2_BR2" LOC ="AN18";
#NET "TRC_BS1_BR1" LOC ="AM18";
#NET "TRC_BS0_BR0" LOC ="AN26";
#NET "CPU_TRST_B" LOC ="AT30";
#NET "CPU_TMS" LOC ="AR14";
#NET "CPU_TDO_TMP" LOC ="AR28";
#NET "CPU_TDI" LOC ="AR30";
#NET "CPU_TCK" LOC ="AT14";
#NET "CPU_HALT_B" LOC ="AR29";
#NET "ATD_4" LOC ="AM24";
#NET "ATD_3" LOC ="AT19";
#NET "ATD_2" LOC ="AP25";
#NET "ATD_1" LOC ="AN25";
#NET "ATD_0" LOC ="AP26";

/////////////////////////////////////////////////////
// DVI
/////////////////////////////////////////////////////

NET "DVI_XCLK_P" LOC ="AG8";
NET "DVI_XCLK_N" LOC ="AH8";
NET "DVI_V" LOC ="AM17";
NET "DVI_RESET_B" LOC ="AM9";
NET "DVI_H" LOC ="AP27";
NET "DVI_GPIO1" LOC ="AN9";
NET "DVI_DE" LOC ="M8";
NET "DVI_D(9)" LOC ="AK15";
NET "DVI_D(8)" LOC ="AM16";
NET "DVI_D(7)" LOC ="AM27";
NET "DVI_D(6)" LOC ="AM26";
NET "DVI_D(5)" LOC ="AN15";
NET "DVI_D(4)" LOC ="AN16";
NET "DVI_D(3)" LOC ="AL27";
NET "DVI_D(2)" LOC ="AL26";
NET "DVI_D(11)" LOC ="AK30";
NET "DVI_D(10)" LOC ="AJ30";
NET "DVI_D(1)" LOC ="AP16";
NET "DVI_D(0)" LOC ="AP15";

/////////////////////////////////////////////////////
// PCI
/////////////////////////////////////////////////////

NET "PCI_P_TRDY_B" LOC ="V10" | PULLUP | BYPASS;
NET "PCI_P_STOP_B" LOC ="G9"  | PULLUP | BYPASS;
NET "PCI_P_SERR_B" LOC ="G8"  | PULLUP | BYPASS;
NET "PCI_P_RST_B" LOC ="H11"  | PULLUP | BYPASS;
NET "PCI_P_REQ_B(4)" LOC ="R7";
NET "PCI_P_REQ_B(3)" LOC ="F6";
NET "PCI_P_REQ_B(2)" LOC ="D7";
NET "PCI_P_REQ_B(1)" LOC ="R8";
NET "PCI_P_REQ_B(0)" LOC ="E7";
# The tools insist on disregarding the IOSTANDARD of the PCI_P_REQ pads even
# though the pads should not be optimized away when disabling the PCI core.
NET "PCI_P_REQ_B(*)" IOSTANDARD="PCI33_3" | PULLUP;
NET "PCI_P_PERR_B" LOC ="G7"  | PULLUP | BYPASS;
NET "PCI_P_PAR" LOC ="E8"     | PULLUP | BYPASS;
NET "PCI_P_LOCK_B" LOC ="J12" | PULLUP | BYPASS;
NET "PCI_P_IRDY_B" LOC ="P8"  | PULLUP | BYPASS;
NET "PCI_P_INTD_B" LOC ="F11";
NET "PCI_P_INTC_B" LOC ="F12";
NET "PCI_P_INTB_B" LOC ="G11";
NET "PCI_P_INTA_B" LOC ="G12";
NET "PCI_P_GNT_B(4)" LOC ="E5";
NET "PCI_P_GNT_B(3)" LOC ="R9";
NET "PCI_P_GNT_B(2)" LOC ="F5";
NET "PCI_P_GNT_B(1)" LOC ="F7";
NET "PCI_P_GNT_B(0)" LOC ="T9";
NET "PCI_P_GNT_B(*)" PULLUP;
NET "PCI_P_FRAME_B" LOC ="P7"  | PULLUP | BYPASS;
NET "PCI_P_DEVSEL_B" LOC ="F9" | PULLUP | BYPASS;
NET "PCI_P_CLK5_R" LOC ="V9";
NET "PCI_P_CLK5" LOC ="L16";
NET "PCI_P_CLK4_R" LOC ="U11";
NET "PCI_P_CLK3_R" LOC ="M9";
NET "PCI_P_CLK1_R" LOC ="U9";
NET "PCI_P_CLK0_R" LOC ="U8";
NET "PCI_P_CBE_B(3)" LOC ="F15";
NET "PCI_P_CBE_B(2)" LOC ="N9";
NET "PCI_P_CBE_B(1)" LOC ="N8";
NET "PCI_P_CBE_B(0)" LOC ="E9";
NET "PCI_P_CBE_B(*)" BYPASS;
NET "PCI_P_AD(9)" LOC ="P12";
NET "PCI_P_AD(8)" LOC ="E12";
NET "PCI_P_AD(7)" LOC ="D12";
NET "PCI_P_AD(6)" LOC ="P11";
NET "PCI_P_AD(5)" LOC ="N10";
NET "PCI_P_AD(4)" LOC ="D13";
NET "PCI_P_AD(31)" LOC ="F10";
NET "PCI_P_AD(30)" LOC ="K14";
NET "PCI_P_AD(3)" LOC ="E14";
NET "PCI_P_AD(29)" LOC ="K13";
NET "PCI_P_AD(28)" LOC ="K12";
NET "PCI_P_AD(27)" LOC ="J11";
NET "PCI_P_AD(26)" LOC ="J13";
NET "PCI_P_AD(25)" LOC ="H13";
NET "PCI_P_AD(24)" LOC ="H10";
NET "PCI_P_AD(23)" LOC ="J10";
NET "PCI_P_AD(22)" LOC ="H14";
NET "PCI_P_AD(21)" LOC ="H15";
NET "PCI_P_AD(20)" LOC ="K10";
NET "PCI_P_AD(2)" LOC ="R10";
NET "PCI_P_AD(19)" LOC ="L10";
NET "PCI_P_AD(18)" LOC ="L12";
NET "PCI_P_AD(17)" LOC ="L11";
NET "PCI_P_AD(16)" LOC ="G13";
NET "PCI_P_AD(15)" LOC ="G14";
NET "PCI_P_AD(14)" LOC ="M11";
NET "PCI_P_AD(13)" LOC ="M12";
NET "PCI_P_AD(12)" LOC ="F14";
NET "PCI_P_AD(11)" LOC ="E13";
NET "PCI_P_AD(10)" LOC ="N11";
NET "PCI_P_AD(1)" LOC ="P10";
NET "PCI_P_AD(0)" LOC ="E15";
NET "PCI_P_AD(*)" BYPASS;
#NET "PCI_FPGA_IDSEL" LOC ="E10";

# Southbridge sideband
NET "SBR_PWG_RSM_RSTJ" LOC ="M17";
NET "SBR_NMI_R" LOC ="AU29";
NET "SBR_INTR_R" LOC ="K28";
NET "SBR_IDE_RST_B" LOC ="AR19";

/////////////////////////////////////////////////////
// IIC/SMBus
/////////////////////////////////////////////////////

NET "IIC_SDA_DVI" LOC ="M7";
NET "IIC_SCL_DVI" LOC ="L9";

NET "FPGA_SDA" LOC ="K8";
NET "FPGA_SCL" LOC ="L7";
NET "IIC_THERM_B" LOC ="AN24";
NET "IIC_RESET_B" LOC ="AK19";
NET "IIC_IRQ_B" LOC ="AK25";
NET "IIC_ALERT_B" LOC ="AK18";

/////////////////////////////////////////////////////
// SPI
/////////////////////////////////////////////////////

NET "SPI_DATA_OUT" LOC ="AP7";
NET "SPI_DATA_IN" LOC ="AP5";
NET "SPI_DATA_CS_B" LOC ="AL10";
NET "SPI_CLK" LOC ="AL9";

/////////////////////////////////////////////////////
// UARTs
/////////////////////////////////////////////////////

NET "UART1_TXD" LOC ="T10";
NET "UART1_RXD" LOC ="V11";
NET "UART1_RTS_B" LOC ="K9";
NET "UART1_CTS_B" LOC ="J8";
NET "UART0_TXD" LOC ="H9";
NET "UART0_RXD" LOC ="T11";
NET "UART0_RTS_B" LOC ="J7";
# Not used by AHBUART:
#NET "UART0_CTS_B" LOC ="H8";

/////////////////////////////////////////////////////
// System monitor
/////////////////////////////////////////////////////

#NET "TEST_MON_VREFP" LOC ="AB22";
NET "TEST_MON_VP0_P" LOC ="AA22";
NET "TEST_MON_VN0_N" LOC ="AB21";
#NET "TEST_MON_AVDD" LOC ="Y22";

/////////////////////////////////////////////////////
// PCI Express
/////////////////////////////////////////////////////

# Slot A
#NET "GTP122_PCIE_SLOTA_CLK_P" LOC ="AT4";
#NET "GTP122_PCIE_SLOTA_CLK_N" LOC ="AT3";
#NET "GTP126_PCIE_SLOTA_CLK_P" LOC ="AW4";
#NET "GTP126_PCIE_SLOTA_CLK_N" LOC ="AY4";
#NET "PCIE_SLOTA_WAKE_B_R" LOC ="K17";
#NET "PCIE_SLOTA_PRSNT2_B_R" LOC ="M28";
#NET "PCIE_SLOTA_PERST_B" LOC ="L27";
#NET "GTP_122_TX1_P_C" LOC ="AW2";
#NET "GTP_122_TX1_N_C" LOC ="AV2";
#NET "GTP_122_TX0_P_C" LOC ="AP2";
#NET "GTP_122_TX0_N_C" LOC ="AR2";
#NET "GTP_122_RX1_P" LOC ="AV1";
#NET "GTP_122_RX1_N" LOC ="AU1";
#NET "GTP_122_RX0_P" LOC ="AR1";
#NET "GTP_122_RX0_N" LOC ="AT1";
#NET "GTP_126_TX1_P_C" LOC ="BA6";
#NET "GTP_126_TX1_N_C" LOC ="BA5";
#NET "GTP_126_TX0_P_C" LOC ="BA1";
#NET "GTP_126_TX0_N_C" LOC ="BA2";
#NET "GTP_126_RX1_P" LOC ="BB5";
#NET "GTP_126_RX1_N" LOC ="BB4";
#NET "GTP_126_RX0_P" LOC ="BB2";
#NET "GTP_126_RX0_N" LOC ="BB3";
#NET "GTP_130_TX1_P_C" LOC ="BA12";
#NET "GTP_130_TX1_N_C" LOC ="BA11";
#NET "GTP_130_TX0_P_C" LOC ="BA7";
#NET "GTP_130_TX0_N_C" LOC ="BA8";
#NET "GTP_130_RX1_P" LOC ="BB11";
#NET "GTP_130_RX1_N" LOC ="BB10";
#NET "GTP_130_RX0_P" LOC ="BB8";
#NET "GTP_130_RX0_N" LOC ="BB9";
#NET "GTP_130_AVCC_PLL" LOC ="AY11";
#NET "GTP_130_AVCC" LOC ="AW10";
#NET "GTP_130_AVCC" LOC ="AY10";

# Slot B
#NET "GTP132_PCIE_SLOTB_CLK_P" LOC ="D16";
#NET "GTP132_PCIE_SLOTB_CLK_N" LOC ="C16";
#NET "GTP128_PCIE_SLOTB_CLK_P" LOC ="D10";
#NET "GTP128_PCIE_SLOTB_CLK_N" LOC ="C10";
#NET "PCIE_SLOTB_WAKE_B_R" LOC ="J30";
#NET "PCIE_SLOTB_PRSNT2_B_R" LOC ="K15";
#NET "PCIE_SLOTB_PERST_B" LOC ="L15";
#NET "GTP_128_TX1_P_C" LOC ="B7";
#NET "GTP_128_TX1_N_C" LOC ="B8";
#NET "GTP_128_TX0_P_C" LOC ="B12";
#NET "GTP_128_TX0_N_C" LOC ="B11";
#NET "GTP_128_RX1_P" LOC ="A8";
#NET "GTP_128_RX1_N" LOC ="A9";
#NET "GTP_128_RX0_P" LOC ="A11";
#NET "GTP_128_RX0_N" LOC ="A10";
#NET "GTP_132_TX1_P_C" LOC ="B13";
#NET "GTP_132_TX1_N_C" LOC ="B14";
#NET "GTP_132_TX0_P_C" LOC ="B18";
#NET "GTP_132_TX0_N_C" LOC ="B17";
#NET "GTP_132_RX1_P" LOC ="A14";
#NET "GTP_132_RX1_N" LOC ="A15";
#NET "GTP_132_RX0_P" LOC ="A17";
#NET "GTP_132_RX0_N" LOC ="A16";

/////////////////////////////////////////////////////
// Serial ATA
/////////////////////////////////////////////////////
#NET "GTP_120_TX1_P" LOC ="J2";
#NET "GTP_120_TX1_N" LOC ="H2";
#NET "GTP_120_TX0_P" LOC ="D2";
#NET "GTP_120_TX0_N" LOC ="E2";
#NET "GTP_120_RX1_P" LOC ="H1";
#NET "GTP_120_RX1_N" LOC ="G1";
#NET "GTP_120_RX0_P" LOC ="E1";
#NET "GTP_120_RX0_N" LOC ="F1";

//////////////////////////////////////////
// Personality module
//////////////////////////////////////////
#NET "PM_IO_9_N" LOC ="J25";
#NET "PM_IO_95_N" LOC ="AV34";
#NET "PM_IO_94_P" LOC ="AV33";
#NET "PM_IO_93_N" LOC ="AU33";
#NET "PM_IO_92_P" LOC ="AU32";
#NET "PM_IO_91_N" LOC ="AR34";
#NET "PM_IO_90_P" LOC ="AR35";
#NET "PM_IO_8_P" LOC ="K25";
#NET "PM_IO_89_N" LOC ="AT34";
#NET "PM_IO_88_P" LOC ="AU34";
#NET "PM_IO_87_N" LOC ="AT35";
#NET "PM_IO_86_P" LOC ="AU36";
#NET "PM_IO_85_N" LOC ="AV36";
#NET "PM_IO_84_P" LOC ="AV35";
#NET "PM_IO_83_N" LOC ="AJ31";
#NET "PM_IO_82_P" LOC ="AH31";
#NET "PM_IO_81_N" LOC ="AG32";
#NET "PM_IO_80_P" LOC ="AH33";
#NET "PM_IO_7_N" LOC ="F17";
#NET "PM_IO_79_N" LOC ="AG33";
#NET "PM_IO_78_P" LOC ="AF32";
#NET "PM_IO_77_N" LOC ="AF31";
#NET "PM_IO_76_P" LOC ="AG31";
#NET "PM_IO_75_N" LOC ="AF12";
#NET "PM_IO_74_P" LOC ="AF11";
#NET "PM_IO_73_N" LOC ="AE10";
#NET "PM_IO_72_P" LOC ="AE9";
#NET "PM_IO_71_N" LOC ="AF10";
#NET "PM_IO_70_P" LOC ="AF9";
#NET "PM_IO_6_P" LOC ="F16";
#NET "PM_IO_69_N" LOC ="AE8";
#NET "PM_IO_68_P" LOC ="AD8";
#NET "PM_IO_67_N" LOC ="AE7";
#NET "PM_IO_66_P" LOC ="AF7";
#NET "PM_IO_65_N" LOC ="AD5";
#NET "PM_IO_64_P" LOC ="AE5";
#NET "PM_IO_63_N" LOC ="AG7";
#NET "PM_IO_62_P" LOC ="AG6";
#NET "PM_IO_61_N" LOC ="AF6";
#NET "PM_IO_60_P" LOC ="AF5";
#NET "PM_IO_5_N" LOC ="L25";
#NET "PM_IO_59_N" LOC ="AC6";
#NET "PM_IO_58_P" LOC ="AC5";
#NET "PM_IO_57_N" LOC ="AB6";
#NET "PM_IO_56_P" LOC ="AB7";
#NET "PM_IO_55_N" LOC ="AH4";
#NET "PM_IO_54_P" LOC ="AG4";
#NET "PM_IO_53_N" LOC ="AD11";
#NET "PM_IO_52_P" LOC ="AD10";
#NET "PM_IO_51_N" LOC ="AH5";
#NET "PM_IO_50_P" LOC ="AH6";
#NET "PM_IO_4_P" LOC ="K24";
#NET "PM_IO_49_N" LOC ="AC9";
#NET "PM_IO_48_P" LOC ="AC8";
#NET "PM_IO_47_N_J" LOC ="AJ5";
#NET "PM_IO_46_P_J" LOC ="AJ6";
#NET "PM_IO_45_N" LOC ="AB8";
#NET "PM_IO_44_P" LOC ="AB9";
#NET "PM_IO_43_N" LOC ="AK5";
#NET "PM_IO_42_P" LOC ="AL5";
#NET "PM_IO_41_N" LOC ="AC10";
#NET "PM_IO_40_P" LOC ="AB11";
#NET "PM_IO_3_N" LOC ="E17";
#NET "PM_IO_3V_9_N" LOC ="U6";
#NET "PM_IO_3V_8_N" LOC ="J5";
#NET "PM_IO_3V_7_N" LOC ="M6";
#NET "PM_IO_3V_6_P" LOC ="H6";
#NET "PM_IO_3V_5_P" LOC ="N5";
#NET "PM_IO_3V_4_P" LOC ="AA7";
#NET "PM_IO_3V_3_P" LOC ="K4";
#NET "PM_IO_3V_2_N" LOC ="K5";
#NET "PM_IO_3V_25_N" LOC ="V6";
#NET "PM_IO_3V_24_P" LOC ="T7";
#NET "PM_IO_3V_23_N" LOC ="W7";
#NET "PM_IO_3V_22_P" LOC ="L6";
#NET "PM_IO_3V_21_N" LOC ="H5";
#NET "PM_IO_3V_20_P" LOC ="G6";
#NET "PM_IO_3V_1_N" LOC ="L5";
#NET "PM_IO_3V_19_N" LOC ="T6";
#NET "PM_IO_3V_18_P" LOC ="V5";
#NET "PM_IO_3V_17_N" LOC ="N6";
#NET "PM_IO_3V_16_N" LOC ="V8";
#NET "PM_IO_3V_15_N" LOC ="W6";
#NET "PM_IO_3V_14_P" LOC ="J6";
#NET "PM_IO_3V_13_P" LOC ="U7";
#NET "PM_IO_3V_12_P" LOC ="W8";
#NET "PM_IO_3V_11_P" LOC ="Y7";
#NET "PM_IO_3V_10_N" LOC ="AA6";
#NET "PM_IO_3V_0_P" LOC ="W5";
#NET "PM_IO_39_N" LOC ="AK7";
#NET "PM_IO_38_P" LOC ="AJ7";
#NET "PM_IO_37_N_J" LOC ="H30";
#NET "PM_IO_36_P_J" LOC ="H29";
#NET "PM_IO_35_N" LOC ="L19";
#NET "PM_IO_34_P" LOC ="L20";
#NET "PM_IO_33_N" LOC ="F29";
#NET "PM_IO_32_P" LOC ="G29";
#NET "PM_IO_31_N" LOC ="N18";
#NET "PM_IO_30_P" LOC ="M18";
#NET "PM_IO_2_P" LOC ="E18";
#NET "PM_IO_29_N" LOC ="H28";
#NET "PM_IO_28_P" LOC ="G28";
#NET "PM_IO_27_N" LOC ="N19";
#NET "PM_IO_26_P" LOC ="M19";
#NET "PM_IO_25_N" LOC ="F27";
#NET "PM_IO_24_P" LOC ="G27";
#NET "PM_IO_23_N" LOC ="L26";
#NET "PM_IO_22_P" LOC ="K27";
#NET "PM_IO_21_N" LOC ="K19";
#NET "PM_IO_20_P" LOC ="K18";
#NET "PM_IO_1_N" LOC ="M24";
#NET "PM_IO_19_N" LOC ="H18";
#NET "PM_IO_18_P" LOC ="J18";
#NET "PM_IO_17_N" LOC ="J27";
#NET "PM_IO_16_P" LOC ="J28";
#NET "PM_IO_15_N" LOC ="G17";
#NET "PM_IO_14_P" LOC ="G18";
#NET "PM_IO_13_N" LOC ="J26";
#NET "PM_IO_12_P" LOC ="H26";
#NET "PM_IO_11_N" LOC ="H16";
#NET "PM_IO_10_P" LOC ="G16";
#NET "PM_IO_0_P" LOC ="L24";
#NET "PM_CLK_TOP" LOC ="M27";
#NET "PM_CLK_BOT" LOC ="L14";

//////////////////////////////////////////
// RocketIO
//////////////////////////////////////////
#NET "GTP_VREF" LOC ="AA4";
#NET "GTP_134_VTTTX" LOC ="AY13";
#NET "GTP_134_VTTTX" LOC ="AY18";
#NET "GTP_134_VTTRX" LOC ="AY14";
#NET "GTP_134_TX1_P_C" LOC ="BA18";
#NET "GTP_134_TX1_N_C" LOC ="BA17";
#NET "GTP_134_TX0_P_C" LOC ="BA13";
#NET "GTP_134_TX0_N_C" LOC ="BA14";
#NET "GTP_134_RX1_P" LOC ="BB17";
#NET "GTP_134_RX1_N" LOC ="BB16";
#NET "GTP_134_RX0_P" LOC ="BB14";
#NET "GTP_134_RX0_N" LOC ="BB15";
#NET "GTP_134_AVCC_PLL" LOC ="AY17";
#NET "GTP_134_AVCC" LOC ="AW16";
#NET "GTP_134_AVCC" LOC ="AY16";
#NET "GTP_132_VTTTX" LOC ="C13";
#NET "GTP_132_VTTTX" LOC ="C18";
#NET "GTP_132_VTTRX" LOC ="C17";
#NET "GTP_132_AVCC_PLL" LOC ="C14";
#NET "GTP_132_AVCC" LOC ="C15";
#NET "GTP_132_AVCC" LOC ="D15";
#NET "GTP_130_VTTTX" LOC ="AY12";
#NET "GTP_130_VTTTX" LOC ="AY7";
#NET "GTP_130_VTTRX" LOC ="AY8";
#NET "GTP_128_VTTTX" LOC ="C12";
#NET "GTP_128_VTTTX" LOC ="C7";
#NET "GTP_128_VTTRX" LOC ="C11";
#NET "GTP_128_AVCC_PLL" LOC ="C8";
#NET "GTP_128_AVCC" LOC ="C9";
#NET "GTP_128_AVCC" LOC ="D9";
#NET "GTP_126_VTTTX" LOC ="AY1";
#NET "GTP_126_VTTTX" LOC ="AY6";
#NET "GTP_126_VTTRX" LOC ="AY2";
#NET "GTP_126_AVCC_PLL" LOC ="AY5";
#NET "GTP_126_AVCC" LOC ="AW5";
#NET "GTP_126_AVCC" LOC ="AY3";
#NET "GTP_124_VTTTX" LOC ="C1";
#NET "GTP_124_VTTTX" LOC ="C6";
#NET "GTP_124_VTTRX" LOC ="C5";
#NET "GTP_124_TX1_P" LOC ="B1";
#NET "GTP_124_TX1_N" LOC ="B2";
#NET "GTP_124_TX0_P" LOC ="B6";
#NET "GTP_124_TX0_N" LOC ="B5";
#NET "GTP_124_RX1_P" LOC ="A2";
#NET "GTP_124_RX1_N" LOC ="A3";
#NET "GTP_124_RX0_P" LOC ="A5";
#NET "GTP_124_RX0_N" LOC ="A4";
#NET "GTP_124_RTERM" LOC ="Y5";
#NET "GTP_124_AVCC_PLL" LOC ="C2";
#NET "GTP_124_AVCC" LOC ="D4";
#NET "GTP_124_AVCC" LOC ="D5";
#NET "GTP_122_VTTTX" LOC ="AP3";
#NET "GTP_122_VTTTX" LOC ="AW3";
#NET "GTP_122_VTTRX" LOC ="AR3";
#NET "GTP_122_AVCC_PLL" LOC ="AV3";
#NET "GTP_122_AVCC" LOC ="AU3";
#NET "GTP_122_AVCC" LOC ="AU4";
#NET "GTP_120_VTTTX" LOC ="D3";
#NET "GTP_120_VTTTX" LOC ="J3";
#NET "GTP_120_VTTRX" LOC ="E3";
#NET "GTP_120_AVCC_PLL" LOC ="H3";
#NET "GTP_120_AVCC" LOC ="G3";
#NET "GTP_120_AVCC" LOC ="G4";
#NET "GTP_118_VTTTX" LOC ="AH3";
#NET "GTP_118_VTTTX" LOC ="AN3";
#NET "GTP_118_VTTRX" LOC ="AJ3";
#NET "GTP_118_TX1_P" LOC ="AN2";
#NET "GTP_118_TX1_N" LOC ="AM2";
#NET "GTP_118_TX0_P" LOC ="AH2";
#NET "GTP_118_TX0_N" LOC ="AJ2";
#NET "GTP_118_RX1_P" LOC ="AM1";
#NET "GTP_118_RX1_N" LOC ="AL1";
#NET "GTP_118_RX0_P" LOC ="AJ1";
#NET "GTP_118_RX0_N" LOC ="AK1";
#NET "GTP_118_AVCC_PLL" LOC ="AM3";
#NET "GTP_118_AVCC" LOC ="AL3";
#NET "GTP_118_AVCC" LOC ="AL4";
#NET "GTP_116_VTTTX" LOC ="K3";
#NET "GTP_116_VTTTX" LOC ="R3";
#NET "GTP_116_VTTRX" LOC ="L3";
#NET "GTP_116_TX1_P" LOC ="R2";
#NET "GTP_116_TX1_N" LOC ="P2";
#NET "GTP_116_TX0_P" LOC ="K2";
#NET "GTP_116_TX0_N" LOC ="L2";
#NET "GTP_116_RX1_P" LOC ="P1";
#NET "GTP_116_RX1_N" LOC ="N1";
#NET "GTP_116_RX0_P" LOC ="L1";
#NET "GTP_116_RX0_N" LOC ="M1";
#NET "GTP_116_AVCC_PLL" LOC ="P3";
#NET "GTP_116_AVCC" LOC ="N3";
#NET "GTP_116_AVCC" LOC ="N4";
#NET "GTP_114_VTTTX" LOC ="AB3";
#NET "GTP_114_VTTTX" LOC ="AG3";
#NET "GTP_114_VTTRX" LOC ="AC3";
#NET "GTP_114_TX1_P" LOC ="AG2";
#NET "GTP_114_TX1_N" LOC ="AF2";
#NET "GTP_114_TX0_P" LOC ="AB2";
#NET "GTP_114_TX0_N" LOC ="AC2";
#NET "GTP_114_RX1_P" LOC ="AF1";
#NET "GTP_114_RX1_N" LOC ="AE1";
#NET "GTP_114_RX0_P" LOC ="AC1";
#NET "GTP_114_RX0_N" LOC ="AD1";
#NET "GTP_114_GTPCLK_P" LOC ="AD4";
#NET "GTP_114_GTPCLK_N" LOC ="AD3";
#NET "GTP_114_AVCC_PLL" LOC ="AF3";
#NET "GTP_114_AVCC" LOC ="AE3";
#NET "GTP_114_AVCC" LOC ="AE4";
#NET "GTP_112_VTTTX" LOC ="AA3";
#NET "GTP_112_VTTTX" LOC ="T3";
#NET "GTP_112_VTTRX" LOC ="U3";
#NET "GTP_112_TX1_P" LOC ="AA2";
#NET "GTP_112_TX1_N" LOC ="Y2";
#NET "GTP_112_TX0_P" LOC ="T2";
#NET "GTP_112_TX0_N" LOC ="U2";
#NET "GTP_112_RX1_P" LOC ="Y1";
#NET "GTP_112_RX1_N" LOC ="W1";
#NET "GTP_112_RX0_P" LOC ="U1";
#NET "GTP_112_RX0_N" LOC ="V1";
#NET "GTP_112_RREF" LOC ="AB4";
#NET "GTP_112_AVCC_PLL" LOC ="Y3";
#NET "GTP_112_AVCC" LOC ="W3";
#NET "GTP_112_AVCC" LOC ="W4";

//////////////////////////////////////////

#NET "VTRXC" LOC ="AA5";
#NET "VRP_BANK6" LOC ="AP18";
#NET "VRP_BANK5" LOC ="P20";
#NET "VRP_BANK23" LOC ="K34";
#NET "VRP_BANK21" LOC ="AP36";
#NET "VRP_BANK19" LOC ="G37";
#NET "VRP_BANK18" LOC ="AD7";
#NET "VRP_BANK17" LOC ="AH39";
#NET "VRP_BANK15" LOC ="U37";
#NET "VRP_BANK13" LOC ="AL40";
#NET "VRP_BANK12" LOC ="P6";
#NET "VRN_BANK6" LOC ="AR18";
#NET "VRN_BANK5" LOC ="N20";
#NET "VRN_BANK23" LOC ="L34";
#NET "VRN_BANK21" LOC ="AP37";
#NET "VRN_BANK19" LOC ="H36";
#NET "VRN_BANK18" LOC ="AD6";
#NET "VRN_BANK17" LOC ="AG39";
#NET "VRN_BANK15" LOC ="V38";
#NET "VRN_BANK13" LOC ="AK40";
#NET "VRN_BANK12" LOC ="P5";
#NET "VREF_DDR2" LOC ="T41";
#NET "VDDA_SATACLK" LOC ="AA8";
#NET "VDDA_SATACLK" LOC ="U10";
#NET "VCC3_PCI" LOC ="L8";
#NET "VCC3V3" LOC ="AG30";
#NET "VCC2V5" LOC ="E26";
#NET "VCC1V8" LOC ="AA38";
#NET "VCC1V0" LOC ="AA14";

#NET "FPGA_VBATT" LOC ="P30";
#NET "FPGA_TMS" LOC ="AH15";
#NET "FPGA_TDO" LOC ="AJ15";
#NET "FPGA_TDI" LOC ="AH16";
#NET "FPGA_TCK" LOC ="AG29";

#NET "FPGA_PROG_B" LOC ="R29";
#NET "FPGA_MODE_2" LOC ="AJ28";
#NET "FPGA_MODE_1" LOC ="AH30";
#NET "FPGA_MODE_0" LOC ="AH29";
#NET "FPGA_LED_USER2" LOC ="AL24";
#NET "FPGA_LED_USER1" LOC ="AM19";

#NET "FPGA_HSWAP" LOC ="P15";
#NET "FPGA_DX_P" LOC ="AC22";
#NET "FPGA_DX_N" LOC ="AC21";

#NET "FPGA_CCLK" LOC ="AH14";
#NET "FPGA_A22" LOC ="AK14";

#NET "$3N7315" LOC ="R30";
#NET "$3N7288" LOC ="AF30";
#NET "$3N7283" LOC ="T30";
