#============================================================
# Build by Terasic System Builder V1.0.0
#============================================================

set_global_assignment -name FAMILY "Stratix IV"
set_global_assignment -name DEVICE EP4SGX530KH40C2
set_global_assignment -name TOP_LEVEL_ENTITY DE4_GOLDEN_TOP
set_global_assignment -name ORIGINAL_QUARTUS_VERSION 9.1
set_global_assignment -name LAST_QUARTUS_VERSION "11.1 SP1"
set_global_assignment -name PROJECT_CREATION_TIME_DATE "17:41:29 NOVEMBER 25,2009"
set_global_assignment -name DEVICE_FILTER_PIN_COUNT 1152
set_global_assignment -name DEVICE_FILTER_SPEED_GRADE 2

#============================================================
# Pin Assign
#============================================================
set_location_assignment PIN_AH5 -to BUTTON[0]
set_location_assignment PIN_AG5 -to BUTTON[1]
set_location_assignment PIN_AG7 -to BUTTON[2]
set_location_assignment PIN_AG8 -to BUTTON[3]
set_location_assignment PIN_V34 -to CPU_RESET_n
set_location_assignment PIN_AK13 -to CSENSE_ADC_F0
set_location_assignment PIN_AG14 -to CSENSE_CS_n[0]
set_location_assignment PIN_AG15 -to CSENSE_CS_n[1]
set_location_assignment PIN_AH13 -to CSENSE_SCK
set_location_assignment PIN_AJ13 -to CSENSE_SDI
set_location_assignment PIN_AK14 -to CSENSE_SDO
set_location_assignment PIN_G33 -to EEP_SCL
set_location_assignment PIN_F33 -to EEP_SDA
set_location_assignment PIN_B20 -to ETH_INT_n[0]
set_location_assignment PIN_AG30 -to ETH_INT_n[1]
set_location_assignment PIN_AE30 -to ETH_INT_n[2]
set_location_assignment PIN_AE31 -to ETH_INT_n[3]
set_location_assignment PIN_R30 -to ETH_MDC[0]
set_location_assignment PIN_J6 -to ETH_MDC[1]
set_location_assignment PIN_K6 -to ETH_MDC[2]
set_location_assignment PIN_N7 -to ETH_MDC[3]
set_location_assignment PIN_W32 -to ETH_MDIO[0]
set_location_assignment PIN_J5 -to ETH_MDIO[1]
set_location_assignment PIN_K5 -to ETH_MDIO[2]
set_location_assignment PIN_N8 -to ETH_MDIO[3]
set_location_assignment PIN_V29 -to ETH_RST_n
set_location_assignment PIN_U31 -to ETH_RX_p[0]
set_location_assignment PIN_N33 -to ETH_RX_p[1]
set_location_assignment PIN_K34 -to ETH_RX_p[2]
set_location_assignment PIN_J34 -to ETH_RX_p[3]
set_location_assignment PIN_T30 -to ETH_TX_p[0]
set_location_assignment PIN_R32 -to ETH_TX_p[1]
set_location_assignment PIN_M32 -to ETH_TX_p[2]
set_location_assignment PIN_P31 -to ETH_TX_p[3]
set_location_assignment PIN_AC11 -to EXT_IO
set_location_assignment PIN_AP20 -to FAN_CTRL
set_location_assignment PIN_F21 -to FLASH_ADV_n
set_location_assignment PIN_F23 -to FLASH_CE_n
set_location_assignment PIN_E22 -to FLASH_CLK
set_location_assignment PIN_N21 -to FLASH_OE_n
set_location_assignment PIN_G21 -to FLASH_RYBY_n
set_location_assignment PIN_D21 -to FLASH_RESET_n
set_location_assignment PIN_R20 -to FLASH_WE_n
set_location_assignment PIN_G22 -to FSM_A[1]
set_location_assignment PIN_F34 -to FSM_A[10]
set_location_assignment PIN_G35 -to FSM_A[11]
set_location_assignment PIN_E34 -to FSM_A[12]
set_location_assignment PIN_J32 -to FSM_A[13]
set_location_assignment PIN_F35 -to FSM_A[14]
set_location_assignment PIN_C24 -to FSM_A[15]
set_location_assignment PIN_A24 -to FSM_A[16]
set_location_assignment PIN_D23 -to FSM_A[17]
set_location_assignment PIN_D24 -to FSM_A[18]
set_location_assignment PIN_T27 -to FSM_A[19]
set_location_assignment PIN_G23 -to FSM_A[2]
set_location_assignment PIN_T28 -to FSM_A[20]
set_location_assignment PIN_D22 -to FSM_A[21]
set_location_assignment PIN_E23 -to FSM_A[22]
set_location_assignment PIN_N20 -to FSM_A[23]
set_location_assignment PIN_P20 -to FSM_A[24]
set_location_assignment PIN_C22 -to FSM_A[25]
set_location_assignment PIN_A25 -to FSM_A[3]
set_location_assignment PIN_H22 -to FSM_A[4]
set_location_assignment PIN_H23 -to FSM_A[5]
set_location_assignment PIN_J22 -to FSM_A[6]
set_location_assignment PIN_K22 -to FSM_A[7]
set_location_assignment PIN_M21 -to FSM_A[8]
set_location_assignment PIN_J23 -to FSM_A[9]
set_location_assignment PIN_K29 -to FSM_D[0]
set_location_assignment PIN_J30 -to FSM_D[1]
set_location_assignment PIN_C35 -to FSM_D[10]
set_location_assignment PIN_D35 -to FSM_D[11]
set_location_assignment PIN_M22 -to FSM_D[12]
set_location_assignment PIN_M28 -to FSM_D[13]
set_location_assignment PIN_C31 -to FSM_D[14]
set_location_assignment PIN_D31 -to FSM_D[15]
set_location_assignment PIN_K30 -to FSM_D[2]
set_location_assignment PIN_L29 -to FSM_D[3]
set_location_assignment PIN_K31 -to FSM_D[4]
set_location_assignment PIN_E32 -to FSM_D[5]
set_location_assignment PIN_F32 -to FSM_D[6]
set_location_assignment PIN_H32 -to FSM_D[7]
set_location_assignment PIN_B32 -to FSM_D[8]
set_location_assignment PIN_C32 -to FSM_D[9]
set_location_assignment PIN_A21 -to GCLKIN
set_location_assignment PIN_AH19 -to GCLKOUT_FPGA
set_location_assignment PIN_AF6 -to GPIO0_D[0]
set_location_assignment PIN_AU9 -to GPIO0_D[1]
set_location_assignment PIN_AT5 -to GPIO0_D[10]
set_location_assignment PIN_AT8 -to GPIO0_D[11]
set_location_assignment PIN_AP5 -to GPIO0_D[12]
set_location_assignment PIN_AP7 -to GPIO0_D[13]
set_location_assignment PIN_AN5 -to GPIO0_D[14]
set_location_assignment PIN_AN10 -to GPIO0_D[15]
set_location_assignment PIN_AM5 -to GPIO0_D[16]
set_location_assignment PIN_AM10 -to GPIO0_D[17]
set_location_assignment PIN_AL10 -to GPIO0_D[18]
set_location_assignment PIN_AM8 -to GPIO0_D[19]
set_location_assignment PIN_AE5 -to GPIO0_D[2]
set_location_assignment PIN_AL8 -to GPIO0_D[20]
set_location_assignment PIN_AK8 -to GPIO0_D[21]
set_location_assignment PIN_AJ11 -to GPIO0_D[22]
set_location_assignment PIN_AK7 -to GPIO0_D[23]
set_location_assignment PIN_AJ5 -to GPIO0_D[24]
set_location_assignment PIN_AH12 -to GPIO0_D[25]
set_location_assignment PIN_AG10 -to GPIO0_D[26]
set_location_assignment PIN_AG13 -to GPIO0_D[27]
set_location_assignment PIN_AG9 -to GPIO0_D[28]
set_location_assignment PIN_AF11 -to GPIO0_D[29]
set_location_assignment PIN_AR8 -to GPIO0_D[3]
set_location_assignment PIN_AT9 -to GPIO0_D[30]
set_location_assignment PIN_AF10 -to GPIO0_D[31]
set_location_assignment PIN_AD10 -to GPIO0_D[32]
set_location_assignment PIN_AD9 -to GPIO0_D[33]
set_location_assignment PIN_AD12 -to GPIO0_D[34]
set_location_assignment PIN_AD13 -to GPIO0_D[35]
set_location_assignment PIN_AN9 -to GPIO0_D[4]
set_location_assignment PIN_AP9 -to GPIO0_D[5]
set_location_assignment PIN_AV5 -to GPIO0_D[6]
set_location_assignment PIN_AW6 -to GPIO0_D[7]
set_location_assignment PIN_AV7 -to GPIO0_D[8]
set_location_assignment PIN_AW7 -to GPIO0_D[9]
set_location_assignment PIN_AW5 -to GPIO1_D[0]
set_location_assignment PIN_AW8 -to GPIO1_D[1]
set_location_assignment PIN_AU6 -to GPIO1_D[10]
set_location_assignment PIN_AT6 -to GPIO1_D[11]
set_location_assignment PIN_AU7 -to GPIO1_D[12]
set_location_assignment PIN_AR5 -to GPIO1_D[13]
set_location_assignment PIN_AP6 -to GPIO1_D[14]
set_location_assignment PIN_AT7 -to GPIO1_D[15]
set_location_assignment PIN_AN7 -to GPIO1_D[16]
set_location_assignment PIN_AN6 -to GPIO1_D[17]
set_location_assignment PIN_AL6 -to GPIO1_D[18]
set_location_assignment PIN_AM6 -to GPIO1_D[19]
set_location_assignment PIN_AW4 -to GPIO1_D[2]
set_location_assignment PIN_AL5 -to GPIO1_D[20]
set_location_assignment PIN_AL9 -to GPIO1_D[21]
set_location_assignment PIN_AK9 -to GPIO1_D[22]
set_location_assignment PIN_AJ6 -to GPIO1_D[23]
set_location_assignment PIN_AJ10 -to GPIO1_D[24]
set_location_assignment PIN_AH11 -to GPIO1_D[25]
set_location_assignment PIN_AH8 -to GPIO1_D[26]
set_location_assignment PIN_AH9 -to GPIO1_D[27]
set_location_assignment PIN_AG12 -to GPIO1_D[28]
set_location_assignment PIN_AH10 -to GPIO1_D[29]
set_location_assignment PIN_AV10 -to GPIO1_D[3]
set_location_assignment PIN_AF13 -to GPIO1_D[30]
set_location_assignment PIN_AE13 -to GPIO1_D[31]
set_location_assignment PIN_AE10 -to GPIO1_D[32]
set_location_assignment PIN_AP10 -to GPIO1_D[33]
set_location_assignment PIN_AE12 -to GPIO1_D[34]
set_location_assignment PIN_AE11 -to GPIO1_D[35]
set_location_assignment PIN_AV8 -to GPIO1_D[4]
set_location_assignment PIN_AW10 -to GPIO1_D[5]
set_location_assignment PIN_AU10 -to GPIO1_D[6]
set_location_assignment PIN_AU8 -to GPIO1_D[7]
set_location_assignment PIN_AP8 -to GPIO1_D[8]
set_location_assignment PIN_AT10 -to GPIO1_D[9]
set_location_assignment PIN_AA35 -to HSMA_CLKIN_N1
set_location_assignment PIN_AE35 -to HSMA_CLKIN_N2
set_location_assignment PIN_AB34 -to HSMA_CLKIN_P1
set_location_assignment PIN_AF34 -to HSMA_CLKIN_P2
set_location_assignment PIN_AC34 -to HSMA_CLKIN0
set_location_assignment PIN_AG35 -to HSMA_CLKOUT_n2
set_location_assignment PIN_AG34 -to HSMA_CLKOUT_p2
set_location_assignment PIN_AC26 -to HSMA_D[0]
set_location_assignment PIN_AC31 -to HSMA_D[1]
set_location_assignment PIN_AD26 -to HSMA_D[2]
set_location_assignment PIN_AC32 -to HSMA_D[3]
set_location_assignment PIN_N38 -to HSMA_GXB_RX_p[0]
set_location_assignment PIN_L38 -to HSMA_GXB_RX_p[1]
set_location_assignment PIN_E38 -to HSMA_GXB_RX_p[2]
set_location_assignment PIN_C38 -to HSMA_GXB_RX_p[3]
set_location_assignment PIN_M36 -to HSMA_GXB_TX_p[0]
set_location_assignment PIN_K36 -to HSMA_GXB_TX_p[1]
set_location_assignment PIN_D36 -to HSMA_GXB_TX_p[2]
set_location_assignment PIN_B36 -to HSMA_GXB_TX_p[3]
set_location_assignment PIN_AH28 -to HSMA_OUT_n1
set_location_assignment PIN_AG28 -to HSMA_OUT_p1
set_location_assignment PIN_AF29 -to HSMA_OUT0
set_location_assignment PIN_J38 -to HSMA_REFCLK_p
set_location_assignment PIN_AK33 -to HSMA_RX_n[0]
set_location_assignment PIN_AH35 -to HSMA_RX_n[1]
set_location_assignment PIN_AU33 -to HSMA_RX_n[10]
set_location_assignment PIN_AV34 -to HSMA_RX_n[11]
set_location_assignment PIN_AU32 -to HSMA_RX_n[12]
set_location_assignment PIN_AU31 -to HSMA_RX_n[13]
set_location_assignment PIN_AR35 -to HSMA_RX_n[14]
set_location_assignment PIN_AP33 -to HSMA_RX_n[15]
set_location_assignment PIN_AR34 -to HSMA_RX_n[16]
set_location_assignment PIN_AJ35 -to HSMA_RX_n[2]
set_location_assignment PIN_AK35 -to HSMA_RX_n[3]
set_location_assignment PIN_AP30 -to HSMA_RX_n[4]
set_location_assignment PIN_AM35 -to HSMA_RX_n[5]
set_location_assignment PIN_AN31 -to HSMA_RX_n[6]
set_location_assignment PIN_AP34 -to HSMA_RX_n[7]
set_location_assignment PIN_AR32 -to HSMA_RX_n[8]
set_location_assignment PIN_AT30 -to HSMA_RX_n[9]
set_location_assignment PIN_AJ32 -to HSMA_RX_p[0]
set_location_assignment PIN_AH34 -to HSMA_RX_p[1]
set_location_assignment PIN_AT33 -to HSMA_RX_p[10]
set_location_assignment PIN_AU34 -to HSMA_RX_p[11]
set_location_assignment PIN_AT32 -to HSMA_RX_p[12]
set_location_assignment PIN_AT31 -to HSMA_RX_p[13]
set_location_assignment PIN_AP35 -to HSMA_RX_p[14]
set_location_assignment PIN_AN32 -to HSMA_RX_p[15]
set_location_assignment PIN_AT34 -to HSMA_RX_p[16]
set_location_assignment PIN_AJ34 -to HSMA_RX_p[2]
set_location_assignment PIN_AK34 -to HSMA_RX_p[3]
set_location_assignment PIN_AN30 -to HSMA_RX_p[4]
set_location_assignment PIN_AM34 -to HSMA_RX_p[5]
set_location_assignment PIN_AM31 -to HSMA_RX_p[6]
set_location_assignment PIN_AN33 -to HSMA_RX_p[7]
set_location_assignment PIN_AP32 -to HSMA_RX_p[8]
set_location_assignment PIN_AR31 -to HSMA_RX_p[9]
set_location_assignment PIN_AB28 -to HSMA_TX_n[0]
set_location_assignment PIN_AB31 -to HSMA_TX_n[1]
set_location_assignment PIN_AD31 -to HSMA_TX_n[10]
set_location_assignment PIN_AL32 -to HSMA_TX_n[11]
set_location_assignment PIN_AH27 -to HSMA_TX_n[12]
set_location_assignment PIN_AL31 -to HSMA_TX_n[13]
set_location_assignment PIN_AH30 -to HSMA_TX_n[14]
set_location_assignment PIN_AM29 -to HSMA_TX_n[15]
set_location_assignment PIN_AL30 -to HSMA_TX_n[16]
set_location_assignment PIN_AE27 -to HSMA_TX_n[2]
set_location_assignment PIN_AD29 -to HSMA_TX_n[3]
set_location_assignment PIN_AE29 -to HSMA_TX_n[4]
set_location_assignment PIN_AF26 -to HSMA_TX_n[5]
set_location_assignment PIN_AG32 -to HSMA_TX_n[6]
set_location_assignment PIN_AH29 -to HSMA_TX_n[7]
set_location_assignment PIN_AC29 -to HSMA_TX_n[8]
set_location_assignment PIN_AK29 -to HSMA_TX_n[9]
set_location_assignment PIN_AB27 -to HSMA_TX_p[0]
set_location_assignment PIN_AB30 -to HSMA_TX_p[1]
set_location_assignment PIN_AD30 -to HSMA_TX_p[10]
set_location_assignment PIN_AK32 -to HSMA_TX_p[11]
set_location_assignment PIN_AG27 -to HSMA_TX_p[12]
set_location_assignment PIN_AK31 -to HSMA_TX_p[13]
set_location_assignment PIN_AJ31 -to HSMA_TX_p[14]
set_location_assignment PIN_AL29 -to HSMA_TX_p[15]
set_location_assignment PIN_AK30 -to HSMA_TX_p[16]
set_location_assignment PIN_AD27 -to HSMA_TX_p[2]
set_location_assignment PIN_AD28 -to HSMA_TX_p[3]
set_location_assignment PIN_AE28 -to HSMA_TX_p[4]
set_location_assignment PIN_AE26 -to HSMA_TX_p[5]
set_location_assignment PIN_AG31 -to HSMA_TX_p[6]
set_location_assignment PIN_AG29 -to HSMA_TX_p[7]
set_location_assignment PIN_AC28 -to HSMA_TX_p[8]
set_location_assignment PIN_AJ29 -to HSMA_TX_p[9]
set_location_assignment PIN_W35 -to HSMB_CLKIN_N1
set_location_assignment PIN_W5 -to HSMB_CLKIN_N2
set_location_assignment PIN_W34 -to HSMB_CLKIN_P1
set_location_assignment PIN_W6 -to HSMB_CLKIN_P2
set_location_assignment PIN_AA5 -to HSMB_CLKIN0
set_location_assignment PIN_W11 -to HSMB_CLKOUT_n2
set_location_assignment PIN_W12 -to HSMB_CLKOUT_p2
set_location_assignment PIN_H10 -to HSMB_D[0]
set_location_assignment PIN_D6 -to HSMB_D[1]
set_location_assignment PIN_G10 -to HSMB_D[2]
set_location_assignment PIN_C6 -to HSMB_D[3]
set_location_assignment PIN_AE2 -to HSMB_GXB_RX_p[0]
set_location_assignment PIN_AC2 -to HSMB_GXB_RX_p[1]
set_location_assignment PIN_U2 -to HSMB_GXB_RX_p[2]
set_location_assignment PIN_R2 -to HSMB_GXB_RX_p[3]
set_location_assignment PIN_N2 -to HSMB_GXB_RX_p[4]
set_location_assignment PIN_L2 -to HSMB_GXB_RX_p[5]
set_location_assignment PIN_E2 -to HSMB_GXB_RX_p[6]
set_location_assignment PIN_C2 -to HSMB_GXB_RX_p[7]
set_location_assignment PIN_AD4 -to HSMB_GXB_TX_p[0]
set_location_assignment PIN_AB4 -to HSMB_GXB_TX_p[1]
set_location_assignment PIN_T4 -to HSMB_GXB_TX_p[2]
set_location_assignment PIN_P4 -to HSMB_GXB_TX_p[3]
set_location_assignment PIN_M4 -to HSMB_GXB_TX_p[4]
set_location_assignment PIN_K4 -to HSMB_GXB_TX_p[5]
set_location_assignment PIN_D4 -to HSMB_GXB_TX_p[6]
set_location_assignment PIN_B4 -to HSMB_GXB_TX_p[7]
set_location_assignment PIN_J8 -to HSMB_OUT_n1
set_location_assignment PIN_K8 -to HSMB_OUT_p1
set_location_assignment PIN_L8 -to HSMB_OUT0
set_location_assignment PIN_AA2 -to HSMB_REFCLK_p
set_location_assignment PIN_C5 -to HSMB_RX_n[0]
set_location_assignment PIN_C10 -to HSMB_RX_n[1]
set_location_assignment PIN_F9 -to HSMB_RX_n[10]
set_location_assignment PIN_N5 -to HSMB_RX_n[11]
set_location_assignment PIN_L5 -to HSMB_RX_n[12]
set_location_assignment PIN_R5 -to HSMB_RX_n[13]
set_location_assignment PIN_P6 -to HSMB_RX_n[14]
set_location_assignment PIN_U5 -to HSMB_RX_n[15]
set_location_assignment PIN_W7 -to HSMB_RX_n[16]
set_location_assignment PIN_C9 -to HSMB_RX_n[2]
set_location_assignment PIN_C8 -to HSMB_RX_n[3]
set_location_assignment PIN_C7 -to HSMB_RX_n[4]
set_location_assignment PIN_E10 -to HSMB_RX_n[5]
set_location_assignment PIN_F5 -to HSMB_RX_n[6]
set_location_assignment PIN_F6 -to HSMB_RX_n[7]
set_location_assignment PIN_E7 -to HSMB_RX_n[8]
set_location_assignment PIN_F8 -to HSMB_RX_n[9]
set_location_assignment PIN_D5 -to HSMB_RX_p[0]
set_location_assignment PIN_D10 -to HSMB_RX_p[1]
set_location_assignment PIN_G9 -to HSMB_RX_p[10]
set_location_assignment PIN_N6 -to HSMB_RX_p[11]
set_location_assignment PIN_M6 -to HSMB_RX_p[12]
set_location_assignment PIN_R6 -to HSMB_RX_p[13]
set_location_assignment PIN_R7 -to HSMB_RX_p[14]
set_location_assignment PIN_V6 -to HSMB_RX_p[15]
set_location_assignment PIN_W8 -to HSMB_RX_p[16]
set_location_assignment PIN_D9 -to HSMB_RX_p[2]
set_location_assignment PIN_D8 -to HSMB_RX_p[3]
set_location_assignment PIN_D7 -to HSMB_RX_p[4]
set_location_assignment PIN_F10 -to HSMB_RX_p[5]
set_location_assignment PIN_G5 -to HSMB_RX_p[6]
set_location_assignment PIN_G6 -to HSMB_RX_p[7]
set_location_assignment PIN_F7 -to HSMB_RX_p[8]
set_location_assignment PIN_G8 -to HSMB_RX_p[9]
set_location_assignment PIN_J9 -to HSMB_TX_n[0]
set_location_assignment PIN_J10 -to HSMB_TX_n[1]
set_location_assignment PIN_L11 -to HSMB_TX_n[10]
set_location_assignment PIN_P8 -to HSMB_TX_n[11]
set_location_assignment PIN_R8 -to HSMB_TX_n[12]
set_location_assignment PIN_T9 -to HSMB_TX_n[13]
set_location_assignment PIN_V9 -to HSMB_TX_n[14]
set_location_assignment PIN_R10 -to HSMB_TX_n[15]
set_location_assignment PIN_V11 -to HSMB_TX_n[16]
set_location_assignment PIN_N10 -to HSMB_TX_n[2]
set_location_assignment PIN_M12 -to HSMB_TX_n[3]
set_location_assignment PIN_R11 -to HSMB_TX_n[4]
set_location_assignment PIN_T12 -to HSMB_TX_n[5]
set_location_assignment PIN_P13 -to HSMB_TX_n[6]
set_location_assignment PIN_G7 -to HSMB_TX_n[7]
set_location_assignment PIN_L10 -to HSMB_TX_n[8]
set_location_assignment PIN_M7 -to HSMB_TX_n[9]
set_location_assignment PIN_K9 -to HSMB_TX_p[0]
set_location_assignment PIN_K10 -to HSMB_TX_p[1]
set_location_assignment PIN_M11 -to HSMB_TX_p[10]
set_location_assignment PIN_N9 -to HSMB_TX_p[11]
set_location_assignment PIN_R9 -to HSMB_TX_p[12]
set_location_assignment PIN_U10 -to HSMB_TX_p[13]
set_location_assignment PIN_V10 -to HSMB_TX_p[14]
set_location_assignment PIN_T10 -to HSMB_TX_p[15]
set_location_assignment PIN_V12 -to HSMB_TX_p[16]
set_location_assignment PIN_N11 -to HSMB_TX_p[2]
set_location_assignment PIN_N12 -to HSMB_TX_p[3]
set_location_assignment PIN_R12 -to HSMB_TX_p[4]
set_location_assignment PIN_T13 -to HSMB_TX_p[5]
set_location_assignment PIN_R13 -to HSMB_TX_p[6]
set_location_assignment PIN_H7 -to HSMB_TX_p[7]
set_location_assignment PIN_M10 -to HSMB_TX_p[8]
set_location_assignment PIN_M8 -to HSMB_TX_p[9]
set_location_assignment PIN_L19 -to HSMC_SCL
set_location_assignment PIN_M19 -to HSMC_SDA
set_location_assignment PIN_V28 -to LED[0]
set_location_assignment PIN_W28 -to LED[1]
set_location_assignment PIN_R29 -to LED[2]
set_location_assignment PIN_P29 -to LED[3]
set_location_assignment PIN_N29 -to LED[4]
set_location_assignment PIN_M29 -to LED[5]
set_location_assignment PIN_M30 -to LED[6]
set_location_assignment PIN_N30 -to LED[7]
set_location_assignment PIN_AV23 -to M1_DDR2_addr[0]
set_location_assignment PIN_AL25 -to M1_DDR2_addr[1]
set_location_assignment PIN_AJ26 -to M1_DDR2_addr[10]
set_location_assignment PIN_AU28 -to M1_DDR2_addr[11]
set_location_assignment PIN_AP26 -to M1_DDR2_addr[12]
set_location_assignment PIN_AD21 -to M1_DDR2_addr[13]
set_location_assignment PIN_AU29 -to M1_DDR2_addr[14]
set_location_assignment PIN_AT29 -to M1_DDR2_addr[15]
set_location_assignment PIN_AW23 -to M1_DDR2_addr[2]
set_location_assignment PIN_AM26 -to M1_DDR2_addr[3]
set_location_assignment PIN_AN26 -to M1_DDR2_addr[4]
set_location_assignment PIN_AK26 -to M1_DDR2_addr[5]
set_location_assignment PIN_AU27 -to M1_DDR2_addr[6]
set_location_assignment PIN_AT27 -to M1_DDR2_addr[7]
set_location_assignment PIN_AL27 -to M1_DDR2_addr[8]
set_location_assignment PIN_AN27 -to M1_DDR2_addr[9]
set_location_assignment PIN_AH26 -to M1_DDR2_ba[0]
set_location_assignment PIN_AD25 -to M1_DDR2_ba[1]
set_location_assignment PIN_AP27 -to M1_DDR2_ba[2]
set_location_assignment PIN_AJ25 -to M1_DDR2_cas_n
set_location_assignment PIN_AT28 -to M1_DDR2_cke[0]
set_location_assignment PIN_AK27 -to M1_DDR2_cke[1]
set_location_assignment PIN_AR28 -to M1_DDR2_clk_n[0]
set_location_assignment PIN_AF20 -to M1_DDR2_clk_n[1]
set_location_assignment PIN_AP28 -to M1_DDR2_clk[0]
set_location_assignment PIN_AE20 -to M1_DDR2_clk[1]
set_location_assignment PIN_AG21 -to M1_DDR2_cs_n[0]
set_location_assignment PIN_AE25 -to M1_DDR2_cs_n[1]
set_location_assignment PIN_AW31 -to M1_DDR2_dm[0]
set_location_assignment PIN_AW26 -to M1_DDR2_dm[1]
set_location_assignment PIN_AU23 -to M1_DDR2_dm[2]
set_location_assignment PIN_AH22 -to M1_DDR2_dm[3]
set_location_assignment PIN_AL17 -to M1_DDR2_dm[4]
set_location_assignment PIN_AT16 -to M1_DDR2_dm[5]
set_location_assignment PIN_AU14 -to M1_DDR2_dm[6]
set_location_assignment PIN_AN13 -to M1_DDR2_dm[7]
set_location_assignment PIN_AV32 -to M1_DDR2_dq[0]
set_location_assignment PIN_AV31 -to M1_DDR2_dq[1]
set_location_assignment PIN_AU25 -to M1_DDR2_dq[10]
set_location_assignment PIN_AT25 -to M1_DDR2_dq[11]
set_location_assignment PIN_AM25 -to M1_DDR2_dq[12]
set_location_assignment PIN_AN25 -to M1_DDR2_dq[13]
set_location_assignment PIN_AR25 -to M1_DDR2_dq[14]
set_location_assignment PIN_AN24 -to M1_DDR2_dq[15]
set_location_assignment PIN_AN23 -to M1_DDR2_dq[16]
set_location_assignment PIN_AP23 -to M1_DDR2_dq[17]
set_location_assignment PIN_AL22 -to M1_DDR2_dq[18]
set_location_assignment PIN_AM22 -to M1_DDR2_dq[19]
set_location_assignment PIN_AW29 -to M1_DDR2_dq[2]
set_location_assignment PIN_AM23 -to M1_DDR2_dq[20]
set_location_assignment PIN_AR23 -to M1_DDR2_dq[21]
set_location_assignment PIN_AT23 -to M1_DDR2_dq[22]
set_location_assignment PIN_AL21 -to M1_DDR2_dq[23]
set_location_assignment PIN_AJ22 -to M1_DDR2_dq[24]
set_location_assignment PIN_AH23 -to M1_DDR2_dq[25]
set_location_assignment PIN_AF22 -to M1_DDR2_dq[26]
set_location_assignment PIN_AE23 -to M1_DDR2_dq[27]
set_location_assignment PIN_AK24 -to M1_DDR2_dq[28]
set_location_assignment PIN_AJ23 -to M1_DDR2_dq[29]
set_location_assignment PIN_AV28 -to M1_DDR2_dq[3]
set_location_assignment PIN_AF23 -to M1_DDR2_dq[30]
set_location_assignment PIN_AE22 -to M1_DDR2_dq[31]
set_location_assignment PIN_AK17 -to M1_DDR2_dq[32]
set_location_assignment PIN_AM17 -to M1_DDR2_dq[33]
set_location_assignment PIN_AH16 -to M1_DDR2_dq[34]
set_location_assignment PIN_AJ16 -to M1_DDR2_dq[35]
set_location_assignment PIN_AG16 -to M1_DDR2_dq[36]
set_location_assignment PIN_AH17 -to M1_DDR2_dq[37]
set_location_assignment PIN_AF17 -to M1_DDR2_dq[38]
set_location_assignment PIN_AE17 -to M1_DDR2_dq[39]
set_location_assignment PIN_AW34 -to M1_DDR2_dq[4]
set_location_assignment PIN_AR17 -to M1_DDR2_dq[40]
set_location_assignment PIN_AN16 -to M1_DDR2_dq[41]
set_location_assignment PIN_AU16 -to M1_DDR2_dq[42]
set_location_assignment PIN_AW16 -to M1_DDR2_dq[43]
set_location_assignment PIN_AN17 -to M1_DDR2_dq[44]
set_location_assignment PIN_AP17 -to M1_DDR2_dq[45]
set_location_assignment PIN_AU15 -to M1_DDR2_dq[46]
set_location_assignment PIN_AT15 -to M1_DDR2_dq[47]
set_location_assignment PIN_AW11 -to M1_DDR2_dq[48]
set_location_assignment PIN_AW12 -to M1_DDR2_dq[49]
set_location_assignment PIN_AW33 -to M1_DDR2_dq[5]
set_location_assignment PIN_AT14 -to M1_DDR2_dq[50]
set_location_assignment PIN_AU12 -to M1_DDR2_dq[51]
set_location_assignment PIN_AW14 -to M1_DDR2_dq[52]
set_location_assignment PIN_AV14 -to M1_DDR2_dq[53]
set_location_assignment PIN_AU11 -to M1_DDR2_dq[54]
set_location_assignment PIN_AT12 -to M1_DDR2_dq[55]
set_location_assignment PIN_AP13 -to M1_DDR2_dq[56]
set_location_assignment PIN_AN14 -to M1_DDR2_dq[57]
set_location_assignment PIN_AL15 -to M1_DDR2_dq[58]
set_location_assignment PIN_AM14 -to M1_DDR2_dq[59]
set_location_assignment PIN_AW28 -to M1_DDR2_dq[6]
set_location_assignment PIN_AR14 -to M1_DDR2_dq[60]
set_location_assignment PIN_AP14 -to M1_DDR2_dq[61]
set_location_assignment PIN_AL14 -to M1_DDR2_dq[62]
set_location_assignment PIN_AL13 -to M1_DDR2_dq[63]
set_location_assignment PIN_AW27 -to M1_DDR2_dq[7]
set_location_assignment PIN_AP25 -to M1_DDR2_dq[8]
set_location_assignment PIN_AV26 -to M1_DDR2_dq[9]
set_location_assignment PIN_AW30 -to M1_DDR2_dqsn[0]
set_location_assignment PIN_AU26 -to M1_DDR2_dqsn[1]
set_location_assignment PIN_AU24 -to M1_DDR2_dqsn[2]
set_location_assignment PIN_AL23 -to M1_DDR2_dqsn[3]
set_location_assignment PIN_AL16 -to M1_DDR2_dqsn[4]
set_location_assignment PIN_AR16 -to M1_DDR2_dqsn[5]
set_location_assignment PIN_AW13 -to M1_DDR2_dqsn[6]
set_location_assignment PIN_AT13 -to M1_DDR2_dqsn[7]
set_location_assignment PIN_AV29 -to M1_DDR2_dqs[0]
set_location_assignment PIN_AT26 -to M1_DDR2_dqs[1]
set_location_assignment PIN_AT24 -to M1_DDR2_dqs[2]
set_location_assignment PIN_AK23 -to M1_DDR2_dqs[3]
set_location_assignment PIN_AK16 -to M1_DDR2_dqs[4]
set_location_assignment PIN_AP16 -to M1_DDR2_dqs[5]
set_location_assignment PIN_AV13 -to M1_DDR2_dqs[6]
set_location_assignment PIN_AR13 -to M1_DDR2_dqs[7]
set_location_assignment PIN_AG20 -to M1_DDR2_odt[0]
set_location_assignment PIN_AE24 -to M1_DDR2_odt[1]
set_location_assignment PIN_AE21 -to M1_DDR2_ras_n
set_location_assignment PIN_AV25 -to M1_DDR2_SA[0]
set_location_assignment PIN_AW25 -to M1_DDR2_SA[1]
set_location_assignment PIN_AH24 -to M1_DDR2_SCL
set_location_assignment PIN_AG24 -to M1_DDR2_SDA
set_location_assignment PIN_AK25 -to M1_DDR2_we_n
set_location_assignment PIN_B14 -to M2_DDR2_addr[0]
set_location_assignment PIN_B11 -to M2_DDR2_addr[1]
set_location_assignment PIN_R18 -to M2_DDR2_addr[10]
set_location_assignment PIN_L14 -to M2_DDR2_addr[11]
set_location_assignment PIN_N15 -to M2_DDR2_addr[12]
set_location_assignment PIN_C19 -to M2_DDR2_addr[13]
set_location_assignment PIN_K14 -to M2_DDR2_addr[14]
set_location_assignment PIN_M13 -to M2_DDR2_addr[15]
set_location_assignment PIN_D14 -to M2_DDR2_addr[2]
set_location_assignment PIN_R14 -to M2_DDR2_addr[3]
set_location_assignment PIN_C13 -to M2_DDR2_addr[4]
set_location_assignment PIN_C11 -to M2_DDR2_addr[5]
set_location_assignment PIN_A11 -to M2_DDR2_addr[6]
set_location_assignment PIN_N13 -to M2_DDR2_addr[7]
set_location_assignment PIN_A10 -to M2_DDR2_addr[8]
set_location_assignment PIN_M14 -to M2_DDR2_addr[9]
set_location_assignment PIN_C12 -to M2_DDR2_ba[0]
set_location_assignment PIN_C14 -to M2_DDR2_ba[1]
set_location_assignment PIN_B10 -to M2_DDR2_ba[2]
set_location_assignment PIN_A13 -to M2_DDR2_cas_n
set_location_assignment PIN_D11 -to M2_DDR2_cke[0]
set_location_assignment PIN_K12 -to M2_DDR2_cke[1]
set_location_assignment PIN_K13 -to M2_DDR2_clk_n[0]
set_location_assignment PIN_A17 -to M2_DDR2_clk_n[1]
set_location_assignment PIN_L13 -to M2_DDR2_clk[0]
set_location_assignment PIN_B17 -to M2_DDR2_clk[1]
set_location_assignment PIN_H19 -to M2_DDR2_cs_n[0]
set_location_assignment PIN_B13 -to M2_DDR2_cs_n[1]
set_location_assignment PIN_H14 -to M2_DDR2_dm[0]
set_location_assignment PIN_M17 -to M2_DDR2_dm[1]
set_location_assignment PIN_G15 -to M2_DDR2_dm[2]
set_location_assignment PIN_F17 -to M2_DDR2_dm[3]
set_location_assignment PIN_P23 -to M2_DDR2_dm[4]
set_location_assignment PIN_B25 -to M2_DDR2_dm[5]
set_location_assignment PIN_D28 -to M2_DDR2_dm[6]
set_location_assignment PIN_C30 -to M2_DDR2_dm[7]
set_location_assignment PIN_F12 -to M2_DDR2_dq[0]
set_location_assignment PIN_H13 -to M2_DDR2_dq[1]
set_location_assignment PIN_L16 -to M2_DDR2_dq[10]
set_location_assignment PIN_K17 -to M2_DDR2_dq[11]
set_location_assignment PIN_P16 -to M2_DDR2_dq[12]
set_location_assignment PIN_N16 -to M2_DDR2_dq[13]
set_location_assignment PIN_J17 -to M2_DDR2_dq[14]
set_location_assignment PIN_H17 -to M2_DDR2_dq[15]
set_location_assignment PIN_B16 -to M2_DDR2_dq[16]
set_location_assignment PIN_A16 -to M2_DDR2_dq[17]
set_location_assignment PIN_F15 -to M2_DDR2_dq[18]
set_location_assignment PIN_D16 -to M2_DDR2_dq[19]
set_location_assignment PIN_E14 -to M2_DDR2_dq[2]
set_location_assignment PIN_C16 -to M2_DDR2_dq[20]
set_location_assignment PIN_E16 -to M2_DDR2_dq[21]
set_location_assignment PIN_G16 -to M2_DDR2_dq[22]
set_location_assignment PIN_G17 -to M2_DDR2_dq[23]
set_location_assignment PIN_C17 -to M2_DDR2_dq[24]
set_location_assignment PIN_E17 -to M2_DDR2_dq[25]
set_location_assignment PIN_F19 -to M2_DDR2_dq[26]
set_location_assignment PIN_G19 -to M2_DDR2_dq[27]
set_location_assignment PIN_C18 -to M2_DDR2_dq[28]
set_location_assignment PIN_D18 -to M2_DDR2_dq[29]
set_location_assignment PIN_F14 -to M2_DDR2_dq[3]
set_location_assignment PIN_F20 -to M2_DDR2_dq[30]
set_location_assignment PIN_G20 -to M2_DDR2_dq[31]
set_location_assignment PIN_N22 -to M2_DDR2_dq[32]
set_location_assignment PIN_M23 -to M2_DDR2_dq[33]
set_location_assignment PIN_K24 -to M2_DDR2_dq[34]
set_location_assignment PIN_J25 -to M2_DDR2_dq[35]
set_location_assignment PIN_R22 -to M2_DDR2_dq[36]
set_location_assignment PIN_P22 -to M2_DDR2_dq[37]
set_location_assignment PIN_M24 -to M2_DDR2_dq[38]
set_location_assignment PIN_J24 -to M2_DDR2_dq[39]
set_location_assignment PIN_J12 -to M2_DDR2_dq[4]
set_location_assignment PIN_G25 -to M2_DDR2_dq[40]
set_location_assignment PIN_C25 -to M2_DDR2_dq[41]
set_location_assignment PIN_A26 -to M2_DDR2_dq[42]
set_location_assignment PIN_C26 -to M2_DDR2_dq[43]
set_location_assignment PIN_G24 -to M2_DDR2_dq[44]
set_location_assignment PIN_F24 -to M2_DDR2_dq[45]
set_location_assignment PIN_D25 -to M2_DDR2_dq[46]
set_location_assignment PIN_D26 -to M2_DDR2_dq[47]
set_location_assignment PIN_F27 -to M2_DDR2_dq[48]
set_location_assignment PIN_G27 -to M2_DDR2_dq[49]
set_location_assignment PIN_J13 -to M2_DDR2_dq[5]
set_location_assignment PIN_F28 -to M2_DDR2_dq[50]
set_location_assignment PIN_H28 -to M2_DDR2_dq[51]
set_location_assignment PIN_H26 -to M2_DDR2_dq[52]
set_location_assignment PIN_J26 -to M2_DDR2_dq[53]
set_location_assignment PIN_E28 -to M2_DDR2_dq[54]
set_location_assignment PIN_G29 -to M2_DDR2_dq[55]
set_location_assignment PIN_C29 -to M2_DDR2_dq[56]
set_location_assignment PIN_A31 -to M2_DDR2_dq[57]
set_location_assignment PIN_C27 -to M2_DDR2_dq[58]
set_location_assignment PIN_D27 -to M2_DDR2_dq[59]
set_location_assignment PIN_G14 -to M2_DDR2_dq[6]
set_location_assignment PIN_A27 -to M2_DDR2_dq[60]
set_location_assignment PIN_A28 -to M2_DDR2_dq[61]
set_location_assignment PIN_B29 -to M2_DDR2_dq[62]
set_location_assignment PIN_B31 -to M2_DDR2_dq[63]
set_location_assignment PIN_D13 -to M2_DDR2_dq[7]
set_location_assignment PIN_P17 -to M2_DDR2_dq[8]
set_location_assignment PIN_N17 -to M2_DDR2_dq[9]
set_location_assignment PIN_E13 -to M2_DDR2_dqsn[0]
set_location_assignment PIN_J16 -to M2_DDR2_dqsn[1]
set_location_assignment PIN_C15 -to M2_DDR2_dqsn[2]
set_location_assignment PIN_F18 -to M2_DDR2_dqsn[3]
set_location_assignment PIN_K23 -to M2_DDR2_dqsn[4]
set_location_assignment PIN_E25 -to M2_DDR2_dqsn[5]
set_location_assignment PIN_D29 -to M2_DDR2_dqsn[6]
set_location_assignment PIN_B28 -to M2_DDR2_dqsn[7]
set_location_assignment PIN_F13 -to M2_DDR2_dqs[0]
set_location_assignment PIN_K16 -to M2_DDR2_dqs[1]
set_location_assignment PIN_D15 -to M2_DDR2_dqs[2]
set_location_assignment PIN_G18 -to M2_DDR2_dqs[3]
set_location_assignment PIN_L23 -to M2_DDR2_dqs[4]
set_location_assignment PIN_F25 -to M2_DDR2_dqs[5]
set_location_assignment PIN_E29 -to M2_DDR2_dqs[6]
set_location_assignment PIN_C28 -to M2_DDR2_dqs[7]
set_location_assignment PIN_D19 -to M2_DDR2_odt[0]
set_location_assignment PIN_A14 -to M2_DDR2_odt[1]
set_location_assignment PIN_J18 -to M2_DDR2_ras_n
set_location_assignment PIN_A18 -to M2_DDR2_SA[0]
set_location_assignment PIN_B19 -to M2_DDR2_SA[1]
set_location_assignment PIN_K15 -to M2_DDR2_SCL
set_location_assignment PIN_J15 -to M2_DDR2_SDA
set_location_assignment PIN_P18 -to M2_DDR2_we_n
set_location_assignment PIN_AW32 -to MAX_CONF_D[0]
set_location_assignment PIN_AG22 -to MAX_CONF_D[1]
set_location_assignment PIN_AV11 -to MAX_CONF_D[2]
set_location_assignment PIN_AG17 -to MAX_CONF_D[3]
set_location_assignment PIN_AP24 -to MAX_I2C_SCLK
set_location_assignment PIN_AN22 -to MAX_I2C_SDAT
set_location_assignment PIN_AC35 -to OSC_50_BANK2
set_location_assignment PIN_AV22 -to OSC_50_BANK3
set_location_assignment PIN_AV19 -to OSC_50_BANK4
set_location_assignment PIN_AC6 -to OSC_50_BANK5
set_location_assignment PIN_AB6 -to OSC_50_BANK6
set_location_assignment PIN_A19 -to OSC_50_BANK7
set_location_assignment PIN_K26 -to OTG_A[1]
set_location_assignment PIN_A29 -to OTG_A[10]
set_location_assignment PIN_J27 -to OTG_A[11]
set_location_assignment PIN_G26 -to OTG_A[12]
set_location_assignment PIN_F26 -to OTG_A[13]
set_location_assignment PIN_G28 -to OTG_A[14]
set_location_assignment PIN_B26 -to OTG_A[15]
set_location_assignment PIN_D17 -to OTG_A[16]
set_location_assignment PIN_F16 -to OTG_A[17]
set_location_assignment PIN_P25 -to OTG_A[2]
set_location_assignment PIN_N25 -to OTG_A[3]
set_location_assignment PIN_R24 -to OTG_A[4]
set_location_assignment PIN_P24 -to OTG_A[5]
set_location_assignment PIN_M25 -to OTG_A[6]
set_location_assignment PIN_L25 -to OTG_A[7]
set_location_assignment PIN_N23 -to OTG_A[8]
set_location_assignment PIN_K28 -to OTG_A[9]
set_location_assignment PIN_P19 -to OTG_CS_n
set_location_assignment PIN_AF16 -to OTG_D[0]
set_location_assignment PIN_AJ14 -to OTG_D[1]
set_location_assignment PIN_AG19 -to OTG_D[10]
set_location_assignment PIN_AM19 -to OTG_D[11]
set_location_assignment PIN_AN19 -to OTG_D[12]
set_location_assignment PIN_AV16 -to OTG_D[13]
set_location_assignment PIN_AT17 -to OTG_D[14]
set_location_assignment PIN_AV17 -to OTG_D[15]
set_location_assignment PIN_AU17 -to OTG_D[16]
set_location_assignment PIN_AW18 -to OTG_D[17]
set_location_assignment PIN_AT18 -to OTG_D[18]
set_location_assignment PIN_AU18 -to OTG_D[19]
set_location_assignment PIN_AD15 -to OTG_D[2]
set_location_assignment PIN_AR19 -to OTG_D[20]
set_location_assignment PIN_AW20 -to OTG_D[21]
set_location_assignment PIN_AW21 -to OTG_D[22]
set_location_assignment PIN_AF19 -to OTG_D[23]
set_location_assignment PIN_AE19 -to OTG_D[24]
set_location_assignment PIN_AE18 -to OTG_D[25]
set_location_assignment PIN_AD19 -to OTG_D[26]
set_location_assignment PIN_G13 -to OTG_D[27]
set_location_assignment PIN_M16 -to OTG_D[28]
set_location_assignment PIN_M27 -to OTG_D[29]
set_location_assignment PIN_AE15 -to OTG_D[3]
set_location_assignment PIN_K27 -to OTG_D[30]
set_location_assignment PIN_L26 -to OTG_D[31]
set_location_assignment PIN_AE16 -to OTG_D[4]
set_location_assignment PIN_AH14 -to OTG_D[5]
set_location_assignment PIN_AM13 -to OTG_D[6]
set_location_assignment PIN_AN15 -to OTG_D[7]
set_location_assignment PIN_AP15 -to OTG_D[8]
set_location_assignment PIN_AG18 -to OTG_D[9]
set_location_assignment PIN_AH20 -to OTG_DC_DACK
set_location_assignment PIN_AP21 -to OTG_DC_DREQ
set_location_assignment PIN_AT22 -to OTG_DC_IRQ
set_location_assignment PIN_AT21 -to OTG_HC_DACK
set_location_assignment PIN_AN21 -to OTG_HC_DREQ
set_location_assignment PIN_AJ20 -to OTG_HC_IRQ
set_location_assignment PIN_N19 -to OTG_OE_n
set_location_assignment PIN_AU22 -to OTG_RESET_n
set_location_assignment PIN_AR22 -to OTG_WE_n
set_location_assignment PIN_V30 -to PCIE_PREST_n
set_location_assignment PIN_AN38 -to PCIE_REFCLK_p
set_location_assignment PIN_AU38 -to PCIE_RX_p[0]
set_location_assignment PIN_AR38 -to PCIE_RX_p[1]
set_location_assignment PIN_AJ38 -to PCIE_RX_p[2]
set_location_assignment PIN_AG38 -to PCIE_RX_p[3]
set_location_assignment PIN_AE38 -to PCIE_RX_p[4]
set_location_assignment PIN_AC38 -to PCIE_RX_p[5]
set_location_assignment PIN_U38 -to PCIE_RX_p[6]
set_location_assignment PIN_R38 -to PCIE_RX_p[7]
set_location_assignment PIN_R31 -to PCIE_SMBCLK
set_location_assignment PIN_W33 -to PCIE_SMBDAT
set_location_assignment PIN_AT36 -to PCIE_TX_p[0]
set_location_assignment PIN_AP36 -to PCIE_TX_p[1]
set_location_assignment PIN_AH36 -to PCIE_TX_p[2]
set_location_assignment PIN_AF36 -to PCIE_TX_p[3]
set_location_assignment PIN_AD36 -to PCIE_TX_p[4]
set_location_assignment PIN_AB36 -to PCIE_TX_p[5]
set_location_assignment PIN_T36 -to PCIE_TX_p[6]
set_location_assignment PIN_P36 -to PCIE_TX_p[7]
set_location_assignment PIN_U35 -to PCIE_WAKE_n
set_location_assignment PIN_B22 -to PLL_CLKIN_p
set_location_assignment PIN_AU2 -to SATA_DEVICE_RX_p[0]
set_location_assignment PIN_AJ2 -to SATA_DEVICE_RX_p[1]
set_location_assignment PIN_AT4 -to SATA_DEVICE_TX_p[0]
set_location_assignment PIN_AH4 -to SATA_DEVICE_TX_p[1]
set_location_assignment PIN_AR2 -to SATA_HOST_RX_p[0]
set_location_assignment PIN_AG2 -to SATA_HOST_RX_p[1]
set_location_assignment PIN_AP4 -to SATA_HOST_TX_p[0]
set_location_assignment PIN_AF4 -to SATA_HOST_TX_p[1]
set_location_assignment PIN_AN2 -to SATA_REFCLK_p
set_location_assignment PIN_AT19 -to SD_CLK
set_location_assignment PIN_AV20 -to SD_CMD
set_location_assignment PIN_AR20 -to SD_DAT[0]
set_location_assignment PIN_AT20 -to SD_DAT[1]
set_location_assignment PIN_AU19 -to SD_DAT[2]
set_location_assignment PIN_AU20 -to SD_DAT[3]
set_location_assignment PIN_AH18 -to SD_WP_n
set_location_assignment PIN_L34 -to SEG0_D[0]
set_location_assignment PIN_M34 -to SEG0_D[1]
set_location_assignment PIN_M33 -to SEG0_D[2]
set_location_assignment PIN_H31 -to SEG0_D[3]
set_location_assignment PIN_J33 -to SEG0_D[4]
set_location_assignment PIN_L35 -to SEG0_D[5]
set_location_assignment PIN_K32 -to SEG0_D[6]
set_location_assignment PIN_AL34 -to SEG0_DP
set_location_assignment PIN_E31 -to SEG1_D[0]
set_location_assignment PIN_F31 -to SEG1_D[1]
set_location_assignment PIN_G31 -to SEG1_D[2]
set_location_assignment PIN_C34 -to SEG1_D[3]
set_location_assignment PIN_C33 -to SEG1_D[4]
set_location_assignment PIN_D33 -to SEG1_D[5]
set_location_assignment PIN_D34 -to SEG1_D[6]
set_location_assignment PIN_AL35 -to SEG1_DP
set_location_assignment PIN_J7 -to SLIDE_SW[0]
set_location_assignment PIN_K7 -to SLIDE_SW[1]
set_location_assignment PIN_AK6 -to SLIDE_SW[2]
set_location_assignment PIN_L7 -to SLIDE_SW[3]
set_location_assignment PIN_B23 -to SMA_CLKIN_p
set_location_assignment PIN_M20 -to SMA_CLKOUT_p
set_location_assignment PIN_W2 -to SMA_GXBCLK_p
set_location_assignment PIN_H35 -to SSRAM_ADV
set_location_assignment PIN_R27 -to SSRAM_BWA_n
set_location_assignment PIN_N31 -to SSRAM_BWB_n
set_location_assignment PIN_R28 -to SSRAM_CE_n
set_location_assignment PIN_N28 -to SSRAM_CKE_n
set_location_assignment PIN_M31 -to SSRAM_CLK
set_location_assignment PIN_H34 -to SSRAM_OE_n
set_location_assignment PIN_L31 -to SSRAM_WE_n
set_location_assignment PIN_AB13 -to SW[0]
set_location_assignment PIN_AB12 -to SW[1]
set_location_assignment PIN_AB11 -to SW[2]
set_location_assignment PIN_AB10 -to SW[3]
set_location_assignment PIN_AB9 -to SW[4]
set_location_assignment PIN_AC8 -to SW[5]
set_location_assignment PIN_AH6 -to SW[6]
set_location_assignment PIN_AG6 -to SW[7]
set_location_assignment PIN_AP19 -to TEMP_INT_n
set_location_assignment PIN_AN18 -to TEMP_SMCLK
set_location_assignment PIN_AP18 -to TEMP_SMDAT
set_location_assignment PIN_AN35 -to UART_CTS
set_location_assignment PIN_AH33 -to UART_RTS
set_location_assignment PIN_AH32 -to UART_RXD
set_location_assignment PIN_AN34 -to UART_TXD




set_location_assignment PIN_P26 -to termination_blk0~_rup_pad
set_location_assignment PIN_N26 -to termination_blk0~_rdn_pad


#============================================================
# I/O Standard
#============================================================
set_instance_assignment -name IO_STANDARD "3.0-V PCI-X" -to BUTTON[0]
set_instance_assignment -name IO_STANDARD "3.0-V PCI-X" -to BUTTON[1]
set_instance_assignment -name IO_STANDARD "3.0-V PCI-X" -to BUTTON[2]
set_instance_assignment -name IO_STANDARD "3.0-V PCI-X" -to BUTTON[3]
set_instance_assignment -name IO_STANDARD "2.5 V" -to CPU_RESET_n
set_instance_assignment -name IO_STANDARD "1.8 V" -to CSENSE_ADC_F0
set_instance_assignment -name IO_STANDARD "1.8 V" -to CSENSE_CS_n[0]
set_instance_assignment -name IO_STANDARD "1.8 V" -to CSENSE_CS_n[1]
set_instance_assignment -name IO_STANDARD "1.8 V" -to CSENSE_SCK
set_instance_assignment -name IO_STANDARD "1.8 V" -to CSENSE_SDI
set_instance_assignment -name IO_STANDARD "1.8 V" -to CSENSE_SDO
set_instance_assignment -name IO_STANDARD "2.5 V" -to EEP_SCL
set_instance_assignment -name IO_STANDARD "2.5 V" -to EEP_SDA
set_instance_assignment -name IO_STANDARD "1.8 V" -to ETH_INT_n[0]
set_instance_assignment -name IO_STANDARD "2.5 V" -to ETH_INT_n[1]
set_instance_assignment -name IO_STANDARD "2.5 V" -to ETH_INT_n[2]
set_instance_assignment -name IO_STANDARD "2.5 V" -to ETH_INT_n[3]
set_instance_assignment -name IO_STANDARD "2.5 V" -to ETH_MDC[0]
set_instance_assignment -name IO_STANDARD "2.5 V" -to ETH_MDC[1]
set_instance_assignment -name IO_STANDARD "2.5 V" -to ETH_MDC[2]
set_instance_assignment -name IO_STANDARD "2.5 V" -to ETH_MDC[3]
set_instance_assignment -name IO_STANDARD "2.5 V" -to ETH_MDIO[0]
set_instance_assignment -name IO_STANDARD "2.5 V" -to ETH_MDIO[1]
set_instance_assignment -name IO_STANDARD "2.5 V" -to ETH_MDIO[2]
set_instance_assignment -name IO_STANDARD "2.5 V" -to ETH_MDIO[3]
set_instance_assignment -name IO_STANDARD "2.5 V" -to ETH_RST_n
set_instance_assignment -name IO_STANDARD LVDS -to ETH_RX_p[0]
set_instance_assignment -name IO_STANDARD LVDS -to ETH_RX_p[1]
set_instance_assignment -name IO_STANDARD LVDS -to ETH_RX_p[2]
set_instance_assignment -name IO_STANDARD LVDS -to ETH_RX_p[3]
set_instance_assignment -name IO_STANDARD LVDS -to ETH_TX_p[0]
set_instance_assignment -name IO_STANDARD LVDS -to ETH_TX_p[1]
set_instance_assignment -name IO_STANDARD LVDS -to ETH_TX_p[2]
set_instance_assignment -name IO_STANDARD LVDS -to ETH_TX_p[3]
set_instance_assignment -name IO_STANDARD "3.0-V PCI-X" -to EXT_IO
set_instance_assignment -name IO_STANDARD "1.8 V" -to FAN_CTRL
set_instance_assignment -name IO_STANDARD "2.5 V" -to FLASH_ADV_n
set_instance_assignment -name IO_STANDARD "2.5 V" -to FLASH_CE_n
set_instance_assignment -name IO_STANDARD "2.5 V" -to FLASH_CLK
set_instance_assignment -name IO_STANDARD "2.5 V" -to FLASH_OE_n
set_instance_assignment -name IO_STANDARD "2.5 V" -to FLASH_RYBY_n
set_instance_assignment -name IO_STANDARD "2.5 V" -to FLASH_RESET_n
set_instance_assignment -name IO_STANDARD "2.5 V" -to FLASH_WE_n
set_instance_assignment -name IO_STANDARD "2.5 V" -to FSM_A[1]
set_instance_assignment -name IO_STANDARD "2.5 V" -to FSM_A[10]
set_instance_assignment -name IO_STANDARD "2.5 V" -to FSM_A[11]
set_instance_assignment -name IO_STANDARD "2.5 V" -to FSM_A[12]
set_instance_assignment -name IO_STANDARD "2.5 V" -to FSM_A[13]
set_instance_assignment -name IO_STANDARD "2.5 V" -to FSM_A[14]
set_instance_assignment -name IO_STANDARD "2.5 V" -to FSM_A[15]
set_instance_assignment -name IO_STANDARD "2.5 V" -to FSM_A[16]
set_instance_assignment -name IO_STANDARD "2.5 V" -to FSM_A[17]
set_instance_assignment -name IO_STANDARD "2.5 V" -to FSM_A[18]
set_instance_assignment -name IO_STANDARD "2.5 V" -to FSM_A[19]
set_instance_assignment -name IO_STANDARD "2.5 V" -to FSM_A[2]
set_instance_assignment -name IO_STANDARD "2.5 V" -to FSM_A[20]
set_instance_assignment -name IO_STANDARD "2.5 V" -to FSM_A[21]
set_instance_assignment -name IO_STANDARD "2.5 V" -to FSM_A[22]
set_instance_assignment -name IO_STANDARD "2.5 V" -to FSM_A[23]
set_instance_assignment -name IO_STANDARD "2.5 V" -to FSM_A[24]
set_instance_assignment -name IO_STANDARD "2.5 V" -to FSM_A[25]
set_instance_assignment -name IO_STANDARD "2.5 V" -to FSM_A[3]
set_instance_assignment -name IO_STANDARD "2.5 V" -to FSM_A[4]
set_instance_assignment -name IO_STANDARD "2.5 V" -to FSM_A[5]
set_instance_assignment -name IO_STANDARD "2.5 V" -to FSM_A[6]
set_instance_assignment -name IO_STANDARD "2.5 V" -to FSM_A[7]
set_instance_assignment -name IO_STANDARD "2.5 V" -to FSM_A[8]
set_instance_assignment -name IO_STANDARD "2.5 V" -to FSM_A[9]
set_instance_assignment -name IO_STANDARD "2.5 V" -to FSM_D[0]
set_instance_assignment -name IO_STANDARD "2.5 V" -to FSM_D[1]
set_instance_assignment -name IO_STANDARD "2.5 V" -to FSM_D[10]
set_instance_assignment -name IO_STANDARD "2.5 V" -to FSM_D[11]
set_instance_assignment -name IO_STANDARD "2.5 V" -to FSM_D[12]
set_instance_assignment -name IO_STANDARD "2.5 V" -to FSM_D[13]
set_instance_assignment -name IO_STANDARD "2.5 V" -to FSM_D[14]
set_instance_assignment -name IO_STANDARD "2.5 V" -to FSM_D[15]
set_instance_assignment -name IO_STANDARD "2.5 V" -to FSM_D[2]
set_instance_assignment -name IO_STANDARD "2.5 V" -to FSM_D[3]
set_instance_assignment -name IO_STANDARD "2.5 V" -to FSM_D[4]
set_instance_assignment -name IO_STANDARD "2.5 V" -to FSM_D[5]
set_instance_assignment -name IO_STANDARD "2.5 V" -to FSM_D[6]
set_instance_assignment -name IO_STANDARD "2.5 V" -to FSM_D[7]
set_instance_assignment -name IO_STANDARD "2.5 V" -to FSM_D[8]
set_instance_assignment -name IO_STANDARD "2.5 V" -to FSM_D[9]
set_instance_assignment -name IO_STANDARD "1.8 V" -to GCLKIN
set_instance_assignment -name IO_STANDARD "1.8 V" -to GCLKOUT_FPGA
set_instance_assignment -name IO_STANDARD "3.0-V PCI-X" -to GPIO0_D[0]
set_instance_assignment -name IO_STANDARD "3.0-V PCI-X" -to GPIO0_D[1]
set_instance_assignment -name IO_STANDARD "3.0-V PCI-X" -to GPIO0_D[10]
set_instance_assignment -name IO_STANDARD "3.0-V PCI-X" -to GPIO0_D[11]
set_instance_assignment -name IO_STANDARD "3.0-V PCI-X" -to GPIO0_D[12]
set_instance_assignment -name IO_STANDARD "3.0-V PCI-X" -to GPIO0_D[13]
set_instance_assignment -name IO_STANDARD "3.0-V PCI-X" -to GPIO0_D[14]
set_instance_assignment -name IO_STANDARD "3.0-V PCI-X" -to GPIO0_D[15]
set_instance_assignment -name IO_STANDARD "3.0-V PCI-X" -to GPIO0_D[16]
set_instance_assignment -name IO_STANDARD "3.0-V PCI-X" -to GPIO0_D[17]
set_instance_assignment -name IO_STANDARD "3.0-V PCI-X" -to GPIO0_D[18]
set_instance_assignment -name IO_STANDARD "3.0-V PCI-X" -to GPIO0_D[19]
set_instance_assignment -name IO_STANDARD "3.0-V PCI-X" -to GPIO0_D[2]
set_instance_assignment -name IO_STANDARD "3.0-V PCI-X" -to GPIO0_D[20]
set_instance_assignment -name IO_STANDARD "3.0-V PCI-X" -to GPIO0_D[21]
set_instance_assignment -name IO_STANDARD "3.0-V PCI-X" -to GPIO0_D[22]
set_instance_assignment -name IO_STANDARD "3.0-V PCI-X" -to GPIO0_D[23]
set_instance_assignment -name IO_STANDARD "3.0-V PCI-X" -to GPIO0_D[24]
set_instance_assignment -name IO_STANDARD "3.0-V PCI-X" -to GPIO0_D[25]
set_instance_assignment -name IO_STANDARD "3.0-V PCI-X" -to GPIO0_D[26]
set_instance_assignment -name IO_STANDARD "3.0-V PCI-X" -to GPIO0_D[27]
set_instance_assignment -name IO_STANDARD "3.0-V PCI-X" -to GPIO0_D[28]
set_instance_assignment -name IO_STANDARD "3.0-V PCI-X" -to GPIO0_D[29]
set_instance_assignment -name IO_STANDARD "3.0-V PCI-X" -to GPIO0_D[3]
set_instance_assignment -name IO_STANDARD "3.0-V PCI-X" -to GPIO0_D[30]
set_instance_assignment -name IO_STANDARD "3.0-V PCI-X" -to GPIO0_D[31]
set_instance_assignment -name IO_STANDARD "3.0-V PCI-X" -to GPIO0_D[32]
set_instance_assignment -name IO_STANDARD "3.0-V PCI-X" -to GPIO0_D[33]
set_instance_assignment -name IO_STANDARD "3.0-V PCI-X" -to GPIO0_D[34]
set_instance_assignment -name IO_STANDARD "3.0-V PCI-X" -to GPIO0_D[35]
set_instance_assignment -name IO_STANDARD "3.0-V PCI-X" -to GPIO0_D[4]
set_instance_assignment -name IO_STANDARD "3.0-V PCI-X" -to GPIO0_D[5]
set_instance_assignment -name IO_STANDARD "3.0-V PCI-X" -to GPIO0_D[6]
set_instance_assignment -name IO_STANDARD "3.0-V PCI-X" -to GPIO0_D[7]
set_instance_assignment -name IO_STANDARD "3.0-V PCI-X" -to GPIO0_D[8]
set_instance_assignment -name IO_STANDARD "3.0-V PCI-X" -to GPIO0_D[9]
set_instance_assignment -name IO_STANDARD "3.0-V PCI-X" -to GPIO1_D[0]
set_instance_assignment -name IO_STANDARD "3.0-V PCI-X" -to GPIO1_D[1]
set_instance_assignment -name IO_STANDARD "3.0-V PCI-X" -to GPIO1_D[10]
set_instance_assignment -name IO_STANDARD "3.0-V PCI-X" -to GPIO1_D[11]
set_instance_assignment -name IO_STANDARD "3.0-V PCI-X" -to GPIO1_D[12]
set_instance_assignment -name IO_STANDARD "3.0-V PCI-X" -to GPIO1_D[13]
set_instance_assignment -name IO_STANDARD "3.0-V PCI-X" -to GPIO1_D[14]
set_instance_assignment -name IO_STANDARD "3.0-V PCI-X" -to GPIO1_D[15]
set_instance_assignment -name IO_STANDARD "3.0-V PCI-X" -to GPIO1_D[16]
set_instance_assignment -name IO_STANDARD "3.0-V PCI-X" -to GPIO1_D[17]
set_instance_assignment -name IO_STANDARD "3.0-V PCI-X" -to GPIO1_D[18]
set_instance_assignment -name IO_STANDARD "3.0-V PCI-X" -to GPIO1_D[19]
set_instance_assignment -name IO_STANDARD "3.0-V PCI-X" -to GPIO1_D[2]
set_instance_assignment -name IO_STANDARD "3.0-V PCI-X" -to GPIO1_D[20]
set_instance_assignment -name IO_STANDARD "3.0-V PCI-X" -to GPIO1_D[21]
set_instance_assignment -name IO_STANDARD "3.0-V PCI-X" -to GPIO1_D[22]
set_instance_assignment -name IO_STANDARD "3.0-V PCI-X" -to GPIO1_D[23]
set_instance_assignment -name IO_STANDARD "3.0-V PCI-X" -to GPIO1_D[24]
set_instance_assignment -name IO_STANDARD "3.0-V PCI-X" -to GPIO1_D[25]
set_instance_assignment -name IO_STANDARD "3.0-V PCI-X" -to GPIO1_D[26]
set_instance_assignment -name IO_STANDARD "3.0-V PCI-X" -to GPIO1_D[27]
set_instance_assignment -name IO_STANDARD "3.0-V PCI-X" -to GPIO1_D[28]
set_instance_assignment -name IO_STANDARD "3.0-V PCI-X" -to GPIO1_D[29]
set_instance_assignment -name IO_STANDARD "3.0-V PCI-X" -to GPIO1_D[3]
set_instance_assignment -name IO_STANDARD "3.0-V PCI-X" -to GPIO1_D[30]
set_instance_assignment -name IO_STANDARD "3.0-V PCI-X" -to GPIO1_D[31]
set_instance_assignment -name IO_STANDARD "3.0-V PCI-X" -to GPIO1_D[32]
set_instance_assignment -name IO_STANDARD "3.0-V PCI-X" -to GPIO1_D[33]
set_instance_assignment -name IO_STANDARD "3.0-V PCI-X" -to GPIO1_D[34]
set_instance_assignment -name IO_STANDARD "3.0-V PCI-X" -to GPIO1_D[35]
set_instance_assignment -name IO_STANDARD "3.0-V PCI-X" -to GPIO1_D[4]
set_instance_assignment -name IO_STANDARD "3.0-V PCI-X" -to GPIO1_D[5]
set_instance_assignment -name IO_STANDARD "3.0-V PCI-X" -to GPIO1_D[6]
set_instance_assignment -name IO_STANDARD "3.0-V PCI-X" -to GPIO1_D[7]
set_instance_assignment -name IO_STANDARD "3.0-V PCI-X" -to GPIO1_D[8]
set_instance_assignment -name IO_STANDARD "3.0-V PCI-X" -to GPIO1_D[9]
set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMA_CLKIN_N1
set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMA_CLKIN_N2
set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMA_CLKIN_P1
set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMA_CLKIN_P2
set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMA_CLKIN0
set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMA_CLKOUT_n2
set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMA_CLKOUT_p2
set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMA_D[0]
set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMA_D[1]
set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMA_D[2]
set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMA_D[3]
set_instance_assignment -name IO_STANDARD "1.4-V PCML" -to HSMA_GXB_RX_p[0]
set_instance_assignment -name IO_STANDARD "1.4-V PCML" -to HSMA_GXB_RX_p[1]
set_instance_assignment -name IO_STANDARD "1.4-V PCML" -to HSMA_GXB_RX_p[2]
set_instance_assignment -name IO_STANDARD "1.4-V PCML" -to HSMA_GXB_RX_p[3]
set_instance_assignment -name IO_STANDARD "1.4-V PCML" -to HSMA_GXB_TX_p[0]
set_instance_assignment -name IO_STANDARD "1.4-V PCML" -to HSMA_GXB_TX_p[1]
set_instance_assignment -name IO_STANDARD "1.4-V PCML" -to HSMA_GXB_TX_p[2]
set_instance_assignment -name IO_STANDARD "1.4-V PCML" -to HSMA_GXB_TX_p[3]
set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMA_OUT_n1
set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMA_OUT_p1
set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMA_OUT0
set_instance_assignment -name IO_STANDARD LVDS -to HSMA_REFCLK_p
set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMA_RX_n[0]
set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMA_RX_n[1]
set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMA_RX_n[10]
set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMA_RX_n[11]
set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMA_RX_n[12]
set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMA_RX_n[13]
set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMA_RX_n[14]
set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMA_RX_n[15]
set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMA_RX_n[16]
set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMA_RX_n[2]
set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMA_RX_n[3]
set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMA_RX_n[4]
set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMA_RX_n[5]
set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMA_RX_n[6]
set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMA_RX_n[7]
set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMA_RX_n[8]
set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMA_RX_n[9]
set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMA_RX_p[0]
set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMA_RX_p[1]
set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMA_RX_p[10]
set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMA_RX_p[11]
set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMA_RX_p[12]
set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMA_RX_p[13]
set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMA_RX_p[14]
set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMA_RX_p[15]
set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMA_RX_p[16]
set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMA_RX_p[2]
set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMA_RX_p[3]
set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMA_RX_p[4]
set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMA_RX_p[5]
set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMA_RX_p[6]
set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMA_RX_p[7]
set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMA_RX_p[8]
set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMA_RX_p[9]
set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMA_TX_n[0]
set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMA_TX_n[1]
set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMA_TX_n[10]
set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMA_TX_n[11]
set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMA_TX_n[12]
set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMA_TX_n[13]
set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMA_TX_n[14]
set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMA_TX_n[15]
set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMA_TX_n[16]
set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMA_TX_n[2]
set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMA_TX_n[3]
set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMA_TX_n[4]
set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMA_TX_n[5]
set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMA_TX_n[6]
set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMA_TX_n[7]
set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMA_TX_n[8]
set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMA_TX_n[9]
set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMA_TX_p[0]
set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMA_TX_p[1]
set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMA_TX_p[10]
set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMA_TX_p[11]
set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMA_TX_p[12]
set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMA_TX_p[13]
set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMA_TX_p[14]
set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMA_TX_p[15]
set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMA_TX_p[16]
set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMA_TX_p[2]
set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMA_TX_p[3]
set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMA_TX_p[4]
set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMA_TX_p[5]
set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMA_TX_p[6]
set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMA_TX_p[7]
set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMA_TX_p[8]
set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMA_TX_p[9]
set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMB_CLKIN_N1
set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMB_CLKIN_N2
set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMB_CLKIN_P1
set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMB_CLKIN_P2
set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMB_CLKIN0
set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMB_CLKOUT_n2
set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMB_CLKOUT_p2
set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMB_D[0]
set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMB_D[1]
set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMB_D[2]
set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMB_D[3]
set_instance_assignment -name IO_STANDARD "1.4-V PCML" -to HSMB_GXB_RX_p[0]
set_instance_assignment -name IO_STANDARD "1.4-V PCML" -to HSMB_GXB_RX_p[1]
set_instance_assignment -name IO_STANDARD "1.4-V PCML" -to HSMB_GXB_RX_p[2]
set_instance_assignment -name IO_STANDARD "1.4-V PCML" -to HSMB_GXB_RX_p[3]
set_instance_assignment -name IO_STANDARD "1.4-V PCML" -to HSMB_GXB_RX_p[4]
set_instance_assignment -name IO_STANDARD "1.4-V PCML" -to HSMB_GXB_RX_p[5]
set_instance_assignment -name IO_STANDARD "1.4-V PCML" -to HSMB_GXB_RX_p[6]
set_instance_assignment -name IO_STANDARD "1.4-V PCML" -to HSMB_GXB_RX_p[7]
set_instance_assignment -name IO_STANDARD "1.4-V PCML" -to HSMB_GXB_TX_p[0]
set_instance_assignment -name IO_STANDARD "1.4-V PCML" -to HSMB_GXB_TX_p[1]
set_instance_assignment -name IO_STANDARD "1.4-V PCML" -to HSMB_GXB_TX_p[2]
set_instance_assignment -name IO_STANDARD "1.4-V PCML" -to HSMB_GXB_TX_p[3]
set_instance_assignment -name IO_STANDARD "1.4-V PCML" -to HSMB_GXB_TX_p[4]
set_instance_assignment -name IO_STANDARD "1.4-V PCML" -to HSMB_GXB_TX_p[5]
set_instance_assignment -name IO_STANDARD "1.4-V PCML" -to HSMB_GXB_TX_p[6]
set_instance_assignment -name IO_STANDARD "1.4-V PCML" -to HSMB_GXB_TX_p[7]
set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMB_OUT_n1
set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMB_OUT_p1
set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMB_OUT0
set_instance_assignment -name IO_STANDARD LVDS -to HSMB_REFCLK_p
set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMB_RX_n[0]
set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMB_RX_n[1]
set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMB_RX_n[10]
set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMB_RX_n[11]
set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMB_RX_n[12]
set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMB_RX_n[13]
set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMB_RX_n[14]
set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMB_RX_n[15]
set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMB_RX_n[16]
set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMB_RX_n[2]
set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMB_RX_n[3]
set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMB_RX_n[4]
set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMB_RX_n[5]
set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMB_RX_n[6]
set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMB_RX_n[7]
set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMB_RX_n[8]
set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMB_RX_n[9]
set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMB_RX_p[0]
set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMB_RX_p[1]
set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMB_RX_p[10]
set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMB_RX_p[11]
set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMB_RX_p[12]
set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMB_RX_p[13]
set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMB_RX_p[14]
set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMB_RX_p[15]
set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMB_RX_p[16]
set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMB_RX_p[2]
set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMB_RX_p[3]
set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMB_RX_p[4]
set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMB_RX_p[5]
set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMB_RX_p[6]
set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMB_RX_p[7]
set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMB_RX_p[8]
set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMB_RX_p[9]
set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMB_TX_n[0]
set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMB_TX_n[1]
set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMB_TX_n[10]
set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMB_TX_n[11]
set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMB_TX_n[12]
set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMB_TX_n[13]
set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMB_TX_n[14]
set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMB_TX_n[15]
set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMB_TX_n[16]
set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMB_TX_n[2]
set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMB_TX_n[3]
set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMB_TX_n[4]
set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMB_TX_n[5]
set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMB_TX_n[6]
set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMB_TX_n[7]
set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMB_TX_n[8]
set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMB_TX_n[9]
set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMB_TX_p[0]
set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMB_TX_p[1]
set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMB_TX_p[10]
set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMB_TX_p[11]
set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMB_TX_p[12]
set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMB_TX_p[13]
set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMB_TX_p[14]
set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMB_TX_p[15]
set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMB_TX_p[16]
set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMB_TX_p[2]
set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMB_TX_p[3]
set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMB_TX_p[4]
set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMB_TX_p[5]
set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMB_TX_p[6]
set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMB_TX_p[7]
set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMB_TX_p[8]
set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMB_TX_p[9]
set_instance_assignment -name IO_STANDARD "1.8 V" -to HSMC_SCL
set_instance_assignment -name IO_STANDARD "1.8 V" -to HSMC_SDA
set_instance_assignment -name IO_STANDARD "2.5 V" -to LED[0]
set_instance_assignment -name IO_STANDARD "2.5 V" -to LED[1]
set_instance_assignment -name IO_STANDARD "2.5 V" -to LED[2]
set_instance_assignment -name IO_STANDARD "2.5 V" -to LED[3]
set_instance_assignment -name IO_STANDARD "2.5 V" -to LED[4]
set_instance_assignment -name IO_STANDARD "2.5 V" -to LED[5]
set_instance_assignment -name IO_STANDARD "2.5 V" -to LED[6]
set_instance_assignment -name IO_STANDARD "2.5 V" -to LED[7]
set_instance_assignment -name IO_STANDARD "SSTL-18 CLASS I" -to M1_DDR2_addr[15]
set_instance_assignment -name IO_STANDARD "1.8 V" -to M1_DDR2_SA[0]
set_instance_assignment -name IO_STANDARD "1.8 V" -to M1_DDR2_SA[1]
set_instance_assignment -name IO_STANDARD "1.8 V" -to M1_DDR2_SCL
set_instance_assignment -name IO_STANDARD "1.8 V" -to M1_DDR2_SDA
set_instance_assignment -name IO_STANDARD "SSTL-18 CLASS I" -to M2_DDR2_addr[15]
set_instance_assignment -name IO_STANDARD "1.8 V" -to M2_DDR2_SA[0]
set_instance_assignment -name IO_STANDARD "1.8 V" -to M2_DDR2_SA[1]
set_instance_assignment -name IO_STANDARD "1.8 V" -to M2_DDR2_SCL
set_instance_assignment -name IO_STANDARD "1.8 V" -to M2_DDR2_SDA
set_instance_assignment -name IO_STANDARD "1.8 V" -to MAX_CONF_D[0]
set_instance_assignment -name IO_STANDARD "1.8 V" -to MAX_CONF_D[1]
set_instance_assignment -name IO_STANDARD "1.8 V" -to MAX_CONF_D[2]
set_instance_assignment -name IO_STANDARD "1.8 V" -to MAX_CONF_D[3]
set_instance_assignment -name IO_STANDARD "1.8 V" -to MAX_I2C_SCLK
set_instance_assignment -name IO_STANDARD "1.8 V" -to MAX_I2C_SDAT
set_instance_assignment -name IO_STANDARD "2.5 V" -to OSC_50_BANK2
set_instance_assignment -name IO_STANDARD "1.8 V" -to OSC_50_BANK3
set_instance_assignment -name IO_STANDARD "1.8 V" -to OSC_50_BANK4
set_instance_assignment -name IO_STANDARD "3.0-V PCI-X" -to OSC_50_BANK5
set_instance_assignment -name IO_STANDARD "2.5 V" -to OSC_50_BANK6
set_instance_assignment -name IO_STANDARD "1.8 V" -to OSC_50_BANK7
set_instance_assignment -name IO_STANDARD "1.8 V" -to OTG_A[1]
set_instance_assignment -name IO_STANDARD "1.8 V" -to OTG_A[10]
set_instance_assignment -name IO_STANDARD "1.8 V" -to OTG_A[11]
set_instance_assignment -name IO_STANDARD "1.8 V" -to OTG_A[12]
set_instance_assignment -name IO_STANDARD "1.8 V" -to OTG_A[13]
set_instance_assignment -name IO_STANDARD "1.8 V" -to OTG_A[14]
set_instance_assignment -name IO_STANDARD "1.8 V" -to OTG_A[15]
set_instance_assignment -name IO_STANDARD "1.8 V" -to OTG_A[16]
set_instance_assignment -name IO_STANDARD "1.8 V" -to OTG_A[17]
set_instance_assignment -name IO_STANDARD "1.8 V" -to OTG_A[2]
set_instance_assignment -name IO_STANDARD "1.8 V" -to OTG_A[3]
set_instance_assignment -name IO_STANDARD "1.8 V" -to OTG_A[4]
set_instance_assignment -name IO_STANDARD "1.8 V" -to OTG_A[5]
set_instance_assignment -name IO_STANDARD "1.8 V" -to OTG_A[6]
set_instance_assignment -name IO_STANDARD "1.8 V" -to OTG_A[7]
set_instance_assignment -name IO_STANDARD "1.8 V" -to OTG_A[8]
set_instance_assignment -name IO_STANDARD "1.8 V" -to OTG_A[9]
set_instance_assignment -name IO_STANDARD "1.8 V" -to OTG_CS_n
set_instance_assignment -name IO_STANDARD "1.8 V" -to OTG_D[0]
set_instance_assignment -name IO_STANDARD "1.8 V" -to OTG_D[1]
set_instance_assignment -name IO_STANDARD "1.8 V" -to OTG_D[10]
set_instance_assignment -name IO_STANDARD "1.8 V" -to OTG_D[11]
set_instance_assignment -name IO_STANDARD "1.8 V" -to OTG_D[12]
set_instance_assignment -name IO_STANDARD "1.8 V" -to OTG_D[13]
set_instance_assignment -name IO_STANDARD "1.8 V" -to OTG_D[14]
set_instance_assignment -name IO_STANDARD "1.8 V" -to OTG_D[15]
set_instance_assignment -name IO_STANDARD "1.8 V" -to OTG_D[16]
set_instance_assignment -name IO_STANDARD "1.8 V" -to OTG_D[17]
set_instance_assignment -name IO_STANDARD "1.8 V" -to OTG_D[18]
set_instance_assignment -name IO_STANDARD "1.8 V" -to OTG_D[19]
set_instance_assignment -name IO_STANDARD "1.8 V" -to OTG_D[2]
set_instance_assignment -name IO_STANDARD "1.8 V" -to OTG_D[20]
set_instance_assignment -name IO_STANDARD "1.8 V" -to OTG_D[21]
set_instance_assignment -name IO_STANDARD "1.8 V" -to OTG_D[22]
set_instance_assignment -name IO_STANDARD "1.8 V" -to OTG_D[23]
set_instance_assignment -name IO_STANDARD "1.8 V" -to OTG_D[24]
set_instance_assignment -name IO_STANDARD "1.8 V" -to OTG_D[25]
set_instance_assignment -name IO_STANDARD "1.8 V" -to OTG_D[26]
set_instance_assignment -name IO_STANDARD "1.8 V" -to OTG_D[27]
set_instance_assignment -name IO_STANDARD "1.8 V" -to OTG_D[28]
set_instance_assignment -name IO_STANDARD "1.8 V" -to OTG_D[29]
set_instance_assignment -name IO_STANDARD "1.8 V" -to OTG_D[3]
set_instance_assignment -name IO_STANDARD "1.8 V" -to OTG_D[30]
set_instance_assignment -name IO_STANDARD "1.8 V" -to OTG_D[31]
set_instance_assignment -name IO_STANDARD "1.8 V" -to OTG_D[4]
set_instance_assignment -name IO_STANDARD "1.8 V" -to OTG_D[5]
set_instance_assignment -name IO_STANDARD "1.8 V" -to OTG_D[6]
set_instance_assignment -name IO_STANDARD "1.8 V" -to OTG_D[7]
set_instance_assignment -name IO_STANDARD "1.8 V" -to OTG_D[8]
set_instance_assignment -name IO_STANDARD "1.8 V" -to OTG_D[9]
set_instance_assignment -name IO_STANDARD "1.8 V" -to OTG_DC_DACK
set_instance_assignment -name IO_STANDARD "1.8 V" -to OTG_DC_DREQ
set_instance_assignment -name IO_STANDARD "1.8 V" -to OTG_DC_IRQ
set_instance_assignment -name IO_STANDARD "1.8 V" -to OTG_HC_DACK
set_instance_assignment -name IO_STANDARD "1.8 V" -to OTG_HC_DREQ
set_instance_assignment -name IO_STANDARD "1.8 V" -to OTG_HC_IRQ
set_instance_assignment -name IO_STANDARD "1.8 V" -to OTG_OE_n
set_instance_assignment -name IO_STANDARD "1.8 V" -to OTG_RESET_n
set_instance_assignment -name IO_STANDARD "1.8 V" -to OTG_WE_n
set_instance_assignment -name IO_STANDARD "2.5 V" -to PCIE_PREST_n
set_instance_assignment -name IO_STANDARD HCSL -to PCIE_REFCLK_p
set_instance_assignment -name IO_STANDARD "1.4-V PCML" -to PCIE_RX_p[0]
set_instance_assignment -name IO_STANDARD "1.4-V PCML" -to PCIE_RX_p[1]
set_instance_assignment -name IO_STANDARD "1.4-V PCML" -to PCIE_RX_p[2]
set_instance_assignment -name IO_STANDARD "1.4-V PCML" -to PCIE_RX_p[3]
set_instance_assignment -name IO_STANDARD "1.4-V PCML" -to PCIE_RX_p[4]
set_instance_assignment -name IO_STANDARD "1.4-V PCML" -to PCIE_RX_p[5]
set_instance_assignment -name IO_STANDARD "1.4-V PCML" -to PCIE_RX_p[6]
set_instance_assignment -name IO_STANDARD "1.4-V PCML" -to PCIE_RX_p[7]
set_instance_assignment -name IO_STANDARD "2.5 V" -to PCIE_SMBCLK
set_instance_assignment -name IO_STANDARD "2.5 V" -to PCIE_SMBDAT
set_instance_assignment -name IO_STANDARD "1.4-V PCML" -to PCIE_TX_p[0]
set_instance_assignment -name IO_STANDARD "1.4-V PCML" -to PCIE_TX_p[1]
set_instance_assignment -name IO_STANDARD "1.4-V PCML" -to PCIE_TX_p[2]
set_instance_assignment -name IO_STANDARD "1.4-V PCML" -to PCIE_TX_p[3]
set_instance_assignment -name IO_STANDARD "1.4-V PCML" -to PCIE_TX_p[4]
set_instance_assignment -name IO_STANDARD "1.4-V PCML" -to PCIE_TX_p[5]
set_instance_assignment -name IO_STANDARD "1.4-V PCML" -to PCIE_TX_p[6]
set_instance_assignment -name IO_STANDARD "1.4-V PCML" -to PCIE_TX_p[7]
set_instance_assignment -name IO_STANDARD "2.5 V" -to PCIE_WAKE_n
set_instance_assignment -name IO_STANDARD LVDS -to PLL_CLKIN_p
set_instance_assignment -name IO_STANDARD "1.4-V PCML" -to SATA_DEVICE_RX_p[0]
set_instance_assignment -name IO_STANDARD "1.4-V PCML" -to SATA_DEVICE_RX_p[1]
set_instance_assignment -name IO_STANDARD "1.4-V PCML" -to SATA_DEVICE_TX_p[0]
set_instance_assignment -name IO_STANDARD "1.4-V PCML" -to SATA_DEVICE_TX_p[1]
set_instance_assignment -name IO_STANDARD "1.4-V PCML" -to SATA_HOST_RX_p[0]
set_instance_assignment -name IO_STANDARD "1.4-V PCML" -to SATA_HOST_RX_p[1]
set_instance_assignment -name IO_STANDARD "1.4-V PCML" -to SATA_HOST_TX_p[0]
set_instance_assignment -name IO_STANDARD "1.4-V PCML" -to SATA_HOST_TX_p[1]
set_instance_assignment -name IO_STANDARD LVDS -to SATA_REFCLK_p
set_instance_assignment -name IO_STANDARD "1.8 V" -to SD_CLK
set_instance_assignment -name IO_STANDARD "1.8 V" -to SD_CMD
set_instance_assignment -name IO_STANDARD "1.8 V" -to SD_DAT[0]
set_instance_assignment -name IO_STANDARD "1.8 V" -to SD_DAT[1]
set_instance_assignment -name IO_STANDARD "1.8 V" -to SD_DAT[2]
set_instance_assignment -name IO_STANDARD "1.8 V" -to SD_DAT[3]
set_instance_assignment -name IO_STANDARD "1.8 V" -to SD_WP_n
set_instance_assignment -name IO_STANDARD "2.5 V" -to SEG0_D[0]
set_instance_assignment -name IO_STANDARD "2.5 V" -to SEG0_D[1]
set_instance_assignment -name IO_STANDARD "2.5 V" -to SEG0_D[2]
set_instance_assignment -name IO_STANDARD "2.5 V" -to SEG0_D[3]
set_instance_assignment -name IO_STANDARD "2.5 V" -to SEG0_D[4]
set_instance_assignment -name IO_STANDARD "2.5 V" -to SEG0_D[5]
set_instance_assignment -name IO_STANDARD "2.5 V" -to SEG0_D[6]
set_instance_assignment -name IO_STANDARD "2.5 V" -to SEG0_DP
set_instance_assignment -name IO_STANDARD "2.5 V" -to SEG1_D[0]
set_instance_assignment -name IO_STANDARD "2.5 V" -to SEG1_D[1]
set_instance_assignment -name IO_STANDARD "2.5 V" -to SEG1_D[2]
set_instance_assignment -name IO_STANDARD "2.5 V" -to SEG1_D[3]
set_instance_assignment -name IO_STANDARD "2.5 V" -to SEG1_D[4]
set_instance_assignment -name IO_STANDARD "2.5 V" -to SEG1_D[5]
set_instance_assignment -name IO_STANDARD "2.5 V" -to SEG1_D[6]
set_instance_assignment -name IO_STANDARD "2.5 V" -to SEG1_DP
set_instance_assignment -name IO_STANDARD "2.5 V" -to SLIDE_SW[0]
set_instance_assignment -name IO_STANDARD "2.5 V" -to SLIDE_SW[1]
set_instance_assignment -name IO_STANDARD "3.0-V PCI-X" -to SLIDE_SW[2]
set_instance_assignment -name IO_STANDARD "2.5 V" -to SLIDE_SW[3]
set_instance_assignment -name IO_STANDARD LVDS -to SMA_CLKIN_p
set_instance_assignment -name IO_STANDARD LVDS -to SMA_CLKOUT_p
set_instance_assignment -name IO_STANDARD LVDS -to SMA_GXBCLK_p
set_instance_assignment -name IO_STANDARD "2.5 V" -to SSRAM_ADV
set_instance_assignment -name IO_STANDARD "2.5 V" -to SSRAM_BWA_n
set_instance_assignment -name IO_STANDARD "2.5 V" -to SSRAM_BWB_n
set_instance_assignment -name IO_STANDARD "2.5 V" -to SSRAM_CE_n
set_instance_assignment -name IO_STANDARD "2.5 V" -to SSRAM_CKE_n
set_instance_assignment -name IO_STANDARD "2.5 V" -to SSRAM_CLK
set_instance_assignment -name IO_STANDARD "2.5 V" -to SSRAM_OE_n
set_instance_assignment -name IO_STANDARD "2.5 V" -to SSRAM_WE_n
set_instance_assignment -name IO_STANDARD "3.0-V PCI-X" -to SW[0]
set_instance_assignment -name IO_STANDARD "3.0-V PCI-X" -to SW[1]
set_instance_assignment -name IO_STANDARD "3.0-V PCI-X" -to SW[2]
set_instance_assignment -name IO_STANDARD "3.0-V PCI-X" -to SW[3]
set_instance_assignment -name IO_STANDARD "3.0-V PCI-X" -to SW[4]
set_instance_assignment -name IO_STANDARD "3.0-V PCI-X" -to SW[5]
set_instance_assignment -name IO_STANDARD "3.0-V PCI-X" -to SW[6]
set_instance_assignment -name IO_STANDARD "3.0-V PCI-X" -to SW[7]
set_instance_assignment -name IO_STANDARD "1.8 V" -to TEMP_INT_n
set_instance_assignment -name IO_STANDARD "1.8 V" -to TEMP_SMCLK
set_instance_assignment -name IO_STANDARD "1.8 V" -to TEMP_SMDAT
set_instance_assignment -name IO_STANDARD "2.5 V" -to UART_CTS
set_instance_assignment -name IO_STANDARD "2.5 V" -to UART_RTS
set_instance_assignment -name IO_STANDARD "2.5 V" -to UART_RXD
set_instance_assignment -name IO_STANDARD "2.5 V" -to UART_TXD





#============================================================
# End of pin assignments by Terasic System Builder
#============================================================


set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
set_global_assignment -name LL_ROOT_REGION ON -section_id "Root Region"
set_global_assignment -name LL_MEMBER_STATE LOCKED -section_id "Root Region"
set_global_assignment -name MISC_FILE "C:/Documents and Settings/user/®à­±/DE4_GOLDEN_TOP/DE4_GOLDEN_TOP/DE4_GOLDEN_TOP.dpf"
set_global_assignment -name SEARCH_PATH ddr2

#============================================================
# DDR2 DIM1 setting
#============================================================

set_instance_assignment -name IO_STANDARD "SSTL-18 CLASS I" -to M1_DDR2_odt[0]
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to M1_DDR2_odt[0]
set_instance_assignment -name IO_STANDARD "SSTL-18 CLASS I" -to M1_DDR2_odt[1]
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to M1_DDR2_odt[1]
set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.8-V SSTL CLASS I" -to M1_DDR2_clk[0]
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to M1_DDR2_clk[0]
set_instance_assignment -name TREAT_BIDIR_AS_OUTPUT ON -to M1_DDR2_clk[1]
set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.8-V SSTL CLASS I" -to M1_DDR2_clk[1]
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to M1_DDR2_clk[1]
set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.8-V SSTL CLASS I" -to M1_DDR2_clk_n[0]
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to M1_DDR2_clk_n[0]
set_instance_assignment -name TREAT_BIDIR_AS_OUTPUT ON -to M1_DDR2_clk_n[1]
set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.8-V SSTL CLASS I" -to M1_DDR2_clk_n[1]
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to M1_DDR2_clk_n[1]
set_instance_assignment -name IO_STANDARD "SSTL-18 CLASS I" -to M1_DDR2_cs_n[0]
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to M1_DDR2_cs_n[0]
set_instance_assignment -name IO_STANDARD "SSTL-18 CLASS I" -to M1_DDR2_cs_n[1]
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to M1_DDR2_cs_n[1]
set_instance_assignment -name IO_STANDARD "SSTL-18 CLASS I" -to M1_DDR2_cke[0]
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to M1_DDR2_cke[0]
set_instance_assignment -name IO_STANDARD "SSTL-18 CLASS I" -to M1_DDR2_cke[1]
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to M1_DDR2_cke[1]
set_instance_assignment -name IO_STANDARD "SSTL-18 CLASS I" -to M1_DDR2_addr[0]
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to M1_DDR2_addr[0]
set_instance_assignment -name IO_STANDARD "SSTL-18 CLASS I" -to M1_DDR2_addr[1]
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to M1_DDR2_addr[1]
set_instance_assignment -name IO_STANDARD "SSTL-18 CLASS I" -to M1_DDR2_addr[2]
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to M1_DDR2_addr[2]
set_instance_assignment -name IO_STANDARD "SSTL-18 CLASS I" -to M1_DDR2_addr[3]
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to M1_DDR2_addr[3]
set_instance_assignment -name IO_STANDARD "SSTL-18 CLASS I" -to M1_DDR2_addr[4]
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to M1_DDR2_addr[4]
set_instance_assignment -name IO_STANDARD "SSTL-18 CLASS I" -to M1_DDR2_addr[5]
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to M1_DDR2_addr[5]
set_instance_assignment -name IO_STANDARD "SSTL-18 CLASS I" -to M1_DDR2_addr[6]
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to M1_DDR2_addr[6]
set_instance_assignment -name IO_STANDARD "SSTL-18 CLASS I" -to M1_DDR2_addr[7]
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to M1_DDR2_addr[7]
set_instance_assignment -name IO_STANDARD "SSTL-18 CLASS I" -to M1_DDR2_addr[8]
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to M1_DDR2_addr[8]
set_instance_assignment -name IO_STANDARD "SSTL-18 CLASS I" -to M1_DDR2_addr[9]
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to M1_DDR2_addr[9]
set_instance_assignment -name IO_STANDARD "SSTL-18 CLASS I" -to M1_DDR2_addr[10]
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to M1_DDR2_addr[10]
set_instance_assignment -name IO_STANDARD "SSTL-18 CLASS I" -to M1_DDR2_addr[11]
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to M1_DDR2_addr[11]
set_instance_assignment -name IO_STANDARD "SSTL-18 CLASS I" -to M1_DDR2_addr[12]
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to M1_DDR2_addr[12]
set_instance_assignment -name IO_STANDARD "SSTL-18 CLASS I" -to M1_DDR2_addr[13]
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to M1_DDR2_addr[13]
set_instance_assignment -name IO_STANDARD "SSTL-18 CLASS I" -to M1_DDR2_addr[14]
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to M1_DDR2_addr[14]
set_instance_assignment -name IO_STANDARD "SSTL-18 CLASS I" -to M1_DDR2_ba[0]
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to M1_DDR2_ba[0]
set_instance_assignment -name IO_STANDARD "SSTL-18 CLASS I" -to M1_DDR2_ba[1]
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to M1_DDR2_ba[1]
set_instance_assignment -name IO_STANDARD "SSTL-18 CLASS I" -to M1_DDR2_ba[2]
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to M1_DDR2_ba[2]
set_instance_assignment -name IO_STANDARD "SSTL-18 CLASS I" -to M1_DDR2_ras_n
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to M1_DDR2_ras_n
set_instance_assignment -name IO_STANDARD "SSTL-18 CLASS I" -to M1_DDR2_cas_n
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to M1_DDR2_cas_n
set_instance_assignment -name IO_STANDARD "SSTL-18 CLASS I" -to M1_DDR2_we_n
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to M1_DDR2_we_n
set_instance_assignment -name IO_STANDARD "SSTL-18 CLASS I" -to M1_DDR2_dq[0]
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to M1_DDR2_dq[0]
set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to M1_DDR2_dq[0]
set_instance_assignment -name IO_STANDARD "SSTL-18 CLASS I" -to M1_DDR2_dq[1]
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to M1_DDR2_dq[1]
set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to M1_DDR2_dq[1]
set_instance_assignment -name IO_STANDARD "SSTL-18 CLASS I" -to M1_DDR2_dq[2]
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to M1_DDR2_dq[2]
set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to M1_DDR2_dq[2]
set_instance_assignment -name IO_STANDARD "SSTL-18 CLASS I" -to M1_DDR2_dq[3]
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to M1_DDR2_dq[3]
set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to M1_DDR2_dq[3]
set_instance_assignment -name IO_STANDARD "SSTL-18 CLASS I" -to M1_DDR2_dq[4]
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to M1_DDR2_dq[4]
set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to M1_DDR2_dq[4]
set_instance_assignment -name IO_STANDARD "SSTL-18 CLASS I" -to M1_DDR2_dq[5]
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to M1_DDR2_dq[5]
set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to M1_DDR2_dq[5]
set_instance_assignment -name IO_STANDARD "SSTL-18 CLASS I" -to M1_DDR2_dq[6]
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to M1_DDR2_dq[6]
set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to M1_DDR2_dq[6]
set_instance_assignment -name IO_STANDARD "SSTL-18 CLASS I" -to M1_DDR2_dq[7]
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to M1_DDR2_dq[7]
set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to M1_DDR2_dq[7]
set_instance_assignment -name IO_STANDARD "SSTL-18 CLASS I" -to M1_DDR2_dq[8]
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to M1_DDR2_dq[8]
set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to M1_DDR2_dq[8]
set_instance_assignment -name IO_STANDARD "SSTL-18 CLASS I" -to M1_DDR2_dq[9]
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to M1_DDR2_dq[9]
set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to M1_DDR2_dq[9]
set_instance_assignment -name IO_STANDARD "SSTL-18 CLASS I" -to M1_DDR2_dq[10]
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to M1_DDR2_dq[10]
set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to M1_DDR2_dq[10]
set_instance_assignment -name IO_STANDARD "SSTL-18 CLASS I" -to M1_DDR2_dq[11]
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to M1_DDR2_dq[11]
set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to M1_DDR2_dq[11]
set_instance_assignment -name IO_STANDARD "SSTL-18 CLASS I" -to M1_DDR2_dq[12]
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to M1_DDR2_dq[12]
set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to M1_DDR2_dq[12]
set_instance_assignment -name IO_STANDARD "SSTL-18 CLASS I" -to M1_DDR2_dq[13]
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to M1_DDR2_dq[13]
set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to M1_DDR2_dq[13]
set_instance_assignment -name IO_STANDARD "SSTL-18 CLASS I" -to M1_DDR2_dq[14]
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to M1_DDR2_dq[14]
set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to M1_DDR2_dq[14]
set_instance_assignment -name IO_STANDARD "SSTL-18 CLASS I" -to M1_DDR2_dq[15]
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to M1_DDR2_dq[15]
set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to M1_DDR2_dq[15]
set_instance_assignment -name IO_STANDARD "SSTL-18 CLASS I" -to M1_DDR2_dq[16]
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to M1_DDR2_dq[16]
set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to M1_DDR2_dq[16]
set_instance_assignment -name IO_STANDARD "SSTL-18 CLASS I" -to M1_DDR2_dq[17]
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to M1_DDR2_dq[17]
set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to M1_DDR2_dq[17]
set_instance_assignment -name IO_STANDARD "SSTL-18 CLASS I" -to M1_DDR2_dq[18]
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to M1_DDR2_dq[18]
set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to M1_DDR2_dq[18]
set_instance_assignment -name IO_STANDARD "SSTL-18 CLASS I" -to M1_DDR2_dq[19]
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to M1_DDR2_dq[19]
set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to M1_DDR2_dq[19]
set_instance_assignment -name IO_STANDARD "SSTL-18 CLASS I" -to M1_DDR2_dq[20]
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to M1_DDR2_dq[20]
set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to M1_DDR2_dq[20]
set_instance_assignment -name IO_STANDARD "SSTL-18 CLASS I" -to M1_DDR2_dq[21]
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to M1_DDR2_dq[21]
set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to M1_DDR2_dq[21]
set_instance_assignment -name IO_STANDARD "SSTL-18 CLASS I" -to M1_DDR2_dq[22]
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to M1_DDR2_dq[22]
set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to M1_DDR2_dq[22]
set_instance_assignment -name IO_STANDARD "SSTL-18 CLASS I" -to M1_DDR2_dq[23]
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to M1_DDR2_dq[23]
set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to M1_DDR2_dq[23]
set_instance_assignment -name IO_STANDARD "SSTL-18 CLASS I" -to M1_DDR2_dq[24]
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to M1_DDR2_dq[24]
set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to M1_DDR2_dq[24]
set_instance_assignment -name IO_STANDARD "SSTL-18 CLASS I" -to M1_DDR2_dq[25]
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to M1_DDR2_dq[25]
set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to M1_DDR2_dq[25]
set_instance_assignment -name IO_STANDARD "SSTL-18 CLASS I" -to M1_DDR2_dq[26]
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to M1_DDR2_dq[26]
set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to M1_DDR2_dq[26]
set_instance_assignment -name IO_STANDARD "SSTL-18 CLASS I" -to M1_DDR2_dq[27]
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to M1_DDR2_dq[27]
set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to M1_DDR2_dq[27]
set_instance_assignment -name IO_STANDARD "SSTL-18 CLASS I" -to M1_DDR2_dq[28]
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to M1_DDR2_dq[28]
set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to M1_DDR2_dq[28]
set_instance_assignment -name IO_STANDARD "SSTL-18 CLASS I" -to M1_DDR2_dq[29]
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to M1_DDR2_dq[29]
set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to M1_DDR2_dq[29]
set_instance_assignment -name IO_STANDARD "SSTL-18 CLASS I" -to M1_DDR2_dq[30]
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to M1_DDR2_dq[30]
set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to M1_DDR2_dq[30]
set_instance_assignment -name IO_STANDARD "SSTL-18 CLASS I" -to M1_DDR2_dq[31]
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to M1_DDR2_dq[31]
set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to M1_DDR2_dq[31]
set_instance_assignment -name IO_STANDARD "SSTL-18 CLASS I" -to M1_DDR2_dq[32]
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to M1_DDR2_dq[32]
set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to M1_DDR2_dq[32]
set_instance_assignment -name IO_STANDARD "SSTL-18 CLASS I" -to M1_DDR2_dq[33]
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to M1_DDR2_dq[33]
set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to M1_DDR2_dq[33]
set_instance_assignment -name IO_STANDARD "SSTL-18 CLASS I" -to M1_DDR2_dq[34]
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to M1_DDR2_dq[34]
set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to M1_DDR2_dq[34]
set_instance_assignment -name IO_STANDARD "SSTL-18 CLASS I" -to M1_DDR2_dq[35]
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to M1_DDR2_dq[35]
set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to M1_DDR2_dq[35]
set_instance_assignment -name IO_STANDARD "SSTL-18 CLASS I" -to M1_DDR2_dq[36]
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to M1_DDR2_dq[36]
set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to M1_DDR2_dq[36]
set_instance_assignment -name IO_STANDARD "SSTL-18 CLASS I" -to M1_DDR2_dq[37]
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to M1_DDR2_dq[37]
set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to M1_DDR2_dq[37]
set_instance_assignment -name IO_STANDARD "SSTL-18 CLASS I" -to M1_DDR2_dq[38]
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to M1_DDR2_dq[38]
set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to M1_DDR2_dq[38]
set_instance_assignment -name IO_STANDARD "SSTL-18 CLASS I" -to M1_DDR2_dq[39]
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to M1_DDR2_dq[39]
set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to M1_DDR2_dq[39]
set_instance_assignment -name IO_STANDARD "SSTL-18 CLASS I" -to M1_DDR2_dq[40]
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to M1_DDR2_dq[40]
set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to M1_DDR2_dq[40]
set_instance_assignment -name IO_STANDARD "SSTL-18 CLASS I" -to M1_DDR2_dq[41]
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to M1_DDR2_dq[41]
set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to M1_DDR2_dq[41]
set_instance_assignment -name IO_STANDARD "SSTL-18 CLASS I" -to M1_DDR2_dq[42]
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to M1_DDR2_dq[42]
set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to M1_DDR2_dq[42]
set_instance_assignment -name IO_STANDARD "SSTL-18 CLASS I" -to M1_DDR2_dq[43]
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to M1_DDR2_dq[43]
set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to M1_DDR2_dq[43]
set_instance_assignment -name IO_STANDARD "SSTL-18 CLASS I" -to M1_DDR2_dq[44]
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to M1_DDR2_dq[44]
set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to M1_DDR2_dq[44]
set_instance_assignment -name IO_STANDARD "SSTL-18 CLASS I" -to M1_DDR2_dq[45]
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to M1_DDR2_dq[45]
set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to M1_DDR2_dq[45]
set_instance_assignment -name IO_STANDARD "SSTL-18 CLASS I" -to M1_DDR2_dq[46]
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to M1_DDR2_dq[46]
set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to M1_DDR2_dq[46]
set_instance_assignment -name IO_STANDARD "SSTL-18 CLASS I" -to M1_DDR2_dq[47]
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to M1_DDR2_dq[47]
set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to M1_DDR2_dq[47]
set_instance_assignment -name IO_STANDARD "SSTL-18 CLASS I" -to M1_DDR2_dq[48]
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to M1_DDR2_dq[48]
set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to M1_DDR2_dq[48]
set_instance_assignment -name IO_STANDARD "SSTL-18 CLASS I" -to M1_DDR2_dq[49]
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to M1_DDR2_dq[49]
set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to M1_DDR2_dq[49]
set_instance_assignment -name IO_STANDARD "SSTL-18 CLASS I" -to M1_DDR2_dq[50]
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to M1_DDR2_dq[50]
set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to M1_DDR2_dq[50]
set_instance_assignment -name IO_STANDARD "SSTL-18 CLASS I" -to M1_DDR2_dq[51]
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to M1_DDR2_dq[51]
set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to M1_DDR2_dq[51]
set_instance_assignment -name IO_STANDARD "SSTL-18 CLASS I" -to M1_DDR2_dq[52]
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to M1_DDR2_dq[52]
set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to M1_DDR2_dq[52]
set_instance_assignment -name IO_STANDARD "SSTL-18 CLASS I" -to M1_DDR2_dq[53]
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to M1_DDR2_dq[53]
set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to M1_DDR2_dq[53]
set_instance_assignment -name IO_STANDARD "SSTL-18 CLASS I" -to M1_DDR2_dq[54]
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to M1_DDR2_dq[54]
set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to M1_DDR2_dq[54]
set_instance_assignment -name IO_STANDARD "SSTL-18 CLASS I" -to M1_DDR2_dq[55]
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to M1_DDR2_dq[55]
set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to M1_DDR2_dq[55]
set_instance_assignment -name IO_STANDARD "SSTL-18 CLASS I" -to M1_DDR2_dq[56]
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to M1_DDR2_dq[56]
set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to M1_DDR2_dq[56]
set_instance_assignment -name IO_STANDARD "SSTL-18 CLASS I" -to M1_DDR2_dq[57]
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to M1_DDR2_dq[57]
set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to M1_DDR2_dq[57]
set_instance_assignment -name IO_STANDARD "SSTL-18 CLASS I" -to M1_DDR2_dq[58]
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to M1_DDR2_dq[58]
set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to M1_DDR2_dq[58]
set_instance_assignment -name IO_STANDARD "SSTL-18 CLASS I" -to M1_DDR2_dq[59]
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to M1_DDR2_dq[59]
set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to M1_DDR2_dq[59]
set_instance_assignment -name IO_STANDARD "SSTL-18 CLASS I" -to M1_DDR2_dq[60]
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to M1_DDR2_dq[60]
set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to M1_DDR2_dq[60]
set_instance_assignment -name IO_STANDARD "SSTL-18 CLASS I" -to M1_DDR2_dq[61]
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to M1_DDR2_dq[61]
set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to M1_DDR2_dq[61]
set_instance_assignment -name IO_STANDARD "SSTL-18 CLASS I" -to M1_DDR2_dq[62]
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to M1_DDR2_dq[62]
set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to M1_DDR2_dq[62]
set_instance_assignment -name IO_STANDARD "SSTL-18 CLASS I" -to M1_DDR2_dq[63]
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to M1_DDR2_dq[63]
set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to M1_DDR2_dq[63]
set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.8-V SSTL CLASS I" -to M1_DDR2_dqs[0]
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to M1_DDR2_dqs[0]
set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to M1_DDR2_dqs[0]
set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.8-V SSTL CLASS I" -to M1_DDR2_dqs[1]
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to M1_DDR2_dqs[1]
set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to M1_DDR2_dqs[1]
set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.8-V SSTL CLASS I" -to M1_DDR2_dqs[2]
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to M1_DDR2_dqs[2]
set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to M1_DDR2_dqs[2]
set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.8-V SSTL CLASS I" -to M1_DDR2_dqs[3]
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to M1_DDR2_dqs[3]
set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to M1_DDR2_dqs[3]
set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.8-V SSTL CLASS I" -to M1_DDR2_dqs[4]
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to M1_DDR2_dqs[4]
set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to M1_DDR2_dqs[4]
set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.8-V SSTL CLASS I" -to M1_DDR2_dqs[5]
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to M1_DDR2_dqs[5]
set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to M1_DDR2_dqs[5]
set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.8-V SSTL CLASS I" -to M1_DDR2_dqs[6]
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to M1_DDR2_dqs[6]
set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to M1_DDR2_dqs[6]
set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.8-V SSTL CLASS I" -to M1_DDR2_dqs[7]
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to M1_DDR2_dqs[7]
set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to M1_DDR2_dqs[7]
set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.8-V SSTL CLASS I" -to M1_DDR2_dqsn[0]
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to M1_DDR2_dqsn[0]
set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to M1_DDR2_dqsn[0]
set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.8-V SSTL CLASS I" -to M1_DDR2_dqsn[1]
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to M1_DDR2_dqsn[1]
set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to M1_DDR2_dqsn[1]
set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.8-V SSTL CLASS I" -to M1_DDR2_dqsn[2]
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to M1_DDR2_dqsn[2]
set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to M1_DDR2_dqsn[2]
set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.8-V SSTL CLASS I" -to M1_DDR2_dqsn[3]
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to M1_DDR2_dqsn[3]
set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to M1_DDR2_dqsn[3]
set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.8-V SSTL CLASS I" -to M1_DDR2_dqsn[4]
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to M1_DDR2_dqsn[4]
set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to M1_DDR2_dqsn[4]
set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.8-V SSTL CLASS I" -to M1_DDR2_dqsn[5]
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to M1_DDR2_dqsn[5]
set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to M1_DDR2_dqsn[5]
set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.8-V SSTL CLASS I" -to M1_DDR2_dqsn[6]
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to M1_DDR2_dqsn[6]
set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to M1_DDR2_dqsn[6]
set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.8-V SSTL CLASS I" -to M1_DDR2_dqsn[7]
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to M1_DDR2_dqsn[7]
set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to M1_DDR2_dqsn[7]
set_instance_assignment -name IO_STANDARD "SSTL-18 CLASS I" -to M1_DDR2_dm[0]
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to M1_DDR2_dm[0]
set_instance_assignment -name IO_STANDARD "SSTL-18 CLASS I" -to M1_DDR2_dm[1]
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to M1_DDR2_dm[1]
set_instance_assignment -name IO_STANDARD "SSTL-18 CLASS I" -to M1_DDR2_dm[2]
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to M1_DDR2_dm[2]
set_instance_assignment -name IO_STANDARD "SSTL-18 CLASS I" -to M1_DDR2_dm[3]
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to M1_DDR2_dm[3]
set_instance_assignment -name IO_STANDARD "SSTL-18 CLASS I" -to M1_DDR2_dm[4]
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to M1_DDR2_dm[4]
set_instance_assignment -name IO_STANDARD "SSTL-18 CLASS I" -to M1_DDR2_dm[5]
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to M1_DDR2_dm[5]
set_instance_assignment -name IO_STANDARD "SSTL-18 CLASS I" -to M1_DDR2_dm[6]
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to M1_DDR2_dm[6]
set_instance_assignment -name IO_STANDARD "SSTL-18 CLASS I" -to M1_DDR2_dm[7]
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to M1_DDR2_dm[7]
set_instance_assignment -name OUTPUT_ENABLE_GROUP 3078784 -to M1_DDR2_dq[0]
set_instance_assignment -name OUTPUT_ENABLE_GROUP 3078784 -to M1_DDR2_dq[1]
set_instance_assignment -name OUTPUT_ENABLE_GROUP 3078784 -to M1_DDR2_dq[2]
set_instance_assignment -name OUTPUT_ENABLE_GROUP 3078784 -to M1_DDR2_dq[3]
set_instance_assignment -name OUTPUT_ENABLE_GROUP 3078784 -to M1_DDR2_dq[4]
set_instance_assignment -name OUTPUT_ENABLE_GROUP 3078784 -to M1_DDR2_dq[5]
set_instance_assignment -name OUTPUT_ENABLE_GROUP 3078784 -to M1_DDR2_dq[6]
set_instance_assignment -name OUTPUT_ENABLE_GROUP 3078784 -to M1_DDR2_dq[7]
set_instance_assignment -name OUTPUT_ENABLE_GROUP 3078784 -to M1_DDR2_dq[8]
set_instance_assignment -name OUTPUT_ENABLE_GROUP 3078784 -to M1_DDR2_dq[9]
set_instance_assignment -name OUTPUT_ENABLE_GROUP 3078784 -to M1_DDR2_dq[10]
set_instance_assignment -name OUTPUT_ENABLE_GROUP 3078784 -to M1_DDR2_dq[11]
set_instance_assignment -name OUTPUT_ENABLE_GROUP 3078784 -to M1_DDR2_dq[12]
set_instance_assignment -name OUTPUT_ENABLE_GROUP 3078784 -to M1_DDR2_dq[13]
set_instance_assignment -name OUTPUT_ENABLE_GROUP 3078784 -to M1_DDR2_dq[14]
set_instance_assignment -name OUTPUT_ENABLE_GROUP 3078784 -to M1_DDR2_dq[15]
set_instance_assignment -name OUTPUT_ENABLE_GROUP 3078784 -to M1_DDR2_dq[16]
set_instance_assignment -name OUTPUT_ENABLE_GROUP 3078784 -to M1_DDR2_dq[17]
set_instance_assignment -name OUTPUT_ENABLE_GROUP 3078784 -to M1_DDR2_dq[18]
set_instance_assignment -name OUTPUT_ENABLE_GROUP 3078784 -to M1_DDR2_dq[19]
set_instance_assignment -name OUTPUT_ENABLE_GROUP 3078784 -to M1_DDR2_dq[20]
set_instance_assignment -name OUTPUT_ENABLE_GROUP 3078784 -to M1_DDR2_dq[21]
set_instance_assignment -name OUTPUT_ENABLE_GROUP 3078784 -to M1_DDR2_dq[22]
set_instance_assignment -name OUTPUT_ENABLE_GROUP 3078784 -to M1_DDR2_dq[23]
set_instance_assignment -name OUTPUT_ENABLE_GROUP 3078784 -to M1_DDR2_dq[24]
set_instance_assignment -name OUTPUT_ENABLE_GROUP 3078784 -to M1_DDR2_dq[25]
set_instance_assignment -name OUTPUT_ENABLE_GROUP 3078784 -to M1_DDR2_dq[26]
set_instance_assignment -name OUTPUT_ENABLE_GROUP 3078784 -to M1_DDR2_dq[27]
set_instance_assignment -name OUTPUT_ENABLE_GROUP 3078784 -to M1_DDR2_dq[28]
set_instance_assignment -name OUTPUT_ENABLE_GROUP 3078784 -to M1_DDR2_dq[29]
set_instance_assignment -name OUTPUT_ENABLE_GROUP 3078784 -to M1_DDR2_dq[30]
set_instance_assignment -name OUTPUT_ENABLE_GROUP 3078784 -to M1_DDR2_dq[31]
set_instance_assignment -name OUTPUT_ENABLE_GROUP 3078784 -to M1_DDR2_dq[32]
set_instance_assignment -name OUTPUT_ENABLE_GROUP 3078784 -to M1_DDR2_dq[33]
set_instance_assignment -name OUTPUT_ENABLE_GROUP 3078784 -to M1_DDR2_dq[34]
set_instance_assignment -name OUTPUT_ENABLE_GROUP 3078784 -to M1_DDR2_dq[35]
set_instance_assignment -name OUTPUT_ENABLE_GROUP 3078784 -to M1_DDR2_dq[36]
set_instance_assignment -name OUTPUT_ENABLE_GROUP 3078784 -to M1_DDR2_dq[37]
set_instance_assignment -name OUTPUT_ENABLE_GROUP 3078784 -to M1_DDR2_dq[38]
set_instance_assignment -name OUTPUT_ENABLE_GROUP 3078784 -to M1_DDR2_dq[39]
set_instance_assignment -name OUTPUT_ENABLE_GROUP 3078784 -to M1_DDR2_dq[40]
set_instance_assignment -name OUTPUT_ENABLE_GROUP 3078784 -to M1_DDR2_dq[41]
set_instance_assignment -name OUTPUT_ENABLE_GROUP 3078784 -to M1_DDR2_dq[42]
set_instance_assignment -name OUTPUT_ENABLE_GROUP 3078784 -to M1_DDR2_dq[43]
set_instance_assignment -name OUTPUT_ENABLE_GROUP 3078784 -to M1_DDR2_dq[44]
set_instance_assignment -name OUTPUT_ENABLE_GROUP 3078784 -to M1_DDR2_dq[45]
set_instance_assignment -name OUTPUT_ENABLE_GROUP 3078784 -to M1_DDR2_dq[46]
set_instance_assignment -name OUTPUT_ENABLE_GROUP 3078784 -to M1_DDR2_dq[47]
set_instance_assignment -name OUTPUT_ENABLE_GROUP 3078784 -to M1_DDR2_dq[48]
set_instance_assignment -name OUTPUT_ENABLE_GROUP 3078784 -to M1_DDR2_dq[49]
set_instance_assignment -name OUTPUT_ENABLE_GROUP 3078784 -to M1_DDR2_dq[50]
set_instance_assignment -name OUTPUT_ENABLE_GROUP 3078784 -to M1_DDR2_dq[51]
set_instance_assignment -name OUTPUT_ENABLE_GROUP 3078784 -to M1_DDR2_dq[52]
set_instance_assignment -name OUTPUT_ENABLE_GROUP 3078784 -to M1_DDR2_dq[53]
set_instance_assignment -name OUTPUT_ENABLE_GROUP 3078784 -to M1_DDR2_dq[54]
set_instance_assignment -name OUTPUT_ENABLE_GROUP 3078784 -to M1_DDR2_dq[55]
set_instance_assignment -name OUTPUT_ENABLE_GROUP 3078784 -to M1_DDR2_dq[56]
set_instance_assignment -name OUTPUT_ENABLE_GROUP 3078784 -to M1_DDR2_dq[57]
set_instance_assignment -name OUTPUT_ENABLE_GROUP 3078784 -to M1_DDR2_dq[58]
set_instance_assignment -name OUTPUT_ENABLE_GROUP 3078784 -to M1_DDR2_dq[59]
set_instance_assignment -name OUTPUT_ENABLE_GROUP 3078784 -to M1_DDR2_dq[60]
set_instance_assignment -name OUTPUT_ENABLE_GROUP 3078784 -to M1_DDR2_dq[61]
set_instance_assignment -name OUTPUT_ENABLE_GROUP 3078784 -to M1_DDR2_dq[62]
set_instance_assignment -name OUTPUT_ENABLE_GROUP 3078784 -to M1_DDR2_dq[63]
set_instance_assignment -name OUTPUT_ENABLE_GROUP 3078784 -to M1_DDR2_dqs[0]
set_instance_assignment -name OUTPUT_ENABLE_GROUP 3078784 -to M1_DDR2_dqs[1]
set_instance_assignment -name OUTPUT_ENABLE_GROUP 3078784 -to M1_DDR2_dqs[2]
set_instance_assignment -name OUTPUT_ENABLE_GROUP 3078784 -to M1_DDR2_dqs[3]
set_instance_assignment -name OUTPUT_ENABLE_GROUP 3078784 -to M1_DDR2_dqs[4]
set_instance_assignment -name OUTPUT_ENABLE_GROUP 3078784 -to M1_DDR2_dqs[5]
set_instance_assignment -name OUTPUT_ENABLE_GROUP 3078784 -to M1_DDR2_dqs[6]
set_instance_assignment -name OUTPUT_ENABLE_GROUP 3078784 -to M1_DDR2_dqs[7]
set_instance_assignment -name OUTPUT_ENABLE_GROUP 3078784 -to M1_DDR2_dqsn[0]
set_instance_assignment -name OUTPUT_ENABLE_GROUP 3078784 -to M1_DDR2_dqsn[1]
set_instance_assignment -name OUTPUT_ENABLE_GROUP 3078784 -to M1_DDR2_dqsn[2]
set_instance_assignment -name OUTPUT_ENABLE_GROUP 3078784 -to M1_DDR2_dqsn[3]
set_instance_assignment -name OUTPUT_ENABLE_GROUP 3078784 -to M1_DDR2_dqsn[4]
set_instance_assignment -name OUTPUT_ENABLE_GROUP 3078784 -to M1_DDR2_dqsn[5]
set_instance_assignment -name OUTPUT_ENABLE_GROUP 3078784 -to M1_DDR2_dqsn[6]
set_instance_assignment -name OUTPUT_ENABLE_GROUP 3078784 -to M1_DDR2_dqsn[7]
set_instance_assignment -name OUTPUT_ENABLE_GROUP 3078784 -to M1_DDR2_dm[0]
set_instance_assignment -name OUTPUT_ENABLE_GROUP 3078784 -to M1_DDR2_dm[1]
set_instance_assignment -name OUTPUT_ENABLE_GROUP 3078784 -to M1_DDR2_dm[2]
set_instance_assignment -name OUTPUT_ENABLE_GROUP 3078784 -to M1_DDR2_dm[3]
set_instance_assignment -name OUTPUT_ENABLE_GROUP 3078784 -to M1_DDR2_dm[4]
set_instance_assignment -name OUTPUT_ENABLE_GROUP 3078784 -to M1_DDR2_dm[5]
set_instance_assignment -name OUTPUT_ENABLE_GROUP 3078784 -to M1_DDR2_dm[6]
set_instance_assignment -name OUTPUT_ENABLE_GROUP 3078784 -to M1_DDR2_dm[7]
set_instance_assignment -name DQ_GROUP 9 -from M1_DDR2_dqs[0] -to M1_DDR2_dq[0..7]
set_instance_assignment -name DQ_GROUP 9 -from M1_DDR2_dqs[0] -to M1_DDR2_dm[0]
set_instance_assignment -name DQSB_DQS_PAIR ON -from M1_DDR2_dqsn[0] -to M1_DDR2_dqs[0]
set_instance_assignment -name DQ_GROUP 9 -from M1_DDR2_dqs[1] -to M1_DDR2_dq[8..15]
set_instance_assignment -name DQ_GROUP 9 -from M1_DDR2_dqs[1] -to M1_DDR2_dm[1]
set_instance_assignment -name DQSB_DQS_PAIR ON -from M1_DDR2_dqsn[1] -to M1_DDR2_dqs[1]
set_instance_assignment -name DQ_GROUP 9 -from M1_DDR2_dqs[2] -to M1_DDR2_dq[16..23]
set_instance_assignment -name DQ_GROUP 9 -from M1_DDR2_dqs[2] -to M1_DDR2_dm[2]
set_instance_assignment -name DQSB_DQS_PAIR ON -from M1_DDR2_dqsn[2] -to M1_DDR2_dqs[2]
set_instance_assignment -name DQ_GROUP 9 -from M1_DDR2_dqs[3] -to M1_DDR2_dq[24..31]
set_instance_assignment -name DQ_GROUP 9 -from M1_DDR2_dqs[3] -to M1_DDR2_dm[3]
set_instance_assignment -name DQSB_DQS_PAIR ON -from M1_DDR2_dqsn[3] -to M1_DDR2_dqs[3]
set_instance_assignment -name DQ_GROUP 9 -from M1_DDR2_dqs[4] -to M1_DDR2_dq[32..39]
set_instance_assignment -name DQ_GROUP 9 -from M1_DDR2_dqs[4] -to M1_DDR2_dm[4]
set_instance_assignment -name DQSB_DQS_PAIR ON -from M1_DDR2_dqsn[4] -to M1_DDR2_dqs[4]
set_instance_assignment -name DQ_GROUP 9 -from M1_DDR2_dqs[5] -to M1_DDR2_dq[40..47]
set_instance_assignment -name DQ_GROUP 9 -from M1_DDR2_dqs[5] -to M1_DDR2_dm[5]
set_instance_assignment -name DQSB_DQS_PAIR ON -from M1_DDR2_dqsn[5] -to M1_DDR2_dqs[5]
set_instance_assignment -name DQ_GROUP 9 -from M1_DDR2_dqs[6] -to M1_DDR2_dq[48..55]
set_instance_assignment -name DQ_GROUP 9 -from M1_DDR2_dqs[6] -to M1_DDR2_dm[6]
set_instance_assignment -name DQSB_DQS_PAIR ON -from M1_DDR2_dqsn[6] -to M1_DDR2_dqs[6]
set_instance_assignment -name DQ_GROUP 9 -from M1_DDR2_dqs[7] -to M1_DDR2_dq[56..63]
set_instance_assignment -name DQ_GROUP 9 -from M1_DDR2_dqs[7] -to M1_DDR2_dm[7]
set_instance_assignment -name DQSB_DQS_PAIR ON -from M1_DDR2_dqsn[7] -to M1_DDR2_dqs[7]

#============================================================
# DDR2 DIM2 setting
#============================================================
set_instance_assignment -name IO_STANDARD "SSTL-18 CLASS I" -to M2_DDR2_odt[0]
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to M2_DDR2_odt[0]
set_instance_assignment -name IO_STANDARD "SSTL-18 CLASS I" -to M2_DDR2_odt[1]
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to M2_DDR2_odt[1]
set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.8-V SSTL CLASS I" -to M2_DDR2_clk[0]
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to M2_DDR2_clk[0]
set_instance_assignment -name TREAT_BIDIR_AS_OUTPUT ON -to M2_DDR2_clk[1]
set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.8-V SSTL CLASS I" -to M2_DDR2_clk[1]
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to M2_DDR2_clk[1]
set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.8-V SSTL CLASS I" -to M2_DDR2_clk_n[0]
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to M2_DDR2_clk_n[0]
set_instance_assignment -name TREAT_BIDIR_AS_OUTPUT ON -to M2_DDR2_clk_n[1]
set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.8-V SSTL CLASS I" -to M2_DDR2_clk_n[1]
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to M2_DDR2_clk_n[1]
set_instance_assignment -name IO_STANDARD "SSTL-18 CLASS I" -to M2_DDR2_cs_n[0]
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to M2_DDR2_cs_n[0]
set_instance_assignment -name IO_STANDARD "SSTL-18 CLASS I" -to M2_DDR2_cs_n[1]
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to M2_DDR2_cs_n[1]
set_instance_assignment -name IO_STANDARD "SSTL-18 CLASS I" -to M2_DDR2_cke[0]
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to M2_DDR2_cke[0]
set_instance_assignment -name IO_STANDARD "SSTL-18 CLASS I" -to M2_DDR2_cke[1]
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to M2_DDR2_cke[1]
set_instance_assignment -name IO_STANDARD "SSTL-18 CLASS I" -to M2_DDR2_addr[0]
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to M2_DDR2_addr[0]
set_instance_assignment -name IO_STANDARD "SSTL-18 CLASS I" -to M2_DDR2_addr[1]
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to M2_DDR2_addr[1]
set_instance_assignment -name IO_STANDARD "SSTL-18 CLASS I" -to M2_DDR2_addr[2]
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to M2_DDR2_addr[2]
set_instance_assignment -name IO_STANDARD "SSTL-18 CLASS I" -to M2_DDR2_addr[3]
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to M2_DDR2_addr[3]
set_instance_assignment -name IO_STANDARD "SSTL-18 CLASS I" -to M2_DDR2_addr[4]
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to M2_DDR2_addr[4]
set_instance_assignment -name IO_STANDARD "SSTL-18 CLASS I" -to M2_DDR2_addr[5]
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to M2_DDR2_addr[5]
set_instance_assignment -name IO_STANDARD "SSTL-18 CLASS I" -to M2_DDR2_addr[6]
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to M2_DDR2_addr[6]
set_instance_assignment -name IO_STANDARD "SSTL-18 CLASS I" -to M2_DDR2_addr[7]
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to M2_DDR2_addr[7]
set_instance_assignment -name IO_STANDARD "SSTL-18 CLASS I" -to M2_DDR2_addr[8]
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to M2_DDR2_addr[8]
set_instance_assignment -name IO_STANDARD "SSTL-18 CLASS I" -to M2_DDR2_addr[9]
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to M2_DDR2_addr[9]
set_instance_assignment -name IO_STANDARD "SSTL-18 CLASS I" -to M2_DDR2_addr[10]
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to M2_DDR2_addr[10]
set_instance_assignment -name IO_STANDARD "SSTL-18 CLASS I" -to M2_DDR2_addr[11]
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to M2_DDR2_addr[11]
set_instance_assignment -name IO_STANDARD "SSTL-18 CLASS I" -to M2_DDR2_addr[12]
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to M2_DDR2_addr[12]
set_instance_assignment -name IO_STANDARD "SSTL-18 CLASS I" -to M2_DDR2_addr[13]
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to M2_DDR2_addr[13]
set_instance_assignment -name IO_STANDARD "SSTL-18 CLASS I" -to M2_DDR2_addr[14]
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to M2_DDR2_addr[14]
set_instance_assignment -name IO_STANDARD "SSTL-18 CLASS I" -to M2_DDR2_ba[0]
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to M2_DDR2_ba[0]
set_instance_assignment -name IO_STANDARD "SSTL-18 CLASS I" -to M2_DDR2_ba[1]
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to M2_DDR2_ba[1]
set_instance_assignment -name IO_STANDARD "SSTL-18 CLASS I" -to M2_DDR2_ba[2]
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to M2_DDR2_ba[2]
set_instance_assignment -name IO_STANDARD "SSTL-18 CLASS I" -to M2_DDR2_ras_n
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to M2_DDR2_ras_n
set_instance_assignment -name IO_STANDARD "SSTL-18 CLASS I" -to M2_DDR2_cas_n
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to M2_DDR2_cas_n
set_instance_assignment -name IO_STANDARD "SSTL-18 CLASS I" -to M2_DDR2_we_n
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to M2_DDR2_we_n
set_instance_assignment -name IO_STANDARD "SSTL-18 CLASS I" -to M2_DDR2_dq[0]
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to M2_DDR2_dq[0]
set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to M2_DDR2_dq[0]
set_instance_assignment -name IO_STANDARD "SSTL-18 CLASS I" -to M2_DDR2_dq[1]
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to M2_DDR2_dq[1]
set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to M2_DDR2_dq[1]
set_instance_assignment -name IO_STANDARD "SSTL-18 CLASS I" -to M2_DDR2_dq[2]
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to M2_DDR2_dq[2]
set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to M2_DDR2_dq[2]
set_instance_assignment -name IO_STANDARD "SSTL-18 CLASS I" -to M2_DDR2_dq[3]
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to M2_DDR2_dq[3]
set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to M2_DDR2_dq[3]
set_instance_assignment -name IO_STANDARD "SSTL-18 CLASS I" -to M2_DDR2_dq[4]
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to M2_DDR2_dq[4]
set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to M2_DDR2_dq[4]
set_instance_assignment -name IO_STANDARD "SSTL-18 CLASS I" -to M2_DDR2_dq[5]
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to M2_DDR2_dq[5]
set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to M2_DDR2_dq[5]
set_instance_assignment -name IO_STANDARD "SSTL-18 CLASS I" -to M2_DDR2_dq[6]
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to M2_DDR2_dq[6]
set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to M2_DDR2_dq[6]
set_instance_assignment -name IO_STANDARD "SSTL-18 CLASS I" -to M2_DDR2_dq[7]
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to M2_DDR2_dq[7]
set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to M2_DDR2_dq[7]
set_instance_assignment -name IO_STANDARD "SSTL-18 CLASS I" -to M2_DDR2_dq[8]
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to M2_DDR2_dq[8]
set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to M2_DDR2_dq[8]
set_instance_assignment -name IO_STANDARD "SSTL-18 CLASS I" -to M2_DDR2_dq[9]
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to M2_DDR2_dq[9]
set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to M2_DDR2_dq[9]
set_instance_assignment -name IO_STANDARD "SSTL-18 CLASS I" -to M2_DDR2_dq[10]
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to M2_DDR2_dq[10]
set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to M2_DDR2_dq[10]
set_instance_assignment -name IO_STANDARD "SSTL-18 CLASS I" -to M2_DDR2_dq[11]
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to M2_DDR2_dq[11]
set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to M2_DDR2_dq[11]
set_instance_assignment -name IO_STANDARD "SSTL-18 CLASS I" -to M2_DDR2_dq[12]
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to M2_DDR2_dq[12]
set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to M2_DDR2_dq[12]
set_instance_assignment -name IO_STANDARD "SSTL-18 CLASS I" -to M2_DDR2_dq[13]
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to M2_DDR2_dq[13]
set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to M2_DDR2_dq[13]
set_instance_assignment -name IO_STANDARD "SSTL-18 CLASS I" -to M2_DDR2_dq[14]
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to M2_DDR2_dq[14]
set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to M2_DDR2_dq[14]
set_instance_assignment -name IO_STANDARD "SSTL-18 CLASS I" -to M2_DDR2_dq[15]
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to M2_DDR2_dq[15]
set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to M2_DDR2_dq[15]
set_instance_assignment -name IO_STANDARD "SSTL-18 CLASS I" -to M2_DDR2_dq[16]
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to M2_DDR2_dq[16]
set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to M2_DDR2_dq[16]
set_instance_assignment -name IO_STANDARD "SSTL-18 CLASS I" -to M2_DDR2_dq[17]
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to M2_DDR2_dq[17]
set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to M2_DDR2_dq[17]
set_instance_assignment -name IO_STANDARD "SSTL-18 CLASS I" -to M2_DDR2_dq[18]
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to M2_DDR2_dq[18]
set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to M2_DDR2_dq[18]
set_instance_assignment -name IO_STANDARD "SSTL-18 CLASS I" -to M2_DDR2_dq[19]
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to M2_DDR2_dq[19]
set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to M2_DDR2_dq[19]
set_instance_assignment -name IO_STANDARD "SSTL-18 CLASS I" -to M2_DDR2_dq[20]
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to M2_DDR2_dq[20]
set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to M2_DDR2_dq[20]
set_instance_assignment -name IO_STANDARD "SSTL-18 CLASS I" -to M2_DDR2_dq[21]
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to M2_DDR2_dq[21]
set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to M2_DDR2_dq[21]
set_instance_assignment -name IO_STANDARD "SSTL-18 CLASS I" -to M2_DDR2_dq[22]
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to M2_DDR2_dq[22]
set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to M2_DDR2_dq[22]
set_instance_assignment -name IO_STANDARD "SSTL-18 CLASS I" -to M2_DDR2_dq[23]
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to M2_DDR2_dq[23]
set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to M2_DDR2_dq[23]
set_instance_assignment -name IO_STANDARD "SSTL-18 CLASS I" -to M2_DDR2_dq[24]
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to M2_DDR2_dq[24]
set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to M2_DDR2_dq[24]
set_instance_assignment -name IO_STANDARD "SSTL-18 CLASS I" -to M2_DDR2_dq[25]
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to M2_DDR2_dq[25]
set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to M2_DDR2_dq[25]
set_instance_assignment -name IO_STANDARD "SSTL-18 CLASS I" -to M2_DDR2_dq[26]
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to M2_DDR2_dq[26]
set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to M2_DDR2_dq[26]
set_instance_assignment -name IO_STANDARD "SSTL-18 CLASS I" -to M2_DDR2_dq[27]
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to M2_DDR2_dq[27]
set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to M2_DDR2_dq[27]
set_instance_assignment -name IO_STANDARD "SSTL-18 CLASS I" -to M2_DDR2_dq[28]
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to M2_DDR2_dq[28]
set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to M2_DDR2_dq[28]
set_instance_assignment -name IO_STANDARD "SSTL-18 CLASS I" -to M2_DDR2_dq[29]
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to M2_DDR2_dq[29]
set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to M2_DDR2_dq[29]
set_instance_assignment -name IO_STANDARD "SSTL-18 CLASS I" -to M2_DDR2_dq[30]
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to M2_DDR2_dq[30]
set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to M2_DDR2_dq[30]
set_instance_assignment -name IO_STANDARD "SSTL-18 CLASS I" -to M2_DDR2_dq[31]
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to M2_DDR2_dq[31]
set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to M2_DDR2_dq[31]
set_instance_assignment -name IO_STANDARD "SSTL-18 CLASS I" -to M2_DDR2_dq[32]
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to M2_DDR2_dq[32]
set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to M2_DDR2_dq[32]
set_instance_assignment -name IO_STANDARD "SSTL-18 CLASS I" -to M2_DDR2_dq[33]
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to M2_DDR2_dq[33]
set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to M2_DDR2_dq[33]
set_instance_assignment -name IO_STANDARD "SSTL-18 CLASS I" -to M2_DDR2_dq[34]
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to M2_DDR2_dq[34]
set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to M2_DDR2_dq[34]
set_instance_assignment -name IO_STANDARD "SSTL-18 CLASS I" -to M2_DDR2_dq[35]
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to M2_DDR2_dq[35]
set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to M2_DDR2_dq[35]
set_instance_assignment -name IO_STANDARD "SSTL-18 CLASS I" -to M2_DDR2_dq[36]
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to M2_DDR2_dq[36]
set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to M2_DDR2_dq[36]
set_instance_assignment -name IO_STANDARD "SSTL-18 CLASS I" -to M2_DDR2_dq[37]
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to M2_DDR2_dq[37]
set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to M2_DDR2_dq[37]
set_instance_assignment -name IO_STANDARD "SSTL-18 CLASS I" -to M2_DDR2_dq[38]
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to M2_DDR2_dq[38]
set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to M2_DDR2_dq[38]
set_instance_assignment -name IO_STANDARD "SSTL-18 CLASS I" -to M2_DDR2_dq[39]
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to M2_DDR2_dq[39]
set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to M2_DDR2_dq[39]
set_instance_assignment -name IO_STANDARD "SSTL-18 CLASS I" -to M2_DDR2_dq[40]
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to M2_DDR2_dq[40]
set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to M2_DDR2_dq[40]
set_instance_assignment -name IO_STANDARD "SSTL-18 CLASS I" -to M2_DDR2_dq[41]
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to M2_DDR2_dq[41]
set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to M2_DDR2_dq[41]
set_instance_assignment -name IO_STANDARD "SSTL-18 CLASS I" -to M2_DDR2_dq[42]
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to M2_DDR2_dq[42]
set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to M2_DDR2_dq[42]
set_instance_assignment -name IO_STANDARD "SSTL-18 CLASS I" -to M2_DDR2_dq[43]
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to M2_DDR2_dq[43]
set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to M2_DDR2_dq[43]
set_instance_assignment -name IO_STANDARD "SSTL-18 CLASS I" -to M2_DDR2_dq[44]
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to M2_DDR2_dq[44]
set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to M2_DDR2_dq[44]
set_instance_assignment -name IO_STANDARD "SSTL-18 CLASS I" -to M2_DDR2_dq[45]
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to M2_DDR2_dq[45]
set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to M2_DDR2_dq[45]
set_instance_assignment -name IO_STANDARD "SSTL-18 CLASS I" -to M2_DDR2_dq[46]
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to M2_DDR2_dq[46]
set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to M2_DDR2_dq[46]
set_instance_assignment -name IO_STANDARD "SSTL-18 CLASS I" -to M2_DDR2_dq[47]
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to M2_DDR2_dq[47]
set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to M2_DDR2_dq[47]
set_instance_assignment -name IO_STANDARD "SSTL-18 CLASS I" -to M2_DDR2_dq[48]
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to M2_DDR2_dq[48]
set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to M2_DDR2_dq[48]
set_instance_assignment -name IO_STANDARD "SSTL-18 CLASS I" -to M2_DDR2_dq[49]
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to M2_DDR2_dq[49]
set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to M2_DDR2_dq[49]
set_instance_assignment -name IO_STANDARD "SSTL-18 CLASS I" -to M2_DDR2_dq[50]
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to M2_DDR2_dq[50]
set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to M2_DDR2_dq[50]
set_instance_assignment -name IO_STANDARD "SSTL-18 CLASS I" -to M2_DDR2_dq[51]
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to M2_DDR2_dq[51]
set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to M2_DDR2_dq[51]
set_instance_assignment -name IO_STANDARD "SSTL-18 CLASS I" -to M2_DDR2_dq[52]
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to M2_DDR2_dq[52]
set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to M2_DDR2_dq[52]
set_instance_assignment -name IO_STANDARD "SSTL-18 CLASS I" -to M2_DDR2_dq[53]
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to M2_DDR2_dq[53]
set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to M2_DDR2_dq[53]
set_instance_assignment -name IO_STANDARD "SSTL-18 CLASS I" -to M2_DDR2_dq[54]
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to M2_DDR2_dq[54]
set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to M2_DDR2_dq[54]
set_instance_assignment -name IO_STANDARD "SSTL-18 CLASS I" -to M2_DDR2_dq[55]
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to M2_DDR2_dq[55]
set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to M2_DDR2_dq[55]
set_instance_assignment -name IO_STANDARD "SSTL-18 CLASS I" -to M2_DDR2_dq[56]
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to M2_DDR2_dq[56]
set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to M2_DDR2_dq[56]
set_instance_assignment -name IO_STANDARD "SSTL-18 CLASS I" -to M2_DDR2_dq[57]
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to M2_DDR2_dq[57]
set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to M2_DDR2_dq[57]
set_instance_assignment -name IO_STANDARD "SSTL-18 CLASS I" -to M2_DDR2_dq[58]
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to M2_DDR2_dq[58]
set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to M2_DDR2_dq[58]
set_instance_assignment -name IO_STANDARD "SSTL-18 CLASS I" -to M2_DDR2_dq[59]
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to M2_DDR2_dq[59]
set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to M2_DDR2_dq[59]
set_instance_assignment -name IO_STANDARD "SSTL-18 CLASS I" -to M2_DDR2_dq[60]
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to M2_DDR2_dq[60]
set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to M2_DDR2_dq[60]
set_instance_assignment -name IO_STANDARD "SSTL-18 CLASS I" -to M2_DDR2_dq[61]
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to M2_DDR2_dq[61]
set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to M2_DDR2_dq[61]
set_instance_assignment -name IO_STANDARD "SSTL-18 CLASS I" -to M2_DDR2_dq[62]
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to M2_DDR2_dq[62]
set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to M2_DDR2_dq[62]
set_instance_assignment -name IO_STANDARD "SSTL-18 CLASS I" -to M2_DDR2_dq[63]
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to M2_DDR2_dq[63]
set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to M2_DDR2_dq[63]
set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.8-V SSTL CLASS I" -to M2_DDR2_dqs[0]
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to M2_DDR2_dqs[0]
set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to M2_DDR2_dqs[0]
set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.8-V SSTL CLASS I" -to M2_DDR2_dqs[1]
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to M2_DDR2_dqs[1]
set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to M2_DDR2_dqs[1]
set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.8-V SSTL CLASS I" -to M2_DDR2_dqs[2]
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to M2_DDR2_dqs[2]
set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to M2_DDR2_dqs[2]
set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.8-V SSTL CLASS I" -to M2_DDR2_dqs[3]
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to M2_DDR2_dqs[3]
set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to M2_DDR2_dqs[3]
set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.8-V SSTL CLASS I" -to M2_DDR2_dqs[4]
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to M2_DDR2_dqs[4]
set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to M2_DDR2_dqs[4]
set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.8-V SSTL CLASS I" -to M2_DDR2_dqs[5]
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to M2_DDR2_dqs[5]
set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to M2_DDR2_dqs[5]
set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.8-V SSTL CLASS I" -to M2_DDR2_dqs[6]
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to M2_DDR2_dqs[6]
set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to M2_DDR2_dqs[6]
set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.8-V SSTL CLASS I" -to M2_DDR2_dqs[7]
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to M2_DDR2_dqs[7]
set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to M2_DDR2_dqs[7]
set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.8-V SSTL CLASS I" -to M2_DDR2_dqsn[0]
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to M2_DDR2_dqsn[0]
set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to M2_DDR2_dqsn[0]
set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.8-V SSTL CLASS I" -to M2_DDR2_dqsn[1]
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to M2_DDR2_dqsn[1]
set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to M2_DDR2_dqsn[1]
set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.8-V SSTL CLASS I" -to M2_DDR2_dqsn[2]
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to M2_DDR2_dqsn[2]
set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to M2_DDR2_dqsn[2]
set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.8-V SSTL CLASS I" -to M2_DDR2_dqsn[3]
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to M2_DDR2_dqsn[3]
set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to M2_DDR2_dqsn[3]
set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.8-V SSTL CLASS I" -to M2_DDR2_dqsn[4]
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to M2_DDR2_dqsn[4]
set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to M2_DDR2_dqsn[4]
set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.8-V SSTL CLASS I" -to M2_DDR2_dqsn[5]
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to M2_DDR2_dqsn[5]
set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to M2_DDR2_dqsn[5]
set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.8-V SSTL CLASS I" -to M2_DDR2_dqsn[6]
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to M2_DDR2_dqsn[6]
set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to M2_DDR2_dqsn[6]
set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.8-V SSTL CLASS I" -to M2_DDR2_dqsn[7]
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to M2_DDR2_dqsn[7]
set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to M2_DDR2_dqsn[7]
set_instance_assignment -name IO_STANDARD "SSTL-18 CLASS I" -to M2_DDR2_dm[0]
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to M2_DDR2_dm[0]
set_instance_assignment -name IO_STANDARD "SSTL-18 CLASS I" -to M2_DDR2_dm[1]
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to M2_DDR2_dm[1]
set_instance_assignment -name IO_STANDARD "SSTL-18 CLASS I" -to M2_DDR2_dm[2]
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to M2_DDR2_dm[2]
set_instance_assignment -name IO_STANDARD "SSTL-18 CLASS I" -to M2_DDR2_dm[3]
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to M2_DDR2_dm[3]
set_instance_assignment -name IO_STANDARD "SSTL-18 CLASS I" -to M2_DDR2_dm[4]
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to M2_DDR2_dm[4]
set_instance_assignment -name IO_STANDARD "SSTL-18 CLASS I" -to M2_DDR2_dm[5]
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to M2_DDR2_dm[5]
set_instance_assignment -name IO_STANDARD "SSTL-18 CLASS I" -to M2_DDR2_dm[6]
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to M2_DDR2_dm[6]
set_instance_assignment -name IO_STANDARD "SSTL-18 CLASS I" -to M2_DDR2_dm[7]
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to M2_DDR2_dm[7]
set_instance_assignment -name OUTPUT_ENABLE_GROUP 3078785 -to M2_DDR2_dq[0]
set_instance_assignment -name OUTPUT_ENABLE_GROUP 3078785 -to M2_DDR2_dq[1]
set_instance_assignment -name OUTPUT_ENABLE_GROUP 3078785 -to M2_DDR2_dq[2]
set_instance_assignment -name OUTPUT_ENABLE_GROUP 3078785 -to M2_DDR2_dq[3]
set_instance_assignment -name OUTPUT_ENABLE_GROUP 3078785 -to M2_DDR2_dq[4]
set_instance_assignment -name OUTPUT_ENABLE_GROUP 3078785 -to M2_DDR2_dq[5]
set_instance_assignment -name OUTPUT_ENABLE_GROUP 3078785 -to M2_DDR2_dq[6]
set_instance_assignment -name OUTPUT_ENABLE_GROUP 3078785 -to M2_DDR2_dq[7]
set_instance_assignment -name OUTPUT_ENABLE_GROUP 3078785 -to M2_DDR2_dq[8]
set_instance_assignment -name OUTPUT_ENABLE_GROUP 3078785 -to M2_DDR2_dq[9]
set_instance_assignment -name OUTPUT_ENABLE_GROUP 3078785 -to M2_DDR2_dq[10]
set_instance_assignment -name OUTPUT_ENABLE_GROUP 3078785 -to M2_DDR2_dq[11]
set_instance_assignment -name OUTPUT_ENABLE_GROUP 3078785 -to M2_DDR2_dq[12]
set_instance_assignment -name OUTPUT_ENABLE_GROUP 3078785 -to M2_DDR2_dq[13]
set_instance_assignment -name OUTPUT_ENABLE_GROUP 3078785 -to M2_DDR2_dq[14]
set_instance_assignment -name OUTPUT_ENABLE_GROUP 3078785 -to M2_DDR2_dq[15]
set_instance_assignment -name OUTPUT_ENABLE_GROUP 3078785 -to M2_DDR2_dq[16]
set_instance_assignment -name OUTPUT_ENABLE_GROUP 3078785 -to M2_DDR2_dq[17]
set_instance_assignment -name OUTPUT_ENABLE_GROUP 3078785 -to M2_DDR2_dq[18]
set_instance_assignment -name OUTPUT_ENABLE_GROUP 3078785 -to M2_DDR2_dq[19]
set_instance_assignment -name OUTPUT_ENABLE_GROUP 3078785 -to M2_DDR2_dq[20]
set_instance_assignment -name OUTPUT_ENABLE_GROUP 3078785 -to M2_DDR2_dq[21]
set_instance_assignment -name OUTPUT_ENABLE_GROUP 3078785 -to M2_DDR2_dq[22]
set_instance_assignment -name OUTPUT_ENABLE_GROUP 3078785 -to M2_DDR2_dq[23]
set_instance_assignment -name OUTPUT_ENABLE_GROUP 3078785 -to M2_DDR2_dq[24]
set_instance_assignment -name OUTPUT_ENABLE_GROUP 3078785 -to M2_DDR2_dq[25]
set_instance_assignment -name OUTPUT_ENABLE_GROUP 3078785 -to M2_DDR2_dq[26]
set_instance_assignment -name OUTPUT_ENABLE_GROUP 3078785 -to M2_DDR2_dq[27]
set_instance_assignment -name OUTPUT_ENABLE_GROUP 3078785 -to M2_DDR2_dq[28]
set_instance_assignment -name OUTPUT_ENABLE_GROUP 3078785 -to M2_DDR2_dq[29]
set_instance_assignment -name OUTPUT_ENABLE_GROUP 3078785 -to M2_DDR2_dq[30]
set_instance_assignment -name OUTPUT_ENABLE_GROUP 3078785 -to M2_DDR2_dq[31]
set_instance_assignment -name OUTPUT_ENABLE_GROUP 3078785 -to M2_DDR2_dq[32]
set_instance_assignment -name OUTPUT_ENABLE_GROUP 3078785 -to M2_DDR2_dq[33]
set_instance_assignment -name OUTPUT_ENABLE_GROUP 3078785 -to M2_DDR2_dq[34]
set_instance_assignment -name OUTPUT_ENABLE_GROUP 3078785 -to M2_DDR2_dq[35]
set_instance_assignment -name OUTPUT_ENABLE_GROUP 3078785 -to M2_DDR2_dq[36]
set_instance_assignment -name OUTPUT_ENABLE_GROUP 3078785 -to M2_DDR2_dq[37]
set_instance_assignment -name OUTPUT_ENABLE_GROUP 3078785 -to M2_DDR2_dq[38]
set_instance_assignment -name OUTPUT_ENABLE_GROUP 3078785 -to M2_DDR2_dq[39]
set_instance_assignment -name OUTPUT_ENABLE_GROUP 3078785 -to M2_DDR2_dq[40]
set_instance_assignment -name OUTPUT_ENABLE_GROUP 3078785 -to M2_DDR2_dq[41]
set_instance_assignment -name OUTPUT_ENABLE_GROUP 3078785 -to M2_DDR2_dq[42]
set_instance_assignment -name OUTPUT_ENABLE_GROUP 3078785 -to M2_DDR2_dq[43]
set_instance_assignment -name OUTPUT_ENABLE_GROUP 3078785 -to M2_DDR2_dq[44]
set_instance_assignment -name OUTPUT_ENABLE_GROUP 3078785 -to M2_DDR2_dq[45]
set_instance_assignment -name OUTPUT_ENABLE_GROUP 3078785 -to M2_DDR2_dq[46]
set_instance_assignment -name OUTPUT_ENABLE_GROUP 3078785 -to M2_DDR2_dq[47]
set_instance_assignment -name OUTPUT_ENABLE_GROUP 3078785 -to M2_DDR2_dq[48]
set_instance_assignment -name OUTPUT_ENABLE_GROUP 3078785 -to M2_DDR2_dq[49]
set_instance_assignment -name OUTPUT_ENABLE_GROUP 3078785 -to M2_DDR2_dq[50]
set_instance_assignment -name OUTPUT_ENABLE_GROUP 3078785 -to M2_DDR2_dq[51]
set_instance_assignment -name OUTPUT_ENABLE_GROUP 3078785 -to M2_DDR2_dq[52]
set_instance_assignment -name OUTPUT_ENABLE_GROUP 3078785 -to M2_DDR2_dq[53]
set_instance_assignment -name OUTPUT_ENABLE_GROUP 3078785 -to M2_DDR2_dq[54]
set_instance_assignment -name OUTPUT_ENABLE_GROUP 3078785 -to M2_DDR2_dq[55]
set_instance_assignment -name OUTPUT_ENABLE_GROUP 3078785 -to M2_DDR2_dq[56]
set_instance_assignment -name OUTPUT_ENABLE_GROUP 3078785 -to M2_DDR2_dq[57]
set_instance_assignment -name OUTPUT_ENABLE_GROUP 3078785 -to M2_DDR2_dq[58]
set_instance_assignment -name OUTPUT_ENABLE_GROUP 3078785 -to M2_DDR2_dq[59]
set_instance_assignment -name OUTPUT_ENABLE_GROUP 3078785 -to M2_DDR2_dq[60]
set_instance_assignment -name OUTPUT_ENABLE_GROUP 3078785 -to M2_DDR2_dq[61]
set_instance_assignment -name OUTPUT_ENABLE_GROUP 3078785 -to M2_DDR2_dq[62]
set_instance_assignment -name OUTPUT_ENABLE_GROUP 3078785 -to M2_DDR2_dq[63]
set_instance_assignment -name OUTPUT_ENABLE_GROUP 3078785 -to M2_DDR2_dqs[0]
set_instance_assignment -name OUTPUT_ENABLE_GROUP 3078785 -to M2_DDR2_dqs[1]
set_instance_assignment -name OUTPUT_ENABLE_GROUP 3078785 -to M2_DDR2_dqs[2]
set_instance_assignment -name OUTPUT_ENABLE_GROUP 3078785 -to M2_DDR2_dqs[3]
set_instance_assignment -name OUTPUT_ENABLE_GROUP 3078785 -to M2_DDR2_dqs[4]
set_instance_assignment -name OUTPUT_ENABLE_GROUP 3078785 -to M2_DDR2_dqs[5]
set_instance_assignment -name OUTPUT_ENABLE_GROUP 3078785 -to M2_DDR2_dqs[6]
set_instance_assignment -name OUTPUT_ENABLE_GROUP 3078785 -to M2_DDR2_dqs[7]
set_instance_assignment -name OUTPUT_ENABLE_GROUP 3078785 -to M2_DDR2_dqsn[0]
set_instance_assignment -name OUTPUT_ENABLE_GROUP 3078785 -to M2_DDR2_dqsn[1]
set_instance_assignment -name OUTPUT_ENABLE_GROUP 3078785 -to M2_DDR2_dqsn[2]
set_instance_assignment -name OUTPUT_ENABLE_GROUP 3078785 -to M2_DDR2_dqsn[3]
set_instance_assignment -name OUTPUT_ENABLE_GROUP 3078785 -to M2_DDR2_dqsn[4]
set_instance_assignment -name OUTPUT_ENABLE_GROUP 3078785 -to M2_DDR2_dqsn[5]
set_instance_assignment -name OUTPUT_ENABLE_GROUP 3078785 -to M2_DDR2_dqsn[6]
set_instance_assignment -name OUTPUT_ENABLE_GROUP 3078785 -to M2_DDR2_dqsn[7]
set_instance_assignment -name OUTPUT_ENABLE_GROUP 3078785 -to M2_DDR2_dm[0]
set_instance_assignment -name OUTPUT_ENABLE_GROUP 3078785 -to M2_DDR2_dm[1]
set_instance_assignment -name OUTPUT_ENABLE_GROUP 3078785 -to M2_DDR2_dm[2]
set_instance_assignment -name OUTPUT_ENABLE_GROUP 3078785 -to M2_DDR2_dm[3]
set_instance_assignment -name OUTPUT_ENABLE_GROUP 3078785 -to M2_DDR2_dm[4]
set_instance_assignment -name OUTPUT_ENABLE_GROUP 3078785 -to M2_DDR2_dm[5]
set_instance_assignment -name OUTPUT_ENABLE_GROUP 3078785 -to M2_DDR2_dm[6]
set_instance_assignment -name OUTPUT_ENABLE_GROUP 3078785 -to M2_DDR2_dm[7]
set_instance_assignment -name DQ_GROUP 9 -from M2_DDR2_dqs[0] -to M2_DDR2_dq[0..7]
set_instance_assignment -name DQ_GROUP 9 -from M2_DDR2_dqs[0] -to M2_DDR2_dm[0]
set_instance_assignment -name DQSB_DQS_PAIR ON -from M2_DDR2_dqsn[0] -to M2_DDR2_dqs[0]
set_instance_assignment -name DQ_GROUP 9 -from M2_DDR2_dqs[1] -to M2_DDR2_dq[8..15]
set_instance_assignment -name DQ_GROUP 9 -from M2_DDR2_dqs[1] -to M2_DDR2_dm[1]
set_instance_assignment -name DQSB_DQS_PAIR ON -from M2_DDR2_dqsn[1] -to M2_DDR2_dqs[1]
set_instance_assignment -name DQ_GROUP 9 -from M2_DDR2_dqs[2] -to M2_DDR2_dq[16..23]
set_instance_assignment -name DQ_GROUP 9 -from M2_DDR2_dqs[2] -to M2_DDR2_dm[2]
set_instance_assignment -name DQSB_DQS_PAIR ON -from M2_DDR2_dqsn[2] -to M2_DDR2_dqs[2]
set_instance_assignment -name DQ_GROUP 9 -from M2_DDR2_dqs[3] -to M2_DDR2_dq[24..31]
set_instance_assignment -name DQ_GROUP 9 -from M2_DDR2_dqs[3] -to M2_DDR2_dm[3]
set_instance_assignment -name DQSB_DQS_PAIR ON -from M2_DDR2_dqsn[3] -to M2_DDR2_dqs[3]
set_instance_assignment -name DQ_GROUP 9 -from M2_DDR2_dqs[4] -to M2_DDR2_dq[32..39]
set_instance_assignment -name DQ_GROUP 9 -from M2_DDR2_dqs[4] -to M2_DDR2_dm[4]
set_instance_assignment -name DQSB_DQS_PAIR ON -from M2_DDR2_dqsn[4] -to M2_DDR2_dqs[4]
set_instance_assignment -name DQ_GROUP 9 -from M2_DDR2_dqs[5] -to M2_DDR2_dq[40..47]
set_instance_assignment -name DQ_GROUP 9 -from M2_DDR2_dqs[5] -to M2_DDR2_dm[5]
set_instance_assignment -name DQSB_DQS_PAIR ON -from M2_DDR2_dqsn[5] -to M2_DDR2_dqs[5]
set_instance_assignment -name DQ_GROUP 9 -from M2_DDR2_dqs[6] -to M2_DDR2_dq[48..55]
set_instance_assignment -name DQ_GROUP 9 -from M2_DDR2_dqs[6] -to M2_DDR2_dm[6]
set_instance_assignment -name DQSB_DQS_PAIR ON -from M2_DDR2_dqsn[6] -to M2_DDR2_dqs[6]
set_instance_assignment -name DQ_GROUP 9 -from M2_DDR2_dqs[7] -to M2_DDR2_dq[56..63]
set_instance_assignment -name DQ_GROUP 9 -from M2_DDR2_dqs[7] -to M2_DDR2_dm[7]
set_instance_assignment -name DQSB_DQS_PAIR ON -from M2_DDR2_dqsn[7] -to M2_DDR2_dqs[7]

#============================================================
# END
#============================================================
set_global_assignment -name MISC_FILE "G:/projet/de4/dev_2/DE4_GOLDEN_TOP/DE4_GOLDEN_TOP.dpf"
set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "2.5 V"
set_global_assignment -name MISC_FILE "G:/projet/de4/test/de4_golden_top/DE4_GOLDEN_TOP.dpf"

set_global_assignment -name MISC_FILE "D:/project/TW/de4/trunk/test/de4_golden_top/DE4_GOLDEN_TOP.dpf"
set_global_assignment -name MISC_FILE "D:/project_bei/de4/trunk/test/de4_golden_top/DE4_GOLDEN_TOP.dpf"
set_location_assignment PIN_AA35 -to HSMA_CLKIN_n1
set_location_assignment PIN_AE35 -to HSMA_CLKIN_n2
set_location_assignment PIN_AC10 -to HSMA_CLKIN_p1
set_location_assignment PIN_W35 -to HSMB_CLKIN_n1
set_location_assignment PIN_W5 -to HSMB_CLKIN_n2
set_location_assignment PIN_W34 -to HSMB_CLKIN_p1
set_location_assignment PIN_W6 -to HSMB_CLKIN_p2
set_location_assignment PIN_AF34 -to HSMA_CLKIN_p2
set_location_assignment PIN_AK13 -to CSENSE_ADC_FO
set_instance_assignment -name IO_STANDARD "1.8 V" -to CSENSE_ADC_FO
set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMB_CLKIN_n1
set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMB_CLKIN_n2
set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMB_CLKIN_p1
set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMB_CLKIN_p2
set_global_assignment -name MISC_FILE "D:/project/WH/de4/trunk/test/de4_golden_top/DE4_GOLDEN_TOP.dpf"
set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMA_CLKIN_n1
set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMA_CLKIN_n2
set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMA_CLKIN_p1
set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMA_CLKIN_p2
set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS ON
set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL ON
set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
set_global_assignment -name NOMINAL_CORE_SUPPLY_VOLTAGE 0.9V
set_global_assignment -name VCCT_L_USER_VOLTAGE 1.1V
set_global_assignment -name VCCT_R_USER_VOLTAGE 1.1V
set_global_assignment -name VCCL_GXBL_USER_VOLTAGE 1.1V
set_global_assignment -name VCCL_GXBR_USER_VOLTAGE 1.1V
set_global_assignment -name VCCR_L_USER_VOLTAGE 1.1V
set_global_assignment -name VCCR_R_USER_VOLTAGE 1.1V
set_global_assignment -name VCCA_L_USER_VOLTAGE 2.5V
set_global_assignment -name VCCA_R_USER_VOLTAGE 2.5V
set_global_assignment -name VCCH_GXBL_USER_VOLTAGE 1.4V
set_global_assignment -name VCCH_GXBR_USER_VOLTAGE 1.4V
set_global_assignment -name POWER_HSSI_VCCHIP_LEFT "Opportunistically power off"
set_global_assignment -name POWER_HSSI_VCCHIP_RIGHT "Opportunistically power off"
set_global_assignment -name POWER_HSSI_LEFT "Opportunistically power off"
set_global_assignment -name POWER_HSSI_RIGHT "Opportunistically power off"
set_global_assignment -name USE_CONFIGURATION_DEVICE OFF
set_global_assignment -name SDC_FILE DE4_GOLDEN_TOP.SDC
set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW"
set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)"
set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top