##############################################################
#
# Xilinx Core Generator version 12.1
# Date: Tue May 04 17:11:53 2010
#
##############################################################
#
#  This file contains the customisation parameters for a
#  Xilinx CORE Generator IP GUI. It is strongly recommended
#  that you do not manually alter this file as it may cause
#  unexpected and unsupported behavior.
#
##############################################################
#
# BEGIN Project Options
SET addpads = false
SET asysymbol = true
SET busformat = BusFormatAngleBracketNotRipped
SET createndf = false
SET designentry = Verilog
SET device = xc5vlx50t
SET devicefamily = virtex5
SET flowvendor = Other
SET formalverification = false
SET foundationsym = false
SET implementationfiletype = Ngc
SET package = ff1136
SET removerpms = false
SET simulationfiles = Behavioral
SET speedgrade = -1
SET verilogsim = true
SET vhdlsim = false
# END Project Options
# BEGIN Select
SELECT Endpoint_Block_Plus_for_PCI_Express family Xilinx,_Inc. 1.14
# END Select
# BEGIN Parameters
CSET acceptable_l0_latency=No_limit
CSET acceptable_l1_latency=No_limit
CSET advanced_flow_control_credit=None
CSET aux_max_current=0mA
CSET bar0_64bit=false
CSET bar0_enabled=true
CSET bar0_prefetchable=false
CSET bar0_scale=Megabytes
CSET bar0_size=1
CSET bar0_type=Memory
CSET bar0_value=FFE00000
CSET bar1_64bit=false
CSET bar1_enabled=false
CSET bar1_prefetchable=false
CSET bar1_scale=Kilobytes
CSET bar1_size=64
CSET bar1_type=IO
CSET bar1_value=00000000
CSET bar2_64bit=false
CSET bar2_enabled=false
CSET bar2_prefetchable=false
CSET bar2_scale=Kilobytes
CSET bar2_size=64
CSET bar2_type=IO
CSET bar2_value=00000000
CSET bar3_64bit=false
CSET bar3_enabled=false
CSET bar3_prefetchable=false
CSET bar3_scale=Kilobytes
CSET bar3_size=64
CSET bar3_type=IO
CSET bar3_value=00000000
CSET bar4_64bit=false
CSET bar4_enabled=false
CSET bar4_prefetchable=false
CSET bar4_scale=Kilobytes
CSET bar4_size=64
CSET bar4_type=IO
CSET bar4_value=00000000
CSET bar5_enabled=false
CSET bar5_prefetchable=false
CSET bar5_scale=Kilobytes
CSET bar5_size=64
CSET bar5_type=IO
CSET bar5_value=00000000
CSET capabilities_register=0001
CSET capability_version=1
CSET cardbus_cis_pointer=00000000
CSET class_code_base=05
CSET class_code_interface=00
CSET class_code_sub=00
CSET class_code_value=050000
CSET component_name=endpoint_blk_plus_v1_14
CSET d0_pme_support=false
CSET d0_power_consumed=0
CSET d0_power_consumed_factor=0
CSET d0_power_dissipated=0
CSET d0_power_dissipated_factor=0
CSET d1_pme_support=false
CSET d1_power_consumed=0
CSET d1_power_consumed_factor=0
CSET d1_power_dissipated=0
CSET d1_power_dissipated_factor=0
CSET d1_support=false
CSET d2_pme_support=false
CSET d2_power_consumed=0
CSET d2_power_consumed_factor=0
CSET d2_power_dissipated=0
CSET d2_power_dissipated_factor=0
CSET d2_support=false
CSET d3_power_consumed=0
CSET d3_power_consumed_factor=0
CSET d3_power_dissipated=0
CSET d3_power_dissipated_factor=0
CSET d3cold_pme_support=false
CSET d3hot_pme_support=false
CSET device_capabilities_register=00000FC2
CSET device_id=0007
CSET device_port_type=PCI_Express_Endpoint_device
CSET device_specific_initialization=false
CSET enable_aspm_l1_support=false
CSET enable_slot_clock_cfg=true
CSET expansion_rom_bar=FFF00001
CSET expansion_rom_enabled=true
CSET expansion_rom_scale=Megabytes
CSET expansion_rom_size=1
CSET force_no_scrambling=false
CSET gt_debug_ports=false
CSET interface_freq=62.5_default
CSET lane_width=X1
CSET link_capabilities_register=0003F411
CSET max_payload_size=512_bytes
CSET maximum_link_speed=1
CSET maximum_link_width=1
CSET msi=1_vector
CSET reference_freq=100
CSET revision_id=00
CSET subsystem_id=0007
CSET subsystem_vendor_id=10EE
CSET trim_tlp_digest=false
CSET tx_buf_diff_ctrl=800
CSET tx_diff_boost=true
CSET tx_diff_ctrl=800
CSET tx_pre_emphasis=52
CSET vendor_id=10EE
# END Parameters
GENERATE
# CRC: 38a13daa
