--- ./mig37/mig_37/user_design/rtl/mig_37.vhd	2013-01-15 16:04:40.000000000 +0100
+++ ./p/a/t/c/h/mig37/mig_37/user_design/rtl/mig_37.vhd	2013-01-15 16:09:19.236761589 +0100
@@ -95,8 +95,9 @@
                                        -- External memory data width.
     C3_MEM_ADDR_WIDTH       : integer := 13; 
                                        -- External memory address width.
-    C3_MEM_BANKADDR_WIDTH   : integer := 3 
+    C3_MEM_BANKADDR_WIDTH   : integer := 3; 
                                        -- External memory bank address width.
+    C3_CLKOUT5_DIVIDE       : integer := 10 
   );
    
   port
@@ -121,6 +122,8 @@
    c3_calib_done                           : out std_logic;
    c3_clk0                                 : out std_logic;
    c3_rst0                                 : out std_logic;
+   clk_125                                 : out std_logic;
+   clk_100                                 : out std_logic;
    mcb3_dram_dqs                           : inout  std_logic;
    mcb3_dram_dqs_n                         : inout  std_logic;
    mcb3_dram_ck                            : out std_logic;
@@ -179,6 +182,7 @@
       C_CLKOUT1_DIVIDE     : integer;
       C_CLKOUT2_DIVIDE     : integer;
       C_CLKOUT3_DIVIDE     : integer;
+      C_CLKOUT5_DIVIDE     : integer;
       C_CLKFBOUT_MULT      : integer;
       C_DIVCLK_DIVIDE      : integer;
       C_INCLK_PERIOD       : integer
@@ -194,11 +198,12 @@
       async_rst                              : out   std_logic;
       sysclk_2x                              : out   std_logic;
       sysclk_2x_180                          : out   std_logic;
+      mcb_drp_clk                            : out   std_logic;
       pll_ce_0                               : out   std_logic;
       pll_ce_90                              : out   std_logic;
       pll_lock                               : out   std_logic;
-      mcb_drp_clk                            : out   std_logic
-
+      clk_125                                : out   std_logic;
+      clk_100                                : out   std_logic
       );
   end component;
 
@@ -362,7 +367,8 @@
    constant C3_CLKOUT1_DIVIDE       : integer := 1; 
    constant C3_CLKOUT2_DIVIDE       : integer := 16; 
    constant C3_CLKOUT3_DIVIDE       : integer := 8; 
-   constant C3_CLKFBOUT_MULT        : integer := 2; 
+--   constant C3_CLKFBOUT_MULT        : integer := 2; 
+   constant C3_CLKFBOUT_MULT        : integer := 10; 
    constant C3_DIVCLK_DIVIDE        : integer := 1; 
    constant C3_INCLK_PERIOD         : integer := ((C3_MEMCLK_PERIOD * C3_CLKFBOUT_MULT) / (C3_DIVCLK_DIVIDE * C3_CLKOUT0_DIVIDE * 2)); 
    constant C3_ARB_NUM_TIME_SLOTS   : integer := 12; 
@@ -429,7 +435,7 @@
    constant C3_DQ13_TAP_DELAY_VAL   : integer := 0; 
    constant C3_DQ14_TAP_DELAY_VAL   : integer := 0; 
    constant C3_DQ15_TAP_DELAY_VAL   : integer := 0; 
-   constant C3_SMALL_DEVICE         : string := ""; 
+   constant C3_SMALL_DEVICE         : string := "FALSE"; 
 
   signal  c3_sys_clk_p                             : std_logic;
   signal  c3_sys_clk_n                             : std_logic;
@@ -457,7 +463,6 @@
 
 c3_sys_clk_p <= '0';
 c3_sys_clk_n <= '0';
-
 memc3_infrastructure_inst : memc3_infrastructure
 
 generic map
@@ -468,6 +473,7 @@
    C_CLKOUT1_DIVIDE                  => C3_CLKOUT1_DIVIDE,
    C_CLKOUT2_DIVIDE                  => C3_CLKOUT2_DIVIDE,
    C_CLKOUT3_DIVIDE                  => C3_CLKOUT3_DIVIDE,
+   C_CLKOUT5_DIVIDE                  => C3_CLKOUT5_DIVIDE,
    C_CLKFBOUT_MULT                   => C3_CLKFBOUT_MULT,
    C_DIVCLK_DIVIDE                   => C3_DIVCLK_DIVIDE,
    C_INCLK_PERIOD                    => C3_INCLK_PERIOD
@@ -483,10 +489,12 @@
    async_rst                       => c3_async_rst,
    sysclk_2x                       => c3_sysclk_2x,
    sysclk_2x_180                   => c3_sysclk_2x_180,
+   mcb_drp_clk                     => c3_mcb_drp_clk,
    pll_ce_0                        => c3_pll_ce_0,
    pll_ce_90                       => c3_pll_ce_90,
    pll_lock                        => c3_pll_lock,
-   mcb_drp_clk                     => c3_mcb_drp_clk
+   clk_125                         => clk_125,
+   clk_100                         => clk_100
    );
 
 
--- ./mig37/mig_37/user_design/rtl/memc3_infrastructure.vhd	2013-01-15 16:04:40.000000000 +0100
+++ ./p/a/t/c/h/mig37/mig_37/user_design/rtl/memc3_infrastructure.vhd	2013-01-15 16:07:09.836762961 +0100
@@ -77,6 +77,7 @@
     C_CLKOUT1_DIVIDE   : integer := 1;
     C_CLKOUT2_DIVIDE   : integer := 16;
     C_CLKOUT3_DIVIDE   : integer := 8;
+    C_CLKOUT5_DIVIDE   : integer := 8;
     C_CLKFBOUT_MULT   : integer := 2;
     C_DIVCLK_DIVIDE   : integer := 1
 
@@ -95,7 +96,10 @@
     mcb_drp_clk     : out std_logic;
     pll_ce_0        : out std_logic;
     pll_ce_90       : out std_logic;
-    pll_lock        : out std_logic
+    pll_lock        : out std_logic;
+    pll_lock0       : out std_logic;
+    clk_125         : out std_logic;
+    clk_100         : out std_logic
   
 );
 end entity;
@@ -129,6 +133,8 @@
   signal   locked              : std_logic;
   signal   bufpll_mcb_locked   : std_logic;
   signal   mcb_drp_clk_sig     : std_logic;
+  signal   clk_125_in          : std_logic;
+  signal   clk_100_in          : std_logic;
 
   attribute max_fanout : string;
   attribute syn_maxfan : integer;
@@ -141,6 +147,7 @@
 
   sys_rst  <= not(sys_rst_n) when (C_RST_ACT_LOW /= 0) else sys_rst_n;
   clk0     <= clk0_bufg;
+  pll_lock0 <= locked;
   pll_lock <= bufpll_mcb_locked;
   mcb_drp_clk <= mcb_drp_clk_sig;
 
@@ -164,7 +171,8 @@
       --***********************************************************************
       -- SINGLE_ENDED input clock input buffers
       --***********************************************************************
-      u_ibufg_sys_clk : IBUFG
+--      u_ibufg_sys_clk : IBUFG
+      u_ibufg_sys_clk : BUFG
         port map (
           I  => sys_clk,
           O  => sys_clk_ibufg
@@ -183,10 +191,10 @@
          CLKIN2_PERIOD      => CLK_PERIOD_NS,
          CLKOUT0_DIVIDE     => C_CLKOUT0_DIVIDE,
          CLKOUT1_DIVIDE     => C_CLKOUT1_DIVIDE,
-         CLKOUT2_DIVIDE     => C_CLKOUT2_DIVIDE,
+         CLKOUT2_DIVIDE     => 10,
          CLKOUT3_DIVIDE     => C_CLKOUT3_DIVIDE,
-         CLKOUT4_DIVIDE     => 1,
-         CLKOUT5_DIVIDE     => 1,
+         CLKOUT4_DIVIDE     => 4,
+         CLKOUT5_DIVIDE     => 5,
          CLKOUT0_PHASE      => 0.000,
          CLKOUT1_PHASE      => 180.000,
          CLKOUT2_PHASE      => 0.000,
@@ -231,8 +239,8 @@
            CLKOUT1          => clk_2x_180,
            CLKOUT2          => clk0_bufg_in,
            CLKOUT3          => mcb_drp_clk_bufg_in,
-           CLKOUT4          => open,
-           CLKOUT5          => open,
+           CLKOUT4          => clk_125_in,
+           CLKOUT5          => clk_100_in,
            DO               => open,
            DRDY             => open,
            LOCKED           => locked
@@ -251,6 +259,15 @@
      I => mcb_drp_clk_bufg_in
      );
 
+
+   clk_125 <= clk_125_in;
+
+   U_BUFG_CLK3 : BUFG 
+    port map (  
+     O => clk_100,
+     I => clk_100_in
+     );
+
    process (clk0_bufg, sys_rst)
    begin
       if(sys_rst = '1') then
