NET "clk_200" TNM_NET =  "SYS_CLK";
TIMESPEC "TS_SYS_CLK" = PERIOD "SYS_CLK" 5 ns HIGH 50 %;

# MIG 3.61


###############################################################################
# Define multicycle paths - these paths may take longer because additional
# time allowed for logic to settle in calibration/initialization FSM
###############################################################################

# MIG 2.1: Eliminate Timegroup definitions for CLK0, and CLK90. Instead trace
#          multicycle paths from originating flip-flop to ANY destination
#          flip-flop (or in some cases, it can also be a BRAM)
# MUX Select for either rising/falling CLK0 for 2nd stage read capture
INST "*/u_phy_calib/gen_rd_data_sel*.u_ff_rd_data_sel" TNM = "TNM_RD_DATA_SEL";
TIMESPEC "TS_MC_RD_DATA_SEL" = FROM "TNM_RD_DATA_SEL" TO FFS
"TS_SYS_CLK" * 4;
# MUX select for read data - optional delay on data to account for byte skews
INST "*/u_usr_rd/gen_rden_sel_mux*.u_ff_rden_sel_mux" TNM = "TNM_RDEN_SEL_MUX";
TIMESPEC "TS_MC_RDEN_SEL_MUX" = FROM "TNM_RDEN_SEL_MUX" TO FFS
"TS_SYS_CLK" * 4;
# Calibration/Initialization complete status flag (for PHY logic only) - can
# be used to drive both flip-flops and BRAMs
INST "*/u_phy_init/u_ff_phy_init_data_sel" TNM = "TNM_PHY_INIT_DATA_SEL";
TIMESPEC "TS_MC_PHY_INIT_DATA_SEL_0" = FROM "TNM_PHY_INIT_DATA_SEL" TO FFS
"TS_SYS_CLK" * 4;
# The RAM path is only used in cases where Write Latency (Additive Latency + 
# (CAS Latency - 1) + (1 in case of RDIMM)) is 2 or below. So these constraints are 
# valid for CAS Latency = 3, Additive Latency = 0 and selected part is not RDIMM. 
# If Write Latency is higher than 3, then a warning will appear in PAR, 
# and the constraint can be ignored as this path does not exist. RAM constraint 
# can be safely removed if the warning is not to be displayed.
TIMESPEC "TS_MC_PHY_INIT_DATA_SEL_90" = FROM "TNM_PHY_INIT_DATA_SEL" TO RAMS
"TS_SYS_CLK" * 4;
# Select (address) bits for SRL32 shift registers used in stage3/stage4
# calibration
INST "*/u_phy_calib/gen_gate_dly*.u_ff_gate_dly" TNM = "TNM_GATE_DLY";
TIMESPEC "TS_MC_GATE_DLY" = FROM "TNM_GATE_DLY" TO FFS "TS_SYS_CLK" * 4;

INST "*/u_phy_calib/gen_rden_dly*.u_ff_rden_dly" TNM = "TNM_RDEN_DLY";
TIMESPEC "TS_MC_RDEN_DLY" = FROM "TNM_RDEN_DLY" TO FFS "TS_SYS_CLK" * 4;

INST "*/u_phy_calib/gen_cal_rden_dly*.u_ff_cal_rden_dly"
  TNM = "TNM_CAL_RDEN_DLY";
TIMESPEC "TS_MC_CAL_RDEN_DLY" = FROM "TNM_CAL_RDEN_DLY" TO FFS
"TS_SYS_CLK" * 4;
############################################################################### 
#The following constraint is added to prevent (false) hold time violations on
#the data path from stage1 to stage2 capture flops.  Stage1 flops are clocked by 
#the delayed DQS and stage2 flops are clocked by the clk0 clock. Placing a TIG 
#on the DQ IDDR capture flop instance to achieve this is acceptable because timing
#is guaranteed through the use of separate Predictable IP constraints. These
#violations are reported when anunconstrained path report is run.	  
############################################################################### 
INST "*/gen*.u_iob_dq/gen*.u_iddr_dq" TIG ;
###############################################################################
# DQS Read Post amble Glitch Squelch circuit related constraints
###############################################################################

###############################################################################
# LOC placement of DQS-squelch related IDDR and IDELAY elements
# Each circuit can be located at any of the following locations:
#  1. Unused "N"-side of DQS differential pair I/O
#  2. DM data mask (output only, input side is free for use)
#  3. Any output-only site
###############################################################################

###############################################################################
#The following constraint is added to avoid the HOLD violations in the trace report
#when run for unconstrained paths.These two FF groups will be clocked by two different
# clocks and hence there should be no timing analysis performed on this path.
###############################################################################
INST "*/u_mem_if_top/u_phy_top/u_phy_io/u_phy_calib/gen_gate*.u_en_dqs_ff" TNM = EN_DQS_FF;
TIMESPEC TS_FROM_EN_DQS_FF_TO_DQ_CE_FF = FROM EN_DQS_FF TO TNM_DQ_CE_IDDR 3.85 ns DATAPATHONLY;

INST "*/gen_dqs*0*u_iob_dqs/u_iddr_dq_ce"	LOC = "ILOGIC_X2Y180";
INST "*/gen_dqs*0*u_iob_dqs/u_iodelay_dq_ce"	LOC = "IODELAY_X2Y180";
INST "*/gen_dqs*1*u_iob_dqs/u_iddr_dq_ce"	LOC = "ILOGIC_X2Y178";
INST "*/gen_dqs*1*u_iob_dqs/u_iodelay_dq_ce"	LOC = "IODELAY_X2Y178";
INST "*/gen_dqs*2*u_iob_dqs/u_iddr_dq_ce"	LOC = "ILOGIC_X2Y176";
INST "*/gen_dqs*2*u_iob_dqs/u_iodelay_dq_ce"	LOC = "IODELAY_X2Y176";
INST "*/gen_dqs*3*u_iob_dqs/u_iddr_dq_ce"	LOC = "ILOGIC_X2Y102";
INST "*/gen_dqs*3*u_iob_dqs/u_iodelay_dq_ce"	LOC = "IODELAY_X2Y102";
INST "*/gen_dqs*4*u_iob_dqs/u_iddr_dq_ce"	LOC = "ILOGIC_X2Y96";
INST "*/gen_dqs*4*u_iob_dqs/u_iodelay_dq_ce"	LOC = "IODELAY_X2Y96";
INST "*/gen_dqs*5*u_iob_dqs/u_iddr_dq_ce"	LOC = "ILOGIC_X0Y22";
INST "*/gen_dqs*5*u_iob_dqs/u_iodelay_dq_ce"	LOC = "IODELAY_X0Y22";
INST "*/gen_dqs*6*u_iob_dqs/u_iddr_dq_ce"	LOC = "ILOGIC_X0Y20";
INST "*/gen_dqs*6*u_iob_dqs/u_iodelay_dq_ce"	LOC = "IODELAY_X0Y20";
INST "*/gen_dqs*7*u_iob_dqs/u_iddr_dq_ce"	LOC = "ILOGIC_X0Y18";
INST "*/gen_dqs*7*u_iob_dqs/u_iodelay_dq_ce"	LOC = "IODELAY_X0Y18";

###############################################################################
# LOC and timing constraints for flop driving DQS CE enable signal
# from fabric logic. Even though the absolute delay on this path is
# calibrated out (when synchronizing this output to DQS), the delay
# should still be kept as low as possible to reduce post-calibration
# voltage/temp variations - these are roughly proportional to the
# absolute delay of the path.                                    
#	The following code has been commented for V5 as the predictable IP will take 
#	care of placement of these flops by meeting the MAXDELAY requirement.  
#	These constraints will be removed in the next release.  
###############################################################################

INST "*/u_phy_calib/gen_gate*0*u_en_dqs_ff"	LOC = SLICE_X51Y90;
INST "*/u_phy_calib/gen_gate*1*u_en_dqs_ff"	LOC = SLICE_X51Y89;
INST "*/u_phy_calib/gen_gate*2*u_en_dqs_ff"	LOC = SLICE_X51Y88;
INST "*/u_phy_calib/gen_gate*3*u_en_dqs_ff"	LOC = SLICE_X51Y51;
INST "*/u_phy_calib/gen_gate*4*u_en_dqs_ff"	LOC = SLICE_X51Y48;
INST "*/u_phy_calib/gen_gate*5*u_en_dqs_ff"	LOC = SLICE_X0Y11;
INST "*/u_phy_calib/gen_gate*6*u_en_dqs_ff"	LOC = SLICE_X0Y10;
INST "*/u_phy_calib/gen_gate*7*u_en_dqs_ff"	LOC = SLICE_X0Y9;

# Control for DQS gate - from fabric flop. Prevent "runaway" delay -
# two parts to this path: (1) from fabric flop to IDELAY, (2) from
# IDELAY to asynchronous reset of IDDR that drives the DQ CE's
# This can be relaxed by the user for lower frequencies:
# 300MHz = 850ps, 267MHz = 900ps. At 200MHz = 950ps.
# In general PAR should be able to route this
# within 900ps over all speed grades.
NET "*/u_phy_io/en_dqs?*?" MAXDELAY = 600 ps;
NET "*/u_phy_io/gen_dqs*.u_iob_dqs/en_dqs_sync" MAXDELAY = 850 ps;

###############################################################################
# "Half-cycle" path constraint from IOB flip-flop to CE pin for all DQ IDDR's
# for DQS Read Post amble Glitch Squelch circuit
###############################################################################

# Max delay from output of IOB flip-flop to CE input of DQ IDDRs =
#  tRPST + some slack where slack account for rise-time of DQS on board.
#  For now assume slack = 0.400ns (based on initial SPICE simulations,
#  assumes use of ODT), so time = 0.4*Tcyc + 0.40ns = 1.6ns @333MHz
INST "*/gen_dqs*.u_iob_dqs/u_iddr_dq_ce" TNM = "TNM_DQ_CE_IDDR";
INST "*/gen_dq*.u_iob_dq/gen_stg2_*.u_iddr_dq" TNM = "TNM_DQS_FLOPS";
TIMESPEC "TS_DQ_CE" = FROM "TNM_DQ_CE_IDDR" TO "TNM_DQS_FLOPS" 2.4 ns;


NET "clk0_tb" TNM_NET = "clk0_tb";
TIMESPEC "TS_clkm_clk0_tb" = FROM "clkm" TO "clk0_tb" 5 ns DATAPATHONLY;
TIMESPEC "TS_clk0_tb_clkm" = FROM "clk0_tb" TO "clkm" 5 ns DATAPATHONLY;

