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#
# Xilinx Core Generator version 13.2
# Date: Sat Nov 19 21:36:36 2011
#
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#
#  This file contains the customisation parameters for a
#  Xilinx CORE Generator IP GUI. It is strongly recommended
#  that you do not manually alter this file as it may cause
#  unexpected and unsupported behavior.
#
##############################################################
#
#  Generated from component: xilinx.com:ip:mig:3.61
#
##############################################################
#
# BEGIN Project Options
SET addpads = false
SET asysymbol = true
SET busformat = BusFormatParenNotRipped
SET createndf = false
SET designentry = VHDL
SET device = xc4vlx60
SET devicefamily = virtex4
SET flowvendor = Synplicity
SET formalverification = false
SET foundationsym = false
SET implementationfiletype = Ngc
SET package = ff668
SET removerpms = false
SET simulationfiles = Behavioral
SET speedgrade = -10
SET verilogsim = false
SET vhdlsim = true
# END Project Options
# BEGIN Select
SELECT MIG family Xilinx,_Inc. 3.61
# END Select
# BEGIN Parameters
CSET component_name=mig_36_1
CSET xml_input_file=./mig.prj
# END Parameters
GENERATE
# CRC: c0675b69
