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###############################################################################
##   ____  ____
##  /   /\/   /
## /___/  \  /    Vendor             : Xilinx
## \   \   \/     Version            : 3.7
##  \   \         Application        : MIG
##  /   /         Filename           : sim.do
## /___/   /\     Date Last Modified : $Date: 2010/10/05 16:43:05 $
## \   \  /  \    Date Created       : Mon Jun 23 2008
##  \___\/\___\
##
## Device           : Virtex-6
## Purpose          :
##                   Sample sim .do file to compile and simulate memory interface
##                   design and run the simulation for specified period of time.
##                   Display the waveforms that are listed with "add wave" command.
## Assumptions      :
##                   Simulation takes place in \sim folder of MIG output directory.
## Reference        :
## Revision History :
###############################################################################

#vlib work

#Map the required libraries here#
#vlib modelsim
#vlib modelsim/unisims_ver
#vmap unisims_ver modelsim/unisims_ver
#vmap unisim <unisim lib path>
#vmap secureip <secureip lib path>

#Compile all modules#
#vlog  ../rtl/ip_top/ddr2_ddr3_chipscope.*
#vlog  ../rtl/ip_top/*
#vlog  ../rtl/controller/*
#vlog  ../rtl/phy/*
#vlog  ../rtl/ui/*
#vlog  ../rtl/ecc/*


#Compile all traffic_gen modules#
#vlog  ../rtl/traffic_gen/*

#Compile files in sim folder (excluding model parameter file)#
#$XILINX variable must be set
#vlog  $env(XILINX)/verilog/src/glbl.v
#vlog  ../sim/wiredly.*
#vlog  ../sim/sim_tb_top.*


#Pass the parameters for memory model parameter file#
#vlog  +incdir+. +define+x1Gb +define+sg187E +define+x16 ddr3_model.v

#Load the design. Use required libraries.#
vsim -t fs -novopt +notimingchecks -L unisims_ver work.sim_tb_top glbl

onerror {resume}
#Log all the objects in design. These will appear in .wlf file#
log -r /*
#View sim_tb_top signals in waveform#
add wave sim:/sim_tb_top/*
#Change radix to Hexadecimal#
radix hex
#Supress Numeric Std package and Arith package warnings.#
#For VHDL designs we get some warnings due to unknown values on some signals at startup#
# ** Warning: NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0#
#We may also get some Arithmetic packeage warnings because of unknown values on#
#some of the signals that are used in an Arithmetic operation.#
#In order to suppress these warnings, we use following two commands#
set NumericStdNoWarnings 1
set StdArithNoWarnings 1

#Choose simulation run time by inserting a breakpoint and then run for specified #
#period. For more details, refer to user guide (UG406).#
when {/sim_tb_top/phy_init_done = 1} {
if {[when -label a_100] == ""} {
when -label a_100 { $now = 50 us } {
nowhen a_100
report simulator control
report simulator state
if {[examine /sim_tb_top/error] == 0} {
echo "TEST PASSED"
stop
}
if {[examine /sim_tb_top/error] != 0} {
echo "TEST FAILED: DATA ERROR"
stop
}
}
}
}

#In case calibration fails to complete, choose the run time and then stop#
when {$now = @1000 us and /sim_tb_top/phy_init_done != 1} {
echo "TEST FAILED: CALIBRATION DID NOT COMPLETE"
stop
}

run -all
stop
