NET "clk48" LOC = L22;
NET "clk48" PERIOD = 20.833333 ns HIGH 50 %;

NET "reset" LOC = AB17;
NET "reset" IOSTANDARD=LVTTL;
NET "reset" PULLDOWN;
NET "reset" TIG;

NET "rxd1"  LOC = "A18";					# Pin A12
NET "txd1"  LOC = "D17" | DRIVE = 8 | SLEW = SLOW;		# Pin A13
NET "dsurx" LOC = "A17";					# Pin A14
NET "dsutx" LOC = "C14" | DRIVE = 8 | SLEW = SLOW;		# Pin A15
								# Pin A16 +3.3v
NET "dsubre"  LOC = "A11";					# Pin A17
NET "dsuact"  LOC = "C13";					# Pin A18

NET "rxd1" IOSTANDARD=LVTTL;
NET "txd1" IOSTANDARD=LVTTL;
NET "dsurx" IOSTANDARD=LVTTL;
NET "dsutx" IOSTANDARD=LVTTL;
NET "dsubre" IOSTANDARD=LVTTL;
NET "dsuact" IOSTANDARD=LVTTL;

##### SD card

#NET "sd_sck" LOC = "H11";
#NET "sd_dat3" LOC = "H14";
#NET "sd_dat" LOC = "P10";
#NET "sd_cmd" LOC = "H13";

##### DDR SDRAM

# --- MIG37 ---
NET "mig_gen.ddrc/MCB_inst/memc?_wrapper_inst/memc?_mcb_raw_wrapper_inst/selfrefresh_mcb_mode" TIG;
NET "mig_gen.ddrc/MCB_inst/c?_pll_lock" TIG;
NET "mig_gen.ddrc/MCB_inst/memc?_wrapper_inst/memc?_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/CKE_Train" TIG; ## This path exists for DDR2 only

# --- MIG39 ---
INST "mig_gen.ddrc/MCB_inst/memc?_wrapper_inst/memc?_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/DONE_SOFTANDHARD_CAL*" TIG;

CONFIG VCCAUX=2.5; # Valid values are 2.5 and 3.3
#CONFIG MCB_PERFORMANCE= STANDARD;
CONFIG MCB_PERFORMANCE= EXTENDED;

############################################################################
## I/O TERMINATION                                                          
############################################################################
NET "mcb3_dram_dq[*]"                                 IN_TERM = NONE;
NET "mcb3_dram_dqs"                                   IN_TERM = NONE;
NET "mcb3_dram_dqs_n"                                 IN_TERM = NONE;
NET "mcb3_dram_udqs"                                  IN_TERM = NONE;
NET "mcb3_dram_udqs_n"                                IN_TERM = NONE;

#NET  "mcb3_dram_dq[*]"                                OUT_TERM = UNTUNED_50;
NET  "mcb3_dram_a[*]"                                 OUT_TERM = UNTUNED_50; 
NET  "mcb3_dram_ba[*]"                                OUT_TERM = UNTUNED_50; 
NET  "mcb3_dram_ck"                                   OUT_TERM = UNTUNED_50; 
NET  "mcb3_dram_ck_n"                                 OUT_TERM = UNTUNED_50; 
NET  "mcb3_dram_cke"                                  OUT_TERM = UNTUNED_50; 
NET  "mcb3_dram_ras_n"                                OUT_TERM = UNTUNED_50; 
NET  "mcb3_dram_cas_n"                                OUT_TERM = UNTUNED_50; 
NET  "mcb3_dram_we_n"                                 OUT_TERM = UNTUNED_50; 
#NET  "mcb3_dram_odt"                                  OUT_TERM = UNTUNED_50; 
NET  "mcb3_dram_dm"                                   OUT_TERM = UNTUNED_50; 
NET  "mcb3_dram_udm"                                  OUT_TERM = UNTUNED_50; 

############################################################################
# I/O STANDARDS 
############################################################################

NET  "mcb3_dram_dq[*]"                               IOSTANDARD = SSTL18_II ;
NET  "mcb3_dram_a[*]"                                IOSTANDARD = SSTL18_II ;
NET  "mcb3_dram_ba[*]"                               IOSTANDARD = SSTL18_II ;
NET  "mcb3_dram_dqs"                                 IOSTANDARD = DIFF_SSTL18_II ;
NET  "mcb3_dram_udqs"                                IOSTANDARD = DIFF_SSTL18_II ;
NET  "mcb3_dram_dqs_n"                               IOSTANDARD = DIFF_SSTL18_II ;
NET  "mcb3_dram_udqs_n"                              IOSTANDARD = DIFF_SSTL18_II ;
NET  "mcb3_dram_ck"                                  IOSTANDARD = DIFF_SSTL18_II ;
NET  "mcb3_dram_ck_n"                                IOSTANDARD = DIFF_SSTL18_II ;
NET  "mcb3_dram_cke"                                 IOSTANDARD = SSTL18_II ;
NET  "mcb3_dram_ras_n"                               IOSTANDARD = SSTL18_II ;
NET  "mcb3_dram_cas_n"                               IOSTANDARD = SSTL18_II ;
NET  "mcb3_dram_we_n"                                IOSTANDARD = SSTL18_II ;
NET  "mcb3_dram_dm"                                  IOSTANDARD = SSTL18_II ;
NET  "mcb3_dram_udm"                                 IOSTANDARD = SSTL18_II ;
NET  "mcb3_rzq"                                      IOSTANDARD = SSTL18_II ;
NET  "mcb3_zio"                                      IOSTANDARD = SSTL18_II ;
############################################################################
# MCB 3
# Pin Location Constraints for Clock, Masks, Address, and Controls
############################################################################

NET  "mcb3_dram_a[0]"                            LOC = "M5" ;
NET  "mcb3_dram_a[10]"                           LOC = "K6" ;
NET  "mcb3_dram_a[11]"                           LOC = "B1" ;
NET  "mcb3_dram_a[12]"                           LOC = "J4" ;
NET  "mcb3_dram_a[1]"                            LOC = "L4" ;
NET  "mcb3_dram_a[2]"                            LOC = "K3" ;
NET  "mcb3_dram_a[3]"                            LOC = "M4" ;
NET  "mcb3_dram_a[4]"                            LOC = "K5" ;
NET  "mcb3_dram_a[5]"                            LOC = "G3" ;
NET  "mcb3_dram_a[6]"                            LOC = "G1" ;
NET  "mcb3_dram_a[7]"                            LOC = "K4" ;
NET  "mcb3_dram_a[8]"                            LOC = "C3" ;
NET  "mcb3_dram_a[9]"                            LOC = "C1" ;
NET  "mcb3_dram_ba[0]"                           LOC = "E3" ;
NET  "mcb3_dram_ba[1]"                           LOC = "E1" ;
NET  "mcb3_dram_ba[2]"                           LOC = "D1" ;
NET  "mcb3_dram_cas_n"                           LOC = "P3" ;
NET  "mcb3_dram_ck"                              LOC = "F2" ;
NET  "mcb3_dram_ck_n"                            LOC = "F1" ;
NET  "mcb3_dram_cke"                             LOC = "J6" ;
NET  "mcb3_dram_dm"                              LOC = "H1" ;
NET  "mcb3_dram_dq[0]"                           LOC = "N3" ;
NET  "mcb3_dram_dq[10]"                          LOC = "R3" ;
NET  "mcb3_dram_dq[11]"                          LOC = "R1" ;
NET  "mcb3_dram_dq[12]"                          LOC = "U3" ;
NET  "mcb3_dram_dq[13]"                          LOC = "U1" ;
NET  "mcb3_dram_dq[14]"                          LOC = "V2" ;
NET  "mcb3_dram_dq[15]"                          LOC = "V1" ;
NET  "mcb3_dram_dq[1]"                           LOC = "N1" ;
NET  "mcb3_dram_dq[2]"                           LOC = "M2" ;
NET  "mcb3_dram_dq[3]"                           LOC = "M1" ;
NET  "mcb3_dram_dq[4]"                           LOC = "J3" ;
NET  "mcb3_dram_dq[5]"                           LOC = "J1" ;
NET  "mcb3_dram_dq[6]"                           LOC = "K2" ;
NET  "mcb3_dram_dq[7]"                           LOC = "K1" ;
NET  "mcb3_dram_dq[8]"                           LOC = "P2" ;
NET  "mcb3_dram_dq[9]"                           LOC = "P1" ;
NET  "mcb3_dram_dqs"                             LOC = "L3" ;
NET  "mcb3_dram_dqs_n"                           LOC = "L1" ;
NET  "mcb3_dram_ras_n"                           LOC = "N4" ;
NET  "mcb3_dram_udm"                             LOC = "H2" ;
NET  "mcb3_dram_udqs"                            LOC = "T2" ;
NET  "mcb3_dram_udqs_n"                          LOC = "T1" ;
NET  "mcb3_dram_we_n"                            LOC = "D2" ;

NET  "mcb3_rzq"                                  LOC = "AA2" ;
NET  "mcb3_zio"                                  LOC = "Y2" ;
