############################################################################
## 
##  Xilinx, Inc. 2006            www.xilinx.com 
##  Mon Aug 30 10:34:47 2010
##  Generated by MIG Version 3.6
##  
############################################################################
##  File name :       example_top.ucf
## 
##  Details :     Constraints file
##                    FPGA family:       virtex6
##                    FPGA:              xc6vlx240t-ff1156
##                    Speedgrade:        -1
##                    Design Entry:      VERILOG
##                    Design:            with Test bench
##                    No.Of Controllers: 1
##
############################################################################ 
##  Modifications for ML605 with LX240T FPGA
##  Start with UCF file generated by MIG 3.4 (ISE 12.1 build M.53.d)
##     
##  1. Majority of ML605 board specific pin assignments entered via MIG3.4 GUI!
##     A. Add LOC and IOSTANDARD for LED indicator "heartbeat" 
##     B. Add LOC and IOSTANDARD for LED indicator "pll_lock" 
##     C. Comment out "sda" and "scl" signals 
##     D. ML605 DCI_CASCADE is correct as defined in MIG3.4 GUI.
##        BANK 26 = left column I/O master; BANK 36 = right column I/O master 
##  2. Change IOSTANDARD for sys_rst to SSTL15 
##  3. Board specific clocking definitions
##     A. Default MIG 3.5 example design assumes 2 clock inputs to design:
##        1. clk_ref to IDELAY_CTRL element (200 MHz)
##        2. sys_clk to PLL circuit (SMA inputs)
##     B. ML605 single clock source, modify constraint file to use 200 MHz 
##        LVDS clock "clk_ref" input for DDR3 SODIMM design @800 Mbps data rate. 
##        - Delete sys_clk_p and sys_clk_n inputs (HDL and LOC constraints)
##        - Comment out sys_clk timing specification
##        - Modify TS_MC_PHY_INIT_SEL to use value "2.5 ns" in multiplication 
##  4. Optional: comment out CONFIG_PROHIBIT lines (pins reserved for MIG)
##     Since this design has LOC'ed I/O don't need to reserve these pins.
##  5. ML605 MIG3.4 BUFIO pin assignments
##         BUFIO:0 pin C13 => X2Y137
##         BUFIO:1 pin L13 => X2Y141
##         BUFIO:2 pin K14 => X2Y143
##         BUFIO:3 pin F21 => X1Y179
##         BUFIO:4 pin B20 => X1Y181
##         BUFIO:5 pin F25 => X1Y137
##         BUFIO:6 pin C28 => X1Y141
##         BUFIO:7 pin D24 => X1Y143
##  6. ML605 MIG3.4 BUFR pin assignments
##         BUFR:0 pin M12 => X2Y139
##         BUFR:1 pin C29 => X1Y139
##
############################################################################
# Timing constraints                                                        #
############################################################################
## ML605 comment out the following 2 lines for single 200MHz input clock
## NET "sys_clk_p" TNM_NET = TNM_sys_clk;
## TIMESPEC "TS_sys_clk" = PERIOD "TNM_sys_clk" 2.5 ns;

NET "clk_ref_p" TNM_NET = TNM_clk_ref;
TIMESPEC "TS_clk_ref" = PERIOD "TNM_clk_ref" 5 ns ;

# Constrain BUFR clocks used to synchronize data from IOB to fabric logic
# Note that ISE cannot infer this from other PERIOD constraints because
# of the use of OSERDES blocks in the BUFR clock generation path
NET "mig_gen.ddr3ctrl/u_memc_ui_top/u_mem_intfc/phy_top0/clk_rsync(?)" TNM_NET = TNM_clk_rsync;
TIMESPEC "TS_clk_rsync" = PERIOD "TNM_clk_rsync" 5 ns;

# Paths between DQ/DQS ISERDES.Q outputs and CLB flops clocked by falling 
# edge of BUFR will by design only be used if DYNCLKDIVSEL is asserted for 
# that particular flop. Mark this path as being a full-cycle, rather than 
# a half cycle path for timing purposes. NOTE: This constraint forces full-
# cycle timing to be applied globally for all rising->falling edge paths 
# in all resynchronizaton clock domains. If the user had modified the logic
# in the resync clock domain such that other rising->falling edge paths 
# exist, then constraint below should be modified to utilize pattern 
# matching to specific affect only the DQ/DQS ISERDES.Q outputs
TIMEGRP "TG_clk_rsync_rise" = RISING  "TNM_clk_rsync";
TIMEGRP "TG_clk_rsync_fall" = FALLING "TNM_clk_rsync";
TIMESPEC "TS_clk_rsync_rise_to_fall" = 
  FROM "TG_clk_rsync_rise" TO "TG_clk_rsync_fall" "TS_clk_ref" * 1;

# Signal to select between controller and physical layer signals. Four divided by two clock
# cycles (8 memory clock cycles) are provided by design for the signal to settle down.
# Used only by the phy modules.
INST "mig_gen.ddr3ctrl/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_init/u_ff_phy_init_data_sel" TNM = "TNM_PHY_INIT_SEL";
TIMESPEC "TS_MC_PHY_INIT_SEL" = FROM "TNM_PHY_INIT_SEL" TO FFS = 10 ns;  ## = "2.5ns * 4" ML605 single clock

disable = reg_sr_o;
disable = reg_sr_r;
############################################################################
########################################################################
# Controller 0
# Memory Device: DDR3_SDRAM->SODIMMs->MT4JSF6464HY-1G1
# Data Width:     64
# Frequency:      400
# Time Period:      2500
# Data Mask:     1
########################################################################


################################################################################
# I/O STANDARDS
################################################################################

NET  "ddr3_dq(*)"                               IOSTANDARD = SSTL15_T_DCI;
NET  "ddr3_addr(*)"                             IOSTANDARD = SSTL15;
NET  "ddr3_ba(*)"                               IOSTANDARD = SSTL15;
NET  "ddr3_ras_n"                               IOSTANDARD = SSTL15;
NET  "ddr3_cas_n"                               IOSTANDARD = SSTL15;
NET  "ddr3_we_n"                                IOSTANDARD = SSTL15;
NET  "ddr3_reset_n"                             IOSTANDARD = SSTL15;
NET  "ddr3_cke(*)"                              IOSTANDARD = SSTL15;
NET  "ddr3_odt(*)"                              IOSTANDARD = SSTL15;
NET  "ddr3_cs_n(*)"                             IOSTANDARD = SSTL15;
NET  "ddr3_dm(*)"                               IOSTANDARD = SSTL15;
## NET  "sys_clk_p"                                IOSTANDARD = LVDS_25;
## NET  "sys_clk_n"                                IOSTANDARD = LVDS_25;
NET  "clk_ref_p"                                IOSTANDARD = LVDS_25;
NET  "clk_ref_n"                                IOSTANDARD = LVDS_25;
## NET  "sda"                                      IOSTANDARD = LVCMOS25;
## NET  "scl"                                      IOSTANDARD = LVCMOS25;
NET  "reset"                                  IOSTANDARD = SSTL15;      ## ML605 
#NET  "phy_init_done"                            IOSTANDARD = LVCMOS25;
NET  "errorn"                                    IOSTANDARD = LVCMOS25;
NET  "ddr3_dqs_p(*)"                            IOSTANDARD = DIFF_SSTL15_T_DCI;
NET  "ddr3_dqs_n(*)"                            IOSTANDARD = DIFF_SSTL15_T_DCI;
NET  "ddr3_ck_p(*)"                             IOSTANDARD = DIFF_SSTL15;
NET  "ddr3_ck_n(*)"                             IOSTANDARD = DIFF_SSTL15;

################################################################################
##SAVE attributes to reserve the pins
################################################################################
## NET  "sda"                                      S;
## NET  "scl"                                      S;

###############################################################################
#DCI_CASCADING
#Syntax : CONFIG DCI_CASCADE = "<master> <slave1> <slave2> ..";
###############################################################################
CONFIG DCI_CASCADE = "26 25";
CONFIG DCI_CASCADE = "36 35";


##################################################################################
# Location Constraints
##################################################################################
NET  "ddr3_dq(0)"                                LOC = "J11" ;          #Bank 35
NET  "ddr3_dq(1)"                                LOC = "E13" ;          #Bank 35
NET  "ddr3_dq(2)"                                LOC = "F13" ;          #Bank 35
NET  "ddr3_dq(3)"                                LOC = "K11" ;          #Bank 35
NET  "ddr3_dq(4)"                                LOC = "L11" ;          #Bank 35
NET  "ddr3_dq(5)"                                LOC = "K13" ;          #Bank 35
NET  "ddr3_dq(6)"                                LOC = "K12" ;          #Bank 35
NET  "ddr3_dq(7)"                                LOC = "D11" ;          #Bank 35
NET  "ddr3_dq(8)"                                LOC = "M13" ;          #Bank 35
NET  "ddr3_dq(9)"                                LOC = "J14" ;          #Bank 35
NET  "ddr3_dq(10)"                               LOC = "B13" ;          #Bank 35
NET  "ddr3_dq(11)"                               LOC = "B12" ;          #Bank 35
NET  "ddr3_dq(12)"                               LOC = "G10" ;          #Bank 35
NET  "ddr3_dq(13)"                               LOC = "M11" ;          #Bank 35
NET  "ddr3_dq(14)"                               LOC = "C12" ;          #Bank 35
NET  "ddr3_dq(15)"                               LOC = "A11" ;          #Bank 35
NET  "ddr3_dq(16)"                               LOC = "G11" ;          #Bank 35
NET  "ddr3_dq(17)"                               LOC = "F11" ;          #Bank 35
NET  "ddr3_dq(18)"                               LOC = "D14" ;          #Bank 35
NET  "ddr3_dq(19)"                               LOC = "C14" ;          #Bank 35
NET  "ddr3_dq(20)"                               LOC = "G12" ;          #Bank 35
NET  "ddr3_dq(21)"                               LOC = "G13" ;          #Bank 35
NET  "ddr3_dq(22)"                               LOC = "F14" ;          #Bank 35
NET  "ddr3_dq(23)"                               LOC = "H14" ;          #Bank 35
NET  "ddr3_dq(24)"                               LOC = "C19" ;          #Bank 26
NET  "ddr3_dq(25)"                               LOC = "G20" ;          #Bank 26
NET  "ddr3_dq(26)"                               LOC = "E19" ;          #Bank 26
NET  "ddr3_dq(27)"                               LOC = "F20" ;          #Bank 26
NET  "ddr3_dq(28)"                               LOC = "A20" ;          #Bank 26
NET  "ddr3_dq(29)"                               LOC = "A21" ;          #Bank 26
NET  "ddr3_dq(30)"                               LOC = "E22" ;          #Bank 26
NET  "ddr3_dq(31)"                               LOC = "E23" ;          #Bank 26
NET  "ddr3_dq(32)"                               LOC = "G21" ;          #Bank 26
NET  "ddr3_dq(33)"                               LOC = "B21" ;          #Bank 26
NET  "ddr3_dq(34)"                               LOC = "A23" ;          #Bank 26
NET  "ddr3_dq(35)"                               LOC = "A24" ;          #Bank 26
NET  "ddr3_dq(36)"                               LOC = "C20" ;          #Bank 26
NET  "ddr3_dq(37)"                               LOC = "D20" ;          #Bank 26
NET  "ddr3_dq(38)"                               LOC = "J20" ;          #Bank 26
NET  "ddr3_dq(39)"                               LOC = "G22" ;          #Bank 26
NET  "ddr3_dq(40)"                               LOC = "D26" ;          #Bank 25
NET  "ddr3_dq(41)"                               LOC = "F26" ;          #Bank 25
NET  "ddr3_dq(42)"                               LOC = "B26" ;          #Bank 25
NET  "ddr3_dq(43)"                               LOC = "E26" ;          #Bank 25
NET  "ddr3_dq(44)"                               LOC = "C24" ;          #Bank 25
NET  "ddr3_dq(45)"                               LOC = "D25" ;          #Bank 25
NET  "ddr3_dq(46)"                               LOC = "D27" ;          #Bank 25
NET  "ddr3_dq(47)"                               LOC = "C25" ;          #Bank 25
NET  "ddr3_dq(48)"                               LOC = "C27" ;          #Bank 25
NET  "ddr3_dq(49)"                               LOC = "B28" ;          #Bank 25
NET  "ddr3_dq(50)"                               LOC = "D29" ;          #Bank 25
NET  "ddr3_dq(51)"                               LOC = "B27" ;          #Bank 25
NET  "ddr3_dq(52)"                               LOC = "G27" ;          #Bank 25
NET  "ddr3_dq(53)"                               LOC = "A28" ;          #Bank 25
NET  "ddr3_dq(54)"                               LOC = "E24" ;          #Bank 25
NET  "ddr3_dq(55)"                               LOC = "G25" ;          #Bank 25
NET  "ddr3_dq(56)"                               LOC = "F28" ;          #Bank 25
NET  "ddr3_dq(57)"                               LOC = "B31" ;          #Bank 25
NET  "ddr3_dq(58)"                               LOC = "H29" ;          #Bank 25
NET  "ddr3_dq(59)"                               LOC = "H28" ;          #Bank 25
NET  "ddr3_dq(60)"                               LOC = "B30" ;          #Bank 25
NET  "ddr3_dq(61)"                               LOC = "A30" ;          #Bank 25
NET  "ddr3_dq(62)"                               LOC = "E29" ;          #Bank 25
NET  "ddr3_dq(63)"                               LOC = "F29" ;          #Bank 25
NET  "ddr3_addr(12)"                             LOC = "H15" ;          #Bank 36
NET  "ddr3_addr(11)"                             LOC = "M15" ;          #Bank 36
NET  "ddr3_addr(10)"                             LOC = "M16" ;          #Bank 36
NET  "ddr3_addr(9)"                              LOC = "F15" ;          #Bank 36
NET  "ddr3_addr(8)"                              LOC = "G15" ;          #Bank 36
NET  "ddr3_addr(7)"                              LOC = "B15" ;          #Bank 36
NET  "ddr3_addr(6)"                              LOC = "A15" ;          #Bank 36
NET  "ddr3_addr(5)"                              LOC = "J17" ;          #Bank 36
NET  "ddr3_addr(4)"                              LOC = "D16" ;          #Bank 36
NET  "ddr3_addr(3)"                              LOC = "E16" ;          #Bank 36
NET  "ddr3_addr(2)"                              LOC = "B16" ;          #Bank 36
NET  "ddr3_addr(1)"                              LOC = "A16" ;          #Bank 36
NET  "ddr3_addr(0)"                              LOC = "L14" ;          #Bank 36
NET  "ddr3_ba(2)"                                LOC = "L15" ;          #Bank 36
NET  "ddr3_ba(1)"                                LOC = "J19" ;          #Bank 36
NET  "ddr3_ba(0)"                                LOC = "K19" ;          #Bank 36
NET  "ddr3_ras_n"                                LOC = "L19" ;          #Bank 36
NET  "ddr3_cas_n"                                LOC = "C17" ;          #Bank 36
NET  "ddr3_we_n"                                 LOC = "B17" ;          #Bank 36
NET  "ddr3_reset_n"                              LOC = "E18" ;          #Bank 36
NET  "ddr3_cke(0)"                               LOC = "M18" ;          #Bank 36
NET  "ddr3_odt(0)"                               LOC = "F18" ;          #Bank 36
NET  "ddr3_cs_n(0)"                              LOC = "K18" ;          #Bank 36
NET  "ddr3_dm(0)"                                LOC = "E11" ;          #Bank 35
NET  "ddr3_dm(1)"                                LOC = "B11" ;          #Bank 35
NET  "ddr3_dm(2)"                                LOC = "E14" ;          #Bank 35
NET  "ddr3_dm(3)"                                LOC = "D19" ;          #Bank 26
NET  "ddr3_dm(4)"                                LOC = "B22" ;          #Bank 26
NET  "ddr3_dm(5)"                                LOC = "A26" ;          #Bank 25
NET  "ddr3_dm(6)"                                LOC = "A29" ;          #Bank 25
NET  "ddr3_dm(7)"                                LOC = "A31" ;          #Bank 25
## NET  "sys_clk_p"                                 LOC = "J9" ;          #Bank 34
## NET  "sys_clk_n"                                 LOC = "H9" ;          #Bank 34
NET  "clk_ref_p"                                 LOC = "J9" ;          #Bank 34
NET  "clk_ref_n"                                 LOC = "H9" ;          #Bank 34
## NET  "sda"                                       LOC = "F9" ;          #Bank 34
## NET  "scl"                                       LOC = "F10" ;          #Bank 34
NET  "reset"                                   LOC = "H10" ;          #ML605 CPU_RESET switch
#NET  "phy_init_done"                             LOC = "AE23" ;         #ML605 GPIO LED 3
NET  "errorn"                                     LOC = "AD24" ;         #ML605 GPIO LED 2
NET  "ddr3_dqs_p(0)"                             LOC = "D12" ;          #Bank 35
NET  "ddr3_dqs_n(0)"                             LOC = "E12" ;          #Bank 35
NET  "ddr3_dqs_p(1)"                             LOC = "H12" ;          #Bank 35
NET  "ddr3_dqs_n(1)"                             LOC = "J12" ;          #Bank 35
NET  "ddr3_dqs_p(2)"                             LOC = "A13" ;          #Bank 35
NET  "ddr3_dqs_n(2)"                             LOC = "A14" ;          #Bank 35
NET  "ddr3_dqs_p(3)"                             LOC = "H19" ;          #Bank 26
NET  "ddr3_dqs_n(3)"                             LOC = "H20" ;          #Bank 26
NET  "ddr3_dqs_p(4)"                             LOC = "B23" ;          #Bank 26
NET  "ddr3_dqs_n(4)"                             LOC = "C23" ;          #Bank 26
NET  "ddr3_dqs_p(5)"                             LOC = "B25" ;          #Bank 25
NET  "ddr3_dqs_n(5)"                             LOC = "A25" ;          #Bank 25
NET  "ddr3_dqs_p(6)"                             LOC = "H27" ;          #Bank 25
NET  "ddr3_dqs_n(6)"                             LOC = "G28" ;          #Bank 25
NET  "ddr3_dqs_p(7)"                             LOC = "C30" ;          #Bank 25
NET  "ddr3_dqs_n(7)"                             LOC = "D30" ;          #Bank 25
NET  "ddr3_ck_p(0)"                              LOC = "G18" ;          #Bank 36
NET  "ddr3_ck_n(0)"                              LOC = "H18" ;          #Bank 36


##################################################################################################
##The following locations must be reserved and cannot be used for external I/O because          ##
##the I/O elements associated with these sites (IODELAY, OSERDES, and associated routing)       ##
##are used to generate and route the clocks necessary for read data capture and synchronization ##
##to the core clock domain. These pins should not be routed out on the user's PCB               ##
##################################################################################################

##################################################################################################
##The logic of this pin is used internally to drive a BUFR in the column. This chosen pin must  ##
##be a clock pin capable of spanning to all of the banks containing data bytes in the particular##
##column. That is, all byte groups must be within +/- 1 bank of this pin. This pin cannot be    ##
##used for other functions and should not be connected externally. If a different pin is chosen,##
##he corresponding LOC constraint must also be changed.                                         ##
##################################################################################################

CONFIG PROHIBIT = C29,M12;

######################################################################################
##Place RSYNC OSERDES and IODELAY:                                                  ##
######################################################################################

##Site: C29 -- Bank 25
INST "mig_gen.ddr3ctrl/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rdclk_gen/gen_loop_col1.u_oserdes_rsync"
  LOC = "OLOGIC_X1Y139";
INST "mig_gen.ddr3ctrl/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rdclk_gen/gen_loop_col1.u_odelay_rsync"
  LOC = "IODELAY_X1Y139";

INST "mig_gen.ddr3ctrl/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rdclk_gen/gen_loop_col1.u_bufr_rsync"
  LOC = "BUFR_X1Y6";

##Site: M12 -- Bank 35
INST "mig_gen.ddr3ctrl/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rdclk_gen/gen_loop_col0.u_oserdes_rsync"
  LOC = "OLOGIC_X2Y139";
INST "mig_gen.ddr3ctrl/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rdclk_gen/gen_loop_col0.u_odelay_rsync"
  LOC = "IODELAY_X2Y139";

INST "mig_gen.ddr3ctrl/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rdclk_gen/gen_loop_col0.u_bufr_rsync"
  LOC = "BUFR_X2Y6";

##################################################################################################
##The logic of this pin is used internally to drive a BUFIO for the byte group. Any clock       ##
##capable pin in the same bank as the data byte group (DQS, DQ, DM if used) can be used for     ##
##this pin. This pin cannot be used for other functions and should not be connected externally. ##
##If a different pin is chosen, the corresponding LOC constraint must also be changed.          ##
##################################################################################################

CONFIG PROHIBIT = B20,C13,C28,D24,F21,F25,K14,L13;

######################################################################################
##Place CPT OSERDES and IODELAY:                                                    ##
######################################################################################

##Site: C13 -- Bank 35
INST "mig_gen.ddr3ctrl/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rdclk_gen/gen_ck_cpt*0*u_oserdes_cpt"
  LOC = "OLOGIC_X2Y137";
INST "mig_gen.ddr3ctrl/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rdclk_gen/gen_ck_cpt*0*u_odelay_cpt"
  LOC = "IODELAY_X2Y137";

##Site: L13 -- Bank 35
INST "mig_gen.ddr3ctrl/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rdclk_gen/gen_ck_cpt*1*u_oserdes_cpt"
  LOC = "OLOGIC_X2Y141";
INST "mig_gen.ddr3ctrl/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rdclk_gen/gen_ck_cpt*1*u_odelay_cpt"
  LOC = "IODELAY_X2Y141";

##Site: K14 -- Bank 35
INST "mig_gen.ddr3ctrl/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rdclk_gen/gen_ck_cpt*2*u_oserdes_cpt"
  LOC = "OLOGIC_X2Y143";
INST "mig_gen.ddr3ctrl/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rdclk_gen/gen_ck_cpt*2*u_odelay_cpt"
  LOC = "IODELAY_X2Y143";

##Site: F21 -- Bank 26
INST "mig_gen.ddr3ctrl/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rdclk_gen/gen_ck_cpt*3*u_oserdes_cpt"
  LOC = "OLOGIC_X1Y179";
INST "mig_gen.ddr3ctrl/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rdclk_gen/gen_ck_cpt*3*u_odelay_cpt"
  LOC = "IODELAY_X1Y179";

##Site: B20 -- Bank 26
INST "mig_gen.ddr3ctrl/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rdclk_gen/gen_ck_cpt*4*u_oserdes_cpt"
  LOC = "OLOGIC_X1Y181";
INST "mig_gen.ddr3ctrl/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rdclk_gen/gen_ck_cpt*4*u_odelay_cpt"
  LOC = "IODELAY_X1Y181";

##Site: F25 -- Bank 25
INST "mig_gen.ddr3ctrl/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rdclk_gen/gen_ck_cpt*5*u_oserdes_cpt"
  LOC = "OLOGIC_X1Y137";
INST "mig_gen.ddr3ctrl/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rdclk_gen/gen_ck_cpt*5*u_odelay_cpt"
  LOC = "IODELAY_X1Y137";

##Site: C28 -- Bank 25
INST "mig_gen.ddr3ctrl/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rdclk_gen/gen_ck_cpt*6*u_oserdes_cpt"
  LOC = "OLOGIC_X1Y141";
INST "mig_gen.ddr3ctrl/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rdclk_gen/gen_ck_cpt*6*u_odelay_cpt"
  LOC = "IODELAY_X1Y141";

##Site: D24 -- Bank 25
INST "mig_gen.ddr3ctrl/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rdclk_gen/gen_ck_cpt*7*u_oserdes_cpt"
  LOC = "OLOGIC_X1Y143";
INST "mig_gen.ddr3ctrl/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rdclk_gen/gen_ck_cpt*7*u_odelay_cpt"
  LOC = "IODELAY_X1Y143";


######################################################################################
## MMCM_ADV CONSTRAINTS                                                             ##
######################################################################################

INST "mig_gen.ddr3ctrl/u_infrastructure/u_mmcm_adv"      LOC = "MMCM_ADV_X0Y8"; #Banks 16, 26, 36



###########################################################################
##  ML605 additions
###########################################################################
#NET  "pll_lock"                 IOSTANDARD = LVCMOS25;
#NET  "heartbeat"                IOSTANDARD = LVCMOS25;

#NET  "heartbeat"                LOC = "AC24";   # ML605 GPIO LED 1
#NET  "pll_lock"                 LOC = "AC22" ;  # ML605 GPIO LED 0


NET "address(0)"                      LOC = "AL8";    ## 29 on U4, A1 on U27
NET "address(1)"                      LOC = "AK8";    ## 25 on U4, B1 on U27
NET "address(2)"                      LOC = "AC9";    ## 24 on U4, C1 on U27
NET "address(3)"                      LOC = "AD10";   ## 23 on U4, D1 on U27
NET "address(4)"                      LOC = "C8";     ## 22 on U4, D2 on U27
NET "address(5)"                      LOC = "B8";     ## 21 on U4, A2 on U27
NET "address(6)"                      LOC = "E9";     ## 20 on U4, C2 on U27
NET "address(7)"                      LOC = "E8";     ## 19 on U4, A3 on U27
NET "address(8)"                      LOC = "A8";     ## 8  on U4, B3 on U27
NET "address(9)"                      LOC = "A9";     ## 7  on U4, C3 on U27
NET "address(10)"                     LOC = "D9";     ## 6  on U4, D3 on U27
NET "address(11)"                     LOC = "C9";     ## 5  on U4, C4 on U27
NET "address(12)"                     LOC = "D10";    ## 4  on U4, A5 on U27
NET "address(13)"                     LOC = "C10";    ## 3  on U4, B5 on U27
NET "address(14)"                     LOC = "F10";    ## 2  on U4, C5 on U27
NET "address(15)"                     LOC = "F9";     ## 1  on U4, D7 on U27
NET "address(16)"                     LOC = "AH8";    ## 55 on U4, D8 on U27
NET "address(17)"                     LOC = "AG8";    ## 18 on U4, A7 on U27
NET "address(18)"                     LOC = "AP9";    ## 17 on U4, B7 on U27
NET "address(19)"                     LOC = "AN9";    ## 16 on U4, C7 on U27
NET "address(20)"                     LOC = "AF10";   ## 11 on U4, C8 on U27
NET "address(21)"                     LOC = "AF9";    ## 10 on U4, A8 on U27
NET "address(22)"                     LOC = "AL9";    ## 9  on U4, G1 on U27
NET "address(23)"                     LOC = "AA23";   ## 26 on U4
NET "data(0)"                      LOC = "AF24";   ## 34 on U4, F2 on U27
NET "data(1)"                      LOC = "AF25";   ## 36 on U4, E2 on U27
NET "data(2)"                      LOC = "W24";    ## 39 on U4, G3 on U27
NET "data(3)"                      LOC = "V24";    ## 41 on U4, E4 on U27
NET "data(4)"                      LOC = "H24";    ## 47 on U4, E5 on U27
NET "data(5)"                      LOC = "H25";    ## 49 on U4, G5 on U27
NET "data(6)"                      LOC = "P24";    ## 51 on U4, G6 on U27
NET "data(7)"                      LOC = "R24";    ## 53 on U4, H7 on U27
NET "data(8)"                      LOC = "G23";    ## 35 on U4, E1 on U27
NET "data(9)"                      LOC = "H23";    ## 37 on U4, E3 on U27
NET "data(10)"                     LOC = "N24";    ## 40 on U4, F3 on U27
NET "data(11)"                     LOC = "N23";    ## 42 on U4, F4 on U27
NET "data(12)"                     LOC = "F23";    ## 48 on U4, F5 on U27
NET "data(13)"                     LOC = "F24";    ## 50 on U4, H5 on U27
NET "data(14)"                     LOC = "L24";    ## 52 on U4, G7 on U27
NET "data(15)"                     LOC = "M23";    ## 54 on U4, E7 on U27
#NET "FLASH_WAIT"                    LOC = "J26";    ## 56 on U4
NET "writen"                    LOC = "AF23";   ## 14 on U4, G8 on U27
NET "oen"                    LOC = "AA24";   ## 32 on U4, F8 on U27
#NET "FPGA_CCLK"                     LOC = "K8";     ##           F1 on U27
NET "alatch"                 LOC = "AC23";   ##           H1 on U27
NET "romsn"                    LOC = "Y24";    ## 30 on U4, B4 on U27 (U10 and switch S2.2 setting select either U4 or U27)
##

NET "erx_col"                       LOC = "AK13";   ## 114 on U80
NET "erx_crs"                       LOC = "AL13";   ## 115 on U80
NET "emdint"                       LOC = "AH14";   ## 32  on U80
NET "emdc"                       LOC = "AP14";   ## 35  on U80
NET "emdio"                      LOC = "AN14";   ## 33  on U80
NET "erstn"                     LOC = "AH13";   ## 36  on U80
NET "erx_clk"                     LOC = "AP11";   ## 7   on U80
NET "erx_dv"                LOC = "AM13";   ## 4   on U80
NET "erxd(0)"                      LOC = "AN13";   ## 3   on U80
NET "erxd(1)"                      LOC = "AF14";   ## 128 on U80
NET "erxd(2)"                      LOC = "AE14";   ## 126 on U80
NET "erxd(3)"                      LOC = "AN12";   ## 125 on U80
NET "erxd(4)"                      LOC = "AM12";   ## 124 on U80
NET "erxd(5)"                      LOC = "AD11";   ## 123 on U80
NET "erxd(6)"                      LOC = "AC12";   ## 121 on U80
NET "erxd(7)"                      LOC = "AC13";   ## 120 on U80
NET "erx_er"                      LOC = "AG12";   ## 9   on U80
NET "etx_clk"                     LOC = "AD12";   ## 10  on U80
NET "etx_en"                LOC = "AJ10";   ## 16  on U80
NET "egtx_clk"                LOC = "AH12";   ## 14  on U80
NET "etxd(0)"                      LOC = "AM11";   ## 18  on U80
NET "etxd(1)"                      LOC = "AL11";   ## 19  on U80
NET "etxd(2)"                      LOC = "AG10";   ## 20  on U80
NET "etxd(3)"                      LOC = "AG11";   ## 24  on U80
NET "etxd(4)"                      LOC = "AL10";   ## 25  on U80
NET "etxd(5)"                      LOC = "AM10";   ## 26  on U80
NET "etxd(6)"                      LOC = "AE11";   ## 28  on U80
NET "etxd(7)"                      LOC = "AF11";   ## 29  on U80
NET "etx_er"                      LOC = "AH10";   ## 13  on U80

NET "dsurx"                      LOC = "J24";    ## 24  on U34
NET "dsutx"                      LOC = "J25";    ## 25  on U34

#NET "GPIO_DIP_SW1"                  LOC = "D22";    ## 1   on SW1 DIP switch (active-high)
#NET "GPIO_DIP_SW2"                  LOC = "C22";    ## 2   on SW1 DIP switch (active-high)
#NET "GPIO_DIP_SW3"                  LOC = "L21";    ## 3   on SW1 DIP switch (active-high)
#NET "GPIO_DIP_SW4"                  LOC = "L20";    ## 4   on SW1 DIP switch (active-high)
#NET "GPIO_DIP_SW5"                  LOC = "C18";    ## 5   on SW1 DIP switch (active-high)
NET "dsubre"                  LOC = "B18";    ## 6   on SW1 DIP switch (active-high)
#NET "GPIO_DIP_SW7"                  LOC = "K22";    ## 7   on SW1 DIP switch (active-high)
#NET "GPIO_DIP_SW8"                  LOC = "K21";    ## 8   on SW1 DIP switch (active-high)
##

NET "led(0)"                    LOC = "AC22";   ## 2   on LED DS12, 1 on J62
NET "led(1)"                    LOC = "AC24";   ## 2   on LED DS11, 2 on J62
NET "led(2)"                    LOC = "AE22";   ## 2   on LED DS9,  3 on J62
NET "led(3)"                    LOC = "AE23";   ## 2   on LED DS10, 4 on J62
NET "led(4)"                    LOC = "AB23";   ## 2   on LED DS15, 5 on J62
NET "led(4)"                    LOC = "AB23";   ## 2   on LED DS15, 5 on J62
NET "led(5)"                    LOC = "AG23";   ## 2   on LED DS14, 6 on J62
#NET "GPIO_LED_5"                    LOC = "AG23";   ## 2   on LED DS14, 6 on J62
#NET "GPIO_LED_6"                    LOC = "AE24";   ## 2   on LED DS22, 7 on J62
#NET "GPIO_LED_7"                    LOC = "AD24";   ## 2   on LED DS21, 8 on J62

NET "dvi_iic_scl"                   LOC = "AN10";   ## 2   on Q5, 15 on U38
NET "iic_scl_main"               LOC = "AK9";    ## 2   on Q19
#NET "IIC_SCL_SFP"                   LOC = "AA34";   ## 2   on Q23
NET "dvi_iic_sda"                   LOC = "AP10";   ## 2   on Q6, 14 on U38
NET "iic_sda_main"               LOC = "AE9";    ## 2   on Q20
#NET "IIC_SDA_SFP"                   LOC = "AA33";   ## 2   on Q21

NET "tft_lcd_data(0)"                        LOC = "AJ19";   ## 63 on U38 (thru series R111 47.5 ohm)
NET "tft_lcd_data(1)"                        LOC = "AH19";   ## 62 on U38 (thru series R110 47.5 ohm)
NET "tft_lcd_data(2)"                        LOC = "AM17";   ## 61 on U38 (thru series R109 47.5 ohm)
NET "tft_lcd_data(3)"                        LOC = "AM16";   ## 60 on U38 (thru series R108 47.5 ohm)
NET "tft_lcd_data(4)"                        LOC = "AD17";   ## 59 on U38 (thru series R107 47.5 ohm)
NET "tft_lcd_data(5)"                        LOC = "AE17";   ## 58 on U38 (thru series R106 47.5 ohm)
NET "tft_lcd_data(6)"                        LOC = "AK18";   ## 55 on U38 (thru series R105 47.5 ohm)
NET "tft_lcd_data(7)"                        LOC = "AK17";   ## 54 on U38 (thru series R104 47.5 ohm)
NET "tft_lcd_data(8)"                        LOC = "AE18";   ## 53 on U38 (thru series R103 47.5 ohm)
NET "tft_lcd_data(9)"                        LOC = "AF18";   ## 52 on U38 (thru series R102 47.5 ohm)
NET "tft_lcd_data(10)"                       LOC = "AL16";   ## 51 on U38 (thru series R101 47.5 ohm)
NET "tft_lcd_data(11)"                       LOC = "AK16";   ## 50 on U38 (thru series R100 47.5 ohm)
NET "tft_lcd_de"                        LOC = "AD16";   ## 2  on U38 (thru series R112 47.5 ohm)
#NET "DVI_GPIO1_FMC_C2M_PG_LS"       LOC = "K9";     ## 18 on U32 (not wired to U38)
NET "tft_lcd_hsync"                         LOC = "AN17";   ## 4  on U38 (thru series R113 47.5 ohm)
NET "tft_lcd_reset_b"                LOC = "AP17";   ## 2  on U32 (DVI_RESET_B pin 13 on U38)
NET "tft_lcd_vsync"                         LOC = "AD15";   ## 5  on U38 (thru series R114 47.5 ohm)
NET "tft_lcd_clk_n"                    LOC = "AC17";   ## 56 on U38
NET "tft_lcd_clk_p"                    LOC = "AC18";   ## 57 on U38

#NET "SYSACE_CFGTDI"                 LOC = "AC8";    ## 81  on U19
NET "sysace_d(0)"                     LOC = "AM15";   ## 66  on U19
NET "sysace_d(1)"                     LOC = "AJ17";   ## 65  on U19
NET "sysace_d(2)"                     LOC = "AJ16";   ## 63  on U19
NET "sysace_d(3)"                     LOC = "AP16";   ## 62  on U19
NET "sysace_d(4)"                     LOC = "AG16";   ## 61  on U19
NET "sysace_d(5)"                     LOC = "AH15";   ## 60  on U19
NET "sysace_d(6)"                     LOC = "AF16";   ## 59  on U19
NET "sysace_d(7)"                     LOC = "AN15";   ## 58  on U19
NET "sysace_mpa(0)"                  LOC = "AC15";   ## 70  on U19
NET "sysace_mpa(1)"                  LOC = "AP15";   ## 69  on U19
NET "sysace_mpa(2)"                  LOC = "AG17";   ## 68  on U19
NET "sysace_mpa(3)"                  LOC = "AH17";   ## 67  on U19
NET "sysace_mpa(4)"                  LOC = "AG15";   ## 45  on U19
NET "sysace_mpa(5)"                  LOC = "AF15";   ## 44  on U19
NET "sysace_mpa(6)"                  LOC = "AK14";   ## 43  on U19
#NET "SYSACE_MPBRDY"                 LOC = "AJ15";   ## 39  on U19
NET "sysace_mpce"                   LOC = "AJ14";   ## 42  on U19
NET "sysace_mpirq"                  LOC = "L9";     ## 41  on U19
NET "sysace_mpoe"                   LOC = "AL15";   ## 77  on U19
NET "sysace_mpwe"                   LOC = "AL14";   ## 76  on U19
NET "clk_33"              LOC = "AE16";   ## 93  on U19
NET "clk_33" PERIOD = 30.000 ;
OFFSET = IN : 20.000 : BEFORE clk_33 ;
OFFSET = OUT : 20.000 : AFTER clk_33 ;


NET "clkm" 		TNM_NET = "clkm";
NET "clk_ddr" 		TNM_NET = "clk_ddr";

TIMESPEC "TS_clkm_clk_ddr" = FROM "clkm" TO "clk_ddr" TIG;
TIMESPEC "TS_clk_ddr_clkm" = FROM "clk_ddr" TO "clkm" TIG;

NET "erx_clk" PERIOD = 8.000 ;
OFFSET = IN : 5.000 : BEFORE erx_clk ;
#OFFSET = IN : 2.000 : BEFORE erx_clk ;

NET "etx_clk" PERIOD = 40.000 ;
OFFSET = OUT : 15.000 : AFTER etx_clk ;
OFFSET = IN : 8.000 : BEFORE etx_clk ;

NET "etx_clk" MAXSKEW= 1.0 ns;
NET "erx_clk" MAXSKEW= 1.0 ns;

#NET "egtx_clk" PERIOD = 8.000 ;
#OFFSET = OUT : 5.500 : AFTER egtx_clk;
#NET "egtx_clk" CLOCK_DEDICATED_ROUTE = FALSE;

NET "gmiiclk_p"                 LOC = "H6";
NET "gmiiclk_n"                 LOC = "H5";
NET "gmiiclk_p" PERIOD = 8.000 ;
OFFSET = OUT : 12.000 : AFTER gmiiclk_p;

////////////////////////////////////////////////////////////////////////////
// VGA clock
////////////////////////////////////////////////////////////////////////////
#NET "clkvga" TNM_NET = "clkvga" | PERIOD = 15.385;
#TIMESPEC "TSPLB_TFT25" = FROM "clkm" TO "clkvga" TIG;
#TIMESPEC "TSPLB_TFT40" = FROM "clkvga" TO "clkm" TIG;



