############################################################################
## This system.ucf file is generated by Base System Builder based on the
## settings in the selected Xilinx Board Definition file. Please add other
## user constraints to this file based on customer design specifications.
## Author: Zhangxi Tan, UC Berkeley
############################################################################

Net clk LOC=AJ15;
Net clk IOSTANDARD = LVCMOS25;
Net resetn LOC=AH5;
Net resetn IOSTANDARD = LVTTL;
## System level constraints
Net clk TNM_NET = clk;
TIMESPEC TS_clk = PERIOD clk 10000 ps;
Net resetn TIG;

NET "ddrclk270" TNM_NET = "ddrclk270"; 
TIMESPEC "TS_ddrclk270" = PERIOD "ddrclk270" 10.000 ns HIGH 50.00%; 
NET "ddrclk0" TNM_NET = "ddrclk0"; 
TIMESPEC "TS_ddrclk0" = PERIOD "ddrclk0" "TS_ddrclk270" * 1.000000 PHASE-7.500ns HIGH 50.00%; 
NET "ddrclk180" TNM_NET = "ddrclk180"; 
TIMESPEC "TS_ddrclk180" = PERIOD "ddrclk180" "TS_ddrclk270" * 1.000000 PHASE-2.500ns HIGH 50.00%; 
NET "ddrclk90" TNM_NET = "ddrclk90"; 
TIMESPEC "TS_ddrclk90" = PERIOD "ddrclk90" "TS_ddrclk270" * 1.000000 PHASE-5.000ns HIGH 50.00%; 


Net "clkgen0/ddrclk_0" TNM_NET = clkgen0_ddrclk_0;
TIMESPEC TS_clkgen0_ddrclk_0 = PERIOD clkgen0_ddrclk_0 10526 ps;
Net "clkgen0/ddrclk_90" TNM_NET = clkgen0_ddrclk_90;
TIMESPEC TS_clkgen0_ddrclk_90 = PERIOD clkgen0_ddrclk_90 TS_clkgen0_ddrclk_0 PHASE 2.632 ns HIGH 50%;  
Net "clkgen0/ddrclk_180" TNM_NET = clkgen0_ddrclk_180;
TIMESPEC TS_clkgen0_ddrclk_180 = PERIOD clkgen0_ddrclk_180 TS_clkgen0_ddrclk_0 PHASE 5.263 ns HIGH 50%  ;
Net "clkgen0/ddrclk_270" TNM_NET = clkgen0_ddrclk_270;
TIMESPEC TS_clkgen0_ddrclk_270 = PERIOD clkgen0_ddrclk_270 TS_clkgen0_ddrclk_0 PHASE 7.895 ns HIGH 50%  ;

#Begin clock to clock delay constraints
TIMEGRP "ddrclk270_rise" = RISING "ddrclk270";
TIMEGRP "clkm_rise" = RISING "clkm";
TIMESPEC "TS_ddrclk270_rise_clkm_rise" = FROM "ddrclk270_rise" TO "clkm_rise" TIG;
TIMEGRP "ddrclk180_rise" = RISING "ddrclk180";
TIMESPEC "TS_ddrclk180_rise_clkm_rise" = FROM "ddrclk180_rise" TO "clkm_rise" TIG;
TIMEGRP "ddrclk90_rise" = RISING "ddrclk90";
TIMESPEC "TS_ddrclk90_rise_clkm_rise" = FROM "ddrclk90_rise" TO "clkm_rise" TIG;
TIMEGRP "ddrclk0_rise" = RISING "ddrclk0";
TIMESPEC "TS_ddrclk0_rise_clkm_rise" = FROM "ddrclk0_rise" TO "clkm_rise" TIG;
TIMESPEC "TS_clkm_rise_ddrclk270_rise" = FROM "clkm_rise" TO "ddrclk270_rise" TIG;
TIMESPEC "TS_clkm_rise_ddrclk180_rise" = FROM "clkm_rise" TO "ddrclk180_rise" TIG;
TIMESPEC "TS_clkm_rise_ddrclk90_rise" = FROM "clkm_rise" TO "ddrclk90_rise" TIG;
TIMESPEC "TS_clkm_rise_ddrclk0_rise" = FROM "clkm_rise" TO "ddrclk0_rise" TIG;
#End clock to clock delay constraints


## IO Devices constraints

#### Module RS232_Uart_1 constraints

Net dsurx LOC=AJ8;
Net dsurx IOSTANDARD = LVCMOS25;
Net dsutx LOC=AE7;
Net dsutx IOSTANDARD = LVCMOS25;
Net dsutx SLEW = SLOW;
Net dsutx DRIVE = 12;

#### Module DDR controller constraints
Net ddr_ad<12> LOC=M25;
Net ddr_ad<12> IOSTANDARD = SSTL2_II;
Net ddr_ad<11> LOC=N25;
Net ddr_ad<11> IOSTANDARD = SSTL2_II;
Net ddr_ad<10> LOC=L26;
Net ddr_ad<10> IOSTANDARD = SSTL2_II;
Net ddr_ad<9> LOC=M29;
Net ddr_ad<9> IOSTANDARD = SSTL2_II;
Net ddr_ad<8> LOC=K30;
Net ddr_ad<8> IOSTANDARD = SSTL2_II;
Net ddr_ad<7> LOC=G25;
Net ddr_ad<7> IOSTANDARD = SSTL2_II;
Net ddr_ad<6> LOC=G26;
Net ddr_ad<6> IOSTANDARD = SSTL2_II;
Net ddr_ad<5> LOC=D26;
Net ddr_ad<5> IOSTANDARD = SSTL2_II;
Net ddr_ad<4> LOC=J24;
Net ddr_ad<4> IOSTANDARD = SSTL2_II;
Net ddr_ad<3> LOC=K24;
Net ddr_ad<3> IOSTANDARD = SSTL2_II;
Net ddr_ad<2> LOC=F28;
Net ddr_ad<2> IOSTANDARD = SSTL2_II;
Net ddr_ad<1> LOC=F30;
Net ddr_ad<1> IOSTANDARD = SSTL2_II;
Net ddr_ad<0> LOC=M24;
Net ddr_ad<0> IOSTANDARD = SSTL2_II;
Net ddr_ba<1> LOC=M26;
Net ddr_ba<1> IOSTANDARD = SSTL2_II;
Net ddr_ba<0> LOC=K26;
Net ddr_ba<0> IOSTANDARD = SSTL2_II;
Net ddr_cas LOC=L27;
Net ddr_cas IOSTANDARD = SSTL2_II;
Net ddr_cke LOC=R26;
Net ddr_cke IOSTANDARD = SSTL2_II;
Net ddr_cs LOC=R24;
Net ddr_cs IOSTANDARD = SSTL2_II;
Net ddr_ras LOC=N29;
Net ddr_ras IOSTANDARD = SSTL2_II;
Net ddr_we LOC=N26;
Net ddr_we IOSTANDARD = SSTL2_II;
Net ddr_dm<7> LOC=U26;
Net ddr_dm<7> IOSTANDARD = SSTL2_II;
Net ddr_dm<6> LOC=V29;
Net ddr_dm<6> IOSTANDARD = SSTL2_II;
Net ddr_dm<5> LOC=W29;
Net ddr_dm<5> IOSTANDARD = SSTL2_II;
Net ddr_dm<4> LOC=T22;
Net ddr_dm<4> IOSTANDARD = SSTL2_II;
Net ddr_dm<3> LOC=W28;
Net ddr_dm<3> IOSTANDARD = SSTL2_II;
Net ddr_dm<2> LOC=W27;
Net ddr_dm<2> IOSTANDARD = SSTL2_II;
Net ddr_dm<1> LOC=W26;
Net ddr_dm<1> IOSTANDARD = SSTL2_II;
Net ddr_dm<0> LOC=W25;
Net ddr_dm<0> IOSTANDARD = SSTL2_II;
Net ddr_dqs<7> LOC=E30;
Net ddr_dqs<7> IOSTANDARD = SSTL2_II;
Net ddr_dqs<6> LOC=J29;
Net ddr_dqs<6> IOSTANDARD = SSTL2_II;
Net ddr_dqs<5> LOC=M30;
Net ddr_dqs<5> IOSTANDARD = SSTL2_II;
Net ddr_dqs<4> LOC=P29;
Net ddr_dqs<4> IOSTANDARD = SSTL2_II;
Net ddr_dqs<3> LOC=V23;
Net ddr_dqs<3> IOSTANDARD = SSTL2_II;
Net ddr_dqs<2> LOC=AA25;
Net ddr_dqs<2> IOSTANDARD = SSTL2_II;
Net ddr_dqs<1> LOC=AC25;
Net ddr_dqs<1> IOSTANDARD = SSTL2_II;
Net ddr_dqs<0> LOC=AH26;
Net ddr_dqs<0> IOSTANDARD = SSTL2_II;
Net ddr_dq<63> LOC=C27;
Net ddr_dq<63> IOSTANDARD = SSTL2_II;
Net ddr_dq<62> LOC=D28;
Net ddr_dq<62> IOSTANDARD = SSTL2_II;
Net ddr_dq<61> LOC=D29;
Net ddr_dq<61> IOSTANDARD = SSTL2_II;
Net ddr_dq<60> LOC=D30;
Net ddr_dq<60> IOSTANDARD = SSTL2_II;
Net ddr_dq<59> LOC=H25;
Net ddr_dq<59> IOSTANDARD = SSTL2_II;
Net ddr_dq<58> LOC=H26;
Net ddr_dq<58> IOSTANDARD = SSTL2_II;
Net ddr_dq<57> LOC=E27;
Net ddr_dq<57> IOSTANDARD = SSTL2_II;
Net ddr_dq<56> LOC=E28;
Net ddr_dq<56> IOSTANDARD = SSTL2_II;
Net ddr_dq<55> LOC=J26;
Net ddr_dq<55> IOSTANDARD = SSTL2_II;
Net ddr_dq<54> LOC=G27;
Net ddr_dq<54> IOSTANDARD = SSTL2_II;
Net ddr_dq<53> LOC=G28;
Net ddr_dq<53> IOSTANDARD = SSTL2_II;
Net ddr_dq<52> LOC=G30;
Net ddr_dq<52> IOSTANDARD = SSTL2_II;
Net ddr_dq<51> LOC=L23;
Net ddr_dq<51> IOSTANDARD = SSTL2_II;
Net ddr_dq<50> LOC=L24;
Net ddr_dq<50> IOSTANDARD = SSTL2_II;
Net ddr_dq<49> LOC=H27;
Net ddr_dq<49> IOSTANDARD = SSTL2_II;
Net ddr_dq<48> LOC=H28;
Net ddr_dq<48> IOSTANDARD = SSTL2_II;
Net ddr_dq<47> LOC=J27;
Net ddr_dq<47> IOSTANDARD = SSTL2_II;
Net ddr_dq<46> LOC=J28;
Net ddr_dq<46> IOSTANDARD = SSTL2_II;
Net ddr_dq<45> LOC=K29;
Net ddr_dq<45> IOSTANDARD = SSTL2_II;
Net ddr_dq<44> LOC=L29;
Net ddr_dq<44> IOSTANDARD = SSTL2_II;
Net ddr_dq<43> LOC=N23;
Net ddr_dq<43> IOSTANDARD = SSTL2_II;
Net ddr_dq<42> LOC=N24;
Net ddr_dq<42> IOSTANDARD = SSTL2_II;
Net ddr_dq<41> LOC=K27;
Net ddr_dq<41> IOSTANDARD = SSTL2_II;
Net ddr_dq<40> LOC=K28;
Net ddr_dq<40> IOSTANDARD = SSTL2_II;
Net ddr_dq<39> LOC=R22;
Net ddr_dq<39> IOSTANDARD = SSTL2_II;
Net ddr_dq<38> LOC=M27;
Net ddr_dq<38> IOSTANDARD = SSTL2_II;
Net ddr_dq<37> LOC=M28;
Net ddr_dq<37> IOSTANDARD = SSTL2_II;
Net ddr_dq<36> LOC=P30;
Net ddr_dq<36> IOSTANDARD = SSTL2_II;
Net ddr_dq<35> LOC=P23;
Net ddr_dq<35> IOSTANDARD = SSTL2_II;
Net ddr_dq<34> LOC=P24;
Net ddr_dq<34> IOSTANDARD = SSTL2_II;
Net ddr_dq<33> LOC=N27;
Net ddr_dq<33> IOSTANDARD = SSTL2_II;
Net ddr_dq<32> LOC=N28;
Net ddr_dq<32> IOSTANDARD = SSTL2_II;
Net ddr_dq<31> LOC=V27;
Net ddr_dq<31> IOSTANDARD = SSTL2_II;
Net ddr_dq<30> LOC=Y30;
Net ddr_dq<30> IOSTANDARD = SSTL2_II;
Net ddr_dq<29> LOC=U24;
Net ddr_dq<29> IOSTANDARD = SSTL2_II;
Net ddr_dq<28> LOC=U23;
Net ddr_dq<28> IOSTANDARD = SSTL2_II;
Net ddr_dq<27> LOC=V26;
Net ddr_dq<27> IOSTANDARD = SSTL2_II;
Net ddr_dq<26> LOC=V25;
Net ddr_dq<26> IOSTANDARD = SSTL2_II;
Net ddr_dq<25> LOC=Y29;
Net ddr_dq<25> IOSTANDARD = SSTL2_II;
Net ddr_dq<24> LOC=AA29;
Net ddr_dq<24> IOSTANDARD = SSTL2_II;
Net ddr_dq<23> LOC=Y26;
Net ddr_dq<23> IOSTANDARD = SSTL2_II;
Net ddr_dq<22> LOC=AA28;
Net ddr_dq<22> IOSTANDARD = SSTL2_II;
Net ddr_dq<21> LOC=AA27;
Net ddr_dq<21> IOSTANDARD = SSTL2_II;
Net ddr_dq<20> LOC=W24;
Net ddr_dq<20> IOSTANDARD = SSTL2_II;
Net ddr_dq<19> LOC=W23;
Net ddr_dq<19> IOSTANDARD = SSTL2_II;
Net ddr_dq<18> LOC=AB28;
Net ddr_dq<18> IOSTANDARD = SSTL2_II;
Net ddr_dq<17> LOC=AB27;
Net ddr_dq<17> IOSTANDARD = SSTL2_II;
Net ddr_dq<16> LOC=AC29;
Net ddr_dq<16> IOSTANDARD = SSTL2_II;
Net ddr_dq<15> LOC=AB25;
Net ddr_dq<15> IOSTANDARD = SSTL2_II;
Net ddr_dq<14> LOC=AE29;
Net ddr_dq<14> IOSTANDARD = SSTL2_II;
Net ddr_dq<13> LOC=AA24;
Net ddr_dq<13> IOSTANDARD = SSTL2_II;
Net ddr_dq<12> LOC=AA23;
Net ddr_dq<12> IOSTANDARD = SSTL2_II;
Net ddr_dq<11> LOC=AD28;
Net ddr_dq<11> IOSTANDARD = SSTL2_II;
Net ddr_dq<10> LOC=AD27;
Net ddr_dq<10> IOSTANDARD = SSTL2_II;
Net ddr_dq<9> LOC=AF30;
Net ddr_dq<9> IOSTANDARD = SSTL2_II;
Net ddr_dq<8> LOC=AF29;
Net ddr_dq<8> IOSTANDARD = SSTL2_II;
Net ddr_dq<7> LOC=AF25;
Net ddr_dq<7> IOSTANDARD = SSTL2_II;
Net ddr_dq<6> LOC=AG30;
Net ddr_dq<6> IOSTANDARD = SSTL2_II;
Net ddr_dq<5> LOC=AG29;
Net ddr_dq<5> IOSTANDARD = SSTL2_II;
Net ddr_dq<4> LOC=AD26;
Net ddr_dq<4> IOSTANDARD = SSTL2_II;
Net ddr_dq<3> LOC=AD25;
Net ddr_dq<3> IOSTANDARD = SSTL2_II;
Net ddr_dq<2> LOC=AG28;
Net ddr_dq<2> IOSTANDARD = SSTL2_II;
Net ddr_dq<1> LOC=AH27;
Net ddr_dq<1> IOSTANDARD = SSTL2_II;
Net ddr_dq<0> LOC=AH29;
Net ddr_dq<0> IOSTANDARD = SSTL2_II;
Net ddr_clk<2> LOC=AC27;
Net ddr_clk<2> IOSTANDARD = SSTL2_II;
Net ddr_clk<1> LOC=AD29;
Net ddr_clk<1> IOSTANDARD = SSTL2_II;
Net ddr_clk<0> LOC=AB23;
Net ddr_clk<0> IOSTANDARD = SSTL2_II;
Net ddr_clkn<2> LOC=AC28;
Net ddr_clkn<2> IOSTANDARD = SSTL2_II;
Net ddr_clkn<1> LOC=AD30;
Net ddr_clkn<1> IOSTANDARD = SSTL2_II;
Net ddr_clkn<0> LOC=AB24;
Net ddr_clkn<0> IOSTANDARD = SSTL2_II;

Net ddr_clk_fb LOC=C16;
Net ddr_clk_fb IOSTANDARD = SSTL2_II;
Net ddr_clk_fb_out LOC=G23;
Net ddr_clk_fb_out IOSTANDARD = SSTL2_II;

## NET ddr_clk_fb FEEDBACK = 1 ns NET ddr_clk_fb_out;

#### Ethernet MAC constraints####
## NET "erx_clk" TNM_NET = "RXCLK_GRP_Ethernet_MAC";
## NET "etx_clk" TNM_NET = "TXCLK_GRP_Ethernet_MAC";
## TIMESPEC "TSTXOUT_Ethernet_MAC" = FROM "TXCLK_GRP_Ethernet_MAC" TO "PADS" 10 ns;
## TIMESPEC "TSRXIN_Ethernet_MAC" = FROM "PADS" TO "RXCLK_GRP_Ethernet_MAC" 6 ns;
## NET "etx_clk" MAXSKEW= 2.0 ns;
## NET "erx_clk" MAXSKEW= 2.0 ns;
NET "etx_clk" PERIOD = 40 ns HIGH 14 ns;
NET "erx_clk" PERIOD = 40 ns HIGH 14 ns;
## NET "erxd<3>" NODELAY;
## NET "erxd<2>" NODELAY;
## NET "erxd<1>" NODELAY;
## NET "erxd<0>" NODELAY;
## NET "erx_dv" NODELAY;
## NET "erx_er" NODELAY;
## NET "erx_crs" NODELAY;
## NET "erx_col" NODELAY;


Net em_slew1 LOC=B3;
Net em_slew1 IOSTANDARD = LVTTL;
Net em_slew1 SLEW = SLOW;
Net em_slew1 DRIVE = 8;
Net em_slew2 LOC=A3;
Net em_slew2 IOSTANDARD = LVTTL;
Net em_slew2 SLEW = SLOW;
Net em_slew2 DRIVE = 8;
Net em_resetn LOC=G6;
Net em_resetn IOSTANDARD = LVTTL;
Net em_resetn SLEW = SLOW;
Net em_resetn DRIVE = 8;
Net erx_crs LOC=C5;
Net erx_crs IOSTANDARD = LVTTL;
Net erx_col LOC=D5;
Net erx_col IOSTANDARD = LVTTL;
Net etxd<3> LOC=C2;
Net etxd<3> IOSTANDARD = LVTTL;
Net etxd<3> SLEW = SLOW;
Net etxd<3> DRIVE = 8;
Net etxd<2> LOC=C1;
Net etxd<2> IOSTANDARD = LVTTL;
Net etxd<2> SLEW = SLOW;
Net etxd<2> DRIVE = 8;
Net etxd<1> LOC=J8;
Net etxd<1> IOSTANDARD = LVTTL;
Net etxd<1> SLEW = SLOW;
Net etxd<1> DRIVE = 8;
Net etxd<0> LOC=J7;
Net etxd<0> IOSTANDARD = LVTTL;
Net etxd<0> SLEW = SLOW;
Net etxd<0> DRIVE = 8;
Net etx_en LOC=C4;
Net etx_en IOSTANDARD = LVTTL;
Net etx_en SLEW = SLOW;
Net etx_en DRIVE = 8;
Net etx_clk LOC=D3;
Net etx_clk IOSTANDARD = LVTTL;
Net etx_er LOC=H2;
Net etx_er IOSTANDARD = LVTTL;
Net erx_er LOC=J2;
Net erx_er IOSTANDARD = LVTTL;
Net erx_clk LOC=M8;
Net erx_clk IOSTANDARD = LVTTL;
Net erx_dv LOC=M7;
Net erx_dv IOSTANDARD = LVTTL;
Net erxd<0> LOC=K6;
Net erxd<0> IOSTANDARD = LVTTL;
Net erxd<1> LOC=K5;
Net erxd<1> IOSTANDARD = LVTTL;
Net erxd<2> LOC=J1;
Net erxd<2> IOSTANDARD = LVTTL;
Net erxd<3> LOC=K1;
Net erxd<3> IOSTANDARD = LVTTL;
Net emdc LOC=M6;
Net emdc IOSTANDARD = LVTTL;
Net emdc SLEW = SLOW;
Net emdc DRIVE = 8;
Net emdio LOC=M5;
Net emdio IOSTANDARD = LVTTL;
Net emdio SLEW = SLOW;
Net emdio DRIVE = 8;

NET dsuact LOC = "AC4";
NET dsuact IOSTANDARD = LVTTL;
NET dsuact DRIVE = 12;
NET dsuact SLEW = SLOW;

NET errorn LOC = "AC3";
NET errorn IOSTANDARD = LVTTL;
NET errorn DRIVE = 12;
NET errorn SLEW = SLOW;
