SDRAM controller enable
CONFIG_DDRSP
  Say Y here to enabled a 16-bit DDR266 SDRAM controller. 

Power-on init
CONFIG_DDRSP_INIT
  Say Y here to enable the automatic DDR initialization sequence.
  If disabled, the sequencemust be performed in software before
  the DDR can be used. If unsure, say Y.

Memory frequency
CONFIG_DDRSP_FREQ
  Enter the frequency of the DDR clock (in MHz). The value is
  typically between 80 - 133, depending on system configuration.
  Some template design (such as the leon3-avnet-eval-lx25)
  calculate this value automatically and this value is not used.

Column bits
CONFIG_DDRSP_COL
  Select the number of colomn address bits of the DDR memory.
  Typical values are 8 - 11. Only needed when automatic DDR
  initialisation is choosen. The column size can always be
  programmed by software as well.

Chip select size
CONFIG_DDRSP_MBYTE
  Select the memory size (Mbytes) that each chip select should decode.
  Only needed when automatic DDR initialisation is choosen. The chip
  select size can always be programmed by software as well.

Read clock phase shift
CONFIG_DDRSP_RSKEW
  On Xilinx targets, the read clock is de-skewed and phase-shifted
  using a DCM connected to the feed-back clock input. On some boards,
  the de-skewing does not work perfectly, and some extra phase shifting
  must be added manually. The entered value is set to the PHASE_SHIFT
  generic on the Xilinx DCM. The Digilent Sparten3E-1600 board typically
  needs a value of 35, while the Avnet Virtex4 Eval board needs -90.
  For Altera CycloneIII, the entered value is set to the PHASE_SHIFT of 
  the PLL in ps (e.g 2500 for 90' shift in 100MHz)
