package sifive.blocks.devices.pwm

import chisel3._ 
import sifive.blocks.devices.pinctrl.{Pin}

class PWMSignals[T <: Data](private val pingen: () => T, val c: PWMParams) extends Bundle {
  val pwm: Vec[T] = Vec(c.ncmp, pingen())
}

class PWMPins[T <: Pin](pingen: () => T, c: PWMParams) extends PWMSignals[T](pingen, c)

object PWMPinsFromPort {
  def apply[T <: Pin] (pins: PWMSignals[T], port: PWMPortIO, clock: Clock, reset: Bool): Unit = {
    withClockAndReset(clock, reset){
      (pins.pwm zip port.gpio) foreach { case (pin, port) =>
        pin.outputPin(port)
      }
    }
  }

  def apply[T <: Pin] (pins: PWMSignals[T], port: PWMPortIO): Unit = {
    (pins.pwm zip port.gpio) foreach { case (pin, port) =>
      pin.outputPin(port)
    }
  }
}

/*
   Copyright 2016 SiFive, Inc.

   Licensed under the Apache License, Version 2.0 (the "License");
   you may not use this file except in compliance with the License.
   You may obtain a copy of the License at

       http://www.apache.org/licenses/LICENSE-2.0

   Unless required by applicable law or agreed to in writing, software
   distributed under the License is distributed on an "AS IS" BASIS,
   WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
   See the License for the specific language governing permissions and
   limitations under the License.
*/
