read_verilog -sv /eda/processor_ci/rtl/RiftCore.sv
read_verilog /var/jenkins_home/workspace/RiftCore/RiftCore/RiftChip/riftChip.v
read_verilog /var/jenkins_home/workspace/RiftCore/RiftCore/RiftChip/axi/axi_full_mst.v
read_verilog /var/jenkins_home/workspace/RiftCore/RiftCore/RiftChip/axi/axi_full_slv.v
read_verilog /var/jenkins_home/workspace/RiftCore/RiftCore/RiftChip/axi/axi_lite_mst.v
read_verilog /var/jenkins_home/workspace/RiftCore/RiftCore/RiftChip/axi/axi_lite_slv.v
read_verilog /var/jenkins_home/workspace/RiftCore/RiftCore/RiftChip/axi/AXI BUS TEMPLE/axi4_full_master.v
read_verilog /var/jenkins_home/workspace/RiftCore/RiftCore/RiftChip/axi/AXI BUS TEMPLE/axi4_full_slave.v
read_verilog /var/jenkins_home/workspace/RiftCore/RiftCore/RiftChip/axi/AXI BUS TEMPLE/axi4_lite_master.v
read_verilog /var/jenkins_home/workspace/RiftCore/RiftCore/RiftChip/axi/AXI BUS TEMPLE/axi4_lite_slave.v
read_verilog /var/jenkins_home/workspace/RiftCore/RiftCore/RiftChip/debug/DM.v
read_verilog /var/jenkins_home/workspace/RiftCore/RiftCore/RiftChip/debug/DMI.v
read_verilog /var/jenkins_home/workspace/RiftCore/RiftCore/RiftChip/debug/DTM.v
read_verilog /var/jenkins_home/workspace/RiftCore/RiftCore/RiftChip/debug/core_monitor.v
read_verilog /var/jenkins_home/workspace/RiftCore/RiftCore/RiftChip/element/gen_asymmetricFIFO.v
read_verilog /var/jenkins_home/workspace/RiftCore/RiftCore/RiftChip/element/gen_bypassfifo.v
read_verilog /var/jenkins_home/workspace/RiftCore/RiftCore/RiftChip/element/gen_counter.v
read_verilog /var/jenkins_home/workspace/RiftCore/RiftCore/RiftChip/element/gen_csrreg.v
read_verilog /var/jenkins_home/workspace/RiftCore/RiftCore/RiftChip/element/gen_dffr.v
read_verilog /var/jenkins_home/workspace/RiftCore/RiftCore/RiftChip/element/gen_dffren.v
read_verilog /var/jenkins_home/workspace/RiftCore/RiftCore/RiftChip/element/gen_dpdffren.v
read_verilog /var/jenkins_home/workspace/RiftCore/RiftCore/RiftChip/element/gen_fifo.v
read_verilog /var/jenkins_home/workspace/RiftCore/RiftCore/RiftChip/element/gen_ppbuff.v
read_verilog /var/jenkins_home/workspace/RiftCore/RiftCore/RiftChip/element/gen_ringStack.v
read_verilog /var/jenkins_home/workspace/RiftCore/RiftCore/RiftChip/element/gen_rsffr.v
read_verilog /var/jenkins_home/workspace/RiftCore/RiftCore/RiftChip/element/gen_slffr.v
read_verilog /var/jenkins_home/workspace/RiftCore/RiftCore/RiftChip/element/gen_sram.v
read_verilog /var/jenkins_home/workspace/RiftCore/RiftCore/RiftChip/element/gen_suffr.v
read_verilog /var/jenkins_home/workspace/RiftCore/RiftCore/RiftChip/element/gen_syn.v
read_verilog /var/jenkins_home/workspace/RiftCore/RiftCore/RiftChip/element/lfsr.v
read_verilog /var/jenkins_home/workspace/RiftCore/RiftCore/RiftChip/element/lzp.v
read_verilog /var/jenkins_home/workspace/RiftCore/RiftCore/RiftChip/riftCore/backEnd.v
read_verilog /var/jenkins_home/workspace/RiftCore/RiftCore/RiftChip/riftCore/frontEnd.v
read_verilog /var/jenkins_home/workspace/RiftCore/RiftCore/RiftChip/riftCore/instr_fifo.v
read_verilog /var/jenkins_home/workspace/RiftCore/RiftCore/RiftChip/riftCore/riftCore.v
read_verilog /var/jenkins_home/workspace/RiftCore/RiftCore/RiftChip/riftCore/backend/commit.v
read_verilog /var/jenkins_home/workspace/RiftCore/RiftCore/RiftChip/riftCore/backend/csrFiles.v
read_verilog /var/jenkins_home/workspace/RiftCore/RiftCore/RiftChip/riftCore/backend/dispatch.v
read_verilog /var/jenkins_home/workspace/RiftCore/RiftCore/RiftChip/riftCore/backend/phyRegister.v
read_verilog /var/jenkins_home/workspace/RiftCore/RiftCore/RiftChip/riftCore/backend/regFiles.v
read_verilog /var/jenkins_home/workspace/RiftCore/RiftCore/RiftChip/riftCore/backend/rename.v
read_verilog /var/jenkins_home/workspace/RiftCore/RiftCore/RiftChip/riftCore/backend/writeBack.v
read_verilog /var/jenkins_home/workspace/RiftCore/RiftCore/RiftChip/riftCore/backend/execute/alu.v
read_verilog /var/jenkins_home/workspace/RiftCore/RiftCore/RiftChip/riftCore/backend/execute/bru.v
read_verilog /var/jenkins_home/workspace/RiftCore/RiftCore/RiftChip/riftCore/backend/execute/csr.v
read_verilog /var/jenkins_home/workspace/RiftCore/RiftCore/RiftChip/riftCore/backend/execute/lsu.v
read_verilog /var/jenkins_home/workspace/RiftCore/RiftCore/RiftChip/riftCore/backend/execute/mul.v
read_verilog /var/jenkins_home/workspace/RiftCore/RiftCore/RiftChip/riftCore/backend/issue/alu_issue.v
read_verilog /var/jenkins_home/workspace/RiftCore/RiftCore/RiftChip/riftCore/backend/issue/bru_issue.v
read_verilog /var/jenkins_home/workspace/RiftCore/RiftCore/RiftChip/riftCore/backend/issue/csr_issue.v
read_verilog /var/jenkins_home/workspace/RiftCore/RiftCore/RiftChip/riftCore/backend/issue/issue_buffer.v
read_verilog /var/jenkins_home/workspace/RiftCore/RiftCore/RiftChip/riftCore/backend/issue/issue_fifo.v
read_verilog /var/jenkins_home/workspace/RiftCore/RiftCore/RiftChip/riftCore/backend/issue/lsu_issue.v
read_verilog /var/jenkins_home/workspace/RiftCore/RiftCore/RiftChip/riftCore/backend/issue/mul_issue.v
read_verilog /var/jenkins_home/workspace/RiftCore/RiftCore/RiftChip/riftCore/cache/L2cache.v
read_verilog /var/jenkins_home/workspace/RiftCore/RiftCore/RiftChip/riftCore/cache/L3cache.v
read_verilog /var/jenkins_home/workspace/RiftCore/RiftCore/RiftChip/riftCore/cache/cache.v
read_verilog /var/jenkins_home/workspace/RiftCore/RiftCore/RiftChip/riftCore/cache/cache_mem.v
read_verilog /var/jenkins_home/workspace/RiftCore/RiftCore/RiftChip/riftCore/cache/dirty_block.v
read_verilog /var/jenkins_home/workspace/RiftCore/RiftCore/RiftChip/riftCore/cache/wt_block.v
read_verilog /var/jenkins_home/workspace/RiftCore/RiftCore/RiftChip/riftCore/frontend/branch_predict.v
read_verilog /var/jenkins_home/workspace/RiftCore/RiftCore/RiftChip/riftCore/frontend/decoder.v
read_verilog /var/jenkins_home/workspace/RiftCore/RiftCore/RiftChip/riftCore/frontend/decoder16.v
read_verilog /var/jenkins_home/workspace/RiftCore/RiftCore/RiftChip/riftCore/frontend/decoder32.v
read_verilog /var/jenkins_home/workspace/RiftCore/RiftCore/RiftChip/riftCore/frontend/iAlign.v
read_verilog /var/jenkins_home/workspace/RiftCore/RiftCore/RiftChip/riftCore/frontend/icache.v
read_verilog /var/jenkins_home/workspace/RiftCore/RiftCore/RiftChip/riftCore/frontend/iqueue.v
read_verilog /var/jenkins_home/workspace/RiftCore/RiftCore/RiftChip/riftCore/frontend/pcGenerate.v
read_verilog /var/jenkins_home/workspace/RiftCore/RiftCore/RiftChip/riftCore/frontend/preDecode.v
set_property include_dirs [list "/var/jenkins_home/workspace/RiftCore/RiftCore/RiftChip" ] [get_filesets sources_1]
read_verilog -sv /eda/processor-ci-controller/modules/uart.sv
read_verilog /eda/processor-ci-controller/modules/UART/rtl/uart_rx.v
read_verilog /eda/processor-ci-controller/modules/UART/rtl/uart_tx.v

#read_verilog -sv /eda/processor-ci-controller/modules/spi.sv;
#read_verilog -sv /eda/processor-ci-controller/modules/SPI-Slave/rtl/spi_slave.sv;

read_verilog -sv /eda/processor_ci/internal/ahblite_to_wishbone.sv
read_verilog -sv /eda/processor_ci/internal/axi4_to_wishbone.sv
read_verilog -sv /eda/processor_ci/internal/axi4lite_to_wishbone.sv
read_verilog -sv /eda/processor-ci-controller/rtl/fifo.sv
read_verilog -sv /eda/processor-ci-controller/rtl/reset.sv
read_verilog -sv /eda/processor-ci-controller/rtl/clk_divider.sv
read_verilog -sv /eda/processor-ci-controller/rtl/memory.sv
read_verilog -sv /eda/processor-ci-controller/rtl/interpreter.sv
read_verilog -sv /eda/processor-ci-controller/rtl/controller.sv
read_verilog -sv /eda/processor-ci-controller/rtl/timer.sv
read_verilog -sv /eda/processor_ci/internal/fpga_top.sv

set_param general.maxThreads 16

read_xdc "/eda/processor_ci/constraints/digilent_arty_a7_100t.xdc"
set_property PROCESSING_ORDER EARLY [get_files /eda/processor_ci/constraints/digilent_arty_a7_100t.xdc]

# synth
synth_design -top "fpga_top" -part "xc7a100tcsg324-1"

# place and route
opt_design
place_design

report_utilization -hierarchical -file digilent_arty_a7_utilization_hierarchical_place.rpt
report_utilization               -file digilent_arty_a7_utilization_place.rpt
report_io                        -file digilent_arty_a7_io.rpt
report_control_sets -verbose     -file digilent_arty_a7_control_sets.rpt
report_clock_utilization         -file digilent_arty_a7_clock_utilization.rpt


route_design

report_timing_summary -no_header -no_detailed_paths
report_route_status                            -file digilent_arty_a7_route_status.rpt
report_drc                                     -file digilent_arty_a7_drc.rpt
report_timing_summary -datasheet -max_paths 10 -file digilent_arty_a7_timing.rpt
report_power                                   -file digilent_arty_a7_power.rpt


# write bitstream
write_bitstream -force "digilent_arty_a7_100t.bit"

exit