Started by timer
[Pipeline] Start of Pipeline
[Pipeline] node
Still waiting to schedule task
Waiting for next available executor
Running on Jenkins in /var/jenkins_home/workspace/RiftCore
[Pipeline] {
[Pipeline] stage
[Pipeline] { (Git Clone)
[Pipeline] sh
+ rm -rf *.xml
[Pipeline] sh
+ rm -rf RiftCore
[Pipeline] sh
+ git clone --recursive --depth=1 https://github.com/whutddk/RiftCore RiftCore
Cloning into 'RiftCore'...
[Pipeline] }
[Pipeline] // stage
[Pipeline] stage
[Pipeline] { (Simulation)
[Pipeline] dir
Running in /var/jenkins_home/workspace/RiftCore/RiftCore
[Pipeline] {
[Pipeline] echo
FPGA > Simulation
[Pipeline] }
[Pipeline] // dir
[Pipeline] }
[Pipeline] // stage
[Pipeline] stage
[Pipeline] { (Utilities)
[Pipeline] dir
Running in /var/jenkins_home/workspace/RiftCore/RiftCore
[Pipeline] {
[Pipeline] sh
+ pwd
+ python3 /eda/processor_ci/core/labeler_prototype.py -d /var/jenkins_home/workspace/RiftCore/RiftCore -c /eda/processor_ci/config -o /jenkins/processor_ci_utils/labels
Trying to read file: /var/jenkins_home/workspace/RiftCore/RiftCore/RiftChip/riftChip.v
Possible cache file: dcache_tb.v
Possible cache file: icache_tb.v
Possible cache file: axi_full_cache_tb.v
Cache-related signals in axi_lite_slv.v
Cache-related signals in axi4_lite_slave.v
Cache-related signals in axi4_lite_master.v
Cache-related signals in axi4_full_master.v
Cache-related signals in axi4_full_slave.v
Possible cache file: icache.v
Cache-related signals in commit.v
Cache-related signals in alu.v
Cache-related signals in bru.v
Cache-related signals in mul.v
Possible cache file: cache.v
Possible cache file: L2cache.v
Cache-related signals in dirty_block.v
Possible cache file: cache_mem.v
Possible cache file: L3cache.v
Cache-related signals in gen_fifo.v
Cache-related signals in gen_ppbuff.v
Cache-related signals in axi_crossbar_v2_1_22_decerr_slave.v
Cache-related signals in axi_crossbar_v2_1_22_crossbar_sasd.v
Cache-related signals in axi_data_fifo_v2_1_vl_rfs.v
Cache-related signals in axi_infrastructure_v1_1_vl_rfs.v
Cache-related signals in axi_crossbar_v2_1_22_axi_crossbar.v
Cache-related signals in generic_baseblocks_v2_1_0_carry_and.v
Cache-related signals in axi_register_slice_v2_1_21_axic_register_slice.v
Cache-related signals in generic_baseblocks_v2_1_0_mux_enc.v
Cache-related signals in axi_crossbar_v2_1_22_addr_decoder.v
Cache-related signals in axi_crossbar_v2_1_vl_rfs.v
Cache-related signals in axi_crossbar_v2_1_22_splitter.v
Cache-related signals in axi_full_crossbar.v
Cache-related signals in generic_baseblocks_v2_1_0_comparator_static.v
Cache-related signals in axi_register_slice_v2_1_vl_rfs.v
Cache-related signals in generic_baseblocks_v2_1_vl_rfs.v
Cache-related signals in axi_crossbar_v2_1_22_addr_arbiter_sasd.v
Results saved to /jenkins/processor_ci_utils/labels/RiftCore.json
[Pipeline] }
[Pipeline] // dir
[Pipeline] }
[Pipeline] // stage
[Pipeline] stage
[Pipeline] { (FPGA Build Pipeline)
[Pipeline] parallel
[Pipeline] { (Branch: digilent_arty_a7_100t)
[Pipeline] stage
[Pipeline] { (digilent_arty_a7_100t)
[Pipeline] lock
Trying to acquire lock on [Resource: digilent_arty_a7_100t]
The resource [digilent_arty_a7_100t] is locked by build riscv #466 #466 since May 28, 2026, 4:59 AM.
[Resource: digilent_arty_a7_100t] is not free, waiting for execution ...
[Required resources: [digilent_arty_a7_100t]] added into queue at position 0
Lock acquired on [Resource: digilent_arty_a7_100t]
[Pipeline] {
[Pipeline] stage
[Pipeline] { (Synthesis and PnR)
[Pipeline] dir
Running in /var/jenkins_home/workspace/RiftCore/RiftCore
[Pipeline] {
[Pipeline] echo
Starting synthesis for FPGA digilent_arty_a7_100t.
[Pipeline] sh
+ python3 /eda/processor_ci/main.py -c /eda/processor_ci/config -p RiftCore -b digilent_arty_a7_100t